Xilinx 7 Series FPGAPower Benchmark
Design Summary
May 2015© Copyright 2015 Xilinx.

Application-centric Benchmarking Process

100G Packet
Processor

OTN
Muxponder

ASIC
Emulation

Wireless Radio &Satellite Modem

Edge
QAM

AVB
Switcher

Military
Radio

Mobil
Backhaul

FPGA resource counts, toggle rates, clock speeds…

Xilinx Power Estimator(XPE) version 2015.1
MAX condition used toestimate worst-casestatic power

Page 2Competitor’s
Estimator

XPE© Copyright 2015 Xilinx.

Early Power Estimator(EPE) versions 15.0
MAX condition used toestimate worst-case staticpower

Power Benchmark: Traffic Manager in 100G Line Card
Virtex-7 X690T FPGA
Xilinx Altera
Transceiver
I/O
Dynamic
Static
1.30X

Interlaken
16 at 10.3125GInterlaken
16 at 10.3125G

Transceivers

20Interlaken

NPU

Interlaken

25

TrafficManagement

30

Transceivers

Total Power (Watts)

35

DDR3
DDR3
DDR3
SDRAM

Backplane
Interface

15
105Resources

0Virtex®-7 Stratix V
X690T 5SGXA7-2LE
I-Grade622K

Environment

Process

Tj = 100°C

Max

Rate

LC/LEs232K-1600 Mb/s

Flip-Flops

167K

32

10.3 Gb/s

Block RAM

15,516 Kb

DSP Blocks

2PLLs

8

Interface

I/OsGTs8 x 32-bit DDR3544

Interlaken-Core Freq.
*Design results sourced from Xilinx Power Estimator (XPE) version 2015.1 and Altera Early Power Estimator (EPE) version 15.0
Page 3© Copyright 2015 Xilinx.

250 MHzPower Benchmark: 100GE over OTU4 Transponder
Virtex-7 X690T FPGA

Total Power (Watts)

30

Transceivers

35100GE
MapperTransceivers

100G
OUT-4
OTL4.10
Optical 10X11.18G
Module100G
EFEC

Transceiver
I/O
Dynamic
StaticOTU-4
FramerXilinx Altera

Overhead Processing

1.27X

CAUI

100G
OUT-4
OpticalModule100GE
Clients

25

Overhead bus

2015105Resources0Interface
Virtex®-7 Stratix V
X690T 5SGXA7 622K-2LE
I-GradeTj = 100°C

Max

LC / LEs

392K-250 Mb/s

Flip-Flops

245K-

1011.1 Gb/s

Block RAM9,360 Kb

-1010.3 Gb/s

Core Freq.

350, 175 MHz

GTs

LVCMOS

50

GTGT© Copyright 2015 Xilinx.

Process

Rate

I/Os

*Design results sourced from Xilinx Power Estimator (XPE) version 2015.1 and Altera Early Power Estimator (EPE) version 15.0
Page 4

Environment

Power Benchmark: ASIC Prototyping
Virtex-7 FPGA 2000TXilinx Altera
2.02X
60

Transceiver
I/O
DynamicStaticTotal Power (Watts)

50403020100Virtex®-7 Stratix V
2000T EEB (x2) 2 x 952K-2LE
I-GradeResources
Interface

I/OsGTs

3 64-bit DDR3366

LVDS408© Copyright 2015 Xilinx.

Process

Tj = 100°C

Max

Rate

LC / LEs

1,224K-1066 Mb/s

Flip-Flops

765 K

-

1000 Mb/s

Block RAM

21,600 Kb

Core Freq.

200 MHz*Design results sourced from Xilinx Power Estimator (XPE) version 2015.1 and Altera Early Power Estimator (EPE) version 15.0
Page 5Environment

Power Benchmark: Wireless WCDMA / LTE Picocell
Kintex-7 325T FPGA64 MB
DDR3DAC
DUC / DDC

OFDM
Modulator

10

OFDM
Demod

PCIe

12MIMO
Modulator

14MIMO
Decoder

Total Power (Watts)

16QAM
DeMod

Layer 1/2 API

1.65X

QAM
DeMod

GbE

18Channel
Encoder

Transceiver
I/O
Dynamic
Static64 MB
DDR3ChannelEncoder

Xilinx Altera

ADC

8MicroBlaze™
Processor

64264 MB
DDR3

Resources

0
Kintex®-7325T-2LI(0.95V)

Stratix V
5SGXA4-4I

Interface

420K

I/Os

GTs

Environment

Process

Tj = 100°C

Max

Rate

LC / LEs

240K

Flip-Flops

150K

Block RAM14,562 Kb

DSP Blocks

342

PCIe® Blocks

13 x 16-bit DDR3129-1066 Mb/s

GT-

24.0 Gb/s

GT-

1

1.25 Gb/s

GT-

1

2.5 Gb/s

Core Freq.
*Design results sourced from Xilinx Power Estimator (XPE) version 2015.1 and Altera Early Power Estimator (EPE) version 15.0Page 6© Copyright 2015 Xilinx.

307.2 MHz1210Digital UpConverter

RRC
Filter

FIFO

FIFO

J.83 Annex
A/B/C
Modulator

14EMAC

1610 Gig

Total Power (Watts)

18

Transceivers

2.02X

2010G Network Interface

Dense Edge QAM Modulator
Kintex-7 325T FPGARF4.6 Gigasample
14-Bit DAC

DAC IF128 Channels RF Port #18External
External
DDR3DDR3Memory
Memory6420Kintex®-7 Stratix V
325T
5SGXEA4 362K
-2LI(0.95V)-3I

Xilinx Altera
Transceiver
I/O
Dynamic
StaticResources
Interface

I/Os

GTs

Rate

LVDS

124-

1152 Mb/s

LVCMOS

12-

15 MHz2x 8-bit DDR355-

800 Mb/s

GT-1

10.3 Gb/s

Environment

Process

Tj = 100°C

Max

LC / LEs

182K

Flip-Flops

157K

Block RAM12,402 Kb

DSP Blocks

641

Core Freq.

384, 576,156, 192, 200 MHz*Design results sourced from Xilinx Power Estimator (XPE) version 2015.1 and Altera Early Power Estimator (EPE) version 15.0
Page 7© Copyright 2015 Xilinx.

Power Benchmark: AVB Switcher
Kintex-7 325T FPGAXilinx Altera

1.37X

Transceiver
I/O
Dynamic
StaticDDR3
DDR3DDR3SDRAM

108SD / HD / 3G
Transmit Interface

16SD/HD/3G
Inputs1

Frame Buffer
Control /Frame Sync

12

Chroma Keyer
Mixes, Wipes,
Effects

14SD / HD / 3G
Receive Interface

Total Power (Watts)

168 SD/HD/3G
Outputs1

642

Resources
0Kintex®-7325T-2LI (0.95V)

Arria V
5AGXB3 362K
I-GradeInterface

I/OsGTs3 x 72-bit DDR3450-GT-16© Copyright 2015 Xilinx.

Process

Tj = 100°C

MaxRateLC / LEs

300K

800 Mb/s

Flip-Flops

188K

2.97 Gb/s

Block RAM

10,800 Kb

DSP Blocks

500Core Freq.

148.5 MHz

*Design results sourced from Xilinx Power Estimator (XPE) version 2015.1 and Altera Early Power Estimator (EPE) version 15.0
Page 8Environment

AVB Switcher (4-channel)
Artix-7 100T FPGADDR 2/3
SDRAM

1.47X
SD / HD / 3G
Transmit Interface

3Chroma Keyer
Mixes, Wipes,
Effects

4Frame Buffer
Control /Frame Sync

4SD/HD/3GInputs*

4Total Power (Watts)

SD / HD / 3G
Receive Interface

54 SD/HD/3GOutputs*

32Control Interface

2*Note: SD/HD/3G inputs and outputs share GTs

110Artix®-7100T-1LI (0.95V)

Cyclone V
5CGXC7C-Grade

149K

Xilinx Altera
Transceiver
I/O
Dynamic
StaticResources
Interface
1 x 64-bit DDR3I/Os

GTs

Process

Tj = 85°C

Max

LC / LEs

75K

Flip-Flops

47K

Block RAM2,250 Kb

DSP Blocks

125Rate

PLL

1112-800 Mb/s

Phaser Block

1-42.97 Gb/s

Core Freq.

GT*Design results sourced from Xilinx Power Estimator (XPE) version 2015.1 and Altera Early Power Estimator (EPE) version 15.0
Page 9Environment© Copyright 2015 Xilinx.

148.5, 400 MHz

Power Benchmark: Single Channel Mobile Backhaul
Artix-7 200T FPGA
Xilinx Altera

Control Plane
Processor

Transceiver
I/O
Dynamic
Static
1.42X

6Traffic Management,
Packet Processing

Modem

TimingSynchronization

Transceivers

7Total Power (Watts)

SRAM

Ethernet Switch

Transceivers

8DDR3

5432

Resources

10Artix®-7200T-1LI(0.95V)

Arria V
5AGXA5I-Grade190K

Tj = 100ºCMax

LC / LEs
Flip-Flops

130K

Block RAM5,076 Kb
345I/OsGTs

1 x 32-bit DDR372-800 Mb/s

LVDS pairs

128-800 Mb/s

DSP Blocks

SEIO150-100 Mb/s

PLL-41.0 Gb/s

Core Freq.

*Design results sourced from Xilinx Power Estimator (XPE) version 2015.1 and Altera Early Power Estimator (EPE) version 15.0
Page 10Process

Interfaces

Switch ports

Rate

Environment© Copyright 2015 Xilinx.

81K

2250, 400 MHz

Power Benchmark: Satellite Modem
Artix-7 100T FPGA
1.57x
1.4

1.57x

Total Power (Watts)

1.2

Xilinx Altera
Transceiver
I/O
Dynamic
Static1.0
0.80.60.4
0.20.0Artix®-7 Cyclone V
100T
5CGEA7 150K-1LI(0.95V) I-grade

Resources
Interface

I/OsGTs1x 32-bit DDR269-© Copyright 2015 Xilinx.

Process

Tj = 85°C

Max

LC/LEs

85 K

Flip-Flops

52 K

Block RAM3,420 Kb

DSP Blocks

126

Rate

PLLs

250 Mb/s

Core Freq.

*Design results sourced from Xilinx Power Estimator (XPE) version 2015.1 and Altera Early Power Estimator (EPE) version 15.0
Page 11

Environment

230, 62.5, 125 MHz

Military Network Protocol Platform Data Aggregator
Artix-7 200T FPGA
7Total Power (Watts)1.41X

6543210Artix®-7200T-1LI(0.95V)

Arria V
5AGXA5 190K
C-GradeXilinx Altera
Transceiver
I/O
Dynamic
StaticResources

Process

Tj = 85°C

Max

LC / LEs

63K

Rate

Flip-Flops

58K

Interface

I/Os

GTs

2x 36-bit RLDRAMs

122-520 Mb/s

Block RAM3,600 Kb

GT-

65 Gb/s

DSP Blocks

400

GT-

82.5 Gb/s

PCIe® Blocks

1GT-

1

2.5 Gb/s

Core Freq.

*Design results sourced from Xilinx Power Estimator (XPE) version 2015.1 and Altera Early Power Estimator (EPE) version 15.0
Page 12Environment© Copyright 2015 Xilinx.

125 MHz