平成29年度

東京大学
大規模集積システム設計教育研究センター

年 報

2017
VLSI Design and Education Center,
The University of Tokyo
Annual Report

VLSI Design and Education Center The University of Tokyo 2017

VLSI Design and Education Center
The University of Tokyo

This is the 2016 Annual Report of VDEC（VLSI Design and Education Center, University of Tokyo）．
Since VDEC was established in 1996, we held “The VDEC 20th Anniversary Symposium” on January 20th this year.
After many warm addresses and messages from representatives of Government, industr y and academia including
oversee, successful researches and educations were reported from VDEC user universities. We also invited speakers on
attractive resent topics in LSI fields. We made a fresh resolve to continue our activities. We also looked back changes inthe semiconductor technology and economic situation in the past 20 years, which is almost a half of the LSI history. We
thank again many attendees and speakers for success of the symposium.
LSI chip design/implementation in 2016 went well as previous years in general. The use of the 0.8 um CMOS,
however, remained low and the use of the 0.18 um CMOS showed decreasing tendency, though the 65 nm SOTB wasfine. We decided to reschedule the 0.18 um fabrication runs. We apologize for any inconvenience caused by the schedulechange. After this we will guarantee two runs per year for each of 0.8 um and 0.18 um CMOS by restructuring VDEC
budget plan for this purpose. And every time when incomes from users reach the cost of another run, we will schedule
an additional run. The third run of 0.18 um would be possible so far as the user demands do not decrease so much.
The demand of 0.8 um CMOS, however, seems hard to recover. For the time being VDEC will use the chip area foruser designs as well as “master slices for QTAT CMOS gate array.” This is one week TAT gate array with one metal
programing. Though users need a small cost, it is easy to design and will be suitable for student labs. It has been used
for the 3rd year education in the EE department of our University for long time. Its PDK is ready for use and we will soon
make an announcement.
Number of users of the VDEC nano-fabrication facilities is still increasing. The rate of facilities operation and theoccupancy of cleanroom are almost 100%. It is a result of a positive feedback that “good conditions of facilities attract
new users and new users help to keep good conditions.” We will keep the feedback by an appropriate budget to thecleanroom. One of the basis of the budget is “MEXT-JST nanotech-platform project.” It is at the turn of the ten-year
project. We want to keep the good reputation of the VDEC activities, so as to continue to the next project, too.
VDEC introduced “the cost-sharing system for VDEC academic CAD licenses” last year. The income will be used
to partially compensate the constant decrease of VDEC budget from Government for the last 20 years. Now theacademic CAD licenses will be provided stably for years. We thank CAD users for understanding. Recent year, however,researches targeting commercial developments are becoming active in academia. The academic CAD licenses are notapplicable for these purposes. VDEC has been looking for a possible way to support them. Thanks to understandingof CAD vendors, VDEC could introduce “extended academic CAD licenses” last year, which can be used for the above
purposes. The first examples were NEDO projects. We would like to support other industry-academia joint projects, too.
The D2T (Design-to-Test) research division, donated by Advantest Corporation, was renewed last October (the 4thterm). The 11th D2T symposium was successfully held on September 21st 2016 and the next symposium is scheduled on
September 28st of this year. We would like to express our sincere thanks to Advantest Corporation for the continuous
support.
We will continue to do our best for the original mission of VDEC, “promotion of education and research in LSI designby means of practical chip-design and implementations”，in order to realize research and education for enhancing thevalue of the semiconductor technology. We thank you for your continuous supports again.
June, 2017

VLSI Design and Education Center, University of Tokyo
Director Kunihiro AsadaVLSI Design and Education Center, The University of Tokyo
Annual Report 2017

C O N T E N T Se a e rre t r

Chapter

t

t

C

ep rt

2

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1.1

Introduction of VDEC activities and activity report of FY2016

1.2

VDEC CAD Tools

2

5

1.3

VLSI Chip Fabrication

1.4

Seminar

10
14

7

1.5

Facilities

1.6

Activity plan for 2017

1.7

Venture companies related to VDEC

1.8

“Nanotechnology Platform”

16
17

18

Ultra Small Lithography and NanometricObservation Site

Chapter

Chapter 3

Chapter

t

t

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e ear h19

2.1

Introduction of “ADVANTEST D2T Research Division”

2.2

Report of “11th D2T Symposium”

2.3

Research Activity Reports of “Advantest D2T Research Division”

2.4

Publications

e ear h

19

20
22

24

C

24

Chapter 1 Activity Report of VDEC
1. 1 Introduction of VDEC activities andactivity report of FY2016

Chapter

1-1
2

VLSI Design and Education Center(VDEC), University

year. We hold the seminar in VDEC and provide distanceof Tokyo was established in May 1996. VDEC has beenlearning through video streaming. We expect spread ofoperating for the following 3 major roles: “spreading

the up-to-date LSI design methodology by using CAD

the latest information on VLSI design and education,”tools.

“providing licenses of CAD tools,” and “suppor tingWe assume our LSI design flow seminars as educations

on VLSI chip fabrications for academic use.” Theon basic LSI design concepts and practical experience of

VDEC activity report of FY 2016 is described hereafter

LSI design with CAD tool chain. VDEC holds “LSI design

according to Fig. 1. 1. 1.

education seminar”，a.k.a. VDEC Refresh Seminar,

t
t
ep rt

The missions of VDEC are for advancement ofonce a year. This year we hold 3 courses, “Analog design

researches and education on LSI design in public andcourse” and “RF design course”，and initiated “MEMS

private universities and colleges in Japan and send many

design course” in July-September time frame. We invite

distinguished VLSI designers into industry. After 19 years

experienced professors among universities as lecturersof VDEC establishment, educations on CAD software,

for the courses to conduct LSI design education courses

LSI design and design flow in universities have been wellwith practical experience. We also hold “Transistor levelestablished. On the other hand, advancement on nano-design flow in VDEC” and “Digital design flow in VDEC

meter CMOS technologies forces design flow and CAD

EDA environment” for designers in universities. We

software complicated. We have been continuing CAD tool

started to charge these two LSI design education courses,

seminar by the lecturers from EDA vendors for twice aas well as VDEC Refresh Seminars.

C
Fig. 1. 1. 1

VDEC activities

In addition to the above seminars, we hold “VDEC

lists to give answers to questions, however, in most cases,

DesignerʼForum” among young professors and students

replies are given by the experienced users of CAD tools

annually. This is a workshop that the par ticipantsand experienced designers within a couple of hours to aexchange their design examples with not only successcouple of days. Moreover, emails are accumulated andstories but also their failure stories, in addition toare open to the VDEC users, as shown in Fig. 1. 1. 2,

invited talks. We expect students and professors who

who have registered VDEC accounts, as the important

will start designs to learn kinds of know-hows. We haveeducational assets. We expect all the VDEC users to makeinitiated “IEEE SSCS Japan Chapter VDEC Design

the full use of this mechanism to help solve problems.
We continue chip fabrication services on FDSOI CMOS

have carried out during the “VDEC DesignerʼForum”．

28 nm by ST Microelectronics, 0.18 mm CMOS by Rohm

Mr. H. Shiomi(Kyoto Univ.) is awarded as “IEEE SSCS

and 0.8μm CMOS by On-semi Sanyo Semiconductor. And

Japan Chapter VDEC Design Award” winner, and Mr.

started chip fabrication services on SOTB CMOS 65 nm

M. Tamura(Univ. of Tokyo), Mr. A. Yoshimura (Naraby Renesas Electronics.

Institute of Science and Technology), Mr. T. Asano (Kobe

Our donated division “Design To Test(D2T)”，which

Univ.) are awarded as “the best VDEC Design Award”，

was founded by donation from Advantest in Oct. 2008,

and Mr. T. Kaan (Tokyo Tech), Mr. S. Imanishi (Shizuoka

focuses on enrichment of education on LSI testing andUniv.), Dr. K. Parit (Univ. of Tokyo) are awarded as thebridging between design and testing.
Fig. 1. 1. 3 shows trends of number of papers throughMr. H. Hayami (NAIST), and W. Nattakarn (NAIST) are

VDEC activities. Number of papers is increasing, which

awarded as the “VDEC Design Award.”means researches in the field of VLSI design have beenencouraged after VDEC establishment.

educations through various seminars and the forum. One

usage, chip fabrications and VDEC facility usages. CAD

of the biggest problems for beginners is the setup of CAD

tools are widely used to write papers. CAD tools aresoftwares. Many of them also get confused by “Esotericused not only chip designs themselves but also usedmessages” come out from CAD softwares, even after theyfor preparation of chip fabrication and they contribute

successfully setup CAD tools. In such situations, VDEC

to verify fundamental ideas of researches. Advanced

mailing-lists make significant contributions. VDEC users

CMOS processes are preferred for publications, and not

can register to VDEC mailing-lists on CAD tools, andonly papers with 65 nm/40 nm CMOS chips, but also

process dependent groups through VDEC web pages,

with 32 nm CMOS, 22 nm CMOS and 14 nm CMOS are

and can ask questions and helps on their facing issues. It

emerging in the world. We would like to prepare chip

is not a responsibility for the registrant of such mailing-

fabrication services for the advanced CMOS processes. In

Fig. 1. 1. 2

Archives of emails of VDEC mailing-list.

C

Fig. 1. 1. 4 shows number of papers related to CAD

ep rt

during actual LSI design scene, even after the basic

3t

LSI designers come up against various dif ficulties

1-1t“VDEC Design Award.” Also Mr. Y. Sato (Shizuoka Univ.),

ChapterAward” this year, and final examination and awardingaddition, we would like to setup chip fabrication services

to fully use of VDEC facilities such like LSI testers, FIB

related to CMOS/MEMS to fulfill the researches for

systems and EB writer for the wide spread of research“More than Moore”．We also encourage researchers

purposes.

Chapter

1-1
4t

Fig. 1. 1. 3

Trends of number of papers through VDEC activities.

t
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Fig. 1. 1. 4

Number of papers related to VDEC facilities.

1. 2 VDEC CAD Tools
Since 1996, VDEC has provided CAD software licenses

colleges.

to the registered researchers in universities and colleges
When one is going to use VDEC CAD tools and chipin Table 1. 2. 1. The researchers can use those CAD

fabrication service (the details are described in Section

tools when their local machines, whose IP addresses are

1-3), some faculty member of his/her research group inregistered in advance, are authorized by one of VDEC

a university or a collage needs to do user registration.

license server located in the ten VDEC subcenters shown

Fig. 1. 2. 2 shows (a) the number of registrants, (b) thein Fig. 1. 2. 1. For each CAD tool, VDEC provides 10-100

number of distinguished universities/colleges of thefloating licenses. Those CAD tools can be utilized only forregistrants, and (c) the number of registrants who appliedresearch and education activities in national universities,

VDEC CAD tools.

other public universities, private universities, andChapterin Japan. The CAD tools we provided in 2017 are shown

1-2

Table 1. 2. 1 VDEC CAD tools
Function

VendorCadence tool set

Verilog-HDL/VHDL entry, Simlation, Logic synthesis, Test
pattern generation, Cell-based (including macros) place,route, and back-annotation, Interactive schematic andlayout editor, Analog circuit simulation, Logic verification,
Circuit extraction

Cadence Design Systems, Inc.

Synopsys tool set

Verilog-HDL/VHDK simulation, Logic synthesis, Test pattern generation, Cell-based (including macros) place, route,and back-annotation, Circuit simulation, Device simulation

Synopsys, Inc.

Mentor tool set

Layout verification, Design rule check

Mentor Graphics Co. Ltd.

Silvaco tool set

Fast circuit simulation

SilvacoADS/Golden Gate

Design and verification of high-frequency circuits

Keysight Technologies

Bach system

BachC-based design, synthesis, and verification

Sharp

LAVIS

Layout visualization platform

TOOL

5

t

Name

t
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Chapter

1-2

Fig. 1. 2. 1 VDEC Subcenters

6

t
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(a) The number of registrants(c) The number of research group applied CAD tools(b) The number of universities colleges of the registrants(d) The number of applied licenses of all CAD tools

Fig. 1. 2. 2 The numbers of VDEC CAD Applications

1. 3 VLSI Chip Fabrication
1. 3. 1 Trends of VLSI Chip
Fabrication Services
Fig. 1. 3. 1 shows a trend of number of designed chips

the number of designed chips shows steady increase,which means drastic improve of the ef fectivenessresearches and education of LSI design, and we assume
drastic increase of number of students related to LSI chip

for VDEC chip fabrication services, including pilot projectprior to VDEC establishment.
VLSI chip fabrication is limited to 0.5 mm CMOS
provided by NTT Electronics during the pilot project

Chapter

in 1994 and 1995. VDEC chip fabrication had started in
1996 with 1.2 mm CMOS provided by Motorola Japan,
which is now On-Semiconductor as well as the 0.5 mm
CMOS. In 1997, VDEC received cooperation from Rohm

1-3and has started 0.6 mm CMOS process. In 1998, VDEC
started chip fabrication ser vices of 0.35 mm CMOS by

7

Hitachi, and in 1999, VDEC started 0.35 mm CMOS by
by STARC through “IP development project” in 2001. We(a) Trend of number of designs fabricated.

ep rtmenu in 2001. From 2002, we started VDEC-MOSIS chipt

added 0.18 mm CMOS by Hitachi into our chip fabricationt

Rohm. We had a test chip fabrication of 0.13 mm CMOS

fabrication program initiated by Prof. Iwata of Hiroshima
University. Under this program, VDEC member canaccess to TSMC and IBM processes with lower price. We
also started Bipolar chip fabrication by NEC CompoundC

Semiconductor Devices. In 2004, we star ted 0.15 mm
SOI-CMOS chip fabrication by Oki Electric as test chip
fabrications. In the same year we started 90 nm CMOS
chip fabrication by ASPLA/STARC. In 2006, we started
0.18 mm CMOS by Rohm and 0.25 mm SiGeBiCMOS
by Hitachi. In 2008, we started 65 nm CMOS process by
eShuttle, after closure of 90 nm CMOS chip fabricationin 2007. In 2010, we star ted 40 nm CMOS process(b) Trend of designed area.

by Renesas Electronics through “Next Generation
Semiconductor Circuits & Architecture” project between
METI and STAR. On the other hand, 1.2 mm CMOS
chip fabrication program came to end by the September
2011. 40 nm CMOS by Renesas Electronics and 65 nm
by eShuttle also come to end by Oct. 2012 and Aug. 2013,
respectively. We started CMOS0.8 μm in Oct. 2012 by
On-semiconductor-Sanyo as a test chip fabrication andopened it as the regular chip fabrication menu in 2012.
We started FD-SOI 28 nm CMOS by ST-Microelectronics
through CMP, France, as the advanced CMOS process
in 2013. We star ted SOTB 65 nm CMOS by Renesas
Electronics in 2015.

(c) Trend of designed area normalized by design rule.

Fig. 1. 3. 1(a) shows trends of number of chip designed
for VDEC chip fabrication. For the first 6 years until 2001,

Fig. 1. 3. 1 Trend of number of designs and designed chip area.

design and education. During few years of stable number
around 400 chip designs per year, we can see transitionof designs toward finer process. In 2007, we saw a large
drop, which was caused by sudden process transition
from 0.35 mm CMOS to 0.18 mm CMOS, and in 2008, we
also saw another drop by process transition from 90 nm
CMOS to 65 nm CMOS.
Fig. 1. 3. 1(b) shows trends of designed chip area,
which shows much clear trends of drop by process
migration. On the other hand, Fig. 1. 3. 1(c) shows
trends of designed chip area normalized by design rule,

Chapterwhich assume to be strong relation with design efforts.
Coming from the fact that the normalized chip area isstill growing, we assume the major reason for decrease of
number of chips and designed area is increase of design

1-3
8

effort per chip and per unit area due to process scaling.

Fig. 1. 3. 2 Trend of number of processors and universities
fabricated chip.

Fig. 1. 3. 2 shows trends number of professors anduniversities fabricated chip. Number of professors whothave contracted NDA for process technologies to accessdesign rules and design libraries are, 72, 274, and 38,trespectively, for 65 nm CMOS, 0.18 mm CMOS, andep rt

0.8 um CMOS.

1. 3. 2 Overview of chip fabricationin 2015
Table 1. 3. 1 lists chip fabrication schedule in 2015.
Please refer to list in Chapter 2 for details of designers
and contents of chip designed.

Table 1.3.1 Chip fabrication schedule in 2016
○ 0.8 mm CMOS (On-Semiconductor - Sanyo)

C

Chip application deadline

Design deadline

Chip delivery

2016 #1

2016/ 7/ 8

2016/ 9/30

2017/ 2/ 9

2016 #2

2016/12/30

2017/ 3/24

2016/ 6/20

Chip application deadline

Design deadline

Chip delivery

2016 #1

2016/ 3/ 7

2016/ 5/30

2016/ 9/20

2016 #2

2016/ 5/ 2

2016/ 7/25

2016/11/14

2016 #3

2016/ 6/28

2016/10/17

2016/12/27

2016 #4

2016/11/28

2017/ 2/20

2017/ 6/16

Chip application deadline

Design deadline

Chip delivery

2016 #1

2016/ 5/23

2016/ 7/ 4

2017/ 2/20

2016 #2

2016/12/12

2017/ 1/23

2017/ 8M

○ 0.18 mm CMOS (Rohm)○ SOTB 65 nm CMOS

1. 3. 3

Libraries and design flows

and design flows for digital design and PDKs for analog
design. Table 1. 3. 2 lists libraries available now.

VDEC have been working to prepare design libraries
Table 1. 3. 2

Libraries available for VDEC chip fabrication

Technology
0.18 mm CMOS
(Rohm)

Name

AuthorContents

Rohm library

Rohm Library
Std. Cells, IO cells, RAM(Distributed with CDROM)

Synthesis(Synopsys)
Simulation(VerilogXL)
P&R(LEF/DEF)

Kyodai Library

Onodera Lab., Kyoto University

Synthesis(Synopsys)

P&R(Astro)
Todai Library

VDEC
Design flow based on library prepared by
Onodera Lab., Kyoto University

Synthesis(RTL Compiler)
Simulation(VerilogXL)
P&R(Encounter)

PDK

VDEC

Chapter

Simulation(VerilogXL)

1-3
9

PDK(IC6.1)

t
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C

1. 4 Seminar

Chapter

1-4
10tSeminar is indispensable for the improvement of LSI

VDEC teachers gave lecturers on transistor level circuitdesign technology. Some seminar and forums, such as

design course, and digital circuit design course under thetechnical seminar for CAD use, refreshing seminar for

VDEC EDA environment. Teachers and students up to 40

working people, designerʼs forums for young professors

people attended a lecture in each course, and master theand students were held in 2016.

use of each tool for VLSI design flow that uses the VDEC

【Technological seminar for CAD use】

library. Moreover, another technical seminar for CAD use

In a technological seminar for CAD use, VDEC

Cadence 2 kind and 5 days, Synopsys 3 kinds and 4 days

invites lecturer from each tool vender, such as Cadence,(Table 1. 4. 1). The demand for these CAD technological

Synopsys and Agilent, to hold the CAD operation course.

seminars is ver y large, and VDEC has maintained theMoreover, the course concerning the design flow inmechanism of a large-scale CAD technological seminar

the VDEC environment was held by the VDEC staff. A

holding cor responding to this situation. So far, thetechnological seminar for CAD use for the beginner wasseminar was held at the University of Tokyo OR other

held in The University of Tokyo VDEC in August and

VDEC branch, however, we star ted to distribute theSeptember at the year 2016. This seminar took 5 days for

lecture using Web streaming, so that students around2 kinds of Cadence tools, 3 days for 2 kinds of Synopsys

VDEC branch can take the seminar at the branch school.

for matured teachers and students was held in March bytools, 1 days for 1 kind of Keysight tool. In addition,

t
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Table 1. 4. 1 CAD technological seminar in summer of the year 2016C

2016/08/02

Keysight Empro Seminar

Univ. of Tokyo13

2016/08/02

Keysight Empro Seminar

Hokkaido Univ.

2

2016/08/02

Keysight Empro Seminar

Kanazawa Univ.

1

2016/08/03-04

Synopsys DesignCompiler+PowerCompilerSeminar

Univ. of Tokyo9

2016/08/03-04

Synopsys DesignCompiler+PowerCompilerSeminar

Hokkaido Univ.

2

2016/08/03-04

Synopsys DesignCompiler+PowerCompilerSeminar

Tohoku Univ.

4

2016/08/03-04

Synopsys DesignCompiler+PowerCompilerSeminar

Osaka Univ.

5

2016/08/30-31

Cadence Virtuoso ADE Seminar

Univ. of Tokyo16

2016/08/30-31

Cadence Virtuoso ADE Seminar

Hokkaido Univ.

3

2016/08/30-31

Cadence Virtuoso ADE Seminar

Tohoku Univ.

5

2016/08/30-31

Cadence Virtuoso ADE Seminar

Kanazawa Univ.

2

2016/08/30-31

Cadence Virtuoso ADE Seminar

Kyoto Univ.

2

2016/08/30-31

Cadence Virtuoso ADE Seminar

Hiroshima Univ.

3

2016/09/01

Synopsys HSPICE Seminar

Univ. of Tokyo12

2016/09/01

Synopsys HSPICE Seminar

Hokkaido Univ.

2

2016/09/01

Synopsys HSPICE Seminar

Tohoku Univ.

4

2016/09/01

Synopsys HSPICE Seminar

Kanazawa Univ.

2

Kyoto Univ.

3

2016/09/01

Synopsys HSPICE Seminar

Osaka Univ.

3

2016/09/01

Synopsys HSPICE Seminar

Hiroshima Univ.

2

2016/09/05-07

Cadencee Virtuoso Layout Seminar

Univ. of Tokyo26

2016/09/05-07

Cadencee Virtuoso Layout Seminar

Hokkaido Univ.

3

2016/09/05-07

Cadencee Virtuoso Layout Seminar

Tohoku Univ.

3

2016/09/05-07

Cadencee Virtuoso Layout Seminar

Kanazawa Univ.

2

2016/09/05-07

Cadencee Virtuoso Layout Seminar

Osaka Univ.

3

2016/09/05-07

Cadencee Virtuoso Layout Seminar

Hiroshima Univ.

1

2017/03/01-02

Cadence Allegro Design Entry Front to Back Seminar

Univ. of Tokyo11

2017/03/01-02

Cadence Allegro Design Entry Front to Back Seminar

Hokkaido Univ.

1

2017/03/01-02

Cadence Allegro Design Entry Front to Back Seminar

Tohoku Univ.

4

2017/03/08

Synopsys XA-VCS CoSim Seminar

Univ. of Tokyo10

2017/03/08

Synopsys XA-VCS CoSim Seminar

Hokkaido Univ.

1

2017/03/08

Synopsys XA-VCS CoSim Seminar

Osaka Univ.

2

2017/03/08

Synopsys XA-VCS CoSim Seminar

Hiroshima Univ.

1

2017/03/09-10

Synopsys IC Compiler Seminar

Univ. of Tokyo14

2017/03/09-10

Synopsys IC Compiler Seminar

Hokkaido Univ.

1

2017/03/09-10

Synopsys IC Compiler Seminar

Osaka Univ.

1

2017/03/09-10

Synopsys IC Compiler Seminar

Hiroshima Univ.

2

2017/03/15

Synopsys HSPICE+VerilogA Seminar

Univ. of Tokyo17

2017/03/15

Synopsys HSPICE+VerilogA Seminar

Hokkaido Univ.

2

2017/03/15

Synopsys HSPICE+VerilogA Seminar

Kyoto Univ.

5

2017/03/15

Synopsys HSPICE+VerilogA Seminar

Hiroshima Univ.

1

2017/03/27-29

Cadence Encounter Digital Implementation Seminar

Univ. of Tokyo7

2017/03/27-29

Cadence Encounter Digital Implementation Seminar

Hokkaido Univ.

1

2017/03/27-29

Cadence Encounter Digital Implementation Seminar

Osaka Univ.

3

1-4
11

t

Synopsys HSPICE Seminar

Chapter

2016/09/01

t

Teachers of universities and designers in the first line

Division to give practicing education of the latest VLSIof the enterprise were invited to the lecturer at "VLSI

design technology, it continues under many suppor ts

design refresh seminar" was held aiming at the latest,from many societies.

the support of Ministry of Education Technical Education

advanced knowledge and technical learning concerning

Course A: analog integrated circuit design (7/11

VLSI design as a refreshing education for working people-13) , C o u r s e M1: M E M S d e s i g n (7/4-5) , C o u r s e

involved in the integrated circuit industry (Table 1. 4. 2).

M2:MEMS fabrication (7/25-7/27), and Course R: RFCThough this seminar started chiefly in year 1998 underep rt【Refresh Seminar for Working People】

circuit design (7/27-28). Teachers from industr y andincluding the practice using a lecture concerning VLSI

universities involved in the integrated circuit research

design and the latest CAD tool. The participants for theand the education were invited as the lecturer, and theycourse A, M1, M2, R were 18, 8, 6, 7, respectively.

introduced a state-of-the-ar t VLSI design technology

Chapter

1-4
12t
Fig. 1. 4. 1 Refresh Seminar at VDEC seminar room at the University of Tokyo, VDEC.

t
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Table 1. 4. 2 Refresh Seminar
Course A: Analog Circuit Design (3 days)
Analog Circuit Design and simulation
Integrated Circuits Verification (LVS, DRC)C

Masahiro Sugimoto (Chuo Univ.), Hidetoshi Onodera(Kyoto Univ.), Koji Kotani (Tohoku Univ.)

Course M1: MEMS Design (2 days)
MEMS Basic 1: Fabrication Process
MEMS Basic 2: Operation Principle
Structual Design
Layout Design
Yoshio Mita (Univ. of Tokyo)

Course M2: MEMS Fabrication (3 days)
CAD Design and Analysis
Lithography, Etching, Release
Vibration measurement and analysis
Yoshio Mita (Univ. of Tokyo)

Course R: CMOS-RF Circuit Design (3days)
Modulation/Demodulation, Cascaded connection
Basic Performace, Tranceiver Architecture
Circuit Element, Design Flow
Hiroyuki Ito (Tokyo Institute of Technology)

【Designerʼs forum for youngteachers and students】

for example, the failure case and the solution in which
LSI designer has a hard time, the inside stor y of CAD
industry, the construction method in the design milieu in

VDEC LSI designer for um intended for students

the laboratory, and so on. This year, we had the meetingand young teachers has been held. The VDEC LSIin Takeda Hall in The University of Tokyo, in August.

designer forum has aimed to sharing information thatNo less than 50 par ticipants were flourishing at thecannot be obtained at a society and a academic society,gathering.

Table 1.4.3 Program of Designers Forum in 2015
8/25(Thu)
Time

Chapter

Reception

10:00-11:00

Prenary Talk
Kazuhiko Takagawara (NTT)
Vital Sensing Technology by Wearable Devices.

11:00-12:00

VDEC Design Award Presentation

1-4

12:00-13:00

lunch

13

13:00-15:00

VDEC Design Award Presentation

15:00-15:20

break

15:20-18:20

VDEC Design Award Presentation

19:00-VDEC Design Award award ceremonyt

9:30-10:00

t
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8/26(Fri)Time
Ph.D Session

12:00-13:00

lunch

13:00-15:00

VDEC Design Award Idea Contest Presentation

15:00-15:20

break

15:20-16:50

VDEC Design Award Idea Contest Presentation

17:00-VDEC Design Award Idea Contest award ceremonyC

9:00-12:00

1. 5 Facilities

Chapter

1-5
14

The VDEC has provided the big facilities for

2016, the EB lithography machine F5112 has been used

universities in Japan from its establishment (1996). Big

1317 times. The reason of slight decrease of number

facilities refer to those which are impossible to acquire

since last year (89 times less from 1406 in 2015) canand or maintain by an individual research unit. Table

be attributed to user shift to new EB apparatus. The

1.5.1 shows the available facilities of VLSI testers andexposure count of the new apparatus (F7000S-VD02) was

some process machines, which are placed at the tester

increased to 1042 times that is +333 increase from lastroom and the super clean room of the Takeda building.

year (709 exposures in 2015). Total exposure number

In 2004, the VLSI tester (T2000) and the EB lithographyof EB machines have therefore increased from 2115 (inmachine (F5112+VD01) were donated to the VDEC by2015) to 2359 (+244).

the ADVANTEST. In the year 2012, VDEC joined MEXT

The facilities can be used by user himself, after a(Ministr y of Education)ʼs Nanotechnology platform tocouple of timesʼtraining by attendance of licensed users;

enforce its multi-use capability. (For Nanotechnology

also, by presence of licensed persons, a new user can

Platform refer section 1.8). From April 2015 to Marchreadily use the machine.

tt

Available facility list

Facility

Equipment name

Description

StatusContact

Logic LSI
test System

EB tester:
IDS10000

The chip surface voltage during operation
can be measured with the LST tester.
The digital circuit with 384 pins, 1 GHz canbe tested.

Available

nanotech@sogo.t.u-tokyo.ac.jp

LSI tester:
ADVANTEST T2000

The digital circuit with 256 pins, 512 MHz
can be tested. Analog test is optional.

Available

nanotech@sogo.t.u-tokyo.ac.jp

Auto prober:PM-90-A

Automated prober for testing LSI wafers,
which can be used with the LSI testers. The
probe card for LSIs with the VDEC standard
pin connections is available.

Available

nanotech@sogo.t.u-tokyo.ac.jp

Analog/RF measurement
system:
B1500A, 4156B, HP4284,
etc

DC parameter measurement, Capacitancemeasurement, Network analyzer, Spectrum
analyzer, etc.

Available

nanotech@sogo.t.u-tokyo.ac.jp

Low-noize manual prober:Cascade Microtec

6 inch wafer can be measured with six DC
probles and two RF probes upto 50 GHz.

Low-noize, temperature
controlled semi-auto prober: Süss Microtec

8inch wafer can be measured. The chip temperature range is ­ 50 to 200°C.

ep rt

Table1. 5. 1C
Analog/RF
measurement system

Minimum linewidth: 50nm.
Lithography for 5 inch photomask (thickness: 2.3 mm), 2-8 inch wafers, and chips is
possible.

Available

Rapid Mask and Direct
lithography: F7000S-VD02

Minimum linewidth: 1xnm.
Lithography for 5 inch photomask (thickness: 2.3 mm), 2-8 inch wafers, and chips
is possible. Stencil character projection of
non-square shapes such as circle, triangle ispossible.

Available

Chlorine ICP plasma etcher CE-S

High density plasma etching with Cl2 andBCl3 is possible.

Available

Silicon DRIE MUC-21
ASE-Pegasus

High speed, high aspect ratio etching of silicon is possible

Available

FIB systemFIB:
SII XVision200TB

Repair of photomask, sample etching, etc.
(Through Nanotech. Platform and LCNet)

Available

LSI FIB system

FIB: FEI V400ACE

Repair of VLSI from both frontside andbackside, with CAD navigation and / or IR
camera is possible. W/SiO2 deposition ispossible.

Available

Wedge Bonder: Westbond
7476D

25 µm φ Al or Au wire wedge bonding
machine.

Available

Epoxy Die Bonder
Westbond7200C

Precision Manupilator system. Epoxy andor Ag paste chip bonding and or glued wiring.

Semi-Auto Bonder
Westbond4700E

18 〜 25 µm φ Au Ball bonding or bumpcreation.

Precision Manual FlipChip Bonder Finetech
Fineplacer Lambda

Face-to-face bonding up to 15 mm squarechips. Alignment is through video camera.
Bonding is by heating chips with TV camera. (Ultrasonic Unit can additionally bepurchased.) XY ± 0.5 µm, and θ =1mrad
precision.

1-5
15

t
t

Chip
Bonding
Systemnanotech@sogo.t.u-tokyo.ac.jp

Chapter

Mask lithography, Direct
lithography: F5112+VD01

Nanotechnol
ogy Platform
Apparatuses

ep rt
C

1. 6 Activity plan for 2017
VDEC will continue activities on chip fabrication

Mentor tools as the main stream design tools. We will

ser vices, CAD tool support, dispatching design related

continue analog RF design environment, GoldenGate andinformation and donated division “D2T”，as has been

ADS by Agilent, C-based design environment, BachC

previous years.

by Sharp. In addition, we continue trial of several CAD【Design related information
dispatching/Seminar】

tools, such as layout platform, Lavis by TOOL. Design

We will continue holding the following seminars:

Chapter(1) CAD tools seminars which have been continued
since 1997, (2) “Refresh seminar” since 1998, (3)debugging platform from SpringSoft has merged into
Cadence tools and will be continued. Smar tSpice by
Silvaco, will be also continued.

【Chip fabrication services】“DesignerʼFor um” since 1997. We will also continue

We will continue chip fabrication ser vices for SOTB

seminars for LSI tester usage at VDEC and sub-centers,

65 nm CMOS by Renesas Electronics, 0.18 mm CMOS

1-6

workshops on LSI testing technologies initiated by D2T.

by Rohm, FD-SOI 28 nm CMOS by ST Microelectronics

16【CAD tool support】

through CMP and 0.8 mm CMOS by On-semiconductorSanyo as the regular services.

t

We will continue Cadence tools, Synopsys tools andt

Table 1. 7. 1 Chip fabrication schedule

ep rt【CMOS 1.2μm 2P2M】 On-Semiconductor(Former Motorola Japan)
Design deadline

Chip delivery

2017 #1

2017/ 7/10

2017/10/ 2

2017/12/25

2017 #2

2018/ 1/15

2018/ 3/26

2018/ 6/25

Chip application deadline

Design deadline

Chip delivery

2017 #1

2017/ 4/ 3

2017/ 6/26

2017/10/13

2017 #2

2017/ 8/ 7

2017/10/30

2018/ 2/16

2017 #3

2017/11/27

2018/ 2/19

2018/ 6/ 8

Chip application deadline

Design deadline

Chip delivery

2017 #1

2017/ 6/19

2017/ 7/31

2018/ 1/18

2017 #2

2017/12/18

2018/ 1/29

2018/ 7/12

C

Chip application deadline【CMOS 0.18μm 1P5M(+MiM)】 Rohm

【FD-SOI CMOS 28 nm1P10M】ST Microelectronics
Based on the chip fabrication schedule through CMP.

【SOTB CMOS 65 nm】 Renesas Electronics

1. 7 Venture companies related to VDEC
Some professors related to VDEC started venture companies. The following is a list of the venture companies
related to VDEC.
[1] AIL Co.,Ltd. (http://www.ailabo.co.jp/)
Related professor : Professor Kazuo Taki, Kobe Univ. (President-Director)[2]

Synthesis Corporation (http://www.synthesis.co.jp/)
Related professor : Professor Emeritus Isao Shirakawa, Osaka Univ. (Director)(2) System LSI design, design services(3) Development and sales of IPs(4) Development of EDA tools[3] Nanodesign Corporation (http://www.nanodesign.co.jp/)
Related professor : Professor Kazuyuki Nakamura, Kyushu Institute of Technology. (Representative Director)

17t

Related professor : Professor Emeritus Atsushi Iwata, Hiroshima Univ. (Representative Director)

1-7t[4] A-R-Tec Corp. (http://www.a-r-tec.jp/)

Chapter

Description of business : (1) Hardware/software co-design

Description of business : (1) Measurement and analysis of LSI substrate noise(3) Training of analog design on the JOB method

ep rt(2) Design of analog-RF mixed signal LSIs

[5] Ishijima Electronics (http://ishi.main.jp/)(2) Software development(3) Consulting

C

Description of business : (1) Electronic circuit development

1.8 “Nanotechnology Platform”:
Ultra Small Lithography and NanometricObservation Site

Chapter

1-8
18

t
t
ep rt

VDEC is operating an open-use nanotechnology

sizing from 1cm-sqare chip to 8-inch round wafers. The

platform “Ultra Small Lithography and Nanometric

per formance is measured by the number of research

Obser vation Site” together with the Institute ofrepor ts and machine use. The University of Tokyo

Engineering Innovation of Graduate School ofsite has received 162 research repor ts, composed ofEngineering. The site is supported by Japanese Ministry

26 from big companies, 4 from Small and Medium-sizeof Education (MEXT)ʼs Nanotechnology Platform grant.

Enterprises (SMEs), 28 from other universities, 91 fromAny researchers in Japanese Universities, Laboratories,

UTokyo researchers (including external collaboration but

and Companies can take full advantage of The University

excluding VDEC), and 11 from public research institutes.

of Tokyoʼs cutting-edge nanotechnology apparatuses

The exposure count was 2359 for 12 months (196.5 /and know-hows. The accessible technology includes

month), which is the record since beginning of existing

Lithography and Etching environment, Ultra High-statistics (total 460 for FY 2000). As shown in the Fig. 1,

Voltage Acceleration (1MV) transmission electron

usage is monotonously increasing. “Open ratio”，which is

microscope (TEM) that is capable of visualizing upto

the number of days in which users outside the University

light materials such as Nitrogen. VDEC takes par t inof Tokyo came, divided by machine open days, was 99%.

the lithography at Takeda Sentanchi Super Cleanroom.

Due to the strong support of nanotech. Platform, even a

Through VDECʼs key apparatus F5112+VD01 donatednovice user can obtain fine lithography result by usingfrom Advantest Corporation as well as F7000S-VD02

the apparatuses with the Platform engineering staffs ofpurchased by national budget, VDEC is supporting post-

VDEC.

VLSI activities such as MEMS. The machine is capableof rapidly writing patterns on arbitrar y-shaped targets

URL: http://nanotechnet.t.u-tokyo.ac.jp/

CFig. 1 Monthly Average Exposure Count of EB Machine (s).

Chapter 2 Activity Report of“ADVANTEST D2T Research Division”
2. 1 Introduction of“ADVANTEST D2T Research Division”

2. 1. 1 Aim of the establishment of“ADVANTEST D2T Research
Division”

in October 2016, we lunched the 4th phase of D2T projectthrough the courtesy of ADVANTEST Corporation.
In 2016, we invited Professor Stewart Smith from the

ADVANTEST D2T research division was established

University of Edinburgh (2016/5–2016/9), and Professor

in VDEC in October 2007. As the name of the research

Krishnendu Chakrabarty from Duke University (2016/9–

division indicates, it is financially suppor ted by

2016/12) for research and educational collaborations with

ADVANTEST Corporation.

VDEC.

The aim of establishment of ADVANTEST D2T

Details of our groupʼs activities are presented in the

research division is to promote the research andfollowing sections.

education environment of VLSI testing in all universities

2. 1. 2 Members of “ADVANTEST D2T
Research Division”

and colleges in Japan.” D2T” means that we consider not
only design but also test. As the results of our activities,
we hope to provide the exper ts of design and test for

Project Professor

industry. In addition, we are exchanging researchers withother universities or research institute in both Japan andKrishnendu Chakrabarty(Sep. 2016–Dec. 2016)

Project Associate Professor Stewart Smith

overseas. Moreover, D2T research division is in a good(May 2016–Sep. 2016)

Chapterenvironment to make collaboration with industry because

Project Lecturer

Rimon Ikeno

testing of VLSI is one of the most practical research topics

Assistant Professor

Nguyen Ngoc Mai-Khanhin industry. Based on those activities, our final goal is to

Researcher

Takahiro Yamaguchi

Researcher

Masahiro Ishida

2-1(ADVANTEST Corporation)

19

become a center of excellence of VLSI Testing in Japan.
D2T research division has spent 9 years in total with(ADVANTEST Laboratories Ltd.)the 1st (Oct. 2007–Sep. 2010), 2nd (Oct. 2010–Sep. 2013),
and 3rd (Oct. 2013–Sep. 2016) project phases already, andAssistant Clerk

Makiko Okazaki

e ear h2. 2. Report of “11th D2T Symposium”“The 11th D2T Symposium” was held on September
21st, 2016 at Takeda Hall.

Chapter
20

also gave lectures on their recent research activities. At

Under its main theme:” Design, fabrication, and test of

the panel discussion, Professor Hiroyuki Fujita (Instituteheterogeneous systems”，the symposium had valuable

for Industrial Science, The University of Tokyo) kindly

lecturers by distinguished researchers invited from bothserved as the moderator to conduct the active discussions

overseas and domestic institutes, latest achievementwith the theme of “Breakthrough technology andreports by VDEC researchers, and a panel discussion by

application of heterogeneous micro/nano systems forthe lecturers and guest panelists.

industrial/economic success.”

The invited lecturers were Professor Anthony Walton

We sincerely appreciate ever y par ticipant for their(The University of Edinburgh) and Professor Kwang-

contribution at the symposium. We look forward to seeing

Ting Cheng (Hong Kong University of Science andmany participants at the next symposium again.

Technology). T wo visiting professors (Professor

2-2

Krishnendu Chakrabarty and Professor Stewart Smith)e ear h11th D2T Symposium program
10:00

Opening Remarks
Kunihiro Asada (Director, VLSI VDEC, The University of Tokyo)
Takashi Sekino (Vice President, Nanotechnology Business, ADVANTEST Corporation)

10:15

Session 1 (Chairman: Yoshio Mita, The University of Tokyo)“Design and Test of Micro-Electrode-Dot-Array (MEDA) Digital Microfluidic Biochips”
Krishnendu Chakrabarty (Duke University, VDEC, The University of Tokyo)“IMPACT - Implantable Microsystems for Personalised Anti Cancer Therapy”
Stewart Smith (The University of Edinburgh, VDEC, The University of Tokyo)

11:45

Lunch

13:15

Session 2 (Chairman: Tetsuya Iizuka, The University of Tokyo)“Experimental Demonstration of Cancelling Systematic Variation for free-Calibration Stochastic ADC”
Nguyen Ngoc Mai Khanh (VDEC, The University of Tokyo)“A new method for measuring alias-free aperture jitter in an ADC output”
Takahiro J. Yamaguchi (ADVANTEST Laboratories, VDEC, The University of Tokyo)“Power Supply Impedance Emulation Technique for ATE Device Power Supply”
Masahiro Ishida (ADVANTEST Corporation, VDEC, The University of Tokyo.)“High-throughput and high-accuracy electron-beam direct writing”
Rimon Ikeno (VDEC, The University of Tokyo)

14:45

Coffee Break

15:15

Session 3 (Chairman: Toru Nakura, The University of Tokyo)“Options for the integration of technologies with CMOS Integrated Circuits”
Anthony J. Walton (The University of Edinburgh)“3D Integrated CMOS-Memristor Hybrid Circuits: Devices, Integration, Architecture, and Applications”
Kwang-Ting (Tim) Cheng (Hong Kong University of Science and Technology)

16:35

Break

16:45

Panel Discussion

Moderator:
Panelists:

18:00

Closing“Breakthrough technology and application of heterogeneous micro/nano systems forindustrial/economic success”
Hiroyuki Fujita (Institute of Industrial Science, The University of Tokyo)
Anthony Walton (Edinburgh University)
Kwang-Ting Cheng (Hong Kong University of Science and Technology)
Krishnendu Chakrabarty (Duke University, The University of Tokyo)
Stewart Smith (Edinburgh University, The University of Tokyo)

Chapter

Theme:

2-2
21

Receptione ear h2. 3 Research Activity Reports of“ADVANTEST D2T Research Division”
The purposes of this research project are to develop a

Chapter2-3
22Fine Resolution Analog-to-Digital converter based

power delivery network modeling method for evaluat-

on Stochastic Comparators

ing power integrity at on-chip power supply nodes in

Nguyen Ngoc Mai-Khanh, Rimon Ikeno, Takahiro

semiconductor devices and a new power integrity con-J. Yamaguchi, Tetsuya Iizuka, Kunihiro Asadatrol method which is based on the feedback operation.

This research is to implement a fine-resolution

This year, for the power deliver y network model-

sub-ranging analog to digital converter (ADC) circuit

ing, we have investigated an algorithm for calculatingbased on stochastic comparators.

an impedance model of the on-chip power deliver y

Process variations together with many factors suchnetwork based on the measurements of voltages andas variations on voltage or temperature lead to mis-

currents at the power supply pins of the device while

matched design parameters that produce input-referredloading a current at the on-chip power supply node, andoffsets and hence cause non-linearity and missing out-

evaluated its feasibility by using computer simulations.

put codes of an ADC. Instead of making an effort to

For the power integrity control method, we have devel-suppress such process variations as conventional ADC,

oped extended methods of the previously proposed

the stochastic ADC approach exploits process varia-

feedback-based power supply characteristic emulation

tions based on the Gaussian distribution assumption ofto 1) a multiple power supply pin control, 2) a correc-

comparator voltage offset.

tion of the compensation current source characteristic,

A layout strategy is proposed to reduce systematicand emulation of serially connected impedance models,variation and achieve Gaussian offset distribution withand demonstrated the concept and feasibility of thea reasonable number of comparators. A measurement

extended methods by computer simulations and experi-

setup for dif ferential signals and low noise is per-ments with an actual hardware including an FPGA.

formed. In addition, several types of modified differential comparators are invested and measured. Several
measured results demonstrated the relationship ofHigh-throughput and high-accuracy electron-beamnumber of comparators and the ef fective resolution

direct writing (EBDW) strategy for wide range of

LSB of stochastic ADC. These results are helpful for a

EBDW applications

design-guide of the tradeoff between the numbers of

Rimon Ikeno, Yoshio Mita, Kunihiro Asada

comparator elements, the required LSB resolution, die

Maskless lithography by Electron-Beam Directarea, and power consumption for the fine-resolution sto-

Writing (EBDW) lithography is expected as a low-costchastic ADC approach.

and short turn-around time (TAT) lithography technology, but it also has some drawbacks like low process
throughput and low accuracy against the intended

e ear hPower Integrity Evaluation Method

layout shapes. We are pursuing high-speed and high-ac-

Masahiro Ishida, Naoki Terao, Akira Matsukawa,curacy EBDW strategy utilizing Character Projection

Rimon Ikeno, Toru Nakura, Tetsuya Iizuka,(CP) method to overcome these concerns and to boost

Kunihiro Asada

EBDW use in arbitrary fields like MEMS, photonics,

While a required power supply voltage has becomeand so on.

lower due to the advanced miniaturization of the semi-

In this year, we applied our high-throughput andconductor process, the power supply current consumed

high-accuracy EB exposure strategy by combination

by a semiconductor device has increased becauseof CP and Variable-Shaped Beam (VSB) methods toof the huge number of transistors integrated on apractical device structures like optical wave guides, andsingle chip. It may increase the power supply noise,

investigated the shot-count reduction capability andand power integrity issues of the device under test in

resultant line-edge roughness (LER) utilizing Atomic

both an ATE and a practical operating environments.

Force Microscopy (AFM) for precise resist shapeobservation and analysis. We also conducted numeri-process to optimize conditions of resist baking, resist

cal analysis of chip temperature during EB exposure

development, and exposure processes.

Chapter2-323

e ear h2. 4 Publications
Eliminate Overkills and Underkills due to the Impedance

Journal papers[1]

Masahiro Ishida, Toru Nakura, Takashi Kusaka, Satoshi
Komatsu, and Kunihiro Asada, “Dynamic Power Integrity

Dif fer ence between ATE and Customer Boar d,”
International Test Conference 2016, November 2016.
[4]

J. Yamaguchi, Tetsuya Iizuka, and Kunihiro Asada,Control of ATE for Eliminating Overkills and Underkills“Experimental Demonstration of Stochastic Comparators

in Device Testing,” Journal of Electronic Testing: Theory

for Fine Resolution ADC Without Calibration,” 2016

and Applications, vol. 32(3), pp. 257-271, 2016.
[2]

IEEE International Conference on Electronics, Circuits,

Rimon Ikeno, Satoshi Maruyama, Yoshio Mita, Makoto
Ikeda, and Kunihiro Asada, “Electron beam lithography
with character projection technique for high-through-& Systems (ICECS), December 2016.
[5]

high-throughput character projection exposure utiliz-

Micro/Nanolithography, MEMS, and MOEMS, 15(3),ing atomic force microscope analysis,” SPIE Advanced

31606, 2016.
Masahiro Ishida, Toru Nakura, Takashi Kusaka, Satoshi
Komatsu, and Kunihiro Asada, “Power Supply Voltage

Lithography 2017, 10148-33, March 2017.
[6]

Kunihiro Asada, and Yoshio Mita, “Test Str uctures

Fault Testing,” IEICE Transactions on Electronics, vol.

for Nano-Gap Fabrication Process Development for

E99-C, no. 10, pp. 1219-1225, October 2016.

[1]

Chapter

2-4

Stewar t Smith, Yudai Takeshir o, Yuji Okamoto,
Jonathan G. Terr y, Anthony J. Walton, Rimon Ikeno,

Control for Eliminating Overkills and Underkills in Delay

International Conferences,
Symposiums, Workshops

Rimon Ikeno, Yoshio Mita, and Kunihiro Asada, “Lineedge quality optimization of electron-beam resist forput exposure with line-edge quality control,” Journal of[3]

Nguyen Ngoc Mai-Khanh, Rimon Ikeno, Takahiro

Nano-Electromechanical Systems,” 30th International
Conference on Microelectronics Test Structures (ICMTS
2017), 9.4, March 2017.
[7]

Naoki Terao, Tor u Nakura, Masahiro Ishida, Rimon

James S. Tandon, Satoshi Komatsu, Takahir o J.

Ikeno, Takashi Kusaka, Tetsuya Iizuka, and Kunihiro

Yamaguchi, and Kunihiro Asada, “A comparative study

Asada, “Extension of Power Supply Impedance Emulationof body biased time-to-digital converters based-on sto-

Method on ATE for Multiple Power Domain,” to be pre-chastic arbiters and stochastic comparators,” IEEE 2016sented at 22nd IEEE European Test Symposium, May

14th IEEE Inter national New Circuits and Systems

2017.

Conference (NEWCAS 2016), June 2016.
[2]24

Takahiro J. Yamaguchi, Katsuhiko Degawa, Tetsuya
Iizuka, and Kunihiro Asada, “Common pitfalls in application of a threshold detection comparator to a continuous-time level crossing quantization,” 21st International
Mixed-Signal Testing Workshop (IMSTW 2016), July
2016.

[3]

Tor u Nakura, Naoki Terao, Masahiro Ishida, Rimon
Ikeno, Takashi Kusaka, Tetsuya Iizuka, and Kunihiro
Asada, “Power Supply Impedance Emulation to

Domestic Conferences, Workshops, etc.
[1]

Rimon Ikeno, “Analysis of IR-drop influence on at-speed
test quality,” 75th FTC Workshop, July 16th, 2016．

[2]

Naoki Terao, Tor u Nakura, Masahiro Ishida, Rimon
Ikeno, Takashi Kusaka, Tetsuya Iizuka, and Kunihiro
Asada, “Emulation of Power Supply Impedance for LSI
Testing,” 2017 IEICE General Conference, A-1-3，March
23rd, 2017.

e ear hChapter 3 Research in VDEC
Asada, Nakura and Iizuka
Laborator y(http://www.mos.t.u-tokyo.ac.jp)

LSI Test and Improved Reliability in Ultra-Fine
Process Technologies
Kunihiro Asada, Toru Nakura, Tetsuya Iizuka,
Akira Matsukawa, Toshiyuki Kikkawa, Takashi Toi, andSupply Fluctuation Monitoring, Analysis andReduction Method

Meikan Chin.
As miniaturization of semiconductor process increas-

Kunihiro Asada, Toru Nakura, Tetsuya Iizuka,

es, power supply voltage fluctuation due to its parasitic

Masahiro Kano

impedance has become serious concer n. LSIs are

As miniaturization of semiconductor process increas-

tested after manufacturing process to see if it will workes, a resonant power supply noise due to parasitic

properly under customerʼs environment. Power supply

impedance on power supply lines and parasitic capaci-

impedance mismatch between testing environment

tance of a core circuit has become a serious problem inand customerʼs environment, however, can potentiallydesigning mixed signal SoCs.

degrade reliability of the test.

Passive decap is one of the most popular method

We proposed power supply module for ATE whichused for resonant power supply noise suppression,

has an ability to change its parasitic inductance andhowever, this requires large silicon area for large capac-

capacitance using compensation current injection, so

itance. Then, we focused on the active charge injectionthat it can emulate customerʼs environment, by which

method in order to realize both noise reduction andwe can expect significant improvement of testing reli-silicon area reduction. For the active charge injec-

ability. Experimental measurement results by prototypetion, there are 2 approaches. One is capacitor-based

system showed that the voltage fluctuation waveform

approach charging and discharging the capacitorsof the ATE was adjusted to that of the customer board,

with a higher supply voltage, and the other is resis-

meaning that the impedance on the customer board

tor-based approach directly extracting the charge fromwas successfully emulated by the ATE.
As an expansion of this method, we proposed an

We analyzed both approaches under certain assump-

application to the devices with multiple power supply

tions and designed the circuits (voltage drop detector,

pins using matrix operation. Also, we proposed theinjection controller circuit and canceling capacitor/

way to emulate not only the parameters of inductor

resistor circuit) to realize the analyzed charge injec-

or capacitor, but also arbitrary power supply network

tion. From the measurement results of the real siliconusing nested-feedback digital filter and confirmed thechips, we realized 14% and 24% noise reduction by using

concept by simulation.

capacitor-based and resistor-based approach, respec-

3-1
25

tively. Also, the proposed circuit using resistor-based
PLL circuit with Time-Domain control

with MOS capacitors for the same amount of noise

Kunihiro Asada, Toru Nakura, Tetsuya Iizuka,

reduction.

Keigo Tu, Tsukasa Kagaya

However, more accurate model and the feedback

In this research, we have applied time-domain con-control realizing it are required for more robust sys-trol methods to PLL circuit. A Pulse-Width Controlledtem.

PLL (PWPLL) is a new type of PLL whose oscillator is
In intermittent systems such as a variety of IoT devices, fast-locking PLL can reduce energy consumption as
well as the latency time for system start-up. Therefore,
the fast-locking method for PWPLL is proposed in thesystem where PWPLL refers and outputs the same fre-Ccontrolled by a pulse width.

e ear happroach consumes only 10% silicon area compared

Chapter 3

a higher supply voltage through the pass transistors.

quency.

keeping the high resolution by using a hierarchicalFor fast-locking, we adopt storing and reproducing
measures for the phase and frequency-control code in
the locked feedback system of PWPLL.

approach.
TDC can be applied for various applications andClock and Data Recovery (CDR) based on Cycle Lock

In order to realize this scheme, we add Time to

Gated Oscillator (CLGO) is one example. Since this

Digital Converter (TDC), Digital to Time Converter

CDR targets at serial communication systems which(DTC), and other memor y circuits to conventional

operate only intermittently, it is important that not only

PWPLL for storing phase and frequency-control code.

increasing power consumption rate in the operational

When PWPLL gets started again after this series ofstate but also minimizing power consumption of stand-the storing procedures, the stored values of phaseby state and maximizing the period of stand-by stateand frequency-control code is set as initial values andby launching quickly. In this research, we proposed

as a result fast-locking is realized.The lock time of thisCDR based on CLGO using Delay Tunable Buffer andfast-locking PWPLL has been proved to be 20~150 ns

Vernier TDC which has same resolution, for increasing

by simulations and 70 ns by measurements.

the data rate and decreasing the power consumption

In order to make the PLL design simpler and takewhile keeping its quick start-up attribute.

less time, we proposed an automatic design flow.
Actually not all the PLLs could be designed automatically, this design flow is suitable for a ADPLL which is

Radiation Detector Utilizing Semiconductor

built by standard cells.

PhotodiodeNowadays, we have realized the design flow to synthesize parts of this ADPLL. In this design flow BothKunihiro Asada, Toru Nakura, Tetsuya Iizuka,
Yang Xiao, Kai Xu

Verilog netlist and Spice netlist are automatically gen-

Scintillation detectors and semiconductor detectors

erated by script. Based on the netlist the layout andhave received wide spread attention since they cansimulation are also engendered in this design flow.

specify the nuclide of radiation and estimate the arriv-

However, this flow only can design the DCO by set

al angle. Former research proposed a detector using

some parameters manually.

In order to improve thethe cube scintillator, SPAD (Single Photon Avalanche

automatic design more conveniently, we are working on

Diode) array image sensors, multi-coated materials,

generating all parameters from performance specifica-and pinholes and verified the method to detect the posi-tionautomatically.

tion of point light source inside the scintillator. We proposed a new method which calculated the track of pho-

Chapter 3

3-1
26

tons to precisely estimate the position of light source.
Time Domain CDR and TDC Designs

This method can cost less time to detect the light

Kunihiro Asada, Toru Nakura, Tetsuya Iizuka,

source position compared to the former research. The

Meikan Chin, Ryuichi Enomoto

result of the simulation verified that by using this meth-e ear hWhile digital circuits directly benefit from advanced

od the position of the light source inside the 1mm-size

process technologies, analog circuits suffer from neg-

scintillator could be detected with a spatial resolution of

ative effects such as small voltage headroom. Time-

10 um-20 um in less than 0.3s. About the structures ofdomain circuits, where analog signals are represented

SPADs we have tested, the p-well/deep-n-well with polyby digital signal edge transitions, could be a solution togate SPAD shows the lowest DCR. A 31x31 SPAD sen-the problem of analog circuits in a nanometer process.

sor featuring breakdown pixels extraction architecture

Time-to-Digital Converter (TDC) is a representativefor efficient data readout has been fabricated, and itʼsexample of time-domain circuits. The TDC converts

ability of capturing a short laser pulse has been proved

a time interval between two rising edges into a digitalby measurements.

C

code by using delay elements. In this research, we
focus on pulse-shrinking TDC. In general, TDC has
a trade-off between the time resolution and dynamic
range, and the trade-off is particularly remarkable in
the pulse-shrinking TDC. We proposed and designed
a new TDC that improves the dynamic range while

Crosstalk Reduction on High Speed Communication

UWB-IR Pulse Generators for Low PowerLine

Application

Kunihiro Asada, Toru Nakura, Tetsuya Iizuka,

Kunihiro Asada, Toru Nakura, Tetsuya Iizuka,

Tokuhiko Nakasato

Nguyen Ngoc Mai-Khanh, Parit Kanjanavirojkul,

With the improvement of the circuit performance

Yudai Suzuki

due to the miniaturization of the semiconductor pro-Wideband pulse generation methods are studied,cess, the speed of transmission has been improving.

aiming at ultra-wideband impulse radio sensing appli-

The data rate necessary for applications also has beencations in high frequency bands. In contrast to con-improving because UHD TVs and automobiles with aventional feedback based switched-oscillator pulse

lot of electrical equipment was developed.

generation, this work focused on excitation based pulse

It is necessary to speed up transmission from bothgeneration, in which the center oscillation frequency

aspects of technology and demand, crosstalk is one ofis not limited by CMOSʼs Fmax. Moreover, it feature

the factors hindering this. As measures for crosstalk, aquick-starting time and zero stand-by power. Two pulse

circuit for reducing crosstalk at the receiving end was

generation techniques utilizing voltage-mode excitation

proposed in the previous research. In this research,and current mode excitation are proposed. The trans-

we proposed a circuit with PD control circuit and time

mission line resonator is used in place of the lump LC

delay element based on the circuit in the previous

resonator, such that the Q factor is highly increased

research. Using simulation, we showed that the circuitand the modeling at high frequency is simpler. As acan reduce crosstalk more effectively.

result the energy conversion ef ficiency of 3.13% isachieved at 12.5 GHz oscillation frequency in measurement. This is improved from conventional excitation

Surface magnetic field modeling for LSI security

type pulse generators, which have efficiency less than

Kunihiro Asada, Toru Nakura, Tetsuya Iizuka,

1%. The prototypes are realized by CMOS chip flipped

Nguyen Ngoc Mai Khanh, Yuki Oda

on the transmission line resonator on quartz substrate.

The modern VLSI systems that demand high reliability require carefully-designed power/ground network
to provide stable power supply. Though the power

High-performance A-D Converters

supply connection is verified before tapeout, it is quite

Kunihiro Asada, Toru Nakura, Tetsuya Iizuka,

difficult to evaluate its actual quality and reliability after

Takaaki Ito, Taiki Sugiyama
Analog-to-Digital Converters (ADC) are widely used

Using the measurement results of magnetic fieldas circuits which convert analog signal to digital signal.

emission from LSI, the proposed method estimates the

The purpose of this study is designing high-resolution

actual current flow from the magnetic field measure-

ADCs which are used in circuits imitating neuron.

ment results, and enables us to find defects or design

These ADC need not execute high-speed conversion.

faults such as VIA/wire disconnections and/or current

However, each circuit component has thermal noise

concentration with low cost.

and non-linear distortion which should be eliminatedfor enhance ADCʼs resolution. Recently, we designed

simulator demonstrate that the proposed method pre-a SAR (successive approximation register) ADC withcisely estimates the current flow in the supply network

redundant bits for high resolution and low-powerand clearly indicates the VIA fault location.

switching method.
Also, LSI process is getting smaller and design ofwith actual measurement results, the test structure isanalog circuits is becoming more difficult. Offset can-designed and fabricated in 0.18 um 1P5M CMOS pro-celling techniques and bigger circuits are used for ADC

cess. Current flow of power network in the chip was

design to eliminate process variation and noise.

successfully estimated by actual measurement data.

Another design approach is stochastic approach inwhich many comparators are driven in parallel. Thisemerging approach can be applied to level-crossing
ADC and it is called level-crossing stochastic ADC.

27

C

To verify the feasibility of the proposed method

3-1

e ear hExperimental result using an electromagnetic field

Chapter 3

fabrication.

We analyze input slope dependency of level-crossing

pared to our previous work, for the large circuits. For

stochastic ADC by circuit simulations. And we will

example, Our experiments on IWLS2005 benchmark

measure the input slope dependency using the chip wesuite show that our method is able to find the perfectdesigned manually.

matching between two 160,000-gate IP in less than 30
seconds.

Fujita Laborator y(http://www.cad.t.u-tokyo.ac.jp/)

High-level description generation method for ECO
and its application
Masahiro FUJITA, Amir Masoud GHAREHBAGHI,

A New Approach for Debugging Logic Circuits
Masahiro FUJITA, Amir Masoud GHAREHBAGHI

Qinhao WANG, Yusuke KIMURA,In VLSI design, ECO (Engineering Change order)

Debugging logic circuits usually requires determin-

may happen after optimizing a gate-level circuit. In thising the new function for some internal nodes such thatcase, designers may modify the gate-level circuit direct-

the circuit behavior becomes the same as the given

ly in order to preserve the optimization effort spent so

specification. In this paper, we present a new approachfar. In this research, we presented a method to gener-

for specifying the new function that focuses on finding

ate a corresponding high-level description utilizing thethe inputs to the new function instead of the function

modified gate-level circuit. Moreover, we presented aitself. First, we try to find the dependency of the newnew equivalence checking method between a gate-level

function to the primary inputs, if they are not known.

circuit and a high-level description.

Then, the internal nodes that are candidate of the
inputs to the new function are selected. Finally, theChapter 3

3-1
28

inputs to the new function are determined. Both the

Efficient Methods for Automatic Test Pattern

primary input, and the internal nodes that are inputs toGeneration (ATPG) for Multiple Faults

the new function are selected based on an iterative SAT

Masahiro FUJITA, Amir Masoud GHAREHBAGHI,

solving procedure that guarantees the correctness ofConrad J. MOORE

the solution. Our experimental results on ITCʼ99 bench-Due to the continuous shrinking of semiconductormarks shows that our method can find the new function

technology, there are more and more subtle errors orafter debug in tens of SAT solver iterations even whenfaults widely distributed in manufactured chips, andthe number of candidates are more than 1000.

traditional “single” stuck-at fault model may become
inappropriate. It is definitely better if all combinationsof multiple faults can be completely tested. Although
there are exponentially more multiple faults than single

Efficient Topological Matching Among Multiple

faults in any given circuit design, our previous works

Circuits

have shown that given an initial set of test patterns for

Masahiro FUJITA, Amir Masoud GHAREHBAGHI

single faults, relatively few additional tests are requirede ear hC

Recognizing similarities and dif ferences amongin order to cover all multiple faults. In this work, themultiple circuits is very useful for managing and main-

exact situations in which test patterns generated bytaining IP libraries as well as merging circuits, fraud

ATPG for single stuck-at (SSA) faults do not detect mul-detection, reverse engineering, and redundancy check-tiple stuck-at (MSA) faults are examined. This will being. We address the problem of finding the maximum

done by presenting proofs which show the conditions

common subcircuit among two or more logic circuits.

that need to be met such that ATPG for single faults

Given the gate-level netlists of the circuits, first we rep-

can cover all multiple faults. An analysis is then per-resent the circuits as graphs. Then, we try to find theformed to determine the exact conditions that, whenlargest common subgraph with a new approach based

removed from the circuit, violate the assumption thaton signature generation and matching. In this work, we

ATPG for single faults will detect all multiple faults.

have introduced a new hash function for the signatures

Finally, we have proposed ATPG algorithm whichalong with its efficient implementation that resulted

detects up to double stuck-at (DSA) faults. Our exper-

in almost an order of magnitude faster matching com-iments show that with the proposed methods, only asmall number of double faults have to be considered

ever, outputs are wrong in a real chip. This is caused

explicitly for test generation, as all the remaining ones

mainly by electrical bugs, which are caused by elec-

are already covered by the test patterns for single fault.

trical factors. It is difficult to reproduce them because
their occurrence depends on operating histor y andconditions. Thus, debugging them is very time-consum-

Communication Aware Compiler for Reconfigurable

ing. To address such problems, trace buffers which are

Processors

on-chip memories are used to record values of some

Masahiro FUJITA, Amir Masoud GHAREHBAGHI,

flip-flops. Some untraced flip-flop values are restored

Qinhao WANG, Lu YI, Tomohiro MARUOKA

from them. Using recorded and restored values, we try

Program optimization on highly parallel systems

to narrow down candidates of electrical bugs by check-is considered a hard work almost with experts doinging exhaustively whether there is possibility that elec-much of performance tuning by hand. In addition, withtrical bugs can be occurred at each flip-flop and at eachthe transistor size development, in deep submicron

cycle.

technology, the interconnection latency of inter-coredata transfer now become
dominating the system latency. These problems

Acceleration of Neural Network with FPGA

cause many-core system performance still underuti-

Masahiro FUJITA, Amir Masoud GHAREHBAGHI,

lized in many scenarios. In this work, we propose an

Tomohiro OKAMOTO, Masato NEISHI

integer linear programming(ILP) based method to

Dedicated hardware is generally faster and more

analysis and optimize program data flow graph on aenergy-ef ficient than a general hardware. A circuit

mesh-structured processors array. The proposed model

optimized for specific calculation can be obtained with-includes interconnect-aware function unit binding andout chip fabrication using a Field Programmable Gate

mapping. as well as data transformation routing. With

Array (FPGA), which is a programmable circuit. In this

this formal and flexible ILP based formulation, we got

work, we have considered acceleration of simulation

the optimized binding, mapping and routing result forof neural networks with multiple FPGA chips. Neuralspecific program on target architecture. This ILP based

network is a mathematical model of the mechanism of

formulation can be used for high level ECO while doa brain. We implemented a highly pipelined circuit onhigh level synthesis, as well as estimate the FU bindinga FPGA to simulate the network composed of 768 spik-

on software defined system.

ing neurons and we could achieve 93x faster operation
than real-time brain on single FPGA. Furthermore, we

Partial C Program Synthesis
Masahiro FUJITA, Yusuke KIMURAFPGA chips that are connected through a ring network.
Our proposed method is able to distribute the opera-

This research targets the method to synthesize ations of 7,400 ( = 768 * \sqrt{93} ) neurons among 93

C program using so-called a “template” which is a C

FPGA chips connected through a ring network suchprogram including vacant places, and some use-cases.

that the operation of the neural network is performed at

CEGIS (Counter Example Guided Inductive Synthesis)

the speed of a human brain.

number of use-cases are enough to synthesize the C
program.

Mapping and routing method for the FPGA which
has wires between only neighbor blocks

3-1
29

e ear his utilized and our experimental results show that small

Chapter 3

have proposed partitioning of neurons among multiple

Masahiro FUJITA, Tomohiro MARUOKA
Narrowing Down Candidates of Electrical Bugs

becomes faster and its cost becomes lower, but theMasahiro FUJITA, Amir Masoud GHAREHBAGHI,

timing closure problem has become a major problem.

Kentarou IWATA

Therefore, to prevent the problem, we consider theAs VLSI becomes denser, placing and routing

FPGA model which has wires between only neighborbecome more difficult. In these circumstances, there

blocks. In this research, we propose the method ofis the case that the function is correctly designed, how-mapping and routing on the FPGA model by formu-

C

Using Trace Buffers

As the integration degree of FPGA increases, FPGA

Ikeda Laborator ylating constraints on mapping and routing as Integer
Linear Programming (ILP) program. Since we could(http://www.mos.t.u-tokyo.ac.jp)

not get a solution in a short time only by the ILP meth-

Current Research Projects

od, we tried to divide a circuit and apply the ILP method to get an acceptable solution in a short time. We
simulated mapping and routing for some benchmark

High-performance Cryptographic Engine Design

circuits on the FPGA model, and it became possible to

M. Ikeda, H. Awano, T.Ikeda, T. Ichihashi, R. Saito,

implement it with a practical number of cycles in small

K. Koga, and F. Arakawa

circuits.

We have designed scalable multi-operation general
purpose cryptographic processors, whose circuit area
and operation times are tunable over a wide range ofTakamiya Laborator y(http://icdesign.iis.u-tokyo.ac.jp/)

values using implementation parameters. One of theconfigurations, synthesized using 65 nm SOTB CMOS
library, with a circuit area of 638k gates, can execute
an elliptic curve scalar multiplication operation in justEnergy Efficient Design for IoT Devices

0.16 ms. We have also studied area efficient implemen-

Makoto Takamiya and Takayasu Sakurai

tation of Elliptic Cur ve Digital Signature Algorithm

Requirements for IoT sensor nodes, wearable health-(ECDSA) signature generation / verification. Basedcare devices, and implanted medical devices are theon synthesis over 65 nm SOTB CMOS, we have estab-wearing-unconsciousness and the maintenance-freelished the relationship between area and processing

operation. To enable the wearing-unconsciousness,time for various sets of coordinate systems, algorithms,

mechanically flexible or small-size devices with theand radices, which acts as a quantitative guideline forwireless connection are required. To enable the main-

selection of methods towards area-efficient implemen-tenance-free operation, energy autonomous devices aretation. We have also studied cryptographic processing

required. The energy autonomy is achieved by both theengine for high-speed extension field calculation.

energy efficient operation and the energy harvesting.
Self-Synchronous System based on Dynamic
Large Area and Flexible Electronics with Organic
Transistors

Circuits
M. Ikeda, and Y. Kim

Chapter 3

In this research, we investigated the low voltage

Makoto Takamiya, Takao Someya, andLarge area electronics is a new frontier in electron-

Voltage Switch Logic (DCVSL), a dynamic circuit used

ics where intelligent electronic devices are distributed

in construction of completely asynchronous circuits,

3-1

on a flexible surface, 10 cm to 10 m on a side, for theparameterized by the number of inputs. We evaluatedhuman interface and the comfortable daily life. Flexible

by performing measurements on a SOTB 65 nm CMOS

and low-cost organic FETs (OFETs) are suitable forchip, with 2 to 6 input transistors optimized for low

large-area electronics and have great potential as a sup-voltage operation, with operating voltage limit, power

plement of solid and expensive silicon MOSFETs for

consumption, delay and power delay product as per-

VLSIʼs. We have proposed and demonstrated several

formance indices. This research aims at aiding a morelarge area and flexible applications including a surface

efficient realization of low power operation dynamic

electromyogram measurement sheet for prosthetic

circuits.

30

Takayasu Sakurai

operating characteristics of Dif ferential Cascodee ear hhand control, a flexible wet sensor sheet for biomedicalCapplications, and a fever alarm armband.
3D-range finding and Secure Sensing by Smart
Image Sensors
M. Ikeda, T. Kikkawa, E. Kume, U. Kim, V.G. Vishwa,
N. Toyoshima, and M. Tanibuchi
We are trying to propose new methods for 3-D mea-surement, with advanced functionality, and secure sens-

devices with higher sensitivity and functionality, theing.

team is working on small-gap electrode fabrication pro-

In 3-D measurement, we have proposed a new meth-cess. The team takes full advantage of newly-acquired

od with the capability of selective light detection and(in 2013) rapid electron beam writer F7000S-VD02.

background suppression, and studied a new circuit with

The capability of high electron dose and sharp edge

in-pixel polarized information acquisition.

due to cell (character) projection machine configura-In secure sensing, we are studying strong and lighttion is used for fabrication process. The target of firstweight sensor data security scheme involving novel

year is reliable sub 100 nm gap electrode fabrication, as

architecture at circuit level. We have proposed anwell as microactuator-integrated nanogap system.

interference attack method against phase shift method
and also proposed a method of protection against theattack. We have also studied pixel parallel analog front-

University-Industry collaborative research on high-end architecture for THz imaging.

ly-functional system by MEMS post-process of
CMOS-VLSI
Y. Mita, K.Tohyama, Y.Nakayama (Konica Minolta),

Mita Laborator y(http://www.if.t.u-tokyo.ac.jp)

M.Takiguchi (Sony), Y.Sato (Nanox Japan)
The research targets are new sensor devices, madeby post-process at clearnrooms such as VDEC Takeda
Supercleanroom and others, of VLSI wafer made

Programmable Matter - Study on LSI-MEMS ener-

through VDEC. The important finding has been thatgy-autonomous distributed microsystems for reali-

VLSI wafer acquired just after transistor fabrication

zation of deformable matter

could sustain processes even with heat treatment, such

Y. Mita, N.Usami, J.Bourgeois,

as deposition, ion implantation, and drive-in. In 2016, a

B.Piranda (FEMTO-ST, France),

VLSI device made on Silicon-on-Insulator (SOI) wafer

S. Delalande (PSA-Peugeot)

was successfully Deep-RIE processed. The industrial
interest is its versatility–many different types of applica-

to open new research and industrial application fields,tion devices, which differ one from another according

the authors are trying to show a top-down application

to request of market, can be fabricated by using theof energy-autonomous distributed microrobots. A num-same technology. More and more companies are inter-ber of identical tiny robots, sized below 1 cm, will be

ested in the scheme and are working on the technology

released in an environment. Individual robot can com-on the collaborative research projects.

municate with their neighbor, can stick each other, canshare energy, to realize cooperative function. The PI
has received a French National Research Center (ANR)

LSI hot-spots active cooling system

grant on behalf of host professor of CNRS laboratory in

Y. Mita, Y. Okamoto, K. Fujimoto (Titech),the Institute of Industrial Science (LIMMS, CNRS-IIS,

H.Ryoson (Titech), and T. Oba (Titech)
A hotspot, which is referred to a high-temperature

PSA-Peugeot Laborator y for such “micro robots thatarea due to the overheating of a circuit block thatcan realize deformable substance by cooperative action,

excess passive cooling capability, is becoming a key

named Programmable Matter”．Target is set in under-

limiting factor of LSI performance. An active coolingstanding on physics and devices working in aqueous

system that tries to actively remove such local heating

environment.

by circulating liquid coolant is our research target. In

3-1
31

e ear hUMI 2820), together with FEMTO-ST Laboratory andChapter 3

As one example of integrated MEMS that is expected

FY2016, an out-of-plane cooling scheme was confirmed
Top-down fabrication of small-gap electrode devices

iments, modeling with equations, and finite element

by Fine E-Beam writing and MEMS process

method simulations.

Y. Mita, Y.Takeshiro, N.Washizu, A.Takada,M. Fujiwara, T.Sawamura, R.Ikeno, and K. Asada
Towards the goal of production of brand-new sensor

C

to be efficient for heat removal, by test structure exper-new functional device called “Neuron MOS Transistor”
Assessment of through-the-chip backside Focused(neuMOS or ν MOS) which mimics the action of a

Ion Beam (FIB) process to transistor characteristics

nerve cell neuron at a single transistor level. Based on

Y. Mita, N.Usami, J.Kinoshita (Toyotsu Electronics Van

such architecture that “association” is the very comput-

Partners), R. Ikeno, Y. Okamoto, and K. Asadaing primitive, we are pursuing human-like intelligence

VDEC acquired a new Focused Ion Beam machine

system implementation directly in silicon integrated

FEI V400ACE in FY 2013, due to supplemental nation-

circuits. Currently research is in progress for robust

al budget decided in 2012. The machine can makeimage recognition and classification processing includ-

through-the-chip etching of VLSI, with capability of

ing robust feature extraction. The sate-of-the-art silicondual-side alignment of infrared (IR) camera and CAD

technology has been utilized to implement such asso-

data. The research aimed at assessing an impact of

ciative processors in both analog and digital CMOS

such through-the-chip FIB process on transistor char-

VLSI chips, and was published.

acteristics. The result revealed a necessity of composing both high-speed (but less precise) and low-speed(but more precise) etching recipes to minimize transis-“Zeolite-Electronics-Nanostructure (ZEN)” integrated

tor characteristics change.

chemical sensor
Y.Mita, K. Yamada, Y.Okamoto, M.Denoual (ENSI deCaen, France), Tixier Mita Agnès, Eric Lebrasseur,

An LSI probing system with CMOS-MEMS
Y. Mita, R.Setoguchi and Y. Okamoto
The team is developing a “MEMS” probe card for

Chapter 3

3-1

Hussein Awala (ENSI de Caen, France), Julien Grand(ENSI de Caen, France), Sveltana Mintova (ENSI deCaen, France)electron device testing such as VLSI. The originality is

One of the most impor tant application field of

to integrate CMOS circuit to provide high functionality.

MEMS is sensors that can detect physical and chem-

In the year 2014, a piezo-resistive stress measurement

ical amount that cannot be sensed by human beings.

circuit was developed to quantify real stress put on the

Following a long history of the groupʼs research, theprobe. A company-made polysilicon resistor, madeteam was appointed in 2015 as a JSPS-CNRS bilateralby post-processing commercial CMOS 0.6 µm 1P2M

cooperative research project grant. The goal of thecircuit, was integrated into cantilever and responded

research is to develop a chemical sensor by integrat-

to the stress with good gauge factor (around 20). The

ing Zeolite material that is new to VLSI, and applying

technology has been standardized and could be applied

post-process on it. Within one year, the team have suc-to other groupsʼresearch work. Also, to have reliable

cessfully demonstrated two types of devices: a zeolite

microprocess, a test structure to visualize end-point ofchemical sensor by resonant frequency shift detection,

Deep-RIE process is developed.

and by thermal capacity change detection according
chemical concentration. A reliable embedding methodof zeolite into 3D silicon MEMS trenches have been

Right-brain-computing integrated circuits: associa-

developed as well.

tive processing systems

32

N.Yamashita, Y.Mitae ear hfast execution of numerical calculations. However, their

sensor for cyber physical system

performance is extremely poor in such tasks like see-Y. Mita, R Ranga Reddy, N. Usami

Digital computers are dedicated machines for vary

Development of shock resonant spectrum (SRS)C

ing, recognizing, and taking immediate actions, which

VDEC is awarded a Japanese JST–Indian DST joint

are ef for tless tasks in our daily life. This research

grant (SICORP) for cyber physical systems research,aims at building intelligent VLSI systems based onin cooperation with IIT Bombay campus. The teamthe psychological model of a brain. In our system pastis participating the project through a Shock Resonant

experience is stored as template vectors in non-volatile

Spectrum (SRS) sensor, which has been a researchvast memories and the maximum-likelihood event totheme of 2012-2014. A new Ph.D student from India isthe current event is recalled in real time by a fully par-assigned and fabrication process was recovered.

allel processing. The key ingredient of the system is ademonstrated ver tical GaAsSb/InGaAs TFETs. We
Development of LSI post-processing for hybrid inte-

have also investigated Ge/s-Si TFET for high Ion opera-

grationtion.

Y. Mita, D. Lämmerer, A. Mizushima, E. Ohta,
N. Kondo, T. Momose (Material Eng.)
To provide new capability to Nanotechnology

Si CMOS photonics

Platform Users, a couple of process technologies

M. Takenaka, S. Takagi, Y. Kim, J. Han, J. Kang,for LSI hybrid integration is under development. In

K. Takeuchi

FY2016, a stable gold electroplating system was pur-We have proposed Ge CMOS photonics platform bychased and a bump plating for LSI flip-chip bonding

using wafer-bonded GeOI wafers on which Ge CMOS

was developed. In parallel, a supercritical fluid depo-

and Ge photonic-wire devices are monolithically inte-

sition (SCFD) machine was restored to investigate

grated. We have successfully demonstrated Ge photon-

trench embedding deposition with metal.

ic-wire waveguide operated at mid-infrared wavelengths
on the GeOI wafer. Optical modulation by carrier injection into the Ge waveguide was also demonstrated for

Takagi-Takenaka Laborator y(http://www.mosfet.k.u-tokyo.ac.jp/)

the first time. For strained SiGe optical modulators, wehave proposed MOS-based optical modulators fabricated by wafer bonding. We have established the void-lesswafer bonding technology by using Al2O3/HfO2 interfa-

III-V/Ge Metal-Oxide-Semiconductor (MOS) FETscial layer for wafer bonding.

S. Takagi, M. Takenaka, Cai Weili, Yu Xiao,
WuKang Kim, Chang Chih-Yu, Ke Mengan,
Liao Chenyu, Aya Shimada
We have conducted the research on high-peformance
III-V/Ge MOSFETs.

III-V CMOS photonics
S. Takagi, M. Takenaka, Y. Chen, J. Park, S. Takashima,
N. Sekine

We have investigated InGaAs gate stack technolo-

We have investigated the III-V CMOS photonics

gies by using La2O3/InGaAs MOS interfaces. We haveplatform by using III-V on insulator wafer. On the IIIV-OI wafer, III-V MOSFETs and III-V photonics can bemonolithically integrated. We have successfully inte-extremeley-thin body Ge-on-Insulator MOSFETs bygrated an InP grating coupler with waveguide InGaAs

using wafer-bonded GeOI wafers. We have revealed thephotodetector (PD) on the III-V CMOS photonics

physical mechanism which degrades hole mobility inplatform. We have also revealed that a depletion-based

the ultra-thin Ge channel.

InGaAsP optical modulator exhibits 4 times higher
modulation efficiency than Si. We have also clarified
the mechanism of quantum well intermixing on the III-

Tunnel FET

V-OI wafer. In addition, the bandgap wavelength shiftof more than 100 nm has been demonstrated, enabling

Daehwan An, Takumi Kato, Yoon Sanghee

active-passive integration on the III-V CMOS photonics

We have investigated tunnel FETs (TFETs) which
can exhibit steep subthreshold slope for low-power
operation. Lateral InGaAs TFETs and GaAsSb/InGaAs

platform.

3-1
33

e ear hS. Takagi, M. Takenaka, Min-Soo Kim, Takahiro Gotow,

Chapter 3

shown that La2O3 deposted by ALD enable superior
MOS interfaces for InGaAs. We have also fabricatedhetro-junction TFETs have been explored. By growing GaAsSb/InGaAs hetrostructure by MBE, we haveCVLSI Design and Education Center, The University of Tokyo
Annual Report
October, 2017
Published by
VLSI Design and Education Center, The University of Tokyo
Director Kunihiro Asada
Address: Yayoi 2-11-16, Bunkyo-ku, Tokyo, 113-8656, Japan
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VLSI Design and Education Center The University of Tokyo 2017