Message from Director of VDEC
VLSI Design and Education Center (VDEC), The University of Tokyo
Director

Masahiro Fujita
VLSI Design and Education Center (VDEC) was established in 1996 in the University of Tokyo as an organization that provides nation-wide services. Its mission isto provide all Japanese academia with practical educational and research environments through semiconductor development, manufacturing and prototyping of
new devices. Unique opportunities to learn about real
semiconductor development, design and manufacturing that cannot be obtained from desk-based learningand exercises have been provided. Through suchopportunities, one can acquire knowledge in all
aspects related to semiconductor systems. As a result,
it is expected that the various technical capabilities ofJapan in the semiconductor from design to manufacturing can be significantly improved.
In fact, there are organizations all over the worldthat are considered to have the same mission as VDEC.
There are organizations and mechanisms in the UnitedStates, Canada, Europe (two), South Korea, Taiwan,
and most recently in mainland China. These organizations hold meetings for information exchange andcooperation basically twice a year. Each organization
has various strengths based on the situation in theregion, and cooperative activities to make the most ofthese strengths are carried out. As a result, we are
now able to carry out international joint chip prototyping smoothly, and we will be able to work more closely together in the future to launch international joint
projects.
On the other hand, VDEC differs from the other similar organizations around the world in that it not only
supports designs and prototyping of semiconductor

chips, but also a research and development environment in a clean room for new semiconductors anddevice by providing a variety of advanced equipmentthat is funded by governmental projects. Users canresearch and develop new semiconductor-related technologies on their own in a clean room. Normally, thedesign and prototyping of a semiconductor chip isbased on the devices that have already been developed. Although this refers to prototyping, VDEC is not
only limited to prototyping, but also to implementing
chips in combination with new devices. This has madeit possible to realize new semiconductor systems thatgive previously unimaginable performance and shape,and has made it possible for us to develop productsthat lead the world. However, the research and development of semiconductor technology using the twoenvironments provided by VDEC is never performed,
and hence it is not at all easy. The truth is that theusers of those two environments do not know muchabout each other. We have realized that it would be
difficult for VDEC alone to achieve it. Therefore, incoordination with developments within School of Engineering, VDEC was re-born on October 1, 2019 as
System Design Research Center within School of Engineering.
In the future, it will become normal to collaborate
with the engineering departments and the information
science and technology departments for the integrated use of the two environments. Through this wewould like to become the center of semiconductor
technology in Japan and also in the world. We lookforward to your support so that we can work better.

Message from Director of d.lab
System Design Lab (d.lab) Center, School of Engineering, The University of Tokyo
Director

Tadahiro Kuroda
Even what appears to be a discontinuous event has a story withwell-connected pieces leading up to it. The Systems Design Lab(d.lab) was established in October of last year. You must be wondering what happened to VDEC with this sudden reorganization. Letme provide you with the background.
From 1996, for a quarter century the VLSI Design and Education
Center (VDCE) offered unparalleled, outstanding education andproduced excellent minds for the semiconductor industry. Every year,
its design environment and chip prototyping service were employedat more than 300 research labs across the country, while its clean
room and related facilities were utilized by more than 200 researchlabs.
However, our outstanding graduates who have entered the semiconductor industry are not always able to fully realize their potential.
In this quarter century, while the worldwide semiconductor industry
maintained a high annual growth rate of 7%, Japan’s semiconductor
industry was on the decline. Why is it that even with the world’s top
minds we have not been able to compete neck and neck with therest of the world?
While there are various theories, mine is that Japan lost the competition of capital investment.
As you know, semiconductor is a low margin business which relies
on volume from mass-produced, general-purpose chips for profit.
The demand for large volume of general-purpose chips is fueled by
the adoption of the von Neumann computer architecture. A majorityof the industry’ s revenue is generated from the sale of large volume
of low-price processors and memory. With the adoption of big data
gaining momentum, sensors should also be added to the fold.
In such a business you compete on capital investment. When adevice like DRAM, flash, CPU or GPU is invented, and its large business potential is recognized, fierce competition follows immediately,
resulting in industry realignment and eventually consolidation.
Japan won in device innovation but lost in capital investmentcompetition.
However, we are now on the cusp of a new era with a gamechanger on the horizon. Convinced that it is impossible to win byemploying only general-purpose chips from dedicated chipmakers
the like of Intel and Qualcomm, IT giants such as GAFA haveembarked on in-house development of specialized chips.
There are 3 reasons for that. The first is the unique energy crisis
faced by data companies. As a result of the crisis, only those who
can improve energy efficiency 10-fold can achieve 10-fold increase incomputing performance, or 10-fold increase in smartphone battery
life. Compared to general-purpose chips which can be used toperform every possible function, specialized chips can achieve amore than 10-fold increase in energy efficiency by eliminating
unnecessary circuits.
The second reason is the rise of AI. AI in the form of neuralnetworks and deep learning offers a new way of information
processing to owners of data. Similar to our brain, neural networks
are based on wired logic where functionality is defined by how thecomponents are wired together. Furthermore, data is processed in aparallel fashion which enables a more than 10-fold improvement in
power efficiency compared to the sequential data processing of von
Neumann architecture.
The third reason is the adoption of the fabless model by theindustry. Under this model, pure-play foundries such as TSMC offer
manufacturing services to the world, which enables any user adopting a business model of providing proprietary chips with maximum
AI performance to develop their own chips. For companies offeringa hardware platform solution that drives the demand for sufficiently
large chip volumes, in-house development allows them to acquire
more quickly higher performance chips at lower cost than procuringfrom dedicated chipmakers.
As a result, a game changer in the form of a shift from general-purpose to specialized chips is happening.
The rise of general-purpose chips is initiated by device innovation,
while its fall results from capital investment competition. Meanwhile,
the rise of specialized chips is initiated by design and development
innovation, while its fall is driven by Moore’s Law.
ASIC (Application Specific Integrated Circuit) had a sizable market
between 1985 and 2000. In the 1980’ s, research and development
efforts led by the University of California at Berkeley resulted in thecreation of automatic layout and logic synthesis technology as wellas the birth of chip design tools vendors. Furthermore, a semi-custom manufacturing process like the one used in tailoring clothes wasdeveloped where a semi-finished chip was made first like a standard
product, which was then tailored towards different applications bycustomizing the interconnect layers.
Using these design and development innovations, chip development productivity improved dramatically by three orders-of-magnitude in total. Nevertheless, with Moore’ s Law increasing integration
density by three orders-of-magnitude in 15 years, even with computer-aided design chip development took more man-hours thanever. This contributed to profit erosion of the ASIC business which
eventually resulted in its demise.
However, Moore’ s Law is now slowing. In the next quarter century, we expect winners in the new arena to be those who lead indesign and development innovation.
The development of specialized chips requires academic knowledge instead of capital investment. Development of automaticlayout and logic synthesis was previously driven by the University ofCalifornia at Berkeley. Similarly, university research will play an
integral role in creating the foundational knowledge required forautomatic generation of functionalities, systems, and so on.
The 20th Century was dominated by “general-purpose.” After thewar, in a quest for material gratification and economic efficiency,
economic growth was driven by mass production of standardized
products.
However, as modern society matures, what we value has shiftedfrom collective growth to personal fulfillment. This has resulted in
the transition from an industrial to a knowledge-based society.
While this transition was spreading from developed to developing
countries, Japan was able to enjoy a period of prosperity by continuing to mass-produce standardized products. But eventually when thetransition was complete, Japan fell behind other Asian nations due
to its slow adaptation to the transition. This is what I believe to be
the societal background for the decline of Japan’ s semiconductor
industry.
The 21st century looks to be the century of “specialization”. The
center of our value is shifting from being capital-intensive to being
knowledge-intensive, from scale to knowledge, from increase inquantity to improvement in quality, from material to spirit, fromconvenience to joy, from products to services, from large volume tolarge variety, from standardization to individualization, from what
everyone can do to what no one else can do.
How should the manufacturing industry adapt to such a shift? It isd.lab’s mission to search for an answer.
In addition to education, we strive to utilize the power of ourscholarship to contribute to the advance of industry and society.
With the newly established Advanced Design Research Division andAdvanced Device Research Division focusing on collaboration withindustry, in addition to the Platform Design Research Division(formerly VDEC) and Platform Device Research Division (formerly
Takeda Cleanroom) focusing on education, we at d.lab are embarking on this new journey.

1

2020
VLSI Design and Education Center,
The University of Tokyo
Annual Report

C

O

N

T

E

N

T

S

Message from Director of VDEC
Message from Director of d.lab ………1

Chapter1

Introduction of d.lab…………………………………………… 4

Chapter2

Activity Report of VDEC……………………………………… 5

2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8

Introduction of VDEC activities and activity report of FY2019 ………5
VDEC CAD Tools ………8
VLSI Chip Fabrication ………10
Seminar ………13
Facilities ………16
Activity plan for 2020 ………18
Venture companies related to VDEC ………19

Platform”“Nanotechnology
Ultra Small Lithography and Nanometric Observation site ………20

Chapter3 Activity Report of ADVANTEST D2T Research Division………… 21
3-1 Introduction of ADVANTEST D2T Research Division ………21
3-2 Report of the 14th D2T Symposium ………22
3-3 Research Activity Reports of the ADVANTEST D2T Research Division ………24
3-4 Publications ………25

Chapter4

Research in VDEC………………………………………………… 26

Chapter1

1-1

Introduction of d.lab

Chapter1 Introduction of d.lab

The Systems Design Lab (d.lab) was established in Oc-

sign environment and chip prototyping service were em-

tober of last year. In addition to education, we strive toployed at more than 300 research labs across the country,

utilize the power of our scholarship to contribute to thewhile its clean room and related facilities were utilized byadvance of industry and society. We are embarking on thismore than 200 research labs. In this annual report, wejourney with the newly established Advanced Design Re-

will summarize its activities and accomplishments in the

search Division and Advanced Device Research Division

2019 fiscal year.

focusing on collaboration with industry, in addition toThis annual report is structured as follows. Chapter 2

the Platform Design Research Division (formerly VDEC)

introduces the operation of VDEC and reports on its ac-

and Platform Device Research Division (formerly Takeda

tivities in 2019. Chapter 3 summarizes the activities of the

Cleanroom) focusing on education.

Advantest D2T Research Division. Chapter 4 provides an

From 1996, for a quarter century VDEC offered unparalleled, outstanding education and produced excellent
minds for the semiconductor industry. Every year, its de-4

overview of the research conducted at the individual labs
within VDEC.

Chapter2

2.1

Activity Report of VDEC

Introduction of VDEC activities and activity report of FY2019
design and design flow in universities have been well es-

sity of Tokyo was established in May 1996. VDEC hastablished. On the other hand, advancement on nano-me-

been operating for the following 3 major roles: “spreading

ter CMOS technologies forces design flow and CAD soft-the latest information on VLSI design and education,”ware complicated. We have been continuing CAD tool“providing licenses of CAD tools,” and “supporting on

seminar by the lecturers from EDA vendors for twice a

VLSI chip fabrications for academic use.” VDEC has

year. We hold the seminar in VDEC and provide distancebeen reorganized, to empower VLSI design activities inlearning through video streaming. We expect spread of thethe University of Tokyo, as Systems Design Lab(d.lab),

up-to-date LSI design methodology by using CAD tools.

Graduate School of Engineering, the University of Tokyo,

We assume our LSI design flow seminars as educations

and VDEC activities has been continued as the VDEC

on basic LSI design concepts and practical experience offunctionality in the Fundamental design division of d.lab.

LSI design with CAD tool chain. VDEC holds “LSI de-

The VDEC activity report of FY 2019 is described hereaf-

sign education seminar”, a.k.a. VDEC Refresh Seminar,

ter according to Fig. 2.1.

once a year. This year we hold 3 courses, “Analog design

The missions of VDEC are for advancement of re-course” and “RF design course”, and initiated “MEMS

searches and education on LSI design in public and pri-design course” in July-September time frame. We invite

vate universities and colleges in Japan and send many dis-experienced professors among universities as lecturers fortinguished VLSI designers into industry. After 24 years of

the courses to conduct LSI design education courses with

VDEC establishment, educations on CAD software, LSI

practical experience. We also hold “Transistor level design

2-1
Chapter2 Activity Report of VDEC

VLSI Design and Education Center(VDEC), Univer-

Fig. 2.1 VDEC activities

5

2-1

flow in VDEC” and “Digital design flow in VDEC EDA

messages” come out from CAD softwares, even after theyenvironment” for designers in universities. We started tosuccessfully setup CAD tools. In such situations, VDEC

charge these two LSI design education courses, as well as

mailing-lists make significant contributions. VDEC users

VDEC Refresh Seminars.

can register to VDEC mailing-lists on CAD tools, andChapter2 Activity Report of VDEC

In addition to the above seminars, we hold “VDEC De-

process dependent groups through VDEC web pages, andsigner’ Forum” among young professors and students an-

can ask questions and helps on their facing issues. It is notnually. This is a workshop that the participants exchangea responsibility for the registrant of such mailing-lists totheir design examples with not only success stories but

give answers to questions, however, in most cases, replies

also their failure stories, in addition to invited talks. We

are given by the experienced users of CAD tools and ex-

expect students and professors who will start designs toperienced designers within a couple of hours to a couple

learn kinds of know-hows. We have initiated “IEEE SSCSof days. Moreover, emails are accumulated and are open

Japan Chapter VDEC Design Award” this year, and fi-

to the VDEC users, as shown in Fig. 2.2, who have reg-

nal examination and awarding have carried out duringistered VDEC accounts, as the important educational as-

the “VDEC Designer’ Forum”. Mr. Y. Fujiwara(Tohoku

sets. We expect all the VDEC users to make the full use ofUniv.) is awarded as “IEEE SSCS Japan Chapter VDEC

this mechanism to help solve problems.

Design Award” winner, and Mr. Y. Fujiwara(Tohoku

We continue chip fabrication services on SOTB CMOS

Univ.), Mr. H. Zhang(Tokyo Institute of Technology),

65nm by Renesas Electronics, 0.18μm CMOS by Rohm

and K. Sugie(Nara Institute of Science and Technolo-

and 0.8μm CMOS by On-semi Sanyo Semiconductor.

gy) are awarded as “the best VDEC Design Award”, andOur donated division “Design To Test(D2T)”, which

Ms. J. Pang(Tokyo Institute of Technology), Mr. H. Ka-

was founded by donation from Advantest in Oct. 2008,

wauchi(Shizuoka Univ.), and Mr. K. Matsuyama(Shizuo-

focuses on enrichment of education on LSI testing andka Univ.) are awarded as the “VDEC Design Award.”

bridging between design and testing.

LSI designers come up against various difficulties dur-Fig. 2.3 shows trends of number of papers throughing actual LSI design scene, even after the basic educa-

VDEC activities. Number of papers is increasing, whichtions through various seminars and the forum. One ofmeans researches in the field of VLSI design have been

the biggest problems for beginners is the setup of CAD

encouraged after VDEC establishment.

softwares. Many of them also get confused by “EsotericFig. 2.4 shows number of papers related to CAD usage,

Fig. 2.2 Archives of emails of VDEC mailing-list.

6chip fabrications and VDEC facility usages. CAD tools
are widely used to write papers. CAD tools are used not
only chip designs themselves but also used for preparationof chip fabrication and they contribute to verify fundamental ideas of researches.

2-1
Chapter2 Activity Report of VDEC

Fig. 2.3 Trends of number of papers through VDEC activities.

Fig. 2.4 Number of papers related to VDEC facilities.

7

2.2 VDEC CAD Tools

2-2
Chapter2 Activity Report of VDEC

Since 1996, VDEC has provided CAD software licens-

other public universities, private universities, and colleges.

es to the registered researchers in universities and colleges

When one is going to use VDEC CAD tools and chipin Japan. The CAD tools we provided in 2020 throughfabrication service (the details are described in Section

the activities of VDEC in Systems Design Lab (d.lab) are1-3), some faculty member of his/her research group in

shown in Table 2.2.1. The researchers can use those CAD

a university or a collage needs to do user registration.

tools when their local machines, whose IP addresses are

Figure 2.2.2 shows (a) the number of registrants, (b) the

registered in advance, are authorized by one of VDEC li-

number of distinguished universities/colleges of the reg-cense server located in the ten VDEC subcenters shown in

istrants, and (c) the number of registrants who applied

Figure 2.2.1. For each CAD tool, VDEC provides 10-100

VDEC CAD tools, (d) the number of applied licenses offloating licenses. Those CAD tools can be utilized only for

all CAD tools.

research and education activities in national universities,
Table 2.2.1 VDEC CAD tools
Name
Cadence tool set

Synopsys tool set

Mentor tool set
Silvaco tool set
ADS/Golden Gate
Bach system
LAVIS

Function
VendorVerilog-HDL/VHDL entry, Simlation, Logic synthesis, Cadence Design Systems, Inc.
Test pattern generation, Cell-based (including macros) place, route, and back-annotation, Interactive
schematic and layout editor, Analog circuit simulation, Logic verification, Circuit extraction
Verilog-HDL/VHDK simulation, Logic synthesis, Test Synopsys, Inc.
pattern generation, Cell-based (including macros)place, route, and back-annotation, Circuit simulation,
Device simulation
Layout verification, Design rule check
Mentor Graphics Co. Ltd.
Fast circuit simulation
SilvacoDesign and verification of high-frequency circuits
Keysight Technologies
BachC-based design, synthesis, and verification
Sharp
Layout visualization platform
TOOL

Fig. 2.2.1 VDEC Subcenters

8

2-2

(b) The number of universities colleges of the registrants(c) The number of research group applied CAD tools(d) The number of applied licenses of all CAD tools

Chapter2 Activity Report of VDEC(a) The number of registrants

Fig. 2.2.2 The numbers of VDEC CAD Applications

92.3 VLSI Chip Fabrication
2.3.1 Trends of VLSI Chip Fabrication Services

2-3

advanced CMOS process in 2013. We started SOTB

Fig. 2.3.1 shows a trend of number of designed

65nm CMOS by Renesas Electronics in 2015. We

chips for VDEC chip fabrication services, including

initiated two more chip fabrication trials in 2017, on

pilot project prior to VDEC establishment.

CMOS 0.6um HV from Ricoh, and CMOS 40nm

VLSI chip fabrication is limited to 0.5μm CMOS

Chapter2 Activity Report of VDEC

provided by NTT Electronics during the pilot project in 1994 and 1995. VDEC chip fabrication had
started in 1996 with 1.2μm CMOS provided byMotorola Japan, which is now On-Semiconductor aswell as the 0.5μm CMOS. In 1997, VDEC received
cooperation from Rohm and has started 0.6μm
CMOS process. In 1998, VDEC started chip fabrication services of 0.35μm CMOS by Hitachi, andin 1999, VDEC started 0.35μm CMOS by Rohm.
We had a test chip fabrication of 0.13μm CMOS by
STARC through “IP development project” in 2001.
We added 0.18μm CMOS by Hitachi into our chip(a) Trend of number of designs fabricated.

fabrication menu in 2001. From 2002, we started
VDEC-MOSIS chip fabrication program initiated by Prof. Iwata of Hiroshima University. Under
this program, VDEC member can access to TSMC
and IBM processes with lower price. We also started
Bipolar chip fabrication by NEC Compound Semiconductor Devices. In 2004, we started 0.15μm
SOI-CMOS chip fabrication by Oki Electric as test
chip fabrications. In the same year we started 90nm
CMOS chip fabrication by ASPLA/STARC. In 2006,
we started 0.18μm CMOS by Rohm and 0.25μm SiGeBiCMOS by Hitachi. In 2008, we started 65nm
CMOS process by eShuttle, after closure of 90nm
CMOS chip fabrication in 2007. In 2010, we start-(b) Trend of designed area.

ed 40nm CMOS process by Renesas Electronics
through “Next Generation Semiconductor Circuits& Architecture” project between METI and STAR.
On the other hand, 1.2μm CMOS chip fabrication
program came to end by the September 2011. 40nm
CMOS by Renesas Electronics and 65nm by eShuttle also come to end by Oct. 2012 and Aug. 2013,
respectively. We started CMOS0.8μm in Oct. 2012by On-semiconductor-Sanyo as a test chip fabrication and opened it as the regular chip fabrication
menu in 2012. We started FD-SOI 28nm CMOS
by ST-Microelectronics through CMP, France, as the(c) Trend of designed area normalized by design rule.
Fig. 2.3.1 Trend of number of designs and designed chip area.

10

from Mie Fujitsu.

who have contracted NDA for process technologies

Fig. 2.3.1(a) shows trends of number of chipto access design rules and design libraries are, 91,

designed for VDEC chip fabrication. For the first

287, and 48, respectively, for 65nm CMOS, 0.18μm

6 years until 2001, the number of designed chips

CMOS, and 0.8um CMOS.

shows steady increase, which means drastic improve
2.3.2 Overview of chip fabrication in 2018of the effectiveness researches and education of LSI

Table 2.3.1 lists chip fabrication schedule in 2019.

students related to LSI chip design and education.

Please refer to list in Chapter 2 for details of design-

During few years of stable number around 400 chipers and contents of chip designed.

designs per year, we can see transition of designs toward finer process. In 2007, we saw a large drop,
which was caused by sudden process transition from0.35μm CMOS to 0.18μm CMOS, and in 2008,
we also saw another drop by process transition from
90nm CMOS to 65nm CMOS.
Fig. 2.3.1(b) shows trends of designed chip area,
which shows much clear trends of drop by process
migration. On the other hand, Fig. 2.3.1(c) shows

2-3
Chapter2 Activity Report of VDEC

design, and we assume drastic increase of number oftrends of designed chip area normalized by design
rule, which assume to be strong relation with design
efforts. Coming from the fact that the normalized
chip area is still growing, we assume the major reason for decrease of number of chips and designed
area is increase of design effort per chip and per unit
area due to process scaling.
Fig. 2.3.2 shows trends number of professors andFig. 2.3.2 Trend of number of processors and universities
fabricated chip.

universities fabricated chip. Number of professors

Table 2.3.1 Chip fabrication schedule in 2017
o0.8μm CMOS (On-Semiconductor - Sanyo)
Chip application deadline

Design deadline

Chip delivery

2019 #1

2019/7/8

2019/9/30

2019/12/23

2019 #2

2020/1/6

2020/3/30

2020/6/18

o0.18μm CMOS (Rohm)
Chip application deadline
2019 #1
2019 #4
2019 #2
2019 #3

2019/4/1
2019/6/17
2019/8/5
2019/12/2

Design deadline
2019/6/24
2019/9/9
2019/10/28
2020/2/24

Chip delivery
2019/10/9
2019/12/18
2020/2/20
2020/6/18

oSOTB 65nm CMOS
Chip application deadline

2019 #1
2019 #2

2019/6/17
2020/1/27

Design deadline

2019/7/29
2020/3/9

Chip delivery

2020/2/25
2020/7E

11

2.3.3 Libraries and design flows
VDEC have been working to prepare design libraries and design flows for digital design and PDKs
for analog design. Table 2.3.2 lists libraries available
now.

2-3
Chapter2 Activity Report of VDEC
12

Table 2.3.2 Libraries available for VDEC chip fabrication
Technology

0.18μm CMOS
(Rohm)

Name

AuthorRohm
library

Rohm Library
Std. Cells, IO cells, RAM(Distributed with CDROM)

Kyodai
Library

Onodera Lab., Kyoto University

Todai
Library

VDEC
Design flow based on library prepared by
Onodera Lab., Kyoto University

PDK

VDEC

Contents
Synthesis(Synopsys)
Simulation(VerilogXL)
P&R(LEF/DEF)
Synthesis(Synopsys)
Simulation(VerilogXL)
P&R(Astro)
Synthesis(RTL Compiler)
Simulation(VerilogXL)
P&R(Encounter)
PDK(IC6.1)

2.4 Seminar
Seminars are always needed as the advancement

ed. VDEC offers the CAD Seminar twice per year.

of LSI design technology. In 2019, VDEC has held

In the CAD Seminar, VDEC invites lecturers fromCAD Seminar, Refresh Seminar, and Designer’s Fo-

venders including Cadence, Synopsys and Keysightrum, for academic and industrial circuit designers.

to give tutorials on their CAD tools. The seminar isheld in VDEC, The University of Tokyo and VDEC

Along with advancement of circuit design CAD
tools, tutorials on these tools are highly demand-

sub-centers simultaneously in several universities nationally, August, September, and March of one fiscal
year. Each tutorial takes one or two days.

Table 2.4.1 CAD technical seminar in 2019 fiscal year
CAD Seminar I
Date
8/21
8/21
8/21
8/21
8/21
8/28
8/29
8/29
8/29
8/29
9/17, 18
9/17, 18
9/17, 18
9/17, 18
9/17, 18
44094
44094
9/24, 25
9/24, 25
9/24, 25
9/24, 25
9/24, 25
9/24, 25

Seminar
Synopsys Sentaurus (TCAD)
Synopsys Sentaurus (TCAD)
Synopsys Sentaurus (TCAD)
Synopsys Sentaurus (TCAD)
Synopsys Sentaurus (TCAD)
Synopsys HSPICE
Keysight GoldenGate
Keysight GoldenGate
Keysight GoldenGate
Keysight GoldenGate
Cadence Virtuoso Analog Design Environment(ADE) Explorer
Cadence Virtuoso Analog Design Environment(ADE) Explorer
Cadence Virtuoso Analog Design Environment(ADE) Explorer
Cadence Virtuoso Analog Design Environment(ADE) Explorer
Cadence Virtuoso Analog Design Environment(ADE) Explorer
Synopsys PrimeTime (Basic)
Synopsys PrimeTime (Basic)
Cadence Virtuoso Analog Design Environment(ADE) Assembler
Cadence Virtuoso Analog Design Environment(ADE) Assembler
Cadence Virtuoso Analog Design Environment(ADE) Assembler
Cadence Virtuoso Analog Design Environment(ADE) Assembler
Cadence Virtuoso Analog Design Environment(ADE) Assembler
Cadence Virtuoso Analog Design Environment(ADE) Assembler

Venue
The Univ. of Tokyo
Nagoya Univ.
Osaka Univ.
Akita Prefectural Univ.
Shinshu Univ.
The Univ. of Tokyo
The Univ. of Tokyo
Hiroshima Univ.
Akita Prefectural Univ.
Shinshu Univ.

Attendees
10
0
2
4
3
8
2
5
4
6

The Univ. of Tokyo

7

Kyoto University

5

Hiroshima Univ.

1

Akita Prefectural Univ.

3

Shinshu Univ.

6

The Univ. of Tokyo
Hiroshima Univ.

6
1

The Univ. of Tokyo

6

Nagoya Univ.

0

Kyoto University

6

Hiroshima Univ.

1

Akita Prefectural Univ.

2

Shinshu Univ.

7

2-4
Chapter2 Activity Report of VDEC

2.4.1 CAD Seminar for VDEC users

13

CAD Seminar II
In this fiscal year, CAD Seminar II was held online due to the pandemic of COVID-19.

2-4
Chapter2 Activity Report of VDEC

Date
3/12
3/13
3/16
3/19
3/24, 25
3/16

SeminarCadence PVS
Cadence Quantus
Cadence System Verilog Real-Number Modeling
Synopsys SiliconSmart
Cadence SKILL
Synopsys StarRC

Venue
WebEx
WebEx
WebEx
WebEx
WebEx
WebEx

Attendees
21
15
17
13
24
14

2.4.2 Refresh Seminar for industry and academia
The fundamental and advanced knowledges areboth imperative to integrated circuit design. VDEC
offers the Refresh Seminar for industrial and academic people. University professors and highly experienced engineers are invited to give lectures on
circuit design, covering the topics on analog, digital, RF, MEMs, and basic design flow. The seminar
was originally launched in 1998, with the supportof Ministry of Education Technical Education Division. It is now being supported by several industrial/academic societies.

Fig. 2.4.2 Refresh Seminar at VDEC seminar room at the University of Tokyo, VDEC.

14

Table 2.4.2 Refresh SeminarDate

6/24, 26

6/11, 12

8/5, 6

8/8, 9

8/19, 20

Contents

Analog Circuit Design

Analog Circuit Design and simulation
Integrated Circuits Verification (LVS,
DRC)

MEMS Basic 1: Fabrication Process
MEMS Basic 2: Operation Principle
MEMS Design
Structural Design
Layout Design
CAD Design and Analysis
MEMS Fabrication
Lithography, Etching, Release
Vibration measurement and analysis
Modulation/Demodulation
Cascaded connection
CMOS-RF Circuit
Basic Performance
DesignTransceiver Architecture
Circuit Element
Design Flow
Custom circuit design flow using
VDEC Transistor-Level
VDEC-collaborated CAD environment
Circuit Design Flowand process
Digital circuit design flow using
VDEC Digital Circuit
VDEC-collaborated CAD environment
Design Flowand process

2.4.3 Designer’s Forum for academia

LectureAttendees

Masahiro Sugimoto(Chuo Univ.)
Hidetoshi Onodera(Kyoto Univ.)
Koji Kotani(Tohoku Univ.)

45

Yoshio Mita
(The Univ. of Tokyo)

8

Yoshio Mita
(The Univ. of Tokyo)

4

Hiroyuki Ito(Tokyo Inst. of Tech.)

10

Toru Nakura(Fukuoka Univ.)

7

Kazutoshi Kobayashi(Kyoto Institute ofTechnology)

32-4
Chapter2 Activity Report of VDEC

7/9, 10, 11

Course

LSI designer had been through and the solution, and

VDEC LSI designer forum intended for students
and young teachers were held. The VDEC LSI de-

the construction method in the design milieu in thelaboratory.

signer forum has aimed to sharing the informationthat generally hard to be obtained common technicalreports or academical papers, such as the failure an

Table 2.4.3 Program of Designers Forum in 2019
9/27, 28 Tendo Hot Spring, Yamagata Attendees: 27
9/27
12:00-12:30
12:40-14:20
14:30-16:10
16:20-17:40
19:009/28
9:00-10:00
10:00-12:00
12:00-13:00
13:00-13:10

Reception
VDEC Design Award Presentation I
VDEC Design Award Presentation II
VDEC Design Award Presentation III
VDEC Design Award Ceremony
Idea Contest Presentation
Ph.D Session
Plenary Talk
Closing15

2.5 Facilities

2-5
Chapter2 Activity Report of VDEC

The dlab/VDEC has been providing the big fa-

Major apparatuses purchased through VDEC andcilities for universities in Japan from its establish-

affiliated laboratories courtesy include: High defini-ment (1996). Big facilities refer to those which aretion Scanning Electron Microscope (SEM) Hitachi

impossible to acquire and or maintain by an indi-

Regulus SU-8230 and SEM with Energy dispersive

vidual research unit. Table 1.5.1 shows the available

X-ray spectroscopy (EDX) JSM-6610LV. Also, afacilities of VLSI testers and some process machines,

1kW CO 2 Laser cutter capable of cutting 3mm-thickwhich are placed at the tester room (VDEC 104),

Aluminum plates has been moved to VDEC backend

the super clean room, the backend process room

room (204) The facilities can be used by user him-

(VDEC 204) of the Takeda building. In 2004, theself, after a couple of times’ training by attendance of

VLSI tester (T2000) and the EB lithography ma-licensed users; also, by presence of licensed persons,chine (F5112+VD01) were donated to the VDEC by

a new user can readily use the machine.

the ADVANTEST. In the year 2012, VDEC joined
MEXT (Ministry of Education)’s Nanotechnology
platform to enforce its multi-use capability. (For Nanotechnology Platform refer section 1.8).

Table2.5.1
Facility

Logic LSI test
SystemAvailable facility list
Equipment nameEB tester:
IDS10000

LSI tester:
ADVANTEST
T2000
Auto prober:PM-90-A

Analog/RF
measurement
system16

Analog/RF measurement system:
B1500A, 4156B,
HP4284, etc
Low-noize manual
prober:Cascade Microtec
Low-noize, temperature controlled
semi-auto prober:
Süss Microtec

Description

StatusContact

The chip surface voltage during operation can bemeasured with the LST tester.
The digital circuit with 384 pins, 1GHz can betested.
The digital circuit with 256 pins, 512MHz can betested. Analog test is optional.

Available

nanotech@sogo.t.u-tokyo.ac.jp

Available

nanotech@sogo.t.u-tokyo.ac.jp

Automated prober for testing LSI wafers, which
can be used with the LSI testers. The probe card for
LSIs with the VDEC standard pin connections isavailable.
DC parameter measurement, Capacitance measurement, Network analyzer, Spectrum analyzer, etc.

Available

nanotech@sogo.t.u-tokyo.ac.jp

Available

nanotech@sogo.t.u-tokyo.ac.jp

6 inch wafer can be measured with six DC probles
and two RF probes upto 50 GHz.
8inch wafer can be measured. The chip temperature
range is -50 to 200℃.

Nanotechnology Platform
Apparatuses

Minimum linewidth: 50nm.
Lithography for 5 inch photomask (thickness: 2.3mm), 2-8 inch wafers, and chips is possible.

Available

Rapid Mask andDirect lithography:
F7000S-VD02

Minimum linewidth: 1xnm.
Lithography for 5 inch photomask (thickness: 2.3mm), 2-8 inch wafers, and chips is possible. Stencil
character projection of non-square shapes such as
circle, triangle is possible.

Available

Chlorine ICP plasma etcher CE-S

High density plasma etching with Cl2 and BCl3 ispossible.

Available

Silicon DRIEHigh speed, high aspect ratio etching of silicon is
MUC-21 ASE-Peg- possible
asus

AvailableFIB:
SII XVision200TB

Repair of photomask, sample etching, etc. (Through Available
Nanotech. Platform and LCNet)

LSI FIB system FIB: FEI V400ACE Repair of VLSI from both frontside and backside,
Availablewith CAD navigation and / or IR camera is possible.
W/SiO deposition is possible.
Chip Bonding Wedge Bonder:
SystemWestbond 7476D

25µmφAl or Au wire wedge bonding machine.

Epoxy Die Bonder
Westbond7200C

Precision Manupilator system. Epoxy and or Ag
paste chip bonding and or glued wiring.

Semi-Auto Bonder
Westbond4700E

18〜25µmφAu Ball bonding or bump creation.

Precision Manual
Flip-Chip Bonder Finetech Fineplacer Lambda

Face-to-face bonding up to 15mm square chips.
Alignment is through video camera. Bonding is byheating chips with TV camera. (Ultrasonic Unit can
additionally be purchased.) XY±0.5µm, and θ=1mrad precision.

Available

nanotech@sogo.t.u-tokyo.ac.jp

2-5
Chapter2 Activity Report of VDEC

FIB system

Mask lithography,
Direct lithography:
F5112+VD01

17

2.6 Activity plan for 2020

2-6

VDEC will continue activities on chip fabrication

We will continue analog RF design environment,

services, CAD tool support, dispatching design re-GoldenGate and ADS by Agilent, C-based design

lated information and dovnated division “D2T”, as

environment, BachC by Sharp. In addition, we con-has been previous years .

tinue trial of several CAD tools, such as layout platform, Lavis by TOOL. Design debugging platform

Chapter2 Activity Report of VDEC

【Design related information dispatching/Seminar】

from SpringSoft has merged into Cadence tools andWe will continue holding the following seminars:

will be continued.

(1) CAD tools seminars which have been continued【Chip fabrication services】

since 1997, (2) “Refresh seminar” since 1998, (3)“Designer’ Forum” since 1997. We will also contin-

We will continue chip fabrication services forue seminars for LSI tester usage at VDEC and sub-0.18μm CMOS by Rohm and 0.8μm CMOS bycenters, workshops on LSI testing technologies ini-

On-semiconductor-Sanyo as the regular services.

tiated by D2T.

Chip fabrication services for SOTB 65nm CMOS byRenesas Electronics will be terminated.

【CAD tool support】
We will continue Cadence tools, Synopsys tools
and Mentor tools as the main stream design tools.

Table 2.6.1 Chip fabrication schedule【CMOS 1.2μｍ 2P2M】 On-Semiconductor(Former Motorola Japan)
Chip application deadline
2020#12020#2

2020/4/13
2020/10/12

Design deadline
2020/7/6
2021/1/12

Chip delivery
2020/9/28
2021/3/29【CMOS 0.18μｍ 1P5M(+MiM)】 Rohm
Chip application deadline
2020 #1
2020 #22020 #32020 #4

2020/5/11
2020/9/7

Design deadline
2020/3/16
2020/6/15
2020/8/3
2020/11/30

Chip delivery
2020/6/8→6/29
2020/9/7
2020/10/26
2021/2/22【SOTB CMOS 65nm】 Renesas Electronics
Chip application deadline
2020 #1

18

Design deadline
2020/7/20

Chip delivery
2020/8/24

2.7 Venture companies related to VDEC
Some professors related to VDEC started venture companies. The following is a list of the venture companies
related to VDEC.
[1] AIL Co.,Ltd. (http://www.ailabo.co.jp/)
Related professor : Professor Kazuo Taki, Kobe Univ. (Representative Director)(2) Engineer dispatching service[2] Synthesis Corporation(Merged with Soliton Systems on July 1st in 2017, http://www.synthesis.co.jp/)
Related professor : Professor Emeritus Isao Shirakawa, Osaka Univ. (Director)
Description of business : (1) System LSI development and design service(2) IP development and sales(3) Development and sales of IPs(4) Development of EDA tools

2-7
Chapter2 Activity Report of VDEC

Description of business : (1) LSI design service[3] ASIP Solutions (http://www.asip-solutions.com/)
Related professor : Professor Masaharu Imai (Representative Director, CTO)
Description of business : (1) R&D, education and consulting of IoT application system(2) Sales of ASIP design tool and consulting of ASIP development[4] Nanodesign Corporation (http://www.nanodesign.co.jp/)
Related professor : Professor Kazuyuki Nakamura, Kyushu Institute of Technology. (Rep-resentative Director)
Description of business : (1) LSI design and development(2) Design consulting, etc.
[5] A-R-Tec Corp. (http://www.a-r-tec.jp/)
Related professor : Professor Emeritus Atsushi Iwata, Hiroshima Univ. (Representative Director)
Description of business : (1) Design and measurement of IC and evaluation board(2) Crosstalk noise analysis(3) Develop human resources for new employees and beginners[6] Ishijima Electronics (http://ishi.main.jp/)
Description of business : (1) Electronic circuit and board development(2) Software development(3) Consulting

19

2.8 “ Nanotechnology Platform”: Ultra Small Lithography and NanometricObservation Site

2-8
Chapter2 Activity Report of VDEC

d.lab/VDEC is operating an open-use nanotech-search reports and machine use. The University of

nology platform “Ultra Small Lithography and Na-

Tokyo site has received 158 research reports from 158

nometric Observation Site” together with the Insti-

research groups. As shown in example of EB writ-tute of Engineering Innovation of Graduate School ofer exposure count per month (that exceeds 210 per

Engineering. The site is supported by Japanese Min-

month) in the Fig. 1, machine usage is monotonous-

istry of Education (MEXT)’s Nanotechnology Plat-

ly increasing. “Open ratio”, which is the number ofform grant. Any researchers in Japanese Universities,

days in which users outside the University of Tokyo

Laboratories, and Companies can take full advantage

came, divided by machine open days, was 99%. Dueof The University of Tokyo’s cutting-edge nanotech-to the strong support of nanotech. Platform, evennology apparatuses and know-hows. The accessible

a novice user can obtain fine lithography result bytechnology includes Lithography and Etching envi-

using the apparatuses with the Platform engineeringronment, Ultra High-Voltage Acceleration (1MV)

staffs of VDEC. Consequently, free machine time istransmission electron microscope (TEM) that is ca-

decreasing so the team is trying to acquire financial

pable of visualizing upto light materials such as Ni-

support to increase the number of machines. Also

trogen. VDEC takes part in the lithography at Take-from FY2019, the French Nanotechnology Network

da Sentanchi Super Cleanroom. Through VDEC’s

project CNRS-RENATECH asked to the UTokyo

key apparatus F5112+VD01 donated from Advant-

VDEC to share the good practice. Also d.lab was

est Corporation as well as F7000S-VD02 purchased

invited by Organisation for Economic Co-operation

by national budget, VDEC is supporting post-VLSI

and Development (OECD)’s international workshop

activities such as MEMS. The machine is capable offor national infrastructure strategy.

rapidly writing patterns on arbitrary-shaped targets
sizing from 1cm-sqare chip to 8-inch round wafers.

URL:http://nanotechnet.t.u-tokyo.ac.jp/

The performance is measured by the number of re-

Figure 1: Monthly Average Exposure Count of EB Machine (s).

20

Chapter3

Activity Report of ADVANTEST D2T Research Division

3.1 Introduction of ADVANTEST D2T Research Division
3.1.1 Aim of establishing
ADVANTEST D2T Division

cial year, i.e., Oct. 2018 – Sep. 2019, of the fourthphase. Systems Design Center, School of Engineering, the University of Tokyo has been established inlished in VDEC in October 2007. As the name sug-

Oct. 2019, and Advantest D2T research department

gests, it is financially supported by ADVANTEST

is within the center. D2T research department pri-Corporation.

marily focuses on D2T research activities and edu-

The aim of establishing ADVANTEST D2T re-cation. The fifth project phase (Oct. 2019 onwards)

search division was to promote the research and ed-of D2T project will be commenced by courtesy ofucation environment with regard to VLSI testing in

ADVANTEST Corporation.

all universities and colleges in Japan. “D2T” signifies

In this financial year, we invited Professor Gil-

that we consider not only design but also testing.

gueng Hwang from CNRS, University of Paris-Sa-

Through our activities, we hope to provide expertiseclay (2019/7 – 9) and Professor Tsung-Hsein Lin

in design and testing for the industry. In addition,(2019/8 – present) from National Taiwan Universi-

we are exchanging researchers with those of otherty for research and educational collaboration with

universities and research institutes both in Japan andd.lab-VDEC.

overseas. Moreover, D2T research division is suitablefor collaborations with the industry because VLSIThe details pertaining to the activities of our groupare presented in the following sections.

testing is one of the most practical research topics
in the industry. On the basis of these activities, our

3.1.2 Members of ADVANTEST D2T Division

final goal is to become a center of excellence of VLSI

Project Professor

testing in Japan.

Project Associate Professor Gilgueng Hwang (2019/7 – 9)Masahiro Fujita

D2T research division has spent a total of 12 years

Project Professor

Tsung-Hsein Lin (2019/8 – present)

to develop the first (Oct. 2007 – Sep. 2010), second

Project Lecturer

Akio Higo(Oct. 2010 – Sep. 2013), third (Oct. 2013 – Sep.

Researcher

Koji Asami (Advantest Laboratories Ltd.)

2016), and fourth (Oct. 2016 – Sep. 2019) phases.

Researcher

Takahiro Yamaguchi

D2T activity report of 2019 presents the last finan-

Assistant Clerk

Makiko Okazaki

3-1
Chapter3 Activity Report of ADVANTEST D2T Research Division

ADVANTEST D2T research division was estab-21

3.2 Report of the 14th D2T Symposium

3-2
Chapter3 Activity Report of ADVANTEST D2T Research Division22

The 14th D2T Symposium was held on September

Paris-Saclay; Prof. Priyank Kalla, The University of

6, 2019, at Takeda Hall. This year, we invited the fol-

Utah; Prof. Kwang-Ting (Tim) Cheng, Hong Kong

lowing overseas lecturers to introduce their research

University of Science and Technology; and Prof. Adit

on biosystems, RF, IoT, and machine learning: Alan

Singh, Auburn University.

Mishchenko, University of California, Berkeley;

We sincerely appreciate each participant for theirProf. Degang Cheng, Iowa State University; Prof.

contributions to the symposium. We look forward to

Tsung-Hsien Lin, National Taiwan University; As-greater participation again at the next symposium.

soc. Prof. Gilgueng Hwang, CNRS, University of14th D2T Symposium program
10:00 Opening Remarks

Masahiro Fujita (Director, VDEC, The University of Tokyo)
Yoshiaki Yoshida (President & CEO, ADVANTEST CORPORATION)
10:15 Session 1 (Chairpersons: Masahiro Fujita, Zule Xu, Nguyen Ngoc MAI-KHANH

VDEC The University of Tokyo)
Circuit-Based Intrinsic Methods to Detect Overfitting
Alan Mishchenko, Full researcher (University of California, Berkeley)
Effective and practical AMS DfT techniques for achieving robust performance and life-time reliability
Degang Chen, Professor (Iowa State University)
Sensor Readout Circuits for IoT/Bio-Medical Applications
Tsung-Hsien Lin, Professor (National Taiwan University)

14:00 Session 2 (Chairperson: Yoshio Mita, VDEC, The University of Tokyo)

Design, Fabrication and Characterizations of On-chip Micro/nanorobotic Swimmers Toward Biological Applications
Gilgueng Hwang, Associate professor (CNRS, University of Paris-Saclay)
Design Automation for Silicon Nanophotonic Integration
Priyank Kalla (The University of Utah)

15:30 Break
16:00 Session 3 (Chairperson: Virendra Singh, Dept. of EE, Indian Institite of Technology Bombay)

Electronic-Photonic Design Automation
K.-T. Tim Cheng, Professor (Hong Kong University of Science and Technology)
The Next Major Test Challenge: Low Power Designs
Adit Singh, Professor (Auburn University)
Session 4
Recent D2T research division progress
Akio Higo, Lecturer (VDEC, The University of Tokyo)

17:55 Closing
18:00 Reception

Chapter3 Activity Report of ADVANTEST D2T Research Division

12:30 Lunch

3-2

23

3.3 Research Activity Reports of the ADVANTEST D2T Research Division
High-Resolution

Analog-to-Digital

Converter

Based on Stochastic Comparators

Using the Wideband Spread Spectrum and Its Ap-

Takahiro J. Yamaguchi, Akio Higo, Tetsuya Iizuka
This

3-3

project

aimed

to

exploreHigh-Performance Analog-to-Digital Conversion

stochastic

plications
Koji Asami, Byambadorj Zolboo, Akio Higo,

Chapter3 Activity Report of ADVANTEST D2T Research Divisionanalog-to-digital converter (ADC) architectures.

Tetsuya Iizuka, Masahiro Fujita

Process variations, along with many factors such

To measure low-cost RF devices for IoT andas voltage or temperature variations, lead to mis-other applications, low-cost and high-efficiency

matched design parameters that in turn result inanalog-to-digital conversion techniques are required.

input-referred offsets. Thereby, non-linearity andTo acquire narrow-band modulation signals scatteredmissing output codes occur in an ADC. Instead ofover a wide frequency range, a compression samplingattempting to suppress such process variations as inmethod was investigated herein.

conventional ADCs, the stochastic ADC approach

In this financial year, we constructed a theoreti-

exploits the stochastic properties of several com-

cal formula for the Noise Figure and confirmed its

parators, such as the random variation of input-re-validity using actual experimental equipment. Thisferred offset and Gaussianity of the internal noise, toresult was submitted to the IEEE TCAS-I. Moreover,enhance the quantization accuracy. To validate thevia analysis of the performance degradation factors

theory for detecting the level-crossing time using a

involved in the implementation, we devised a cali-

stochastic median, both numerical experiments andbration method and confirmed its use by means ofexperiments using the CMOS comparator array were

simulation.

performed. These experiments use N comparatorsand detect the level-crossing times of a ramp input
under the condition of external noise = zero, andHigh-Throughput

andHigh-Accuracy

Elec-non-zero internal noise with various process varia-

tron-Beam Direct Writing (EBDW) Strategy fortions. The theory has been verified experimentally

Wide Range of EBDW Applications

using a prototype CMOS comparator array, which

Akio Higo, Yoshio Mita, Masahiro Fujita

consists of 256 differential comparators. The experi-

Maskless lithography via electron-beam direct

ments were performed under the conditions of exter-

writing (EBDW) is expected to be a low-cost lithog-

nal signal in the form of a step input, zero externalraphy technology with a short turn-around timenoise, and non-zero internal noise with process var-

(TAT). However, it presents some drawbacks suchiations. The theory was also validated in the volt-

as low process throughput and low accuracy against

age domain via application of the step input to thethe intended layout shapes. We are pursuing a high-comparator array. This allowed for the prevention of

speed and high-accuracy EBDW strategy utilizing

complicated and time-consuming measurement pro-the character projection (CP) method to overcome

cesses in the time domain.

these concerns and boost EBDW use in fields suchas MEMS and photonics.
We investigated the fabrication process for thehigh-resolution observation of lithographic results
using our high-throughput and high-accuracy EB
exposure strategy, which combines the CP and variable-shaped beam (VSB) methods. We fabricated aluminum thin film periodic CP/VSB nanostructures
on a quartz plate via CP and VSB on a glass substrate
and measured the optical characteristics.

24

3.4 Publications
International Journals[1]

A kio Higo, Tomoki Sawamura, Makoto

Fujiwara, Eric Lebrasseur, Ayako Mizushima,
Etsuko Ota, Yoshio Mita, “Experimental
Comparison
Electron

of

Beam

Rapid

Large-area

Exposure

Methods

Directwith

Vol.31, No.8, pp.2511-2525, 2019 (2019.05)
doi: 10.18494/SAM.2019.2443

3-4
Chapter3 Activity Report of ADVANTEST D2T Research Division

Plasmonic Devices,” Sensors and Materials,

25

Chapter4

Research in VDEC

Kuroda Laboratory(http://www.kuroda.t.u-tokyo.ac.jp/index.html）

TCI:ThruChip Interface

4-1

cryptography, according to the standard change. In
this study, we have explored design spaces with parameters such as cryptographic curves, structure ofChapter4 Research in VDEC

T. Kuroda, M. Hamada, T. Shidei, M. Okada,arithmetic units, and the number of parallel oper-

Wai-Yeung Yip

ations, and obtained optimal design parameters in

TCI is a 3D integration technology that employs

terms of throughput and latency. We establishedinductive coupling between coils created with on-

HDL generation for the obtained optimal designs.

chip metal line patterns for data communication

On the other hand, it is also important to build

across stacked chips. It realizes the same or better

Trusted Execution Environment (TEE) for systems

performance as TSV (Through Silicon Via) but at ausing cryptographic engines. we participated in thelower cost. Last year, we presented the HDSV (High-task group to extend the specifications for TEE ofly Doped Silicon Via) technology which enables

the RISC-V architecture and proposed specifications

power delivery without using TSV for TCI stacked

suitable for IoT systems. We also evaluated the area

chips, and the TCI 2.5-D integration technology.

overhead of hardware for TEE and examined its applicability to small-scale processors for IoT.

TLC:Transmission Line Coupler
T. Kuroda, M. Hamada, T. Shidei, M. Okada,

Functional Encryption Engine Design

Wai-Yeung Yip

M. Ikeda, C.Cai, S. Sugiyama, and R. Nakayama

TLC is a data communication technique between

High-functional

cryptography

exemplifiedbycircuit boards by utilizing electromagnetic couplingsearchable encryption and ID and attribute-based

between transmission lines on them. It solves theencryption is the basis of privacy guard, that is theissues in conventional connectors such as wearing,biggest concern in cloud services. Functional cryp-

reliability against vibration, and impedance mis-

tography has a disadvantage that the cryptograph-

match, realizing wireless connectors. Last year, we

ic algorithms used for its implementation has highsuccessfully realized a demonstration of wireless con-computational cost. In this study, we implemented

nectors for USB3.0 signals.

and optimized two main algorithms, optimal Atepairing on elliptic curve and fully homomorphic en-

Ikeda Laboratory(http://www.mos.t.u-tokyo.ac.jp)
Current Research Projects

cryption (FHE). In both cases, we employed operations on quotient ring as the unit of arithmetic, andconstructed pipeline by unrolling loop that is small
but repeated many times in the algorithms. By op-

Design Optimization of High-Performance Cryp-

timizing data flow of the pipeline, we have realized

tographic Engine

8.2 us per pairing. For the case of FHE, we achieved

M. Ikeda, K. Ikeda, F. Arakawa

19.2 times better throughput (synthesize result)

We have explored the optimal design of data-path

compared to GPU.

for high-performance encryption engine for such

26

application spanning from cloud to sensor-node.

A study on hardware implementation of reservoir

One of the issues for such high-performance cryp-

computing system

tographic design in ASIC is the manufacturing cost,

M. Ikeda, C.Cai and B. Amartuvshin

and there exists difficulty of re-implementation of

The hardware realization of artificial neural net-mathematical formulas and parameters used forworks (ANNs) is a challenging task due to large re-source requirements of the involved operations. Res-

light to pulse frequency modulation pixel for both

ervoir computing (RC), based on a random recurrent

background suppression and digital signal selection

neural network (RNN), is a simple yet powerfulcapabilities.

model that is well suited for time-series data processing. It consists of a reservoir for mapping inputs into

Design and Measurement of Weak-Signal-Readouta high-dimensional space and a readout for pattern

Integrated Circuit for Terahertz-Video-Imaging
M. Ikeda, and T. Kikkawa

ervoir. The reservoir is fixed and only the readout is

We designed a readout integrated circuit (ROIC)

trained with a simple method such as linear regres-for Terahertz-Video-Imaging which converts a weaksion and classification. Thus, the major advantage

signal detected by InAs MOS-HEMT to digital sig-of reservoir computing compared to other recurrent

nal. The ROICs are integrated as 8x7 array on 180nm

neural networks is fast learning, resulting in low

CMOS and utilized with the detectors stacked on

training cost. We are trying to propose digital hard-them. Each ROIC contains transimpedance am-ware implementations of echo state network (ESN)

plifier, lock-in amplifier and ΔΣ analog-to-digital

designed for brain-computer interface based on EEG

converter as well as digital-to-analog converter totime-series data with online learning capability.

calibrate the detectors. In our work, several control
parameters and digitized signals are serially commu-

Self-Synchronous Circuits Design

nicated by serial peripheral interface (SPI). The fab-

M. Ikeda, and D. Cuiricated chip is stacked with array of antennas andWe have been working on the research of highInAs MOS-HEMT detectors integrated on a glass

throughput gate-level pipeline self-synchronous

substrate by stud bumps. By measurement with acircuits free from timing errors. The dual-pipeline

THz signal generator, we realized synchronous-de-

self-synchronous logic gate duplicates the DCVSL

tection of the signal under a noise equivalent power

circuit into two identical pipelines and uses the same(NEP) of 0.215pW/√Hz.

4-1
Chapter4 Research in VDEC

analysis from the high-dimensional states in the res-completion detection signal to control both pipelines. When one pipeline is in the evaluation phase,the other pipeline must be in the pre-charge phase,results in concealing of pre-charge time and control.

Fujita Laboratory(http://www.cad.t.u-tokyo.ac.jp/）

Gate-level pipeline enables throughput enhance-

Synthesis and Generalization of Parallel Algorithm

ment. Besides the high-throughput operation, wefor Matrix-vector Multiplication

are trying to design the self-synchronous arithmetic

Masahiro FUJITA, Akihiro GODA, Ashish MITTAL,

units which can also allow for latency reduction andYukio MIYASAKA

area utilization improvement.

Recently, there have been more chances to calculate
matrix-vector multiplication due to the growing use

Advanced 3-D Measurement System by Smart Im-of the neural network. We have proposed the meth-age Sensors and Secure Sensing

od to automatically synthesize the optimum parallel

M. Ikeda, N. Takeda, Y. Liu,

algorithm for the given environment and synthesized

D. Jiang, and N. Watanabe

an algorithm for matrix-vector multiplication of a

We have been working toward the advanced 3-D

specific size matrix with 4 nodes connected in a one-measurement system with secure sensing scheme

way ring. This work proposes a method to general-

by integrating smart signal processing functionali-

ize the synthesized algorithm to deal with any sizety onto the smart image sensors. We have studied

matrix. We generalized the synthesized algorithm for

ToF image sensor with current mode backgroundthe 32 × 32 matrix to calculate N × N matrix-vector

suppression capability for modulated light projec-

multiplication.

tion. We have also studied ToF image sensor with

27

4-1

Synthesis and Generalization of Parallel Algo-

Approximate Arithmetic Circuit Design Using arithms Considering Communication Constraints

Fast and Scalable Method

Chapter4 Research in VDEC

Masahiro FUJITA, Yukio MIYASAKA,

Masahiro FUJITA, Amir Masoud GHAREHBAGHI,

Amir Masoud GHAREHBAGHI, Akihiro GODA

Qi LU

Recently, the opportunities of parallel comput-

Approximate computing can be applied to error

ing are expanding rapidly in various applications

tolerant applications, by trading off accuracy forincluding neural networks and machine learning. It

lower power consumption, shorter delay and small-is, however, not at all straightforward to develop aner area. In this work, we focus on the approximate

efficient algorithm for each parallel computing en-arithmetic circuit design especially targeting combi-

vironment since communications always introduce

national multipliers and adders, which are essential

overhead in computation. In this work, we propose

computing components in machine learning such asa design method of optimum parallel computing un-

neural network computation. We propose a novel

der user-specified communication constraints. The

approach to generate approximate circuits from thebasic strategy is to automatically generate optimum

given correct circuits. The basic idea is to study thescheduling from small instances of the target prob-

circuit’s characteristics from the small instances oflem and then they are semi-automatically generalized

the circuits and then establish a common algorithm

to much larger problems. Several experiments target-

for larger circuits with the same architectures. We

ing matrix vector multiplication and convolutional

propose two different methods and apply them toneural networks have been conducted. Their results

adders and multipliers with different architectures.

show the correctness and usefulness of the proposed

The experimental results demonstrate that our meth-method as well as its scalability.

od outperforms the state-of-art methods in terms of
the quality of the circuits with orders of magnitude

Signal Selection Methods for Debugging Gate-Lev-

shorter processing time.

el Sequential Circuits
Masahiro FUJITA,An Automatic Test Pattern Generation Method forAmir Masoud GHAREHBAGHI, Yusuke KIMURA

Multiple Stuck-at Faults by Incrementally Extend-

This work introduces methods to modify a bug-ing the Test Patterns

gy sequential gate-level circuit to conform to theMasahiro FUJITA, Amir Masoud GHAREHBAGHI,

specification. In order to preserve the optimization

Peikun WANG

efforts, the modifications should be as small as pos-As the number of transistors in the fabricated cir-sible. Assuming that the locations to be modified are

cuits becomes extremely larger, not only single stuck-

given, our proposed method finds an appropriate

at faults, but also multiple stuck-at faults are likely

set of fan-in signals for the patch function of thoseto happen in the circuits, especially for the large-

locations by iteratively calculating the state corre-scale circuit. Multiple faults are difficult to be fully

spondence between the specification and the buggy

covered due to the exponentially enormous number

circuit and applying a method for debugging combi-of all possible faults. Although there are methods

national circuits. The experiments are conducted on

proposed to deal with the multiple faults, they fail

ITC99 benchmark circuits, and it is shown that ourto generate compact test patterns to detect all faults

proposed method can work when there are at most

within an acceptable running time. In order to solve

30,000 corresponding reachable state pairs between

these problems, this work proposes an incremental

two circuits. Moreover, a heuristic method using theAutomatic Test Pattern Generation method to deal

information of data-path FFs is proposed, which canwith multiple stuck-at faults. Instead of traversing

find a correct set of fan-ins for all the benchmark

the entire n multiple fault list, the proposed meth-circuits within practical time.

od only selects the faults undetected by the existing
test patterns for n-1faults, and then generates addi-

28

tional test patterns. Staring from a complete test set

Modeling and Design of Nonvolatile SRAM andfor single faults, the proposed ATPG method can be

FeFET Using Ferroelectric HfO2.

incrementally applied to handle all multiple faults.

Kiyoshi Takeuchi,

Moreover, since the number of undetected faults that

Masaharu Kobayashi and Toshiro Hiramoto

are selected is extremely smaller comparing to the

Ferroelectric memory device using ferroelec-

total number of the entire fault list, the proposed

tric-HfO 2 is expected to be CMOS-compatible, low-method can generate compact test patterns to cover

cost and low-power memory. Although the research-

all faults within an acceptable running time.

es on a single memory device have been extensively
done, only a few studies have been done addressing(http://nano-lsi.iis.u-tokyo.ac.jp/）

Device Physics on Negative Capacitance Transistor

cell array. In this work, we built models taking into
account the variability in ferroelectric HfO 2 memory
devices. We revealed the scalability and an optimum

Masaharu Kobayashi and Toshiro Hiramoto

design of nonvolatile SRAM for normally-off com-

Negative capacitance transistor (NCFET) using

puting in IoT applications. We also proposed opti-

ferroelectric-HfO 2 gate insulator is a promising tran-

mum FeFET cell designs considering read and write

sistor technology that can realize sub-60 subthresh-

disturb in a cell array configuration.

old slope (SS) for low voltage operation. However,the physical mechanism of sub-60 SS and unique
phenomenon in NCFET remains to be understood.
In this work, by using the transient negative capac-

4-1
Chapter4 Research in VDEC

Kobayashi Laboratory

technical challenges in memory device scaling and

Iizuka Laboratory(http://www.mos.t.u-tokyo.ac.jp)

itance theory based on the dynamics of ferroelectric

Waveform Reconstruction Technique for Wide-material, we successfully built the model of negative

band Signal

differential conductance and reverse DIBL uniquely

Tetsuya Iizuka, Byambadorj Zolboo

seen in NCFET.

The Modulated Wideband Converter (MWC) is
one of the promising Sub-Nyquist sampling archi-

Demonstration of an IGZO Channel FeFET for

tectures for sparse wideband signal sensing, cogni-

3D-Stacked High-Density Memory Application

tive radio applications and so on. Since resources

Masaharu Kobayashi and Toshiro Hiramoto

within Automatic Test Equipment (ATE) are limited

Ferroelectric transistor (FeFET) memory is a prom-on sampling rate, the MWC can be useful for testing

ising low-power and high-density memory by using

devices with various frequency band.

CMOS-compatible HfO 2 material. To compete withIn this research, we are investigating a feasibility of

flash memory for storage application, it is impor-

MWC to reconstruct a waveform of sparse wideband

tant to solve reliability issues and realize 3D-stacked

signals for measurement equipment. We created a

low-cost and high-density memory. In this work, forsimulation platform system of MWC in MATLAB

3D-stacked FeFET, we proposed FeFET by using

environment and the MWC system perfectly recon-

IGZO channel instead of poly-Si channel. We werestructs the waveform of original wideband signal un-able to fabricate FeFET device by low temperature

der several ideal assumptions. But in practical imple-

process below 400oC without forming an interfacial

mentation, it could suffer in some drawbacks due tolayer which can be the cause of reliability issues. We

non-ideal components and noisy situation.

demonstrated low voltage switching at less than 3V
with nearly ideal subthreshold slope.

Therefore, we implemented a single-channel
MWC using off-the-shelf analog components. The
reconstruction performance based on the ideal sensing matrix was not acceptable due to the non-ideal
hardware components. The conventional way of the

29

4-1
Chapter4 Research in VDEC

calibration is to stimulate the MWC with sequential

In another research topic, we proposed a new loop

single-tone signals then estimates the actual sensing

architecture for a fractional-N PLL that achieves low

matric components. This method is quiet time-con-phase noise and spurs in a more compact mannersuming and inaccurate. Thus, we proposed novel

when compared to prior arts. By employing a dualcalibration method for the MWC using multi-tone

feedback architecture based on a Harmonic Mixer

signal to estimate the actual sensing matrix from a(HM), the proposed PLL prevents amplification of

single-measurement to reduce the calibration time

the quantization noise generated by the fractional

and the timing noise. In terms of NMSE perfor-

frequency divider (MMD; Multi-Modulus Divider),mance, the proposed calibration method has reason-and spurs caused by the PFD/CP nonlinearity. The

ably good performance compared to the convention-effects of the technique were demonstrated throughal one.

measurements and simulations. Furthermore, theIn terms of noise performance, we proposed an

PLL was designed to optimize the trade-off between

average noise figure (ANF) theoretical notation tophase noise and power consumption.

expect the noise figure of MWC. The accuracy of theWe have also tried to optimize the

ADC perfor-

analytical formula is ensured with MATLAB simula-mance. We focused on Cyclic Assisted MASH (Mul-tion results. We have also verified the feasibility of

ti-stAge noise SHaping) ADC for applications suchthe analysis with the measurement in the practicalas sensor interface, which has advantages in small

implementations.

area and high SNR. In this research, we analyzed theperformance deterioration caused by the nonideali-

Design Automation and Optimization Techniquesties such as capacitance mismatch and the finite DC

for Analog Integrated Circuits

gain of the amplifiers so that we could find the most

Tetsuya Iizuka, Zule Xu, Naoki Ojima, Masaru Osada,significant parameter of this circuit. The first stage

Akira Matsuokaof this circuit is 1st order delta sigma ADC, and the

Designing analog integrated circuits often requires

second stage is cyclic ADC. The results of Simulink

time and effort, due to manual layout and parameter

simulation showed that the effect of cyclic ADC’s

search. In order to reduce the burden and improve

finite DC gain of the amplifier was smaller than thatthe performance, we conducted researches on theof other parameters, and other parameters contrib-

techniques for analog integrated circuits, such as de-uted to the degradation of SNDR by 10dB from thesign automation and circuit optimization.

ideal value in the worst case. In addition, we showed

We researched an automated design flow of suc-that the linearity requirement of the cyclic ADC wascessive approximation register (SAR) type ADC andrelaxed because the cyclic ADC input is only theits suitable architecture. By automating the design ofquantization noise from the first stage.

ADCs, which are indispensable for signal processing

30

systems, it is possible to quickly implement a whole

mm-Wave Circuit Design for Communication

system and greatly contribute to reducing costs. This

through Dielectric Waveguide

year, we devised some methods for improving the

Tetsuya Iizuka, Nguyen Ngoc Mai-Khanh,performance of each circuit building block, which

Yoshitaka Otsuki, Daisuke Yamazaki,

is fully composed of standard cells. In particular, aTakafumi Hara, Takamichi Horikawa

pre-distortion method for inverter-based resistive

High-speed communication with the millime-

DACs made it possible to greatly improve the con-ter-wave band has been actively researched. Wireline

version linearity. We designed a 10-bit resolution

communication with a dielectric waveguide such

SAR ADC using the proposed automated design flow

as polymer has been proposed and many researches

and confirmed its operation by simulation. Accord-have been conducted recently. It enables to increase

ing to the simulation results, the power consumption

the communication distance at low cost while main-

per conversion step was estimated to be about 2.3 pJ.

taining the communication speed.

A power amplifier circuit is one of the most important circuit building blocks in a transmitter, and as its

demonstrated through the detailed simulation withmeasured characteristics of the actual flat cables.

output power increases, the communication distanceand the BER improve. In this research, we designed
a power amplifier circuit with high output powerusing a passive power combiner, and optimized the

Takagi-Takenaka Laboratory(http://www.mosfet.k.u-tokyo.ac.jp/)

limit of the output power. We fabricated and meas-

III-V/Ge Metal-Oxide-Semiconductor (MOS) FETs

ured the prototype chip using CMOS 65nm process

and the 3 dimensional integrationand presented the issues in parallelization.

S. Takagi, M. Takenaka, Kasidit Toprasertpong,
Kwangwon Jo, Cheol-Min Lim, Tsung-En Lee,sign, and the amplifier at the most antenna side isSanghee Yoon, Chia Tsong Chen, Zilong Wang,

by far the most important. Analyzing the transis-

Kei Sumita, Jun Takeyasu, Xueyang Han

tor as linear network, its size was optimized by theWe have conducted the research on high-perfor-

available minimum noise factor, and was matchedmance III-V/Ge MOSFETs and the 3 dimensionalby transmission line network. However during thisstacked CMOS structures by using these high mobil-

process it became apparent that at this frequency

ity MOSFETs. We have proposed the accurate eval-the insertion loss of the matching network itself is auation method of a metal S/D formed on high-elec-

big factor in amplifier design. In addition, multiple

tron mobility InAs membrane channel formed bymodulation schemes were compared by simulating

Smart-cut technology. We have also found that 0.5%

with the measured frequency response of dielectric

tensile strain was introduced into the condensed Ge

waveguide.

layer during additional oxidation after the initial

4-1
Chapter4 Research in VDEC

Noise figure is an important factor in receiver de-compressive strain in condensed SiGe layer relaxed.
Signal Crosstalk Cancellation Technique for High-We have also found the electron effective mobility

Speed Wireline Communications

increased when the Ge thickness was thinned down

Tetsuya Iizuka, Daigo Takahashi

to 2.5 nm. In conjunction with the tensile strain

With the improvement of the circuit performanceand the thinning effect, the large electron mobility

due to the miniaturization of the semiconductor pro-of 777 cm2/Vs in GeOI nFET was successfully ob-

cess, the speed of transmission has been improving.

tained.

The data rate necessary for applications also has been
improving because UHD TVs and automobiles witha lot of electrical equipment have been developed.
It is necessary to speed up transmission from both

Ferroelectric gate insulator MOSFETs
S. Takagi, M. Takenaka, Kasidit Toprasertpong,
Xuan Luo, Zaoyang Lin, Kento Tahara,

aspects of technology and demand, crosstalk is one

Zeyu Wang, Eishin Nakoof the factors hindering this. As measures for cross-

We have conducted the research for MOSFETs us-

talk, a method for reducing crosstalk at the receivering ferroelectric gate insulators. We have confirmed

was proposed in the previous research. In this re-

ferroelectricity of ALD Hf1-xZrxO2 films on Si

search, we proposed a method for reducing crosstalkand the operation of MOSFETs with ferroelectricat the transmitter with a delay adjustment circuit

hysteresis characteristics. We have found that theand a high-pass filter. Using simulation, we showed

Si interface with low interface trap density can bethat the proposed method can reduce crosstalk moreachieved by decreasing the crystallization tempera-

effectively with minimal additional circuits. The

ture of Hf1-xZrxO2 and proposed the process de-proposed crosstalk cancellation circuits have beensign of ferroelectric-gate MOSFETs for improving

implemented with 40nm CMOS technology. The ef-

memory characteristics. We have proposed a meas-

fectiveness of the proposed crosstalk cancellation cir-urement technique to evaluate the charge density

cuit even with the performance variations has been

under the MOSFET ferroelectric gate and found the31strong coupling between the ferroelectric polariza-

bonding. By using SOG doping to form a lateraltion and the interface charge traps. For the edge AI

PIN junction, we have improved the modulation ef-

application, by utilizing the memory effect and non-ficiency of a carrier-injection Ge optical modulator.

linear properties of ferroelectric insulators, we have

We have also found that a reverse-biased Ge PIN

proposed a low-training-cost reservoir computing

junction enabled the detection of 2 m-wavelength

using ferroelectric-gate MOSFETs, and successfully

optical signal through the defect-mediated opticaldemonstrated the reservoir computing operation inabsorption.

our fabricated ferroelectric-gate MOSFETs.
4-1

2D material devices

Chapter4 Research in VDEC

On-chip/Off-chip optical interconnec

M. Takenaka, S. Takagi, Kasidit Toprasertpong,

M. Takenaka, S. Takagi, Kasidit Toprasertpong,Roda Nur, Hanzhi Tang, Xiaoxuan Zhang,

Qiang Li, Naoki Sekine, Hanzhi Tang,

Tipat Piyapatarakul

Dongheng Lyu, Qianfeng Chen, Dongrui Wu,

We have investigated 2D materials such as

Yuto Miyataket

graphene and MoS2 for semiconductor devices. We

We have investigated Si photonics for on-chip andhave revealed that the high photo responsivity can

off-chip optical interconnection for CMOS LSI. We

been obtained in the MoS2 phototransistor withhave demonstrated a racetrack optical modulator

HfO 2 gate dielectric due to the photo-gating effect.

with a III-V/Si hybrid MOS optical phase shifter for

We have also successfully evaluate the impurity con-the first time. The parasitic capacitance was also suc-centration of MoS2 by making a thick-body MoS2

cessfully removed by introducing a SiO2-embedded

Schottky junction by exfoliation.

Si waveguide for a III-V/Si hybrid MOS optical phaseshifter, resulting in 10 Gbps optical modulation. We
have proposed a taper-less hybrid MOS optical phaseshifter using an ultrathin III-V membrane. We havealso numerically analyzed an ultrathin InGaAs mem-

Mita Laboratory(http://www.if.t.u-tokyo.ac.jp)
Current Research Projects

brane photodetector monolithically integrated with

Programmable Matter - Study on LSI-MEMS ener-a slot waveguide.

gy-autonomous distributed microsystems for realization of deformable matter

Si photonic integrated circuit for AI

Y. Mita, K.Misumi, N.Usami,

M. Takenaka, S. Takagi, Kasidit Toprasertpong,

E. Lebrasseur G. Ulliac, (LIMMS, CNRS-UTokyo IIS),

Qiang Li, Hanzhi Tang, Shuhei Ohno,

J.Bourgeois, B.Piranda (FEMTO-ST, France),

Yuto Miyatake, Kohei Watanabe

S. Delalande (PSA-Peugeot)

We have investigated programmable photonic in-

As one example of future integrated MEMS that is

tegrated circuits (PICs) including a universal PIC for

expected to open new research and industrial applica-

deep learning. We have fabricated a programmabletion fields, the authors are trying to show a topdown

Si PICs based on micro ring crossbar array and con-application of energy-autonomous dis-tributed mi-firmed the fundamental operation of the deep learn-crorobots. A number of identical tiny robots, sizeding.

below 1cm, will be released in an en-vironment. Individual robot can communicate with their neigh-32

Ge mid-infrared photonic integrated circuit

bor, stick each other, and share ener-gy, to realize

M. Takenaka, S. Takagi, Kasidit Toprasertpong,cooperative function. The PI is receiving a French

Chong Pei Ho, Ziqiang Zhao, Yuto Miyatake

National Research Center (ANR) grant on behalf ofWe have also conducted the research of thehost professor of CNRS laboratory in the Institute of

mid-infrared photonic integrated circuits based on

Industrial Science (LIMMS, CNRS-IIS, UMI 2820),

Ge-on-Insulator (GeOI) wafer fabricated by wafer

together with FEMTO-ST Laboratory and PSA-Peu-

by post-process at clearnrooms such as VDEC

alize deformable substance by cooperative action,

Takeda Supercleanroom and others, of VLSI wafer

named Programmable Matter”. In year 2019, an

made through VDEC. The important finding has

electrostatic chucking actuator system that attaches

been that VLSI wafer acquired just after transistor

and detaches the external skeleton of the Matter has

fabrication could sustain processes even with heat

been developed, by on tiny (1mm to 10mm) objects

treatment, such as deposition, ion implantation,is performed and analyses were conducted. The ac-and drive-in. In 2016, a VLSI de-vice made on Sili-

tuation force has been electromagnetically analyzed.

con-on-Insulator (SOI) wafer was successfully Deep-

Fabrication technology of flexible electrode has been

RIE processed. The in-dustrial interest is its versa-

investigated in order to realize electrodes in arbitraltility – many different types of application devices,

facets of the Matter by rolling technology.

which differ one from another according to requestof market, can be fabricated by using the same tech-Integration of electrode devices on MEMS fluidic

nology. More and more companies are interested indevicesthe scheme and are working on the technology on

Y. Mita,A. Higo, T.Ezawa, E.Ota, Y.Okamoto,the col-laborative research projects. One of the re-N.Washizu (Advantest), T.Takada (Advantest),

search works have been awarded this year.

M. Fujiwara, T.Sawamura
Towards the goal of production of brand-new sensor devices with higher sensitivity and func-tionality,

High-sensitive ultrasonic probe by integrated

4-1
Chapter4 Research in VDEC

geot Laboratory for such “micro robots that can re-

MEMS technology

the team is working on small-gap electrode fabrica-

Y. Mita, R.Yamaguchi, N.Usami, A.Higo,tion process. The target of the second year was relia-

T.Yoshimura (Osaka Prefectural University),

ble water penetration in the nanopores.

T.Mizuno (Konika Minolta),
K.Suzuki (Konika Minolta),

Fine Large-Area Electron Beam Lithography Expo-

Y.Nakayama (Konika Minolta),

sure Methods

T.Endo (Nagoya Medical Center)

Y. Mita,A. Higo, M. Fujiwara, T.Sawamura,

Using the same scheme as above mentioned

M.Takizawa (Advantest), Y.Kudo (Advantest)

CMOS-MEMS post process R&D scheme, thisThe team explores newly-acquired (in 2013) rap-

pro-ject aims at integrating piezoelectric material

id electron beam writer F7000S-VD02. The ca-pa-

and MEMS post-processing to obtain a brand-new

bility of high electron dose and sharp edge due toultrasonic inspection probe, whose sensitivity is ascell (character) projection machine configura-tion

100 times as cutting-edge technology. In year 2019,is being examined. The breakthrough in question is

the team was highly ranked in the evaluation fromto extend the large-area EB lithography, whose pat-a public funding from Japan Agency of MEdical

tern approximation have been limited to rectangular

Research and Development (AMED), followed byshapes, into expressing free-form smooth shapes andsupplemental budget that was used for design anda number of periodical small patterns. This year’s

fabrication of high-voltage electronic circuit for in-outcome include a reliable investigation method

tegration. The work has been awarded in the IEEJ

of repetitive pattern size, pitch, and distribution

36th Sensor symposium.

through a simple optical spec-tral measurement.
LSI hot-spots active cooling system
University-Industry collaborative research on

Y. Mita, Y. Okamoto, K. Fujimoto (Titech),highly-functional system by MEMS post-process

H.Ryoson (Titech), and T. Oba (Titech)of CMOS-VLSI

A hotspot, which is referred to a high-temperature

Y. Mita, S. Inagaki, T. Kuriyama, Y.Sato (Nanox Japan)

area due to the overheating of a circuit block that

The research targets are new sensor devices, madeexcess passive cooling capability, is becoming a key

33

4-1
Chapter4 Research in VDEC

limiting factor of LSI performance. An ac-tive cool-very few research activities have been done in sensors

ing system that tries to actively remove such local

applications; if we can realize integrated photodiodes

heating by circulating liquid coolant is our researchthat have extended sensitive wavelength as long astarget. To conclude the five-year research, electroos-

1.35µm-1.4µm wavelength, such devices can be usedmotic MEMS device fully inte-grated with function-by many new appli-cations such as security cameras

alized LSI high voltage circuity has been demonstrat-

and / or Laser Radar (Lidar) under sunlight. The

ed. To our knowledge, the highest pumping volume

aim of this research is to find an integration method

per driving voltage, as well as flow speed has been

for beyond Si-LSI device. We try to integrate colloi-

achieved. Using elec-troosmotic flow, an LSI com-

dal quantum dots of which absorption spectra canponent cooling (heater and sensor) has been demon-

be designed through molecular design. By inte-gra-strated. An inter-esting cooling phenomenon hastion, Silicon device will be able not only to capture

been found and has been analyzed.

infrared wavelength lights, which is impossi-ble byits original characteristics, but also my include in-

Project PARIS: PARallel Integrated microSystemformation reading and computation circuits. For thefor High Frequency Action-Based Non-Invasive

first year’s exploratory study, partly financed by theMulti-Modal Cell Analyses

LIMMS internal project grant, spin coating integra-

Y.Mita, T.Tsuchiya, Y.Okamoto, A.Mizushima,tion method has been investigated. Root cause that

E.Lebrasseur,

prevented Electrical Quantum Efficiency has been

T.Bauvent (ENS Paris-Saclay, exchange student),

identified to an unexpected reverse Schottky junc-

C.Moslonka (ENS Paris-Saclay, VDEC internship stu-tion. Test structure was proposed and proved to bedent), B. le Pioufle C.Moslonka (ENS Paris-Saclay),efficient to quantitatively analyze such unexpected

Tixier Mita Agnès (UTokyo RCAST),

parasitic compo-nent in the device.

Olivier Français (ESI-EE, Univ. Paris Est),
F.Marty (ESIEE, Univ. Paris Est)

Development of zero power multiple-threshold

Having granted again JSPS-CNRS bilateral pro-maximum acceleration sensor for cyber physicalject 2018, the team is developing a large-scale mul-systemti-modal cell analyses system (project name: PAR-

Y. Mita, R Ranga Reddy

IS). The electrorotation method, which is known

VDEC is awarded a Japanese JST – Indian DST

to measure a mechanical rotational response to thejoint grant (SICORP) for cyber physical systems

incident rotational electrical field fre-quency is used.

re-search, in cooperation with IIT Bombay cam-

The method is non-invasive so the evaluated cells

pus. The team is participating the project throughare possible to be used in fur-ther biological experi-a Shock Resonant Spectrum (SRS) sensor, which hasments. In this year fabrication of classical electrodes

been a research theme of 2012-2014. A new Ph.D

was first leaned by VDEC internship student. Then

student from India is assigned and fabrication pro-thicker electrodes were made in collaboration withcess was recovered. This year we have analyzed com-

ESIEE and ex-periments were done at ENS Paris-Sa-

plete system to record 10-levels of maximum acceler-

clay. LSI has been designed in order to integrate withation in MEMS device. Based on the result, we havedriving electrodes..

started collaboration with India. We have hosted aninternship student from IITB for two weeks, two

Colloidal integrated Infrared Detector
A.Higo, N.Miyazawa, N. Usami, Y. Okamoto,
W. Haibin, N. Kubo, K. Segawa, Y. Mita
Electron devices using colloidal quantum dots are
believed to open new application fields such as lightemitting devices and or photovoltaics. Up to date,34

students from IITH for three months and started
device design.

System Design Lab (d.lab),
School of Engineering, The University of Tokyo
Annual ReportAugust, 2020
Published by
System Design Lab (d.lab), School of Engineering, The University of Tokyo
Tadahiro Kuroda
Address: Hongo 7-3-1, Bunkyo-ku, Tokyo, 113-8656, Japan
Printed in
SOHOKKAI co., Ltd. Tokyo Branch
Address: Koutoubashi 4-25-10, Sumida-Ku, Tokyo, 130-0022, Japan
Copyright Ⓒ by System Design Lab (d.lab), School of Engineering, The University of Tokyo