平成30年度
VLSI Design and Education Center The University of Tokyo 2018東京大学
大規模集積システム設計教育研究センター
年報

2018
VLSI Design and Education Center,
The University of Tokyo
Annual Report

VLSI Design and Education Center The University of Tokyo 2018

VDEC年報2018_H1_4E.indd 4-1

2018/09/19 9:26

VLSI Design and Education Center
The University of Tokyo

I was appointed as director of VLSI Design and Education Center (VDEC) on April 1 following the director, Prof.
Asada. VDEC was established in May 1996, and has been operating for 22 years. The first director, Prof. Hoh andthe previous director, Prof. Asada have made VDEC as one of the most important and widely used organizationsin Japanese academia for VLSI chip design and development. Annually around 300 research groups in academia
use the design tools provided through VDEC, and nearly 200 research groups use various facilities including clean
rooms and measurement tools for chip development.

Semiconductor industry has been continuously growing since the last century and is expected to continue togrow with the increasing need from IoT and related technology. It is extremely important to support academia as
it is the basis of semiconductor industry. There are several organizations in the world, specifically in US, Canada,
Europe, South Korea, and Taiwan, and others, whose goals are basically the same as VDEC. There have been
efforts in the collaboration among these organizations. Every year, multiple meetings to discuss collaborative ways
to supply various services for world-wide VLSI chip design and development are set up, and more intensive joint
activities are expected to come.

D2T (Design to Test) which is an industry donated division in VDEC has been working for ten years and hasreceived a number of world top-level visiting professors. D2T has already stimulated educational and research
activities of VLSI testing in broad sense and has generated several results which have actually influenced the VLSI
testing area world-wide. It is expected to continue to generate more influential results in VLSI design and testing.

VDEC is an essential organization for academic VLSI design and development. Now it is planned to expand
to include not only just chip development, but also ICT system developments through tighter collaboration withvarious resources in information technology. With that goal in mind, VDEC continues to work for more efficient
ways of chip and system developments, EDA tools which can be used commercial chips, and integration of VLSI
chip and device developments. VDEC including myself appreciates your continuous support.

VLSI Design and Education Center, University of Tokyo
Director Masahiro Fujita

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2018/09/19 9:26

VLSI Design and Education Center, The University of Tokyo
Annual Report 2018

C O N T E N T Se a e rre t r

Chapter

t

t

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2

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1.1

Introduction of VDEC activities and activity report of FY2017

1.2

VDEC CAD Tools

2

5

1.3

VLSI Chip Fabrication

1.4

Seminar

10
13

7

1.5

Facilities

1.6

Activity plan for 2018

1.7

Venture companies related to VDEC

1.8

“Nanotechnology Platform”

15
16

17

Ultra Small Lithography and NanometricObservation Site

Chapter

Chapter 3

Chapter

t

t

ep rt
e ear h18

2.1

Introduction of “ADVANTEST D2T Research Division”

2.2

Report of “12th D2T Symposium”

2.3

Research Activity Reports of “Advantest D2T Research Division”

2.4

Publications

e ear h

18

19
21

23

C

24

Chapter 1 Activity Report of VDEC
1.1 Introduction of VDEC activities andactivity report of FY2017

Chapter

1-1
2

VLSI Design and Education Center(VDEC), University

year. We hold the seminar in VDEC and provide distanceof Tokyo was established in May 1996. VDEC has beenlearning through video streaming. We expect spread ofoperating for the following 3 major roles: “spreading

the up-to-date LSI design methodology by using CAD

the latest information on VLSI design and education,”tools.

“providing licenses of CAD tools,” and “suppor tingWe assume our LSI design flow seminars as educations

on VLSI chip fabrications for academic use.” Theon basic LSI design concepts and practical experience of

VDEC activity report of FY 2017 is described hereafter

LSI design with CAD tool chain. VDEC holds “LSI design

according to Fig. 1.1.

education seminar”，a.k.a. VDEC Refresh Seminar,

t
t
ep rt

The missions of VDEC are for advancement ofonce a year. This year we hold 3 courses, “Analog design

researches and education on LSI design in public andcourse” and “RF design course”，and initiated “MEMS

private universities and colleges in Japan and send many

design course” in July-September time frame. We invite

distinguished VLSI designers into industry. After 22 years

experienced professors among universities as lecturersof VDEC establishment, educations on CAD software,

for the courses to conduct LSI design education courses

LSI design and design flow in universities have been wellwith practical experience. We also hold “Transistor levelestablished. On the other hand, advancement on nano-design flow in VDEC” and “Digital design flow in VDEC

meter CMOS technologies forces design flow and CAD

EDA environment” for designers in universities. We

software complicated. We have been continuing CAD tool

started to charge these two LSI design education courses,

seminar by the lecturers from EDA vendors for twice aas well as VDEC Refresh Seminars.

C
Fig. 1.1

VDEC activities

In addition to the above seminars, we hold “VDEC

lists to give answers to questions, however, in most cases,

DesignerʼForum” among young professors and students

replies are given by the experienced users of CAD tools

annually. This is a workshop that the par ticipantsand experienced designers within a couple of hours to aexchange their design examples with not only successcouple of days. Moreover, emails are accumulated and arestories but also their failure stories, in addition to invited

open to the VDEC users, as shown in Fig. 1.2, who havetalks. We expect students and professors who will startregistered VDEC accounts, as the important educational

designs to learn kinds of know-hows. We have initiatedassets. We expect all the VDEC users to make the full use“IEEE SSCS Japan Chapter VDEC Design Award” thisof this mechanism to help solve problems.
We continue chip fabrication services on FDSOI CMOS

out during the “VDEC Designerʼ For um”．Mr. H.

28 nm by ST Microelectronics, 0.18 mm CMOS by Rohm

Asano(Kobe Univ.) is awarded as “IEEE SSCS Japanand 0.8μm CMOS by On-semi Sanyo Semiconductor. And

Chapter VDEC Design Award” winner, and Mr. H.

started chip fabrication services on SOTB CMOS 65 nm

Asano(Kobe Univ.), Mr. K. Fujimoto(Nara Institute of

by Renesas Electronics.

Science and Technology), Mr. Y. Matsushita(Keio Univ.))

Our donated division “Design To Test(D2T)”，which

are awarded as “the best VDEC Design Award”，and Mr.

was founded by donation from Advantest in Oct. 2008,

T. Yamaguchi (Nara Institute of Science and Technology),

focuses on enrichment of education on LSI testing andM r. H . H a y a m i ( N a r a I n s t i t u t e o f S c i e n c e a n dbridging between design and testing.
Fig. 1.3 shows trends of number of papers throughthe “VDEC Design Award.” Also Mr. D. Terutsuki(Univ.

VDEC activities. Number of papers is increasing, whichof Tokyo) are awarded as the “VDEC Design Award.”means researches in the field of VLSI design have beenencouraged after VDEC establishment.

educations through various seminars and the forum. One

chip fabrications and VDEC facility usages. CAD tools areof the biggest problems for beginners is the setup of CAD

widely used to write papers. CAD tools are used not only

softwares. Many of them also get confused by “Esotericchip designs themselves but also used for preparation of

messages” come out from CAD softwares, even after they

chip fabrication and they contribute to verify fundamental

successfully setup CAD tools. In such situations, VDEC

ideas of researches. Advanced CMOS processes aremailing-lists make significant contributions. VDEC users

preferred for publications, and not only papers withcan register to VDEC mailing-lists on CAD tools, and65 nm/40 nm CMOS chips, but also with 32 nm CMOS,

process dependent groups through VDEC web pages,

22 nm CMOS and 14 nm CMOS are emerging in theand can ask questions and helps on their facing issues. It

world. We would like to prepare chip fabrication services

is not a responsibility for the registrant of such mailing-

for the advanced CMOS processes. In addition, we would

Fig. 1.2

Archives of emails of VDEC mailing-list.

C

Fig. 1.4 shows number of papers related to CAD usage,

ep rtduring actual LSI design scene, even after the basic

3t

LSI designers come up against various dif ficulties

1-1tTechnology), Mr. H. Sun(Waseda Univ.) are awarded as

Chapteryear, and final examination and awarding have carriedlike to setup chip fabrication services related to CMOS/

facilities such like LSI testers, FIB systems and EB writer

MEMS to fulfill the researches for “More than Moore”．

for the wide spread of research purposes.

We also encourage researchers to fully use of VDEC

Chapter

1-1
4t

Fig. 1.3

Trends of number of papers through VDEC activities.

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Fig. 1.4

Number of papers related to VDEC facilities.

1.2 VDEC CAD Tools
Since 1996, VDEC has provided CAD software licenses

colleges.
When one is going to use VDEC CAD tools and chipin Japan. The CAD tools we provided in 2018 are shown

fabrication service (the details are described in Sectionin Table.1.2.1. The researchers can use those CAD tools

1-3), some faculty member of his/her research group inwhen their local machines, whose IP addresses area university or a collage needs to do user registration.

registered in advance, are authorized by one of VDEC

Fig. re 1.2.2 shows (a) the number of registrants, (b)license server located in the ten VDEC subcenters shown

the number of distinguished universities/colleges of thein Fig. re 1.2.1. For each CAD tool, VDEC provides 10-100

registrants, and (c) the number of registrants who applied

floating licenses. Those CAD tools can be utilized only for

VDEC CAD tools, (d) the number of applied licenses ofresearch and education activities in national universities,

all CAD tools.

other public universities, private universities, andChapterto the registered researchers in universities and colleges

1-2

Table 1.2.1 VDEC CAD tools
Name

VendorCadence Design Systems, Inc.

Cadence tool set

Verilog-HDL/VHDL entry, Simlation, Logic synthesis, Test pattern generation, Cell-based (including macros) place, route,and back-annotation, Interactive schematic and layout editor,
Analog circuit simulation, Logic verification, Circuit extraction
Verilog-HDL/VHDK simulation, Logic synthesis, Test patterngeneration, Cell-based (including macros) place, route, andback-annotation, Circuit simulation, Device simulation

Synopsys, Inc.

Synopsys tool set
Mentor tool set

Layout verification, Design rule check

Mentor Graphics Co. Ltd.

Silvaco tool set

Fast circuit simulation

SilvacoADS/Golden Gate

Design and verification of high-frequency circuits

Keysight Technologies

Bach system

BachC-based design, synthesis, and verification

Sharp

LAVIS

Layout visualization platform

TOOL

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Fig. 1.2.1 VDEC Subcenters5tFunctionChapter(a) The number of registrants(c) The number of research group applied CAD tools

1-2
6

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(b) The number of universities colleges of the registrants(d) The number of applied licenses of all CAD tools

Fig. 1.2.2 The numbers of VDEC CAD Applications

1.3 VLSI Chip Fabrication
1.3.1 Trends of VLSI Chip
Fabrication Services
Fig. 1.3.1 shows a trend of number of designed chips

Fig. 1.3.1(a) shows trends of number of chip designed
for VDEC chip fabrication. For the first 6 years until 2001,
the number of designed chips shows steady increase,which means drastic improve of the ef fectivenessfor VDEC chip fabrication services, including pilot projectprior to VDEC establishment.
VLSI chip fabrication is limited to 0.5 mm CMOS
provided by NTT Electronics during the pilot project

Chapter

in 1994 and 1995. VDEC chip fabrication had started in
1996 with 1.2 mm CMOS provided by Motorola Japan,
which is now On-Semiconductor as well as the 0.5 mm
CMOS. In 1997, VDEC received cooperation from Rohm

1-3and has started 0.6 mm CMOS process. In 1998, VDEC
started chip fabrication ser vices of 0.35 mm CMOS by

7

Hitachi, and in 1999, VDEC started 0.35 mm CMOS by
by STARC through “IP development project” in 2001. We(a) Trend of number of designs fabricated.

ep rtmenu in 2001. From 2002, we started VDEC-MOSIS chipt

added 0.18 mm CMOS by Hitachi into our chip fabricationt

Rohm. We had a test chip fabrication of 0.13 mm CMOS

fabrication program initiated by Prof. Iwata of Hiroshima
University. Under this program, VDEC member canaccess to TSMC and IBM processes with lower price. We
also started Bipolar chip fabrication by NEC CompoundC

Semiconductor Devices. In 2004, we star ted 0.15 mm
SOI-CMOS chip fabrication by Oki Electric as test chip
fabrications. In the same year we started 90 nm CMOS
chip fabrication by ASPLA/STARC. In 2006, we started
0.18 mm CMOS by Rohm and 0.25 mm SiGeBiCMOS
by Hitachi. In 2008, we started 65 nm CMOS process by
eShuttle, after closure of 90 nm CMOS chip fabricationin 2007. In 2010, we star ted 40 nm CMOS process(b) Trend of designed area.

by Renesas Electronics through “Next Generation
Semiconductor Circuits & Architecture” project between
METI and STAR. On the other hand, 1.2 mm CMOS
chip fabrication program came to end by the September
2011. 40 nm CMOS by Renesas Electronics and 65 nm
by eShuttle also come to end by Oct. 2012 and Aug. 2013,
respectively. We started CMOS 0.8μm in Oct. 2012 by
On-semiconductor-Sanyo as a test chip fabrication andopened it as the regular chip fabrication menu in 2012.
We started FD-SOI 28 nm CMOS by ST-Microelectronics
through CMP, France, as the advanced CMOS process
in 2013. We star ted SOTB 65 nm CMOS by Renesas
E lec tr onic s in 2015. We in it iat ed t wo mo r e c hi p(c) Trend of designed area normalized by design rule.

fabrication trials in 2017, on CMOS 0.6 um HV from
Ricoh, and CMOS 40 nm from Mie Fujitsu.

Fig. 1.3.1 Trend of number of designs and designed chip area.

researches and education of LSI design, and we assume
drastic increase of number of students related to LSI chip
design and education. During few years of stable number
around 400 chip designs per year, we can see transitionof designs toward finer process. In 2007, we saw a large
drop, which was caused by sudden process transition
from 0.35 mm CMOS to 0.18 mm CMOS, and in 2008, we
also saw another drop by process transition from 90 nm
CMOS to 65 nm CMOS.
Fig. 1.3.1(b) shows trends of designed chip area, whichshows much clear trends of drop by process migration.

ChapterOn the other hand, Fig. 1.3.1(c) shows trends of designed
chip area normalized by design rule, which assume to bestrong relation with design efforts. Coming from the factthat the normalized chip area is still growing, we assume

1-3
8

the major reason for decrease of number of chips andFig. 1.3.2 Trend of number of processors and universities
fabricated chip.

designed area is increase of design effort per chip andper unit area due to process scaling.

t

Fig. 1.3.2 shows trends number of professors anduniversities fabricated chip. Number of professors who

1.3.2 Overview of chip fabrication in
2017

t
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have contracted NDA for process technologies to access

Table 1.3.1 lists chip fabrication schedule in 2017.

design rules and design libraries are, 83, 283, and 45,

Please refer to list in Chapter 2 for details of designers

respectively, for 65 nm CMOS, 0.18 mm CMOS, andand contents of chip designed.

0.8 um CMOS.
Table 1.3.1 Chip fabrication schedule in 2017C

○ 0.8 mm CMOS (On-Semiconductor - Sanyo)
Chip application deadline

Design deadline

Chip delivery

2017 #1

2017/ 7/10

2017/10/ 2

2018/ 1/ 4

2017 #2

2018/ 1/15

2018/ 3/26

2018/ 6/25

Chip application deadline

Design deadline

Chip delivery

2017 #1

2017/ 5/21

2017/ 6/26

2017/ 9/21

2017 #4

2017/ 9/ 7

2017/ 9/19

2017/12/19

2017 #2

2017/ 8/ 7

2017/10/30

2018/ 1/31

2017 #3

2017/11/27

2018/ 2/19

2018/ 5/28

Chip application deadline

Design deadline

Chip delivery

2017 #1

2017/ 6/19

2017/ 7/18

2017/12/14

2017 #2

2017/12/18

2018/ 2/23

2017/ 8M

○ 0.18 mm CMOS (Rohm)○ SOTB 65 nm CMOS

and design flows for digital design and PDKs for analog

1.3.3 Libraries and design flows

design. Table 1.3.2 lists libraries available now.

VDEC have been working to prepare design libraries
Table 1.3.2 Libraries available for VDEC chip fabrication
Technology

Name

AuthorContents

0.18 mm CMOS
(Rohm)

Rohm library

Rohm Library
Std. Cells, IO cells, RAM(Distributed with CDROM)

Synthesis(Synopsys)
Simulation(VerilogXL)
P&R(LEF/DEF)

Onodera Lab., Kyoto University

Synthesis(Synopsys)
Simulation(VerilogXL)

Chapter

Kyodai Library

P&R(Astro)
Todai Library

VDEC
Design flow based on library prepared by
Onodera Lab., Kyoto University

Synthesis(RTL Compiler)
Simulation(VerilogXL)

1-3
9

P&R(Encounter)
VDEC

PDK(IC6.1)

t

PDK

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1.4 Seminar

Chapter

1-4
10tSeminar is indispensable for the improvement of LSI

VDEC teachers gave lecturers on transistor level circuitdesign technology. Some seminar and forums, such as

design course, and digital circuit design course under thetechnical seminar for CAD use, refreshing seminar for

VDEC EDA environment. Teachers and students up to 40

working people, designerʼs forums for young professors

people attended a lecture in each course, and master theand students were held in 2016.

use of each tool for VLSI design flow that uses the VDEC

【Technological seminar for CAD use】

library. Moreover, another technical seminar for CAD use

In a technological seminar for CAD use, VDEC

Cadence 2 kind and 4 days, Synopsys 2 kinds and 2 days

invites lecturer from each tool vender, such as Cadence,(Table 1.4.1). The demand for these CAD technological

Synopsys and Agilent, to hold the CAD operation course.

seminars is ver y large, and VDEC has maintained theMoreover, the course concerning the design flow inmechanism of a large-scale CAD technological seminar

the VDEC environment was held by the VDEC staff. A

holding cor responding to this situation. So far, thetechnological seminar for CAD use for the beginner wasseminar was held at the University of Tokyo OR other

held in The University of Tokyo VDEC in August and

VDEC branch, however, we star ted to distribute theSeptember at the year 2017. This seminar took 5 days for

lecture using Web streaming, so that students around2 kinds of Cadence tools, 3 days for 2 kinds of Synopsys

VDEC branch can take the seminar at the branch school.

for matured teachers and students was held in March bytools, 1 days for 1 kind of Keysight tool. In addition,

t
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Table 1.4.1 CAD technological seminar in summer of the year 2016C

2017/08/17-18

Synopsys DesignCompiler+PowerCompiler Seminar

Univ. of Tokyo13

2017/08/17-18

Synopsys DesignCompiler+PowerCompiler Seminar

Kyoto Univ.

1

2017/08/17-18

Synopsys DesignCompiler+PowerCompiler Seminar

Osaka Univ.

6

2017/08/17-18

Synopsys DesignCompiler+PowerCompiler Seminar

Hiroshima Univ.

2

2017/08/22-23

Cadence Virtuoso ADE Seminar

Univ. of Tokyo11

2017/08/22-23

Cadence Virtuoso ADE Seminar

Tohoku Univ.

3

2017/08/22-23

Cadence Virtuoso ADE Seminar

Kyoto Univ.

1

2017/08/22-23

Cadence Virtuoso ADE Seminar

Hiroshima Univ.

1

2017/08/22-23

Cadence Virtuoso ADE Seminar

Akita Pref. Univ.

2

2017/09/6-8

Cadencee Virtuoso Layout Seminar

Univ. of Tokyo15

2017/09/6-8

Cadencee Virtuoso Layout Seminar

Kyoto Univ.

2

2017/09/6-8

Cadencee Virtuoso Layout Seminar

Osaka Univ.

5

2017/09/6-8

Cadencee Virtuoso Layout Seminar

Hiroshima Univ.

1

2017/09/6-8

Cadencee Virtuoso Layout Seminar

Akita Pref. Univ.

5

2017/09/13

Synopsys HSPICE Seminar

Univ. of Tokyo8

2017/09/13

Synopsys HSPICE Seminar

Tohoku Univ.

2

2017/09/13

Synopsys HSPICE Seminar

Osaka Univ.

4

2017/09/13

Synopsys HSPICE Seminar

Hiroshima Univ.

1

2017/09/13

Synopsys HSPICE Seminar

Akita Pref. Univ.

5

2017/09/13

Synopsys HSPICE Seminar

Ariake Tech. Col.

9

2017/09/14

Keysight Golden Gate Seminar

Univ. of Tokyo

9

Osaka Univ.

1

2017/09/14

Keysight Golden Gate Seminar

Hiroshima Univ.

1

2017/09/14

Keysight Golden Gate Seminar

Akita Pref. Univ.

5

2018/03/08-09

Cadence Innovus Seminar

Univ. of Tokyo16

2018/03/08-09

Cadence Innovus Seminar

Osaka Univ.

3

2018/03/08-09

Cadence Innovus Seminar

Hiroshima Univ.

3

2017/03/13

Synopsys XA-VCS CoSim Seminar

Univ. of Tokyo13

2017/03/13

Synopsys XA-VCS CoSim Seminar

Hiroshima Univ.

2

2017/03/13

Synopsys XA-VCS CoSim Seminar

Miyazaki Univ.

1

2017/03/14

Synopsys IC Symplify Seminar

Univ. of Tokyo19

2017/03/14

Synopsys IC Symplify Seminar

Hiroshima Univ.

2

2017/03/19-20

Cadence Allegro PCB + Sigrity Seminar

Univ. of Tokyo13

2017/03/19-20

Cadence Allegro PCB + Sigrity Seminar

Hokkaido Univ.

2

2017/03/19-20

Cadence Allegro PCB + Sigrity Seminar

Hiroshima Univ.

2

1-4
11

t

Keysight Golden Gate Seminar

Chapter

2017/09/14

tfrom many societies.
Course A: analog integrated circuit design (7/10-12), Course M1: MEMS design (6/12-13), Courseof the enterprise were invited to the lecturer at "VLSI

M2:MEMS fabrication (7/18-20), and Course R: RF

design refresh seminar" was held aiming at the latest,

circuit design (7/13-14). Teachers from industr y andadvanced knowledge and technical learning concerning

universities involved in the integrated circuit research

VLSI design as a refreshing education for working people

and the education were invited as the lecturer, and they

involved in the integrated circuit industry (Table 1.4.2).

introduced a state-of-the-ar t VLSI design technology

Though this seminar started chiefly in year 1998 underincluding the practice using a lecture concerning VLSI

the support of Ministry of Education Technical Education

design and the latest CAD tool. The participants for theDivision to give practicing education of the latest VLSI

course A, M1, M2, R were 19, 14, 12, 3, respectively.

design technology, it continues under many suppor ts

Fig. 1.4.2 Refresh Seminar at VDEC seminar room at the University of Tokyo, VDEC.

C

Teachers of universities and designers in the first line

ep rt

【Refresh Seminar for Working People】

Table 1.4.2 Refresh Seminar
Course A: Analog Circuit Design (3 days)
Analog Circuit Design and simulation
Integrated Circuits Verification (LVS, DRC)
Masahiro Sugimoto (Chuo Univ.), Hidetoshi Onodera(Kyoto Univ.), Koji Kotani (Tohoku Univ.)
Course M1: MEMS Design (2 days)
MEMS Basic 1: Fabrication Process
MEMS Basic 2: Operation Principle
Structual Design
Layout Design

Chapter

1-4
12

Yoshio Mita (Univ. of Tokyo)
Course M2: MEMS Fabrication (3 days)
CAD Design and Analysis
Lithography, Etching, Release
Vibration measurement and analysis
Yoshio Mita (Univ. of Tokyo)
Course R: CMOS-RF Circuit Design (3days)ttModulation/Demodulation, Cascaded connection
Basic Performace, Tranceiver Architecture
Circuit Element, Design Flowep rt

Hiroyuki Ito (Tokyo Institute of Technology)

example, the failure case and the solution in which【Designerʼs forum for youngteachers and students】

LSI designer has a hard time, the inside stor y of CAD
industry, the construction method in the design milieu in

C

VDEC LSI designer forum intended for students andthe laboratory, and so on. This year, we had the meeting

young teachers has been held. The VDEC LSI designer

in Futsukaichi Hot Spring, in September. No less than 35

for um has aimed to sharing information that cannot

participants were flourishing at the gathering.

be obtained at a society and an academic society, for
Table 1.4.3 Program of Designers Forum in 2017
9/4 (Mon)Time
12:00-12:30

Reception

12:40-14:20

VDEC Design Award Presentation I

14:30-16:10

VDEC Design Award Presentation II

16:20-17:40

VDEC Design Award Presentation III

19:00-VDEC Design Award Ceremony

9/5 (Tue)Time
9:00-10:00

Idea Contest Presentaion

10:00-12:00

Ph.D Session

12:00-13:00

Plenary Talk

13:00-13:10

Closing

1.5 Facilities
The VDEC has provided the big facilities for

Platform refer section 1.8).

universities in Japan from its establishment (1996). Big

In 2017, VDEC has launched a cooperative project withfacilities refer to those which are impossible to acquire

LPKF Laser & Electronics Corporation Japan. LPKFʼsand or maintain by an individual research unit. TableUV laser printed circuit machine (ProtoLaser U3) is

1.5.1 shows the available facilities of VLSI testers andinstalled in Takeda Building room 204 (called as VDEC

some process machines, which are placed at the tester

backend room). The machine is capable of engraving up

room and the super clean room of the Takeda building.

to 35 µm-thick copper wirings and othermaterials.
The facilities can be used by user himself, after amachine (F5112+VD01) were donated to the VDEC bycouple of timesʼtraining by attendance of licensed users;

the ADVANTEST. In the year 2012, VDEC joined MEXT

also, by presence of licensed persons, a new user can(Ministr y of Education)ʼs Nanotechnology platform toreadily use the machine.

Chapter

In 2004, the VLSI tester (T2000) and the EB lithography

enforce its multi-use capability. (For Nanotechnology
Table1.5.1

1-5

Available facility list
Description

StatusContact

Logic LSI test
SystemEB tester:
IDS10000

The chip surface voltage during operation can be measured with the LST tester.
The digital circuit with 384 pins, 1 GHz
can be tested.

Available

nanotech@sogo.t.u-tokyo.ac.jp

LSI tester:
ADVANTEST T2000

The digital circuit with 256 pins, 512 MHz
can be tested. Analog test is optional.

Available

nanotech@sogo.t.u-tokyo.ac.jp

Auto prober:PM-90-A

Automated prober for testing LSI wafers,
which can be used with the LSI testers.
The probe card for LSIs with the VDEC
standard pin connections is available.

Available

nanotech@sogo.t.u-tokyo.ac.jp

Analog/RF measurement
system:
B1500A, 4156B, HP4284,
etc

DC parameter measurement, Capacitancemeasurement, Network analyzer,
Spectrum analyzer, etc.

Available

nanotech@sogo.t.u-tokyo.ac.jp

Low-noize manual prober:Cascade Microtec

6 inch wafer can be measured with six
DC probles and two RF probes upto
50 GHz.

Low-noize, temperature
controlled semi-auto prober: Süss Microtec

8inch wafer can be measured. The chiptemperature range is -50 to 200 °C.

Mask lithography, Direct
lithography: F5112+VD01

Minimum linewidth: 50 nm.
Lithography for 5 inch photomask (thickness: 2.3 mm), 2-8 inch wafers, and chips
is possible.

Available

nanotech@sogo.t.u-tokyo.ac.jp

Rapid Mask and Direct
lithography: F7000S-VD02

Minimum linewidth: 1xnm.
Lithography for 5 inch photomask (thickness: 2.3 mm), 2-8 inch wafers, and chips
is possible. Stencil character projection of
non-square shapes such as circle, triangle
is possible.

Available

Chlorine ICP plasma etcher CE-S

High density plasma etching with Cl2 andBCl3 is possible.

Available

Silicon DRIE MUC-21
ASE-Pegasus

High speed, high aspect ratio etching ofsilicon is possible

Available

C

Nanotechnology
Platform
Apparatuses

ep rtAnalog/RF
measurement
system13t

Equipment nametFacilityChapter

1-5
14

t
t

UV Laser Printed Circuit
Board Engraver LPKF
ProtoLaser U3Using UV laser, copper material up to
35µm and other materials such as flexible
material can be engraved.

Available
at VDEC
204

FIB systemFIB:
SII XVision200TB

Repair of photomask, sample etching,etc. (Through Nanotech. Platform and
LCNet)

Available

LSI FIB system

FIB: FEI V400ACE

Repair of VLSI from both frontside andbackside, with CAD navigation and / orIR camera is possible. W/SiO2 depositionis possible.

Available

Chip Bonding
SystemWedge Bonder: Westbond
7476D

25 µm φ Al or Au wire wedge bonding
machine.

Available

Epoxy Die Bonder
Westbond7200C

Precision Manupilator system. Epoxy
and or Ag paste chip bonding and or
glued wiring.

Semi-Auto Bonder
Westbond4700E

18 〜 25 µm φ Au Ball bonding or bumpcreation.

Precision Manual FlipChip Bonder Finetech
Fineplacer Lambda

Face-to-face bonding up to 15 mm squarechips. Alignment is through video camera. Bonding is by heating chips with TV
camera. (Ultrasonic Unit can additionally be purchased.) XY ± 0.5 µm, and θ=1mrad precision.

ep rt
C

1.6 Activity plan for 2018
VDEC will continue activities on chip fabrication

Mentor tools as the main stream design tools. We will

ser vices, CAD tool support, dispatching design related

continue analog RF design environment, GoldenGate andinformation and donated division “D2T”，as has been

ADS by Agilent, C-based design environment, BachC

previous years.

by Sharp. In addition, we continue trial of several CAD【Design related information
dispatching/Seminar】

tools, such as layout platform, Lavis by TOOL. Design

We will continue holding the following seminars:
since 1997, (2) “Refresh seminar” since 1998, (3)Cadence tools and will be continued. Smar tSpice by
Silvaco, will be also continued.

【Chip fabrication services】“DesignerʼFor um” since 1997. We will also continue

We will continue chip fabrication ser vices for SOTB

seminars for LSI tester usage at VDEC and sub-centers,

65 nm CMOS by Renesas Electronics, 0.18 mm CMOS

workshops on LSI testing technologies initiated by D2T.

by Rohm, FD-SOI 28 nm CMOS by ST Microelectronics【CAD tool support】

through CMP and 0.8 mm CMOS by On-semiconductorSanyo as the regular services.

1-6
15

t

We will continue Cadence tools, Synopsys tools andChapter(1) CAD tools seminars which have been continued

debugging platform from SpringSoft has merged intot

Table 1.7.1 Chip fabrication schedule
Design deadline

Chip delivery

2018 #1

2017/ 7/10

2017/10/ 2

2017/12/25

2018 #2

2018/ 1/15

2018/ 3/26

2018/ 6/25

Chip application deadline

Design deadline

Chip delivery

2018 #1

2018/ 4/ 2

2018/ 6/25

2018/10/12

2018 #2

2018/ 6/18

2018/ 9/10

2018/12/28

2018 #3

2018/ 8/13

2018/11/ 5

2019/ 2/22

2018 #4

2018/12/ 3

2019/ 2/25

2019/ 6/14

Chip application deadline

Design deadline

Chip delivery

2018 #1

2018/ 6/18

2018/ 7/30

2019/ 2/ 2

2018 #2

2018/12/17

2019/ 1/28

2019/ 7/27

C

Chip application deadline

ep rt【CMOS 1.2μm2P2M】 On-Semiconductor(Former Motorola Japan)【CMOS 0.18μm1P5M(+MiM)】 Rohm

【FD-SOI CMOS 28 nm1P10M】ST Microelectronics
Based on the chip fabrication schedule through CMP.

【SOTB CMOS 65 nm】 Renesas Electronics

1.7 Venture companies related to VDEC
Some professors related to VDEC started venture companies. The following is a list of the venture companies related
to VDEC.

[1] AIL Co., Ltd. (http://www.ailabo.co.jp/)
Related professor : Professor Kazuo Taki, Kobe Univ. (President-Director)[2] Synthesis Corporation (http://www.synthesis.co.jp/)

Chapter

Related professor : Professor Emeritus Isao Shirakawa, Osaka Univ. (Director)
Description of business : (1) Hardware/software co-design(2) System LSI design, design services(3) Development and sales of IPs

1-7
16(4) Development of EDA tools[3] Nanodesign Corporation (http://www.nanodesign.co.jp/)tRelated professor : Professor Kazuyuki Nakamura, Kyushu Institute of Technology. (Representative Director)t[4] A-R-Tec Corp. (http://www.a-r-tec.jp/)

ep rt

Related professor : Professor Emeritus Atsushi Iwata, Hiroshima Univ. (Representative Director)
Description of business : (1) Measurement and analysis of LSI substrate noise(2) Design of analog-RF mixed signal LSIs
(3) Training of analog design on the JOB method

C[5] Ishijima Electronics (http://ishi.main.jp/)
Description of business : (1) Electronic circuit development(2) Software development(3) Consulting

1.8 “Nanotechnology Platform”:
Ultra Small Lithography and NanometricObservation Site

Engineering Innovation of Graduate School ofbut excluding VDEC), and 10 from public researchEngineering. The site is supported by Japanese Ministry

institutes. The exposure count was 2434 for 12 monthsof Education (MEXT)ʼs Nanotechnology Platform grant.

(202.8 / month), which is the first time that use per

Any researchers in Japanese Universities, Laboratories,

month exceeded 200. As shown in the Fig. 1, usage is

and Companies can take full advantage of The University

monotonously increasing. “Open ratio”，which is theof Tokyoʼs cutting-edge nanotechnology apparatuses

number of days in which users outside the University ofand know-hows. The accessible technology includes

Tokyo came, divided by machine open days, was 99%.

Lithography and Etching environment, Ultra High-Due to the strong support of nanotech. Platform, even a

Voltage Acceleration (1MV) transmission electron

novice user can obtain fine lithography result by using

microscope (TEM) that is capable of visualizing upto

the apparatuses with the Platform engineering staffs oflight materials such as Nitrogen. VDEC takes par t in

VDEC. Consequently, free machine time is decreasing so

the lithography at Takeda Sentanchi Super Cleanroom.

the team is trying to acquire financial support to increase

Through VDECʼs key apparatus F5112+VD01 donatedthe number of machines. Also in FY2017, the Frenchfrom Advantest Corporation as well as F7000S-VD02

Nanotechnology Network project CNRS-RENATECH

purchased by national budget, VDEC is supporting post-

asked to the UTokyo VDEC to launch an engineer-

VLSI activities such as MEMS. The machine is capableclass international exchange program. The program isof rapidly writing patterns on arbitrar y-shaped targets

financially fully supported by VDECʼs project and one

sizing from 1cm-sqare chip to 8-inch round wafers. The

Ph.D-holding research engineer from France (FEMTO-

per formance is measured by the number of research

ST, Besançon) is with VDEC Mita Lab for one year.

repor ts and machine use. The University of Tokyosite has received 168 research repor ts, composed of

URL:http://nanotechnet.t.u-tokyo.ac.jp/

Fig. 1 Monthly Average Exposure Count of EB Machine (s).

1-8
17

C

UTokyo researchers (including external collaboration

ep rtEnterprises (SMEs), 35 from other universities, 91 from

Obser vation Site” together with the Institute oftplatform “Ultra Small Lithography and Nanometrict

29 from big companies, 4 from Small and Medium-size

Chapter

VDEC is operating an open-use nanotechnology

2. Activity Report of
ADVANTEST D2T Research Division
2.1 Introduction of
ADVANTEST D2T Research Division

2.1.1 Aim of the establishment of
ADVANTEST D2T Research
DivisionT h e A D VA N T E S T D2T r e s e a r c h d i v i s i o n w a s
established in VDEC in October 2007. As the namesuggests, it is financially suppor ted by ADVANTEST
Corporation.
The aim of establishment of the ADVANTEST D2T

In this financial year, we invited Professor Adit Singhfrom Aubur n University (2018/1–）for research andeducational collaboration with VDEC.
The details of our groupʼs activities are presented in thefollowing sections.

2.1.2 Members of ADVANTEST D2T
Research Divisionresearch division is to promote the research andProject Professor

education environment of VLSI testing in all universities

Project Professor

Adit Singh (2018/1〜)

and colleges in Japan. “D2T” means that we consider not

Project Lecturer

Akio Higo (2017/10〜)

only design but also testing. Through our activities, we

Project Lecturer

Rimon Ikeno (〜2017/9)

hope to provide expertise in design and testing for the

Project Researcher

Parit Kanjanavirojkul

industry. In addition, we are exchanging researchers withother universities and research institutes in both Japan

Chapter2-1
18Masahiro Fujita(2017/4〜2018/3)
Researcher

Takahiro Yamaguchi

and overseas. Moreover, the D2T research division is(ADVANTEST Laboratories Ltd.)suitable for collaborations with the industry because the(〜2017/12)

testing of VLSI is one of the most practical research topics

Researcher

in the industry. Based on these activities, our final goal is(ADVANTEST Corporation)

to become a center of excellence of VLSI testing in Japan.
The D2T research division has spent 10 years in total

Masahiro Ishida(〜2017/9)

Researcher

Koji Asami

for the 1st (Oct. 2007–Sep. 2010), 2nd (Oct. 2010–Sep.

(ADVANTEST Corporation)2013), and 3rd (Oct. 2013–Sep. 2016) project phases, and(2017/10〜)

now we are in the 4th phase of the D2T project courtesyof ADVANTEST Corporation.

Assistant Clerk

Makiko Okazaki

e ear h2.2 Report of 12th D2T Symposium
The 12th D2T Symposium was held on September 28th,2017 at Takeda Hall.

Prof. Wolfgang Kunz and Prof. Dominik Stof fel fromTechnische Universität Kaiserslautern. The symposiumThis year, we invited four lecturers from overseas

also featured special lectures by Prof. Shinichi Takagi andfor their work on research topics related to IoT and

Prof. Hiroyuki Morikawa from the University of Tokyo.

data analytics: Prof. Kwang-Ting (Tim) Cheng fromWe sincerely appreciate ever y par ticipant for theirHong Kong University of Science and Technology, Prof.

contribution at the symposium. We look forward to seeing

Shawn Blanton from Carnegie Mellon University, andmany participants again at the next symposium.

Chapter2-2
19

e ear h12th D2T Symposium program
10:00

Opening Remarks
Kunihiro Asada (Director, VDEC, The University of Tokyo)
Koichi Tsukui (Managing Executive Officer Executive Vice President, Corporate Relations
Group, ADVANTEST Corporation)

10:30

Session 1 (Chairman: Makoto Ikeda, The University of Tokyo)“Advanced MOS device technology for ultra-low-power IoT applications”
Shinichi Takagi (The University of Tokyo)“Going Digital: Transformation of Society, Industry, and Life”
Hiroyuki Morikawa (The University of Tokyo)

12:00

Lunch

13:15

Session 2 (Chairman: Tetsuya Iizuka, The University of Tokyo)“Power Supply Impedance Emulation to Eliminate Overkills and Underkills due to the ImpedanceDifference between ATE and Customer Board”
Toru Nakura (The University of Tokyo)“Common Pitfalls in Application of a Threshold Detection Comparator to a Continuous-Time LevelCrossing Quantization”
Takahiro J. Yamaguchi (Advantest Laboratories Ltd., The University of Tokyo)

14:05

Break

14:15

Session 3 (Chairman: Yoshio Mita, The University of Tokyo)“Variation and Failure Characterization Through Test Data Analytics”
Kwang Ting Cheng (Hong Kong University of Science and Technology)

Chapter“Test-Chip Design for Yield Learning at the 7-nm Technology Node”
Shawn Blanton (Carnegie Mellon University)
15:45

Coffee Break

16:15

Session 4 (Chairman: Masahiro Fujita, The University of Tokyo)

2-2

Rethinking Design in the IoT Era - How Formal Methods Help to Meet the Challenges”
Wolfgang Kunz (Technische Universität Kaiserslautern)

20“Software in a Hardware View: New Models for Firmware Development and Safety Analysis in IoT
Systems”
Dominik Stoffel (Technische Universität Kaiserslautern)
17:45

Closing

18:00

Receptione ear h2.3 Research Activity Reports of ADVANTEST
D2T Research Divisionrity control method based on the feedback operation.
High-Resolution Analog-to-Digital Converter Basedon Stochastic Comparators

We proposed a new modeling method of series
impedance connection using the nested-feedback

Takahiro J. Yamaguchi, Parit Kanjanavirojkul,

configuration in the digital filter composition for the

Nguyen Ngoc Mai-Khanh, Rimon Ikeno,

previously proposed feedback-based power supply

Tetsuya Iizuka, Kunihiro Asada

impedance emulation, and we demonstrated its feasi-

This project aimed to implement a high-resolution

bility through computer simulation and experiments.

sub-ranging analog-to-digital converter (ADC) circuit

We also extended the impedance modeling method tobased on stochastic comparators.

cases with multiple power-supply pins and carried out

Process variations, together with many factors such

simulation-based studies to verify the assumed mod-as variations in voltage or temperature, lead to mis-eling methods. Furthermore, we demonstrated thatmatched design parameters that produce input-referred

the proposed method can eliminate the discrepancy ofoffsets and hence cause non-linearity and missing out-

test results between two power-supply environments

put codes in an ADC. Instead of attempting to suppress

through an experiment with FPGA devices.

such process variations as in conventional ADC, thestochastic ADC approach exploits process variations
based on the assumption of a Gaussian distribution ofHigh-Performance Analog-to-Digital Conversion

comparator offset voltage. We identified the root cause

Using the Wideband Spread Spectrum and Itsof a voltage bounce of the source nodes of the compar-

Application
Koji Asami, Byambadorj Zolboo, Akio Higo,error of the flash ADC circuit at the first stage in our

Tetsuya Iizuka, Kunihiro Asada,

Chapterator input PMOSFETs, which introduces a conversion
sub-ranging ADC system, as quick signal transition.

To measure low-cost RF devices for IoT and otherWe improved the performance of the ADC by refining

applications, analog-to-digital conversion techniques

operational conditions, such as input signal frequency,with a low cost and high efficiency are required. To

2-3

slope, and voltage range, as well as by adding a delay inacquire narrow-band modulation signals scattered in a

21

starting the differential current integration so as to dis-wide frequency range, a compression sampling methodcard the unstable current during the bouncing period.

is studied.
In this financial year, a modulated wideband converter was investigated as a compression sampling method.

Power Integrity Evaluation Method

After a recovery error using an arbitrary waveform was

Masahiro Ishida, Naoki Terao, Rimon Ikeno,

estimated, we determined that the recovery of a side

Toru Nakura, Tetsuya Iizuka, Kunihiro Asadalobe, as well as the main lobe, is required in a modulated waveform. Therefore, the relationship among recov-

decreased owing to the advanced miniaturization ofery error, ADC performance (resolution and sampling

the semiconductor process, the power-supply currentrate), and the number of channels is needed to estab-consumed by a semiconductor device has increased

lish the cost of ADC. We study the cost of ADC, spreadbecause of the huge number of transistors integrated

code, recover y algorithm, and mismatch correction

on a single chip. This may increase the power-supply

between analog-to-digital channels.

noise and cause power integrity issues of the device
under test in both an ATE and practical operating environments. The purposes of this research project are todevelop a power deliver y network modeling method
for evaluating power integrity at on-chip power-supply
nodes in semiconductor devices and a new power integ-

e ear hWhile the required power-supply voltage has

EBDW use in fields such as MEMS and photonics.
High-Throughput and High-Accuracy Electron-Beam

We investigated the resist and development process

Direct Writing (EBDW) Strategy for Wide Range ofconditions for the high-resolution observation of litho-

EBDW Applications

graphic results by our high-throughput and high-accu-

Rimon Ikeno, Akio Higo, Yoshio Mita, Kunihiro Asada
Maskless lithography by electron-beam direct writ-variable-shaped beam (VSB) methods. A new CP masking (EBDW) is expected to be a low-cost lithography

for the F7000S EB writing system in the VDEC Takeda

technology with a short turn-around time (TAT), but it

Clean Room was designed for fur ther per formance

has some drawbacks such as a low process throughput

improvement. We also conducted a numerical analysis

and low accuracy against the intended layout shapes.

of chip temperature during the EB exposure process as

We are pursuing a high-speed and high-accuracy

well as the propagation loss of light waveguides depen-

EBDW strategy utilizing the character projection (CP)dent on the line-edge (wall) condition.

method to overcome these concer ns and to boost

Chapter2-3
22

racy EB exposure strategy that combines the CP ande ear h2.4 Publications
International Conferences,
Symposiums, Workshops

Domestic Conferences, Workshops, etc.

[1]

Naoki Terao, Tor u Nakura, Masahiro Ishida, Rimon

Asada “Performance Analysis of Level-Cross Detection

Ikeno, Takashi Kusaka, Tetsuya Iizuka, and Kunihiro

Method Based on Stochastic Comparator,” IEICE-

Asada, “Extension of Power Supply Impedance Emulation
Method on ATE for Multiple Power Domain,” 22nd IEEE
European Test Symposium (ETS 2017), May 2017.

T. Sugiyama，T. Iizuka，T. Yamaguchi，T. Nakura，K.

CAS2017-66, IEICE-ICD2017-54, IEICE-CPSY2017-63,
12/14/2017.

Chapter2-423

e ear hChapter 3 Research in VDEC
Asada, Nakura and Iizuka
Laborator y(http://www.mos.t.u-tokyo.ac.jp)

lation results of area, power and jitter of PWPLL withdifferent gate length cells and choose an appropriate
PWPLL design from performance specification. The
inputs of the compiler are standard cell libraries, several manual cells, SPICE parameters and the target spec-

LSI Test and Improved Reliability in Ultra-Fineification input-output frequency, the division ratio andProcess Technologies

the Process, Voltage, and Temperature (PVT) corner

Kunihiro Asada, Toru Nakura, Tetsuya Iizuka,

conditions. The PLL compiler calculates rough values

Naoki Teraoof the design parameters, runs SPICE simulations, ana-

In LSI test, mismatch of power supply impedancelyze the waveform files to adjust the design parameters,

between an automatic test equipment (ATE) and a cus-considering the variation of the PLL characteristics

tomer board can cause overkills and underkills. We pro-with the given PVT variation. When the waveform sat-pose power supply impedance control method on theisfies the specification, the compiler generates a verilog

ATE for emulating arbitrary power supply impedance

netlist and a GDS is designed from the netlist.

using compensation current injection. Experimental

Besides, since skilled circuit designers need to spend

measurement results by a prototype system shows thata lot of time to make PLL(Phase Locked Loop) cir-the voltage fluctuation waveform of the ATE is adjusted

cuits, so a method by which everyone can create a PLL

to that of the customer board, meaning that the imped-

circuits in a short time is required. In this research,ance on the customer board is successfully emulated

automatic design was made possible by creating a DCO

by the ATE.

(Digital Controlled Oscillator) in the digital PLL circuit

Our digital filter implementation method using feed-using an inverter, NAND gate and 4-input multiplexer.

back can be applied to arbitrary impedance network,

We automatically simulated the DCO performance by

not only for the power supply with single supply pin but

SPICE, automatically found the appropriate parameters

also for the power supply with multiple power domains.

of the DCO circuit from the input performance of DCO

To confirm the effect of the proposed method on real

and automatically created the layout of DCO using a C

LSI test, we developed a virtual ATE for demonstration.

Chapter 3

3-1
24

program.

Test result of 50 real devices shows significant reduc-We also do a research on LDO. Designing LDO reg-tion of overkills and underkills under the power supply

ulators nowadays almost largely demands analog cir-condition with impedance emulation.

cuit design flows. Because Analog flows take time andeffort, they become a bottleneck in designing LDOs.
In this research, to remove the loads of analog flows,e ear hPLL and LDO circuits with Time-Domain control

we applied a method of making LDOs with a P&R tool

Kunihiro Asada, Toru Nakura, Tetsuya Iizuka,

which is usually used in digital circuit design flows. In

Keigo Tu, Jing Wang, Naoki Ojima, Hidemasa

conventional LDOs, the parts which makes compar-

Yoshimuraison between the reference and the output, such as

C

In this research, we have applied time-domain con-error amplifiers or comparators, often require analog

trol methods to PLL circuit and its measurement. A

flows. The proposed circuit in the research contains

Pulse-Width Controlled PLL (PWPLL) is a new typetwo inverter chains and a phase detector. The phaseof PLL whose oscillator is controlled by a pulse width.

detector recognizes the voltage difference between ref-

The PWPLL is implementable in a very small area, on

erence and output as the delay difference between two

the one hand, its operating conditions are sensitive to

inverter chains. This comparison part is all synthesiz-

the several variations. For example, a lock range of theable from standard cells, so all the circuit can be madePWPLL tends to be narrower than that of other PLLs.

by a P&R tool. We designed and made the proposed

We demonstrated a PWPLL compiler which generates GDS data and summarizes synthesized and simu-

circuit, and confirmed trackability when the referenceor the load current are changed.

have received wide spread attention since they canTime Domain CDR and TDC Designs

specify the nuclide of radiation and estimate the arriv-

Kunihiro Asada, Toru Nakura, Tetsuya Iizuka,

al angle. Former research proposed a detector using

Meikan Chin, Ryuichi Enomoto

the cube scintillator, SPAD (Single Photon Avalanche

While digital circuits directly benefit from advanced

Diode) array image sensors, multi-coated materials,

process technologies, analog circuits suffer from neg-and pinholes and verified the method to detect the posi-

ative effects such as small voltage headroom. Time-tion of point light source inside the scintillator. We pro-domain circuits, where analog signals are represented

posed a new method which calculated the track of pho-by digital signal edge transitions, could be a solution totons to precisely estimate the position of light source.

the problem of analog circuits in a nanometer process.

This method can cost less time to detect the lightTime-to-Digital Converter (TDC) is a representative

source position compared to the former research. The

example of time-domain circuits. TDC basically con-result of the simulation verified that by using this meth-verts a time interval between two rising edges into aod the position of the light source inside the 1 mm-size

digital code by using delay elements. In our research,

scintillator could be detected with a spatial resolution of

we focus on a pulse-shrinking TDC, which is one kind

10 um-20 um in less than 0.3s.

of the sub-gate-delay resolution TDCs. In general, TDC

About the SPAD imager, we have designed several

has a trade-off between the time resolution and dynam-

SPADs with dif ferent structures in standard CMOS

ic range, and the trade-off is particularly remarkable inprocess, and found a suitable structure. Then, a 31 x

the pulse-shrinking TDC. Last year we designed and

31 SPAD imager with event discriminator based on themeasured a TDC that improves the dynamic range

proposed breakdown pixel extraction architecture has

while keeping the high resolution by using a hierar-

been fabricated, and its functionality of short weak lightchical approach. We found that the TDC has a serious

detection has been demonstrated.

nonlinearity caused by process variation. So, we analyzed the impact of it by Monte Carlo simulation anddesigned a new TDC resistant to process variation.
TDC can be applied for various applications andHigh-Frequency Circuit Design for Communication
through Dielectric Waveguide
Kunihiro Asada, Toru Nakura, Tetsuya Iizuka, Nguyen

Gated Oscillator (CLGO) is one example. Since the

Ngoc Mai-Khanh，Yoshitaka Otsuki, Daisuke Yamazaki

CDR consumes no dynamic power in its standby state

High-speed communication with the millimeter-wave

and resumes from the standby state just after a 4-bitband has been actively researched. Wireline communi-

preamble, it can improve the total power efficiency of

cation with a dielectric waveguide such as polymer has

serial communication systems that work intermittently

been proposed and expanded research. Because it issuch as mobile and IoT sensor node applications which

possible to increase the communication distance at low

require not only low power consumption in operation

cost while maintaining the communication speed.
The signal leaks to the outside at the bent portion ofstandby state. We proposed CDR using Delay Tunable

the waveguide when the frequency is low in the dielec-

Buffer (DTB) and Vernier TDC for tracking frequency

tric waveguide communication. Therefore, a high-fre-range extension and low power consumption, designed

quency oscillator is required. In this research, we stud-and measured. While DTB and digital control work as

ied oscillators that oscillate at 140 GHz and have low

designed, we found the deviation of timing in Vernierphase noise, and also designed transmission lines andTDC. So we proposed new Vernier TDC whose refer-pads for measurement.

ence level is tunable.

3-1
25

e ear hbut also in standby state and quick startup form the

Chapter 3

Clock and Data Recovery (CDR) based on Cycle Lock

The dielectric waveguide is superior to the metal
waveguide in terms of weight and price, the loss is

Radiation Detector Utilizing Semiconductor
PhotodiodeKunihiro Asada, Toru Nakura, Tetsuya Iizuka,
Yang Xiao
Scintillation detectors and semiconductor detectors

In this research, we designed a low loss on-chip coupler for use in dielectric waveguides.
One of the main causes of the electric-electromagnetic wave conversion loss in the on-chip coupler is thatpart of the electric power is converted into heat due toClarge, so that a low loss on-chip coupler is required.

the eddy current generated in the substrate. For thisa circuit with PD control circuit and time delay element

reason, we propose a method to suppress the eddy

based on the circuit in the previous research. Using

current by removing the Si substrate of the chip andsimulation, we showed that the circuit can reduce

reduce the loss during conversion. We verified this low

crosstalk more effectively.

loss implementation method and designed a chip forverification.
High-Precision A-D Converters
Kunihiro Asada, Toru Nakura, Tetsuya Iizuka, Takaaki
Design and Analysis Method for High-Reliability
LSIs

Ito, Taiki Sugiyama
Analog-to-Digital Converters (ADC) are widely used

Kunihiro Asada, Toru Nakura, Tetsuya Iizuka, Nguyen

as circuits which convert analog signal to digital signal.

Ngoc Mai-Khanh, Norihiko Nakasato,

Low-power and high-precision ADCs are needed for

Daigo Takahashi, Tamaki Fukudome

applications such as biomedical sensing and wireless

The modern VLSI systems that demand high reliabil-sensor network. In this study, successive approxima-

ity require carefully-designed power/ground networktion register (SAR) ADC which have several advantag-

to provide stable power supply. Using the measurement

es for better power efficiency is designed in order toresults of magnetic field emission from LSI, the pro-achieve high-precision and low-power ADCs. Though

posed method estimates the actual current flow fromthere is a tradeoff between conversion accuracy andthe magnetic field measurement results and enables

power consumption, we optimized power consumption

us to find defects or design faults such as VIA/wireby combining noise tunability implemented to compara-

disconnections and/or current concentration with low

tor and redundant bit technique. Recently, we designed

cost. To verify the feasibility of the proposed method

prototype ADC and evaluated its performance.

with actual measurement results, the test structure is

ADC based on level-cross detection quantizes time

designed and fabricated in 0.18 um 1P5M CMOS pro-rather than voltage. When the clock frequency is

cess. Current flow of power network in the chip was

doubled, SNR of ADC improves 3 dB whereas thatsuccessfully estimated by actual measurement data.

of level-crossing ADC improves 6 dB. Therefore, lev-

Information security is very important in the mod-el-crossing ADC benefits more from fine time resolu-

ern society in which the Internet has penetrated. Intion in scaled technologies. A stochastic comparator

this research, we propose a method to enhance thethat drives multiple comparators in parallel is proposed

reliability of PUF (Physical Unclonable Function) andto improve both voltage and time resolutions by utiliz-

Chapter 3

TRNG (True Random Number Generator) by employ-ing stochastic nature of offset and noise whose impact

ing aging phenomenon of scaled MOSFET to control

is increasing through process miniaturization. A sto-

the threshold voltage. Reliability enhancement of both

chastic comparator is familiar with the digital design

circuits will lead to miniaturization and low-power

because of the concept based on process variation and

3-1

consumption of security hardware. Currently, we con-

it will improve the performance by process miniatur-firmed by measurement that it is possible to improveization. We analyze the precision of level-cross-timing

the reliability of both circuits by inducing proper degra-

estimation method based on a stochastic comparator.

dation in the SRAM.

We show that the level-cross-timing estimation method

26

e ear hC

With the improvement of the circuit performance

exhibits finer resolution compared to that uses the sin-

due to the miniaturization of the semiconductor pro-gle comparator with the same total area of comparators.

cess, the speed of transmission has been improving.

We also verify the theor y by measurement. Another

The data rate necessary for applications also has been

design approach is stochastic approach in which many

improving because UHD TVs and automobiles withcomparators are driven in parallel. This emerging

a lot of electrical equipment was developed. It is nec-

approach can be applied to level-crossing ADC and it isessary to speed up transmission from both aspects ofcalled level-crossing stochastic ADC. We analyze input

technology and demand, crosstalk is one of the factors

slope dependency of level-crossing stochastic ADC byhindering this. As measures for crosstalk, a circuit forcircuit simulations. And we will measure the input slope

reducing crosstalk at the receiving end was proposed

dependency using the chip we designed manually.

in the previous research. In this research, we proposed

Fujita Laborator y(http://www.cad.t.u-tokyo.ac.jp/)

Post-Silicon Debugging of Electrical Bugs
Masahiro FUJITA, Amir Masoud GHAREHBAGHI,
Kentaro IWATA

Automatic Correction of Logic Bugs after ECO

Electrical bugs are an important category of post-sil-

Masahiro FUJITA, Amir Masoud GHAREHBAGHI,

icon bugs that are typically hard to debug due to com-

Yusuke KIMURA, Peikun WANG, Yukio MIYASAKA,

plex interdependence of layout and netlist as well as

Kentaro IWATA, Xingming LE, Xiaoran HAN

their dependency to the running workload and environ-

Correction of logic bugs after ECO usually requires

ment. In this work, we tackle the problem of debugging

changing the functionality of some logic gates as wellelectrical bugs using trace buffers. Given erroneous

as changing the topology or connections among thevalues captured in the trace buffer due to occurrence

gates. In this work, we have introduced techniques toof an electrical bug, we try to identify the spatial andefficiently accommodate even hard ECO cases, such

temporal location of the error. We have formulated theas changing the functionality for a few minterms of the

problem of debugging electrical bugs as a SAT prob-

whole circuit. Our experiments on ITCʼ99 benchmarks

lem and proposed a debugging method based on that.

show that we can find the function after ECO after tens

Moreover, we have shown that the existing signal selec-of iterations of solving SAT problems even in the casetion methods for logical bugs that are typically trying toof hard ECO problems. In addition, we have shown the

maximize signal restoration ratio (SRR) metric, do notpotential application of the method for approximate

perform better than random selection when debugging

logic synthesis. Moreover, we have extended our pre-electrical bugs. On the other hands, utilizing a morevious method to deal with multiple buggy locations

sophisticated signal selection that is considering prop-

in addition to its ef ficient implementation. Our pro-agation of bit-flips due to electrical bugs is more effec-

gram for “Resource-aware Patch Generation”, named

tive.

DEPAG, has won the 3rd prize in the 2017 CAD contest
at ICCAD conference (among 38 participated teams inthe same track).

Template-Based High-Level Partial Synthesis
Masahiro FUJITA, Amir Masoud GHAREHBAGHI,
Yusuke KIMURA, Qinhao WANG

Efficient Test Pattern Generation for Different Fault
ModelsIn this work, we have introduced method for C
language description generation method based on
templates. We have used the method to reconstruct

Peikun WANG

the corresponding C description after ECO in regis-

are not sufficient for the modern LSI chips, as the sim-

description before ECO, which is not equivalent tople model of single stuck-at fault cannot cover many

the design after ECO, we iteratively try to change thekinds of defects. Therefore, it is necessar y to have

portions of the C description until the solution is found,

efficient ATPG methods for other fault models such as

and the new C description becomes equivalent to themultiple stuck-at fault and bridging fault. In this work,

design after ECO. Moreover, we have shown applica-

we have introduced efficient methods for test patterntion of the method in high-performance computing. In

generation for double stuck-at fault model. Moreover,this method, starting from an original description that

we have introduced a new approach for diagnosing

is not suitable for hardware implementation or acceler-bridging faults. Our experiments on ISCAS bench-

ation, the design is refined iteratively by using the tem-marks shows that even in large benchmarks, with aplates until it becomes ready for hardware implementa-

couple of SAT solving, on average, a fault can be diag-tion/acceleration.

nosed.

3-1
27

C

ter transfer level (RTL). Starting from the original Ce ear hTraditional test pattern generation (ATPG) methods

Chapter 3

Masahiro FUJITA, Amir Masoud GHAREHBAGHI,electronic object. To enable the levitation of a particle,
Acceleration of Neural Network with FPGA

a custom IC chip is essential in reducing the size andMasahiro FUJITA, Amir Masoud GHAREHBAGHI,

weight of the particle. In the design of the custom IC

Tomohiro OKAMOTO

chip, a new voltage detector circuit enabling an accu-

Acceleration of large neural networks is usually notrate voltage detection and a correct output during thepossible by a single FPGA chip. Therefore, we need tostart-up is proposed to achieve an intermittent lighting

utilize multiple connected chips to be able to accelerateof the LED to increase the maximum distance between

large neural networks. In this work, we have intro-

the transmitter and the receiver coil. Luciola is applied

duced methods to efficiently partition computations of

to a self-luminous pixel in a mid-air display and draw-

a spiking neural network on several FPGA chips con-ings of characters in mid-air are demonstrated.

nected together in a ring topology. We have shown thatwith 8 FPGA chips, 6144 (8*768) neurons can be simulated.

Programmable Gate Driver IC for IGBT
Makoto Takamiya and Takayasu Sakurai
A programmable gate driver IC for IGBT to dynami-

Design Automation for FPGAs with Neighboringcally change the gate driving current during the switch-Communication

ing of IGBT is developed. In the proposed gate driver,

Masahiro FUJITA, Amir Masoud GHAREHBAGHI,

the 6-bit gate control signals with four 160-ns time steps

Tomohiro MARUOKA

are globally optimized using a simulated annealing

In this work, we have presented design automation

algorithm, reducing the collector current overshoot bytechniques for special kind of programmable devices

37% and the switching loss by 47% at the double pulse(FPGAs) that their internal logic blocks only havetest of 300 V, 50 A IGBT.

communication with neighboring blocks. We have formulated the problem of mapping and routing as integer
linear programming (ILP), and introduced heuristics

Integrated Voltage Regulators for Energy Efficientto accelerate solving the problem. We have shown that

Microprocessors

for medium size ISCAS circuits, efficient mapping androuting is feasible within practical time.

Makoto Takamiya and Takayasu Sakurai
A 2/3 and 1/2 reconfigurable switched capacitor(SC) DC-DC conver ter is developed for a per-core
dynamic voltage scaling of many-core microproces-

Chapter 3

3-1
28

sors. The power conversion efficiency and the output

Takamiya Laborator y(http://icdesign.iis.u-tokyo.ac.jp/)

power density of the SC DC-DC converter in 2/3 modeis degraded, because full-swing and half-swing drivers
for power transistors are mixed and the resistive lossof the power MOSFETs with the half-swing drivers is

Energy Harvesting, Wireless Powering, and DC-DC

large. To solve the problem, a fully-integrated driver

Converters for IoT Nodes.

amplitude doubler (DAD) is proposed. In DAD, thee ear hMakoto Takamiya and Takayasu Sakurai

gate amplitude of the power MOSFETs is increasedC

We present an approach to realize the levitation of

from half-swing to full-swing by generating a 1/3 input

a small object with an embedded electronic circuit.

voltage sampled from a flying capacitor. In the fabri-

Luciola is a light-emitting particle with a diameter ofcated 2.7-V input SC DC-DC converter mounting four

3.5 mm and a weight of 16.2 mg moving in mid-air in

100-nF 0402 (0.4 mm x 0.2 mm x 0.2 mm) multilayer

a 10.4 cm x 10.4 cm x 5.4 cm space through acoustic

ceramic chip capacitors (MLCCs) on 180-nm CMOS dielevitation using two 40-kHz 17 x 17 ultrasonic trans-achieves the highest efficiency of 92.9% at the output

ducer arrays placed face-to-face at a distance of 20 cm

power density of 62 mW/mm2 in the published step-

and wirelessly powered by 12.3-MHz resonant induc-down SC DC-DC converters.

tive coupling. The novelty is the acoustically levitatedelectronic object by the combined application of ultrasonic levitation and wireless powering to the levitated

Ikeda Laborator y(http://www.mos.t.u-tokyo.ac.jp)

which is a additive homomorphic cryptosystem widelyused in the field of biometric authentication, and highspeed implementation of lattice-based encr yption forthe post-quantum era. Examining the degree of paralel-

Design of High Performance Cryptographic

lism and area cost for the number theoretic transform

Processor(NTT), which is the core algorithm for lattice-based

M. Ikeda, H. Awano, S. Sugiyama, R. Saito, andcryptography, we implemented an evaluation chip.

F. Arakawa
Public key cr yptography based on elliptic cur ve
cryptography is widely employed from automobiles to

Evaluation of attack resistance of PUF Using Deep

terminal sensor nodes, and performance requirement

Learning

for cryptographic engines is also diversified. For exam-

M. Ikeda, H. Awano, and T. Iizuka

ple, in vehicle-to-vehicle communication, signature

Recently PUF (Physically Unclonable Function)

generation and signature authentication with extremely

has attracted a lot of attention as a method that is low

low latency and high throughput are required for auton-

cost and secure device authentication. Among PUFs,

omous driving, so speeding up by hardware imple-

Double-Arbiter PUF (DAPUF) is known to be highly

mentation of elliptic curve cryptography is becoming

resistant to modeling attacks. We proposed a deep

important. We have designed and fabricated crypto-pro-neural network-based modeling attack for DAPUF andcessors capable of scalar multiplication which the coreevaluated the resistance of that. Our model successfully

operation for elliptic curve cryptography. We optimized

predicted responses to unseen challenges with proba-

the scheduling of pipeline Montgomer y multipliers,

bility of 88.4%, which is 21.1% higher than the conven-results in throughput per area by 1.6 times comparedtional method. Those results highlight an importantwith the conventional state-of-the art. Measurement

fact that PUF-based authentication schemes should

results demonstrates signature generation time of

be carefully designed considering the rapid evolving

31.3us, which fulfills requirements of V2V communi-

machine learning technology.

cation. Meanwhile, it is essential to realize small footprint public key based crypto-engine for sensor nodes.
We have optimized radix of multipliers, and minimized

A Weak-Signal-Readout Integrated Circuit for

temporar y variables to realize lowest foot-print cr yp-

Terahertz-Video-Imaging

to-engine.

M. Ikeda, H. Awano, T. Kikkawa, and E. Kume
integrated circuit (ROIC) which converts a weak signal

Design of Functional Cryptographic Processor
M. Ikeda, H. Awano, T. Ichihashi, K. Koga, and C. Cai

detected by InAs MOS-HEMT to digital signal. The
ROICs which contain low noise amplifier, lock-in amplifier and ΔΣ analog-to-digital converter are integrated as

cryptography, which is capable of, for example, search-

8x7 array on 180 nm CMOS and utilized with the detec-

ing among encr ypted data or statistical processing

tors stacked on them. On the chip, digital-to-analog

without decryption along with secure communication,

converters are also implemented adjacent to the ROICs

and lattice-based cr yptography, which has gained

to calibrate the detectors. In our work, several control

increasing attention as quantum computers are emerg-

parameters and digitized signals are serially communi-

ing. One of the most important primitives for functional

cated by serial peripheral interface. As a future work,

cr yptography is a computation called pairing, whose

we will demonstrate the ROIC with stacked detectors

computational complexity prevents many schemes tofor the imaging.

the-art CPUs. We studied a wide range of sub-algorithm
and architectural possibilities and showed that withdedicated hardware a pairing can be computed under
40us. On the other hand, we are also investigating efficient hardware implementation of Paillier encryption,

29

C

be feasible, 210us for each pairing even with state-of-

3-1

e ear hWe study hardware implementation of functional

Chapter 3

For Terahertz-Video-Imaging, we designed a readout

Advanced 3-D Measurement System by Smart Image

Top-down fabrication of small-gap electrode devices

Sensors and Secure Sensing

by Fine E-Beam writing and MEMS process

M. Ikeda, H. Awano, U. Kim, V.G. Vishwa, and

Y. Mita, Y. Takeshiro, N. Washizu, A. Takada,N. Takeda

M. Fujiwara, T. Sawamura, R. Ikeno, and K. Asada

We are trying to propose new methods for 3-D mea-

Towards the goal of production of brand-new sensor

surement, with advanced functionality, and secure

devices with higher sensitivity and functionality, thesensing. In 3-D measurement, we have proposed a newteam is working on small-gap electrode fabrication pro-method and a image sensor with the capability of selec-

cess. The team takes full advantage of newly-acquired

tive light detection and background suppression, and(in 2013) rapid electron beam writer F7000S-VD02.

are fabricating and measuring a CMOS image sensor

The capability of high electron dose and sharp edge

in which polarizers are discretely arranged in specificdue to cell (character) projection machine configura-

pixels to obtain polarization information necessary fortion is used for fabrication process. The target of firstdetection of specular reflection. Towards secure sens-

year is reliable sub 100 nm gap electrode fabrication, as

ing, we are trying a unified architecture, merging thewell as microactuator-integrated nanogap system.

functions of A/D conversion and data encryption andauthentication.
University-Industry collaborative research on highly-functional system by MEMS post-process of
CMOS-VLSI

Mita Laborator y(http://www.if.t.u-tokyo.ac.jp)

Y. Mita, S. Inagaki, T. Kuriyama,
Y. Nakayama (Konica Minolta), Y. Sato (Nanox Japan)
The research targets are new sensor devices, madeby post-process at clearnrooms such as VDEC Takeda
Supercleanroom and others, of VLSI wafer madegy-autonomous distributed microsystems for reali-

through VDEC. The important finding has been thatzation of deformable matter

VLSI wafer acquired just after transistor fabrication

Y. Mita, N. Usami, G. Ulliac,

could sustain processes even with heat treatment, such

E. Lebrasseur (LIMMS, CNRS-UTokyo IIS),

as deposition, ion implantation, and drive-in. In 2016, a

J. Bourgeois, B. Piranda (FEMTO-ST, France),

VLSI device made on Silicon-on-Insulator (SOI) wafer
was successfully Deep-RIE processed. The industrial

Chapter 3

Programmable Matter - Study on LSI-MEMS ener-

S. Delalande (PSA-Peugeot)
As one example of integrated MEMS that is expectedinterest is its versatility–many different types of applica-

to open new research and industrial application fields,tion devices, which differ one from another according

the authors are trying to show a top-down application

to request of market, can be fabricated by using the

3-1of energy-autonomous distributed microrobots. A num-same technology. More and more companies are inter-ber of identical tiny robots, sized below 1 cm, will be

ested in the scheme and are working on the technology

released in an environment. Individual robot can com-on the collaborative research projects.

30

e ear hmunicate with their neighbor, can stick each other, canshare energy, to realize cooperative function. The PI
has received a French National Research Center (ANR)

LSI hot-spots active cooling system

grant on behalf of host professor of CNRS laboratory in

Y. Mita, Y. Okamoto, K. Fujimoto (Titech),the Institute of Industrial Science (LIMMS, CNRS-IIS,

H. Ryoson (Titech), and T. Oba (Titech)C

UMI 2820), together with FEMTO-ST Laboratory andA hotspot, which is referred to a high-temperature

PSA-Peugeot Laborator y for such “micro robots thatarea due to the overheating of a circuit block thatcan realize deformable substance by cooperative action,

excess passive cooling capability, is becoming a key

named Programmable Matter”．Target is set in under-

limiting factor of LSI performance. An active coolingstanding on physics and devices working in aqueous

system that tries to actively remove such local heating

environment.

by circulating liquid coolant is our research target. In
FY2016, an out-of-plane cooling scheme was confirmedto be efficient for heat removal, by test structure experiments, modeling with equations, and finite element“Zeolite-Electronics-Nanostructure (ZEN)” integrated

method simulations.

chemical sensor
A. Higo, N. Usami, Y. Okamoto,K. Yamada, (LIMMS, Mita Laboratory)

Assessment of Critical Dimension by direct Laser

W. Haibin, N. Kubo, K. Segawa,patterning

M. Sugiyama, (Next PV, CNRS-UTokyo RCAST)

Y. Mita, N. Usami, A. Higo, Y. Okamoto

Y. Mita

Direct patterning using UV Lasers has potential toElectron devices using colloidal quantum dots are

become an ultimate short Turn Around Time (TAT)

believed to open new application fields such as lightfabrication method with because it can suppress lithog-

emitting devices and or photovoltaics. Up to date, very

raphy step. To further extend its resolution down to

few research activities have been done in sensors

beyond 10 µm, assessment of systematic and random

applications; if we can realize integrated photodiodes

size variability is mandatory. We have therefore devel-that have extended sensitive wavelength as long as 1.

oped a test structure design to electrically measure

35 µm-1.4 µm wavelength, such devices can be usedand extract discrepancy between designed and realizedby many new applications such as security cameras

dimensions. Precision that can go down to 1 µm has

and / or Laser Radar (Lidar) under sunlight. The

been obtained.

aim of this research is to find an integration method
for beyond Si-LSI device. We tr y to integrate colloidal quantum dots of which absorption spectra can be“Zeolite-Electronics-Nanostructure (ZEN)” integrated

designed through molecular design. By integration,

chemical sensor

Silicon device will be able not only to capture infrared

Y. Mita, K. Yamada, Y. Okamoto,wavelength lights, which is impossible by its original

M. Denoual (ENSI de Caen, France),

characteristics, but also my include information reading

Tixier Mita Agnès, Eric Lebrasseur,and computation circuits. For the first yearʼs explorato-

Hussein Awala (ENSI de Caen, France),

ry study, partly financed by the LIMMS internal project

Julien Grand (ENSI de Caen, France),

grant, spin coating integration method has been investi-

Sveltana Mintova (ENSI de Caen, France)

gated. The enhancement of absorbance spectra at such

One of the most impor tant application field of

wavelength has been experimentally confirmed.

MEMS is sensors that can detect physical and chemFollowing a long history of the groupʼs research, theDevelopment of shock resonant spectrum (SRS)

team was appointed in 2015 as a JSPS-CNRS bilateral

sensor for cyber physical systemcooperative research project grant. The goal of theY. Mita, R Ranga Reddy, N. Usami
VDEC is awarded a Japanese JST–Indian DST joint

ing Zeolite material that is new to VLSI, and applying

grant (SICORP) for cyber physical systems research,post-process on it. Within one year, the team have suc-in cooperation with IIT Bombay campus. The team

cessfully demonstrated two types of devices: a zeolite

is participating the project through a Shock Resonant

chemical sensor by resonant frequency shift detection,

Spectrum (SRS) sensor, which has been a researchand by thermal capacity change detection according

theme of 2012-2014. A new Ph. D student from India ischemical concentration. A reliable embedding methodassigned and fabrication process was recovered. Thisof zeolite into 3D silicon MEMS trenches have beenyear we have developed microactuators included testdeveloped as well.

structure to extract static and dynamic friction coeffi-

31

C

cient of DRIE walls.

3-1

e ear hresearch is to develop a chemical sensor by integrat-

Chapter 3

ical amount that cannot be sensed by human beings.

operation. Lateral InGaAs TFETs, Ge TFET, GaAsSb/
Development of LSI post-processing for hybrid inte-

InGaAs hetero-junction, Ge/strained Si hetero-junction

grationand ZnO/(Si, Ge) TFETs have been explored. It was

Y. Mita, X. Hurtaud E. Ohta, T. Momose (Material Eng.)

found that abrupt np junctions in Ge can be formed by

To provide new capability to Nanotechnology

P diffusion and the Ge p-channel TFETs using these

Platform Users, a couple of process technologies

source junctions operates. Also, we have proposedfor LSI hybrid integration is under development. In

novel oxide semiconductor/column-VI semiconductor

FY2016, a stable gold electroplating system was pur-hetero-structure TFETs utilizing vertical tunneling. We

chased and a bump plating for LSI flip-chip bonding

have fabricated these ZnO/Si and ZnO/Ge n-channel

was developed. In parallel, a supercritical fluid depo-

TFETs and demonstrated the operation.

sition (SCFD) machine was restored to investigate
trench embedding deposition with metal. This year, wehave found a condition of SCFD over trenches covered
with silicon dioxide.

Ferroelectric gate insulator MOSFETs
S. Takagi, M. Takenaka, Kimihiko Kato, Kiyoshi Endo,
Ichitaro Fukui, Masashi Yamaguchi
We have conducted the research for MOSFETs
using ferroelectric gate insulators. We have confirmed

Takagi-Takenaka Laborator y(http://www.mosfet.k.u-tokyo.ac.jp/)

ferroelectricity of ALD HfZrO2 films on Si and theoperation of MOSFETs with these gate insulators. On
the other hand, the physical origin of the ferroelectric
hysteresis and reduction in S factors of MOSFETs with

III-V/Ge Metal-Oxide-Semiconductor (MOS) FETs and

ALD La2O3 is found to be attributed mainly to drift ofthe 3 dimensional integration

any ions in the La2O3 gate insulators.

S. Takagi, M. Takenaka, WuKang Kim, Ke Mengan,
Kwangwon Jo, Cheol-Min Lim, Tsung-En Lee,
Sanghee Yoon, Chiaki Yokoyama, Zilong Wang,
Kei Sumita
We have conducted the research on high-per formance III-V/Ge MOSFETs and the 3 dimensional

Si CMOS photonics
M. Takenaka, S. Takagi, Frederic Boeuf, Qiang Li,
Ziqiang Zhao, Takumi Fujigaki, Dongheng Lyu,
Yoshitaka Taguchi

stacked CMOS structures by using these high mobility

We have conducted the research for MOS-based Si

Chapter 3

MOSFETs. For reliability of InGaAs MOS inter fac-

optical modulators. We have successfully demonstrat-

es, we have found that amounts of interface states at

ed that the III-V/Si hybrid MOS optical modulator

InGaAs MOS interfaces generated by electrical stressexhibits 10 times smaller modulation loss than Si MOS

have correlation with substrate hole currents of InGaAs

modulator. As a result, we have revealed that the III-V/

3-1

n-MOSFETs, suggesting a hole-triggered mechanism

Si hybrid MOS optical modulator is suitable for high-of interface states. For Ge MOSFETs, we have foundspeed optical interconnect beyond 50 Gbps. Moreover,that thinning SiGe layers in SiGe/SOI substrates used

we have demonstrated an optical switch based on thefor Ge condensation significantly increases compres-

III-V/Si hybrid MOS optical phase shifter, suitable forsive strain in Ge-on-Insulator structures, leading to theoptical deep learning using an universal photonic inte-

realization of SiGe-OI pMOSFETs with high hole mobil-

grated circuit. We have also conducted the research ofity.

the mid-infrared photonic integrated circuits based on

32

e ear hGe-on-Insulator (GeOI) wafer fabricated by wafer bonding. We have successfully demonstrated a suspendedC

Tunnel FET
S. Takagi, M. Takenaka, Huang Po-Chin,
Kimihiko Kato, Takahiro Gotow, Taeeon Bae,
Daehwan Ahn, Ryotaro Takaguchi
We have investigated tunnel FETs (TFETs) which
can exhibit steep subthreshold slope for low-power

Ge waveguide for the first time by removing a SiO2 buried oxide underneath the Ge waveguide.

III-V CMOS photonics
M. Takenaka, S. Takagi, Naoki, Sekine,
Pengyuan Cheng, Takaaki Sanjoh
We have investigated the III-V CMOS photonics
platform by using III-V on insulator wafer. On the IIIV-OI wafer, III-V MOSFETs and III-V photonics can bemonolithically integrated. We have numerically analyzed the InGaAsP depletion optical modulator which
exhibits superior modulation characteristics to Si optical modulator. To improve the heat dissipation of IIIV-OI platform, we have proposed the III-V on SiC platform. By making III-V on SiC wafer by wafer bonding,the heat dissipation was significantly improved.

2D material devices
M. Takenaka, S. Takagi, Yuki Yamaguchi,
Masashi Yamashita, Hanzhi Tang
We have investigated 2D materials such as grapheneand MoS2 for semiconductor devices. We have numerically analyzed graphene optical phase modulator. It
was found that pure optical phase modulation can beobtained by suing mid-infrared wavelength.

Chapter 33-1
33

e ear hC

VLSI Design and Education Center, The University of Tokyo
Annual Report
October, 2018
Published by
VLSI Design and Education Center, The University of Tokyo
Director Masahiro Fujita
Address: Yayoi 2-11-16, Bunkyo-ku, Tokyo, 113-8656, Japan
Printed in
Sanbi Printing Co., Ltd.
Address: Nishinippori 5-9-8, Arakawa-ku, Tokyo, 116-0013, Japan

Copyright © by VLSI Design and Education Center, The University of Tokyo平成30年度
VLSI Design and Education Center The University of Tokyo 2018東京大学
大規模集積システム設計教育研究センター
年報

2018
VLSI Design and Education Center,
The University of Tokyo
Annual Report

VLSI Design and Education Center The University of Tokyo 2018

VDEC年報2018_H1_4E.indd 4-1

2018/09/19 9:26