平成28年度

東京大学
大規模集積システム設計教育研究センター

年 報

VLSI Design and Education Center The University of Tokyo 2016

2016
VLSI Design and Education Center,
The University of Tokyo
Annual Report

VLSI Design and Education Center The University of Tokyo 2016

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VLSI Design and Education Center
The University of Tokyo

This is the 2015 Annual Report of VDEC（VLSI Design and Education Center, University of Tokyo）.
In 2015 LSI chip design/implementation and processing of nano-fabrication facilities went well as previous years.
This year, however, was the ﬁnal year of the 6-year-plan of our University, so that a lot of time was spent on discussions
about the next 6-year-plan. Our University decided to introduce the key process indicator (KPI) for the assessment ofactivities in Divisions. VDEC also decided a policy to deﬁne our KPIs. The basis of VDEC activities is LSI chip design/
implementation and processing of nano-fabrication facilities, Our KPIs are numbers of new LSI chips and nanofabrications. The former is now stable and the latter is still increasing. VDEC has also set new targets to be promoted
in future, namely the internationalization and the industrialization, to which VDEC has been proceeding for several
years.
Though instability of budget, due to KPI ﬂuctuation, is not favorable for the stable inter-university collaborative
projects, the major portion of the VDEC budget has been guaranteed as a stable budget thanks to understanding of
the President of our University. However, the gradual reduction of the budget of 1-2% per year will continue for the
next 6 years. Following intensive discussions at the VDEC Nationwide Advisory Board, VDEC decided to introduce
a supplementary charge system from 2016. Each CAD user/laboratory will be requested to contribute 50k – 100k
yen/year depending on the number of licenses, though CAD use for education purposes will be free of charge as it
was. VDEC would like to ask for usersʼ understanding. It is unavoidable in order to keep a stable VDEC CAD license
system for future.
The CAD licenses of VDEC are restricted for the purpose of education and research in academia. These cannot be
used for designs targeting industrial/commercial purpose. Because of the stagnant status of Japanese semiconductor
industry, however, such cases are increasing as the national projects, where academia are requested to more actively
contribute the information society in terms of IoT and AI, exceeding the restriction of the CAD licenses of VDEC.
International collaborative researches with developing countries would be often in the same situation. The developing
countries are aiming at industrialization of LSI designs. VDEC is recognizing the need of the new CAD environment
bridging between academia and industry. VDEC is trying to realize it step by step, so that students/researchers
trained by VDEC system can bring their design ability into full play.
As the annual event of the D2T (Design-to-Test) research division, donated by Advantest Corporation, the 10th
symposium was successfully held on August 21st 2015, inviting distinguished lecturers from oversea and domestic
institutes. We are scheduling the 11th symposium in September 21st this year, too. We would like to express our
sincere thanks to invited lecturers, audiences and Advantest Corporation for the continuous support.
We will continue to do our best efforts for the original mission of VDEC, “promotion of education and research in
LSI design by means of practical chip-design and implementations”, in order to realize research and education forenhancing the value of the semiconductor technology. We thank you for your continuous supports again.
May 2016

VLSI Design and Education Center, University of Tokyo
Director Kunihiro Asada

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VLSI Design and Education Center, The University of Tokyo
Annual Report 2016

C O N T E N T S

Message from Director of VDEC
Chapter 1

2

Activity Report of VDEC 
1.1

Introduction of VDEC activities and activity report of FY2015

1.2

VDEC CAD Tools

   2

   5

1.3

VLSI Chip Fabrication

1.4

Seminar

   10
   14

   7

1.5

Facilities

1.6

Activity plan for 2016

1.7

Venture Companies Related to VDEC

   16
   17

1.8 “Nanotechnology Platform”    18       Ultra Small Lithography and Nanometric       Observation site

Chapter 2	Activity Report of19“ADVANTGEST D2T Research Division” 

Chapter 3

VDEC2016_巻頭_目次E.indd 1

2.1

Introduction of “ADVANTGEST D2T Research Division”

2.2

Report of “10th D2T Symposium”

2.3

Research Activity Reports of “Advantest D2T Research Division”

2.4

Publications

   19

   20
   22

   23

Research in VDEC 

24

2016/12/07 17:09

Chapter 1 Activity Report of VDEC
1. 1  Introduction of VDEC activities andactivity report of FY2015

VLSI Design and Education Center(VDEC), University

year. We hold the seminar in VDEC and provide distanceof Tokyo was established in May 1996. VDEC has beenlearning through video streaming. We expect spread ofoperating for the following 3 major roles: “spreading

the up-to-date LSI design methodology by using CAD

the latest information on VLSI design and education,”tools.

Chapter 1“providing licenses of CAD tools,” and “suppor ting

1-1

The missions of VDEC are for advancement ofyear. This year we hold 3 courses, “Analog design course”

researches and education on LSI design in public andand “RF design course”，and initiated “MEMS designprivate universities and colleges in Japan and send many

course” in May-July time frame. We invite experienced

distinguished VLSI designers into industry. After 19 years

professors among universities as lecturers for the courses

of VDEC establishment, educations on CAD software,

to conduct LSI design education courses with practical

LSI design and design flow in universities have been wellexperience. We also hold “T ransistor level design

established. On the other hand, advancement on nano-flow in VDEC” and “Digital design flow in VDEC EDA

meter CMOS technologies forces design flow and CAD

environment” for designers in universities. We started tosoftware complicated. We have been continuing CAD tool

charge these two LSI design education courses, as well as

seminar by the lecturers from EDA vendors for twice a

VDEC Refresh Seminars.

2

We assume our LSI design flow seminars as educations

on VLSI chip fabrications for academic use.” Theon basic LSI design concepts and practical experience of

VDEC activity report of FY 2015 is described hereafter

LSI design with CAD tool chain. VDEC holds “LSI design

according to Fig. 1. 1.

education seminar”，a.k.a. VDEC Refresh Seminar, once a

Activity Report of VDEC

Fig. 1. 1

VDEC2016_E.indb 2

VDEC activities

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In addition to the above seminars, we hold “VDEC

and experienced designers within a couple of hours to a

DesignerʼForum” among young professors and students

couple of days. Moreover, emails are accumulated and are

annually. This is a workshop that the par ticipants

open to the VDEC users, as shown in Fig. 1. 2, who haveexchange their design examples with not only successregistered VDEC accounts, as the important educational

stories but also their failure stories, in addition to invitedassets. We expect all the VDEC users to make the full use

talks. We expect students and professors who will startof this mechanism to help solve problems.

designs to learn kinds of know-hows. We have initiated

We continue chip fabrication services on FDSOI CMOS

“IEEE SSCS Japan Chapter VDEC Design Award” this

28 nm by ST Microelectronics, 0.18 μm CMOS by Rohm

year, and final examination and awarding have carriedand 0.8 μm CMOS by On-semi Sanyo Semiconductor.

out during the “VDEC DesignerʼForum”．Mr. T. Ozaki

And started chip fabrication ser vices on SOTB CMOS

(Kobe Univ.) is awarded as “IEEE SSCS Japan Chapter

65 nm by Renesas Electronics.
Our donated division “Design To Test(D2T)”，which

Institute of Science and Technology (NAIST)), Mr. K.

was founded by donation from Advantest in Oct. 2008,

Nakata (Tokyo Institute of Techology (TITECH)), Mr. K.

focuses on enrichment of education on LSI testing and

Kaiwa (Yamagata Univ.) are awarded as “the best VDEC

bridging between design and testing.
Fig. 1. 4 shows trends of number of papers throughMatsuzuka (Kobe Univ.), Mr. T. Kawajiri (Keio Univ.) are

VDEC activities. Number of papers is increasing, which

awarded as the “VDEC Design Award.”means researches in the field of VLSI design have been

LSI designers come up against various dif ficulties

encouraged after VDEC establishment.

during actual LSI design scene, even after the basic

Fig. 1. 5 shows number of papers related to CAD usage,

educations through various seminars and the forum. One

chip fabrications and VDEC facility usages. CAD tools areof the biggest problems for beginners is the setup of CAD

widely used to write papers. CAD tools are used not only

softwares. Many of them also get confused by “Esotericchip designs themselves but also used for preparation of

messages” come out from CAD softwares, even after they

chip fabrication and they contribute to verify fundamental

successfully setup CAD tools. In such situations, VDEC

ideas of researches. Advanced CMOS processes aremailing-lists make significant contributions. VDEC users

preferred for publications, and not only papers withcan register to VDEC mailing-lists on CAD tools, and65 nm/40 nm CMOS chips, but also with 32 nm CMOS,

process dependent groups through VDEC web pages,

22 nmCMOS and 14 nmCMOS are emerging in the world.

and can ask questions and helps on their facing issues. It

We would like to prepare chip fabrication services for theis not a responsibility for the registrant of such mailing-

advanced CMOS processes. In addition, we would like tolists to give answers to questions, however, in most cases,

setup chip fabrication services related to CMOS/MEMS

replies are given by the experienced users of CAD tools

to fulfill the researches for “More than Moore”．We also

Fig. 1. 2

VDEC2016_E.indb 3

1-1
3

Activity Report of VDEC

Design Award”，and Mr. H. Okuhara (Keio Univ.), Mr. R.

Chapter 1

VDEC Design Award” winner, and Mr. H. Hayami (NaraArchives of emails of VDEC mailing-list.

2016/12/07 17:09

encourage researchers to fully use of VDEC facilities

wide spread of research purposes.

such like LSI testers, FIB systems and EB writer for the

Chapter 1

1-1
4

Activity Report of VDEC

Fig. 1. 3

Trends of number of papers through VDEC activities.

Fig. 1. 4

VDEC2016_E.indb 4

Number of papers related to VDEC facilities.

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1. 2  VDEC CAD Tools
Since 1996, VDEC has provided CAD software licenses

and colleges.

to the registered researchers in universities and colleges
When one is going to use VDEC CAD tools and chipin Table 1. 2. 1. The researchers can use those CAD

fabrication service (the details are described in Section

tools when their local machines, whose IP addresses are

1-3), some faculty member of his/her research group inregistered in advance, are authorized by one of VDEC

a university or a collage needs to do user registration.

license server located in the ten VDEC subcenters shown

Figure 1. 2. 2 shows (a) the number of registrants, (b)in Figure 1. 2. 1. For each CAD tool, VDEC provides

the number of distinguished universities/colleges of the

10-100 floating licenses. Those CAD tools can be utilized

registrants, and (c) the number of registrants who applied

only for research and education activities in national

VDEC CAD tools.

universities, other public universities, private universities,

1-2

Table 1. 2. 1 VDEC CAD tools
Function

VendorCadence tool set

Verilog-HDL/VHDL entry, Simlation, Logic synthesis, Test

Cadence Design Systems, Inc.

pattern generation, Cell-based (including macros) place,route, and back-annotation, Interactive schematic andlayout editor, Analog circuit simulation, Logic verification,
Circuit extraction
Verilog-HDL/VHDK simulation, Logic synthesis, Test pattern

Synopsys, Inc.

generation, Cell-based (including macros) place, route, andback-annotation, Circuit simulation, Device simulation
Mentor tool set

Layout verification, Design rule check

Mentor Graphics Co. Ltd.

Silvaco tool set

Fast circuit simulation

SilvacoADS/Golden Gate

Design and verification of high-frequency circuits

Keysight Technologies

Bach system

BachC-based design, synthesis, and verification

Sharp

LAVIS

Layout visualization platform

TOOL

VDEC2016_E.indb 5

5

Activity Report of VDEC

Name

Synopsys tool set

Chapter 1

in Japan. The CAD tools we p-rovided in 2016 are shown

2016/12/07 17:09

Chapter 1

1-2

Fig. 1. 2. 1 VDEC Subcenters

6

Activity Report of VDEC(a) The number of registrants(c) The number of research group applied CAD tools(b) The number of universities colleges of the registrants(d) The number of applied licenses of all CAD tools

Fig. 1. 2. 2 The numbers of VDEC CAD Applications

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1. 3  VLSI Chip Fabrication
1. 3. 1 Trends of VLSI Chip
Fabrication Services
Fig. 1. 3. 1 shows a trend of number of designed chips

the number of designed chips shows steady increase,which means drastic improve of the ef fectivenessresearches and education of LSI design, and we assume
drastic increase of number of students related to LSI chip

for VDEC chip fabrication services, including pilot projectprior to VDEC establishment.
VLSI chip fabrication is limited to 0.5 μm CMOS
provided by NTT Electronics during the pilot project

Chapter 1

in 1994 and 1995. VDEC chip fabrication had started in
1996 with 1.2 μm CMOS provided by Motorola Japan,
which is now On-Semiconductor as well as the 0.5 μm
CMOS. In 1997, VDEC received cooperation from Rohm
and has started 0.6 μm CMOS process. In 1998, VDEC

1-3

started chip fabrication ser vices of 0.35 μm CMOS by

7

Activity Report of VDEC

Hitachi, and in 1999, VDEC started 0.35 μm CMOS by
Rohm. We had a test chip fabrication of 0.13 μm CMOS
by STARC through “IP development project” in 2001. We
added 0.18 μm CMOS by Hitachi into our chip fabrication(a) Trend of number of designs fabricated.

menu in 2001. From 2002, we started VDEC-MOSIS chip
fabrication program initiated by Prof. Iwata of Hiroshima
University. Under this program, VDEC member canaccess to TSMC and IBM processes with lower price. We
also started Bipolar chip fabrication by NEC Compound
Semiconductor Devices. In 2004, we star ted 0.15 μm
SOI-CMOS chip fabrication by Oki Electric as test chip
fabrications. In the same year we started 90 nm CMOS
chip fabrication by ASPLA/STARC. In 2006, we started
0.18 μm CMOS by Rohm and 0.25 μm SiGeBiCMOS
by Hitachi. In 2008, we started 65 nm CMOS process by
eShuttle, after closure of 90 nm CMOS chip fabricationin 2007. In 2010, we star ted 40 nm CMOS process(b) Trend of designed area.

by Renesas Electronics through “Next Generation
Semiconductor Circuits & Architecture” project between
METI and STAR. On the other hand, 1.2 μm CMOS
chip fabrication program came to end by the September
2011. 40 nm CMOS by Renesas Electronics and 65 nm
by eShuttle also come to end by Oct. 2012 and Aug. 2013,
respectively. We started CMOS 0.8 μm in Oct. 2012 by
On-semiconductor-Sanyo as a test chip fabrication andopened it as the regular chip fabrication menu in 2012.
We started FD-SOI 28 nm CMOS by ST-Microelectronics
through CMP, France, as the advanced CMOS process
in 2013. We star ted SOTB 65 nm CMOS by Renesas
Electronics in 2015.

(c) Trend of designed area normalized by design rule.

Fig. 1. 3. 1(a) shows trends of number of chip designed
for VDEC chip fabrication. For the first 6 years until 2001,

VDEC2016_E.indb 7

Fig. 1. 3. 1 Trend of number of designs and designed chip area.

2016/12/07 17:09

design and education. During few years of stable number
around 400 chip designs per year, we can see transitionof designs toward finer process. In 2007, we saw a large
drop, which was caused by sudden process transition
from 0.35 μm CMOS to 0.18 μm CMOS, and in 2008, we
also saw another drop by process transition from 90 nm
CMOS to 65 nm CMOS.
Fig. 1. 3. 1(b) shows trends of designed chip area,
which shows much clear trends of drop by process
migration. On the other hand, Fig. 1. 3. 1(c) shows
trends of designed chip area normalized by design rule,

Chapter 1

which assume to be strong relation with design efforts.

1-3

effort per chip and per unit area due to process scaling.

8

Coming from the fact that the normalized chip area isstill growing, we assume the major reason for decrease of

Fig. 1. 3. 2 Trend of number of processors and universities
fabricated chip.

number of chips and designed area is increase of design
Fig. 1. 3. 2 shows trends number of professors andActivity Report of VDEC

universities fabricated chip. Number of professors who
have contracted NDA for process technologies to access1. 3. 2 Overview of chip fabricationin 2015

design rules and design libraries are, 64, 274, and 36,

Table 1. 3. 1 lists chip fabrication schedule in 2015.

respectively, for 65 nm CMOS, 0.18 μm CMOS, andPlease refer to list in Chapter 2 for details of designers

0.8 um CMOS.

and contents of chip designed.

Table 1. 3. 1 Chip fabrication schedule in 2015
○ 0.8 μm CMOS (On-Semiconductor - Sanyo)
Chip application deadline

Design deadline

Chip delivery

2015 #1

2015/ 7/ 6

2015/ 9/28

2015/12/13

2015 #2

2015/12/29

2016/ 3/22

2016/ 6/24

Chip application deadline

Design deadline

Chip delivery

2015 #5

2014/11/ 3

2015/ 1/26

2015/ 5/21

2015 #2

2015/ 4/13

2015/ 7/ 6

2015/10/21

2015 #3

2015/ 6/ 1

2015/ 8/24

2015/12/ 4

2015 #4

2015/ 8/24

2015/11/16

2016/ 2/26

2015 #5

2015/11/ 2

2016/ 1/25

2016/ 6/22

Design deadline

Chip delivery

2015 Nov.

2015/10/E

2016/ 6/17

2016 March

2016/ 3/B

2016/ 9○ 0.18 μm CMOS (Rohm)○ 28 nm CMOS (STMicro/CMP)
Chip application deadline

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1. 3. 3 Libraries and design flows

and design flows for digital design and PDKs for analog
design. Table 1. 3. 2 lists libraries available now.

VDEC have been working to prepare design libraries
Table 1. 3. 2 Libraries available for VDEC chip fabrication
Technology

Name

AuthorContents

0.18μm CMOS
(Rohm)

Rohm
library

Rohm Library
Std. Cells, IO cells, RAM(Distributed with CDROM)

Synthesis(Synopsys)
Simulation(VerilogXL)
P&R(LEF/DEF)

Onodera Lab., Kyoto University

Synthesis(Synopsys)
Simulation(VerilogXL)
P&R(Astro)

Todai
Library

VDEC
Design flow based on library prepared by
Onodera Lab., Kyoto University

Synthesis(RTL Compiler)
Simulation(VerilogXL)
P&R(Encounter)

VDEC2016_E.indb 9VDEC

PDK(IC6.1)

1-3
9

Activity Report of VDEC

PDK

Chapter 1

Kyodai
Library

2016/12/07 17:09

1. 4  Seminar
Seminar is indispensable for the improvement of LSI

VDEC teachers gave lecturers on transistor level circuitdesign technology. Some seminar and forums, such as

design course, and digital circuit design course under thetechnical seminar for CAD use, refreshing seminar for

VDEC EDA environment. Teachers and students up to 40

working people, designerʼs forums for young professors

people attended a lecture in each course, and master theand students were held in 2011.

use of each tool for VLSI design flow that uses the VDEC

【Technological seminar for CAD use】

library. Moreover, another technical seminar for CAD use

In a technological seminar for CAD use, VDEC

Cadence 3 kind and 5 days, Synopsys 4 kinds and 4 days

Chapter 1

invites lecturer from each tool vender, such as Cadence,(Table 1. 4. 1). The demand for these CAD technological

Synopsys and Agilent, to hold the CAD operation course.

seminars is ver y large, and VDEC has maintained theMoreover, the course concerning the design flow inmechanism of a large-scale CAD technological seminar

the VDEC environment was held by the VDEC staff. A

holding cor responding to this situation. So far, the

1-4

technological seminar for CAD use for the beginner wasseminar was held at the University of Tokyo OR other

held in The University of Tokyo VDEC in August and

VDEC branch, however, we star ted to distribute theSeptember at the year 2015. This seminar took 4 days for

lecture using Web streaming, so that students around2 kinds of Cadence tools, 4 days for 3 kinds of Synopsys

VDEC branch can take the seminar at the branch school.

10

for matured teachers and students was held in March by

Activity Report of VDEC

tools, 1 days for 1 kind of Keysight tool. In addition,
Table 1. 4. 1 CAD technological seminar in summer of the year 20132015/07/27

Cadence ADE Seminar

Univ. of Tokyo13

2015/07/27

Cadence ADE Seminar

Hokkaido Univ.

5

2015/07/27

Cadence ADE Seminar

Tohoku Univ.

4

2015/07/27

Cadence ADE Seminar

Kanazawa Univ.

1

2015/07/27

Cadence ADE Seminar

Nagoya Univ.

7

2015/07/27

Cadence ADE Seminar

Nagasaki Univ.

5

2015/07/29-31

Cadence Virtuoso Seminar

Univ. of Tokyo21

2015/07/29-32

Cadence Virtuoso Seminar

Hokkaido Univ.

5

2015/07/29-33

Cadence Virtuoso Seminar

Tohoku Univ.

3

2015/07/29-34

Cadence Virtuoso Seminar

Kanazawa Univ.

1

2015/07/29-35

Cadence Virtuoso Seminar

Nagoya Univ.

3

2015/07/29-36

Cadence Virtuoso Seminar

Kyoto Univ.

4

2015/07/29-37

Cadence Virtuoso Seminar

Hiroshima Univ.

2

2015/07/29-38

Cadence Virtuoso Seminar

Nagasaki Univ.

5

2015/09/09

Synopsys DesignCompiler+PowerCompiler Seminar

Univ. of Tokyo15

2015/09/09

Synopsys DesignCompiler+PowerCompiler Seminar

Tohoku Univ.

4

2015/09/09

Synopsys DesignCompiler+PowerCompiler Seminar

Osaka Univ.

5

2015/09/09

Synopsys DesignCompiler+PowerCompiler Seminar

Hiroshima Univ.

4

2015/09/11

Keysight GoldenGate Seminar

Univ. of Tokyo10

2015/09/11

Keysight GoldenGate Seminar

Tohoku Univ.

1

2015/09/14

Synopsys VCS-AMS Seminar

Univ. of Tokyo

13

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Synopsys VCS-AMS Seminar

Hokkaido Univ.

1

2015/09/14

Synopsys VCS-AMS Seminar

Tohoku Univ.

6

2015/09/14

Synopsys VCS-AMS Seminar

Osaka Univ.

7

2015/09/17-18

Synopsys IC Compiler+Milkyway Seminar

Univ. of Tokyo28

2015/09/17-20

Synopsys IC Compiler+Milkyway Seminar

Tohoku Univ.

4

2015/09/17-23

Synopsys IC Compiler+Milkyway Seminar

Osaka Univ.

6

2016/03/09

Synopsys StarRCXT Seminar

Univ. of Tokyo11

2016/03/09

Synopsys StarRCXT Seminar

Hokkaido Univ.

5

2016/03/09

Synopsys StarRCXT Seminar

Tohoku Univ.

3

2016/03/09

Synopsys StarRCXT Seminar

Kyoto Univ.

2

2016/03/09

Synopsys StarRCXT Seminar

Hiroshima Univ.

1

2016/03/10

Synopsys Tetra Max Seminar

Univ. of Tokyo8

1-4

2016/03/10

Synopsys Tetra Max Seminar

Kyoto Univ.

211

2016/03/10

Synopsys Tetra Max Seminar

Hiroshima Univ.

2

2016/03/11

Synopsys Milkyway Seminar

Univ. of Tokyo10

2016/03/11

Synopsys Milkyway Seminar

Tohoku Univ.

1

2016/03/11

Synopsys Milkyway Seminar

Kyoto Univ.

2

2016/03/11

Synopsys Milkyway Seminar

Osaka Univ.

3

2016/03/11

Synopsys Milkyway Seminar

Hiroshima Univ.

1

2016/03/23

Synopsys Prime Time Seminar

Univ. of Tokyo4

2016/03/23

Synopsys Prime Time Seminar

Hokkaido Univ.

2

2016/03/23

Synopsys Prime Time Seminar

Tohoku Univ.

1

2016/03/23

Synopsys Prime Time Seminar

Kyoto Univ.

2

2016/03/23

Synopsys Prime Time Seminar

Hiroshima Univ.

2

2016/03/24

Cadence Verilog-A Seminar

Univ. of Tokyo14

2016/03/24

Cadence Verilog-A Seminar

Tohoku Univ.

6

2016/03/24

Cadence Verilog-A Seminar

Osaka Univ.

7

2016/03/24

Cadence Verilog-A Seminar

Hiroshima Univ.

3

2016/03/24

Cadence Verilog-A Seminar

Miyazaki Univ.

2

2016/03/28

Cadence Stratus Seminar

Univ. of Tokyo11

2016/03/28

Cadence Stratus Seminar

Hokkaido Univ.

3

2016/03/28

Cadence Stratus Seminar

Tohoku Univ.

1

2016/03/28

Cadence Stratus Seminar

Kyoto Univ.

4

2016/03/28

Cadence Stratus Seminar

Hiroshima Univ.

6

2016/03/15-16

Cadence Skill Language Programming Seminar

Univ. of Tokyo18

2016/03/15-17

Cadence Skill Language Programming Seminar

Hokkaido Univ.

1

2016/03/15-18

Cadence Skill Language Programming Seminar

Osaka Univ.

5

Activity Report of VDEC

VDEC2016_E.indb 11

Chapter 1

2015/09/14

2016/12/07 17:09

【Refresh Seminar for Working People】

from many societies.
Course A: analog integrated circuit design (6/22

Teachers of universities and designers in the first line-24), Course M1: MEMS design (6/9-10), Courseof the enterprise were invited to the lecturer at "VLSI

M2:MEMS fabrication (6/29-7/1), and Course R: RF

design refresh seminar" was held aiming at the latest,

circuit design (5/21-22). Teachers from industr y andadvanced knowledge and technical learning concerning

universities involved in the integrated circuit research

VLSI design as a refreshing education for working people

and the education were invited as the lecturer, and they

involved in the integrated circuit industry (Table 1. 4. 2).

introduced a state-of-the-ar t VLSI design technology

Though this seminar started chiefly in year 1998 underincluding the practice using a lecture concerning VLSI

the support of Ministry of Education Technical Education

design and the latest CAD tool. The participants for theDivision to give practicing education of the latest VLSI

course A, M1, M2, R were 15, 12, 8, 13, respectively.

Chapter 1

design technology, it continues under many suppor ts

1-4
12

Activity Report of VDEC
Fig. 1. 4. 1 Refresh Seminar at VDEC seminar room at the University of Tokyo, VDEC.

Table 1. 4. 2 Refresh Seminar
Course A: Analog Circuit Design (3 days)
Analog Circuit Design and simulation
Integrated Circuits Verification (LVS, DRC)
Masahiro Sugimoto (Chuo Univ.), Hidetoshi Onodera(Kyoto Univ.), Koji Kotani (Tohoku Univ.)

Course M1: MEMS Design (2 days)
MEMS Basic 1: Fabrication Process
MEMS Basic 2: Operation Principle
Structual Design
Layout Design
Yoshio Mita (Univ. of Tokyo)

Course M2: MEMS Fabrication (3 days)
CAD Design and Analysis
Lithography, Etching, Release
Vibration measurement and analysis
Yoshio Mita (Univ. of Tokyo)

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Course R: CMOS-RF Circuit Design (3days)
Modulation/Demodulation, Cascaded connection
Basic Performace, Tranceiver Architecture
Circuit Element, Design Flow
Hiroyuki Ito (Tokyo Institute of Technology)【Designerʼs forum for young teachersand students】

for example, the failure case and the solution in which

VDEC LSI designer for um intended for students

the laboratory, and so on. This year, we had the meetingand young teachers has been held. The VDEC LSI

in Yamashiro Hot Spring, in August. No less than 48

designer forum has aimed to sharing information thatparticipants were flourishing at the gathering.

LSI designer has a hard time, the inside stor y of CAD
industry, the construction method in the design milieu inTable 1. 4. 3 Program of Designers Forum in 20158/28 (Fri)

Chapter 1

cannot be obtained at a society and a academic society,1-4
13

10:30-11:00

Reception

11:00-12:00

Prenary Talk
Hiroki Morimura (NTT)Role and Expectation for LSI Technologies in IoT Ara.

12:00-13:00

lunch

13:00-15:00

Ph.D session
Strongest Laboratories that I Think

14:30-15:20

VDEC Design Award Finalist Presentation

Activity Report of VDEC

Time

break
18:00-20:00

VDEC Design Award award ceremony

8/29 (Sat)Time

VDEC2016_E.indb 13

10:00-12:00

VDEC Design Award Idea Contest Presentation

12:00-12:30

VDEC Design Award Idea Contest award ceremony

2016/12/07 17:09

1. 5  Facilities
universities in Japan from its establishment (1996). Big

1406 times. The reason of decrease of number since last

facilities refer to those which are impossible to acquire

year (439 times less from 1845 in 2014) was unexpected

and or maintain by an individual research unit. Table

trouble of vacuum pump controller that was no more

1.5.1 shows the available facilities of VLSI testers andavailable in a market. However exposure count of thesome process machines, which are placed at the tester

new apparatus (F7000S-VD02) was increased up to 709

room and the super clean room of the Takeda building.

times, that is +509 increase from last year (201 exposures

In 2004, the VLSI tester (T2000) and the EB lithography

in 2014). Total exposure number of EB machines havetherefore increased from 2074 (2014) to 2115.

machine (F5112+VD01) were donated to the VDEC by
the ADVANTEST. In the year 2012, VDEC joined MEXT

The facilities can be used by user himself, after a(Ministr y of Education)ʼs Nanotechnology platform tocouple of timesʼtraining by attendance of licensed users;

enforce its multi-use capability. (For Nanotechnology

also, by presence of licensed persons, a new user can

1-5

Platform refer section 1.8). From April 2015 to Marchreadily use the machine.

14

Table1. 5. 1

Activity Report of VDEC

2016, the EB lithography machine F5112 has been used

Chapter 1

The VDEC has provided the big facilities for

Facility

Equipment name

Description

StatusContact

Logic LSI test
SystemEB tester:
IDS10000

The chip surface voltage during operation
can be measured with the LST tester.
The digital circuit with 384 pins, 1GHz canbe tested.

Available

nanotech@sogo.t.u-tokyo.ac.jp

LSI tester:
ADVANTEST T2000

The digital circuit with 256 pins, 512MHz
can be tested. Analog test is optional.

Available

nanotech@sogo.t.u-tokyo.ac.jp

Auto prober:PM-90-A

Automated prober for testing LSI wafers,
which can be used with the LSI testers.
The probe card for LSIs with the VDEC
standard pin connections is available.

Available

nanotech@sogo.t.u-tokyo.ac.jp

Analog/RF measurement
system:
HP4156B, HP4284, etc

DC parameter measurement, Capacitancemeasurement, Network analyzer,
Spectrum analyzer, etc.

Available

nanotech@sogo.t.u-tokyo.ac.jp

Low-noize manual prober:Cascade Microtec

6 inch wafer can be measured with six DC
probles and two RF probes upto 50 GHz.

Low-noize, temperature
controlled semi-auto prober: Süss Microtec

8inch wafer can be measured. The chiptemperature range is -50 to 200 °C.

Mask lithography, Direct
lithography: F5112+VD01

Minimum linewidth: 50nm.
Lithography for 5 inch photomask (thickness: 2.3 mm), 2-8 inch wafers, and chips
is possible.

Available

nanotech@sogo.
t.u-tokyo.ac.jp

Rapid Mask and Direct
lithography: F7000S-VD02

Minimum linewidth: 1xnm.
Lithography for 5 inch photomask (thickness: 2.3 mm), 2-8 inch wafers, and chips
is possible. Stencil character projection of
non-square shapes such as circle, triangle
is possible.

Available

Available facility list

Analog/RF
measurement
systemNanotechnology
Platform
Apparatuses

VDEC2016_E.indb 14

2016/12/07 17:09

Available

Silicon DRIE MUC-21
ASE-Pegasus

High speed, high aspect ratio etching ofsilicon is possible

Available

FIB systemFIB:
SII XVision200TB

Repairment of photomask, sample etching, etc. (Through Nanotech. Platformand LCNet)

Available

Chip Bonding
SystemWedge Bonder: Westbond
7476D

25 µm φ Al or Au wire wedge bonding
machine.

Available

Epoxy Die Bonder
Westbond7200C

Precision Manupilator system. Epoxy andor Ag paste chip bonding and or glued wiring.

Semi-Auto Bonder
Westbond4700E

18～25 µm φ Au Ball bonding or bumpcreation.

Precision Manual FlipChip Bonder Finetech
Fineplacer Lambda

Face-to-face bonding up to 15mm squarechips. Alignment is through video camera. Bonding is by heating chips with TV
camera. (Ultrasonic Unit can additionally be purchased.) XY ± 0.5 µm, and θ=1mrad precision.

VDEC2016_E.indb 15

1-5
15

Activity Report of VDEC

High density plasma etching with Cl and
BCl is possible.

Chapter 1

Chlorine ICP plasma etcher CE-S

2016/12/07 17:09

1. 6  Activity plan for 2015
VDEC will continue activities on chip fabrication

Mentor tools as the main stream design tools. We will

ser vices, CAD tool support, dispatching design related

continue analog RF design environment, GoldenGate andinformation and donated division “D2T”，as has been

ADS by Agilent, C-based design environment, BachC

previous years.

by Sharp. In addition, we continue trial of several CAD【Design related information
dispatching/Seminar】

tools, such as layout platform, Lavis by TOOL. Design

We will continue holding the following seminars:

debugging platform from SpringSoft has merged into
Cadence tools and will be continued. Smar tSpice by
Silvaco, will be also continued.

Chapter 1(1) CAD tools seminars which have been continued“DesignerʼFor um” since 1997. We will also continue

We will continue chip fabrication ser vices for SOTB

seminars for LSI tester usage at VDEC and sub-centers,

65 nm CMOS by Renesas Electronics, 0.18 μm CMOS

1-6

workshops on LSI testing technologies initiated by D2T.

by Rohm, FD-SOI 28 nm CMOS by ST Microelectronics

16【CAD tool support】

since 1997, (2) “Refresh seminar” since 1998, (3)【Chip fabrication services】

through CMP and 0.8 μm CMOS by On-semiconductor-

Activity Report of VDEC

Sanyo as the regular services.

We will continue Cadence tools, Synopsys tools andTable 1. 7. 1 Chip fabrication schedule【CMOS 1.2μm 2P2M】 On-Semiconductor (Former Motorola Japan)
Chip application deadline

Design deadline

Chip delivery

2016#1

2016/ 7/ 8

2016/ 9/30

2016/12/23

2016#2

2016/12/30

2017/ 3/24

2016/ 6/20

Chip application deadline

Design deadline

Chip delivery

2016 #1

2016/ 3/ 7

2016/ 5/30

2016/ 9/16

2016 #2

2016/ 5/ 2

2016/ 7/25

2016/11/11

2016 #3

2016/ 6/28

2016/ 9/20

2016/12/27

2016 #5

2016/11/28

2017/ 2/20

2017/ 6/16

Chip application deadline

Design deadline

Chip delivery

2016 #1

2016/ 5/23

2016/ 7/4

2016/12/15

2016 #2

2016/12/12

2017/ 1/23

2017/ 7/ 6

【CMOS 0.18μm 1P5M (+MiM)】 Rohm

【FD-SOI CMOS 28 nm 1P10M】ST Microelectronics
Based on the chip fabrication schedule through CMP.
【SOTB CMOS 65 nm】 Renesas Electronics

VDEC2016_E.indb 16

2016/12/07 17:09

1. 7  Venture companies related to VDEC
Some professors related to VDEC started venture companies. The following is a list of the venture companies
related to VDEC.
[1] AIL Co.,Ltd. (http://www.ailabo.co.jp/)
Related professor : Professor Kazuo Taki, Kobe Univ. (President-Director)[2] Synthesis Corporation (http://www.synthesis.co.jp/)
Related professor : Professor Emeritus Isao Shirakawa, Osaka Univ. (Director)(2) System LSI design, design services(3) Development and sales of IPs(4) Development of EDA tools[3] Nanodesign Corporation (http://www.nanodesign.co.jp/)
Related professor :Professor Kazuyuki Nakamura, Kyushu Institute of Technology. (Representative Director)

Related professor : Professor Emeritus Atsushi Iwata, Hiroshima Univ. (Representative Director)
Description of business : (1) Measurement and analysis of LSI substrate noise(2) Design of analog-RF mixed signal LSIs
(3) Training of analog design on the JOB method[5] Ishijima Electronics (http://ishi.main.jp/)
Description of business : (1) Electronic circuit development(2) Software development

1-7
17

Activity Report of VDEC

[4] A-R-Tec Corp. (http://www.a-r-tec.jp/)

Chapter 1

Description of business : (1) Hardware/software co-design(3) Consulting

VDEC2016_E.indb 17

2016/12/07 17:09

1. 8  “Nanotechnology Platform”:
Ultra Small Lithography and NanometricObservation Site
VDEC is operating an open-use nanotechnology

sizing from 1cm-sqare chip to 8-inch round wafers. The

platform “Ultra Small Lithography and Nanometric

per formance is measured by the number of research

Obser vation Site” together with the Institute ofreports and machine use. The University of Tokyo site

Engineering Innovation of Graduate School ofhas received 159 research reports including 22 from big

Engineering. The site is supported by Japanese Ministrycompanies, 4 from Small and Medium-size Enterprises

Chapter 1of Education (MEXT)ʼs Nanotechnology Platform grant.

(SMEs), 29 from other universities, 100 from UTokyo

Any researchers in Japanese Universities, Laboratories,

researchers (including exter nal collaboration but

and Companies can take full advantage of The University

excluding VDEC), and 4 from public research institutes.

of Tokyoʼs cutting-edge nanotechnology apparatuses

The exposure count was 2115 for 12 months (176.3/

1-8

and know-hows. The accessible technology includes

month), which is the record since beginning of existing

Lithography and Etching environment, Ultra High-statistics (460 for FY 2000). As shown in the Fig. 1, usage

Voltage Acceleration (1MV) transmission electron

is monotonously increasing. “Open ratio”，which is the

microscope (TEM) that is capable of visualizing upto

number of days in which users outside the University oflight materials such as Nitrogen. VDEC takes par t inTokyo came, divided by machine open days, was 99%.

the lithography at Takeda Sentanchi Super Cleanroom.

Due to the strong support of nanotech. Platform, even a

Through VDECʼs key apparatus F5112+VD01 donatednovice user can obtain fine lithography result by usingfrom Advantest Corporation as well as F7000S-VD02

the apparatuses with the Platform engineering staffs ofpurchased by national budget, VDEC is supporting post-

VDEC.

18

Activity Report of VDEC

VLSI activities such as MEMS. The machine is capableof rapidly writing patterns on arbitrar y-shaped targets

URL:http://nanotechnet.t.u-tokyo.ac.jp/

Fig. 1 Monthly Average Exposure Count of EB Machine (s).

VDEC2016_E.indb 18

2016/12/07 17:09

2. Activity Report of“ADVANTEST D2T Research Division”
2. 1 Introduction of“ADVANTEST D2T Research Division”

2.1.1 Aim of the establishment of“ADVANTEST D2T Research
Division”

star ted in October 2013 thr ough the cour tesy of
ADVANTEST Corporation. We are approaching the lastyear of the third phase with very fruitful achievements

ADVANTEST D2T research division was establishedin research, education, symposium organization, andin VDEC in October 2007. As the name of the researchso on. We also invited Professor Mehdi B. Karlsruhe

division indicates, it is financially suppor ted by

Institute of Technology from August to December 2015,

ADVANTEST Corporation.

and leveraged research collaborations between KIT and

The aim of establishment of ADVANTEST D2T
research division is to promote the research andeducation environment of VLSI testing in all universities
and colleges in Japan. “D2T” means that we consider not
only design but also test. As the results of our activities,
we hope to provide the exper ts of design and test forindustry. In addition, we are exchanging researchers with

VDEC, other research institutes and companies.
Details of our groupʼs activities are presented in thefollowing sections.

2.1.2 Members of “ADVANTEST D2T
Research Division”
Project Professor

other universities or research institute in both Japan andMehdi Baradaran Tahoori(Aug. 2015–Dec. 2015)

Project Lecturer

Rimon Ikeno

environment to make collaboration with industry because

Assistant Professor

Nguyen Ngoc Mai Khanhtesting of VLSI is one of the most practical research topics

Researcher

Takahiro Yamaguchi

in industry. Based on those activities, our final goal is tobecome a center of excellence of VLSI Testing in Japan.

(ADVANTEST Laboratories Ltd.)
Researcher

The first phase and the second phase of D2T activities
respectively. We are currently in its third phase that

VDEC2016_E.indb 19(ADVANTEST Corporation)
Assistant Clerk

Makiko Okazaki

2-1
19

ADVANTEST D2T Research Division

had finished in September 2010 and September 2013,

Masahiro Ishida

Chapter 2

overseas. Moreover, D2T research division is in a good

2016/12/07 17:09

2. 2.  Report of “10th D2T Symposium”“The 10th D2T Symposium” was held on August 21st,

University of Tokyo, and Professor Tibor Grasser from2015 at Takeda Building with more than 160 participants.

TU Wien. At the panel discussion whose theme wasUnder its main theme: “Reliability for automotive and“Reliability / dependability of industrial standards forother applications”, the symposium had valuable lecturers

automotive systems”, we invited two guest panelists,by distinguished researchers invited from both overseas

Professor Tomohiro Yoneda from National Institute forand domestic institutes, latest achievement repor ts

Informatics and Takao Futagami from Toyo Corporation,

by VDEC researchers, and a panel discussion by thein addition to the invited lecturers. Highly-reliablelecturers and guest panelists.

electronics systems for automotive applications and

The invited lecturers were Takashi Setoya fromits standardization were discussed lively. We sincerely

Toshiba Corporation, Professor Subhasish Mitra

appreciate every participant for their contribution at thefrom Stanford University, Professor Mehdi B. Tahoori

symposium.

from Karlsr uhe Institute of Technology and The

Chapter 22-2
20

ADVANTEST D2T Research Division
VDEC2016_E.indb 20

2016/12/07 17:09

9th D2T Symposium Program
Opening Remarks
Kunihiro Asada (Director, VDEC, The University of Tokyo)
Shinichiro Kuroe (President and CEO, ADVANTEST Corporation)

10:15

Session 1 (Chairman: Toru Nakura, The University of Tokyo)“High reliability and process control technique of LSI for Automotive product” [Invited]
Takashi Setoya (Toshiba Corporation, JEITA)“Cross-layer Resilient Design for Automotive Electronics” [Invited]
Mehdi B. Tahoori (Karlsruhe Institute of Technology)

11:45

Lunch

13:00

Session 2 (Chairman: Shinichi Takagi, The University of Tokyo)“Robust Systems: Overcoming Complexity and Reliability Challenges” [Invited]
Subhasish Mitra (Stanford University)“Advanced Modeling and Characterization of Bias Temperature Instabilities and Hot Carrier Degradation” [Invited]
Tibor Grasser (TU Wien)

14:30

Coffee Break

15:00

Session 3 (Chairman: Makoto Ikeda, The University of Tokyo)“Activities of VDEC Advantest D2T Research Division”
Rimon Ikeno (The University of Tokyo)“FET-R-C Circuits: A Unified Treatment”
Tetsuya Iizuka (The University of Tokyo)“A Novel Circuit for Transition-Edge Detection”
Takahiro Yamaguchi (ADVANTEST Laboratories)“Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills”
Masahiro Ishida (ADVANTEST Corporation)

16:25

Break

16:40

Panel Discussion“Reliability / dependability of industrial standards for automotive systems”
Theme:
Moderator: Masahiro Fujita (VDEC, The University of Tokyo)
Tomohiro Yoneda (National Institute for Informatics)
Panelists:
Takao Futagami (Toyo Corporation / SESSAME)
Mehdi B. Tahoori (Karlsruhe Institute of Technology)
Subhasish Mitra (Stanford University)

2-2

18:00

Closing21

18:15

Reception

ADVANTEST D2T Research Division

VDEC2016_E.indb 21

Chapter 2

10:00

2016/12/07 17:09

2. 3.  Research Activity Reports of“ADVANTEST D2T Research Division”
This year, for the power delivery network modeling,
On-chip Stochastic Data Converter/On-chip

we have investigated an algorithm for calculating a sim-

Spectrum Analyzer

ple circuit model of the on-chip power delivery network

Takahiro Yamaguchi, Nguyen Ngoc Mai Khanh,based on measurements of currents supplied from

Rimon Ikeno, Kunihiro Asada

power supplies to the device, and evaluated its feasibil-

In the research toward on-chip digitizer systems uti-

ity by using an actual laid out power delivery network

lizing stochastic comparator groups, comparator circuitwith computer simulations. Furthermore, for the power

and its measurement methodology are studied.

integrity control method, we have developed a new

We progressed theoretical study of the stochastic

method which can emulate any power supply character-comparators based on the measurement data of com-

istics based on the feedback control and demonstrated

parator groups that had been designed by Dr. James S.

the concept and feasibility of the proposed method byTandon in 65 nm CMOS technology with single-ended

experiments using actual hardware including FPGA.

circuitry.
We are also pursuing a differential comparators for

Chapter 2

2-3
22

better noise immunity and improved symmetry in theHigh-throughput and high-accuracy electron-beam

offset variation. Test chips in 180 nm CMOS and 65 nm

direct writing (EBDW) strategy for wide range of

SOTB CMOS processes were designed. DC measure-

EBDW applications

ment methodology for such differential-signal circuits

Rimon Ikeno, Satoshi Maruyama, Yoshio Mita,

were investigated to realize low-noise and high-resolu-

Makoto Ikeda, Kunihiro Asadation measurement.

Maskless lithography by Electron-Beam Direct
Writing (EBDW) lithography is expected as a low-costand short turn-around time (TAT) lithography technol-

Power Integrity Evaluation Method

ogy, but it also has some drawbacks like low process

ADVANTEST D2T Research Division

Masahiro Ishida, Naoki Terao, Toru Nakura,

throughput and low accuracy against the intended

Rimon Ikeno, Kunihiro Asada

layout shapes. We are pursuing high-speed and high-ac-

While a required power supply voltage has become

curacy EBDW strategy utilizing Character Projection

lower due to the advanced miniaturization of the semi-(CP) method to overcome these concerns and to boost

conductor process, the power supply current consumed

EBDW use in arbitrary fields like MEMS, photonics,

by a semiconductor device has increased because ofand so on.

the huge number of transistors integrated on a sin-This year, we applied our layout-data conversion

gle chip. It may increase the power supply noise, andmethodology for high-accuracy CP exposure of arcs

power integrity issues of the device under test in bothand oblique edges to our lithography experiments ofan ATE and a practical operating environments.

the practical device structures like light wave guides.

The purposes of this research project are to devel-

We introduced a high-resolution EB resist material, andop a method for evaluating power integrity at on-chip

established a total process and observation flow to see

power supply nodes in semiconductor devices (power

the relationship between the data-conversion param-

delivery network modeling method) and a new power

eters and the resultant device quality like line edge

integrity control method which is more suitable for theroughness (LER).

ATE than our conventional method.

VDEC2016_E.indb 22

2016/12/07 17:09

2. 4.  Publications
Proceedings of SPIE 9781, Design-Process-Technology

Journal papers[1]

Masahiro Ishida, Toru Nakura, Takashi Kusaka, Satoshi
Komatsu, and Kunihiro Asada, “Dynamic Power Integrity

Co-optimization for Manufacturability X, 978110, March
2016.
[4]

Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura andKunihiro Asada, “Analytical design optimization ofControl of ATE for Eliminating Overkills and Underkills

sub-ranging ADC based on stochastic comparator,” 5.7.3,

in Device Testing,” to be published on Journal of

Design, Automation and Test in Europe (DATE) 2016,

Electronic Testing: Theory and Applications, 2016.

March 2016.

International Conferences,
Symposiums, Workshops

Domestic Conferences, Workshops, etc.

[1]

[1]

[2]

Takahiro J. Yamaguchi, Katsuhiko Degawa, Masayuki

Rimon Ikeno, “Advanced electron beam direct writing

Kawabata, Masahiro Ishida, Kouichiro Uekusa, andtechnique for arbitrar y layout figures using the latest

Mani Soma, “A new method for measuring alias-free

EB lithography apparatus in VDEC,” Joint Workshop ofaperture jitter in an ADC output,” in Proceedings of IEEE

Nanofabrication and Advanced Characterization Platforms

International Test Conference, Anaheim, CA, October 6-8,

in The University of Tokyo, Nanotechnology Platforms of

2015.

the Ministry of Education, Culture, Sports, Science andMasahiro Ishida, Tor u Nakura, Akira Matsukawa,Technology (MEXT), Japan, Nov. 2015.

Rimon Ikeno, and Kunihiro Asada, “A Technique forAnalyzing On-chip Power Supply Impedance,” Asian Test
Symposium (ATS) 2015, 6B-1, November 2015.
[3]

Rimon Ikeno, Satoshi Maruyama, Yoshio Mita, Makoto

Patent[1]

Masahiro Ishida, Takashi Kusaka, Rimon Ikeno,
Kunihiro Asada, Tor u Nakura, and Naoki Terao,

phy with character projection exposure for throughput“Apparatus and method to emulate impedance charac-enhancement with line-edge quality optimization,”teristics of power supply network,” Patent application(Japan) 2016-014282, Jan. 28th, 2016.

Chapter 2

Ikeda, and Kunihiro Asada, “Electron beam lithogra-

2-4
23

ADVANTEST D2T Research Division

VDEC2016_E.indb 23

2016/12/07 17:09

Chapter 3 Research in VDEC
Asada, Nakura and Iizuka
Laborator y(http://www.mos.t.u-tokyo.ac.jp)

PLL circuit with Time-Domain control
Kunihiro Asada, Toru Nakura, Tetsuya Iizuka,
Toshiyuki Kikkawa, Takashi Toi, and Meikan Chin.
In this research, we have applied time-domain con-Supply Fluctuation Monitoring, Analysis andtrol methods to PLL circuit and its measurement. A

Reduction Method

Pulse-Width Controlled PLL (PWPLL) is a new type

Kunihiro Asada, Toru Nakura, Tetsuya Iizuka,of PLL whose oscillator is controlled by a pulse width.

Masahiro Kano, Satoshi Matsukawa, Naoki Terao

The PWPLL is implementable in a very small area, on

As miniaturization of semiconductor process increas-

the one hand, its operating conditions are sensitive toes, power supply voltage fluctuation due to its parasitic

the several variations. For example, a lock range of the

impedance has become serious concern.

PWPLL tends to be narrower than that of other PLLs.

Passive decap is one of the most popular method

Therefore, we proposed two methods to improveused for supply noise reduction, however, this requires

a tolerance of the PWPLL especially against pro-large silicon area for large capacitance. Then, we

cess-variations. As the first method, we employed afocused on the active charge injection method in ordervariable-length ring oscillator where the number of theto realize both noise reduction and silicon area reduc-ring stages is controllable. Also, we tried to control thetion. Previous works of this method did not mention theload-capacitance of the oscillator. We fabricated two

amount of charge injected into supply line, therefore

prototype chips and their measurement results show

we analyzed this method under certain assumptions

an enhancement of the lock range and reduction of theand designed the circuits (voltage drop detector, injec-

rms jitter.

Chapter 3tion controller circuit and canceling capacitor circuit)

We also demonstrated a PWPLL compiler which gen-to realize the analyzed charge injection. We simulated

erates GDS data from performance specification. The

these circuits with post-layout parasitic wire capaci-

inputs of the compiler are standard cell libraries, SPICE

tance and realized about 30% noise reduction and aboutparameters and the target specification file including

70% area reduction.

the output frequency, the division ratio and the Process,Also, the parasitic impedance on supply line andVoltage, and Temperature (PVT) corner conditions.

power supply voltage fluctuation do not affect only the

The PLL compiler calculates rough values of the design

inside of LSI chip.Generally, LSI undergoes test after

parameters, r uns SPICE simulations, analyses the

3-1

manifuctured to see if it will work normally. However,waveform files to adjust the design parameters, consid-

impedance mismatch between ATE and customer envi-

ering the variation of the PLL characteristics with the24ronment will degrade reliability of the test.

given PVT variation. When the waveform satisfies the

Research in VDEC

We proposed and designed power supply system for
ATE which has an ability to adjust its impedance to any

specification, the compiler generates a verilog netlist
and a GDS is designed by the netlist.

one by using feedback system with compensation cur-Furthermore, we proposed a measurement method

rent source, so it can emulate customer environment.

of PLL frequency characteristics not through analog

We are currently successfull of changing impedance

measurement but through digital interface in orderusing compensation current but voltage fluctuation

to reduce the test cost. The proposed method utilizes

waveform is still not exactly the same as expected, so

Digital-to-Time Converter (DTC) as an integrated stim-

more adjustment will be needed.

ulus generator, and Time-to-Digital Converter (TDC)
as an integrated response analyzer. Since both the DTC
and the TDC are composed of the same delay cells
in our proposed method, the measurement result isrobust against the PVT variations. The robustness of
our proposed method is demonstrated by HSPICE sim-

VDEC2016_E.indb 24

2016/12/07 17:09

ulations. We also worked on a PLL bandwidth control

noise of the oscillator has been a big issue. We resolved

as an application of the proposed measurement meth-the problem by introducing a feed-back architectureod.

with a digital controller and Fractional Delay Control
Scheme.

Time Domain CDR and TDC Designs
Kunihiro Asada, Toru Nakura, Tetsuya Iizuka, Norihito

Radiation Detector Utilizing Semiconductor

Tohge, Takehisa Koga, Tomohiko Yano

PhotodiodeWhile digital circuits directly benefit by advanced
process technologies, analog circuits suffer from neg-

Kunihiro Asada, Toru Nakura, Tetsuya Iizuka, Yang
Xiao, Kai Xu

ative effects such as small voltage headroom. Time-

Scintillation detectors and semiconductor detectors

mode circuits, where analog signals are represented

have received wide spread attention since they canby digital signal edge transitions, could be a solution

specify the nuclide of radiation and estimate the arriv-of analog circuits in a nanometer process. In thisal angle. Former research proposed a detector using

research, time-mode analog signal accumulator isthe cube scintillator, SPAD (Single Photon Avalanche

proposed as a fundamental building block of analog

Diode) array image sensors, multi-coated materials,

circuits. The proposed accumulator holds the time vari-and pinholes and verified the technique to detect theable by the time interval of two pulses which propagate

locus of the lighting electron by this detector. However

on a single delay-line ring consisting of gated invert-

the detect and estimate costs plenty of time. Thisers, eliminating drift error due to the delay mismatch

research proposed a technique to detect the location

between the two pulses.

of the electron emitting light in high speed utilizing
the periodicity of the arrangement of the pinholes(TDC) is known as one of representative time domain

and SPADS. The result of the simulation verified thatcircuits. TDC converts a time difference between two

by using this technique the location of the electron

signals into a digital code by using delay elements.

emitting light in a scintillator could be detected with a

We dealt with an issue of conventional pulse-shrink-spatial resolution of 20 um within 20-40 seconds. About

ing TDC, one of the architectures of TDCs, which isthe structures of SPADs we have tested, the p-well/a tradeoff between linearity of the conversion and the

deep-n-well with poly gate SPAD shows the lowest

performances of sampling rate, power consumption,

DCR. A 31x31 SPAD sensor featuring breakdown pix-and jitter. We designed new scheme so as to solve thatels extraction architecture for efficient data readout

problem, and validated the per formances of higher

has been fabricated, and itʼs ability of capturing a shortsampling frequency, lower power consumption, andlaser pulse (40 ns) has been proved by measurements.

more precise single shot than conventional ones.
TDC can be applied for various applications, forSurface magnetic field modeling for LSI security

communication systems, it has been emphasized to

Kunihiro Asada, Toru Nakura, Tetsuya Iizuka,

increase data rate or power consumption per bit, how-

Yuki Oda, Tomohiro Hirata

3-125

ever, total amount of power consumption include both

The test of modern circuit is becoming more diffi-

in stand-by state and in operational state. However,cult because its structure is getting smaller and more

especially for optimizing energy consumption of serial

complex. Fast, cost-effective and accurate test method

communication systems which operate only intermit-

is highly in demand. Magnetic probe testing method is

tently, it is important that not only increasing power

focused in this paper.

consumption rate in their operational state but also min-

Magnetic emission of circuit board is measured

imizing power consumption of stand-by state and maxi-

by probe, and current distribution is estimated withmizing the period of stand-by state by launching quick-obtained magnetic field map. Estimated current dis-ly. A Clock-and-Data Recovery Circuit which is based

tribution can be used for non-destructive circuit test

on Cycle Lock Gated Oscillator has been proposed tomethod. The accuracy of current estimation is evaluat-

realize that. However, frequency mismatch resulted

ed by calculating thermal noise of probe and condition

from its feed-for ward architecture and quantization

number of trans-impedance matrix. We validated thisVDEC2016_E.indb 25

Research in VDEC

example the following research. In the realm of serial

Chapter 3

In addition to that circuit, time-to-digital circuit

2016/12/07 17:09

method by using electromagnetic field simulation.

For designing circuit of avoiding NBTI, we need accurate and fast simulation of NBTI. Thus, we propose an
accurate simulation method with calculation of potential

CMOS Based Sub-Millimeter Sensing System Using

NBTI. In this study, we record the states of potential

Time-Domain Spectroscopy Technique

NBTI by calculation of NBTI phenomena.

Kunihiro Asada, Tetsuya Iizuka, Nguyen Ngoc Mai-

In addition, for quick variation of NBTI on circuit

Khanh, Parit Kanjanavirojkul,Yudai Suzuki, Mitsuki

operation, the proposed method can realize high-speed

Nakamura,and Taiki Sugiyama

calculation by high accuracy approximate based on fre-

The target of this research is to implement sub-milli-

quency dependence of NBTI.

meter wave (THz) transceivers for sensing applications,based on time-domain spectroscopy (TDS) technique.
A wideband pulse generator realized by CMOS inte-

Chapter 3

grated on glass substrate is proposed. The pulse gen-

Kunihiro Asada, Toru Nakura, Tetsuya Iizuka,

erator features zero stand-by power, quick star ting

Maruf Hossain, Takaaki Ito, Ryosuke Saito

time, high efficiency. In addition, it is suitable for highA per formance model for Analog to Digitalfrequency generation, and not limited by CMOS Fmax.

Converter (ADC) based on stochastic comparator has

On the receiver side, sampling-based pulse receiv-

been proposed by analyzing the random variation in

er is studied. Equivalent sampling, detection method

comparator offset voltage. Probability Density Functionof Time Domain Spectroscopy(TDS), is used for this(PDF) has been formulated to establish the relation

receiver to detect and obtain waveform of received

among different design parameters and the resolution

pulse. The sampling-based detector switches matchingof a stochastic comparator. This PDF is used to calcu-

and mismatching states between antenna and mixer

late the yield of the ADC and the correlation among

impedance with NMOS (used as a Voltage Controlled

the analog steps of the ADC output code is ignored for

Resistor) and sampling pulse (inputted to NMOSʼgate).

simplicity. The validity of our model is then verified by

Array antenna for the system is also studied. Even

performing Monte Carlo simulation and it is shown

though, on-chip millimeter-wave band array antennathat the model is precise for a practical value of yield >has been developed in recent years, it is difficult to real-

0.8. This model is then applied to a sub-ranging ADC

ize sharp directivities because of the timing constraints

based on stochastic comparator to find out the optimaland limited aper ture length. The method proposed

resource distribution between the conventional deter-

and evaluated, can estimate the position and reflection

ministic architecture and the novel stochastic approach.

intensity of every look angle using set of receiving elec-

Sample and Hold Circuit used in an ADC generates

tric field when sending pulses with unsharp directivi-

nonlinear distortion, and it worsens ADCʼs accuracy.

ties.

Distortion analysis has already been conducted, andFor future applications, transmission properties of

it is known that distortion can be controlled by chang-THz through material are also examined. Fundamental

ing Sample and Hold Circuit parameters. To verify the26

property of terahertz time domain spectrometer was

accuracy of distortion analysis, we want to design a

Research in VDEC

3-1

High-performance A-D Converters

measured, and after that, measuring terahertz absorp-

Sample and Hold Circuit and measure its distortion.

tion property of submillimeter wave filter was attempt-

Recently, we checked by simulation that it is possible

ed. As a result, it became clear that teraher tz time

to measure the distortion and designed the distortion

domain spectrometer can be used to measure terahertz

measurement chip.

absorption property of submillimeter wave filter.

VLSI Reliability Improvement in nano-meter process
technologies
Kunihiro Asada, Toru Nakura, Tetsuya Iizuka, andKazunori Mori
Recent process miniaturization causes reliability
problems such as NBTI degradation on digital circuit.

VDEC2016_E.indb 26

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Fujita Laborator y(http://www.cad.t.u-tokyo.ac.jp/)

on a general purpose processor. This circuit is designed
to be scalable to the number of neurons. In the future
work, we will use multi-FPGA network to simulate tensof thousands of neurons.

Efficient Topological Matching Among Multiple
Circuits

Continuous miniaturization and per for mance
improvement of electronic equipment causes more

Masahiro FUJITA, Amir Masoud GHAREHBAGHI,

serious electromagnetic interference problems than

Hossein IZADI RAD

before. Insufficient performance of current simulators

Recognizing similarities and dif ferences amonglead to depending on real testing equipment with high-multiple circuits is very useful for managing and main-er cost. To tackle this problem, we have implemented

taining IP libraries as well as merging circuits, frauda fast simulator using FPGA for 2D and 3D simulation.

detection, reverse engineering, and redundancy check-

The original program can simulate around 100 MCell/ing. In this work, we address the problem of finding

Sec. The multi-core version of the program can run

the maximum common subcircuit among two or more

up to 2 times faster than the single-core version. Our

logic circuits. Given the gate-level netlists of the cir-

FPGA implementation runs more than 5 times fast-cuits, first we represent the circuits as graphs. Then,er than the multi-core version of the program (1130

we try to find the largest common subgraph with a new

MCell/Sec)

approach based on signature generation and matching.
We have defined a signature based on topology of thefanin cones of the circuit elements. Given two circuits,

High-Level ECO Through Mapping with Gate-Level

first we find all the circuit elements with unique signa-

Designture between the two input circuits. After that, we try

Masahiro FUJITA, Amir Masoud GHAREHBAGHI,

to expand the matching area by our expansion rules

Qinhao WANG

as much as possible. We iteratively find the uniqueIn the hardware design flow, there are often thematches and expand the matching area until no further

situations that the bugs or the specification need tomatching is possible. Our experiments on IWLS2005

be changed quite late in the design flow. Designers
do not want re-run the whole design flow from begin-to find the per fect matching between two 160,000-

ning since the cost and time-consuming. Engineeringgate IP in 5 minutes. In addition, our method is more

Change Order (ECO) may happen in a design due to athan two order of magnitude faster than our previous

bug fix or a change in the original specification. ECO isgraph-matching based method, while the size of the

expected to be a small change.

matched area is comparable or larger.

High-level design methodology is used for implementing new algorithms since it can increase thedesign abstraction and reduce the time to market.

Acceleration of Calculation with FPGA

However, little change from high-level description will

Chapter 3benchmark suite show that our method is able

3-1

Masahiro FUJITA, Amir Masoud GHAREHBAGHI,

have a great impact on circuit structure after high-level

27

Taro KAWAO

synthesis. In this work, we proposed a method for highResearch in VDEC

Dedicated hardware is generally faster and morelevel ECO. First, the original topological (part of data

energy-ef ficient than a general hardware. A circuit

flow graph) is fixed, and then we replace partial opera-

optimized for specific calculation can be obtained with-

tions (nodes of DFG) by programmable datapath. Thisout chip fabrication using a Field Programmable Gate

transform the ECO to an equivalent problem, and thenArray (FPGA), which is a programmable circuit. In thisget the solution by SMT solver automatically. We also

work, we have considered acceleration of simulation ofextend the problem to the situation when the designneural network and analysis of electromagnetic field.

specification is not given. Experimental results show

Neural network is a mathematical model of themechanism of a brain. We implemented a highly pipe-that this method can solve several practical examples ofhigh-level ECO.

lined circuit on a FPGA to simulate the network composed of 1024 spiking neurons and we could accelerate
the simulation by 47x compared to real time calculation

VDEC2016_E.indb 27

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Debugging Electrical Bugs using Trace Buffers
Masahiro FUJITA, Amir Masoud GHAREHBAGHI,
Kentarou IWATA

Reverse Engineering of gate level circuit
Masahiro FUJITA, Yusuke KIMURA
This research topicʼs aim is to suggest the correspon-As VLSI becomes denser and place and route stage

dence between high-level description and synthesized

becomes more difficult, more electrical bugs can occur,gate-level description. Gate-level circuits usually have

which are caused by thermal change, drop in supply

state machines, and it is one of the causes of difficulty

voltage or crosstalk. It is difficult to reproduce because

in analyzing the correspondence. We suggested thethese bugs occur randomly. So debugging is time-con-tentative method for extracting flip-flops related to statesuming. Therefore, we use trace buf fers as on-chipmachine from gate level circuit. By analyzing the state

memory to record partial values of flip-flops repeatedly.

transition of the flip-flops, we can get the correspon-

Furthermore, past state values are restored from thosedence between the state of high-level description and ofvalues in order to find a location of electrical bugs. A

gate-level circuit.

major problem is to identify whether recorded values
are correct or not because the location and time ofoccurrence of electrical bugs are unknown.

Takamiya Laborator y(http://icdesign.iis.u-tokyo.ac.jp/)
HW/SW Co-Verification of embedded system
Masahiro FUJITA, Yusuke KIMURA
As embedded software becomes more complex
nowadays, verification technique for its verification

towards Energy Autonomous Electronic Devices
Makoto Takamiya and Takayasu Sakurai

Chapter 3

becomes more important. Interruption service routine

Requirements for IoT sensor nodes, wearable health-(ISR) is one of the characteristic functions of embedded

care devices, and implanted medical devices are thesystem, and we focused on verification method consid-

wearing-unconsciousness and the maintenance-freeering ISR in this topic. We suggested to use constraints

operation. To enable the wearing-unconsciousness,

generated from real systemʼs in-out data for verification

mechanically flexible or small-size devices with thein order to reduce the number of execution paths thatwireless connection are required. To enable the main-

are used for test. We additionally implemented thetenance-free operation, energy autonomous devices arevariable dependencies solving method and the number

required. The energy autonomy is achieved by both theof execution paths for testing becomes less than lastenergy efficient operation and the energy harvesting.

yearʼs. We successfully verified an industrial example inreasonable time.
Large Area and Flexible Electronics with Organic

3-1
28

Integrated Power Management Circuits and Systems

Transistors
SW Synthesis

Research in VDEC

Masahiro FUJITA, Yusuke KIMURA,
Kuntarou ISHIYAMA

Makoto Takamiya, Takao Someya, andTakayasu Sakurai
Large area electronics is a new frontier in electron-

In order to debug the software ef ficiently, we

ics where intelligent electronic devices are distributed

researched about the software synthesis method using

on a flexible surface, 10 cm to 10 m on a side, for thesmall number of input-output patterns. Without specify-

human interface and the comfortable daily life. Flexible

ing whole input-output patterns, the tool can generate

and low-cost organic FETs (OFETs) are suitable forthe program by asking appropriate outputs for somelarge-area electronics and have great potential as a sup-inputs. This technique can apply for the debugging

plement of solid and expensive silicon MOSFETs forwhen error localization is finished and for the synthe-

VLSIʼs. We have proposed and demonstrated several

sis for the place where it is difficult for human to write

large area and flexible applications including a surface

code manually, for example bit calculation.

electromyogram measurement sheet for prosthetic
hand control, a flexible wet sensor sheet for biomedical
applications, and a fever alarm armband.

VDEC2016_E.indb 28

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Ikeda Laborator y(http://www.mos.t.u-tokyo.ac.jp)
Current Research Projects

Digital control for an Electrostatic Micro Actuatorwith CMOS circuit
M. Ikeda, S. Maruyama
Control of MEMS devices are usually done by analog

High-performance Cryptographic Engine Design
M. Ikeda, M. Tamura, T.Ikeda

domain, however, in this study, we tried to study digitaldomain control of MEMS devices. We applied PWM

We have studied about the implementation of cryp-

control pulses to micro-actuator with electro-static con-tographic engines. We implemented elliptic cur vetrol with higher frequency than the electro-mechanicaldigital signature algorithm（ECDSA）using 65 nm

resonance of the actuator, and at the same time, we

SOTB CMOS. We have proposed pipelined high radix

carried out measurement of MEMS displacement by

Montgomery multiplier for critical path delay minimi-

capacitance measurement. With this scheme, we eval-zation. We realized 1.6x throughput than the conven-uated control of delta-sigma modulator for the electro-

tional Montgomery multiplier and minimize signature

static micro actuator in the digital domain.

generation time for ECDSA. Measurement resultsshows signature generation time and energy consumption of 330 us and 13.9 uJ, respectively at the nominal

3D-range finding by Smart Image Sensors

power supply of 1.1V, and those of 2.3 ms and 1.68uJ,

M. Ikeda, U. Kim, D. Uehara, J. Imabayashi,

respectively at energy minimum operating condition

M. Tanibuchi

of power supply voltage of 0.3V. The area of this circuit

We have studied smar t image sensors for 3-D

is 1.92 mm2. We also implemented 1024 bit RSA cryp-

range-finding with back-ground illumination rejec-

tographic engine showing area-delay tradeoffs for radix

tion capability by utilizing modulated light projection.

2 to 1024 of Montgomer y multiplier. The results ofCommon-mode rejection circuit is introduced to lock-in

logic synthesis with 65 nm SOTB CMOS library shows

type pixel to enhance back-ground illumination rejec-

the fastest 1024 bit RSA encryption of 81 us by usingtion. In addition, we have studied faster range-finding

1024 bit multipliers.

technique by utilizing de Bruijn sequence.

SEU resistivity of Self-Synchronous System based

Mita Laborator y(http://www.if.t.u-tokyo.ac.jp)

Chapter 3

on Dynamic Circuits
M. Ikeda, D. Sai
Self-Synchronous Controlling by hand-shaking
based on gate-level completion detection is regarded

Study on LSI-MEMS integrated pond-skating robot

as reliable controlling mechanism under large process

for energy-autonomous distributed microsystems

variation and large power supply bounce, especially for

Y. Mita, I. Mori, Y. Okamoto Y. Li, S. Smith, A.J. Waltonlower voltage operations. Dynamic circuits are, howev-(Univ. of Edinburgh)

3-1
29

As one example of integrated MEMS that is expected

injection for the advanced process with lower operating

to open new research and industrial application fields,

voltage. In this study, we have studied SEU probability

the authors are trying to show a top-down application

estimation method by injecting charges into nodes forof energy-autonomous distributed microrobots. The

standard cells comprising the self-synchronous basic

research belongs to the “top-down” research categorycells. SEU probability estimation is carried out by

and through the research the team looks for ward to

charge injection timing, time domain probability, andprovide the “Engineered Nature”; the team does not

simplified area estimation, special domain probability,

intend to just copy how nature works in implementation

for circuits nodes. We extracted the most SEU tolerant

level, but to realize with cutting-edge technologies whatcell by exhaustive calculation of SEU error probabilities

nature is aiming at in highly-functional level. Recent

for possible netlist of a function, and possible transistor

top-down activities include autonomous distributed

placements.

mobile robot: “Pond Skater”，which to date had not

Research in VDEC

er, assumed to be vulnerable against SEU by neutron

been realized by any other microsystems group. The

VDEC2016_E.indb 29

2016/12/07 17:09

availability of a leading low voltage technology at the
Scottish Microelectronic Centre (SMC) the University

Top-down fabrication of small-gap electrode devicesof Edinburgh that could electrically change surfaces

by Fine E-Beam writing and MEMS processfrom hydrophobic to hydrophilic proved to be crucial to

Y. Mita, Y.Takeshiro, N. Washizu, A. Takada,achieving this goal as was the previous involvement of

M. Fujiwara, T. Sawamura, R. Ikeno, and K. Asada

SMC staff in wireless technology. The major challenge

Towards the goal of production of brand-new sensor

is propulsion, and it is clear that directly mimicking

devices with higher sensitivity and functionality, thethe pond skating insectʼs propulsion mechanism would

team is working on small-gap electrode fabrication pro-be problematic. The idea that was developed was tocess. The team takes full advantage of newly-acquired

propel the device using Electro-Wetting Of Dielectric(2013) rapid electron beam writer F7000S-VD02. The(EWOD) to move air bubbles, which had the significant

capability of high electron dose and sharp edge due

advantage that there we no moving mechanical parts,

to cell (character) projection machine configuration iswhich simplified the construction and helped to mini-

used for fabrication process. The target of first year ismize the weight which was important if the pondskat-reliable sub 100 nm gap electrode fabrication, as well as

ing device was to float using surface tension. Based on

microactuator-integrated nanogap system.

the worldʼs first wireless pond-skating propulsion, theteam is developing VLSI control circuit and integration
technology for continuous skating. In FY2015, CMOS-

University-Industry collaborative research on high-Post-processed HV generating photovoltaic process has

ly-functional system by MEMS post-process of

become so reliable that top-down applications can rely

CMOS-VLSI

on it. As one practical advantage, wavelength modula-

Y. Mita, R. Sekiguchi (Canon Research Laboratory),tion control scheme has been experimentally verified;Y. Nakayama (Konica Minolta)

by sending lights of two dif ferent wavelength, theThe research targets are new sensor devices, madedevice can intentionally charge and discharge MEMS

by post-process at clearnrooms such as VDEC Takeda

devices with sufficiently short time. High frequency

Supercleanroom and others, of VLSI wafer made(around resonant frequency) has become possible.

through VDEC. The important finding has been that
VLSI wafer acquired just after transistor fabrication
could sustain processes even with heat treatment,such as deposition, ion implantation, and drive-in. In

MEMS air-flow actuator local fluidics optimization

2015, an integrated Teraherz wave receiver has been

Y. Mita, K. Kawahara, and Y. Okamoto

fabricated and successfully demonstrated. Also, a VLSIThe PI has received a French National Researchdevices made on Silicon-on-Insulator (SOI) wafer wasCenter (ANR) grant on behalf of host professor of

successfully Deep-RIE processed. The industrial inter-

3-1

CNRS laboratory in the Institute of Industrial Science

est is its versatility–many different types of application(LIMMS, CNRS-IIS, UMI 2820), together with FEMTO-

devices, which differ one from another according to30

ST Laborator y. The objective is “an actuator system

request of market, can be fabricated by using the same

Research in VDEC

Chapter 3

Smart BlocksII Project–A higher alignment accuracy

that can auto-reconfigure as well as make conveyancetechnology. More and more companies are interested

function”． In the last year, a microactuator systemin the scheme and are working on the technology on

with higher alignment accuracy was developed. Past

the collaborative research project.

devices have suffered from turbulence of ejected air,yielding relatively low alignment accuracy. By carefully
designing local air fluidics, we have demonstrated highly accurate conveyance of micro objects, both experimentally and in FEM simulation.

An LSI probing system with CMOS-MEMS
Y. Mita, R. Setoguchi and Y. Okamoto
The team is developing a “MEMS” probe card forelectron device testing such as VLSI. The originality is
to integrate CMOS circuit to provide high functionality.
In the year 2014, a piezo-resistive stress measurement
circuit was developed to quantify real stress put on theprobe. A company-made polysilicon resistor, madeVDEC2016_E.indb 30

2016/12/07 17:09

by post-processing commercial CMOS 0.6 µm 1P2M

MEMS are replaceable so that the system can havecircuit, was integrated into cantilever and responded

always a “fresh” surface. The key enabling technolo-

to the stress with good gauge factor (around 20). The

gy is wireless energy and command transfer, with ontechnology has been standardized and could be applied

electrical wiring in between. For that purpose the teamto other groupsʼresearch work. Also, to have reliabletries to use resonance power transfer method in the

microprocess, a test structure to visualize end-point ofsubmillimeter-scale, 1 GHz-range carrier. By Phenitec

Deep-RIE process is developed.

Semiconductor VDEC run LC oscillator was fabricated.
Magnetic power coupling experiments were successful in between the LSI and power receiver with ciliary

Right-Brain-Computing Integrated Circuits:

motion MEMS actuator. The method was experimen-

Associative Processing Systems

tally applied to both “voltage driven (=electrostatic)”

B. Ka, N. Yamashita, Y. Mita
Digital computers are dedicated machines for varyand “current driven” microactuators; the same circuit
could drive both types of microactuators.

fast execution of numerical calculations. However, theirperformance is extremely poor in such tasks like seeing, recognizing, and taking immediate actions, which“Zeolite-Electronics-Nanostructure (ZEN)” integrated

are ef for tless tasks in our daily life. This researchchemical sensor

aims at building intelligent VLSI systems based on

Y. Mita, S. Inoue, M. Denoual (ENSI de Caen, France),

the psychological model of a brain. In our system past

Tixier Mita Agnès, Eric Lebrasseur, Hussein Awala

experience is stored as template vectors in non-volatile(ENSI de Caen, France), Julien Grand (ENSI de Caen,vast memories and the maximum-likelihood event toFrance), Sveltana Mintova (ENSI de Caen, France)
One of the most impor tant application field ofallel processing. The key ingredient of the system is a

MEMS is sensors that can detect physical and chem-

new functional device called “Neuron MOS Transistor”

ical amount that cannot be sensed by human beings.

(neuMOS orνMOS) which mimics the action of a nerve

Following a long history of the groupʼs research, thecell neuron at a single transistor level. Based on suchteam was appointed in 2015 as a JSPS-CNRS bilateralarchitecture that “association” is the ver y computing

cooperative research project grant. The goal of theprimitive, we are pursuing human-like intelligence

research is to develop a chemical sensor by integrat-

system implementation directly in silicon integrated

ing Zeolite material that is new to VLSI, and applying

circuits. Currently research is in progress for robust

post-process on it. Within one year, the team alreadyimage recognition and classification processing includ-

have successfully demonstrated two types of devices:ing robust feature extraction. The sate-of-the-art silicona zeolite chemical sensor by resonant frequency shifttechnology has been utilized to implement such asso-

detection, and by thermal capacity change detection

ciative processors in both analog and digital CMOS

according chemical concentration.

Chapter 3

the current event is recalled in real time by a fully par-3-1

VLSI chips, and was published.

31

Research in VDEC

Takagi-Takenaka Laborator y
Micro Wireless Resonant Power Transfer that(http://www.mosfet.k.u-tokyo.ac.jp/)

Enables Metabolism of Fragile MEMS Actuator.
Y. Mita, N. Sakamoto, B. Stefenelli, A. Kaiser (ISEN/
IEMN-CNRS)

III-V/Ge Metal-Oxide-Semiconductor (MOS) FETs

The most severe problem of MEMS in which micro-

S. Takagi, M. Takenaka, Cai Weili, Yu Xiao,

actuators are exposed to the external world, such as

WuKang Kim, Chang Chih-Yu, Ke Mengan,

Smar tBlocksII demonstrators, is that fragile micro-

Liao Chenyu, Aya Shimada

actuators are little by little broken during usage, andfinally the entire system become unusable. The team

We have conducted the research on high-peformance
III-V/Ge MOSFETs.

proposes a “Metabolism MEMS” concept–the system

We have investigated InGaAs gate stack technolo-

is composed with detachable two parts: One is frag-gies by using La2O3/InGaAs MOS interfaces. We haveile MEMS and the other is robust VLSI. The fragile

shown that La2O3 deposted by ALD enable superior

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MOS interfaces for InGaAs. We have also fabricatedic-wire waveguide operated at mid-infrared wavelengths

extremeley-thin body Ge-on-Insulator MOSFETs byon the GeOI wafer. Optical modulation by carrier injec-

using wafer-bonded GeOI wafers. We have revealed thetion into the Ge waveguide was also demonstrated forphysical mechanism which degrades hole mobility inthe first time. For strained SiGe optical modulators, wethe ultra-thin Ge channel.

have proposed MOS-based optical modulators fabricated by wafer bonding. We have established the void-lesswafer bonding technology by using Al2O3/HfO2 interfa-

Tunnel FET

cial layer for wafer bonding.

S. Takagi, M. Takenaka, Min-Soo Kim, Takahiro Gotow,
Daehwan An, Takumi Kato, Yoon Sanghee
We have investigated tunnel FETs (TFETs) which

III-V CMOS photonics

can exhibit steep subthreshold slope for low-power

S. Takagi, M. Takenaka, Y. Chen, J. Park, S. Takashima,

operation. Lateral InGaAs TFETs and GaAsSb/InGaAs

N. Sekine

hetro-junction TFETs have been explored. By grow-We have investigated the III-V CMOS photonics

ing GaAsSb/InGaAs hetrostructure by MBE, we haveplatform by using III-V on insulator wafer. On the III-

demonstrated ver tical GaAsSb/InGaAs TFETs. We

V-OI wafer, III-V MOSFETs and III-V photonics can behave also investigated Ge/s-Si TFET for high Ion opera-monolithically integrated. We have successfully inte-tion.

grated an InP grating coupler with waveguide InGaAs
photodetector (PD) on the III-V CMOS photonics
platform. We have also revealed that a depletion-based

Si CMOS photonics

InGaAsP optical modulator exhibits 4 times higher

M. Takenaka, S. Takagi, Y. Kim, J. Han, J. Kang,

modulation efficiency than Si. We have also clarified

K. Takeuchi

the mechanism of quantum well intermixing on the III-We have proposed Ge CMOS photonics platform by

V-OI wafer. In addition, the bandgap wavelength shiftusing wafer-bonded GeOI wafers on which Ge CMOS

of more than 100 nm has been demonstrated, enablingand Ge photonic-wire devices are monolithically inte-

active-passive integration on the III-V CMOS photonics

grated. We have successfully demonstrated Ge photon-

platform.

Chapter 3

3-1
32

Research in VDEC
VDEC2016_E.indb 32

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VLSI Design and Education Center, The University of Tokyo
Annual Report
July, 2016
Published by
VLSI Design and Education Center, The University of Tokyo
Director Kunihiro Asada
Address: Yayoi 2-11-16, Bunkyo-ku, Tokyo, 113-8656, Japan
Printed in
Sanbi Printing Co., Ltd.
Address: Nishinippori 5-9-8, Arakawa-ku, Tokyo, 116-0013, Japan

Copyright © by VLSI Design and Education Center, The University of Tokyo

VDEC2016_E.indb 33

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平成28年度

東京大学
大規模集積システム設計教育研究センター

年 報

VLSI Design and Education Center The University of Tokyo 2016

2016
VLSI Design and Education Center,
The University of Tokyo
Annual Report

VLSI Design and Education Center The University of Tokyo 2016

VDEC年報2016_H1_4E.indd 4-1

2016/12/07 17:07