Vol. 54 No. 2  Material Science and Technology of Japan, 54㸦2017㸧65㹼6923Regular Paper
Shape Control of Floating Si Wires Fabricated by Anodization
Mitsuya MOTOHASHI1,*, Takuya IMAIZUMI1, Takatoshi TAGUCHI1,Toshiaki SUZUKI2, Takayuki YOSHINO1 and Masaaki NIWA1
1

School of Engineering, Tokyo Denki University, 5 Senju-Asahi-Cho, Adachi-ku, Tokyo 120-8551, Japan.

2

IB Business Unit, JEOL, 3-1-2 Musashino, Akisima, Tokyo 196-8558, Japan.

Received Aug. 19, 2016; accepted for publication Jan. 11, 2017
Abstract
We fabricated silicon wires of different thicknesses, shapes, and crystal types on wafers with pre-etched dislocations
using anodization with a hydrogen fluoride and ethanol mixture. Control of the groove outlines for dislocation madevarious wire configurations possible. The crystallinity of the wires was controlled by crystal face selection. The wires
featured a porous surface and crystalline ends when formed on a (100) Si wafer crystal face. On the other hand,entirely porous Si wires were formed when using wafers with a (111) crystal face. In addition, the capacity of thesewires for future device use was examined based on the wire crystallinity. Moreover, we discussed the formation
mechanism of these wires based on their shapes, where carrier transport in the wafer during anodization played a keyrole.
Keywords: Si wire, shape control, dislocation, anodization, porous Si

1.

Introduction

systems in order to develop new devices using floating wires.
asHowever, control of the wire size and crystallinity (crystalline orimportant components in future devices such as waveguides andporous) is not well established for these systems, as introducing

modulators for optical communication devices [1–3] andthe dislocations in a controlled manner is difficult. Furthermore,

photonic integrated circuits (ICs) [4–6]. These wires are typicallyconnections and curves are required of these wires to achieve

fabricated using traditional lithography techniques, where thehigh performance and multi-functional devices. This paper

wires are formed on silicon wafers. As a result, they are directly

reports the fabrication of wires having various controlledconnected to the wafer surface, restricting the possible wireconfigurations (such as lines, curves and crosses) using

shapes that can be formed. The contact area between the wires

anodization after introducing dislocations. The formationand the surface of the wafer can lead to carrier leakage,mechanism of these dislocations is also discussed.

Micronanostructured

siliconwires

areanticipatedelectro-magnetic effects, carrier transport and indexing issues for2.

photo integrated circuits. Furthermore, this contact reduces theExperimental methods

freedom of the wiring. Previously, we developed a new method

P-type (100) and (111) crystalline silicon wafers formed byfor fabricating Si wires using anodization after introducing

the Czochralski process were used as starting materials. Thedislocations into crystalline Si [7]. Wires made in this mannerresistivity and thickness of the wafers ranged from 1–100 ȍ·cm

have hybrid structures (with porous surfaces and crystalline

and 0.525–0.625 mm, respectively. The wires were fabricated bybottom layers) and freestanding structures. In addition, ouranodization after forming grooves on the silicon wafer surfaces

free-standing floating Si wire has free space around the wire.

using metal or diamond tip pens. The head radius of the metal

Such wires are expected to boost device performance, and newpen (GENERAL, Tungsten carbide point scriber/etching pen, #use cases are possible that utilize the space around the wires.

88) was 70 Ɋm, while the radius of the diamond one (Tokyo

Control of the wire shape and crystallinity is needed for suchseimitsu, Stylus of surface texture and contour measuring*Corresponding author: mmitsuya@cck.dendai.ac.jp(65)