2019VLSI Design and Education Center,
The University of Tokyo
Annual Report

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Message from Director of VDEC

Chapter1
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8

Activity Report of VDEC……………………………………… 2

Introduction of VDEC activities and activity report of FY2018………2
VDEC CAD Tools………5
VLSI Chip Fabrication………6
Seminar………9
Facilities………13
Activity plan for 2019………15
Venture companies related to VDEC………17“Nanotechnology Platform”
Ultra Small Lithography and Nanometric Observation Site………18

Chapter2 Activity Report of “ADVANTEST D2T Research Division”… ……19
2-1 Introduction of ADVANTEST D2T Research Division………19
2-2 Report of “13th D2T Symposium”………20
2-3 Research Activity Reports of “ADVANTEST D2T Research Division”………22
2-4 Pubications………23

Chapter3

Research in VDEC………………………………………………… 24

Chapter1

1.1
1-1

Activity Report of VDEC

Introduction of VDEC activities and activity report of FY2018

Chapter1 Activity Report of VDEC

VLSI Design and Education Center(VDEC), Universi-

year. We hold the seminar in VDEC and provide distancety of Tokyo was established in May 1996. VDEC has beenlearning through video streaming. We expect spread of theoperating for the following 3 major roles: “spreading the

up-to-date LSI design methodology by using CAD tools.

latest information on VLSI design and education,” “pro-We assume our LSI design flow seminars as educations

viding licenses of CAD tools,” and “supporting on VLSI

on basic LSI design concepts and practical experience ofchip fabrications for academic use.” The VDEC activity

LSI design with CAD tool chain. VDEC holds “LSI de-report of FY 2017 is described hereafter according to Fig.

sign education seminar”, a.k.a. VDEC Refresh Seminar,

1.1.

once a year. This year we hold 3 courses, “Analog design

The missions of VDEC are for advancement of re-course” and “RF design course”, and initiated “MEMS

searches and education on LSI design in public and pri-design course” in July-September time frame. We invite

vate universities and colleges in Japan and send many dis-experienced professors among universities as lecturers fortinguished VLSI designers into industry. After 23 years of

the courses to conduct LSI design education courses with

VDEC establishment, educations on CAD software, LSI

practical experience. We also hold “Transistor level design

design and design flow in universities have been well es-

flow in VDEC” and “Digital design flow in VDEC EDA

tablished. On the other hand, advancement on nano-me-

environment” for designers in universities. We started to

ter CMOS technologies forces design flow and CAD soft-

charge these two LSI design education courses, as well as

ware complicated. We have been continuing CAD tool

VDEC Refresh Seminars.

seminar by the lecturers from EDA vendors for twice a

In addition to the above seminars, we hold “VDEC De-

Fig. 1.1 VDEC activities

2

give answers to questions, however, in most cases, replies

nually. This is a workshop that the participants exchange

are given by the experienced users of CAD tools and ex-

their design examples with not only success stories but

perienced designers within a couple of hours to a couple

also their failure stories, in addition to invited talks. Weof days. Moreover, emails are accumulated and are open

expect students and professors who will start designs toto the VDEC users, as shown in Fig. 1.2, who have reg-learn kinds of know-hows. We have initiated “IEEE SSCS

istered VDEC accounts, as the important educational as-

Japan Chapter VDEC Design Award” this year, and final

sets. We expect all the VDEC users to make the full use of

examination and awarding have carried out during thethis mechanism to help solve problems.

“VDEC Designer’ Forum”. Ms. Y. Kanazawa(Hokkaido

We continue chip fabrication services on FDSOI

Univ.) is awarded as “IEEE SSCS Japan Chapter VDEC

CMOS 28nm by ST Microelectronics, 0.18mm CMOS

Design Award” winner, and Ms. S. Yokoyama(Hokkaido

by Rohm and 0.8μm CMOS by On-semi Sanyo Semi-

Univ.), Mr. A. Kameyama(Nara Institute of Science andconductor. And started chip fabrication services on SOTBTechnology), and H. Liu(Tokyo Institute of Technology)

CMOS 65nm by Renesas Electronics.

are awarded as “the best VDEC Design Award”, and Ms.

Our donated division “Design To Test(D2T)”, which

S. Tajima(Waseda Univ.), H. Kawauchi(Shizuoka Univ.),

was founded by donation from Advantest in Oct. 2008,

and T. Ikegami(Hokkaido Univ.) are awarded as thefocuses on enrichment of education on LSI testing and“VDEC Design Award.”

bridging between design and testing.

LSI designers come up against various difficulties dur-Fig. 1.3 shows trends of number of papers throughing actual LSI design scene, even after the basic educa-

VDEC activities. Number of papers is increasing, whichtions through various seminars and the forum. One ofmeans researches in the field of VLSI design have been

the biggest problems for beginners is the setup of CAD

encouraged after VDEC establishment.

softwares. Many of them also get confused by “EsotericFig. 1.4 shows number of papers related to CAD usage,

messages” come out from CAD softwares, even after they

chip fabrications and VDEC facility usages. CAD tools

successfully setup CAD tools. In such situations, VDEC

are widely used to write papers. CAD tools are used not

mailing-lists make significant contributions. VDEC users

only chip designs themselves but also used for preparation

can register to VDEC mailing-lists on CAD tools, andof chip fabrication and they contribute to verify funda-

process dependent groups through VDEC web pages, andmental ideas of researches. Advanced CMOS processes

can ask questions and helps on their facing issues. It is not

are preferred for publications, and not only papers witha responsibility for the registrant of such mailing-lists to

65nm/40nm CMOS chips, but also with 32nmCMOS,

1-1
Chapter1 Activity Report of VDEC

signer’ Forum” among young professors and students an-

Fig. 1.2 Archives of emails of VDEC mailing-list.

322nmCMOS and 14nmCMOS are emerging in theities such like LSI testers, FIB systems and EB writr for theworld. We would like to prepare chip fabrication services

wide spread of research purposes.

for the advanced CMOS processes. In addition, we would
like to setup chip fabrication services related to CMOS/MEMS to fulfill the researches for “More than Moore”.
1-1

We also encourage researchers to fully use of VDEC facil-

Chapter1 Activity Report of VDEC
Fig. 1.3 Trends of number of papers through VDEC activities.

Fig. 1.4 Number of papers related to VDEC facilities.

4

1.2 VDEC CAD Tools
other public universities, private universities, and colleges.

to the registered researchers in universities and colleges in

When one is going to use VDEC CAD tools and chipJapan. The CAD tools we provided in 2019 are shown

fabrication service (the details are described in Sectionin Table 1.2.1. The researchers can use those CAD tools

1-3), some faculty member of his/her research group inwhen their local machines, whose IP addresses are regis-

a university or a collage needs to do user registration.

tered in advance, are authorized by one of VDEC license

Figure 1.2.2 shows (a) the number of registrants, (b) theserver located in the ten VDEC subcenters shown in Fig-

number of distinguished universities/colleges of the reg-ure 1.2.1. For each CAD tool, VDEC provides 10-100

istrants, and (c) the number of registrants who applied

floating licenses. Those CAD tools can be utilized only for

VDEC CAD tools, (d) the number of applied licenses ofresearch and education activities in national universities,

all CAD tools.

Table 1.2.1 VDEC CAD tools
Name
Cadence tool set

Synopsys tool set

Mentor tool set
Silvaco tool set
ADS/Golden Gate
Bach system
LAVIS

Function
VendorVerilog-HDL/VHDL entry, Simlation, Logic synthesis, Cadence Design Systems, Inc.
Test pattern generation, Cell-based (including macros) place, route, and back-annotation, Interactive
schematic and layout editor, Analog circuit simulation, Logic verification, Circuit extraction
Verilog-HDL/VHDK simulation, Logic synthesis, Test Synopsys, Inc.
pattern generation, Cell-based (including macros)place, route, and back-annotation, Circuit simulation,
Device simulation
Layout verification, Design rule check
Mentor Graphics Co. Ltd.
Fast circuit simulation
SilvacoDesign and verification of high-frequency circuits
Keysight Technologies
BachC-based design, synthesis, and verification
Sharp
Layout visualization platform
TOOL

1-2
Chapter1 Activity Report of VDEC

Since 1996, VDEC has provided CAD software licenses

Fig. 1.2.1 VDEC Subcenters5

1.3 VLSI Chip Fabrication
1.3.1 Trends of VLSI Chip Fabrication Services

1-3

advanced CMOS process in 2013. We started SOTB

Fig. 1.3.1 shows a trend of number of designed

65nm CMOS by Renesas Electronics in 2015. We

chips for VDEC chip fabrication services, including

initiated two more chip fabrication trials in 2017, on

pilot project prior to VDEC establishment.

CMOS 0.6um HV from Ricoh, and CMOS 40nm

Chapter1 Activity Report of VDEC

VLSI chip fabrication is limited to 0.5mm CMOS
provided by NTT Electronics during the pilot project in 1994 and 1995. VDEC chip fabrication had
started in 1996 with 1.2mm CMOS provided byMotorola Japan, which is now On-Semiconductor aswell as the 0.5mm CMOS. In 1997, VDEC received
cooperation from Rohm and has started 0.6mm
CMOS process. In 1998, VDEC started chip fabrication services of 0.35mm CMOS by Hitachi, andin 1999, VDEC started 0.35mm CMOS by Rohm.
We had a test chip fabrication of 0.13mm CMOS by
STARC through “IP development project” in 2001.
We added 0.18mm CMOS by Hitachi into our chip(a) Trend of number of designs fabricated.

fabrication menu in 2001. From 2002, we started
VDEC-MOSIS chip fabrication program initiated by Prof. Iwata of Hiroshima University. Under
this program, VDEC member can access to TSMC
and IBM processes with lower price. We also started
Bipolar chip fabrication by NEC Compound Semiconductor Devices. In 2004, we started 0.15mm
SOI-CMOS chip fabrication by Oki Electric as test
chip fabrications. In the same year we started 90nm
CMOS chip fabrication by ASPLA/STARC. In 2006,
we started 0.18mm CMOS by Rohm and 0.25mm
SiGeBiCMOS by Hitachi. In 2008, we started 65nm
CMOS process by eShuttle, after closure of 90nm
CMOS chip fabrication in 2007. In 2010, we start-(b) Trend of designed area.

ed 40nm CMOS process by Renesas Electronics
through “Next Generation Semiconductor Circuits& Architecture” project between METI and STAR.
On the other hand, 1.2mm CMOS chip fabrication
program came to end by the September 2011. 40nm
CMOS by Renesas Electronics and 65nm by eShuttle also come to end by Oct. 2012 and Aug. 2013,
respectively. We started CMOS0.8μm in Oct. 2012by On-semiconductor-Sanyo as a test chip fabrication and opened it as the regular chip fabrication
menu in 2012. We started FD-SOI 28nm CMOS
by ST-Microelectronics through CMP, France, as the(c) Trend of designed area normalized by design rule.
Fig. 1.3.1 Trend of number of designs and designed chip area.

6

from Mie Fujitsu.

who have contracted NDA for process technologies

Fig. 1.3.1(a) shows trends of number of chipto access design rules and design libraries are, 88,

designed for VDEC chip fabrication. For the first

287, and 48, respectively, for 65nm CMOS, 0.18

6 years until 2001, the number of designed chips

mm CMOS, and 0.8um CMOS.

shows steady increase, which means drastic improve
1.3.2 Overview of chip fabrication in 2018of the effectiveness researches and education of LSI

Table 1.3.1 lists chip fabrication schedule in 2018.

students related to LSI chip design and education.

Please refer to list in Chapter 2 for details of design-

During few years of stable number around 400 chipers and contents of chip designed.

designs per year, we can see transition of designs toward finer process. In 2007, we saw a large drop,
which was caused by sudden process transition from0.35mm CMOS to 0.18mm CMOS, and in 2008,
we also saw another drop by process transition from
90nm CMOS to 65nm CMOS.
Fig. 1.3.1(b) shows trends of designed chip area,
which shows much clear trends of drop by process

1-3
Chapter1 Activity Report of VDEC

design, and we assume drastic increase of number of

migration. On the other hand, Fig. 1.3.1(c) shows
trends of designed chip area normalized by design
rule, which assume to be strong relation with design
efforts. Coming from the fact that the normalized
chip area is still growing, we assume the major reason for decrease of number of chips and designed
area is increase of design effort per chip and per unit
area due to process scaling.
Fig. 1.3.2 shows trends number of professors andFig. 1.3.2 Trend of number of processors and universities
fabricated chip.

universities fabricated chip. Number of professors

Table 1.3.1 Chip fabrication schedule in 2017
o0.8μm CMOS (On-Semiconductor - Sanyo)2018 #1

Chip application deadline
2018/7/9

Design deadline
2018/9/10

Chip delivery
2018/12/24

2018 #2

2019/1/15

2019/3/25

2019/6/E

o0.18μm CMOS (Rohm)
Chip application deadline
2018 #1
2018 #4
2018 #2
2018 #3

2018/4/2
2018/6/18
2018/8/13
2018/12/3

Design deadline
2018/6/25
2018/9/10
2018/11/5
2019/2/25

Chip delivery
2018/9/26
2018/12/14
2019/2/15
2019/6/3

oSOTB 65nm CMOS
Chip application deadline

2018 #1
2018 #2

2018/6/18
2018/12/17

Design deadline

2018/7/28
2019/2/23

Chip delivery

2019/1/28
2019/7E

71.3.3 Libraries and design flows

for analog design. Table 1.3.2 lists libraries available

VDEC have been working to prepare design li-

now.

braries and design flows for digital design and PDKs

Table 1.3.2 Libraries available for VDEC chip fabrication
1-3
Chapter1 Activity Report of VDEC
8

Technology

0.18μm CMOS
(Rohm)

Name

AuthorRohm
library

Rohm Library
Std. Cells, IO cells, RAM(Distributed with CDROM)

Kyodai
Library

Onodera Lab., Kyoto University

Todai
Library

VDEC
Design flow based on library prepared by
Onodera Lab., Kyoto University

PDK

VDEC

Contents
Synthesis(Synopsys)
Simulation(VerilogXL)
P&R(LEF/DEF)
Synthesis(Synopsys)
Simulation(VerilogXL)
P&R(Astro)
Synthesis(RTL Compiler)
Simulation(VerilogXL)
P&R(Encounter)
PDK(IC6.1)

1.4 Seminar
kyo VDEC in August and September in 2018. This

LSI design technology. In 2018, VDEC has held sev-

seminar took 4 days for 2 Cadence tools, 1 days foreral seminars and a forum including technical sem-

1 Synopsys tool, 1 day for 1 Keysight tool. In ad-

inar for CAD users, refreshing seminar for working

dition, VDEC teachers gave lecturers on transistor

people, and designer’s forum for young professors

level circuit design course, and digital circuit designand students.

course under the VDEC EDA design environment.
Up to 40 students on average attended each course.

【Technical Seminar for CAD Users】

Moreover, another technical seminar for CAD users

In technical seminars for CAD users, VDEC in-for matured teachers and students was held in Marchvites lecturers from tool venders including Cadence,by Cadence for 4 days, Synopsys for 3 days (Table

Synopsys and Keysight to give lectures on the use of

1.4.1). The demand for these CAD technical semi-

CAD tools. VDEC also provides the courses on thenars is large, and VDEC has organized such a large-

design flow under the VDEC design environment

scale CAD technical seminar toward this situation.

by their staffs. A technical seminar for CAD users

The seminar was held in the University of Tokyo andfor the beginner was held in The University of To-

other VDEC branches simultaneously.

1-4
Chapter1 Activity Report of VDEC

Seminars are indispensable as the advancement ofTable 1.4.1 CAD technical seminar in 2018 fiscal year
Date
8/21
8/21
8/21
8/21
9/10
9/10
9/10
9/10
9/18, 19
9/18, 19
9/18, 19
9/18, 19
9/20, 21
9/20, 21
9/20, 21
9/20, 21
3/1
3/1
3/1
3/1
3/1
3/4
3/4
3/4
3/4
3/4

SeminarKeysight ADS Fundamentals
Keysight ADS Fundamentals
Keysight ADS Fundamentals
Keysight ADS Fundamentals
Synopsys Verdi
Synopsys Verdi
Synopsys Verdi
Synopsys Verdi
Cadence Virtuoso Layout Suite-L
Cadence Virtuoso Layout Suite-L
Cadence Virtuoso Layout Suite-L
Cadence Virtuoso Layout Suite-L
Cadence Virtuoso Digital Implementation
Cadence Virtuoso Digital Implementation
Cadence Virtuoso Digital Implementation
Cadence Virtuoso Digital Implementation
Synopsys Designer Compiler
Synopsys Designer Compiler
Synopsys Designer Compiler
Synopsys Designer Compiler
Synopsys Designer Compiler
Cadence AMS DesignerCadence AMS DesignerCadence AMS DesignerCadence AMS DesignerCadence AMS Designer

Venue
The Univ. of Tokyo
Nagoya Univ.
Akita Prefectural Univ.
Shinshu Univ.
The Univ. of Tokyo
Kyoto Univ.
Hiroshima Univ.
Shinshu Univ.
The Univ. of Tokyo
Nagoya Univ.
Akita Prefectural Univ.
Shinshu Univ.
The Univ. of Tokyo
Kyoto Univ.
Osaka Univ.
Shinshu Univ.
The Univ. of Tokyo
Kanazawa Univ.
Nagoya Univ.
Hiroshima Univ.
Shinshu Univ.
The Univ. of Tokyo
Kanazawa Univ.
Nagoya Univ.
Kyoto Univ.
Hiroshima Univ.

Attendees
8
4
6
11
7
2
1
7
18
8
6
20
15
5
3
19
18
1
4
2
4
14
0
2
2
1

9

1-4
Chapter1 Activity Report of VDEC

3/4
3/6
3/6
3/6
3/6
3/6
3/6
3/26, 27
3/26, 27
3/26, 27
3/26, 27
3/26, 27
3/28, 29
3/28, 29
3/28, 29
3/28, 29
3/28, 29
3/28, 29

Cadence AMS DesignerCadence Genus
Cadence Genus
Cadence Genus
Cadence Genus
Cadence Genus
Cadence Genus
Synopsys IC Compiler II
Synopsys IC Compiler II
Synopsys IC Compiler II
Synopsys IC Compiler II
Synopsys IC Compiler II
Cadence Spectre RF
Cadence Spectre RF
Cadence Spectre RF
Cadence Spectre RF
Cadence Spectre RF
Cadence Spectre RF【Refresh Seminar for Working People】

4
16
0
1
1
3
3
18
1
3
3
4
14
1
1
3
8
3

with wide support from various societies.

Teachers of universities and designers in the first

Course A: analog integrated circuit design (6/18-

line of the enterprise were invited to the lecturer at20), Course M1: MEMS design (7/9-10), Course"VLSI design refresh seminar" which was held aim-

M2: MEMS fabrication (7/23-25), and Course R:

ing at the latest, advanced knowledge and technical

RF circuit design (7/18-19). Teachers from indus-

learning concerning VLSI design as a refreshing edu-

try and universities involved in the integrated cir-cation for working people involved in the integrated

cuit research and the education were invited as thecircuit industry (Table 1.4.2). Started in year 1998,

lecturers, and they introduced a state-of-the-art andthe seminar has been mainly supported by Minis-

practical VLSI design knowledge and methodology.

try of Education Technical Education Division on

The participants for the course A, M1, M2, R were

purpose of giving practicing education of the latest

8, 11, 4, 6, respectively.

VLSI design technology, it is now being continued

10

Shinshu Univ.
The Univ. of Tokyo
Kanazawa Univ.
Nagoya Univ.
Kyoto Univ.
Hiroshima Univ.
Shinshu Univ.
The Univ. of Tokyo
Kanazawa Univ.
Nagoya Univ.
Hiroshima Univ.
Shinshu Univ.
The Univ. of Tokyo
Kanazawa Univ.
Nagoya Univ.
Hiroshima Univ.
Shinshu Univ.
Akita Prefectural Univ.

1-4
Chapter1 Activity Report of VDEC

Fig. 1.4.2 Refresh Seminar at VDEC seminar room at the University of Tokyo, VDEC.

Table 1.4.2 Refresh Seminar
Course A: Analog Circuit Design (3 days)
Analog Circuit Design and simulation
Integrated Circuits Verification (LVS, DRC)
Masahiro Sugimoto (Chuo Univ.), Hidetoshi Onodera(Kyoto Univ.), Koji Kotani (Tohoku Univ.)
Course M1: MEMS Design (2 days)
MEMS Basic 1: Fabrication Process
MEMS Basic 2: Operation Principle
Structural Design
Layout Design
Yoshio Mita (Univ. of Tokyo)
Course M2: MEMS Fabrication (3 days)
CAD Design and Analysis
Lithography, Etching, Release
Vibration measurement and analysis
Yoshio Mita (University of Tokyo)
Course R: CMOS-RF Circuit Design (2 days)
Modulation/Demodulation, Cascaded connection
Basic Performance, Transceiver Architecture
Circuit Element, Design Flow
Hiroyuki Ito (Tokyo Institute of Technology)

11

1-4
Chapter1 Activity Report of VDEC
12

【Designer’s Forum for Young Teachers and Students】

an LSI designer had been through and the solution,

VDEC LSI designer forum intended for students

the inside story of CAD industry, and the construc-and young teachers were held. The VDEC LSI de-tion method in the design milieu in the laboratory.

signer forum has aimed to sharing the information

In this year, we held the forum in Noboribetsu Hot

that generally hard to be obtained common techni-

Spring in September. 27 participants were attended

cal reports or academical papers, such as the failure

the forum.

Table 1.4.3 Program of Designers Forum in 2018
Sep. 27
12:00-12:30
12:40-14:20
14:30-16:10
16:20-17:40
19:00Sep. 28

AgendaReception
VDEC Design Award Presentation I
VDEC Design Award Presentation II
VDEC Design Award Presentation III
VDEC Design Award Ceremony

9:00-10:00
10:00-12:00
12:00-13:00
13:00-13:10

Idea Contest Presentaion
Ph.D Session
Plenary Talk
Closing

1.5 Facilities
Major apparatuses purchased through VDEC anduniversities in Japan from its establishment (1996).

affiliated laboratories courtesy include: 3D Laser mi-

Big facilities refer to those which are impossible tocroscope (Olympus OLS-5000), Digital Microscopes

acquire and or maintain by an individual research(Keyence VHX-6000, VHX-7000), Laser direct li-

unit. Table 1.5.1 shows the available facilities of VLSI

thography machine (Heidelberg DWL66+), Parylene

testers and some process machines, which are placed

Coarter (SCS PDS2010), High Density Generalat the tester room (VDEC 104), the super clean

Purpose Load-Lock Sputtering Machine (CFS-4EP-

room, the backend process room (VDEC 204) of theLL), and Nickel Electroplating Bath. Also, in collab-

Takeda building. In 2004, the VLSI tester (T2000)

oration with Faculty of Engineering, an Auger Elec-and the EB lithography machine (F5112+VD01)

tron Spectroscopy Apparatus (AES, ULVAC Phi680)

were donated to the VDEC by the ADVANTEST.

is also installed.

In the year 2012, VDEC joined MEXT (Ministry of

The facilities can be used by user himself, after a

Education)’s Nanotechnology platform to enforce its

couple of times’ training by attendance of licensed

multi-use capability. (For Nanotechnology Platform

users; also, by presence of licensed persons, a newrefer section 1.8).

user can readily use the machine.

Table1.5.1
Facility

Logic LSI test
SystemAvailable facility list
Equipment nameEB tester:
IDS10000

LSI tester:
ADVANTEST
T2000
Auto prober:PM-90-A

Analog/RF
measurement
system

1-5
Chapter1 Activity Report of VDEC

The VDEC has been providing the big facilities for

Analog/RF measurement system:
B1500A, 4156B,
HP4284, etc
Low-noize manual
prober:Low-noize, temperature controlled
semi-auto prober:
Süss Microtec

Description

StatusContact

The chip surface voltage during operation can bemeasured with the LST tester.
The digital circuit with 384 pins, 1GHz can betested.
The digital circuit with 256 pins, 512MHz can betested. Analog test is optional.

Available

nanotech@sogo.t.u-tokyo.ac.jp

Available

nanotech@sogo.t.u-tokyo.ac.jp

Automated prober for testing LSI wafers, which
can be used with the LSI testers. The probe card for
LSIs with the VDEC standard pin connections isavailable.
DC parameter measurement, Capacitance measurement, Network analyzer, Spectrum analyzer, etc.

Available

nanotech@sogo.t.u-tokyo.ac.jp

Available

nanotech@sogo.t.u-tokyo.ac.jp

6 inch wafer can be measured with six DC probles
and two RF probes upto 50 GHz.
8inch wafer can be measured. The chip temperature
range is -50 to 200℃.

13

Nanotechnology Platform
Apparatuses

1-5
Chapter1 Activity Report of VDEC
14

FIB system

Mask lithography,
Direct lithography:
F5112+VD01

Minimum linewidth: 50nm.
Lithography for 5 inch photomask (thickness: 2.3mm), 2-8 inch wafers, and chips is possible.

Available

Rapid Mask andDirect lithography:
F7000S-VD02

Minimum linewidth: 1xnm.
Lithography for 5 inch photomask (thickness: 2.3mm), 2-8 inch wafers, and chips is possible. Stencil
character projection of non-square shapes such as
circle, triangle is possible.

Available

Chlorine ICP plasma etcher CE-S

High density plasma etching with Cl2 and BCl3 ispossible.

Available

Silicon DRIEHigh speed, high aspect ratio etching of silicon is
MUC-21 ASE-Peg- possible
asus

AvailableFIB:
SII XVision200TB

Repair of photomask, sample etching, etc. (Through Available
Nanotech. Platform and LCNet)

LSI FIB system FIB: FEI V400ACE Repair of VLSI from both frontside and backside,
Availablewith CAD navigation and / or IR camera is possible.
W/SiO2 deposition is possible.
Chip Bonding Wedge Bonder:
SystemWestbond 7476D

25µmφAl or Au wire wedge bonding machine.

Epoxy Die Bonder
Westbond7200C

Precision Manupilator system. Epoxy and or Ag
paste chip bonding and or glued wiring.

Semi-Auto Bonder
Westbond4700E

18〜25µmφAu Ball bonding or bump creation.

Precision Manual
Flip-Chip Bonder Finetech Fineplacer Lambda

Face-to-face bonding up to 15mm square chips.
Alignment is through video camera. Bonding is byheating chips with TV camera. (Ultrasonic Unit can
additionally be purchased.) XY±0.5µm, and θ=1mrad precision.

Available

nanotech@sogo.t.u-tokyo.ac.jp

1.6 Activity plan for 2019
VDEC will continue activities on chip fabrication

We will continue analog RF design environment,

services, CAD tool support, dispatching design re-GoldenGate and ADS by Agilent, C-based design

lated information and donated division “D2T”, as

environment, BachC by Sharp. In addition, we con-has been previous years.

tinue trial of several CAD tools, such as layout plat-

1-6

form, Lavis by TOOL. Design debugging platform

Chapter1 Activity Report of VDEC

【Design related information dispatching/Seminar】

from SpringSoft has merged into Cadence tools andWe will continue holding the following seminars:

will be continued. SmartSpice by Silvaco, will be also

(1) CAD tools seminars which have been continued

continued.

since 1997, (2) “Refresh seminar” since 1998, (3)【Chip fabrication services】“Designer’ Forum” since 1997. We will also continue
seminars for LSI tester usage at VDEC and sub-cen-

We will continue chip fabrication services forters, workshops on LSI testing technologies initiated

SOTB 65nm CMOS by Renesas Electronics,

by D2T.

0.18mm CMOS by Rohm, FD-SOI 28nm CMOS
by ST Microelectronics through CMP and 0.8mm【CAD tool support】

CMOS by On-semiconductor-Sanyo as the regular

We will continue Cadence tools, Synopsys tools

services.

and Mentor tools as the main stream design tools.

Table 1.7.1 Chip fabrication schedule【CMOS 1.2μm 2P2M】 On-Semiconductor(Former Motorola Japan)
Chip application deadline
2019#12019#2

2019/7/8
2020/1/6

Design deadline
2019/9/30
2020/3/30

Chip delivery
2019/12/23
2020/6/29【CMOS 0.18μm 1P5M(+MiM)】 Rohm
Chip application deadline
2019 #1
2019 #2
2019 #3
2019 #4

2019/4/1
2019/6/17
2019/8/5
2019/12/2

Design deadline
2019/6/24
2019/9/9
2019/10/28
2020/2/24

Chip delivery
2019/10/11
2019/12/27
2020/2/14
2020/6/12【FD-SOI CMOS 28nm 1P10M】ST Microelectronics
Based on the chip fabrication schedule through CMP.

15

【SOTB CMOS 65nm】 Renesas Electronics
Chip application deadline

1-6
Chapter1 Activity Report of VDEC
16

Design deadline

Chip delivery

2019 #1

2019/6/17

2019/7/29

2020/2/1

2019 #2

2020/1/27

2020/3/9

2020/9/5

1.7 Venture companies related to VDEC
Some professors related to VDEC started venture companies. The following is a list of the venture companies
related to VDEC.
[1] AIL Co.,Ltd. (http://www.ailabo.co.jp/)
Description of business : (1) LSI design service(2) Engineer dispatching service[2] Synthesis Corporation(Merged with Soliton Systems on July 1st in 2017, http://www.synthesis.co.jp/)
Related professor : Professor Emeritus Isao Shirakawa, Osaka Univ. (Director)
Description of business : (1) System LSI development and design service(2) IP development and sales(3) Development and sales of IPs(4) Development of EDA tools

1-7
Chapter1 Activity Report of VDEC

Related professor : Professor Kazuo Taki, Kobe Univ. (Representative Director)[3] ASIP Solutions (http://www.asip-solutions.com/)
Related professor : Professor Masaharu Imai (Representative Director, CTO)
Description of business : (1) R&D, education and consulting of IoT application system(2) Sales of ASIP design tool and consulting of ASIP development[4] Nanodesign Corporation (http://www.nanodesign.co.jp/)
Related professor : Professor Kazuyuki Nakamura, Kyushu Institute of Technology. (Representative Director)
Description of business : (1) LSI design and development(2) Design consulting, etc.
[5] A-R-Tec Corp. (http://www.a-r-tec.jp/)
Related professor : Professor Emeritus Atsushi Iwata, Hiroshima Univ. (Representative Director)
Description of business : (1) Design and measurement of IC and evaluation board(2) Crosstalk noise analysis(3) Develop human resources for new employees and beginners[6] Ishijima Electronics (http://ishi.main.jp/)
Description of business : (1) Electronic circuit and board development(2) Software development(3) Consulting

17

1.8 “ Nanotechnology Platform”: Ultra Small Lithography and NanometricObservation Site

1-8
Chapter1 Activity Report of VDEC

VDEC is operating an open-use nanotechnology

search reports and machine use. The University ofplatform “Ultra Small Lithography and NanometricTokyo site has received 153 research reports from

Observation Site” together with the Institute of En-

139 research groups. As shown in the Fig. 1, usage

gineering Innovation of Graduate School of Engi-

is monotonously increasing. “Open ratio”, which isneering. The site is supported by Japanese Ministry

the number of days in which users outside the Uni-

of Education (MEXT)’s Nanotechnology Platformversity of Tokyo came, divided by machine open

grant. Any researchers in Japanese Universities, Lab-days, was 99%. Due to the strong support of nano-oratories, and Companies can take full advantage oftech. Platform, even a novice user can obtain fine

The University of Tokyo’s cutting-edge nanotech-lithography result by using the apparatuses with the

nology apparatuses and know-hows. The accessible

Platform engineering staffs of VDEC. Consequently,

technology includes Lithography and Etching envi-

free machine time is decreasing so the team is trying

ronment, Ultra High-Voltage Acceleration (1MV)

to acquire financial support to increase the number

transmission electron microscope (TEM) that is ca-

of machines. Also from FY2017 to 2018, the French

pable of visualizing upto light materials such as Ni-

Nanotechnology Network project CNRS-RENAT-

trogen. VDEC takes part in the lithography at Take-ECH asked to the UTokyo VDEC to launch an en-

da Sentanchi Super Cleanroom. Through VDEC’s

gineer-class international exchange program. The

key apparatus F5112+VD01 donated from Advant-program is financially fully supported by VDEC’s

est Corporation as well as F7000S-VD02 purchased

project and one Ph.D-holding research engineer

by national budget, VDEC is supporting post-VLSI

from France (FEMTO-ST, Besançon) is with VDEC

activities such as MEMS. The machine is capable ofMita Lab for one year.

rapidly writing patterns on arbitrary-shaped targets
sizing from 1cm-sqare chip to 8-inch round wafers.

URL:http://nanotechnet.t.u-tokyo.ac.jp/

The performance is measured by the number of re-

Figure 1: Monthly Average Exposure Count of EB Machine (s).

18

Chapter2

Activity Report of ”ADVANTEST D2T Research Division”

2.1 Introduction of ADVANTEST D2T Research Division
2.1.1 Aim of the establishment of
ADVANTEST D2T Research Division
tablished in VDEC in October 2007. As the namesuggests, it is financially supported by ADVANTEST Corporation.

project phases, and now we are in the 4th phase of
the D2T project courtesy of ADVANTEST Corporation.
In this financial year, we invited Professor Adit
Singh from Auburn University (2018/1 – 5) and

The aim of establishment of the ADVANTEST

Professor Kalla Priyank (2018/5 – 8) from Universi-

D2T research division is to promote the researchty of Utah for research and educational collaborationand education environment of VLSI testing in allwith VDEC.

universities and colleges in Japan. “D2T” meansthat we consider not only design but also testing.

The details of our group’s activities are presented
in the following sections.

Through our activities, we hope to provide expertisein design and testing for the industry. In addition,
we are exchanging researchers with other universities

2.1.2 M embers of ADVANTEST D2T
Research Divisionand research institutes in both Japan and overseas.

Project Professor

Masahiro Fujita

Moreover, the D2T research division is suitable for

Project Professor

Adit Singh (2018/1~5)

collaborations with the industry because the testing

Project Professor

Kalla Priyank (2018/5~8)of VLSI is one of the most practical research topics

Project Lecturer

Akio Higoin the industry. Based on these activities, our final

Researcher

Koji Asami

goal is to become a center of excellence of VLSI testing in Japan.
The D2T research division has spent 10 years in(ADVANTEST Corporation)
Researcher

Takahiro Yamaguchi

Assistant Clerk

Makiko Okazaki

2-1
Chapter2 Activity Report of “ADVANTEST D2T Research Division

The ADVANTEST D2T research division was es-

2010 – Sep. 2013), and 3rd (Oct. 2013 – Sep. 2016)

total for the 1st (Oct. 2007 – Sep. 2010), 2nd (Oct.

192.2 Report of 13th D2T Symposium
The 13th D2T Symposium was held on September
26th, 2018 at Takeda Hall.

2-2
Chapter2 Activity Report of “ADVANTEST D2T Research Division
20

Hong Kong University of Science and Technology
and Prof. Adit Singh from Auburn University. The

This year, we invited four lecturers from overseas

symposium also featured lectures by Assoc. Prof.

for their work on research topics related to biosys-

Yasuyuki Ozeki and Assoc. Prof. Agnes Tixier-Mita

tems, RF, IoT and machine learning: Assoc. Prof.

from the University of Tokyo.

Gilgueng Hwang from CNRS, University of Par-We sincerely appreciate every participant for theiris-Saclay, Prof. Sule Ozev from Arizona State Univer-contribution at the symposium. We look forward tosity, Prof. Abhijit Chatterjee from Georgia Instituteseeing many participants again at the next symposi-of Technology, Prof. Kwang-Ting (Tim) Cheng fromum.

13th D2T Symposium program
10:00 Opening Remarks

Masahiro Fujita (Director, VDEC, The University of Tokyo)
Toshiyuki Okayasu (Executive Officer, Senior Vice President, New Concept Product Initiative, ADVANTEST Corporation)
10:30 Session 1 (Chairperson: Akio Higo, VDEC, The University of Tokyo)

12:30 Lunch
14:00 Session 2 (Chairperson: Tetsuya Iizuka, VDEC, The University of Tokyo)"Ensuring Product Quality through Design for Test for Embedded Circuits"
Sule Ozev(Arizona State University)"Power-Performance Aware, Off-Line and On-Line Adaptation of Mixed-Signal/RF Circuits and Systems: A Machine
Learning Assisted Approach"
Abhijit Chatterjee (Georgia Institute of Technology)

15:30 Break
16:00 Session 3 (Chairman: Masahiro Fujita, VDEC, The University of Tokyo)"Hardware Security - Verification, Test, and Defense Mechanisms"
K.-T. Tim Cheng (Hong Kong University of Science and Technology)"Are System Level Tests Unavoidable for High End Processors?"
Adit Singh (Auburn University)
Session 4"Activities of D2T research division"
Akio Higo (VDEC D2T, The University of Tokyo)

17:45 Closing
18:00 Reception

2-2
Chapter2 Activity Report of “ADVANTEST D2T Research Division"On-chip micro/nanorobotic swimmers towards biomedical applications"Gilgueng Hwang (CNRS, University of Paris-Saclay)"Large-scale biological imaging of cells with ultrafast lasers"
Yasuyuki Ozeki (Dept. of EEIS, The University of Tokyo)"Thin-Film-Transistor Technology: Display Technology for Biological Applications"
Agnes Tixier-Mita (RCAST, The University of Tokyo)

21

2.3 Research Activity Reports of ADVANTEST D2T Research Division
High-Resolution

Analog-to-Digital

Converter

Based on Stochastic Comparators

2-3

ity has been confirmed by the simulation. This research results have been submitted to IEEE journal

Chapter2 Activity Report of “ADVANTEST D2T Research Division

Takahiro J. Yamaguchi, Parit Kanjanavirojkul,

as a technical paper. In the next step, we plan to

Rimon Ikeno, Tetsuya Iizuka, Kunihiro Asada

apply the theory to further investigation of the noiseThis project aimed to implement a high-resolution

budget in the measurement system, and to develop

sub-ranging analog-to-digital converter (ADC) cir-experimental circuits. We will also investigate thecuit based on stochastic comparators.

practical issues such as measurement error and com-

Process variations, together with many factors

pensation methods.

such as variations in voltage or temperature, leadto mismatched design parameters that produce input-referred offsets and hence cause non-linearity

High-Throughput

andHigh-Accuracy

Elec-and missing output codes in an ADC. Instead of at-tron-Beam Direct Writing (EBDW) Strategy for

tempting to suppress such process variations as in

Wide Range of EBDW Applications

conventional ADC, the stochastic ADC approach

Akio Higo, Yoshio Mita, Masahiro Fujita

exploits process variations based on the assumption

Maskless lithography by electron-beam directof a Gaussian distribution of comparator offset volt-

writing (EBDW) is expected to be a low-cost lithog-

age. We identified the root cause of a voltage bounce

raphy technology with a short turn-around timeof the source nodes of the comparator input PMOS-(TAT), but it has some drawbacks such as a low pro-

FETs, which introduces a conversion error of thecess throughput and low accuracy against the intend-

flash ADC circuit at the first stage in our sub-ranging

ed layout shapes. We are pursuing a high-speed and

ADC system, as quick signal transition. In order tohigh-accuracy EBDW strategy utilizing the character

validate the detection theory using median of prob-

projection (CP) method to overcome these concerns

ability, numerical experiments have been performed.

and to boost EBDW use in fields such as MEMS and

The experiments use N comparators and detect lev-

photonics.

el-crossing times of a ramp, under the condition of

We investigated the fabrication process for theexternal noise = zero, non-zero internal noise withhigh-resolution observation of lithographic results

various process variations.

by our high-throughput and high-accuracy EB exposure strategy that combines the CP and varia-

High-Performance Analog-to-Digital Conversion

ble-shaped beam (VSB) methods. A new CP mask for

Using the Wideband Spread Spectrum and Its Ap-

the F7000S EB writing system in the VDEC Takeda

plication

Clean Room was designed for further performance

Koji Asami, Byambadorj Zolboo, Akio Higo,

improvement. We also measured silicon wire optical

Tetsuya Iizuka, Masahiro Fujita

waveguides for the propagation loss of dependent on

To measure low-cost RF devices for IoT and oth-the line-edge (wall) condition.

er applications, analog-to-digital conversion techniques with a low cost and high efficiency are required. To acquire narrow-band modulation signals
scattered in a wide frequency range, a compression
sampling method is studied.
In this financial year, a configuration to implement a modulated wideband converter in automatic
test equipment (ATE). The theoretical equation of
the noise figure has been constructed, and its valid-222.4 Publications
International Conferences, Symposiums, Workshops[1]

A kio Higo, Tomoki Sawamura, Makoto Fujiwara, Etsuko Ota, Ayako Mizushima, Eric
Lebrasseur, Taro Arakawa, and Yoshio Mita,”Ature to Optimize Pattern Approximation in
Direct Lithography Technologies”, 2019 IEEE
Conference on Microelectronic Test Structures(ICMTS 2019), Kita-Kyushu, Japan (2019.03)

2-4
Chapter2 Activity Report of “ADVANTEST D2T Research Division

Micro Racetrack Optical Resonator Test Struc-23

Research in VDEC

Chapter3

Fujita Laboratory(http://www.cad.t.u-tokyo.ac.jp/)

3-1

High-level description generation method for ECO
and its application
Masahiro FUJITA, Amir Masoud GHAREHBAGHI,"Application of Partial Synthesis to Program Par-

Qinhao WANG, Yusuke KIMURA,

allelization"

In VLSI design, ECO (Engineering Change order)

Chapter3 Research in VDEC

Masahiro FUJITA, Yukio MIYASAKA, Ashish MITTAL

may happen after optimizing a gate-level circuit. In

In recent years, many studies have been conduct-

this case, designers need to modify the gate-level cir-ed to apply the partial synthesis method, which has

cuit directly in order to preserve the optimization

been used for logic circuit synthesis, to program

effort spent so far. In this research, we presented asynthesis. In this study, we proposed to synthesize

method to generate a corresponding high-level de-parallel programs from single-threaded programs ac-

scription utilizing the modified gate-level circuit.

cording to parallel processing environment. For the

The experimental results show that the method can

problem that parallelization of a large program does

be applied to the AES256 encryption program.

not end in real time, we reduced the search space ofsynthesis problem by imposing constraints based on

Signal fan-in selection for debugging logic circuit

the solution obtained by parallelization of a small

Masahiro FUJITA, Amir Masoud GHAREHBAGHI,

program, and the problem became feasible.

Yusuke KIMURA
When a bug found in gate-level circuit in VLSI de-

An optimization method of systems with template

sign process, the designers sometimes need to mod-and state transition expression

ify the gate-level circuit directly with small changes.

Masahiro FUJITA, Akihiro GODA

In this research, it is assumed that the gates (targets)

A formal verification of sequential circuits is muchto be modified are known, and the method to se-more difficult than that of combinational circuits

lect fan-in signals for correction is proposed. Our

because a sequential comparison of inputs and out-

proposed method can get a good quality solution

puts is necessary in the case of sequential circuits. A

for multiple targets, and the experimental resultsformal verification of an FSMD (Finite State Ma-

show that the method can be applied to the existing

chine with Data-path) is also difficult since it in-benchmark circuits within practical time.

herently represents a sequential circuit. Therefore, averification method of an FSMD, “Karfa’s method”,

Partial Logic Synthesis

is proposed, which can execute an efficient formal

Masahiro FUJITA, Amir Masoud GHAREHBAGHI,

verification of an FSMD although it is false nega-

Xiaoran HAN

tive. And thanks to that, a partial synthesis method

Partial logic synthesis is to synthesize the vacantof any systems, “Template-based Synthesis”, became

portions in the given entire circuit and has been for-to be able to be applied to an FSMD. In this work,

mulated with QBF (Quantified Boolean Formula)

the FSMD synthesis method is proposed with Karfa’s

using LUT (Look up Table). As LUT can practicallymethod and Template-based Synthesis. Moreover, we

represent maximum 16 or so inputs, the vacant por-show that the synthesis with the proposed method istions cannot have large number of inputs. In thispossible in the experiments.

work, we show a way to partial synthesis by using
SOP (sum of product) and POS (product of sum)based QBF formulation. Any SOP/POS formulaewith n variables and m products/sums are represented by a set of coefficients which are associated24with literals, and the synthesis problem is to find

Ikeda Laboratory

appropriate values for the coefficients by solving(http://www.mos.t.u-tokyo.ac.jp)

the QBF problems. The SOP and the POS perform

Current Research Projects

better than the previous LUT based QBF method
when the vacant portions have more than 16 inputs,

Design of High-Performance Cryptographic Pro-

however, depending on the circuit, the performancecessor
M. Ikeda, H. Awano, S. Sugiyama, and F. Arakawa

experiments on ISCAS89 circuits. The SOP based

We have studied scalable functional encryption en-

QBF method can synthesis up to 27 inputs, the POS

gine applicable for cloud to sensor-nodes. For cloud

based method can synthesis up to 24 inputs.

applications, we have investigated fully homomorphic encryption, which makes any calculation possi-

Template-Based High-Level Partial Synthesis

ble to be on cipher-text space, is essential technique

Masahiro FUJITA, Amir Masoud GHAREHBAGHI,

for complete secrecy of personal information. But

Qinhao WANG

it still needs speeding up for practical use. In thisIn this work, we present a techniques to automati-

study, we investigated large-scale batch processing

cally adjust Register-transfer level (RTL) implemen-of polynomial operations on hardware such as ASIC

tation for Engineering Change Order (ECO) in highand FPGA or GPGPU. In ASIC implementation, welevel. Our method focuses on the datapath structure,achieved 1.45 times faster than CPU implementa-

where circuit topologies are mostly, and only partial

tion. On the other case, in sensor-node, public-key

portions are replaced by programmable datapath.

cryptography design in limited hardware resources

Exploring the correct configuration of the datapath

is required. For example, 256-bit multiplication isis formulated as Quantified Boolean Formula (QBF)

divided into several 32-bit or 16-bit multiplications.

problem, and can be solved by using Satisfiability

For further speed and area efficiency, we proposed an(SAT) /Satisfiability Modulo Theories (SMT) solver

implementation of Montgomery multiplication us-

in an incremental way automatically. The experimen-

ing 256-bit times 2-bit multiplier, and achieved 2.3

tal results with several example cases have confirmed

times faster and 2.5 times more area-efficient thanthat effectiveness of the proposed method.

32-bit multiplier.

Automatic Test Pattern Generation for Double

Design of Functional Cryptographic Processor

Stuck-at Faults Based on Test Patterns of Single

M. Ikeda, H. Awano, T. Ichihashi, K. Koga,

FaultsC. Cai, and R. Nakayama

Masahiro FUJITA, Amir Masoud GHAREHBAGHI,

3-1
Chapter3 Research in VDEC

is different. We have performed the partial synthesis

Recently, with the popularization of IoT, thePeikun WANG

amount of intensive data in the cloud space has in-

In this work, an improved incremental ATPG

creased explosively, and simple data encryption canmethod is proposed for DSA faults. Four steps of theno more solve a wide range of security risks. Paillier

proposed method are introduced, including the cir-Cryptography is a kind homomorphic, functional

cuit initialization, ATPG initialization, finding thecryptograph algorithm, which has additive homo-

undetected DSA fault and generating the additional

morphic properties, is regarded as a lightweight andtest patterns. According to the experimental results,

high-speed homomorphic cryptography which is ex-

the proposed method can generate complete test

pected to be applicable in the areas of e-voting, se-patterns for all the given benchmark circuits, withcure biometrics, and so on. However, authentication

the processing speed that is more than two orders ofand comparison require a huge amount of compu-

magnitude faster than the previous work.

tational cost for huge amount of data in the database, so performance improvement are essential forthe practical use of the the Paillier Cryptography. In

25this study, a dedicated hardware architecture for the

A Weak-Signal-Readout Integrated Circuit for Ter-

Paillier Encryption is investigated to improve com-ahertz-Video-Imaging with Global Shutter Opera-

putational time for Paillier, by utilizing high radixtion

Montgomery multiplication and increasing the de-

M. Ikeda, and T. Kikkawa

gree of parallelism in the encryption process.

We designed a readout integrated circuit (ROIC)
for Terahertz-Video-Imaging which converts a weak

3-1
Chapter3 Research in VDEC

Evaluation of Machine Learning Attack Vulnerabil-signal detected by InAs MOS-HEMT to digital sig-

ity for PUF-based Device Authentication Systemnal. The ROICs are integrated as 8x7 array on 180nm

and Examination of Design Guidelines

CMOS and utilized with the detectors stacked on

M. Ikeda, H. Awano, and T. Iizuka

them. Each ROIC contains low noise amplifier,

Recently PUF (Physically Unclonable Function)lock-in amplifier and ΔΣ analog-to-digital converter

has attracted a lot of attention as a method that is

as well as digital-to-analog converter to calibrate thelow cost and secure device authentication. Amongdetectors. In our work, several control parameters

PUFs, Double-Arbiter PUF (DAPUF) and PL-PUF

and digitized signals are serially communicated by

are known to be highly resistant to machine learn-

serial peripheral interface (SPI). The SPI also realizes

ing attacks. We proposed a end-to-end deep neuralglobal shutter operation where the ΔΣADC output

network-based modeling attack for DAPUF and PL-

signals are captured in 8x7 clock cycles and serially

PUF. Our model successfully predicted responses

read out in following cycles. Moreover, we imple-

to unknown responses of DAPUF with probability

mented a temperature sensor by MOSFET whose IV

21.1% higher than the conventional method. Fur-characteristics depend on temperature variation.

thermore, we presented that prediction rate of PLPUF depends on the response bit to be predicted andAdvanced 3-D Measurement System by Smart Im-

number of oscillation cycles. Based on experimental

age Sensors and Secure Sensing

results, we examined the design guideline of PUF-

M. Ikeda, U. Kim, V.G. Vishwa, N. Takeda, and Y. Liubased device authentication system to improve ma-

We are trying to propose new measurement meth-chine learning attack vulnerability.

ods, with advanced functionality, and secure sensing.
In advanced measurement, we have proposed a new

Self-Synchronous Circuits Design
M. Ikeda, and D. Cui

the capability of selective light detection and back-We are working on the research of high through-ground suppression, and are fabricating and meas-

put gate-level pipeline self-synchronous circuits freeuring a CMOS image sensor in which polarizers arefrom timing errors. The dual-pipeline self-synchro-

discretely arranged in specific pixels to obtain polar-

nous logic gate duplicates the DCVSL circuit into

ization information necessary for detection of spec-

two identical pipelines and uses the same completionular reflection. Towards secure sensing, we are trying

detection signal to control both pipelines. When one

a unified architecture, merging the functions of A/Dpipeline is in the evaluation phase, the other pipeline

conversion and data encryption and authentication.

must be in the pre-charge phase, results in concealing of pre-charge time. Gate-level pipelining enables
throughput enhancement. Based on the self-synchronous logic gate, we designed a high throughput
self-synchronous arithmetic unit, and a self-synchronous CPU.

26

3-D measurement method and a image sensor with

Takamiya Laboratory(http://icdesign.iis.u-tokyo.ac.jp/)

self-luminous pixel in a 3-dimensional (3D) mid-air
display and the drawing of characters in mid-air isalso demonstrated.

Switched Capacitor DC–DC Converters Mounting
Multilayer Ceramic Chip Capacitors on CMOS Die
Makoto Takamiya and Takayasu Sakurai
2/3 and 1/2 reconﬁgurable switched capacitor

Iizuka Laboratory(http://www.mos.t.u-tokyo.ac.jp)

Waveform Reconstruction Technique for Wide-dynamic voltage scaling of many-core microproces-band Signal

sors. In the fabricated 2.7-V input SC DC–DC con-

Tetsuya Iizuka, Byambadorj Zolboo

verter mounting four 100-nF 0402 (0.4 mm × 0.2

The Modulated Wideband Converter (MWC) is

mm × 0.2 mm) multilayer ceramic chip capacitors

one of the promising Sub-Nyquist sampling archi-

on 180-nm CMOS die achieves the highest efﬁcien-

tectures for sparse wideband signal sensing, cogni-

cy of 92.9% at the output power density of 62 mW/tive radio applications and so on. Since resources

mm2 in the published step-down SC DC–DC con-within Automatic Test Equipment (ATE) are limited

verters.

on sampling rate, the MWC can be useful for testing
devices with various frequency band.

Programmable Gate Driver IC for IGBTIn this research, we are investigating a feasibility of

Makoto Takamiya and Takayasu Sakurai

MWC to reconstruct a waveform of sparse wideband

A programmable gate driver IC for IGBT to dy-

signals for measurement equipment. We created anamically change the gate driving current during thesimulation platform system of MWC in MATLAB

switching of IGBT is developed. In the proposed

environment and the MWC system perfectly recon-gate driver, the 6-bit gate control signals with four

structs the waveform of original wideband signal un-

160-ns time steps are globally optimized using a sim-

der several ideal assumptions. But in practical imple-

ulated annealing algorithm, reducing the collector

mentation, it could suffer in some drawbacks due tocurrent overshoot by 37% and the switching loss by

non-ideal components and noisy situation.

47% at the double pulse test of 300V, 50A IGBT.

3-1
Chapter3 Research in VDEC(SC) DC–DC converter is developed for a per-core

In terms of noise performance, we proposed anaverage noise figure (ANF) theoretical notation to

Luciola: A Millimeter-Scale Light-Emitting Particle

expect the noise figure of MWC. The accuracy of theMoving in Mid-Air Based On Acoustic Levitation

analytical formula is ensured with MATLAB simula-and Wireless Poweringtion results.

Makoto Takamiya, Yasuaki Kakehi,
and Yoshihiro Kawahara

Design Automation and Optimization Techniques

We present an approach to realize the levitation of

for Analog Integrated Circuitsa small object with an embedded electronic circuit.

Tetsuya Iizuka, Zule Xu, Naoki Ojima, Masaru Osada

Luciola is a light-emitting particle with a diameter ofThanks to the exponential advancement of process

3.5mm and a weight of 16.2mg moving in mid-air.

technology, performance of digital logic circuits has

The novelty of Luciola is the ultrasonically levitatedbeen drastically improved, and hence most part ofelectronic object powered by resonant inductive cou-

signal processing is now carried out with digital log-pling. To enable the levitation of a particle, a custom

ic. However, some analog circuits remain in signal

IC chip is essential in reducing the size and weightprocessing; data converters, phase locked loops, andof the particle. Ths custom IC chip is designed to

power management circuits still require analog de-achieve an intermittent lighting of the LED, whichsign flows. Thus, easier and faster implementation ofincreases the maximal distance between the trans-them is needed for low cost and efficient development

mitter and the receiver coils. Luciola is applied to aof signal process flows. In this work we propose the27design methods of them in which a commercial au-

showed through simulation that an offset within

tomatic place and route tool is utilized. We designed

10ps can be reduced to within 1ps.

a successive approximation register analog-to-digital

3-1
Chapter3 Research in VDEC
28

converter (SAR ADC), a phase locked loop (PLL),Time Domain Approach for Analog Integrated Cir-and a digital low-dropout regulator (LDO). In thecuit Designs

SAR ADC, analog components such as resistive

Tetsuya Iizuka, Zule Xu, Meikan Chin, Jing Wang

digital to analog converters (RDAC), a four-input

While digital circuits directly benefit from ad-

clocked comparator, and track and hold (T/H) cir-vanced process technologies, analog circuits suffer

cuits are fully implemented with standard cells. The

from negative effects such as small voltage head-

6-bit resolution prototype is fabricated in a 65 nm

room. Time-domain circuits, where analog signals

standard CMOS technology, and its performance isare represented by digital signal edge transitions,

measured. In the PLL, injection lock is utilized. The

could be a solution to the problem of analog circuits

PLL is now in development to achieve the goal of

in a nanometer process.

low jitter and phase noise. In the digital LDO, withWe have applied time-domain control methods toinverter chains as voltage-controlled delay lines, the

PLL circuit and its measurement. Especially for thedifference between output and reference voltages is

IoT devices, the circuits start only when they are nec-

converted into delay difference, then compared inessary for the entire system. While the whole system

the time-domain. Since the time-domain differenceis going to be activated from the standby state whereis straightforwardly captured by a phase detector that

the PLL is acquiring lock, the power consumption

consists of a D-FF, the proposed LDO does not needin this period is just a waste, thus it should be re-an analog voltage comparator, which requires careful

duced. Pulse-Width PLL (PWPLL) is an analog-dig-manual design. The prototype of the proposed LDO

ital mixed PLL, which controls the output frequency

is fabricated in a 65 nm standard CMOS technology.

with Soft Thermometer Code (STC) without using a

The measurement results show that this prototype

low pass filter. Most of the PWPLL is a digital PLL,

exhibit good trackability of output with the fluctua-

which is compatible with P&R. In this research,tion of the reference and load.

to reduce the PWPLL startup time and reduce theIn this research, a DLL (Delay Locked Loop) was

power consumption of the system, a feedback systemdesigned to produce a clock signal for a high-per-parameter (= target value) at the time of locking isformance TDC (Time to Digital Converter). TDCs

stored and a method for reproducing the parameterare used in various applications such as ADPLLs (Allat the next start is used There was. The conventional

Digital Phase Locked Loop) and measurements. The

fast-start PWPLL creates a layout by manual design,

DLL had a 1GHz input signal and consisted of 16

but it takes time and the specification adjustment isdelay elements. In order to achieve high resolutiondifficult. In this research, in order to save labor on

for the TDC, the DLL was required to have less thanlayout design, we created a layout using an automat-

2ps offset between the input and output, and lessic placement tool and designed a fast startup PWPLL

than 2ps variation between the delays in each ele-with performance equivalent to manual design.

ment. We first analyzed the effect of thermal noise in

Time-to-Digital Converter (TDC) is a representa-

the CP (Charge Pump), PFD (Phase Frequency De-

tive example of time-domain circuits. TDC basical-

tector), and Buffers through calculation and simula-

ly converts a time interval between two rising edges

tion, and showed that the produced jitter was within

into a digital code by using delay elements. In our

the requirements. We then used a cascode-multipath

research, we focus on a pulse-shrinking TDC, whicharchitecture for the CP to avoid current mismatch,is one kind of the sub-gate-delay resolution TDCs.

and achieved an offset of 600fs in simulation. Fi-

In general, TDC has a trade-off between the timenally we implemented a calibration technique using

resolution and dynamic range, and the trade-off iscapacitor arrays to account for process variation, andparticularly remarkable in the pulse-shrinking TDC.

Last year we designed and measured a TDC that im-a small area and low power consumption while main-

proves the dynamic range while keeping the high res-taining low phase noise. In order to solve these prob-

olution by using a hierarchical approach. We foundlems, we studied to produce a signal of 140 GHz us-that the TDC has a serious nonlinearity caused bying a frequency doubler, and proposed a method toprocess variation. So, we analyzed the impact of it bysolve the above problem by removing the impedanceMonte Carlo simulation and designed a new TDC

matching circuit between each block. We confirmed

resistant to process variation.

by actual measurement that the proposed circuit

TDC can be applied for various applications andsolves this problem.
In a transceiver, it is necessary to modulate andLock Gated Oscillator (CLGO) is one example.

amplify the signal generated by the oscillator. In thisSince the CDR consumes no dynamic power in its

research, we adopted on-off-keying as a modulation

standby state and resumes from the standby state justand proposed an architecture of on-off-keying withafter a 4-bit preamble, it can improve the total power

low loss and high on-off ratio. We implemented thisefficiency of serial communication systems that work

modulator with a 65 nm CMOS process and con-intermittently such as mobile and IoT sensor node

firmed that it is operating with high on-off ratio andapplications which require not only low power con-

low loss by measurement. Furthermore, we imple-

sumption in operation but also in standby state andmented an power amplifier circuit in the same pro-quick startup form the standby state. We proposedcess and confirmed that it was possible to amplify a

CDR using Delay Tunable Buffer (DTB) and Verniersignal of 140 GHz.

TDC for tracking frequency range extension and low

In addition, we aim to reduce loss by substrate

power consumption, designed and measured. While

removal of on-chip antenna in dielectric waveguide

DTB and digital control work as designed, we foundcommunication. Then, building blocks necessary

the deviation of timing in Vernier TDC. So we pro-for actual measurement were fabricated using Rohm

posed new Vernier TDC whose reference level is

0.18 μm process. Also, we evaluated the de-embed-

tunable. The entire CDR system has been fabricatedding methods required for actual measurement. The

with 65nm CMOS process and 2.3Gbps operation issignal transfer characteristics of the dielectric wave-

verified with measurement results.

guide were evaluated with measurement.

mm-Wave Circuit Design for Communication

Signal Crosstalk Cancellation Technique for High-through Dielectric Waveguide

Speed Wireline Communications

Tetsuya Iizuka, Nguyen Ngoc Mai-Khanh,

Tetsuya Iizuka, Daigo Takahashi

Yoshitaka Otsuki, Daisuke Yamazaki,

With the improvement of the circuit performance

Takafumi Haradue to the miniaturization of the semiconductor

High-speed communication with the millime-

process, the speed of transmission has been improv-

ter-wave band has been actively researched. Wireline

ing. The data rate necessary for applications also has

communication with a dielectric waveguide such as

been improving because UHD TVs and automobiles

polymer has been proposed and expanded research.

with a lot of electrical equipment was developed.

Because it is possible to increase the communication

It is necessary to speed up transmission from bothdistance at low cost while maintaining the commu-

aspects of technology and demand, crosstalk is one ofnication speed.

the factors hindering this. As measures for crosstalk,In this research, we designed a voltage controlled

a method for reducing crosstalk at the receiver was

oscillator (VCO) oscillating at 140 GHz. Oscillator

proposed in the previous research. In this research,is essential circuit in all systems involving commu-

we proposed a method for reducing crosstalk at the

nication. In this circuit, it is difficult to operate in atransmitter with a delay adjustment circuit and asuperhigh frequency band exceeding 100 GHz, withhigh-pass filter based on the method in the previous

3-1
Chapter3 Research in VDEC

Clock and Data Recovery (CDR) based on Cycle

29research. Using simulation, we showed that the pro-ator integrated nanopore system.

posed method can reduce crosstalk more effectively. The proposed crosstalk cancellation circuits have

Fine Large-Area Electron Beam Lithography Expo-been implemented with 40nm CMOS technology.

sure Methods
Y. Mita,A. Higo, M. Fujiwara, T.Sawamura,

Mita Laboratory(http://www.if.t.u-tokyo.ac.jp)

3-1

Current Research Projects

M.Takizawa (Advantest), Y.Kudo (Advantest)
The team explores newly-acquired (in 2013) rapid electron beam writer F7000S-VD02. The ca-pa-

Chapter3 Research in VDEC

bility of high electron dose and sharp edge due toProgrammable Matter - Study on LSI-MEMS ener-

cell (character) projection machine configura-tion

gy-autonomous distributed microsystems for re-is being examined. The breakthrough in question isalization of deformable matterto extend the large-area EB lithography, whose pat-Y. Mita, N.Usami, G. Ulliac,

tern approximation have been limited to rectangular

E. Lebrasseur (LIMMS, CNRS-UTokyo IIS),

shapes, into expressing free-form smooth shapes and

J.Bourgeois, B.Piranda (FEMTO-ST, France),

a number of periodical small patterns. This year’s

S. Delalande (PSA-Peugeot)

outcome include a micro race-track optical resona-

As one example of integrated MEMS that is ex-

tor test structure to quantify the quality of pattern

pected to open new research and industrial ap-pli-

approximation by optical absorbance spectrum.

cation fields, the authors are trying to show a topdown application of energy-autonomous dis-tributed

University-Industry collaborative research on

microrobots. A number of identical tiny robots,highly-functional system by MEMS post-process

sized below 1cm, will be released in an en-viron-of CMOS-VLSI

ment. Individual robot can communicate with their

Y. Mita, S. Inagaki, T. Kuriyama, Y.Sato (Nanox Japan),neighbor, can stick each other, can share energy, toT.Ono (Sony)realize cooperative function. The PI has received a

The research targets are new sensor devices, madeFrench National Research Center (ANR) grant on

by post-process at clearnrooms such as VDEC

behalf of host professor of CNRS laboratory in the

Takeda Supercleanroom and others, of VLSI wafer

Institute of Industrial Science (LIMMS, CNRS-IIS,

made through VDEC. The important finding has

UMI 2820), together with FEMTO-ST Laboratory

been that VLSI wafer acquired just after transistor

and PSA-Peugeot Laboratory for such “micro robots

fabrication could sustain processes even with heatthat can realize deformable substance by cooperative

treatment, such as deposition, ion implantation,action, named Programmable Matter”. In this year,

and drive-in. In 2016, a VLSI de-vice made on Sili-an electrostatic actuation on tiny (1mm to 10mm)

con-on-Insulator (SOI) wafer was successfully Deep-objects is performed and analyses were conducted.

RIE processed. The in-dustrial interest is its versatility – many different types of application devices,

Integration of electrode devices on MEMS fluidic

which differ one from another according to request

devicesof market, can be fabricated by using the same tech-

Y. Mita,A. Higo, Y.Takeshiro, Y.Okamoto,nology. More and more companies are interested in

N.Washizu (Advantest), A.Takada (Advantest),

the scheme and are working on the technology on

M. Fujiwara, T.Sawamura

the col-laborative research projects.

Towards the goal of production of brand-new sensor devices with higher sensitivity and func-tionality,
the team is working on small-gap electrode fabrication process. The target of first year is reliable electrode integration on nanopore, as well as microactu-

30

High-sensitive ultrasonic probe by integrated

limited to tungsten so it is impossible to wire bond

MEMS technology

on the post-fabricated pads. On the contrary, there
exists needs for wire-bonding on the post-process

T.Yoshimura (Osaka Prefectural University),

FIB opened pads, in order to integrate it into theT.Mizuno (Konika Minolta),

printed circuit testing board. To-wards that end, we

K.Suzuki (Konika Minolta),

developed a MEMS shadow masking methods to de-

Y.Nakayama (Konika Minolta),

posit wiring material through them. An assessment

T.Endo (Nagoya Medical Center)of transistor characteristics under such probe wasUsing the same scheme as above mentioned

performed and proved no mechanical impact.

CMOS-MEMS post process R&D scheme, this project aims at integrating piezoelectric material and“Zeolite-Electronics-Nanostructure (ZEN)” inte-

MEMS post-processing to obtain a brand-new ultra-

grated chemical sensor

sonic inspection probe, whose sensitivity is as 100

Y.Mita, K. Yamada, Y.Okamoto,times as cutting-edge technology. From 2018, theM.Denoual (ENSI de Caen, France),

team is accepting a public funding from Japan Agen-

Tixier Mita Agnès (UTokyo RCAST),

cy of MEdical Research and Devel-opment (AMED)

Eric Lebrasseur,to accelerate research towards clinical application.

Hussein Awala (ENSI de Caen, France),

3-1
Chapter3 Research in VDEC

Y. Mita, R.Yamaguchi, N.Usami, A.Higo,

Julien Grand (ENSI de Caen, France),
LSI hot-spots active cooling system

Svetlana Mintova (ENSI de Caen, France)

Y. Mita, Y. Okamoto, K. Fujimoto (Titech),

One of the most important application field of

H.Ryoson (Titech), and T. Oba (Titech)

MEMS is sensors that can detect physical and chem-

A hotspot, which is referred to a high-temperature

ical amount that cannot be sensed by human beings.

area due to the overheating of a circuit block that

Following a long history of the group’s research, theexcess passive cooling capability, is becoming a key

team was appointed in 2015 as a JSPS-CNRS bilat-

limiting factor of LSI performance. An ac-tive cool-eral cooperative research project grant. The goal ofing system that tries to actively remove such local

the research is to develop a chemical sensor by inte-

heating by circulating liquid coolant is our researchgrating Zeolite material that is new to VLSI, and ap-

target. This year an electroosmotic pumping actua-

plying post-process on it. Within one year, the team

tor and high-voltage generation CMOS MEMS de-have successfully demonstrated two types of devices:

vice was independently proven to be working. Also,

a zeolite chemical sensor by resonant frequency shift

a zeta potential measure-ment system, which is man-detec-tion, and by thermal capacity change detection

datory for evaluating surfaces for electroosomotic

according chemical concentration. An improvement

flow, is developed. This system only have to stick-on

on the stress detection device by using LSI compo-

the surface to be evaluated.

nents is made.

Test Pad post-processing for LSI diagnosys
Y. Mita,Y. Okamoto, A. Higo, A. Mizushima,
J.Kinoshita (Nexty Electronics)
An academic-industry collaborative project to enhance the capability of LSI post fabrication di-agnoses. In VDEC also, a Focused Io Beam (FIB) machine is installed to analyze and repair the LSI. The
practical limit of such system is availability of wiring
material, which is machine dependent. In case of
VDEC’s machine (FEI V400ACE), the material is31

Project PARIS: PARallel Integrated microSystem

first year’s exploratory study, partly financed by thefor High Frequency Action-Based Non-Invasive

LIMMS internal project grant, spin coating integra-

Multi-Modal Cell Analyses

tion method has been investigated. The enhance-

Y.Mita, T.Tsuchiya, Y.Okamoto, A.Mizushima,ment of absorbance spectra at such wavelength has

E.Lebrasseur, C.Moslonka (ENS Paris-Saclay, VDEC in-been experimentally confirmed.

ternship student), B. le Pioufle C.Moslonka (ENS Par-

3-1
Chapter3 Research in VDEC

is-Saclay), Tixier Mita Agnès (UTokyo RCAST), Olivier

Development of zero power multiple-threshold

Français (ESIEE, Univ. Paris Est), F.Marty (ESIEE, Univ.

maximum acceleration sensor for cyber physical

Paris Est)

systemHaving granted again JSPS-CNRS bilateral pro-Y. Mita, R Ranga Reddy

ject 2018, the team is developing a large-scale mul-

VDEC is awarded a Japanese JST – Indian DST

ti-modal cell analyses system (project name: PAR-

joint grant (SICORP) for cyber physical systems

IS). The electrorotation method, which is known

research, in cooperation with IIT Bombay campus.

to measure a mechanical rotational response to the

The team is participating the project through a Shockincident rotational electrical field fre-quency is used.

Resonant Spectrum (SRS) sensor, which has been a

The method is non-invasive so the evaluated cells

research theme of 2012-2014. A new Ph.D student

are possible to be used in fur-ther biological experi-

from India is assigned and fabrication process wasments. In this year fabrication of classical electrodes

recovered. This year we have developed complete

was first leaned by VDEC internship student. Thensystem to record 10-levels of maximum acceleration

thicker electrodes were made in collaboration within MEMS device.

ESIEE and ex-periments were done at ENS Paris-Saclay in Cachan. The measurement revealed the prob-

Development of LSI post-processing for hybrid in-lem of Z-axis controllability so new device structure

tegration

was proposed and proven to be efficient.

Y. Mita, N.Usami, E. Ohta, A.Higo,
T. Momose (Material Eng.)

Colloidal integrated Infrared Detector
A.Higo, N. Usami, Y. Okamoto,Platform Users, a couple of process technologies

W. Haibin, N. Kubo, K. Segawa, Y. Mita

for LSI hybrid integration is under development. In

Electron devices using colloidal quantum dots are

FY2016, a stable gold electroplating system was pur-believed to open new application fields such as lightchased and a bump plating for LSI flip-chip bond-emitting devices and or photovoltaics. Up to date,ing was developed. In parallel, a supercritical fluid

very few research activities have been done in sensors

deposition (SCFD) machine was restored to investi-

applications; if we can realize integrated photodiodes

gate trench embedding deposition with metal. Thisthat have extended sensitive wavelength as long as

year, we have obtained a reliable protocol of surface

1.35µm-1.4µm wavelength, such devices can be usedtreatment, with which the SCFD Cu stick sufficient-by many new appli-cations such as security cameras

ly strong to be used as seed material for following

and / or Laser Radar (Lidar) under sunlight. The

processes (such as electroplating).

aim of this research is to find an integration method
for beyond Si-LSI device. We try to integrate colloidal quantum dots of which absorption spectra canbe designed through molecular design. By inte-gration, Silicon device will be able not only to capture
infrared wavelength lights, which is impossi-ble byits original characteristics, but also my include information reading and computation circuits. For the32

To provide new capability to Nanotechnology

Takagi-Takenaka Laboratory(http://www.mosfet.k.u-tokyo.ac.jp/)

On-chip/Off-chip optical interconnect
M. Takenaka, S. Takagi, Kasidit Toprasertpong,
Qiang Li, Naoki Sekine, Pengyuan Cheng,

III-V/Ge Metal-Oxide-Semiconductor (MOS) FETs

Dongheng Lyu, Qianfeng Chen, Dongrui Wu,

and the 3 dimensional integration

Yuto Miyatake
We have investigated Si photonics for on-chip and

Ke Mengan, Kwangwon Jo, Cheol-Min Lim,

off-chip optical interconnection for CMOS LSI.

Tsung-En Lee, Sanghee Yoon, Chiaki Yokoyama,

We have revealed that an efficient optical phase was

Zilong Wang, Kei Sumita, Jun Takeyasu

available in reverse-biased III-V/Si hybrid MOS ca-

We have conducted the research on high-perfor-

pacitor through carrier depletion and Franz-Keldysh

mance III-V/Ge MOSFETs and the 3 dimensional

effect. We have also found that an efficient gratingstacked CMOS structures by using these high mo-coupler can be automatically designed using one ofbility MOSFETs. We have investigated Smart-cut

the artificial intelligence, that is, evolution strategy.

technology for forming an high-mobility ultrathin

We have also investigated the III-V CMOS photon-

InAs channel. By optimizing the condition of hydro-

ics platform by using III-V on insulator wafer. We

gen ion implantation, we have successfully achieved

have numerically analyzed the modulation proper-

InAs Smart-cut, and obtained ultrathin InAs-on-in-

ties of InP-slot optical modulator with EO polymer.

3-1
Chapter3 Research in VDEC

S. Takagi, M. Takenaka, Kasidit Toprasertpong,sulator wafer. We have also conducted the researchof Ge condensation for Ge-on-insulator MOSFETs.

Si photonic integrated circuit for AI

We found that the slow cooling procedure after the

M. Takenaka, S. Takagi, Kasidit Toprasertpong,condensation resulted in high compressive strained

Qiang Li, Shuhei Ohnoin the condensed Ge-OI layer.

We have investigated programmable photonic integrated circuits (PICs) including a universal PIC

Tunnel FET

for deep learning. We have proposed programmable

S. Takagi, M. Takenaka, Kasidit Toprasertpong,

PICs integrated with III-V/Si hybrid MOS optical

Kimihiko Kato, Taeeon Bae, Daehwan Ahn,

phase shifters and revealed its learning capability. We

Ryotaro Takaguchi

have also proposed ring resonator crossbar array Si

We have investigated tunnel FETs (TFETs) which

PIC for deep learning.

can exhibit steep subthreshold slope for low-power
operation. Lateral InGaAs TFETs, Ge TFET, GaAs-

Ge mid-infrared photonic integrated circuit

Sb/InGaAs hetero-junction, Ge/strained Si hete-

M. Takenaka, S. Takagi, Kasidit Toprasertpong,ro-junction and ZnO/(Si, Ge) TFETs have been

Chong Pei Ho, Ziqiang Zhao, Takumi Fujigaki

explored. We have successfully demonstrated theWe have also conducted the research of thesubthreshold slope of 49 mV/dec. by EOT scaling of

mid-infrared photonic integrated circuits based on

InGaAs TFET with ZrO2 high gate dielectric.

Ge-on-Insulator (GeOI) wafer fabricated by wafer
bonding. We have achieved high-quality GeOI wa-

Ferroelectric gate insulator MOSFETs

fer, enabling high-Q micro ring cavity on GeOI. We

S. Takagi, M. Takenaka, Kasidit Toprasertpong,have also demonstrated efficient Ge thermo-optic

Kimihiko Kato, Zaoyang Lin, Kento Tahara

phase shifters on GeOI wafer.

We have conducted the research for MOSFETs using ferroelectric gate insulators. We have confirmed
ferroelectricity of ALD HfZrO2 films on Si and theoperation of MOSFETs with these gate insulators.

33

2D material devices
M. Takenaka, S. Takagi, Kasidit Toprasertpong,Roda Nur, Hanzhi Tang, Xiaoxuan Zhang
We have investigated 2D materials such as grapheneand MoS2 for semiconductor devices. We have proposed a black-body thermal emitter using graphene
coupled into a Si waveguide. We have numerically
3-1
Chapter3 Research in VDEC
34

analyzed graphene thermal emitter.

VLSI Design and Education Center,
The University of Tokyo
Annual ReportAugust, 2019
Published by
VLSI Design and Education Center, The University of Tokyo
Director Masahiro Fujita
Address: Yayoi 2-11-16, Bunkyo-ku, Tokyo, 113-0032, Japan
Printed in
SOHOKKAI co., Ltd. Tokyo Branch
Address: Koutoubashi 4-25-10, Sumida-Ku, Tokyo, 130-0022, Japan
Copyright Ⓒ by VLSI Design and Education Center, The University of Tokyo