平成26年度
VLSI Design and Education Center The University of Tokyo 2014

東京大学
大規模集積システム設計教育研究センター

年 報

2014
VLSI Design and Education Center,
The University of Tokyo
Annual Report

VLSI Design and Education Center The University of Tokyo 2014

2014VDEC年報H1̲4E.indd H4-H1

14/07/28 12:06

VLSI Design and Education Center
The University of Tokyo

This is the 2013 Annual Report of VDEC（VLSI Design and Education Center, University of Tokyo）.
In 2013 VDEC has decided a new policy of activities; “international collaborations and cross-bridges to industry”.
As a result of Japanese semiconductor industry, which has given up in-house development of advanced technologies
beyond 40 nm and steered to “fabless” or “fablite” business models, it is getting hard for VDEC to find partners
for advanced chip fabrication. So, we decided to make an agreement with CMP in France in order access to 28nm
FDSOI/CMOS technology of ST Microelectronics as an advanced fabrication technology for the time being. Since
it is a new and complicated technology, we carried out a test run under a support from STARC. Experienced design
teams about 10 laboratories in Japanese universities has contributed to the test run to check design rules and design
environments for establishing VDEC design flow. Measurement results of the test chips will be available soon. VDEC
has a plan to start a new chip fabrication service of 28 nm FDSOI/CMOS twice a year, based on the measurement
results.
VDEC and ICREC in Vietnam National University signed an MOU last November for collaborations in education
and research. ICDREC is enthusiastic about developing commercial products. It will be a good partner for VDEC toestablish cross-bridges to industry. ICDREC has a plan to send engineers to VDEC this year for training of clean room
technologies. We would also like to start collaborations with other countries in Asia and Middle East.
In order to lead to a breakthrough in current situation of the semiconductor industry in Japan, we need to bridge
gaps between researches in universities and venture businesses, making transition smooth in terms of design andfabrication environments. We have started discussions with CAD vendors and semiconductor foundries. But, because
it is impossible without a new budget plan, we would like to proceed step by step. When we make a progress, we willreport in the VDEC seasonal letters.
Today, the number of registered members of VDEC design services and the number of VDEC clean room users(mainly MEMS researchers) are almost identical. Since the former is the number of teachers and the latter is thenumber of researchers and students, it is not simple to compare them. But, it is remarkable that the clean room users
are increasing recent years. It is indispensable to maintain and renew facilities for keeping clean room processes
in good conditions. Fortunately last year, we could newly introduce or replace VDEC facilities, such as EB patterngenerator, FIB machine, etching equipment and high speed measurement apparatuses, by the supplementary budgetof the Government. Especially booking of the old EB pattern generator has been full, but this year it will be relaxed
due to higher throughput of the new machine.
As an annual event of the D2T (Design-to-Test) research division, which was donated by Advantest Corporation, the
8th symposium was successfully held on October 24th 2013, inviting distinguished lecturers on future LSI system andtest technologies from oversea and domestic counties. We are scheduling the 9th symposium in August 26th this year,
too. We would like to express our sincere thanks to Advantest Corporation for the continuous support.
We will continue to make our best effort for the original mission of VDEC, “promotion of education and research in
LSI design field by means of practical chip-design and implementations”, with foreseeing the future of semiconductor
society. We thank you for your continuous supports again.

June 2014

VLSI Design and Education Center, University of Tokyo
Director

2014VDEC年報H1̲4E.indd H2-H3

Kunihiro Asada

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VLSI Design and Education Center, The University of Tokyo
Annual Report 2013

C O N T E N T S
Message from Director of VDEC
Chapter 1

Chapter 2

Chapter 3

VDEC2014̲E.indb 1

2

Activity Report of VDEC
1. 1

Introduction of VDEC activities and activity report of FY2012

1. 2

VDEC CAD Tools

2

5

1. 3

VLSI Chip Fabrication

1. 4Seminar10

1. 5

Facilities

14

7

15

1. 6

Activity plan for 2014

1. 7

Venture companies related to VDEC

1. 8

“Nanotechnet” : Ultra Small Lithography and Nanometric Observation Site

16

18

Activity Report of “D2T Research Division”
2. 1

Introduction of “D2T Research Division”

2. 2

Report of “D2T Symposium”

17

18

19

2. 3

Research Activity Reports of “Advantest D2T Research Division”

2. 4

Publications

21

23

Research in VDEC

24

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Chapter 1 Activity Report of VDEC
1. 1 Introduction of VDEC activities andactivity report of FY2013
VLSI Design and Education Center（VDEC）, University

year. We hold the seminar in VDEC and provide distanceof Tokyo was established in May 1996. VDEC has beenlearning through video streaming. We expect spread ofoperating for the following 3 major roles:“spreading

the up-to-date LSI design methodology by using CAD

the latest information on VLSI design and education,”tools.

on VLSI chip fabrications for academic use.” Theon basic LSI design concepts and practical experience of

VDEC activity report of FY 2013 is described hereafter

LSI design with CAD tool chain. VDEC holds“LSI design

according to Fig. 1. 1.

education seminar”，aka VDEC Refresh Seminar, once

Chapter 1

We assume our LSI design flow seminars as educations“providing licenses of CAD tools,” and“suppor ting

1-1

The missions of VDEC ar e for advancement ofa year from November to Januar y time frame for thisresearches and education on LSI design in public andpurpose. As for the VDEC Refresh Seminar, this year

private universities and colleges in Japan and send many

we continued“Analog design course” and“RF design

distinguished VLSI designers into industry. After 17 years

course”，and initiated“MEMS design course”．We inviteof VDEC establishment, educations on CAD software,experienced professors among universities as lecturers

LSI design and design flow in universities have been wellfor the courses to conduct LSI design education courses

established. On the other hand, advancement on nano-with practical experience. We also hold“Transistor level

meter CMOS technologies forces design flow and CAD

design flow in VDEC” and“Digital design flow in VDEC

software complicated. We have been continuing CAD tool

EDA environment” for designers in universities.

2

Activity Report of VDEC

seminar by the lecturers from EDA vendors for twice a

Fig. 1. 1

VDEC2014̲E.indb 2

In addition to the above seminars, we hold“VDEC

VDEC activities

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DesignerʼForum” among young professors and students

and experienced designers within a couple of hours to aannually. This is a workshop that the par ticipants

couple of days. Moreover, emails are accumulated and are

exchange their design examples with not only success

open to the VDEC users, as shown in Fig. 1. 2, who havestories but also their failure stories, in addition to invited

registered VDEC accounts, as the important educationaltalks. We expect students and professors who will start

assets. We expect all the VDEC users to make the full use

designs to learn kinds of know-hows. We have initiatedof this mechanism to help solve problems.
With August 2013 shuttle, we shut-down eShuttle

year, and final examination and awarding have carried

65 nm CMOS chip fabrication ser vice. After METI-

out during the“VDEC DesignerʼFor um”．Mr. K. Imai

STARC project terminated in FY2012, STARC supported（Shizuoka Univ.）is awarded as“IEEE SSCS Japanto have chip fabrication test r un for STMicro 28 nm

Chapter VDEC Design Award” winner, and Dr. G. He

FDSOI CMOS chip fabrication. We continue chip

（Kobe Univ.）, Dr. S. Yoshimoto（Kobe Univ.）, Dr. H.

fabrication ser vices on 0.18 μm CMOS by Rohm andKonoura（Osaka Univ.）, and Mr. K. Takagi（Kobe Univ.）

0.8 μm CMOS by On-semi Sanyo Semiconductor.

are awarded as“the best VDEC Design Award”，and Mr.

Our donated division“Design To Test
（D2T）”，whichR. Wu（TITECH）, H. Takehara（NAIST）, Mr. Y. Umeki

was founded by donation from Advantest in Oct. 2008,（Kobe Univ.）, Mr. R. Hori
（Ritsumeikan Univ.）, and Dr. N.

focuses on enrichment of education on LSI testing andKamae（Kyoto Univ.）are awarded as the“VDEC Design

bridging between design and testing.

Award.”

Fig. 1. 3 shows trends of number of papers through
VDEC activities. Number of papers is increasing, which

during actual LSI design scene, even after the basicmeans researches in the field of VLSI design have been

educations through various seminars and the forum. One

encouraged after VDEC establishment.

of the biggest problems for beginners is the setup of CAD

Fig. 1. 4 shows number of papers related to CAD usage,

softwares. Many of them also get confused by“Esotericchip fabrications and VDEC facility usages. CAD tools aremessages” come out from CAD softwares, even after theywidely used to write papers. CAD tools are used not only

successfully setup CAD tools. In such situations, VDEC

chip designs themselves but also used for preparation of

mailing-lists make significant contributions. VDEC users

chip fabrication and they contribute to verify fundamental

can register to VDEC mailing-lists on CAD tools, andideas of researches. Advanced CMOS processes areprocess dependent groups through VDEC web pages,

preferred for publications, and not only papers with 65 nm

and can ask questions and helps on their facing issues. It

CMOS chips, but also with 45 nm CMOS, 32 nm CMOS

is not a responsibility for the registrant of such mailing-and 22 nm CMOS are emerging in the world. We would

lists to give answers to questions, however, in most cases,

like to prepare chip fabrication services for the advanced

replies are given by the experienced users of CAD tools

CMOS processes. In addition, we would like to setup chipFig. 1. 2

VDEC2014̲E.indb 3

1-1
3

Activity Report of VDECLSI designers come up against various dif ficulties

Chapter 1“IEEE SSCS Japan Chapter VDEC Design Award” thisArchives of emails of VDEC mailing-list.

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fabrication services related to CMOS/MEMS to fulfill thetesters, FIB systems and EB writer for the wide spread ofresearches for “More than Moore”．We also encourage

research purposes.

researchers to fully use of VDEC facilities such like LSI

Chapter 1

1-1
4

Fig. 1. 3

Trends of number of papers through VDEC activities.

Activity Report of VDEC
Fig. 1. 4

VDEC2014̲E.indb 4

Number of papers related to VDEC facilities.

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1. 2 VDEC CAD Tools
Since 1996, VDEC has provided CAD software licenses

and colleges.

to the registered researchers in universities and colleges
When one is going to use VDEC CAD tools and chipin Table 1. 2. 1. The researchers can use those CAD

fabrication service (the details are described in Section

tools when their local machines, whose IP addresses are

1-3), some faculty member of his/her research group inregistered in advance, are authorized by one of VDEC

a university or a collage needs to do user registration.

license server located in the ten VDEC subcenters shown

Figure 1. 2. 2 shows (a) the number of registrants, (b)in Figure 1. 2. 1. For each CAD tool, VDEC provides

the number of distinguished universities/colleges of the

10–100 floating licenses. Those CAD tools can be utilized

registrants, and (c) the number of registrants who applied

only for research and education activities in national

VDEC CAD tools.

universities, other public universities, private universities,
Table 1. 2. 1 VDEC CAD tools

1-2

Function

VendorCadence tool set

Verilog-HDL/VHDL entry, Simlation, Logic synthesis, Test
pattern generation, Cell-based (including macros) place,route, and back-annotation, Interactive schematic andlayout editor, Analog circuit simulation, Logic verification,
Circuit extraction

Cadence Design Systems, Inc.

Synopsys tool set

Verilog-HDL/VHDK simulation, Logic synthesis, Test pattern generation, Cell-based (including macros) place, route,and back-annotation, Circuit simulation, Device simulation

Synopsys, Inc.

Mentor tool set

Layout verification, Design rule check

Mentor Graphics Co. Ltd.

Silvaco tool set

Fast circuit simulation

SilvacoADS/Golden Gate

Design and verification of high-frequency circuits

Agilent Technologies

Bach system

BachC-based design, synthesis, and verification

Sharp

LAVIS

Layout visualization platform

TOOL

5

Activity Report of VDEC

Name

VDEC2014̲E.indb 5

Chapter 1

in Japan. The CAD tools we provided in 2009 are shown

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Chapter 1

1-2

Fig. 1. 2. 1 VDEC Subcenters

6

Activity Report of VDEC(a) The number of registrants(c) The number of research group applied CAD tools(b) The number of universities colleges of the registrants(d) The number of applied licenses of all CAD tools

Fig. 1. 2. 2 The numbers of VDEC CAD Applications

VDEC2014̲E.indb 6

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1. 3 VLSI Chip Fabrication
1. 3. 1

Trends of VLSI Chip
Fabrication Services

the number of designed chips shows steady increase,which means drastic improve of the ef fectivenessresearches and education of LSI design, and we assume

Fig. 1. 3. 1 shows a trend of number of designed chips
for VDEC chip fabrication services, including pilot projectprior to VDEC establishment.
VLSI chip fabrication is limited to 0.5 μm CMOS
provided by NTT Electronics during the pilot project in

Chapter 1

1994 and 1995. VDEC chip fabrication had started in 1996
with 1.2 μm CMOS provided by Motorola Japan, which
is now On-Semiconductor as well as the 0.5 μm CMOS.
In 1997, VDEC received cooperation from Rohm and has
started 0.6 μm CMOS process. In 1998, VDEC started

1-3chip fabrication services of 0.35 μm CMOS by Hitachi,

7

had a test chip fabrication of 0.13 μm CMOS by STARC
through“IP development project” in 2001. We added（a）Trend of number of designs fabricated.

0.18 μm CMOS by Hitachi into our chip fabrication
menu in 2001. From 2002, we started VDEC-MOSIS chip
fabrication program initiated by Prof. Iwata of Hiroshima
University. Under this program, VDEC member canaccess to TSMC and IBM processes with lower price. We
also started Bipolar chip fabrication by NEC Compound
Semiconductor Devices. In 2004, we star ted 0.15 μm

Activity Report of VDEC

and in 1999, VDEC started 0.35 μm CMOS by Rohm. We

SOI-CMOS chip fabrication by Oki Electric as test chip
fabrications. In the same year we started 90 nm CMOS
chip fabrication by ASPLA/STARC. In 2006, we started
0.18 μm CMOS by Rohm and 0.25 μm SiGeBiCMOS
by Hitachi. In 2008, we started 65 nm CMOS process by
eShuttle, after closure of 90 nm CMOS chip fabrication（b）Trend of designed area.

in 2007. In 2010, we star ted 40 nm CMOS process
by Renesas Electronics through“Next Generation
Semiconductor Circuits & Architecture” project between
METI and STAR. On the other hand, 1.2 μm CMOS
chip fabrication program came to end by the September
2011. 40 nm CMOS by Renesas Electronics and 65 nm
by eShuttle also come to end by Oct. 2012 and Aug. 2013,
respectively. We started CMOS0.8 μm in Oct. 2012 by
On-semiconductor-Sanyo as a test chip fabrication andopened it as the regular chip fabrication menu in 2012.
We started FD-SOI 28 nm CMOS by ST-Microelectronics
through CMP, France, as the advanced CMOS process in2013.

（c）Trend of designed area normalized by design rule.

Fig. 1. 3. 1(a) shows trends of number of chip designed
for VDEC chip fabrication. For the first 6 years until 2001,

VDEC2014̲E.indb 7

Fig. 1. 3. 1 Trend of number of designs and designed chip area.

14/07/28 12:05

drastic increase of number of students related to LSI chip
design and education. During few years of stable number
around 400 chip designs per year, we can see transitionof designs toward finer process. In 2007, we saw a large
drop, which was caused by sudden process transition
from 0.35 μm CMOS to 0.18 μm CMOS, and in 2008, we
also saw another drop by process transition from 90 nm
CMOS to 65 nm CMOS.
Fig. 1. 3. 1(b) shows trends of designed chip area,
which shows much clear trends of drop by process
migration. On the other hand, Fig. 1. 3. 1(c) shows

Chapter 1

trends of designed chip area normalized by design rule,

1-3

number of chips and designed area is increase of design8

which assume to be strong relation with design efforts.

Fig. 1. 3. 2

Trend of number of processors and universities
fabricated chip.

1. 3. 2

Overview of chip fabricationin 2013

Coming from the fact that the normalized chip area isstill growing, we assume the major reason for decrease ofeffort per chip and per unit area due to process scaling.
Fig. 1. 3. 2 shows trends number of professors andActivity Report of VDEC

universities fabricated chip. Number of professors

Table 1. 3. 1 lists chip fabrication schedule in 2013.

who have contracted NDA for process technologies toPlease refer to list in Chapter 2 for details of designers

access design rules and design libraries are, 253, and 28,

and contents of chip designed.

respectively, for 0.18 μm CMOS, and 0.8 um CMOS.
Table 1. 3. 1

Chip fabrication schedule in 2013

○ 0.8 μm CMOS (On-Semiconductor - Sanyo)
Chip application deadline

Design deadline

Chip delivery

2013 #1

2013/ 6/ 3

2013/ 8/26

2013/12/10

2013 #2

2012/ 1/10

2014/ 3/24

2014/ 7(Schedule)

Chip application deadline

Design deadline

Chip delivery

2012 #5

2013/ 1/ 8

2013/ 3/12

2013/ 5/16

2013 #1

2013/ 3/25

2013/ 6/17

2013/10/16

2013 #2

2013/ 5/ 1

2013/ 7/24

2013/10/16

2013 #3

2013/ 6/19

2013/ 9/11

2013/12/26

2013 #4

2013/ 7/29

2013/10/21

2014/ 2/14

2013 #5

2013/11/ 4

2014/ 1/27

2014/ 5/14

Chip application deadline

Design deadline

Chip delivery

2013/ 6/12

2013/ 7/24

2013/11/12

Chip application deadline

Design deadline

Chip delivery○ 0.18 μm CMOS (Rohm)○ 65 nm CMOS (eShuttle/STARC)

2013 April○ 28 nm CMOS (STMicro/CMP)

2013 Nov.

2013/11/24

This chip fabrication is carried out as METI/STARC project.

VDEC2014̲E.indb 8

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1. 3. 3

Libraries and design flows

and design flows for digital design and PDKs for analog
design. Table 1. 3. 2 lists libraries available now.

VDEC have been working to prepare design libraries
Table 1. 3. 2

Libraries available for VDEC chip fabrication

Technology

Name

AuthorContents

0.18 μm CMOS
(Rohm)

Rohm
library

Rohm Library
Std. Cells, IO cells, RAM(Distributed with CDROM)

Synthesis(Synopsys)
Simulation(VerilogXL)
P&R(LEF/DEF)

Kyodai
Library

Synthesis(Synopsys)
Simulation(VerilogXL)
P&R(Astro)

Todai
Library

Synthesis(RTL Compiler)
VDEC
Design flow based on library prepared by
Onodera Lab., Kyoto University

Simulation(VerilogXL)
P&R(Encounter)

VDEC2014̲E.indb 9VDEC

PDK(IC6.1)

1-3
9

Activity Report of VDEC

PDK

Chapter 1

Onodera Lab., Kyoto University

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1. 4 Seminar
Seminar is indispensable for the improvement of LSI

teachers gave lecturers on transistor level circuit design

design technology. Some seminar and forums, such ascourse, and digital circuit design course under the VDEC

technical seminar for CAD use, refreshing seminar for

EDA environment. Teachers and students up to 40 people

working people, designerʼs forums for young professors

attended a lecture in each course, and master the use

and students were held in 2011.

of each tool for VLSI design flow that uses the VDEC

【Technological seminar for CAD use】

library. Moreover, another technical seminar for CAD use
for matured teachers and students was held in March by

In a technological seminar for CAD use, VDEC

Cadence 2 kind and 3 days, Synopsys 1 kind and 1 days,

Chapter 1

invites lecturer from each tool vender, such as Cadence,

Agilent 1 kind and 1 days (Table 1. 4. 1). The demand

Synopsys and Agilent, to hold the CAD operation course.

for these CAD technological seminars is very large, andMoreover, the course concerning the design flow in

VDEC has maintained the mechanism of a large-scale

the VDEC environment was held by the VDEC staff. A

CAD technological seminar holding corresponding to this

1-4

technological seminar for CAD use for the beginner was

situation. So far, the seminar was held at the University

held in The University of Tokyo VDEC in August andof Tokyo OR other VDEC branch, however, we started

September at the year 2013. This seminar took 5 days forto distribute the lecture using Web streaming, so that

2 kinds of Cadence tools, 5 days for 3 kinds of Synopsys

students around VDEC branch can take the seminar attools, 1 days for 1 kind of Agilent tool. In addition, VDEC

the branch school.

10

Activity Report of VDEC

Table 1. 4. 1 CAD technological seminar in summer of the year 20132013/08/05-06

Synopsys DesignCompiler+Power Compiler Seminar

Univ. of Tokyo19

2013/08/05-06

Synopsys DesignCompiler+Power Compiler Seminar

Tohoku Univ.

2

2013/08/05-06

Synopsys DesignCompiler+Power Compiler Seminar

Nagoya Univ.

11

2013/08/05-06

Synopsys DesignCompiler+Power Compiler Seminar

Kyoto Univ.

2

2013/08/07-08

Synopsys Milkyway+IC Compiler Seminar

Univ. of Tokyo25

2013/08/07-08

Synopsys Milkyway+IC Compiler Seminar

Tohoku Univ.

4

2013/08/07-08

Synopsys Milkyway+IC Compiler Seminar

Nagoya Univ.

2

2013/08/07-08

Synopsys Milkyway+IC Compiler Seminar

Kyoto Univ.

8

2013/08/07-08

Synopsys Milkyway+IC Compiler Seminar

Osaka Univ.

6

2013/08/07-08

Synopsys Milkyway+IC Compiler Seminar

Hiroshima Univ.

3

2013/08/09

Synopsys VCS-AMS(XA)+Mixed Signal sim Seminar

Univ. of Tokyo10

2013/08/09

Synopsys VCS-AMS(XA)+Mixed Signal sim Seminar

Tohoku Univ.

3

2013/08/09

Synopsys VCS-AMS(XA)+Mixed Signal sim Seminar

Nagoya Univ.

1

2013/08/09

Synopsys VCS-AMS(XA)+Mixed Signal sim Seminar

Kyoto Univ.

7

2013/08/09

Synopsys VCS-AMS(XA)+Mixed Signal sim Seminar

Osaka Univ.

7

2013/08/09

Synopsys VCS-AMS(XA)+Mixed Signal sim Seminar

Hiroshima Univ.

2

2013/08/26-27

Cadence ADE Simulation Seminar

Univ. of Tokyo26

2013/08/26-27

Cadence ADE Simulation Seminar

Tohoku Univ.

6

2013/08/26-27

Cadence ADE Simulation Seminar

Nagoya Univ.

1

2013/08/26-27

Cadence ADE Simulation Seminar

Kyoto Univ.

2

2013/08/26-27

Cadence ADE Simulation Seminar

Osaka Univ.

4

2013/08/26-27

Cadence ADE Simulation Seminar

Hiroshima Univ.

4

VDEC2014̲E.indb 10

14/07/28 12:05

Miyazaki Univ.

16

2013/08/28-30

Cadence IC ６１x Virtuoso Layout Seminar

Univ. of Tokyo24

2013/08/28-30

Cadence IC ６２x Virtuoso Layout Seminar

Tohoku Univ.

10

2013/08/28-30

Cadence IC ６４x Virtuoso Layout Seminar

Nagoya Univ.

1

2013/08/28-30

Cadence IC ６５x Virtuoso Layout Seminar

Kyoto Univ.

3

2013/08/28-30

Cadence IC ６６x Virtuoso Layout Seminar

Osaka Univ.

6

2013/08/28-30

Cadence IC ６６x Virtuoso Layout Seminar

Hiroshima Univ.

3

2013/08/28-30

Cadence IC ６７x Virtuoso Layout Seminar

Miyazaki Univ.

14

2013/09/09-10

Digital Design Flow on VDEC Environment Seminar

Univ. of Tokyo30

2013/09/11-12

Transistor Level Design Flow on VDEC Environment seminar

Univ. of Tokyo26

2013/09/13

Agilent GoldenGate Seminar

Univ. of Tokyo7

2013/09/13

Agilent GoldenGate Seminar

Tohoku Univ.

2

2013/09/13

Agilent GoldenGate Seminar

Kyoto Univ.

1

2014/03/03

Synopsys CustimSim-VCS Co-sim Seminar

Univ. of Tokyo7

2014/03/03

Synopsys CustimSim-VCS Co-sim Seminar

Hokkaido Univ.

12

2014/03/03

Synopsys CustimSim-VCS Co-sim Seminar

Tohoku Univ.

1

2014/03/03

Synopsys CustimSim-VCS Co-sim Seminar

Kanazawa Univ.

1

2014/03/03

Synopsys CustimSim-VCS Co-sim Seminar

Osaka Univ.

2

2014/03/03

Synopsys CustimSim-VCS Co-sim Seminar

Hiroshima Univ.

2

2014/03/03

Synopsys CustimSim-VCS Co-sim Seminar

Nagasaki Univ.

2

2014/03/04

Cadence Encounter Test Seminar

Univ. of Tokyo5

2014/03/04

Cadence Encounter Test Seminar

Hokkaido Univ.

10

2014/03/04

Cadence Encounter Test Seminar

Tohoku Univ.

1

2014/03/04

Cadence Encounter Test Seminar

Kanazawa Univ.

2

2014/03/04

Cadence Encounter Test Seminar

Osaka Univ.

1

2014/03/04

Cadence Encounter Test Seminar

Hiroshima Univ.

3

2014/03/04

Cadence Encounter Test Seminar

Nagasaki Univ.

3

2014/03/26-27

Cadence IC615 Virtuoso Seminar

Univ. of Tokyo12

2014/03/26-27

Cadence IC615 Virtuoso Seminar

Hokkaido Univ.

10

2014/03/26-27

Cadence IC615 Virtuoso Seminar

Tohoku Univ.

5

2014/03/26-27

Cadence IC615 Virtuoso Seminar

Kanazawa Univ.

11

2014/03/26-27

Cadence IC615 Virtuoso Seminar

Osaka Univ.

7

2014/03/26-27

Cadence IC615 Virtuoso Seminar

Hiroshima Univ.

3

2014/03/26-27

Cadence IC615 Virtuoso Seminar

Tsuruoka Kosen

1

2014/03/26-27

Cadence IC615 Virtuoso Seminar

Nagasaki Univ.

3

2014/03/25

Agilent Momentumn Seminar

Univ. of Tokyo6

2014/03/25

Agilent Momentumn Seminar

Hokkaido Univ.

8

2014/03/25

Agilent Momentumn Seminar

Tohoku Univ.

4

2014/03/25

Agilent Momentumn Seminar

Hiroshima Univ.

3

VDEC2014̲E.indb 11

1-4
11

Activity Report of VDEC

Cadence ADE Simulation Seminar

Chapter 1

2013/08/26-27

14/07/28 12:05

【Refresh Seminar for Working People】

from many societies.
Course A: analog integrated circuit design (1/7–1/9),

Chapter 1

Teachers of universities and designers in the first line

in addition, newly-star ted Course M1: MEMS designof the enterprise were invited to the lecturer at "VLSI(1/21–1/22), and Course M2: MEMS fabrication

design refresh seminar" was held aiming at the latest,(3/4–3/6) of three courses were held concerning VLSI

advanced knowledge and technical learning concerning

design of recent year. 7 teachers from industr y and

VLSI design as a refreshing education for working people

universities involved in the integrated circuit research

involved in the integrated circuit industry (Table 1. 4. 2).

and the education were invited as the lecturer, and theyThough this seminar started chiefly in year 1998 under

introduced a state-of-the-ar t VLSI design technology

the support of Ministry of Education Technical Education

including the practice using a lecture concerning VLSIDivision to give practicing education of the latest VLSI

design and the latest CAD tool. The participants were 13,

design technology, it continues under many suppor ts

13 and 11 people for course A, M1 and M2, respectively.

1-4
12

Activity Report of VDEC
Fig. 1. 4. 1 Refresh Seminar at VDEC seminar room at the University of Tokyo, VDEC.

Table 1. 4 .2 Refresh Seminar
Course A: Analog Circuit Design (3 days)
Analog Circuit Design and simulation
Integrated Circuits Verification (LVS, DRC)
Masahiro Sugimoto (Chuo Univ.), Hidetoshi Onodera(Kyoto Univ.), Koji Kotani (Tohoku Univ.)

Course M1: MEMS Design (2 days)
MEMS Basic 1: Fabrication Process
MEMS Basic 2: Operation Principle
Structual Design
Layout Design
Yoshio Mita (Univ. of Tokyo)

Course M2: MEMS Fabrication (3 days)
CAD Design and Analysis
Lithography, Etching, Release
Vibration measurement and analysis
Yoshio Mita (Univ. of Tokyo)

VDEC2014̲E.indb 12

14/07/28 12:05

【Designerʼ s forum for young eachersand students】

the failure case and the solution in which LSI designer
has a hard time, the inside stor y of CAD industr y,
the constr uction method in the design milieu in the

VDEC LSI designer forum intended for students andlaboratory, and so on. This year, we had the meeting inyoung teachers has been held. The VDEC LSI designer

The University of Tokyo, Takeda hall from August/24 toforum has aimed to sharing information that cannot be

25. No less than 50 participants were flourishing at theobtained at a society and a academic society, for example,

gathering.

Table 1. 4. 3 Program of Designers Forum in 2011.
8/24 (Sat)VDEC Designers' Forum
Reception

10:00-10:10

Opening Remark

10:10-10:50

VDEC Prenary（VDEC Prof. Takeshi Shimizu）(rest)

11:00-17:30

VDEC Design Award Presentaion

17:30-19:00

VDEC Design Award Reception

1-4

19:00

Ph.D. session & Poster session

13

10:00-13:00

Linux Intro and CAD install/setup

Activity Report of VDEC

8/25 (Sun) VDEC Seminar

VDEC2014̲E.indb 13

Chapter 1

9:10-10:00

14/07/28 12:05

1. 5 Facilities
The VDEC has provided the big facilities forand installed several big apparatuses. The apparatuses

universities in Japan from the beginning of the VDEC

include rapid EB lithography machine (ADVANTEST

foundation (1996). Big facilities refer to those which are

F7000S-VD02), backside access FIB machine (FEI V400

impossible to acquire and or maintain by an individualACE), batch etching machines (ULVAC CE-S and SPTS

research unit. Table 1. 5. 1 shows the available facilities

DRIE MUC-21 ASE-Pegasus). From April 2013 to Marchof VLSI testers and some process machines, which are

2014, the EB lithography machine F5112 has been used

placed at the tester room and the super clean room of the

1,602 times. The reason of the slight decrease from last

Takeda building. In 2004, the VLSI tester (T2000) and theyear (1,882 times) is machine closure for new equipment

Chapter 1

EB lithography machine (F5112+VD01) were donated to

installation. Average exposure count is increased to 160/

the VDEC by the ADVANTEST. In the year 2012, VDEC

month in FY2013 from that of FY2012 (157/month). The

joined MEXT (Ministry of Education)ʼs Nanotechnology

facilities for the LSI testing can be used after attending

platfor m to enforce its multi-use capability. (Forthe technical seminar. The licenses are also required to

1-5

Nanotechnology Platform refer section 1.8). In the year

use the EB lithography and the FIB.

14

2013, VDEC acquired governmentʼs supplemental budget

Activity Report of VDEC

Table 1. 5. 1

Available facility list

Facility

Equipment name

Description

StatusContact

Logic LSI
test System

EB tester:
IDS10000

The chip surface voltage during operation canbe measured with the LST tester.
The digital circuit with 384 pins, 1GHz can betested.

Available

equipment@
vdec.u-tokyo.ac.jp

LSI tester:
HP8300The digital circuit with 384 pins, 1GHz can betested.

Available

HP83000@
vdec.u-tokyo.ac.jp

LSI tester:
ADVANTEST T2000

The digital circuit with 256 pins, 512MHz can betested. Analog test is optional.

Available

equipment@
vdec.u-tokyo.ac.jp

FIB: IDSP2X

Cutting wires of LSIs and depositing Pt wires
are available to repair the LSI design errors.

Available

IDSP2X@
vdec.u-tokyo.ac.jp

Auto prober:PM-90-A

Automated prober for testing LSI wafers, which
can be used with the LSI testers. The probecard for LSIs with the VDEC standard pin connections is available.

Available

equipment@
vdec.u-tokyo.ac.jp

Analog/RF measurement
system:
HP4156B, HP4284, etc

DC parameter measurement、Capacitancemeasurement, Network analyzer, Spectrum analyzer, etc.

Available

equipment@
vdec.u-tokyo.ac.jp

Low-noize manual prober:Cascade Microtec

6 inch wafer can be measured with six DC probles and two RF probes upto 50 GHz.

Low-noize, temperature
controlled semi-auto prober: Süss Microtec

8inch wafer can be measured. The chip temperature range is -50 to 200 ℃.

Mask lithography, Direct
lithography: F5112+VD01

Minimum linewidth: 50nm.
Lithography for 5 inch photomask (thickness:
2.3 mm), 2-8 inch wafers, and chips is possible.

Available

equipment@
vdec.u-tokyo.ac.jp

Rapid Mask and Direct
lithography: F7000S-VD02

Minimum linewidth: 1xnm.
Lithography for 5 inch photomask (thickness:
2.3 mm), 2-8 inch wafers, and chips is possible.
Stencil character projection of non-squareshapes such as circle, triangle is possible.

In preparation

Chlorine ICP plasma
etcher CE-S

High density plasma etching with Cl2 and BCl3
is possible.

In preparation

Silicon DRIE MUC-21
ASE-Pegasus

High speed, high aspect ratio etching of silicon
is possible

In preparation

FIB:
SII XVision200TB

Repairment of photomask, sample etching, etc.
(Through Nanotech. Platform and LCNet)

Available

Analog/RF
measurement system

EB lithography system

FIB system

VDEC2014̲E.indb 14

equipment@
vdec.u-tokyo.ac.jp

14/07/28 12:05

1. 6 Activity plan for 2014
VDEC will continue activities on chip fabrication

continue analog RF design environment, GoldenGate andser vices, CAD tool support, dispatching design related

ADS by Agilent, C-based design environment, BachC

information and donated division“D2T”，as has been

by Sharp. In addition, we continue trial of several CAD

previous years.

tools, such as layout platform, Lavis by TOOL. Design【Design related information
dispatching/Seminar】
We will continue holding the following seminars: (1)Cadence tools and will be continued. Smar tSpice by
Silvaco, will be also continued.

【Chip fabrication services】

1997, (2)“Refresh seminar” since 1998, (3)“Designerʼ

We will continue chip fabrication ser vices for

Forum” since 1997. We will also continue seminars for0.18 μm C M O S b y R o h m , a n d 0.8 μm C M O S b y

LSI tester usage at VDEC and sub-centers, workshops on

On-semiconductor-Sanyo as the regular ser vices. We

LSI testing technologies initiated by D2T.

will start regular services of FD-SOI 28 nm CMOS by ST
Microelectronics through CMP. We will ask packaging for【CAD tool support】

the above chip fabrications to J-Device to meet the diverse
needs of the assembly.

Mentor tools as the main stream design tools. We will
Table 1. 7. 1

Chip fabrication schedule【CMOS 1.2μm 2P2M】 On-Semiconductor (Former Motorola Japan)
Chip application deadline

Design deadline

Chip delivery

2014 #1

2014/ 7/14

2014/10/ 6

2014/12/29

2014 #2

2014/12/29

2015/ 3/23

2015/ 6/15

Chip application deadline

Design deadline

Chip delivery

2014 #1

2014/ 1/27

2014/ 4/21

2014/ 8/11

2014 #2

2014/ 4/14

2014/ 7/ 7

2014/10/27

2014 #3

2014/ 6/ 9

2014/ 9/ 1

2014/12/15

2014 #4

2014/ 8/25

2014/11/17

2015/ 3/16

2014 #5

2014/11/ 3

2015/ 1/26

2015/ 5/18

1-6
15

Activity Report of VDEC

We will continue Cadence tools, Synopsys tools andChapter 1

CAD tools seminars which have been continued sincedebugging platform from SpringSoft has merged into

【CMOS 0.18μm 1P5M (+MiM)】 Rohm

【FD-SOI CMOS 28 nm 1P10M】ST Microelectronics
Based on the chip fabrication schedule through CMP.

VDEC2014̲E.indb 15

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1. 7 Venture companies related to VDEC
Some professors related to VDEC started venture companies. The following is a list of the venture companies related
to VDEC.
[1] AIL Co.,Ltd. (http://www.ailabo.co.jp/)
Related professor : Professor Kazuo Taki, Kobe Univ. (President-Director)[2] Synthesis Corporation (http://www.synthesis.co.jp/)
Related professor : Professor Emeritus Isao Shirakawa, Osaka Univ. (Director)

Chapter 1

Description of business : (1) Hardware/software co-design(2) System LSI design, design services(3) Development and sales of IPs(4) Development of EDA tools

1-7
16[3] ASIP Solutions, Inc. (http://www.asip-solutions.com/)
Related professor : Professor Masaharu Imai, Osaka Univ. (Representative Director and CTO)

Activity Report of VDEC

Description of business : (1) EDA Tool
(2) Design Service and Consultation(3) IP Development[4] Nanodesign Corporation (http://www.nanodesign.co.jp/)
Related professor : Professor Kazuyuki Nakamura, Kyushu Institute of Technology. (Representa-tive Director)[5] A-R-Tec Corp. (http://www.a-r-tec.jp/)
Related professor : Professor Emeritus Atsushi Iwata, Hiroshima Univ. (Representative Direc-tor)
Description of business : (1) Measurement and analysis of LSI substrate noise(2) Design of analog-RF mixed signal LSIs
(3) Training of analog design on the JOB method

VDEC2014̲E.indb 16

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I. 8 “Nanotechnology Platform”:
Ultra Small Lithography and NanometricObservation Siteplatform “Ultra Small Lithography and Nanometric

VLSI activities such as MEMS. The machine is capable

Obser vation Site” together with the Institute ofof rapidly writing patterns on arbitrar y-shaped targets

Engineering Innovation of Graduate School ofsizing from 1cm-sqare chip to 8-inch round wafers. The

Engineering. The site is supported by Japanese Ministry

per formance is measured by the number of researchof Education (MEXT)ʼs Nanotechnology Platform grant.

reports and machine use. The University of Tokyo site

Any researchers in Japanese Universities, Laboratories,

has received 150 research reports including 9 from big

and Companies can take full advantage of The University

companies, 3 from SMEs, 32 from other universities,

of Tokyoʼs cutting-edge nanotechnology apparatuses

33 from UTokyo and external collaborators, 67 fromand know-hows. The accessible technology includes

UTokyo researchers (excluding VDEC), and 6 from

Lithography and Etching environment, Ultra High-public research institutes. The exposure count was 1,602

Voltage Acceleration (1MV) transmission electronfor 10 months (160.2/month). “Open ratio” , which is the

microscope (TEM) that is capable of visualizing upto

number of days in which users outside the University oflight materials such as Nitrogen. VDEC takes par t inTokyo came, divided by machine open days, was 99%.

the lithography at Takeda Sentanchi Super Cleanroom.
Through VDECʼs key apparatus F5112+VD01 donated

VDEC2014̲E.indb 17

URL:http://nanotechnet.t.u-tokyo.ac.jp/

1-8
17Activity Report of VDEC

from Advantest Corporation, VDEC is supporting post-

Chapter 1

VDEC is operating an open-use nanotechnology

14/07/28 12:05

Chapter 2 Activity Report of“D2T Research Division”
2. 1 Introduction of “D2T Research Division”
2. 1. 1 Aim of “D2T Research Division”

had finished in September 2010 and September 2013,
respectively. The third phase star ted at October 2013

ADVANTEST D2T research division was establishedthrough the courtesy of Advantest Corporation. This year

in VDEC in October 2007. It continued for 3 years. As thewas the first year of the third phase, so we have actively

name of the research division indicates, it is financiallyconducted researches, educations, and symposium insupported by ADVANTEST Corporation. Through thethe area of design and test. In this year, we invited two

kindness of ADVANTEST Corporation, the research divi-

visiting professors, Prof. Krishnendu Chakrabarty fromsion was renewed and the second phase of D2T research

Duke University and Prof. Subash Shankar from (Citydivision started from October 2010.

University of New York). They had made the big impact

The aim of D2T research division is to promote theas members of D2T group.

research and education environment of VLSI testing in
all universities and colleges in Japan. “D2T” means that

2. 1. 2

we consider not only design but also test. As the results

Members of “Advantest D2T
Research Division”

of our activities, we hope to provide the experts of design

Staff

Chapter 2

and test for industr y. In addition, we are exchanging

Project Associate Professor Satoshi Komatsu

researchers with other universities or research instituteProject Assistant Professor Rimon Ikeno

in both Japan and overseas. Moreover, D2T research divi-

Project Researcher

James Tandon

sion is in a good environment to make collaboration with

Project Researcher

Nguyen Ngoc Mai Khanh

2-1industry because testing of VLSI is one of the most practi-

Researcher

Takahiro Yamaguchi

18

cal research topics in industry. Based on those activities,
our final goal is to become a center of excellence of VLSI(Advantest Laboratories Ltd.)
Researcher

ADVANTEST D2T Research Division

Testing in Japan.
The first phase and the second phase of D2T activities

VDEC2014̲E.indb 18

Masahiro Ishida(Advantest Corporation)

Assistant Clerk

Makiko Okazaki

14/07/28 12:05

2. 2 Report of “D2T Symposium”“The 8th VDEC D2T Symposium” took place on

Solutions for Future LSI Systems and Testing”, a variety

October 24th, 2013 at Takeda Building. In the sympo-

of topics was actively discussed among panelists and audi-

sium, five outstanding researchers were invited to giveences.

the state-of-the-art researches in the field of cyberphysi-

More than 100 researchers from industr y as well

cal systems, 2.5D/3D tests, yield enhancement of LSIs,

as professors / students attended the symposium. We

and mixed-signal DFT. In addition to the invited talks, thebelieve the symposium was very interesting and exciting

members of “Advantest D2T Research Division” reported

one for all attendees. VDEC will continue to have the sym-

their activities. In the panel session titled “Challenges andposium in future and we hope for your joining the events.

Chapter 22-2
19

ADVANTEST D2T Research Division

VDEC2014̲E.indb 19

14/07/28 12:05

Symposium Program
10:00

Opening Remark
Kunihiro Asada (Director of VLSI Design and Education Center, University of Tokyo)
Toshio Maruyama (Chairman of the Board and Representative Director, Advantest Corporation)

10:10

Session 1“Technologies and Platforms for Cyberphysical Systems”
Giovanni De Micheli (Ecole Polytechnique Federale de Lausanne)“Test and Design-for-Testability Solutions for 2.5D/3D Integrated Circuits”
Krishnendu Chakrabarty (University of Tokyo / Duke University)“Activities of VDEC Advantest D2T Research Division”
Satoshi Komatsu (University of Tokyo)

12:05

Lunch

13:20

Session 2“Universal Methodology for Yield Enhancement of ULSIC's Employing Product Test, IC Layout andComprehensive Suite of Characterization Vehicles”
Andrzej Strojwas (Carnegie Mellon University / PDF Solutions, Inc.)“Signal and Noise: A Radical Perspective on Mixed-Signal Test Research and Education”
Mani Soma (University of Washington)“A Stochastic Sampling Time-to-Digital Converter”
Takahiro J. Yamaguchi (Advantest Laboratories)

Chapter 2

15:15

Coffee Break

15:40

Session 3“Synthesis from Oracles”
Subash Shankar (University of Tokyo / City University of New York)

2-2“Layout Design for Practical Application of Electron-Beam Lithography with Character Projection Technique”
Rimon Ikeno (University of Tokyo)

20

ADVANTEST D2T Research Division“Introduction of Multi-Purpose EB Lithography system F7000S”
Masahiro Takizawa (Advantest)
17:00

Panel Discussion “Challenges and Solutions for Future LSI Systems and Testing”
Moderator: Krishnendu Chakrabarty (University of Tokyo / Duke University)
Panelists:
Andrzej Strojwas (Carnegie Mellon University / PDF Solutions, Inc.)
Giovanni De Micheli (Ecole Polytechnique Federale de Lausanne)
Mani Soma (University of Washington)
Takahiro J. Yamaguchi (Advantest Laboratories)

18:20

Closing Remark

18:30

Reception

VDEC2014̲E.indb 20

14/07/28 12:05

2. 3 Research Activity Reports of“Advantest D2T Research Division”
on-chip power deliver y network by judging Pass or
On-chip Digitizer/On-chip Spectrum Analyzer

Fail of the device under test while injecting controlled

Takahiro Yamaguchi, James Tandon, Nguyen Ngoc

power supply noises into on-chip power supply nodes.

Mai Khanh, Satoshi Komatsu, Kunihiro Asada

In order to validate the concept of our method, we have

We introduced a stochastic time-to-digital converter(TDC) with 180-770fs tunable resolution, less thanfabricated a TEG chip with Rohm 0.18-um CMOS process.

0.6LSB INL, and selectable dynamic range of fset.
Previous arbiter-based TDCs had fine resolution but
small dynamic range which was difficult to calibrate.
Our approach uses comparators as decision elements
to precisely control dynamic range offset.

Structural Test Technique for Analog Circuits
Satoshi Komatsu
In this research, we propose an ef fective test
method for system LSIs by introducing structural test

digital conver ter (ADC) core for the of fset control,

approaches used in digital testing for analog circuit

which is based on the flash ADC architecture withtests. Both digital circuits and analog circuits are often

63 clocked comparators giving 6-bit resolution at the

integrated into a system LSI, so the final target of theoutput. It is our first test chip using 28 nm FD (fully

research is to test analog circuits by using digital cir-

depleted) SOI/CMOS process, and we plan to evaluate

cuits using structural test manner. This year, we havethe impact of process variations to clocked comparator

investigated and analyzed observability and controlla-

stability as well as the basic ADC performance.

bility of such system LSIs and conducted some experiments about the observability and controllability.

Chapter 2

We designed a test chip of the rail-to-rail analog-to-

2-3
Method for Testing Power Integrity Fault
High-throughput and high-accuracy electron-beam

Kunihiro Asada

direct writing (EBDW) strategy for wide range ofWhile a required power supply voltage has become

EBDW applications

lower due to the advanced miniaturization of the semi-

Rimon Ikeno, Satoshi Komatsu, Yoshio Mita, andconductor process, the power supply current consumed

Kunihiro Asadaby an LSI chip has increased because of the huge num-

Electron-beam direct writing (EBDW) lithography

ber of transistors integrated on a single chip. It may

is widely used in fabrication of not only semiconduc-increase the power supply noise, and power integrity

tor devices but also MEMS and photonic devices,

issues of the device under test in both an ATE and abecause it offers low-cost and short turn-around timepractical operating environments.

(TAT) device fabrication opportunity with its mask-

In this research project, we proposed a power integri-

less feature. On the other hand, EBDW is known as aty fault testing method for detecting the power integrity

low-throughput lithographic technology, despite somefaults, e.g. excessive fluctuations of the power supply

evolutional techniques have already been introduced

voltage and excessive variations of the power supply

and utilized such like Variable Shaped Beam (VSB)

impedance, at the on-chip power supply nodes of theand Character Projection (CP) methods. In general,

device under test. The proposed method evaluates thehigh-throughput means less e-beam shots. Then, in

power integrity faults by observing an operation of thesome cases, the lithographic results have poor accu-

device under test while controlling its power integrity

racy against the intended layout shapes, or they showwith synchronizing to the device operation by using on-

roughness on their edges, if the data decomposition

chip noise sources. Furthermore, it can test a tolerance

from the original layouts to e-beam shots is not appro-of the device under test against power integrity in thepriately processed.

VDEC2014̲E.indb 21

21

ADVANTEST D2T Research Division

Toru Nakura, Masahiro Ishida, Satoshi Komatsu,

14/07/28 12:05

In 2013, we star ted a collaborative research withand future expectations through their device fabrica-

Advantest Corp. on the total solution of the high-speedtion using EBDW. We investigated software frameworkand high-accuracy CP EBDW technique for wide range

for new layout-data conversion flow, and started imple-of EBDW applications like MEMS, photonics, and somenting geometric routines and CAD-tool interfaces.

on.

We also designed a CP mask for our experiments toThis year, we discussed with EBDW users in Takeda
Super Clean Room, and extracted their past findings

investigate efficient character sets for wide range of
EBDW applications.

Chapter 2

2-3
22

ADVANTEST D2T Research Division
VDEC2014̲E.indb 22

14/07/28 12:05

2. 4 Publications
Komatsu, and Kunihiro Asada, “A Stochastic Sampling

Journals[1]

T ime-to-Digital Conver ter with T unable 180-770fs
Resolution, INL less than 0.6LSB, and Selectable

Rimon Ikeno, Takashi Mar uyama, Satoshi Komatsu,

Dynamic Range Of fset,” IEEE Custom Integrated

Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada, “High-Circuits Conference (CICC), September 2013.

throughput Electron Beam Direct Writing of VIA Layers
by Character Projection with One-dimensional VIA[2]Takahiro. J. Yamaguchi, James S. Tandon, Satoshi
Komatsu, and Kunihiro Asada, “A Novel Test Structure

Characters,” IEICE Transactions on Fundamentals offor Measuring Variance of Thr eshold Voltage inElectronics, Communications and Computer Sciences,

MOSFETs,” 2013 IEEE International Test Conference,

Vol.E96-A, No.12, pp.2458-2466, Dec. 2013.

September 2013.
[3]

International Conferences/
Symposiums/Workshops[1]

S. Komatsu, “On-chip Measurement / Monitor Circuits
Based-on Stochastic Approach,” 2013 International Test
Conference (Elevator Talk), September 2013.

James S. Tandon, Takahiro J. Yamaguchi, Satoshi

Chapter 2

2-4
23

ADVANTEST D2T Research Division

VDEC2014̲E.indb 23

14/07/28 12:05

Chapter 3 Research in VDEC

Asada, Nakura and Iizuka
Laborator yfaster circuits, while also contributing to reduction of（http://www.mos.t.u-tokyo.ac.jp）

the time domain circuits over voltage-domain circuits

jitter. This paper aims at verifying the effectiveness ofin terms of their dynamic range performances, where
It has been shown that for a given technology the

Supply Fluctuation Monitoring and Reduction

time domain dynamic range is superior to the voltage

Methoddomain dynamic range by a factor of（ωT =B）2 where

Kunihiro Asada, Toru Nakura, and Yoshitaka Yamauchi

ωT is the unity gain frequency and B is the bandwidth.

While the supply voltage is lowering due to the scal-

To accurately estimate the impact of aging on theing rule, the power supply current in the LSI is increas-

circuit reliability, a simulation technique of NBTI degra-

ing because of the progress of integration. As a result,dation under the actual operating condition is essential.

the supply fluctuation becomes more serious for practi-Thus, we also propose a faster circuit simulation meth-cal operations and to ensure the power integrity of theod for NBTI degradation in this study. By use of circuit

LSI needs more cost. For example, much chip area iselements to express the physical phenomenon of NBTI

paid for decoupling capacitors on the chip to reduce di/degradation, the proposed scheme has achieved the

dt noise and resonant noise.

estimation of NBTI degradation simultaneously with

To mitigate the chip area penalty for on-chip decou-

the circuit simulation. In addition, the proposed method

pling capacitors, a supply fluctuation cancellation

can realize accelerated degradation test by tuning themethod named active charge sharing has been pro-parameters of the circuit elements.

posed. This method aimed to reduce the supply fluctuation mainly caused by DVS. This year, we proposed a
new supply fluctuation monitoring circuit to apply the

CMOS Imaging Sensing in THz band
Kunihiro Asada, Toru Nakura, Tetsuya Iizuka,

by DVS scheduled in OS but also caused in hardware

Parit Kanjanavirokju, Shinichi Miuralevels. The monitoring circuit consists of TDC and DLL

The reason that THz Imaging system cannot be wide-and detects average supply fluctuation in clock cycles

ly commercialized is lack of portable, high-power, andby utilizing the gate delay dependence on the sup-cheap source. Photonics source is always large because

ply voltage. The behavior of the proposed circuit was

it requires cr yogenic system for efficient operation.

24

checked by circuit simulations. A circuit design for an

Thus it is crucial that electronics source is developed.

Research in VDEC

Chapter 3

cancellation to the supply fluctuation not only caused

experimental verification was completed.

CMOS, as a standard technology for mixed-signal cir-

3-1

cuit in microwave technology, has a very good potential
for implementation of compact THz system in the near
Reliability Improvement of LSIs with the fine pitch

future. However, CMOS operation is limited by Fmax,

process

which is well below 1 THz.

We developed ideas ofKunihiro Asada, Toru Nakura, Tetsuya Iizuka,

high frequency pulse generation that is not limited by

Kevin Nagri, Kazuhiro Mori

Fmax. Instead, high frequency component is extracted

It is believed that the time-domain resolution of afrom fast falling edge generated by CMOS technology,

digital signal edge transition is superior to the volt-

using passive transmission line network. The idea has

age resolution of an analog signal in advanced CMOS

been verified by simulation result. The edge generator

processes. The reasoning behind this is that operating

circuit as a part of the transmission-line-based pulse

voltage has been reducing, making the signal moregenerator was also fabricated on 0.18-μm CMOS andvulnerable to noise power due to scaling. On the other28-nm CMOS.

hand, in time domain, scaling has resulted to design of

VDEC2014̲E.indb 24

Lack of high directivity source is also a limiting fac-

14/07/28 12:05

tor for CMOS 3D imaging system. We propose a novel

threshold control method uses body bias effect and thecoherent imaging system which is superior to the con-threshold compensation method applies amplified volt-

ventional one in size, cost, and mobility and evaluatedage to gate terminals. We evaluated the performance of

it with numerical simulations. The model is based on

the proposed rectifier as a start-up rectifier. As a result,

Hygensʼprinciple. The shape of an unknown object iswhen using only one of the two methods, the perfor-

estimated by varying the directivity patterns of Tx andmance of the rectifier is not good if the load resistance

Rx array antenna, which are implemented on the sameis large or small. In contrast to this, the proposed recti-

plane, and measuring received power repeatedly. Sincefier is always better than Dickson charge pump even if

transmitted patterns are used, constrain on directivity

the load resistance is large or small. In addition to this,of antenna is loosen. A simulation result shows that if

we proposed output voltage universal cur ves, which

we have SNR of at least 10 dB, this model can estimatesnormalize the relation between two design parameters,

shapes with one wavelength accuracy by using proper

the antenna resistance and the load resistance. By uti-

set of directivity patterns for measuring power.

lizing this, the simulation process of rectifiers, whichis laborious due to a lot of transient analyses, can beshortened.

Estimation of wire current utilizing surface magnetic
field for LSI security
Kunihiro Asada, Toru Nakura, Tetsuya Iizuka,

Time-Domain Signal Processing and its Application

Yoji Nakamura

for PLL Design

Sophistication of LSI is advancing while company

Kunihiro Asada, Toru Nakura, Tetsuya Iizuka,with own fabrication is decreasing. They are outsourc-

Toshiyuki Kikkawa, Norihito Tohge, Koji Sato, anding the manufacturing of LSI to companies overseas.

Tomohiko Yano.
In this research, we are engaged in the improve-

however danger of malicious modification to the chip

ment of Pulse Width controlled Phase Looked Loop

increases. Method to find out this modification is need-（PWPLL）. First, we improve the automatic design flow

ed and method utilizing path delay, power consump-for PWPLL. We renovated maintainability and extensi-

tion and other side channel signal is studied. In thisbility of software and increased the number of variable

research method to estimate wire current of LSI whileparameters to enhance the process portability. We dem-

functioning utilizing surface magnetic field is proposed.

onstrated its process portability by applying it for the

Evaluation of proposed method was done in simulation

new 28 nm FD-SOI process. Moreover, we considered

and relation between height of probe, noise figure of

the adaptability of PWPLL against the process variabil-

amplifier, duration of measurement and accuracy ofity. In order to improve this adaptability, we designed aestimation was studied.

variable ring oscillator which can dynamically change
the number of stages according to the control signals.

Rectifier for RF Energy Harvesting

which detects whether the PLL is locked within a cer-

Kunihiro Asada, Toru Nakura, Tetsuya Iizuka,

tain period or not. By HSPICE simulation, the modified

Hiroaki Matsui

PWPLL showed correct operation under process vari-

In RF energy har vesting, where using ambientability.

and faint radio waves as energy sources, a rectifier

Also, we are working for utilizing time-domain signal

is needed to convert AC radio waves to DC. Usually,

processing. We proposed a Pulse Width Accumulator

Dickson charge pump is used as a rectifier of RF ener-（PWACC）circuit for time-domain analog signal pro-gy harvesting. That has two problems, one of those is

cessing. PWACC integrates input pulse width andabout for ward voltage drop of diodes, and the otherrepresents integrated value as output pulse width. In

is about reverse current. In order to overcome theseorder to hold time-domain information in the integrator,

problems, we proposed the rectifier based on Dickson

the PWACC utilizes pulse regeneration ring where twocharge pump, which utilizes both the threshold control

short pulses run around keeping some time differenc-

method and the threshold compensation method. The

es. By changing the positional relation between the two

VDEC2014̲E.indb 25

3-1
25

Research in VDEC

The control signal is generated by a lock detector

Chapter 3This enables Cutting the budget of manufacturing,

14/07/28 12:05

pulses in the ring according to the input pulse width,ver y hard to detect all design bugs in design phases

the output pulse width becomes the integration of the

before fabrication, which increases the number of bugs

input pulse width. We applied the PWACC to a PWPLL

that escape verification processes before fabricationand made zero phase-offset PWPLL. A prototype wasand are firstly detected by running a chip after fabrica-

fabricated by 180 nm standard CMOS process. Time-tion. In addition, a risk of electrical errors is increasing

domain information was also utilized for on-chip trans-

as fabrication processes shrink. Post-silicon valida-

fer function measurement of PLL. In our proposedtion techniques are to validate VLSI chips if there aremeasurement scheme, phase modulation to obtain theerroneous behaviors caused by such bugs or electricaltransfer function is carried out by switching delay onerrors, and useful to avoid the additional costs requiredreference clock of the PLL. Then, the response of thefor re-spins. In this topic, we propose（1）an efficientloop is also observed by TDC as time-domain informa-

method to derive logic functions for programmabletion. We are trying to apply this time-domain informa-

circuits inside designs, which are inserted to improvetion to optimize a bandwidth of PLL under variable con-a chance of validation, and（2）a method to select a set

ditions.

of flip-flops in a circuit so that the number of states thatcan be restored is maximum. The first method enables
us to rectify a buggy circuit using programmability.

Improvement of Detection in Radiation Detector

We confirmed that our proposed method can work

Utilizing Semiconductor Photodiode Based on

for ISCAS benchmarks with up to 100 programmableStandard CMOS Technology

circuits. The second method is based on a formula-

Kunihiro Asada, Toru Nakura, Tetsuya Iizuka,tion with Pseudo-Boolean Optimization（PBO）, which

Zhu Hongbo, Yang Xiao, Masaki Ikegawa

guarantees that a solution is optimum if any solution

Scintillation detectors and semiconductor detectors
have received widespread attention since they can

is found. We are evaluating how large circuits can besolved by PBO solvers.

specify the nuclide of radiation and estimate the arrival
angle. However, traditional detectors have two disadvantages. One is that they can not be carried easily, thePost-silicon Debugging of Designs at Transaction

other is that they do not have enough spatial resolution

Level
Masahiro FUJITA, Amir Masoud GHAREHBAGHI

the detector using the cube scintillator, SPAD（Single

Moder n System-on-Chips（SoCs）are becoming

Photon Avalanche Diode）array image sensors, multi-

more complex as their number of cores increases. As acoated materials, and pinholes. Distributions of theresult, pre-silicon verification methods cannot guaran-

detected photons on the SPAD array are simulated intee implementation of a bug free system. Hence, someadvance, and that distributions are compared with thebugs may escape to prototype or even final system.

26

actual detection results to estimate the trajectory of an

In this research, we introduce a post-silicon debug

Research in VDEC

Chapter 3of radiation position. In prior research, they proposed

electron emitting light. Simulation results verified thatmethod that employs transactions among cores in a

the proposed detector realizes a higher spatial resolu-

SoC. Our method is based on monitoring the commu-

tion than that of the conventional detectors.

nication behavior of the cores（i.e. transactions that are

3-1

sent/received）and using them to backtrack from thecurrent state of the system to the previous states to findFujita Laborator y

the cause of errors. Backtracking is performed in the（http://www.cad.t.u-tokyo.ac.jp/）

transaction-level model of the system, assuming thatthe design of the system has started from that level.
First, we extract a transaction-level state machine of the

Post-Silicon Validation Techniques

system. Then, we employ the chip transaction trace toMasahiro FUJITA, Takeshi MATSUMOTO,

find the execution path on the extracted state machine.

Amir Masoud GHAREHBAGHI, Satoshi JO,

By using formal methods, we check the design proper-

Choudhary SHRIDHAR

ties on the extracted path to find the bugs as well as theDue to increase of the size of VLSI, it has become

VDEC2014̲E.indb 26

constraints that caused the error. To show the effec-

14/07/28 12:05

tiveness of our method, we have selected a distributed

tion for the erroneous signal. We confirmed that ourdeadlock detection and resolution algorithm as our

proposed method successfully rectifies a control circuit

case study. We have implemented it at transaction-levelin an out-of-order pipelined processor with an error

on top of a network-on-chip（NoC）. We show that using

recovery functionality. Also, when the control circuit is

our method, we can successfully backtrack at transac-

implemented by programmable circuits, rectification

tion-level as well as finding constraints on the internal

can be achieved by re-programming those program-variables that has leaded to the error.

mable circuits without changing place and route.

Interconnect Synthesis
Masahiro FUJITA, Jiayi ZHANG
The emerging many-core system-on-chip design

Low Latency Computing using FPGAs
Masahiro FUJITA, Takeshi MATSUMOTO,
Naoki TAGUCHIFor applications which require very low latency oper-

nect system. Network-on-Chip（NoC）is one of theations, application-specific hardware implementations

candidates which may meet this requirement best. By

can achieve lower latency than software implementa-

deploying the NoC, the next generation of the intercon-

tions running on general purpose processors. This isnect structure, system designer can reduces the design

because, in application-specific hardware, we can utilize

effort significantly. However, to design a NoC which iscustomized memor y systems and arithmetic circuit

able to be compatible to the protocols of existing IPs,

modules for a target application, and those modules

to efficiently utilize the bandwidth and to be reliable

and memories can run in parallel. In this research, foris still a challenge. We would like to ease the design

a line-handler in stock trading systems as an example,

challenge by developing a tool which will automate thewe implemented it on FPGA in order to achieve lower

design process. This tool uses the protocols of desiredlatency. A line-handler is used in high frequency trading

IPs and the specification of data flows among these IPs

such as algorithmic trading. It accepts buy/sell orders

as input information. It is able to automatically output

from clients and sends them to a stock exchange after

the optimal interconnect with mesh network-on-chip asformatting them to a specified format by the stockback bone and insert protocol converters for the mis-exchange. By executing with our FPGA system, behav-

matched IP pairs.

iors of the line-handler can be completed several micro
seconds, while a software implementation spends morethan 20 micro seconds for the same behavior. For fur-

Verification and Debugging of Processor

ther lower latency, we have a plant to implement TCP

Architecturescommunication processing as customized hardware as

Masahiro FUJITA, Amir Masoud GHAREHBAGHI,

well as the line-handler.

3-1
27

Takeshi MATSUMOTO, Satoshi JO
plicated by adopting various functionalities for higher

Hardware Acceleration of Neural Network

performance and more reliability, such as pipelining,

Simulation

speculative execution, and error recovery. To ensure

Masahiro FUJITA, Takeshi MATSUMOTO,

the correctness of complicated processor architectures,

Kosuke OSHIMA, Taro KAWAO

verification and debugging of processor architectures

Recently, improving simulation speed of scientific

are a key issue. In this work, we have proposed a meth-simulation using FPGA or GPU draws much attention

od for debugging and automatic rectification of bugs infrom researchers in various fields, as it can realize a

microarchitecture of processors. The proposed method

high-speed simulation with a low cost. In this topic,

first identifies bug locations in circuits, and then, finds

we have developed a FPGA-based neural network

out a set of input patterns for which an erroneous sig-

simulation. Our simulation is based on DSSN（Digital

nal needs to be changed（i.e. inver ted）, in order toSpiking Silicon Neuron）model. In this model, we needmake the entire behavior of a circuit under debugging

to calculate a weighted sum of all values that are input

correct. As a result, we can get a corrected logic func-

to one neuron from other neurons through synapse.

Research in VDEC

Processor architectures are becoming more com-

VDEC2014̲E.indb 27

Chapter 3

requires high per formance, high reliable intercon-

14/07/28 12:05

To improve simulation speed, we introduced a pipeline
processing to calculate this weighted sum. Since theEfficient Topological Matching Among Multiple

capacity of BRAM in FPGA is limited, it is impossible

Circuits

to store all intermediate data inside FPGA when the

Masahiro FUJITA, Amir Masoud GHAREHBAGHI,

number of neurons is large. To solve this scalability

Hossein IZADI RAD

problem, we utilized on-chip RAM and stored interme-

Recognizing similarities and differences among mul-diate results to RAM. We have developed and evaluatedtiple circuits is very useful for managing and maintain-

several FPGA circuits for neural network simulation,

ing IP libraries. In this work, we address the problem ofand confirmed that 1000 neurons can be simulated on

finding the maximum common subcircuit among two or

FPGA.

more logic circuits. Given the gate-level netlists of thecircuits, first we represent the circuits as graphs. Then,
we try to find the largest common subgraph, following

Design Debugging Support

Chapter 3

3-1

the common approaches that are used for identifying

Masahiro FUJITA, Takeshi MATSUMOTO,

matched graphs. In the first step, we build a conflict

Kosuke OSHIMA, Qinhao WANG, Takashi TOI,

graph from the circuit graphs. In the next step, we try

Takefumi KOGA

to find the largest common subgraph by finding inde-

In hardware designs, a considerable time is spent

pendent sets of the conflict graph, using our proposedfor design debugging. Therefore, automated designnear-linear approximation algorithm. Finally, we try to

debugging techniques are essential to improve design

increase the size of the largest common subgraph byefficiency. In this work, we propose three methods toconsidering neighbors of the circuit graph nodes, step-

support design debugging. One is a method to derive

by-step in a controlled manner. We have performeda correct circuit by replacing some gates in a circuit

extensive experiments on ISCAS85 circuits as wellwith Look-Up Tables（LUTs）and finding a logic func-

as a number of IPs from OpenCores. Comparing ourtion implemented by LUTs when a specification and a

results to the optimum solution that is obtained by ancircuit under debugging is equivalent. However, cor-

exact algorithm, the average size of the identified com-

rection may not be feasible, depending on how LUTs

mon subcircuit is around 10 ％ smaller, but the average

are inserted. In the case, we add an input of LUT andprocessing speed is two to three orders of magnitudeconnect it with a selected signal which satisfies somefaster.

requirement condition. The second method is static
analysis of embedded program with interrupt. Sincefunctions that are called and executed when the main
program is interrupted are usually decided at the timeof interrupt, it is difficult to include such functions in a28

dependence graph of programs. Therefore, we propose

Research in VDEC

to explicitly link those functions with the main function

Hideya Ochiai, AssistantProfessor,（http://www.hongo.wide.ad.jp/~jo2lxq/）

and make a dependence graph including those func-

Facility management with IEEE1888 and embedded

tions. In the last work, we propose a new coverage met-

systems

ric considering to detect mistakes of order of condition-

Hideya Ochiai

al branches. The coverage is calculated by examining

To manage and control the facilities for Smart Grid

all combinations of orders of branches with a set of test

applications, designing and implementing interfaces

patterns. If the output of a program is different fromand protocols for embedded systems to communica-

the original, we decided that the branch order is cov-

tion ser vers over the Internet is necessar y. We haveered. We have confirmed that, in some cases, this new

developed IEEE1888 protocol, implemented it onto

coverage is sensitive to bugs in conditions or branchsuch systems, and demonstrated that it allows the man-orders, while conventional coverage metrics are not.

agement and control of the heating, ventilating and airconditioning（HVAC）systems, light systems and otherfacilities.

VDEC2014̲E.indb 28

14/07/28 12:05

Mita Laborator yArchitecture of IP packet delivery for buildings（http://www.if.t.u-tokyo.ac.jp）

Hideya Ochiai
This work integrates many communication media
used for facility networking in buildings onto the

Study on LSI-MEMS integrated pond-skating robot

Internet Protocol（IP）. We have focused on “IP overfor energy-autonomous distributed microsystems

RS485”and “IP over DTN”architecture, and developed

Y. Mita, I.Mori, Y. Li, A. J. Walton（Univ. of Edinburgh）

the platform that provides IP reachability to the end

As one example of integrated MEMS that is expected

nodes of such facility networks.

to open new research and industrial application fields,
the authors are trying to show a top-down applicationof energy-autonomous distributed microrobots. The

Takamiya Laborator yresearch belongs to the “top-down”research category（http://icdesign.iis.u-tokyo.ac.jp/）

and through the research the team looks for ward toprovide the “Engineered Nature”; the team does notintend to just copy how nature works in implementation

Energy Efficient Extremely Low Voltage VLSI Circuit

level, but to realize with cutting-edge technologies what

Designnature is aiming at in highly-functional level. Recent

Makoto Takamiya, Takayasu Sakurai, Hiroshi Fuketa

top-down activities include autonomous distributed

Reducing the power consumption of every electronic

mobile robot: “Pond Skater”，which to date had notdevice is required to mitigate the global warming. To

been realized by any other microsystems group. The

meet the requirement, VLSI circuit design techniques

availability of a leading low voltage technology at theincluding logic circuits, memor y circuits, analog

Scottish Microelectronic Centre（SMC）the University

circuits, power management circuits, and wirelessof Edinburgh that could electrically change surfaces

transceiver circuits operating with the 0.5-V powerfrom hydrophobic to hydrophilic proved to be crucial tosupply voltage are developed with 65/45 nm CMOS

achieving this goal as was the previous involvement ofprocess to reduce the power consumption to 1/10 of

SMC staff in wireless technology. The major challenge

the conventional VLSIʼs.

is propulsion, and it is clear that directly mimicking
be problematic. The idea that was developed was to

Design of Large Area Electronics with LSIʼs andpropel the device using Electro-Wetting Of Dielectric

Emerging Devices（EWOD）to move air bubbles, which had the signifi-

Makoto Takamiya, Takayasu Sakurai, Hiroshi Fuketa,cant advantage that there we no moving mechanical

Takao Someya, Tsuyoshi Sekitani

parts, which simplified the construction and helped tominimize the weight which was important if the ponds-

where intelligent electronic devices are distributed

kating device was to float using surface tension. Basedon a flexible surface, 10 cm to 10 m on a side, for theon the worldʼs first wireless pond-skating propulsion,

human interface and the comfortable daily life. Flexible

the team is developing VLSI control circuit and integra-

and low-cost organic FETs (OFETs) are suitable fortion technology for continuous skating. In FY2013, sup-large-area electronics and have great potential as a

porting technology, which is on-chip energy source is

supplement of solid and expensive silicon MOSFETs

developed. High-voltage generating photovoltaic cell isfor VLSIʼs. We have proposed and demonstrated several

ameliorated.

3-1
29

Research in VDEC

Large area electronics is a new frontier in electronics

Chapter 3

the pond skating insectʼs propulsion mechanism would

large area applications combining OFETs and VLSIʼ
s and the relevant circuits including Braille display, awireless power transmission sheet, a communication

LSI-MEMS integrated device by submicron-wide

sheet, an EMI measurement sheet, and a User

opening deep reactive ion etching technology

Customizable Logic Paper (UCLP).

Y. Mita, T.N.Binh, T. Sawamura, I.Mori, A.Hirakawa,
M. Kubota
Narrow and deep str uctures such as microholes

VDEC2014̲E.indb 29

14/07/28 12:05

and trenches are playing key roles in modern electro

Institute（ITRI）, the team is developing a “MEMS”

and mechanical systems. In standard micro fabrica-

probe card for electron device testing such as VLSI.

tion technology, patterns are composed of rectangles

The originality is to integrate CMOS preprocessing

and vertically transferred to the depth direction, yield-

circuit to provide high functionality. In the year 2013,

ing long-cubic structures. However, just by thinking

demonstration with real optical device, which is in factof lens shape, one can realize that cubic shape is not

LED wafer with high cur ving due to internal stress,

necessarily the optimum shape for all kinds of applica-

was successful. The originality of the probe is that one

tions. Hence it can be said that the ideal micro fabrica-

probe pin has two independent tip that can be used astion technology must be capable of realizing surfaces

an “electrical detection”of probe touch down. Then

having arbitral curvatures that are top-down requested

it is experimentally shown the possibility to perform

by applications. The team aims at acquiring compre-

4-terminal（Kelvin）measurement; the uncertainty due

hensive study on such “arbitral cur vature providing

to contact resistance is suppressed.

micro fabrication technologies” from three aspects:（1）Top-down concrete applications,（2）Enabling micro
fabrication methods by cutting-edge technologies andDesign and Development of Micro-Latch Mechanism

ideas, and（3）non-destructive profiling method of suchfor Low-Power and Long-Life MEMS Memory

surfaces. Top-down applications published in FY 2013

Y. Mita, K. Komeda, M. Kubota, A. Tixier-Mita

include（1-5）thermal energy harvester that takes full

A low-power and long-life MEMS memor y having

advantage of profile control by DRIE tuning, as well as

data retention time over 1,000 years, write power under“high-voltage compatible IC out of standard CMOS pro-pico-Joule, and zero power for data retention. One ofcess.

the application scenarios is cumulative hazard（such as
total exposure to radioactivity and or chemicals）memory. The proposed multi-level memory stores the infor-

Chapter 3

3-1

Smart Blocks II project–Development of UV patten-

mation in terms of mechanical energy stored in theable polyimide microactuator

MEMS spring that may yield low-power writing energy

Y. Mita, J. Malapert（FEMTO-ST）, K. Yasuda,and stable data retention. In the year 2013, which is the

M. Ataka, H. Fujita

second year of the project, precision in the process is

In a framework of French national research projectacquired.

（ANR）“Smart BlocksII”，Dr. Julien Malapert stayedin Mita Lab., to develop a brand-new thermal microactuator array and control circuit. The principle ofRight-Brain-Computing Integrated Circuits:

microactuator is thermal bimorph actuator developed

Associative Processing Systems

by Ataka et. al; however the process required O2 plasma

B. Ka, N. Yamashita, Y. Mita30

ashing for patterning with hardmask, yielding 6 pro-

Digital computers are dedicated machines for vary

Research in VDEC

cess steps par layer. To improve process efficiency, thefast execution of numerical calculations. However, theirteam adopted new material that is photo-sensitive poly-

performance is extremely poor in such tasks like see-

imide for structure, thus was successful in reducing

ing, recognizing, and taking immediate actions, which

process step into half of original one. Following suc-are effortless tasks in our daily life. This research aims

cessful demonstration of the microactuator array withat building intelligent VLSI systems based on the psy-

maximum displacement amplitude of 15 µm and cut-off

chological model of a brain. In our system past experi-

frequency of 10 Hz, the team worked on the LSI circuit

ence is stored as template vectors in non-volatile vastthat controls the actuator.

memories and the maximum-likelihood event to thecurrent event is recalled in real time by a fully parallel
processing. The key ingredient of the system is a new

An LSI probing system with CMOS-MEMS

functional device called “Neuron MOS Transistor”

Y. Mita, K. Hosaka, R. Matsui, Y.-T. Chen（ITRI）, and（neuMOS orνMOS）which mimics the action of aM. Kubota

nerve cell neuron at a single transistor level. Based on

W ith Taiwan Industrial Technology Research

VDEC2014̲E.indb 30

such architecture that “association”is the very comput-

14/07/28 12:05

ing primitive, we are pursuing human-like intelligence

Takagi-Takenaka Laborator ysystem implementation directly in silicon integrated（http://www.mosfet.k.u-tokyo.ac.jp/）

circuits. Currently research is in progress for robust
image recognition and classification processing including robust feature extraction. The sate-of-the-art silicon

Ge Metal-Oxide-Semiconductor（MOS）FETs

technology has been utilized to implement such asso-

S. Takagi, M. Takenaka, Rui Zhang, Yu Xiao, J. Rin,

ciative processors in both analog and digital CMOS

WuKang Kim, Katsuaki Tanaka

VLSI chips.

We have conducted the research on high-peformance
Ge MOSFETs. We have investigated ECR plasma oxidation after depositing Al2O3 on Ge by the ALD to form

CMOS-MEMS Device that Interacts Five Senses ofhigh-quality Ge MOS interface. We have successfully

Human Being.

formed high-quality gate stack on strained Ge grownY. Mita, M. Honda, T. Hiraki, E. Shion a Si substrate. We have achieved high-performance

It is believed that MEMS may open new applica-

strained Ge p-MOSFETs using this gate stack. Wetion field, including sensor and actuator system thathave also conducted the research of reliability of Geinteracts five senses of human being. The team aims

gate stacked formed by plasma oxidation. We have also

at developing compact VLSI-integrated microdevices.

investigated Ge condensation to form Ge-on-Insulator

The device is then distributed into environment; coop-

wafers. By using Sb doping from SOG, we have suc-eration of the devices makes functionality in an efficient

cessfully demonstrated n-MOSFETs on the GOI wafer.

way. The development includes wide-range MEMS
microphone that has no moving par t, integrated-tohuman-body actuator to stimulate taste, and prospec-

III-V compound semiconductor Metal-Oxide-tive device for identification of the sound-origin orienta-

Semiconductor（MOS）FET

tion “Tetra-Pentachan”．

S. Takagi, M. Takenaka, M. Yokoyama, S.H. Kim,
Chih-Yu Chang
We have conducted the research on high-per formance III-V MOSFETs. We have successfully dem-Technology

onstrated Ni-InGaAs metal S/D self-aligned InGaAs

Y. Mita, M. Denoual（ENSI de Caen, France）,

MOSFETs on the III-V-OI wafer fabricated by the direct

Eric Lebrasseur, Camille Gay（INSA de Lyon, France）,

wafer bonding. The well-behaved FinFET operation

Jean-Bernard Pourciel（LAAS-CNRS, France）,

has been obtained even scaling the gate length down to

Takahisa Masuzawa（professor emeritus UTokyo）

20 nm. We have also demonstrated GaSb-OI wafer byusing a GaSb layer grown on an InAs wafer. By using

is “sixth sense”，which means that sensors that can

InAs passivation, high-performance GaSb p-MOSFETs

detect physical and chemical amount that cannot be

have been demonstrated.

sensed by human beingsʼsensors. The team aims atsolving this issue by VLSI-integrated compact microdevice. The development includes an integrated bolometer that can detect infrared wave very rapidly and sensitively, and integrated system that can make profilingof very small holes.

Tunnel FET
S. Takagi, M. Takenaka, M. Kim, Sangmin Ji
For low-power application, tunnel FET, which can
exhibit steep subthreshold slope have been investigat-

3-1
31

Research in VDEC

One of the most important application field of MEMS

Chapter 3“Sixth Sense” Devices with CMOS-MEMS

ed. We have developed Zn diffusion from Spin-on-Glass（SOG）for forming high-quality junction, and successfully demonstrated lateral InGaAs TFET exhibiting asubthreshold slope of approximately 60 mV/dec. Ge/
Si hetero-junction TFETs have also been investigated.
By using in-situ B doping in Ge, we have improved the
TFET operation.

VDEC2014̲E.indb 31

14/07/28 12:05

Si CMOS photonics

Ikeda Laboratory(http://www.mos.t.u-tokyo.ac.jp)

M. Takenaka, S. Takagi, Y. Kim, J. Han, J. Kang
High-sensitivity Ge photodetectors（PDs）has been
investigated. It is found that GeO2 surface passivation
formed by plasma post-oxidation can reduce the sur-Self-Synchronous System Realization
M. Ikeda, A. Ito, M. Tamura, D. Sai, T. Nishibe, H. Li

face leakage current of MSM Ge photodetectors by one

To decr ease the energy consumption of LSI,

order of magnitude. We have found the relationshipoperating by low voltage is proposed. Variation

between the surface potential and the dark current ofdecrease reliability in low voltage. We proposed

Ge PDs. We have also investigated SiGe optical modu-

using gate-level pipelined self-synchronous circuits

lators. We have successfully demonstrated enhanced

for low voltage operations. We pr oposed gate-plasma dispersion effect in strained SiGe in the laterallevel dynamic body-bias control by utilizing activity

PIN-junction SiGe optical modulators. SiGe MOS inter-ratio of completion detection signal in gate-level

faces for modulator application have also been investi-

self-synchronous circuit. With this control, powergated. We have found that plasma post-nitridation canconsumption when gates are under condition of waiting

improve interface traps density of the SiGe MOS inter-of valid signals has reduced by 90% with delay increase

face by one order of magnitude. By introduction high-less than 10%. We proposed design automation flow

k dielectric, the feasibility of EOT scaling of SiGe gateusing logic synthesis and P&R for this gate-level self-

stack down to 1 nm is demonstrated.

synchronous circuits. Soft error due to the collisionof neutron from cosmic rays may cause LSI operation
to be unexpected situation. In this research we

III-V CMOS photonics
S. Takagi, M. Takenaka, Y. Chen, Y. Ikku,

investigated SEU tolerance of self-synchronous circuits
by analyzing the types and influences of SEU.

Park Jinkwon, M. Kuramochi
High-per formance electronic-photonic integrated
circuits using III-V-OI wafer have been investigated. An

3D-range finding by Smart Image Sensors
M. Ikeda, X. Hu, H. Yabe, and T. Matsushima,rent injection has been demonstrated for the first time.

R. Ishikawa

The InGaAsP optical switch exhibited 1/10 time drive

Our research topics are about CMOS image sensors

current as compared with Si owing to the large free-that are specialized on 3-D image acquisition based oncarrier effect in InGaAsP. We have also demonstrated

light section. We proposed a CMOS image sensor that

low-crosstalk switching owing to the large free-carrier

employs in-pixel maximum voltage circuit to detect theinduced refractive index change. A waveguide InGaAs

sheet light on the pixel array, thereby reducing the data

32

photodetector monolithically integrated with an InP

transmission required for 3-D shape reconstruction

Research in VDEC

Chapter 3

InGaAsP photonic-wire optical switch driven by cur-photonic-wire waveguide is also demonstrated for theof a target object. A 0.18 um CIS process was used

first time.

for the design and simulation. We also investigated

3-1

texture mapping of real objects with a chip equippedwith two image sensors for simultaneous measurement
2D CMOS photonics
S. Takagi, M. Takenaka, T. Kayouda, K Sasakiof 2-D and 3-D, calculation corresponding point, andpasting 2-D images on 3-D polygons. Using a scanGraphene-based photonic devices have been inves-

light used in light section method as a light source

tigated. For realizing Graphene optical modulators, weof 2-D photographing, we aim at 2-D and 3-D high-have investigated graphene-gate-metal MOS capaci-

speed simultaneous measurement under the darktors, revealing that the chemical potential in grapheneenvironment. For this photographing method, we

can be modulated up to 0.5 eV. Thus, we can show theredesigned dual core imager in CIS process (Mr.

feasibility of the graphene optical modulators. We have

Mandai designed previous chip in 0.18 um Rohm

also conducted the research of transistors based on 2D

process). In 3-D image acquisition with the light-

transition metal dichalcogenides such as MoS2.

section method, an image sensor can suppress

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background illumination by the use of modulated lightand correlation technique. However, a sensor needs
correlation circuits and pixel size becomes very large

Near field communication system
M. Ikeda, and K. Miyazaki

if each pixel has a correlation circuit. Therefore, we

We have studied wide-band spectr um capture

study an image sensor which has correlation circuits insystems for white-space searching for such likethe outside of the pixel array. The sensor searches the

cognitive radio, which uses white space for theregion which light is projected on in each scan. So, it

communication by detecting available channels. We

doesn't need many correlation circuits and obtains highhave investigated a wide-band spectr um capture

resolution due to small pixels.

systems.

Chapter 3

3-1
33

Research in VDEC

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VLSI Design and Education Center, The University of Tokyo
Annual ReportAugust, 2014
Published by
VLSI Design and Education Center, The University of Tokyo
Director Kunihiro Asada
Address: Yayoi 2-11-16, Bunkyo-ku, Tokyo, 113-8656, Japan
Printed in
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Copyright © by VLSI Design and Education Center, The University of Tokyo

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平成26年度
VLSI Design and Education Center The University of Tokyo 2014

東京大学
大規模集積システム設計教育研究センター

年 報

2014
VLSI Design and Education Center,
The University of Tokyo
Annual Report

VLSI Design and Education Center The University of Tokyo 2014

2014VDEC年報H1̲4E.indd H4-H1

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