Message from Director of d.lab
System Design Lab (d.lab) Center, School of Engineering, The University of Tokyo
Director

Tadahiro Kuroda
In Japan, semiconductors are called “the rice of industry” to indicate their necessity. But is that really the case?
Japan is able to produce 100% of the rice it consumes as a staple food. In fact, rice is the only crop for which Japan maintains self-sufficiency. However, as the diet of the Japanese people diversifies, rice consumption has been on the decline year
after year. For the current consumption level, it takes only 60% of the country’ s paddy fields to produce the rice needed as astaple food.
Meanwhile, Japan’ s self-sufficiency rate in semiconductor production has only been falling in the last 30 years. There are
predictions that at the current rate it will drop to 0% by 2030. On the other hand, semiconductor consumption has been
increasing every year. The deepened recognition of the importance of digital transformation (DX) under the COVID pandemic
has fueled additional growth in semiconductor demand. As a result, reports of fire, power outage, or water supply shortage atsemiconductor fabs, or the fragmentation of the world’ s supply chain often create considerable anxiety about semiconductor
supply disruptions.
In such a current state, the expression “the rice of industry” seems to be out of step with the times. Outside of Japan, “oil”
may be a better analogy for necessity than “rice.” But what is emerging as the next “oil” of the world is not semiconductors
but data.
So what is a more appropriate way to describe semiconductors going forward?
For me, it is “the brain cell (neuron) of society.” There are three reasons.
Firstly, it is because of the shift of value from things to knowledge and information. As we transform from a capital-intensive
to a knowledge-intensive society, semiconductors are assuming a more important role by changing from being a component
to a means of knowledge creation and dissemination.
Secondly, it is because the application of semiconductors is broadening from industry to society. The infrastructure of a digital society consists of information networks for which semiconductors are indispensable.
Thirdly, it is because the semiconductor industry’ s battleground is shifting from the general purpose to specialized chipmarket. The shift is driven by the ability of specialized chips to reduce energy consumption by orders of magnitude. Thechange is necessary to protect the environment given the large energy consumption required by the application of AI to big
data analysis. Energy conservation is top priority for any green growth strategy.
While it is acceptable to rely on imports for “the rice of industry,” a nation should be able to create its own “brain cell ofsociety.” For Japan’ s Ministry of Economy, Trade and Industry (METI), digitization is not a goal to shoot for, but a necessary
condition for Japan’ s future. As a result, it is formulating policies with the digital industry, digital infrastructure, and semiconductor industry as the country’s three core pillars.
US President Biden recently talked passionately about the importance of semiconductors while holding a chip in his hand.
Meanwhile in Japan, the ruling Liberal Democratic Party is launching a caucus of lawmakers to discuss the future of the country’s semiconductor industry under the belief that whoever controls semiconductors controls the world.
Iron was once considered to be what makes a country. Will silicon become what makes a country in the future?

1

2021本文レイアウト_英語_7_最終.indd 1

2021/08/19 0:55

2021
Systems Design Lab, School ofEngineering,(VLSI Design and Education Center),
The University of Tokyo
Annual Report

C

O

N

T

E

N

T

S

Message from Director of d.lab ………1

Chapter1

Introduction of d.lab…………………………………………… 4

Chapter2

Activity Report of d.lab……………………………………… 5

2-1
2-2
2-3
2-4
2-5

Advanced Design Research Division……… 5
Advanced Device Research Division………8
Platform Design Research Division (VDEC Function) FY 2020 Report and FY 2021 plan………9
Platform Device Research Division………13
ADVANTEST D2T Research Department ………18

Chapter3

Research in d.lab ………………………………………………… 23

Appendix……………………………………………………………………………… 38
A-1 VDEC CAD Tools………38
A-2 Status of Chip Fabrication Support at Platform Design Research Division………40
A-3 Seminar………43
A-4 Venture companies related to VDEC………462021本文レイアウト_英語_7_最終.indd 3

2021/08/19 0:55

Chapter1

1

Introduction to d.lab

Chapter1 Introduction of d.lab

The VLSI Design and Education Center (VDEC)

kyo established the Systems Design Lab (d.lab) in Octo-

was established at the University of Tokyo in 1996. At

ber of 2019 and formed a strategic alliance with TSMC

the time of its founding, Japan’s semiconductor industry

a month later. d.lab was formed by establishing the Ad-

held a 50% share of the USD 50-billion global market,

vanced Design Research Division and the Advanced De-

and engineers who could hit the ground running were invice Research Division and adding them to the existinghigh demand. VDEC has since provided unparalleled,

Platform Design Research Division and Platform Device

outstanding education to develop many high-caliber en-

Research Division which had been operating VDEC

gineers for the semiconductor industry.

and the Takeda Clean Room. Subsequently in October

However, have these graduates of VDEC been able toof 2020, d.lab started an industrial partnership program

fully realize their potential? In the last quarter century,

which has grown to include more than 40 corporateeven though the global semiconductor market enjoyed amembers.

rapid 7% annual growth rate, Japan’s share continued toFurthermore, the Research Association for Advanced

shrink, falling to the current level of about 10% of a mar-

Systems (RaaS) was founded in August of 2020 to lay out

ket that is now approaching USD 500 billion.

the framework for the university to collaborate with both

The current semiconductor business is one of mass

the industry and the government. Using d.lab and RaaS

production of high volume, low margin general purpose

to realize a two-pronged strategy of open and closed col-chips. General purpose chips have been able to achievelaboration respectively, the university is actively promot-

large volumes because of the wide adoption of the voning cooperation between academia and society as well as

Neumann computer architecture constructed with thecollaborative creation with industry. Our research aims to

combination of memory and processor chips. While Ja-boost the time-performance of semiconductors, with tar-

pan led the world in memory device innovation, it lost the

get goals of 10x increase in both energy and development

business competition on capital investment.

efficiencies.

The mass production, mass consumption model has its

Japan is aiming to transition from the current indus-

limits. Because of the excessive burdens it places on thetrial/information society to Society 5.0, a human-centric

environment, the world is now facing an energy crisis. The

society where knowledge is value. In this knowledge-based

recent trend of applying AI to big data analysis is fuelingsociety, semiconductors will evolve from being a necessity

further growth in energy consumption.

of industry to the brain cell of society.

In the middle of this development, a game changer has

What strategy should the semiconductor industry pur-emerged. Recognizing that it is hard to compete by us-

sue to address this evolution? It is d.lab’s mission to finding general purpose chips procured from semiconductor

the answer.

makers, technology giants including GAFA have started
to develop their own specialized logic chips in-house.
In response to this paradigm shift, the University of To-

42021本文レイアウト_英語_7_最終.indd 42021/08/19 0:55

Chapter2

Activity Report of d.lab

2.1 Advanced Design Research Division
2.1.1

Division Overview

conferences and introduce and assess the most advanced
technologies from the likes of TSMC. Unfortunately, be-sists of four professors, one associate professor, one lectur-cause of COIVD-19, we were forced to center our activ-

er, one project professor, and one senior fellow (joint-ap-

ities around seminars which could be held in the form of

pointment included). Its goal is to enable the design ofwebinars. Below is a summary of our activities in FY2020.

integrated circuits with both high energy efficiency and

Because we started the membership drive for FY2020

high design efficiency. In addition to its research effort, it

late, our activities were limited to the second half of thehas two organizational responsibilities. First, it operates

year from last October to March of this year. Table 2.1.2

the d.lab Partnership Program with help from other d.lab

lists the seminars we organized in FY2020. Particularly

divisions. Second, it founded and operates the Researchworth mentioning is the inaugural seminar held on Oct

Association for Advanced Systems. The following section

28, 2020. In that seminar Professor Tadahiro Kuroda, Di-

is the FY2020 report on these two operations.

rector of d.lab, discussed the new strategy for the semiconductor industry. He explained how the international and2.1.2.

d.lab Partnership Program Activities

societal state of affairs as well as geopolitical factors are

The d.lab Partnership Program was launched to estab-driving further growth in the already rising dependencelish an international center of knowledge-value whereof every application on semiconductors. The focus of his

system designers and members of the semiconductor in-discussion was on how Japan could thrive under such an

dustry meet to exchange information and ideas and toenvironment.

engage in open discussion of collaboration between aca-

On Nov 11, we held a briefing on the 2020 Interna-

demia and society. The Program aims to create a hub thattional Conference on Solid State Devices and Materials

brings together ideas from system designers in industries(SSDM2020). Professor Ken Uchida, Program Commit-

including IoT, AI, 5G, automated driving, and healthcare,

tee Chair of this long-running conference, led an analysis

advanced semiconductor technologies such as advancedof the future trends in semiconductor device and material

CMOS processes and 3D integration technologies, as

technologies. Because materials have the potential to help

well as enablers of such technologies including materials

the industry overcome the limits faced by Moore’s Law,

and manufacturing equipment. For FY2020, the Program

the analysis focused on the possibility, through the searchstarted recruiting members in July and was able to achieve

for new materials, of discovering the technology that willa membership of 21 corporations. Table 2.1.1 contains

take us to the next century.

the list of FY2020 corporate members. We would like tothank these members again for their participation.

2-1
Chapter2 Activity Report of d.lab

The Advanced Design Research Division faculty con-

On Nov 28, we held a discussion of TSMC’s technology. We welcomed President Onodera, Mr. Alex Hsiao,

In our original vision for the Program, we planned toand Mr. Masahiro Koike from TSMC Japan on live stage

not only create a platform for the dissemination of theto provide an introduction of TSMC’s latest technolo-

research accomplishment of d.lab, but also to turn ourgies, which was followed by a Q&A session. Because of

Mejirodai campus into a new venue for interaction and

TSMC’s leading role in advanced semiconductor technol-

learning. We planned to host various events to enable Pro-ogy development, it was an invaluable experience to begram members to interact with renowned professors andable to hear directly from key members of the company

students of the University of Tokyo, with universities andthe latest development trends.

research organizations from around the world, and withOn Dec 25, we held a briefing on the 66th IEEE Inter-other industrial executives and leaders, as well as events

national Electron Devices Meeting (IEDM2020). IEDM

to share information and knowledge from international

is the world’s preeminent conference on device technolo-

52021本文レイアウト_英語_7_最終.indd 5

2021/08/19 0:55

2-1
Chapter2 Activity Report of d.lab

gy. In this briefing, professors from d.lab analyzed papers

search Association for Advanced Systems (RaaS) on Aug

from the conference and elaborated on various topics in-

17, 2020. The founding members are the University ofcluding More Moore and More than Moore technology

Tokyo, Toppan, Panasonic, Hitachi, and MIRISE Tech-trends, emerging devices such as those based on quan-nologies. It is the goal of RaaS to create a design platform

tum effects, as well as co-design of device and circuit tofor the specialized chips required to enable a data-driven

meet the needs of novel computing, Their presentations

society. It aims to increase 10-fold the development effi-

were delivered in an easy-to-understand manner for evenciency of such specialized chips by adopting open archi-

non-experts in the field.

tecture in the design platform. Furthermore, through theSoon after the New Year on Jan 13, we organized an

research and development of 3D integration technology

IBM Day with the theme “Thinking about Quantum

for stacking in the same package multiple chips made with

Computing.” We invited speakers from IBM which has

the latest 7nm CMOS process, it strives to achieve a 10-

already launched a quantum computing business. To-

fold increase in energy efficiency.

gether with Associate Professor Shuntaro Takeda from

We believe that leading semiconductor businesses are

the Graduate School of Engineering at the University oftransitioning back from general purpose to specialized

Tokyo, they presented on the current state of quantum

chips. This is being driven by the unique energy crisis facedcomputing technology and its future outlook. It was a bal-by a data society. The energy crisis is spurred by the explo-

anced presentation, with Professor Takeda providing ansive growth in data volume and the increasing sophistica-easy-to-understand explanation of quantum computing

tion of AI processing. At the current pace, IT equipment

technology, followed by the IBM speakers elaborating on

alone is projected to consume almost two times the total

its practical application.

power consumption of today by the year 2030, increasing

The FY2020 seminar series closed with a briefing on

to 200 times by the year 2050. We cannot really hope forthe 2021 International Solid-State Circuits Conferencea sustainable future if digital transformation consumes so(ISSCC2021). The world’s preeminent conference onmuch energy as to destroy the environment.

integrated circuits technology was held in February. Pro-

Under such a condition, only those who can increase

fessors from d.lab, led by Professor Makoto Ikeda whoenergy efficiency 10-fold can boost computer performanceserved as ISSCC2021’s Technical Program Committee

10-fold, or extend smartphone battery life 10-fold. Com-

Chair, explained the latest trends seen in the conference

pared to general purpose chips which can be used for any

including the flourishing of machine learning processor

task, specialized chips achieve orders-of-magnitude better

development, ICs that enable novel computing exempli-

energy efficiency by eliminating superfluous circuits. That

fied by quantum computers, as well as ICs for 5G, AI, andis why specialized chips are in demand. Meanwhile, sincegame consoles which will drive the future semiconductor

the neural networks used for AI processing process data inmarket. In addition to providing a summary of the pa-

parallel, they cannot be efficiently implemented using thepers, the speakers also positioned them within the context

von Neumann architecture which processes data sequen-of the technology trends in their respective disciplines totially. As a result, specialized chips are being developed all

make it easy for even non-experts to understand.

over the world to serve as AI accelerators. Furthermore,

Unfortunately, it appears that we will have to continue
to focus on remote seminars in FY2021. Nevertheless, we

the slowing of Moore’s Law is providing another favorable
condition for the rise of specialized chips.

are considering adding something new by planning net-

Unfortunately, specialized chips development is not forworking events for intellectual exchange between mem-

everyone. The number of transistors integrated on a chip

bers and the university as well as among members of thehas exceeded the world’s population. IC development has

Program.

seen its cost dramatically increase in recent years, reaching
100 million dollars. Even with a team of several hundred

2.1.3.

Research Association for Advanced Sys-

tems Activities
We started preparation in FY2019 and launched the Re-

designers, it can take several years to develop a chip. It
is an unacceptably long turnaround time given how fast
technology advances nowadays.

6

2021本文レイアウト_英語_7_最終.indd 6

2021/08/19 0:55

With software, even if there is a bug, it can be patchedlater after the software’s release. In contrast, hardware
must be bug-free before it is released. Hardware development is indeed “hard” since the design is more difficult
and the risk higher than software.
Software development has been aided by the use ofcompilers. If a similar technology, in other words a silicon

Table 2.1.1 List of FY2020 d.lab Partnership Program Members
Cadence Design Systems, Japan
Dai Nippon Printing Co., Ltd.
Daikin Industries, Ltd.
FUJIFILM Corporation
Fujitsu Ltd.
Hitachi, Ltd.
JSR Corporation

be possible to reduce its cost and lower its risk. Further-KIOXIA Corporation

more, it will expand the pool of hardware designers. Even-

MIRISE Technologies Corporation

tually, with the open source culture taking roots, and the
expansion of the hardware ecosystem network across its
hierarchy, we expect to see the rise of mass collaboration,
and we will be able to develop chips the way software is
written.
Alan Kay once said, “People who are really serious

Mitsubishi Chemical Corporation
Nihon Synopsys G.K.
NIKON CORPORATION
Panasonic Corporation
ROHM Co., Ltd.
Semiconductor Energy Laboratory Co., Ltd.
Shin-Etsu Chemical Co., Ltd.

about software should make their own hardware.” System

Sony Corporation

development requires both hardware and software devel-

Sumitomo Corporation

opment.
Our goal is to democratize access to silicon technology.
To that end, we will innovate on silicon compiler technol-

2-1Chapter2 Activity Report of d.lab

compiler, is available to hardware development, it should

Tokyo Electron Ltd.
TOKYO OHKA KOGYO CO., LTD.
Toppan Printing CO., LTD.

ogy to enable designing chips like writing software andcreate a platform for quick prototype development (agile
authentic prototyping).
Our technology target is 10-fold increase in both development and energy efficiency. We will create an agile
design platform and adopt open architecture to improve
development efficiency. At the same time, we will employ
the most advanced CMOS manufacturing technology
and 3D integration to boost energy efficiency.
We believe that semiconductors should be provided asa service instead of being sold as a product. The missionof RaaS is to research and develop the necessary technologies.
We had planned to have researchers from member companies to conduct research at our Mejirodai International
Village location so as to create an environment that stimulates cross-pollination. Unfortunately, we had to changethat plan too into one centered around remote work. Our
most significant accomplishment of the year was to put
in place the environment for prototype design using themost advanced CMOS technology which included closing use agreements with foundry and CAD vendors andacquiring hardware tools for the design work.

7

2021本文レイアウト_英語_7_最終.indd 7

2021/08/19 0:55

Table 2.1.2 List of FY2020 d.lab Partnership Program Seminars
Date
10/28/2020
11/11/2020

2-2

11/25/2020

Chapter2 Activity Report of d.lab

12/25/2020

1/13/2021

3/3/2021

Title
d.lab Partnership Program Kickoff
Meeting
SSDM Report

Presenter(s)Prof. Tadahiro Kuroda, d.lab

Prof. Ken Uchida, d.lab
Prof. Toshiro Hiramoto, d.lab
Prof. Tadahiro Kuroda, d.lab
Masaaki Niwa, Senior Fellow,
d.lab
TSMC Day
Mr. Makoto Onodera, TSMC
-TSMC Technology ChatJapan
Mr. Masahiro Koike, TSMC
Japan
Mr. Alex Hsiao, TSMC JapanIEDM2020 Report
Prof. Shinichi Takagi, d.lab- Unraveling IEDM
Prof. Ken Takeuchi, d.lab
Prof. Ken Uchida, d.lab
Takeshi Takagi, Principal Researcher, d.lab
IBM Day
Shuntaro Takeda, Associate- Thinking About Quantum Computing Professor, Graduate School ofEngineering
Mr. Roh Mitsuhashi, IBM
Mr. Shintaro Yamamichi, IBM
ISSCC Report
Prof. Makoto Ikeda, d.lab
Prof. Ken Takeuchi, d.lab
Tetsuya Iizuka, Associate Professor, d.lab
Atsutake Kosuge, Lecturer, d.lab
Mototsugu Hamada, Project
Professor, d.lab

2.2 Advanced Device Research Division
Advanced Device Research Division is working for thehas attracted much attention. One of the examples is thedevelopment of three-dimensional (3D) integration tech-hybrid bonding technology that enables WoW (Wafer on

nology and advanced device technology aiming at ten

Wafer), where same kinds of wafers such as memories aretimes higher energy efficiency of semiconductor systems

multiply stacked, and CoW (Chip on Wafer), where mul-in the data-driven systems.

tiple chips with different sizes, types, or nodes are stacked

In 2020, we discussed the launch of a new project of thein a 3D manner. We are at a major turning point fromnext-generation 3D integration technology. Recently, thepackage-level 3D integration with micro-bump connec-

computing technology for processing large amount of data

tions to direct bonding 3D integration based on bumplessis becoming more important and the energy consumption

direct bonding technology. We are planning to propose aby frequent data transfer between memories and proces-

new project of solving main technological challenges ofsors is a severe problem. To solve this problem, the direct

hybrid bonding by excellent original technologies in Ja-

bonding 3D stack technology, where the data transfer dis-pan and apply for the national project.

tance is shortened by direct bonding of chips or wafers,

82021本文レイアウト_英語_7_最終.indd 8

2021/08/19 0:55

2.3 P latform Design Research Division (VDEC Function) FY 2020 Report
and FY 2021 plan
2-3.1 Overview of Platform Design Research Divisionsions to improve the convenience of participation. In addition, in view of the current situation where the tool-chainsof various companies are becoming more complex and it

Education Center (VDEC) at the University of Tokyo has

is difficult to fully use the introduced tools, lectures on the

been developing projects that contribute to integrated cir-tool-chains recommended by each tool vendor were also

cuit design education at universities and technical colleges

held in conjunction with the individual tool seminars.

in Japan, based on the three major roles: ”spreading the

From the end of FY2019, we received permission fromlatest information on VLSI design and education,” ”pro-each EDA vendor to use EDA tools from home, to avoid

viding licenses of CAD tools,” and ”supporting on VLSI

delay&slowdown in integrated circuit design research andchip fabrications for academic use.” On October 1, 2019,education in Japan.

VDEC has been re-organized into Systems Design Lab(d.lab), Graduate School of Engineering, the Universityof Tokyo as part of an organizational restructuring aimed

2-3.2 Status of Education at Platform Design Research Division

at strengthening integrated circuit related activities in the

The LSI Design Flow Seminar is designed to educate

University of Tokyo's semiconductor integrated circuit-re-the basic concepts of LSI design and to provide hands-

lated activities. The Platform Design Research Division of

on experience of practical design examples using multiple

d.lab continues to carry out the functions of the VDEC

CAD tools. For this purpose, VDEC has been organizing

and continues “VDEC activities” seamlessly. Here, theLSI design education seminars as well as “Refresh Semi-

outline of “VDEC activities” of the FY2020 is reportednar” for re-education programs for engineers. “Analog De-

below.

sign Course”, “RF Design Course,” and “MEMS Design

The missions of VDEC are for advancement of re-

Course,” which started in 2012, were held from June tosearches and education on LSI design in public and pri-

September. All of these courses are experiential educationvate universities and colleges in Japan and send many dis-courses with exercises, and experienced instructors fromtinguished VLSI designers into industry. After 25 years ofmajor universities are invited as lecturers. In addition,

VDEC establishment, educations on CAD software, LSI“Transistor Level Design in VDEC Environment (Course

design and design flow in universities have been well es-

VT)” and “Digital Design Methodology in VDEC EDA

tablished. On the other hand, advancement on nano-me-

Environment (Course VD Course VT)” and “VDEC

ter CMOS technologies forces design flow and CAD soft-

Digital Design Methodology Course (Course VD)” areware complicated. We have been continuing CAD tool

conducted for designers in universities. The “Refresh

seminar by the lecturers from EDA vendors for twice a

Seminar” are all held online in FY2020, and as a result,year. We hold the seminar in VDEC and provide distancethe number of participants has increased compared to pre-learning through video streaming. We expect spread of thevious years.

up-to-date LSI design methodology by using CAD tools.

In addition to these seminars, VDEC holds the “VDEC

In order to make it more convenient for the partici-

Designers’ Forum” once a year, mainly for young faculty

pants, the seminars have been held only in Tokyo sincemembers and students. This is a workshop-style meeting,2009, and at the same time, the seminars have been

where participants bring their design cases and exchange

broadcasted to individual participating lab. The VDEC

their successes and failures, in addition to invited lectures

expects that the latest CAD use-case will be shared amongfrom companies and universities. In FY2020, the VDEC

labs through the seminar organized by VDEC, and will be

Designer Forum had been held online. Since FY2011, thea trigger to spread the technology nationwide. In FY2020,“IEEE SSCS Japan Chapter VDEC Design Award” has

all seminars will be conducted online. Some items werebeen presented as an award for VDEC activities. The final

conducted in the form of on-demand plus live Q&A ses-judging and awarding of the “IEEE SSCS Japan Chapter

2-3
Chapter2 Activity Report of d.lab

Since its establishment in 1996, the VLSI Design and

92021本文レイアウト_英語_7_最終.indd 92021/08/19 0:55

2-3

VDEC Design Award” has been held at VDEC Designers’

ter for the “CAD mail group” and the “Prototyping Tech-

Forum since 2011, and in 2020, the IEEE SSCS Japan

nology User Group” on the VDEC website, where they

Chapter VDEC Design Award will be presented to Mr.

can post their questions and ask for help. The registered

Koki Ishida of Kyushu University. Three VDEC Designusers of the mail groups are not obligated to respond, but

Award Excellence Awards, (Mr. Koki Ishida (Kyushu

in most cases they can get help from experienced users

University), Mr.Naoki Ojima(The University of Tokyo),within a few hours or days. We hope that you will takeand Mr. Masaru Osada(The University of Tokyo)), andadvantage of this system to help solve your problems.

Chapter2 Activity Report of d.lab

two VDEC Design Award Encouragement Prizes (Mr.
Kentaro Nagai(Kyoto University), Mr. Kenji Sugie(NaraInstitute of Science and Technology)), and five VDEC

2-3.3 Publications related to Platform Design Research Division

Design Award Commendation Prizes for Idea Contest

Figure 2.1 shows the trend of number of papers through(Dr. Junichiro Kadomoto(The University of Tokyo), Mr.

VDEC activities. Figure 2.2 show the number of papers

Ryuki Shigemasu (Shizuoka University), Mr. Takuya Mu-

related to VDEC facilities. It can be confirmed that CAD

rakami(Nagoya University), Mr. Kosuke Fukumitsu(Ky-software is widely used in writing papers. Since CAD soft-

ushu University), and Mr.Tatsuya Nomura(Shizuoka

ware is often used not only in chip design but also in the

University).

preparation stage of chip prototyping, its contribution as

Although the educational system through such seminars and forums has enabled students to learn the basics

a tool to demonstrate the basic idea of the research is alsosignificant.

of LSI design, they still face various difficulties in actual
LSI design situations. For beginners, setting up the CAD

2-3.4 Report on AI Chip Design Center

software is the biggest problem. Even after setting up the

VDEC and the AIST have been jointly commissioned

software, they are often baffled by the “difficult error mes-by NEDO to develop a common platform technology forsages” issued by the CAD software. VDEC users can regis-

accelerating AI chip development under the “Innovation

Fig. 2.1 Trends of number of papers through VDEC activities.
Fig. 2.2 Number of papers related to VDEC facilities.

10

2021本文レイアウト_英語_7_最終.indd 10

2021/08/19 0:55

Promotion Project for Accelerating AI Chip Develop-

debugging platform from SpringSoft has merged into Ca-

ment / R&D Item 2: Development of Common Platform

dence tools and will be continued.

Technology for Accelerating AI Chip Development” since
2018. In this project, we have established an EDA uti-

【Chip fabrication services】

We will continue chip fabrication services for 0.18μm

and small and medium-sized enterprises(SMEs) in Japan,

CMOS by Rohm and 0.8μm CMOS by On-semiconduc-and are working as an “AI chip design center(AIDC)”.

tor-Sanyo as the regular services. Chip fabrication services

In this activity, in addition to the introduction of EDA

for SOTB 65nm CMOS by Renesas Electronics will betool licenses that allow venture companies and small andterminated.

medium-sized companies to prototype up to engineering
samples, we have introduced IP for 40nm and 28nm,

In addition to the above. We will continue to devel-

and are also providing a large-scale, high-speed design

op an "AIDC” activities, in collaboration with AIST. We

and verification environment using a hardware emulator,

will introduce a logic emulator for large-scale AI digitalwhich was introduced with a subsidy from the Ministry ofchip design verification, and maintain and operate EDA

Economy, Trade and Industry at the start of this project.

licenses for industrial applications. The main objective of

In FY2020, we have designed a SoC platform with NoC,

this project is to provide small and medium-sized venture

PCIe, DDR4, etc., and multiple functional IP cores, andcompanies with a development environment for AI chip

taped out the platform as a SoC with multiple AI IP coresdesign, evaluation, and verification in order to accelerate

designed by multiple users. In order to further strengthen

the development of AI chips, but we also plan to im-

this activity, we are accelerating our research by establish-

prove the environment for use by universities in order to

ing the "AIST-The University of Tokyo AI Chip Design

promote university-originated companies in the field ofOpen Innovation Laboratory" (AIDL) in the Takeda

AI-related integrated circuits.

2-3
Chapter2 Activity Report of d.lab

lization and design environment for venture companies

Building, Asano Campus, The University of Tokyo on
September 1, 2019.
2-3.5 Plan for FY 2021 “VDEC Activities” of Platform Design Research Division
In FY2021, we will continue the VDEC Activities foracademics as before.
【Design related information dispatching/Seminar】

We will continue holding the following seminars: (1)CAD tools seminars which have been continued since1997, (2) “Refresh seminar” since 1998, (3) “Designer’
Forum” since 1997. We will also continue seminars for
LSI tester usage at VDEC and sub-centers, workshops on
LSI testing technologies initiated by D2T.
【CAD tool support】

We will continue Cadence tools, Synopsys tools and
Mentor tools as the main stream design tools. We willcontinue analog RF design environment, GoldenGate
and ADS by Agilent, C-based design environment, BachC
by Sharp. In addition, we continue trial of several CAD
tools, such as layout platform, Lavis by TOOL. Design112021本文レイアウト_英語_7_最終.indd 11

2021/08/19 0:55

Table 2.1 Chip fabrication schedule【CMOS 1.2μｍ 2P2M】 On-Semiconductor(Former Motorola Japan)
Chip application deadline
2021#12021#22021/7/5
2022/1/11

Design deadline
2021/9/27
2022/3/28

Chip delivery
2021/12/20
2022/6/27【CMOS 0.18μｍ 1P5M(+MiM)】 Rohm
2-3

Chip application deadline

Chapter2 Activity Report of d.lab

2021 #1
2021 #2
2021 #3
2021 #4

2021/4/5
2021/6/14
2021/8/4
2021/12/6

Design deadline
2021/6/28
2021/9/6
2021/10/27
2022/2/28

Chip delivery
2021/10/15
2021/12/24
2022/2/13
2022/6/17【SOTB CMOS 65nm】
Chip application deadline

Design deadline

Chip delivery

2021 #1 2021/6/14

2021/7/26

2022/1/22

2021 #2 2022/1/24

2022/3/7

2022/8/27

122021本文レイアウト_英語_7_最終.indd 12

2021/08/19 0:55

2.４

Platform Device Research Division

2.4.1

Missiongroup in universities, companies, research institutes, andNPOs, to individually “own” such large-scale facility andviding every researcher with three essential elements fornecessary budget by themselves; If researchers wish to “co-research on new devices. The division is with around 20

operate” with the other researchers in a platform, which

staffs, powered by Dr. Yoshio Mita, the playing division

is equally open to everybody, they can “effectively own”

director who himself actively performs experiments inthe most advanced “open platform”, and thereby the cut-the Cleanroom as a leading researcher, and operated inting-edge research activities can be held anywhere in Ja-

collaboration with related departments (such as Institutepan. This is the principle of d.lab’s open device platform,of Engineering Innovation, Electrical Engineering andwhich is in fact a lateral expansion of “shared economy

Information Systems, and Mechanical Engineering) inmodel in VLSI design and fabrication” to micro-nano fab-terms of human and budget resources. Research in emerg-

rication and measurement research field, originally estab-ing fields of semiconductor electronics devices (such as in-lished by VDEC for Japan in 1996.

tegrated circuits), sensors and microsystems requires three

Towards that end, d.lab Platform Device Research Divi-essential elements: (1) fabrication machines with stupen-sion takes full advantages of spaces (of its own and of open

dous amount of budget, (2) rich accumulation of fabrica-

rental) in Takeda Sentanchi Building. The building wastion technology knowledges, and (3) research capability

inaugurated in December 2003, thanks to the enormous

to develop new technologies required for new devices. In

donation in 2001 from Mr. Ikuo Takeda (founder of Ad-

Japan, these three elements had been prepared and kept invantest) to the faculty of engineering (Dean was Professor

an individual research group until the end of 20 century.

Hiroshi Komiyama) as well as VDEC (director was Pro-

However, due to the technology trends towards advanced

fessor Kunihiro Asada). In the building, a 600m2-square

fabrication over larger-scale wafers, it has become almost

supercleanroom including “official ISO3 (a.k.a. federal

impossible for a research group to purchase and main-class 1. Once measured as ISO1)” area (Fig.1). The clean-tain the cutting-edge fabrication machine line, in the 21

stroom and affiliated experimental rooms are equipped withcentury. Originally, it was impossible for every research

cutting-edge nanofabrication and measurement machines,thFig2.4.1

2-4
Chapter2 Activity Report of d.lab

D.lab platform device research division aims at pro-Development of Takeda Sentanchi Supercleanroom

13

2021本文レイアウト_英語_7_最終.indd 13

2021/08/19 0:55

2-4
Chapter2 Activity Report of d.lab

Fig.2.4.2

List of equipment under d.lab Platform Device Research Division

total valued over 3.6 billion yens (30M euros). The users

sion takes full advantages of spaces (of its own and of open

can openly use such nice machines really inexpensively.

rental) in Takeda Sentanchi Building. The building was

Over 70 apparatuses are openly accessible (Fig.2), in-inaugurated in December 2003, thanks to the enormouscluding, “world’s fastest” large-area direct electron beam

donation in 2001 from Mr. Ikuo Takeda (founder of Ad-(EB) writing machine Advantest F5112+VD01, which

vantest) to the faculty of engineering (Dean was Professor

has been donated according to the wise decision of Mr

Hiroshi Komiyama) as well as VDEC (director was Pro-

Ooura, a chairman of Advantest, fine EB writer Advant-fessor Kunihiro Asada). In the building, a 600m2-square

est F7000S-VD02 and Silicon Deep Reactive Ion Etchingsupercleanroom including “official ISO3 (a.k.a. federal

machine SPTS MUC-21 ASE-Pegasus, both purchased

class 1. Once measured as ISO1)” area (Fig.1). The clean-

by Japanese government’s supplemental budget (known

room and affiliated experimental rooms are equipped withas Abenomics, the first arrow), and the scanning electron

cutting-edge nanofabrication and measurement machines,

microscope (SEM) Hitachi Regulus SU8230 that pro-

total valued over 3.6 billion yens (30M euros). The users

vides highest-class resolution among those obtainable bycan openly use such nice machines really inexpensively.

research laboratory. The machines can cover most of theOver 70 apparatuses are openly accessible (Fig.2), in-research steps in nanotechnology, which are cleaning, film

cluding, “world’s fastest” large-area direct electron beam

deposition, lithography, etching, packaging and charac-(EB) writing machine Advantest F5112+VD01, which

terization. Not all apparatuses are yet installed in Takeda

has been donated according to the wise decision of Mr

Building, however due to nationwide platform network,

Ooura, a chairman of Advantest, fine EB writer Advant-researchers can access in another equivalent nanofabrica-

est F7000S-VD02 and Silicon Deep Reactive Ion Etchingtion platform center(s).

machine SPTS MUC-21 ASE-Pegasus, both purchased

institutes, and NPOs, to individually “own” such large-

by Japanese government’s supplemental budget (known

scale facility and necessary budget by themselves; If re-

as Abenomics, the first arrow), and the scanning electron

searchers wish to “cooperate” with the other researchers inmicroscope (SEM) Hitachi Regulus SU8230 that pro-a platform, which is equally open to everybody, they canvides highest-class resolution among those obtainable by“effectively own” the most advanced “open platform”, andresearch laboratory. The machines can cover most of thethereby the cutting-edge research activities can be held

research steps in nanotechnology, which are cleaning, film

anywhere in Japan. This is the principle of d.lab’s open

deposition, lithography, etching, packaging and charac-

device platform, which is in fact a lateral expansion ofterization. Not all apparatuses are yet installed in Takeda“shared economy model in VLSI design and fabrication”

Building, however due to nationwide platform network,

to micro-nano fabrication and measurement researchresearchers can access in another equivalent nanofabrica-

field, originally established by VDEC for Japan in 1996.

tion platform center(s).

Towards that end, d.lab Platform Device Research Divi-

14

2021本文レイアウト_英語_7_最終.indd 14

2021/08/19 0:55

2.4.2 “Takeda Sentanchi Supercleanroom” coop-corresponds to: (1) User’s payment to participate budget

eration platform

acquisition (charged according to the officially-approvedd.lab’s internal rule), and (2) national budget allocatedkyo Nanofabrication site” according to the MEXT’s na-

to d.lab platform research division, MEXT Nanotech-tional project, or simply “Takeda Sentanchi Cleanroom”

nology Platform project, and (3) major laboratories (who(in short, Takeda CR). The platform is widely open to

rent space in Takeda Building for their research work) as

those who share the “value of cooperation”. The mostwell as research projects with d.lab operation laboratories

important understanding for every user is the platform(such as Mita Lab). Of course, each budget category ismust not be considered as a simple outsourcing agent;righteously dispensed in perfectly following its own rule

being understood the value of “own help, mutual help,

defined by corresponding laws and ordinances. The year-

and public help”, the participant can drastically minimize

ly operation cost of 260 million yens are composed ofcosts (personnel, budget, and time), which should haveequipment installation, electricity and water fees, mainte-otherwise been totally covered by each researcher, and cannance, and personnel. National Universities have acquired

directly jump into advanced research. Key Performancebudget flexibility since the date of private agency statuses.

Indicators of such benefits are as follows: over 7.5 billion

It helps a lot to ensure staff employment as well as small

yens for installation cost of building and equipment, overto middle sized equipment acquisition.

260 million yens for yearly operating cost, and reduction

Platform Device Research Division staffs acquire im-of over 20 years’ leading time to acquire know-hows inplicit information for future fabrication technologies, due

advanced fabrications. These benefits have attracted many

to daily help to massively parallel research projects. The

research groups. Since ten years, the number of researchteam develops technologies with high demand and uni-groups who sent us the letter of consensus exceeded 420.

versality and make them accessible by publishing papers.

Over 750 members are yearly subscribed (including re-

As the most recent example of successful application to

newal and new subscription). In year 2020, over 500

multiple research domains, we have developed a platform

persons have used cleanroom and their total access counttechnology of nano pores (a couple of hundreds of mi-

exceeds 15,000.

crons) on an alumina(γ-Al2O3)membrane. The technol-

Operation principle is also “own help, public help, andogy was initially developed for “bio measurement device”

mutual help”. Budgetwise, each term of the principle

through d.lab PDRD’s collaborative research project with

Fig.2.4.3

2-4
Chapter2 Activity Report of d.lab

The platform is called “Nanotechnology Platform UTo-Group photo after award ceremony

15

2021本文レイアウト_英語_7_最終.indd 15

2021/08/19 0:55

a company; then through conversation at Takeda’s cloth

Technology, Fukuoka Institute of Technology, and Carn-changing room, the same fabrication process was foundegie-Mellon University), and a national research institute

to be best for a completely different device application:(NIST). The research topic was ring LASER and integrat-

circular-polarized deep ultraviolet light generating mem-ed nanoscale needle in order to drastically reduce powerbrane [1].

for hard drive by using near-field optics.

[1] K. Konishi et al., Optica, 7, No. 8, pp. 855-863 (2020)
2-4

DOI:10.1364/OPTICA.393816【Function authorization】The MEXT Nanotech-

nology platform project also authorizes Function

Chapter2 Activity Report of d.lab

for highly-skilled engineers.

In year 2020, d.lab

Moreover, taking full advantage that PDRD is a divi-

PDRD recommended Mr. Makoto Fujiwara andsion of d.lab, the team has been developed for over 10

Mrs. Etsuko Ota. They were acknowledged as “Ex-year, a reliable research scheme for integration of LSI andpert”. Accordingly, all the PDRD forward engineers

MEMS devices, known as “Integrated MEMS research(Sawamura, Mizushima, Lebrasseur, Fujiwara, anddomain”. As summarized in a peer-reviewed journal [2],Ota) are acknowledged as “Expert”. The engineer

through VDEC function of d.lab “LSI foundry”, a specif-

with such grade is known to be capable of not only

ic LSI circuit silicon wafers are fabricated through com-

helping users but also are capable of developing newpany (such as Phenitec Semiconductor). Then the wafer

technologies. Such highly-skilled engineers are rareis “post”-processed in an open nanofabrication platform

in Japan: During years Heisei 27 to 30, only 28 out

including Takeda Sentanchi Supercleanroom. The criticalof 166 acknowledged (three levels) engineers has got

advantage of such scheme is that researchers can “easily”“Expert”. Thereby, the PDR division is externallyobtain silicon wafers with transistor circuits, which has

acknowledged as skillful nanotechnology expert lab-

been really difficult for university cleanrooms to acquireoratory.

reliability, and can fabricate by themselves specific MEMS

【Impartial anti-Pandemic measure】Due to thethat no foundry company can provide. Namely, research-

COVID-19 pandemic, cleanroom has been underers can produce “World’s first functionality” with “World’s

shut-down sequence since 7/Apr/2020, and com-highest quality”. Such a flexible scheme is unique in thepletely locked down since 16/Apr, which was the day

world. Yearly one multi-chip fabrication is performedof “State of emergency for entire Japan”. During(pre-fixed participants upon request), including collabo-

three month’s lock down period, the team has inten-

rative research works with industries.

tionally considered how to prevent mutual infection[2] Y. Mita et al., Japanese Journal of Applied Physics,

despite massive use of cleanroom. The resulted pro-56, p. 06GA03, 2017 (2017) DOI: 10.7567/JJAP.56.

cedure has been accepted by the Faculty’s task force.

06GA03After reopening, the team strictly follow the UTo-

2.4.3 Activity Report 2020 of Platform Device Research Division【Prize】The MEXT Nanotechnology Platform Project

kyo’s alert level and perform corresponding measure.
The principle is in two levels: those who are allowedby responsible to come for operation are one-by-one
checked and granted for use. Those who cannot

gives prizes for good usage of platform. Every year, sev-

come due to the reasons such as prohibition of theireral projects are selected by specialists’ award committee,

origin entity have also helped by PDRD’s engineersamong solicited candidates selected from over 3000 re-

and professors’ proxy use.

search project reports. Among the projects that PDRD

【No infection case & no decrease in platform

have solicited, we won the 1st prize “Best use award” onuses】As a result, zero infection case as well as zeroⓇdevice for thermally-assisted hard drive”

mutual infection has been obtained. The users’ par-(Fig.3). Note that our division has been awarded con-ticipation (fee) summed up to around 80 million

secutively for two years. The awarded group are Nano-

yens, which has been smaller than the year 2019

photonics Engineering Organization (NPEO), Innovast-(around 100M) but was equivalent to the year

ella corporation, three universities (Toyohashi Institute of2018. Taking three month’s lockdown, the use has“Nanoheater

16

2021本文レイアウト_英語_7_最終.indd 16

2021/08/19 0:55

ject, by officially stating “use heritage of nanotech“Nanotechnology platform use report” for 2020 was

platform”, for digital transformation (DX) in mate-

164, which was even more than that of the year 2019

rials including MEMS devices. The name of the new(158 reports). As the dean of Faculty of Engineer-

project is called “Material DX”. Structurally speak-ing Prof. Takao Someya stated, we continuously try

ing, material DX have adopted “research domain

to “asymptote the risk down to zero%, and asymp-

hub-and-spoke” system, in contrast with Nanoplat’s

tote the research activity up to 100%”. Towards that“technology domain system” composed of character-goal, every division of the faculty has been asked toization, nanofabrication, and material syntheses.

try whatever popssible measures. D.lab PDRD isd.lab PDRD has been merged with Nano Engineer-

proud of the achievement of satisfactory results. The

ing Center of Institute of Engineering Innovationachievement is due to the system that has been care-and Information Technology Center to form a strong

fully considered both users’ expediency and safety;

hub team, under presidency of Professor Yuichi Iku-

above all, the division chief would like to express

hara. The team has been highly appreciated by thehis sincere thanks to each division staffs who worked

evaluation committee and was granted for 10-year

enormously as an “Essential Worker”.

project’s “hub” site. Indeed, d.lab PDRD had been

【Granted to Supplemental Government Budge】

with Nano Engineering Center for the Nanotechnol-

While wishing the pandemic end as early as possible,

ogy Network project (2007-2012), which is in fact

the PDRD was aware of importance of turning thea precedent project of nanotechnology platform.

cleanroom into “Cyber Physical” one, for the con-Also, Nano engineering center is offering cleanroom

tinuous use of cleanroom in case of future disasters.

infrastructure operation (through Cleanroom Oper-

In year 2020, Japanese government has opened a callation Room, Room 311 of Takeda Building). There-

for supplemental budget to make research laborato-

fore we are sure for future successful cooperation ofries automatic and remote operation; d.lab PDRD

the new Material DX project. To begin with, MEXT

proposed a project of “Cybe Physical Cleanroom”.

has granted us a big (>100M yens) supplemental

The project has been selected by UTokyo internalbudget for our proposal to enhance performance ofcompetition, and the direction asked d.lab PDRD to

our cleanroom that will take place at mid-FY2021.

2-4
Chapter2 Activity Report of d.lab

was proven to be increased. Also, the number ofbe a leading laboratory to create a proposal to MEXT
in combining with Nano Measurement Centre and
UTokyo museum’s projects. The UTokyo project has
won 4 th place out of 91 universities projects. Dueto the budget, all cleanroom machines that are controlled by PCs and workstations have been connected to a secure internet system. Now the engineers (aswell as users) can handle all keyboard, mouse, andvideo functions from outside of cleanroom, while
perfectly keeping information security.

The ma-chine is already in operation, and many projects takeadvantage for inside-outside cleanroom connection
projects as well as remote troubleshooting.

【Granted to Post-Nanotech platform national

project】The major part of “public” help for cleanroom has been covered by MEXT Nanotechnology
platform. Nanotechnology platform project will end
his period at the end of financial year Reiwa 3 rd (31/Mar/2022); MEXT has started another national pro-

17

2021本文レイアウト_英語_7_最終.indd 17

2021/08/19 0:55

2.5

Activity Report of ADVANTEST D2T Research Department

2.5.1 Introduction of ADVANTEST D2T Research
Department

not only design but also testing. Through our activities,
we hope to provide expertise in design and testing for theindustry. In addition, we are exchanging researchers with

2.5.1.1
2-5

Aim of establishing ADVANTEST D2T Depart-

ment

those of other universities and research institutes both inJapan and overseas. Moreover, D2T research division is

Chapter2 Activity Report of d.lab

ADVANTEST D2T research division was establishedsuitable for collaborations with the industry because VLSIin VDEC in October 2007. As the name suggests, it istesting is one of the most practical research topics in thefinancially supported by ADVANTEST Corporation.

industry. On the basis of these activities, our final goal is

The aim of establishing ADVANTEST D2T research

to become a center of excellence of VLSI testing in Japan.

division was to promote the research and education en-

D2T research division has spent a total of 12 years tovironment with regard to VLSI testing in all universities

develop the first (Oct. 2007 – Sep. 2010), second (Oct.

and colleges in Japan. “D2T” signifies that we consider

2010 – Sep. 2013), third (Oct. 2013 – Sep. 2016), and

182021本文レイアウト_英語_7_最終.indd 18

2021/08/19 0:55

fourth (Oct. 2016 – Sep. 2019) phases. D2T activity

2.5.2

Report of the 15th D2T Symposium

The 15th D2T Symposium was held on September 17,

2019 – Sep. 2020, of the fifth phase. Systems Design2020 online. This year, we invited the following overseas

Center, School of Engineering, the University of Tokyo

lecturers to introduce their research on biosystems, RF,

has been established in Oct. 2019, and Advantest D2T

IoT, Memory, and Hardware security: Professor Brian

research department is within the center. D2T research

Floyd from North Carolina State University, Professor

department primarily focuses on D2T research activities

Alex Orailoglu from University of California, San Diego,

and education. The fifth project phase (Oct. 2019 on-

Mr. Takeshi Iwasaki from ASAHI KASEI MICRODE-

wards) of D2T project will be commenced by courtesy of

VICES, Kazumi Hatayama-sensei from EVALUTOADVANTEST Corporation.

Corporation and Gunma University, Assistant Professor

In this financial year, we invited Professor Tsung-Hsein

Michihiro Shintani from NAIST, Associate Professor Ma-

Lin (2019/8 – 2020/1) from National Taiwan Universi-saharu Kobayashi from d.lab, the University of Tokyo andty for research and educational collaboration with d.lab-

Mr. Ryo Tamura from Advantest Corporation for their

VDEC.

distinguished research topics.

The details pertaining to the activities of our group arepresented in the following sections.

We sincerely appreciate each participant for their contributions to the symposium. We look forward to greater

2-5
Chapter2 Activity Report of d.lab

report of 2020 presents the last financial year, i.e., Oct.

participation again at the next symposium.
2.5.1.2

Members of ADVANTEST D2T Division

Project Professor

Masahiro Fujita

Project Professor	
Tsung-Hsein

Lin(2019/8–

2020/1)
Project Lecturer

Akio Higo

Researcher	Koji Asami (Advantest Laboratories Ltd.)
Researcher	Masahiro Ishida (Advantest Corporation)
Researcher

Takahiro Yamaguchi

Assistant Clerk

Makiko Okazaki

192021本文レイアウト_英語_7_最終.indd 19

2021/08/19 0:55

15th D2T Symposium Program ONLINE
9:50

2-5

Opening Remarks
Tadahiro Kuroda (Director, d.lab, School of Engineering, The University of Tokyo)
Yoshiaki Yoshida (President & CEO, ADVANTEST CORPORATION)

Chapter2 Activity Report of d.lab

10:00 Session 1 (Chairpersons: Makoto Ikeda, Tetsuya Iizuka, d.lab, The University of Tokyo)
Beamforming Arrays and their Test and Calibration
Brian Floyd, Professor (North Carolina State University, Raleigh, NC)
Adaptive Test Pattern Construction for Hardware Trojan Detection
Alex Orailoglu, Professor (University of California, San Diego)
The Solution of Testing the Millimeter-Wave (76- to 81- GHz) without Expensive Instruments
Takeshi Iwasaki, (ASAHI KASEI MICRODEVICES CORPORATION))
12:00 Lunch

13:00 Session 2 (Chairperson: Masahiro Fujita, d.lab, The University of Tokyo)
Recycled FPGA detection using exhaustive fingerprinting characterization
Michihiro Shintani, Assistant Professor (Nara Institute of Science and Technology)
Viewing Test Technology Trends from presentations at Recent Test Related Conferences
Kazumi Hatayama, (EVALUTO Corporation and Gunma University)
Session 3 (Chairperson: Ken Takeuchi, d.lab, The University of Tokyo)
STT-MRAM memory test system with an electromagnet
Ryo Tamura, (Advantest Corporation)
A Monolithic Integration of RRAM Array and Oxide Semiconductor FET for In-memory Computing in 3D Neural
Network
Masaharu Kobayashi, Associate Professor (d.lab, the University of Tokyo)
Recent D2T research department progress
Akio Higo, Lecturer (d.lab, The University of Tokyo)
Closing Remarks
Masahiro Fujita (d.lab, School of Engineering, The University of Tokyo)

202021本文レイアウト_英語_7_最終.indd 20

2021/08/19 0:55

2.5.3 Research Activity Reports of the ADVANTEST
D2T Research Department

High-Resolution

Analog-to-Digital

Converter

Based on Stochastic Comparators

Using the Wideband Spread Spectrum and Its Ap-

Takahiro J. Yamaguchi, Akio Higo, Tetsuya Iizuka
project

aims

toexplorestochastic

plications
Koji Asami, Byambadorj Zolboo, Akio Higo,analog-to-digital converter (ADC) architectures.

Tetsuya Iizuka, Masahiro Fujita

Process variations, together with many factors such

To measure low-cost RF devices for IoT andas variations in voltage or temperature, lead to mis-other applications, low-cost and high-efficiency

matched design parameters that produce input-re-analog-to-digital conversion techniques are required.

ferred offsets and hence cause non-linearity andTo acquire narrow-band modulation signals scatteredmissing output codes in an ADC. Instead of at-over a wide frequency range, a compression sampling

tempting to suppress such process variations as inmethod was investigated herein.

conventional ADC, the stochastic ADC approach

In this financial year, we analyzed the factor of

exploits the stochastic properties of many compara-

the degrade of implemented Modulated Wideband

tors such as random variation of input-referred offset

Converter performance and developed a method to

and Gaussianity of the internal noise to enhance theimprove the performance. By unique calibration sig-

quantization accuracy. However, the published pa-

nals, a degrade wave from the periodic sign function

pers only show that stochastic ADCs are noisier thanto multiply to a measured signal before A/D conver-

the conventional flash ADCs [TCAS-I,Vol. 57, no.

sion and a frequency characteristic of analog circuits

11, 2010]. The central limit theorem can be appliedin front of an A/D converter are separated and iden-

to discrete type RVs such as a group of comparators

tified. A 4-channel MWC circuit was fabricated forand their sum [A. Papoulis 2000]. It shows that for

the verification experiments.

2-5
Chapter2 Activity Report of d.lab

ThisHigh-Performance Analog-to-Digital Conversion

this discrete RV, many more terms are required in
the sum before going convergence to a Gaussian distribution [S. L. Miller 2004]. These results in theadequate number of bits (ENOB) of the stochastic
ADC are represented by log44B [TCAS-I,Vol. 57,
no. 11, 2010], being smaller than the ENOB of theconventional flash ADC, which is given by log22B.
An approach for robustly detecting level-crossing
time using stochastic median is investigated to address randomness issues and achieve accuracy.

21

2021本文レイアウト_英語_7_最終.indd 21

2021/08/19 0:55

5G multi-channel/millimeter-wave signal measurement
Koji Asami, Ryogo Koike, Nguyen Ngoc Mai-Khanh,
Akio Higo, Tetsuya Iizuka, Masahiro Fujita
To measure the millimeter-wave signals in an over2-5

the-air environment, we study and develop funda-

Chapter2 Activity Report of d.lab

mental research. In this financial year, we were establishing the experimental setup for millimeter-wave
measurement. We were preparing the radio box withspherical scanning and planar scanning stage inside
for near-field and far-field millimeter-wave measurement. In addition, we designed and fabricated the
directional probe, and we develop the calibration
method for probe characteristics and antenna measurement.
High-Speed and High-accuracy Multi-Pin Timing
CAL for ATE
Masahiro Ishida, Tetuya Iizuka, Zule Xe,
Toru Nakura, Akio Higo, Masahiro Fujita
Semiconductor test equipment (ATE) has thousands to tens of thousands of signal input and output channels. It requires timing calibration (CAL)
to correspond the test signal output's timing to thedevice under the test (DUT) and the comparison
timing of the signals output from the DUT. In thisresearch, we focus on a high-speed and high-accuracy multi-pin timing CAL method applicable to ATE.
In this financial year, we identified issues to clarify
our research goals and studied the circuit scheme torealize the timing of CAL. The target accuracy of thetiming CAL was set at 1 ps. It clarified that the problem to achieve the target was to minimize the change
in characteristics of the CAL circuit in response toenvironmental changes. The fundamental method of
the timing CAL was determined by discussion, anda circuit simulation analyzed the effects of environmental changes such as applied voltage and temperature on the CAL error.

22

2021本文レイアウト_英語_7_最終.indd 22

2021/08/19 0:55

Chapter3

Research in d.lab

Kuroda Kosuge Laboratory(http://www.kuroda.t.u-tokyo.ac.jp/index.html）

TCI: ThruChip Interface

In addition, data management algorithm and ECC
are developed for the storage system. Finally, a highspeed storage system is developed to autonomously
adjust SCM capacity according to the applicationda, Wai-Yeung Yip

characteristics.

TCI is a 3D integration technology that employs
inductive coupling between coils created with on-

Approximate Memory

chip metal line patterns for data communication

Chihiro Matsui and Ken Takeuchi

across stacked chips. It realizes the same or better

We have proposed approximate non-volatile mem-

performance as TSV (Through Silicon Via) but at

ory system for 5G network. Performance and powera lower cost. Last year, we presented the 3D SRAM

evaluation platform is developed for the edge/cloudstacking using TCI and the TCI 2.5-D integration

servers. Approximate memory that tolerates mem-technology.

ory cell errors for machine learning applications is

3
Chapter3 Research in d.lab

T. Kuroda, M. Hamada, A. Kosuge, T. Shidei, M. Oka-

proposed to improve both performance and energy
TLC: Transmission Line Couplerof the memory system. By efficiently using approxi-

T. Kuroda, M. Hamada, A. Kosuge, T. Shidei, M. Oka-

mate memory, the bottleneck of 5G network systemda, Wai-Yeung Yip, Y. Hayashi

and the edge/cloud servers is resolved.

TLC is a data communication technique between
circuit boards by utilizing electromagnetic coupling

Long-term Semiconductor Memory

between transmission lines on them. It solves the is-

Ken Takeuchi

sues in conventional connectors such as wearing, re-We have proposed long-term memory semicon-

liability against vibration, and impedance mismatch,ductor memory system with ReRAM. The data life-

realizing wireless connectors. Last year, we presented

time is significantly improved by introducing the

new coupler technologies enabling long communi-“Finalize” programming that increase the write volt-

cation distance for direct board-to-board communi-

age before the data-retention. In addition, by opti-

cation systems, and the compact SerDes circuit for

mizing the program stress based on the endurance,transmitting multiple signals.

both long-term data storage and high endurance areachieved.

Takeuchi Laboratory(https://co-design.t.u-tokyo.ac.jp/）

High Speed Semiconductor Storage
Chihiro Matsui and Ken Takeuchi

Nakamura Laboratory(http://www.hal.ipc.i.u-tokyo.ac.jp/index-e.html)

IoT/Cyber-Physical System

We have developed semiconductor storage system

We investigated Reinforcement Learning (RL) op-

that uses different types of storage class memories

timization methods for Energy Harvesting Wireless(SCM) such as S-SCM and M-SCM which are slow-

Sensor Nodes (EHWSNs) by balancing the device

er than DRAM but has larger capacity and lower

energy consumption with the unpredictable energy

cost. Non-volatile memories store different types ofsupply. RL generally requires long time for learning

data in order to resolve trade-offs in speed, energy

because of large computing cost. For this problem,

consumption, cost, and reliability of storage-type

we proposed a distributed learning solution that co-

SCM (S-SCM) and memory-type SCM (M-SCM).

ordinates the many sensor nodes of a network to ef-

23

2021本文レイアウト_英語_7_最終.indd 23

2021/08/19 0:55

ficiently explore the large state space concurrently.

Quantization Techniques for Small Number of Bits

Our method significantly minimizes learning risks

in Transformer based Natural Language Process-and accelerates the learning process.

ing
Masahiro FUJITA, Shin-ichi O'UCHI, Ding YI,

Low-Power Computing

3

After decades of development, natural language

Chapter3 Research in d.lab

We conducted a research on power reduction of lo-

processing is widely used in life and research. In re-cal 5G small cell base stations. Specifically, The pro-cent years, the Transformer-based NLP model has

posed method co-optimizes the control of two pow-

achieved good results on many tasks, in which a mod-er-performance knobs: the power of ampliers and theel called BERT is a major progress in recent years.

number of active antennas. For the co-optimization,

However, the BERT model is really large, which re-

the relationship between transmission ability andquires a lot of storage and computing resources. In

power consumption is modeled. The proposed meth-order to implement the BERT model on hardware,

od is applied to the case in which multiple nodes

Intel has built a project named Q8BERT to quan-

exist at different distances and have dynamic traffic.

tize the model parameters to save memory space and

The experimental results reveal the proposed method

computing resources. This research implements the

reduces the power consumption effectively.

Q8BERT, and makes some improvements by proposing clipping, which is to limit the range of weights,

Network Security

and piece-wise quantization, which is to divide theZigbee is a short-range wireless communication

range of weights into several pieces to get higher res-protocol and needs low power and low bandwidth

olutions. We show experimentally that the clippingat the sacrifice of its short transfer range and slow

can get higher accuracy while inference, which is

speed. Due to this nature, it is widely used in small

better than the Q8BERT. And we get some interme-

inexpensive sensors and IoTs that run on batteries,

dium results of non-linear experiments. Experiments

As Zigbee uses indirect communication to achievefor piece-wise quantization are in progress.

low power consumption, it incurs a vulnerability to
LDoS attacks. To solve this problem, we proposed a

Efficient Attention Mechanism by Softmax Func-

countermeasure against it and confirmed its effec-

tion with Trained Coefficient

tiveness through experimental simulation.

Masahiro FUJITA, Shin-ichi O’UCHI, Kaito HIROTA
BERT is a neural network model which has accom-

Fujita Laboratory

plished state-of-the-art performance on eleven natu-(http://www.cad.t.u-tokyo.ac.jp/)

ral language processing tasks such as inference andPartial logic synthesis via training a topologicallycomputations available on edge devices. We propose

similar binarized neural network

an efficient hardware implementation method for

Masahiro FUJITA, Chaoyi JIN

the part of this model by modifying Softmax func-

We present an experimental technique for solving

tion. Softmax function is a part of the most signif-

partial logic synthesis problems through training a

icant calculation in BERT in terms of computation

topologically similar binarized neural network. Par-

cost, and its hardware implementation on FPGA ortial logic synthesis means that most parts of the logic

ASIC has not been explored. We have succeeded incircuit are known whereas the missing portions must

reducing the number of additions and exponential

be logic synthesized from specification. By replacing

functions to 1%, while retaining 95% of the BERT’s

2-input logic gates with perceptron model and in-accuracy through experiments.

paraphrasing. So it is desired to make BERT based

heriting the topological structure of the logic circuit,
we are able to recover the missing parts with backpropagation and discrete training.

24

2021本文レイアウト_英語_7_最終.indd 24

2021/08/19 0:55

Scheduling Sparse Matrix-Vector Multiplication

way to reduce the number of variables in QBF prob-

onto Parallel Communication Architecturelems. In the method, we start with smaller inputs

Masahiro FUJITA, Ruitao GAO, Mingfei YU

LUT and gradually increase the number of inputs in

There is an obvious trend to make use of hard-order to reduce variables. This method has reduced

ware including many-core CPU, GPU and FPGA,

calculation time by up to around 80% when solving

to conduct computationally intensive tasks of deep

large QBF problem.

learning implementations, while a large proporSAT-Based Data-Flow Mapping Onto Array Proces-sparse matrix-vector multiplication(SpMV). In thissorresearch, the minimum scheduling problem of 4*4

Masahiro FUJITA, Yukio MIYASAKASpMV on ring-connected architecture is first stud-

Recently, it has been common to perform parallelied. We have put forward a decomposition-based

processing in machine learning. Reconfigurable ar-algorithm for larger matrices. With the proposed

ray processor is drawing attention in terms of easyalgorithm, search space of the minimum schedulecustom adjustment and highis considerably reduced. Through comparison withperformance. We propose a method to map a da-an exhaustive search method and a brute force-based

ta-flow onto an array processor using a SAT solver.

parallel scheduling method, the proposed algo-

The proposed method is combined with an automat-

rithm is proved to be able to offer scheduling solu-

ic transformation method, which changes the ordertions of high-equality: averagely utilize 65.27% ofof calculations, to generate a more efficient compu-

the sparseness of the involved matrices and achieve

tation scheme. We have solved mapping problems

91.39% of the performance of the solutions generat-of matrix-vector multiplication. In our experiment,

ed by exhaustive search, with a remarkable saving ofa SAT solver was more scalable than an ILP solv-

compilation time cost (250 times less) and the best

er. Our method handled a dataflow of more than ascalability among the above mentioned approaches.

hundred nodes using MAC operation. We have also

3
Chapter3 Research in d.labtion of which can be formulated into the format ofmapped sparse matrix multiplication with varying
Efficient Reachability Analysis Based on Inductive

latency and throughput and generated faster sched-

Invariant Using X-value Based Flipflop Selection

ules utilizing the sparsity.

Masahiro FUJITA, Ryogo KOIKE
For sequetial circuits, it is well known that the setsof reachable states may be much smaller than the

Evaluation on Approximate Multiplier for CNN Calculation

entire state space, and computing the supersets ofMasahiro FUJITA, Takashi MATSUMOTO, Yuechuanreachable states is practically useful due to the less

ZHANG

computational complexity than the exact set of the

Improving the accuracy of a convolutional neuralreachable states. Inductive invariant is the one of the

network (CNN) typically requires larger hardware

methods to compute such supersets. For inductivewith more energy consumption. On the other hand,invariants, it is important to select the subset of flip-

the error tolerance of CNNs allows approximate

flops in order to find a small and/or useful superset

computing to cut down the implementation costs.

of reachable state. Unknown value X based analy-

Given that multiplication is the most resource-inten-

sis is used to find the subset of flipflops. In somesive and power-hungry operation in CNNs, approx-

HWMCC2017 benchmark circuits, the proposed

imate multipliers (AMs) can be used to reduce hard-

method can find the subset of flipflops to proveware cost. There are various existing approximate

the correctness of the property. The calculation ofmultiplier generation methods. However, it remains

inductive invariants is formulated with Quantified

unknown whether a specific AM is suitable for CNN

Boolean Formula. The QBF problem can be solved

calculation and its effect on inference accuracy. In

by repeatedly applying SAT solvers. We also show athis paper, we implement an 8-bit quantized Alex-25

2021本文レイアウト_英語_7_最終.indd 25

2021/08/19 0:55

3

net into hardware. The relationship between error

small but repeated many times in the algorithms. We

caused by AMs and the accuracy of CNN inference

introduced micro-sequencer on-chip to accelerate

is established. Mainly two AMs are considered: 1)

pairing engine on BN254 curve free from IO bottle

Cartesian Genetic Programming (CGP)-based AMs

neck, also we implemented multiple core architec-2) flexible Error-estimating based AMs. Besides, weture for further acceleration of the pairing engine.

propose two techniques, input zoom and error com-

For FHE by RingLWE design, we have investigat-

pensation to improve the performance of AMs in

ed optimum design of numeric theory translation

CNN calculation.

(NTT). We also studied attribute-based encryption

Chapter3 Research in d.lab

as a possible application hardware acceleration by
the pairing engine.

Ikeda Laboratory(http://www.mos.t.u-tokyo.ac.jp)

Attack Resilience Evaluation of Cryptographic Cir-

Design Optimization of High-Performance Cryptographic Engine

M. Ikeda, K. Abe

M. Ikeda, K. Ikeda, F. Arakawa
With

the

cuits

development

Security of cryptographic circuits is threatened byof

IoT

technology,side-channel attacks. In this work, we have evaluatedhigh-performance cryptographic engines, such as

the feasibility of lattice attacks that can break thesearchable cryptography and ID and attribute-based

digital signature algorithm. In lattice attacks, there

cryptography, are required to meet increasingly di-is a trade-off between the amount of information

verse requirement specifications. We improved theobtained by side-channel attacks and the amount of

performance of the elliptic curve cryptography en-computation required to recover the secret key. We

gine by using scheduling and an optimal modular

have investigated conditions regarding the amount

multiplication algorithm, and obtained a latency ofof information to recover the secret key within a re-18.14us including the coordinate transformation

alistic amount of time through experiments using

part. For the elliptic curve pairing, we optimized avarious key lengths as targets of the attack, and somelarge-scale scheduling problem and investigated aof the results showed the attack could recover the se-design method to automatically describe the sub-se-

cret key with less information than reported in pre-quences in HDL using the results. This method isvious attacks. We have been investigating whether

expected to improve the design cost, which is an is-side-channel attacks can acquire enough information

sue in hardware cryptographic design.

for lattice attacks, utilizing an ASIC chip in which
ECDSA is implemented as an attack target and tem-

Functional Encryption Engine Design

plate attack as an attack method.

M. Ikeda, R. Nakayama, A. Opasatian, T. Shimada
High-functional

cryptography

exemplifiedbysearchable encryption and ID and attribute-based

A study on hardware implementation of reservoir
computing system

encryption is the basis of privacy guard, that is the

M. Ikeda, B. Amartuvshin

biggest concern in cloud services. Functional cryp-

The hardware realization of artificial neural net-

tography has a disadvantage that the cryptograph-works (ANNs) is a challenging task due to large re-ic algorithms used for its implementation has highsource requirements of the involved operations. Res-

computational cost. In this study, we implemented

ervoir computing (RC), based on a random recurrent

and optimized two main algorithms, optimal Ate

neural network (RNN), is a simple yet powerfulpairing on elliptic curve and fully homomorphic

model that is well suited for time-series data process-encryption (FHE). In both cases, we employed op-

ing. It consists of a reservoir for mapping inputs into

erations on quotient ring as the unit of arithmetic,a high-dimensional space and a readout for patternand constructed pipeline by unrolling loop that isanalysis from the high-dimensional states in the res-26

2021本文レイアウト_英語_7_最終.indd 26

2021/08/19 0:55

ervoir. The reservoir is fixed and only the readout is

nas and InAs MOS-HEMT detectors integrated on a

trained with a simple method such as linear regres-glass substrate by stud bumps. By measurement withsion and classification. Thus, the major advantage

a THz signal generator, we realized synchronous-de-of reservoir computing compared to other recurrent

tection of the signal.

neural networks is fast learning, resulting in low
training cost. We are trying to propose digital hardware implementations of echo state network (ESN)

Iizuka Laboratory(http://www.mos.t.u-tokyo.ac.jp/iizuka)

designed for brain-computer interface based on EEG
Waveform Reconstruction Technique for Wideband Signal
Advanced 3-D Measurement System by Smart Im-

Tetsuya Iizuka, Byambadorj Zolboo

age Sensors and Secure Sensing

The Modulated Wideband Converter (MWC) is

M. Ikeda, Y. Liu, D. Jiang, and N. Watanabe

one of the promising Sub-Nyquist sampling archi-

We have been working toward the advanced 3-D

tectures for sparse wideband signal sensing, cogni-

measurement system with secure sensing scheme

tive radio applications and so on. Since resources

by integrating smart signal processing functionality

within Automatic Test Equipment (ATE) are limited

onto the smart image sensors. We have studied ToF

on sampling rate, the MWC can be useful for testing

image sensor with current mode background sup-devices with various frequency band.

pression capability for modulated light projection.

In this research, we are investigating a feasibility of

We added phase shifting circuits for expanding the

MWC to reconstruct a waveform of sparse wideband

measurement ranges, and evaluated measurement ac-

signals for measurement equipment.

curacy according to parameter variations. We have

The reconstruction performance based on thealso studied ToF image sensor with light to pulse fre-ideal sensing matrix was not acceptable due to thequency modulation pixel for both background sup-non-ideal hardware components. The convention-pression and digital signal selection capabilities.

al way of the calibration is to stimulate the MWC

3
Chapter3 Research in d.lab

time-series data with online learning capability.

with sequential single-tone signals then estimates the
Design and Measurement of Weak-Signal-Readoutactual sensing matric components. This method is

Integrated Circuit for Terahertz-Video-Imaging

quite time-consuming and inaccurate. Thus, we pro-

M. Ikeda, and T. Kikkawa

posed novel calibration method for the MWC using

We designed a readout integrated circuit (ROIC)

multi-tone signal to estimate the actual sensing ma-

for Terahertz-Video-Imaging which converts a weaktrix from a single measurement to reduce the calibra-

signal detected by InAs MOS-HEMT to digital sig-

tion time and the timing noise. In terms of NMSE

nal. The ROICs are integrated as 8x7 array on 180nm

performance, the proposed calibration method has

CMOS and utilized with the detectors stacked onreasonably good performance compared to the con-them. Each ROIC contains transimpedance ampli-

ventional one.

fier, lock-in amplifier and ΔΣ analog-to-digital con-

In terms of noise performance, we proposed anverter as well as digital-to-analog converter (DAC)

average noise figure (ANF) theoretical notation toto calibrate the detectors. In our previous work, we

expect the noise figure of MWC. The accuracy of thecost a lot of time to optimize some control parame-

analytical formula is ensured with MATLAB simula-ters. Therefore, we modified the architecture of thetion results. We have also verified the analytical for-amplifier to realize higher gain and easier control-

mula in the practical implementations.

lability. Moreover, as a DAC architecture, we em-

We proposed a new method for constructing aployed a resistor string instead of capacitor bank todigital compensation filter to equalize a non-ideal

solve the problem of leakage current.

frequency characteristic of an analog filter. Without

The fabricated chip is stacked with array of anten-

the compensation filter, the reconstruction perfor-

27

2021本文レイアウト_英語_7_最終.indd 27

2021/08/19 0:55

3

mance of the MWC is not satisfactory. Thus, thebe of great use in applications such as communica-

digital compensation filter is necessary for practicaltions and sensing.

Chapter3 Research in d.lab

realizations to maximize the performances. The pre-We proposed a digital PLL architecture that

vious works by other researchers were impossible toachieves low phase noise by introducing noise shap-

estimate the LPF without disconnecting the LPF cir-ing ADC to phase detector. First, the quantization

cuit from the MWC circuit, which makes the meth-noise of TDC(Time-to-Digital Converter)-PLL canod infeasible in some practical implementations. The

be reduced by replacing conventional nyquist TDC

other issue was that the compensation filter building

with ΔΣ TDC that consists of phase detector andmethod could not be used in the advanced MWC

voltage-controlled delay line. ΔΣ TDC was proposed

case. The proposed method can be directly used inin previous research. Second, in order to reduce thethe advanced MWC circuit without disconnecting

quantization noise of FDC(Frequency-to-Digital

any component.

Converter)-PLL which controls the output frequen-

We demonstrated the measurement results of thecy by feedback to divider, the design of high order

MWC taken from the practical implementation. The

ΔΣ FDC was achieved by cascade connection of ΔΣmeasurement result of the noise figure in MWC vali-

ADC and quantizer in FDC. The noise performancedates the correctness of the theoretical noise analysis.

of these two PLLs was demonstrated through sim-

The proposed calibration technique for the MWC

ulations. It is proved that FDC noise is lower thanestimated the actual sensing matrix coefficients with

TDC noise because of quantization bit rate, and thatsingle measurements. In contrast, conventional cali-ΔΣ FDC-PLL is more practical than ΔΣ TDC-PLL

bration needs many measurements. The calibration

because the cost of ΔΣ FDC-PLL is fewer.

performance has been demonstrated in NMSE andWe demonstrated LPF is necessary before and be-

IRR compared to the uncalibrated performance;hind in frequency conversion in main PLL of Tri-

more than 50 dB and 42 dB improvements have been

ple-loop PLL by Matlab Simulink. This LPF de-achieved on NMSE and IRR, respectively.

creases the spurious which may occur because of
convolution of RF signal from VCO and LO signal

Phase-Locked Loop Circuit Techniques for Low

from Integer-N PLL in frequency region. Further-Phase Noise

more, we improved frequency conversion part inTetsuya Iizuka, Zule Xu, Masaru Osada, Ryoga Iwash-

TL-PLL and demonstrated TL-PLL can be used inita, Ryoya Shibata

28GHz for 5G NR communication by schematic

We implemented a fractional-N PLL that achieves

design and simulation. In this design, we used Sub-

low-noise in a compact manner by employing a HM

harmonic mixer instead of Sample & Hold circuit(Harmonic-Mixer) and a dual-feedback architectureused in previous research and Ring Oscillator for LO

to avoid noise amplification, then demonstrated its

input to convert high frequency using the merit ofbenefits through measurements. Furthermore, we

TL-PLL which can avoid increasing noise in loop.

performed an analysis of tones that can arise in all
S/H (Sample-and-Hold) circuit-based HMs, andHigh-Precision Analog-to-Digital Conversion Cir-established a design methodology for LPFs (Low-cuit Techniques

Pass-Filters) to suppress these tones. Finally, we

Tetsuya Iizuka, Zule Xu, Shuowei Li, Akira Matsuoka

proposed a new PLL architecture where an auxiliary

With the increasing demand for high-speed

PLL is placed in the feedback path of the dual-feed-

communication and high-speed analog-to-digitalback PLL to further suppress the DSM quantization

converter, the design demand for high-speed andnoise, and demonstrated its benefits through simu-

low-power comparators is increasing. The Strong-lation. This architecture can allow low-noise, ring

ARM comparator can meet the demand well.

oscillator based PLLs to be realized without complex

A conventional Strong-ARM comparator usuallycalibration schemes such as LMS, and is expected tohas a large offset. In previous research, an auxiliary

28

2021本文レイアウト_英語_7_最終.indd 28

2021/08/19 0:55

combiner. With a simple combining structure, how-parator by current compensation. In this research,ever, there is a challenge in achieving the optimum

we build the mathematical model to describe theimpedance matching in > 100 GHz mm-wave due

operating principle of such Strong-ARM comparator

to its layout asymmetry. In this paper we propose

and the influence of the introduction of an auxiliary

a symmetric layout structure in the balun-based

circuit with different parameter settings on the per-power combiner in D-band to have equal input im-

formance of the comparator. The simulation resultspedance at all the primary input ports so that theshow that the model can describe the behavior of theformer-stage amplifiers can look into balanced im-comparator and predict the influence of the auxiliary

pedance. A 2-parallel power-combined amplifier iscircuit on the main circuit well. The designer canfabricated in a 65-nm bulk CMOS process, which

effectively set the parameters of the auxiliary circuitachieves 6.0 dBm OP1dB and 11.4 dBm saturated

and globally optimize the comparator based on this

output power. A 4-parallel prototype with the sym-model.

metric-balun-based power combiner is designed andHigh-resolution

analog-to-digitalconverters

verified with post-layout simulation with the same

(ADC) are essential for audio and sensor applica-

process technology, which achieves 9.4 dBm OP1dB

tions, and oversampling ADCs are used due to theand 14 dBm saturated output power.

noise-shaping and oversampling. Discrete-time delta-sigma ADCs (DT DS ADC) is one of the oversam-

Implementation of Neuron Device based on CMOS

pling ADCs and has an advantage in its robustness

Analog Circuits

to clock jitter and PVT variations. To reduce power

Tetsuya Iizuka, Xiangyu Chen

consumption in DT DS ADC, dynamic amplifier is

Neuromorphic computing is a technique that sim-

used, which has no static current. We presented aulates the biological mechanisms of neurons andsecond-order delta-sigma ADC with closed-loop dy-

synapses in the human brain and is being actively

namic floating inverter amplifier (FIA).

studied and applied in various fields. The spiking

FIA has a stable output common-mode voltage andneural network (SNN) is called the third-generation

unsensitive to input common-mode voltage. To get

artificial neural network, which more realistical-

high SNR, high gain FIA + Cascode FIA was pro-ly imitates biological neural networks. Among theposed. Simulation results showed that FIA + Cas-

many models, due to the simplicity of the leaky in-code FIA had high gain and input common-mode

tegrate-and-fire (LIF) neuron model, it has received

voltage robustness. Proposed ADC achieved a 85.5

widespread attention.

dB SNDR while consuming 45.5 µW in simulation.

3
Chapter3 Research in d.lab

circuit was proposed to reduce the offset of the com-

In most cases, neurons need a very large time constant to process signals. However, large on-chip ca-

Millimeter-Wave Circuit Design for Communica-

pacitors and resistors are not conducive to systemtion through Dielectric Waveguide

integration. Based on the LIF model, we designed an

Tetsuya Iizuka, Mai-Khanh Nguyen Ngoc, Takamichi

analog neuron element with a small area and an ad-

Horikawa

justable time constant. Proposed circuit consists of a

Recently, a high-speed communication techniquecapacitor and two pseudo resistors (PRs). By adjust-with millimeter-wave (mm-wave) band has been ac-

ing the bias voltage of PR, the time constant of thetively studied for its wide bandwidth. A power ampli-

circuit can be changed. The capacitance is a constantfier (PA) with high output power is always demand-value of 2pF, and the maximum time constant can

ed for these purposes to further improve the systemreach 0.15ms with TSMC 65nm process fabrication.

performance such as communication distance, data

We also constructed a synapse circuit based on arate and signal-to-noise ratio. In this research wering oscillator. This circuit uses leakage current toproposed a PA architecture that realizes high out-

drive the oscillator to work, hence it consumes very

put power in D-band by using a balun-based power

little energy. The synapse integrates the impulse

29

2021本文レイアウト_英語_7_最終.indd 29

2021/08/19 0:55

from the neuron and outputs a frequency signal

rated voltages. In this study, we are pursuing the po-corresponding to the value of the integral, which is

tential of silicon IGBT based on new concepts oftransmitted to the next neuron. We taped out the

IGBT scaling and double-gate IGBT.

proposed circuit using TSMC 65nm process.
Device Physics of Negative Capacitance Field-Effect-Transistor

Hiramoto & Kobayashi Laboratory3(http://nano-lsi.iis.u-tokyo.ac.jp/)

Chapter3 Research in d.lab

Variability in Nano-Scale CMOS Devices

Masaharu Kobayashi and Toshiro Hiramoto
Negative capacitance FET (NCFET) is a promising next generation transistor technology which canbreak the physical limit of 60mV/dec in subthresh-Toshiro Hiramoto and Masaharu Kobayashi

old swing. However, the comprehensive understand-As the size of MOS transistors is miniaturized, theing on the physics of such steep subthreshold slope

effect of random variability of device characteristics

and unique phenomena has not been done yet. In

is becoming too large to be overlooked. Although thethis work, based on the transient negative capaci-

main reason in conventional bulk transistors is thetance by the dynamics of ferroelectric polarization

fluctuation of the number of dopants, the variability

switching, we made a more comprehensive NCFET

causes of nanowire transistors, which is one of themodel including fixed charge and charge trap in thenext-generation device candidates, remain unknown.

insulator and at the interface, which contributes to

In this study, we have clarified that the quantum

further physical understanding of the device physics

confinement fluctuation caused by line width rough-of NCFET.

ness is the new origin of random threshold voltage
variability. We are also investigating the effect on the

3D neural network by co-integration of IGZO tran-

drain current variability.

sistor and RRAM
Masaharu Kobayashi and Toshiro Hiramoto

Low Temperature Characteristics of Nano-Scale
CMOS Devices

AI algorithm such as machine learning requires
massive data for learning and inference. Thus con-Toshiro Hiramoto and Masaharu Kobayashi

ventional computing using CPU and main memory

The quantum computing has attractive much at-

has severe challenges on the bottleneck of data trans-

tention for a future computing technology that isfer. In-memory computing is getting more attentions

fundamentally different from classical computing by

to tackle this challenge by the fusion of computation

CMOS circuits. In the quantum computing systems,

and memory function. However, in order to increase

conventional CMOS circuits are utilized to control

the accuracy of the neural network, memory array

quantum bits. Therefore, it is essential to clarify

size needs to be increased, which causes long laten-

and model CMOS transistor characteristics at low

cy and energy consumption in the interconnects.

temperature. In this study, we are studying the sub-In this study, we developed monolithic integrationthreshold swing of bulk and nanowire transistors.

of IGZO FET and RRAM on the interconnect lay-

We are also evaluating the characteristics variability

ers. We demonstrated no performance degradation

at low temperature.

through this co-integration process. We also demonstrated XNOR operation by using IGZO FET and

Silicon Power Devices

RRAM as a basic element of binary neural network.

Toshiro Hiramoto
Although new materials such as SiC or GaN are
widely studied for power devices, silicon IGBT (In-

Physical mechanism of the emergence of ferroelectricity in HfO2

sulated Gate Bipolar Transistor) is still a mainstream

Masaharu Kobayashi and Toshiro Hiramoto

device for power electronics in very wide range of

Ferroelectric HfO2 is getting much attentions

30

2021本文レイアウト_英語_7_最終.indd 30

2021/08/19 0:55

as an emerging memory material which is CMOSGe Metal-Oxide-Semiconductor (MOS) FETs andcompatible showing ferroelectricity even at less thanthe 3 dimensional integration
S. Takagi, Cheol-Min Lim, Tsung-En Lee, Chia Tsong

duces asymmetric orthorhombic phase in a thermal

Chen, Xueyang Han, Makoto Kutaragi, Kasidit To-

process, which leads to ferroelectricity. However, theprasertpong, M. Takenaka

physical mechanism of the emergence of ferroelec-

We are investigating the technology to real-

tricity in HfO2 through the whole thermal process

ize ultra-thin Ge-On-Insulator (GOI) structures

has not been fully understood yet. In this study, byon Si substrates, the performance improvement ofusing ab-initio calculation, we revealed two stephigh-performance GOI CMOS using these struc-

phase transition process: (1) amorphous phase totures, and the device physics that determines thetetragonal phase at high temperature due to dopant

electrical characteristics, with the aim of applying

effect and interface energy, and (2) tetragonal phasethem to 3D integrated CMOS. In this fiscal year,

to ferroelectric phase due to the kinetics of selective

we have demonstrated the operation of (111)-sur-transition by thermal activation barrier. The latter

face GOI nMOSFETs using the substrate bonding

was confirmed by ab-initio molecular dynamics sim-

method, for the first time, and the higher mobility

ulation.

than that on (100)-surface ones. We also investigateda gate stack formation technique on SiGe channels

Takagi Laboratory

3
Chapter3 Research in d.lab

10nm thickness. It is known that doped HfO2 in-with improved MOS interface characteristics, and(https://sites.google.com/g.ecc.u-tokyo.ac.jp/mosfet/)

have found that a low interface defect density can

III-V Metal-Oxide-Semiconductor (MOS) FETs and

TMA surface treatment.

be achieved by using a TiN/Y2O3 gate stack with athe 3 dimensional integration
S. Takagi, Kei Sumita, Jun Takeyasu, Ryohei Yoshizu,

HfO2-based Ferroelectric devices

Kasidit Toprasertpong, M. Takenaka

S. Takagi, Kasidit Toprasertpong, Xuan Luo, Kento

3D-integrated CMOS, in which transistors are

Tahara, M. Takenaka

vertically stacked, is expected to be a key device for

MOSFETs (FeFETs) using ferroelectrics with po-

future logic LSIs. In order to realize such stacked

larization reversal as gate dielectrics and FeRAMs

MOSFETs, channels such as III-V compound sem-using metal sandwich structures (MFM structures)

iconductors and Ge are promising because they canas memory cells are expected to be future devices forbe fabricated at low temperatures and are expected

ultra-low power memory and logic. In particular,

to have high mobility and injection speed. In our

devices based on ferroelectric and anti-ferroelectriclaboratory, we are investigating the realization ofmaterials such as Hf1-xZrxO2 and ZrO2, which

ultra-thin III-V-On-Insulator (III-V-OI) structures

have been discovered recently, are of great intereston Si substrates, and the performance improvement

because of their extremely high compatibility withof III-V nMOSFETs using these structures aiming

current Si CMOS technology. We are studying theat application to 3D stacked CMOS. In this fiscal

properties of these ferroelectric thin films depositedyear, we have proposed a novel subband engineering

by atomic layer deposition (ALD) method, the de-using (111) surface ultra-thin InAs-OI channels withvice operation principle of FeFETs and the optimum

high electron mobility, and have demonstrated InAs

device structures to realize excellent device charac-nMOSFETs on Si using the smart-cut method. Fur-teristics. In this year's research, we have demonstrat-

thermore, we have also proposed a method to evalu-

ed an MFM memory cells with significantly reduced

ate the contact resistance with InAs metal alloys andoperating voltage by reducing the crystallization

have demonstrated that it has extremely low contact

temperature of Hf0.5Zr0.5O2 and thinning theresistance.

films to take advantage of the wake-up effect of theferroelectric properties.

31

2021本文レイアウト_英語_7_最終.indd 31

2021/08/19 0:55

Reservoir computing based on ferroelectric devices
S. Takagi, Kasidit Toprasertpong, Eishin Nako, Zeyu

Takenaka Laboratory(https://sites.google.com/g.ecc.u-tokyo.ac.jp/takenaka-lab/)

Wang, R. Nakane, M. Takenaka
Reservoir computing has recently attracted atten-

3On-chip/Off-chip optical interconnect

Chapter3 Research in d.labtion as a AI computation method with computa-

Mitsuru Takenaka, Naoki Sekine, Hanzhi Tang, Qian-tional load for learning. We have recently proposed

feng Chen, Dongrui Wu, Yuto Miyatake, Takayathat FeFETs and FeRAMs with memory-in-logic andOchiainonlinear analog computing functions are promising

We have been conducting research on optical in-

hardware for physical implementation of reservoir

terconnection and I/O of LSIs using silicon photon-

computing. Also, we have demonstrated its reservoir

ics and other technologies. We have succeeded incomputing operation for the first time in the world.

demonstrating the operation of a hybrid MOS op-

Aiming to realize new AI hardware on Si platforms

tical modulator consisting of an ultra-thin InGaAsP

that can perform inference and learning with ex-membrane bonded to a silicon ring resonator. We

tremely low power consumption, we are conducting

have also proposed a waveguide-type hybrid photot-

research on improving AI performance by optimiz-

ransistor, in which an ultrathin InGaAs membrane

ing operation ways and device structures.

is bonded onto a silicon waveguide. By using thesilicon waveguide as the gate electrode, we succeed-

Understanding of Si CMOS operation under ul-

ed in demonstrating extremely high sensitivity. In

tra-low temperature for quantum computing ap-

addition, the operation of a hybrid optical modula-

plication

tor combining a slot optical waveguide with an InP

S. Takagi, Minsoo Kang, Kasidit Toprasertpong, M.

membrane and an EO polymer was analyzed, and it

Takenaka

was shown that optical modulation at a rate of overIn quantum computing systems, in addition to

100 Gb/s was possible.

devices that manipulate qubits, CMOS integrated
circuits that control signals are also indispensable.

Si photonic integrated circuit for AI

To scaling up the quantum computing system, it isMitsuru Takenaka, Hanzhi Tang, Shuhei Ohno, Yuto

necessary to place Si CMOS circuits that can oper-

Miyatake, Kohei Watanabe, Kazuma Takiate at cryogenic temperatures such as 4K near theWe have been conducting research on deep learn-

devices for qubit operation. For this purpose, it ising for AI using programmable photonic circuits

mandatory to quantitatively clarify the behavior

such as universal optical circuits. We have demon-of MOS transistors at cryogenic temperatures withstrated that the programmable silicon photonic

deep understanding of their physical mechanism. We

circuits with the prototype ring resonator crossbar

are conducting experimental and theoretical studies

array can perform MAC operations and inferential

to clarify the electrical characteristics and reliabili-

operations are possible. We also proposed on-chipty of Si MOSFETs at cryogenic temperatures and to

backpropagation using silicon photonic circuits, andquantify the physical parameters.

successfully demonstrated its basic operation.
Ge mid-infrared photonic integrated circuit
M. Takenaka, Ziqiang Zhao, Yuto Miyatake, Chao
Zhang
We have been studying mid-infrared photonic integrated circuits based on Ge waveguides formed on
Ge-on-insulator (GeOI) wafer. We have successfully fabricated phototransistors by forming PNP- or
NPN-type junctions in Ge waveguides for the first32

2021本文レイアウト_英語_7_最終.indd 32

2021/08/19 0:55

time. We have also developed a mid-infrared opti-

and the accuracy will be intensively checked to fur-cal phase shifter using phase-change materials. We

ther improve the calculation technique and to finddemonstrated that a low-loss optical phase shifter

materials for new types of molecular sensors.

can be realized by using GST at the mid-infrared
wavelength.

Thermal-aware Design of Nanodevices
Ken Uchida

2D material devices

LSI has drastically improved the performanceby reducing the size of MOS transistors. Recently,

Piyapatarakul

the introduction of new three-dimensional device

We have been studying semiconductor devices us-

structure; nanosheet transistor, is expected, and theing graphene and molybdenum disulfide. Schottky

Joule-heating-induced temperature rise in device

junctions fabricated by transferring molybdenum di-channel is suggested as one of the most serious prob-

sulfide onto Si substrates using the scotch tape meth-lems. We have developed a technique to minimize

od were formed and we quantitatively evaluated thethe operating temperature of the CMOS channel

carrier concentration of molybdenum disulfide fromby thermal-aware design. Moreover, detailed evalu-

capacitance measurements. By combining the carrier

ations of the electron-phonon transport properties

concentration obtained with the Schottky junctions

have been conducted in our group. The molecularand capacitance measurement results of molybde-

dynamic simulation and the nonequilibrium Green's

num disulfide MOS capacitors fabricated by thefunction method were simultaneously performed,

same method, we succeeded in quantitatively eval-and it is suggested that there are vibrational modes

uating the energy distribution of the interface trap

peculiar to the Si/SiO2 interface, and that the vibra-

density using the Terman method.

tional mode enhances the electron-phonon scatter-

3
Chapter3 Research in d.lab

Mitsuru Takenaka, Roda Nur, Xiaoxuan Zhang, Tipat

ing near the interface.

Uchida Laboratory(http://www.ssn.t.u-tokyo.ac.jp/publications/awards/)

Nanoscale Molecular Sensors for Volatile Organic
Compounds (VOC)Ken Uchida
Human breath contains various kinds of volatile

Someya Laboratory(http://www.ntech.t.u-tokyo.ac.jp/)

Breathable mechanoacoustic sensor that listens toyour heart
Md Osman Goni Nayeem and Takao Someya

organic compounds (VOCs), in which metabolites

We developed a multilayered nanofiber structured

related with diseases or health condition should be

ultralight weight (5 mg) mechanoacoustic sensor

included. Therefore, we can expect that the very earlywith world’s highest acoustic sensitivity. In addi-

diagnosis of the disease could be achieved, if VOCs

tion, our sensor allows the skin to breathe when at-

related with human diseases can be selectively detect-tached on chest wall of a human subject. In future,

ed. We have experimentally demonstrated successful

it is expected that our sensor may replace the bulky

operations of low-power metal-nanosheet-based mo-stethoscope that requires highly skilled clinicians tolecular sensors. However, atomistic-level simulation

identify abnormal heart sounds, and even current

methodologies which can reproduce the response ofstate-of-art wearable patch type sensor that lacks

molecular sensors have not been established. We havebreathability for continuous inflammation-free heartdeveloped a new atomistic simulation method formonitoring.

molecular sensors by combining the molecular dynamics simulation and the nonequilibrium Green's
function method. In future, the developed techniquewill be applied to various types of molecular sensors

33

2021本文レイアウト_英語_7_最終.indd 33

2021/08/19 0:55

Mita Laboratory(http://www.if.t.u-tokyo.ac.jp)

to realize cooperative function. The PI is receivinga French National Research Center (ANR) grant onbehalf of host professor of CNRS laboratory in the3
Chapter3 Research in d.lab

TopoMEMS: Development of Ideal Variable MEMS

Institute of Industrial Science (LIMMS, CNRS-IIS,

in view of Future Topological Quantum Computing

UMI 2820), together with FEMTO-ST Labora-

Y. Mita, K.Tsuji, A.Higo, T.Iizuka, Z.Xu, M.Ezawa (Dept.

tory and PSA-Peugeot Laboratory for such “micro

Applied Physics)

robots that can realize deformable substance by co-

Recently, new computation methods that use Top-

operative action, named Programmable Matter”. In

ological nature are drawing much attentions in view

year 2020, an electrostatic chucking actuator systemof future Quantum computing. Calculation takesthat attaches and detaches the external skeleton ofadvantages Topological natures existing in several

the Matter has been presented in an international

different fields expressed as Hamiltonian matrices.

conference. Based on the actuation force electromag-

Our team, granted by JST CREST project, tries tonetically analyzed, the ideal structure of the flexible

explore electrical expression of Hamiltonian matri-electrode (named Flexiboard) has been identified,ces used for computation. Team Mita will devel-

and fabrication technology of flexible electrode has

op ideal variable electrical devices as well as ideal

been investigated.

MEMS devices. We named such devices and systems“TopoMEMS”. As an initiating study, we have tak-Integration of electrode devices on MEMS fluidic

en Su-Schriffer-Heeger model. We have developed adevices

MEMS state-variable capacitor integrated SSH elec-

Y. Mita,A. Higo, T.Ezawa, E.Ota, Y.Okamoto (AIST),

trical circuit and have been successful in Topolog-

N.Washizu (Advantest), A.Takada (Advantest), M.

ical / Trivial state switching due to MEMS device.

Fujiwara, T.Sawamura

Through the experiences, an ideal MEMS device de-

Towards the goal of production of brand-new sen-sign has been identified and fabrication process was

sor devices with higher sensitivity and functionality,

developed.

the team is working on small-gap electrode fabrication process. This year we have integrated depletion

Programmable Matter - Study on LSI-MEMS ener-

type FET with microelectrode. Because channel ofgy-autonomous distributed microsystems for re-depletion FET is open at the gate-source voltage as

alization of deformable matter

low as 0V, the sensor can get rid of parasitic cur-Y. Mita, K.Misumi, N.Usami (Dept. of Aeronautics

rent and thereby leading to higher precision meas-

and Astronautics),

urement. A special ASIC with threshold tuned de-E. Lebrasseur, G. Hwang (LIMMS, CNRS-UTokyo IIS /pletion transistor was integrated with electrode, and

CNRS C2N),

coulter measurement has been successful.

G. Ulliac, (LIMMS, CNRS-UTokyo IIS, FEMTO-ST),
J.Bourgeois, B.Piranda (FEMTO-ST, France), S. Dela-

Fine Large-Area Electron Beam Lithography Expo-lande (Groupe PSA, France)

sure Methods

As one example of future integrated MEMS that

A. Higo, Y. Ochiai, M. Fujiwara, T.Sawamura, Y. Mita

is expected to open new research and industrial ap-

The team explores newly-acquired (in 2013) rap-

plication fields, the authors are trying to show a

id electron beam writer F7000S-VD02. The capa-

top-down application of energy-autonomous dis-bility of high electron dose and sharp edge due totributed microrobots. A number of identical tinycell (character) projection machine configuration is

robots, sized below 1cm, will be released in an en-

being examined. The breakthrough in question isvironment. Individual robot can communicate withto extend the large-area EB lithography, whose pat-

their neighbor, stick each other, and share energy,tern approximation have been limited to rectangularshapes, into expressing free-form smooth shapes and34

2021本文レイアウト_英語_7_最終.indd 34

2021/08/19 0:55

a number of periodical small patterns. This year, pat-small-scale image acquisition system.

tern and process design has been successful to obtaingap structure less than 16-nm wide.

Project PARIS: PARallel Integrated microSystem
for High Frequency Action-Based Non-Invasive

Universities-Industries collaborative research on

Multi-Modal Cell Analyses

highly-functional system by MEMS post-process

Y.Mita, T.Tsuchiya, K.Misumi, Y.Okamoto (AIST),of CMOS-VLSI

A.Mizushima, E.Lebrasseur, T.Bauvent (ENS Paris-Saclay, exchange student), C.Moslonka (ENS

G. Larrieu (LAAS-CNRS,Toulouse), Y.Ikeuchi (IIS), K.

Paris-Saclay, VDEC internship student), B. le Pioufle

Saito (Nihon Univ.), Y.Sato (Nanox Japan)

C.Moslonka (ENS Paris-Saclay), Tixier Mita Agnès

The research targets are new sensor devices,(UTokyo RCAST), Olivier Français (ESIEE, Univ. Parismade by post-process at clearnrooms such as d.lab

Est), F.Marty (ESIEE, Univ. Paris Est)

Takeda Supercleanroom and others, of VLSI wafer

Having granted again JSPS-CNRS bilateral pro-made through VDEC. The important finding has

ject 2018, the team is developing a large-scale mul-been that VLSI wafer acquired just after transistor

ti-modal cell analyses system (project name: PAR-fabrication could sustain processes even with heat

IS). The electrorotation method, which is known

treatment, such as deposition, ion implantation,

to measure a mechanical rotational response to theand drive-in. In 2016, a VLSI device made on Sili-

incident rotational electrical field frequency is used.

con-on-Insulator (SOI) wafer was successfully Deep-

The method is non-invasive so the evaluated cells

RIE processed. The industrial interest is its versa-

are possible to be used in further biological exper-

tility – many different types of application devices,

iments. In year 2020, massively parallel device has

which differ one from another according to request

been investigated. Device topology that can infinite-of market, can be fabricated by using the same tech-ly expand the working area and corresponding fab-

nology. More and more companies are interested inrication process of sandwitched electrode array havethe scheme and are working on the technology on

been successfully developed.

3
Chapter3 Research in d.lab

Y. Mita, T. Yamaguchi, T. Lévi(IMS-CNRS,Bordeaux),

the collaborative research projects, including international cooperative research projects.

Colloidal integrated Infrared Detector
A.Higo, N.Miyazawa, N. Usami, M. Kobayashi (Dept.

High-sensitive ultrasonic probe by integrated

EEIS),MEMS technology

W. Haibin, N. Kubo, K. Segawa (RCAST), Y. Mita

Y. Mita, A.Higo, T.Yoshimura (Osaka Prefectural Uni-

Electron devices using colloidal quantum dots are

versity), T.Mizuno (Konika Minolta), K.Suzuki (Koni-

believed to open new application fields such as lightka Minolta), Y.Nakayama (Konika Minolta), T.Endo

emitting devices and or photovoltaics. Up to date,(Nagoya Medical Center)very few research activities have been done in sen-Using the same scheme as above mentioned

sors applications; if we can realize integrated pho-

CMOS-MEMS post process R&D scheme, thistodiodes that have extended sensitive wavelength asproject aims at integrating piezoelectric material

long as 1.35µm-1.4µm wavelength, such devices canand MEMS post-processing to obtain a brand-new

be used by many new applications such as security

ultrasonic inspection probe, whose sensitivity is as

cameras and / or Laser Radar (Lidar) under sunlight.

100 times as cutting-edge technology. In year 2020,

The aim of this research is to find an integration

the team investigated LSI test circuit of high-voltage

method for beyond Si-LSI device. We try to inte-

electronic circuit, fabricated by support from a pub-grate colloidal quantum dots of which absorption

lic funding from Japan Agency of MEdical Research

spectra can be designed through molecular design.

and Development (AMED). Based on the results ob-

By integration, Silicon device will be able not only totained, an application LSI circuit was designed for

capture infrared wavelength lights, which is impossi-

35

2021本文レイアウト_英語_7_最終.indd 35

2021/08/19 0:55

ble by its original characteristics, but also my include
information reading and computation circuits. For
the first year’s exploratory study, partly financed by
the LIMMS internal project grant, spin coating integration method has been investigated. Root causethat prevented Electrical Quantum Efficiency has
been identified to an unexpected reverse Schottky
3junction. The existence of unexpected junction was

Chapter3 Research in d.lab

first confirmed by using new test structure (Coaxial
Circular TLM) and was doubly confirmed by Angle-Resolved Photo-Emission Spectroscopy (ARPES). Based on the result, device parameter optimization has been made and resulted in better External
Quantum Efficiency (EQE).
Development of zero power multiple-thresholdmaximum acceleration sensor for cyber physicalsystemY. Mita, R Ranga Reddy
D.lab is awarded a Japanese JST – Indian DST
joint grant (SICORP) for cyber physical systems
research, in cooperation with IIT Bombay campus.
The team is participating the project through a ShockResonant Spectrum (SRS) sensor, which has been a
research theme of 2012-2014. A new Ph.D student
from India is assigned and fabrication process wasrecovered. This year we have analyzed complete system to record 10-levels of maximum acceleration in
MEMS device. Based on the result, we have started
collaboration with India. We have distantly followed
research internship student from IITH who stayed
three months. Also, the design heritage of latchingmechanism has been employed for development ofideal MEMS research in view of future quantum
computing.

36

2021本文レイアウト_英語_7_最終.indd 36

2021/08/19 0:55

3
Chapter3 Research in d.lab
372021本文レイアウト_英語_7_最終.indd 37

2021/08/19 0:55

Appendix
A.1

A-1

VDEC CAD Tools

Appendix

Since 1996, VDEC has provided CAD software licens-

other public universities, private universities, and colleges.

es to the registered researchers in universities and colleges

When one is going to use VDEC CAD tools and chipin Japan. The CAD tools we provided in 2021 throughfabrication service (the details are described in Section

the activities of VDEC in Systems Design Lab (d.lab) are1-3), some faculty member of his/her research group in

shown in Table A.1.1. The researchers can use those CAD

a university or a collage needs to do user registration.

tools when their local machines, whose IP addresses are

Figure A.1.2 shows (a) the number of registrants, (b) the

registered in advance, are authorized by one of VDEC li-

number of distinguished universities/colleges of the reg-cense server located in the ten VDEC subcenters shown in

istrants, and (c) the number of registrants who applied

Figure A.1.1. For each CAD tool, VDEC provides 10-100

VDEC CAD tools, (d) the number of applied licenses offloating licenses. Those CAD tools can be utilized only for

all CAD tools.

research and education activities in national universities,
Table A.1.1 VDEC CAD tools
Name
Cadence tool set

Synopsys tool set

Mentor tool set
Silvaco tool set
ADS/Golden Gate
Bach system
LAVIS

Function
VendorVerilog-HDL/VHDL entry, Simlation, Logic synthesis, Cadence Design Systems, Inc.
Test pattern generation, Cell-based (including macros) place, route, and back-annotation, Interactive
schematic and layout editor, Analog circuit simulation, Logic verification, Circuit extraction
Verilog-HDL/VHDK simula-tion, Logic synthesis, Test Synopsys, Inc.
pattern generation, Cell-based (including mac-ros)
place, route, and back-annotation, Circuit simulation,
Device simula-tion
Layout verification, Design rule check
Mentor Graphics Co. Ltd.
Fast circuit simulation
SilvacoDesign and verification of high-frequency cir-cuits
Keysight Technologies
BachC-based design, synthesis, and verification
Sharp
Layout visualization platform
TOOL

Fig. A.1.1

VDEC Subcenters

38

2021本文レイアウト_英語_7_最終.indd 38

2021/08/19 0:55

A-1
Fig(c)

Fig(b)

Fig(d)

AppendixFig(a)

Fig.A.1.2

392021本文レイアウト_英語_7_最終.indd 39

2021/08/19 0:55

A.2 S tatus of Chip Fabrication Support at Platform Design Research Division
As for the support for VLSI chip prototyping, in thepilot project in FY 1994 and 1995, there was only one
foundry, NEL's CMOS 0.5μm (the process was later continued by Hitachi Hokkai Semiconductor). After the inauguration of VDEC in 1996, the 1.2-μm CMOS processof Motorola Japan (which was continued by ON Semiconductor in 1999) started cooperation, and the 0.6-μm
CMOS process of ROHM was added in 1997. In 1997,
A-2

CMOS 0.6μm from ROHM was added, followed by

Appendix

0.35μm from Hitachi, Ltd. in 1998, and 0.35μm from
ROHM in 1999. In addition, as part of the IP development project, a prototype of STARC 0.13μm was devel-(a)Trend of number of designs fabricated.

oped. Since FY 2001, we have been providing servicesof CMOS 0.18μm from Hitachi, Ltd. In 2002, under
the leadership of Dr. Iwata of Hiroshima University, we
conducted a trial trial fabrication service in cooperation
with VDEC and MOSIS. This service provides overseas
fabs such as TSMC and IBM at low cost through MOSIS. Furthermore, under the leadership of Dr. Shibata of
the University of Tokyo, NEC Compound Device, Inc.
provided a prototype service for bipolar LSI. In 2004,
we started prototyping Oki Electric CMOS SOI 0.15μm
process and ASPLA 90nm process as test prototypes, andthe 90nm prototype was operated as a regular prototype
from 2005 in the form of public solicitation. In FY2006,
we started trial production of 0.18μm process by ROHM(b)Trend of designed area

and test production of 0.25μm SiGeBiCMOS by Hitachi,Ltd. In FY 2007, we started to study an advanced process
to succeed 90nm CMOS, which was terminated in FY
2007, and in FY 2008, we started trial production of eShuttle's 65nm CMOS. In addition, as part of the METISTARC project "Next Generation Semiconductor Circuit
Architecture Commercialization Support Project," prototype production using Renesas Electronics' 40nm CMOS
was also started. On the other hand, CMOS1.2μm was
terminated in September 2011, Renesas Electronics'
40nm CMOS prototyping was terminated in 2012, andeShuttle's 65nm CMOS prototyping was terminated inAugust 2013. As a successor to CMOS 1.2μm, a test prototype of CMOS 0.8μm was conducted in October 2012
with the cooperation of Onsemi-Sanyo Semiconductor
Manufacturing Co. As for the leading-edge prototyp-(c)Trend of designed area normalized by design rule.
Figure A.2.1 Trend of number of designs and designed chip area.b

ing, STMicroelectronics started FD-SOI 28nm CMOS

40

2021本文レイアウト_英語_7_最終.indd 40

2021/08/19 0:55

prototyping through CMP of France in FY 2013. In addition, we started SOTB 65nm CMOS prototyping byRenesas Electronics as a regular prototyping in FY2015.
In FY2020, we started to study BiCMOS 0.18um prototypes under an agreement with IHP of Germany.
Fig. A.2.1(a) shows trends of number of chip designed
for VDEC chip fabrication. For the first 6 years until
2001, the number of designed chips shows steady increase, which means drastic improve of the effectivenessdrastic increase of number of students related to LSI chip
design and education. During few years of stable number
around 400 chip designs per year, we can see transition

A-2
Figure A.2.2 Trend of number of processors
and universities fabricatedchip.

Appendix

researches and education of LSI design, and we assumeof designs toward finer process. In 2007, we saw a large
drop, which was caused by sudden process transition
from 0.35μm CMOS to 0.1μm CMOS, and in 2008, we
also saw another drop by process transition from 90nm
CMOS to 65nm CMOS.
Fig. A.2.1(b) shows trends of designed chip area, whichshows much clear trends of drop by process migration.
On the other hand, Fig. A.2.1(c) shows trends of designed
chip area normalized by design rule, which assume to bestrong relation with design efforts. Coming from the factthat the normalized chip area is still growing, we assume
the major reason for decrease of number of chips and designed area is increase of design effort per chip and perunit area due to process scaling.

41

2021本文レイアウト_英語_7_最終.indd 41

2021/08/19 0:55

Table A.2.1 Chip fabrication schedule in 2020
○0.8μm CMOS (On-Semiconductor - Sanyo)
Chip application deadline

Design deadline

Chip delivery

2020 #1

2020/7/6

2020/9/28

2020/12/17

2020 #2

2021/1/12

2021/3/29

2021/6/28○0.18μm CMOS (Rohm)
Chip application deadline

A-2

2020 #1
2020 #22020 #32020 #4

2020/3/16
2020/6/15
2020/8/3
2020/11/30

Design deadline
2020/6/8
2020/9/7
2020/10/26
2021/2/22

Chip delivery
2020/10/6
2020/12/8
2021/2/2
2021/6/4

Appendix○SOTB 65nm CMOS
Chip application deadline

2020 #1
2020 #2

2020/8/3
2021/1/25

Design deadline

2020/8/24
2021/3/8

Chip delivery

2021/2/16
2021/9(est.)

422021本文レイアウト_英語_7_最終.indd 422021/08/19 0:55

A.3

SeminarSeminars are always needed as the advancement of LSI

tutorials on these tools are highly demanded. VDEC of-design technology. In 2020, VDEC has held CAD Semi-

fers the CAD Seminar twice per year. In the CAD Semi-nar, Refresh Seminar, and Designer's Forum, for academicnar, VDEC invites lecturers from venders including Ca-

and industrial circuit designers. In this fiscal year, all thedence, Synopsys and Keysight to give tutorials on theirseminars were held online due to the pandemic of COV-

CAD tools. The seminar is held in VDEC, The University

ID-19.

of Tokyo and VDEC sub-centers simultaneously in several universities nationally, August, September, and March

A.3.1 CAD Seminar for VDEC users

of one fiscal year. Each tutorial takes one or two days.

Along with advancement of circuit design CAD tools,

A-3
Appendix

Table A.3.1 CAD technical seminar in 2019 fiscal year
CAD Seminar I
Date

Tutorial

Venue

Attendees

8/11

Keysight Empro

Online14

8/19, 19
8/25
8/27, 28
9/1
9/4
8/11
8/19, 19
8/25

Synopsys IC Compiler-II
Synopsys IC Validator
Cadence Virtuoso Schematic, Layout
Synopsys Custom DesignerCadence Innovus
Keysight Empro
Synopsys IC Compiler-II
Synopsys IC Validator

OnlineOnlineOnlineOnlineOnlineOnlineOnlineOnline

27
19
74
18
24
14
27
19

CAD Seminar II
Date

Tutorial

3/18

Cadence Innovus

3/19
3/24
3/25
3/26
Until 3/31
Until 3/31
Until 3/31

Synopsys SiliconSmart
Cadence SpectreRF
Cadence Quantus
Synopsys Q&A Meeting
Synopsys Formality
Synopsys Design Compiler
Synopsys IC Compiler-II

Venue

Attendees

Online35

OnlineOnlineOnlineOnlineOn-demand
On-demand
On-demand

16
50
34
14
95
113
114

43

2021本文レイアウト_英語_7_最終.indd 43

2021/08/19 0:55

A.3.2 Refresh Seminar for industry and academia
The fundamental and advanced knowledges are both
imperative to integrated circuit design. VDEC offers theRefresh Seminar for industrial and academic people. University professors and highly experienced engineers areinvited to give lectures on circuit design, covering the topics on analog, digital, RF, MEMs, and basic design flow.
The seminar was originally launched in 1998, with thesupport of Ministry of Education Technical Education
Division. It is now being supported by several industrial/
A-3

academic societies.

Appendix
Fig. A.3.1Refresh Seminar at VDEC seminar room at the University of Tokyo, VDEC.

Fig. A.3.2 Screen shot of Refresh Seminar online.

44

2021本文レイアウト_英語_7_最終.indd 44

2021/08/19 0:55

Table A.3.2 Refresh Seminar
Date
6/23, 24

7/6, 7, 8

CourseContents

LectureAttendees

VDEC Digital Circuit
Design Flow

Digital circuit design flow using
Kazutoshi Kobayashi
VDEC-collaborated CAD environment (Kyoto Institute ofand process
Technology)

36

Analog Circuit Design

Masahiro Sugimoto(Chuo Univ.)
Hidetoshi Onodera(Kyoto Univ.)
Koji Kotani(Tohoku Univ.)

48

Hiroyuki Ito(Tokyo Inst. of Tech.)

12

Toru Nakura(Fukuoka Univ.)

27

Yoshio Mita
(The Univ. of Tokyo)

2

Yoshio Mita
(The Univ. of Tokyo)

1Analog Circuit Design and simulation
Integrated Circuits Verifica-tion (LVS,
DRC)

A.3.3 Matlab Seminar for industry and academia

A-3
Appendix

Modulation/Demodulation
Cascaded connection
CMOS-RF Circuit
Basic Performance
7/20, 21
DesignTransceiver Architecture
Circuit Element
Design Flow
Custom circuit design flow using
Transistor-Level Circuit
8/20, 21
VDEC-collaborated CAD environment
Design Flowand process
Custom circuit design flow using
VDEC-collaborated CAD environment
and pro-cess MEMS Basic 1: Fabri-cat9/7, 8
MEMS Design VDEC ion Process
MEMS Basic 2: Operation Principle
Structural Design
Layout Design
CAD Design and Analysis
9/14, 15, 16 MEMS Fabrication
Lithography, Etching, Release
Vibration measurement and analysis

A.3.4 Designer's Forum for academia

Collaborating with Mathworks Inc., we successfully

VDEC LSI designer forum intended for students andheld a seminar named “Improving development efficiency

young teachers were held. The VDEC LSI designer fo-

for FPGA/ASIC using Matlab/Simulink”. The attendee

rum has aimed to sharing the information that generally

number is 27. Using fruitful documents and design re-hard to be obtained common technical reports or academ-

sources provided by Mathworks Inc, we were being tu-

ical papers, such as the failure an LSI designer had been

tored about translating Simulink block diagram to HDL

through and the solution, and the construction method in

automatically during the 4-hour seminar.

the design milieu in the laboratory.

Table A.3.3 Program of Designers Forum in 2020
Table B.3.5 Program of Designers Forum in 2020
9/25
12:00-12:45
Reception
12:45
Opening
13:00-14:00
Keynote Speech
14:00-14:10
Break
14:10-15:50
VDEC Design Award Presentation I
9/26
13:00-13:50
Idea Contest Presentation
13:50-14:00
Break
14:00-14:50
Idea Contest Presentation
14:50-15:00
Voting
15:30Awarding Ceremony and Closing

452021本文レイアウト_英語_7_最終.indd 45

2021/08/19 0:55

A.4

Venture companies related to VDEC

Some professors related to VDEC started venture companies. The following is a list of the venture companies
related to VDEC.
[1] AIL Co.,Ltd. (http://www.ailabo.co.jp/)
Related professor : Professor Kazuo Taki, Kobe Univ. (Representative Director)
Description of business : (1) LSI design service(2) Engineer dispatching service

A-4[2] Synthesis Corporation

Appendix(Merged with Soliton Systems on July 1st in 2017, http://www.synthesis.co.jp/)
Related professor : Professor Emeritus Isao Shirakawa, Osaka Univ. (Director)
Description of business : (1) System LSI development and design service(2) IP development and sales(3) Development and sales of IPs(4) Development of EDA tools[3] ASIP Solutions (http://www.asip-solutions.com/)
Related professor : Professor Masaharu Imai (Representative Director, CTO)
Description of business : (1) R&D, education and consulting of IoT application system(2) Sales of ASIP design tool and consulting of ASIP development[4] Nanodesign Corporation (http://www.nanodesign.co.jp/)
Related professor : Professor Kazuyuki Nakamura, Kyushu Institute of Technology. (Rep-resentative Director)
Description of business : (1) LSI design and development(2) Design consulting, etc.
[5] A-R-Tec Corp. (http://www.a-r-tec.jp/)
Related professor : Professor Emeritus Atsushi Iwata, Hiroshima Univ. (Representative Director)
Description of business : (1) Design and measurement of IC and evaluation board(2) Crosstalk noise analysis(3) Develop human resources for new employees and beginners[6] Ishijima Electronics (http://ishi.main.jp/)
Description of business : (1) Electronic circuit and board development(2) Software development(3) Consulting

46

2021本文レイアウト_英語_7_最終.indd 46

2021/08/19 0:55

System Design Lab (d.lab),
School of Engineering, The University of Tokyo
Annual ReportAugust, 2021
Published by
System Design Lab (d.lab), School of Engineering, The University of Tokyo
Tadahiro Kuroda
Address: Hongo 7-3-1, Bunkyo-ku, Tokyo, 113-8656, Japan
Printed in
SOHOKKAI co., Ltd. Tokyo Branch
Address: Koutoubashi 4-25-10, Sumida-Ku, Tokyo, 130-0022, Japan
Copyright Ⓒ by System Design Lab (d.lab), School of Engineering, The University of Tokyo

2021本文レイアウト_英語_7_最終.indd 48

2021/08/19 0:55