東京大学大学院工学系研究科
附属システムデザイン研究センター
先端設計研究部門・先端デバイス研究部門（旧VDEC）基盤設計研究部門・基盤デバイス研究部門

令和５年度
ISSN 2436-6552

年 報

2023
Systems Design Lab, School of Engineering,(VLSI Design and Education Center), The University of Tokyo

Annual Report

Systems Design Lab, School of Engineering
The University of Tokyo 2023

Message from the Director of d.lab

Tadahiro Kuroda
Director
Systems Design Lab (d.lab)
School of Engineering, The University of Tokyo

In Februaryof thisyear,
the Ministryof Education,
Culture,Sports,and ofTechnology(MEXT)
issued amost
call for
proThebook ChipWar
by Chris
Miller has
won a wide
audience.
AsScience
its subtitle
The fight for
the world’s
criticalposals undersuggests,
their「次 世代X-nics半導 体 the創 成
拠 点of形the成 battles
事 業」(Translation:
Initiative
Establish
Centers fortechnology
it depicts
in detailhistory
between nations
into
thearea ofInnovation
semiconductors.
Next-Generation
X-nics Semiconductors).
Theirthere
ultimatethe creationforof groundbreaking,neXt-generation,novel
But Chip War describes
only one scenario;
are goal
otherispossibilities
the future. That was
the motivationforsemiconductors
throughmulti-disciplinarysynergy(multiplication“X”), much
likebookthe creationof various
functionalme
to write the bookthat
I originally called
Semiconductor
Democracy.
The
was eventually
publishedindevicJapaes fromspintronics
and title
photonics,
novel computingoftechnologies
from –neurophysiology
quantum thatmechanics,
and
nese
with
the modifiedof The Super-Evolution
Semiconductors
The Future of theand
Technology
Dominates
integrated
theWorld. devices from novel materials based on topotronics.
The future described in the book is as follows.

Regardless of the speciﬁc form of the novel semiconductor, a key requirement is the improvement of energy efﬁciency.◇◇◇◇◇◇◇◇(Translated
In the last decade, while the fromamountAI processing skyrocketed by 4 orders of magnitude, the energy efﬁciency of
theof
Postscript)
general-purpose
increased
only
antwo
order
of magnitude.
has
platform
providersas GAFAM
Semiconductorprocessors
democracy
and chipbywar
are
sides
of the sameThis
coin.
Indriven
this book,my focusis on suchsemiconductor
to develop their in-house specialized chips to achieve high energy efﬁciency. However, the development of specialized
democracy.
chips
requiresincreasingly
moretime andhigher cost.
Given therapid
in AI technology,
if ittakes acontemyear to
In the19th century,
Otto vonBismarck
explained
in a speechhowironadvancemade a nation.
Indeed, ironcreateddevelopa specialized
is alreadyobsolete by the time the development is complete. The strategy for growth in theporarycitiesand gavechip,birthit toweaponry.
DXToday,
age requires
rapid iteration(being agile)
the development-improvement
can be Whatachieved
LSI chips are
the technology
battlegroundis inofsemiconductors.
Semiconductorscycle.
makeThisa nation.
willifsemiconducdesigned
theway
softwareis written
prototyped
a programis compiled
tors
create,andwhatwill they
break?andIt willbe up to the
our way
imagination
andwisdom. to make them updatable like software.
Chip makers are engaged in fierce battles to dominate in the manufacturing of next-generation semiconductors.
However, semiconductors are evolving into such a giant collection of technologies that the challenges can no

A related
questionby
is how
to acceleratetechnology
The answer
canbe foundinof
theidea of a collective
longerbe overcome
a single
corporation
or even ainnovation.
single country.
We reallyshouldthink
semiconductors
as abrain expounded
globalcommons. by Joseph Henrich, Professor of Human Evolutionary Biology at Harvard University. The bigger thecollective
brain
is,should
the easieris toacceleratetechnology innovation.
For instance,
researchecosystems.
conducted on variAs a result,
wenotitbeinstigating
semiconductor
wars; instead,
we needthroughto be building
ous
Paciﬁc islands,
the paper“Population
Size Predicts
TechnologicalComplexity
in Oceania”
foundofa correlation
Technology
is getting
more andmore complex.
Therefore,
we must lookat the entire
forest instead
the individbetweenof variationin ﬁshingandthe population
theforest,island.orThe
that, even
witha arichsmallerbrainualtrees. theThesizechallenge
ahead
for thetools
world
is how
to nurtureofthe
in reasonother words,
createindustrial
than Neanderthals, Homo sapiens were able to invent and utilize various tools is also thought to be due to their integraecosystem.
tion
Thetheinternet
has enabled
Weintocanlarge
take groups.
hints frombotanical
world. a giant collective brain of 7.7 billion people. A platform that attracts
manypeople plants
will turninto a center
for accelerated
Nowadaysflourisheverywhereacross thetechnology
globe. Theinnovation.
revolution that created the world of today was started
by flower-bearing plants.

We
at d.lab proposed
an “Agile-X
forflowers
Democratizationofresulted
Innovative
Semiconductor
Technology.”
targetbyisA
co-existence
relationshipborn Center
betweenand insects
in theirco-evolution
where oneOur
evolveda 10-fold increasein thepopulation
ofvicechipversa.
designers. To that end, we will create an agile development platform topromotingevolutionin theother, andreducebothofthetime andcost forchip
development
and prototyping
by anoforderof magnitude. During the application
The birthflowers
providedthetrigger
for the accelerated
evolution
life forms.
process,
we wereasked bythe X-nics
review committee
what
X stands
answered
thattheir
it is theunknown
Accordingto Darwin’s
theoryof evolution,
only the fittest
survive
andfor.
areWe
able
to continue
familylines. Inofa“what” innovationwillchange theHowever,world. Nevertheless,we know “where”
the innovation
willuncovered
come from.
thenutshell,life is about
competition.
the hidden mechanismof evolutionthat is beingbyThatthe islatestplatforma largepopulation
peoplecongregate.
I ampleasedto saythat our toproposalhas other.
been accepted.
scienceis wherethat livingorganisms
not ofonly
competewith eachother
but also
cooperate
help eachThat is theIbelieve that,
intheory
addition
More Moore and More than Moore, More People will accelerate the creation of intellectual
essenceof theof tosuper-evolution.
value.
Similarly, to enrich the “semiconductor forest,” it is important to find its “flower.” It was with that thought in mind
that I set forth my theory of the super-evolution of semiconductors in this book.
I started by describing how high-performance semiconductors are developed from the standpoints of More Moore
and More than Moore.

1

Next, I shared my thoughts on what high-performance semiconductors can create from the standpoint of innovation, or in other words, the standpoint of More People.
Will we be able to find the “flower” that is needed to evolve semiconductors from the age of competition to theage of co-existence and co-evolution? It is going to take more than capital and Moore’s Law to make semiconductors
a global commons.
The need is to get many people involved. That is More People.
◇◇◇◇◇◇◇◇
One other point I would like to bring up is agility.
◇◇◇◇◇◇◇◇(Translated from Chapter 1, Section 4, “The Semiconductor Forest: Co-existence and Co-evolution”)
Eventually, flowers acquired new power.
It was the shortened lifecycle. The time from pollination to fertilization was shortened from one year to a few
hours. That resulted in accelerated evolution of all life forms.
y = a(1+r)nThat is the formula for calculating compound interest, where r is the interest rate and n the number of times interest is compounded. Even if you start with a small principal a, the future value can grow large if you continue thecompounding for a long time.
If you replace n with 1/t, where t is the development cycle time, you get the fundamental equation for the digital
economy. The same equation applies to both the improvement in chip performance and the growth of a company.
Put differently, the strategy to grow the digital economy is to repeatedly iterate the improvement cycle at highspeed. Rather than the amount of improvement (r), the key is to increase the number of times improvement is made(n), or in other words, reduce the development cycle time (t).
That is why we want to be agile.
◇◇◇◇◇◇◇◇The book presents the fundamental thinking of d.lab. I would appreciate it if you would get hold of a copy and giveit a read.

2

2023
Systems Design Lab, School ofEngineering,(VLSI Design and Education Center),
The University of Tokyo
Annual Report

C

O

N

T

E

N

T

S

Message from the Director of d.lab ……… 1
Chapter 1

Introduction to d.lab………………………………………… 4

Chapter 2

d.lab Overview and FY2022 Annual Report……… 5

2.1
2.2
2.3
2.4
2.5

Advanced Design Research Division………5
Advanced Device Research Division………11
Platform Design Research Division………12
Platform Device Research Division………16
Activity Report of ADVANTEST D2T Research Department………20

Chapter 3

Research in d.lab………………………………………………… 23

Appendix……………………………………………………………………………… 39
A

Former VDEC contents………39
A.1 VDEC CAD Tools………39
A.2 Status of Chip Fabrication Support at Platform Design Research Division………40
A.3 Seminar………43
A.4 Venture companies related to VDEC………44

Chapter 1

1﻿
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Introduction to d.lab

The VLSI Design and Education Center (VDEC) was

ber of 2019 and formed a strategic alliance with TSMC aestablished at the University of Tokyo in 1996. At themonth later. d.lab was formed by establishing the Ad-

time of its founding, Japan’s semiconductor industry heldvanced Design Research Division and the Advanced De-

a 50% share of the USD 50-billion global market, andvice Research Division and adding them to the existing

engineers who could hit the ground running were in highPlatform Design Research Division and Platform Device

demand. VDEC has since provided unparalleled, out-

Research Division which had been operating VDEC andstanding education to develop many high-caliber engi-

the Takeda Clean Room. Subsequently in October ofneers for the semiconductor industry.

2020, d.lab started an industrial partnership program

However, have these graduates of VDEC been able tofully realize their potential? In the last quarter century,

which has grown to include more than 40 corporate
members.

even though the global semiconductor market enjoyed aFurthermore, the Research Association for Advanced

rapid 7% annual growth rate, Japan’s share continued to

Systems (RaaS) was founded in August of 2020 to lay out

shrink, falling to the current level of about 10% of a mar-the framework for the university to collaborate with both

ket that is now approaching USD 500 billion.

the industry and the government. Using d.lab and RaaS to

The current semiconductor business is one of mass pro-realize a two-pronged strategy of open and closed collabo-

duction of high volume, low margin general purpose

ration respectively, the university is actively promoting

chips. General purpose chips have been able to achieve

cooperation between academia and society as well as col-large volumes because of the wide adoption of the vonlaborative creation with industry. Our research aims to

Neumann computer architecture constructed with theboost the time-performance of semiconductors, with tar-combination of memory and processor chips. While Ja-

get goals of 10x increase in both energy and development

pan led the world in memory device innovation, it lost theefficiencies.

business competition on capital investment.

Japan is aiming to transition from the current industri-

The mass production, mass consumption model has its

al/information society to Society 5.0, a human-centric

limits. Because of the excessive burdens it places on thesociety where knowledge is value. In this knowledge-based

environment, the world is now facing an energy crisis. The

society, semiconductors will evolve from being a necessity

recent trend of applying AI to big data analysis is fuelingof industry to the brain cell of society.

further growth in energy consumption.
In the middle of this development, a game changer has
emerged. Recognizing that it is hard to compete by using

What strategy should the semiconductor industry pursue to address this evolution? It is d.lab’s mission to findthe answer.

general purpose chips procured from semiconductor makers, technology giants including GAFA have started todevelop their own specialized logic chips in-house.
In response to this paradigm shift, the University of Tokyo established the Systems Design Lab (d.lab) in Octo-

4

Tadahiro Kuroda
Director, Systems Design Lab

Chapter 2

d.lab Overview and FY2022 Annual Report

2.1 Advanced Design Research Division
2.1.1

Division Overview

The Advanced Design Research Division faculty con-rate members. We would like to thank these members
again for their participation.

er, one project professor, one senior fellow, and one pro-off to a certain extent, in addition to organizing various

ject researcher (joint appointments included). Its goal is toseminars in the form of webinars as in previous years, weenable the design of integrated circuits with both highwere able to pursue our original vision of not only sharing

energy efficiency and high design efficiency.

the research accomplishment of d.lab, but also hosting

In August 2022, NEC Corporation, the University ofevents to enable program members to interact with re-Tokyo, and Canon Inc. were selected to undertake the re-nowned professors and students from the University ofsearch and development of versatile high-level synthesis

Tokyo, with universities and research organizations fromtechnology and novel general-purpose, data-flow comput-

around the world, and with other industrial executives

ing mechanism by the New Energy and Industrial Tech-and leaders, as well as events to share information andnology Development Organization (NEDO) under its

knowledge from international conferences and introduce

Project for Innovative AI Chip and Next-Generationand experience the most advanced technologies from theComputing Technology Development, R&D Area 4:

likes of TSMC. The remainder of the section summarizes

Technology Development to Accelerate Industrial Appli-

the Partnership Program activities of FY2022. As in previ-

cation of AI Edge Computing. The research is scheduled

ous years, our activities spanned almost the entire year

to be completed by March 31, 2025.

from May 2022 to March 2023. Table 2.1.2 summarizes

In addition to its research effort, the Advanced Design

the seminars we held in FY2022.

Research Division has two organizational responsibilities.

We held our Program kickoff meeting of the fiscal year

First, it operates the d.lab Partnership Program with help

on May 25, 2022, which also featured special presenta-

from other d.lab divisions. Second, it operates the Re-

tions by some of the young researcher winners of the 2021

search Association for Advanced Systems. The following

MIT Technology Review Innovators Under 35 Award.

section is the FY2022 report on these two operations.

Specifically, three of the young researchers gave talks on

2-1

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CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCIn FY2022, because COVID-19 restrictions had eased

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sists of four professors, one associate professor, one lectur-

next-generation electronics technology, followed by a
2.1.2

d.lab Partnership Program Activities

presentation summarizing the Program activities planned

The d.lab Partnership Program was launched in FY2020

for the year. The first presenter was Motion Lib CEO

to establish an international center of knowledge-value

Takahiro Mizoguchi. Dr. Mizoguchi and his company

where system designers and members of the semiconduc-have developed real haptics technology to control touch

tor industry meet to exchange information and ideas andsensations and strength adjustment, as well as the ABC-

to engage in open discussion of collaboration between ac-

CORE chip at the core of the technology. He discussed

ademia and society. The Program aims to create a hub that

their business of helping to solve the labor shortage prob-

brings together ideas from system designers in industries

lem through the use of robots capable of performing deli-including IoT, AI, 5G, automated driving, and healthcare,cate tasks.

advanced semiconductor technologies such as advanced

The second presenter was Dr. Takuya Sasatani, project

CMOS processes and 3D integration technologies, as wellassistant professor from the Graduate School of Engineer-as enablers of such technologies including materials anding at the University of Tokyo. He has developed technolo-

manufacturing equipment. In FY2022, a total of 49 cor-gy to provide wireless charging across the space of an entire

porations joined the Program, which is 6 more than theroom. His presentation focused on the research and devel-

prior year. Table 2.1.1 contains the list of FY2022 corpo-

opment of applied technology based on wireless charging

5

technology for the realization of a cable-free lifestyle.
The third presenter was Dr. Atsutake Kosuge, lecturer

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a next-generation core technology.

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from the Systems Design Lab of the Graduate School of

On Aug 25, we held another seminar to report on theEngineering at the University of Tokyo. He is developing

2022 IEEE VLSI Symposium on Technology & Circuits,

ultra-low power AI chip technology. His talk discussed AI

which took place from Jun 12 to 17 in Honolulu, USA.

sensing technology that enables the widespread adoption

Since 1987, this has been a premier international confer-and advancement of automation in the field, including

ence for the microelectronics industry on state-of-the-art

factories and construction sites, in order to solve the labor

semiconductor device and process technology, as well as

shortage challenges faced by an aging society. He was fol-semiconductor circuit technology, jointly held by thelowed by Professor Tadahiro Kuroda, Director of d.lab,

IEEE Electron Device Society/Solid State Circuits Society

who provided a preview of the FY2022 d.lab Partnershipand the Japan Society of Applied Physics (sponsored by

Program activities.

the Institute of Electronics, Information and Communi-

On Jun 22, as a follow-up to our event in Jan 2021, we

cation Engineers). Its location alternates between Kyoto,

held an IBM Day to introduce IBM Albany and provide an

Japan, and Honolulu, USA. In 2022 it was held in the

update on IBM’s quantum computing development. This

US. (Because of COVID-19, it was held onsite for thewas a hybrid event where, in addition to the normal web-first time in 3 years.) With “Technology and Circuits for

cast, we added an onsite visit to IBM’s Shin-Kawasaki Facil-

the Critical Infrastructure of the Future” as its theme, theity “Shin-Kawasaki Souzou no Mori.” We arranged a tour

program covered the latest technology in advanced logic

of a working quantum computer both before and after the

CMOS, memory, image sensor, photonics, machinepresentations. The event also featured a poster session. Re-

learning, AI, digital, communication, and analog. Topics

garding IBM Albany, Dr. Shintaro Yamamichi from IBM

discussed also included the development and realization

provided a technology update on the research and develop-of future technology, as well as how to foster the next-gen-ment of advanced AI core, chip, and packaging at the IBM

eration professionals. We focused our report on the tech-

AI Hardware Center, as well as explaining how to partici-

nology trends and topics in the areas of circuit, communi-pate in the development. Regarding IBM quantum com-cation system, AI, machine learning, advanced CMOS,

puting, Mr. Daiju Nakano and Mr. Norie Iwasaki frommemory, and 3D integration.

IBM introduced its technology and roadmap, as well as its
construction of an ecosystem including hardware.

On Oct 26, as a continuation from the year before, we
held a technology exchange meeting for our corporate

On Jul 20, we hosted a seminar to report on the 2022

members. By popular demand, the event this year wasIEEE 72nd Electronic Components and Technology Con-thheld onsite at Takeda Hall on the 5 floor of Takeda

ference (ECTC2022). The conference is organized by the

Building. Thirteen of our corporate members who ex-IEEE Electronics Packaging Society to provide a forum forpressed interest in a panel exhibition delivered a shortwide ranging discussion of the science and technology ofpresentation, followed by a poster session in the foyer. As

packages, components, and microelectronics systems. It is

the organizer, we were delighted to be able to provide a

one of the world’s long-established and foremost interna-

forum for our members to interact and network.

nd6

stream for our current activities, and hybrid bonding that is

tional conferences, held for the 72 time last year. It was

On Nov 29, we organized a tour of the TSMC 3DIC

held onsite for the first time in 3 years. The technology pro-Center together with another onsite member networking

gram covered the latest achievement in development andevent. The TSMC Japan 3DIC R&D Center is the firstinnovative technologies from across the full spectrum ofoverseas R&D center established by Taiwan Semiconduc-packaging technology. Its main topics included advanced

tor Manufacturing Company (TSMC) outside of Taiwan.

packaging, modeling and simulation, photonics, intercon-

Guests including high-ranking government officials were

nection, material and process, reliability, manufacturinginvited to the opening ceremony held on Jun 24, 2022.

technology, components and RF, as well as emerging tech-

Given the increasing importance of backend processing,nologies. In our report, we focused on the latest trends andincluding 3D implementation, the Center aims to pursue

topics in advanced packaging technology that is main-

R&D of the most advanced 3D IC implementation ininar where we introduced thermal control technology andment manufacturers, research institutions, and universi-

the latest packaging technology, as well as d.lab’s materials

ties in Japan. The event was made possible thanks to thestrategy. At the seminar, Prof. Masahiro Nomura from thekind cooperation of the TSMC Japan 3DIC R&D Center.

Institute of Industrial Science at the University of Tokyo

The event started with a presentation by the Center at thediscussed “The Key to Semiconductors Thermal Solution:

Tsukuba International Conference Center, located close

The Physics of Heat Transfer and Thermal Flow Control

to the Tsukuba Central Station and in the vicinity of theTechnology,” while Mr. Hidenori Abe, senior director

Center. Afterwards, participants were divided into 3

from Resonac, presented on “Semiconductor Materials

groups to take turns to visit the Center. The tour took theDevelopment at the New Resonac, a Chemical Company

participants up to the state-of-the-art clean room and pro-Based on Co-creation.” In addition, Mr. Kazunori

vided an introduction to the latest technology.

Yamamoto, project researcher from d.lab, described theductor performance, it is essential to simultaneously ad-“New Semiconductor Packaging Materials Strategy Envisioned by d.lab.”vance both device scaling technology and advanced pack-

We ended our FY2022 seminar series with a meeting

aging technology, the latter exemplified by chiplet. On

on Mar 15, 2023, to report on the 2023 International

Dec 13, continuing from the year before, we held an imec

Solid-State Circuits Conference (ISSCC2023). ISSCC

Day where we invited leaders of imec, who are drivingthcelebrated its 70 anniversary this year. In addition to everthese technology areas, to introduce to us the world’s most

more engaging discussion of processor technology for ma-

advanced 3D system integration technologies. It provided

chine learning, there were many presentations on imaging

a great opportunity to hear live from imec as the world

devices and memory, which are strongholds of the Asianauthority in this domain. We were lucky to have Dr. Nao-region. ISSCC is the top international conference on IC

to Horiguchi, imec Logic CMOS device program direc-

technology held in February. Based on what was seen at

tor, discuss “Future CMOS device scaling by 3D architec-the conference, Prof. Makoto Ikeda, who has been fortures,” and Dr. Eric Beyne, imec Senior Fellow, VP R&D,

years the chair of ISSCC’s technology program, and other

Program Director 3D System Integration, present on “3D

faculty members of d.lab discussed the latest trends in IC

Integration Technology: Enabling Heterogeneous Systemtechnology that will likely be driving the semiconductor

Scaling.”

industry going forward.

At the beginning of the year on Jan 18, 2023, we held a

In FY2022, while carefully monitoring the develop-

seminar to report on IEDM2022. IEDM (International

ment of COVID-19, we organized a mix of remote semi-

Electron Devices Meeting) is the world’s top internationalnars and in-person events. We were able to incorporate

conference on device technology organized by IEEE. The

entirely new activities like the tours of IBM and TSMC.

conference was held in a hybrid format – allowing bothIn FY2023, we plan to continue to organize events to pro-in-person and on-demand access – from Dec 3 to 7. In our

mote active intellectual exchange between our Program

meeting, faculty members from d.lab provided an overview

members and the university community, as well as ex-of the conference and discussed the latest trends in devicechange among our Program members.

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To realize further improvement in advanced semicon-

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collaboration with materials and semiconductor equip-

technology, focusing on advanced CMOS device technology and materials, non-volatile memory technology, computing technology, and 3D integration technology.

2.1.3

Research Association for Advanced Systems Activities

In recent years, the debate over the end of Moore’s Law

The Research Association for Advanced Systems (RaaS)

has become increasingly serious, and the development of

was established on Aug 17, 2020. The goal of RaaS is tochiplet and 3D IC semiconductor packages more con-increase 10-fold the development efficiency of specialized

crete. As the integration level of semiconductor packages

chips, which are indispensable in a data-driven society, byincreases, in addition to high-performance, the materials

constructing a design platform for such chips and byused must be compatible with the process, which is diffi-

adopting an open architecture for hardware design. In ad-cult to achieve. On Feb 8, we held a d.lab Materials Sem-dition, RaaS aims to increase 10-fold energy efficiency by

7

2-1
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researching and developing 3D integration technology

dition, more people can become hardware designers.

and by stacking multiple chips manufactured in the latest

Eventually, as the open-source culture takes root in hard-

7nm CMOS technology in a single package.

ware development and the supporting ecosystem expands

RaaS believes that the driver of the semiconductor in-and develops into a multi-layer network, mass collabora-

dustry is once again swinging back from general purpose

tion will become possible. When that happens, one will beto specialized chips, against the backdrop of the uniqueable to develop chips like writing software.

energy crisis of the data society. The crisis is being spurred

Alan Kay once said that “People who are really seriousby the exponential growth in data and the increasing so-

about software should make their own hardware.” Indeed,

phistication of AI processing. On the current trajectory,

system development requires both hardware and software

IT equipment alone is expected to consume close to twice

development.

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the total available power of today by 2030, and about 200

Our goal at RaaS is to democratize access to silicontimes the total available power of today by 2050. It will betechnology. We aim to create a development platform toimpossible to realize a sustainable future if digital transfor-

realize agile authentic prototyping where prototypes canmation consumes so much energy as to destroy the earth’s

be created rapidly by innovating silicon compiler technol-

environment.

ogy to enable designing chips like writing software.

Under such a condition, only those who can improve

Our technology goal is a 10-fold increase in both devel-

energy efficiency 10-fold can afford to increase computer

opment efficiency and energy efficiency. We plan to im-

performance 10-fold, or extend smartphone use 10-fold.

prove development efficiency by creating an agile design

Compared to general purpose chips which are required toplatform and adopting an open architecture. In addition,

handle all tasks, specialized chips achieve orders-of-mag-

we aim to increase energy efficiency through manufactur-

nitude improvement in energy efficiency by eliminatinging chips in the most advanced CMOS process and im-

unneeded circuits. That is why specialized chips are in de-plementation of 3D integration.

mand. In addition, since AI processing utilizes neural net-

We provide semiconductors as a service, rather than sellworks which process data in parallel, it is difficult for vonthem as a product. It is the role of RaaS to develop the

Neumann architecture designed for sequential processing

necessary technologies to achieve that goal.

to deliver adequate performance. As a result, specialized

RaaS had planned to bring researchers from member

chips are being developed around the world to serve as AI

companies together at the Mejirodai International Village

accelerators. Furthermore, the slowing of Moore’s Law iscampus of the University of Tokyo where they can con-providing additional tailwind for specialized chips.

duct research while providing stimulation to each other.

Unfortunately, specialized chips development requires
special skills and cannot be easily undertaken by everyone.

8

However, because of COVID-19, RaaS activities have also
been limited to center around remote work.

The latest chips integrate more transistors than there are

In FY2021, RaaS applied to and was accepted by thepeople in the world. Development costs have skyrocketed“Project for Research and Development of Enhanced In-

in recent years to approach $100 million. It will take evenfrastructures for Post 5G Information and Communica-

a team of several hundred designers several years to devel-tions Systems / Development of Advanced Semiconduc-op a specialized chip, which makes it difficult to keep pace

tor Manufacturing Technology (b) Development ofwith today’s rapid technological advance.

Advanced Semiconductor Backend Processing Technolo-

In software development, bugs can be patched after thegy (More than Moore)” of the New Energy and Industrial

fact. But hardware cannot be shipped unless it is com-

Technology Development Organization (NEDO). The

pletely error-free. Compared to software, hardware devel-

development theme is “(b2) Implementation Technology

opment is indeed hard and carries more risk.

for Edge Computing.”

If technologies similar to compilers used in software

In system R&D, RaaS, together with the University ofdevelopment are available to chip development, in otherTokyo, authored and presented multiple conference papers

words, if silicon compilers become a reality, we can expect

in FY2022 to report on its evaluation of a 7nm prototype

both hardware development cost and risk to drop. In ad-

chip. In technology R&D, based on the NEDO projectmentioned above, RaaS focused its efforts on the establishment and implementation of technology for WoW (wafer-on-wafer) and CoW (chip-on-wafer) integration using
Cu-Cu low temperature bonding as part of its direct bonding 3D integration technology development (equipment
and process development for WoW and CoW).
2-1

C

CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC

Aoha, Inc.
Asahi Kasei Microdevices Corporation
ADVANTEST CORPORATION
Analog Devices KK
Ushio Inc.
ORGANO CORPORATIONKIOXIA Corporation
Gigaphoton Inc
Kobe Steel, Ltd.
Kobelco Research Institute, Inc.
Samsung R&D Institute Japan
Siemens Electronic Design Automation Japan K.K.
JSR Corporation
JCU Corporation
Shin-Etsu Chemical Co., Ltd.
SCREEN Holdings Co., Ltd. (Raas)
Sumitomo Corporation
Socionext Inc.
Sony Corporation
Daikin Industries, Ltd. (RaaS)
Dai Nippon Printing Co., Ltd.
DISCO Inc.
Tokyo Electron Ltd.
TOKYO OHKA KOGYO CO., LTD.
Toyobo CO., LTD.
TORAY INDUSTRIES, INC.
Toppan Printing CO., LTD. (RaaS)
Nagase & Co., Ltd
NIKON CORPORATIONIBM Japan, Ltd.
Cadence Design Systems, Japan
Nihon Synopsys G.K.
JEOL Ltd.
NEXTY Electronics
Panasonic Industry Co., Ltd.
Panasonic Connect Co., Ltd. (RaaS)
Semiconductor Energy Laboratory Co., Ltd.
Hitachi, Ltd. (RaaS)
Fujitsu Ltd.
FUJIFILM Corporation (RaaS)
Micron Memory Japan, G.K.
Mitsui Chemicals
Mitsubishi Chemical Corporation
Mitsubishi Electric Corporation
MIRISE Technologies Corporation (RaaS)
Murata Manufacturing Co., Ltd.
Renesas Electronics Corporation
Resonac Corporation
ROHM Co., Ltd.

CCCCCCCCC

Table 2.1.1 L ist of FY2022 d.lab Partner Members(in Japanese phonetic order)

9

Table 2.1.2
Date
5/25/2022

6/22/2022

2-1
CCCCCCCCC
C

7/20/2022

CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC

8/25/2022

10/26/2022

11/29/2022
12/13/2022
1/18/2023

2/8/2023

3/15/2023

10

List of FY2022 d.lab Partnership Program Seminars
Title
Presenter(s)Special Presentations by Young Researcher Winners of MIT Takahiro Mizoguchi, CEO, Motion Lib
Technology Review Innovators Under 35 Award and FY2022 Takuya Sasatani, Project Assistant Professor, GradKickoff
uate School of Engineering, University of Tokyo
Atsutake Kosuge, Lecturer, d.lab
Tadahiro Kuroda, Professor, d.lab
IBM Day
Daiju Nakano, IBM
Norie Iwasaki, IBM
Shintaro Yamamichi, IBM
ECTC 2022 Report
Kai Takeuchi, Project Researcher, d.lab
Masaya Kawano, Project Researcher, d.lab
Masaaki Niwa, Senior Fellow, d.lab
Takeshi Takagi, Principal Researcher, d.lab
2022 VLSI Symposium Report
Mototsugu Hamada, Project Professor, d.lab
Atsutake Kosuge, Lecturer, d.lab
Toshiro Hiramoto, Professor, d.lab
Shinichi Takagi, Professor, d.lab
Masaharu Kobayashi, Associate Professor, d.lab
Masaaki Niwa, Senior Fellow, d.lab
d.lab Partners Technology Exchange
Kazutoshi Wakabayashi, Senior Fellow, d.lab
ADVANTEST CORPORATION
Kobe Steel, Ltd.
Kobelco Research Institute, Inc.
JCU Corporation
Showa Denko Materials Co., Ltd.
Dai Nippon Printing Co., Ltd.
DISCO Inc.
Toyobo CO., LTD.
Toray Industries, Inc.
NIKON CORPORATION
Cadence Design Systems, Japan
Mitsubishi Chemical Corporation
Renesas Electronics Corporation
TSMC 3DIC Center Tour and Onsite Technology Exchange
Tadahiro Kuroda, Professor, d.lab
imec Day
Naoto Horiguchi, imec
Eric Beyne, imec
IEDM2022 Report
Toshiro Hiramoto, Professor, d.lab
Shinichi Takagi, Professor, d.lab
Masaharu Kobayashi, Associate Professor, d.lab
Ken Takeuchi, Professor, d.lab
Takeshi Takagi, Principal Researcher, d.lab
d.lab Materials Seminar
Masahiro Nomura, Professor, Institute of Industrial Science, University of Tokyo
Hidenori Abe, Senior Director, Resonac
Kazunori Yamamoto, Project Researcher, d.lab
ISSCC2023 Report
Makoto Ikeda, Professor, d.lab
Atsutake Kosuge, Lecturer, d.lab
Mototsugu Hamada, Project Professor, d.lab
Tetsuya Iizuka, Associate Professor, d.lab
Ken Takeuchi, Professor, d.lab

2.2

Advanced Device Research Division

Advanced Device Research Division is working for the(RaaS), a technology research association on 3D integra-

development of three-dimensional (3D) integration tech-tion technology operated by d.lab as the headquarters, isnology and advanced device technology aiming at ten

working with member companies of RaaS on the theme

times higher energy efficiency of semiconductor systemsof “Development of direct bonding 3D lamination tech-in the data-driven systems.

nology (equipment and process development for WoW

large amounts of data processing, energy consumption as-

key point technology related to WoW (Wafer on Wafer)sociated with large and frequent data transfers between

bonding technology and CoW (Chip on Wafer) bonding

memory and processors has become a major issue. As atechnology by low-temperature hybrid bonding of Cu-

technology to solve such problems, we are focusing on

Cu.

direct bonding 3D stacking technology that forms direct

This year is the second year of the project, and we arebonds at the chip level or wafer level, shortens the distancefocusing on introducing and starting-up of major equip-of data movement, and improves energy efficiency.

ment and developing elemental technologies. The projectIn the NEDO project “Post 5G information communi-

is off to a good start and is progressing largely according tocation system infrastructure strengthening research andplan. We are accelerating research and development todevelopment project / development of advanced semicon-

achieve the target value of the intermediate gate scheduled

ductor manufacturing technology (subsidy)” adopted infor December 2023.

2021, The Research Association for Advanced Systems

2-2

C

CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC

and CoW)”. This project aims to develop and implement

CCCCCCCCC

In computing technologies such as AI, which require112.3 P latform Design Research Division (VDEC Function) FY 2022 Report
and FY 2023 plan
2.3.1

2-3
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CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC
12

Overview of Platform Design Research Di-

sions to improve the convenience of participation. In ad-visiondition, in view of the current situation where the tool-

Since its establishment in 1996, the VLSI Design andchains of various companies are becoming more complex

Education Center (VDEC) at the University of Tokyo has

and it is difficult to fully use the introduced tools, lectures

been developing projects that contribute to integrated cir-on the tool-chains recommended by each tool vendor

cuit design education at universities and technical colleges

were also held in conjunction with the individual toolin Japan, based on the three major roles: ”spreading theseminars. From the end of FY2019, we received permis-

latest information on VLSI design and education,” ”pro-sion from each EDA vendor to use EDA tools from home,viding licenses of CAD tools,” and ”supporting on VLSI

to avoid delay&slowdown in integrated circuit design re-chip fabrications for academic use.” On October 1, 2019,search and education in Japan.

VDEC has been re-organized into Systems Design Lab(d.lab), Graduate School of Engineering, the University ofTokyo as part of an organizational restructuring aimed at

2.3.2

Status of Education at Platform Design Research Division

strengthening integrated circuit related activities in the

The LSI Design Flow Seminar is designed to educate

University of Tokyo’s semiconductor integrated circuit-re-the basic concepts of LSI design and to provide hands-on

lated activities. The Platform Design Research Division ofexperience of practical design examples using multiple

d.lab continues to carry out the functions of the VDEC

CAD tools. For this purpose, VDEC has been organizing

and continues “VDEC activities” seamlessly. Here, theLSI design education seminars as well as “Refresh Semi-

outline of “VDEC activities” of the FY2022 is reportednar” for re-education programs for engineers. In FY2022,

below.

we have canceled “Refresh Seminar.”

The missions of VDEC are for advancement of re-

In addition to these seminars, VDEC holds the “VDEC

searches and education on LSI design in public and pri-

Designers’ Forum” once a year, mainly for young facultyvate universities and colleges in Japan and send many dis-members and students. This is a workshop-style meeting,tinguished VLSI designers into industry. After 27 years of

where participants bring their design cases and exchange

VDEC establishment, educations on CAD software, LSI

their successes and failures, in addition to invited lecturesdesign and design flow in universities have been well es-

from companies and universities. In FY2022, the VDEC

tablished. On the other hand, advancement on nano-me-

Designer Forum had been held in hybrid format at

ter CMOS technologies forces design flow and CAD soft-

Yupopo Akita Art Village. Since FY2011, the “IEEE SSCS

ware complicated. We have been continuing CAD tool

Japan Chapter VDEC Design Award” has been presented

seminar by the lecturers from EDA vendors for twice a

as an award for VDEC activities. The final judging andyear. We hold the seminar in VDEC and provide distanceawarding of the “IEEE SSCS Japan Chapter VDEC De-

learning through video streaming. We expect spread of thesign Award” has been held at VDEC Designers’ Forum

up-to-date LSI design methodology by using CAD tools.

since 2011, and in 2022, the IEEE SSCS Japan Chapter

In order to make it more convenient for the partici-

VDEC Design Award will be presented to Mr. T. Shimada

pants, the seminars have been held only in Tokyo sinceof University of Tokyo. Four VDEC Design Award Excel-

2009, and at the same time, the seminars have beenlence Awards, (Mr. T. Shimada(University of Tokyo), Mr.

broadcasted to individual participating lab. The VDEC

FU XI(Tokyo Institute of Technology), Mr. L. Zheng(To-expects that the latest CAD use-case will be shared among

kyo Institute of Technology), and Mr. R. Okada(Nara In-labs through the seminar organized by VDEC, and will be

stitute of Science and Technology)), and three VDEC

a trigger to spread the technology nationwide. In FY2022,

Design Award Encouragement Prizes (Mr. Y. Watanabe

all seminars will be conducted online. Some items were

(Tohoku University), Mr. M. Osada (University of To-

conducted in the form of on-demand plus live Q&A ses-kyo), and Mr. S. Yamaguchi(Kyoto University)), and one

VDEC Design Award Commendation Prizes for Idea

/ R&D Item 2: Development of Common Platform Tech-Contest (Mr. K. Mii(Osaka University)).

nology for Accelerating AI Chip Development” sincenars and forums has enabled students to learn the basics oftion and design environment for venture companies and

LSI design, they still face various difficulties in actual LSI

small and medium-sized enterprises(SMEs) in Japan, anddesign situations. For beginners, setting up the CAD soft-

are working as an “AI chip design center(AIDC)”. In thisware is the biggest problem. Even after setting up the soft-

activity, in addition to the introduction of EDA tool li-ware, they are often baffled by the “difficult error messag-

censes that allow venture companies and small and medi-es” issued by the CAD software. VDEC users can registerum-sized companies to prototype up to engineering sam-for the “CAD mail group” and the “Prototyping Technol-

ples, we have introduced IP for 40nm, 28nm, and 12nm,

ogy User Group” on the VDEC website, where they can

and are also providing a large-scale, high-speed design andpost their questions and ask for help. The registered users

verification environment using a hardware emulator,of the mail groups are not obligated to respond, but inwhich was introduced with a subsidy from the Ministry of

most cases they can get help from experienced users with-

Economy, Trade and Industry at the start of this project.

in a few hours or days. We hope that you will take advan-

In FY2020, we have designed a SoC platform with NoC,

tage of this system to help solve your problems.

PCIe, DDR4, etc., and multiple functional IP cores, andtaped out the platform as a SoC with multiple AI IP cores

2.3.3

Publications related to Platform Design Re-

designed by multiple users, and after almost 1-year delay,

search Division

we have received assembled chip in the beginning of Jan.

Figure 2.3.1 shows the use of the VDEC facility in the2022, and after one week we could evaluate most of SoC

published literature related to VDEC. It can be confirmedfunctionalities and by the end of March 2022, almost allthat CAD software is widely used in writing papers. Sinceof IPs got fully verified. We have also designed and taped

CAD software is often used not only in chip design but

out with 4 AI IP cores in 12nm in June 2022, and all thealso in the preparation stage of chip prototyping, its con-

IP cores have been successfully demonstrated by the end

tribution as a tool to demonstrate the basic idea of theof March 2023. In order to further strengthen this activi-

2-3

C

CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC

2018. In this project, we have established an EDA utiliza-

CCCCCCCCC

Although the educational system through such semi-

research is also significant.
2.3.4

Report on AI Chip Design Center

VDEC and the AIST have been jointly commissioned
by NEDO to develop a common platform technology foraccelerating AI chip development under the “Innovation
Promotion Project for Accelerating AI Chip Development

Fig. 2.3.1 Trends of number of papers through VDEC activities.

Fig. 2.3.2

Number of papers related to VDEC facilities.

13

ty, we are accelerating our research by establishing thetion, we continue trial of several CAD tools, such as lay-

“AIST-The University of Tokyo AI Chip Design Open In-

out platform, Lavis by TOOL. Design debugging plat-

novation Laboratory” (AIDL) in the Takeda Building, As-form from SpringSoft has merged into Cadence tools andano Campus, The University of Tokyo on September 1,

will be continued.

2019.
【Chip fabrication services】

2-3
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CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC
14

2.3.5

Plan for FY 2023 “VDEC Activities” of Platform Design Research Division

In FY2023, we will continue the VDEC Activities foracademics as before.
【Design related information dispatching/Seminar】

We will continue chip fabrication services for 0.18µm
CMOS by Rohm, 0.8µm CMOS by On-semiconductor-Sanyo, and IHP SiGeBiCMOS 0.18um as the regularservices.
In addition to the above. We will continue to develop

We will continue holding the following seminars: (1)an “AIDC” activities, in collaboration with AIST. We will

CAD tools seminars which have been continued since

introduce a logic emulator for large-scale AI digital chip

1997, (2) “Refresh seminar” since 1998, (3) “Designer’design verification, and maintain and operate EDA licens-

Forum” since 1997. We will also continue seminars for

es for industrial applications. The main objective of this

LSI tester usage at VDEC and sub-centers, workshops on

project is to provide small and medium-sized venture

LSI testing technologies initiated by D2T.

companies with a development environment for AI chip
design, evaluation, and verification in order to accelerate【CAD tool support】

the development of AI chips, but we also plan to improve

We will continue Cadence tools, Synopsys tools andthe environment for use by universities in order to pro-

Mentor tools as the main stream design tools. We will

mote university-originated companies in the field ofcontinue analog ADS/EMPro/GoldenGate by Agilent,AI-related integrated circuits.

C-based design environment, BachC by Sharp. In addi-

Table 2.3.1

Chip fabrication schedule【CMOS 1.2μm 2P2M】On-Semiconductor(Former Motorola Japan)
2023#12023#2Chip application deadline
2023/7/3
2023/1/9

Design deadline
2023/9/25
2023/3/25

Chip delivery
2023/12/18
2023/6/24

Design deadline
2023/6/26
2023/9/4
2023/10/23
2024/2/26

Chip delivery
2023/10/13
2023/12/16
2024/2/9
2024/6/7【CMOS 0.18μm 1P5M(+MiM)】Rohm
2-3
CCCCCCCCCC

CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC

2023 #1
2023 #2
2023 #3
2023 #4

Chip application deadline
2023/4/3
2023/6/12
2023/7/31
2023/12/4152-4
CCCCCCCCC
C

2.4

Platform Device Research Division

2.4.1

Missionand (3) research capability to develop new technologies

CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC

D.lab platform device research division aims at provid-

required for new devices. In Japan, these three elements

ing every researcher with three essential elements for re-had been prepared and kept in an individual researchsearch on new devices. The division is with around 30

group until the end of 20

staffs, powered by Professor Yoshio Mita, the playing divi-technology trends towards advanced fabrication over larg-sion director who himself actively performs experiments

er-scale wafers, it has become almost impossible for a re-in the Cleanroom as a leading researcher, and operated insearch group to purchase and maintain the cutting-edge

collaboration with related departments (such as Institutefabrication machine line, in the 21 st century. Originally,of Engineering Innovation, Electrical Engineering and In-

it was impossible for every research group in universities,

formation Systems, and Mechanical Engineering) incompanies, research institutes, and NPOs, to exclusively

terms of human and budget resources. Especially in the“own” such large-scale facility and necessary budget byyear 2022, two new institutes was born on the basis of ourthemselves; If researchers wish to “cooperate” with theworld-class activity. The objective is to visualize re-other researchers in a platform, which is equally open to

search-oriented activities. To do that, a new center “Nano-

everybody, they can “effectively own” the most advancedstsystem Integration Center” was established on 1th

century. However, due to the

April“open platform”, and thereby the cutting-edge research

2022, in order to assemble cutting-edge researchers of theactivities can be held anywhere in Japan. This is the prin-

Faculty of Engineering. Professor Mita is leading the de-ciple of d.lab’s open device platform, which is in fact avice research and development division, and aims at rais-

lateral expansion of “shared economy model in VLSI de-ing research activities including international coopera-

sign and fabrication” to micro-nano fabrication and meas-

tions. The second is endowed division for “Nanosystemurement research field, originally established by VDEC

Integration Technology Innovation”. The purpose is “ac-for Japan in 1996.

cumulation”, “maturation”, and “generation” of technolo-

Towards that end, d.lab Platform Device Research Di-

gies to open new research domains, by taking Takeda SCR

vision takes full advantages of spaces (of its own and ofas an assembling point.

open rental) in Takeda Sentanchi Building. The building

Research in emerging fields of semiconductor elec-

was inaugurated in December 2003, thanks to the enor-

tronics devices (such as integrated circuits), sensors andmous donation in 2001 from Mr. Ikuo Takeda (founder

microsystems requires three essential elements: (1) fabri-of Advantest) to the faculty of engineering (Dean was Pro-

cation machines with stupendous amount of budget, (2)fessor Hiroshi Komiyama) as well as VDEC (director was

rich accumulation of fabrication technology knowledges,

Professor Kunihiro Asada). In the building, a 600m

2

建物
用地

寄付

超純水

購入

２００３
２００１

大型装置

購入

大型装置

寄付

２００４
２００５
2006 MITA,
YoshioFig.1

16

Development of Takeda Sentanchi Supercleanroom

11.

Cleaning, annealing!-Miller
CFS-4ES
SIH-450

2. Material deposition

RTA HP2-9
Inertgas Oven

EB-380Evap.(x2)Oxidation

SCFDElectroplating(Au/Cu/Ni)

F5112 EB
F7000S＋ EB
Beamer＋Tracer
DWL66+ 405nm

3. Lithography

Fig.2

Samco FA-1
Idonus VaporHF
Sand blast

7476D wedgebond
7200C diebonder

Elite300 prober
Electrical measurements
Shield room

4700E autobond
Lambda2 flipchip

RegulusSU8230 SEM
TM3030 SEM+EDX
JSM-6610LV SEM+EDX+Analyzer
Crossection Polisher / PECS /Carbon Coater
Phi680 AES
L-traceII AFM
Dektak, Tohospec,
OLS5000 Confocal
VH-6000 Digital Microscope
Microscopes
VR-120S resistivity

X2. Package / Jigs
LPKF Protolaser U4/ProtoMat S62
60W CO2 laser cutter Universal VLS4.60
1kW Fiber Laser cutter HGCF0606
NC Roland MDX-40
Metal NC Kitmill NC Micro MC-1
3D Printer Afinia H+ / Projet MJP5500X
Eximer ablator Hamamatsu

List of equipment under d.lab Platform Device Research Division-square supercleanroom including “official ISO3 (a.k.a.

tional project, or simply “Takeda Sentanchi Cleanroom”

federal class 1. Once measured as ISO1)” area (Fig.1).

(in short, Takeda CR). The platform is widely open to

The cleanroom and affiliated experimental rooms arethose who share the “value of cooperation”. The most im-

equipped with cutting-edge nanofabrication and meas-

portant understanding for every user is the platform musturement machines, total valued over 4.3 billion yens

not be considered as a simple outsourcing agent; being(22M euros, due to cheap JPY ratio). The users can open-

understood the value of “own help, mutual help, and pub-ly use such nice machines really inexpensively.

lic help”, the participant can drastically minimize costs

Over 100 apparatuses are openly accessible (Fig.2), in-(personnel, budget, and time), which should have other-cluding, “world’s fastest” large-area direct electron beamwise been totally covered by each researcher, and can di-(EB) writing machine Advantest F5112+VD01, which

rectly jump into advanced research. Key Performance In-

has been donated according to the wise decision of Mr

dicators of such benefits are as follows: over 8.3 billion

Ooura, a chairman of Advantest, fine EB writer Advantest

yens for installation cost of building and equipment, over

F7000S-VD02 and Silicon Deep Reactive Ion Etching

350 million yens for yearly operating cost, and reduction

machine SPTS MUC-21 ASE-Pegasus, both purchasedof over 20 years’ leading time to acquire know-hows in

by Japanese government’s supplemental budget (known asadvanced fabrications. These benefits have attracted many

Abenomics, the first arrow), and the scanning electron

research groups. Since ten years, the number of research

microscope (SEM) Hitachi Regulus SU8230 that pro-groups who sent us the letter of consensus exceeded 550.

vides highest-class resolution among those obtainable byOver 1062 members are yearly subscribed (including re-research laboratory. The machines can cover most of the

newal and new subscription).

research steps in nanotechnology, which are cleaning, film

Operation principle is also “own help, public help, anddeposition, lithography, etching, packaging and charac-mutual help”. Budgetwise, each term of the principle cor-terization. Not all apparatuses are yet installed in Takeda

responds to: (1) User’s payment to participate budget ac-

Building, however due to nationwide platform network,

quisition (charged according to the officially-approved

researchers can access in another equivalent nanofabrica-d.lab’s internal rule), and (2) national budget allocated totion platform center(s).

d.lab platform research division, MEXT Nanotechnology

2-4C

CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC

MSA-500
8” prober

6. Characterization

ZEP auto developer
Mask auto dev.
Spray coater
Automatic Liftoff
V400ACE FIB
Xvision200TB FIB

X1. In-line test

CCCCCCCCC

DAD3460 diamond
DFL7340 stealthPM5 4”CMP

Parylene

MA-6 PEM-800
436/405/365nm
EVG101

MUC-21 Pegasus CF-S ICP
NLD-5700Si
NE-550 ICP
Samco 10NR
CE-300I ICPSamco XeF2

4. Etching
5. Dicing and wiring

UV1
AQ-50

Clean Drafts
EVG301

Platform project, and (3) major laboratories (who rent
2.4.2 “Takeda Sentanchi Supercleanroom” cooperation platform

space in Takeda Building for their research work) as well
as research projects with d.lab operation laboratories (suchThe platform is called “Nanotechnology Platform UTo-

as Mita Lab). Of course, each budget category is right-

kyo Nanofabrication site” according to the MEXT’s na-

eously dispensed in perfectly following its own rule de-

17

2-4
CCCCCCCCC
C

fined by corresponding laws and ordinances. The yearlyhighest quality”. Such a flexible scheme is unique in theoperation cost of 350 million yens are composed of equip-

world. Yearly one multi-chip fabrication is performed

ment installation, electricity and water fees, maintenance,(pre-fixed participants upon request), including collabora-

and personnel. Recently electricity cost is drastically in-tive research works with industries.

creasing. National Universities have acquired budget flex-[2] Y. Mita et al., Japanese Journal of Applied Physics, 56,

ibility since the date of private agency statuses. It helps ap. 06GA03, 2017 (2017) DOI: 10.7567/JJAP.56.06GA03

lot to ensure staff employment as well as small to middle
2.4.3

sized equipment acquisition.
Platform Device Research Division staffs acquire im-

Research Division

CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC

plicit information for future fabrication technologies, due【Prize】 The MEXT Nanotechnology Platform Pro-to daily help to massively parallel research projects. The

ject gives prizes for good usage of platform. Every year,

team develops technologies with high demand and uni-several projects are selected by specialists’ award commit-

versality and make them accessible by publishing papers.

tee, among solicited candidates selected from over 3000
research project reports. Among the projects that PDRD

Moreover, taking full advantage that PDRD is a divi-sthave solicited, we won again and again the 1 prize “Bestsion of d.lab, the team has been developed for over 10

use award” (Fig.3). Note that our division has been award-

year, a reliable research scheme for integration of LSI anded consecutively for four years, including three last years

MEMS devices, known as “Integrated MEMS researchas the best use award. No equivalent research platformdomain”. As summarized in a peer-reviewed journal [1],exists in Japan. The awarded group are UTokyo Professor

through VDEC function of d.lab “LSI foundry”, a specif-

Hitoshi Tabata group as well as Gaianixx.

ic LSI circuit silicon wafers are fabricated through compa-【No infection case & no decrease in platform uses】Inny (such as Phenitec Semiconductor). Then the wafer isthe year 2022, we also continued strict but acceptable an-“post”-processed in an open nanofabrication platform in-ti-pandemic protocol. This year also, zero transfection hascluding Takeda Sentanchi Supercleanroom. The criticalbeen obtained, thereby accumulating the supporting dataadvantage of such scheme is that researchers can “easily”

of validity of our countermasure.

obtain silicon wafers with transistor circuits, which has【Post-Nanotech platform national project】The ma-

been really difficult for university cleanrooms to acquire

jor part of “public” help for cleanroom has been covered

reliability, and can fabricate by themselves specific MEMS

by MEXT Nanotechnology platform. Nanotechnologythat no foundry company can provide. Namely, research-platform project that finished at Reiwa 3rd (31/Mar/2022);

ers can produce “World’s first functionality” with “World’s

MEXT has started another national project, by officially

Fig.3

18

Activity Report 2022 of Platform Device

Group photo after award ceremony

has been highly appreciated by the evaluation committee

transformation (DX) in materials including MEMS de-

and was granted for 10-year project’s “hub” site. Attachedvices. The name of the new project is called “Advanced

to the national project, MEXT continuously grants us a

Research Infrastructure for Material research (ARIM) ”.

big supplemental budget for our proposal to enhance per-

Structurally speaking, material DX have adopted “researchformance of our cleanroom. Also, d.lab was awarded bydomain hub-and-spoke” system, in contrast with Nano-

MEXT’s “Next generation X-nics research site” and ma-plat’s “technology domain system” composed of character-chines have been installed accordingly. In total, we haveization, nanofabrication, and material syntheses.

identified that 4500 millions of yens is necessary to complete competitive Cleanroom; yielding 300M yens per

Center of Institute of Engineering Innovation and Infor-

year if we renew everything at every 15 years. The teammation Technology Center to form a strong hub team,will try his best to assemble and share “machine, technol-

under presidency of Professor Yuichi Ikuhara. The teamogy, and people”.

C

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d.lab PDRD has been merged with Nano Engineering

2-4
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stating “use heritage of nanotech platform”, for digital

19

2.5

Activity Report of ADVANTEST D2T Research Department

2.5.1

Introduction of ADVANTEST D2T Research

testing is one of the most practical research topics in the

Department

industry. On the basis of these activities, our final goal is
to become a center of excellence of VLSI testing in Japan.

2-5
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CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC
202.5.1.1 Aim of establishing ADVANTEST D2T Depart-D2T research division has spent a total of 12 years toment (former D2T research division)develop the first (Oct. 2007 – Sep. 2010), second (Oct.

ADVANTEST D2T research division was established2010 – Sep. 2013), third (Oct. 2013 – Sep. 2016), andin VDEC in October 2007. As the name suggests, it is fi-

fourth (Oct. 2016 – Sep. 2019) phases. D2T activity re-nancially supported by ADVANTEST Corporation.

port of 2022 presents the last financial year, i.e., Oct.

The aim of establishing ADVANTEST D2T research2021 – Sep. 2022, of the fifth phase. Systems Design

division was to promote the research and education envi-

Center, School of Engineering, the University of Tokyo

ronment with regard to VLSI testing in all universities andhas been established in Oct. 2019, and Advantest D2Tcolleges in Japan. “D2T” signifies that we consider notresearch department is within the center. D2T research

only design but also testing. Through our activities, we

department primarily focuses on D2T research activities

hope to provide expertise in design and testing for theand education. The sixth project phase (Oct. 2022 on-industry. In addition, we are exchanging researchers withwards) of D2T project was commenced by courtesy of

those of other universities and research institutes both in

ADVANTEST Corporation. The details pertaining to theJapan and overseas. Moreover, D2T research division is

activities of our group are presented in the following sec-

suitable for collaborations with the industry because VLSI

tions.

2.5.1.2 Members of ADVANTEST D2T Division
Project Professor

Makoto Ikeda

2.5.2

Report of the 17th D2T Symposium

The 17th D2T Symposium was held on September 15,

Postdoctoral research fellow Zolboo Byambadorj

2022, hybrid. This year, we will invite lecturers overseas,

Project Lecturer

Assistant Professor, Zhongrui Wang from Hong Kong

Akio Higo

Researcher	
Koji Asami (Advantest
Laboratories Ltd.)
Researcher	
Masahiro Ishida (Ad-

University, Reika Ichihara from Institute of Memory
Technology R&D, Kioxia Corporation, Associate Professor Shintaro Hisatake from Gifu University, Takahiro Nakamura, Ph.D. from AIO Core Co., Ltd., Dr. Motoaki

Researcher

Takahiro Yamaguchi

Hara, Senior researcher from National Institute of Infor-

Assistant Clerk

Makiko Okazaki

mation and Communications Technology (NICT), Associate Professor Katsuhiro Tomioka from Hokkaido UniWe sincerely appreciate each participant for their contributions to the symposium. We look forward to greater
participation again at the 18th D2T symposium on Sep. 8
Fri. 2023.

17th D2T Symposium Program ONLINE

September 15, 2022

10:00 Opening Remarks

Makoto Ikeda (d.lab, School of Engineering, the University of Tokyo)
Yoshiaki Yoshida (President & CEO, ADVANTEST CORPORATION)
10:10 Session 1 (Chairperson: Tetsuya Iizuka, d.lab, the University of Tokyo)
Measurements in millimeter-wave and THz wave band based on photonics
Shintaro Hisatake, Associate Professor (Gifu University)
High-density integrated optical transceiver based on silicon photonics technology”
Takahiro Nakamura, Ph.D. (AIO Core Co., Ltd.)
11:40 Lunch

C

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versity, for their distinguished research topics.

2-5
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vantest Corporation)

13:10 Session 2 (Chairperson: Atsutake Kosuge, d.lab, the University of Tokyo)

Reliability study of ferroelectric HfO2 memory using advanced analytical techniques
Reika Ichihara (Institute of Memory Technology R&D, Kioxia Corporation)
Memristor-based echo state networks
Zhongrui Wang, Assistant Professor (Department of Electrical and Electronic Engineering at the University of Hong Kong)
15min break
14:40 Session 3 (Chairperson: Yoshio Mita, d.lab, the University of Tokyo)
14:55 Vertical III-V Nanowire Transistors and Prospects
Katsuhiro Tomioka, Associate Professor (Hokkaido University)
CLIFS: Chip Level Integrated Frequency Standard, How do we approach the cliff of CLIFS?
Motoaki Hara, Senior Researcher (National Institute of Information and Communications Technology (NICT))
Session 4
Recent D2T research department progress
16:15 Akio Higo, Lecturer (d.lab, the University of Tokyo)
16:30 Closing Remarks

Tadahiro Kuroda (Director, d.lab, School of Engineering, the University of Tokyo)

21

2.5.3

Research Activity Reports of the ADVANT-

High-Speed and High-Accuracy Multi-Pin Timing

EST D2T Research Department

CAL for ATE
Masahiro Ishida, Hidaka Otsuka, Tetsuya Iizuka,

High-Resolution

Analog-to-Digital

Converter

Zule Xe, Akio Higo, Masahiro Fujita, Makoto Ikeda

Based on Stochastic Comparators
Takahiro J. Yamaguchi, Akio Higo, Tetsuya Iizuka,
2-5
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Automatic test equipment (ATE) for Semiconductors

CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC

Makoto Ikeda

has thousands to tens of thousands of signal input andThis project aimed to explore new stochastic

output channels. It requires timing calibration (CAL) to

analog-to-digital converter (ADC) architectures. To re-correspond the test signal output’s timing to the device

duce randomness and increase accuracy, an approach forunder the test (DUT) and the comparison timing of therobustly detecting level-crossing time via stochastic medi-

signals output from the DUT. This research focuses on aan is investigated.

high-speed and high-accuracy multi-pin timing CAL

The validity and appropriateness of the root mean

method applicable to ATE. This year, we evaluated a pro-square error as a performance measure was verified. Our

totype TEG circuit fabricated in TSMC 65nm CMOS

proposed theory which was developed for “comparators

process last year. We confirmed that the difference in char-with random fluctuations caused by process variations”

acteristics between the reference timing generator circuits

was verified by Monte Carlo experiments.

for comparator CAL and the difference between the timing measurement circuits for driver CAL does not change

5G multi-channel/millimeter-wave signal meas-

significantly depending on the operating environment

urement(temperature and supply voltage). We found that the tar-

Koji Asami, Zolboo Byambadorj, Ryogo Koike,get accuracy of the timing CAL was able to be at one ps.

Sheng Guo, Nguyen Ngoc Mai-Khanh, Akio Higo,

The research theme on High-Speed and High-accuracy

Tetsuya Iizuka, Masahiro Fujita, Takashi Matsumoto,Multi-Pin Timing CAL for ATE was completed by sum-

Makoto Ikeda

marizing issues such as crosstalk, signal extraction, andWe study and develop fundamental research to measure

CAL for CAL circuits when circuits for the timing CAL of

the millimeter-wave signals in an over-the-air (OTA) envi-

many channels are implemented on one chip.

ronment. A 4-channel planar antenna array has been developed for the near-field measurements of the millime-

2.5.4

Publication

ter-wave antenna. Metasurface was fabricated to reducethe coupling between antennas. Antenna probes were fab-

Journalricated, and experiments are underway to confirm the[1]

Zolboo Byambadorj, Koji Asami, Takahiro J.

characteristics and measure the antennas. In addition, to

Yamaguchi, Akio Higo, Masahiro Fujita andconfirm the measurement algorithm, a commercially

Tetsuya Iizuka, “High-Precision Sub-Nyquist

available horn antenna was used as a probe to measureSampling System Based on Modulated Wide-antennas for 5G. We confirmed that the far field could beband Converter for Communication Device

estimated accurately by correcting the influence of the

Testing,” IEEE Transactions on Circuits andprobe from the measured near field.

Systems-I: Regular Papers, vol. 69, no. 1, pp.
378 - 388, Jan. 2022

22

Chapter 3

Research in d.lab

Kuroda and Kosuge Lab(http://www.kuroda.t.u-tokyo.ac.jp/index.html)

TCI: ThruChip Interface

tenna and wireless circuits on a tiny chip less than 1 mm
square and combine it with an intelligent reader to pursue
an extremely low-cost IoE (Internet of Everything) system. This year, we developed a new collision avoidance
function that deterministically avoids collisions based on

M. Okada, Wai-Yeung Yip, K. Shiba, T. Omori

received signals by utilizing adiabatic circuits. We devel-

TCI is a 3D integration technology that employs in-

oped a low-power RFID tag circuit using TSMC 0.18m

ductive coupling between coils created with on chip metal

CMOS process by using our proposed the adiabatic logic

line patterns for data communication across stacked chips.

circuit. We have also developed a new bonding-less

It realizes the same or better performance as TSV (Throughmounting technology in which the coil mounted on the

Silicon Via) but at a lower cost. This year, we presented

RFID tag is coupled to the coil on the PCB. A test chip

research papers on TCI-based 3D SRAM stacking tech-

was developed and evaluated using TSMC 0.18um

nologies including (a) circuit technology for low-power

CMOS process, and papers were presented at SSC-L’22.

3
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T. Kuroda, M. Hamada, A. Kosuge, T. Shidei,Ccomputation, (b) area efficient coil-design, and (c) computing architecture and AI processing algorithms to use

Wired-logic AI Processor

3D stacked SRAMs efficiently. We presented our achieve-

T. Kuroda, M. Hamada, A. Kosuge, K. Shiba,

ments at HotChips’22, A-SSCC’22.

Yao-Chung Hsu, R. Sumikawa, F. Hondo, Zhan Zhijie
We are studying non-von Neumann AI processors fo-

TLC: Transmission Line Couplercusing on wired-logic to reduce power consumption. The

T. Kuroda, M. Hamada, A. Kosuge, Y. Hayashi,area efficiency is a bottleneck of the wired-logic processor

Ximing Wangand it is significantly degraded due to the need to imple-

TLC is a data communication technique between cir-ment a huge number of elements on a chip. Therefore, we

cuit boards by utilizing electromagnetic coupling between

have developed two new technologies: (1) a technology totransmission lines on them. It solves the issues in conven-

optimize the network by removing unnecessary neurons

tional connectors such as wearing, reliability against vibra-

and synapses, called pruning in the human brain, and (2)tion, and impedance mismatch, realizing wireless connec-

a nonlinear neural network technology that incorporates

tors. This year, through joint research with a company, we

the property of human neurons to use a wide variety of

conducted research and development of compact andnonlinear functions in the right places to increase the rep-

high-density TLC mounting technology for connecting

resentation capability of the network in order to prune

packaged boards and PCBs, and research on fully sealed

more drastically than before and save the number of ele-

non-contact connector technology for simultaneous com-ments. In addition, we are developing convolutional

munication of non-contact power supply and TLC in

wired-logic architecture circuits that reuse circuits in ac-

close proximity to each other. GND shielding technology

cordance with the processing of convolutional algorithms.

is studied to prevent mutual interference between wireless

The FPGA implementation was accepted to HotChips’22.

power transmission and contactless communication. We

In addition, SRAM-based in-memory computing tech-presented our achievements at ICECES’22.

niques are researched. The achievements are accepted to
NEWCAS, TCAS-1, ASSCC and SSC-L.

RFID Tag Chip Design
T. Kuroda, M. Hamada, A. Kosuge, R. Miura,
S. Shibata
We are developing a wireless tag that integrates an an-

23

3
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C

mmWave Imaging Radar based Object Recogni-

tion-in-Memory (CiM) to solve the knapsack problem,tion

one of the combinatorial optimization problems, is pro-T. Kuroda, M. Hamada, A. Kosuge, Wai-Yeung Yip

posed. Proposed log-encoding simulated annealing (SA)In harsh environments (bad weather, night, dirt on

on ReRAM CiM reduces the array area of ReRAM CiM

cameras), conventional human/object detectors utilizingby 97.6%. To co-design ReRAM device and SA, error in-conventional cameras have low accuracy. Since millimeterjection is applied. As a result, the asymmetric ReRAM

wave radar technology has high environmental resistance,

error increases the acceptable bit-error rate (BER) by 10

the radar is promising solution for the harsh environment.

times and the acceptable bit precision to 5-bit.

However, unlike image recognition, it has a problem in
detection algorithm due to low-resolution blur data. In

In-sensor Computing

this research, we are developing a new deep learning AI

Ken Takeuchi and Chihiro Matsui

technology that handles millimeter wave images based on

We have proposes an integration of event-based visiona new semi-automatic training data generation technolo-

sensor (EVS) and processor (e.g., computation-in-memo-

gy and develop a highly accurate AI technology for hu-

ry, CiM) for low-power processing. By using newly definedman/object identification. This year, we mainly studied

characterization method of frame and EVS camera, an

the characteristics of millimeter-wave radar data and theevent-driven SRAM CiM with partitioned word-line

network structure that matches them and developed a(WL) activation method is proposed for 3D-integration ofcamera-radar cooperative semi-automatic learning data

EVS. The multiple-bit synaptic weights are stored in a set

generation technique and developed a millimeter-wave-6of SRAMs. The proposed CiM for EVS achieves 10 times

radar AI system that can detect the type and location of six

energy efficiency compared with CiM for frame camera.

types of objects with the same accuracy as image recognition. The paper is accepted to IEEE Trans. Instrumentation and Measurement.

Takeuchi Laboratory(https://co-design.t.u-tokyo.ac.jp/)

Computation in memory (CiM)

Nakamura Laboratory(http://www.hal.ipc.i.u-tokyo.ac.jp/)

IoT Network Security
Hiroshi Nakamura
Zigbee is a short-range wireless communication protocol and needs low power and low bandwidth at the sacri-

Ken Takeuchi and Chihiro Matsui

fice of its short transfer range and slow speed. Due to thisWe have developed a comprehensive Computa-

nature, it is widely used in small inexpensive sensors andtion-in-Memory (CiM) simulation platform. The simula-

IoTs that run on batteries, As Zigbee adopts indirect com-tion platform has capability to emulate multi-level cellmunication to achieve low power consumption, it incurs(MLC) and various memory device non-idealities such asa vulnerability to LDoS attacks. To address this problem,

uniform/non-uniform conductance variation and shift.

we proposed a method to prevent LDoS attacks and iden-

The simulation results address that the conductance shift

tify attackers while satisfying the limitations of IoT devic-

has much more critical impact than conductance varia-

es, which require fewer resources for processing and con-tion on inference accuracy in CiM.

sume less power. In addition, we studied a hardware
mechanism to realize this method and clarified its effec-

Simulated Annealing
Ken Takeuchi, Chihiro Matsui and Naoko Misawa
Memory error tolerant ReRAM-based Computa-

24

tiveness.

Coarse-Grain Reconfigurable Architecture
Takuya Kojima, Hiroshi Nakamura
Coarse-grained reconfigurable architectures (CGRAs)

Ikeda Laboratory(http://www.mos.t.u-tokyo.ac.jp)

Design optimization of high-performance cryp-of computing including embedded systems and high-per-tographyformance computing due to its benefit of high-energy ef-

M. Ikeda, A. Opasatian, K. Masada, M. Fukuda,

ficiency and programmability. CGRA consists of an array

and Y. Takeshimaof numerous processing element and its efficiency heavily

Pairing-based cryptography (PBC) is one of the mostdepends on the quality of compiler which maps applica-

important fundamentals for many novel encryption

tions onto these PEs. So far, we have proposed a novel al-

schemes. PBC normally involves extensive computations,gorithm called GenMap (A Genetic Algorithmic Ap-

so the high-performance cryptographic accelerator would

proach for Optimizing Spatial Mapping), which is agreatly benefit many applications. To meet those needs,

mappaing framework based on a genetic algorithm. We

we have designed high-performance pairing accelerators

have extended GenMap to deal with not only spatial but

targeting different curves (asymmetric pairing: BLS12-also temporal reconfiguration and confirmed its effective-

381, BLS24-315, BLS24-317, and BLS24-509/symmet-

ness. We have also shown that by incorporating approxi-

ric pairing: SS1024) and explore its use case in different

mate calculations, CGRA can achieve the required accura-

applications such as the Identity-based Encryption (IBE),

cy while saving area and power.

the Searchable Symmetric Encryption (SSE), and the At-

3
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are expected as a promising architecture for wide variety

Ctribute-based Encryption (ABE). The design is also exLightweight Runtime Environment of ROS2 nodes

tended for the hash-to-point accelerator as well. The auto-for Embedded Devices

matic schedule creation process is introduced to shorten

Hideki Takase, Hiroshi Nakamura

the design time, and the optimization of the modular

The Robot Operating System (ROS) and ROS2, themultiplier module is also investigated.

latest version of ROS, have attracted attention as a design
platform for distributed robot software development.

Implementation of fully homomorphic encryption

One of the drawbacks of ROS2 is that it is necessary to

M. Ikeda, T. Shimada, and Y. Zhao

employ high-performance and power-hunger devices

Fully homomorphic encryption (FHE) is a way to del-since it requires a Linux environment for operation. Thisegate the processing of your data, without giving a way

drawback prevents ROS2 from being applied to embed-

access to it. It can calculate ciphertexts without secret key.

ded devices because they must be quick in response andAlthough FHE is expected to be used in secure delegating

consumes less power. Thus, we have proposed a novel

computation, it is far from application due to the low

solution called mROS2, which is a lightweight runtime

speed of FHE. The goal of this research is to speed up theenvironment of ROS2 nodes. One of the advantages of

FHE schemes like TFHE and BGV by hardware imple-

mROS2 is that it provides efficient communication mech-mentation. The implementation on FPGA is 4 times fast-

anisms with less memory consumption. Currently, we are

er than CPU this year. Further improvement still remains

designing software architecture for this communicationin the next year. Beside hardware implementation, we also

flow. This work is expected to contribute to the power

pay attention to the optimization of FHE algorithm. Af-

saving and real-time performance enhancement of mobile

ter tons of trade-off, we increase the number of input

robot systems.

ports of homomorphic logic gates from 3 to 10. We also
optimize the parameter of FHE to maintain the runningtime, decryption failure rate and security level.

25

Implementation of Post-Quantum Cryptography

3
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C

rity and low cost. We suggested method to estimate theM. Ikeda, HQ. Bui, T. Shimada, and K. Kotani

security against solving DLP (discrete logarithm problem)

Post-quantum cryptography (PQC) is public-key cryp-

and ECDLP(elliptic curve discrete logarithm problem)

tography and digital signatures (DS) performed by a con-and hardware costs such as area, cycles, and latency of par-ventional computer resistant to classical and quantum

ing-based cryptography, using only characteristic as varia-

computer attacks. It aims to replace modern-day cryptog-

bles, and applied the method to BN, BLS12 and BLS24

raphy standards such as Diffie-Hellman, RSA, and elliptic

curves.

curve cryptography (ECC) which all can be cracked inpolynomial time with a sufficient quantum computer.
PQC algorithms that will be standardized include

Neural Networks and its Security
M. Ikeda, Z. Wang, Y. Miao, B. Amartuvshin

CRYSTALS-Kyber (lattice-based PKE/KEM), CRYS-

Spiking neural networks (SNNs), due to their potential

TALS-Dilithium (lattice-based DS), FALCON (lat-energy efficiency, are promising candidates for next-gener-

tice-based DS), and SPHINCS+ (hash-based DS). Poten-

ation neural networks and are also expected to be able totial algorithms to be standardized (as of 4th round of

integrate with neuromorphic sensors for efficient infor-

PQC standardization process) include BIKE (code-based

mation processing. However, currently hardware imple-

PKE/KEM), Classic McEliece (code-based PKE/KEM),

mentations of SNN face significant difficulties mainly due

HQC (code-based PKE/KEM), and SIKE (isogeny-based

to the additional membrane potentials introduced by

PKE/KEM).

spiking neuron. To this end, we propose a lossless com-

Note that NIST is planning to standardize additionalpression method for membrane potentials, which allows,

DSs with the first set of proposals submitted by 2023,

for the first time, the use of a reduced-precision fixed-

Jun. 1.

point format representation for membrane potentials in

In this study, we have implemented CRYSTALS-Kyber

deep SNNs, thus achieving the lowest resource footprintin 65nm ASIC, and SIKE and its basic operations by

and energy consumption of any FPGA-based SNN accel-

FPGA.

erators.
On the other hand, cloud computing has become a26

Security Measures of Crypto-engine

popular field in neural network due to its complex calcu-

M. Ikeda, K. Abe, and S. Kikuoka

lations. However, the data privacy remains a significant

Cryptographic implementations must be resistant toconcern in widely applying cloud computing. Fully ho-

side-channel attacks and their resistance assessments aremomorphic encryption (FHE) is a promising method forrequired. The resistance against side-channel attacks of a

privacy protection, but it suffers from the slow speed. To

256-bit ECDSA hardware was evaluated by performing

address this, we focused on improving the speed of FHE-

template attacks on scalar multiplication using measured

based neural network calculations in both software andcurrent consumption waveforms, and then the perfor-

hardware field. Firstly, we designed a fast algorithm for themance and the leakage success rate of implementations

inference in FHE-based recurrent neural network (RNN),

with some countermeasures that are considered to be ef-

which avoids the most time-consuming bootstrapping

fective are evaluated based on the results of logic synthesis

procedure and significantly improves the throughput.

and logic simulations. This enabled an evaluation of theMoreover, hardware designed for a fully residue numeraleffectiveness of each countermeasure and a quantitative

system (RNS) based FHE scheme can further accelerateleakage evaluation at the design stage. For hardware im-

the calculations. Compared to other hardware design, theplementations of elliptic curve pairings, it is important tohardware resource is highly reduced by avoiding the com-select the optimal curve that achieves both sufficient secu-

plicated big number calculation.

Security on Logic Circuits and Processors
M. Ikeda, Z. Ye, J. Xin, T. Matsumoto, F. Arakawa,and T. Kikkawa

ence spur, 175-fs integrated RMS jitter, and −240-dB
FOM with a 125-MHz reference clock.
Low-jitter and low-spur PLLs are highly demanded by
the emerging high-speed communication systems. Re-

to protect digital circuits from unauthorized access andcently, sampling/sub-sampling PLLs with high phase de-reverse engineering, tampering and counterfeiting. Add-

tection gain have shown their capability to simultaneously

ing key-dependent elements to the circuit or modifying

lower spur, jitter, and power consumption, resulting in athe circuit’s structure in a key-dependent manner achieves

low spur < −65dBc and an excellent jitter-power Fig-

this technology. The previously proposed logical locking

ure-of-Merit (FoM) < −258dB. However, to achieve sub-techniques have had drawbacks, such as high overhead or

100-fs RMS jitter, they typically require a huge reference

security flaws. To address these drawbacks, chaotic struc-buffer to provide a high-slew-rate clock with low PN, pe-tures controlled by attractors with a small area consump-nalizing PLL’s power efficiency. We proposed a refer-tion have been inserted into the circuit in this study. By

ence-sampling PLL with low-ripple double-sampling

adjusting the number of chaotic structures, a balance be-phase detector to lower the PD’s in-band phase noise

tween security and overhead can be achieved.

(PN) by 3dB without raising PLL’s input load and crystal

We also study integrating a post-quantum crypto-accel-

oscillator’s power consumption. With a 100-MHz input

erator to RISC-V open-source instruction set architec-

reference, the prototype in 65-nm CMOS achieves anture, to improve the public-key encryption performance

RMS jitter of 63fs with a spur level of −80dBc. The total

on open-source hardware.

power consumption is 3.1mW at 3.4GHz.

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Logical locking is a technique used in hardware security

C

Harmonic-Mixer (HM) -Based fractional-N PLLs are

Iizuka Laboratory(http://www.mos.t.u-tokyo.ac.jp/iizuka)

excellent solutions to achieve low noise fractional operation without relying on noise cancelling circuits that require heavy calibration. The HM is usually realized by

Phase-Locked Loop Circuit Techniques for Low

taking advantage of the frequency translation of a Sample-

Phase Noise

and-Hold (S/H) circuit. Accordingly, properly designed

Tetsuya Iizuka, Zunsong Yang, Masaru Osada,filters must be placed before and after the S/H to filter out

Ryoga Iwashita

unwanted spurs at the PLL output. However, the detailed

Ring voltage-controlled oscillator (VCO) is attractive

mechanism for the tone generation and the requirements

for a compact footprint, multiple phases, and no magnet-

for the filters were not made clear in the previous works,

ic coupling. However, for the low-jitter PLL higher than 5

and their designs were done in an unclear and/or ad-hoc

GHz, most previous works still resort to LC VCOs where

manner. Therefore, in this work, we provided 1) a qualita-

the inductors suffer from a large area and underlying mag-tive explanation of the generation mechanism of the HM

netic coupling. We proposed an inductorless cascaded

related tones and how the filter helps to suppress them, 2)

PLL with ultralow jitter that leverages the large perfor-some detailed analysis of the spur location and amplitude,

mance gap between low- and high-frequency ring oscilla-and 3) the requirements for the filters to appropriately

tors. A single-stage sample-and-hold subsampling phasesuppress the tones to a desired level. The results weredetector is proposed for the 1st stage, where the oscillator’sbacked by behavioral and schematic level simulation re-control voltage is updated only when the impulse sensitiv-

sults.

ity function is zero, enabling wider loop bandwidth, lower

Ring VCO based PLLs have many advantages overjitter, and lower spur. Fabricated in 65-nm CMOS, thetheir LC VCO based counterparts, making them an at-

prototype operating at 10GHz achieves −63-dBc refer-tractive solution for many area intensive or coupling sen-27

3
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C

sitive applications among others. At the same time, cali-thesizable SAR CADC that uses entirely standard cells,

bration free fractional-N PLLs are attractive circuits due

enabling automatic placement and routing (P/R) using ato their robust operation, ease of implementation, andcommercial digital implementation tool. Due to the lim-

improved locking time compared to PLLs that rely on

ited tape-out time, we opted to complete the P/R processcalibration heavy circuits. Naturally, ring VCO based cali-manually for this prototype. We also suggest a differential

bration-free fractional-N PLLs are a topic of great interest.

architecture for this design that utilizes an inverter-based

However, both ring VCO based PLLs and fractional-N

CDAC, which offers higher feasibility and a more exten-

PLLs are known for their large noise compared to theirsive input range. Leveraging our previous research on

LC VCO based or integer-N counterparts. Therefore, in

MOSFET-based gate-voltage-independent capacitors, we

this work, we propose a PLL architecture that combines

propose an inverter-based gate-voltage-independent ca-

the HM based PLL with a previously reported method

pacitor that can sample and hold the input voltage andthat uses a nested PLL as a phase-domain filter. As a result,generate the DAC voltage while mitigating its capacitancethis PLL simultaneously achieves a wide loop bandwidthvariation due to the input voltage by connecting theto suppress the ring VCO phase noise, and effective sup-source and drain of the p-MOSFET and n-MOSFET inpression of the quantization noise coming from fraction-

the inverter. Moreover, we demonstrate the principle ofal-N operation. The implemented design achieves an FoM

DAC voltage linearity compensation when using the ex-of -227.6dB at 3.1GHz using a 50MHz reference, which

tracted series-capacitor unit from the inverter as theis a state-of-the-art value among calibration-free ring

CDAC unit. To switch analog signals, we propose a ful-

VCO based fractional-N PLLs.

ly-inverter-based switch embedded in a dummy switch,

Based on the conventional second-order ΔΣ FDC(Frequency-to-Digital Converter)-PLL that can reduce phaseeliminating the need for any uncommon digital cell orprocess in the overall design.

noise with noise shaping, we proposed a higher-order

Stochastic resonance is a phenomenon where noise of a

MASH(Multi-stAge noise SHaping) 2-k FDC-PLL for acertain intensity contributes to system performance inwider loop bandwidth and lower phase noise. The MASH

nonlinear systems, and has been studied and applied in

2-1 FDC-PLL can be designed by using a SAR ADC forvarious fields. We have verified the effectiveness of apply-

the first stage, and using a ΔΣ ADC with FIAs(Floating

ing this phenomenon to a successive approximation regis-

Inverter Amplifiers) for the next stage. We designed theter analog-to-digital converter (SAR ADC), which re-proposed FDC-PLL in 65nm CMOS process and demon-quiresstrated that the proposed FDC-PLL achieves -102dBc/Hz

analog-to-digital conversion in a binary search. In thein-band noise and -230dB FoM with 26MHz reference

proposed circuit, additional comparisons are repeated af-

clock by post-layout simulation.

ter the normal SAR ADC operation to achieve higher res-multiplecomparisonswhen

performing

olution. In addition, by using the noise in the circuit for

28

High-Precision Analog-to-Digital Conversion Cir-

stochastic resonance, the power normally used for noise

cuits and its Design Automation Techniques

suppression is reduced to achieve low power consump-

Tetsuya Iizuka, Shuowei Li, Ryoya Shibata,tion. Optimal conditions for the number of the addition-

Haoming Zhang, Yo Kumano, Ritaro Takenaka

al comparisons and noise intensity were obtained throughAnalog circuits based on standard cells have numerous

the performance analysis and simulations, and the results

advantages, such as high reusability, high integration,

show that the power efficiency of the proposed circuit iscompatibility with automated design, and reliability,

higher than that of a normal SAR ADC.

making them highly promising for current and future re-Dynamic circuit is a one type of CMOS integrated cir-search. In this study, we propose a novel design for a syn-cuit. It’s faster than static CMOS circuit while it cannot

be used in standard cell design since it’s difficult to charac-

Design of Low-Noise Receiver for Deep-Spaceterize because of its complex timing. In this research, we

Probes
Tetsuya Iizuka, Takamichi Horikawa, Sota Kano

we use to characterize the dynamic circuit, then we define

As there has been an increasing demand for the minia-

several timing parameters for the dynamic cell based on

turized spacecrafts in recent years, it has become essential

this timing model. To get the values of the timing param-

to reduce the size and weight of the micro-wave tran-

eter, we did simulation of the circuit. And we used thesesponders. Although current transponders use off-the-shelfvalues to construct a liberty file for the cell. After that, weelectronic components to achieve downsizing, the combi-

execute the static timing analysis (STA) to verify it. To getnation of consumer products makes it difficult to guaran-a more accurate and convincing result, as a second part,tee long-term reliable operation during deep space explo-

we design a test structure to measure the required timing

ration. To achieve miniaturization and reliability at theparameters for dynamic circuit characterization. After thesame time, one promising solution is to integrate the en-chip is taped out, we will do the measurement and replacetire building blocks including the analog RF front-end as

the simulation result with measured result to constructwell as the digital signal processing on a single chip.

the liberty file for dynamic circuit.

3
CCCCCCCCC CCCCCCCCCCCCCCCCC

first proposed a timing model for dynamic circuit whichC

For deep space probes, receiver noise figure (NF) andFor high-precision and power-efficient ADC design, weradiation hardness are important specifications of the in-studied a fully dynamic discrete-time Delta-Sigma ADC

tegrated receiver front-end. To avoid the very small signal

using a Floating Inverter Amplifier (FIA). We have evalu-

from the earth being buried in the noise floor and unableated Correlated level shifting (CLS) and sampling noise

to be demodulated, it is necessary to improve receiver sen-cancellation techniques, which have been continued fromsitivity and dynamic range by minimizing the noise added

the previous year, by actual measurements, and are inves-in the circuits.

tigating new techniques to further improve performance

In this work, we proposed a 7.2 GHz on-chip receiver

based on this measurement. A circuit configuration thatfront-end with a narrowband noise-cancelling technique.

cancels the noise effect of dither to achieve multi-bit

In addition to the conventional receiver path consisting ofquantizer and an integrator configuration with higher DC

a low noise amplifier (LNA) and a down-conversion mix-

gain are required.

er, an auxiliary noise-cancelling path is placed to cancel

High-speed wireless and wired communications re-out the thermal noise caused by inductors in the LNA.

quire high-speed, high-precision analog-to-digital con-

The proposed receiver front-end is designed with radia-

verters (ADCs). Time-interleaving is a technique to speed

tion-hardened 130-nm SiGe BiCMOS process to miti-

up the conversion by operating multiple ADCs in parallelgate the irradiation effects in the space. The schematic-lev-

and is essential for multi GS/s ADCs. The performance ofel simulation using ideal behavioral models only for LO

time-interleaved ADCs is severely affected by the errors

generation and GM blocks demonstrates 1.03 dB NF at

between each ADC such as DC offset and clock skew, soroom temperature, which is 1.61 dB lower than the case

it is important to minimize or calibrate them. For each

only with the main path. The temperature dependence

factor, we proposed an optimal implementation based on

can be compensated by calibrating the input bias voltage

theoretical analysis, and designed an 8-channel 4GS/sof the LNA.

ADC in 28nm FD-SOI process. Simulated performancewith noise and layout parasitics achieved a Schreier FoM
of 161.6dB, which is higher than the state-of-the-art
ADCs.

29

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C

30

Design of Time-Domain Neuron Devices and Eval-

represented more efficiently in time domain, i.e., a timeuation of Learning Systems

interval of two signal transitions. This so-called time-do-

Tetsuya Iizuka, Xiangyu Chen, Byambadorj Zolboo,

main circuit have another advantage in its power efficien-

Ckristian Duran, Shun Ito, Yuto Wakui

cy as it often consists of inverters or logic gates that ideally

Deep neural networks (DNNs), which are the second

consume no DC power. Thus, time-domain circuits are

generation of artificial neural networks (ANNs), have ex-

ideal for future implementations of low-power SNNs.

tensively explored in recent years for the growing number

TSMC 65nm process designed neuron, synapse, andof applications. However, their huge energy consumption

weight circuits were prototyped and measured. The meas-

especially for the memory access in conventional von-Neu-

ured results were submitted to the APL, while a circuitmann architecture has forced people to find an alternative

was designed to expand the oscillation frequency range ofway to achieve more power-efficient solutions. Spiking

the created synaptic circuit to solve the problem of theneural network (SNN) is one of the attractive solutions as

small oscillation frequency range of the synaptic circuit

the third generation of ANNs that can realize a learning

used to implement the SNN. The circuit was designed

function with low power by mimicking biological neu-

using TSMC’s 65nm process, and the first prototype wasrons. SNNs consist of neurons and synapses, and are usu-

able to expand the oscillation frequency from 15Hz toally built using a bottom-up approach, which means that

130kHz. This oscillation frequency range is based on ac-

each component of the SNNs needs to be designed first.

tual measurements. This was achieved by changing theMany hardware implementations of pulsed neurons oroscillator part to a differential inverter and grounding thesynapses have been reported. To implement the leaky in-

NMOS source of the oscillator. However, to output an

tegrate function of neurons, conventional designs usuallyoscillation frequency of 130 kHz, it was necessary to use abuild integrators with operational amplifiers (op-amps)

10 MHz input, which did not match the input-output

and often use large on-chip capacitors and resistors toorder; in the second prototype, the oscillation frequency

mimic the millisecond time constants of biological neu-

could be increased from 400 Hz to 6 MHz. These valuesrons. Moreover, to implement the neuron “fire” function,

are from simulations with parasitic capacitance; it allows

a dedicated circuit structure of a continuous-time orfor inhibitory inputs in addition to excitatory inputs, andclocked comparator is usually used to set the threshold fora Schmitt trigger inverter was added to prevent chattering.

neuron excitation. The bias current of the continu-

The steady-state value of the oscillation frequency is 20

ous-time comparator undoubtedly increases the power

kHz, with a maximum output frequency of 6 MHz with

consumption of the neuron, while the clocked compara-

excitatory input and a minimum output frequency of 400

tor requires additional clock signal distribution and theHz with inhibitory input. The input frequency is 10 MHz

complex comparator structure occupies a large chip area.

for the maximum output frequency of 6 MHz, solving the

While more advanced processes can achieve low power

problem of the 1st prototype input and output not match-consumption by reducing supply voltage and static leak-ing the order of the frequency. These two circuits solved

age current, this also leads to a narrower dynamic range,

the problem of the small oscillation frequency range of thesmaller available margin, and degraded noise immunity ofsynaptic circuit.

the voltage/current-domain analog circuits. This is detri-

In addition, we tested whether sine waves can bemental to conventional neural networks that use analog

learned correctly by connecting actual designed synaptic

quantities, such as voltage and current, to communicate

circuits together, using the spiking neural network. As awith each other. On the other hand, thanks to the scaled

result, only sine waves around a specific frequency could

transistors that have an improved operation speed withbe learned. Since the frequency at which learning was pos-

sharp signal transitions, the analog information can besible varied up and down in the simulation using imagi-

nary circuits in which the voltage leakage and output fre-tions when the measurement setup is correctly calibrated,

quency of the synaptic circuit were changed, it isand the measurement parameters is chosen with properconsidered necessary to use different circuits depending

values. To capture such 120º range of the AUT, a probe

on what is to be learned.

with low directivity is necessary. The preliminary meas-

Antenna Measurement and Testing Techniques forduce the sampling points in near-field measurement to

Wireless Communications

reduce the measurement time and cost.

Tetsuya Iizuka, Mai Khanh Nguyen Ngoc,
Byambadorj Zolboo, Sheng Guo

Design of High-Sensitivity On-Chip Network Ana-

In 5G technologies, over the air (OTA) measurements

lyzer Circuits

are necessary for 5G antennas due to the technologies rely

Tetsuya Iizuka, Zunsong Yang, Yuyang Zhu,

on millimeter-wave frequencies and small-sized terminals.

Zhenyu Cheng

The conventional OTA measurement is based on far-field

A VNA system is a test instrument for measuring elec-

measurement. However, the far-field measurement is al-trical network parameters, which is essential for radio fre-most infeasible in the millimeter-wave due to high pathquency (RF) and microwave component analysis of a wideloss and low measurement accuracy. Therefore, near-field

variety of passive and active devices, including filters, an-measurement takes place of OTA measurement in thetennas, and power amplifiers. VNA can provide stimulus

millimeter-wave range. The far-field measurement data

signal to the device under test (DUT) and measures thecan be achieved from near-field measurement by using

vector response over frequency with phase and magnitudenear-field to far-field methods.

information, like transmission, reflection, impedance

In this research, there are plenty of challenges frommeasurements, as well as S-parameters S11, S12, S21,

hardware to software including automated near-field

S22. Nevertheless, most VNA systems are external system,measurement equipment, millimeter-wave probe, andwhich are area-consuming and expensive. Meanwhile, it isnear-field to far-field transformation methods. In near-also a challenge to test a very weak signal buried in noise

field measurement, one of the easiest ways is to measurethat come out from the DUT in a wide frequency range

S-parameters on the planar scanning area in front of the(for us, is 1-5GHz).

antenna under test (AUT).

3
CCCCCCCCC CCCCCCCCCCCCCCCCC

urement results show that it is possible to effectively re-C

In this work, we proposed an on-chip VNA with a

For the near-field probing hardware and measurement

phase interpolator (PI), a low-noise amplifier (LNA) andsetup, we design and fabricate a low-cost planar monopole

a lock-in amplifier (LIA), to test the S-parameter of ouron PCB. The proposed NF antenna operates at 28-GHz

DUT, which contains two-port inputs and has ultra-low

frequency by employing an arrow-shaped structure to en-

S21 and S23 parameters (the minimum can reach -95dB).

hance the total electric field at the head when point-by-

The 1-5GHz PI is used to apply two phase-adjustable sig-

point scanning on the AUT’s surface. A prototype is thennals to the DUT for testing S23 parameter versus input

fabricated and measured to validate the simulation results.

phase difference. The LNA and LIA are used to measure

The measurement results of the proposed antenna show a

the weak output signal from the DUT.

wide bandwidth of 2.6 GHz and a center frequency of 28

Until now, we have designed the whole circuit and fin-GHz. In addition, we successfully built a compact ane-ished the layout of the chips (including PI chip, LNA

choic chamber with automate motorized control for near-chip, LIA chip, and an overall chip containing all parts) infield measurement in mm-wave frequency range.

TSMC CMOS 65nm process. For PI, at 2.5GHz, theThe far-field pattern has been achieved under 0.5 dB

maximum DNL is 0.67LSB and maximum INL iserror within 120º on both elevation and azimuth direc-

2.4LSB; at 5GHz, the maximum DNL is 0.38LSB and

31

3
CCCCCCCCC CCCCCCCCCCCCCCCCC
C

the maximum INL is 3.24LSB. For the LNA, thein the EM simulation and on-chip measurement at the

post-simulation indicates noise figure of 3-5 dB over 1-5

topological phase, implementing the existence of MZMs

GHz. For the whole system, the pre-simulation andat both edges.

post-simulation showed similar S21 and S23 curves to theThen, on the 2nd version chip, we added the CMOS

measured results of our DUT, which suggests that theswitches to control the topological properties of the whole

proposed structure can work properly. The real-chip test

SSH chain and each unit cells in the Kitaev chain. We

will be done after getting the chip.

have observed from the measurement that impedance

The next step of our work is aiming to improve thepeaks emerging at the edges of the SSH model chains. On

noise performance of our system, at the meanwhile, athe Kitaev topological-trivial switchable circuit chain, by

1-5G PLL will be made to provide multi-phase clock sig-

generating the proper control signals, we simulate how

nals for PI.

two topological segments moving, splitting and fusing on
the Kitaev chains with two different resonant frequencies,

Verification of Topological Quantum State based

and observe the impedance peaks at each topological-triv-

on Electrical Circuits

ial boundaries in the real measurements, corresponding to

Tetsuya Iizuka, Yuan Haochen

the existence of zero-energy modes acquired for the braid-

Topological quantum computing (TQC) is a method

ing operations of the topological quantum computation.

of fault-tolerant quantum computing, in which a single
quantum gate could be generated by the braiding of certain topological quantum objects, named “anyons”, andtopological quantum computing has the natural property
of being immune to decoherence and accurately executing

Hiramoto & Kobayashi Laboratory(http://nano-lsi.iis.u-tokyo.ac.jp/)

Variability in Nano-Scale CMOS Devices

predefined algorithms. One simplest realization of a

Toshiro Hiramoto and Masaharu Kobayashi

non-Abelian anyon is a quasiparticle named Majorana fer-

As the size of MOS transistors is miniaturized, the ef-

mion which obeys ordinary Fermi-Dirac statistics andfect of random variability of device characteristics is be-owns a particular mechanism, Majorana zero mode

coming too large to be overlooked. Although the main

(MZM). Therefore, we focus on the 1D circuit chain real-reason in conventional bulk transistors is the fluctuation

ization of Majorana zero-energy edge states to discoverof the number of dopants, the variability causes of nano-whether the MZM will appear at the boundaries, bywire transistors, which is one of the next-generation de-measuring the nodes’ two-point impedance between thevice candidates, remain unknown. In this study, we haveleft/right edge nodes.

clarified that the quantum confinement fluctuation caused

Based on CMOS 180 nm process, we implemented in-by line width roughness is the new origin of random

tegrated circuit realization of Su-Schrieffe-Heeger and Ki-

threshold voltage variability. We are also investigating thetaev models on the chip. By simulating in the EM simula-effect on the drain current variability.

tion tools and measuring on the real chip, we observe theimpedance peaks at the edges of these chains demonstrat-

Low Temperature Characteristics of Nano-Scaleing the existence of MZMs.

CMOS Devices

On the 1st version chip, for the Kitaev model, we have32

Toshiro Hiramoto and Masaharu Kobayashi

constructed three topological circuit chains with different

The quantum computing has attractive much attention

resonant frequencies by adjusting the values of capacitors

for a future computing technology that is fundamentallyand inductors, also with three trivial chains for compari-different from classical computing by CMOS circuits. In

son. The rapidly increasing two-point impedance is found

the quantum computing systems, conventional CMOS

circuits are utilized to control quantum bits. Therefore, ithorizontally aligned after crystallization anneal but theyis essential to clarify and model CMOS transistor charac-

are vertically aligned after applying voltage cycling. This

teristics at low temperature. In this study, we are studying

indicates that ferroelectricity can emerge even in 3D-struc-the subthreshold swing of bulk and nanowire transistors.

ture.

3

temperature.
Silicon Power Devices

Takagi Laboratory(https://sites.google.com/g.ecc.u-tokyo.ac.jp/mosfet/)

Toshiro Hiramoto

III-V Metal-Oxide-Semiconductor (MOS) FETs andAlthough new materials such as SiC or GaN are widely

the 3-dimensional integration

studied for power devices, silicon IGBT (Insulated Gate

Shinichi Takagi, Kei Sumita, Ryohei Yoshizu,

Bipolar Transistor) is still a mainstream device for power

Kasidit Toprasertpong, Mitsuru Takenaka

electronics in very wide range of rated voltages. In this

3D-integrated CMOS, in which transistors are vertical-

study, we are pursuing the potential of silicon IGBT based

ly stacked, is expected to be a key device for future logic

on new concepts of IGBT scaling and double-gate IGBT.

LSIs. In order to realize such stacked MOSFETs, channels

CCCCCCCCC CCCCCCCCCCCCCCCCC

We are also evaluating the characteristics variability at low

Csuch as III-V compound semiconductors and Ge are
Research on atomic layer deposition of oxide sem-promising because they can be fabricated at low tempera-

iconductor and its application to 3D integrated

tures and are expected to have high mobility and injection

memory devices.

speed. In our laboratory, we are investigating the identifi-

Masaharu Kobayashi, Toshiro Hiramoto

cation of channel materials with high mobility in extreme-

While 2D scaling is getting challenging, 3D monolith-

ly-thin channel thickness, the realization of ultra-thin

ic integration that requires active device formation in

III-V-On-Insulator (III-V-OI) structures on Si substrates,

BEOL layers is getting more attentions. Oxide semicon-

and the performance improvement of III-V n-MOSFETs

ductor is attractive because it can be formed in BEOL lay-using these structures aiming at application to 3D stacked

ers at low process temperature. Sputtering has been used

CMOS. In this fiscal year, we addressed the quantitativefor flat panel display device of oxide semiconductor, but

assessment of channel materials that can achieve high mo-cannot be used for conformal deposition on 3D structure.

bility even under thickness fluctuation (surface rough-In this research, we developed In2O3 deposition methodness) scattering, which is an important scattering mecha-

by using Atomic Layer Deposition (ALD). Then we de-nism that determines the mobility of thin-film channel

signed 3D vertical channel ferroelectric transistor memo-

MOSFETs, revealing the usefulness of (111) InAs-OI andry with HfO2-based ferroelectric. We demonstrated good(111) Ge-On-Insulator (GOI) n-MOSFETs, where elec-

memory characteristics and reliability by experiment.

trons can transfer into the L-valleys. Furthermore, as amethod to accurately determine the interface state density

Research on the physical understanding of theat the InAs MOS interfaces, we proposed an evaluation

emergence of ferroelectricity in HfO2-based ma-

method using CV characteristics at cryogenic tempera-

terialtures and experimentally demonstrated that the interface

Masaharu Kobayashi, Toshiro Hiramoto

state density can be evaluated with high accuracy.

In this research, we aimed at elucidating the physicalmechanism of the emergence of the ferroelectricity in
HfO2-based material for 3D-structureed ferroelectric devices. This year, we illustrated that ferroelectric grains are

33

3
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C

Ge Metal-Oxide-Semiconductor (MOS) FETs andthick ultra-thin MFM capacitor for FeRAM applications,the 3-dimensional integration

the low operating electric field decreases the polarization

Shinichi Takagi, Chia Tsong Chen, Xueyang Han,

due to fatigue of the ferroelectric film occurs, whereas thisKasidit Toprasertpong, Mitsuru Takenaka

fatigue can be recovered by applying a higher electric field

We are investigating the technology to realize ultra-thinpulse.

Ge-On-Insulator (GOI) structures on Si substrates, theperformance improvement of high-performance GOI

Reservoir computing based on ferroelectric devices

CMOS using these structures, and the device physics that

Shinichi Takagi, Kasidit Toprasertpong, Eishin Nako,

determines the electrical characteristics, with the aim of

Rikuo Suzuki, Mitsuru Takenaka, Ryosho Nakane

applying them to 3D integrated CMOS. In this fiscal

Reservoir computing has recently attracted attention as

year, we have demonstrated that high hole mobility can be

an AI computation method with computational load for

obtained even in extremely-thin GOI p-MOSFETs by in-learning. We have proposed that FeFETs and FeRAMs

troducing uniaxial compressive strain into (110) Si-with memory-in-logic and nonlinear analog computation

Ge-On-Insulator (SGOI) structures, fabricated by Ge

capabilities are promising hardware for the physical im-

condensation of (110) SiGe/SOI substrates. We also ex-

plementation of reservoir computing. Thus, we are search-

perimentally demonstrated that additional oxidation aftering for methods to improve AI performance of reservoir

the completion of Si oxidation in the Ge condensation

computing based on ferroelectric devices by examining

process can introduce a larger tensile strain than expected

operating schemes and device characteristics. In this fiscal

by the thermal expansion coefficient.

year, we demonstrated that AI performance can be improved by utilizing not only drain current but also source

HfO2-based Ferroelectric devices

current and substrate current as output data. For applica-

Shinichi Takagi, Kasidit Toprasertpong,tion to speech recognition, we proposed a system that per-

Makoto Kawano, Koichiro Iwashige,

forms the task of spoken digit classification using a paral-

Masaki Ootomo, Zhenhong Liu, Mitsuru Takenaka

lel-operating FeFET reservoir and experimentally achieved

MOSFETs using ferroelectrics (FeFETs) with polariza-a classification accuracy of 95.9%.

tion reversal as gate dielectrics and FeRAM using metal

34

sandwich structures (MFM structures) as memory cells

Understanding of Si CMOS operation under ul-

are expected to be future devices for ultra-low power

tra-low temperatures for quantum computing ap-

memory and logic. In particular, devices based on ferroe-

plication

lectric and anti-ferroelectric materials such as Hf1-xZrxO2Shinichi Takagi, Minsoo Kang, Yutong Chen,

and ZrO2, which have been discovered recently, are of

Kasidit Toprasertpong, Mitsuru Takenaka

great interest because of their extremely high compatibili-

In quantum computing systems, Si CMOS circuits thatty with current Si CMOS technology. We are studying thecan operate at cryogenic temperatures such as 4 K must be

properties of these ferroelectric thin films deposited by anplaced close to the qubit chip in order to improve the

ALD method, the device operation principle of FeFETs,

number of qubits. For this purpose, we are conducting

and the optimum device structures to realize excellent de-experimental and theoretical studies to quantitatively de-vice characteristics. In this fiscal year, we investigated thescribe the electrical characteristics of MOS transistors at

mechanism that determines the memory window ofcryogenic temperatures and to clarify their physical mech-

FeFET memory, proposed an analytical expression for it,

anisms. In this fiscal year, we experimentally evaluated theand clarified the impacts of various physical parameterschange in SS (sub-threshold swing) values of Si n-MOS-

on the memory window. Also, we found that, in a 4 nm-

FETs with different substrate concentrations from room

temperature to 4 K. We found that the tail states and lo-

sulator (GeOI) wafer. We have successfully demonstrated

calized interface states near the band edge, which affect SSavalanche photodetection through defect-mediated pro-values, increase with an increase in the substrate concen-

cess using a Ge waveguide with a lateral PIN junction We

tration, and that the tail states and localized interface

have achieved the device operation at > 1 Gbps.

perimental results of the substrate bias dependence of the2D material devices
Mitsuru Takenaka, Tipat Piyapatarakul

SS values.

We have been studying semiconductor devices using

Takenaka Laboratory(https://sites.google.com/g.ecc.u-tokyo.ac.jp/takenaka-lab/)

On-chip/Off-chip optical interconnect

graphene and molybdenum disulfide. We have proposed a
new MOS-based optical modulator using a III-V membrane waveguide with a graphene transparent electrode.
Since the optical absorption and resistivity of the graphene

Mitsuru Takenaka, Rui Tang, Hanzhi Tang,electrode can be reduced simultaneously by doping, weYuto Miyatake, Tipat Piyapatarakul, Kazuma Taki,have numerically revealed that the proposed modulator

Taketoshi Nakayama, Tomohiro Akazawa, Sheng Fu,

enables low-loss and high-speed modulation.

3
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states have a similar physical origin, judging from the ex-C

Hiroya Sakumoto
We have been conducting research on optical interconnection and I/O of LSIs using silicon photonics and othertechnologies. We have successfully demonstrated a Si hy-

Uchida Laboratory(http://www.ssn.t.u-tokyo.ac.jp)

brid waveguide-coupled photodetector using an InGaAs

In the Internet-of-Things (IoT) era, every physical de-membrane on a Si slot waveguide. Using a Si slot wave-

vice will be connected to network. In this framework, any

guide, the absorption in the InGaAs membrane can bephysical devices will have sensors that will continuously

enhanced. As a result, we have successfully achieved a highobtain various kinds of physical as well as chemical infor-

responsivity and low capacitance simultaneously.

mation around us. We expect that big data consisting ofthese sensor outputs will be analyzed with AI and valuable

Si photonic integrated circuit for AI

information will be extracted to improve our quality of

Mitsuru Takenaka, Rui Tang, Hanzhi Tang,life. In our group, low-energy sensors and information

Yuto Miyatake, Kazuma Taki, Mingzhi Huang,

processing devices have been developed by pursuing phys-

Tomohiro Akazawa, Masahiro Fujita, Yosuke Wakita

ics of nano-mateials and nano-devices. Recent research

We have been conducting research on deep learning for

topics are as follows.

AI using programmable photonic circuits such as univer-

1. Metal nano-film sensors for breath diagnosis

sal optical circuits. We have developed a new phase change

2. 
Thermal transport analysis of nano-meterials formaterial, GeSbTeS (GSTS) and demonstrated that the
optical absorption of GSTS is reduced significantly at a

low-energy sensors
3. Electron-phonon interactions at the interface of insula-

wavelength of 2.34 µm. As a result, we have successfully

tor and semiconductor

demonstrated a low-loss optical phase shifter using GSTS.

4. Supramolecular sensors
5. Information processing devices beyond von Neumann

Ge mid-infrared photonic integrated circuitarchitecture

M. Takenaka, Yuto Miyatake, Chao Zhang
We have been studying mid-infrared photonic integrated circuits based on Ge waveguides formed on Ge-on-in-

35Someya-Yokota-Lee Laboratory

3
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Mita Laboratory(http://www.ntech.t.u-tokyo.ac.jp/, https://fles.t.u-tokyo.ac.jp/)(http://www.if.t.u-tokyo.ac.jp)

Improvement of photo-stability in Organic Photo-

TopoMEMS: Development of Ideal Variable MEMS

detectors

in view of Future Topological Quantum Computing

Wijaya Theodorus, Tomoyuki Yokota,

Y. Mita, K.Tsuji, A.-C.Eiler,A.Higo, T.Iizuka, Z.Xu,

Sunghoon Lee, and Takao Someya

M.Ezawa (Dept. Applied Physics)

By using optical devices, biological information such as

Recently, new computation methods that use Topolog-

blood pressure, pulse rate, and blood oxygen concentra-

ical nature are drawing much attentions in view of futuretion can be non-invasively acquired. We have successfully

Quantum computing. Calculation takes advantages Top-

improved the stability of organic photodetectors by using

ological natures existing in several different fields ex-

an electron transport layer (ETL) made of thermally treat-pressed as Hamiltonian matrices. Our team, granted by

ed zinc oxide (ZnO) or the mixture of ZnO and polyeth-

JST CREST project, tries to explore electrical expression

yleneimine (PEI). The sol-gel method, which is highlyof Hamiltonian matrices used for computation. Teamcompatible with flexible substrates, has been widely used

Mita will develop ideal variable electrical devices as well as

to form ZnO ETL. However, the conventional annealingideal MEMS devices. We named such devices and sys-

temperature was low at 180°C, and there was a problem oftems “TopoMEMS”. As an initiating study, we have taken

traps in the ETL due to the presence of remaining precur-

Su-Schriffer-Heeger model. We have developed a MEMS

sors. These traps are considered to be one of the causes ofstate-variable capacitor integrated SSH electrical circuit

increased dark current when exposed to light. For weara-

and have been successful in Topological / Trivial state

ble sensor applications that require long-term stability, it

switching due to MEMS device. The result has been pre-was necessary to improve the stability against light irradi-sented in the top MEMS conference. Then, we have iden-

ation. It was found that increasing the annealing temper-

tified another interesting computation scheme by directly

ature of the ZnO layer to 350°C dramatically improved

using dynamics of MEMS. Towards that end, a bistable

photo-stability. This is believed to be due to the reduction

MEMS actuator towards MEMS Ising machine was pub-in trap density caused by the high annealing temperature.

lished in peer-reviewed journal, and multi-level bistable

Furthermore, by using a mixture of ZnO precursor and

MEMS actuator has been accepted in the top internation-

the polymer PEI as PEI-Zn in the electron transport layer,

al conference..

we succeeded in reducing the trap density and improving
stability even at the conventional annealing temperature

Programmable Matter - Study on LSI-MEMS ener-of 180°C. Additionally, by integrating these devices with

gy-autonomous distributed microsystems for re-organic light-emitting diodes, we have successfully real-

alization of deformable matter

ized a wearable pulse wave sensor that can be attached and

Y. Mita, K.Misumi, N. Usami (Dept. of Aer-

used in everyday life to sense pulse waves over a long peri-

onautics and Astronautics), E. Lebrasseur,od of time.

G. Hwang (LIMMS, CNRS-UTokyo IIS / CNRS C2N),
G. Ulliac, (LIMMS, CNRS-UTokyo IIS, FEMTO-ST),
J.Bourgeois, B.Piranda (FEMTO-ST, France),
S. Delalande (Groupe PSA, France)
As one example of future integrated MEMS that is expected to open new research and industrial application
fields, the authors are trying to show a top-down applica-

36

lithography, whose pattern approximation have been lim-

number of identical tiny robots, sized below 1cm, will beited to rectangular shapes, into expressing free-form

released in an environment. Individual robot can commu-

smooth shapes and a number of periodical small patterns.

nicate with their neighbor, stick each other, and share en-

This year, pattern and process design has been successful

ergy, to realize cooperative function. The PI is receiving a

to obtain gap structure less than 16-nm wide. The result

French National Research Center (ANR) grant on behalf

has been presented as a peer-reviewed journal.

of host professor of CNRS laboratory in the Institute ofIndustrial Science (LIMMS, CNRS-IIS, UMI 2820), to-

Universities-Industries collaborative research on

gether with FEMTO-ST Laboratory and PSA-Peugeot

highly-functional system by MEMS post-process

Laboratory for such “micro robots that can realize deform-of CMOS-VLSI

able substance by cooperative action, named Programma-

Y. Mita, T. Yamaguchi, S. Nakajima,ble Matter”. In year 2020, an electrostatic chucking actu-

R. Shimamura, T. Lévi(IMS-CNRS,Bordeaux),

ator system that attaches and detaches the external

G. Larrieu (LAAS-CNRS,Toulouse), Y.Ikeuchi (IIS),

skeleton of the Matter has been presented in an interna-

K.Saito (Nihon Univ.)

tional conference. Based on the actuation force electro-

The research targets are new sensor devices, made bymagnetically analyzed, the ideal structure of the flexible

post-process at clearnrooms such as d.lab Takeda Super-electrode (named Flexiboard) has been identified, and acleanroom and others, of VLSI wafer made throughreliable integration process with thinned high-voltage

VDEC. The important finding has been that VLSI wafer

photovoltaic cells have been presented in the international

acquired just after transistor fabrication could sustain pro-conference.

cesses even with heat treatment, such as deposition, ion

3
CCCCCCCCC CCCCCCCCCCCCCCCCC

tion of energy-autonomous distributed microrobots. A

Cimplantation, and drive-in. In 2016, a VLSI device madeIntegration of electrode devices on MEMS fluidic

on Silicon-on-Insulator (SOI) wafer was successfully

devices

Deep-RIE processed. The industrial interest is its versatil-

Y. Mita, A.-C. Eiler, A. Higo, T.Ezawa, E.Ota,

ity – many different types of application devices, which

Y.Okamoto (AIST), N.Washizu (Advantest),

differ one from another according to request of market,

A.Takada (Advantest), M. Fujiwara, T.Sawamura

can be fabricated by using the same technology. More andTowards the goal of production of brand-new sensor

more companies are interested in the scheme and are

devices with higher sensitivity and functionality, the teamworking on the technology on the collaborative researchis working on small-gap electrode fabrication process.

projects, including international cooperative research pro-This year, we have post-processed Fully-Depleted SOI

jects. This year, a world’s lowest-level (1.5V) soft microac-

VLSI device for massively parallel measurement and its

tuator with highest figure-of-merit has been developed

integration is underway.

and presented in a peer-reviewed journal paper and domestic conference (was late news award finalist).

Fine Large-Area Electron Beam Lithography Exposure Methods
A. Higo, Y. Ochiai, M. Fujiwara, T.Sawamura, Y. Mita
The team explores newly-acquired (in 2013) rapid elec-

Test Structure for high-density CMOS-MEMS hybrid integrated Technology
Y.Mita, H. Matsuoka, Y.Ebihara, A.Mizushima,tron beam writer F7000S-VD02. The capability of highT.Yoda (TITech), K.Hirakawa (TITech),

electron dose and sharp edge due to cell (character) pro-M.Iwase (TITech), M.Ogasawara (TITech),jection machine configuration is being examined. The

A.Higo and Y.Ochiai

breakthrough in question is to extend the large-area EB

Chip-level highly-dense bonding integration is drawing

37

high attention to simply obtain high-functional system; it
has been almost impossible to individually examine padto-pad connections, whose size is in an order of several
3
CCCCCCCCC CCCCCCCCCCCCCCCCC
C

38

microns and whose number is order of 1 million. New test
structures and methods are mandatory. We have proposeda two-pads-per-probe scheme, in which one of the pad isused for testing pad to make what we call “loop-backtest”. A test LSI have been designed, fabricated, and integrated with gold bumps as well as MEMS test structures.

Appendix
A.1 VDEC CAD Tools
Since 1996, VDEC has provided CAD software licens-

cense server located in the ten VDEC subcenters shown in

es to the registered researchers in universities and colleges

Figure A.1.1. For each CAD tool, VDEC provides 10-

in Japan. The CAD tools we provided in 2023 through1000 floating licenses. Those CAD tools can be utilized

the activities of VDEC in Systems Design Lab (d.lab) areonly for research and education activities in national uni-

shown in Table A.1.1. The researchers can use those CAD

versities, other public universities, private universities,

tools when their local machines, whose IP addresses are

and colleges.

Table A.1.1

VDEC CAD tools

Name
Cadence tool set

Synopsys tool set

Siemens tool set
Silvaco tool set
ADS/Golden Gate
Bach system
LAVIS

A-1
Appendixregistered in advance, are authorized by one of VDEC li-

Function
VendorVerilog-HDL/VHDL entry, Simlation, Logic synthesis, Cadence Design Systems, Inc.
Test pattern generation, Cell-based (including macros) place, route, and back-annotation, Interactive
schematic and layout editor, Analog circuit simulation, Logic verification, Circuit extraction
Verilog-HDL/VHDL simulation, Logic synthesis, Test Synopsys, Inc.
pattern generation, Cell-based (including macros)place, route, and back-annotation, Circuit simulation,
Device simulation
Layout verification, Design rule check
Siemens Electronic Design Automation Japan K.K.
Fast circuit simulation
Silvaco Japan Co., Ltd.
Design and verification of high-frequency circuits
Keysight Technologies
BachC-based design, synthesis, and verification
Sharp
Layout visualization platform
TOOL

Fig. A.1.1 VDEC Subcenters

39

A.2

 tatus of Chip Fabrication Support at Platform Design Research
S
Division

As for the support for VLSI chip prototyping, in thepilot project in FY 1994 and 1995, there was only one
foundry, NEL’s CMOS 0.5µm (the process was later continued by Hitachi Hokkai Semiconductor). After the inauguration of VDEC in 1996, the 1.2-µm CMOS processof Motorola Japan (which was continued by ON Semiconductor in 1999) started cooperation, and the 0.6-µm
A-2

CMOS process of ROHM was added in 1997. In 1997,

Appendix

CMOS 0.6µm from ROHM was added, followed by
0.35µm from Hitachi, Ltd. in 1998, and 0.35µm from
ROHM in 1999. In addition, as part of the IP development project, a prototype of STARC 0.13µm was devel-(a) Trend of number of designs fabricated.

oped. Since FY 2001, we have been providing services of
CMOS 0.18µm from Hitachi, Ltd. In 2002, under theleadership of Dr. Iwata of Hiroshima University, we conducted a trial trial fabrication service in cooperation with
VDEC and MOSIS. This service provides overseas fabs
such as TSMC and IBM at low cost through MOSIS.
Furthermore, under the leadership of Dr. Shibata of the
University of Tokyo, NEC Compound Device, Inc. provided a prototype service for bipolar LSI. In 2004, westarted prototyping Oki Electric CMOS SOI 0.15µm
process and ASPLA 90nm process as test prototypes, andthe 90nm prototype was operated as a regular prototype
from 2005 in the form of public solicitation. In FY2006,
we started trial production of 0.18µm process by ROHM

(b) Trend of designed area.

and test production of 0.25µm SiGeBiCMOS by Hitachi,Ltd. In FY 2007, we started to study an advanced process
to succeed 90nm CMOS, which was terminated in FY
2007, and in FY 2008, we started trial production of eShuttle’s 65nm CMOS. In addition, as part of the METISTARC project “Next Generation Semiconductor Circuit
Architecture Commercialization Support Project,” prototype production using Renesas Electronics’ 40nm CMOS
was also started. On the other hand, CMOS1.2µm was
terminated in September 2011, Renesas Electronics’
40nm CMOS prototyping was terminated in 2012, andeShuttle’s 65nm CMOS prototyping was terminated inAugust 2013. As a successor to CMOS 1.2µm, a test prototype of CMOS 0.8µm was conducted in October 2012
with the cooperation of Onsemi-Sanyo Semiconductor
Manufacturing Co. As for the leading-edge prototyping,

40(c) Trend of designed area normalized by design rule.
Figure A.2.1 T rend of number of designs and designed chiparea.b

STMicroelectronics started FD-SOI 28nm CMOS prototyping through CMP of France in FY 2013. In addition,
we started SOTB 65nm CMOS prototyping by Renesas
Electronics as a regular prototyping in FY2015, and concluded in FY2022. In FY2021, we started BiCMOS
0.18um prototypes under an agreement with IHP of Germany.
Fig. A.2.1(a) shows trends of number of chip designed
for VDEC chip fabrication. For the first 6 years until
2001, the number of designed chips shows steady increase, which means drastic improve of the effectivenessA-2

drastic increase of number of students related to LSI chip
design and education. During few years of stable number
around 400 chip designs per year, we can see transition of

Figure A.2.2 T rend of number of processors and universities
fabricated chip.

Appendix

researches and education of LSI design, and we assume

designs toward finer process. In 2007, we saw a large drop,
which was caused by sudden process transition from0.35µm CMOS to 0.18µm CMOS, and in 2008, we also
saw another drop by process transition from 90nm
CMOS to 65nm CMOS.
Fig. A.2.1(b) shows trends of designed chip area, whichshows much clear trends of drop by process migration.
On the other hand, Fig. 2.3.1(c) shows trends of designed
chip area normalized by design rule, which assume to bestrong relation with design efforts. Coming from the factthat the normalized chip area is still growing, we assume
the major reason for decrease of number of chips and designed area is increase of design effort per chip and perunit area due to process scaling.
Fig. A.2.2 shows trends number of professors and universities fabricated chip. Number of professors who havecontracted NDA for process technologies to access design
rules and design libraries are, 93, 294, and 55, respectively, for 65nm CMOS, 0.18 µm CMOS, and 0.8um
CMOS.
Table A.2.1 lists chip fabrication schedule in 2022.
Please refer to list in Appendix B for details of designers
and contents of chip designed.

41

Table A.2.1

Chip fabrication schedule in 2022

0.8 µm CMOS (On-Semiconductor - Sanyo)
2021 #1
2021 #2

Chip application deadline
2022/7/4
2023/1/10

Design deadline
2022/9/26
2023/3/27

Chip delivery
2023/1/31
2023/6/6

Design deadline
2022/6/27
2022/9/5
2022/10/24
2023/2/27

Chip delivery
2022/9/27
2022/12/20
2023/2/7
2023/6/19

Design deadline
2022/7/25

Chip delivery
2023/3/E

0.18 µm CMOS (Rohm)
2021 #1
2021 #2
2021 #3
2021 #4

Chip application deadline
2022/4/4
2022/6/13
2022/8/1
2022/12/5

A-2

SOTB 65nm CMOS

Appendix2022 #1

42

Chip application deadline
2022/6/13

A.3

SeminarSeminars are always needed as the advancement of LSI

fers the CAD Seminar twice per year. In the CAD Semi-

design technology. In 2022, VDEC has held CAD Semi-nar, VDEC invites lecturers from venders including Ca-

nar and Designer’s Forum, for academic circuit designers.

dence, Synopsys and Keysight to give tutorials on their
CAD tools. The seminar is held in VDEC, The University

A.3.1

CAD Seminar for VDEC usersof Tokyo and VDEC sub-centers simultaneously in sever-Along with advancement of circuit design CAD tools,
tutorials on these tools are highly demanded. VDEC ofTable A.3.1

al universities nationally, in March of one fiscal year. Eachtutorial takes one or two days.

CAD technical seminar in 2022 fiscal year

A-3

Date

Venue

Number of Applicants

2/28-3/1

Keysight ADS Advanced

online34

3/13-14
3/15
3/13-17

Cadence Virtuoso Layout Suite-L
Cadence Clarity 3D Solver

onlineonlineonline72
2147

online73

onlineonline2234

3/13-17
3/17
3/28

A.3.2

Tutorial

Synopsys TCAD (On-Demand

Web Training)

Synopsys IC Compiler II (On-Demand Web Training)
Synopsys Q&A Meeting
Cadence Innovus Digital Implementation System

Appendix

CAD Seminar I

Designer’s Forum for academia

VDEC LSI designer forum intended for students andyoung teachers were held. The VDEC LSI designer forum
has aimed to sharing the information that generally hard
to be obtained common technical reports or academical
papers, such as the failure an LSI designer had been
through and the solution, and the construction method in
the design milieu in the laboratory.
Table A.3.2

Program of Designers Forum in 2022

9/30-10/1 Hybrid Attendees: On-Site 28, Online 7
9/30
13:00Reception
13:30-13:35
Opening
13:35-14:35
Keynote Speech
14:35-14:45
Lunch
14:45-16:05
Design Award Presentation I
16:05-16:10
Break
16:10-17:10
Design Award Presentation II
17:10-17:15
Break
17:15-18:15
Design Award Presentation III
10/1
9:00-10:00
Design Award Presentation IV
10:00-10:45
Idea Contest Presentation
10:45-10:50

Break

10:50-12:20

PhD Session

12:20-

Voting and Award Ceremony

43

A.4

Venture companies related to VDEC

Some professors related to VDEC started venture companies. The following is a list of the venture companies related to
VDEC.
[1] AIL Co.,Ltd. (http://www.ailabo.co.jp/)
Related professor : Professor Kazuo Taki, Kobe Univ. (Representative Director)
Description of business : (1) LSI design service(2) Engineer dispatching service(3) Recruitment(4) Management consulting

A-4
Appendix[2] Synthesis Corporation(Merged with Soliton Systems on July 1st in 2017, http://www.synthesis.co.jp/)
Related professor : Professor Emeritus Isao Shirakawa, Osaka Univ. (Director)
Description of business : (1) System LSI development and design service(2) IP development and sales(3) Development and sales of IPs(4) Development of EDA tools[3] ASIP Solutions (http://www.asip-solutions.com/)
Related professor : Professor Masaharu Imai (Representative Director, CTO)
Description of business : (1) R&D, education and consulting of IoT application system(2) Sales of ASIP design tool and consulting of ASIP development[4] Nanodesign Corporation (http://www.nanodesign.co.jp/)
Related professor : Professor Kazuyuki Nakamura, Kyushu Institute of Technology. (Representative Director)
Description of business : (1) LSI design and development(2) Development of LSI CAD and LSI evaluation tools(3) Design consulting, etc.
[5] A-R-Tec Corp. (http://www.a-r-tec.jp/)
Related professor : Professor Emeritus Atsushi Iwata, Hiroshima Univ. (Representative Director)
Description of business : (1) Analog IC design and measurement(2) PCB noise analysis(3) Develop human resources, OJT, Lecture[6] Ishijima Electronics (http://ishi.main.jp/)
Description of business : (1) Electronic circuit and board development(2) Software development(3) Consulting

44

System Design Lab (d.lab),
School of Engineering, The University of Tokyo
Annual ReportAugust, 2023
Published by
System Design Lab (d.lab), School of Engineering, The University of Tokyo
Tadahiro Kuroda
Address: Hongo 7-3-1, Bunkyo-ku, Tokyo, 113-8656, Japan
Printed in
SOHOKKAI co., Ltd. Tokyo Branch
Address: Koutoubashi 4-25-10, Sumida-Ku, Tokyo, 130-0022, Japan
Copyright Ⓒ by System Design Lab (d.lab), School of Engineering, The University of Tokyo

Systems Design Lab, School of Engineering, The University of Tokyo 2023