東京大学大学院工学系研究科
附属システムデザイン研究センター
先端設計研究部門・先端デバイス研究部門（旧VDEC）基盤設計研究部門・基盤デバイス研究部門

令和４年度

年 報

2022
Systems Design Lab, School of Engineering,(VLSI Design and Education Center), The University of Tokyo

Annual Report

Systems Design Lab, School of Engineering
The University of Tokyo 2022

Message from the Director of d.lab

Tadahiro Kuroda
Director
Systems Design Lab (d.lab)
School of Engineering, The University of Tokyo

In February of this year, the Ministry of Education, Culture, Sports, Science and Technology (MEXT) issued a call for proposals under their「次 世 代X-nics半 導 体 創 成 拠 点 形 成 事 業」(Translation: Initiative to Establish Innovation Centers for
Next-Generation X-nics Semiconductors). Their ultimate goal is the creation of groundbreaking, neXt-generation, novel
semiconductors through multi-disciplinary synergy (multiplication “X”), much like the creation of various functional devices from spintronics and photonics, novel computing technologies from neurophysiology and quantum mechanics, andintegrated devices from novel materials based on topotronics.
Regardless of the speciﬁc form of the novel semiconductor, a key requirement is the improvement of energy efﬁciency. In the last decade, while the amount of AI processing skyrocketed by 4 orders of magnitude, the energy efﬁciency ofgeneral-purpose processors increased by only an order of magnitude. This has driven platform providers such as GAFAM
to develop their in-house specialized chips to achieve high energy efﬁciency. However, the development of specialized
chips requires increasingly more time and higher cost. Given the rapid advance in AI technology, if it takes a year todevelop a specialized chip, it is already obsolete by the time the development is complete. The strategy for growth in the
DX age requires rapid iteration (being agile) of the development-improvement cycle. This can be achieved if LSI chips aredesigned the way software is written and prototyped the way a program is compiled to make them updatable like software.
A related question is how to accelerate technology innovation. The answer can be found in the idea of a collective
brain expounded by Joseph Henrich, Professor of Human Evolutionary Biology at Harvard University. The bigger thecollective brain is, the easier it is to accelerate technology innovation. For instance, through research conducted on various Paciﬁc islands, the paper “Population Size Predicts Technological Complexity in Oceania” found a correlation
between the size of variation in ﬁshing tools and the population of the island. The reason that, even with a smaller brain
than Neanderthals, Homo sapiens were able to invent and utilize various tools is also thought to be due to their integration into large groups. The internet has enabled a giant collective brain of 7.7 billion people. A platform that attracts
many people will turn into a center for accelerated technology innovation.
We at d.lab proposed an “Agile-X Center for Democratization of Innovative Semiconductor Technology.” Our target isa 10-fold increase in the population of chip designers. To that end, we will create an agile development platform to
reduce both the time and cost for chip development and prototyping by an order of magnitude. During the application
process, we were asked by the X-nics review committee what X stands for. We answered that it is the unknown of“what” innovation will change the world. Nevertheless, we know “where” the innovation will come from. That is theplatform where a large population of people congregate. I am pleased to say that our proposal has been accepted. I
believe that, in addition to More Moore and More than Moore, More People will accelerate the creation of intellectual
value.

1

2022
Systems Design Lab, School ofEngineering,(VLSI Design and Education Center),
The University of Tokyo
Annual Report

C

O

N

T

E

N

T

S

Message from the Director of d.lab ………1

Chapter1

Introduction of d.lab…………………………………………… 4

Chapter2

Activity Report of d.lab……………………………………… 5

2-1
2-2
2-3
2-4
2-5

Advanced Design Research Division……… 5
Advanced Device Research Division………10
Platform Design Research Division………11
Platform Device Research Division………15
ADVANTEST D2T Research Department………19

Chapter3

Research in d.lab ………………………………………………… 24

Appendix……………………………………………………………………………… 42
A

Former VDEC contents………42
A-1 VDEC CAD Tools………42
A-2 Status of Chip Fabrication Support at Platform Design Research Division……44
A-3 Seminar………46
A-4 Venture Companies Related to VDEC………49

Chapter1

1

Introduction to d.lab

Chapter1 Introduction of d.lab

The VLSI Design and Education Center (VDEC)

kyo established the Systems Design Lab (d.lab) in Octo-

was established at the University of Tokyo in 1996. At

ber of 2019 and formed a strategic alliance with TSMC

the time of its founding, Japan’s semiconductor industry

a month later. d.lab was formed by establishing the Ad-

held a 50% share of the USD 50-billion global market,

vanced Design Research Division and the Advanced De-

and engineers who could hit the ground running were invice Research Division and adding them to the existinghigh demand. VDEC has since provided unparalleled,

Platform Design Research Division and Platform Device

outstanding education to develop many high-caliber en-

Research Division which had been operating VDEC

gineers for the semiconductor industry.

and the Takeda Clean Room. Subsequently in October

However, have these graduates of VDEC been able toof 2020, d.lab started an industrial partnership program

fully realize their potential? In the last quarter century,

which has grown to include more than 40 corporateeven though the global semiconductor market enjoyed amembers.

rapid 7% annual growth rate, Japan’s share continued toFurthermore, the Research Association for Advanced

shrink, falling to the current level of about 10% of a mar-

Systems (RaaS) was founded in August of 2020 to lay out

ket that is now approaching USD 500 billion.

the framework for the university to collaborate with both

The current semiconductor business is one of mass

the industry and the government. Using d.lab and RaaS

production of high volume, low margin general purpose

to realize a two-pronged strategy of open and closed col-chips. General purpose chips have been able to achievelaboration respectively, the university is actively promot-

large volumes because of the wide adoption of the voning cooperation between academia and society as well as

Neumann computer architecture constructed with thecollaborative creation with industry. Our research aims to

combination of memory and processor chips. While Ja-boost the time-performance of semiconductors, with tar-

pan led the world in memory device innovation, it lost the

get goals of 10x increase in both energy and development

business competition on capital investment.

efficiencies.

The mass production, mass consumption model has its

Japan is aiming to transition from the current indus-

limits. Because of the excessive burdens it places on thetrial/information society to Society 5.0, a human-centric

environment, the world is now facing an energy crisis. The

society where knowledge is value. In this knowledge-based

recent trend of applying AI to big data analysis is fuelingsociety, semiconductors will evolve from being a necessity

further growth in energy consumption.

of industry to the brain cell of society.

In the middle of this development, a game changer has

What strategy should the semiconductor industry pur-emerged. Recognizing that it is hard to compete by us-

sue to address this evolution? It is d.lab’s mission to finding general purpose chips procured from semiconductor

the answer.

makers, technology giants including GAFA have started
to develop their own specialized logic chips in-house.
In response to this paradigm shift, the University of To-

4

Chapter2

Activity Report of d.lab

2.1 Advanced Design Research Division
2.1.1

Division Overview

As noted in our last annual report, our original vision
was to not only create a platform for the dissemination ofsists of four professors, one associate professor, one lec-

the research accomplishment of d.lab, but also to turn ourturer, one project professor, and one senior fellow (joint

Mejirodai campus into a new venue for interaction andappointment included). Its goal is to enable the design oflearning. We were planning to host various events to en-

integrated circuits with both high energy efficiency andable program members to interact with renowned profes-

high design efficiency.

sors and students at the University of Tokyo, with univer-

In July 2021, NEC Corporation and the University ofsities and research organizations from around the world,Tokyo were selected to lead the research and development

and with other industrial executives and leaders, as wellof a new computing mechanism to accelerate data struc-as events to share information and knowledge from inter-ture processing, as part of a pilot study to identify R&D

national conferences and introduce and assess the mostchallenges for the Project for Innovative AI Chip andadvanced technologies from the likes of TSMC. Unfor-

Next-Generation Computing Technology Development

tunately, same as in FY2020, because of COVID-19, weof the New Energy and Industrial Technology Develop-

were forced to once again center our activities in FY2021

ment Organization (NEDO). The research is scheduledaround seminars held in the form of webinars. Our ac-

to complete by the end of June 2022.

tivities spanned almost the entire year from May 2021

In addition to its research effort, the Advanced Design
Research Division has two organizational responsibilities.

2-1
Chapter2 Activity Report of d.lab

The Advanced Design Research Division faculty con-to March 2022. Table 2.1.2 summarizes the seminars weheld in FY2021.

First, it operates the d.lab Partnership Program with help

We held our program kickoff meeting on May 19, 2021

from other d.lab divisions. Second, it founded and oper-

which also featured a keynote presentation. With 5G ser-ates the Research Association for Advanced Systems. The

vice having been rolled out in Japan as well, the focus offollowing section is the FY2021 report on these two op-

R&D in the country has been shifting to Post/Beyond

erations.

5G. Professor Akihiro Nakao of the School of Engineering, University of Tokyo, who has led Japan’s 5G tech-

2.1.2.

d.lab Partnership Program Activities

nology development, discussed what lies ahead beyond

The d.lab Partnership Program was launched in FY2020

5G and the role semiconductor will play in a talk entitledto establish an international center of knowledge-value“The Direction of Beyond 5G/Post 5G R&D and What

where system designers and members of the semiconduc-

We Can Expect from Semiconductor Development.” He

tor industry meet to exchange information and ideas andwas followed by Professor Tadahiro Kuroda, Director of

to engage in open discussion of collaboration between ac-d.lab, who provided an overview of d.lab and introduced

ademia and society. The Program aims to create a hub thatthe d.lab Partnership Program activities in FY2021 to-brings together ideas from system designers in industries

gether with their schedule.

including IoT, AI, 5G, automated driving, and healthcare,

On Jun 29, we held a seminar to report on the 2021

advanced semiconductor technologies such as advanced

VLSI Technology/Circuit Symposia which took place

CMOS processes and 3D integration technologies, as wellfrom Jun 13 to 19 earlier in the year. We reported on theas enablers of such technologies including materials andcircuit, system, process, and device technologies presented

manufacturing equipment. For FY2021, a total of 43 cor-at the Symposia. We also invited the Small and Medium

porations joined the Program. Table 2.1.1 contains the list

Enterprise Agency to the seminar to introduce the support

of FY2021 corporate members. We would like to thankprogram aimed at promoting the semiconductor industry.

these members again for their participation.

On Jul 21, we hosted another seminar to report on the

5

2-1

2021 IEEE 71st Electronic Components and Technology

Electronics Corporation in the third installment of ourConference (ECTC 2021). The conference is organizedtechnology exchange meeting.

Chapter2 Activity Report of d.lab

by the IEEE Electronics Packaging Society to provide a

On Dec 17, we organized an imec Day event where weforum for wide ranging discussion of the science and tech-heard directly from executives in charge of R&D at imec,

nology of packages, components, and microelectronic sys-which leads the world in the research and development

tems. It is one of the world’s long-established and leadingof ever advancing, ultra-high performance silicon systems.

international conferences, held for the 71st time last year.

The speakers introduced their efforts in extending CMOS

The technology program covered the latest achievement

device scaling and development of the most advanced 3D

in development across the full spectrum of packaging

system integration process and device technologies. It

technology. Its main topics included advanced packaging,

was an excellent opportunity for the audience to receive

modeling and simulation, photonics, interconnection,

firsthand information on the most advanced silicon sys-

material and process, reliability, manufacturing technolo-

tem technologies. Dr. Naoto Horiguchi, imec Program

gy, components and RF, as well as emerging technologies.

Director of Logic CMOS Device, discussed “CMOS de-

In our report, we focused on the latest trends and topics

vice scaling options toward N1 and beyond,” while Dr.

in advanced packaging, which is a mainstream technology

Eric Beyne, imec Senior Fellow, VP R&D, and Programfor our current activities, and hybrid bonding, which is a

Director of 3D System Integration, presented on “A 3D

next-generation core technology. The seminar was preced-

Integration Future: enabling continued system-level elec-

ed by an announcement of the “VDEC Refresh Seminartronic scaling.”

for Engineers, Course M” by Associate Professor Yoshio
Mita.

6

The theme of our seminar on Dec 22 was TSMC Day.
TSMC (Taiwan Semiconductor Manufacturing Com-

On Aug 18, we held our first technology exchange meet-pany, Ltd.), headquartered in Hsinchu City of Taiwan,

ing for our corporate partners, where some of our partners

is the world's largest and most advanced semiconduc-presented on their differentiating technologies and expec-

tor foundry. The company established the TSMC Japantation for future technology exchange. Presentation was

3DIC R&D Center in Japan in 2021. It is without ques-

made by six of our partners - Ushio Inc., Analog Devices,tion that, in addition to semiconductor scaling to achieveInc., Showa Denko Materials Co., Ltd., KIOXIA Corpo-

More Moore technology innovation, 3DIC technology,

ration, Semiconductor Energy Laboratory Co., Ltd., andwhich realizes More Than Moore technology innovation,

Toppan Inc. The goal of the technology exchange meetingis key to the future of the semiconductor industry. Center

is to promote collaboration between our corporate part-

Director Emoto and Technical Director Ichikawa present-

ners and with d.lab faculty members and students.

ed the mission of the R&D center in “Overview and in-

On Sep 22, the second installment of the technology

itiatives of TSMC Japan 3DIC R&D Center.” They also

exchange meeting was held. The six presenting corporate

provided an update on the latest technology development

partners were Dai Nippon Printing Co., Ltd., Alchip

in the company.

Technologies, Limited, Gigaphoton Inc, Nikon Corpo-

At the beginning of the year on Jan 19, 2022, we held

ration, DISCO Corporation, and Organo Corporation.

a seminar to report on IEDM2021. IEDM (International

On Nov 17, we held a special seminar “Gastronomy,

Electron Devices Meeting) is the world's top international

Robotics, and Semiconductor” in conjunction with theconference on device technology organized by IEEE. The

third installment of the technology exchange meeting. For

conference was held in a hybrid format – allowing boththe keynote presentation, Mr. Masahiro Fujita of Sonyin-person and on-demand attendance – from Dec 11 toGroup Corporation described the future that could be re-15. In our meeting, faculty members from d.lab provid-

alized with the advance in semiconductor, AI, and robot-

ed a summary of the conference and discussed the latest

ics. From a novel perspective of gastronomy, he discussed

trends in device technology, focusing on advanced CMOS

his research on using AI and robots to expand humandevice technology and material, non-volatile memory

creativity. The keynote was followed by the presentations

technology, computing technology, and 3D integrationof TOKYO OHKA KOGYO CO., LTD. and Renesas

technology.

purpose to specialized chips, against the backdrop of thevided a forum for the first time in the d.lab Partnershipunique energy crisis of the data society. The crisis is be-

Program for d.lab faculty members to introduce their re-ing spurred by the exponential growth in data and thesearch activities. The event was held in response to interest

increasing sophistication of AI processing. On the current

expressed by our partners in learning about the research of

trajectory, IT equipment alone is expected to consume

our faculty members, a year and a half after the program

close to twice the total available power of today by 2030,

started. It is hoped that the seminar will stimulate newand about 200 time the total available power of today by

activities such as collaborative research.

2050. It will be impossible to realize a sustainable future if

As the last event of our FY2021 seminar series, we helda meeting on Mar 23 to report on the 2022 International

digital transformation will consume so much energy as todestroy the earth’s environment.

Solid-State Circuits Conference (ISSCC2021). ISSCC is

Under such a condition, only those who can improve

the top international conference on IC technology held inenergy efficiency 10-fold can afford to increase computer

February. Starting with Professor Makoto Ikeda who has

performance 10-fold, or extend smartphone use 10-fold.

been for years the chair of ISSCC’s technology program,Compared to general purpose chips which are required tofaculty members from d.lab discussed the latest trends

handle all tasks, specialized chips achieve orders-of-mag-seen in the conference in the thriving area of machine

nitude improvement in energy efficiency by eliminating

learning processors, ICs enabling emerging computing

unneeded circuits. That is why specialized chips are in de-technologies exemplified by quantum computing, as wellmand. In addition, since AI processing utilizes neural net-

as 5G, AI, and game console ICs which are expected toworks which process data in parallel, it is difficult for vondrive the future of the semiconductor market.

Neumann architecture which is designed for sequential

For FY2022, we are considering organizing a mix ofprocessing to deliver adequate performance. As a result,

remote seminars and in-person events, while carefully

specialized chips are being developed around the world

monitoring the development of COVID-19. In addition

to serve as AI accelerators. Furthermore, the slowing of

to incorporating first-time events in our plan, we would

Moore’s Law is also providing a tailwind for specialized

like to continue to promote intellectual exchange between

chips.

our partners and the university, and among our partners
themselves.

2-1
Chapter2 Activity Report of d.lab

On Mar 2, we organized a d.lab Day event which pro-

Unfortunately, specialized chips development requires
special skills and cannot be easily undertaken by everyone.
The latest chips integrate more transistors than there are

2.1.3


Research Association for Advanced Sys-

people in the world. Development costs have skyrocketed

tems Activities

in recent years to approach $100 million. It will take evenWith preparation that started in FY2019, the Researcha team of several hundred designers several years to devel-

Association for Advanced Systems (RaaS) was established

op a specialized chip, which makes it difficult to keep paceon Aug 17, 2020. The founding members are the Univer-with today’s rapid technological advance.

sity of Tokyo, Toppan Inc., Panasonic Corporation, Hi-

In software development, bugs can be patched after thetachi, Ltd., and MIRISE Technologies. The goal of RaaS

fact. But hardware cannot be shipped unless it is com-

is to increase 10-fold the development efficiency of spe-

pletely error-free. Compared to software, hardware devel-

cialized chips, which are indispensable in a data-driven so-

opment is indeed hard and carries more risk.

ciety, by constructing a design platform for such chips and

If technologies similar to compilers used in softwareby adopting an open architecture for hardware design. In

development are available to chip development, in otheraddition, RaaS aims to increase 10-fold energy efficiency

words, if silicon compilers become a reality, we can expect

by researching and developing 3D integration technology

both hardware development cost and risk to drop. In ad-

and by stacking multiple chips manufactured in the latest

dition, more people can become hardware designer. Even-

7nm CMOS technology in a single package.

tually, as the open source culture takes root in hardware

At RaaS, we believe that the driver of the semiconduc-development and the supporting ecosystem expands andtor industry is once again swinging back from generaldevelops into a multi-layer network, mass collaboration

7

will become possible. When that happens, one will be able

able to complete the design and prototyping of a chip us-

to develop chips like writing software.

ing the latest CMOS technology with complicated design

Alan Kay once said that “People who are really serious

2-1

about software should make their own hardware.” Indeed,In the technology R&D, based on the NEDO projectsystem development requires both hardware and software

mentioned above, our efforts have been focused on thedevelopment.

establishment and implementation of technology for

Chapter2 Activity Report of d.lab

Our goal at RaaS is to democratize access to silicon

WoW (wafer-on-wafer) and CoW (chip-on-wafer) inte-technology. We aim to create a development platform togration using Cu-Cu low temperature bonding as part ofrealize agile authentic prototyping where prototypes canour direct bonding 3D integration technology develop-

be created rapidly by innovating silicon compiler technol-

ment (equipment and process development for WoW andogy to enable designing chips like writing software.

CoW).

Our technology goal is a 10-fold increase in both development efficiency and energy efficiency. We plan to improve development efficiency by creating an agile design
platform and adopting an open architecture. In addition,
we aim to increase energy efficiency through manufacturing chips in the most advanced CMOS process and implementation of 3D integration.
We provide semiconductors as a service, rather than sellthem as a product. It is the role of RaaS to develop thenecessary technologies to achieve that goal.
RaaS has planned to bring researchers from member
companies together at the Mejirodai International Village
campus of the University of Tokyo where they can conduct research while providing stimulation to each other.
Unfortunately, because of COVID-19, RaaS activities
have also been limited to center around remote work.
In FY2021, RaaS applied to and was accepted by the“Project for Research and Development of Enhanced
Infrastructures for Post 5G Information and Communications Systems / Development of Advanced Semiconductor Manufacturing Technology (b) Development ofAdvanced Semiconductor Backend Processing Technology (More than Moore)” of the New Energy and Industrial
Technology Development Organization (NEDO). The
development theme is “(b2) Implementation Technology for Edge Computing.” As a result, we were joined by
SCREEN Holdings Co., Ltd., DAIKIN INDUSTRIES,
Ltd., FUJIFILM Corporation, and Panasonic Connect
Co., Ltd. as new members of RaaS, adding technology
R&D to the system R&D which we have been pursuingfrom the beginning.
In the system R&D, RaaS completed the design of andtaped out our first chip in the 7nm process in FY2021. It
is our biggest accomplishment of the year where we were8

rules in less than a year since our inception.

Table 2.1.1 L ist of FY2021 d.lab Partner Members (in Japanese phonetic order)
Advantest Corporation
Analog Devices, Inc.
Alchip Technologies, Limited
Ushio Inc.
Organo CorporationKIOXIA Corporation
Gigaphoton Inc
Samsung R&D Institute Japan
Siemens EDA JapanJSR Corporation
Showa Denko Materials Co., Ltd.
Shin-Etsu Chemical Co., Ltd.
SCREEN Holdings Co., Ltd.
Sumitomo Corporation
Socionext Inc.
Sony Group Corporation
DAIKIN INDUSTRIES, Ltd.
Dai Nippon Printing Co., Ltd.
TDK Corporation
DISCO Corporation
Tokyo Electron Limited
TOKYO OHKA KOGYO CO., LTD.
Toppan Inc.
Nikon Corporation
IBM Japan, Ltd.
Cadence Design Systems, Japan
Nihon Synopsys G.K.
JEOL Ltd.
Panasonic Corporation
Panasonic Smart Factory Solutions Co., Ltd.
Semiconductor Energy Laboratory Co., Ltd.
Hitachi, Ltd.
Fujitsu Limited
FUJIFILM Corporation
Micron Memory Japan, K.K.
Mitsubishi Chemical Corporation
Mitsubishi Electric Corporation
MIRISE Technologies
Miraxia Edge Technology Corporation
Murata Manufacturing Co., Ltd.
Renesas Electronics Corporation
ROHM Co., Ltd.

Table 2.1.2
Date
5/19/2021

6/29/2021

8/18/2021

9/22/2021

11/17/2021

Title
Presenter(s)FY2021 d.lab Partnership Program Kick- Prof. Akihiro Nakao, School ofoff & Special Keynote
Engineering
Prof. Tadahiro Kuroda, d.lab
Business Restructuring Grant Program
Mr. Kento Tsuda, Deputy
Director, Small and Medium
Enterprise Agency, METI
2021 VLSI Symposia Report
Prof. Ken Takeuchi, d.lab
Prof. Makoto Ikeda, d.lab
Mototsugu Hamada, ProjectProf., d.lab
Prof. Toshiro Hiramoto, d.lab
Prof. Shinichi Takagi, d.lab
Masaaki Niwa, Senior Fellow,
d.lab
Seminar Announcement
Yoshio Mita, Associate Prof.,d.lab
ECTC 2021 Report
Toru Ogawa, RaaS Advisor
Takeshi Takagi, Principal Researcher, d.lab
Tadatomo Suga, RaaS Advisor
Masaaki Niwa, Senior Fellow,
d.lab
d.lab Partners Technology Exchange (1) Mr. Takafumi Mizojiri, Ushio
Inc.
Mr. Shogo Arita, Analog Devices, Inc.
Mr. Takahiro Tanabe, Showa
Denko Materials Co., Ltd.
Mr. Takaya Ogawa, KIOXIACorporation
Mr. Haruyuki Baba, Semiconductor Energy Laboratory Co.,Ltd.
Mr. Tatsuo Noguchi & Mr.
Keiichiro Uchida, Toppan Inc.
d.lab Partners Technology Exchange (2) Mr. Koji Ichimura, Dai Nippon
Printing Co., Ltd.
Mr. Hiroyuki Furuzono & Mr.
Eijiro Sasa, Alchip Technologies, Limited
Mr. Kenji Oishi, Gigaphoton
Inc
Mr. Yuta Komatsu, Nikon
Corporation
Mr. Shunsuke Teranishi, DISCO Corporation
Mr. Hiroshi Sugawara, Organo
Corporation
Special Technology Seminar “Gastrono- Mr. Masahiro Fujita, Sonymy, Robotics, and Semiconductor”
Group Corporationd.lab Partners Technology Exchange (3)2-1Chapter2 Activity Report of d.lab

7/21/2021

List of FY2021 d.lab Partnership Program Seminars

Mr. Satoshi Fujimura, TOKYOOHKA KOGYO CO., LTD.
Mr. Hirotaka Hara, Renesas
Electronics Corporation

9

12/17/2021

imec Day

12/22/2021

TSMC Day

1/19/2022

IEDM2021 Report

3/2/2022

d.lab Day

3/23/2022

ISSCC2022 Report

Dr. Naoto Horiguchi, imec
Dr. Eric Beyne, imec
Mr. Yutaka Emoto, TSMC
Japan
Mr. Kinya Ichikawa, TSMC
Japan
Prof. Toshiro Hiramoto, d.lab
Prof. Shinichi Takagi, d.lab
Masaharu Kobayashi, AssociateProf., d.lab
Prof. Ken Takeuchi, d.lab
Takeshi Takagi, Principal Researcher, d.lab
Prof. Shinichi Takagi, d.lab
Prof. Makoto Ikeda, d.lab
Prof. Ken Takeuchi, d.lab
Yoshio Mita, Associate Prof.,d.lab
Masaharu Kobayashi, AssociateProf., d.lab
Prof. Makoto Ikeda, d.lab
Prof. Ken Takeuchi, d.lab
Tetsuya Iizuka, Associate Prof.,d.lab
Mototsugu Hamada, ProjectProf., d.lab
Atsutake Kosuge, Lecturer, d.lab

2-2
Chapter2 Activity Report of d.lab

2.2 Advanced Device Research Division
Advanced Device Research Division is working for thetion and Communication Technology Infrastructuredevelopment of three-dimensional (3D) integration tech-

Reinforcement Research and Development Project /nology and advanced device technology aiming at ten

Development of Advanced Semiconductor Manufactur-

times higher energy efficiency of semiconductor systems

ing Technology (Subsidy)", the Research Association forin the data-driven systems.

Advanced Systems (RaaS) which d.lab is the headquar-

In 2021, we launched a new project of the next-generation 3D integration technology.

technology, proposed "Direct 3D Stacking Technology

Recently, the computing technology for processing

Development (Development of Equipment and Processes

large amount of data is becoming more important and thefor WoW (Wafer on Wafer) and CoW (Chip on Wa-

energy consumption by frequent data transfer betweenfer) )", and this proposal was adopted. Currently, we arememories and processors is a severe problem. To solve thisworking with RaaS member companies to develop andproblem, the direct bonding 3D stack technology, where

implement chokepoint technologies related to WoW andthe data transfer distance is shortened by direct bonding

CoW bonding technologies using low-temperature hy-of chips or wafers, has attracted much attention.

brid bonding of Cu-Cu.

This year, in the NEDO project "Post 5G Informa-

10ters of technology research association on 3D integrated

2.3 Platform Design Research Division

2.3.1

Overview of Platform Design Research Di-

sions to improve the convenience of participation. In addi-

visiontion, in view of the current situation where the tool-chainsof various companies are becoming more complex and it

Education Center (VDEC) at the University of Tokyo has

is difficult to fully use the introduced tools, lectures on the

been developing projects that contribute to integrated cir-tool-chains recommended by each tool vendor were also

cuit design education at universities and technical colleges

held in conjunction with the individual tool seminars.

in Japan, based on the three major roles: ”spreading the

From the end of FY2019, we received permission fromlatest information on VLSI design and education,” ”pro-each EDA vendor to use EDA tools from home, to avoid

viding licenses of CAD tools,” and ”supporting on VLSI

delay&slowdown in integrated circuit design research andchip fabrications for academic use.” On October 1, 2019,education in Japan.

VDEC has been re-organized into Systems Design Lab(d.lab), Graduate School of Engineering, the Universityof Tokyo as part of an organizational restructuring aimed

 tatus of Education at Platform Design Re2.3.2 S
search Division

at strengthening integrated circuit related activities in the

The LSI Design Flow Seminar is designed to educate

University of Tokyo's semiconductor integrated circuit-re-the basic concepts of LSI design and to provide hands-

lated activities. The Platform Design Research Division of

on experience of practical design examples using multiple

d.lab continues to carry out the functions of the VDEC

CAD tools. For this purpose, VDEC has been organizing

and continues “VDEC activities” seamlessly. Here, theLSI design education seminars as well as “Refresh Sem-

outline of “VDEC activities” of the FY2021 is reported

inar” for re-education programs for engineers. “Analog

below.

Design Course”, and “RF Design Course,” were held

The missions of VDEC are for advancement of re-from June to September. All of these courses are experi-

searches and education on LSI design in public and pri-ential education courses with exercises, and experienced

vate universities and colleges in Japan and send many dis-

instructors from major universities are invited as lecturers.

tinguished VLSI designers into industry. After 25 years of

In addition, “Transistor Level Design in VDEC Environ-

VDEC establishment, educations on CAD software, LSI

ment (Course VT)” and “Digital Design Methodology indesign and design flow in universities have been well es-

VDEC EDA Environment (Course VD Course VT)” andtablished. On the other hand, advancement on nano-me-“VDEC Digital Design Methodology Course (Course

ter CMOS technologies forces design flow and CAD soft-VD)” are conducted for designers in universities. The

ware complicated. We have been continuing CAD tool

“Refresh Seminar” are all held online in FY2021, and as aseminar by the lecturers from EDA vendors for twice a

result, the number of participants has increased compared

year. We hold the seminar in VDEC and provide distanceto previous years.

learning through video streaming. We expect spread of the

In addition to these seminars, VDEC holds the “VDEC

up-to-date LSI design methodology by using CAD tools.

Designers’ Forum” once a year, mainly for young faculty

In order to make it more convenient for the partici-

members and students. This is a workshop-style meeting,pants, the seminars have been held only in Tokyo since

where participants bring their design cases and exchange

2009, and at the same time, the seminars have been

their successes and failures, in addition to invited lectures

broadcasted to individual participating lab. The VDEC

from companies and universities. In FY2021, the VDEC

expects that the latest CAD use-case will be shared among

Designer Forum had been held online. Since FY2011, thelabs through the seminar organized by VDEC, and will be“IEEE SSCS Japan Chapter VDEC Design Award” hasa trigger to spread the technology nationwide. In FY2020,

been presented as an award for VDEC activities. The final

all seminars will be conducted online. Some items were

judging and awarding of the “IEEE SSCS Japan Chapter

conducted in the form of on-demand plus live Q&A ses-

VDEC Design Award” has been held at VDEC Designers’

2-3
Chapter2 Activity Report of d.lab

Since its establishment in 1996, the VLSI Design and11Forum since 2011, and in 2021, the IEEE SSCS Japan

2-3

2.3.4

Report on AI Chip Design Center

Chapter2 Activity Report of d.lab

Chapter VDEC Design Award will be presented to Mr. R.

VDEC and the AIST have been jointly commis-

Okada of Nara Institute of Science and Technology. Threesioned by NEDO to develop a common platform

VDEC Design Award Excellence Awards, (Mr. R. Okada

technology for accelerating AI chip development(Nara Institute of Science and Technology), Mr. A. Mat-

under the “Innovation Promotion Project for Accel-

suoka(The University of Tokyo), and Mr. H. Sakai(Tokyoerating AI Chip Development / R&D Item 2: Devel-

University of Science)), and three VDEC Design Award

opment of Common Platform Technology for Accel-

Encouragement Prizes (Mr. T. Tsujimura(Nagoya Univer-erating AI Chip Development” since 2018. In thissity), Mr. K. Sahara(Tokyo University of Science), andproject, we have established an EDA utilization and

Y. Mori(Nara Institute of Science and Technology)), anddesign environment for venture companies and small

three VDEC Design Award Commendation Prizes forand medium-sized enterprises(SMEs) in Japan, andIdea Contest (K. Kawahara(Tokyo University of Science),

are working as an “AI chip design center(AIDC)”. In

S. Mitsuno(the University of Tokyo), and T. Fukush-

this activity, in addition to the introduction of EDA

ima(Tokyo Denki University)).

tool licenses that allow venture companies and small

Although the educational system through such semi-

and medium-sized companies to prototype up to en-nars and forums has enabled students to learn the basics

gineering samples, we have introduced IP for 40nm

of LSI design, they still face various difficulties in actualand 28nm, and are also providing a large-scale, high-

LSI design situations. For beginners, setting up the CAD

speed design and verification environment using asoftware is the biggest problem. Even after setting up the

hardware emulator, which was introduced with asoftware, they are often baffled by the “difficult error mes-

subsidy from the Ministry of Economy, Trade andsages” issued by the CAD software. VDEC users can regis-

Industry at the start of this project. In FY2020,

ter for the “CAD mail group” and the “Prototyping Tech-

we have designed a SoC platform with NoC, PCIe,

nology User Group” on the VDEC website, where they

DDR4, etc., and multiple functional IP cores, andcan post their questions and ask for help. The registered

taped out the platform as a SoC with multiple AI IP

users of the mail groups are not obligated to respond, butcores designed by multiple users, and after almost

in most cases they can get help from experienced users

1-year delay, we have received assembled chip in

within a few hours or days. We hope that you will takethe beginning of Jan. 2022, and after one week weadvantage of this system to help solve your problems.

could evaluate most of SoC functionalities and by
the end of March 2022, almost all of Ips got fully

2.3.3

Publications related to Platform Design Re-

verified. In order to further strengthen this activi-

search Divisionty, we are accelerating our research by establishing

Figure 2.4 shows the use of the VDEC facility inthe "AIST-The University of Tokyo AI Chip Design

the published literature related to VDEC. It canOpen Innovation Laboratory" (AIDL) in the Takeda

be confirmed that CAD software is widely used in

Building, Asano Campus, The University of Tokyo

writing papers. Since CAD software is often usedon September 1, 2019.

not only in chip design but also in the preparation
stage of chip prototyping, its contribution as a tool
to demonstrate the basic idea of the research is alsosignificant.

12

Table 2.3.1 Chip fabrication schedule【CMOS 1.2μｍ 2P2M】 On-Semiconductor(Former Motorola Japan)
Chip application deadline
2022#12022#22022/7/4
2023/1/10

Design deadline
2022/9/26
2023/3/27

Chip delivery
2022/12/19
2023/6/26【CMOS 0.18μｍ 1P5M(+MiM)】 Rohm
Chip application deadline
2022/4/4
2022/6/13
2022/8/1
2022/12/5

Design deadline
2022/6/27
2022/9/5
2022/10/24
2023/2/27

Chip delivery
2022/10/14
2022/12/23
2023/2/11
2023/6/16【SOTB CMOS 65nm】
Chip application deadline

Design deadline

Chip delivery

2022 #1 2022/6/13

2022/7/25

2023/1/21

2022 #2 2023/1/23

2023/3/6

2023/8/26

2-3
Chapter2 Activity Report of d.lab

2022 #1
2022 #2
2022 #3
2022 #413

2.3.5

Plan for FY 2022 “VDEC Activities” of Platform Design Research Division【Chip fabrication services】

We will continue chip fabrication services for 0.18μm
In FY2021, we will continue the VDEC Activities foracademics as before.

CMOS by Rohm, 0.8μm CMOS by On-semiconductor-Sanyo, SOTB 65nm CMOS by Renesas Electronics,
and IHP SiGeBiCMOS 0.18um as the regular services.

2-3【Design related information dispatching/Seminar】

Chapter2 Activity Report of d.lab

We will continue holding the following seminars: (1)In addition to the above. We will continue to devel-

CAD tools seminars which have been continued since

op an "AIDC” activities, in collaboration with AIST. We

1997, (2) “Refresh seminar” since 1998, (3) “Designer’will introduce a logic emulator for large-scale AI digital

Forum” since 1997. We will also continue seminars forchip design verification, and maintain and operate EDA

LSI tester usage at VDEC and sub-centers, workshops on

licenses for industrial applications. The main objective of

LSI testing technologies initiated by D2T.

this project is to provide small and medium-sized venturecompanies with a development environment for AI chip

【CAD tool support】

design, evaluation, and verification in order to accelerate

We will continue Cadence tools, Synopsys tools andthe development of AI chips, but we also plan to im-

Mentor tools as the main stream design tools. We will

prove the environment for use by universities in order tocontinue analog RF design environment, GoldenGate

promote university-originated companies in the field ofand ADS by Agilent, C-based design environment, BachC

AI-related integrated circuits.

by Sharp. In addition, we continue trial of several CAD
tools, such as layout platform, Lavis by TOOL. Design
debugging platform from SpringSoft has merged into Cadence tools and will be continued.

Fig. 2.3.1

14

Trends of number of papers through VDEC activities.

Fig. 2.3.2

Number of papers related to VDEC facilities.

2.４

Platform Device Research Division

2.4.1  Mission

the end of 20th century. However, due to the technology
trends towards advanced fabrication over larger-scale wa-

viding every researcher with three essential elements forfers, it has become almost impossible for a research groupresearch on new devices. The division is with around 30

to purchase and maintain the cutting-edge fabrication

staffs, powered by Dr. Yoshio Mita, the playing division

machine line, in the 21st century. Originally, it was impos-

director who himself actively performs experiments in thesible for every research group in universities, companies,

Cleanroom as a leading researcher, and operated in collab-

research institutes, and NPOs, to exclusively “own” suchoration with related departments (such as Institute of En-

large-scale facility and necessary budget by themselves; If

gineering Innovation, Electrical Engineering and Infor-

researchers wish to “cooperate” with the other research-mation Systems, and Mechanical Engineering) in terms of

ers in a platform, which is equally open to everybody,human and budget resources. Especially in the year 2021,

they can “effectively own” the most advanced “open plat-

thanks to the invaluable help of Prof. Yuji Suzuki, viceform”, and thereby the cutting-edge research activities

dean for education, we could launch new subcontracting

can be held anywhere in Japan. This is the principle ofsystem to the Ph.D student as “excellent Ph.D”, in orderd.lab’s open device platform, which is in fact a lateral ex-

that they help the team by mentoring all junior members

pansion of “shared economy model in VLSI design andon behalf of experienced senior member in TakedaSCR.

fabrication” to micro-nano fabrication and measurement

Research in emerging fields of semiconductor electronics

research field, originally established by VDEC for Japandevices (such as integrated circuits), sensors and microsys-

in 1996.

tems requires three essential elements: (1) fabrication ma-

Towards that end, d.lab Platform Device Research Divi-chines with stupendous amount of budget, (2) rich accu-

sion takes full advantages of spaces (of its own and of open

mulation of fabrication technology knowledges, and (3)rental) in Takeda Sentanchi Building. The building was

research capability to develop new technologies requiredinaugurated in December 2003, thanks to the enormous

for new devices. In Japan, these three elements had been

donation in 2001 from Mr. Ikuo Takeda (founder of Ad-

prepared and kept in an individual research group until

vantest) to the faculty of engineering (Dean was Professor

Fig2.4.1

2-4
Chapter2 Activity Report of d.lab

D.lab platform device research division aims at pro-Development of Takeda Sentanchi Supercleanroom

15

2-4
Chapter2 Activity Report of d.lab

Fig.2.4.2

List of equipment under d.lab Platform Device Research Division

Hiroshi Komiyama) as well as VDEC (director was Professor Kunihiro Asada). In the building, a 600m2-squaresupercleanroom including “official ISO3 (a.k.a. federal
class 1. Once measured as ISO1)” area (Fig.1). The cleanroom and affiliated experimental rooms are equipped with
cutting-edge nanofabrication and measurement machines,
total valued over 3.9 billion yens (33M euros). The users
can openly use such nice machines really inexpensively.
Over 70 apparatuses are openly accessible (Fig.2), including, “world’s fastest” large-area direct electron beam(EB) writing machine Advantest F5112+VD01, which
has been donated according to the wise decision of Mr
Ooura, a chairman of Advantest, fine EB writer Advantest F7000S-VD02 and Silicon Deep Reactive Ion Etchingmachine SPTS MUC-21 ASE-Pegasus, both purchased
by Japanese government’s supplemental budget (known
as Abenomics, the first arrow), and the scanning electron
microscope (SEM) Hitachi Regulus SU8230 that provides highest-class resolution among those obtainable byresearch laboratory. The machines can cover most of theresearch steps in nanotechnology, which are cleaning, film
deposition, lithography, etching, packaging and characterization. Not all apparatuses are yet installed in Takeda
Building, however due to nationwide platform network,
researchers can access in another equivalent nanofabrication platform center(s).

162.4.2 “Takeda Sentanchi Supercleanroom” cooperation platform

defined by corresponding laws and ordinances. The yearly operation cost of 300 million yens are composed of

The platform is called “Nanotechnology Platform UTo-

equipment installation, electricity and water fees, mainte-

kyo Nanofabrication site” according to the MEXT’s na-

nance, and personnel. National Universities have acquired

tional project, or simply “Takeda Sentanchi Cleanroom”

budget flexibility since the date of private agency statuses.

(in short, Takeda CR). The platform is widely open to

It helps a lot to ensure staff employment as well as small

those who share the “value of cooperation”. The mostto middle sized equipment acquisition.
Platform Device Research Division staffs acquire im-must not be considered as a simple outsourcing agent;plicit information for future fabrication technologies, due

being understood the value of “own help, mutual help,

to daily help to massively parallel research projects. The

and public help”, the participant can drastically minimize

team develops technologies with high demand and uni-

costs (personnel, budget, and time), which should haveversality and make them accessible by publishing papers.

otherwise been totally covered by each researcher, and canMoreover, taking full advantage that PDRD is a divi-

directly jump into advanced research. Key Performancesion of d.lab, the team has been developed for over 10

Indicators of such benefits are as follows: over 7.7 billion

year, a reliable research scheme for integration of LSI andyens for installation cost of building and equipment, over

MEMS devices, known as “Integrated MEMS research

300 million yens for yearly operating cost, and reduction

domain”. As summarized in a peer-reviewed journal [1],of over 20 years’ leading time to acquire know-hows inthrough VDEC function of d.lab “LSI foundry”, a specif-

advanced fabrications. These benefits have attracted many

ic LSI circuit silicon wafers are fabricated through com-

research groups. Since ten years, the number of researchpany (such as Phenitec Semiconductor). Then the wafer

groups who sent us the letter of consensus exceeded 456.

is “post”-processed in an open nanofabrication platform

Over 900 members are yearly subscribed (including re-including Takeda Sentanchi Supercleanroom. The criticalnewal and new subscription). In year 2020, over 550

advantage of such scheme is that researchers can “easily”

persons have used cleanroom and their total access countobtain silicon wafers with transistor circuits, which has

exceeds 16,000.

been really difficult for university cleanrooms to acquire

Operation principle is also “own help, public help, andreliability, and can fabricate by themselves specific MEMS

mutual help”. Budgetwise, each term of the principlethat no foundry company can provide. Namely, research-corresponds to: (1) User’s payment to participate budget

ers can produce “World’s first functionality” with “World’s

acquisition (charged according to the officially-approved

highest quality”. Such a flexible scheme is unique in thed.lab’s internal rule), and (2) national budget allocatedworld. Yearly one multi-chip fabrication is performed

to d.lab platform research division, MEXT Nanotech-(pre-fixed participants upon request), including collabo-

nology Platform project, and (3) major laboratories (whorative research works with industries.

rent space in Takeda Building for their research work) as[2] Y. Mita et al., Japanese Journal of Applied Physics,

well as research projects with d.lab operation laboratories

56, p. 06GA03, 2017 (2017) DOI: 10.7567/JJAP.56.

(such as Mita Lab). Of course, each budget category is

06GA032-4
Chapter2 Activity Report of d.lab

important understanding for every user is the platformrighteously dispensed in perfectly following its own rule17

2.4.3

Activity Report 2021 of Platform Device Re-

the end of financial year Reiwa 3rd (31/Mar/2022);

search Division

MEXT has started another national project, by of-【Prize】The MEXT Nanotechnology Platform Project

2-4
Chapter2 Activity Report of d.lab

gives prizes for good usage of platform. Every year, sev-

for digital transformation (DX) in materials includ-eral projects are selected by specialists’ award committee,

ing MEMS devices. The name of the new project

among solicited candidates selected from over 3000 re-

is called “Material DX”. Structurally speaking, ma-search project reports. Among the projects that PDRD

terial DX have adopted “research domain hub-and-have solicited, we won again the 1st prize “Best use award”

spoke” system, in contrast with Nanoplat’s “technol-on “Silicon MEMS monolithic SPR spectroscopy sensor

ogy domain system” composed of characterization,by using plasmonic structure” (Fig.3). Note that our di-nanofabrication, and material syntheses.

vision has been awarded consecutively for three years, in-d.lab PDRD has been merged with Nano Engi-

cluding two last years as the best use award. The awarded

neering Center of Institute of Engineering Innova-group are UEC Tetsuo Kan’s group. It is about MEMS

tion and Information Technology Center to form

devices that can make selective spectroscopy enhanced bya strong hub team, under presidency of Professor

nanostructure.

Yuichi Ikuhara. The team has been highly appreciat-【No infection case & no decrease in platform

ed by the evaluation committee and was granted foruses】In the year 2021, we also continued strict but

10-year project’s “hub” site. Following the year 2020,

acceptable anti-pandemic protocol. Due to the in-

MEXT has granted us a big supplemental budget forfluence of Omicron variant, which is less toxic but

our proposal to enhance performance of our clean-much more contagious, we identified three positive

room that will take place at mid-FY2022. Also, d.labcases (of maintenance company as well as user), but

was awarded by MEXT’s “Next generation X-nics re-zero transfection has been obtained.

search site” and also supplemental budget has been

【Post-Nanotech platform national project】The

granted. In total, we have identified 4500 millions

major part of “public” help for cleanroom has beenof yens to complete competitive Cleanroom; yield-

covered by MEXT Nanotechnology platform. Nano-

ing 300M yens per year if we renew everything at

technology platform project will end his period atevery 15 years.

Fig.2.4.3

18

ficially stating “use heritage of nanotech platform”,

Group photo after award ceremony

2.5

ADVANTEST D2T Research Department

2.5.1

Introduction of ADVANTEST D2T Research

testing is one of the most practical research topics in the

Department

industry. On the basis of these activities, our final goal is
to become a center of excellence of VLSI testing in Japan.

2.5.1.1 Aim of establishing ADVANTEST D2T Department (former D2T research division)

D2T research division has spent a total of 12 years todevelop the first (Oct. 2007 – Sep. 2010), second (Oct.
2010 – Sep. 2013), third (Oct. 2013 – Sep. 2016), andin VDEC in October 2007. As the name suggests, it isfourth (Oct. 2016 – Sep. 2019) phases. D2T activity

financially supported by ADVANTEST Corporation.

report of 2021 presents the last financial year, i.e., Oct.

The aim of establishing ADVANTEST D2T research2020 – Sep. 2021, of the fifth phase. Systems Design

division was to promote the research and education en-

Center, School of Engineering, the University of Tokyo

vironment with regard to VLSI testing in all universities

has been established in Oct. 2019, and Advantest D2T re-and colleges in Japan. “D2T” signifies that we consider

search department is within the center. D2T research de-

not only design but also testing. Through our activities,

partment primarily focuses on D2T research activities andwe hope to provide expertise in design and testing for theeducation. The fifth project phase (Oct. 2019 onwards) ofindustry. In addition, we are exchanging researchers with

D2T project was commenced by courtesy of ADVANT-

those of other universities and research institutes both in

EST Corporation. The details pertaining to the activities

Japan and overseas. Moreover, D2T research division isof our group are presented in the following sections.

2-5
Chapter2 Activity Report of d.lab

ADVANTEST D2T research division was establishedsuitable for collaborations with the industry because VLSI

19

2.5.1.2 Members of ADVANTEST D2T Division

2-5

2.5.2.

Report of the 16th D2T Symposium

Project Professor

Masahiro Fujita

Postdoctoral research fellow

Zolboo Byambadorj

2021, online (a part of the talk is hybrid). This year, we

Project Lecturer

Akio Higo

invited the following overseas lecturers to introduce their

Researcher	
Koji Asami (Advantest

Chapter2 Activity Report of d.lab

Laboratories Ltd.)
Researcher	
Masahiro Ishida (Ad-The 16th D2T Symposium was held on September 15,

research on biosystems, BioMEMS, Memory, 3D integration, and Design Optimization, AI chips: President of
the University of Tokyo, Professor Teruo Fujii, director ofvantest Corporation)d.lab, Professor Tadahiro Kuroda, Professor Wayne Luk

Researcher

Takahiro Yamaguchi

from Imperial College London, Professor Alex Orailoglu

Assistant Clerk

Makiko Okazaki

from University of California, San Diego, Fellow of the
University of Tokyo and Professor Tim Cheng from Hong
Kong University of Science and Technology, Professor
Mehdi Tahoori from Karlsruhe Institute of Technology,
Dr. Shin-ich Ouchi from AIST for their distinguishedresearch topics. Dr. Zolboo presented the recent D2T research activities.
We sincerely appreciate each participant for their contributions to the symposium. We look forward to greater
participation again at the next symposium.

20

16th D2T Symposium Program ONLINE

September 15, 2021

10:00 Opening Remarks
Tadahiro Kuroda (Director, d.lab, School of Engineering, the University of Tokyo)
Yoshiaki Yoshida (President & CEO, ADVANTEST CORPORATION)
10:15 Session 1 (Chairpersons: Yoshio Mita, Masahiro Fujita, d.lab, the University of Tokyo)
Microfluidics for Cellular and Molecular Systems
Teruo Fujii, President (the University of Tokyo)
Meta-programming Strategies for Multi-Target Design Optimisation
Wayne Luk, Professor (Imperial College London)
12:00 Lunch

2-5

13:00 Session 2 (Chairperson: Tetsuya Iizuka, d.lab, the University of Tokyo)
Time Performance Improvement by Agile Design and 3D Integration
Tadahiro Kuroda, Professor (d.lab, the University of Tokyo)
Design of Reliable and Efficient Deep Learning Processing Systems
Alex Orailoglu, Professor (University of California, San Diego)
14:45 Session 3 (Chairperson: Makoto Ikeda, d.lab, The University of Tokyo)
Ratio based Resistive Memory Cells for Low Error Rate and High Energy Efficiency
K.-T. Tim Cheng, Professor (Hong Kong University of Science and Technology and Fellow, the University of Tokyo)
AI-Accelerator Proof of Concept by a Multi-IP Chip ProjectShin-ichi O'uchi (S. O'uchi)
Laboratory Team Leader, AIST-UTokyo AI Chip Design Open Innovation Laboratory (AIDL)National Institute of Advanced Industrial Science and Technology (AIST)
16:30 Session 4 (Chairperson: Masahiro Fujita, d.lab, The University of Tokyo)
Recent D2T research department progress
Akio Higo, Lecturer (d.lab, The University of Tokyo)
Analysis and Calibration Techniques of Modulated Wideband Converter for High-Precision Sub-Nyquist Sampling System
Zolboo Byambadorj, Doctoral research fellow (d.lab, The University of Tokyo)
Computing Paradigms based on Flexible Inorganic Printed Electronics
Mehdi Tahoori, Professor (Dependable Nano-Computing at Karlsruhe Institute of Technology)

Chapter2 Activity Report of d.lab

18:00 Closing Remarks
Masahiro Fujita (d.lab, School of Engineering, The University of Tokyo)

21

2.5.3

Research Activity Reports of the ADVANTEST D2T Research Department

High-Resolution

Analog-to-Digital

Converter

Based on Stochastic Comparators
2-5

prove the characteristics. We measured and verified
characteristics by the Bluetooth and LTE waveforms

Chapter2 Activity Report of d.lab

Takahiro J. Yamaguchi, Akio Higo, Tetsuya Iizuka

that used the device under test for RF communica-Thistion, and this project was closed by the end of Marchproject

aims

toexplorestochastic

analog-to-digital converter (ADC) architectures.

2021.

Process variations, together with many factors suchas variations in voltage or temperature, lead to mis-

5G multi-channel/millimeter-wave signal meas-

matched design parameters that produce input-re-urement

ferred offsets and hence cause non-linearity andKoji Asami, Zolboo Byambadorj, Ryogo Koike,missing output codes in an ADC. Instead of at-

Sheng Guo, Nguyen Ngoc Mai-Khanh, Akio Higo,

tempting to suppress such process variations as in

Tetsuya Iizuka, Masahiro Fujita

conventional ADC, the stochastic ADC approach

We study and develop fundamental research to

exploits the stochastic properties of many compara-measure the millimeter-wave signals in an over-the-tors such as random variation of input-referred offset

air environment. In this financial year, we designed

and Gaussianity of the internal noise to enhance theand fabricated the planar monopole probe anten-

quantization accuracy. However, the published pa-

na with a high spatial resolution for the near field

pers only show that stochastic ADCs are noisier than

measurement of the millimeter-wave antenna. We

the conventional flash ADCs [TCAS-I, Vol. 57, no.

developed algorithms for the near-to-far-field trans-

11, 2010]. The central limit theorem can be applied

formation and the identification of probe character-to discrete type RVs such as a group of comparators

istics. We have established the experimental setup

and their sum [A. Papoulis 2000]. It shows that forfor millimeter-wave measurement and are currently

this discrete RV, many more terms are required inproceeding the verification and the performance im-

the sum before going convergence to a Gaussian dis-

provement by using actual antennas for 5G.

tribution [S. L. Miller 2004]. These results in theadequate number of bits (ENOB) of the stochastic

High-Speed and High-accuracy Multi-Pin Timing

ADC are represented by log44B [TCAS-I, Vol. 57,

CAL for ATE

no. 11, 2010], being smaller than the ENOB of theMasahiro Ishida, Hidaka Otsuka, Tetsuya Iizuka,

conventional flash ADC, which is given by log22B.

Toru Nakura, Zule Xe, Akio Higo, Masahiro Fujita

An approach for robustly detecting level-crossing

Automatic test equipment (ATE) for Semicon-time using stochastic median is investigated to ad-

ductors has thousands to tens of thousands of signal

dress randomness issues and achieve accuracy.

input and output channels. It requires timing calibration (CAL) to correspond the test signal output's

22

High-Performance Analog-to-Digital Conversion

timing to the device under the test (DUT) and theUsing the Wideband Spread Spectrum and Its Ap-

comparison timing of the signals output from theplications

DUT. This research focuses on a high-speed andKoji Asami, Zolboo Byambadorj, Akio Higo, Tetsuya

high-accuracy multi-pin timing CAL method ap-

Iizuka, Masahiro Fujita

plicable to ATE. In this financial year, we discussed

We investigate the compression sampling methodand determined the circuit scheme to realize ourto measure low-cost RF devices for IoT and otherresearch goal that the target accuracy of the timing

applications. A 4-channel MWC circuit was fabri-

CAL is at 1 ps. Then, we designed the test elementcated, and we verified our proposed methods to im-group (TEG) chip for LSI shuttle services in VDEC

2.5.4 P ublication
Journal[1] Zolboo Byambadorj, Koji Asami, Takahiro J.
Yamaguchi, Akio Higo, Masahiro Fujita andWe discussed the challenges for developing the tim-

Tetsuya Iizuka, “A Calibration Technique foring CAL devices, and we decided to fabricate TEG

Simultaneous Estimation of Actual Sensing

for evaluating the CAL accuracy degradation by

Matrix Coefficients on Modulated Wideband

the power variation and thermal environment. We

Converters,” IEEE Transactions on Circuits

designed the TEG layout and LSI circuit using theand Systems-I: Regular Papers, vol. 67, no. 12,

TSMC 65 nm CMOS process, and we confirmed

pp. 5561 - 5573, Dec. 2020.

the target accuracy of 1 ps by simulations. Then, we
taped out the design.
function at d.lab design platform research division. We discussed the challenges for developing thetiming CAL devices, and we decided to fabricate
TEG for evaluating the CAL accuracy degradationby the power variation and thermal environment.

2-5
Chapter2 Activity Report of d.lab

function at d.lab design platform research division.

We designed the TEG layout and LSI circuit using
the TSMC 65 nm CMOS process, and we confirmed
the target accuracy of 1 ps by simulations. Then, we
taped out the design.

23

Chapter3

Research in d.lab

Kuroda and Kosuge Laboratory(http://www.kuroda.t.u-tokyo.ac.jp/index.html）

TCI: ThruChip Interface
3

T. Kuroda, M. Hamada, A. Kosuge, T. Shidei, M. Oka-

Chapter3 Research in d.lab

da, Wai-Yeung Yip, K. Shiba, T. Omori

We are developing a wireless tag that integrates
an antenna and wireless circuits on a tiny chip lessthan 1 mm square and combine it with an intelligent
reader to pursue an extremely low-cost IoE (Internetof Everything) system. This year, we developed a new

TCI is a 3D integration technology that employs

collision avoidance function that deterministicallyinductive coupling between coils created with on

avoids collisions based on received signals by uti-

chip metal line patterns for data communication

lizing adiabatic circuits. We developed a low-power

across stacked chips. It realizes the same or better

RFID tag circuit using TSMC 0.18m CMOS process

performance as TSV (Through Silicon Via) but at aby using our proposed the adiabatic logic circuit andlower cost. This year, we presented research papers

presented our experimental results at A-SSCC'21.

on TCI-based 3D SRAM stacking technologies in-

We have also developed a new bonding-less mount-cluding (a) circuit technology for low-power com-

ing technology in which the coil mounted on theputation, (b) area efficient coil-design, and (c) com-

RFID tag is coupled to the coil on the PCB. A test

puting architecture and AI processing algorithms tochip was developed and evaluated using TSMC

use 3D stacked SRAMs efficiently. We presented our

0.18um CMOS process, and papers were presented

achievements at ESSCIRC’21 and EDAPS’21.

at SSDM'21, ASP-DAC'21, and JJAP’22.

TLC: Transmission Line Coupler

Wired-logic AI Processor

T. Kuroda, M. Hamada, A. Kosuge, Y. Hayashi, Ximing
Wang

T. Kuroda, M. Hamada, A. Kosuge, K. Shiba, YaoChung Hsu, R. Sumikawa, F. Hondo

TLC is a data communication technique between

We are studying non-von Neumann AI proces-

circuit boards by utilizing electromagnetic couplingsors focusing on wired-logic to reduce power con-

between transmission lines on them. It solves the is-sumption. The area efficiency is a bottleneck of thesues in conventional connectors such as wearing, re-wired-logic processor and it is significantly degradedliability against vibration, and impedance mismatch,due to the need to implement a huge number of el-realizing wireless connectors. This year, throughements on a chip. Therefore, we have developed two

joint research with a company, we conducted re-

new technologies: (1) a technology to optimize thesearch and development of compact and high-den-

network by removing unnecessary neurons and syn-sity TLC mounting technology for connecting pack-apses, called pruning in the human brain, and (2) aaged boards and PCBs, and research on fully sealed

nonlinear neural network technology that incorpo-

non-contact connector technology for simultaneous

rates the property of human neurons to use a wide

communication of non-contact power supply andvariety of nonlinear functions in the right places to

TLC in close proximity to each other. GND shield-

increase the representation capability of the network

ing technology is studied to prevent mutual interfer-

in order to prune more drastically than before andence between wireless power transmission and con-save the number of elements. In addition, we are de-tactless communication.

veloping convolutional wired-logic architecture circuits that reuse circuits in accordance with the pro-

RFID Tag Chip Design
T. Kuroda, M. Hamada, A. Kosuge, R. Miura, S. Shibata

24

cessing of convolutional algorithms. Research works
regarding MNIST and CIFAR-10 using FPGA were
published on IEEE JETCAS and OJCAS respectively.

mmWave Imaging Radar based Object Recognition

Simulated Annealing
Ken Takeuchi, Chihiro Matsui and Naoko Misawa

T. Kuroda, M. Hamada, A. Kosuge, Wai-Yeung Yip, S.
SuehiroMemory error tolerant ReRAM-based Computation-in-Memory (CiM) to solve the knapsack problem, one of the combinatorial optimization prob-

cameras), conventional human/object detectors uti-

lems, is proposed. Proposed log-encoding simulated

lizing conventional cameras have low accuracy. Since

annealing (SA) on ReRAM CiM reduces the arraymillimeter wave radar technology has high environ-area of ReRAM CiM by 97.6%. To co-design Re-

mental resistance, the radar is promising solution

RAM device and SA, error injection is applied. As

for the harsh environment. However, unlike imagea result, the asymmetric ReRAM error increases therecognition, it has a problem in detection algorithm

acceptable bit-error rate (BER) by 10 times and thedue to low-resolution blur data. In this research, we

acceptable bit precision to 5-bit.

are developing a new deep learning AI technologythat handles millimeter wave images based on a new

3
Chapter3 Research in d.lab

In harsh environments (bad weather, night, dirt on

In-sensor Computing

semi-automatic training data generation technolo-

Ken Takeuchi and Chihiro Matsui

gy and develop a highly accurate AI technology for

We have proposes an integration of event-based

human/object identification. This year, we mainly

vision sensor (EVS) and processor (e.g., computa-

studied the characteristics of millimeter-wave radartion-in-memory, CiM) for low-power processing.

data and the network structure that matches them

By using newly defined characterization method ofand developed a camera-radar cooperative semi-au-

frame and EVS camera, an event-driven SRAM CiMtomatic learning data generation technique and de-with partitioned word-line (WL) activation methodveloped a millimeter-wave radar AI system that canis proposed for 3D-integration of EVS. The multi-

detect the type and location of six types of objects

ple-bit synaptic weights are stored in a set of SRAMs.

with the same accuracy as image recognition.

The proposed CiM for EVS achieves 10-6 times energy efficiency compared with CiM for frame camera.

Takeuchi Laboratory(https://co-design.t.u-tokyo.ac.jp/)

Nakamura Laboratory

Computation in memory (CiM)(http://www.hal.ipc.i.u-tokyo.ac.jp/)

Ken Takeuchi and Chihiro Matsui
We have developed a comprehensive Computation-in-Memory(CiM)

simulation

platform.

IoT Network Security
Hiroshi Nakmaura

The simulation platform has capability to emulate

Zigbee is a short-range wireless communication

multi-level cell (MLC) and various memory device

protocol and needs low power and low bandwidth

non-idealities such as uniform/non-uniform con-at the sacrifice of its short transfer range and slow

ductance variation and shift. The simulation results

speed. Due to this nature, it is widely used in small

address that the conductance shift has much more

inexpensive sensors and IoTs that run on batteries,

critical impact than conductance variation on infer-

As Zigbee adopts indirect communication to achieve

ence accuracy in CiM.

low power consumption, it incurs a vulnerability to
LDoS attacks. To solve this problem, we proposed acountermeasure method and attacker detection algo-25

3rithm without consuming large computing resources

this communication flow. This work is expected toor power to satisfy the constraints of IoT devices.

contribute to the power saving and real-time perfor-

Through experimental simulation, we confirmed its

mance enhancement of mobile robot systems.

effectiveness.

Chapter3 Research in d.lab

Coarse-Grain Reconfigurable Architecture

Fujita Laboratory(http://www.cad.t.u-tokyo.ac.jp/)

Takuya Kojima, Hiroshi Nakamura
Coarse-grained

reconfigurable

architectures(CGRAs) are expected as a promising architecture
for wide variety of computing including embedded
systems and high-performance computing due to its

Logic Synthesis for Generalization and Learning
Addition
Masahiro FUJITA, Xinpei ZHANG, Mingfei YU, Qingyang YI, Yukio MIYASAKA

benefit of high-energy efficiency and programmabil-

Logic synthesis generates a logic circuit of a giv-

ity. CGRA consists of an array of numerous process-en Boolean function, where the size and depth ofing element and its efficiency heavily depends on thethe circuit are optimized for small area and low de-quality of compiler which maps applications ontolay. On the other hand, machine learning has beenthese PEs. So far, we have proposed a novel algo-extensively studied and used for many applications

rithm called GenMap (A Genetic Algorithmic Ap-

these days. Its general approach of training a model

proach for Optimizing Spatial Mapping), which is afrom a set of input-output samples is similar to logic

mappaing framework based on a genetic algorithm.

synthesis with external don’t-cares, except that in the

We extend GenMap to handle not only spatial but

case of machine learning the goal is to come up withalso temporal reconfiguration and confirmed its ef-

a general understanding from the given samples. See-

fectiveness.

ing this resemblance from another perspective, we
can think of logic synthesis targeting a generaliza-

Lightweight Runtime Environment of ROS2 nodes

tion of the care-set. In this research, we try such log-

for Embedded Devices

ic synthesis that generates a logic circuit where the

Hideki Takase, Hiroshi Nakamura

given incomplete relation between input and output

The Robot Operating System (ROS) and ROS2,

is generalized. We compared popular logic synthesis

the latest version of ROS, have attracted attention

methods and machine learning models and analyzed

as a design platform for distributed robot software

their characteristics. We found that there were somedevelopment. One of the drawbacks of ROS2 isarithmetic functions that these conventional models

that it is necessary to employ high-performance andcannot effectively learn. Out of them, we further ex-

power-hunger devices since it requires a Linux en-

perimented on addition operations using tree models

vironment for operation. This drawback preventsand found a heuristic minimization method of BDD

ROS2 from being applied to embedded devices be-achieves the highest accuracy.

cause they must be quick in response and consumes

26

less power. Thus, we have proposed a novel solution

FPGA Based Accelerator for Neural Networks Com-called mROS2, which is a lightweight runtime en-putation with Flexible Pipelining

vironment of ROS2 nodes. One of the advantages

Masahiro FUJITA, Heming SUN, Qingyang YI

of mROS2 is that it provides efficient communica-

FPGA is appropriate for fix-point neural networks

tion mechanisms with less memory consumption.

computing due to high power efficiency and con-Currently, we are designing software architecture for

figurability. However, its design must be intensively

refined to achieve high performance using limited

Ikeda Laboratory

hardware resources. We present an FPGA-based(http://www.mos.t.u-tokyo.ac.jp)

neural networks accelerator and its optimization
Implementation of Fully Homomorphic Encryp-various CNN models and FPGA resources. Target-tion

ing high throughput, we adopt layer-wise pipeline

M. Ikeda, T. Shimada, Y. Zhao, and M. Fujitaarchitecture for higher DSP utilization. To get the

Fully homomorphic encryption (FHE) is a pub-

optimal performance, a flexible algorithm to allo-

lic-key cryptography scheme that allows any oper-

cate balanced hardware resources to each layer is also

ation to be performed in ciphertext without a se-

proposed, supported by activation buffer design.

cret key. While this technology is expected to be a

Through our well-balanced implementation of four

solution to the privacy problem, which is the biggest

CNN models on ZC706, the DSP utilization andconcern of current cloud-based services, it has theefficiency are over 90%. For VGG16 on ZC706, theproblem of large computational resources. This re-proposed accelerator achieves the performance of

search aims to speed up the fully homomorphic en-

2.58x, 1.53x and 1.35x better than the referenced

cryption, such as TFHE and BGV, by implementing

non-pipeline architecture, A, pipeline architecture B

ASIC. The chip prototyped this year has achieved

and C, respectively.

a 4-fold speedup compared to CPU, and further

3
Chapter3 Research in d.lab

framework, which can achieve optimal efficiency forspeedups are expected in the future.
FPGA Based Accelerator for Neural Networks Com-We are also focusing on improving algorithms andputation with Flexible Pipelining

security parameters to achieve higher speeds when

Masahiro FUJITA, Ryogo KOIKE

implemented in hardware. Specifically, we have pro-Due to the large scale integration of VLSI in re-posed a method to increase the number of operations

cent years, formal verification technique becomestypes that can be performed in a single step by modi-

much important. One of them is inductive invari-fying the TFHE algorithm. We also studied methods

ant that is used to compute sets of reachable state

to optimize the security parameters for the shortest

in a sequential circuit. For inductive invariants, it

execution time under the constraints of hardware ar-is important to select the subset of flipflops in orderchitecture and security level, etc.

to find a small and/or useful superset of reachable
states. It is difficult to compute inductive invariants

Design optimization of high-performance cryp-with all flipflops, so it may be useful to use the sub-tographysets of flipflops. In this research, the calculation of
inductive invariants is formulated with Quantified

M. Ikeda, K. Ikeda, A. Opasatian, K. Masada, and F.
Arakawa

Boolean Formula (QBF). The QBF problem can be

The development of more advanced technology

solved incrementally by using MUX for choosing

such as IoT and Functional encryption, such as at-

flipflops. We confirmed the validity of our method

tribute-based encryption, drives the need for high-with ISCAS89 benchmark circuits.

er and broader specification of high-performance
cryptographic computation. To achieve those needs,
the performance of elliptic curve cryptography computations are improved in various ways. Using thescheduling and optimal modular multiplication algorithm, we extend the acceleration of pairing cal-27

3Chapter3 Research in d.lab

culation to the scalar multiplication and the hash to

Security Measures of Crypto-engine

point calculation as well. The pairing engine is also

M. Ikeda, K. Abe, and S. Kikuoka

designed to support the computation in many curves

Cryptographic circuits must be resistant tosetting. Moreover, the automated design of accelera-side-channel attacks. We conducted template attacks

tor architecture for different curve are also being re-using measured current consumption on a hardware

searched to help reduce the design time, which is an

implementation of 256-bit ECDSA to leak a part ofissue in hardware cryptographic design. The demon-

secret information and confirmed that it is possible

stration of practical use case is showcased by inte-

to recover the secret key via lattice attacks. In ad-

grating the pairing engine to accelerate the softwaredition, we considered the conditions under which

implementation of the file encryption system based

the attack was likely to succeed and countermeasureson attribute-based encryption.

based on the attack results.
For hardware implementations of elliptic curve

Implementations of Post-Quantum Cryptography

pairings, it is important to select the optimal curve(PQC) Algorithms

that achieves both sufficient security and low cost.

M. Ikeda, H. Bui, and T. Shimada

We evaluated the security against solving DLP (dis-Post-quantum cryptography is a type of public-key

crete logarithm problem) and ECDLP(elliptic curve

cryptography that is resistant to attacks by both clas-

discrete logarithm problem) and hardware costs such

sical and quantum computers yet can be performed

as area, cycles, and latency of paring-based cryptog-

by a conventional computer. It aims to replaceraphy on major pairing-friendly elliptic curves likemodern-day cryptography standards such as classic

BN and BLS12 curve with multiple parameters.

Diffie-Hellman, RSA, and elliptic curve which all
can be cracked in polynomial time with a sufficient28

Neural network and its security

quantum computer. Examples of some PQC algo-

M. Ikeda, Z. Wang, and B. Amartuvshin

rithms include lattice-based cryptography (NTRU),

The huge computing cost of neural network has

codes-based cryptography (Classsic McEliece) and,become an obvious obstruction from its wide ap-

super-singular-isogeny-based cryptography (SIKE).

plication. Specific hardware can greatly reduce theAmong these PQC algorithms, we are currently

computation time and energy consumption but its

focusing on an improved SIKE implementation as

designing is still a changeling task due to large re-it provides multiple benefits over the others chief ofsource requirements of involved operations. Re-

which is that it is an extension of elliptic curve cryp-

cently Binary Neural Network (BNN) has attracted

tography. Its main problem lies in its speed, which ismuch attention because of its compactness and easy

an order of magnitude slower to run than the other

implementation. We designed a self-synchronous

PQC candidates. Our research aims to improve thecircuit for BNN to further enhance the energy ef-

speed of the algorithm by using the inherent par-ficiency and calculation speed. The simulation re-allelism offered by hardware acceleration and bysults showed the light-weightness while considerable

using a dataflow approach to the design applicablethroughput is kept.

for ASIC implementation. Currently, we have deter-

On the other hand, cloud computing is anothermined the maximum speed that SIKE can achieve

method to prevent the unaffordable computational

and are aiming to use clocking techniques to reduce

cost on personal computers. However, it may in-

the amount of hardware resources yet maintain thevolve severe privacy problems due to uploading orig-

speed at around the same level.

inal data to the cloud server. Fully Homomorphic

posed a method that allows adjustment of the classprivacy concern, while it still suffers from the huge

width so that finer measurements can be taken incomputing cost and as only addition and multiplica-

the early stages of decay with limited hardware re-tion are supported in FHE, degradation of accuracy

sources. In addition, intending to efficiently process

is unavoidable. In this research we designed ASIC

temporal information of input photons in real-time,

hardware to highly improve the computing speed

we are working to introduce event-based data pro-compared with the common platforms such as CPU

cessing methods for SPAD image sensors. We haveand GPU. We chose BGV algorism, which is one ofdesigned the sensors, and evaluation of the fabricat-

FHE schemes, for encrypting the computations in

ed sensors is in progress.

neural network and have designed a polynomial multiplier for accelerating BGV computations. Also, we
adjusted the neural network structure to meet the

Iizuka Laboratory(http://www.mos.t.u-tokyo.ac.jp/iizuka)

FHE requirements. We investigated the effects of activation function, training method and layer struc-

Phase-Locked Loop Circuit Techniques for Low

ture of the neural network with only additions andPhase Noise

multiplications and made the accuracy almost thesame as the original network.

3
Chapter3 Research in d.lab

Encryption (FHE) is believed as a solution to the

Tetsuya Iizuka, Zule Xu, Zunsong Yang, Masaru Osada, Ryoga Iwashita, Yo Kumano
Switched-capacitor sampling PLLs (SC-SPLL) are

Smart Image Sensors / SPAD Sensors and Meas-

competitive for both low phase noise and low power

urement Methods

consumption. However, the conventional type-I ar-

M. Ikeda, Y. Miao, D. Jiang, N. Watanabe, H. Matsuoka, and T. Kikkawa

chitecture is unsuitable to fractional-N operation. A
type-II PLL is a good candidate, but it convention-

We have been working toward new types of image

ally demands a transconductance-based (gm-based)

sensors with higher functionality and performance,

integrator or an extra DAC, which necessitates extra

such as smart image sensors and SPAD sensors.

power and area. In this work, we propose a type-II

Smart image sensors integrate advanced informa-hybrid architecture re-using sampling capacitor as ation processing into the sensor to achieve various

capacitive digital-to-analog converter (CDAC) thatfunctions. We designed a ToF image sensor withreceives the digital integrator’s output. In this way,light to pulse frequency modulation and digital pro-no gm cell or extra DAC are needed. Thus, the en-cessing for decoding the modulated signal, for sig-

tire architecture is compact and with high perfor-

nal identification under multi-user interference. We

mance as well. The prototype chip in 65-nm CMOS

also design a ToF image sensor with long-distanceachieves −80-dBc reference spur, 236-fs integrated

ranging capability by adding phase shifting circuits.

RMS jitter, and 4.6-mW power consumption, trans-

These sensors have been fabricated, and we havelating to −246-dB FoM.

evaluated the real-world performance.

Ring voltage-controlled oscillator (VCO) is attrac-

SPAD sensors have extremely high sensitivity andtive for a compact footprint, multiple phases, andtime resolution and are thus considered to be prom-no magnetic coupling. However, for the low-jitter

ising for applications such as distance ranging and

PLL higher than 5 GHz, most previous works still

fluorescence lifetime imaging (FLIM). In FLIM

resort to LC VCOs where the inductors suffer fromphotons’ arrival time histograms are used. To achievea large area and underlying magnetic coupling. We

high-efficient histogram generating, we have pro-proposed an inductorless cascaded PLL with ultra-29

3

low jitter that leverages the large performance gap

signed by using a SAR ADC for the first stage, andbetween low- and high-frequency ring oscillators.

using a ΔΣ ADC with FIAs(Floating Inverter Ampli-

A single-stage sample-and-hold subsampling phasefiers) for the next stage.

Chapter3 Research in d.lab

detector is proposed for the 1st stage, where the os-

Performance indicators of voltage-controlled oscil-cillator’s control voltage is updated only when thelators (VCOs) include phase noise, power consump-

impulse sensitivity function is zero, enabling wider

tion, circuit area, and oscillation frequency, etc. In

loop bandwidth, lower jitter, and lower spur. Fabri-fields such as wireless communications, LC-VCOs

cated in 65-nm CMOS, the prototype operating at

are generally used because of their superior phase

10GHz achieves −63-dBc reference spur, 175-fs in-noise characteristics. As one of the topologies, a gate

tegrated RMS jitter, and −240-dB FOM with a 125-bias is applied to the cross-coupling transistor, and it

MHz reference clock.

is always operated in the saturated region to increase

We proposed a low phase noise, fractional-N ringthe conversion efficiency from DC power to signal

PLL that makes use of the Harmonic-Mixer (HM)(RF) power. We have designed and fabricated pro-based feedback architecture and a nested PLL based

totypes of NMOS and CMOS Class-C VCOs thatphase-domain filter. Compared to their LC-based

reduce power consumption while keeping the phasecounterparts, ring oscillators enjoy benefits such as

noise atsmall area, multi-phase outputs, and absence of mag-the same level as conventional ones. Unfortunately,

netic coupling among others. However, their inferi-

we could not measure the phase noise of the NMOS

or phase noise requires a wide PLL loop bandwidth,

VCO due to a buffer design error, but we plan to

making it difficult to employ in fractional-N PLLs

confirm the phase noise of the CMOS VCO as soon

where the Multi-Modulus-Divider (MMD) contrib-

as we receive the chips TO in January. FoM is expect-utes large quantization noise. To overcome this issue,

ed to be 188~190dBc/Hz based on simulation.

this work proposed an architecture that uses HMbased feedback to avoid noise amplification, and a

High-Precision Analog-to-Digital Conversion Cir-

nested-PLL-based phase-domain filter to both filter

cuits and its Design Automation Techniquesout the quantization noise and increase the shaping
frequency. The effectiveness of the proposed meth-30

Tetsuya Iizuka, Zule Xu, Shuowei Li, Akira Matsuoka,
Ryoya Shibata, Haoming Zhang

od was shown through calculation, simulation, andThere is a strong demand for high resolution andmeasurement of an actual chip designed in 65nm

high power efficient ADC. To improve the power ef-

CMOS process.

ficiency of edge devices, fully-dynamic discrete-time

Based on the conventional second-order ΔΣ FD-

A/D converters (DTADC) are suitable, which haveC(Frequency-to-Digital Converter)-PLL that can

the scalability of the power and the operating speed.

reduce phase noise with noise shaping, we proposed

This research proposes a fully-dynamic DTADC

a higher-order ΔΣ FDC-PLL for a wider loop band-using floating inverter amplifiers (FIA). Correlated

width and lower phase noise. To solve the stability

level shifting (CLS) is applied to FIA, which results

issue from the higher-order ΔΣ FDC, we introduced

in 50dB DC gain with one stage amplifier. A new

MASH(Multi-stAge noise SHaping). We demon-sampling noise cancel technique with CLS-FIA wasstrated the higher-order quantization noise shaping

proposed. Proposed ADC achieved a 91.8 dB SNDR,of the MASH 2-k FDC and the lower phase noise/

while consuming 76.2 µW in simulation.

jitter performance of the proposed FDC-PLL by

As the demand for high-speed communications

MATLAB Simulink. The MASH FDC can be de-and high-speed analog-to-digital converters contin-

combinational logic, it has the advantage of power-ef-

and low-power comparators are increasing. We haveficiency and higher speed and smaller area because of

established a mathematical model and simplified it.

using less transistors, especially P-MOS. However, a

By controlling a few parameters, the degree of cali-

clock signal has to be added to take control of thebration of the strong-arm comparator can be com-phase of the periodic charging and discharging while

pletely predicted. The designer can easily set up theensuring the correct logic function, thus the timing

circuit for the strong-arm comparator based on ourof dynamic circuit is much more complicated thandesign guidelines to make a calibration. Also, to sim-

the common static logic and is always a difficult task

plify the design of analog circuits, we try to designthat need huge manual force to be properly arranged.

the ADC based on standard cells. For the capaci-

In this study, we want to reduce that manual force by

tor selection of the sampling circuit, we found thatsemi-automizing the timing arrangement. The spe-

we can select an appropriate channel length, floatcific method is to characterize the dynamic circuit

the source and drain terminals of the transistor, toto a standard cell with timing information, and use

obtain a MOSFET-based capacitor that is almost

Synopsys tool to check the complex timing in the

independent of the bias voltage, thereby replacing

proper way. Since it is not a traditional circuit, thethe commonly used MIM and MOM capacitors. It

construction of the model of dynamic circuit and the

becomes possible to design sampling circuits based

utility of tool is challenging.

3
Chapter3 Research in d.lab

ues to grow, the design requirements for high-speed

on standard cells.
Noise generally causes poor system performance,and various techniques are used or additional power

Millimeter-Wave Circuit Design for Wideband
Communications

is consumed to avoid the noise. Stochastic resonanceTetsuya Iizuka, Takamichi Horikawa, Sota Kano

is a phenomenon in which adding noise of a certain

In recent years, there is growing demand for theintensity to a nonlinear system improves the per-next-generation wireless communications such asformance of the system. When this phenomenon is

Beyond 5G and 6G, which realize ultra-high-speed

applied to analog-to-digital converters (ADC), it iscommunications exceeding 100 Gb/s. Millimeter

expected to improve the detection accuracy of weak

wave band from 30 to 300 GHz offers a wide fre-signals and reduce power consumption by allowing

quency bandwidth and is being actively studied fornoise in the circuit. In our study, the proposed cir-Beyond 5G and 6G applications.

cuit utilizes the same architecture as a charge-redis-

In this study, we designed an oscillator, which is

tribution successive approximation register (SAR)

essential component in millimeter-wave integrat-

ADC. We have analyzed the performance under theed circuits, with operating frequency of 150 GHz.

assumption of ideal noise application. In addition,

It is challenging to ensure gain for oscillation at

our simulations have shown that when the input sig-

these very high frequencies near the operating lim-

nal amplitude is comparable to the input-referred

it of transistor. Thus, we presented a novel method

noise of the comparator, the performance of the pro-of increasing the oscillation frequency and output

posed circuit can be better than the SAR ADC.

power, using the design method of power amplifiers

The dynamic circuit is a type of circuit that differ

optimizing the power gain. In the proposed meth-from static circuit, it is a combinational logic thatod, impedance matching based on transmission lines

make flexible use of the storage of information in the

maximizes the power extracted from transistors, andform of charge on the capacitance. Even though it’ssimultaneously adjusts the oscillation frequency tofunctionally identical as the commonly used static

the target value using the phase shift caused by the31

3line length. We actually designed the oscillator us-

higher than the power consumption of the human

ing a SiGe BiCMOS 130nm process, and shown inbrain of about 20W. It Shows a clear advantage insimulation that the output of 147.5 GHz and -0.13

terms of power consumption compared to DNN.

Chapter3 Research in d.lab

dBm can be estimated. Furthermore, for application

It is well known that billions of neurons in theto 300 GHz band a frequency doubler was simulat-

brain are interconnected by trillions of synapses to

ed, and we demonstrated that in total design the 300

form a complex, high-level computational system

GHz oscillator can operate at -12 dBm output pow-that can process in parallel the vast amount of in-er.

formation received through various sensory organs.
These neurons communicate with each other and

Implementation of Neuron Device based on CMOS

process information through action potentials or

Analog Circuits

spiking signals. Spiking neural networks (SNNs) are

Tetsuya Iizuka, Xiangyu Chen, Byambadorj Zolboo

known as the third generation of ANNs and greatly

As von Neumann's bottleneck worsens and Moore's

bridge the gap between ANNs and biological neural

Law is about to end, researchers face unprecedented

networks (BNNs). SNNs are event-based learning

challenges. One of the solutions to these problems

that do not require external storage and are consid-

is a computational model architecture inspired byered to be the most promising neuro- morphic com-

the human brain, which has the potential to elim-

puting systems. Like BNNs, SNNs are composed

inate the bottleneck of von Neumann and lead theof neurons and synapses and are considered to be

next generation of computer engineering. Morphic

the most promising neuromorphic computational

computing has emerged as a hotspot for research.

systems. ANNs are usually built using a bottom-up

Deep Neural Networks (DNN), the second gener-

approach, meaning that each component of BNNs

ation of artificial neural networks (ANN), can per-needs to be simulated.Therefore, the first and mostform operations in multiple processor layers and areimportant step to implement SNNs in hardware is

widely used in many fields such as pattern recog-

to design their basic building blocks, such as spiking

nition, language translation, and object detection.

neurons and synapses.

In 2017, AlphaGo, a DNNs-based Go program de-

A number of hardware-implemented spiking neu-

veloped by Google DeepMind, played against a hu-

rons or synapses have been reported. However, mostman Go world champion and finally won. It seemsof these conventional spiking neurons use analog in-that DNN's great success has defeated the humanformation such as voltage and current to communi-

brain. This performance is really great, but can it

cate with each other, which leads to requirements onreally be said that DNN can beat the human brain?

the magnitude of the voltage or current. To imple-

There is an important question that cannot be avoid-

ment the Leaky-integration function of neurons on

ed: how much energy does this computational pro-signals, integrators with operational amplifiers arecess require? Deep learning basically only adjusts

often built and use large on-chip capacitors and re-

the weights by a method called gradient descent tosistors to achieve long time constants. Even more, toobtain the optimum value, and the large amount ofachieve the “fire” function of neurons, the inclusion

multiplication / integration operations performedof comparators is used to simulate the threshold of

by DNN in the process consumes a large amountneurons. These approaches will undoubtedly makeof power. AlphaGo uses more than 2000 CPUs andthe neuron power consumption very high and themore than 300 GPUs and consumes 100-200kW ofchip area occupied very large.

power, which is about 10 ^ 4 orders of magnitude

32

we propose a neuron-synapse structure that usestime-domain analog signals (pulse interval, pulse

fabrication of the arrow-shaped antenna, the target

width and frequency) for signaling, and the circuit

frequency is slightly changed from 28 GHz to 27.5

structure includes a leaky integrate-and-fire (LIF)

GHz due to some mismatch in the physical dimen-

neuron, a synapse, and a weight circuit. The pro-sion of the arrow-shaped conductor.
In near-field measurement, one of the easiest ways

ers as well as comparators and maintains a subthresh-

is to measure S-parameters on the planar scanningold state in the absence of signal input. In addition,area in front of the antenna under test (AUT). Not

since the proposed neuron-synapse structure trans-

only it is practically uncomplicated to make themits temporal signals rather than voltage and cur-measurement, but the transformation method af-

rent, it is well suited for applications in reservoir

ter the measurement is also straightforward. In thiscomputing and STDP construction.

research, the near-field measurement is made on a

In addition, we also build pulse-based neural net-

rectangular plane within the range of near-field dis-

works with these proposed elements and train themtance from AUT. During the scanning process onwith the recursive least squares method to achieve

the rectangular plane, AUT and probe connections

the learning function of sine waveforms.

are impacted by undesirable vibration from moving

3
Chapter3 Research in d.lab

posed LIF neuron does not use operational amplifi-

sliders.
Antenna Measurement and Testing Techniques for
Wireless Communications
Tetsuya Iizuka, Mai Khanh Nguyen Ngoc, Byambadorj Zolboo, Sheng Guo

The method of near-field to far-field transformation in our research is based on plane wave spectrum(PWS). Using several differently oriented measurements of unknown patterned AUT with the un-

In 5G technologies, over the air (OTA) measure-known patterned arrow-shaped monopole probe an-ments are necessary for 5G antennas due to the tech-tenna, the pattern of AUT is theoretically obtainablenologies rely on millimeter-wave frequencies andunder several assumptions. Due to the mismatch ofsmall-sized terminals. The conventional OTA meas-

physical parameters, it is impossible to achieve suchurement is based on far-field measurement. Howev-

ideal assumptions which lead to some undesirable ef-

er, the far-field measurement is almost infeasible infect on near-field measured data.

the millimeter-wave due to high path loss and low

The preliminary results show that near-field to far-measurement accuracy. Therefore, near-field meas-

field transformed data from the measured data does

urement takes place of OTA measurement in thehave some errors compared to the simulation data

millimeter-wave range. The far-field measurement

and the reference data of AUT due to unwanted mis-data can be achieved from near-field measurement

match of hardware. Under the correct measurement

by using near-field to far-field methods.

setup, moderate performance on the far-field pattern

In this research, there are plenty of challenges fromcan be achieved.

hardware to software including automated near-fieldmeasurement equipment, millimeter-wave probe,

High-Precision Inter-Pin Skew Detection Tech-and near-field to far-field transformation methods.

nique for Automatic VLSI Test Equipments

In the millimeter-wave probe application, we focus

Tetsuya Iizuka, Hidaka Otsuka

on an arrow-shaped monopole antenna design on a

Timing Calibration (calibration of pin-to-pin

standard PCB board. The radiation pattern is prov-skew) is necessary for automated testing performed

en to have an effective directivity in the simulationonenvironment. In the measurement result after the(ATE). Conventional CAL methods are incapable ofsemiconductor

Automatic Test

Equipment

33

3
Chapter3 Research in d.lab
34

performing CAL of less than 10ps, but as process

Verification of Topological Quantum State based

miniaturization and signal speeds increase, high-on Electrical Circuits

er-precision CAL methods will be required in the

Tetsuya Iizuka, Yuan Haochen

future. Also, the characteristic of ATE is that it has

Topological quantum computing(TQC) is a meth-many pins, and the CAL method must also support

od of fault-tolerant quantum computing, in which

multiple channels. We designed and measured a pin-

a single quantum gate could be generated by theto-pin skew detection circuit to realize CAL with an

braiding of certain topological quantum objects,

accuracy of 1 ps.

named "anyons", and one simplest realization of aConventional CAL methods use the driver andnon-Abelian anyon is a quasiparticle named Majora-comparator of the ATE itself to mutually detect thena fermion which obeys ordinary Fermi-Dirac statis-skew. In the proposed method, the skew detection

tics and owns a particular mechanism, Majorana zero

circuit is implemented on a CAL board (perfor-

mode(MZM). Therefore, we focus on the 1D cir-mance board) and is designed to detect skew at a

cuit chain realization of Majorana zero-energy edge

point closer to the DUT. There is a clock tree instates to discover whether the MZM will appear at

the circuit that can distribute precisely timed signals

the boundaries, by measuring the nodes' eigenmode

to each channel. By passing this signal through thevoltages and two-point impedance.

comparator of the ATE, the pin-to-pin skew fromTo realize the Majorana edge mode, there are sev-

the DUT to the comparator is detected. There is alsoeral models including the 1D SSH model and 1D

a skew detector on each channel in the circuit toKitaev model. In this research, we focus on the cir-detect skew between the channel input signals andcuit realization of the 1D Kitaev model.

the clock tree signals. The detected skew is dimen-

The circuit chain contains two main lines, one line

sionally converted to the voltage domain for externalconsists of capacitors C in series representing elec-

readout. By passing the ATE driver signals throughtron band while another one consists of inductors L

each channel, this feature can be used to detect pin-in series representing hole band, to realize the oppo-

to-pin skew from the driver to the DUT.

site hopping parameters between electron and hole

The design was done in TSMC CMOS 65nm

bands. The interaction between the electrons andprocess and the chip was measured by probing. In

holes is simulated by bridging capacitors C_X andthe simulation, the process variation of the chan-inductors L_X. And each electron/hole node is con-nel-to-channel skew was suppressed to σ93fs, andnected to the ground via capacitors C_0 or inductors

the variation of the channel-to-channel skew of the

L_0, to make the circuit chain topological.

clock tree with respect to environmental variations

We have constructed three topological circuit

was suppressed to less than 80fs. In the measurement,

chains with different resonant frequencies by ad-

the channel-to-channel skew was large due to factors

justing the values of capacitors and inductors, also

not modeled in the simulation. However, it was con-with three trivial chains for comparison. The rapid-

firmed that even when the power supply voltage wasly increasing two-point impedance is found in thevaried by 1% and a current of about 20mA was ap-

topological models with the EM simulation results,

plied to the heater inside the circuit, the amount of

implementing the existence of MZMs at both edges.

skew variation could be kept below 1ps.

We taped out using Rohm 0.18um process.

Hiramoto & Kobayashi Laboratory

IGBT scaling and double-gate IGBT.

(http://nano-lsi.iis.u-tokyo.ac.jp/)

Research on monolithic integration technology of
Variability in Nano-Scale CMOS Devices

embedded memory device using Sn-doped IGZO
Masaharu Kobayashi, Toshiro Hiramoto

As the size of MOS transistors is miniaturized, theOxide semiconductor material such as IGZO has

effect of random variability of device characteristics

been used for flat panel display applications, andis becoming too large to be overlooked. Although the

now becomes promising for integrated circuit appli-

main reason in conventional bulk transistors is thecations because of its low temperature process, ex-fluctuation of the number of dopants, the variability

tremely low leakage current by wide bandgap, and its

causes of nanowire transistors, which is one of thehigh voltage tolerance. Reliability characteristics cannext-generation device candidates, remain unknown.

be improved by doping Sn in IGZO. In addition,

In this study, we have clarified that the quantum

mobility can be enhanced by the Sn-doped IGZO

confinement fluctuation caused by line width rough-(IGZTO. In this study, we clarified the physical ori-

ness is the new origin of random threshold voltage

gin of the mobility enhancement in IGZTO. Widely

variability. We are also investigating the effect on the

distributed s-orbital wave function can flatten thedrain current variability.

potential fluctuation originated from cation disor-

3
Chapter3 Research in d.lab

Toshiro Hiramoto and Masaharu Kobayashi

der in IGZO. Furthermore, we demonstrated the
Low Temperature Characteristics of Nano-Scale

stable endurance characteristics in IGZTO-capped

CMOS Devices

ferroelectric HfO 2 capacitors. Finally, we developed

Toshiro Hiramoto and Masaharu Kobayashi

co-integration process of IGZTO FETs and ferro-

The quantum computing has attractive much at-

electric-HfO 2 capacitor at less than 400 ℃ process,tention for a future computing technology that isand demonstrated 1T1C memory cell operation, andfundamentally different from classical computing bypredicted sub-ns operation by SPICE simulation.

CMOS circuits. In the quantum computing systems,
conventional CMOS circuits are utilized to control

Research on fundamental material properties ofquantum bits. Therefore, it is essential to clarify

ferroelectric-HfO2

and model CMOS transistor characteristics at low

Masaharu Kobayashi, Toshiro Hiramoto

temperature. In this study, we are studying the sub-Ferroelectric-HfO2 is a promising material for next

threshold swing of bulk and nanowire transistors.

generation ferroelectric memory applications because

We are also evaluating the characteristics variabilityof its high CMOS compatibility, ferroelectricity lessat low temperature.

than 10nm thickness, and high coercive voltage. In
general, ferroelectric-HfO2 appears in a poly-crystal-

Silicon Power Devices

line film, while conventional perovskite is formed in a

Toshiro Hiramoto

single crystalline film. While out-of-plane polarization

Although new materials such as SiC or GaN areof ferroelectric phase grains are preferred for memory

widely studied for power devices, silicon IGBT (In-

operation, however, it is not verified yet whether out-sulated Gate Bipolar Transistor) is still a mainstream

of-plane polar grains can align themselves or not in fer-

device for power electronics in very wide range ofroelectric-HfO2. In this study, we showed that in-plane

rated voltages. In this study, we are pursuing the po-polar (010) orientation is thermodynamically stable bytential of silicon IGBT based on new concepts ofab-initio simulation. We also experimentally found that35

FE-HfO2 grains have in-plane polar (010) orientation
by electron diffraction mapping method. However, by

Takagi Laboratory(https://sites.google.com/g.ecc.u-tokyo.ac.jp/mosfet)

applying electric field, we found that FE-HFO2 grains
3
Chapter3 Research in d.lab

turn its orientation to (001) by the same method. We

III-V Metal-Oxide-Semiconductor (MOS) FETs andstudied the kinetic pathway of the transition from in-the 3 dimensional integration

plane to out-of-plane polar orientation by ab-initio
simulation. We demonstrated that the transition can

S. Takagi, Kei Sumita, Ryohei Yoshizu, Kasidit Toprasertpong, M. Takenaka

occur through the intermediate tetragonal phase only

3D-integrated CMOS, in which transistors arewith an extra small energy. This result indicate that FE-

vertically stacked, is expected to be a key device for

HfO2 can align its polar-axis to out-of-plane orienta-

future logic LSIs. In order to realize such stacked

tion in any 3D structure under the electric field.

MOSFETs, channels such as III-V compound semiconductors and Ge are promising because they can

Research on 3D ferroelectric/anti-ferroelectricbe fabricated at low temperatures and are expectedtransistor memory devices

to have high mobility and injection speed. In our

Masaharu Kobayashi, Toshiro Hiramoto
Ferroelectric

FET(FeFET)using

laboratory, we are investigating the realization of ulferroelec-

tra-thin III-V-On-Insulator (III-V-OI) structures on

tric-HfO 2 is a promising memory device for highSi substrates, and the performance improvement ofdensity storage applications. A FeFET can work as

III-V nMOSFETs using these structures aiming at

a memory cell by itself just like NAND flash mem-

application to 3D stacked CMOS. In this fiscal year,

ory, FeFETs can also take 3D stack architecture for

we established a novel model of thickness fluctuationhigh density memory. In our previous work, we pro-(surface roughness) scattering, which is an impor-posed oxide semiconductor-channel FET instead oftant scattering mechanism that determines the elec-

conventional poly-silicon channel toward 3D stacktron mobility of thin-body channel MOSFETs, and

FeFETs. We showed that short gate length and thinshown that further mobility enhancement of InAs

film thickness help to increase memory window, by

nMOSFETs is possible by improving the MOS in-

simulation. In order to realize 3D FeFET, however,terface roughness. Furthermore, we proposed a newoxide semiconductor has to be conformally deposit-

method to evaluate the interface state density inside

ed in 3D trench structure. In this tudy, we developed

the conduction band of InAs at InAs MOS inter-

conformal deposition process of InOx by ALD meth-faces and experimentally demonstrated that the InAs

od in 3D structure. Based on the design guideline

MOS interfaces have excellent interfacial properties.

described above, we successfully fabricated a verticalchannel FeFET and demonstrated its memory op-

Ge Metal-Oxide-Semiconductor (MOS) FETs anderation with memory window > 1V. Furthermore,the 3 dimensional integration

we propose to use anti-ferroelectric gate insulator
instead of ferroelectric, as anti-ferroelectric FET

S. Takagi, Tsung-En Lee, Chia Tsong Chen, XueyangHan, Kasidit Toprasertpong, M. Takenaka(AFeFET), and use half-loop hysteresis for efficient

We are investigating the technology to real-erase operation. We experimentally demonstrated

ize ultra-thin Ge-On-Insulator (GOI) structures

the memory operation of the AFeFET. This workon Si substrates, the performance improvement ofshows the feasibility of FeFET and AFeFET for 3D

high-performance GOI CMOS using these struc-

structure high density and low power memory.

tures, and the device physics that determines theelectrical characteristics, with the aim of applying

36and FeRAMs with memory-in-logic and nonline-

we demonstrated that extremely-high hole mobility

ar analog computation capabilities are promising

can be obtained even in ultra-thin body channels by

hardware for physical implementation of reservoir

introducing uniaxial strain through the thinning ofcomputing. Thus, we are searching for methods to

a compressively-strained GOI structures, fabricatedimprove AI performance of reservoir computing

by the Ge condensation method. We also demon-

based on ferroelectric devices by examining operat-

strated that EOT can be reduced down to 1 nm withing schemes and device characteristics. In this fiscal

maintaining a low interfacial defect density in a

year, we demonstrated that AI performance can be

TiN/Y2O3/SiGe gate stack structure with ultra-thin

improved by using combining original and invert-

Y2O3 formed by atomic layer deposition (ALD).

ed input data applied to the gate electrode. We also
investigated the effect of FeFET degradation on AI

HfO2-based Ferroelectric devices
S. Takagi, Kasidit Toprasertpong, Xuan Luo, Makoto
Kawano, Koichiro Iwashige, M. Takenaka

performance, and found that AI performance can be
maintained by updating weights even when FeFET

3
Chapter3 Research in d.lab

them to 3D integrated CMOS. In this fiscal year,

memory characteristics significantly deteriorate.

MOSFETs (FeFETs) using ferroelectrics with polarization reversal as gate dielectrics and FeRAM us-

Understanding of Si CMOS operation under ul-

ing metal sandwich structures (MFM structures) as

tra-low temperature for quantum computing ap-

memory cells are expected to be future devices forplication

ultra-low power memory and logic. In particular,
devices based on ferroelectric and anti-ferroelectric

S. Takagi, Minsoo Kang, Kasidit Toprasertpong, M.
Takenaka

materials such as Hf1-xZrxO 2 and ZrO 2, which have

In quantum computing systems, Si CMOS circuits

been discovered recently, are of great interest becausethat can operate at cryogenic temperatures such as 4of their extremely high compatibility with current Si

K must be placed close to the qubit chip in order to

CMOS technology. We are studying the properties

improve the number of qubits. For this purpose, weof these ferroelectric thin films deposited by an ALD

are conducting experimental and theoretical studies

method, the device operation principle of FeFETs

to quantitatively describe the electrical characteris-and the optimum device structures to realize excel-

tics of MOS transistors at cryogenic temperatures

lent device characteristics. In this year, we demon-and to clarify their physical mechanisms. In thisstrated for FeRAM applications that MFM capaci-year, we experimentally evaluated the variation oftors with Hf0.5Zr0.5O 2 films thinned to around 4

sub-threshold swing from room temperature to 4 K

nm, which is expected to operate at low voltages,

for Si n-MOSFETs with different substrate concen-

significantly improves dielectric reliability and ena-

trations and found that the values of sub-thresholdbles more than 1014 write cycles at 1.2 V operation.

swing can be quantitatively reproduced regardless ofthe substrate concentration by assuming both tailReservoir computing based on ferroelectric devic-

states and localized interface states existing near theesband edge.

S. Takagi, Kasidit Toprasertpong, Eishin Nako, Zeyu
Wang, R. Nakane, M. Takenaka
Reservoir computing has recently attracted attention as a AI computation method with computational load for learning. We have proposed that FeFETs

37

Takenaka Laboratory(https://sites.google.com/g.ecc.u-tokyo.ac.jp/takenaka-lab/)

We have been studying semiconductor devices using graphene and molybdenum disulfide. We
have successfully demonstrated a phototransistor

3

On-chip/Off-chip optical interconnect

Chapter3 Research in d.lab

Mitsuru Takenaka, Hanzhi Tang, Yuto Miyatake, Tipat Piyapatarakul, Kazuma Taki, Taketoshi Nakayama,

by bonding MoS2 on HfO 2 gate dielectric. Usinghole traps in HfO 2, we achieved high responsivity
through photogating effect.

Tomohiro Akazawa
We have been conducting research on optical interconnection and I/O of LSIs using silicon pho-

Uchida Laboratory（http://www.ssn.t.u-tokyo.ac.jp）

tonics and other technologies. We have successfully
demonstrated a multi-bandgap III-V-on-insulator

Nanoscale Molecular Sensors for Volatile Organic(III-V-OI) wafer using quantum well intermixing.

Compounds (VOC)

As a result, passive waveguides, photodetectors, and

Ken Uchida

optical modulators were monolilthically integrated

Human breath contains various kinds of volatile

on a III-V-OI wafer.

organic compounds (VOCs), in which metabolites
related with diseases or health condition should be

Si photonic integrated circuit for AI

included. Therefore, we can expect that the very early

Mitsuru Takenaka, Hanzhi Tang, Yuto Miyatake, Ko-

diagnosis of the disease could be achieved, if VOCs

hei Watanabe, Kazuma Taki, Mingzhi Huang, Akifumi

related with human diseases can be selectively detect-

Kurumatani

ed. We have experimentally demonstrated successful

We have been conducting research on deep learn-

operations of low-power metal-nanosheet-based mo-

ing for AI using programmable photonic circuits

lecular sensors. However, atomistic-level simulationsuch as universal optical circuits. We have demon-

methodologies which can reproduce the response of

strated a non-volatile optical phase shifter in con-molecular sensors have not been established. We havejunction with a III-V/Si hybrid MOS phase shifter

developed a new atomistic simulation method for

and ferroelectric FET.

molecular sensors by combining the molecular dynamics simulation and the nonequilibrium Green's

Ge mid-infrared photonic integrated circuit
M. Takenaka, Ziqiang Zhao, Yuto Miyatake, Chao
Zhang
We have been studying mid-infrared photonic integrated circuits based on Ge waveguides formed onfunction method. In future, the developed techniquewill be applied to various types of molecular sensors
and the accuracy will be intensively checked to further improve the calculation technique and to findmaterials for new types of molecular sensors.

Ge-on-insulator (GeOI) wafer. We have found thathigh-energy ion implantation of hydrogen into a Ge

Thermal-aware Design of Nanodevices

bulk wafer enables the low crystal defect density in

Ken Uchida

the Ge device layer, resulting in obtaining an n-type

LSI has drastically improved the performance

Ge-OI wafer. As a result, a low-loss Ge waveguideby reducing the size of MOS transistors. Recently,

was obtained using an n-type GeOI wafer.

the introduction of new three-dimensional device
structure; nanosheet transistor, is expected, and the2D material devices
Mitsuru Takenaka, Roda Nur, Tipat Piyapatarakul

38

Joule-heating-induced temperature rise in device
channel is suggested as one of the most serious prob-

Mita Laboratorylems. We have developed a technique to minimize
the operating temperature of the CMOS channel(http://www.if.t.u-tokyo.ac.jp)

by thermal-aware design. Moreover, detailed evaluTopoMEMS: Development of Ideal Variable MEMS

have been conducted in our group. The molecularin view of Future Topological Quantum Computing

dynamic simulation and the nonequilibrium Green's

Y. Mita, K.Tsuji, A.-C.Eiler,A.Higo, T.Iizuka, Z.Xu,

function method were simultaneously performed,

M.Ezawa (Dept. Applied Physics)

and it is suggested that there are vibrational modes

Recently, new computation methods that use Top-

peculiar to the Si/SiO 2 interface, and that the vibra-

ological nature are drawing much attentions in viewtional mode enhances the electron-phonon scatter-of future Quantum computing. Calculation takes

ing near the interface.

advantages Topological natures existing in several
different fields expressed as Hamiltonian matrices.

Someya-Yokota-Lee Laboratory(http://www.ntech.t.u-tokyo.ac.jp/,
https://fles.t.u-tokyo.ac.jp/)

Our team, granted by JST CREST project, tries to3
Chapter3 Research in d.lab

ations of the electron-phonon transport properties

explore electrical expression of Hamiltonian matrices used for computation. Team Mita will develop ideal variable electrical devices as well as ideal

Highly durable skin-applied electrodes for elec-

MEMS devices. We named such devices and systems

trocardiographic measurement“TopoMEMS”. As an initiating study, we have tak-Yan Wang, Sunghoon Lee, Tomoyuki Yokota andTakao Someya

en Su-Schriffer-Heeger model. We have developed aMEMS state-variable capacitor integrated SSH elec-

We developed the world's thinnest and lightest

trical circuit and have been successful in Topologicalskin attachable electrode which can measure electro-/ Trivial state switching due to MEMS device. The

cardiograms with high accuracy for one week. The

result has been presented in the top MEMS confer-

skin attachable electrode was fabricated on a stretch-ence. Then, we have identified another interesting

able nanosheet that is ultra-thin, highly durable,

compu-tation scheme by directly using dynamics ofhighly adhesive, and breathable. The nanosheet can

MEMS. Towards that end, a bistable MEMS actua-

be attached to the skin without the adhesive mate-

tor has been developed and presetnted in an interna-rials. The very thin dimethylpolysiloxane was rein-tional conference.

forced by several layers of polyurethane nanofibers
to achieve excellent mechanical durability. In fact, it

Programmable Matter - Study on LSI-MEMS ener-

enables long-term measurement of health conditions

gy-autonomous distributed microsystems for re-in daily activities, and is expected to be applied as

alization of deformable mattera wearable device for early detection of illness andpoor physical condition in the medical and healthcare fields in the future.

Y. Mita, K.Misumi, N.Usami (Dept. of Aeronautics
and Astronautics),
E. Lebrasseur, G. Hwang (LIMMS, CNRS-UTokyo IIS /CNRS C2N),
G. Ulliac, (LIMMS, CNRS-UTokyo IIS, FEMTO-ST),
J.Bourgeois, B.Piranda (FEMTO-ST, France), S. Delalande (Groupe PSA, France)
As one example of future integrated MEMS that is
expected to open new research and industrial appli-39

3
Chapter3 Research in d.lab

cation fields, the authors are trying to show a top-

bility of high electron dose and sharp edge due todown application of energy-autonomous dis-tribut-

cell (character) projection machine configura-tion

ed microrobots. A number of identical tiny robots,

is being examined. The breakthrough in question issized below 1cm, will be released in an en-vironment.

to extend the large-area EB lithography, whose pat-

Individual robot can communicate with their neigh-tern approximation have been limited to rectangularbor, stick each other, and share ener-gy, to realize

shapes, into expressing free-form smooth shapes andcooperative function. The PI is receiving a French

a number of periodical small patterns. This year, pat-National Research Center (ANR) grant on behalf oftern and process design has been successful to obtainhost professor of CNRS laboratory in the Institute ofgap structure less than 16-nm wide. The result has

Industrial Science (LIMMS, CNRS-IIS, UMI 2820),

been presented in the top MEMS conference.

together with FEMTO-ST Laboratory and PSA-Peugeot Laboratory for such “micro robots that can re-Universities-Industries collaborative research on

alize deformable substance by cooperative action,highly-functional system by MEMS post-process

named Programmable Matter”. In year 2020, anof CMOS-VLSI

electrostatic chucking actuator system that attaches

Y. Mita, T. Yamaguchi, T. Lévi(IMS-CNRS,Bordeaux),

and detaches the external skeleton of the Matter has

G. Larrieu (LAAS-CNRS,Toulouse), Y.Ikeuchi (IIS), K.Sai-

been presented in an international conference. Basedto (Nihon Univ.)on the actuation force electromagnetically ana-lyzed,

The research targets are new sensor devices,

the ideal structure of the flexible electrode (named

made by post-process at clearnrooms such as d.lab

Flexiboard) has been identified, and a reliable inte-

Takeda Supercleanroom and others, of VLSI wafer

gration process with thinned high-voltage photovol-

made through VDEC. The important finding has

taic cells have been developed.

been that VLSI wafer acquired just after transistor
fabrication could sustain processes even with heat

Integration of electrode devices on MEMS fluidic

treatment, such as deposition, ion implantation,

devicesand drive-in. In 2016, a VLSI de-vice made on Sili-

Y. Mita, A.-C. Eiler, A. Higo, T.Ezawa, E.Ota, Y.Okamo-

con-on-Insulator (SOI) wafer was successfully Deep-to (AIST), N.Washizu (Advantest), A.Takada (Advant-

RIE processed. The in-dustrial interest is its versa-est), M. Fujiwara, T.Sawamura

tility – many different types of application devices,

Towards the goal of production of brand-new sen-which differ one from another according to request

sor devices with higher sensitivity and func-tionality,of market, can be fabricated by using the same tech-

the team is working on small-gap electrode fabrica-

nology. More and more companies are interested intion process. This year, we have newly acquired athe scheme and are working on the technology on

Fully-Depleted SOI VLSI device for massively paral-

the col-laborative research projects, including inter-lel measurement and its post-process have been de-national cooperative research projects. This year, aveloped.

world’s lowest-level (1.5V) soft microactuator withhighest figure-of-merit has been developed and pre-Fine Large-Area Electron Beam Lithography Expo-sented in the top MEMS conference.

sure Methods
A. Higo, Y. Ochiai, M. Fujiwara, T.Sawamura, Y. Mita

High-sensitive ultrasonic probe by integrated

The team explores newly-acquired (in 2013) rap-

MEMS technology

id electron beam writer F7000S-VD02. The ca-pa-

40

Y. Mita, A.Higo, T.Yoshimura (Osaka Prefectural Uni-

versity), T.Mizuno (Konika Minolta), K.Suzuki (Konika
Minolta), Y.Nakayama (Konika Minolta), T.Endo (Nagoya Medical Center)
Using the same scheme as above mentioned
project aims at integrating piezoelectric materialand MEMS post-processing to obtain a brand-new
ultrasonic inspection probe, whose sensitivity is as
100 times as cutting-edge technology. In year 2020,
the team investigated LSI test circuit of high-voltage
electronic circuit, fabricated by support from a public funding from Japan Agency of MEdical Researchand Development (AMED). This year, the fully-in-

3
Chapter3 Research in d.lab

CMOS-MEMS post process R&D scheme, thistegrated system has been investigated.
Test Structure for high-density CMOS-MEMS hybrid integrated Technology
Y.Mita, Y.Ebihara, A.Mizushima, T.Yoda (TITech),
K.Hirakawa (TITech), M.Iwase (TITech), M.Ogasawara(TITech), A.Higo and Y.Ochiai
Chip-level highly-dense bonding integration is
drawing high attention to simply obtain high-functional system; it has been almost impossible to individually examine pad-to-pad connec-tions, whose
size is in an order of several microns and whose number is order of 1 million. New test structures andmethods are mandatory. We have proposed a twopads-per-probe scheme, in which one of the pad isused for testing pad to make what we call “loop-backtest”. A test LSI have been designed, fabricated, andintegrated with gold bumps as well as MEMS test
structures. The failure mode has been emulated andsuccessfully verified. The result has been presented
in an international conference.

41

Appendix
A.1

A-1

VDEC CAD Tools

Appendix

Since 1996, VDEC has provided CAD software licens-

other public universities, private universities, and colleges.

es to the registered researchers in universities and colleges

When one is going to use VDEC CAD tools and chipin Japan. The CAD tools we provided in 2022 throughfabrication service (the details are described in Section

the activities of VDEC in Systems Design Lab (d.lab) are1-3), some faculty member of his/her research group in

shown in Table A.1.1. The researchers can use those CAD

a university or a collage needs to do user registration.

tools when their local machines, whose IP addresses are

Figure 1.2.2 shows (a) the number of registrants, (b) the

registered in advance, are authorized by one of VDEC li-

number of distinguished universities/colleges of the reg-cense server located in the ten VDEC subcenters shown in

istrants, and (c) the number of registrants who applied

Figure A.1.1. For each CAD tool, VDEC provides 10-100

VDEC CAD tools, (d) the number of applied licenses offloating licenses. Those CAD tools can be utilized only for

all CAD tools.

research and education activities in national universities,
Table A.1.1 VDEC CAD tools
Name
Cadence tool set

Synopsys tool set

Mentor tool set
Silvaco tool set
ADS/Golden Gate
Bach system
LAVIS

Function
VendorVerilog-HDL/VHDL entry, Simlation, Logic synthesis, Cadence Design Systems, Inc.
Test pattern generation, Cell-based (including macros) place, route, and back-annotation, Interactive
schematic and layout editor, Analog circuit simulation, Logic verification, Circuit extraction
Verilog-HDL/VHDL simulation, Logic synthesis, Test Synopsys, Inc.
pattern generation, Cell-based (including macros)place, route, and back-annotation, Circuit simulation,
Device simulation
Layout verification, Design rule check
Mentor Graphics Co. Ltd.
Fast circuit simulation
SilvacoDesign and verification of high-frequency circuits
Keysight Technologies
BachC-based design, synthesis, and verification
Sharp
Layout visualization platform
TOOL

Fig. A.1.1

42

VDEC Subcenters

Table A.2.1 Chip fabrication schedule in 2021
0.8μm CMOS (On-Semiconductor - Sanyo)
Chip application deadline
2021#12021#22021/7/5
2022/1/11

Design deadline
2021/9/27
2022/3/28

Chip delivery
2022/2/1
2022/6/16

0.18μm CMOS (Rohm)
Chip application deadline
2021 #1
2021 #2
2021 #3
2021 #4

2021/4/5
2021/6/14
2021/8/4
2021/12/6

Design deadline
2021/6/28
2021/9/6
2021/10/27
2022/2/28

Chip delivery
2021/9/21
2021/12/24
2022/2/13
2022/6/10

A-1

SOTB 65nm CMOS
Design deadline

Chip delivery

2021/7/26

2022/1/28

2021 #2 2022/1/24

2022/3/7

2022/8/27(est)

Appendix

Chip application deadline
2021 #1 2021/6/14

43

A.2 S tatus of Chip Fabrication Support at Platform Design Research
Division
As for the support for VLSI chip prototyping, inthe pilot project in FY 1994 and 1995, there wasonly one foundry, NEL's CMOS 0.5μm (the process
was later continued by Hitachi Hokkai Semiconductor). After the inauguration of VDEC in 1996, the
1.2-μm CMOS process of Motorola Japan (which
was continued by ON Semiconductor in 1999) started cooperation, and the 0.6-μm CMOS process of
A-2

ROHM was added in 1997. In 1997, CMOS 0.6μm

Appendixfrom ROHM was added, followed by 0.35μm from
Hitachi, Ltd. in 1998, and 0.35μm from ROHM
in 1999. In addition, as part of the IP development
project, a prototype of STARC 0.13μm was devel-(a) Trend of number of designs fabricated.

oped. Since FY 2001, we have been providing services of CMOS 0.18μm from Hitachi, Ltd. In 2002,
under the leadership of Dr. Iwata of Hiroshima University, we conducted a trial trial fabrication service
in cooperation with VDEC and MOSIS. This service
provides overseas fabs such as TSMC and IBM at
low cost through MOSIS. Furthermore, under theleadership of Dr. Shibata of the University of Tokyo,
NEC Compound Device, Inc. provided a prototype
service for bipolar LSI. In 2004, we started prototyping Oki Electric CMOS SOI 0.15μm process
and ASPLA 90nm process as test prototypes, andthe 90nm prototype was operated as a regular prototype from 2005 in the form of public solicitation.

(b) Trend of designed area.

In FY2006, we started trial production of 0.18μm
process by ROHM and test production of 0.25μm
SiGeBiCMOS by Hitachi, Ltd. In FY 2007, we started to study an advanced process to succeed 90nm
CMOS, which was terminated in FY 2007, and in
FY 2008, we started trial production of eShuttle's
65nm CMOS. In addition, as part of the METISTARC project "Next Generation Semiconductor
Circuit Architecture Commercialization Support
Project," prototype production using Renesas Electronics' 40nm CMOS was also started. On the other
hand, CMOS1.2μm was terminated in September
2011, Renesas Electronics' 40nm CMOS prototyping was terminated in 2012, and eShuttle's 65nm
CMOS prototyping was terminated in August 2013.
As a successor to CMOS 1.2μm, a test prototype of

44(c) Trend of designed area normalized by design ruleFigure A.2.1 Trend of number of designs and designed chiparea.bCMOS 0.8μm was conducted in October 2012 withthe cooperation of Onsemi-Sanyo Semiconductor
Manufacturing Co. As for the leading-edge prototyping, STMicroelectronics started FD-SOI 28nm
CMOS prototyping through CMP of France in FY
2013. In addition, we started SOTB 65nm CMOS
prototyping by Renesas Electronics as a regular prototyping in FY2015. In FY2021, we started BiCMOS 0.18um prototypes under an agreement with
IHP of Germany.
Fig. A.2.1(a) shows trends of number of chipA-2

6 years until 2001, the number of designed chips
shows steady increase, which means drastic improveof the effectiveness researches and education of LSI

Figure 2.3.2 Trend of number of processors and universities
fabricated chip.

Appendix

designed for VDEC chip fabrication. For the first

design, and we assume drastic increase of number ofstudents related to LSI chip design and education.
During few years of stable number around 400 chip
designs per year, we can see transition of designs toward finer process. In 2007, we saw a large drop,
which was caused by sudden process transition from0.35μm CMOS to 0.18μm CMOS, and in 2008,
we also saw another drop by process transition from
90nm CMOS to 65nm CMOS.
Fig. A.2.1(b) shows trends of designed chip area,
which shows much clear trends of drop by process
migration. On the other hand, Fig. A.2.1(c) shows
trends of designed chip area normalized by design
rule, which assume to be strong relation with design
efforts. Coming from the fact that the normalized
chip area is still growing, we assume the major reason for decrease of number of chips and designed
area is increase of design effort per chip and per unit
area due to process scaling.
Fig. A.2.2 shows trends number of professors anduniversities fabricated chip. Number of professors
who have contracted NDA for process technologies to access design rules and design libraries are,92, 287, and 49, respectively, for 65nm CMOS,
0.18μm CMOS, and 0.8μm CMOS.

45

A.3

SeminarSeminars are always needed as the advancement of LSI

tools, tutorials on these tools are highly demand-

design technology. In 2021, VDEC has held CAD Semi-

ed. VDEC offers the CAD Seminar twice per year.

nar, Refresh Seminar, and Designer's Forum, for academic

In the CAD Seminar, VDEC invites lecturers fromand industrial circuit designers. In this fiscal year, all thevenders including Cadence, Synopsys and Keysightseminars were held online due to the pandemic of COV-

to give tutorials on their CAD tools. The seminar is

ID-19.

held in VDEC, The University of Tokyo and VDEC
sub-centers simultaneously in several universities na-

A.3.1 CAD Seminar for VDEC users
A-3

tionally, August, September, and March of one fiscal

Along with advancement of circuit design CAD

year. Each tutorial takes one or two days.

Appendix

Table A.3.1 CAD technical seminar in 2021 fiscal year
CAD Seminar I
Date

Tutorial

8/3

Keysight Empro

8/17
8/24
8/30
9/22
Until 9/30
Until 9/30

Synopsys IC Compiler-II
Synopsys IC Validator
Cadence Virtuoso Schematic, Layout
Synopsys Custom DesignerCadence Innovus
Keysight Empro

Venue

Attendees

Online40

OnlineOnlineOnlineOnlineOn-demand
On-demand

41
40
22
6
12
12

Venue

Attendees

Online31

OnlineOnlineOnlineOnlineOn-demand
On-demand
On-demand

58
34
37
29
65
61
38

CAD Seminar II
Date

46

Tutorial

3/4

Cadence Innovus

3/8, 9
3/11
3/15, 16
3/29
Until 3/31
Until 3/31
Until 3/31

Cadence Layout (GXL, EAD)
Cadence EMX
Cadence SKILL
Synopsys TCAD Q&A Meeting
Synopsys Design Compiler
Synopsys ICC-II
Synopsys TCAD

A.3.2 Refresh Seminar for industry and academia
The fundamental and advanced knowledges are both
imperative to integrated circuit design. VDEC offers theRefresh Seminar for industrial and academic people. University professors and highly experienced engineers areinvited to give lectures on circuit design, covering the topics on analog, digital, RF, MEMs, and basic design flow.
The seminar was originally launched in 1998, with thesupport of Ministry of Education Technical Education
Division. It is now being supported by several industrial/academic societies.

A-3
Appendix

Fig. A.3.1 Refresh Seminar at VDEC seminar room at the University of Tokyo, VDEC.

Fig. A.3.2  Screen shot of Refresh Seminar online.

47

Table A.3.2 Refresh Seminar
Date

Course5/31, 6/1

CMOS-RF Circuit
Design8/11, 12

VDEC Digital Circuit
Design Flow

8/25, 26, 27 Analog Circuit Design

A-3
Appendix

9/2, 3

Contents
Modulation/Demodulation
Cascaded connection
Basic Performance
Transceiver Architecture
Circuit Element
Design Flow
Digital circuit design flow using
VDEC-collaborated CAD environment
and process
Analog Circuit Design and simulation
Integrated Circuits Verification (LVS,
DRC)

VDEC LSI designer forum intended for students andyoung teachers were held. The VDEC LSI designer forum has aimed to sharing the information that generally
hard to be obtained common technical reports or academical papers, such as the failure an LSI designer had been
through and the solution, and the construction method in
the design milieu in the laboratory.

Table A.3.3 Program of Designers Forum in 2021
9/24 Online Attendees: 54

13:40 – 15:00
15:00 – 15:10
15:10 – 16:30
16:30 – 16:40
16:40 – 17:40
17:30 ~

48

Hiroyuki Ito(Tokyo Inst. of Tech.)

Kazutoshi Kobayashi(Kyoto Institute ofTechnology)
Masahiro Sugimoto(Chuo Univ.)
Tetsuya Iizuka(The Univ. of Tokyo)
Koji Kotani(Tohoku Univ.)

Custom circuit design flow using
Transistor-Level Circuit
Toru Nakura
VDEC-collaborated CAD environment
Design Flow
(Fukuoka Univ.)and process

A.3.3 Designer's Forum for academia

9/24
9:30
10:00 – 10:15
10:15 – 11:15
11:15 – 12:30
12:30 – 13:30
13:30 – 13:40

LectureReception
Opening
Idea Contest Presentation
Lunch
Keynote Speech
Break
Design Award Presentation I
BreakDesign Award Presentation II
Break
Design Award Presentation III
Voting and Award Ceremony

Attendees

20

44

67

23

A.4

Venture companies related to VDEC

Some professors related to VDEC started venture companies. The following is a list of the venture companies
related to VDEC.
[1] AIL Co.,Ltd. (http://www.ailabo.co.jp/)
Related professor : Professor Kazuo Taki, Kobe Univ. (Representative Director)
Description of business :(1) LSI design service(2) Engineer dispatching service(3) Recruitment(4) Management consulting(Merged with Soliton Systems on July 1st in 2017, http://www.synthesis.co.jp/)
Related professor : Professor Emeritus Isao Shirakawa, Osaka Univ. (Director)
Description of business :Appendix[2] Synthesis Corporation

A-4(1) System LSI development and design service(2) IP development and sales(3) Development and sales of IPs(4) Development of EDA tools[3] ASIP Solutions (http://www.asip-solutions.com/)
Related professor : Professor Masaharu Imai (Representative Director, CTO)
Description of business :(1) R&D, education and consulting of IoT application system(2) Sales of ASIP design tool and consulting of ASIP development[4] Nanodesign Corporation (http://www.nanodesign.co.jp/)
Related professor : Professor Kazuyuki Nakamura, Kyushu Institute of Technology. (Rep-resentative Director)
Description of business :(1) LSI design and development(2) Development of LSI CAD and LSI evaluation tools(3) Design consulting, etc.

[5] A-R-Tec Corp. (http://www.a-r-tec.jp/)
Related professor : Professor Emeritus Atsushi Iwata, Hiroshima Univ. (Representative Director)
Description of business :(1) Analog IC design and measurement(2) PCB noise analysis(3) Develop human resources, OJT, Lecture[6] Ishijima Electronics (http://ishi.main.jp/)
Description of business :(1) Electronic circuit and board development(2) Software development(3) Consulting

49

System Design Lab (d.lab),
School of Engineering, The University of Tokyo
Annual ReportAugust, 2022
Published by
System Design Lab (d.lab), School of Engineering, The University of Tokyo
Tadahiro Kuroda
Address: Hongo 7-3-1, Bunkyo-ku, Tokyo, 113-8656, Japan
Printed in
SOHOKKAI co., Ltd. Tokyo Branch
Address: Koutoubashi 4-25-10, Sumida-Ku, Tokyo, 130-0022, Japan
Copyright Ⓒ by System Design Lab (d.lab), School of Engineering, The University of Tokyo

Systems Design Lab, School of Engineering, The University of Tokyo 2022