Kilho Lee

Pedro Pachuca

Principal Engineer,

Director,

Samsung Semiconductor

GLOBALFOUNDRIES

Dr. Kilho Lee is Principal
Pedro Pachuca is the director ofEngineerofAdvanced
the global microcontroller
Technology
Development
business
line
at
Team
in
Samsung
GLOBALFOUNDRIES, Pedro
Semiconductor R&D center, leading the development brings more than 25 years of experience in theof STT-MRAM products. He has been working on the semiconductor
industry.
Prior
toresearch of various new memories such as MRAM, GLOBALFOUNDRIES Pedro held multiple business
PRAM, RRAM and FRAM. He received Ph.D. degree and technical positions at Freescale semiconductor,
in Materials Science and Engineering from POSTECH Silicon laboratories and Renesas electronics, deeply(Pohang University of Science and Technology) in involve in architecture definition of embedded
South Korea in 2005. He was a post-doctoral systems with Non-Volatile Memory (eNVM).
researcher in UC Berkeley from 2005 to 2007,
studying multiferroic materials. Since he joined Global Foundries MRAM Solutions
Samsung Electronics in 2007, he has contributed to thedevelopment of MRAM and PRAM. His specialty is for IoT and Industrial Applications
to integrate new memory devices and establish new With eFlash reaching its economic scaling limit at thecharacterization method and reliability standards
28nm node, MRAM has emerged as the technology ofchoice to meet AI, IoT, Industrial, and Automotive
application requirements.
With the increasing
Embedded STT-MRAM
functionality and data requirements for today’s
Development for Frame Buffer
applications, embedded memory has need to not only
Memory Application with CISdemonstrate cost scaling but has also been challenged
to improve performance metrics. Memory is being
compatible Process
pushed to support very high endurance and excellent
Unlike conventional memories such as SRAM, retention under harsh environmental conditions while
eDRAM and eFlash, STT-MRAM covers a wide simultaneously increasing memory capacity. The
spectrum of applications. One of the unique and drive towards faster CMOS logic is pushing for
fascinating features of MRAM technology is the improved read/write latencies, and the pervasivenesssystematic tunability of major properties, such as of mobile processing drives the need to support ultraswitching current, retention and endurance. From this low leakage and low power modes. In this session, we
point of view, we successfully present eMRAM as a will describe how GlobalFoundries is meeting ourframe buffer memory solution for future mobile and customer’s requirements with production-readywearable applications by developing reliable fast industrial grade MRAM solutions as well as theswitching property with superior endurance. We opportunities and challenges facing MRAM towards
demonstrate embedded STT-MRAM fully integrated empowering the continued development of
onto 28nm CIS logic platform, highlighting the world- differentiated, feature-rich products.
best macro density of 13.94 Mb/㎟. The macroprovides 55% area saving over 28nm SRAM. The
Yuan-Jen Lee
MTJ processes are compatible with standard 3DTechnical Manager,
stacked CIS integration processes that requiresufficient 400℃ heat budget. For fast write operation
TSMC(<50ns) and high endurance property (>1E10 cycles)with 400℃ BEOL compatibility, each ultra-thin
Yuan-Jen Lee is a Technicalmagnetic layers have been systematically re-designed.
Manager of MRAM Program at
Furthermore, we have confirmed superior scalability
TSMC. He has 16 years ofof MTJ processes beyond 28nm. With advanced MTJ
professional experiences in thepatterning processes, we have verified that MTJ short research and development MRAM. Prior to joining
failure rate can be suppressed below 1ppm even at a TSMC, he was a Senior Manager in the STT-MRAM
40% smaller pitch as compared to the current MTJ team at TDK-Headway Technologies. He received
pitch at 28nm. This result reveals that our frame-buffer Ph.D. degree in Physics from National Taiwan
STT-MRAM technology is scalable to 14nm FinFET University in 2003. He has published 30+ MRAM
node. These achievements provide a substantial relative papers and holds 20+ issued U.S. patents.
progress of eMRAM towards wide-range applications,and eMRAM solution will provide differentiated N16 Embedded MRAM Technology
benefits with power-saving and low cost.

for Reflow Application and Beyond

Embedded MRAM (eMRAM) is expected to replace the stringent performance and reliability requirements
embedded Flash (eFlash) for microcontroller unit of the industrial market. We have achieved high speed(MCU) applications beyond the 28 nm technology reliable switching over the full operating temperaturenode. Compared to eFlash, eMRAM not only excels range from -40°C to +85°C with data retention of morein write endurance and write speed, it also provides than 10 years at +105°C and endurance of greater thansignificant cost advantage as fewer masks are required 1e15 cycles at -40°C. This advanced STT-MRAM
to integrate memory device. This quick process technology will be deployed in an upcoming line ofturnaround is also a boon in the current semiconductor Serial Peripheral Interface (SPI) products, delivering
chip shortage environment. The N16 solder-reflow- the highest performance SPI STT-MRAM on thecapable eMRAM can operate up to 150°C for market.
automotive grade-1 applications. The memory cellarea of the reflow eMRAM is 0.033 um2, a 28%
Brent Yardley
reduction in area versus the 22nm eMRAM cell.
While the critical dimension (CD) of MTJ is reduced
Senior Technical Staff
vs. MTJ in 22nm eMRAM cell, it continues to achieve
Member,good data retention and reflow yield. The MTJ film
IBMstack is optimized to achieve sufficient read marginand high reliability yield at 150°C.
Brent Yardley is a SeniorIn addition to the cell optimized for reflow andTechnical Staff Member andautomotive usage, a high-yielding MRAM cell withMaster Inventor with IBM
0.018 um2 area is demonstrated on 16nm technology Systems, where he focuses on developing All Flashwith shorter write time and low write power to support Arrays (AFAs). Brent is currently the overall Chief
RAM-like applications where MTJ optimization focus Hardware Engineer responsible for the hardwareon improving write speed and higher memory density architecture, design, and integration of IBM's storage
compared to SRAM.
hardware products and planning future generation
storage platforms. He specializes in system designs
that integrate multiple I/O protocols, FPGAs, and
ASICs, and is an expert in both hardware and software
design and system integration. A 21-year veteran ofIBM, Brent holds multiple patents focused on storage
Senior Director,
architectures and solutions. He has an extensive
Everspin Technologies
background and understanding of the architecture,design, and implementation of highly available
Dimitri Houssameddine is storage-based systems and solutions. He has earned
Senior Director of Product BS degrees in both Software and Hardware
Characterization and Reliability at Everspin Engineering from the Oregon Institute of Technology.
Technologies, where he focuses on bringing new
MRAM products to market. He has extensive
experience on STT-MRAM technology development MRAM for IBM FlashCore modules
with a focus on product and device characterization. Solid State Devices (SSDs) are prolific in the all flash
Throughout
hiscareerwithEverspin, array enclosures. Power loss protect for these devices
GLOBALFOUNDRIES and IBM, he has been an can be implemented in a number of ways. IBM
integral member of teams commercializing STT- FlashCore Modules has taken a unique approach to
MRAM for standalone and embedded applications. this design, by using STT-MRAM as a form of power
Dimitri received his Ph.D. in Physics from Joseph loss protection media, which allows for the reduction
Fourier University, Grenoble, France.
of the total energy needed one when of these eventsoccurs. This presentation covers the use of STTMRAM in the IBM FlashCore Module to assist in data
Spin-Transfer Torque MRAM
protection of the device during power loss use cases.

Dimitri
Houssameddine

Technology For Low-Latency
Industrial Applications

Kazuhiro Bessho

STT-MRAM technology is gaining traction in the
Senior Manager,market and being used in an increasing number ofapplications such as for data centers, industrial
SONY
products, wearable devices, or aerospace. Successful
Kazuhiro Bessho is a Senioradoption of an emerging memory product requires
ManageratSony
careful co-optimization of the technology and circuit
Semiconductor
Solutionsdesign. This presentation introduces the next
Corporation currently engaged
generation of Everspin’s MRAM technology
in
STT-MRAMdevelopment.
He joined Sony in 1992
optimized for low-latency industrial applications. We
andstartedtheresearchon
analysesof magnetic films
will cover the evolution of our technology to addressand nanostructures. After studying on GMR/TMR competitive process for RF-MEMS devices targeting
materials at Stanford University in 1996-1997 as a mobile phone market. Prior to that he developed
visiting researcher, he launched the development of advanced BCD/CMOS device technology at Atmel’s
MRAM at Sony in the early 2000s.
analog and mixed-signal foundry in France and at the
Semiconductor Division of Teledyne Dalsa in Canada,
3D stacked CIS compatible 40nm where he also led MEMS inertial sensors testdevelopment for mass production. He holds a Ph.D.
embedded STT-MRAM for buffer from the University of Nantes, and he is Engineer frommemoryPolytech Nantes School of Engineering.
STT-MRAM has attracted increasing attention to
replace embedded-flash memory and SRAM [1-6] Test architecture addressing MRAM
owing to its high-performance operation and CMOS
specificities for High Volume
compatible process. Compared with SRAM, STTManufacturing
MRAM has the advantage of not only achieving nonvolatile data retention but also possessing smaller bit Replacement of transistor-based memories by MRAM
cells that enable larger capacity of buffer memory. In is on the way of being proven with the recent
this work, we demonstrate a 40nm 30Mbit embedded commercial introduction of Spin Transfer Torque
STT-MRAM for buffer memory, that is compatible (STT)-MRAM for eFlash applications at 22nm andwith the 3D stacked CMOS image sensor (CIS) 28nm technological nodes. The promising next steps
process. We optimized a CoFeB-based perpendicular for MRAM in the coming years are to overcome
magnetic tunnel junction (p-MTJ) to suppress SRAM issues on power consumption and integration
degradation of the magnetic properties caused by the density at single digit technological nodes. Since
3D stacked wafer process. With improved processes, MRAM are introduced at back-end-of-line (BEOL),
we achieved high speed write operation below 40 ns excelling on process control and yield performances
under typical operation voltage conditions at -30 °C, are crucial for High Volume Manufacturing (HVM) as
endurance up to 1E+10 cycles at 105 °C and 1 s data the largest part of the manufacturing process is alreadyretention at 85 °C required for a buffer memory. In executed when building the MTJ, including the front
addition, to broaden the applications of embedded end of line (FEOL) most expensive steps. Indeed,
MRAM (eMRAM), we propose a novel fusion when the wafer is ready to be tested with BEOL MTJs,
technology integrating embedded non-volatile the fab process cost ratio is at 70-90% of the final chipmemory (eNVM) and buffer memory type embedded cost. Therefore, accurate metrics to determine “goodMRAM on the same chip through p-MTJ size die” or fabrication issues are essential to secure themodulation. We achieved a data retention of 1 s to >10 remaining test and assembly process cost. The
years with a sufficient write margin using the fusion designed test flow of eMRAM chip should be at thetechnology.
same time cost efficient (high throughput) and[1] J.G. Alzate et al., IEDM, 2019, [2] S. H. Han et al., IEDM, consider STT-MRAM specificities at each test stages
2020(MTJ, arrays and chip). Hence, a metrology flow
[3] T. Y. Lee et al., IEDM, 2020, [4] V. B. Naik et al., IEDM,
smartly designed at the utmost with consideration of2019[5] O. Golonzka et al., IEDM, 2018, [6] Yi-Chun Shih et al., the Magnetic Tunnel Junctions (MTJ) and writing
mechanisms physics involved (STT, SOT…) are key
IEDM, 2020.
to ensure that chip product meet the target
specifications.
Siamak Salimy
Even though STT-MRAM use in final product isCTO,
purely electrical, the stored information is magnetic
and the programming (state switching of the MTJ) can
HPROBEbe triggered from electrical current, temperature or
Dr. Siamak Salimy is founder magnetic field. Because of this, magnetic andand CTO of Hprobe, a company temperature simultaneously used during electrical test
providing Automated Test are introduced at the Wafer Acceptance Test (WAT),
Equipment (ATE) for High Wafer Sort (WS) and Final Test (FT) to establish
Volume Manufacturing (HVM) of MRAM and secured foundation to support STT-MRAM ramp-up
magnetic sensor. He has more than 15 years in HVM. In this presentation, I will discuss the testing
experiences in semiconductor test development and requirements for HVM of STT-MRAM in the back
implementation for chip products and device end and assembly process and analysis the test
technologies (CMOS, BCD, MEMS sensors, RF- architectures compared to traditional purely electrical
MEMS and Spintronics) dedicated to large scale ‘CMOS like’ manufacturing processes. I will present
deployments on both consumers and automotive state of the art solutions test cases of WAT and WS,
applications. He is currently leading Hprobe and envisioned solutions by Hprobe to improve testing
technology and products development. Prior to that, he speed.
oversaw back-end test implementation at Delfmems(France) where he released in production a

Additionally, the time delay in adoption of newtechnologies into defense products can take a decadeor more, governed by a prescribed maturation process
RMD JUMP Liaison,utilized within the industry, the Technology Readiness
Raytheon Technologies
Level (TRL) scale. The rate limiting processes within
Mike Burkland has been with the TRL lifetime are usually paced by qualification,
Raytheon in Tucson, AZ since the degree of disruption to existing systems of
1999. He currently facilitates adoption, as well as the establishment of a reliable andthe identification and creation affordable supply chain.
of technologies to support innovative solutions for The hopeful light at the end of the tunnel may be with
Raytheon Missiles & Defense business needs. A the development of low temperature Back-End-Of the
primary focus is directing development of advanced Line (BEOL) fabrication of novel memory and logic
microelectronics technologies through Raytheon’s technologies; specifically vertical CMOS and beyond
participation in the Semiconductor Research CMOS devices, with lower fabrication cost. For
Corporation JUMP and nCORE university research instance, non von Neumann architectures are being
programs. From Purdue University Mike earned a investigated using STT-RAM for high throughput, lowbachelor’s degree in physics and mathematics, and a energy and latency processing [2]. However, further
Ph.D in physics with a minor in quantum optics from opportunities emerging from domestic research, suchas university research sponsored by thethe University of Arizona.
Since 2015 Mike has represented Raytheon in Semiconductor Research Corporation [3], can only be
SRC research, first in the STARnet program and transferable by a robust industrial base supporting
continuing into JUMP and nCORE. From this history successful rapid prototyping and sustained production.
of engagement, a number of DARPA contracts have Cognizant of these issues, the United States has
been awarded to Raytheon in partnership with recently increased investment in on-shore advanced
academic researchers for further maturation of SRC microelectronics development and manufacturing via
research products.
Over the course of his career, the recently passed $52B CHIPS Act. Thus, a pivot by
Mike has authored over ten patents and has existing commercial microelectronics suppliers,
publications spanning research in Meteoritics to especially those with magnetic-based device
fabrication, in support of low volume (compared toElectro-Optics.
commercial) specialized BEOL microelectronics innear-term would provide for emerging defense
Technology transfers into the defense theneeds while laying a foundation for a larger
industry: implications for spintronics commercial market demand anticipated in the coming
five to ten years [3]. As well, opportunities forin the future of national security
emerging spintronic-based suppliers could address a
President Eisenhower, in his 1961 farewell address to market segment of TRL 4-6 range of near-term DIB
the nation, warned “against the unwarranted influence, development needs.
whether sought or unsought, by the Military-Industrial [1] W. J. Lynn III, "The End of the Military-Industrial
Complex.” The concern of excessive government Complex", Foreign Affairs Magn., Nov/Dec (2014).
spending on defense continues to be a contentious [2] K. Kim et al., "MRAM-based Deep In-memory
issue today. However, coupled with President Architectures", GOMACTech21, (2021).
Kennedy’s plan to put a (US) man on the moon, [3] J. Neuffrer et al., "Decadal Plan for Semiconductors",
Semiconductor Research Corp., (2021).
government investment in microelectronics continued
through the 1980’s and helped position the United
Shinji Yuasa
States as the only super power to emerge from theCold War – with the defense and aerospace industries
Professor,
driving innovation.
By mid-1990 the tide had shifted with commercial
AISTelectronics as the market driver of design andShinji Yuasa received a PhD inapplications. In 2014, William Lynn III, the former
Physics from Keio University
Deputy of Defense, wrote of “The End of the Military(Yokohama, Japan) in 1996.
Industrial Complex,” emphasizing the need of theAfter receiving his doctorate, hedefense industry to work with, and incorporate from,servedasa
staff
scientistat the National Institute of
the commercial sector [1].
Advanced
Industrial
Scienceand Technology (AIST).
While the collaboration of the Defense Industrial Base
Since
2010,
he
has
been
a
Directorof research center(DIB) with the domestic commercial microelectronics
at
AIST
and
a
Professor
atUniversityof Tsukuba.
sector has been sufficient to meet the demand, the cost
Since
2000,
he
has
been
studying
thin
film
magnetism
and
time
of
developmentofadvancedandspintronics,
more
specificallythetunnelmicroelectronics has dramatically increased while themagnetoresistance(TMR)
effectandspin-transfer
supply from domestic foundries has become limited
torque (STT) in magnetic tunnel junctions (MTJs) andwith industry consolidation.
their applications to various devices such as magnetic

Michael Burkland

sensors and magnetoresistive random-access-memory joining ASU in 2019, he was an assistant professor in(MRAM). His most important scientific achievements Department of Electrical and Computer Engineering at
are the development of MgO-based MTJs including University of Central Florida, Orlando, FL, USA. He
CoFeB/MgO/CoFeB-type MTJs and their applications received his M.S. and Ph.D. degrees, under theto read heads of hard disk drives and STT-MRAM. For supervision of Prof. Kaushik Roy, in Electrical andhis pioneering contributions to the MgO-based MTJs, Computer Engineering from Purdue University, Westhe has been awarded or co-awarded more than 20 Lafayette, IN, USA, in 2012 and 2015, respectively.
awards and prizes, including the Asahi Award in 2008 Dr. Fan’s primary research interest includes Energy
and IEEE Fellow in 2021.
Efficient and High Performance Processing-InMemory Circuit, Architecture and Algorithm crosslayer software & hardware co-design, with
Voltage Control of Magnetic
applications in Deep Neural Network, Data
Anisotropy for Voltage-Controlled Encryption, Graph Processing and Bioinformatics;
MRAM
Hardware-aware deep learning optimization;
Adversarial
AI
security;
Brain-inspired
Giant tunnel magnetoresistance (TMR) effect and(Neuromorphic) Computing. He has authored and cospin-transfer torque (STT) in MgO-based magnetic
authored130+peer-reviewed
internationaltunnel junctions (MTJs) are the key technologies injournal/conference papers in above area. He is themagnetoresistive random access memory (MRAM)
receipt of best paper award of 2019 ACM Great Lakes[1]. STT-MRAM has been commercialized as
Symposium on VLSI, 2018 IEEE Computer Society
embedded non-volatile memory for system LSI. For
Annual Symposium on VLSI (ISVLSI), and 2017
MRAM to replace SRAM, however, MRAM needs toIEEE ISVLSI. His research paper was also nominatedhave higher speed and lower energy consumption foras best paper candidate of 2021 Design Automation
writing. For developing such advanced MRAM, we
Conference (DAC), 2019 Asia and South Pacifichave been working on new writing technology as well
Design Automation Conference and 2019as MTJs with materials. Voltage-induced dynamic
International Symposium on Quality Electronic
switching based on voltage control of magnetic
Design (ISQED). He is also the technical area chair of
anisotropy (VCMA) is expected to be an ultimate
DAC 2021, GLSVLSI 2019/2020/2021, ISQED
writingtechnology
withultra-low
power
2019/2020/2021, and the financial chair of ISVLSI
consumption. By doping 5d elements into Fe electrode2019. He served as technical reviewers for over 30of MgO-based MTJ, we have achieved very highinternational journals/conferences, such as Nature
VCMA coefficient (>300 fJ/Vm) [2], which isElectronics, IEEE TNNLS, TVLSI, TCAD, TNANO,
sufficient for cache memory application. The biggest
TC, TCAS, etc. He also served as the Technicalremaining issue for developing novel voltageProgram Committee member of DAC, ICCAD,
controlled MRAM (VC-MRAM) is the high write
HPCA, MICRO, WACV, GLSVLSI, ISVLSI, ASPerror rate (WER) of the dynamic switching [3]. By
DAC,
etc.
Pleaserefer
tocontrolling the spin dynamics induced by ultra-fast
https://dfan.engineering.asu.edu/ for more details.
voltage pulses, we have successfully suppressed WER
below 10-6 [3-6], which is sufficiently low for some
Energy Efficient and Intelligent
applications. Aiming at more reliable voltage-induced
switching, we have also been working on new writing
Processing-In-Memory for Datamethods based on VCMA [7,8]. In our talk, we will
Intensive Applications - Fromreview recent progress on VCMA and discuss
Device to Algorithm
perspectives of VC-MRAM.
[1] S. Yuasa, K. Hono, G. Hu, D. C. Worledge, MRS Bulletin
43, 352 (2018), [2] T. Nozaki et al., NPG Asia Materials 9, e451
(2017), [3] T. Nozaki et al., Micromachines 10, 327 (2019), [4]T. Ikeura et al., Jpn. J. Appl. Phys. 57, 040311 (2018), [5] T.
Yamamoto et al., Phys. Rev. Appl. 11, 014013 (2019), [6] T.
Yamamoto et al., J. Phys. D: Appl. Phys. 52, 164001 (2019),[7] T. Yamamoto et al., Nano Letters 20, 6012 (2020), [8] R.
Matsumoto et al., Appl. Phys. Express 12, 053003 (2019).

In-memory computing is becoming a promisingsolution to overcome the well-known ‘memory-wall’
challenge, through directly processing the data withinmemory where data is stored. Therefore, it will reduce
massive power hungry data traffic between computing
and memory units, leading to significant improvementof entire system performance and energy efficiency.
Many different memory technologies have been
Deliang Fan
explored for the design of processing-in-memory(PIM) or in-memory computing (IMC), such as
Assistant Professor,
emerging post-CMOS Magnetic Random Access
Memory (MRAM), Static Random Access Memory
Arizona State University(SRAM) or Dynamic RAM (DRAM), etc. In this talk,Dr. Deliang Fan is currently an Prof. Deliang Fan, from Arizona State University
Assistant Professor in the (ASU), will present his recent research in energy
School of Electrical, Computer efficient and intelligent cross-layer processing-inand
EnergyEngineering, memory design for data-intensive applications,Arizona State University, Tempe, AZ, USA. Before spanning from MRAM memory device &circuit to in-memory computing architecture & algorithm co- working at input power smaller than the one used for
optimization, to intrinsically integrate memory and Schottky diodes. However, from a technological point
processing units. In this talk, Dr. Fan will present the of view one wish a broadband response for energy
software-hardware co-design of PIM for different harvesting in order to collect energy from different
data-intensive applications, including deep neural source. In our recent work, we have experimentally
network, data encryption, graph processing and demonstrated that this broadband detection can bebioinformatics.
achieved by exciting nonlinear dynamics, i.e. large
amplitude magnetization precession. In particular, this
Giovanny Finnocchio has been achieved with a bias-field-free spin-torquediodes having a canted magnetization in the free layer
as equilibrium state. We have shown an efficient
Professor,
harvester of broadband ambient RF radiation to power
Messina University
a black phosphorous nanodevice. [4] Recently, it has
Giovanni Finocchio received been also shown that those devices when connected in
the Ph.D. degree in advanced series can supply also a LED. [5] I will also discusstechnologies in optoelectronic, briefly how the frequency response of spin-torquephotonic and micromagnetic diodes and their current tunability can be also used asmodeling from the University of Messina, Italy, in building blocks of the hardware realization of neurons
2006. Since 2010, he is now Associate professor now and synapses in neuromorphic applications and fort
with the Department of Mathematical and Computer hardware implementation of analog multiplication. In
Sciences, Physical Sciences and Earth Sciences at the the last part of the talk, I will show potential
University of Messina. He is director of the laboratory implementations of THz detectors based on
PETASPIN (Petascale computing and Spintronics). antiferromagnets which can be used as wake-up
His research interests include spintronics, skyrmions, receiver. [6]andcomputing [1] B. Fang et. al, Giant Spin-Torque Diode Sensitivity in the
Absence of Bias Magnetic Field, Nat. Commun. 7, (2016),(https://scholar.google.co.uk/citations?user=eKDbn- [2] L. Zhang et. al, Ultrahigh Detection Sensitivity Exceeding
oAAAAJ&hl=en). In the last 10 years, he served on 10 5 V/W in Spin-Torque Diode, Appl. Phys. Lett. 113, 102401
many technical program committees of international (2018), [3]M. Goto et. al, Uncooled Sub-GHz Spinconferences and organized more than 10 international Bolometer Driven by Auto-Oscillation, Nat. Commun. 2021
conferences and workshops as Chair, Program 121 12, 1 (2021),
Committee Member, or in other positions. He is [4] B. Fang et. al, Experimental Demonstration of Spintronic
Broadband Microwave Detectors and Their Capability for
regularly invited at conferences in Magnetism and Powering Nanodevices, Phys. Rev. Appl. 11, 014022 (2019),
Spintronics. He is also president of Petaspin [5] R. Sharma et. al, Electrically Connected Spin-Torqueassociation (www.petaspin.com), chair of the IEEE Oscillators Array for 2.4 GHz WiFi Band Transmission andMagnetics Italy chapter, AdCOM member of the IEEE Energy Harvesting, Nat. Commun. 2021 121 12, 1 (2021),
Magnetics society and chair of the TC-16 on Quantum, [6] A. Safin et. al, Electrically Tunable Detector of THzneuromorphic and unconventional computing of the Frequency Signals Based on an Antiferromagnet, Appl. Phys.
Lett. 117, 222411 (2020).
IEEE Nanotechnology council.

Magnetic Tunnel Junctions forElectromagnetic Energy Harvesting
and computing

PANEL DISCUSSION:

Current MRAM wide adoption:
what is holding it back?
The spintronic technology takes advantage of themanipulation of the electron spin together with its
charge. This technology potentially combines Moderator: Jack Guedj (CEO, Numem)
important characteristics such as ultralow power
needs, compactness (nanoscale size) and it is CMOScompatible. Microwave detectors based on the spin- Panelists:
torque diode effect are among the key emerging
Scott Hanson
spintronic devices. Those devices realized withmagnetic tunnel junctions working in active regime
Chief Technology Officer,
exhibit high-detection sensitivity >200kV/W at roomAmbiq
temperature, without any external bias fields, and for
low-input power (micro-Watts or lower), [1] [2] value
Scott Hanson is the Chief
which can reach more than 1MV/W in presence ofTechnology
Officerandfield and an additional bolometric effect. [3] On thefounder of Ambiq.
Scottother hand, when working in passive regime thoseinvented SPOT, Ambiq’s coredevices can be used as electromagnetic energy sub-threshold technology platform, to enable theharvesting. We have shown that those devices can world’s most energy-efficient chips during his PhD
exhibit resonant rectification at sub-nW power studies at the University of Michigan. He foundedAmbiq in 2010 and led the development of the world Engineering from Texas A&M University in 1988 andrecord-setting Apollo, Ambiq's first flagship 1991 respectively.
processor. Under Scott's leadership, Ambiq has
shipped more than 100 million chips to the world's top
Nilesh Gharia
brands and has grown into the global leader in ultralow power solutions.
CTO,
In addition to his role as CTO, he has variously played
Numem
roles leading product definition and development,
managing production test, and, most importantly,
Nilesh has 20+ years ofspending a great deal of time with customers toexperienceintheunderstand their needs and their vision. As a widely
semiconductor industry with arecognized innovator in low power circuits, Scottdiversebackgroundin
today leads the development of Ambiq's technology semiconductor design and product development.
roadmap.
Nilesh was part of the startup team at NetLogic
Scott's pioneering work in sub-threshold design and Microsystems which went IPO in 2004, and was later
picowatt processors has been widely published, with acquired by Broadcom in 2012 for $3.7B, which inmore than 30 leading publications, more than 20 turn was acquired by Avago in 2016 for $37B. He waspatents on related technology, and a wide variety of also the 1st Engineer at Lanstar Semiconductor, which
speaking engagements. Scott's work was honored by also went IPO. Nilesh worked in Virtual Silicon
the University of Michigan with the 2014 Arbor Technology, and was responsible for team
Networks PhD Research Impact Award and the 2020 development and product design. His expertiseECE Alumni Rising Star Award and was honored by includes startups, emerging memories, memory
Ernst & Young as an Entrepreneur of the Year 2020 compiler development, MRAM technologies,
finalist.
semiconductor IP development, network processors,
and team/project management. Nilesh holds a Masters
in Electrical Engineering from the New Jersey
Zhao Wang
Institute of Technology and has a portfolio of 13 US
issued patents.
Research scientist

META/Facebook

Testuo Endho

Dr. Wang received his PhD in
Professor,
Electrical Engineering from
University of Texas at Dallas in
Tohoku University
2012. He has worked in TI,
Tetsuo Endoh joined ULSI
Qualcomm, Apple, TSMC and Facebook in different
Research Center Toshiba Co. inareas of custom chips design. Currently he is a1987 and was engaged in the
research scientist and chip lead in camera sensor
R&D of NAND Memory. He
research group in Meta RL research. His current
research interests include computing in memory, non- became a lecturer at the Research Institute of Electricalvolatile memory applications, novel sensor chip Communication, Tohoku University in 1995. He is a
professor at the Department of Electrical Engineering,architectures etc.
the Graduate School of Engineering, Tohoku
University and director of the Center for Innovative
Thomas Jews
Integrated Electronic Systems (CIES). His current
interests are novel 3D structured device technology,
CTO,such as Vertical MOSFETs; high-density memory,
NXP
such as SRAM, DRAM, 3D-NAND memory andThomas Jew is a Fellow in STT-MRAM; and beyond-CMOS technology, such as
NXP’s CTO, Front End spintronics-based non-volatile Logic for ultralow
Innovation group and currently power systems such as mobile systems, AI systems
leads Non-Volatile Memory and IoT systems. He is also interested in powerdevelopment for Advanced Microcontroller and management technology, such as GaN on Si based
Microprocessor applications. He has worked on power devices and power integrated circuits with low
discrete non-volatile memory products and embedded energy loss and low power consumption formemory designs including traditional flash and automotive applications. He received the 14th Prime
disruptive memory technologies integrated in Minister’s Award for his Contribution to Industrymicrocontrollers for IOT and automotive applications Academia-Government Collaboration in 2016.
for ~29 years. Prior to joining NXP by way of He received 2017 National Invention Award "the 21stFreescale Semiconductor/Morotola, he worked for century Encouragement of Invention Prize" on June
Texas Instruments, designing discrete flash memories. 12th for his contribution of the invent of 3D-NAND
Thomas received his BS and MS degrees in Electrical Memory technology.

13th MRAM Global Innovation ForumSan Francisco, 16 December 2021
1st Forum: San Jose, California
2nd Forum: Tokyo, Japan
3rd Forum: Paris, France
4th Forum: Seoul, South Korea
5th Forum: Tokyo, Japan
6th Forum: Santa Clara, California
7th Forum: Zurich, Switzerland
8th Forum: Seoul, South Korea
9th Forum: San Francisco, California
10th Forum: San Francisco, California
11th Forum: San Francisco, California
12th Forum: Virtual

Chair: Bernard Dieny, Luc Thomas and Kevin Garello
Program committee:
Daniel Worledge (IBM Research, USA)
Luc Thomas (Applied Materials, USA)
Kyung-Jin Lee (Korea Univ., South Korea)
Shunsuke Fukami (Tohoku University, Japan)
Jordan Katine (Western Digital, USA)
Bernard Dieny (SPINTEC, France)
Kevin Garello (SPINTEC, France)

Acknowledgements:
This Forum is the 13th of a series initiated by Samsung
Semiconductor in 2013.
It is supported by Samsung Semiconductor through adonation to the IEEE Magnetics Society.
The whole Society deeply thanks Samsung for this generous sponsorship.

Phyllis Mahoney (Widerkehr and Associates) and Jean Anne Incorvia (University of Texas at Austin) aresincerely acknowledged for their help with the Forum organization.