平成27年度
VLSI Design and Education Center The University of Tokyo 2015

東京大学
大規模集積システム設計教育研究センター

年 報

2015
VLSI Design and Education Center,
The University of Tokyo
Annual Report

VLSI Design and Education Center The University of Tokyo 2015

VDEC年報2015_H1_4E.indd 4-1

2015/07/17 13:47

VLSI Design and Education Center
The University of Tokyo

This is the 2014 Annual Report of VDEC (VLSI Design and Education Center, University of Tokyo).
In 2014 we introduced a high-density assembling system as a tool for enhancing added-value of integrated circuits.
Taking into account rapid increase of VDEC cleanroom users, the system consists of a flip-chip bonding and its
peripheral apparatuses to implement a high-density chip assembly. High-density boards/chip-carriers, to which barechips are attached, can be fabricated using the electron beam lithography that is already introduced in the cleanroom.
Using the new system we are expecting to efficiently integrate bare chips with other devices for demonstrating highly
value-added systems, such like sensor systems, integrated MEMS, Ultra-high frequency systems and so on.
Under the circumstance of hard access to new technologies beyond 40 nm CMOS in Japan, we carried out a test
run for 28 nm FDSOI/CMOS technology of ST Microelectronics two years ago, collaborating with CMP. It was
successfully finished last year, thanks to a lot of cooperation of VDEC major users. We have already made a new menuof the 28 nm FDSOI/CMOS open for all the VDEC users. Because its price per chip area is, however, considerably
high, we received many requests from committee members of the VDEC council for chip fabrication menus withmoderate prices between 40 nm and 90 nm. So, we have been discussing in VDEC about a possibility of new foundries
for these requests, including oversea companies. Fortunately, it was found that the 65 nm CMOS/SOTB, developed by
the national project, LEAP (Low-power Electronics Association and Project), will be available via Renesas Electronics
even after the end of the project. We have already included it in the chip fabrication menu of VDEC from this year.
Though we have to pay attention to the regulation of VDEC academic CAD licenses, the new technology is open
for commercial use and oversea countries, as well. We are expecting that it will be used for seamless research anddevelopment from academia to industry. We are also recognizing importance of introducing commercial CAD licenses
for direct transfer of research results from academia to industry. Though we have been discussing and negotiating on
this matter with persons concerned, it will still take a time before providing them from VDEC. Now, new commercial
services, such like the cloud CAD tools, are about starting, along with the second/third CAD vendor tools, almost
compatible with the mainstream of CAD tools with reasonable prices. It would be important for academia to establish
LSI design environments based on these new comers.
As the annual event of the D2T (Design-to-Test) research division, donated by Advantest Corporation, the 9th
symposium was successfully held on August 26th 2014, inviting distinguished lecturers from oversea and domestic
institutes. We are scheduling the 10th symposium in August 21st this year, too. The main subject of the 10th symposium
will be “Reliability for automotive and other applications.” We would like to express our sincere thanks to invitedlecturers, audiences and Advantest Corporation for the continuous support.
We will continue to do our best efforts for the original mission of VDEC, “promotion of education and research in
LSI design by means of practical chip-design and implementations” , in order to realize research and education forenhancing the value of the semiconductor technology. We thank you for your continuous supports again.
June 2015

VLSI Design and Education Center, University of Tokyo
Director Kunihiro Asada

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VLSI Design and Education Center, The University of Tokyo
Annual Report 2015

C O N T E N T S

Message from Director of VDEC
Chapter 1

Chapter 2

Chapter 3

VDEC2015_E.indd 1

2

Activity Report of VDEC
1.1

Introduction of VDEC activities and activity report of FY2014

1.2

VDEC CAD Tools

2

5

1.3

VLSI Chip Fabrication

1.4

Seminar10

1.5

Facilities

14

1.6

Activity plan for 2015

1.7

Venture companies related to VDEC

I.8

“Nanotechnology Platform”
18
Ultra Small Lithography and NanometricObservation Site

7

16
17

Activity Report of“ADVANTEST D2T Research Division”

19

2.1

Introduction of “ADVANTEST D2T Research Division”

2.2

Report of “9th D2T Symposium”

2.3

Research Activity Reports of “Advantest D2T Research Division”

2.4

Publications

19

20
22

23

Research in VDEC

24

2015/07/17 13:45

Chapter 1 Activity Report of VDEC

1. 1  Introduction of VDEC activities and activity
report of FY2014
VLSI Design and Education Center(VDEC), University

year. We hold the seminar in VDEC and provide distanceof Tokyo was established in May 1996. VDEC has beenlearning through video streaming. We expect spread ofoperating for the following 3 major roles: “spreading

the up-to-date LSI design methodology by using CAD

the latest information on VLSI design and education,”tools.

Chapter 1“providing licenses of CAD tools,” and “suppor ting

1-1

The missions of VDEC are for advancement ofonce a year. This year we shifted these seminars fromresearches and education on LSI design in public andNovember-Januar y time frame to May-July time frame.

private universities and colleges in Japan and send many

We also added “Digital design course” in addition to

distinguished VLSI designers into industry. After 18 years

three courses “Analog design course” and “RF designof VDEC establishment, educations on CAD software,course”，and initiated “MEMS design course”．We invite

LSI design and design flow in universities have been wellexperienced professors among universities as lecturers

established. On the other hand, advancement on nano-for the courses to conduct LSI design education courses

meter CMOS technologies forces design flow and CAD

with practical experience. We also hold “Transistor levelsoftware complicated. We have been continuing CAD tool

design flow in VDEC” and “Digital design flow in VDEC

seminar by the lecturers from EDA vendors for twice a

EDA environment” for designers in universities. We

2

We assume our LSI design flow seminars as educations

on VLSI chip fabrications for academic use.” Theon basic LSI design concepts and practical experience of

VDEC activity report of FY 2014 is described hereafter

LSI design with CAD tool chain. VDEC holds “LSI design

according to Fig. 1. 1.

education seminar”，a.k.a. VDEC Refresh Seminar,

Activity Report of VDEC

Fig. 1. 1

VDEC2015_E.indd 2

VDEC activities

2015/07/17 13:45

started to charge these two LSI design education courses,

process dependent groups through VDEC web pages,

as well as VDEC Refresh Seminars.

and can ask questions and helps on their facing issues. It

In addition to the above seminars, we hold “VDEC

is not a responsibility for the registrant of such mailing-

DesignerʼForum” among young professors and students

lists to give answers to questions, however, in most cases,

annually. This is a workshop that the par ticipants

replies are given by the experienced users of CAD tools

exchange their design examples with not only successand experienced designers within a couple of hours to astories but also their failure stories, in addition tocouple of days. Moreover, emails are accumulated and areinvited talks. We expect students and professors who

open to the VDEC users, as shown in Fig. 1. 2, who havewill start designs to learn kinds of know-hows. We haveregistered VDEC accounts, as the important educational

initiated “IEEE SSCS Japan Chapter VDEC Design

assets. We expect all the VDEC users to make the full use

Award” this year, and final examination and awardingof this mechanism to help solve problems.
We continue chip fabrication ser vices on 0.18mm

Mr. T. Kawamura(Nara Advanced Institute of Science

CMOS by Rohm and 0.8 μm CMOS by On-semi Sanyoand Technology (NAIST)) is awarded as “IEEE SSCS

Semiconductor. And star ted chip fabrication ser vices

Japan Chapter VDEC Design Award” winner, and Mr. C.

on FDSOI CMOS 28 nm by ST Microelectronics inMonteiro(Gifu Univ.), Mr. T. Yamaguchi(NAIST), Mr. H.

cooperation with CMP.
Our donated division “Design To Test(D2T)”，which

awarded as “the best VDEC Design Award”，and Dr. S.

was founded by donation from Advantest in Oct. 2008,

Wang(Kyushu Inst. of Tech.), Mr. F. Mochizuki(Shizuoka

focuses on enrichment of education on LSI testing andU n i v. ) , S . Ya m a s a k i ( H i r o s h i m a U n i v. ) , M s . A .

bridging between design and testing.

Oshima(Kyoto Inst. of Tech.), Mr. S. Kanda(Kyoto Inst.

Fig. 1. 4 shows trends of number of papers throughof Tech), and Mr. S. Uenohara(Kyushu Inst. of Tech) are

VDEC activities. Number of papers is increasing, which

awarded as the “VDEC Design Award.”means researches in the field of VLSI design have been

LSI designers come up against various dif ficulties

encouraged after VDEC establishment.

during actual LSI design scene, even after the basic

Fig. 1. 5 shows number of papers related to CAD usage,

educations through various seminars and the forum. One

chip fabrications and VDEC facility usages. CAD tools areof the biggest problems for beginners is the setup of CAD

widely used to write papers. CAD tools are used not only

softwares. Many of them also get confused by “Esotericchip designs themselves but also used for preparation of

messages” come out from CAD softwares, even after they

chip fabrication and they contribute to verify fundamental

successfully setup CAD tools. In such situations, VDEC

ideas of researches. Advanced CMOS processes aremailing-lists make significant contributions. VDEC users

preferred for publications, and not only papers with 65 nm

can register to VDEC mailing-lists on CAD tools, and

CMOS chips, but also with 45nmCMOS, 32nmCMOS

Fig. 1. 2

VDEC2015_E.indd 3

1-1
3

Activity Report of VDEC

Hayami(NAIST), and Mr. T. Usui(Shizuoka Univ.) are

Chapter 1

have carried out during the “VDEC DesignerʼForum”．

Archives of emails of VDEC mailing-list.

2015/07/17 13:45

and 22nmCMOS are emerging in the world. We would

researches for “More than Moore”．We also encourage

like to prepare chip fabrication services for the advanced

researchers to fully use of VDEC facilities such like LSICMOS processes. In addition, we would like to setup chiptesters, FIB systems and EB writer for the wide spread offabrication services related to CMOS/MEMS to fulfill the

research purposes.

Chapter 1

1-1
4

Activity Report of VDEC

Fig. 1. 3

Trends of number of papers through VDEC activities.

Fig. 1. 4

VDEC2015_E.indd 4

Number of papers related to VDEC facilities.

2015/07/17 13:45

1. 2  VDEC CAD Tools
Since 1996, VDEC has provided CAD software licenses
to the registered researchers in universities and colleges

other public universities, private universities, andcolleges.
When one is going to use VDEC CAD tools and chipin Table 1. 2. 1. The researchers can use those CAD

fabrication service (the details are described in Section

tools when their local machines, whose IP addresses are

1-3), some faculty member of his/her research group inregistered in advance, are authorized by one of VDEC

a university or a collage needs to do user registration.

license server located in the ten VDEC subcenters shown

Fig. 1. 2. 2 shows (a) the number of registrants, (b) thein Fig. 1. 2. 1. For each CAD tool, VDEC provides 10-100

number of distinguished universities/colleges of thefloating licenses. Those CAD tools can be utilized only forregistrants, and (c) the number of registrants who appliedresearch and education activities in national universities,

VDEC CAD tools.

Table 1. 2. 1 VDEC CAD tools
Function

VendorCadence tool set

Verilog-HDL/VHDL entry, Simulation, Logic synthesis,
Test pattern generation, Cell-based (including macros)place, route, and back-annotation, Interactive schematicand layout editor, Analog circuit simulation, Logic verification, Circuit extraction

Cadence Design Systems, Inc.

Synopsys tool set

Verilog-HDL/VHDK simulation, Logic synthesis, Test
pattern generation, Cell-based (including macros) place,route, and back-annotation, Circuit simulation, Device
simulation

Synopsys, Inc.

Mentor tool set

Layout verification, Design rule check

Mentor Graphics Co. Ltd.

Silvaco tool set

Fast circuit simulation

SilvacoADS/Golden Gate

Design and verification of high-frequency circuits

Agilent Technologies

Bach system

BachC-based design, synthesis, and verification

Sharp

LAVIS

Layout visualization platform

TOOL

Laker, Verdi

Layout editor and debugger

Springsoft Inc.

VDEC2015_E.indd 5

1-2
5

Activity Report of VDEC

Name

Chapter 1

in Japan. The CAD tools we provided in 2009 are shown

2015/07/17 13:45

Chapter 1

1-2

Fig. 1. 2. 1 VDEC Subcenters

6

Activity Report of VDEC(a) The number of registrants(c) The number of research group applied CAD tools(b) The number of universities colleges of the registrants(d) The number of applied licenses of all CAD tools

Fig. 1. 2. 2 The numbers of VDEC CAD Applications

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1. 3  VLSI Chip Fabrication
1. 3. 1 Trends of VLSI Chip
Fabrication Services

which means drastic improve of the ef fectivenessresearches and education of LSI design, and we assume
drastic increase of number of students related to LSI chipFig. 1. 3. 1 shows a trend of number of designed chips
for VDEC chip fabrication services, including pilot projectprior to VDEC establishment.
VLSI chip fabrication is limited to 0.5 μm CMOS
provided by NTT Electronics during the pilot project

Chapter 1

in 1994 and 1995. VDEC chip fabrication had started in
1996 with 1.2 μm CMOS provided by Motorola Japan,
which is now On-Semiconductor as well as the 0.5 μm
CMOS. In 1997, VDEC received cooperation from Rohm
and has started 0.6 μm CMOS process. In 1998, VDEC

1-3

started chip fabrication ser vices of 0.35 μm CMOS by

7

Activity Report of VDEC

Hitachi, and in 1999, VDEC started 0.35 μm CMOS by
Rohm. We had a test chip fabrication of 0.13 μm CMOS
by STARC through “IP development project” in 2001. We
added 0.18 μm CMOS by Hitachi into our chip fabrication（a）Trend of number of designs fabricated.

menu in 2001. From 2002, we started VDEC-MOSIS chip
fabrication program initiated by Prof. Iwata of Hiroshima
University. Under this program, VDEC member canaccess to TSMC and IBM processes with lower price. We
also started Bipolar chip fabrication by NEC Compound
Semiconductor Devices. In 2004, we star ted 0.15 μm
SOI-CMOS chip fabrication by Oki Electric as test chip
fabrications. In the same year we started 90 nm CMOS
chip fabrication by ASPLA/STARC. In 2006, we started
0.18 μm CMOS by Rohm and 0.25 μm SiGeBiCMOS
by Hitachi. In 2008, we started 65 nm CMOS process by
eShuttle, after closure of 90 nm CMOS chip fabricationin 2007. In 2010, we star ted 40 nm CMOS process（b）Trend of designed area.

by Renesas Electronics through “Next Generation
Semiconductor Circuits & Architecture” project between
METI and STAR. On the other hand, 1.2 μm CMOS
chip fabrication program came to end by the September
2011. 40 nm CMOS by Renesas Electronics and 65 nm
by eShuttle also come to end by Oct. 2012 and Aug. 2013,
respectively. We started CMOS 0.8 μm in Oct. 2012 by
On-semiconductor-Sanyo as a test chip fabrication andopened it as the regular chip fabrication menu in 2012.
We started FD-SOI 28 nm CMOS by ST-Microelectronics
through CMP, France, as the advanced CMOS process in2013.
Fig. 1. 3. 1(a) shows trends of number of chip designed
for VDEC chip fabrication. For the first 6 years until 2001,
the number of designed chips shows steady increase,

VDEC2015_E.indd 7（c）Trend of designed area normalized by design rule.
Fig. 1. 3. 1 Trend of number of designs and designed chip area.

2015/07/17 13:45

design and education. During few years of stable number
around 400 chip designs per year, we can see transitionof designs toward finer process. In 2007, we saw a large
drop, which was caused by sudden process transition
from 0.35 μm CMOS to 0.18 μm CMOS, and in 2008, we
also saw another drop by process transition from 90 nm
CMOS to 65 nm CMOS.
Fig. 1. 3. 1(b) shows trends of designed chip area,
which shows much clear trends of drop by process
migration. On the other hand, Fig. 1. 3. 1(c) shows
trends of designed chip area normalized by design rule,

Chapter 1

which assume to be strong relation with design efforts.

1-3

effort per chip and per unit area due to process scaling.

8

Coming from the fact that the normalized chip area isstill growing, we assume the major reason for decrease of

Fig. 1. 3. 2

Trend of number of processors and universities
fabricated chip.

number of chips and designed area is increase of design
Fig. 1. 3. 2 shows trends number of professors andActivity Report of VDEC

universities fabricated chip. Number of professors

1. 3. 2 Overview of chip fabricationin 2014

who have contracted NDA for process technologies toTable 1. 3. 1 lists chip fabrication schedule in 2014.

access design rules and design libraries are, 262, and 32,

Please refer to list in Chapter 2 for details of designers

respectively, for 0.18 μm CMOS, and 0.8 um CMOS.

and contents of chip designed.

Table 1. 3. 1 Chip fabrication schedule in 2014
○ 0.8 μm CMOS (On-Semiconductor - Sanyo)
Chip application deadline

Design deadline

Chip delivery

2014 #1

2014/ 7/14

2014/10/ 6

2014/12/18

2014 #2

2014/12/29

2015/ 3/23

2015/6(Schedule)

Chip application deadline

Design deadline

Chip delivery

2013 #5

2013/11/ 4

2014/ 1/27

2014/ 5/14

2014 #1

2014/ 1/27

2014/ 4/21

2014/ 8/ 5

2014 #2

2014/ 4/14

2014/ 7/ 7

2014/10/21

2014 #3

2014/ 6/ 9

2014/ 9/ 1

2014/ 1/28

2014 #4

2014/ 8/25

2014/11/17

2014/ 3/12

2014 #5

2014/11/ 3

2015/ 1/26

2015/5(Schedule)

Chip application deadline

Design deadline

Chip delivery○ 0.18 μm CMOS (Rohm)○ 28 nm CMOS (STMicro/CMP)

2015 Jan.

VDEC2015_E.indd 8

2015/ 1/ 5

2015/07/17 13:45

1. 3. 3 Libraries and design flows

and design flows for digital design and PDKs for analog
design. Table 1. 3. 2 lists libraries available now.

VDEC have been working to prepare design libraries
Table 1. 3. 2 Libraries available for VDEC chip fabrication
Technology

Name

AuthorContents

0.18μm CMOS
(Rohm)

Rohm
library

Rohm Library
Std. Cells, IO cells, RAM(Distributed with CDROM)

Synthesis(Synopsys)
Simulation(VerilogXL)
P&R(LEF/DEF)
Synthesis(Synopsys)

Onodera Lab., Kyoto University

Simulation(VerilogXL)
P&R(Astro)

Todai
Library

VDEC2015_E.indd 9

VDEC

Synthesis(RTL Compiler)
Simulation(VerilogXL)
P&R(Encounter)
PDK(IC6.1)

1-3
9

Activity Report of VDEC

PDK

VDEC
Design flow based on library prepared by
Onodera Lab., Kyoto University

Chapter 1

Kyodai
Library

2015/07/17 13:45

1. 4  Seminar
Seminar is indispensable for the improvement of LSI

teachers gave lecturers on transistor level circuit design

design technology. Some seminar and forums, such ascourse, and digital circuit design course under the VDEC

technical seminar for CAD use, refreshing seminar for

EDA environment. Teachers and students up to 40 people

working people, designerʼs forums for young professors

attended a lecture in each course, and master the use

and students were held in 2011.

of each tool for VLSI design flow that uses the VDEC

【Technological seminar for CAD use】

library. Moreover, another technical seminar for CAD use

In a technological seminar for CAD use, VDEC

Cadence 2 kind and 3 days, Synopsys 3 kinds and 4 days,

Chapter 1

invites lecturer from each tool vender, such as Cadence,

Agilent 1 kind and 1 days (Table 1. 4. 1). The demand

Synopsys and Agilent, to hold the CAD operation course.

for these CAD technological seminars is very large, andMoreover, the course concerning the design flow in

VDEC has maintained the mechanism of a large-scale

the VDEC environment was held by the VDEC staff. A

CAD technological seminar holding corresponding to this

1-4

technological seminar for CAD use for the beginner was

situation. So far, the seminar was held at the University

held in The University of Tokyo VDEC in August andof Tokyo OR other VDEC branch, however, we started

September at the year 2014. This seminar took 5 days forto distribute the lecture using Web streaming, so that

2 kinds of Cadence tools, 5 days for 3 kinds of Synopsys

students around VDEC branch can take the seminar attools, 1 days for 1 kind of Agilent tool. In addition, VDEC

the branch school.

10

for matured teachers and students was held in March by

Activity Report of VDEC

Table 1. 4. 1 CAD technological seminar in summer of the year 20132014/08/04-05

Synopsys IC Compiler Seminar

Univ. of Tokyo9

2014/08/04-06

Synopsys IC Compiler Seminar

Kanazawa Univ.

1

2014/08/04-07

Synopsys IC Compiler Seminar

Nagoya Univ.

2

2014/08/04-08

Synopsys IC Compiler Seminar

Kyoto Univ.

2

2014/08/04-09

Synopsys IC Compiler Seminar

Hiroshima Univ.

1

2014/08/06-07

Cadence OrCAD Seminar

Univ. of Tokyo13

2014/08/06-08

Cadence OrCAD Seminar

Tohoku Univ.

3

2014/08/06-09

Cadence OrCAD Seminar

Nagoya Univ.

1

2014/08/06-10

Cadence OrCAD Seminar

Nagasaki Univ.

5

2014/08/20

Agilent EMPro Seminar

Univ. of Tokyo12

2014/08/21

Agilent EMPro Seminar

Nagoya Univ.

3

2014/08/22

Agilent EMPro Seminar

Kyoto Univ.

2

2014/08/23

Agilent EMPro Seminar

Osaka Univ.

3

2014/08/21

Synopsys HSPICE Seminar

Univ. of Tokyo17

2014/08/22

Synopsys HSPICE Seminar

Tohoku Univ.

2

2014/08/23

Synopsys HSPICE Seminar

Nagoya Univ.

1

2014/08/24

Synopsys HSPICE Seminar

Kyoto Univ.

1

2014/08/25

Synopsys HSPICE Seminar

Osaka Univ.

5

2014/08/26

Synopsys HSPICE Seminar

Nagasaki Univ.

3

2014/09/02-03

Digital Design Flow on VDEC Environment Seminar

Univ. of Tokyo23

2014/09/04-05

Transistor Level Design Flow on VDEC Environment seminar

Univ. of Tokyo

25

VDEC2015_E.indd 10

2015/07/17 13:45

Synopsys Design Compiler+Power Compiler Seminar

Univ. of Tokyo13

2014/09/17-19

Synopsys Design Compiler+Power Compiler Seminar

Kanazawa Univ.

1

2014/09/17-20

Synopsys Design Compiler+Power Compiler Seminar

Kyoto Univ.

1

2014/09/17-21

Synopsys Design Compiler+Power Compiler Seminar

Osaka Univ.

6

2014/09/24-26

Cadence IC61 Virtuoso Layout Seminar

Univ. of Tokyo22

2014/09/24-27

Cadence IC62 Virtuoso Layout Seminar

Kanazawa Univ.

3

2014/09/24-28

Cadence IC63 Virtuoso Layout Seminar

Hiroshima Univ.

1

2015/03/06

Synopsys TCAD Seminar

Univ. of Tokyo10

2015/03/07

Synopsys TCAD Seminar

Tohoku Univ.

7

2015/03/08

Synopsys TCAD Seminar

Kanazawa Univ.

2

2015/03/09

Synopsys TCAD Seminar

Nagoya Univ.

1

2015/03/10

Synopsys TCAD Seminar

Osaka Univ.

4

1-4

2015/03/11

Synopsys TCAD Seminar

Hiroshima Univ.

311

2015/03/10

Agilent ADS Momentum Seminar

Univ. of Tokyo10

2015/03/11

Agilent ADS Momentum Seminar

Tohoku Univ.

4

2015/03/12

Agilent ADS Momentum Seminar

Nagoya Univ.

1

2015/03/11

Synopsys XA+VCS mixed sim Seminar

Univ. of Tokyo7

2015/03/12

Synopsys XA+VCS mixed sim Seminar

Hokkaido Univ.

5

2015/03/13

Synopsys XA+VCS mixed sim Seminar

Tohoku Univ.

5

2015/03/14

Synopsys XA+VCS mixed sim Seminar

Hiroshima Univ.

1

2015/03/18

Synopsys HSPICE Seminar

Univ. of Tokyo17

2015/03/19

Synopsys HSPICE Seminar

Hokkaido Univ.

3

2015/03/20

Synopsys HSPICE Seminar

Tohoku Univ.

5

2015/03/21

Synopsys HSPICE Seminar

Nagoya Univ.

1

2015/03/22

Synopsys HSPICE Seminar

Kyoto Univ.

1

2015/03/23

Synopsys HSPICE Seminar

Osaka Univ.

5

2015/03/24

Synopsys HSPICE Seminar

Hiroshima Univ.

1

2015/03/25

Synopsys HSPICE Seminar

Nagasaki Univ.

2

2015/03/26

Synopsys HSPICE Seminar

Miyazaki Univ.

6

2015/03/12-13

Cadence OrCAD Seminar

Univ. of Tokyo5

2015/03/12-14

Cadence OrCAD Seminar

Hokkaido Univ.

4

2015/03/12-15

Cadence OrCAD Seminar

Tohoku Univ.

3

2015/03/25-27

Cadence EDI Seminar

Univ. of Tokyo6

2015/03/25-28

Cadence EDI Seminar

Hokkaido Univ.

5

2015/03/25-29

Cadence EDI Seminar

Nagoya Univ.

1

2015/03/25-30

Cadence EDI Seminar

Osaka Univ.

7

2015/03/25-31

Cadence EDI Seminar

Hiroshima Univ.

1

Activity Report of VDEC

VDEC2015_E.indd 11

Chapter 1

2014/09/17-18

2015/07/17 13:45

【Refresh Seminar for Working People】

from many societies.
Course A: analog integrated circuit design (5/26-

Chapter 1

Teachers of universities and designers in the first line

5/28), Course D:digital integrated circuit design (6/3-of the enterprise were invited to the lecturer at "VLSI

6/5), Course M1: MEMS design (6/12-6/13), Course

design refresh seminar" was held aiming at the latest,

M2:MEMS fabrication (6/25-6/27), and Course R: RF

advanced knowledge and technical learning concerning

circuit design (7/3-7/4). Teachers from industr y and

VLSI design as a refreshing education for working people

universities involved in the integrated circuit research

involved in the integrated circuit industry (Table 1. 4. 2).

and the education were invited as the lecturer, and theyThough this seminar started chiefly in year 1998 under

introduced a state-of-the-ar t VLSI design technology

the support of Ministry of Education Technical Education

including the practice using a lecture concerning VLSIDivision to give practicing education of the latest VLSI

design and the latest CAD tool. The participants for thedesign technology, it continues under many suppor ts

course A, D, M1, M2, R were 22, 21, 7, 6, 17, respectively.

1-4
12

Activity Report of VDEC
Fig. 1. 4. 1 Refresh Seminar at VDEC seminar room at the University of Tokyo, VDEC.

Table 1. 4. 2 Refresh Seminar
Course A: Analog Circuit Design (3 days)
Analog Circuit Design and simulation
Integrated Circuits Verification (LVS, DRC)
Masahiro Sugimoto (Chuo Univ.), Hidetoshi Onodera(Kyoto Univ.), Koji Kotani (Tohoku Univ.)

Course M1: MEMS Design (2 days)
MEMS Basic 1: Fabrication Process
MEMS Basic 2: Operation Principle
Structual Design
Layout Design
Yoshio Mita (Univ. of Tokyo)

Course M2: MEMS Fabrication (3 days)
CAD Design and Analysis
Lithography, Etching, Release
Vibration measurement and analysis
Yoshio Mita (Univ. of Tokyo)

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Course D: Digital Circuit Design (3days)
Verilog HDL
Logic Synthesis, P&R, Layout Verification
Embede Analog Macros and SRAM
Makoto Ikeda (Univ. of Tokyo)

Course R: CMOS-RF Circuit Design (3days)
Modulation/Demodulation, Cascaded connection
Basic Performace, Tranceiver Architecture
Circuit Element, Design Flow
Hiroyuki Ito (Tokyo Institute of Technology)

the failure case and the solution in which LSI designer
has a hard time, the inside stor y of CAD industr y,
the constr uction method in the design milieu in thelaboratory, and so on. This year, we had the meeting inyoung teachers has been held. The VDEC LSI designer

Noro Hot Spring, in August. No less than 31 participants

forum has aimed to sharing information that cannot bewere flourishing at the gathering.

obtained at a society and a academic society, for example,
Table 1.4.3 Program of Designers Forum in 2011.
8/29 (Fri)Time
10:30-11:00

Reception

11:00-13:00

VDEC Design Award second selection:
Short presentation & Poster session & voting/totaling

13:00-14:00

lunch

14:20-14:30

Opening remark

14:30-15:20

Plenary Talk
Toshio Yoshida (Fujitsu)
SPARC64 XIfx: Fujitsuʼs Next Generation Processor for HPC

1-4
13

Activity Report of VDEC

VDEC LSI designer forum intended for students andChapter 1【Designerʼs forum for youngteachers and students】

break
15:30-18:00

VDEC Design Award presentation by the finalists

18:00-20:00

Design Award final totaling, award ceremony

8/30 (Sat)Time
10:00-12:00

VDEC2015_E.indd 13

Ph.D session

2015/07/17 13:45

1. 5  Facilities
The VDEC has provided the big facilities for

Bonding machine (Finetech Fineplacer Lambda, Fig. 1)

universities in Japan from its establishment (1996). Big

that can align two chips face-to-face under TV-camera

facilities refer to those which are impossible to acquire

obser vation. The precision is XY ± 0.5µm, and θ

and or maintain by an individual research unit. Table=1 mrad, Semi-Auto Wire Bodner (Westbond 4700E)

1. 5. 1 shows the available facilities of VLSI testers andthat can bond gold bump and or bumped wires. Also,

some process machines, which are placed at the tester

Vapor phase HF machine was installed for stable MEMS

room and the super clean room of the Takeda building.

releasing process. From April 2014 to March 2015, theIn 2004, the VLSI tester (T2000) and the EB lithography

EB lithography machine F5112 has been used 2074 times.

Chapter 1

machine (F5112+VD01) were donated to the VDEC by

The increase of number since last year (1,594 times) was

the ADVANTEST. In the year 2012, VDEC joined MEXT

very large. The reason was opening the new apparatus(Ministr y of Education)ʼs Nanotechnology platform to(F7000S-VD02) to public, yielding average exposure

enforce its multi-use capability. (For Nanotechnology

count increase as well (160->173 exposures/month) The

1-5

Platform refer section 1. 8). In the FY 2014, VLSI chipfacilities can be used by user after learning how to use

integration apparatuses were installed in the cleanroom.

the a couple of attended use; use result can directly be

The apparatus include Precision Manual Flip-chip

obtained by attended use.

14

Activity Report of VDEC

Table1. 5. 1

Available facility list

Facility
Logic LSI test
SystemAnalog/RF
measurement
systemNanotechnology
Platform
Apparatuses

VDEC2015_E.indd 14

Equipment name

Description

StatusContact

EB tester:
IDS10000

The chip surface voltage during operation
can be measured with the LST tester.
The digital circuit with 384 pins, 1 GHz canbe tested.

Available

equipment@
vdec.u-tokyo.ac.jp

LSI tester:
ADVANTEST T2000

The digital circuit with 256 pins, 512 MHz
can be tested. Analog test is optional.

Available

equipment@
vdec.u-tokyo.ac.jp

FIB: IDSP2X

Cutting wires of LSIs and depositing Pt wires
are available to repair the LSI design errors.

Available

IDSP2X@
vdec.u-tokyo.ac.jp

Auto prober:PM-90-A

Automated prober for testing LSI wafers,
which can be used with the LSI testers. The
probe card for LSIs with the VDEC standard
pin connections is available.

Available

equipment@
vdec.u-tokyo.ac.jp

Analog/RF measurement system:
HP4156B, HP4284, etc

DC parameter measurement, Capacitancemeasurement, Network analyzer, Spectrum
analyzer, etc.

Available

equipment@
vdec.u-tokyo.ac.jp

Low-noize manual prober:Cascade Microtec

6 inch wafer can be measured with six DC
probles and two RF probes upto 50 GHz.

Low-noize, temperature
controlled semi-autoprober: Süss Microtec

8inch wafer can be measured. The chip temperature range is -50 to 200 ℃ .

Mask lithography,
Direct lithography:
F5112+VD01

Minimum linewidth: 50 nm.
Lithography for 5 inch photomask (thickness: 2.3 mm), 2-8 inch wafers, and chips is
possible.

Available

nanotech@sogo.t.u-tokyo.ac.jp

Rapid Mask and Direct
lithography: F7000SVD02

Minimum linewidth: 1xnm.
Lithography for 5 inch photomask (thickness: 2.3 mm), 2-8 inch wafers, and chips is
possible. Stencil character projection of nonsquare shapes such as circle, triangle is possible.

Available

2015/07/17 13:45

High density plasma etching with Cl2 andBCl3 is possible.

Available

Silicon DRIE MUC-21
ASE-Pegasus

High speed, high aspect ratio etching of silicon is possible

Available

FIB systemFIB:
SII XVision200TB

Repairment of photomask, sample etching,etc. (Through Nanotech. Platform and
LCNet)

Available

Chip Bonding
SystemWedge Bonder:
Westbond 7476D

25µm φ Al or Au wire wedge bonding
machine.

Available

Epoxy Die Bonder
Westbond7200C

Precision Manupilator system. Epoxy and or
Ag paste chip bonding and or glued wiring.

Semi-Auto Bonder
Westbond4700E

18～25µm φ Au Ball bonding or bump creation.

Precision Manual FlipChip Bonder Finetech
Fineplacer Lambda

Face-to-face bonding up to 15 mm squarechips. Alignment is through video camera.
Bonding is by heating chips with TV camera.
(Ultrasonic Unit can additionally be purchased.) XY ± 0.5µm, and θ =1mrad precision.

Chapter 1

Chlorine ICP plasma
etcher CE-S

1-5
15

Activity Report of VDEC

Fig. 1 Precision Manual Flip-Chip Bonder Finetech Fineplacer Lambda

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1. 6  Activity plan for 2015
VDEC will continue activities on chip fabrication

continue analog RF design environment, GoldenGate andser vices, CAD tool support, dispatching design related

ADS by Agilent, C-based design environment, BachC

information and donated division “D2T”，as has been

by Sharp. In addition, we continue trial of several CAD

previous years.

tools, such as layout platform, Lavis by TOOL. Design【Design related information
dispatching/Seminar】

debugging platform from SpringSoft has merged into

We will continue holding the following seminars:

Chapter 1(1) CAD tools seminars which have been continued

Cadence tools and will be continued. Smar tSpice by
Silvaco, will be also continued.

【Chip fabrication services】

s i n c e 1997, (2) “ R e f r e s h s e m i n a r ” s i n c e 1998,

We will continue chip fabrication ser vices for(3)“DesignerʼForum” since 1997. We will also continue

0.18 μm CMOS by Rohm, FD-SOI 28 nm CMOS by ST

seminars for LSI tester usage at VDEC and sub-centers,

Microelectronics through CMP and 0.8 μm CMOS by

1-6

workshops on LSI testing technologies initiated by D2T.

On-semiconductor-Sanyo as the regular services. We will

16

【CAD tool support】

start regular services of SOTB CMOS 65 nm by Renesas

Activity Report of VDEC

Electronics. We will ask packaging for the above chip

We will continue Cadence tools, Synopsys tools and
Mentor tools as the main stream design tools. We will

fabrications to J-Device to meet the diverse needs of theassembly.

Table 1.7.1 Chip fabrication schedule【CMOS 1.2μm 2P2M】 On-Semiconductor (Former Motorola Japan)
Chip application deadline

Design deadline

Chip delivery

2015#1

2015/7/6

2015/9/28

2015/12/28

2015#2

2015/12/29

2016/3/22

2016/6/20

Chip application deadline

Design deadline

Chip delivery

2015 #2

2015/4/13

2015/7/6

2015/10/30

2015 #3

2015/6/1

2015/8/24

2015/12/11

2015 #4

2015/8/24

2015/11/16

2016/3/18

2015 #5

2015/11/2

2016/1/25

2016/5/20

Chip application deadline

Design deadline

Chip delivery

2015 #1

2015/6/1

2015/7/13

2016/1/5

2015 #2

2015/12/1

2016/1/12

2016/7/6【CMOS 0.18μm 1P5M (+MiM)】 Rohm

【FD-SOI CMOS 28nm 1P10M】ST Microelectronics
Based on the chip fabrication schedule through CMP.
【SOTB CMOS 65nm】 Renesas Electronics

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1. 7  Venture companies related to VDEC
Some professors related to VDEC started venture companies. The following is a list of the venture companies related
to VDEC.
[1] AIL Co.,Ltd. (http://www.ailabo.co.jp/)
Related professor : Professor Kazuo Taki, Kobe Univ. (President-Director)[2] Synthesis Corporation (http://www.synthesis.co.jp/)
Related professor : Professor Emeritus Isao Shirakawa, Osaka Univ. (Director)(2) System LSI design, design services(3) Development and sales of IPs(4) Development of EDA tools[3] Nanodesign Corporation (http://www.nanodesign.co.jp/)[4] A-R-Tec Corp. (http://www.a-r-tec.jp/)
Related professor : Professor Emeritus Atsushi Iwata, Hiroshima Univ. (Representative Director)
Description of business : (1) Measurement and analysis of LSI substrate noise(2) Design of analog-RF mixed signal LSIs
(3) Training of analog design on the JOB method

VDEC2015_E.indd 17

1-7
17

Activity Report of VDEC

Related professor :Professor Kazuyuki Nakamura, Kyushu Institute of Technology. (Representative Director)

Chapter 1

Description of business : (1) Hardware/software co-design

2015/07/17 13:45

I. 8  “Nanotechnology Platform”:
Ultra Small Lithography and NanometricObservation Site
VDEC is operating an open-use nanotechnology

per formance is measured by the number of researchplatform “Ultra Small Lithography and Nanometric

reports and machine use. The University of Tokyo site

Obser vation Site” together with the Institute ofhas received 179 (150 for precedent year) researchEngineering Innovation of Graduate School ofreports including 17 (9) from big companies, 10 (3) fromEngineering. The site is supported by Japanese Ministry

Small and Medium-size Enterprises (SMEs), 36 (32) from

Chapter 1of Education (MEXT)ʼs Nanotechnology Platform grant.

other universities, 109 (100) from UTokyo researchers

Any researchers in Japanese Universities, Laboratories,(including external collaboration but excluding VDEC),

and Companies can take full advantage of The University

and 7 (6) from public research institutes. The exposureof Tokyoʼs cutting-edge nanotechnology apparatuses

count was 2074 for 12 months (172.4/month), which is

1-8

and know-hows. The accessible technology includes

the record since beginning of existing statistics (460 for

Lithography and Etching environment, Ultra High-FY 2000). As shown in the Fig. 1, usage is monotonously

Voltage Acceleration (1MV) transmission electron

increasing. “Open ratio”，which is the number of days

microscope (TEM) that is capable of visualizing uptoin which users outside the University of Tokyo came,light materials such as Nitrogen. VDEC takes par t individed by machine open days, was 99%. Due to thethe lithography at Takeda Sentanchi Super Cleanroom.

strong suppor t of nanotech. Platform, even a novice

Through VDECʼs key apparatus F5112+VD01 donateduser can obtain fine lithography result by using thefrom Advantest Corporation as well as F7000S-VD02

apparatuses with the Platform Engineering Staf fs ofpurchased by national budget, VDEC is supporting post-

VDEC.

18

Activity Report of VDEC

VLSI activities such as MEMS. The machine is capableof rapidly writing patterns on arbitrar y-shaped targets

URL:http://nanotechnet.t.u-tokyo.ac.jp/

sizing from 1cm-sqare chip to 8-inch round wafers. The

Fig. 1 Monthly Average Exposure Count of EB Machine (s).

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2. Activity Report of“ADVANTEST D2T Research Division”
2. 1  Introduction of“ADVANTEST D2T Research Division”

2. 1. 1 Aim of the establishment of“ADVANTEST D2T Research
Division”

The first phase and the second phase of D2T activities
had finished in September 2010 and September 2013,
respectively. We are currently in its third phase that

ADVANTEST D2T research division was establishedstar ted in October 2013 thr ough the cour tesy ofin VDEC in October 2007. As the name of the research

ADVANTEST Corporation. We have finished the middle

division indicates, it is financially suppor ted byyear of the third phase with very fruitful achievements in

ADVANTEST Corporation.

research, education, symposium organization, and so on.

The aim of establishment of ADVANTEST D2T

Their details are presented in the following sections inresearch division is to promote the research andthis report.

education environment of VLSI testing in all universities

2. 1. 2 Members of “Advantest D2T
Research Division”

and colleges in Japan. “D2T” means that we consider not
only design but also test. As the results of our activities,
we hope to provide the exper ts of design and test for

Project Lecturer

industry. In addition, we are exchanging researchers with

Assistant Professor Nguyen Ngoc Mai Khanhother universities or research institute in both Japan andResearcher

environment to make collaboration with industry because(Advantest Laboratories Ltd.)
Researcher

testing of VLSI is one of the most practical research topics
in industry. Based on those activities, our final goal is tobecome the center of excellence of VLSI Testing in Japan.

Takahiro Yamaguchi
Masahiro Ishida(Advantest Corporation)

Assistant Clerk

Makiko Okazaki

Chapter 2

overseas. Moreover, D2T research division is in a good

Rimon Ikeno

2-1
19

ADVANTEST D2T Research Division

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2. 2  Report of “9th D2T Symposium”“The 9th D2T Symposium” was held on August 26th,
2014 at Takeda Building.

express our warm gratitude again to all these participantsat the symposium.

With the main theme of “System, Circuit, and Testing

The invited lecturers are distinguished researchers andof Ultra-Low Voltage VLSI”，the symposium had eightengineers in each filed. The audience must have madelectures from wide variety of technical fields like process/use of such great opportunity to exchange their thoughts

device technology, circuit, system, and testing of ultra-with these great lectures at the sessions, the panel, andlow voltage LSI operation. Following these lecture

the reception, we hope.

sessions, we had a panel discussion entitled “FD SOI for

D2T Symposium will be continuously held in the future.

analog-digital compatibility in ultra-low voltage era” andThe date of the next, 10th, symposium is fixed in this year

a reception in the evening. The number of the attendees

in the same season as the 9th symposium. We expect

was more then 180, which made the record through themany attendees there again.

whole D2T Symposium histor y. Here we would like to

Chapter 22-2
20

ADVANTEST D2T Research Division
VDEC2015_E.indd 20

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9th D2T Symposium Program

10:15“Activities of ADVANTEST D2T Research Division, VDEC”
Rimon Ikeno (The University of Tokyo)

10:25

Session 1“Phase Noise and Jitter in Circuits: Origins, and How They Affect Signals”
Asad A. Abidi (University of California, Los Angeles)“Numerical and Theoretical Analysis on Voltage and Time Domain Dynamic Range of Scaled CMOS Circuits”
Toru Nakura (The University of Tokyo)“A Subsampling Stochastic Coarse-Fine ADC with SNR 55.3dB and >5.8TS/s Effective Sample Rate for an on-Chip
Signal Analyzer”
Takahiro J. Yamaguchi (Advantest Laboratories)

12:00

Lunch

13:15

Session 2“Present Status of Characteristics Variability in Advanced MOSFETs”
Toshiro Hiramoto (The University of Tokyo)“Process and Design Differentiations at Ultra-Low-Voltage in UTBB FDSOI 28nm”
Philippe Roche (ST Microelectronics)“Ultralow-Voltage Design and Technology of Silicon-on-Thin-Buried-Oxide (SOTB) CMOS for Highly Energy EfficientElectronics in IoT Era”
Nobuyuki Sugii (Low-power Electronics Association & Project)

15:15

Coffee Break

15:45

Session 3“Cross-Layer Approaches for Variation-aware System Design”
Mehdi B. Tahoori (Karlsruhe Institute of Technology)“30-Gb/s Optical and Electrical Test Solution for High-Volume Testing”
Daisuke Watanabe (Advantest Corporation)

16:50

Break

17:00

Panel Discussion“FD SOI for analog-digital compatibility in ultra-low voltage era”
Moderator: Toshiro Hiramoto (The University of Tokyo)
Panelists: Asad A. Abidi (University of California, Los Angeles),Philippe Roche (ST Microelectronics),
Nobuyuki Sugii (Low-power Electronics Association & Project),Mehdi B. Tahoori (Karlsruhe Institute of Technology)

18:20

Closing Remarks

18:30

Reception

VDEC2015_E.indd 212-2
21

ADVANTEST D2T Research Division

Opening Remarks
Kunihiro Asada (Director, VLSI Design and Education Center, The University of Tokyo)
Yoshiaki Yoshida (Director, Advantest Corporation)

Chapter 2

10:00

2015/07/17 13:45

2. 3  Research Activity Reports of“Advantest D2T Research Division”
eling, we have produced an algorithm for calculating
On-chip Digitizer/On-chip Spectrum Analyzer

a simple circuit model of the on-chip power deliver y

Takahiro Yamaguchi, Nguyen Ngoc Mai Khanh,

network based on power integrity measurements, andRimon Ikeno, Satoshi Komatsu, Kunihiro Asadaconfirmed its operation by using computer simulations.

A new transition-edge search circuit is introduced

Furthermore, in order to demonstrate the feasibility ofwhich utilizes a stochastic comparator group. By

the proposed method, we have conducted experiments

incorporating stochastic proper ties into the circuit,of comparison between an actual power delivery net-

this design accelerates the accumulation of data andwork circuit extracted from laid out CMOS circuit and aenhances test quality.

simpler circuit model derived from the CMOS circuit.

We developed a test chip based on a differential-signal comparator which improves symmetry of the offset
proper ty. We expect more precise evaluation of theHigh-throughput and high-accuracy electron-beamstochastic properties with the chip. Since the chip con-direct writing (EBDW) strategy for wide range oftains all required components for our sub-ranging ADC

EBDW applications

architecture, we plan system-level demonstration of theRimon Ikeno, Satoshi Maruyama, Yoshio Mita,architecture using this test chip.

Makoto Ikeda, Kunihiro Asada
Maskless lithography by Electron-Beam Direct
Writing (EBDW) lithography is expected as a low-cost

Chapter 2

2-3
22Power Integrity Evaluation Method

and short turn-around time (TAT) lithography technol-

Masahiro Ishida, Akira Matsukawa, Rimon Ikeno,

ogy, but it also has some drawbacks like low process

Toru Nakura, Kunihiro Asada

throughput and low accuracy against the intended

ADVANTEST D2T Research Division

While a required power supply voltage has becomelayout shapes. We are pursuing high-speed and high-ac-

lower due to the advanced miniaturization of the semi-

curacy EBDW strategy utilizing Character Projection

conductor process, the power supply current consumed(CP) method to overcome these concerns and to boost

by a semiconductor device has increased because of

EBDW use in arbitrary fields like MEMS, photonics,

the huge number of transistors integrated on a sin-and so on.

gle chip. It may increase the power supply noise, andThis year, we proposed a layout data conversion

power integrity issues of the device under test in bothmethodology that enables high-accuracy CP exposure

an ATE and a practical operating environments.

of arcs and oblique edges, where the conventional

In this research project, we propose two methods

Variable Shaped Beam (VSB) exposure might givefor evaluating power integrity at on-chip power supply

poor accuracy or considerable roughness in the resul-

nodes in semiconductor devices: a power integrity test-

tant structures. We demonstrated it with the practicaling method and a power deliver y network modelingdevice structures like cur ved light wave guides, andmethod.

confirmed its effectiveness in reducing EB shot count.

This year, we have constr ucted an experimental

We are processing test fabrication of the device

setup for evaluating a TEG chip which is fabricatedstructures to evaluate both device shapes a per for-to demonstrate the concept of the proposed powermance in cooperation with the other research groups

integrity testing method for detecting power integrity

inside/outside the university.

faults in the DUT. For the power delivery network mod-VDEC2015_E.indd 22

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2. 4.  Publications
Journals[1]

Satoshi Komatsu, Takahiro J. Yamaguchi, Mohamed

International Conferences/
Symposiums/Workshops

Abbas, Nguyen Ngoc Mai Khanh, James S. Tandon,[1]

Komatsu, Kunihiro Asada, “A subsampling stochastic

Using a Group of Unbalanced CMOS Arbiters,” IEICE

coarse-fine ADC with SNR 55.3 dB and >5.8 TS/s effec-

TRANSACTIONS on Fundamentals of Electronics,

tive sample rate for an on-chip signal analyzer,”2014

Communications and Computer Sciences Vol.E97-A

IEEE International Symposium on Circuits and Systems

No.3 pp. 777-780, March 2014.
[2]

James S. Tandon, Takahiro J. Yamaguchi, Satoshi

Kunihiro Asada, “A Flash TDC with 2.6-4.2 ps Resolution

Rimon Ikeno, Takashi Mar uyama, Satoshi Komatsu,(ISCAS), pp. 93-96, June 2014.
[2]

Masahiro Ishida, Takashi Kusaka, Tor u Nakura,

Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada, “ASatoshi Komatsu, and Kunihiro Asada, “Statistical

Structured Routing Architecture for Practical Application

Silicon Results of Dynamic Power Integrity Control ofof Character Projection Method in Electron-Beam

ATE for Eliminating Overkills and Underkills,” IEEE

Direct Writing,” IEICE Transactions on Fundamentals ofElectronics, Communications and Computer Sciences,Vol. E97-A, No. 8, pp. 1688-1698, August 2014.

International Test Conference, pp. 1-10, October 2014.
[3]

Takahiro J. Yamaguchi, James S. Tandon, Satoshi
K om a t s u , K u n i h i r o A s a d a , “ A N ove l Cir cuit f o r
Transition-Edge Detection: Using a Stochastic
Comparator Group to Test T ransition-Edge,”2014
IEEE 23rd Asian Test Symposium (ATS), pp. 168-173,
November 2014.

Chapter 2

2-4
23

ADVANTEST D2T Research Division

VDEC2015_E.indd 23

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Chapter 3 Research in VDEC
Asada, Nakura and Iizuka
Laborator y(http://www.mos.t.u-tokyo.ac.jp)

accurate transient simulation method of NBTI degradation based on Reaction-Diffusion model by calculatinghydrogen distribution at gate oxide in each transistor
according to the gate input level obtained by logic simulations, and an acceleration scheme of NBTI simula-

Supply Fluctuation Monitoring, Analysis andtion based on the frequency dependence of NBTI deg-

Reduction Method

radation. In this method, hydrogen distribution enables

Kunihiro Asada, Toru Nakura, Masahiro Kano andsimulation from continuance of a place at which input

Satoshi Matsukawa

parameter is changed.

In recent years when nm process and GHz operation

And, in an analog to digital converter, comparators

are normal, it becomes a problem that power supply

are used to decide whether the analog input is greater

noises, such as di/dt noise and resonant power supply

than or less than the reference voltage. But in an actual

noise, are caused by parasitic inductances in package

comparator circuit, the reference voltage fluctuates andbonding and power supply networks.

thus has a range of uncertainty. By using a set of sto-

We aimed at the mitigation of area penalty with thechastic comparators, analog input within this uncertain-

passive decap widely used to reduce supply noise,ty range can be converted to digital signal. Therefore,

so we considered active charge injection with capac-

the relations between the parameters of a set of sto-itor. We have developed the environment to optimize

chastic comparators have been derived analytically.

injection current to minimize the quantity of injection

It is showed that effective resolution is inversely pro-charge under the constraint that power supply voltage

portional to the Probability Density Function (PDF) of

fluctuation within a certain level is allowed. As a result,

the reference voltage fluctuation and the total number

the area penalty of optimized active charge injectionof comparators. Then, this configuration is used withbecame about 40 smaller than that of passive decap.

traditional comparators to form a sub-ranging ADC.

Also, we have proposed the method for impedance
estimation of on-chip power supply networks. In thisThe optimal point of operation of this circuit is found bymodeling the PDF as a Gaussian Distribution.

Chapter 3

method, by measuring current flowing in each power
supply pin when operating each current load which isplaced on the chip in advance, the simple circuit modelis created which is composed of resistance, capaci-

Sub-MMW Pulse Generation using CMOS
Kunihiro Asada, Toru Nakura, Parit Kanjanavirokju

3-1tance, and inductance. Determining the parameters of

The target of this research is to implement sub-mil-the model by least squares method to minimizing thelimeter wave pulse generator for short-range imaging

24

difference between the response of the chip and it ofand radar application. Recent literature focus on gen-

Research in VDEC

the model, we can estimate the distribution of imped-

erating continuous wave oscillator, normally based onance. Moreover, we confirmed that the voltage fluctua-

push-push technique. As opposed to those continuous

tion on the

wave generator, we have proposed a direct sub-millime-

power supply network can be estimated by simulating the model.

ter wave pulse burst generator circuit based on transmission line to realize a wide-band pulse with frequency
even higher than Fmax. We have shown that energy
conversion efficiency can be increased by our proposed

Reliability Improvement of LSIs with the fine pitch

technique. The circuit consist of on-chip trigger and off-

process

chip passive transmission line resonator. A test chip has

Kunihiro Asada, Toru Nakura, Kazuhiro Mori,been verified using standard FR-4 board. The generat-

Maruf Hossain

ed pulses by the prototype circuit still has low output

NBTI degradation is one of the important problems

power and power conversion efficiency. We are workingof reliability in nano-scale transistors. We propose an

towards higher frequency by using better board and

VDEC2015_E.indd 24

2015/07/17 13:45

flip-chip technique.

strated that the proposed PWPLL was adaptable to the
PVT variations. We also designed a prototype chip of
the PWPLL in 0.18 um CMOS process.

Surface magnetic field modeling for LSI security
Kunihiro Asada, Toru Nakura, Yuki Oda

Finally, we worked on an improvement of the PulseShrinking (PS) TDC. PSTDC has some advantages ofIn recent years, side channel attack has been devel-small area and high resolution. However it has relative-

oped to expose the secret data in encr yption LSI.

ly high nonlinearity. The main cause of the nonlinearity

Magnetic field from LSI is used to anomaly detection.

is dif ference between the rise and fall propagation

This method models the magnetic field using the wiredelay of the buffer which shrinks the input pulse. We

layout patterns and the current values estimated byproposed an architecture that gives offset width of 1ns

SPICE simulation. However, magnetic field is influ-

to the input pulse and completes the time-to-digital con-enced not only by the current in wire but also by theversion when the pulse width gets smaller than 1ns.

current in base. In this research, we estimated theeffect of base current by using electromagnetic field
simulation. This simulation showed in which condition

Radiation Detector Utilizing Semiconductor

the effect of base current cannot be ignored.

Photodiode Based on Standard CMOS Technology
Kunihiro Asada, Toru Nakura, Zhu Hongbo, Yang Xiao,
Kai XuTime-Domain Circuit Design

Scintillation detectors and semiconductor detectors

Kunihiro Asada, Toru Nakura, Toshiyuki Kikkawa,

have received wide spread attention since they can

Tomohiko Yano, Takehisa Koga, Takashi Toi

specify the nuclide of radiation and estimate the arriv-

In our research, we employed time domain tech-

al angle. Former research proposed a detector usingniques on some conventional circuits and improved

the cube scintillator, SPAD (Single Photon Avalanche

their performances.

Diode) array image sensors, multi-coated materials,

First of all, we proposed a fully differential time-mode

and pinholes and verified the technique to detect thesignal integrator. Having only one buffer-ring to hold alocus of the lighting electron by this detector. Howevertime-mode signal, the proposed integrator has smaller

the detect and estimate costs plenty of time. Thissystematic input-referred time offset error comparedresearch proposed a technique to detect the location

with previous works.

of the electron emitting light in high speed utilizing
the periodicity of the arrangement of the pinholes and
SPADS. The result of the simulation verified that by

We proposed an on-chip measurement method ofusing this technique the location of the electron emit-

PLL transfer function. In our proposed scheme, weting light in a scintillator could be detected with a spa-

modulated the phase of the PLL input in triangulartial resolution of 20 um within 20-40 seconds. About theform by Digital-to-Time Conver ter (DTC) and read

structures of SPADs we have tested, the p-well/deep-out the response on the PLL feedback signal by Time-n-well with poly gate SPAD shows the lowest DCR. A

25

to-Digital Conver ter (TDC). By combination of thesummation circuit to count the number of breakdown

DTC and TDC, we can derive the transfer function of

pixels in SPAD array, and a circuit that only output thethe PLL both in the amplitude domain and the phaseaddress of breakdown pixels had been fabricated. And

domain. Since the DTC and TDC can be controlled andthe functions of these circuits were experiment demon-obser ved by digital signal, the measurement can be

strated.

Research in VDEC

Chapter 3

We also worked on the research of Phase Locked
Loop (PLL).

conducted only by slow digital signals.
We also improved a robustness of Pulse Width

3-1

Controlled PLL (PWPLL) using Soft-Thermometer
Code. Conventional PWPLL is not adaptable to process,voltage, and temperature (PVT) variations. Therefore
we proposed a PWPLL with frequency calibration function which has a length-variable ring oscillator. Bothopen-loop and closed-loop transient simulations demon-

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Fujita Laborator y(http://www.cad.t.u-tokyo.ac.jp/)such as 3n - 1 faults. We need “implicit” representationof faults in order to deal with such huge numbers offaults or fault combinations. We present SAT based formulations for ATPG of circuits having very large num-Partial synthesis and Engineering Change Orderbers of faults by implicitly eliminating detected faults.

(ECO)

We solve a set of SAT problems whose constraints

Masahiro FUJITA, Amir Masoud GHAREHBAGHI,

increase pure incrementally (here “pure” means never

Satoshi JO, Kentaro IWATA

deleting constraints), and so the entire solving process

Engineering Change Order (ECO) may happen incan be very efficient, as all learnings obtained so far are

a design due to a bug fix or a change in the original

valid in the following SAT problems. Experiments are

specification. ECO is expected to be a small change.

performed on combinational parts of ISCAS89 circuits

Therefore, we want to reuse the previous circuit topolo-

in their AIG (AND-Inverter Graph) representations. We

gy and the layout as much as possible to keep the previ-

have successfully generated the complete set of test

ous timing optimizations of the design as much as pos-

vectors assuming that faults happen only at outputs ofsible. Hence, reducing the overall time of applying thegates. Our ATPG techniques can also start with a givenchange. In this work, we propose an ECO method thatset of test vectors. If we start the ATPG processes withkeeps the previous circuit topology of an old circuit anda set of test vectors for single stuck-at faults, we cantries to accommodate the new circuit functionality byobtain the set of additional test vectors required forchanging minimum number of gates. We have defined

multiple stuck-at faults. Results are a little bit surpris-

the gate change model using a number of parametering in the sense that we need very few additional test

variables. By changing the parameters, a gate type canvectors for multiple faults, although the numbers of

be converted to another gate type. Experimental results

fault combinations are exponentially larger. As far asshows that selecting more gates as candidates to be

we know, for the first time, complete test vectors for allchanges results in better ECO success rate. Moreover,stuck-at faults for ISCAS89 circuits where faults happen

more candidate gates results in longer ECO runtime.

only at outputs of gates in AIG representations of thecircuits have been obtained.

Automatic Test Pattern Generation (ATPG) for
Multiple and Various Faults
Naoki TAGUCHI, Satoshi JO

Architectures
Masahiro FUJITA, Amir Masoud GHAREHBAGHI

Due to the continuous shrinking of semiconductor

Processor architectures are becoming more com-technology, there are more and more subtle errors orplicated by adopting various functionalities for higher

3-1

faults widely distributed in manufactured chips, andperformance and more reliability, such as pipelining,

traditional “single” stuck-at fault model may become

speculative execution, and error recovery. To ensure

26

inappropriate. It is definitely better if all combinations

the correctness of complicated processor architectures,

Research in VDEC

Chapter 3

Masahiro FUJITA, Amir Masoud GHAREHBAGHI,

Verification and Debugging of Processorof multiple faults can be completely tested. In this work,

verification and debugging of processor architectures

we present ATPG (Automatic Test Pattern Generation)

are a key issue. In this work, we present a method fortechniques targeting all multiple stuck-at faults, i.e. allautomatic rectification of design bugs in processors.

combinations of stuck-at faults. That is, given “n” pos-Given a golden sequential instr uction-set architec-

sibly faulty locations in a circuit, the target set of faults

ture model of a processor and its erroneous detailed

consists of 3n - 1 fault combinations, as each possibly

cycle-accurate model at the micro-architecture level,

faulty location is under stuck-at 1, stuck-at 0, or nor-we perform symbolic simulation and property check-mal/non-faulty. Traditional ATPG flows use fault sim-

ing combined with concrete simulation iteratively toulators to eliminate all detectable faults by the current

detect the buggy location and its corresponding fix. We

set of test vectors. The problem, however, fault simula-

have used the truth-table model of the function that is

tors represent fault lists explicitly in the sense that all

required for correction, which is a very general model.

possible faults are enumerated in the fault lists. This

Moreover, we do not represent the truth-table explicitly

prevents us from dealing with ultra large fault lists,in the design. We use, instead, only the required mint-

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erms, which are obtained from the output of our back-and are firstly detected by running a chip after fabrica-

end formal engine. This way, we avoid adding any newtion. In addition, a risk of electrical errors is increasing

variable for representing the truth-table. Therefore, ouras fabrication processes shrink. In this work, we havecorrection model is scalable to the number of inputs offocused on post-silicon debugging techniques based on

the truth-table that could grow exponentially. We havetrace buffers. The main problem is that only a limited

shown the effectiveness of our method on a complex

number of signals can be traced, due to the area over-

out-of-order superscalar processor supporting atomic

head that is introduced by trace buffers. Therefore,

execution of instructions. Our method reduces theit is important to select the signals which can restore

model size for correction by 6.0x and total correction

most of the other ones. There exist researches that try

time by 12.6x, on average, compared to our previous

to heuristically select a set of state variables (flip-flops)

work.

which maximizes the restorability. Those existing
works are not so robust and the cost functions used
for selections do not work well in some cases. We have

Acceleration of Calculation with FPGA
Masahiro FUJITA, Taro KAWAO

introduced a method that tries to improve the initial
selection by repeatedly swapping the flip-flops to be

Dedicated hardware is generally faster and more

traced. Moreover, we have a hardware based imple-

energy-ef ficient than a general hardware. A circuit

mentation of the method. As the hardware-based swap-

optimized for specific calculation can be obtained with-ping is faster than software by 4-5 orders of magnitude,

out chip fabrication using a Field Programmable Gate

we can swap much more times and can get consistentArray (FPGA), which is a programmable circuit. In thisresults even for large circuits. Results shows signal res-work, we have considered acceleration of simulation of

toration improvement up to 30% for ISCAS89 circuits.

neural network and analysis of electromagnetic field.
Neural network is a mathematical model of themechanism of a brain. We implemented a highly

Efficient Topological Matching Among Multiple

pipelined circuit on a FPGA to simulate the network

Circuits

composed of 256 spiking neurons and we could accel-

Masahiro FUJITA, Amir Masoud GHAREHBAGHI,

erate the simulation by 320x compared to real time

Hossein IZADI RAD
Recognizing similarities and dif ferences amongis designed to be scalable to the number of neurons.

multiple circuits is very useful for managing and main-

In the future work, we will use multi-FPGA network totaining IP libraries as well as merging circuits, fraud

simulate tens of thousands of neurons.

detection, reverse engineering, and redundancy check-Continuous miniaturization and per for manceing. In this work, we address the problem of finding theimprovement of electronic equipment causes moremaximum common subcircuit among two or more logic

serious electromagnetic interference problems thancircuits. Given the gate-level netlists of the circuits, first

before. Insufficient performance of current simula-

we represent the circuits as graphs. Then, we tr y totors lead to depending on real testing equipment withfind the largest common subgraph, following the com-27

higher cost. To tackle this problem, we are working

mon approaches that are used for identifying matchedon a fast simulator using FPGA that runs several times

graphs. In the first step, we build a conflict graph fromfaster than a sophisticated multi-core software simula-

the circuit graphs. In the next step, we try to find thetor.

largest common subgraph by finding independent sets

Research in VDEC

Chapter 3

calculation on a general purpose processor. This circuitof the conflict graph, using our proposed near-linear
approximation algorithm. Finally, we tr y to increase
Post Silicon Verification and Debugging

the size of the largest common subgraph by consider-

Masahiro FUJITA, Amir Masoud GHAREHBAGHI,

ing neighbors of the circuit graph nodes, step-by-step

Shridhar CHOUDHARY

in a controlled manner. We have performed extensive

Due to increase of the size of VLSI, it has become

experiments on ISCAS85 circuits as well as a number ofver y hard to detect all design bugs in design phases

IPs from OpenCores. Comparing our results to the opti-

before fabrication, which increases the number of bugs

mum solution that is obtained by an exact algorithm,

that escape verification processes before fabrication

the average size of the identified common subcircuit is

VDEC2015_E.indd 27

3-1

2015/07/17 13:45

around 10% smaller, but the average processing speed

Takayasu Sakurai

is two to three orders of magnitude faster. For example,

Large area electronics is a new frontier in electron-

our proposed algorithm needs less than 20 minutes for

ics where intelligent electronic devices are distributed

a circuit with 100,000 gates. Moreover, the size of theon a flexible surface, 10 cm to 10 m on a side, for thecommon subcircuit that is identified by our method ishuman interface and the comfortable daily life. Flexible

on average 60% larger than the one that is identified byand low-cost organic FETs (OFETs) are suitable fora state-of-the-art graph manipulation tool-set.

large-area electronics and have great potential as a supplement of solid and expensive silicon MOSFETs for
VLSIʼs. We have proposed and demonstrated several

Interrupt Analysis for Realtime Software based onlarge area and flexible applications including a surface

HW/SW Co-Testing using Concolic Execution

electromyogram measurement sheet for prosthetic

Masahiro FUJITA, Yusuke KIMURAAs the software of embedded systems become more

hand control, a flexible wet sensor sheet for biomedical
applications, and a fever alarm armband.

complex, its verification becomes harder. As a result,
we need more sophisticated and more ef ficient verification methods. Interrupt is one of characteristic

Ikeda Laborator yfunctions of real time embedded systems. In this work,(http://www.mos.t.u-tokyo.ac.jp)

we have focused on verification of interruptions in

Current Research Projects

an embedded software. We have proposed a comprehensive analysis method using Concolic Execution.
In order to reduce the huge number of required test

Jacob Shearer

patterns, we extract the restrictions from the Simulink

3D-range finding based on light-section methodmodel of the target embedded system, and apply themby Smart Image Sensors

during the verification.

M. Ikeda, H. Yabe, D. Uehara, J. Shearer
Two chips for 3-D measurement based on light section, where we can measure the shape of the 3-D object

Takamiya Laborator y(http://icdesign.iis.u-tokyo.ac.jp/)

using sheet light. The first chip is a dual-core image
sensor for high-speed texture mapping. The two pixel
arrays on the chip can operate in either 2-D or 3-D
1. Under background light, obtain part of the object

Designwhich is not illuminated by the sheet light, 2. In dark

Makoto Takamiya, Hiroshi Fuketa, andcondition, obtain the image by lowering sensitivity. The

3-1

Takayasu Sakurai

second chip proposes an image sensor chip which can

Reducing the power consumption of every electronic

detect sheet light on the pixel array. Each column of28

device is required to mitigate the global warming. To

the pixel array of our proposed sensor has two mini-

Research in VDEC

Chapter 3

mode. In 2-D mode we are using two exposure modes:
Energy Efficient Extremely Low Voltage VLSI Circuit

meet the requirement, VLSI circuit design techniques

mum voltage circuits, which can be used to detect theincluding logic circuits, memor y circuits, analog cir-line position without reading out all the pixel intensity

cuits, power management circuits, and wireless trans-values by performing binary section and linear search

ceiver circuits operating with the 0.5-V power supply

on the array. Our proposed method can realize a high-voltage are developed with 65/45 nm CMOS process to

speed and highly effective 3-D acquisition.

reduce the power consumption to 1/10 of the conventional VLSIʼs.
3D-range finding by Smart Image Sensors
M. Ikeda, T. Matsushima
Large Area and Flexible Electronics with Organic
Transistors
Makoto Takamiya, Hiroshi Fuketa, Takao Someya, andTime-of-Flight (ToF) method and light-section method are representative of 3-D imaging methods. In ToF
method, infra-red light is projected to the object andwe obtain the delay time between projected light and

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reflected light by the sensor. 3-D information of themultiplication method is used for RSA. A RSA circuit

object is obtained by this delay time. In light-section

has a Montgomery multiplier and there are 3 types ofmethod, sheet light is projected to the object and we

Montgomer y multiplication algorithm. Montgomer yscan the sheet light on the surface of the object. We

multiplier using different algorithm has different arith-acquire 3-D information by triangulation. We study the

metic core. Furthermore, there are 9 types of arithme-

sensor which can be applied to both ToF and light-sec-tic core, with different port width in each algorithm

tion method. The pixel of our sensor consists of a cou-so that RSA circuit can be designed in 27 dif ferent

ple of lock-in pixels. It enables improving the efficiency

ways. ECC is the cr yptography using elliptic cur veof speed and area in ToF method. Our sensor also real-

over finite field. Elliptic cur ve digital signature algo-izes fast and accurate position detection of sheet lightrithm (ECDSA), one of the ECC, is researched in ourin light-section method by combining single-slope ADC

laboratory. In ECDSA, private key is used to generate

and priority encoder. We evaluated a trial chip.

signature and public key is used to authenticate. Scalarpoint multiplication is performed in those processes.
There are a lot of methods to perform scalar point multiplication. First, we have to decide which kind of field

Application of electrostatic MEMS scanner integra-

is used. There are two kinds of field, binary field andtion with image sensor

prime field. We use prime filed because of robustness.

M.Ikeda, S.Maruyama

Second, we have to decide which coordinates are used.

We have studied co-integration of MEMS (Micro-

In some projective coordinates, modular inversion isElectro-Mechanical Systems) and CMOS image sen-

not needed so throughput is improved. Finally, sched-sors. MEMS micro-mirrors have features that areuling is considered and implemented by using self-syn-smaller than galvanometer mir rors, lower driving

chronous circuit.

voltage, and co-integrate with LSIs by micro-fabrication process. PWM (pulse width modulation) drivingof MEMS enables to simplify ADC and DAC for controlling MEMS devices. The target of this study is to

Design flow of Self-Synchronous Systems
M. Ikeda, A.Ito
We have studied design flow of the self-synchro-ror position detection and mirror position calibrationnous system with gate-level pipelining, to realize

circuits to realize high-precision, high-speed and low

automatic design like synchronous systems. Starting

power scanner.

with VerilogHDL, obtain netlist with 2-inputs gates bySynopsys DesignCompiler, and translate it into 3 to 4
input gates by ABC developed by UC Berekeley, andCryptographic processor by Self-Synchronous

inser t buf fers again by ABC to equalize number ofSystems

gate stages. We have also studied loop conditions for

M. Ikeda, M. Tamura, T.Ikeda

throughput optimization.

3-1
29

Our research theme is implementation of cr ypMany calculations are needed in encr yption and

SEU resistivity of Self-Synchronous System based

decr yption process and in some cases high through-on Dynamic Circuits

put is required. So we utilize high-speed performance

M. Ikeda, D. Saiof self-synchronous circuit. T wo algorithms are

SEU (Single Event Upset) by radiation becomes crit-researched in our laboratory. One is RSA and the otherical for the advanced CMOS circuits. We have studied

is elliptic curve cryptography (ECC). RSA is the cryp-

SEU tolerance of the self-synchronous system with

tography using exponential and modular calculation.

dynamic circuits. We carried out spice simulation inject-

In this reserch, self-synchronous RSA circuit using

ing charges mimicking neutron injection, and classified

Montgomery power ladder algorithms is desined in dif-

SEU types for the dynamic circuits. We also realized

ferent way, and comparing each of them in the point ofsimple estimation method of collision cross-section ofarea and speed reveals the best implementation of RSA.

neutron, from netlist. SEU tolerance for the dynam-

To execute faster modular calculation, Montgomer y

ic circuits can be estimated by temporal probability

Research in VDEC

tographic algorithm using self-synchronous circuit.

VDEC2015_E.indd 29

Chapter 3

include capacitance sensor for micro-actuator for mir-

2015/07/17 13:45

obtained by simulation, and special area estimation.
LSI-MEMS integrated device by submicron-wide
opening deep reactive ion etching technology

Mita Laborator y(http://www.if.t.u-tokyo.ac.jp)

Y. Mita, T. Sawamura, I. Mori, A. Hirakawa, K. Yasuda,
M. Kubota
Narrow and deep str uctures such as microholes
and trenches are playing key roles in modern electro

Study on LSI-MEMS integrated pond-skating robot

and mechanical systems. In standard micro fabricationfor energy-autonomous distributed microsystems

technology, patterns are composed of rectangles and

Y. Mita, I. Mori, Y. Okamoto, Y. Li,

vertically transferred to the depth direction, yielding

A.J. Walton (Univ. of Edinburgh)

long-cubic structures. However, just by thinking of

As one example of integrated MEMS that is expected

lens shape, one can realize that cubic shape is not nec-

to open new research and industrial application fields,

essarily the optimum shape for all kinds of applications.

the authors are trying to show a top-down application

Hence it can be said that the ideal micro fabricationof energy-autonomous distributed microrobots. The

technology must be capable of realizing surfaces hav-

research belongs to the “top-down” research category

ing arbitral cur vatures that are top-down requested

and through the research the team looks for ward toby applications. The team aims at acquiring compre-

provide the “Engineered Nature”; the team does nothensive study on such “arbitral cur vature providing

intend to just copy how nature works in implementation

micro fabrication technologies” from three aspects: (1)level, but to realize with cutting-edge technologies what

Top-down concrete applications, (2) Enabling micro

nature is aiming at in highly-functional level. Recent

fabrication methods by cutting-edge technologies andtop-down activities include autonomous distributed

ideas, and (3) non-destructive profiling method of such

mobile robot: “Pond Skater”，which to date had notsurfaces. Top-down applications published in FY 2013

been realized by any other microsystems group. The

include (1-5) thermal energy harvester that takes fullavailability of a leading low voltage technology at theadvantage of profile control by DRIE tuning, as well as

Scottish Microelectronic Centre (SMC) the University(2-4) Experimental analyses of trench vertical profile

of Edinburgh that could electrically change surfaces

with process parameters were performed.

from hydrophobic to hydrophilic proved to be crucial toachieving this goal as was the previous involvement of

Chapter 3

SMC staff in wireless technology. The major challenge

Smart Blocks II project–Wireless operation UV pat-is propulsion, and it is clear that directly mimicking

terned polyimide microactuator

the pond skating insectʼs propulsion mechanism would

Y. Mita, N. Sakamoto, Y. Okamoto, K. Kawahara,

be problematic. The idea that was developed was to

J. Malapert (FEMTO-ST), M. Ataka, H. Fujita

3-1

propel the device using Electro-Wetting Of Dielectric

In a framework of French national research project(EWOD) to move air bubbles, which had the significant(ANR) “Smart BlocksII”，Dr. Julien Malapert stayed30

advantage that there we no moving mechanical parts,

in Mita Lab., to develop a brand-new thermal microac-

Research in VDEC

which simplified the construction and helped to mini-

tuator array and control circuit. Following a successful

mize the weight which was important if the pondskat-

demonstration of the microactuator array with maxi-

ing device was to float using surface tension. Based on

mum displacement amplitude of 15µm and cut-off fre-

the worldʼs first wireless pond-skating propulsion, thequency of 10 Hz, the team integrated the actuator arrayteam is developing VLSI control circuit and integration

into a 2.5 cm-cubic “smart block” demonstration device.

technology for continuous skating. In FY2014, a first

The block was with ZigBee-communicating microcon-

experiments of remote EWOD driving was successfully

troller and lithium polymer battery. The team was suc-performed by integrating CMOS-post-processed one-

cessful in tele-operating the microacauator array. The

chip HV generating photovoltaic cells and Ta2O5 EWOD

device was appreciated in the MICRONORA exposition

device made at UTokyo Takeda Cleanroom.

held in Besançon in September.

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circuits. Currently research is in progress for robust
An LSI probing system with CMOS-MEMS
Y. Mita, R. Setoguchi and M. Kubota

image recognition and classification processing including robust feature extraction. The sate-of-the-art silicon

The team is developing a “MEMS” probe card fortechnology has been utilized to implement such asso-

electron device testing such as VLSI. The originality is

ciative processors in both analog and digital CMOS

to integrate CMOS circuit to provide high functionality.

VLSI chips.

In the year 2014, a piezo-resistive stress measurement
circuit was developed to quantify real stress put on theprobe. A company-made polysilicon resistor, made byMicro Wireless Resonant Power Transfer that

post-processing commercial CMOS 0.6µm 1P2M cir-Enables Metabolism of Fragile MEMS Actuator.

cuit, was integrated into cantilever and responded toY. Mita, N. Sakamoto, B. Stefenelli,

the stress with good gauge factor (around 20).

A. Kaiser (ISEN/IEMN-CNRS)
The most severe problem of MEMS in which microactuators are exposed to the external world, such as

Design and Development of Micro-Latch Mechanism

Smar tBlocksII demonstrators, is that fragile micro-

for Low-Power and Long-Life MEMS Memory

actuators are little by little broken during usage, and

Y. Mita, K. Komeda, M. Kubota, A. Tixier-Mita

finally the entire system become unusable. The team

A low-power and long-life MEMS memor y having

proposes a “Metabolism MEMS” concept–the systemdata retention time over 1,000 years, write power underis composed with detachable two parts: One is frag-pico-Joule, and zero power for data retention. One ofile MEMS and the other is robust VLSI. The fragile

the application scenarios is cumulative hazard (suchMEMS are replaceable so that the system can haveas total exposure to radioactivity and or chemicals)

always a “fresh” surface. The key enabling technolo-

memory. The proposed multi-level memory stores thegy is wireless energy and command transfer, with on

information in terms of mechanical energy stored inelectrical wiring in between. For that purpose the teamthe MEMS spring that may yield low-power writingtries to use resonance power transfer method in theenergy and stable data retention. In the year 2014, a

submillimeter-scale, 1 GHz-range carrier. By Phenitec

zero hold-power memory device has been realized.

Semiconductor VDEC run LC oscillator was fabricated.
Magnetic power coupling experiments were successful in between the LSI and power receiver with ciliary
motion MEMS actuator.

Chapter 3

Right-Brain-Computing Integrated Circuits:
Associative Processing Systems
B. Ka, N. Yamashita, Y. Mita
Digital computers are dedicated machines for vary
fast execution of numerical calculations. However, their“Sixth Sense” Devices with CMOS-MEMS
Technology
Y. Mita, S. Inoue, M. Denoual (ENSI de Caen, France),

ing, recognizing, and taking immediate actions, which

Eric Lebrasseur,are ef for tless tasks in our daily life. This researchJean-Bernard Pourciel (LAAS-CNRS, France),

aims at building intelligent VLSI systems based on

Takahisa Masuzawa (professor emeritus UTokyo)

3-1
31

the psychological model of a brain. In our system past

One of the most important application field of MEMS

experience is stored as template vectors in non-volatile

is “sixth sense”，which means that sensors that canvast memories and the maximum-likelihood event todetect physical and chemical amount that cannot be

the current event is recalled in real time by a fully par-sensed by human beingsʼsensors. The team aims atallel processing. The key ingredient of the system is asolving this issue by VLSI-integrated compact microde-new functional device called “Neuron MOS Transistor”

vice. The development includes an integrated bolome-(neuMOS or νMOS) which mimics the action of ater that can detect infrared wave very rapidly and sensi-

nerve cell neuron at a single transistor level. Based on

tively, and integrated system that can make profiling ofsuch architecture that “association” is the very comput-

very small holes.

Research in VDEC

performance is extremely poor in such tasks like see-ing primitive, we are pursuing human-like intelligencesystem implementation directly in silicon integrated

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Takagi-Takenaka Laborator y(http://www.mosfet.k.u-tokyo.ac.jp/)

We have also developed Ge/s-Si TFET for high Ion operation.

Current Research Projects
Si CMOS photonics
III-V/Ge Metal-Oxide-Semiconductor (MOS) FETs
S. Takagi, M. Takenaka, Cai Weili, Yu Xiao,
WuKang Kim, Chang Chih-Yu, Kouichi Nishi,
Ke Mengan
We have conducted the research on high-peformance
III-V/Ge MOSFETs.

M. Takenaka, S. Takagi, Y. Kim, J. Han, J. Kang,
K. Takeuchi
High-sensitivity Ge photodetectors (PDs) has been
investigated. We have successfully developed high-qualitgy Ge-on-Insulator (GOI) by using wafer bonding
and splitting. We have also developed carrier-injection

We have successfully demonstrated wafer-size scalable

strained SiGe-based optical modulators with MZI inter-

III-V-OI wafer by using the direct wafer bonding of III-V

ferometers and successfully demonstrated the enhanced

epi on Si substrate. By using the III-V-OI, the high-per-plasma dispersion effect in SiGe. We have also inves-formance InGaAs MOSFETs were obtained. We havetigated MOS based SiGe optical modulators. We havealso demonstrated InAs/GaSb CMOS by using the wafer

revealed the plasm post-nitridation can form high-quality

bonding.

SiGe MOS interface even on the (110) surface.

We have also obtained high-quality Ge-on-Insulator(GOI) wafer by suing high-temperature Ge condensation.

III-V CMOS photonics
S. Takagi, M. Takenaka, Y. Chen, Y. Ikku, J. Park,
S. Takashima

Tunnel FET

High-per formance electronic-photonic integrated

S. Takagi, M. Takenaka, Min-Soo Kim, Kouichi Nishi,

circuits using III-V-OI wafer have been investigated. By

Sangmin Ji, Daehwan An, Daiki Ueda

using Si implantation and SOG Zn diffusion, we have

For low-power application, tunnel FET, which canformed low-resistance lateral PIN junction on the III-V-

exhibit steep subthreshold slope have been investigated.

OI wafer. We have also demonstrated low-dark-current

We have found that even in high-indium-content InGaAs

waveguide InGaAs photodetector on the III-V-OI wafer

channel, a low Ioff and steep subthreshold slope can beby using InAlAs passivation.

Chapter 3

obtained by using the InGaAs quantum well structure.

3-1
32

Research in VDEC
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VDEC2015_E.indd 33

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VLSI Design and Education Center, The University of Tokyo
Annual Report
July, 2015
Published by
VLSI Design and Education Center, The University of Tokyo
Director Kunihiro Asada
Address: Yayoi 2-11-16, Bunkyo-ku, Tokyo, 113-8656, Japan
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平成27年度
VLSI Design and Education Center The University of Tokyo 2015

東京大学
大規模集積システム設計教育研究センター

年 報

2015
VLSI Design and Education Center,
The University of Tokyo
Annual Report

VLSI Design and Education Center The University of Tokyo 2015

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