Takayasu Sakurai
Center for Collaborative Research and Institute of Industrial Science, University of Tokyo
7-22-1, Roppongi, Minato-ku, Tokyo 106-8558, Japan

Abstract

Introduction

VLSI designers will face three crises in the
coming years: the power crisis, interconnection
crisis, and complexity crisis. This paper discusses
these crises and possible solutions to them andpresents a possible view of future VLSIs.

In the last few years, the economic environment surrounding the semiconductor industry has been harsh, but from this year, strong
growth is expected to return, as shown in Fig.
1. The market has been changing from being

Fig. 1 World semiconductor market. Data is taken from world semicon market statistics.

memory oriented to being processor and logicoriented. The market leader is expected to be
the System-on-a-Chip (SoC), which integrates
processors, logic, and memory. Technicallyspeaking, the history of VLSIs is a history ofminiaturization. The gate length of MOSFETs

Fig. 3 Scaling law. k denotes a scaling variable, which is 2 when the size is scaled down to a half. For
example, power density increases by a factor of 20.7 (~1.6) when the device size is shrunk to a half.

1

Fig. 2 Trend in design rule of VLSI, gate length of MOS transistors, gate oxide thickness and
DRAM bit capacity per chip. Data is taken from ITRS’99 [1].

Fig.4 Ever Increasing VLSI Power. Data points are taken from processors reported at theInternational Solid-State Circuits Conference.

JSAP International No.3 (January 2001)15

has now shrunk to 0.13µm and the gate oxide
is only a few SiO2 molecule layers thick, asshown in Fig. 2. This miniaturization is backed
by the scaling theory, which states that a
MOSFET operates at higher speed without any
degradation of reliability when the device sizeis scaled by a factor of k and, at the same time,
the operating voltage is scaled by a factor of k
as shown in Fig. 3. The circuit cost per functionis also decreased by miniaturization. Thus, thecost-performance is rapidly improved as devices
are scaled down. That is why miniaturization
has been pursued so persistently for the last
thirty years and will continue to be pursued in
the future. Recently, however, undesirable sideeffects of scaling have become noticeable. The
power density increases; interconnect-related
quantities, such as interconnect delay, current
density, and noise, increase; and, since the number of devices on a chip increases, designingand testing VLSIs become more difficult.
In short, there will be three crises in making VLSIs in the coming years: a power crisis,interconnection crisis, and complexity crisis. This
paper discusses these crises and possible solutions to them and presents a possible view of
future VLSIs.

Fig.5 Supply voltage, power and current trend.

Fig.7 Important technologies for low-power

Power crisis
Is the power crisis real? The answer isshown in Fig. 4. A single chip processor in production consumes more than 100 W of power
and this value will rise to about 150 W during
the next decade, as shown in Fig. 5, which iscomparable to an electric light bulb. The power
consumption does not sound like an important
figure-of-merit, when compared with speed
and cost. When we think back to the 1980s,
however, we recall that CMOS technology took
over the position of dominant technology fromNMOS and bipolar technology. CMOS is more
expensive than NMOS and slower than bipolarat the device level, but its low-power characteristics led to higher integration that yieldedhigher performance at the system level. Thus,
power consumption is a very important figureof-merit in predicting the trend of technology.
In addition to the heat generated by the
consumed power, the huge current needed tooperate VLSIs is also an issue. The increase incurrent will come from the decrease in supply
voltage (VDD) to about 0.3 V in 15 years. Thishuge current will give rise to the IR (currentresistance) voltage drop problem, which is described in the interconnect section. Low-power
design of VLSIs is important not only because
power consumption is rising dramatically as a

Fig.6 Power and delay dependence on VDD and VTH

Table 1 Controlling VDD and VTH for low power

Fig.8 Device-circuit cooperative approach for low power. Multiple use of VDD,VTH and tox is the key.

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Fig.9 VDD hopping for low-power

Fig.10 Interconnect determines cost and performance.

direct result of the scaling law, but also because
mobile electronic systems, which will form theinfrastructure of the information technology
age, need longer-lasting batteries.
The power and delay of a CMOS gate areexpressed bywhere pt is switching probability, CL is load
capacitance, VTH is threshold voltage, is a velocity saturation index whose value is about 1.3
for recent MOSFETs [2], f is the clock frequency,
and s is an s-factor whose value is about 0.1 V/
decade for bulk CMOS technology. The powerand delay of a typical CMOS gate are plottedin Fig. 6 and some of the important approaches
to achieving low power are summarized in Fig.
7. As can be understood from Fig. 6, if VDD islowered, the power is reduced effectively because it depends quadratically on VDD; however,the delay increases. The delay can be shortened
by decreasing VTH, but a low VTH induces a large
subthreshold leakage current, which prevents
the total power being decreased. Consequently,
the trade-off between speed and power should
be considered in order to decrease the power.
Promising schemes handle this trade-off bycontrolling VDD and VTH in some ways to reduce
power wastage and to adaptively use power
only when and where it is needed, as shown in
Table 1.
Low power has been pursued by many
researchers and engineers at the process, device, circuit, CAD, software, and system levels.

Fig.11 Interconnect cross-section and IR drop.

The new trend, however, is to search for a solution utilizing cooperation among different
levels, such as device-circuit cooperation andcircuit-software cooperation. One such effort
is shown in Fig. 8, where the device side provides transistors with multiple oxide thicknesses
and multiple threshold voltages, while the circuit side makes use of the various transistors
together with multiple voltages to lower the
power. For example, the CMOS logic part of a
VLSI is built with low-VTH MOSFETs, which areleaky, but a high-VTH, thick-tOX device is inserted
in series with the logic part to cut off the leakage when the logic is not being used. The leakage is caused not only by the subthreshold current, but also by gate oxide tunneling and thereverse-biased junction current. Boosting thegate voltage of the inserted transistor maxi-

Fig.12 Trend in coupling capacitance.

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for any data input but the highest performanceis only needed for 6% of the time. How muchof the time do you work flat out? Not much,huh? If you worked at maximum performance
all the time, you'd soon become burnt out. The
same is true for the variable VDD processor. Highest performance, though, defines your capability.

Interconnect crisis

Fig.13 Delay fluctuation due to coupling capacitance [6]Fig.14 Delay reduction by buffer insertion. a) without buffers and b) with buffers.

Fig.15 Delay fluctuation due to coupling capacitance with non-staggered and staggered buffers.

mizes the drain conductance of the inserted
transistor, which in turn yields high-speed operation [3]. The effective use of multiple values
of VDD, tOX, and VTH is the key to prevent power
consumption from increasing explosively.
Another example of a promising cooperative approach is found in the circuit and software level, as shown in Fig. 9, namely the VDD
hopping scheme. The circuit side provides a18

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processor whose operating frequency and VDD
can be varied by software. The software side
controls the frequency and VDD adaptively sothat the frequency is halved when high-speed
operation is not needed. The scheme has been
applied to a digital video codec system and theprocessor power is only one-fourth that of theconventional fixed VDD processor [4, 5]. The video
codec system guarantees real-time operation

The interconnect crisis is shown in Fig. 10.
The cost, delay, power, reliability, and turnaround time of the future VLSIs will be determined not by transistors but by interconnects.
There are many design issues for deep-submicron interconnects. The higher current leads tostatic and dynamic IR voltage drop problems
and reliability degradation due to electro-migration. The smaller geometry and denser pattern lead to an increase in RC delay and signal
integrity problems such as high crosstalk noiseand large delay fluctuation due to capacitive
coupling among adjacent lines. The higher
speed causes inductance-related issues andelectromagnetic interference problems.
A huge operating current will be requiredin the future for high-performance VLSIs as
shown in Fig. 5. Such a high current creates a
voltage drop due to the resistance of the power
supply lines. Even a medium-power-consuming chip will need a very thick metal layer, like
10 µm, to keep the IR drop within an acceptable level as shown in Fig. 11. This thick metal
will be implemented in a package. In the future, area pads and co-design of a VLSI and its
package will become necessary.
Signal integrity is becoming one of the
major design issues due to the increased coupling capacitance between interconnects. The
higher aspect ratio of deep sub-micron interconnects increases the coupling capacitanceamong lines, relative to the grounding capacitance as shown in Fig. 12. The delay of an interconnect may fluctuate by a factor of about
4 between in-phase and anti-phase driving ofadjacent lines (see Fig. 13) [6]. This forces designers to think about the voltage behaviors ofadjacent lines in addition to the delay of thetarget interconnect, which is a nightmare. The
delay fluctuation due to the coupling capacitance can be mitigated by using a buffer insertion technique as shown in Fig. 14. The fluctuation will be further reduced by staggering
the locations of buffers even in the worst caseas shown in Fig. 15 [7].
Efforts are being made to lower the resistance and capacitance of interconnects asFig.16 Trend in interconnect related parameters. Data istaken from ITRS’97.

Fig.17 RC delay and gate delay.

Fig.18 Trend in interconnect delay with buffer insertion.

shown in Fig. 16. Still, the interconnect delay is
a big headache in designing a scaled-down interconnect system. If we use the interconnect
with the minimum cross-section, the signal cannot propagate a distance of 1 mm in one clock
cycle as shown in Fig. 17. The RC delay problem can be mitigated by using the buffer insertion technique already described in Fig. 14. The
delay can be reduced by this technique asshown in Fig. 18, but the power increases by
about 70% due to the inserted buffers, which
will be described in more detail below. Anotherway to decrease the interconnect delay without increasing the power is to use a thicker andwider metal layer as in Fig. 16 using the superconnect technology described below. If a thickmetal layer is available, which could be a layer
in a package, by using a 6 µm x 6 µm crosssection interconnect, the RC delay can be reduced to the point where the signal can propagate anywhere within the chip within one aclock cycle as shown in Fig. 19. This approach
does not increase capacitance and hence power
in contrast to the buffer insertion approach.
The drawback is the density.
Here, I would like to add an importantpiece of information concerning the RC delayof an interconnect and its behavior due to thescaling. It is known that inserting buffers (orsometimes they are called repeaters) can lower
the delay of a long interconnect. Let us think
about the delay of a buffered interconnect system. The delay of an unbuffered interconnect
can be approximately expressed aswhere CINT is the capacitance of the interconnect and RINT is its resistance, CT is the gate capacitance of the load, and RT is the drain effec-

tive resistance of the driving transistor (see Fig.
14). If the interconnect is divided into k sections and (k-1) buffers are inserted, the total
delay of the buffered interconnect system isexpressed aswhere h denotes the gate size of the inserted
buffer, C0 is the gate capacitance of the minimum width transistor, and R0 is the gate effective resistance of the minimum width transistor. Here, k and h should be optimized to minimize the delay expressed in the above formula. By differentiating with respect to h andk, and setting the derivatives equal to zero,
we can easily obtain the optimum h, hOPT, andoptimum k, kOPT.

Then the optimized delay is expressed as

Here, (τINT (=RINTCINT) is a time constant of theinterconnect and ( τ MOS (=R0C0) is a time constant of the inserted buffer, which is proportional to the logic gate delay of a certain technology node; p1 is 0.377 and p2 is 0.693 forthe case of the delay from zero to a half VDD,
but even if these values are different, optimization is possible for the delay from zero to 0.9
V DD or to other intermediate values. In thissense, the formula is quite general. The above

Fig.19 RC delay of global interconnects.

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Fig.20 Technologies integrated on a chip. The numbers in the bars show the increase ofmask steps extra to a logic process.

Fig.22 Super-connect technology.

Fig.21 System-on-a-Chip vs. System-in-a-Package.

Fig.23 Performance gap between off-chip and on-chip interconnects.

expression is interesting in that the delay of thebuffered interconnect system is the geometricmean of the interconnect delay itself and thedelay of the logic gate. Since the scaling factorof the interconnect delay is almost constant andthe delay of the logic gate is expected to improve very rapidly as technology advances, scaling of the delay of the buffered interconnect
system should improve slowly along with the
speed improvement of the logic gates.
In the optimally buffered interconnect, thecapacitance of the system increases due to theinserted buffers. The total gate capacitance ofbuffers is expressed as

This means that the total capacitance is 73%

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higher than that of a system without buffers.
The increase in capacitance in turn increases
power consumption.

Complexity crisis
It is quite impossible to design a VLSI withbillions of transistors from scratch. The complexity crisis can only be solved by sharing design data and re-using it. By doing so, we candesign an electronic system at a higher level ofabstraction. The so-called IP (Intellectual Property)-based System-on-a-Chip (SoC) design style
will be preferable. Here, the IP is transferable
design data related to VLSIs. The virtual components are put together on a silicon chip tobuild billion-transistor VLSIs, which can be compared to the present system implementation

with separately packaged VLSI components andprinted circuit boards.
However, SoC issues have been getting
clear as the VLSI industry has pursued extensively the SoC. Some issues are undistributedIPs (i.e., CPU, DSP of a certain company), huge
initial investment for masks and development,
IP testability, upfront IP test cost, process-dependent memory IPs, difficulty in embedding
high-precision analog IPs due to noise, and process incompatibility with non-Si materials and/or MEMS. The mask count increases greatly if
different types of technologies are included ona single chip as shown in Fig. 20. Moreover,the embedding technologies should be developed for each generation and if the types oftechnologies are diverse, the required engineer-Table 2 Predicted important parameters related to VLSI’s in 2014. Factor is the ratio between the values in2014 and those in 1999.

ing efforts are too big to sustain.
Another way to cope with the complexity
crisis is to make use of an advanced assembly
technology. Here, components are real components instead of virtual components and we
can design an electronic system by assembling
the real components; that is, we can design inhigher abstraction and thus escape from thecomplexity crisis. A new type of assembly technology called System-in-a-Package has been
proposed as shown in Fig. 21. This will use 'super-connect' technology, as shown in Fig. 22,with an interconnect thickness on the order of
10 µm. Super-connect technology will fill thetechnology vacuum between the design ruleorders of 1 µm for on-chip interconnects and100 µm for off-chip interconnects. Super-connects in a package used in cooperation withon-chip interconnects will solve the IR voltage
drop problem, the clock distribution problem,and other problems of future VLSIs. The codesign of on-chip interconnects and super-connects in a package will become important, but
it will require the development of a new set of
EDA tools.
The super-connect technology fills the gap
between off- and on-chip interconnects not
only in terms of design rules but also in termsof power, bandwidth, area, cost, and turnaround-time, as shown in Fig. 23. The major
issue in making the System-in-a-Package, however, is to establish a method for selecting
known good dies before assembly. It is very
difficult to test a bare chip at its operating speed
without a package, since probing needles used
for the wafer test cannot handle signals more

Fig.24 Possible electronic system in the future.

than a hundred MHz. Recently, however, a new
test method using a pseudo-package called aninterposer has been proposed. The pseudopackage enables a chip to be tested at full operating speed, which may solve the known
good die problem. Assembly and packaging
technology is becoming vital to VLSIs as evidenced by the following passage from the International Technology Roadmap for Semiconductors (ITRS): “There is an increased awareness in the industry that assembly and packaging is
becoming a differentiator in product development.”

predictions are taken from the ITRS [1]. The overall future prospects for VLSIs in 2014 are shownin Fig. 24. Sensors and actuators can be built ona chip. The design rule will be around 0.035 µm,
integrating more than 3 billion silicon transistors on a chip. Some mechanism to control VTH
and VDD will be necessary to cope with the highpower consumption problem. The clock frequency is predicted to be around 17 GHz locallyand globally the chip will be operated asynchronously. VLSIs, packages, and higher assembly
structures will be co-designed to raise the performance of electronic systems.

VLSIs in coming years
Some of the important parameters related
to VLSIs in 2014 are summarized in Table 2. These

References[1] International Technology Roadmap for Semiconductors: 1999 edition. Austin, TX: International
SEMATECH,1999.
[2] T. Sakurai and A. Newton, “Alpha-power law MOSFET model and its application to CMOS inverter delay
and other formulas,” IEEE JSSC, vol. 25, no. 2, pp. 584-594, Apr. 1990.
[3] T. Inukai, M. Takamiya, K. Nose, H. Kawaguchi, T. Hiramoto and T. Sakurai, “Boosted Gate MOS (BGMOS):
Device/Circuit Cooperation Scheme to Achieve Leakage-Free Giga-Scale Integration,” CICC'00, p. 409,
May 2000.
[4] S. Lee and T. Sakurai, “Run-time Power Control Scheme Using Software Feedback Loop for Low-Power
Real-time Applications,”ASPDAC'00, A5.2, pp. 381-386, Jan. 2000.
[5] S. Lee and T. Sakurai, “Run-time Voltage Hopping for Low-power Real-time Systems,” DAC'00, June 2000.
[6] H. Kawaguchi and T. Sakurai, “Delay and Noise Formulas for Capacitively Coupled Distributed RC Lines,”
1998 ASPDAC, Digest of Tech. Papers, pp. 35-43, Feb. 1998.
[7] Koichi Nose, private communications.

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