CH32V003 Datasheet
V1.3

Overview
CH32V003 series is an industrial-grade general-purpose microcontroller designed based on QingKe RISC-V2A
core, which supports 48MHz system main frequency in the product function. The series features wide voltage,
single-wire serial debug interface, low-power consumption and ultra-small package. It provides commonly used
peripheral functions, built-in 1 group of DMA controller, 1 group of 10-bit analog-to-digital conversion ADC, 1
group of op-amp comparator, multiple timers, standard communication interfaces such as USART, I2C, SPI, etc.
The rated operating voltage of the product is 3.3V or 5V, and the operating temperature range is -40℃～85℃
industrial- grade.

Features
l

l

l

l

l

Core
- QingKe 32-bit RISC-V core, RV32EC
instruction set- Fast programmable interrupt controller +hardware interrupt stack- Support 2-level interrupt nesting- Support system main frequency 48MHz
Memory- 2KB volatile data storage area SRAM
- 16KB program memory CodeFlash- 1920B BootLoader- 64B non-volatile system configuration
memory- 64B user-defined memory
Power management and low-power
consumption- System power supply VDD: 3.3V or 5V- Low-power mode: Sleep, Standby
Clock & Reset- Built-in factory-trimmed 24MHz RC
oscillator- Built-in 128KHz RC oscillator- High-speed external 4~25MHz oscillator- Power on/down reset, programmable voltage
detector
1 group of 1-channel general-purpose DMA
controller- 7 channels, support ring buffer- Support TIMx/ADC /USART/I2C/SPI

l
l

l

l

l

l
l
l

1 group of OPA and comparator: connectedwith ADC and TIM2
1 group of 10-bit ADC- Analog input range: 0~VDD- 8 external signals + 2 internal signals- Support external delayed triggering
Multiple timers- 1 16-bit advanced-control timers, with deadzone control and emergency brake; can offer
PWM complementary output for motor control- 1 16-bit general-purpose timers, provide
input capture/output comparison/PWM/pulse
counting/incremental encoder input- 2 watchdog timers (independent watchdog
and window watchdog)- SysTick: 32-bit counter
Communication interfaces- 1 USART interfaces- 1 I2C interfaces- 1 SPI interfaces
GPIO port- 3 groups of GPIO ports, 18 I/O ports- Mapping 1 external interrupt
Security features: 64-bit unique ID
Debug mode: 1-wire serial debug interface(SDI)
Package: SOP, TSSOP or QFNModelCH32V003F4P6

General- Advanced- GeneralSystem ADC
Flash
Pin
PackageSRAM
purpose control purpose Watchdog clock ChannelSPI I2C USART
memory
No.
Form
I/O
timer
timer
source No.
16K

2K

20

18

1

1

2

3

8

CH32V003A4M6

16K

2K

16

14

1

1

2

3

6

CH32V003J4M6

16K

2K

8

6

1

1

2

3

6

CH32V003F4U6

1-TSSOP20

1

1

1

1

SOP16

1

1

SOP8

QFN20

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Chapter 1 Specification
1.1 System architecture
The microcontroller is based on the RISC-V instruction set of QingKe V2A design, and its architecture
includes the core, arbitration unit, DMA module, SRAM storage and other parts of the interaction throughmultiple groups of buses. The design integrates a general-purpose DMA controller to reduce CPU load andimprove access efficiency, and also has data protection mechanisms and automatic clock switching protection
to increase system stability. The following diagram shows the overall architecture of the product.
Figure 1-1 System block diagram

RISC-V (V2A)
SWIO

RV32EC

D-code Bus

DMA 7 Channels

Flash
MemoryMUX

PFIC
1-wire SDI

System Bus

MUX

VDD : 2.7V~5.5V
VSS

@VDD

FLASH
CTRL

I-code Bus

Reset &
MUX & DIVSRAM

SYSCLK

HSI-RC*2

AHBCLK

WWDG

HSE

GPIO
IWDG_CLKPWR_CLKIWDG

LSI-RCEXTIAHB Fmax = 50MHz

EXTEN
AIN0~AIN7ETR、ETR2

ADC
Amplify

OPAPx
OPANx
(x=0,1)

PWR
I2C
AFIO

OPAO
CompareTIM2_CH1
4 channels, ETR

GPIOA

PA1 ~ PA2GPIOC

PC0 ~ PC7GPIOD

PD0 ~ PD7

TIM2
TIM1

RX, TX, CTS, RTS, CK

4 channels
3 complementary Channels
ETR, BIKN

USART
SPI

V1.3

SCL, SDA

1

MOSI,MISO,SCK, NSS

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1.2 Memory map
Figure 1-2 Memory address map
Reserved
0x5005 0400

Reserved
0x4002 3C00
0x4002 3800

EXTEND
Reserved

0x4002 2400
0x4002 2000
0x4002 1400
0x4002 1000

Flash Interface
Reserved
RCC
Reserved

0x4002 0400
0x4002 0000

DMA

Reserved
0x4001 3C00
0x4001 3800
0x4001 3400
0x4001 3000
0x4001 2C00
0x4001 2800
0x4001 2400

0xFFFF FFFFF

0x4001 1800
0x4001 1400

0x1FFF FFFF
0x1FFF F840
0x1FFF F8000x1FFF F7C0
0x1FFF F780

Reserved

Reserved
Option Bytes
Vendor Bytes
Reserved

0x4001 1000
0x4001 0C00

0xE010 0000
0xE000 0000

0x4001 0800

Core Private
Peripherals

0x4001 0400
0x4001 0000

USART
Reserved
SPI
TIM1
Reserved
ADC
Reserved
Port DPort C
Reserved
Port A
EXTI
AFIO
Reserved

0x4000 7400

System FLASH(BOOT_1920B)

0x4000 7000

PWR

Reserved

0x1FFF F000

Reserved
Reserved
0x4000 5800

0x0800 4000

0x4000 0000
Code FLASH
16KB

0x0800 0000

0x0000 0000

Aliased to Flash or
system memory
depending on
softwareconfiguration

Peripherals
Reserved

0x2000 0800

2KB SRAM

0x2000 0000

0x4000 3000
0x4000 2C00

0x0000 0000

2

I2C
Reserved

0x4000 3400

FLASH

4G linear address space

V1.3

0x4000 5400

IWDG
WWDG
Reserved

0x4000 0400
0x4000 0000

TIM2

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1.3 Clock tree
Three groups of clock sources are introduced into the system: internal high-frequency RC oscillator (HSI),
internal low-frequency RC oscillator (LSI), external high-frequency oscillator (HSE), and external
low-frequency oscillator (LSE). Among them, the low-frequency clock source provides the clock reference
for RTC and independent watchdog. The high-frequency clock source is directly or indirectly output assystem clock (SYSCLK) via 2X frequency. The system clock is then provided by each prescaler to provide
the AHB domain in peripheral control clock and sampling or output clock. Some modules need to be directly
provided by the PLL clock.

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Figure 1-3 Clock tree block diagram
to gpio(internal,to time)

128kHzLSI RCIWDGCLK

to independent watchdog
to pwr(low power clock source)

RCC_CFGR0
OSC_INOSC_OUT

SW*2

4~25MHzHSE OSCSYSCLK
to Flash(time base)

/3

SW

24MHz
HSI RCHSICSSMCO[1:0]

MCO

HSI
HSE

PLLSRC

to Flash（register）

AHB prescaler/1,/2.../256

PLLCLKFCLK core free running clock
to Core System Timer/8
HCLK
48MHz max

to SRAM/DMA
peripheral clock enable
to AHB peripherals
peripheral clock enable

to TIM2
peripheral clock enable
to TIM1
peripheral clock enable/2,/4,/6,/8,/12,/1
6…,/64,/96,/128/4096
peripheral clock enable

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ADCPREto ADC

to WWDG

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1.4 Functional description
1.4.1 RISC-V2A processor
The RISC-V2A supports the EC subset of the RISC-V instruction set. The processor is managed internally ina modular fashion and contains units such as a fast programmable interrupt controller (PFIC), extended
instruction support, and more. The bus is connected to an external unit module to enable interaction between
the external function module and the core. RV32EC instruction set, small-end data mode.
The processor with its minimal instruction set, multiple operating modes, and modular custom expansion canbe flexibly applied to different scenarios of microcontroller design, such as small area low-power embedded
scenarios.
l Support machine model Fast Programmable Interrupt Controller (PFIC)l 2-level hardware interrupt stack
l 1-wire serial debug interface (SDI)l

Custom extended commands

1.4.2 On-chip memory and boot mode
Built-in 2K bytes SRAM area for data storage, data loss after power down.
Built-in 16K bytes of program flash memory storage (Code FLASH) for user applications and constant data
storage.
Built-in 1920 bytes of system storage (System FLASH) for system bootloader storage (factory-cured
bootloader)
64 bytes are used for the system non-volatile configuration information storage area and 64 bytes are used forthe user select word storage area.
Support Boot and user code jumping to each other.

1.4.3

Power supply scheme

VDD = 2.7～5.5V: Power supply for some I/O pins and internal voltage regulator (VDD performance gradually
deteriorates if less than 2.9V when using ADC).

1.4.4 Power supply monitor
This product integrates a power-on reset (POR)/power-down reset (PDR) circuit, which is always in working
condition to ensure that the system is in supply. It works when the power exceeds 2.7V; when VDD is lower
than the set threshold (VPOR/PDR), the device is placed in the reset state without using an external reset circuit.
In addition, the system is equipped with a programmable voltage monitor (PVD), which needs to be turnedon by software to compare the voltage of VDD power supply with the set threshold VPVD.Turn on thecorresponding edge interrupt of PVD, and you can receive interrupt notification when VDD drops to the PVD
threshold or rises to the PVD threshold. Refer to Chapter 4 for the values of VPOR/PDR and VPVD.

1.4.5 Voltage regulator
After reset, the regulator is automatically turned on, and there are 3 operation modes according to theapplication mode.
l ON mode: Normal operation, providing stable core power.
l Low-power mode: When the CPU enters Stop mode, system automatically enters Standby mode.
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1.4.6 Low-power mode
The system supports 2 low-power modes, which can be selected for low-power consumption, short start-up
time and multiple wake-up events to achieve the best balance.
l Sleep mode
In Sleep mode, only the CPU clock is stopped, but all peripheral clocks are powered normally and the
peripherals are in a working state. This mode is the shallowest low-power mode, but it is the fastest mode to
wake up the system.
Exit condition: any interrupt or wake-up event.

l Standby mode
The PDDS and SLEEPDEEP bits are set, and the WFI/WFE instruction is executed to enter. The power
supply of the kernel part is turned off, and the RC oscillator of HSI and the HSE crystal oscillator are also
turned off, and the lowest power consumption can be achieved in this mode.
Exit conditions: any external interrupt/event (EXTI signal), external reset signal on NRST, IWDG reset,
where EXTI signal includes one of 18 external I/O ports, output of PVD, AWU auto-wakeup.

1.4.7 Fast Programmable Interrupt Controller (PFIC)
The product's built-in Fast Programmable Interrupt Controller (PFIC) supports up to 255 interrupt vectors,
providing flexible interrupt management capabilities with minimal interrupt latency. The current productmanages 4 core private interrupts and 23 peripheral interrupt management, with other interrupt sources
reserved. the registers of PFIC are all accessible in machine privileged mode.
l 2 individually maskable interrupts
l Provide a non-maskable interrupt NMI
l Hardware interrupt stack (HPE) support without instruction overheadl Provide 2-way meter-free interrupt (VTF)l Support vector table mode for address or instruction model Support 2-level interrupt nestingl Support break tail link function

1.4.8 External interrupt/event controller (EXTI)The external interrupt/event controller contains a total of 8 edge detectors for generating interrupt/event
requests. Each interrupt line can be independently configured with its trigger event (rising or falling edge or
double edge) and can be individually masked; the pending register maintains the status of all interrupt
requests. EXTI can detect clock cycles with pulse widths less than the internal AHB. 18 general purpose I/O
ports are optionally connected to the same external interrupt source.

1.4.9 General-purpose DMA controller
The system has built-in 1 group of general-purpose DMA controllers, manages 8 channels in total, andflexibly handles high-speed data transmission from memory to memory, peripherals to memory, and memory
to peripherals, and supports ring buffer mode. Each channel has a dedicated hardware DMA request logic tosupport one or more peripherals' access requests to the memory. The access priority, transfer length, source
address and destination address of the transfer can be configured.
The main peripherals used by DMA include: general-purpose/advanced-control/basic timers TIMx, DAC,
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USART, I2C and SPI.
Note: DMA and CPU access the system SRAM after arbitration by the arbiter.

1.4.10 Clock and bootThe system clock source HSI is turned on by default. After the clock is not configured or reset, the internal
24MHz RC oscillator is used as the default CPU clock, and then an external 4~25MHz clock or PLL clock
can be additionally selected. When the clock security mode is turned on, if the HSE is used as the system
clock (directly or indirectly), the system clock will automatically switch to the internal RC oscillator whenthe external clock is detected to be invalid, and the HSE and PLL will be automatically turned off at the sametime; in low-power consumption mode, the system will automatically switch to the internal RC oscillator
after waking up. If the clock interrupt is enabled, the software can receive the corresponding interrupt.

1.4.11 Analog-to-digital converter (ADC)
The product is embedded with a 10-bit analog/digital converter (ADC) that shares up to eight external
channels and two internal channel samples, with programmable channel sampling times for single,
continuous, sweep or intermittent conversion. Provides analog watchdog function allows very accuratemonitoring of one or more selected channels for monitoring channel signal voltages. Supports external
event-triggered transitions with trigger sources including internal signals from the on-chip timer and external
pins. Support for using DMA operation. Supports external trigger delay function. When this function isenabled, the controller delays the trigger signal according to the configured delay time when an external
trigger edge is generated, and the ADC conversion is triggered as soon as the delay time is reached.

1.4.12 Timer and watchdog
The timers in the system include an advanced-control timer, a general-purpose timer, two watchdog timers
and system time base timer.
l Advanced-control timer
The advanced-control timer is a 16-bit auto-loading up/down counter with a 16-bit programmable prescaler.
In addition to the complete general-purpose timer function, it can be regarded as a three-phase PWM
generator distributed to 6 channels, with a complementary PWM output function with dead zone insertion,
allowing the timer to be updated after a specified number of counter cycles to repeat counting cycle, braking
function, etc. Many functions of the advanced-control timer are the same as the general timer, and the internal
structure is also the same. Therefore, the advanced-control timer can cooperate with other TIM timers
through the timer link function to provide synchronization or event link functions.
l General-purpose timer
The general-purpose timer is a 16-bit or 32-bit auto-loading up/down counter with a programmable 16-bit
prescaler and 4 independent channels. Each channel supports input capture, output comparison, and PWM
generation and single pulse mode output. It can also work with advanced-control timers through the timer
link function to provide synchronization or event link functions. In Debug mode, the counter can be frozen
while the PWM outputs are disabled, thereby cutting off the switches controlled by these outputs. Any
general-purpose timer can be used to generate PWM output. Each timer has an independent DMA request
mechanism. These timers can also process signals from incremental encoders, as well as digital outputs from
1 to 3 Hall sensors.

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http://wch.cnl Independent watchdog
The independent watchdog is a configurable 12-bit down counter that supports 7 frequency division factors.
The clock is provided by an internal independent 128 KHz RC oscillator (LSI); because the LSI isindependent of the main clock, it can run in Stop and Standby modes. IWDG is outside the main program andcan work completely independently. Therefore, it is used to reset the entire system when a problem occurs, or
as a free timer to provide timeout management for the application. It can be configured as software or
hardware to start the watchdog through the option byte. In Debug mode, the counter can be frozen.
l Window Watchdog
The window watchdog is a 7-bit down counter and can be set to free-running. It can be used to reset the entire
system when a problem occurs. It is driven by the main clock and has an early warning interrupt function; in
Debug mode, the counter can be frozen.
l SysTick Timer
This is a 32-bit optional increment or decrement counter that comes with the core controller. It is used togenerate SYSTICK anomalies (exception number: 15). It can be dedicated to the real-time operating system(RTOS) to provide a "heartbeat" tick for the system, or it can be used as a standard 32-bit counter. It has an
automatic reload function and a programmable clock source.

1.4.13 Communication interface
1.4.13.1 Universal Synchronous/Asynchronous Receiver Transmitter (USART)The product provides 1 group of Universal Synchronous/Asynchronous Receiver Transmitters (USART). It
supports full-duplex asynchronous communication, synchronous one-way communication and half-duplex
single-wire communication. It also supports LIN (Local Interconnect Network), compatible with ISO7816
smart card protocol and IrDA SIR ENDEC transmission codec specification, and modem (CTS/RTS
hardware flow control) operation. It also allows multi-processor communication. It uses a fractional baud rate
generator system and supports DMA operation continuous communication.
1.4.13.2 Serial Peripheral Interface (SPI)
1 serial peripherals interface (SPI) provide master or slave operation, dynamic switching. Support
multi-master mode, full-duplex or half-duplex synchronous transmission, support basic SD card and MMC
mode. Programmable clock polarity and phase, data bit width provides 8 or 16-bit selection, hardware CRC
generation/check for reliable communication, and continuous communication support for DMA operation.
1.4.14.3 I2C bus
1 I2C bus interface, able to work in multi-master mode or slave mode, complete with all I2C bus specifictiming, protocols, arbitration, etc., supporting both standard and fast communication speeds.
The I2C interface provides 7-bit or 10-bit addressing and supports dual slave address addressing in 7-bit slavemode. A hardware CRC generator/checker is built-in.

1.4.14 General-purpose input and output (GPIO)The system provides 3 groups of GPIO ports with a total of 18 GPIO pins. Each pin can be configured bysoftware as output (push-pull or open-drain), input (with or without pull-up or pull-down) or multiplexed
peripheral function port. Most GPIO pins are shared with digital or analog multiplexed peripherals. Except forports with analog input functions, all GPIO pins have high current passing capabilities. A locking mechanism isprovided to freeze the I/O configuration to avoid accidental writing to the I/O register.
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The I/O pins in the system is provided by VDD. Changing the VDD power supply will change the highvalue of the I/O pin output level to adapt to the external communication interface level. Please refer tothe pin description for specific pins.

1.4.15 Operational amplifier/comparator (OPA)
The product has a built-in set of op-amps/comparators, with internal selection associated to the ADC and
TIM2 (CH1) peripherals, whose inputs and outputs can be selected by changing the configuration for
multiple channels. Support for external analog small signals are amplified and fed into the ADC to achievesmall signal ADC conversion, can also complete the signal comparator function, the comparison results fromthe GPIO output or directly into the TIMx input channel.

1.4.16 1-wire serial debug interface (SDI)
The core comes with a 1-wire serial debug interface, SWIO pin (Single Wire Input Output). The default
debug interface pin function is turned on after system power on or reset.

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Chapter 2 Pinouts and pin definition
2.1 Pin arrangement
CH32V003F4P6
1
2
3
4
5
6
7
8
9
10

PD4/A7/UCK/T2CH1ETR/OPO/T1CH4ETR_
PD3/A4/T2CH2/AETR/UCTS/T1CH4_
PD5/A5/UTX/T2CH4_/URX_
PD2/A3/T1CH1/T2CH3_/T1CH2N_
PD6/A6/URX/T2CH3_/UTX_
PD1/SWIO/AETR2/T1CH3N/SCL_/URX_
PD7/NRST/T2CH4/OPP1/UCK_
PC7/MISO/T1CH2_/T2CH2_/URTS_
PA1/OSCI/A1/T1CH2/OPN0
PC6/MOSI/T1CH1CH3N_/UCTS_/SDA_
PA2/OSCO/A0/T1CH2N/OPP0/AETR2_
PC5/SCK/T1ETR/T2CH1ETR_/SCL_/UCK_/T1CH3_
VSS
PC4/A2/T1CH4/MCO/T1CH1CH2N_
PD0/T1CH1N/OPN1/SDA_/UTX_
PC3/T1CH3/T1CH1N_/UCTS_
VDD
PC2/SCL/URTS/T1BKIN/AETR_/T2CH2_/T1ETR_
PC0/T2CH3/UTX_/NSS_/T1CH3_
PC1/SDA/NSS/T2CH4_/T2CH1ETR_/T1BKIN_/URX_

20
19
18
17
16
15
14
13
12
11

20

19

18

17

16

PD4/A7/UCK/T2CH1ETR
PD4/OPO/T1CH4ETR_

PD3/A4/T2CH2/AETR
PD3/UCTS/T1CH4_

PD2/A3/T1CH1/T2CH3_
PD2/T1CH2N_

PC5/SCK/T1ETR/T2CH1ETR_
PC5/SCL_/UCK_/T1CH3_

12

PD0/T1CH1N/OPN1
PD0/SDA_/UTX_

PC4/A2/T1CH4/MCO
PC4/T1CH1CH2N_

11

PC3/T1CH3/T1CH1N_
PC3/UCTS_

13

PC2/SCL/URTS/T1BKIN
PC2/AETR_/T2CH2_/T1ETR_

14

9

5

VSS

15

PC7/MISO/T1CH2_
PC7/T2CH2_/URTS_

PC1/SDA/NSS/T2CH4_
PC1/T2CH1ETR_/T1BKIN_/URX_

4

PD1/SWIO/AETR2
PD1/T1CH3N/SCL_/URX_

PC6/MOSI/T1CH1CH3N_
PC6/UCTS_/SDA_

8

PA2/OSCO/A0/T1CH2N
PA2/OPP0/AETR2_

PC0/T2CH3/UTX_
PC0/NSS_/T1CH3_

PA1/OSCI/A1
PA1/T1CH2/OPN0

3

VDD

2

7

PD7/NRST/T2CH4
PD7/OPP1/UCK_

6

1

10

VSS

PD5/A5/UTX
PD5/T2CH4_/URX_

0

PD6/A6/URX
PD6/T2CH3_/UTX_

CH32V003F4U6

CH32V003A4M6
1
2
3
4
5
6
7
8

V1.3

PC1/SDA/NSS/T2CH4_/T2CH1ETR_/T1BKIN_/URX_ PC0/T2CH3/UTX_/NSS_/T1CH3_
PC2/SCL/URTS/T1BKIN/AETR_/T2CH2_/T1ETR_
VDD
PC3/T1CH3/T1CH1N_/UCTS_
VSS
PC4/A2/T1CH4/MCO/T1CH1CH2N_
PA2/OSCO/A0/T1CH2N/OPP0/AETR2_
PC6/MOSI/T1CH1CH3N_/UCTS_/SDA_
PA1/OSCI/A1/T1CH2/OPN0
PC7/MISO/T1CH2_/T2CH2_/URTS_
PD7/NRST/T2CH4/OPP1/UCK_
PD1/SWIO/AETR2/T1CH3N/SCL_/URX_
PD6/A6/URX/T2CH3_/UTX_
PD4/A7/UCK/T2CH1ETR/OPO/T1CH4ETR_
PD5/A5/UTX/T2CH4_/URX_

10

16
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CH32V003J4M6

1
2
3
4

PD6/A6/URX/T2CH3_/UTX_
PA1/OSCI/A1/T1CH2/OPN0

PD4/A7/UCK/T2CH1ETR/OPO/T1CH4ETR_
PD5/A5/UTX/T2CH4_/URX_
PD1/SWIO/AETR2/T1CH3N/SCL_/URX_

VSS

7

PC4/A2/T1CH4/MCO/T1CH1CH2N_
PC2/SCL/URTS/T1BKIN
PC2/AETR_/T2CH2_/T1ETR_

PA2/OSCO/A0/T1CH2N/OPP0/AETR2_
VDD

PC1/SDA/NSS/T2CH4_/T2CH1ETR_/T1BKIN_/URX_

8

6
5

Note: The multiplexed functions in the pin diagram are abbreviated.
Example: A: ADC, A7 (ADC_IN7)
T: TIME, T2CH4 (TIM2_CH4)
U: USART, URX (USART_RX)
OP: OPA, OPO (OPA_OUT), OPP1 (OPA_P1)
OSCI (OSCIN)OSCO (OSCOUT)
SDA (I2C_SDA)
SCL (I2C_SCL)
SCK (SPI_SCK)NSS (SPI_NSS)
MOSI (SPI_MOSI)MISO (SPI_MISO)AETR(ADC_ETR)

2.2 Pin description
Table 2-1 CH32V003xx pin definitions
Note: The pin function descriptions in the table below are for all functions and do not relate to specific model
products. Peripheral resources may vary between models, so please check the availability of this function
according to the product model resource table before viewing.

SOP16
TSSOP2
0

QFN20

SOP8

Pin No.

-

0

-

-

Pin
name

Pin
type

Main
function(afterreset)

Default alternate function

Remapping function

VSS

P

VSS

-

-

UCK/T2CH1ETR(1)/A7/

8

1

18

8

PD4

I/O/A

PD4

9

2

19

8

PD5

I/O/A

PD5

UTX/A5

T2CH4_3/URX_2

10

3

20

1

PD6

I/O/A

PD6

URX/A6

T2CH3_3/UTX_2

11

4

1

-

PD7

I/O/A

PD7

NRST/T2CH4/OPP1

UCK_1/UCK_2/T2CH4_2

12

5

2

1

PA1

I/O/A

PA1

T1CH2/A1/OPN0

OSCI/T1CH2_2

13

6

3

3

PA2

I/O/A

PA2

TICH2N/A0/OPP0

OSCO/AETR2_1/TICH2N_2

14

7

4

2

VSS

P

VSS

-

-

-

8

5

-

PD0

I/O/A

PD0

TICH1N/OPN1

SDA_1/UTX_1/TICH1N_2

15

9

6

4

VDD

P

VDD

-

-

16

10

7

-

PC0

I/O

PC0

T2CH3

NSS_1/UTX_3/T2CH3_2

V1.3

OPO

11

TIETR_2/T1CH4_3

CH32V003 Datasheet

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1

11

8

5

PC1

I/O/FT

PC1

SDA/NSS

T1BKIN_1/T2CH4_1
T2CH1ETR(1)_2/URX_3/T2CH1ETR(1)_3/T1BKIN_3

2

12

9

6

PC2

I/O/FTPC2

SCL/URTS/T1BKIN

AETR_1/T2CH2_1/T1ETR_3/URTS_1/T1BKIN_2

3

13

10

-

PC3

I/O

PC3

T1CH3

T1CH1N_1/UCTS_1/T1CH3_2/T1CH1N_3

4

14

11

7

PC4

I/O/A

PC4

T1CH4/MCO/A2

T1CH2N_1/T1CH4_2/T1CH1_3

SCK/T1ETR

T2CH1ETR(1)_1/SCL_2/SCL_3/UCK_3/T1ETR_1/T1CH3_3/SCK_1

MOSI

T1CH1_1/UCTS_2/SDA_2/SDA_3/UCTS_3/T1CH3N_
3/MOSI_1

-

5

15

16

12

13

-

-

PC5

PC6

I/O/FT

I/O/FT

PC5

PC6

6

17

14

-

PC7

I/O

PC7

MISO

T1CH2_1/URTS_2/T2CH2_3/URTS_3/T1CH2_3/MISO_1

7

18

15

8

PD1

I/O/A

PD1

SWIO/T1CH3N/AETR2

SCL_1/URX_1/T1CH3N_1/T1CH3N_2

-

19

16

-

PD2

I/O/A

PD2

T1CH1/A3

T2CH3_1/T1CH2N_3/T1CH1_2

-

20

17

-

PD3

I/O/A

PD3

A4/T2CH2/AETR/UCTS

T2CH2_2/T1CH4_1

Note: 1. TIM2_CH1, TIM2_ETR;
2. The value after the underline of the remapping function indicates the configuration value of thecorresponding bit in the AFIO register. For example: T1CH4_3 indicates that the corresponding bit of the
AFIO register is configured as 11b;
3. Explanation of table abbreviations:
I = TTL/CMOS level Schmitt input.
O = CMOS level tri-state output.
P = power supply.
FT = 5V tolerant.
A = Analog signal input or output.

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2.3 Pin alternate functions
Note: The pin function descriptions in the table below are for all functions and do not relate to specific model products. Peripheral resources may vary between models,so please check the availability of this function according to the product model resource table before viewing.
Table 2-2 CH32V003xx alternate function pin definitions
Alternate
Pin

PA1
PA2
PC0

ADC

TIM1

A1
A0/AETR2_1

T1CH2/T1CH2_2
T1CH2N/T1CH2N_2
T1CH3_1

PC1
PC2

T1BKIN_1/T1BKIN_3
AETR_1

PC3
PC4

A2

PC5
PC6
PC7
PD0
PD1

AETR2

PD2

A3

T1BKIN/T1ETR_3/T1BKIN_2
T1CH3/T1CH1N_1
T1CH3_2/T1CH1N_3
T1CH4/T1CH2N_1/T1CH4_2/T1CH1_3
T1ETR/T1CH3_3/T1ETR_1
T1CH1_1/T1CH3N_3
T1CH2_1/T1CH2_3
T1CH1N/T1CH1N_2
T1CH3N/T1CH3N_1/T1CH3N_2
T1CH1/T1CH2N_3/T1CH1_2
T1CH4_1
T1ETR_2/T1CH4_3

PD3
A4/AETR
PD4
A7
PD5
A5
PD6
A6
PD7
Note: TIM2_CH1、TIM2_ETR.

V1.3

TIM2

USART

SYS

I2C

SPI

SWIO

OSCI
OSCO
T2CH3/T2CH3_2
T2CH4_1/T2CH1ETR(1)_2/T2CH1ETR(1)_3

OPN0
OPP0

UTX_3

T2CH2_1

OPA

NSS_1

URX_3

SDA

URTS/URTS_1

SCL

NSS

UCTS_1
MCO
T2CH1ETR(1)_1

UCK_3

SCL_2/SCL_3

SCK/SCK_1

UCTS_2/UCTS_3
URTS_2/URTS_3
UTX_1

SDA_2/SDA_3

T2CH2_3

MOSI/MOSI_1
MISO/MISO_1

URX_1

SCL_1

SDA_1

OPN1
SWIO

T2CH3_1
T2CH2/T2CH2_2
T2CH1ETR(1)
T2CH4_3
T2CH3_3
T2CH4/T2CH4_2

UCTS
UCK
UTX/URX_2
URX/UTX_2
UCK_1/UCK_2

13

OPO

NRST

OPP1

CH32V003 Datasheet

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Chapter 3 Electrical characteristics
3.1 Test conditions
Unless otherwise specified and marked, all voltages are referenced to VSS.
All minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage
and clock frequency. Typical values are based on normal temperature (25℃) and VDD = 3.3V or 5V environment,
which are given only as design guidelines.
The data based on comprehensive evaluation, design simulation or technology characteristics are not tested in
production. On the basis of comprehensive evaluation, the minimum and maximum values refer to sample tests.
Unless otherwise specified that is tested, the characteristic parameters are guaranteed by comprehensive evaluation
or design.
Power supply scheme:
Figure 3-1 Typical circuit for conventional power supply

VDD
2.7-5.5V

0.1uF

VSS

3.2 Absolute maximum ratings
Stresses at or above the absolute maximum ratings listed in the table below may cause permanent damage tothe device.
Table 3-1 Absolute maximum ratings
SymbolDescription

Min.

Max.

Unit

TA

Ambient temperature during operation

-40

85

℃

TS

Ambient temperature during storage

-40

125

℃

VDD-VSS

External main supply voltage (VDD)

-0.3

5.5

V

Input voltage on the FT (5V tolerant) pin

VSS-0.3

5.5

V

Input voltage on other pins

VSS-0.3

VDD+0.3

VIN|△VDD_x|

Variations between different main power supply pins

50

mV|△VSS_x|

Variations between different ground pins

50

mV

V1.3

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CH32V003 Datasheet

VESD(HBM)

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Electrostatic discharge voltage (human body model, non-contact)

4K

V

IVDD

Total current into VDD power lines (supply current)

100

IVss

Total current out of VSS ground lines (outflow current)

80

Sink current on any I/O and control pin

20

Output current on any I/O and control pin-20

OSC_IN pin of HSE+/-4

Injected current on other pins+/-4

Total injected current on all I/Os and control pins

+/-20

II/O
IINJ(PIN)∑IINJ(PIN)mA

3.3 Electrical characteristics
3.3.1 Operating conditions
Table 3-2 General operating conditions
SymbolParameter

Condition

FHCLKInternal AHB clock frequency

VDD

Standard operating voltage

TA
TJ

Min.

Max.

Unit

50

MHz

ADC not used

2.7

5.5

Use ADC (recommended)

2.8

5.5

Ambient temperature

-40

85

℃

Junction temperature range

-40

85

℃

Min.

Max.

Unit

VDD rise time rate

0∞

VDD fall time rate

30

∞

V

Table 3-3 Power-on and power-down conditions
SymboltVDD

Parameter

Condition

us/V

3.3.2 Embedded reset and power control block characteristics
Table 3-4 Reset and voltage monitor (For PDR, select high threshold gear)
Symbol

VPVD

V1.3

(1)

Parameter

Programmable voltage
detector level selection

Condition

Min.

Typ.

Max.

Unit

PLS[2:0] = 000 (rising edge)

2.85

V

PLS[2:0] = 000 (falling edge)

2.7

V

PLS[2:0] = 001 (rising edge)

3.05

V

PLS[2:0] = 001 (falling edge)

2.9

V

PLS[2:0] = 010 (rising edge)

3.3

V

PLS[2:0] = 010 (falling edge)

3.15

V

PLS[2:0] = 011 (rising edge)

3.5

V

PLS[2:0] = 011 (falling edge)

3.3

V

PLS[2:0] = 100 (rising edge)

3.7

V

PLS[2:0] = 100 (falling edge)

3.5

V

PLS[2:0] = 101 (rising edge)

3.9

V

PLS[2:0] = 101 (falling edge)

3.7

V

PLS[2:0] = 110 (rising edge)

4.1

V

15

CH32V003 Datasheet

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VPVDhyst

PVD hysteresis

VPOR/PDR

Power-on/power-down
reset threshold

VPDRhyst

PDR hysteresistRSTTEMPOPLS[2:0] = 110 (falling edge)

3.9

V

PLS[2:0] = 111 (rising edge)

4.4

V

PLS[2:0] = 111 (falling edge)

4.2

V

0.18

V

Rising edge

2.32

2.5

2.68

V

Falling edge

2.3

2.48

2.66

V

20

Power on reset

12

Other resets

17

mV
22

300

mS
uS

Note: 1. Normal temperature test value.

3.3.3 Embedded reference voltage
Table 3-5 Embedded reference voltage
SymbolParameter

VREFINTInternal reference voltage

TS_vrefint

ADC sampling time whenreading the internalreference voltage

Condition

Min.

Typ.

Max.

Unit

TA = -40℃~85℃

1.17

1.2

1.23

V

500

1/fADC3

3.3.4 Supply current characteristics
Current consumption is a comprehensive index of a variety of parameters and factors. These parameters andfactors include operating voltage, ambient temperature, I/O pin load, the software configuration of the
product, the operating frequency, flip rate of the I/O pin, the location of the program in memory and theexecuted code, etc. The current consumption measurement method is as follows:
Figure 3-2 Current consumption measurement
Electric current
measurement

VDD
Electric current
measurement

The microcontroller is in the following conditions:
Normal temperature VDD = 3.3V or 5V case, when testing: all IO ports configured with pull-down inputs;
HSI on when testing HSE, HSE off when testing HSI, HSE= 24M, HIS= 24M (calibrated); system clock
source CLK*2 when FHCLK= 48MHz, 16MHz; clock on all peripherals only when turning on all peripherals.
Enables or disables power consumption of all peripheral clocks.

V1.3

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Table 3-6-1 Typical current consumption in Run mode, data processing code runs from the internal Flash(VDD = 3.3V)
Typ.
SymbolParameter

Condition

External clock

IDD

(1)

Supplycurrent inRun mode

Runs
on
the
high-speed internal
RC oscillator (HSI).
Uses AHB prescaler
toreducethefrequency.

All peripherals
enabledAll peripherals
disabled

FHCLK = 48MHz

7.0

4.6

FHCLK = 24MHz

5.2

4.2

FHCLK = 16MHz

4.6

3.8

FHCLK = 8MHz

3.1

2.7

FHCLK = 750KHz

1.8

1.8

FHCLK = 48MHz

6.3

3.9

FHCLK = 24MHz

4.3

3.1

FHCLK = 16MHz

3.9

3.1

FHCLK = 8MHz

2.3

1.9

FHCLK = 750KHz

1.1

1.0

Unit

mA

Note: 1. The above are measured parameters.
2. When VDD < 3V, the current power consumption will increase.

Table 3-6-2 Typical current consumption in Run mode, data processing code runs from the internal Flash(VDD = 5V)
Typ.
SymbolParameter

Condition

External clock

IDD

(1)

Supplycurrent inRun mode

Runs
on
the
high-speed internal
RC oscillator (HSI).
Uses AHB prescaler
toreducethefrequency.

All peripherals
enabledAll peripherals
disabled

FHCLK = 48MHz

8.0

5.6

FHCLK = 24MHz

6.4

5.6

FHCLK = 16MHz

5.8

5.0

FHCLK = 8MHz

3.8

3.4

FHCLK = 750KHz

2.2

2.1

FHCLK = 48MHz

7.3

4.9

FHCLK = 24MHz

5.3

4.1

FHCLK = 16MHz

5.0

4.3

FHCLK = 8MHz

3.1

2.7

FHCLK = 750KHz

1.4

1.4

Unit

mA

Note: 1. The above are measured parameters.

Table 3-7-1 Typical current consumption in Sleep mode, data processing code runs from internal Flash or
SRAM (VDD = 3.3V)
Typ.
SymbolIDD(1)
V1.3

Parameter
SupplyCondition
External clock

FHCLK = 48MHz
17

All peripherals
enabledAll peripherals
disabled

Unit

4.9

2.5

mA

CH32V003 Datasheet

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current in
Sleep mode
(In this case,
peripheral
power supply
and clock aremaintained)

Runs
on
the
high-speed internalRC
oscillator(HSI). Uses AHB
prescaler to reduce
the frequency.

FHCLK = 24MHz

2.9

1.7

FHCLK = 16MHz

2.5

1.7

FHCLK = 8MHz

1.7

1.3

FHCLK = 750KHz

1.2

1.1

FHCLK = 48MHz

4.2

1.8

FHCLK = 24MHz

2.2

1.0

FHCLK = 16MHz

1.8

1.0

FHCLK = 8MHz

1.0

0.6

FHCLK = 750KHz

0.4

0.4

Note: 1. The above are measured parameters.
Table 3-7-2 Typical current consumption in Sleep mode, data processing code runs from internal Flash or
SRAM (VDD = 5V)
Typ.
SymbolIDD

Parameter

Condition

Supplycurrent in
Sleep mode
(In this case,
peripheral
power supply
and clock aremaintained)(1)

External clock

Runs
on
the
high-speed internalRC
oscillator(HSI). Uses AHB
prescaler to reduce
the frequency.

All peripherals
enabledAll peripherals
disabled

FHCLK = 48MHz

4.9

2.5

FHCLK = 24MHz

2.9

1.7

FHCLK = 16MHz

2.5

1.7

FHCLK = 8MHz

1.7

1.3

FHCLK = 750KHz

1.2

1.1

FHCLK = 48MHz

4.2

1.8

FHCLK = 24MHz

2.2

1.0

FHCLK = 16MHz

1.8

1.0

FHCLK = 8MHz

1.0

0.6

FHCLK = 750KHz

0.4

0.4

Unit

mA

Note: 1. The above are measured parameters.

Table 3-8 Typical current consumption in Standby mode
SymbolParameter
Supplycurrent
Standby mode

IDD

Conditionin

LSI onLSI off

Typ.

VDD = 3.3V

10.5

VDD = 5V

11.1

VDD = 3.3V

9.0

VDD = 5V

9.6

Unit

uA

Note: The above are measured parameters.

3.3.5 External clock source characteristics
Table 3-9 From external high-speed clock
SymbolFHSE_ext
VHSEH
V1.3

(1)

Parameter

Condition

External clock frequency
OSC_IN input pin high level

Min.

Typ.

Max.

Unit

4

24

25

MHz

VDD

V

0.8VDD18

CH32V003 Datasheet

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voltage
VHSEL(1)

OSC_IN input pin low-level
voltageCin(HSE)OSC_IN input capacitance

DuCy(HSE)

Duty cycle

IL

0

0.2VDD54050

OSC_IN input leakage current

V
pF

60

%

±1

uA

Note: 1. Failure to meet this condition may cause level recognition error.
Figure 3-3 External high-frequency clock source circuit
External clock source

fHS E_ext
OSC_INOSC_OUT

Table 3-10 High-speed external clock generated from a crystal/ceramic resonator
SymbolParameter

FOSC_IN

Resonator frequency

RFFeedback resistance

250

kΩ

C

Recommendedload
capacitance and corresponding RS = 60Ω(1)crystal series impedance RS

20

pF

I2

HSE drive current

VDD = 3.3V，20p load

0.32

mA

gm

Oscillator transconductanceStartup

6.8

mA/V

Startup time

VDD is stable, 24M
crystal2

mstSU(HSE)

Condition

Min.

Typ.

Max.

Unit

4

24

25

MHz

Note 1: It is recommended that the ESR of 25M crystal should not exceed 60 Ω, and it can be relaxed if it islower than 25M.
Circuit reference design and requirements:
The load capacitance of the crystal is subject to the recommendation of the crystal manufacturer, generally
CL1 = CL2.
Figure 3-4 Typical circuit of external 24M crystal
CL1
OSC_IN
24MHz
CrystalOscillator
OSC_OUT
CL2

V1.3

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CH32V003 Datasheet

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3.3.6 Internal clock source characteristics
Table 3-11 Internal high-speed (HSI) RC oscillator characteristics
SymbolFHSIParameter

Condition

Min.

Typ.

Frequency (after calibration)

Max.

24

DuCyHSI

Duty cycle

45

ACCHSI

Accuracy of HSI oscillator (after TA = 0℃～70℃
calibration)
TA = -40℃～85℃

tSU(HSI)

HSI
oscillator
stabilization time

IDD(HSI)HSI oscillator power consumption

Unit
MHz

50

55

%

-1.2

1.6

%

-2.2

2.2

%

startup

10
120

us

180

270

uA

Table 3-12 Internal low-speed (LSI) RC oscillator characteristics
SymbolParameter

Condition

Min.

Typ.

Max.

Unit

FLSI

Frequency

100

128

150

KHz

DuCyLSI

Duty cycle

45

50

55

%

tSU(LSI)

LSI
oscillator
stabilization time

startup

IDD(LSI)

LSI
oscillator
consumption

power

80

us

1.5

uA

3.3.7 Wakeup time from low-power mode
Table 3-13 Wakeup time from low-power mode(1)SymbolParameter

twusleep

Wakeup from Sleep mode
Wakeup from Standby modetWUSTDBY

Condition

Typ.

Unit

Wake up using HSI RC clock

30

us

LDO stabilization time + HSI RC
clock wake up + code load time(2)(take 128K as example)

200

us

Max.

Unit

Note: The above parameters are measured parameters.

3.3.8 Memory characteristics
Table 3-14 Flash memory characteristics
SymbolParameter

ConditionMin.

tERASE_64

Typ.

Page (64 bytes) programmingtime

TA = -20℃～85℃

2.4

3.1

ms

tERASE

Page (64 bytes) erase time

TA = -20℃～85℃

2.4

3.1

ms

tprog

16-bit programming time

TA = -20℃～85℃

2.4

3.1

ms

tME

Whole chip erase time

TA = -20℃～85℃

2.4

3.1

ms

Vprog

Programming voltage

2.8

5.5

V

Max.

Unit

Table 3-15 Flash memory endurance and data retention
SymbolNEND
V1.3

Parameter
Endurance

Condition
TA = 25℃
20

Min.

Typ.

10K

80K(1)

times

CH32V003 Datasheet

tRET

http://wch.cn

Data retention

10

year

Note: The endurance parameter is actual measured, which is not guaranteed.

3.3.9 I/O port characteristics
Table 3-16 General-purpose I/O static characteristics
SymbolParameter

Condition

Min.

Typ.

Max.

Unit

Standard I/O pin, input high level
voltage

0.22*(VDD2.7)+1.55

VDD+0.3

V

FT I/O pin, input high level voltage

0.22*(VDD2.7)+1.55

5.5

VStandard I/O pin, input low-level
voltage-0.3

0.19*(VDD2.7)+0.65

V

FT I/O pin, input low-level voltage-0.3

0.19*(VDD2.7)+0.65

V

Vhys

Schmitt trigger voltage hysteresis

150

Ilkg

Input leakage current

RPU

Weak pull-up equivalent resistance

35

45

55

kΩ

RPD

Weak pull-down equivalent resistance

35

45

55

kΩ

CI/O

I/O pin capacitance

VIH

VIL

mV

Standard I/O port

1

FT I/O port

3

5

uA

pF

Output drive current characteristics
GPIO (General-Purpose Input/Output Port) can sink or output up to ±8mA current, and sink or output±20mA current (not strictly to VOL/VOH). In user applications, the total driving current of all I/O pins cannot
exceed the absolute maximum ratings given in Section 3.2:

Table 3-17 Output voltage characteristics
SymbolParameter

VOL

Output low level when 8 pins are sunk

VOH

Output high level when 8 pins are sourced

VOL

Output low level when 8 pins are sunk

VOH

Output high level when 8 pins are sourced

VOL

Output low level when 8 pins are sunk

VOH

Output high level when 8 pins are sourced

Condition
TTL port, II/O = +8mA
2.7V< VDD <5.5V
CMOS port, II/O = +8mA
2.7V< VDD <5.5V
II/O = +20mA
2.7V< VDD <5.5V

Min.

Max.
0.4

VDD-0.4
0.4
2.3
1.3
VDD-1.3

Unit
V
V
V

Note: In the above conditions, if multiple I/O pins are driven at the same time, the total current cannot exceed
the absolute maximum ratings given in Table 3.2. In addition, when multiple I/O pins are driven at the sametime, the current on the power/ground point is very large, which will cause the voltage drop to make theinternal I/O voltage not reach the power supply voltage in the table, resulting in the drive current being lessthan the nominal value.

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Table 3-18 Input/output AC characteristics
MODEx[1:0]configuration
10（2MHz）
01（10MHz）
11（30MHz）

SymbolParameter

Condition

Fmax(I/O)out

Maximum frequencytf(I/O)out

Output high to low fall timetr(I/O)out

Output low to high rise time

Fmax(I/O)out

Maximum frequencytf(I/O)out

Output high to low fall timetr(I/O)out

Output low to high rise time

Fmax(I/O)out

Maximum frequencytf(I/O)out

Min.

Max.

Unit

2

MHz

125

ns

125

ns

10

MHz

25

ns

25

ns

CL = 50pF, VDD = 2.7-5.5V

30

MHz

Output high to low fall time

CL = 50pF, VDD = 2.7-5.5V

10nstr(I/O)out

Output low to high rise time

CL = 50pF, VDD = 2.7-5.5V

10

ns

tEXTIpw

The EXTI controller detects
the pulse width of theexternal signal

CL = 50pF, VDD = 2.7-5.5V
CL = 50pF, VDD = 2.7-5.5V
CL = 50pF, VDD = 2.7-5.5V
CL = 50pF, VDD = 2.7-5.5V

10

ns

Max.

Unit

-0.3

0.28*(VDD-1.8)+0.6

V

0.41*(VDD-1.8)+1.3

VDD+0.3

V

3.3.10 NRST pin characteristics
Table 3-19 External reset pin characteristics
SymbolParameter

Condition

VIL(NRST)

NRST
voltage

input

low-level

VIH(NRST)

NRST
voltageinput

high-level

Vhys(NRST)

NRST Schmitt
voltage hysteresis

RPU(1)Min.

Trigger

Typ.

150

Weak pull-up equivalent
resistance

35

mV
45

55

kΩ

Note: 1. The pull-up resistor is a real resistor in series with a switchable PMOS implementation. The
resistance of this PMOS/NMOS switch is very small (approximately 10%).
Circuit reference design and requirements:
Figure 3-5 Typical circuit of external reset pin
VDD
NRST

RPU

0.1μF

3.3.11 TIM timer characteristics
Table 3-20 TIMx characteristics
SymbolV1.3

Parameter

Condition
22

Min.

Max.

Unit

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tres(TIM)

Timer reference clock

FEXT

Timer external clock frequency on
CH1 to CH4

ResTIM

Timer resolution

tCOUNTER

16-bit counter clock cycle when theinternal clock is selected

tMAX_COUNT

Maximum possible countfTIMxCLK = 48MHz

1

tTIMxCLK

13.9

ns

0

fTIMxCLK/2

MHz

0

36

MHz

16

位

1

65536

tTIMxCLK

0.0139

910

us

65535

tTIMxCLK

59.6

s

fTIMxCLK = 48MHz

fTIMxCLK = 48MHz
fTIMxCLK = 48MHz

3.3.12 I2C interface characteristics
Figure 3-6 I2C bus timing diagram
tw(SCKH)
tr(SCL)th(STA)

SCL

tw(SCKL)tf(SCL)tSU(SDA)tf(SDA)SDAtSU(STO)th(SDA)

Repeat start condition

tw(STO:STA)

tr(SDA)

Stop conditiontSU(STA)

Start condition

Table 3-21 I2C interface characteristics
SymbolStandard I2CParameter

Min.

Max.

Fast I2C
Min.

Max.

Unit

tw(SCKL)SCL clock low time

4.7

1.2

us

tw(SCKH)

SCL clock high time

4.0

0.6

us

tSU(SDA)SDA data setup time

250

100

ns

th(SDA)SDA data hold time

0

0

900

tr(SDA)/tr(SCL)

SDA and SCL rise time1000

tf(SDA)/tf(SCL)

SDA and SCL fall time300th(STA)

Start condition hold time

4.0

0.6

us

tSU(STA)

Repeated start condition setup time

4.7

0.6

us

tSU(STO)

Stop condition setup time

4.0

0.6

us

tw(STO:STA)

Time from stop condition to start condition(bus free)

4.7

1.2

us

Cb

V1.3

Capacitive load for each bus

400

23

20

ns
ns
ns

400

pF

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3.3.13 SPI interface characteristics
Figure 3-7 SPI timing diagram in Master modetr(SCK)tf(SCK)tSCKSCK Output
CPHA=0
CPOL=0CPHA=0
CPOL=1tw(SCKH)
tw(SCKL)SCK Output
CPHA=1
CPOL=0CPHA=1
CPOL=1tsu(MI)MISO Inputth(MI)
Input highest bit

MOSI Output

Input 6-1 bittV(MO)th(MO)

Output highest bit

Output 6-1 bit

Input lowest bit

Output lowest bit

Figure 3-8 SPI timing diagram in Slave mode (CPHA = 0)
NSS Input

SCK Input
CPHA=0
CPOL=0CPHA=0
CPOL=1tsu(NSS)ta(SO)MISO Output
tsu(SI)MOSI Input

V1.3

tV(SO)
Output highest bitth(NSS)tr(SCK)tf(SCK)tSCKth(SO)
Output 6-1 bit

tdis(SO)
Output lowest bitth(SI)
Input highest bit

Input 6-1 bit

24

Input lowest bit

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Figure 3-9 SPI timing diagram in Slave mode (CPHA = 1)
NSS Input

SCK Input
CPHA=1
CPOL=0CPHA=1
CPOL=1tsu(NSS)tV(SO)ta(SO)MISO Output

tdis(SO)th(SO)

Output highest bit

Output 6-1 bit

Output lowest
bit

Input 6-1 bit

Input lowest bitth(SI)

tsu(SI)MOSI Inputth(NSS)tr(SCK)tf(SCK)tSCK

Input highest bit

Table 3-22 SPI interface characteristics
SymbolParameter

fSCK/tSCKSPI clock frequencytr(SCK)/tf(SCK)

Max.

Unit

Master mode

24

MHz

Slave mode

24

MHz

SPI clock rise and fall time

Load capacitance:C = 30pF

20

ns

tSU(NSS)NSS setup time

Slave mode

2tPCLKnsth(NSS)NSS hold time

Slave mode

2tPCLKns

SCK high and low time

Master mode, fPCLK = 48MHz,
Prescaler factor = 2

30

Master mode

5

ns

Slave mode

5

ns

Master mode

5

ns

Slave mode4nstw(SCKH)/tw(SCKL)tSU(MI)tSU(SI)th(MI)th(SI)

Condition

Data input setup time
Data input hold time

Min.

70

ns

ta(SO)

Data output access time

Slave mode, fPCLK = 24MHz

0

1tPCLKnstdis(SO)

Data output disable time

Slave mode

0

10

ns

Slave mode (After enable edge)

5nsMaster mode (After enable edge)

5nstV(SO)tV(MO)th(SO)th(MO)

Data output valid time
Data output hold time

Slave mode (After enable edge)2ns

Master mode (After enable edge)0ns

3.3.14 10-bit ADC characteristics
Table 3-23 ADC characteristics
SymbolParameter

VDD

Supply voltage

IDD

Supply current

V1.3

Condition

Min.

Typ.

2.8
370

25

Max.

Unit

5.5

V
uA

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ADC clock frequency

VAIN

Conversion voltage range

CADC

Internal sample
capacitor

fS

1

6

VDD = 3.2 to 5.5V

1

12

VDD = 4.5 to 5.5V

1

24

VSS

VDD

hold

Sampling rate

ts
tSTAB

and

VDD = 2.8 to 5.5V

Sampling time

3
285

fADC = 6 MHz

430

fADC = 12 MHz

857

fADC = 24 MHz

1710

fADC = 4 MHz

0.75

fADC = 6 MHz

0.5

fADC = 12 MHz

0.25

KHz

us

7

Total
conversion
time(including sampling time)

tCONV

V
pF

fADC = 4 MHz

Power-on time

MHz

us

fADC = 4 MHz

3.5

us

fADC = 6 MHz

2.33

us

fADC = 12 MHz

1.17

us

-

14

1/fADC

Note: Above parameters are guaranteed by design.

Table 3-24 ADC error (fADC = 12MHz:RAIN < 10kΩ,VDD > 2.9V)(fADC = 24MHz:RAIN < 3kΩ,VDD = 5V)
SymbolET

Parameter

Condition

Min.

Typ.

Max.

Total data deviation

fADC = 12 MHz

24

fADC = 24MHz total data deviation

fADC = 24 MHz

3

6

EO

Misalignment error

fADC = 12 MHz

1

3

EG

Gain error

fADC = 12 MHz

1

2

ED

Differential nonlinearity error

fADC = 12 MHz

0.5

2

EL

Integral nonlinearity error

fADC = 12 MHz

0.6

2.5

ETF24

Unit

LSB

Note: Source simulation.
Cp represents the parasitic capacitance on the PCB and the pad (about 5pF), which may be related to thequality of the pad and PCB layout. A larger Cp value will reduce the conversion accuracy, the solution is to
reduce the fADC value.
Figure 3-10 ADC typical connection diagram
VDD
RAIN

VAIN

V1.3

Parasitic
capacitance

AINx

CP

26

VT
0.6V

Sample and hold ADC converter
RADC
10-bitconverter

VT
0.6V

CADC

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Figure 3-11 Analog power supply and decoupling circuit reference
VDD
0.1uF

VSS

3.3.15 OPA characteristics
Table 3-25 OPA characteristics
SymbolParameter

VDD

Supply voltage

CMIR

Commonvoltage

Condition

mode

input

Min.

Typ.

Max.

Unit

2.8

5.5

V

0

VDD

V

10

mV

1.5

mA

VIOFFSET

Input offset voltage

ILOAD

Drive current

IDDOPAMP

Current consumption

No load, static mode

CMRR(1)

Common
ratio

@1KHz

PSRR(1)

Power supply rejection ratio

@1KHz

88

dB

AV(1)

rejection

273

uA

81

dB

Open loop gain

CLOAD = 50pF

105

dB

(1)

Unit gain bandwidth

CLOAD = 50pF

12

MHz

(1)

GBW
PM

mode

3

Phase margin

CLOAD = 50pF

75

deg

SR(1)

Slew rate limited

CLOAD = 50pF

7.7

V/us

tWAKU(1)

Setup time from shutdown to
Input V DD /2, C LOAD =50pF,R LOAD =4kΩwake up, 0.1%

520

ns

RLOAD

Resistive load

CLOAD

Capacitive load

VOHSAT(2)Highsaturation
voltage

output RLOAD = 4kΩ, input VDD

VDD-180

RLOAD = 20kΩ, input VDD

VDD-36VOLSAT(2)Lowsaturation
voltage

output RLOAD = 4kΩ, input 0

5

RLOAD = 20kΩ, input 0

5

EN(1)

Equivalent
noise

input

4
50

83

RLOAD = 4kΩ, @10KHz

28

voltage

27

pF
mV

RLOAD = 4kΩ, @1KHz

Note: 1. Design parameters are guaranteed.
2. The load current limits the saturated output voltage.

V1.3

kΩ

mV

nv
Hz

CH32V003 Datasheet

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Chapter 4 Package and ordering information
Packages
Part No.

Package

Body size

Lead pitch

CH32V003F4P6TSSOP20

4.4*6.5mm

0.65mmCH32V003F4U6

QFN20

3.0*3.0mm

0.4mm

Quad Flat No-lead Package

Tape & Reel

CH32V003A4M6

SOP16

3.9*10mm

1.27mmSmall Outline Package

Tube

CH32V003J4M6

SOP8

3.9*5.0mm

1.27mmSmall Outline Package

Tape & Reel

Description
Thin Shrink Small Outline
Package

Packing type
Tape & Reel

Note: 1. The packing type of QFP/QFN is usually tray. Please confirm with the packaging factory for specificpart number.
2. Size of tray: The size of tray is generally a uniform size (322.6*135.9*7.62). There are differences inthe size of the restriction holes for different package types, and there are differences between different
packaging factories for tubes, please confirm with the manufacturer for details.

V1.3

28

CH32V003 Datasheet

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Note: All dimensions are in millimeters. The pin center spacing values are nominal values, with no error.
Other than that, the dimensional error is not greater than the greater of ±0.2mm or 10%.
Figure 4-1 TSSOP20 package

Figure 4-2 QFN20 package

V1.3

29

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Figure 4-3 SOP16 package

Figure 4-4 SOP8 package

V1.3

30

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Series product naming rules
Example:Device family

CH32

V

3

03

R

F = ARM-based
V = QingKe RISC-V-based
Product type
0 = QingKe V2 core
1 = M3/ QingKe V3A core, clock speed @72M
2 = M3/ QingKe V4B_C core, clock speed @144M
3 = QingKe V4F floating-point core, clock speed @144M
Device subfamily
03 = General-purpose
05 = Connectivity (USB high-speed, SDIO, dual CAN)
07 = Interconnectivity (USB high-speed, dual CAN, Ethernet, DVP, SDIO, FSMC)
08 = Wireless (BLE5.3, CAN, USB, Ethernet)
Pin countJ = 8 pins

A = 16 pins

F = 20 pins

G = 28 pins

K = 32 pins

T = 36 pins

C = 48 pins

R = 64 pins

W = 68 pins

V = 100 pins

Z = 144 pins

Flash memory size
4 = 16 Kbytes of Flash memory
6 = 32 Kbytes of Flash memory
8 = 64 Kbytes of Flash memory
B = 128 Kbytes of Flash memory
C = 256 Kbytes of Flash memory
Package
T = LQFPU = QFN

R = QSOP

P = TSSOP

M = SOP

Temperature range
6 = -40℃～85℃ (industrial-grade)
7 = -40℃～105℃ (automotive-grade 2)
3 = -40℃～125℃ (automotive-grade 1)
D = -40℃～150℃ (automotive-grade 0)

V1.3

31

8

T

6