Parameter design of a Five-Level Inverter
for PV systems
Yugo. Kashihara1, and Jun-ichi. Itoh1
1

Nagaoka University of Technology, 1603-1 Kamitomioka-cho Nagaoka City Niigata, 940-2188, Japan

Abstract-- This paper discusses the parameter design
method for an active neutral-point-clamped (ANPC)
multilevel inverter. The power losses of the ANPC inverter
are calculated by mathematical expressions and themathematical results are confirmed well agreed with theexperimental results. Furthermore, this paper also discusses
on the optimization of the switching frequency, in order toimprove the efficiency and to downsizing the capacitor
volume.
Index Terms— Active NPC, Multilevel converter,
Parameter design, PV system

I. INTRODUCTION
Applications of multilevel converters are actively
researched recently [1]-[4]. Comparing multilevel
converters to conventional 2-level converters, themultilevel converters show advantages, for example a
multilevel converter can reduce the voltage stress of aswitching device to 1/(n-1) of the DC input voltage andalso reduce the harmonic component of the output
voltage. Therefore, the multilevel converters can be usedwith high speed and low voltage rating switching devices.
Furthermore, the multilevel converters have possiblilty toobtain higher efficiency than the conventional converters
because a low voltage drop device can be used.
In general, the multilevel converters are applied in thefield of medium voltage application such as the power
converter for high power motor driving and also thepower transmission line. Recently, the low voltage
applications are also being studied to use with multilevel
converters for higher efficiency such as the power
converter for photo voltaic cells (PVs) [5].
There are two conventional multilevel topologies; theneutral point clamped (NPC) type and the flying
capacitor (FC) type [6] [7]. NPC type outputs the voltage
level based on from the neutral point voltage clamped byusing diodes. However the number of switching devices
increases in proportional to the voltage level. FC typeoutputs the voltage level based on the DC link voltage byadding flying capacitor voltage. However, FC type needs
more capacitors as the voltage level increased.
An active neutral point clamped (ANPC) which is oneof the multilevel topology has been proposed in Refs. [8][11]. The ANPC type is a new topology that combines the
NPC and FC type into one converter. Compared to theconventional NPC and FC type converters, the ANPC
type can reduce the number of devices, as a result, ANPC
type is lower cost and higher efficiency than theconventional NPC and FC type.
Selection criteria of switching devices for the multi-

level converter are necessary in order to obtain higher
efficiency than the two-level inverter in PV applications.
Loss analysis by using the simulator is a simple method
to study the losses among the multilevel converter
topologies under a same device specification. However
the loss estimation by simulation is not useful method tofind the optimized circuit parameter because hundreds ofsimulations are required to conduct under different
conditions. On the other hand, loss analysis bymathematical can calculate the power loss depending on
the device parameters and circuit structure. Thus, it ispossible to study about optimum design for a five-level
ANPC converter which satisfies the specifications interms of the volume, efficiency and power density.
This paper establishes mathematical expressions toestimate the power loss and also discusses the capacitor
designing method for a five-level ANPC inverter for PV
systems. The point of the mathematical expression is toobserve the losses of a converter based on the study of thedevice condition. Selection of the capacitor is alsomentioned based upon the design method. The validity ofthe proposed calculation results is confirmed with theexperimental results.
II. FIVE-LEVEL ACTIVE NPC INVERTER TOPOLOGY
A. ANPC circuit
Figure 1 shows the single leg diagram of a five-level
ANPC inverter, which is constructed by eight switches
and three capacitors. The switching operation of theswitching devices of the five-level ANPC inverter isdifferent at Cell1 and Cell2. The switching devices of theCell1 are operated at switching frequency of 20 kHz. The
switching devices of the Cell2 are operated at output
frequency. There are three capacitors in the five-level
ANPC inverter. The capacitor C1 is operated as the flying
capacitor. The capacitors C2 and C3 are operated as theDC smoothing capacitor. The quarter voltage of the input
voltage is clamped by the flying capacitor C1. The half
voltage of the input voltage is clamped by the DCsmoothing capacitors C1 and C2.
The ANPC converter has two advantages; first, the
ANPC inverter is able to obtain high efficiency. This isdue to the low switching loss because there are two
switching frequencies in an ANPC converter. In theconventional multi-level converter topology, theswitching frequency of all the switching devices is sameto the carrier frequency, on the other hand, in an ANPC,
the switching frequency of the Cell2 switching device in
Fig.1 is same to the output frequency (50Hz) and only

Cell1 switching devices use the carrier frequency. As aresult, the switching loss is greatly reduced. It should be
noted that the voltage rating equals to half of the DC link
voltage is required for the switching devices in Cell2.
The second advantage is the ANPC converter can control
over the flying capacitor voltage C1 and therefore a
voltage balance circuit is not necessary, then, the size ofthe circuit is compact and small.
Figure 2 shows the positive current pathway of the
ANPC converter. Table 1 shows the switching pattern of
the five-level ANPC converter and the flying capacitor
voltage. The five-level ANPC inverter outputs five kindof voltage levels which are –1/2Edc, –1/4Edc, 0, +1/4Edc,
and +1/4Edc. The five kind of voltage levels are given bysumming the flying capacitor voltage and the DCsmoothing capacitor voltage. There are eight switchingpattern in the five-level ANPC inverter. When theswitching pattern is +1/4Edc or -1/4Edc, the flying
capacitor is in charge mode or discharge mode.

Fig.1. Single phase 5-level ANPC inverter circuit topology.

B. Control strategy
Figure 3 shows the gate signal waveform of the fivelevel ANPC inverter. The gate signals of Cell1 switches
are generated by phase shift carrier-based PWM strategy.
These gate signals are generated by comparing to the
output voltage command with two carriers which thephase is reversed to each other. The duty ratio command
Dref for Cell1 is given by;Dref = 2a sin θ − 1(0 ≤ θ ≤ π ) .................................... (1),

D ref = 2 a sin θ + 1(π ≤ θ ≤ 2π ) ................................ (2),

(a)

(b)

where a is the modulation index and θ is the reference
phase angle.
When the polarity of the output voltage command ispositive, the gate signals of S5 and S7 are turned on.
When the polarity of voltage command is negative, thegate signals of S6 and S8 are turned on. This control
method can balance the flying capacitor voltage
automatically, by choosing the discharge and charge
modes according to the cycle of carrier frequency.
III. CALCULATION METHOD OF SEMICONDUCTOR LOSS
This chapter explains the power loss expression of the
five-level ANPC inverter. The ANPC inverter isassumed to operate in an ideal state. The power loss of
the ANPC inverter is calculated under two ideal
conditions, that is no load ripple current and no voltage
ripple of capacitors. Then, the power loss of the ANPC
inverter is given by
PLoss = PCell 1 + PCell 2 + PFC + C DCSC ............................ (3),where PLoss is the total loss (W) and PCell1 is the Cell1
loss (W) and PCell2 is the Cell2 loss (W) and PFC is theflying capacitor loss (W) and PDCSC is the DC smoothing
capacitor loss (W). Furthermore, the power loss consistsof the switching loss and the conduction loss, which are
generated at turn on and off, from the forward voltage
drop of a switching device, respectively.
A. Power loss of Cell1
1) Conduction loss(c)(d)
Fig.2. Current pathway of 5-level ANPC inverter circuit topology.
TABLE I
Switching pattern and flying capacitor voltage.

The conduction loss is separated into two, namely
switch side loss and FWD side loss. We assume that thepositive current flows through the switch side and thenegative current flows through the FWD side. In addition,
if the switching device of the ANPC converter is
MOSFET, on-resistance is low, positive current andnegative current flow through the switch side due to low
on-resistance. The average value of the conduction loss iscalculated from the on-voltage and the switch current andthe duty ratio command Dref which can be given by
1 π −φvon i sw1 dx .............................................. (4),2π ∫φv on = ron I + v 0 ............................................................... (5),PSwitch =1
isw1 = I m sin (θ + φ ) 1 + Dref  ................................... (6),
2


(

)

where von is the on-voltage, ron is the on-resistance (Ω),
I is the current flows through the switch (A), v0 is thedrop voltage (V) when I equals to approximately 0 A, Im
is the peak phase current, a is the modulation index, φ isthe power factor.
The on-voltage is supposed use of the IGBT. The onvoltage occurs in the switching device from on-resistanceand p-n junction, which is expressed in the equation (5).
On the other hand, if the switching device of the ANPC
converter is MOSFET, v0=0 in the equation (5).
The conventional loss Pon_sw1 in the switch side areexpressed in the equation (7) from the equation (4), (5),
(6).
1
1
v
POn _ sw1 = I m  0 − v0 cos φ +I m ron sin 2φ8π
 2π 2..... (7)1
2
1
−I m ronφ −I m aron cos φ − av0 cos φ 
4π
3π
4


On the other hand, the conventional loss Pon_FWD1 inthe switch side are given by1
1
v
POn _ FWD1 = I m  0 + v0 cos φ +I m ron sin 2φ8π
 2π 2
1
1
2+
I m ron +I m ronφ −I m aron cos φ .. (8).
4π
4π
3π
1

− av0 cos φ 42) Switching loss
We assume that the switching loss of the switches inCell1 is proportional to the applied voltage and current
Therefore, the switching loss of the Cell1 depends on thecurrent flows through the switches and the number ofswitching. The Cell1 switching loss Psw1 is given by
Psw1 =()

1 E dc I m
eon + eoff f c .................................... (9),4π E dcd I md

where Edc is the input voltage (V), eon is the turn-on
energy (J) per switching at datasheet, eoff is the turn-off
energy (J) per switching at datasheet, Edcd is the voltage(V) at the measurement condition of switching loss atdatasheet, Imd is the current (A) at the measurement
condition of switching loss at datasheet and fc is thecarrier frequency (Hz). The recovery loss PRec1 in Cell1 isgiven byFig.3. Gate signals.

1 E dc I m
PRe c =
err f c ............................................. (10),4π E dcd I md
where err is the recovery energy (J) from per switching at
datasheet.

B. Power Loss of Cell2
1) Conduction Loss
The conduction loss in Cell2 is obtained by the samethe formula that is used to calculate the conduction loss in
Cell1. However, the current flow through the Cell2
switches is different from the Cell1 because of thefollowing two conditions, S5 and S7 are turn-on when the
output voltage command is positive and S6 and S8 areturn-on when the output voltage command is negative.
isw2A is the switch current flows to S5 and S7 and isw2B isthe switch current flows to S5 and S7, which are given by1
i sw1 = I m sin(θ − φ ) 1 + Dref  (0 < θ < π )i sw2 A = 
(11),
2

0
(
π
<
θ
<
2
π
)


(

)

(0 < θ < π )0
i sw2 B = 
(12).
1

i sw1 = I m sin (θ − φ ) 2 1 + Dref  (π < θ < 2π )




(

)

Therefore, the conduction loss Pon_sw2A is calculated bysubstituting equation (11) into equation (4). Pon_sw2A isgiven by
POn _ sw 2 A =1  12
1 2
aron  cos 2φ + cos φ +  I m
2π   6
3
2

1
1
1

+ av0  π cos φ − sin φ + φ cos φ 
2
2
2


........ (13).

The conduction loss of the FWD side of S5 and S7 aregiven by4
1  
φ 
 I m a 8I m ron sin  − 3v0 sin φ
12π  ..... (14).
2+ 3φv0 cos φ )]POn _ FWD 2 A =Likewise, the conduction loss for the switch side of theS6 and S8 is given by (15) and the conduction loss for the
FWD side of the S6 and S8 is given by (16)1
[I m v 0 (cos φ + 1)
Pon _ sw2 B =2ππ φ 1+ I m r  + − sin 2φ 2 2 4


Pon _ FWD 2 B =. (15),

1  2 φ 1

 I m r  − sin 2φ  − I m v0
2π 
2 4


1
I m av0 (sin φ − φ cos φ ) ......... (16).
2
2
1 
1
2
+ I m ar  cos 2φ − cos φ +  
3
2 
6

+ I m v0 cos φ −2) Switching loss
The switching loss in the Cell2 is depending on the
output frequency (50Hz). As a result, the switching loss
in the Cell2 is lower than the switching loss in the Cell1,
which is nearly equal to zero and therefore the switchingloss can be disregarded.

I m sin (θ + φ )I T
Tch arg e = m k ......................... (20),
C FC
C FC

where k is the voltage time product coefficient given
by
k=

2

1
1
π

− I m av 0  cos φ − sin φ + φ cos φ 
2
2
2


2
1 
1
+ I m ar  cos 2φ + cos φ + 
3
2 
6

∆V FC =

 2V2Vmsin θ sin (θ + φ )  m sin θ < 0.5  ................ (21),E dc
 E dck = sin (θ + φ ) −

 2V

2Vm
sin θ sin (θ + φ )  m sin θ ≥ 0.5  (22).
E dc
E
 dc


k is a non-dimensional coefficient i.e. k does notdepends on power capacity, output voltage and output
current. The value of the ripple current will change
depending on the following factors; reference phase angle,
the power factor, modulation index (2Vm/Edc) and others.
Figure 4 shows the relationship between the phase andvoltage coefficient k. The maximum value of the voltage
coefficient is calculated from figure 4. At first,
modulation index a is defined bya=2Vm.................................................................... (23).
E dc

The output phase and the voltage coefficient arechanged by the modulation index. The maximum value
kmax of the voltage coefficient is given by
kmax =

2Vm
Edc(0 < a < 0.5) .......................................... (24)

IV. PARAMETER DESIGN OF THE CAPACITORSA. Flying capacitor
1) Design of the capacity
This chapter explains the parameter design of thecapacitors using phase shift carrier-based PWM strategy.
The summation of the current flows through the flying
capacitor becomes zero at per switching cycle with phaseshift carrier-based PWM strategy. Therefore, the voltage
time product of the charging time and the discharging
time is same. Thus, the charging time is discussed to
calculate ripple voltage of the flying capacitor.
At first, the charging time Tcharge of the flying capacitor
is discussed. When the duty ratio command Dref ispositive, the switching pattern of the charging mode is No
2 in the table 1. Thus, the period S2 S3 turn on becomes
Tcharge is given by
Tch arg e =2Vm
T sin θE dc

Fig.4. Relationship of output phase and voltage coefficient k.

 2Vm



 E sin θ < 0.5  ................... (17),
 dc


 2V
  2V
Tch arg e = T 1 − m sin θ   m sin θ ≥ 0.5  ............ (18),EEdc
  dcwhere T is the carrier cycle (sec) and Vm is the
maximum output voltage (V). Relationship between the
ripple voltage ∆Vc of the flying capacitor and current at
minute time ∆Τ is given by∆Vc =I∆T .............................................................. (19).
C

If we calculate the product of time and current, ripple
voltage is given by equation (19). Thus, the voltage ripple∆VFC is charged by the flying capacitor at charging mode.
Therefore, ∆VFC is given by equation (20) from equation(17) and (18).

Fig.5. Current coefficient of flying capacitor.

k max =E dc
8Vm(0.5 ≤ a ≤ 1) ........................................... (25)

The application of the ANPC converter in this paper
assumes a PV system. Thus, the modulation index a isdesigned as larger than 0.5 in terms of the voltage
utilization. The voltage ripple ∆VFC and the capacity CFCof the flying capacitor are given by∆V FC =C FC =

I m T E dc..................................................... (26),
8C FC VmI m T E dc..................................................... (27).
8∆V FC Vm

2) Calculation method of the flying capacitor loss
The conduction loss PFC occurs in the flying capacitor
from equivalent series resistance (ESR) [12]. The
conduction loss PFC is given by2

PFC = I rms _ FC RFC ...................................................... (28),where Irms_FC is the rms value of the flying capacitor
current (A) and RFC is the ESR value of the flying
capacitor (Ω). The ripple current of the capacitors arelimited as a permitted value in terms of the lifetime of thecapacitor. Thus, Irms_FC is important factor for capacitor
selection. The rms value of the ripple current at switchingfrequency is nonlinear value. Therefore, the calculation as
for a general solution is difficult and the complexity isimpractical. The current of the flying capacitor is afunction for the output power factor and modulationindex. These values are also non-dimensional. The rms
value of the flying capacitor value is given by equation(29) using the flying capacitor current coefficient Kfc. The
flying capacitor current coefficient Kfc is calculated fromthe normalized simulation.

that flows through the neutral point from U phase is given
by equation (32). In addition, other phase currents are
given by equation (33) and equation (34).
I dc1 =Pout1
V
= m I m {cos φ − cos(2θ + φ )} ............... (32)
E dc 2 E dc

I dc 2 =


 

Vm
2 
I m cos φ − cos 2θ − π  + φ  ............. (33)
E dc 
3 
 


I dc 3 =


 

Vm
4 
I m cos φ − cos 2θ − π  + φ  ............. (34)
E dc 
3 
 


The injected current to the DC neutral point iscalculated by the sum among equation (32), equation(33) and equation (34). However, the injected current to
the DC neutral point changes the current direction basedon the pole of the output voltage. The injected current to
the DC neutral point can be expressed by signum
function is shown as 
2 
I dcn = sign(sin θ )I dc1 + sign sinθ − π   I dc 2
3 
 
 
4 
+ sign sinθ − π   I dc 3
3 
 

Equation (36) and equation (40) are calculated bysubstituting equation (35) into equation (32) and equation(33) and equation (34), respectively.
I dcn =Vm
I m k i ........................................................... (36)E dc

k i = sign(sin θ )(cos φ − cos(2θ + φ )) 
2 + sign sin θ − π  (cos φ
3 
 

 

2 
− cos 2θ − π  + φ  

3 
 
  ............ (37)

I rms _ FC = K cf I m .......................................................... (29)Figure 5 shows the conversion of the flying capacitor
current coefficient Kfc. Kfc is defined by the output phasefactor and modulation index. The maximum value of KCF
is 0.65 when the modulation index in figure 5 is 0.5 to 0.6.
The ESR Rfc of the flying capacitor is given bytan δ 1R FC =..................................................... (30),2πfC FC F fn
where tanδ is the tangent of loss angle. Tanδ in theequation (30) is the normalized value at 120Hz. Thus,
Irms_FC and RFC at the switching frequency are calculatedby the using frequency correction coefficient Ffn.
B. DC smoothing capacitor
1) Design of the capacity
The ANPC converter is connected with DC smoothing
capacitors C2 and C3 at the DC link, because the ANPC
converter uses DC neutral voltage to output multiple levelof the voltage. The DC smoothing capacitor is designedby the fluctuation of the neutral voltage. When the output
voltage is positive, the output power of per phase Pout1 isgiven by
Pout1 =

1
{Vm I m cos φ − cos(2θ + φ )} ............................. (31)2

When the duty ratio command is positive at single
phase half bridge topology, the output power Pout1 isapplied from the upper side capacitor. Thus, the current........... (35)

 
4 
+ sign sin θ − π  (cos φ
3 
 
 

4 
− cos 2θ − π  + φ  

3 
 


ki is a non-dimensional value which is dominated bypower factor φ and the output phase θ.
Figure 6 shows the relationship between the angle ofinverter output and the current coefficient. ki changes
pole at every 60 degree.
The neutral point current is calculated from θ=0 toθ=π/3. At first, the signum functions for all the neutral
point current are given bysign (sin θ ) = 1 ........................................................... (38),

 
2 
sign sinθ − π   = −1 ........................................... (39),
3 
 
 
4 
sign sinθ − π   = 1 ............................................. (40).
3 
 

The neutral point current of the area from θ=0 degree
to θ= π/3 is given by

V
π 

I dcn = m I m 1 − 2 sin 2θ +  .............................. (41)
E dc





6 

The ripple current becomes maximum at θ= π/6 which
is given byVm
I m .............................................................. (42)E dc

I dcn =The DC smoothing capacitor becomes parallel
connection from the neutral point.
The voltage fluctuation is given byvcn =1
I dcn dt ................................................... (43)2C DCSC ∫The maximum value of the ripple voltage of the DCsmoothing capacitor can be found from the definite
integration between θ=0 to θ=π/3. Thus, the maximum
value of the ripple voltage of the DC smoothing capacitor
is given by equation (44). In addition, the capacity CDCSC
of the DC smoothing capacitor is given by equation (45).
∆v cn =VmπI m  3 −  ............................... (44)2ωC DCSC E dc 3C DCSC =Vmπ
I m  3 −  ............................... (45)2ω∆v cn E dc 32) Calculation loss of the DC smoothing capacitor
The calculation for the DC smoothing capacitor loss isobtained by the same formula that is used to calculate theflying capacitor loss. The DC smoothing capacitor loss isgiven by
2

PDCSC = I rms _ CDSC RDCSC ............................................. (46),Figure 9 shows the switching loss analysis of the fivelevel ANPC inverter based on the theoretical calculation.
In the five-level ANPC inverter, the major loss isdominant by the conduction loss. In order to achieve highefficiency, the switching devices which are featuring thelow on-resistance or low on-voltage are selected. In thedevices selection, focus should be on the conduction loss,
because the switching loss in the Cell2 is very low. Notethat there is tread off between the switching speed andon-resistance in a power device. That is, the switching
device in the Cell 2 should be designed as low onresistance even the switching speed becomes slow.
B. Experimental result
Figure 10 shows the operation waveforms for the fivelevel ANPC inverter. Table 1 shows the device
parameters of the five-level ANPC inverter. The input
voltage is 283 V, the output voltage is 141 V, 50 Hz, theoutput power is 1 kW (rating), the flying capacitor
voltage command is set to 70V and the carrier frequency
is 10 kHz. The output current shows a sinusoidal
waveform without distortion. In addition, the flying
capacitor voltage agrees with the voltage command,
which is approximately 70 V. Furthermore, a five-step
waveform is shown at the output voltage of the ANPC
inverter. The cause of the surge voltage which occurs at
the zero cross is because of the switching time of theI rms _ CDSC = K cdc I m ...................................................... (47),
R DCSC =tan δ1.............................................. (48),2πfC DCSC F fn

where Irms_CDSC is the rms value of the ripple current
flows through the DC smoothing capacitor (A) and RCDC
is the ESR of the DC smoothing capacitor (Ω) and KCDC
is the DC capacitor current coefficient Kcdc.
Figure 7 shows the current coefficient of the DCsmoothing capacitor. Kcdc is calculated by normalized
simulation. Figure 7 indicates that the maximum value of
Kcdc becomes 0.46 at a=0.6. In addition, the main
component of the DC smoothing capacitor is theswitching frequency component and the triple componentof output frequency. When the power factor is 1, the rms
value Irms_CDSC of the ripple current flows through the DCsmoothing capacitor can be expressed by equation (47).
In addition, the rms value Irms_CDSC3rd of the triplecomponent of output frequency is given by
I rms _ CDSC 3rd =1
2 2

Fig.6 Relationship of angle of inverter output and current coefficient.

aI m ............................................... (49)

V. EXPERIMENTAL VERIFICATION
A. Loss analysis
Figure 8 shows the loss analysis of the five-level
ANPC inverter based on the theoretical calculation andexperimental results. The error rate between thetheoretical value and experimental value is 2 % at rated
load. The causes of the error at light load are affected by
the current from the floating capacitance and the chargedischarge current flows through the source to drain
capacitance of the switching devices.

Fig.7. Current coefficient of DC smoothing capacitor.

switching device in the Cell1 is slower than the switchingtime of the pole of output voltage in the Cell2.
Figure 11 shows the voltage and ripple voltage
waveforms of the capacitors for the five-level ANPC
inverter. The ripple voltage of the capacitors was
designed to be lesser than 10%. The design values areshown as the dotted lines in the Figure 3. The ripple
voltage of the DC smoothing capacitor is 9V (6.4%). The
ripple voltage of the flying capacitor is 6.8V (9.8%).
Figure 12 shows the efficiency of the five-level ANPC
inverter. The maximum efficiency is 98.9% at a 0.6 kW
load. The Five-level ANPC inverter can obtain efficiencyof over 98% in wide load conditions.

ANPC inverter loss is analyzed by the mathematicalexpressions and experimental results. The error rate
between the theoretical value and experimental value is
2 % at the rated load. The ripple voltage of the capacitors
was designed to be lesser than 10%. The ripple voltage of
the DC smoothing capacitor is 9V (6.4%). The ripple
voltage of the flying capacitor is 6.8V (9.8%).
In future works, the maximum power density of the
ANPC inverter will be discussed.

VI. CONCLUSIONSThis paper established mathematical expressions toestimate the power loss and also a capacitor designing
method for a five-level ANPC inverter. The five-level(a)Voltage waveform of the capacitors.

Fig.8 Loss of the ANPC inverter.

Fig.9. Loss analysis.

(b) Ripple voltage of the DC smoothing capacitor

Fig.10. Experimental waveform of the ANPC inverter.

(c)Ripple voltage of the flying capacitor.
Fig.11. Experimental waveform of the capacitors.

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Fig.12. Efficiency of the ANPC inverter (Experimental results).
Table 2 Experimental parameters.
(a) Circuit parameters.

(b) MOSFET parameter1 (S1-S4).

(c) MOSFET parameter2 (S5-S8).

(d) Capacitor parameter (C1-C3).

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