Power Losses of Multilevel Converters in Termsof the Number of the Output Voltage Levels
Yugo Kashihara

Jum-ichi Itoh

Energy and Environmental Science
Nagaoka University of Technology
Nagaoka, Niigata, Japankasihara@stn.nagaokaut.ac.jp

Electrical Engineering
Nagaoka University of Technology
Nagaoka, Niigata, Japan
itoh@vos.nagaokaut.ac.jp

Abstract— This paper presents loss calculation methodsof which the multilevel converters have several number ofthe output voltage level. The multilevel converters of theflying capacitor topology and the active neutral point clamp
topology are evaluated in terms of the high efficiency in thispaper. In addition, the power losses of the multilevel
converters are discussed using two power devices. As aresult, in case of the MOSFET device, the active neuralpoint clamp topology is better than the flying capacitor
topology, regardless of the number of level. The power lossof the two-level inverter is lower than other topologies.
Keywords— Inverter, Multilevel converter, Power loss,
Photo voltaic.

I.

INTRODUCTION

In terms of system integration on power electronics
system, it is important to choose suitable circuit topology
according to the purpose of the system. Multilevel
converters are one of the good options in order to obtainhigh efficiency. In general, multilevel converters areapplied in medium-voltage applications, such as large
power motor drives and 6.6-kVA power transmission
lines because by comparing between the multilevel
converters and the conventional two-level converters, themultilevel converter can reduce the voltage stress of aswitching device to 1/(n-1) of the DC input voltage andalso reduce the harmonic component of the output
voltage. Hence, applications of multilevel converters
have been actively investigated [1-5].
However, in order to achieve high efficiency using
low conduction loss devices such as MOSFETs and size
reduction of the output filter, the multilevel converters
have been applied in low-voltage applications, such as
uninterrupted power supplies (UPSs) and power
converters for photo voltaic cells (PVs) [6].
In order to achieve high efficiency when multilevel
converter is concerned, this factor need to be consideredseriously, i.e., the suitable circuit topologies selection andthe number of output voltage level. Although there aremany topologies for multilevel converters, however ingeneral, this converter can be categorized into separated
two topologies, which are the diode clamp (DCLMP)
topology and the flying capacitor (FC) topology [1], [2].
Besides that, these two topologies have shared the same
waveforms at the same levels. Thus, it is difficult toselect the circuit topology in the multilevel topologies. In
addition, the number of the voltage levels of multilevel
converter is decided depending on the application.
Numbers of studies have demonstrated the power
losses of a multilevel converter in terms of number of theoutput voltage level [7], [8]. Those studies analyzed thepower losses of the multilevel converters using
mathematical expression. This method calculates thepower loss depending on the device parameters and thecircuit structure only. Thus, it is possible to design themultilevel converters depending on the application interms of some parameters such as efficiency, volume,
cooling performance, cost, reliability and so on.
However, previous studies did not evaluate and compare
power losses of the multilevel converter topologies interms of number of the output voltage levels.
This paper presents several numbers of loss
calculation methods with regard to the type of themultilevel converters, and regardless of the number oflevel. In addition, the power losses of the multilevel
converters are discussed using two kinds of the powerdevices which are MOSFET and IGBT. Thus, the best
topology and output voltage level of the multilevel
converter can be selected based on its application. First,
the loss calculation methods of the FC topology and theactive neural point clamp (ANPC) topology are discussed[1], [3] because these topologies do not require thevoltage balance circuit at DC link capacitor. In addition,
the power losses of the two multilevel topologies using
two power devices are discussed. The power losses of thetwo multilevel topologies using MOSFETs from threelevel to eleven-level of output voltage levels arecalculated based on the mathematical expression. On theother hand, the power losses of the two multilevel
topologies using IGBTs from two-level to five-level of
output voltage levels are calculated. In addition, power
losses of the conventional two-level inverter and thediode clamp (DCLMP) topology are also discussed withsimulation results in the case of IGBT. Finally, power
loss characteristics are compared in terms of the numbersof the output voltage level. From the point of efficiency,
in the case of MOSFET, the ANPC topology shows
better results than other types of multilevel converters,
regardless of the number of level. On the other hand, inthe case of IGBT, the two-level converter shows the best
result compared to other types of multilevel converters,
regardless of the number of level.

II.

MULTILEVEL CONVERTER TOPOLOGYA.

Flying capacitor topology
Figure 1 shows the single phase generalized FC
topology [1]. The number of the flying capacitors andswitches in the generalized FC topology increases inproportion to the number of levels. Outputs step
waveform of FC topology is sum of the voltages of theflying capacitor and DC smoothing capacitor.
B.

Active neutral point clamp topology
Figure 2 shows the single phase generalized ANPC
topology. The ANPC topology combines the DC and FC
topologies into one converter. Due to switching devicesof the ANPC topology has two switching frequencies, the
ANPC topology can be separated into two cells as shownin the Figure 2. Switching frequency of the Cell 1
switches is the carrier frequency. On the other hand,switching frequency of the Cell 2 switches is same to the
output frequency. Thus, switching loss of the Cell 2
switches is low. In addition, circuit structure of the Cell 1
is similar to FC topology. Thus, number of the flying
capacitors in the Cell 1 increases in proportion to thenumber of levels. On the other hand, number of thesemiconductors in the Cell 2 increases in proportion to
the number of levels. However, in the Cell 2, a highvoltage rating device can be used instead of many low
voltage rating devices.

Fig.1. Single phase generalized flying capacitor converter.

III.
CALCULATION METHODS OF THE TWO
GENERALIZED MULTILEVEL CONVERTER TOPOLOGIES
These multilevel converter topologies are assumed to
be operated under ideal condition. The power losses arecalculated under ideal condition, i.e., no current andvoltage ripples in the capacitors. The voltage fluctuationin the flying capacitor occurs only during the switchingcycle. In addition, the applied voltage of the switches
fluctuates during the switching cycle. However, there are
two switches that apply low voltage and high voltage forthe same switching pattern. Thus, the power loss byvoltage ripple is counterbalanced.
Semiconductor loss is separated into the switch-side
loss and the FWD-side loss [6]. The power losses of theswitch-side Psw and the FWD-side PD are given by
Psw = Pcon _ sw + Pswitch + Pnl _ sw , .............................................. (1)PD = Pcon _ D + Prec + Pnl _ D , ................................................ (2)where Pcon_sw is the conduction loss of the switch-side,
Pswitch is the switching loss, Pnl_sw is the no-load loss,
Pcon_D is the conduction loss of the FWD-side, Prec is therecovery loss, and Pnl_D is the no-load loss of the FWDside.
The conduction loss is separated into the switch-side
loss and the FWD-side loss. In addition, if the switchingFig.2. Single phase generalized active neutral point clamp converter.

device of the two-level converter is a MOSFET, both thepositive and negative currents will flow into the switch
side due to low on-resistance. We assume that positive
current flows into the switch-side and negative current
flows into the FWD-side. The conduction losses of theswitch-side and the FWD-side are calculated from onvoltage of the semiconductor and switch current. Thus,
conduction loss of the semiconductor Pcon is given by
PCon =1 β
von i sw dx , ...................................................... (3)2π ∫αvon = ron i sw + v0 ,............................................................ (4)isw = λI m sin (θ + φ ) , ....................................................... (5)where von is the on-voltage, isw is the switch current, αand β are phase angle during current flowing, ron is theon-resistance, v0 is the on-state voltage when Imsinθ
equals to approximately 0 A, λ is the duty ratio command,θ is the power factor, and φ is the phase angle.
Using switching characteristics from a data sheet, theswitching loss and recovery loss are given by
Edc(eon + eoff ) f c 1 ∫xy iout dθ , ....................................... (6)
n −1
2π
E
1 y
Prec = dc (erec ) f cidθ , ............................................... (7)
out
n −1
2π ∫x
Pswitch =where Edc is the input voltage, eon is the turn-on energy
per switching from datasheet, eoff is the turn-off energy
from switching at datasheet, Iout is the output current, fc isthe carrier frequency, n is output voltage level, x and y
are the phase angles while the current is passed, erec is therecovery energy per switching from datasheet.
The no-load loss occurs as a result of the parasitic
capacitance of switching devices. When an input voltage
is applied to the switching devices, the parasitic
capacitance of the drain-source of the switching device
charges the voltage in the MOSFET. The parasitic
capacitance for the IGBT is on the collector-emitter ofthe switching device. When the voltage of the floating
capacitor is discharged, the no-load loss occurs at the on
resistance of the switching device. The no-load loss isgiven by1
2
Pnloss = C p ΔVsw f c , ........................................... (8)2where Cp is the parasitic capacitance of the switching
device, and ΔVsw is the applied voltage of the switching
device.
A.

Power loss of the generalized FC topology
This section explains the power loss expression of thegeneralized FC topology. The switching pulse pattern of
all switches in the FC topology is same. Thus,
semiconductor loss per one switch is same.
The conduction loss PFC_con_sw on the switch-side andconduction loss PFC_con_FWD on the FWD-side can begiven by
⎛1 1
⎞
⎛ 1 1
⎞
2
+ a cos φ ⎟v0 I m ,.............. (9)PFC _ con _ sw = ⎜ +a cos φ ⎟ron I m + ⎜⎝ 8 3π⎠⎝ 2π 8
⎠
⎛1 1
⎞
⎛ 1 1
⎞
2
− a cos φ ⎟v 0 I m . ....... (10)PFC _ con _ FWD = ⎜ −a cos φ ⎟ ron I m + ⎜⎝ 8 3π⎠⎝ 2π 8⎠Therefore, the switching loss depends on the current
flows through the switches and the number of switches.
The switching loss PFC_sw is given by
PFC _ sw =1

Edc I m1

Edc I m(e + e ) f(n −1)π Edcd I md on off c . ....................................... (11)
In addition, the recovery loss PFC_rec is given by
PFC _ rec =(n −1)π Edcd I md rr c ................................................. (12)Finally, the no-load loss PFC_nl is given bye f

2

1 ⎡ E ⎤ f
PFC _ nl = C p ⎢ dc ⎥ c . .................................................... (13)2 ⎣ (n − 1)⎦ 2

Thus, total semiconductor loss per one switch in the nlevel FC topology is given by
PFC _ Loss _ semi = 2(n − 1)(PFC _ con _ Sw + PFC _ con _ FWD + PFC _ switch + PFC _ rec + PFC _ nl ) .
..................................................................................... (14)B.

Power loss of the generalized ANPC topology
This section explains the power loss expression of thegeneralized ANPC topology (Figure 2). The conduction
loss PANPC_con_Cell1_sw on the switch side can be given by1 ⎛ ⎡11
4⎤
2⎜ sin 2φ − φ + a cosφ ⎥ron I m
2π ⎜⎝ ⎢⎣ 4
2
3⎦

PANPC _ con _ Cell1 _ sw =

⎞
⎡ ⎛π
⎤
⎞
+ ⎢1 + ⎜ a − 1⎟ cosφ ⎥v0 I m ⎟⎟
⎠
⎣ ⎝2
⎦
⎠

...............(15)On the other hand, the conduction
PANPC_con_Cell1_FWD on the switch side is given by
PANPC _ con _ Cell1 _ FWD =1 ⎛⎡ 114π⎤2⎜ − sin 2φ + φ − a cos φ + ⎥ ron I m
2π ⎜⎝ ⎢⎣ 4
2
3
2⎦

⎞
⎡ ⎛ π ⎞⎤
+ ⎢1 + ⎜1 − a ⎟ cosφ ⎥ v0 I m ⎟⎟⎣ ⎝ 2 ⎠⎦⎠loss

. ...(16)The conduction loss in Cell2 is obtained by the same
formula that is used to calculate the conduction loss inCell 1. However, the current that flows into the Cell 2
switches is different from the current that flows into the
Cell 1 switches because Sn and Sn+2 are turned on when
the output voltage command is positive and Sn+1 and Sn+3
are turned on when the output voltage command isnegative.
Therefore, the conduction loss PANPC_con_Cell2_swA for theswitch side of Sn and Sn+3 is given by
PANPC _ con _ Cell 2 _ swA =a ⎡⎛ 12
1⎞
2⎜ cos 2φ + cos φ + ⎟ron I m
2π ⎢⎣⎝ 632⎠

1⎤+ (− sin φ + (π + φ )cos φ ) v0 I m ⎥2⎦. .................(17)The conduction loss PANPC_con_Cell2_FWDA for the FWD
side of Sn and Sn+3 is given by
PANPC _ con _ Cell 2 _ FWDA =

4
⎤
a ⎡
⎛φ ⎞
2
⎢8 sin ⎜ ⎟ ron I m + 3(− sin φ + φ cos φ )v0 I m ⎥12π ⎣⎢⎝2⎠⎦⎥.

.....................................................................................(18)

Likewise, the conduction loss for the switch side of
Sn+1 and Sn+2 is given by
PANPC _ con _ Cell 2 _ swB =2
1 ⎞⎤1 ⎡⎡⎛ π φ 1⎞ ⎛12⎢ ⎜ + − sin 2φ ⎟ + a⎜ cos 2φ + cosφ + ⎟⎥ ron I m
32 ⎠⎦2π ⎣⎢⎣⎝ 2 2 4
⎠ ⎝6

⎤
⎡
1
1
⎛π
⎞⎤
+ ⎢(cosφ + 1) − a⎜ cosφ − sin φ + φ cosφ ⎟⎥ v0 I m ⎥
2
2
⎝2
⎠⎦
⎣
⎦

, ....................................................................................(19)and the conduction loss for the FWD side of Sn+1 and Sn+2
is given by
PANPC _ con _ Cell 2 _ FWDB =1 ⎡ ⎡⎛ φ 1
2
1 ⎞⎤
⎞ ⎛1
2
⎢ ⎜ − sin 2φ ⎟ + a⎜ cos 2φ − cos φ + ⎟ ⎥ ron I m
2π ⎣ ⎢⎣⎝ 2 4
3
2 ⎠⎦
⎠ ⎝6

1
⎤
⎡
⎤
+ ⎢ − 1 + cos φ − a (sin φ − φ cos φ )⎥ v0 I m ⎥
2
⎣
⎦
⎦

.

.....................................................................................(20)Thus, the switching loss of the switches in Cell 1 is
proportional to the applied voltage and current.
Therefore, the switching loss of Cell 1 depends on thecurrent flows through the switches and the numbers ofswitch. The Cell 1 switching loss PANPC_switching_Cell1 isgiven by
PANPC _ switching_ Cell1 =1

Edc I m(n − 1)π Edcd I md

(e + e ) f . ...........................(21)
on

off

c

The recovery loss PANPC_rec_Cell1 is given by
P5 A _ rec _ Cell1 =1

Edc I me f(n −1)π Edcd I md rr c . ..........................................(22)The switching loss in Cell 2 depends on the output
frequency (50 Hz).As a result, the switching loss in Cell

2 is lower than that in Cell 1, which is approximately
zero, and therefore can be ignored.
No-load loss in the Cell1 PANPC_nl_Cell1 is calculated by
2

1 ⎡ E ⎤PANPC_ nl _ Cell1 = C p ⎢ dc ⎥ f c . .............................................. (23)2 ⎣ (n −1) ⎦On the other hand, the no-load loss in Cell 2 is also
approximately zero, and therefore can be ignored basedon the switching loss in the Cell 2.
Thus, total semiconductor loss per one switch in the nlevel FC topology is given by⎡ (n − 3) ⎤+ 1⎥(PANPC _ con _ sw _ Cell1 + PANPC _ con _ FWD _ Cell1
PANPC _ Loss _ semi = 2⎢⎦
⎣ 2
+ PANPC _ switch _ Cell1 + PANPC _ rec _ Cell1 + PANPC _ nl _ Cell1 )⎡ (n − 1) ⎤(PANPC _ con _ sw _ Cell 2 A + PANPC _ con _ FWD _ Cell 2 A+ 2⎢⎣ 2 ⎥⎦+ PANPC _ con _ sw _ Cell 2 B + PANPC _ con _ FWD _ Cell 2 B ).

(a) Three-level FC topology.

..................................................................................... (24)C.

Experimental verification
Table 1 shows the converter specifications and device
parameters. This section discusses the validity ofmathematically calculated losses based on theexperimental results. Thus, the three-level FC inverter
and the five-level ANPC inverter are designed based onconverter specifications and device parameters.
Figure 3 shows the experimental waveforms of the
prototypes of the single-phase three-level FC inverter andthe single-phase five-level ANPC inverter for a 3.3 kW
load. Both inverters show a perfect sinusoidal waveform
without distortion of the output current, respectively. In
addition, a three-step waveform of the output voltages of
the three-level FC inverter is shown, Figure 3 (a). On theother hand, a five-step waveform of the output voltagesof the five-level ANPC inverter is shown as well, Figure
3 (b).
Figure 4 shows the no-load loss comparison between
the calculation and simulation results of the both
multilevel inverters. Note that the parametric capacitanceof the MOSFET is measured by LCR meter (5 V, 10kHz). Both, the calculation results of no-load loss and theexperimental results show a good agreement. In addition,
the error ratio is under 2.2 %.
Figure 5 shows the power loss comparison between
the calculation results and experimental results of theboth inverters. Both, the calculation results and theexperimental results show a good agreement. In addition,
the error ratio is under 6 %. The validity of the loss(b) Five-level ANPC topology.
Fig. 3. Experimental waveforms.

Fig. 4. No-load loss comparison.

TABLE 1
SPECIFICATION

Fig. 5. Power loss comparison.

calculation method for the both generalized multilevel
inverters is confirmed by the experimental results. The
power loss comparison results as shown in Figure 5
include the wire resistance, equivalent series resistance(ESR) of the flying capacitor, and ESR of the DCsmoothing capacitor. The measurement results of thoseparameters are as follow, 13.5 mΩ (wire resistance of thethree-level FC), 14.9 mΩ (wire resistance of the fivelevel ANPC), 21.0 mΩ (ESR of the flying capacitor), and19.8 mΩ (ESR of the DC smoothing capacitor).
IV.

POWER LOSS EVALUATION IN TERMS OF THE

Fig.6. Scatter plot of on-resistance and breakdown voltage of MOSFET.

NUMBER OF LEVELSThis section discusses the power loss in terms of thenumber of levels using two kinds of the power devices,which are MOSFET and IGBT. First, in the case of
MOSFET, the power losses from three-level to elevenlevel are calculated based on the mathematical expression.
On the other hand, in the case of IGBT, the power losses
from two-level to five-level are calculated similar to thecase of MOSFET.
A. MOSFET
Figure 6 shows the scatter plot of the on-resistanceand the breakdown voltage of the MOSFET. The
MOSFETs are selected from five different semiconductor
manufactures which are Infineon, IR, IXYS, Renesas,
and TOSHIBA. The criterions of selecting devices are therange of breakdown voltage from 60 V to 300 V and therange of continuous drain current from 50 A to 100 A. In
Figure 6, we assume that the on-resistance of the
MOSFET increases in proportional to the breakdown
voltage of the MOSFET. Thus, a line in the Figure 6 iscalculated by approximate expression based on the
hypothesis situation. In addition, power losses of the both
multilevel converters the range of the number of levels
from three-level to eleven-level are calculated based on
the line. Note that the 10-kW application of three-phase
inverter for PV is considered. On the other hand, ANPC
topology is considered for two conditions. First condition
is Cell 2 devices of the ANPC topology 1 use highvoltage rating devices. Second condition is Cell 2 devicesof the ANPC topology 2 use the same devices rating of
the Cell 1 devices.
Figure 7 shows the power loss characteristics of themultilevel converters that are structured from three-levelto eleven-level. From Figure 7 (a), the conduction loss of
ANPC topology 2 is the same to the conduction loss of
FC topology. On the other hand, the switching loss of the
ANPC topology is half of the switching loss of the FC
topology in the Figure 7 (b). Thus, the power loss of the
ANPC topology is lower than the power loss of the FC
topology in the Figure 7 (c).
Table 2 shows the relationship between number ofswitch per one switching state and total on-voltage.
Power loss of the multilevel inverter decreases in inverse
proportion to the number of level. The condition that(a) Conduction loss(b) Switching loss(c) Total loss
Fig.7. Power loss characteristics of multilevel converters.
1 [p.u.] of the figure 7 (a) is normalized value by total conduction loss ofthe three-level ANPC topology 1. On the other hand, 1 [p.u.] of the figure
7 (b) are normalized by total switching loss of the three-level ANPC
topology 1. Finally, 1 [p.u.] of the semiconductor losses of figure 7 (c)are normalized value by total loss of the three-level ANPC topology 1.
Cell 2 devices of the ANPC topology 1 use high-voltage rating devices.
Cell 2 devices of the ANPC topology 2 use same rating devices of the
Cell 1 devices.

TABLE 2
RELATIONSHIP BETWEEN LEVEL AND NUMBER OF SWITCH AND TOTAL
ON-RESISTANCE

6

Selection critea
Breakdown voltage : 600V-1800V
Continuous drain current: 550A-1800A
Device product : ABB, Fuji electric. Infeneon,IR, MITSUBISHI, Renesas

5
4
3
2
1
0

von _ nl <1

Conduction loss [p.u.]

500
1000
1500
2000
Breakdown Volltage of device [V]
Fig.8. Scatter plot of on-voltage and breakdown voltage of MOSFET.

power loss decreases in inverse proportion to the numberof level is discussed based on Figures 6 and 7. Multilevel
converter increases the number of semiconductor device
per on switching state in proportion to the number oflevel in the table 2. Thus, if the total resistance ofsemiconductor per on switching state of n-level inverter
is lower than the total resistance of the (n-1)-level
inverter, the n-level inverter can achieve low
semiconductor loss. The condition that power loss
decreases in inverse proportion to the number of level isgiven by0v

(n − 1) on _ 2l , .......................................................... (22)
Where von_nl is on-voltage of semiconductor of n-level
inverter, von_2l is on-voltage of semiconductor of 2-level
inverter. For example, the level of inverter is assumed tochange from three-level to five-level. If the total onresistance of the five-level inverter is achieved byreferring equation (22), the power loss of the five-level
inverter is reduced. On the other hand, if the five-level
inverter is not achieved by referring equation (22), thepower loss of the five-level inverter is larger than thethree-level inverter. Thus, it is not effective to change thelevel from three-level to five-level. However, the power
loss of three-level inverter can be reduced if low onresistance MOSFET which is lower than existing
MOSFET. Note that the level of inverter is held the samelevel. Thus, the power loss of three-level inverter can be
reduced.

B. IGBT
Figure 8 shows the scatter plot of the on-voltage andthe breakdown voltage of the IGBT device. The IGBTs
are selected from five different semiconductor
manufactures which are ABB, Fuji electric, Infineon, IR,
MITUBISHI, and Renesas. The criterions of selecting
devices are the range of breakdown voltage from 600 V
to 1800 V and the range of continuous drain current from
550 A to 1800 A. In Figure 8, we assume that the onvoltage of the IGBT increases in proportion to thebreakdown voltage of the IGBT. Thus, a line in the
Figure 8 is calculated by approximate expression basedon the hypothesis situation. In addition, this section
discusses the power loss among four topologies which
are ANPC topology, FC topology, DCLMP topology, andconventional two-level topology. It is because the(a) Conduction loss
1.2

Two-level topology
ANPC topology 1

1.0

ANPC topology 2
FC topology

0.8

DCLMP topology

Specification
Rated power: 250 kW
Input voltage: 550 V
Output voltage: 300 V
Output current: 481 A
Output frequency : 50 Hz
Carrier frequency : 1 kHz

0.6
0.4
0.2
0.0

2

3

4
Number of level(b) Switching loss

56(c) Total loss
Fig.9. Power loss characteristics of multilevel converters.
1 [p.u.] of the figure 9 (a) is normalized value by total conduction loss ofthe two-level topology. On the other hand, 1 [p.u.] of the figure 9 (b) arenormalized by total switching loss of the two-level topology. Finally, 1[p.u.] of the semiconductor losses of figure 9 (c) are normalized value by
total loss of the two-level ANPC topology 1. Cell 2 devices of the ANPC
topology 1 use high-voltage rating devices. Cell 2 devices of the ANPC
topology 2 use same rating devices of the Cell 1 devices.

conventional two-level topology and the DCLMP
topology are applied in medium-voltage application. The
power losses of four multilevel converters, the range ofthe number of levels from two-level to five-level arecalculated based on the line. Note that the application offour topologies is 250-kW three-phase inverter for PV. In
addition, the two-level topology is calculated bymathematical expression [8]. On the other hand, DCLMP
topology is calculated by simulation software (PSIM).
Figure 9 shows the power loss characteristics ofmultilevel converters that are structured from two-level tofive-level. From Figure 9 (a), the conduction loss of the
two-level inverter is the lowest than other topologies. On
the other hand, the conduction loss of ANPC topology 2
is the same to the conduction loss of FC topology. From
Figure 9 (b), the switching loss of the five- level DLMPC
inverter is the lowest than other topologies. From Figure
9 (d), the power loss of the two-level inverter is lower
than other topologies.
Power loss of the multilevel inverter increases inproportion to the number of level. This result is different
in the case of MOSFET. It is because there is littlechange in on-voltage of the IGBT which is the range of
breakdown voltage from 600 V to 1800 V. It is difficult
to achieve the criteria of selecting devices by equation(22). Thus, in case of the IGBT, it is not effective forpower converter in medium-voltage application toincrease the number of levels in terms of the power loss.
V.

CONCLUSION

This paper discussed power losses of two multilevel
topologies in terms of numbers of the output voltage level
using two power devices. In case of the MOSFET, power
loss of the multilevel inverter decreases in inverse
proportion to the number of level. In addition, the ANPC
topology is better results comparing to the FC topology,
regardless of the number of level. On the other hand incase of the IGBT, power loss of the multilevel inverter
increases in proportion to the number of level. The twolevel converter shows the best result compared to othertypes of multilevel converters, regardless of the numberof level.
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