Current THD Reduction for High-Power-Density LCL-Filter-Based
Grid-Tied Inverter Operated in Discontinuous Current Mode
Hoai Nam Le, Jun-ichi Itoh
Nagaoka University of Technology
1603-1 Kamitomioka-cho
Nagaoka city Niigata, Japan
Tel., Fax: +81 / (258) – 47.9533.
E-Mail: lehoainam@stn.nagaokaut.ac.jp, itoh@vos.nagaokaut.ac.jp
URL: http://itohserver01.nagaokaut.ac.jp/itohlab/index.html

Keywords«Single-phase grid-tied inverter», «Continuous current mode», «Discontinuous current mode», «Disturbance compensation», «Nonlinearity compensation»

Abstract
This paper proposes a discontinuous current mode (DCM) feedback current control for a single-phasegrid-tied inverter in order to minimize a LCL filter without worsening total harmonic distortion (THD)
of a grid current. In DCM, there are two nonlinearities occurring in the transfer functions; the first nonlinearity occurs in the duty-ratio-to-current transfer function which worsens the current command response, whereas the second nonlinearity occurs in the disturbance-to-current transfer function which
reduces the disturbance effect. In the proposed DCM current control, the first nonlinearity is compensated by utilizing the duty ratio at the previous calculation period in order to achieve the same control
performance of the current command response as in continuous current mode. Meanwhile, the second
nonlinearity is utilized in order to reduce the disturbance effect when the LCL filter with a small impedance is applied. Furthermore, a design procedure of the LCL filter is introduced under the condition thatthe impedance of the LCL filter can be minimized without worsening the grid current THD by applying
the proposed DCM control. A 1-kW 100-kHz inverter with several LCL filters of different impedances(3.0%, 0.6% and 0.04%) is constructed in order to confirm the operation of the proposed DCM current
control. As a result, the grid current THD is reduced from 8.5% to 3.7% at rated load. Furthermore, theinductor volume is reduced by 77.0%, whereas the converter loss is reduced by 17.1%.

I. Introduction
Grid-tied inverters are used in order to connect photovoltaic (PV) cells to a single-phase ac grid. A
filter is required between the inverter and the grid for reducing harmonics of the inverter output current.
LCL filters have been commonly used in grid-tied inverters because they can achieve the size reduction
by the use of small values of inductors and capacitors comparing to the L filter and LC filter [1]-[3].
The high attenuation of the LCL filter allows the design of the high cutoff frequency in the filter to meet
harmonic constraints as defined by standards such as IEEE-519-1992 [4]. However, the small impedanceof the LCL filter highly increases the disturbance gain of the conventional PI-controller-based continuous current mode (CCM) feedback current control. In order to overcome this problem, a disturbanceobserver which is designed based on CCM is utilized. This disturbance observer estimates the disturbances and eliminates them from the current feedback control. However, this method requires high speed
controllers in order to estimate the rapidly-changing disturbances, e.g. the dead-time error voltage [5].
On the other hand, the effects of the disturbances can be reduced by discontinuous current mode
(DCM). In particular, a DCM nonlinearity occurs in the disturbance-to-current transfer function, which
results in the natural decrease in the disturbance gain. However, another nonlinearity occurs in the duty-to-current transfer function, which worsens the current command response [6]-[7]. In past few years,many researches focusing on the control of DCM have been reported to solve this problem [8]-[13].
However, in those control methods, the DCM nonlinearity compensation method becomes circuit-parameter-dependent. In the PV application, the system is usually required to deal with the severe changeof the ambient environment, where the circuit condition such as the operation temperature varies frequently. This leads to the instability of the circuit-parameter-dependent control.
This paper proposes a circuit-parameter-independent DCM current control. The original idea is thatthe nonlinearity compensation in the DCM current control is constructed by utilizing the duty ratio at
the previous calculation period instead of using the circuit parameter, whereas the DCM nonlinearity
occurring in the disturbance-to-current transfer function is used to reduce the disturbance effect, i.e. thereduction of the current distortion. This paper is organized as follows; first two DCM nonlinearities
which occur in the current command response and the disturbance response are investigated. Then, thecompensation for the DCM nonlinearity in the current command response is proposed and the mechanism to utilize the DCM nonlinearity in the disturbance response to reduce the current distortion is
explained. After that, the volume evaluation of the LCL filter is conducted. Finally, the effectiveness ofthe proposed DCM feedback current control is confirmed experimentally.

II. Proposed DCM Current-Feedback Control
Fig. 1 indicates the circuit configuration of the single-phase grid-tied inverter. In this paper, a singlephase H-bridge inverter is applied due to its simplicity. The LCL filter connects the inverter to the gridfor smoothing the inverter output current iout. Note that the grid has its own intrinsic inductor Lg, thevalue is different depending on the type of the grid [3]-[4].
Fig. 2 indicates the equivalent circuit of the single-phase grid-tied inverter when the grid voltage ispositive. The grid-side inductors Lg, Lf, and the filter capacitor Cf are omitted due to the simplification.
Note that the grid-tied inverter is operated in bipolar modulation.
Fig. 3 depicts the inductor current waveform in DCM, where D1, D2 and D3 denote the duty ratios of
the first, the second and the zero-current interval. The equation based on the average model of the inverter shown in Fig. 5 is given by (1) [6]-[7],VL  D1 (Vdc  Vg )  D2 (Vdc  Vg )(1)
where VL is the average inductor voltage, Vdc is the DC-link voltage and Vg is the grid voltage. The
average current iavg and the current peak ipeak, which are shown in Fig. 3 are expressed as,
Grid side
SW2

SW1

Lf

L

ig

iout
Vdc

Lg

vg

Cf

SW1

SW2

Fig. 1. Single-phase H-bridge grid-tied inverter with LCL filter. A single-phase H-bridge inverter is applied due to its simplicity, which
is important for stability analysis and reliability design.

L

L

iout
Vdc

iout

Vg

Vdc

Vg

(a) Charging of inductor(b) Discharge of inductor
Fig. 2. Equivalent circuit of inverter when grid voltage is positive. The bipolar modulation is applied to reduce common-mode current.

iavg i peak(2)( D1  D2 )2
Vdc  Vgi peak 
D1Tsw
L

(3)

where Tsw is the switching period. Substituting (3) into (2) and solving the equation for the duty ratio
D2. The duty ratio D2 is expressed by (4),2 Liavg
(4)
D2 
 D1
D1Tsw (Vdc  Vac )Substituting (4) into (1) in order to remove the duty ratio D2 and represent (1) as a function of only the
duty ratio D1, then (5) is obtained [6]-[7].

2 Liavg
VL  Vdc (2 D1  1)  Vg  (Vdc  Vg )1 (5) (Vdc  Vg ) D1Tsw Then, the inverter circuit model in DCM is establish based on (5).
Fig. 4 illustrates the circuit model of the inverter operating in DCM which is based on (5). In CCM,
the dash line part does not exist, because the average current iavg equals to the half current peak ipeak/2.
On the other words, this makes the zero-current interval D3Tsw shown in Fig. 3 become zero. However,in DCM, the zero-current interval introduces the nonlinearities into the DCM transfer function. The
design of the compensation part for the DCM nonlinearity is explained as follows. First, the circuit
model in Fig. 4 is linearized at steady state.
Fig. 5 depicts the linearized circuit model. The duty-ratio-to-current transfer functions in CCM and
DCM are derived from Fig. 5, and expressed as in (6) and (7) respectively,
i ( s ) 2Vdc _ s
Gi _ CCM ( s )  avg
(6)
D1 ( s )sL
Gi _ DCM ( s) iavg ( s)
D1 ( s)
sL 

4Vdc _ s
2 L(Vdc _ s  Vg _ s )(7)

D1_ sTsw (Vdc _ s  Vg _ s )Fig. 6 depicts the gain of the duty-ratio-to-current transfer function in CCM and DCM under different
conditions of the steady-state duty ratio D1_s and the grid voltage Vg_s based on (6)-(7). In most cases,
the frequency corresponding to the pole of Gi_DCM is certainly much higher than the cutoff frequency ofCurrentPeak
ipeak

Inductor
current
iout

Averagecurrent
iavg

0
D1Tsw

D2Tsw

D3Tsw

Tsw

Fig. 3. Inductor current waveform in DCM. The zero-current interval introduces nonlinearities into the DCM operation.
Vg

1
D1
[0~1]

VL

Vdc

2

1
sL

iavg

Nonlinear factor
Vdc + Vg
D31iavg
0.5ipeak(Vdc-Vg)Tsw
2L

0.5ipeak

Do notexist in
CCM

iavg

Fig. 4. Circuit model of inverter operated in DCM. In DCM, the current control depends greatly on the current value, i.e. the nonlinearities occurring in the duty-ratio-to-current transfer function and the disturbance-to-current transfer function.

the current control loop fn. Consequently, the open loop gain in DCM is much lower than in CCM. Thisworsens the current response in DCM if the same PI controller as in CCM is employed in DCM. Therefore, the output of PI controller is necessary to be compensated when the circuit is operated in DCM inorder to achieve the same current command response as in CCM. In order to eliminate the dash line partin Fig. 5, in the control system, the value of D1_s is approximated as the duty ratio of SW1 at the previous
calculation period D1[n-1]. As a result, the circuit model is necessary to be analyzed in the discrete model.
Fig. 7 depicts the discretized circuit model. In order to compensate the DCM nonlinearity at theoutput of the PI controller designed in CCM, the dash line part in Fig. 7 is necessary to be set as 1 when
the circuit is operated in DCM. Therefore, in the control system, the inverse part of the dash line partin Fig. 7 is multiplied at the output of the PI controller in order to compensate for the DCM nonlinearity.
Fig. 8 illustrates the conventional CCM current control, and the proposed DCM current control. In
CCM, the disturbance effect increases 10 times when L is reduced from 1 p.u. to 0.1 p.u., because thegain of the disturbance response inversely proportional to L [5]. On the other hand, in the proposed
DCM current control, the PI controller is designed as same as in CCM, whereas the DCM nonlinearity
compensation is calculated by using the duty ratio of SW1 at the previous calculation period D1[n-1]. The
estimation of the duty ratio at steady state D1_s as the duty ratio of SW1 at the previous calculation period
D1[n-1] provides the control system circuit-parameter-independence, and short computation time. The
switches SW1 and SW2 are controlled separately depending on the polarity of the duty ratio D1. The
synchronous switching of SW1 and SW2 can be employed in order to further improve the inverter efficiency [7], [10]. Note that the absolute value of the grid voltage is calculated in order to use the same
DCM nonlinearity compensation when the grid voltage becomes negative.
Fig. 9 shows the gain of the disturbance response in CCM and DCM under different conditions of
the steady-state duty-ratio D1_s. In CCM, the minimization of the inductor value L worsens the disturbance response. In general, when the typical dead-time error voltage compensation is applied with thehigh L, the current distortion is effectively reduced. However, when L is greatly reduced, only a small
mismatch between the estimated and actual dead-time error voltage (vdeadtime_est and vdeadtime) which is
caused by such as the current detection delay, results in a high current distortion due to the greatlyVL

2Vdc_s

ΔD1

1
sL

iavg

2L(Vdc_s + Vg_s)

2Vdc_s

D1_sTsw(Vdc_s - Vg_s)

Do not exist in CCM

Fig. 5. Linearized circuit model. By estimating the duty ratio at steady states, the DCM nonlinearity can be compensated. Consequently,
the controller in DCM can be designed as same as in the CCM operation, which has been researched and analyzed thoroughly.
140
CCM

120

Gain [dB]100

Inductance L: 150 mH
DC-link Voltage Vdc: 380 V
Switching Period Tsw: 20 ms

80
DCM Vg_s = 10 V
D1_s = 0.2

60
40
20
0

Vg_s = 100 V

-20
-40
0.1

1

D1_s = 0.05

10

100
1k
10k 100k 1M 10M
Frequency f [Hz]Fig. 6. Bode diagram of duty-ratio-to-current transfer function for CCM and DCM. The zero-current interval in DCM introduces the first
nonlinearity into the duty-ratio-to-current transfer function, which greatly worsens the DCM current command response.

ΔD1

z-1
z

2Vdc_sD1_s(Vdc_s - Vg_s)
Vdc_s + Vg_s

VL

Tsw
L(z-1)

Δiavg

Fig. 7. Discretized circuit model. The original idea of the DCM nonlinearity compensation is to estimate the duty ratio at steady statesby the duty ratio at the previous calculation. Consequently, the inductance is not required in the DCM nonlinearity compensation.

PI Controller

Control System Circuitvg
vg

Kp(sTi+1)
sTi

1 D1
Vdc

iavg*
iavg

sign

VdcTd fsw

vdis

Vdc

vdeadtime
1 iout_avg
sL

vdeadtime_est
e-sT(a) Conventional CCM feedback current control block with typical dead-time error voltage compensation. When the inductors is minimized
by reducing the inductance, the inverter become more vulnerable to the disturbances, i.e. the increase in the disturbance gain.
Conventional CCM PI
Controller
V*L
iavg*
PI

Compensation for nonlinearity in duty-tocurrent transfer function
Vdc + |vg|
2Vdc(Vdc - |vg|)

iavg

a

a/b

Duty ratio polarity alternation
iout

D1

SW1

b

|x|

z-1

-1

SW2

1

iavg

0A

0

D1

0

Disturbance response gain [dB](b) Proposed DCM current control for inverter. In DCM, the switches SW1 and SW2 are controlled separately depending on the polarityof the duty ratio, i.e. the polarity of the grid voltage in unity power factor.
Fig. 8. Conventional CCM current control and proposed DCM current control for inverter.
0
-10
-20
-30
-40
-50
-60
-70
-80

Grid-connected Inductance L: 150 mH
DC-link Voltage Vdc: 380 V
Grid Voltage Vg_s: 141 V

CCM

D1_s = 0.3

DCM

D1_s = 0.1

D1_s = 0.05

10

100
1000
Disturbance frequency f [Hz]Fig. 9. Disturbance response in CCM and DCM. The DCM nonlinearity in the disturbance-to-current transfer function makes the DCM
current more resistant to the disturbance than the CCM current. Therefore, the LCL filter can be further minimized in DCM.

increasing gain of the disturbance response. On the other hand, in DCM when the steady-state duty-ratio
D1_s becomes smaller, the disturbance response gain in DCM decreases. The reason is that the proposed
DCM nonlinearity compensation for the current command response does not compensate for the DCM
nonlinearity in the disturbance response. Consequently, the disturbance response depends on the steadystate duty-ratio D1_s. Therefore, by utilizing this nonlinearity characteristic in which the disturbance gain
decreases greatly with the small steady-state duty-ratio D1_s, i.e. the interval near the current zero-crossing point or the light load, the current distortion can be reduced.

III. LCL Filter Design Procedure
Fig. 10 indicates the LCL filter design algorithm. The following parameters are needed for the filter
design: the rated active power Pn, the dc-link voltage Vdc, the single-phase grid voltage vg, and the gridfrequency fg. First, the base impedance of the inverter is defined by (8), [1]

Zb 

vg2
Pn

(8)

Next, in order to design the filter capacitor, the base capacitance is defined by (9),
1
1 Pn
Cb 

(9)
2f g Z b 2f g vg2

Input: Pn,Vdc, vg, fg
Reactive
Power
Restriction

Capacitor Cf = 0.01~0.05 x CB
Select Min. Switching Frequency
Select Max. Impedance of Inter. Inductor

Current
Distortion
LimitsIEEE 519-1992

Inverter-side Inductor L → Vol.
Required Attenuation → Lf → Vol.
Capacitor Current Ripple → Vol. Cf
Decrease Impedance of Inter. InductorN%ZL＜Min. of %ZL
YIncrease Switching Frequency

Nfsw＞fsw_max
Y
Output: LCL Filter Volume

Fig. 10. LCL filter design algorithm. In DCM, the LCL filter can be optimized in aspect of volume or loss because the DCM disturbancegain is much smaller compared to CCM even with a small impedance of the LCL filter.

Filter Volume [cm3]1000

VDC: 380V vg: 200Vrms Pn: 1.0kW fg: 50Hz fsw: 100kHz100%ZL=3.0%
(P1)

10

1

Total Vol
%ZL=0.6%(P2)%ZL=0.04%
(P3)

VolL
VolLf
VolCf

Lf ≦ Lg Lf ＞Lg

0.1

10

1
0.1
Impedance of Inverter-side Inductor %ZL [%]0.01

Fig. 11. Relationship between filter volume and inductor impedance at switching frequency of 100 kHz. The filter volume can be minimized greatly when reducing the impedance of the inverter-side inductor.

The filter capacitor value is limited by the decrease of the power factor at rated power (generally lessthan 5%), i.e. the reactive power restriction. Next, at the certain combination of the switching frequency
fsw and the impedance of the inverter-side inductor %ZL, the inductor value L is calculated. In the conventional CCM current control, the impedance of the inverter-side inductor L is necessary to be designed
larger than several percentages of the base impedance of the inverter, because the disturbance response
worsens with a small impedance of the inductor. This limits the minimization of the inductor. In the
proposed DCM current control, the impedance of the inverter-side inductor L can be simply reduced inorder to minimize the inductor volume, because the gain of the disturbance response is much smaller
than that of the conventional CCM current control as shown in Fig. 9. This enables the optimization of
the inductor volume in aspect of the inductor volume. Then, selecting a current ripple attenuation withrespect to the ripple on the inverter side, the filter inductor value Lf is calculated. Minor inductor design
loops are conducted in order to optimize the inductor volume and loss. After that, the volume of thefilter capacitor is calculated based on the capacitor current ripple. Finally, the switching frequency andthe impedance of the inverter-side inductor are varied in order to optimize the LCL filter [14]-[16].
Fig. 11 depicts the filter volume against the impedance of the inverter-side inductor. For the simplification, in this digest only the switching frequency of 100 kHz and the filter capacitor value of 0.2 mF
are considered. When %ZL decreases: the volume of the filter capacitor is almost unchanged; the filter
inductor value Lf increases due to the increase in the required attenuation. However, the filter inductor
volume stays at zero until the filter inductor value Lf becomes higher the minimum value of the grid

intrinsic inductor value Lg, which is 42 mH [3]-[4]. On the other hand, the inverter-side inductor volume
VolL decreases due to the decrease in the inductance. The analysis of the current control performanceand the volume evaluation of the inverter are carried out at three design points (P1-P3).

IV. Experimental Results
Table I depicts the experimental parameters. The operation frequency of the current controller is
synchronized with the sampling frequency of 25 kHz despite of the high switching frequency of 100
kHz. This enables the use of low speed controllers.
Table II shows the specifications of the inductors in LCL filters, whereas Fig. 12 depicts the prototypes of the inverter-side inductors L under different conditions of the inductor impedance %ZL. Ferrite
is chosen to be the core material in order to minimize the core loss at the switching frequency of 100
kHz, whereas Litz wire is used in order to minimize the winding loss coming from the proximity effectand the skin effect. By the application of DCM, the impedance of the inductor impedance %ZL can be
minimized without worsening the disturbance response as shown in Fig. 9. Consequently, by reducing
the impedance of the inverter-side inductor %ZL from 3.0% to 0.04%, the inductor volume is reducedby 77%.
Fig. 13 shows the grid voltage, grid current and inverter output current. The IEEE-519-1992 standards require the grid current THD below 5% at rated load, which can be accomplished simply with thehigh impedance of the inverter-side inductor %ZL as shown in Fig. 13(a) [1]. However, as the inverterTABLE I
SYSTEM PARAMETERS.
Circuit Parameter
VDC
vg
Pn
fg
Zb
Cb
Cf
fsw
tdead

DC link Voltage
Grid Voltage
Nominal Power
Switching Device
Grid Frequency
Base ImpedanceBase Capacitance
Filter Capacitor
Switching Frequency
Deadtime

fsamp

380 V
200 Vrms
1 kW
sch2080ke
50 Hz
26.7 W
119 mF
2 mF
100 kHz400 ns

z
fc
VDSS
ID
Rds
tr
tf
VSD

Current Controller Parameter
Sampling Frequency
25 kHzDamping Factor
0.707
Cutoff Frequency
1 kHz
SiC Device Ratings
Drain – Source Voltage 1200 V
Continuous Drain Cur. 40 A
On-state Resistance
117 mW
Rise time
33 ns
Fall time
28 ns
Forward Voltage
1.3 V

TABLE IISPECIFICATIONS OF INDUCTORS IN LCL FILTERS.
0.6% (P2) 0.04% (P3)
XL1 / Zb 3% (P1)
7.2
7.6
15.5
Max. Cur. ipeak [A]
3800
770
50
Inv. side Ind. L [mH]
EE55
EE42
EE36
Core TypeCore Material
Ferrite N87
Litz Round 2UEWSTC 100 / f0.1
Wire
Air Gap [mm]31.92
Number of Turns
59
16
115
Volume [cm3] 119 (1 p.u.) 52 (0.43 p.u.) 25 (0.21 p.u.)
7.6
31.3
1.9
Filter Ind. Lf [mH]Using grid-side inductor Lg as Lf because Lf < Lg
L(%ZL=3.0%)
VolL=110cm3(1.0p.u.)
L(%ZL=0.6%)
VolL=52cm3(0.47p.u.)

w = 29 mm

w = 19 mm

h = 37 mm

h = 43 mm

h = 57 mm

w = 35 mm

L(%ZL=0.04%)
VolL=25cm3(0.23p.u.)l = 36 mm
l = 55 mm
l = 42 mm
Fig. 12. Prototypes of inverter-side inductors under different condition of inductor impedance. By reducing the impedance of the inverter-side inductor %ZL from 3.0% to 0.04%, the inductor volume is reduced by 77%.

Grid Voltage vg (500 V/div)

Grid Current ig (5 A/div)

THDig=2.0%

THDig=5.0%
Grid Voltage vg (500 V/div)

Grid Current ig (5 A/div)

Inverter Output Current iout (10 A/div)

Time (10 ms/div)(a) Operation waveforms (%ZL=3.0%, rated load)

Inverter Output Current iout (1 A/div)

Time (10 ms/div)(b) Operation waveforms (%ZL=3.0%, light load of 0.1p.u.)
Grid Voltage vg (500 V/div)

Grid Current ig (5 A/div)

THDig=8.5%

THDig=16.6%
Grid Voltage vg (500 V/div)

Time (10 ms/div)

Grid Current ig (5 A/div)

Inverter Output Current iout (10 A/div)

Time (10 ms/div)(c) Operation waveforms (%ZL=0.6%, rated load)
Grid Voltage vg (500 V/div)

Grid Current ig (5 A/div)

Inverter Output Current iout (1 A/div)(d) Operation waveforms (%ZL=0.6%, light load of 0.1p.u.)
Grid Voltage vg (500 V/div)

Grid Current ig (5 A/div)

THDig=3.7%

THDig=12.0%

Inverter Output Current iout (10 A/div)

Time (10 ms/div)

Inverter Output Current iout (1 A/div)

Time (10 ms/div)(e) Operation waveforms (%ZL=0.04%, rated load)(f) Operation waveforms (%ZL=0.04%, light load of 0.1p.u.)
Fig. 13. Measured grid voltage, grid current and inverter output current. By the employment of the proposed DCM current control, thegrid current THD below 5% at rated load is achieved even with a small inductor impedance of 0.04%.

side inductor value is reduced to minimize the LCL filter as shown in Fig. 11, the disturbance effects
increase with the small ZL. Consequently, the grid current THD rises from 2.0% to 8.5% when %ZL is
reduced from 3% to 0.6%. This problem can be overcome by increasing the control bandwidth of thecurrent controller, which is difficult to employ with low speed controllers. On the other hand, when the
inverter is operated in DCM, the disturbance effects naturally reduce at low duties as shown in Fig. 9,
i.e. the zero-crossing intervals, due to the nonlinearity in the disturbance response. Therefore, the low
grid-current THD of 3.7% is achieved with the proposed DCM current control even when %ZL is reduced
to 0.04%. Furthermore, at the light load of 0.1 p.u., the grid current THD reduction by the proposed
DCM current control is also confirmed from 16.6% to 12.0% as shown in Fig. 13(d) and 13(f).
Fig. 14 shows the comparison of the grid current THD and the efficiency under different values of
the inductor impedance. In CCM, the disturbance gain is constant against load, which results in theincrease of the grid current THD at light load. On the other hand, by utilizing the DCM nonlinearity inthe disturbance response, in which the disturbance gain decreases naturally at light load, the low gridcurrent THD can be achieved. In particular, as shown in Fig. 14(a), even when the impedance of thegrid-tied inductor %ZL is minimized to 0.04% of the inverter total impedance, the grid current THD ismaintained to be lower than 5% over wide load range from 0.6 p.u. to 1.0 p.u. by the proposed DCM
current feedback control. Furthermore, as shown in Fig. 14(b), the efficiency at rated load with %ZL =0.04% is improved by 0.7% compared with %ZL = 3.0% due to the decrease in the winding loss by
reducing the inductor value. However, the efficiency at rated load with % ZL = 0.04% is lower by 0.5%
compared with %ZL = 0.6% due to the increase in the current peak ipk. At light load of 1.0 p.u., theefficiency %ZL = 0.04% is improved by 1.2% and 5.3% compared with %ZL = 0.6% and %ZL = 3.0%,

%ZL=0.6% (CCM)

1598

Vdc = 380 V
Vin = 200 Vrms
fsw = 100 kHz
1 p.u. = 1 kW
SiC devices

10%ZL=0.04% (DCM)%ZL=0.04% (DCM)%ZL=0.6% (CCM)

97
96
95
Efficiency [%]Total Harmonic Distortion of grid current [%]

20

0.7%

1.2%

94
93
92

0.5%

5.3%
%ZL=3.0% (CCM)

Vdc = 380 V
Vin = 200 Vrms
fsw = 100 kHz
1 p.u. = 1 kW
SiC devices

91

5

90
%ZL=3.0% (CCM)

89

0

88
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Load [p.u.]
Load [p.u.](a) Grid current THD against load(b) Efficiency against load
Fig. 14. Comparison of grid current THD and efficiency under different values of inductor impedance. By the application of DCM, thelow grid current THD and the efficiency improvement can be achieved.
0

45
40

0.2

Semi. device
losses0.1

Conduction loss
Switching loss

Loss [W]

5.9

17.7
0.4

25

0.4

1.2

1.6

6.7
41

20
15

Winding loss
Core loss

Damping Resistor Loss
Experimental Result

35
30Inductorlosses

13.1
34

15.7

14.5

29

10
5

5.9
5.9
0
3% (P1) - CCM
0.6% (P2) - CCM
XL1/Zb
h
95.9%
97.1%
Error
3.5%
3.9%
Fig. 15. Volume and loss distribution of at three design points (P1-P3).

12.8

0.04% (P3) - CCM
96.6%
1.7%

respectively. The reason is because when the inverter is operated in DCM, the current ripple naturally
decreases at light load, whereas the current ripple in CCM is constant against the load as shown in Fig.
13. The reduction in the current ripple at light load results in the decrease in the inductor loss and theswitching device loss.
Fig. 15 depicts the loss distribution at three design points (P1-P3) and the measured inverter loss.
The semiconductor device losses and the damping resistor loss are obtained from the simulator PLECS,
whereas the inductor losses are obtained from the GECKO simulation. At the high %ZL of 3% the winding loss dominates the total loss as shown in Table II due to the high number of turns to obtain the highinductance L. Note that the core loss at P1 is very small due to the small current ripple as shown in Fig.
13(a). On the other hand, when %ZL is reduced to 0.04% to operate the inverter completely in DCM, theconduction loss of the semiconductor greatly increases due to the high current ripple as shown in Fig.
13(e). Nevertheless, the switching loss and the winding loss decrease due to the elimination of the recovery loss and the small numbers of winding turns. Furthermore, the maximum error between the calculated value and the experimental result is 3.9%. This small error enables the maximum power densityof the gird-tied inverter with an acceptable efficiency to be achieved by the evaluation of the overall
volume and loss [12].

V. Conclusion
When the grid-tied inductor was minimized by reducing the inductor impedance, the disturbanceeffects increased highly in the CCM operation, which distorted the grid current. On the other hand, inthe DCM operation, the nonlinearity occurred in the disturbance response which resulted in the natural
decrease in the disturbance gain at light load. By utilizing this DCM nonlinearity in the disturbance
response, the grid current THD was maintained below 5% over wide load range even when the inductor
impedance is minimized to 0.04%. However, another DCM nonlinearity occurred in the current command response, which made the open loop gain of DCM much lower than CCM. Therefore, the circuitparameter-independent DCM nonlinearity compensation for the current command response was proposed by utilizing the duty ratio at the previous calculation period.
In the future work, the current control of the mixed-current-mode between CCM and DCM will be
investigated in order to minimize the inductors without worsening the efficiency.

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