Multi-level Inverter with H-bridge Clamp Circuit
for Single-Phase Three-Wire Grid Connection
Suitable for Super-junction/SiC MOSFET
Yuichi Noge

Jun-ichi Itoh

Department of Electrical engineering
Nagaoka University of Technology
Niigata, Japan
noge@stn.nagaokaut.ac.jp

Department of Electrical engineering
Nagaoka University of Technology
Niigata, Japan
itoh@vos.nagaokaut.ac.jp

Abstract—A multilevel inverter with H-bridge clamp circuit is
proposed for single-phase three-wire (1P3W) utility connected
applications such as PV system. The proposed inverter consists of
two n-level inverters and a H-bridge clamp circuit. The proposed
inverter features high compatibility with next generation
semiconductors because the uses of a high voltage H-bridge
clamp circuit at grid frequency switching. The proposed inverter
requires only 12 controllable switches to obtain a 5-level output
voltage. In conventional multi-level converters with grounded
neutral point of the DC-bus, 16 switches are required. The
control strategy is discussed in this paper. Moreover, a numericalparameter design method is considered and then verified bysimulation. Finally, conduction loss of the clamp circuit is shown
lower than that comparing with the conventional active neutral
point clamped (ANPC) inverter using Super-junction MOSFET
or SiC MOSFET.

On the other hand, a multi-level inverter has studied apply
to three-phase grid connected systems for efficiency
improvement [6], [7]. A n-level inverter can reduce the voltage
stress of a switching device to 1/(n-1) of the DC bus voltage.
However, a n-level inverter requires 2(n-1) switches per leg. As
a result, the cost for semiconductors and controller becomes
higher. Thus, the cost reduction of the multi-level inverter is
especially important for home appliance. The ANPC inverter
has been proposed [8]. The ANPC requires less high frequency
switching devices and the controller is simple. However, thenumber of the switching devices is as same as conventional
multi-level inverter. Therefore, to decrease the number of theswitching devices, the shared active stacked NPC (SASNPC)
inverter was proposed [9]. The SASNPC inverter consists ofunified clamp circuit to reduce the number of switching
devices. In Ref. [9], the SASNPC inverter is only discussed fora three-phase three-level operation. Furthermore, all of theswitching devices including the high voltage (Vdc) clamp circuit
are operated in carrier frequency. Therefore, the switching loss
is high.

KeywordsMulti-level inverter, Single-phase three-wire(1P3W) connection, SiC MOSFET, Photovoltaic(PV) systems,
Transformerless, Active neutral point clamped (ANPC).

I.

INTRODUCTION

Recently, the grid connected photovoltaic(PV) system is
becoming more popular. The grid connected inverter is an
important part in this PV system. A nonisolated inverter has
advantages such as isolating transformerless and highefficiency [1]. A single-phase two-wire (1P2W) connection isused for home appliance. There is a common mode leakage
current flows through the parasitic capacitor between the PV
and the ground by H-bridge inverters at three-level operation.
Several circuit topologies have proposed to avoid this issue asshown in Ref. [2], [3]. For using these topologies, a common
mode voltage is kept in constant at every switching state.
However, some additional switches are used on these
topologies. A single-phase three-wire (1P3W) connection iscommonly used in Japan. Generally, a H-bridge inverter withneutral point grounded DC bus configuration is applied toeliminate the common mode current [4], [5]. Therefore, using
the 1P3W connection, the common mode current can beeliminated. In addition, a three-level line-to-line output voltage
and a safety improvement due to grounded DC bus can beachieved.
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In this paper, a multi-level inverter topology with H-bridge
clamp circuit for a 1P3W connection is presented. The
proposed inverter requires only 12 switches at a 5-level
construction. It is lesser than any other type of multi-level
topologies which uses 16 switches. In addition, the proposed
inverter can be expanded for 2n-1 level variations using two
pair of n-level inverters. Furthermore, the H-bridge clamp
circuit is operated in the grid frequency without switchinglosses. The features of the proposed circuit and the control
strategy are described. In addition, the parameter design
method is considered and verified in simulation. Finally, theconduction loss of the clamp circuit is confirmed lower thanthat comparing with the conventional ANPC inverter using
Super-junction MOSFET or SiC MOSFET.
II.

PROPOSED CIRCUIT

A. SASNPC and ANPC inverter
Fig.1 shows a three-phase three-level SASNPC inverter.
The basic idea of this topology is to share DC bus with

switching devices. The voltage rating of the output clamp
circuit is equaled to the DC bus.
Fig.2 shows the circuit configuration of a 2n-1 level ANPC
inverter applied in 1P3W grid. This inverter can use 8 switches
as the clamp circuit. The voltage rating of the clamp circuit is
1/2Vdc.
B. Proposed inverter
Fig.3 (a) shows a 2n-1 level construction of the proposed
inverter. The proposed inverter consists of two n-level DC side
inverters and H-bridge clamp circuit. The clamp circuit iscomplementary to switch at the grid frequency. Thus, theswitching loss is very low in the clamp circuit.

U

n

n

III.

n-levelinvertern-levelinverterClamp circuit

Figure 2. Active neutral point clamped (ANPC) multi-level inverter

n-levelinverter

CONTROL STRATEGY

Table 2 indicates the switching conditions and the output
voltages of the proposed 5-level inverter. For example, in the
sector I of Fig.4, the output voltage of the U phase is +Vdc/4 or
0. The switching pattern No, 2~4 is used in sector I. Using No,
3 and 4, the flying capacitor C1 can be charged or discharged

Switch(Carrier freq.)nFigure 1. Three-phase three-level SASNPC inverter

A. PWM strategy
Fig.4 shows the voltage waveforms of the proposed 5-level
inverter. The upper and lower 3-level FC inverter is used in the
PWM region. In the upper inverter, +Vdc/2 to 0 patterns areused. In the lower inverter, 0 to -Vdc/2 patterns are used. The
180degree phase shift carrier modulation is applied to each
inverter. The instantaneous magnitude of the reference signal(Vu*, Vw*) is compared with the carrier signal. The clamp circuit(S1u, S2u, S1w, S2w) are switched complementary with U and W
phase at grid frequency.

TABLE I.

W

Clamp circuit

Fig.3 (b) shows a 5-level model of the proposed inverter
where 3-level flying capacitor type (FC) used as a DC side
inverter. Using the 3-level FC inverter, the voltage balance offlying capacitors can be controlled simply by using 180degree
phase shift modulation.
Table 1 shows a comparison among the diode clamped(DCLP), FC, ANPC and proposed inverter at 5-level model.
All devices are standardized by 1/4Vdc voltage rating becauseof 5-level operation. The largest advantage of the proposed
inverter is that the proposed inverter can reduce the number ofthe switches and capacitors. The actual number of theswitching devices becomes 12, which is 3/4 of the conventional
5-level inverter. Note that the voltage rating of the clamp
circuit becomes full Vdc because the clamp circuit is connected
to line-to-line grid voltage.

V

COMPARISON OF THE DCLP, FC, ANPC ANDPROPOSED INVERTER

Proposed

ANPC

DCLP

FC

8

8

16

16

16 (8)*

0

0

0
2

24
0

0
12 (6)*

Switch16 (4)*(Grid freq.)
Diode0
Flying Capacitor
2*Actual number of devices

n-levelinverterClamp circuit
(a)
S1

C1

S2
L1

S3

Vdc

S4

S1u

S1w

U

W

S5

C2

S6

Vu

Vw
S2u

S2w

L2

S7
S8

(b)
Figure 3. Circuit configuration of proposed multilevel inverter for
single-phase three-wire utility connected system. (a) Proposed H-bridge
clamped inverter. (c) Proposed H-bridge clamped inverter at 5-level
configuration

to control the voltage. The charge and discharge patterns areequally generated in a single carrier period. Same output
current direction in each phase is not allowed. If U phasecurrent is positive, W phase current should be negative.
B. Control block diagram
Fig.5 shows the grid current controller of the proposed
inverter. The output current command iu* and iw* are received
from external MPPT controller. The output currents arecontrolled by two independent PI regulators which areconnected to each phase. Then, the grid voltages vu and vw arecompensated by adding the detected value after the PI
regulators. The output current polarity is detected by “sign”
function. For example, if U phase current is positive, the Uphase output voltage command is connected to the upper
modulator. On the other hand, the W-phase output voltage
command is connected to the lower modulator.
IV.

PARAMETER DESIGN METHOD

A. Inductor (L1, L2)
When the switching frequency is higher than the input
frequency, the fundamental component of the inductor voltage
is assumed to be constant during a switching cycle. The current
ripple becomes the highest value at modulation ratio =0.5.
Then, the relationship between the inductor Ln and the input
current ripple iin can be expressed asiin  Vt
Ln  V[H ] (2)iinwhere V is the output voltage ripple of the inverter, t is theswitching period of the inverter. The V becomes 1/8Vdc at
=0.5. The t becomes 1/4fs due to the phase shift modulation.
Consequently, the Ln can be expressed as
TABLE II.

Phase

U

W

Vdc/2
Vdc/4
Vdc/4
0
0
-Vdc/4-Vdc/4-Vdc/2
Vdc/2
Vdc/4
Vdc/4
0
0
-Vdc/4-Vdc/4-Vdc/2

No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

Outputcurrent
direction

Positive

Negative

Positive

Negative

III IV

V

VI

Vu*

0

t

Vw*

Vdc/4
Vdc/2
S1u

t

S2u

t

S1w

t

S2w

t
PWM region

Figure 4. Operation of internal inverter and clamp switches
iu*+

PI

+

-

+
vu

iu
iw*+

PI

+

iw

MUX

Upper
modulator

S1,S2,S3,S4
S1u,S2w

sign
MUX

+
vw

Lower
modulator

S2u,S1w
S5,S6,
S7,S8

Figure 5. Control block diagram

SWITCHING CONDITIONS AND OUTPUT VOLTAGES

Flying capacitor
C1
ChargeDischarge
ChargeDischarge-

II+Vdc/4t[A] (1)Ln

Eq.1 can be modified to

OutputvoltageI+Vdc/2

C2
ChargeDischarge
ChargeDischarge
-

S1
ON
ON
OFF
OFF
x
x
x
x
ON
ON
OFF
OFF
x
x
x
x

Upper
S2
S3
ON OFFOFF ONON OFFOFF ON
x
x
x
x
x
x
x
x
ON OFFOFF ONON OFFOFF ON
x
x
x
x
x
x
x
x

Switching condition ("x"= not applicable)
InverterClamp circuit
Lower
U
W
S4
S5
S6
S7
S8
S1u
S2u S1w S2w
OFF
x
x
x
x
OFF
x
x
x
x
ON OFF OFF ON
ON
x
x
x
x
ON
x
x
x
x
x
ON
ON OFF OFFx
ON OFF ON OFF
OFF ONON OFFx
OFF ON OFF ONx
OFF OFF ON
ON
OFF
x
x
x
x
OFF
x
x
x
x
OFF ONON OFF
ON
x
x
x
x
ON
x
x
x
x
x
ON
ON OFF OFFx
ON OFF ON OFF
ON OFF OFF ONx
OFF ON OFF ONx
OFF OFF ONON1
1
Ln  Vdc[ H ] (3)84i  f s

B. Flying capacitor (C1, C2)
The output voltage variations of the proposed inverter are±Vdc/2, ±Vdc/4, and 0. Note that ±Vdc/4 levels are outputtedthrough the flying capacitor Cn. In addition, the all output
current flows through the Cn at Vn*=±Vdc/4. In this case, theoutput current in at the Vn*=±Vdc/4 can be decided by1
Vm sin t  Vdc[V ] (4)4Vin  im sin t  im dc [ A] (5)4Vm
Consequently, the maximum voltage ripple vn of Cn isgiven by

Vu

0
-100

Vw

Grid current [A]

Iu

20
0
-20

Iw

U phase output voltage [V]
100
0
-100
W phase output voltage [V]
100
0
-100
Flying capacitor (C1) voltage [V]V
1Cn  im dc 
[ F ] (6)4Vm 2v  f s
Table 3 shows the designed parameters which arecalculated by (3) and (6).

V.

Grid voltage [V]100

SIMULATION AND EXPERIMENTAL RESULTS

Fig 6 (a) shows the simulation result of the proposed 5level inverter at 50Hz grid frequency. The grid voltage is 200V
and the output power is 4kW. Clean sinusoidal input current
waveform is obtained, and the 5-level output voltage can beobserved.
Fig. 6 (a) and (b) show the enlarged waveforms to verify
the validity of the parameter design method shown in chapter
IV. The output current ripple is in good agreement withdesigned value (iu=1.41A). However, the flying capacitor
voltage is measured in 10.0V, which is 1.25V higher than thedesigned value. The reason of the variation is a phase shift of
the input current depends on the output inductor. This variation
causes error of (5).
Fig. 7 shows the step response of the output current. The
output current command Iu* and Iw* are step changed from
0.5p.u. to 1.0p.u. at 5ms. The current over shoot is suppressedin 2.0ms. The voltage ripple of the flying capacitor is as sameas Fig. 6.
Fig. 8 shows the step response of the grid voltage
fluctuation. The grid voltage Vu and Vw are step changed from
1.0p.u. to 0.8p.u. at 5ms. The current fluctuation is suppressedin 1.5ms. The voltage ripple of the flying capacitor is different
from nominal value due to Vm of (5). The current ripple of theflying capacitor is inversely proportional to the Vm. In this case,the voltage ripple of the flying capacitor is increased to 10.9V.

95

8.75V

90
85
0

10
Time [ms]

5

15

20

(a)
Output current ripple (Iu) [A]
9.0

1.41A

8.0
7.0
6.0

50ms/div(b)
Figure 6. Operating waveforms. (a) Waveforms of inverter output andvoltage ripple of the Flying capacitor (C1). (b) Waveform of inverter
output current ripple.
Grid voltage [V]

Vu

100
0
-100

Vw

Grid current [A]

Iu

Iu *

20
0
-20

2.0ms

Iw *

U phase output voltage [V]

Iw

100
0
-100
W phase output voltage [V]
100
0
-100
Flying capacitor (C1) voltage [V]
95

8.75V

90

TABLE III.
Rated power
DC bus voltage
Grid voltage
Grid frequency
Grid current

PARAMETERS AND CONDITIONS
4kW
350V
200V
50Hz
20A

Inductor
Flying capacitor
Carrier frequency
Output current ripple
FC voltage ripple

387mH
50mF
20kHz
5%
10%

85
0

5

10
Time [ms]15

20

Figure 7. Step change of the output current command. (0.5p.u. to
1.0p.u. at 5ms)

Grid voltage [V]

Vu

100
0
-100

Voltage and current
detection board

Vw

Grid current [A]Digital controller

Iu

20
0
-20

1.5ms

Iw

Main circuit

U phase output voltage [V]Inductor

100

AC
output0

DC input-100

Gate drive unit

W phase output voltage [V]100

Figure 9. Experimental setup

0-100
Flying capacitor (C1) voltage [V]Capacitor voltage vC2[50V/div]
Output Voltage vuo [100V/div]

10.9V

95
90

0

85
0

5

10
Time [ms]

15

20

0

Figure 8. Step change of the grid voltage. (1.0p.u. to 0.8p.u. at 5ms)

Fig.9 and table 4 shows a prototype. It is conducted tofurther evaluate the validity of the proposed circuit.
Fig.10 shows the experimental result of the proposed 5level inverter at 50Hz output frequency. The line-to-line output
voltage is 200V and the output power is 750W. Clean
sinusoidal output current waveform is obtained, and the 5-level
output voltage can be observed. The flying capacitor voltage
VC2 is kept constant at 75V (1/4 Vdc). The efficiency of the
proposed inverter is 98.7%, which is measured by WT1600
from Yokogawa Electric.
VI.

EFFECT OF APPLYING SUPER-JUNCTION AND SIC
MOSFETFig.11 shows the on-resistance index [m/cm2] of next
generation semiconductors [10]-[15]. The on-resistance of thenormal Silicone devices is decreased in low voltage region. It is
suitable for a low voltage multi-level inverter. On the other
hand, on-resistance is drastically increased in the high voltage
region. These devices are applied to clamp circuit of the
proposed and ANPC inverter. The conduction loss of the clamp
circuit affects significantly in efficiency. However, the superjunction MOSFET can be used at 600V or more voltage rating.
It has lower on-resistance index than 300V normal Si devices.
Furthermore, the on-resistance of the 600V class 4H-SiC
MOSFET is close to the 300V class due to a limitation ofchannel resistance (Rch) and contact resistance (Rc). As a result,conduction loss of the proposed inverter is to be less than the
ANPC inverter for using the same total chip size of clamp
circuit.
In this section, the proposed inverter is compared with a
ANPC inverter. The highest efficiency in PV grid connected
application can be achieved by using ANPC inverter comparedwith DCLP and FC [7]. The operation of the DC side low
voltage inverter in the proposed inverter is exactly the same

Output current iu [5A/div]

0[5ms/div]

Figure 10. Experimental results
TABLE IV.
SPECIFICATION OF EXPERIMENTAL SETUP
Output power
750W
Load
25j
DC bus voltage
300V
Flying capacitor
14mF
Output voltage
200V
Carrier frequency
20kHz
Grid frequency
50Hz
Output current
3.9A
Controller
Switching devices
DSP
C6713
Inverter circuit
H5N2007FN
FPGA
APA300Clamp circuit
IPW65R070C6

operation as the ANPC. However the clamp circuit
configuration is different. Therefore, the conduction losses
from the two inverters are calculated by using the same total
chip size of clamp circuit. The on-resistance index is shown
below. Si super-junction MOSFET (300V, 5.0m/cm2, 600V,
7.9m/cm2) and SiC MOSFET (300V, 1.5m/cm2, 600V,
1.7m/cm2) is used in calculation.
Fig. 12(a) shows the conduction loss of clamp circuitaccording to the total chip size of clamp circuit using Si
devices. In the case of same total chip size, the clamp circuit
conduction loss of the proposed inverter is 20.7% less than
ANPC.
Fig. 12(b) shows the case of SiC MOSFET. The clamp
circuit conduction loss of the proposed inverter is 42.6% lessthan ANPC. .
VII. CONCLUSION
A multilevel inverter with H-bridge clamp circuit is
proposed for single-phase three-wire utility connected

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On-resistance index [m/cm2][1]

Clamp circuit

Proposed

Super-junction
Si MOSFET

ANPC

Low voltage part ofproposed and ANPC

10.0

IGBT

1.0
4H-SiClimited by Rch and Rc
Si

0.1
10

4H-SiC

100

GaN

1000

Device voltage rating [V]10000

Figure 11. On-resistance index of Si, SiC and GaN semiconductors.
(Ref. [10]-[12])2.0Conduction loss [%]REFERENCES

100.0

1.5

ANPC
1.0
0.5

Proposed
0.0
1.0

2.0
3.0
4.0
5.0
Total chip size of clamp circuit [cm2]
(a)

0.5

Conduction loss [%]applications. The proposed inverter requires only 12
controllable switches to obtain a 5-level output voltage. In thecase of conventional multi-level converters with grounded
neutral point of the DC-bus, 16 switches are required. The
control strategy has been evaluated. Moreover, a numericalparameter design method is considered and verified bysimulation and experiment. Finally, comparing to theconventional ANPC inverter, the conduction loss of the clamp
circuit can be reduced by 20.7% with Super-junction MOSFET,
and on the other hand, the conduction loss is reduced by 42.6%
with SiC MOSFET.

0.4

ANPC
0.3

0.2
0.1

Proposed

0.0

1.0

2.0
3.0
4.0
5.0
Total chip size of clamp circuit [cm2](b)Figure 12. Total chip size of clamp circuit for conduction loss comparedwith ANPC. (a) 600V Super-junction Si-MOSFET[12] is used for
proposed inverter and 300V Si-MOSFET is used for ANPC. The clamp
circuit conduction loss of the proposed inverter is 20.7% less than
ANPC. (b) Theoretical limitation value of 600V and 300V 4H-SiC
MOSFET are used for each inverter. The clamp circuit conduction lossof the proposed inverter is 42.6% less than ANPC.