SRV05-4
ESD Protection Diode Array
Low Clamping Voltage

The SRV05−4MR6 surge protection is designed to protect highspeed data lines from ESD, EFT, and lighting.
Featureswww.onsemi.com• Protects 4 I/O Lines• Low Working Voltage: 5 V• Low Clamping Voltage• Low Capacitance (<5 pF) for High Speed Interfaces• Transient Protection for High Speed Lines to:

LOW CAPACITANCE
SURGE PROTECTION ARRAY
300 WATTS PEAK POWER
6 VOLTS

IEC61000−4−2 (ESD) ±15 kV (air), ±8 kV (contact)
IEC61000−4−4 (EFT) 40 A
IEC61000−4−5 (Lightning) 12 A
• TSOP−6 is Footprint Compatible with SOT−23 6 Lead,
SC−59 6 Lead and SC−74• UL Flammability Rating of 94 V−0• This is a Pb−Free Device

PIN CONFIGURATION
AND SCHEMATIC

Typical Applications• High Speed Communication Line Protection• USB 1.1 and 2.0 Power and Data Line Protection• Digital Video Interface (DVI)• Monitors and Flat Panel Displays

I/O 1

6 I/O

VN 2

5 VP

I/O 3

4 I/O

6
1
TSOP−6CASE 318G
PLASTICMAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
RatingSymbol

Value

Unit

Ppk

300

W

Operating Junction Temperature Range

TJ−55 to +125

°C

Storage Temperature Range

Tstg−55 to +150

°C

Lead Solder Temperature −Maximum (10 Seconds)

TL

260

°C

Human Body Model (HBM)
Machine Model (MM)IEC 61000−4−2 Air (ESD)
IEC 61000−4−2 Contact (ESD)

ESD

16000
400
30000
30000

V

IEC 61000−4−4 (5/50 ns)

EFT

40

A

IEC 61000−4−5 (8 x 20 ms)

−

12

A

Peak Power Dissipation
8 x 20 ms @ TA = 25°C (Note 1)

MARKING DIAGRAM

See Application Note AND8308/D for further description ofsurvivability specs.

M

Stresses exceeding those listed in the Maximum Ratings table may damage thedevice. If any of these limits are exceeded, device functionality should not beassumed, damage may occur and reliability may be affected.
1. Non−repetitive current pulse per Figure 5 (Pin 5 to Pin 2)

63

G

G

63 = Specific Device CodeM = Date CodeG = Pb−Free Package(Note: Microdot may be in either location)*Date Code orientation may varydepending upon manufacturing location.

ORDERING INFORMATION
Device
SRV05−4MR6T1G

Package

Shipping

TSOP−6 3000/Tape & Reel
(Pb−Free)†For information on tape and reel specifications,
including part orientation and tape sizes, pleaserefer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2011

November, 2017 − Rev. 3

1

Publication Order Number:
SRV05−4/D

SRV05−4
ELECTRICAL CHARACTERISTICSI(TA = 25°C unless otherwise noted)
SymbolIF

Parameter

IPP

Maximum Reverse Peak Pulse Current

VC

Clamping Voltage @ IPP

VRWM

Working Peak Reverse Voltage

VC VBR VRWM

IR

Maximum Reverse Leakage Current @ VRWM

VBR

Breakdown Voltage @ IT

IT

Test Current

IF

Forward Current

VF

Forward Voltage @ IF

Ppk

Peak Power Dissipation

C

Capacitance @ VR = 0 and f = 1.0 MHz

V

IR VF
IT

IPP

Uni−Directional*See Application Note AND8308/D for detailed explanations ofdatasheet parameters.

ELECTRICAL CHARACTERISTICS (TJ=25°C unless otherwise specified)Parameter

SymbolConditions

Min

Typ

Max

Unit

5.0

V

Reverse Working Voltage

VRWM(Note 2)

Breakdown Voltage

VBR

IT=1 mA, (Note 3)

Reverse Leakage Current

IR

VRWM = 5 V

5.0

mA

Clamping Voltage

VC

IPP = 1 A (Note 4)

12.5

V

Clamping Voltage

VC

IPP = 5 A (Note 4)

17.5

V

Junction Capacitance

CJ

VR = 0 V, f=1 MHz between I/O Pins and GND

3.0

5.0

pF

Junction Capacitance

CJ

VR = 0 V, f=1 MHz between I/O Pins

1.5

3.0

pF

Clamping Voltage

VC

Per IEC 61000−4−2 (Note 5)

6.0

V

Figure 1 and 2

V

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Productperformance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Surge protection devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal or greaterthan the DC or continuous peak operating voltage level.
3. VBR is measured at pulse test current IT.
4. Non−repetitive current pulse per Figure 5 (Any I/O Pin to Ground)
5. For test procedure see Figures 3 and 4 and Application Note AND8307/D.

Figure 1. ESD Clamping Voltage Screenshot
Positive 8 kV Contact per IEC61000−4−2

Figure 2. ESD Clamping Voltage Screenshot
Negative 8 kV Contact per IEC61000−4−2

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2

SRV05−4
IEC61000−4−2 Waveform

IEC 61000−4−2 Spec.

Ipeak

Level

Test Voltage (kV)First Peak
Current(A)

Current at
30 ns (A)Current at
60 ns (A)

1

2

7.5

4

2

2

4

15

8

4

3

6

22.5

12

6

4

8

30

16

8

100%
90%

I @ 30 ns
I @ 60 ns
10%tP = 0.7 ns to 1 ns

Figure 3. IEC61000−4−2 Spec
DeviceESD Gun

Under

Oscilloscope

Test

50 W

50 W

Cable

Figure 4. Diagram of ESD Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.

systems such as cell phones or laptop computers it is notclearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in theform of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates thesescreenshots and how to interpret them please refer toAND8307/D.

ESD Voltage Clamping

For sensitive circuit elements it is important to limit thevoltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since theIEC61000−4−2 was written as a pass/fail spec for larger% OF PEAK PULSE CURRENT

100

PEAK VALUE IRSM @ 8 ms

tr

90

PULSE WIDTH (tP) IS DEFINEDAS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms

80
70
60

HALF VALUE IRSM/2 @ 20 ms

50
40
30

tP

20
10
0

0

20

40
t, TIME (ms)60

Figure 5. 8 x 20 ms Pulse Waveform

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380

SRV05−4
TYPICAL PERFORMANCE CURVES(TJ = 25°C unless otherwise noted)

30

4.5
4.0

CLAMPING VOLTAGE (V)JUNCTION CAPACITANCE (pF)

5.0

3.5
3.0

I/O−Ground2.5
2.0
I/O lines

1.5
1.0
0.5
0.0

0

1

2

3

4

25
20
15
10
5
0

5

0

2

4

6

8

10

12

PEAK PULSE CURRENT (A)VBR, REVERSE VOLTAGE (V)Figure 7. Clamping Voltage vs. Peak Pulse Current(8 x 20 ms Waveform)

Figure 6. Junction Capacitance vs Reverse Voltage

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4

SRV05−4
APPLICATIONS INFORMATION
Option 2
Protection of four data lines with bias and power supply
isolation resistor.

The new SRV05−4MR6 is a low capacitance surge
protection diode array designed to protect sensitiveelectronics such as communications systems, computers,
and computer peripherals against damage due to ESD eventsor transient overvoltage conditions. Because of its low
capacitance, it can be used in high speed I/O data lines. The
integrated design of the SRV05−4MR6 offers surge rated,
low capacitance steering diodes and a surge protection diodeintegrated in a single package (TSOP−6). If a transientcondition occurs, the steering diodes will drive the transientto the positive rail of the power supply or to ground. The
surge protection device protects the power line against
overvoltage conditions to avoid damage to the power supply
and any downstream components.

I/O 1
I/O 2
VCC
1

6

2

5

3

4

10 k

I/O 3
I/O 4

SRV05−4MR6 Configuration Options
The SRV05−4MR6 is able to protect up to four data lines
against transient overvoltage conditions by driving them toa fixed reference point for clamping purposes. The steering
diodes will be forward biased whenever the voltage on theprotected line exceeds the reference voltage (Vf or VCC +Vf). The diodes will force the transient current to bypass thesensitive circuit.
Data lines are connected at pins 1, 3, 4 and 6. The negativereference is connected at pin 2. These pins must beconnected directly to ground by using a ground plane tominimize the PCB’s ground inductance. It is very importantto reduce the PCB trace lengths as much as possible tominimize parasitic inductances.

The SRV05−4MR6 can be isolated from the power supply
by connecting a series resistor between pin 5 and VCC. A
10 kW resistor is recommended for this application. This
will maintain a bias on the internal surge protection andsteering diodes, reducing their capacitance.
Option 3
Protection of four data lines using the internal surge
protection diode as reference.
I/O 1
I/O 2

Option 1
Protection of four data lines and the power supply using
VCC as reference.
I/O 1
I/O 2

1

6

2

5

3

4

NC

I/O 3
I/O 4
1

6

2

5

3

4

In applications lacking a positive supply reference or
those cases in which a fully isolated power supply isrequired, the internal surge protection can be used as thereference. For these applications, pin 5 is not connected. In
this configuration, the steering diodes will conduct
whenever the voltage on the protected line exceeds theworking voltage of the surge protection plus one diode drop
(Vc = Vf + VRWM).

VCC

I/O 3
I/O 4

For this configuration, connect pin 5 directly to thepositive supply rail (VCC), the data lines are referenced tothe supply voltage. The internal surge protection diodeprevents overvoltage on the supply rail. Biasing of thesteering diodes reduces their capacitance.

ESD Protection of Power Supply Lines
When using diodes for data line protection, referencing to
a supply rail provides advantages. Biasing the diodes
reduces their capacitance and minimizes signal distortion.
Implementing this topology with discrete devices does havedisadvantages. This configuration is shown below:

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5

SRV05−4PowerSupplyIESDpos

VCC

Protected Data Line
DeviceEven with good board layout, some disadvantages are stillpresent when discrete diodes are used to suppress ESD
events across datalines and the supply rail. Discrete diodes
with good transient power capability will have larger die andtherefore higher capacitance. This capacitance becomesproblematic as transmission frequencies increase. Reducing
capacitance generally requires reducing die size. These
small die will have higher forward voltage characteristics attypical ESD transient current levels. This voltage combinedwith the smaller die can result in device failure.
The ON Semiconductor SRV05−4MR6 was developed toovercome the disadvantages encountered when using
discrete diodes for ESD protection. This device integrates asurge protection diode within a network of steering diodes.

D1

IESDpos

D2
IESDneg

IESDneg

VF + VCC−VF

Looking at the figure above, it can be seen that when apositive ESD condition occurs, diode D1 will be forward
biased while diode D2 will be forward biased when anegative ESD condition occurs. For slower transientconditions, this system may be approximated as follows:
For positive pulse conditions:
Vc = VCC + VfD1
For negative pulse conditions:
Vc = −VfD2
ESD events can have rise times on the order of somenumber of nanoseconds. Under these conditions, the effectof parasitic inductance must be considered. A pictorial
representation of this is shown below.

D1

D3

D5

D7

D2

D4

D6

D8

0
Power
SupplyFigure 8. SRV05−4MR6 Equivalent Circuit

IESDpos

During an ESD condition, the ESD current will be driven
to ground through the surge protection diode as shown
below.

VCC
Protected
DeviceD1

IESDpos

D2

VC = VCC + Vf + (L diESD/dt)
IESDneg

IESDneg

Data LinePower
SupplyVCC
D1
Protected
Device

VC = −Vf − (L diESD/dt)

An approximation of the clamping voltage for these fasttransients would be:
For positive pulse conditions:
Vc = VCC + Vf + (L diESD/dt)
For negative pulse conditions:
Vc = −Vf – (L diESD/dt)
As shown in the formulas, the clamping voltage (Vc) not
only depends on the Vf of the steering diodes but also on the
L diESD/dt factor. A relatively small trace inductance canresult in hundreds of volts appearing on the supply rail. This
endangers both the power supply and anything attached tothat rail. This highlights the importance of good board
layout. Taking care to minimize the effects of parasitic
inductance will provide significant benefits in transient
immunity.

IESDpos

Data LineD2

The resulting clamping voltage on the protected IC willbe: Vc = VF + VRWM.
The clamping voltage of the surge protection diode isprovided in Figure 7 and depends on the magnitude of the
ESD current. The steering diodes are fast switching devices
with unique forward voltage and low capacitancecharacteristics.

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6

SRV05−4
TYPICAL APPLICATIONSUPSTREAM
USB PORT
VBUS

VBUS

VBUS

VBUS
D+

RT

D+

RT

D−

VBUS

GND

USB
Controller

D−

VBUS
SRV05−4MR6

CT CT

DOWNSTREAM
USB PORT

GND

VBUS
NUP2201DT1

VBUS

RT

D+

RT

D−
GND

CT CT

DOWNSTREAM
USB PORT

Figure 9. ESD Protection for USB Port

RJ45
Connector
TX+

TX+

TX−
TX−
PHY
Ethernet(10/100)

Coupling
Transformers

RX+

RX+

RX−
RX−
SRV05−4MR6
VCC
GND
N/C

N/C

Figure 10. Protection for Ethernet 10/100 (Differential mode)

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7

SRV05−4
R1
RTIP
R3

R2

RRING

T1

VCC

T1/E1
TRANCEIVER

SRV05−4MR6

R4
TTIP
R5

TRING

T2

Figure 11. TI/E1 Interface Protection

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8MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONSTSOP−6 3.00x1.50x0.90, 0.95P
CASE 318G
ISSUE W

DOCUMENT NUMBER:DESCRIPTION:

98ASB14888C

DATE 26 FEB 2024

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

TSOP−6 3.00x1.50x0.90, 0.95P

PAGE 1 OF 2

onsemi andare trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particularpurpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

© Semiconductor Components Industries, LLC, 2019www.onsemi.com

TSOP−6 3.00x1.50x0.90, 0.95P
CASE 318G
ISSUE WDATE 26 FEB 2024

GENERICMARKING DIAGRAM*XXXAYWGG

XXX MGG
1

1
IC
XXX = Specific Device CodeA
=Assembly Location
Y= YearW= Work Week
G
= Pb−Free Package

STANDARDXXX = Specific Device CodeM
= Date CodeG
= Pb−Free Package*This information is generic. Please refer to device data
sheet for actual part marking. Pb−Free indicator, “G”
or microdot “G”, may or may not be present. Some
products may not follow the Generic Marking.

STYLE 1:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAINSTYLE 2:
PIN 1. EMITTER 2
2. BASE 1
3. COLLECTOR 1
4. EMITTER 1
5. BASE 2
6. COLLECTOR 2

STYLE 3:
PIN 1. ENABLE
2. N/C
3. R BOOST
4. Vz
5. V in6. V out

STYLE 4:
PIN 1. N/C
2. V in
3. NOT USED
4. GROUND
5. ENABLE
6. LOADSTYLE 5:
PIN 1. EMITTER 2
2. BASE 2
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
6. COLLECTOR 2

STYLE 6:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. EMITTER
5. COLLECTOR
6. COLLECTORSTYLE 7:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. N/C
5. COLLECTOR
6. EMITTERSTYLE 8:
PIN 1. Vbus
2. D(in)
3. D(in)+
4. D(out)+
5. D(out)
6. GNDSTYLE 9:PIN 1. LOW VOLTAGE GATE
2. DRAIN
3. SOURCE
4. DRAIN
5. DRAIN
6. HIGH VOLTAGE GATESTYLE 10:
PIN 1. D(OUT)+
2. GND
3. D(OUT)−
4. D(IN)−
5. VBUS6. D(IN)+

STYLE 11:
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
6. DRAIN 1/GATE 2

STYLE 12:PIN 1. I/O
2. GROUND
3. I/O
4. I/O
5. VCC
6. I/OSTYLE 13:
PIN 1. GATE 1
2. SOURCE 2
3. GATE 2
4. DRAIN 2
5. SOURCE 1
6. DRAIN 1

STYLE 14:
PIN 1. ANODE
2. SOURCE
3. GATE
4. CATHODE/DRAIN
5. CATHODE/DRAIN
6. CATHODE/DRAINSTYLE 15:
PIN 1. ANODE
2. SOURCE
3. GATE
4. DRAIN
5. N/C
6. CATHODE

DOCUMENT NUMBER:DESCRIPTION:

98ASB14888C

STYLE 16:
PIN 1. ANODE/CATHODE
2. BASE
3. EMITTER
4. COLLECTOR
5. ANODE
6. CATHODESTYLE 17:
PIN 1. EMITTER
2. BASE
3. ANODE/CATHODE
4. ANODE
5. CATHODE
6. COLLECTOR

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

TSOP−6 3.00x1.50x0.90, 0.95P

PAGE 2 OF 2

onsemi andare trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particularpurpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

www.onsemi.com© Semiconductor Components Industries, LLC, 20192www.onsemi.com

onsemi,, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of theinformation, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or useof any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance mayvary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any licenseunder any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
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