GIGABIT ETHERNET CONSORTIUM
Clause 40
Physical Medium Attachment (PMA) Test Suite
Version 2.5
Technical Document

Last Updated: 20 May 2008 1:26:57 PM

Gigabit Ethernet Consortium
University of New Hampshire
InterOperability Laboratory

121 Technology Drive, Suite 2
Durham, NH 03824
Phone: +1-603-862-0090
Fax: +1-603-862-4181
http://www.iol.unh.edu/consortiums/ge(C) 2006 University of New Hampshire InterOperability Laboratory.

The University of New Hampshire
InterOperability Laboratory
TABLE OF CONTENTSTABLE OF CONTENTS ....................................................................................................... 2
MODIFICATION RECORD ............................................................................................... 3
ACKNOWLEDGMENTS ..................................................................................................... 4
INTRODUCTION ................................................................................................................... 5
GROUP 1: PMA ELECTRICAL SPECIFICATIONS ............................................... 7
TEST 40.1.1 – PEAK DIFFERENTIAL OUTPUT VOLTAGE AND LEVEL ACCURACY ......................... 8
TEST 40.1.2 – MAXIMUM OUTPUT DROOP ................................................................................... 9
TEST 40.1.3 – DIFFERENTIAL OUTPUT TEMPLATES.................................................................... 10
TEST 40.1.4 – MDI RETURN LOSS ............................................................................................. 11
TEST 40.1.5 – TRANSMITTER TIMING JITTER, FULL TEST (EXPOSED TX_TCLK) ............... 13
PART I – MASTER/SLAVE Jtxout MEASUREMENTS...................................................................................15
PART II – UNFILTERED AND FILTERED TX_TCLK JITTER (MASTER MODE).....................................16
PART III – UNFILTERED AND FILTERED TX_TCLK JITTER (SLAVE MODE).......................................18

TEST 40.1.6 – TRANSMITTER DISTORTION ................................................................................. 19
TEST 40.1.7 – TRANSMIT CLOCK FREQUENCY ........................................................................... 20
TEST 40.1.8 – COMMON-MODE OUTPUT VOLTAGE .................................................................... 21

GROUP 2: PMA RECEIVE TESTS ............................................................................... 22
TEST 40.2.1 – BIT ERROR RATE VERIFICATION ......................................................................... 23

TEST SUITE APPENDICES ............................................................................................. 25
APPENDIX 40.A – 1000BASE-T TRANSMITTER TEST FIXTURES ............................................... 26
APPENDIX 40.B – TRANSMITTER TIMING JITTER, NO TX_TCLK ACCESS................................. 41
APPENDIX 40.C – JITTER TEST CHANNEL .................................................................................. 46
APPENDIX 40.D – TRANSMITTER SPECIFICATIONS ..................................................................... 54
APPENDIX 40.E – RISE TIME CALCULATION .............................................................................. 56
APPENDIX 40.F – CATEGORY 5E CABLE TEST ENVIRONMENT ................................................... 57
APPENDIX 40.G – TRANSMITTER DISTORTION MEASUREMENT ................................................. 58
APPENDIX 40.H – TRANSMITTER DISTORTION RESEARCH ......................................................... 61

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MODIFICATION RECORD•

April 11, 2008 (Version 2.5)
Collin Sad•

March 5, 2006 (Version 2.4)
Jon Beckwith•

Added figure names for jitter tests.
Added Tests 40.1.6, 40.1.7 and Appendices F-H
Modified Test 40.2.1 to include a wider range of attenuation levels

March 31, 2004 (Version 2.0)
Jon Beckwith:•

Changed Test 40.1.1 to calculate percent difference for points A and B
Added copyright on cover page

November 22, 2004 (Version 2.1)
Jon Beckwith:•

Updated references to 802.3TM-2005.

January 20, 2005 (Version 2.2)
Jon Beckwith•

Added Test 40.1.8

February 2, 2006 (Version 2.3)
Jon Beckwith•

Updated Test 40.1.6 in accordance with 802.3ay
Updated Appendix 40.G

Added Tests 40.1.5, 40.2.1 and Appendices B-E.

Sep 19, 2003 (Version 1.2)
Mostly formatting changes, plus one technical typo fix
Andy Baldman:
Updated cover page to include consortium name, full test suite name, and new IOL logo
Reorganized document to put Table of Contents first
Revised and reorganized Introduction section
Changed referencing style to distinguish between internal/external references
Modified test numbers by removing subclause indicator (e.g. “40.6.1.1” became “40.1.1”)
All references to disturber voltage levels in Appendix 40.A now show correct values•

Jun 18, 2003 (Version 1.1)
Jon Beckwith:•

General formatting changes
Updated references to reflect latest standards
Added schematics for return loss jig and 8-pin modular breakout board

Oct 08, 1999 (Version 1.0)
Initial release

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ACKNOWLEDGMENTS
The University of New Hampshire would like to acknowledge the efforts of the following individuals in thedevelopment of this test suite.

Andy Baldman
Jon Beckwith
Adam Healey
Eric Lynskey
Bob Noseworthy
Matthew Plante
Gary Pressler
Collin Sad

University of New Hampshire
University of New Hampshire
University of New Hampshire
University of New Hampshire
University of New Hampshire
University of New Hampshire
University of New Hampshire
University of New Hampshire

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INTRODUCTIONThe University of New Hampshire’s InterOperability Laboratory (IOL) is an institution designed to improve theinteroperability of standards based products by providing an environment where a product can be tested against other
implementations of a standard. This particular suite of tests has been developed to help implementers evaluate the functionalityof the Physical Medium Attachment (PMA) sublayer of their 1000BASE-T products.
These tests are designed to determine if a product conforms to specifications defined in the IEEE 802.3 standard.
Successful completion of all tests contained in this suite does not guarantee that the tested device will operate with other devices.
However, combined with satisfactory operation in the IOL’s interoperability test bed, these tests provide a reasonable level ofconfidence that the Device Under Test (DUT) will function properly in many 1000BASE-T environments.
The tests contained in this document are organized in such a manner as to simplify the identification of information
related to a test, and to facilitate in the actual testing process. Tests are organized into groups, primarily in order to reduce setup
time in the lab environment, however the different groups typically also tend to focus on specific aspects of device functionality.
A three-part numbering system is used to organize the tests, where the first number indicates the clause of the IEEE 802.3
standard on which the test suite is based. The second and third numbers indicate the test’s group number and test number withinthat group, respectively. This format allows for the addition of future tests to the appropriate groups without requiring therenumbering of the subsequent tests.
The test definitions themselves are intended to provide a high-level description of the motivation, resources,
procedures, and methodologies pertinent to each test. Specifically, each test description consists of the following sections:PurposeThe purpose is a brief statement outlining what the test attempts to achieve. The test is written at the functional level.
References
This section specifies source material external to the test suite, including specific subclauses pertinent to the test
definition, or any other references that might be helpful in understanding the test methodology and/or test results. Externalsources are always referenced by number when mentioned in the test description. Any other references not specified by number
are stated with respect to the test suite document itself.
Resource Requirements
The requirements section specifies the test hardware and/or software needed to perform the test. This is generally
expressed in terms of minimum requirements, however in some cases specific equipment manufacturer/model information may
be provided.
Last Modification
This specifies the date of the last modification to this test.
Discussion
The discussion covers the assumptions made in the design or implementation of the test, as well as known limitations.
Other items specific to the test are covered here.
Test Setup
The setup section describes the initial configuration of the test environment. Small changes in the configuration should
not be included here, and are generally covered in the test procedure section, below.
Procedure
The procedure section of the test description contains the systematic instructions for carrying out the test. It provides a
cookbook approach to testing, and may be interspersed with observable results.
Observable Results
This section lists the specific observables that can be examined by the tester in order to verify that the DUT is operating
properly. When multiple values for an observable are possible, this section provides a short discussion on how to interpret them.
The determination of a pass or fail outcome for a particular test is generally based on the successful (or unsuccessful) detection ofa specific observable.
Possible Problems

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This section contains a description of known issues with the test procedure, which may affect test results in certain
situations. It may also refer the reader to test suite appendices and/or whitepapers that may provide more detail regarding theseissues.

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GROUP 1: PMA ELECTRICAL SPECIFICATIONS
Overview:
This group of tests verifies several of the electrical specifications of the 1000BASE-T Physical Medium
Attachment sublayer outlined in Clause 40 of the IEEE 802.3-2005TM standard.
Scope:All of the tests described in this section have been implemented and are currently active at the University of
New Hampshire InterOperability Lab.

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Test 40.1.1 – Peak Differential Output Voltage and Level Accuracy
Purpose: To verify correct transmitter output levels.
References:[1] IEEE Std 802.3-2005TM, subclause 40.6.1.1.2 - Test modes[2] Ibid., Figure 40-19 - Example of transmitter test mode 1 waveform[3] Ibid., subclause 40.6.1.1.3 - Test fixtures[4] Ibid., subclause 40.6.1.2.1 - Peak differential output voltage and level accuracy
Resource Requirements: Refer to appendix 40.A
Last Modification: January 17, 2005 (version 1.3)
Discussion:
Reference [1] states that all 1000BASE-T devices must implement four transmitter test modes. This test
requires the Device Under Test (DUT) to operate in transmitter test mode 1. While in test mode 1, the DUT shallgenerate the pattern shown in [2] on all four transmit pairs, denoted BI_DA, BI_DB, BI_DC, and BI_DD,
respectively.
In this test, the peak differential output voltage is measured at points A, B, C, and D as indicated in [2]while the DUT is connected to test fixture 1 defined in [3]. The conformance requirements for the peak differential
output voltage and level accuracy are specified in [4].
Note that the percent difference is measured for points A and B, while percent error is measured for points
C and D.
Test Setup: Refer to appendix 40.A
Procedure:
1. Configure the DUT so that it is sourcing the transmitter test mode 1 waveform.
2. Connect pair BI_DA from the MDI to test fixture 1.
3. Measure the peak voltage of the waveform at points A, B, C, and D.
4. For enhanced accuracy, repeat step 3 multiple times and average the voltages measured at each point.
5. Repeat steps 2 through 4 for pairs BI_DB, BI_DC, and BI_DD.
Observable Results:
a. The magnitude of the voltages at points A and B shall be between 670 and 820 mV.
b. The magnitude of the voltages at points A and B shall differ by less than 1%.
c. The magnitude of the voltage at point C shall not differ from 0.5 times the average of the voltage
magnitudes at points A and B by more than 2%.
d. The magnitude of the voltage at point D shall not differ from 0.5 times the average of the voltage
magnitudes at points A and B by more than 2%.
Possible Problems: None.

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Test 40.1.2 – Maximum Output Droop
Purpose: To verify that the transmitter output level does not decay faster than the maximum specified rate.
References:[1] IEEE Std 802.3-2005TM, subclause 40.6.1.1.2 - Test modes[2] Ibid., Figure 40-19 - Example of transmitter test mode 1 waveform[3] Ibid., subclause 40.6.1.1.3 - Test fixtures[4] Ibid., subclause 40.6.1.2.2 - Maximum output droop
Resource Requirements: Refer to appendix 40.A
Last Modification: September 14, 2003 (version 1.2)
Discussion:
Reference [1] states that all 1000BASE-T devices must implement four transmitter test modes. This test
requires the Device Under Test (DUT) to operate in transmitter test mode 1. While in test mode 1, the DUT shallgenerate the pattern shown in [2] on all four transmit pairs, denoted BI_DA, BI_DB, BI_DC, and BI_DD,
respectively.
In this test, the differential output voltage is measured at points F, G, H, and J as indicated in [2] while the
DUT is connected to test fixture 2 defined in [3]. The conformance requirements for the maximum output droop are
specified in [4].
Test Setup: Refer to test suite appendix 40.A
Procedure:
1. Configure the DUT so that it is operating in transmitter test mode 1.
2. Connect pair BI_DA from the MDI to test fixture 2.
3. Measure differential output voltage at points F, G, H, and J.
4. For enhanced accuracy, repeat step 3 multiple times and average the voltages measured at each point.
5. Repeat steps 2 through 4 for pairs BI_DB, BI_DC, and BI_DD.
Observable Results:
a. The voltage magnitude at point G shall be greater than 73.1% of the voltage magnitude at point F.
b. The voltage magnitude at point J shall be greater than 73.1% of the voltage magnitude at point H.
Possible Problems: None.

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Test 40.1.3 – Differential Output Templates
Purpose: To verify that the transmitter output fits the time-domain transmit templates.
References:[1] IEEE Std 802.3-2005TM, subclause 40.6.1.1.2 - Test modes[2] Ibid., Figure 40-19 - Example of transmitter test mode 1 waveform[3] Ibid., subclause 40.6.1.1.3 - Test fixtures[4] Ibid., Figure 40-6 - Normalized transmit templates as measured at MDI using transmit test fixture 1[5] Ibid., subclause 40.6.1.2.3 - Differential output templates
Resource Requirements: Refer to appendix 40.A
Last Modification: September 14, 2003 (version 1.2)
Discussion:
Reference [1] states that all 1000BASE-T devices must implement four transmitter test modes. This test
requires the Device Under Test (DUT) to operate in transmitter test mode 1. While in test mode 1, the DUT shallgenerate the pattern shown in [2] on all four transmit pairs, denoted BI_DA, BI_DB, BI_DC, and BI_DD,
respectively.
In this test, the differential output waveforms are measured at points A, B, C, D, F, and H as indicated in[2] while the DUT is connected to test fixture 1 defined in [3]. The various waveforms will be compared to thenormalized time domain transmit templates specified in [4]. The waveforms around points A and B are compared tonormalized time domain transmit template 1 after they are normalized to the peak voltage at point A. The
waveforms around points C and D are compared to normalized time domain transmit template 1 after they arenormalized to 0.5 times the peak voltage at point A. The waveforms around points F and H are compared tonormalized time domain transmit template 2 after they are normalized to the peak voltages at points F and H,
respectively.
The waveforms may be shifted in time to achieve the best fit. After normalization and shifting, thewaveforms around points A, B, C, D, F, and H shall fit within their corresponding templates, as specified in [5].
Test Setup: Refer to appendix 40.A
Procedure:
1. Configure the DUT so that it is operating in transmitter test mode 1.
2. Connect pair BI_DA from the MDI to test fixture 1.
3. Capture the waveforms around points A, B, C, D, F, and H.
4. For more thorough testing, repeat step 3 multiple times and accumulate a 2-dimensional histogram (voltage
and time) of each waveform. This is often referred to as a persistence waveform.
5. Normalize the waveforms around points A, B, C, and D and compare them with normalized time domaintransmit template 1. The waveforms may be shifted in time to achieve the best fit.
6. Normalize the waveforms around points F and H and compare them with normalized time domain transmit
template 2. The waveforms may be shifted in time to achieve the best fit.
7. Repeat steps 2 through 6 for pairs BI_DB, BI_DC, and BI_DD.
Observable Results:
a. After normalization, the waveforms around points A, B, C, and D shall fit within normalized time domaintransmit template 1.
b. After normalization, the waveforms around points F and H shall fit within normalized time domain transmit
template 2.
Possible Problems: None.

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Test 40.1.4 – MDI Return Loss
Purpose: To measure the return loss at the MDI for all four channels
References:[1] IEEE Std 802.3-2005TM, subclause 40.8.3.1 - MDI return loss
[2] Ibid., subclause 40.6.1.1.2 - Test modes
Resource Requirements:• RF Vector Network Analyzer (VNA)• Return loss test jig• Post-processing PC
Last Modification: September 14, 2003 (version 1.2)
Discussion:
A compliant 1000BASE-T device shall ideally have a differential impedance of 100Ω. This is necessary tomatch the characteristic impedance of the Category 5 cabling. Any difference between these impedances will resultin a partial reflection of the transmitted signals. Because the impedances can never be exactly 100Ω, and because
the termination impedance varies with frequency, some limited amount of reflection must be allowed. Return loss isa measure of the signal power that is reflected due to the impedance mismatch. Reference [1] specifies theconformance limits for the reflected power measured at the MDI. The specification states that the return loss must
be maintained when connected to cabling with a characteristic impedance of 100Ω ± 15%, and while transmitting
data or control symbols.

Test Setup:
Connect the devices as shown in Figure 40.1.4-1 using the test jig shown in Figure 40.1.4-2.

Figure 40.1.4-1: Return loss test setup

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Figure 40.1.4-2: Test Jig #2

Note that Test Jig #2 is a standard jig used by the IOL for various return loss tests. In 100Base-Tx PMD
testing, Port B is utilized to send IDLE to the DUT. Here, we do not need to send IDLE to the DUT, and thus, Port
B is not used. Also, because the network analyzer is connected to pins 1 and 2 of the 8-pin modular jack, four short
UTP cables (approximately 4” long) are needed in order to map the BI_DA, BI_DB, BI_DC, and BI_DD signals
from the DUT to the 1-2 pair of the test jig Port A. The effect of each of these cables is removed during calibrationof the Network Analyzer.
The specification states that the return loss must be maintained while transmitting data or control symbols.
Therefore, it is necessary to configure the DUT so that it is transmitting a signal meeting these requirements. The
test mode 4 signal specified in [2] is used in this case to approximate a valid 1000BASE-T symbol stream.

Procedure:
1. Configure the DUT so that it is operating in transmitter test mode 4.
2. Connect the BI_DA pair of the DUT to the reflection port of the network analyzer.
3. Calibrate the network analyzer to remove the effects of the test jig and connecting cable.
4. Measure the reflections at the MDI referenced to a 50Ω characteristic impedance.
5. Post-process the data to calculate the reflections for characteristic impedances of 85 and 115Ω.
6. Repeat steps 2 to 5 for the BI_DB, BI_DC, and BI_DD pairs.

Observable Results:
a. The return loss measured at each MDI pair shall be at least 16 dB from 1 to 40 MHz, and at least
10-20log10(f/80) dB from 40 to 100MHz when referenced to a characteristic impedance of 100Ω ± 15%.
Possible Problems: None.

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Test 40.1.5 – Transmitter Timing Jitter, FULL TEST (EXPOSED TX_TCLK)
Purpose:To verify that the DUT meets the jitter specifications defined in Clause 40.6.1.2.5 of IEEE 802.3.

References:[1] IEEE standard 802.3-2005TM, subclause 40.6.1.1.1 – Test channel[2] Ibid., subclause 40.6.1.1.2, figure 40-20 – Test modes[3] Ibid., subclause 40.6.1.1.3, figure 40-25 – Test fixtures[4] Ibid., subclause 40.6.1.2.5 – Transmitter Timing Jitter[5] Test suite appendix 40.6.A – 1000BASE-T transmitter test fixtures
Resource Requirements:• A DUT with an exposed TX_TCLK clock signal• A Link Partner device which also provides an exposed TX_TCLK• Digital storage oscilloscope, Tektronix CSA7404 or equivalent• (Optional) High-impedance differential probe, Tektronix P6248 or equivalent (2)• Jitter Test Channel as defined in [1]• 8-pin modular plug break-out board• 50 Ω coaxial cables, matched length• 50 Ω line terminations (6)Last Modification:

March 22, 2002 (Version 1.1)

Discussion:
The jitter specifications outlined in Clause 40.6.1.2.5 define a set of measurements and procedures that may
be used to characterize the jitter of a 1000BASE-T device. The clause defines multiple test configurations that serve
to isolate and measure different aspects of the jitter in the overall system. While the spec makes distinctions
between MASTER mode jitter and SLAVE mode jitter, additional distinctions are made between filtered andunfiltered jitter. Also, there are different timing references by which the jitter is determined depending on theconfiguration.
For the purpose of this test suite, a step-by-step procedure is outlined that will determine all MASTER andSLAVE mode jitter parameters for a particular DUT. The entire test is separated into three distinct sections in orderto minimize test setup complexity and facilitate understanding of the measurement methodology.
The purpose of the first section will be to measure Jtxout , which is defined as the peak-to-peak jitter on the
MDI output signal relative to the TX_TCLK while the DUT is operating in either Test Mode 2 (MASTER timingmode), or Test Mode 3 (SLAVE timing mode). This value is measured for each of the four MDI pairs, BI_DA,
BI_DB, BI_DC, and BI_DD for when the DUT is configured as MASTER, and when the DUT is configured as
SLAVE. This produces eight Jtxout values for a particular DUT.
The purpose of the second section will be to measure both the unfiltered and filtered peak-to-peak jitter on
the TX_TCLK itself, relative to an “unjittered reference”, while the DUT is configured as the MASTER and isoperating under normal conditions (i.e., linked to the Link Partner using a short piece of UTP). While the standard
does not provide any further definition for what exactly an “unjittered reference” is or how it is to be derived, for the
purposes of this test suite it is to be defined as the straight-line best fit of the zero crossings for any specific captureof the signal under test. Thus, the jitter for any particular edge is defined as the time difference between the actual
observed zero crossing time and the corresponding “ideal” crossing time. The setup for this section is relatively
straightforward, and is much less complicated than the setup required for the third and final section.
The third and most involved part of the test will measure both the unfiltered and filtered TX_TCLK jitterfor the case where the DUT is operating in SLAVE mode. Note that while the MASTER TX_TCLK jitter of theprevious section was defined with respect to an “unjittered reference”, the SLAVE TX_TCLK jitter of this section is

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instead defined with respect to the MASTER TX_TCLK. Thus in order to perform this test, both the DUT and the
Link Partner TX_TCLK’s must be simultaneously monitored with the DSO. In addition, the standard also requiresthat the DUT and Link Partner be connected by means of the Jitter Test Channel defined in [1], instead of the shortpiece of UTP used in the previous section.
Note that in order to perform these tests as specified in the standard, it is a requirement that the DUT
provide access to the TX_TCLK clock signal (which is not always the case). In addition, the test setup requires afunctioning Link Partner device that also provides access to the TX_TCLK. While access to the TX_TCLK signal isrelatively straightforward and easy to provide on evaluation boards and prototype systems, it can become quite
impractical in more complicated systems. In the case where no exposed TX_TCLK signal is available, it may bepossible to perform a simplified version of the full jitter test procedure, which could provide some useful
information about the jitter in the system, and possibly verify some subset of the full set of specifications to somedegree. Please refer to Appendix 40.6.B for more on this issue.

The full jitter test procedure, in three parts, is presented in the following three sections.

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PART I – MASTER/SLAVE Jtxout MEASUREMENTS
Test Set-Up:

Figure 40.1.5-1: Setup for Jtxout tests
Procedure:
1.
2.
3.
4.
5.
6.

Configure the DUT for transmitter Test Mode 2 operation (MASTER timing mode).
Connect the TX_TCLK and BI_DA signals to the DSO.
Capture 100ms to 1000ms worth of edge data for both the TX_TCLK and BI_DA signals.
Compute and record the peak-to-peak jitter on the BI_DA output signal relative to the TX_TCLK.
Repeat steps 2, 3, and 4 for pairs BI_DB, BI_DC, and BI_DD.
Configure the DUT for Test Mode 3 (SLAVE timing mode), and repeat steps 2 through 5.

Observable Results:
The results of this section will be combined with the results of Parts II and III in order to produce the final
pass/fail jitter values. While the 8 values determined here do ultimately affect the final results, no specific pass/failcriteria are assigned to the Jtxout values themselves.
Possible Problems: None.

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PART II – UNFILTERED AND FILTERED TX_TCLK JITTER (MASTER MODE)
Test Set-Up:

Figure 40.1.5-2: Setup for Master timing mode tests

Procedure:
1. Configure the DUT for normal operation in the MASTER timing mode.
2. Configure the Link Partner for normal operation in the SLAVE timing mode.
3. Connect the DUT to the Link Partner using a standard UTP patch cable, and verify that a valid link exists
between the two devices.
4. Connect the DUT TX_TCLK signal to the DSO.
5. Capture 100ms to 1000ms worth of TX_TCLK edge data.
6. Compute and record the peak-to-peak jitter on the TX_TCLK relative to an unjittered reference.
7. Pass the sequence of jitter values from Step 6 through a 5KHz high-pass filter, and record the peak-to-peakvalue of the result. Add to this value the worst pair MASTER Jtxout value measured in Part I. Record theresult.
Observable Results:
The result of Step 6 should be less than 1.4 ns.
The result of Step 7 should be less than 0.3 ns.
Possible Problems:Clause 40.6.1.2.5 states that, “for all unfiltered jitter measurements, the peak-to-peak value shall bemeasured over an interval of not less than 100ms and not more than 1 second.” In general, it is well beyond theability of most current DSO’s to perform single-shot captures of this length at the sample rates required for this test
(5GS/s recommended minimum). To compensate for this, it will generally be necessary to perform multiple
captures such that that the total number of observed clock edges satisfies the required limits. In this case, a new

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InterOperability Laboratory“unjittered reference clock” must be computed for each capture in order to measure the jitter. One should note thatas the single-shot capture length decreases, the reference clock extraction function (PLL) will be less effective in its
ability to “track” any low frequency modulation in the transmit clock. If a longer duration single-shot capture ispossible, these slow variations will show up as jitter. For this test, it is recommended that the DSO be set to utilize
the maximum possible single-shot memory depth in order to minimize the impact of this effect.
Note that this issue only pertains to the unfiltered jitter measurements, since the standard requires that all
filtered jitter measurements be performed over an unbiased sample of, “at least 105 clock edges”, which is easily
within the single-shot memory depth of most current DSO’s.

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PART III – UNFILTERED AND FILTERED TX_TCLK JITTER (SLAVE MODE)
Test Set-Up:

Figure 40.1.5-3: Setup for Slave timing mode tests
Procedure:
1. Configure the DUT for normal operation in the SLAVE timing mode.
2. Configure the Link Partner for normal operation in the MASTER timing mode.
3. Insert the Jitter Test Channel between the DUT and the Link Partner, oriented such that Port A of the Test
Channel is connected to the DUT.
4. Connect both the DUT and the Link Partner TX_TCLK signals to the DSO.
5. Ensure that the DUT is receiving valid data by verifying that the DUT GMII Management Register bit
10.13 is set to 1.
6. Capture 100ms to 1000ms worth of TX_TCLK edge data for both the DUT and Link Partner.
7. Compute the jitter waveform on the Link Partner TX_TCLK, relative to an unjittered reference. Filter thiswaveform with a 5KHz HPF. Store the peak-to-peak value of the result.
8. Compute the jitter waveform on the DUT TX_TCLK, relative to the Link Partner TX_TCLK. Record thepeak-to-peak value.
9. Pass the jitter waveform from Step 8 through a 32KHz HPF, and record the peak-to-peak value of theresult. Add to this the worst pair SLAVE mode Jtxout value from Part I. Subtract the result obtained in Step
7 above. Record the result.
Observable Results:
The result from Step 8 should be less than 1.4 ns.
The result from Step 9 should be less than 0.4 ns.
Possible Problems: (See possible problems discussion from Part II.)

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Test 40.1.6 – Transmitter Distortion
Purpose: To verify that the distortion of the transmitter is within the correct limits.
References:[1] IEEE Std 802.3-2005TM, subclause 40.6.1.1.2 - Test modes[2] Ibid., Figure 40-21 - Example of transmitter test mode 4 waveform[3] Ibid., subclause 40.6.1.1.3 - Test fixtures[4] Ibid., subclause 40.6.1.2.4 – Transmitter Distortion[5] Appendix 40.H, Transmitter Distortion Measurement
Resource Requirements: Refer to appendix 40.A
Last Modification: April 11, 2008 (version 2.0)
Discussion:
Reference [1] states that all 1000BASE-T devices must implement four transmitter test modes. This test
requires the Device Under Test (DUT) to operate in transmitter test mode 4. While in test mode 4, the DUT shallgenerate the pattern shown in [2] on all four transmit pairs, denoted BI_DA, BI_DB, BI_DC, and BI_DD,
respectively.
In this test, the peak distortion is measured by capturing the test mode 4 waveform and finding the least
mean squared error. The peak error between the ideal reference after partial response filtering and the observed
symbols is the peak transmitter distortion.
Reference [5] states that the sampling time values are obtained using the TX_TCLK from the DUT.
Because this is not always available, the reference clock used to sample the data is extracted from the Test Mode 4
waveform itself. In cases where the TX_TCLK has been provided, it is used as the reference clock.
Test Setup: Refer to appendix 40.A
Procedure:
1. Configure the DUT so that it is sourcing the transmitter test mode 4 waveform.
2. Connect pair BI_DA from the MDI to test fixture 3.
3. Capture 2047 consecutive symbols in the test mode 4 waveform.
4. For enhanced accuracy, repeat step 3 multiple times and average the voltages measured at each point.
5. Measure the peak distortion of 2047 consecutive symbols in the test mode 4 waveform.
6. Repeat step 3 using a sampling phase offset from .025 to 1 unit interval in increments of .025.
7. Repeat steps 2 through 6 for pairs BI_DB, BI_DC, and BI_DD.
Observable Results:
a. The peak transmitter distortion should be less than 10mV for at least 60% of the UI within the eye opening.
Possible Problems: None.

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Test 40.1.7 – Transmit Clock Frequency
Purpose: To verify that the frequency of the Transmit Clock is within the conformance limits
References:[1] IEEE Std 802.3-2005TM, clause 40.6.1.2.6[2] Appendix 40.B, Transmitter Timing Jitter, No TX_TCLK AccessResource Requirements: Refer to appendix 40.A
Last Modification: July 27, 2004 (version 1.0)
Discussion:
Reference [1] states that all 1000BASE-T devices must have a quinary symbol transmission rate of 125.00
MHz ± 0.01% while operating in Master timing mode.
The reference clock used in this test is the one obtained in test 40.1.5, Transmitter Timing Jitter, Master
Timing Mode. The frequency of this clock shall have a base frequency of 125 MHz ± 12.5kHz.

Test Setup: Refer to appendix 40.A
Procedure:
1. Configure the DUT for normal operation in the MASTER timing mode.
2. Configure the Link Partner for normal operation in the SLAVE timing mode.
3. Connect the DUT to the Link Partner using a standard UTP patch cable, and verify that a valid link exists
between the two devices.
4. Connect the DUT TX_TCLK signal to the DSO
5. Capture 100ms to 1000ms worth of TX_TCLK edge data
6. Measure the frequency of the transmit clock.
Observable Results:
a. The transmit clock generated by the DUT shall have a frequency of 125MHz ± 12.5kHz.
Possible Problems:
In some cases, access to the reference clock is not provided. In these cases, the reference clock shall bederived from the Test Mode 2 signal using the procedure outlined in Appendix 40.B.

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Test 40.1.8 – Common-mode Output Voltage
Purpose: To verify that the common-mode output voltage is below the specified limit
References:[1] IEEE Std 802.3-2005TM, clause 40.8.3.3
Resource Requirements: Refer to appendix 40.A
Last Modification: February 9, 2006 (version 1.0)
Discussion:
The common-mode output voltage seen on a 1000BASE-T transmitter is the algebraic average of the twobalanced signals referenced to a common reference. Reference [1] states that the total common-mode output
voltage, Ecm_out, when measured on all four transmit circuits BI_DA, BI_DB, BI_DC, and BI_DD, shall be less than
50 mV peak-to-peak when transmitting data.

Test Setup:

Figure 40.1.8-1: Setup for Common-mode Output Voltage
Procedure:
1. Configure the DUT for Test Mode 4 operation.
2. Connect pair A to the setup shown in figure 40.1.8-1.
3. Measure the Peak Common-mode output voltage
4. For enhanced accuracy, repeat step 3 multiple times and average the result
5. Repeat for all four pairs.
Observable Results:
a. The magnitude of the total common-mode output voltage, Ecm_out, on any transmit circuit, shall be less than
50mV peak-to-peak when transmitting data.
Possible Problems:
None

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GROUP 2: PMA RECEIVE TESTS
Overview:
This section verifies the integrity of the 1000BASE-T PMA Receiver through frame reception tests.
Scope:All of the tests described in this section have been implemented and are currently active at the University of
New Hampshire InterOperability Lab.

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Test 40.2.1 – Bit Error Rate Verification
Purpose: To verify that the device under test (DUT) can maintain low bit error rate in the presence of the worstcase input signal-to-noise ratio.
References:[1] IEEE Std. 802.3-2005TM, clause 40[2] Ibid, Clause 40.4.2.3, PMA Receive Function[3] Ibid, Clause 40.7, Link Segment Characteristics[4] Ibid, Clause 40.6, PMA Electrical Specifications[5] IOL TP-PMD Test Suite Appendix 25.E
Resource Requirements:• Transmit station capable of producing a worst case signal• Category 5 cable plants• Monitor
Last Modification:

September 7, 2004 (Version 2.0)

Discussion:
The operation of the 1000BASE-T PMA sublayer is defined in [1], to operate with a bit error rate of 10-10,
as specified in [2], over a worst case channel, as defined in [3]. This test shall verify a 10-10 Bit Error Rate using
cable lengths ranging from minimum to maximum attenuation in 10% increments and two worst-case rise times.
Based on the analysis given in reference [5], if more than 7 errors are observed in 3x1010 bits (about
2,470,000 1,518-byte packets), it can be concluded that the error rate is greater than 10-10 with less than a 5% chanceof error. Note that if no errors are observed, it can be concluded that the BER is no more than 10-10 with less than a
5% chance of error.
The transmit station is configured to transmit the worst case rise time and output amplitude, while still
meeting the requirements set in [4]. Two worst-case scenarios are utilized. A slow rise time of 5.12ns createsworst-case quantization error; a fast rise time of 4.61ns maximizes the signal bandwidth. Both of the transmit
settings utilize the lowest transmit amplitude possible. The electrical specifications for these transmit conditions areprovided in Appendix 40.D. Rise time estimation is determined using the techniques described in Appendix 40.E.
Note that in the cases where specific equipment models are specified, any piece of equipment with similarcapabilities may be substituted. For multiple port devices, note that the length of the unshielded twisted pair (UTP)
cable used to connect to the monitor station should be kept as short as possible (less than a foot). If longer lengths
are necessary, the impact of the cable on the measurement must be evaluated and steps taken to remove its effect.
Test Setup:
Connect the transmit station to the DUT across the cable plant as shown in figure 40.2.1-1.

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Figure 40.2.1-1: Receiver Test Setups
Procedure:
1. Configure the transmit station such that it generates the slowest worst-case rise time and output amplitude,
while maintaining the minimum electrical requirements discussed in [4].
2. The test station shall send 2,470,000 1,518-byte packets (for a 10-10 BER) and the monitor will count the
number of packet errors.
3. Repeat steps 1 through 2 for the fastest worst-case rise time.
4. Repeat steps 1 through 3 using cable plants having attenuation ranging from 10% to 100% of maximum
attenuation.
Observable Results: There shall be no more than 7 errors for any iteration.
Possible Problems: None

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TEST SUITE APPENDICES
Overview:
The appendices contained in this section are intended to provide additional low-level technical details
pertinent to specific tests defined in this test suite. Test suite appendices often cover topics that are beyond thescope of the standard, but are specific to the methodologies used for performing the measurements covered in thistest suite. This may also include details regarding a specific interpretation of the standard (for the purposes of thistest suite), in cases where a specification may appear unclear or otherwise open to multiple interpretations.
Scope:
Test suite appendices are considered informative, and pertain only to tests contained in this test suite.

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Appendix 40.A – 1000BASE-T Transmitter Test Fixtures
Purpose: To provide a reference implementation of test fixtures 1 through 4
References:[1] IEEE Std 802.3-2005TM, subclause 40.6.1.1.3 - Test fixtures[2] Ibid., Figure 40-22 - Transmitter test fixture 1 for template measurement[3] Ibid., Figure 40-23 - Transmitter test fixture 2 for droop measurement[4] Ibid., Figure 40-24 - Transmitter test fixture 3 for distortion measurement[5] Ibid., Figure 40-25 - Transmitter test fixture 4 for jitter measurement
Resource Requirements:• Disturbing signal generator, Tektronix AWG2021 or equivalent• Digital storage oscilloscope, Tektronix CSA7404 or equivalent• Vector Network Analyzer, HP 8753C or equivalent• Spectrum analyzer, HP 8593E or equivalent• Vector Network Analyzer, HP 8712B or equivalent• Power splitters, Mini-Circuits ZSF-2-1W or equivalent (2)• 8-pin modular plug break-out board• 50 Ω coaxial cables, matched length (3 pairs)• 50 Ω line terminations (6)Last Modification: September 14, 2003 (version 1.2)
Discussion:
40.A.1 - Introduction
References [1] through [5] define four test fixtures to be used in the verification of 1000BASE-T
transmitter specifications. The purpose of this appendix is to present a reference implementation of these test
fixtures.
In test fixtures 1 through 3, the Device Under Test (DUT) is directly connected to a 100Ω differential
voltage generator. The voltage generator transmits a sine wave of specific frequency and amplitude, which isreferred to as the disturbing signal, Vd. An oscilloscope monitors the output of the DUT through a high impedance
differential probe. The three test fixtures differ only in the specification of the disturbing signal and the inclusion ofa high pass test filter. The test fixture characteristics are given in Table 40.A-1.

Table 40.A-1: Characteristics of test fixtures 1 through 3
Test Fixture
1
2
3

Vd Amplitude
2.8 V peak-to-peak
2.8 V peak-to-peak
5.4 V peak-to-peak

Vd Frequency
31.25 MHz
31.25 MHz
20.83 MHz

Test Filter
Yes
No
Yes

The purpose of Vd is to simulate the presence of a remote transmitter (1000BASE-T employs bi-directionaltransmission on each twisted pair). If the DUT is not sufficiently linear, the disturbing signal will cause significant
distortion products to appear in the DUT output. Note that while the oscilloscope sees the sum of the Vd and the
DUT output, only the DUT output is of interest. Therefore, a post-processing block is required to remove thedisturbing signal from the measurement.

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Upon looking at the diagrams shown in [2], [3], and [4], it is important to note that Vd is defined as thevoltage before the 50Ω resistors. Thus, the amount of voltage seen at the transmitter under test is 50% of theoriginal amplitude of Vd.
In test fixture 4, the DUT is directly connected to a 100Ω resistive load. Once again, the oscilloscope
monitors the DUT output through a high impedance differential probe.
This appendix describes a single test setup that can be used as test fixtures 1 through 4. A block diagram ofthis test setup is shown in Figure 40.A-1, and the modular break out board used is shown in Figure 40.A-2. Eachtest fixture is realized through the settings of the disturbing voltage generator and configuration of the postprocessing block.

Disturbing Signal Generator
(DSG)
CH 1
8-pin modular
break-out
CH 2

Device Under Test
(DUT)Power Splitter A
1
S
2

Digital Storage
Oscilloscope (DSO)

1
TX_TCLKS
2Power Splitter B

CH 1
Post-Processing

CH 2

50 Ω line termination
(x 6)

CH 3

Figure 40.A-1: Test setup block diagram

Figure 40.A-2: 8-pin modular breakout board

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Note that this test setup does not employ high impedance differential probes. In order to use highimpedance differential probes, the vertical range of the oscilloscope must be set to accommodate the sum of Vd andthe DUT output. For example, in order to analyze the 2V peak-to-peak DUT output using test fixture 3, the verticalrange of the oscilloscope must be set to at least 4.7 V peak-to-peak. If a digital storage oscilloscope (DSO) is used,
this increases the quantization error on the DUT output by more than a factor of two. Since a DSO must be used tomake post-processing possible, it is beneficial to use the smallest vertical range possible.
To this end, the test setup in Figure 40.A-1 uses power splitters. As its name implies, the power splitter
divides a power input to port S evenly between ports 1 and 2. Conversely, inputs to ports 1 and 2 are averaged to
produce the output at port S. The key feature of the power splitter is that ports 1 and 2 are isolated. The test setup
uses this feature to apply the disturbing signal to the DUT while having a minimum amount of it reach the DSO. In
effect, the test setup replicates the hybrid function present in 1000BASE-T devices.
Due to the nature of the setup, Vd is not set to 2.8V peak-to-peak. The magnitude of Vd as seen at port S
should be equal to half that defined in the standard. For test fixtures 1 and 2, this is 1.4V peak-to-peak. This meansthat the actual output voltage of the Disturbing Signal Generator should be approximately 1.4V+3dB. Prior to eachtest performed, the voltage at port S is verified to be 1.4V peak-to-peak.
Figure 40.A-3 shows the signal flow through the power splitter. Note that the isolation between ports 1 and
2 is no more than 6 dB better than the return loss of the termination at port S. For example, an input to port 1 loses 3
dB on its way to port S. The termination at port S reflects some amount of the power back into the splitter, which isthen split evenly between ports 1 and 2 (another 3 dB loss). For conformant 1000BASE-T devices, the return loss at
the MDI is greater than 16 dB from 1 to 40 MHz. Therefore, the isolation between ports 1 and 2 is expected to bebetter than 22 dB when port S is connected to a conformant 1000BASE-T device. In this configuration, the verticalrange of the DSO must be set to accommodate the sum of the residual Vd and the DUT output. Since this is muchcloser to 2V peak-to-peak than 7.4V peak-to-peak, the quantization error on the DUT output will be smaller.
The test setup block diagram in Figure 40.A-1 may be implemented with the equipment listed in Table
40.A-2. The remainder of this appendix discusses the test setup in the context of this implementation.

Disturbing
SignalGenerator
1
S
2
DigitalStorage
Oscilloscope

DeviceUnder
Test

Power Splitter

Figure 40.A-3: Power splitter operation

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Table 40.A-2: Equipment list
Functional Block
Disturbing signal generator

Equipment
Tektronix AWG2021

Digital storage oscilloscope

Tektronix CSA7404

Power splitter

Mini-Circuits ZSC-2-1W

Key Features
2 channels, 5 V peak-to-peak
output per channel, 250 MS/s
sample rate
4 channels, 4 GHz bandwidth,
20GS/s sample rate, 32 million
sample memory
2-way 0o, 1 to 650 MHz

40.A.2 - Power splitters
Since the power splitters are single-ended devices, two of them are required to make differential
measurements. This imposes two constraints. First, the port impedance of the power splitter must be 50Ω so that adifferential 100Ω load is presented to the DUT. Second, the power splitters must be matched devices. Differencesin the insertion loss, delay, and port impedance of the power splitters will degrade the common-mode rejection of
the test setup.
The insertion loss of power splitters A and B are plotted on the same axis in Figure 40.A-4. The
measurement was performed using the HP 8753C network analyzer with the HP 85047A S-parameter test set. From
this figure, it can be seen that the power splitters are well matched to about 700 MHz. In addition, the insertion loss
is about 3.2 dB from 1 to 150 MHz. Note that a 3 dB insertion loss is intrinsic to the operation of a power splitter.
The performance of a power splitter is gauged by how much the insertion loss exceeds 3 dB.

Figure 40.A-4: Power splitter high-frequency insertion loss

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Note that the power splitters are AC-coupled devices. The low frequency -3dB cut-off point of the power
splitters must also be known so that their impact on droop measurements can be removed. Since the network
analyzer is an AC-coupled instrument with a minimum frequency of 300 kHz, the test setup shown in figure 40.A-5
was used to properly measure the low-frequency response.
The test setup shown in Figure 40.A-5 uses the Tektronix AWG2021 to inject low-frequency sine waves
into port S of the power splitters. The power splitters are driven differentially. In other words, the input to power
splitter B is 180o out of phase with the input to power splitter A. The DSO captures the resultant sine waves at port
1 of the splitters and takes the difference to get a differential signal. The ratio of the differential output amplitude to
the differential input amplitude is recorded for a range of frequencies and the results are presented in Figure 40.A-6.
The differential input amplitude was 200 mV.

Digital Storage
Oscilloscope (DSO)

Power Splitter A

Disturbing Signal Generator
(DSG)

1
S
CH 1

2

CH 2

1

CH 1

CH 2
S

2
50 Ω line termination

Power Splitter B

Figure 40.A-5: Test setup for low-frequency cut-off measurement

Figure 40.A-6: Low-frequency response of power splitter pair

The low-frequency -3dB cut-off point of the power splitter pair was determined to be 18.3 kHz. This
number will be used in the post-processing block to compensate for the low-frequency response of the power
splitters and improve the accuracy of droop measurements.

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40.6.A.3 – Disturbing signal generator
The disturbing signal generator (DSG) must be able to output a sine wave with the amplitude and frequency
required by the test fixture. Furthermore, the DSG must meet spectral purity and linearity constraints and it musthave a port impedance of 50Ω to match the power splitters.
The spectral purity and linearity constraints stem from the typical method used to remove the disturbing
signal during post-processing. This method uses standard curve fitting routines to find the best-fit sine wave at the
disturbing signal frequency. The best-fit sine wave is subtracted from the waveform leaving any harmonics anddistortion products behind. Significant harmonics and distortion products can lead to measurement errors.
Therefore, the standard requires that all harmonics be at least 40 dB down from the fundamental. Furthermore, thestandard states that the DSG must be sufficiently linear so that it does not introduce any “appreciable” distortion
products when connected to a 1000BASE-T transmitter.
Note that the use of power splitters makes these constraints easier to satisfy. First, thanks to the isolation
between ports 1 and 2, the disturbing signal and the accompanying harmonics and distortion products are greatly
attenuated when they reach the DSO. Second, due to the nature of the power splitter, only half of the power output
by the 1000BASE-T transmitter reaches the DSG. This reduces the amplitude of any distortion products generated
by the DSG. However, since only half of the power output by the DSG reaches the DUT, the DSG is forced to
output twice the power in order to get the amplitude required by a given test fixture.
Synthesized 31.25 and 20.83 MHz sine waves from the Tektronix AWG2021 were measured directly withan HP 8593E spectrum analyzer. The results are presented in Figures 40.A-7 and 40.A-8 respectively. Thesefigures show that all harmonics are at least 40 dB below the fundamental.

Figure 40.A-7: Spectrum of 31.25 MHz synthesized sine wave from the Tektronix AWG2021

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Figure 40.A-8: Spectrum of 20.83 MHz synthesized sine wave from the Tektronix AWG2021

The Tektronix AWG2021 includes built-in filters, which were used to achieve greater harmonic
suppression. In order to provide the correct disturbing signal amplitude at the DUT, the output of the Tektronix
AWG2021 was set to a level that would compensate for the combined insertion loss of the filter and the power
splitter. A complete list of the settings is included in Table 40.A-3.

Table 40.A-3: Tektronix AWG2021 channel 1 settings
Setting
Test Fixtures 1 and 2
Test Fixture 3
Sample Rate
250 MS/s
250 MS/s
Samples Per Cycle
8
12
Amplitude
1.26V peak-to-peak
2.12V peak-to-peakFilter50 MHz50 MHzOffset00Note: The settings for channel 2 are identical except that the amplitude of the sine wave is inverted.

The linearity of the Tektronix AWG2021 was tested using the setup shown in Figure 40.A-9. The resistive
splitter shown in the test setup has an insertion loss of 6 dB between any two ports. The spectrum measured at theoutput of port 3 is shown in Figure 40.A-10. This figure shows that all harmonics and distortion products are at least
40 dB below the fundamental. Note that the outputs from channels 1 and 2 are both 4V peak-to-peak.

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Resistive Power Splitter1

16.7 Ω
CH 1

CH 2

16.7 Ω

3

HP 8593E
Spectrum
Analyzer

16.7 Ω

Tektronix AWG 2041
2

Figure 40.A-9: Test setup for disturbing signal generator linearity measurement

Figure 40.A-10: Spectrum measured at port 3 of the resistive splitter

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40.A.4 – Digital Storage Oscilloscope
A digital storage oscilloscope (DSO) with at least three channels is required. Two channels are required tomeasure the differential signal present at port 2 of the power splitters. These channels must be DC-coupled and theymust present a 50Ω characteristic impedance. The third channel is used in test fixtures 3 and 4 to monitor
TX_TCLK. The requirements for this channel depend on how TX_TCLK is presented.
Ideally, the frequency response of the oscilloscope would be flat across the bandwidth of interest. Given a
3 ns rise time, the fastest rise time expected for a 1000BASE-T signal, the bandwidth of interest would be roughly
117 MHz, using the bandwidth=0.35/risetime rule of thumb.
Another rule of thumb states that the bandwidth of the instrument should be 10 times the bandwidth ofinterest. If the instrument is assumed to be a first-order low pass filter, the gain only drops 0.5% at one-tenth of the
cut-off frequency. Therefore, if the bandwidth of the instrument were on the order of 1 GHz, the frequency response
would be reasonably flat out to 117 MHz.
A third rule of thumb is that the sample rate must be at least 10 times the bandwidth of interest for linear
interpolation to be used. A minimum sample rate of 2GS/s is recommended for 1000BASE-T signals.
Finally, the DSO should have sufficient sample memory to store the 1000BASE-T transmitter test
waveforms. These waveforms are on the order of 16 µs in length. At a 2GS/s sample rate, this would require asample memory of 32K samples. Deeper sample memories are useful for jitter measurements, but that is beyond thescope of this appendix.

40.A.5 – Post-Processing Block
The post-processing block removes the disturbing signal from the measurement, compensates for theinsertion loss and low-frequency response of the power splitters, and applies the high pass test filter when required.
Figure 40.A-11 shows the waveform seen by the oscilloscope when the test setup is functioning as test
fixture 1. This waveform is the sum of the transmitter test mode 1 waveform and some residual disturbing signal.
The residual disturbing signal can be removed by subtracting the best-fit sine wave at the disturbing signal
frequency. Note that only amplitude and delay (phase) must be fit, since the exact frequency can be measured apriori. If multiple waveforms were captured for the purpose of measurement averaging, the amplitude would only
need to be fit for the first iteration, leaving phase as the only uncertainty. These shortcuts can be employed toreduce the execution time of the curve-fitting routines.
For the example in Figure 40.A-11, the curve-fitting routine determined that the best-fit amplitude was 48
mV and the best-fit phase was 3.1 µs. The best-fit sine wave was subtracted from the waveform and a scale factor
1.44 (103.2/20) was applied to compensate for the insertion loss of the power splitters. Figure 40.A-12 shows theprocessed waveform and the DUT output, also referred to as the test setup input, plotted on the same axis. This
figure demonstrates the impact that the power splitter’s low-frequency response has on the waveform.
The low-frequency response of the power splitter is modeled as first-order high pass filter with a cut-off
frequency of 18.3 kHz. Applying the inverse function of this filter to scaled output waveform yields the waveformshown in Figure 40.A-13.

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Figure 40.A-11: Observed transmitter test mode 1 waveform before post-processing

Figure 40.A-12: Input waveform and scaled output waveform with best-fit sine wave removed

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Figure 40.A-13: Output waveform with droop compensation

Figure 40.A-14: Output of transmitter test filter

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Note from Figure 40.A-13 that the processed waveform is now indistinguishable from the DUT output.
This implies that the post-processing successfully removed the distortion of the test setup and that the DUT was
linear. If the DUT was not sufficiently linear, then the output would have been distorted due to the presence of the
disturbing signal.
Test fixtures 1 and 3 require the presence of a high pass test filter whose cut-off frequency is 2 MHz.
While the test filter may be a discrete component, the test setup described in this appendix implements the filter inthe post-processing block. An example of the output from this test filter is provided in Figure 40.A-14.

40.A.6 – Complete test setup
The complete test setup must be evaluated in terms of the differential impedance presented to the DUT andthe common-mode rejection ratio. Since the test setup is composed of two single-ended circuits, each circuit wasmeasured independently and their differential equivalent was computed. This requires the 8-pin modular plugbreakout board to be removed from the measurement. If care is taken with the construction of the board, it will havea minimal impact on the performance of the test setup. This means that the traces from the 8-pin modular plug to
the RF connectors must be as short as possible and the trace length must be matched on a pair-for-pair basis. If forsome reason the traces must be long (more than 2”), steps must be taken to ensure that the trace impedance is 50Ω.
The reflection coefficient of each circuit with respect to a 50Ω resistive source was measured using an HP
8712B network analyzer. It can be shown that the differential reflection coefficient is the average of the singleended reflection coefficients. The return loss, which is the magnitude of the reflection coefficient expressed indecibels, is given in Figure 40.A-15.
Note that any differences in the impedance of the two circuits will result in an error in the differential gainof the test setup. If the input impedance of circuit A is ZA and the input impedance to circuit B is ZB, the gain error
is given in Equation 40.A-1.

Gain Error =ZA
ZB+
50 + Z A 50 + Z B(Equation 40.A-1)

Equation 40.A-1 assumes that the differential source impedance is a precisely balanced 100Ω resistance.
The impedance of each circuit was derived from the reflection coefficient and the gain error is plotted in Figure40.A-16.
In section 40.A.2, the frequency response of the power splitters was measured for each differential
component and again as a pair. Comparing Figures 40.A-4 and 40.A-6, the pass-band gain of each individual power
splitter is greater than the gain of the differential pair. This difference is due to the impedance imbalance, and themagnitude of the difference agrees with the data in Figure 40.A-16.
Impedance unbalance also causes common-mode noise to appear as a differential signal. The performanceof a differential probe is measured in terms of how well it rejects common-mode noise. This is referred to as thecommon-mode rejection ratio (CMRR). The CMRR can be computed that difference between the transfer functionof the individual circuits. An HP 8712B network analyzer was used to measure the transfer function of eachindividual circuit and the difference is plotted in Figure 40.A-17.

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Figure 40.A-15: Differential return loss at the input to the test setup

Figure 40.A-16: Differential gain error due to impedance imbalance in the test setup

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Figure 40.A-17: Test setup common-mode rejection

40.A.7 - Conclusion
This appendix has presented a reference implementation for test fixtures 1 through 4. A single physical test
setup was used and each individual test fixture was realized through the configuration of the disturbing signal
generator and the post-processing block. Table 40.A-5 summarizes the configuration required to realize each test
fixture.
The test setup utilizes a hybrid function to minimize the level of the disturbing signal that reaches theoscilloscope. This allows a smaller vertical range to be used, which in turn reduces the quantization noise on themeasurement. Furthermore, it relaxes the constraints placed on the disturbing signal generator in terms of spectral
purity. However, the hybrid function also requires additional steps in the post-processing block to deal withinsertion loss and the high pass nature of the hybrid.
The test setup was shown to present a reasonable line termination to the device under test. Despite the factthat the test setup uses two single-ended circuits to perform the differential measurement, the matching was
sufficient to provide good impedance balance and common-mode rejection.

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Table 40.A-5: Realization of 1000BASE-T Transmitter Test Fixtures
Setting
AWG2021 Channel 1
Sample Rate
Samples Per Cycle
Filter
Amplitude (peak-to-peak)
OffsetPost-Processing
Vd Removal
Waveform Scaling
Droop Compensation
Test Filter

Test Fixture 1

Test Fixture 2

Test Fixture 3

Test Fixture 4

250 MS/s
8
50 MHz1.26 V0250 MS/s
8
50 MHz1.26 V0250 MS/s
12
50 MHz2.12 V
0

—
—
—
—
—

Yes
Yes
Yes
Yes

Yes
Yes
Yes
No

Yes
Yes
Yes
Yes

No
Yes
Yes
No

Miscellaneous
Monitor TX_TCLK
No
No
Yes
Yes
Note 1: The settings for channels 1 and 2 of the AWG2021 are identical except for a 180o phase-shift.

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Appendix 40.B – Transmitter Timing Jitter, No TX_TCLK AccessPurpose:To provide an analysis of the Transmitter Timing Jitter test method defined in Clause 40.6.1.2.5 ofIEEE 802.3, and to propose an alternative method that may be used in cases where a device does notprovide access to the TX_TCLK signal.

References:[1] IEEE standard 802.3-2005TM, subclause 40.6.1.1.1 – Test channel[2] Ibid., subclause 40.6.1.1.2, figure 40-20 – Test modes[3] Ibid., subclause 40.6.1.1.3, figure 40-25 – Test fixtures[4] Ibid., subclause 40.6.1.2.5 – Transmitter Timing Jitter[5] Test suite appendix 40.6.A – 1000BASE-T transmitter test fixtures
Resource Requirements:• A DUT without an exposed TX_TCLK clock signal• Digital storage oscilloscope, Tektronix CSA7404 or equivalent• 8-pin modular plug break-out board• 50 Ω coaxial cables, matched length• 50 Ω line terminations (6)Last Modification:

March 25, 2002 (Version 1.1)

Discussion:

40.B.1 – Introduction
In addition to supporting the standard transmitter Test Modes, the jitter specifications found in Clause
40.6.1.2.5 require a device to provide access to the internal TX_TCLK signal in order to perform the Transmitter
Timing Jitter tests. While access to the TX_TCLK signal is relatively straightforward and easy to provide on
evaluation boards and prototype systems, it can become impractical in more formal implementations. In the casewhere no exposed TX_TCLK signal is available, it may be possible to perform a simplified version of the full jitter
test procedure which could provide some useful information about the quality and stability of a device’s transmit
clock. This Appendix will discuss the present test method, and will propose an alternate test procedure that may be
used to perform a simplified jitter test for devices that support both transmitter Test Mode 2 (TM2) and Test Mode 3(TM3), but do not provide access to the TX_TCLK signal. Because this procedure deviates from the specifications
outlined in Clause 40.6.1.2.5, it is not intended to serve as a legitimate substitute for that clause, but rather as an
informal test that may provide some useful insight regarding the overall purity and stability of a device’s transmit
clock.

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40.B.2 – MASTER timing mode tests
The formal MASTER timing mode jitter procedure of Clause 40.6.1.2.5 can basically be summarized by
the following steps (with the DUT configured as MASTER):- Measure the pk-pk jitter from the TX_TCLK to the MDI (i.e., “Jtxout”).
- Measure the pk-pk jitter on the TX_TCLK, relative to an unjittered reference.
- This must be less than 1.4ns.
- HPF (5KHz) the TX_TCLK jitter, take the peak-to-peak value, and add Jtxout- This result must be less than 0.3 ns.
We see that there are essentially specifications on the following two parameters:
1) Unfiltered jitter on the TX_TCLK.
2) Sum of the filtered TX_TCLK jitter plus the unfiltered Jtxout.
In actual systems, it should be fairly reasonable to assume that Jtxout will be relatively small compared to thefiltered TX_TCLK jitter. If Jtxout were zero, access to the internal TX_TCLK wouldn’t be necessary, because theTM2 jitter at the MDI would be identical to the jitter on the internal TX_TCLK. In effect, you would essentially beable to “see” the TX_TCLK jitter through the MDI.
It is this idea that allows us to design a hypothetical test procedure for the case when a device does notprovide access to TX_TCLK. Suppose the following procedure is performed:- Measure the unfiltered peak-to-peak jitter on the TM2 output at the MDI,
relative to an unjittered reference.
- Filter the MDI output jitter with the 5KHz HPF to determine the filtered peak-to-peakjitter.
Note that the TM2 jitter measured at the MDI is actually the sum of the TX_TCLK jitter plus Jtxout. Given
this fact, one could argue that if the TM2 jitter, relative to an unjittered reference, is less than 1.4ns, then the
TX_TCLK jitter component alone must be less than 1.4ns as well. (In other words, if the results are conformant
when Jtxout is included, the results would be even better if Jtxout could be separately measured and subtracted.) Thus,
the device could be given a legitimate passing result for the unfiltered MASTER TX_TCLK jitter if the measured
TM2 jitter relative to an unjittered reference is less than 1.4ns.
A similar argument can be made for the filtered TX_TCLK jitter case. In the formal jitter test procedure,
Jtxout is not filtered before it is added to the filtered TX_TCLK jitter. For our hypothetical test, the jitter at the MDI(after filtering) is effectively the sum of the filtered TX_TCLK jitter plus the filtered Jtxout. Thus, we can conclude
that if the filtered TM2 jitter is greater than 0.3ns, it would only fail in a worse manner if Jtxout were not filtered prior
to being added to the filtered TX_TCLK jitter.
Note that this test is inconclusive if the peak-to-peak value of the filtered MDI jitter is less than 0.3ns. Thisis because it can’t be known for sure exactly how the filtered jitter is distributed between Jtxout and actual TX_TCLK
jitter. For example, suppose that in our hypothetical test, the result for the filtered jitter was just under 0.3ns, and thedevice was given a passing result for the filtered TX_TCLK jitter test. If the filtered jitter was 100% due to Jtxout(i.e., TX_TCLK jitter was zero), then the device would actually fail the formal test, where Jtxout is measured sansfilter before being added to the filtered TX_TCLK jitter. Thus, the original passing result of our hypothetical test
would have been incorrect.
By the same logic, the results are also inconclusive for the unfiltered jitter case when the peak-to-peakresult is greater than 1.4ns. Again, this is because it is not possible to know how much of this value is due to Jtxout.
Thus, assigning a failing result to a device whose unfiltered TM2 jitter was just above 1.4ns could be incorrect if it

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was otherwise determined that a large part of the jitter was due to Jtxout, which would not have been included in theunfiltered TX_TCLK jitter value had the formal jitter test procedure been performed.
The table below summarizes the possible outcomes of the hypothetical test, and lists the pass/fail result that
may be assigned for the given outcome.

Table 40.B-1: Hypothetical test outcomes and results
Paramter
Unfiltered TM2 jitter
Filtered TM2 jitter

Conformance Limit
1.4ns
0.3ns

Result < Limit
PASS
Inconclusive

Result > Limit
Inconclusive
FAIL

40.B.3 – SLAVE timing mode tests
The question remains as to the possibility of designing a similar hypothetical test for the SLAVE timingmode case based on the Test Mode 3 (TM3) signal observable at the MDI. Unfortunately, this is not as
straightforward as was the case for the MASTER timing mode. This is due to the fact that the formal procedure ofClause 40.6.1.2.5 relies heavily on access to both the MASTER and SLAVE TX_TCLK signals for SLAVE jittermeasurements, in addition to the fact that the SLAVE measurements are to be made with both devices operating
normally, connected to each other via their MDI ports, which precludes the use of the MDI for the purpose ofgaining access to the internal TX_TCLK.
Furthermore, the meaning of the Test Mode 3 mode itself is somewhat confusing as it is described in
Clause 40.6.1.1.2:“When test mode 3 is enabled, the PHY shall transmit the data symbol sequence {+2, –2} repeatedly on all channels.
The transmitter shall time the transmitted symbols from a 125.00 MHz +/-0.01% clock in the SLAVE timing mode. A typicaltransmitter output for transmitter test modes 2 and 3 is shown in Figure 40–20.”

A SLAVE physical layer device is defined in Clause 1.4.255 as, “the PHY that recovers its clock from thereceived signal and uses it to determine the timing of transmitter operations.” If it is truly intended that a device be
operating in the SLAVE timing mode while in Test Mode 3, it would need to be provided with a signal at the MDIfrom which to determine the recovered clock. This, however, would preclude the measurement of the SLAVE Jtxout
values due to the fact that one cannot simultaneously provide a reference clock and monitor the TM3 waveform on
the same bi-directional MDI wire pair. The most reasonable interpretation of intended TM3 operation (on the partof the author, anyway,) would be that a DUT would use it’s own MASTER clock as the “received signal”, andprovide it internally to the SLAVE clock recovery mechanism, which would then generate the clock used fortransmitting the {+2, -2} symbol sequence for TM3. The problem with this method from a conformance perspectiveis that it is impossible to verify that a device is truly operating in this manner when it is in TM3. (Perhaps a better
implementation of TM3 would be to simply send another device’s TM2 signal into the DUT’s MDI while the
DUT’s transmitter remains silent. Then, the jitter on the DUT (SLAVE) TX_TCLK could be measured with respect
to the incoming TM2 signal.) Regardless, it is still difficult to design an abbreviated test for SLAVE mode jitter thatstrictly adheres to the specifications of Clause 40.6.1.2.5, and does not require access to the TX_TCLK.

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It may be possible however, to design a test that attempts to emulate the intentions of the formal procedure,
while deviating from it as little as possible. To begin, note that the formal method for measuring the SLAVE-related
jitter parameters can be summarized by the following steps:- Configure DUT (SLAVE) for TM3. Measure the jitter from the TX_TCLK to the MDI(i.e., “Jtxout”).
- Connect the DUT to the Link Partner (MASTER) through the Jitter Test Channel.
- Measure the jitter on the MASTER TX_TCLK, relative to an unjittered reference.
Filter this jitter waveform with a 5KHz HPF. Record the peak-to-peak value of theresult. (This value will be subtracted later from the measured SLAVE jitter value.)- Measure the jitter on the DUT TX_TCLK, relative to the MASTER TX_TCLK.
- This must be less than 1.4ns peak-to-peak.
- Filter the DUT TX_TCLK jitter waveform with a 32KHz HPF, take the peak-to-peakvalue, add Jtxout, and subtract the recorded peak-to-peak filtered MASTER jitter value.
- This result must be less than 0.4 ns.
The key concepts of this method are basically:
1) Measure the filtered jitter on the “source clock”.
2) Pass the clock through a worst-case echo environment.
3) Measure the unfiltered jitter on the “recovered clock”, with respect to the source clock.
4) Filter this jitter, subtract Jtxout, and subtract the filtered jitter from the source clock.
If a device is intended to use its own MASTER clock as the input from which the SLAVE clock is derived,a hypothetical approximation for this procedure for the case where one only has access to the MDI signaling mightbe:1) Measure the DUT’s TM2 jitter relative to an unjittered reference, filter with a
5KHz HPF, and record both the filtered and unfiltered peak-to-peak values.
2) Measure the DUT’s TM3 jitter relative to an unjittered reference. Subtract
the unfiltered TM2 peak-to-peak jitter value.
- This result must be less than 1.4ns.
3) Filter the TM3 jitter with a 32KHz HPF, subtract the filtered TM2 pk-pk jitter value.
- This result must be less than 0.4ns.
This procedure approximates the formal procedure, with two exceptions. The first is that it is obviously notpossible to insert the jitter test channel between the source clock and the recovered clock. The second difference isthat in addition to the jitter test channel, the MASTER’s Jtxout is also present between the source and recovered
clocks in the formal procedure, but is not present in the hypothetical test procedure (although it should be zero if the
DUT’s internal MASTER TX_TCLK is being used directly as the input to the PLL.)
Given that these two differences actually make the clock recovery operation easier for the DUT, it istechnically inappropriate to apply the same SLAVE mode conformance limits specified in Clause 40.6.1.2.5. (Ifsomehow the alternate test conditions were more difficult, the same argument from the hypothetical MASTER test
could be used, i.e., if the device can still pass under tougher conditions, we can be fairly certain that it would passunder the formal test conditions.) One solution to this problem would be to revise the conformance limits to stricter
values, however this would require research into what these values should be, and these values would need to beverified an accepted by the general community. Not having this, a possible alternative would be to perform the tests
and report the numerical results for purely informational purposes without judging them on a pass/fail basis, with the
only exception being the results of the MASTER mode (TM2) tests when the results are within the pass/fail regions
shown in Table 40.6.B-1.

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40.B.4 – Conclusion
This appendix was intended as an analysis of the jitter test procedure of Clause 40.6.1.2.5, for the casewhere a device does not provide access to the TX_TCLK signal. An attempt was made to basically “do the bestwith what you’ve got”, and determine what subset (if any) of the jitter specifications can be verified if the
TX_TCLK signal is not available. The analysis provides a method that is solely based on the Test Mode 2 and Test
Mode 3 signals as observed at the MDI. The method for the MASTER mode jitter parameters can, under somecircumstances, yield legitimate pass/fail results for a particular DUT however, depending on the measured values,
will produce inconclusive results. In these cases, while it may not be possible to assign a pass/fail judgment, thedetermined jitter values may still be useful from a design perspective and could be reported for informational
purposes only.
It was concluded that it is not possible to strictly verify any of the SLAVE mode jitter parameters without
access to the TX_TCLK, however an alternate method was presented which approximates the intentions of theformal procedure. Because the method is a simplified version of the formal procedure, it is not possible to apply thesame conformance limits specified in the standard, thus reducing it to a purely informal test. Depending on thevalidity of the analysis and the ultimate need for such a test, it might be possible to develop this method into a valid
alternative, although new conformance limits would need to be determined and the method would need to be
accepted by the standards body.

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Appendix 40.C – Jitter Test Channel
Purpose: To show that the test channel used for jitter measurements used by the IOL is compliant with the IEEE
802.3 Standard.
References:[1] IEEE Standard 802.3-2005TM, Subclause 40.6.1.1.1[2] IEEE Standard 802.3-2005TM, Subclause 40.7
Last Modification: October 7, 2004 (Version 1.0)
Discussion:
Reference [1] describes the procedure for creating a worst case environment to test the jitter between a
Master and Slave TX_TCLK. Reference [2] describes the specifications that are to be met for the entire test
channel. The following tables and figures show that the test channel used by the InterOperability Lab is compliant
with [2].
A Fluke DSP-4000 was used to measure the cable parameters. To verify compliance, an Agilent 4395A
Network Analyzer was used to measure Attenuation and Return Loss. All data gathered was processed using
Matlab.
Both attenuation and propagation delay are a function of cable length. The objective was to create achannel with marginal attenuation and propagation delay. Since there is no way to change one without affecting theother, the cable length was adjusted until both parameters passed. Unfortunately, this meant the propagation delay
value was further from the limit than desired. The attenuation plot, which is marginal, is shown in figures 1 and 2.
The propagation delay, while not marginal, is still high. This is shown in table 1.

Table 40.C-1: Propagation delay values for test channel.
Pair
Limit
Pair A
Pair B
Pair C
Pair D
Average
Delay (ns)
570
538
522
517
535
528

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A ttenuation Data gathered on Fluke DSP -4000
25Standard Lim it
Pair A
Pair B
Pair C
Pair D
Average

Attenuation (dB)

20

15

10

5

0

0

10

20

30

40

50

60

70

80

90

100

30

40
50
60
Frequency (Hz)

70

80

90

100

2
Lim itA M argin
B M argin
C M argin
D M argin
Average M argin

Margin (dB)

1.5

1

0.5

0

0

10

20

Figure 40.C-1: Attenuation data gathered using Fluke DSP-4000
Note: According to reference [1], the AVERAGE of the attenuation on all four pairs needs to pass. The averageattenuation margin passes at all frequencies.
Table 40.C-2: Minimum margins for each pair
Test
Min. Margin (dB)Pair A
0.0948Pair B
0.1909Pair C0.1358Pair D
0.1297
Average
0.1631

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Attenuation Data gathered on HP 4395A
25

Attenuation (dB)

20

15

10

Lim itPair A
Pair B
Pair C
Pair D
Average

5

0

0

10

20

30

40

50

60

70

80

90

100

20

30

40
50
60
Frequency (M Hz)

70

80

90

100

2.5
Lim itPair A
Pair B
Pair C
Pair D
Average

Margin (dB)

2

1.5

1

0.5

0

0

10

Figure 40.C-2: Attenuation data gathered using Agilent 4395A Network Analyzer
As the above figure shows, the average attenuation is below the limit over all frequencies. The minimum margin is
0.156.
Table 40.C-3: Minimum margins for each pair
Test
Min. Margin (dB)Pair A
0.0187
Pair B
0.2303
Pair C
0.1966
Pair D
0.1718Average
0.1563

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NEXT Data gathered on Fluke DSP-4000
100
90NEXT Loss (dB)

80
70
60
50
40
30
20

0

10

20

30

40

0

10

20

30

40

50

60

70

80

90

100

50
60
Frequency (Hz)

70

80

90

100

0

Margin (dB)

-10

-20

-30

-40

-50

Figure 40.C-3: NEXT data for each test
Table 40.C-4: Minimum margins for each test
Test
Min. Margin (dB)Pair A-Pair B
4.4411
Pair A-Pair C
1.7882
Pair A-Pair C
1.3178Pair B-Pair C
2.1852
Pair B-Pair D
2.2564
Pair C-Pair D
8.0805
Average
6.6205

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ELFEXT Data gathered on Fluke DSP -4000
9080

ELFEXT Loss (dB)

70
60
50
40
30
20
10

0

10

20

30

40

0

10

20

30

40

50

60

70

80

90

100

50
60
Frequency (Hz)

70

80

90

100

0

-10

Margin (dB)

-20

-30

-40

-50

-60

Figure 40.C-4: ELFEXT data for each test
Table 40.C-5: Minimum margins for each test
Test
Min. Margin (dB)Pair A-Pair B
17.4173
Pair A-Pair C
12.4950
Pair A-Pair D
12.9268
Pair B-Pair A
18.2580
Pair B-Pair C
10.4900
Pair B-Pair D
12.7964
Pair C-Pair A
11.7292
Pair C-Pair B
8.9298Pair C-Pair D
13.0103
Pair D-Pair A
11.7185
Pair D-Pair B
13.4379
Pair D-Pair C
12.0910
Average
16.8857

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PSELFEXT Data gathered on Fluke DSP-4000
80Standard Limit
Pair A
Pair B
Pair C
Pair D
Average

PSELFEXT Loss (dB)

70
60
50
40
30
20
10

0

10

20

30

40

50

60

70

80

90

100

30

40
50
60
Frequency (Hz)

70

80

90

100

0
Limit
A M argin
B M argin
C M argin
D M argin
Average Margin-5

Margin (dB)

-10
-15

-20
-25

-30

0

10

20

Figure 40.C-5: PSELFEXT data for each pair
Table 40.C-6: Minimum margins for each pair
Test
Min. Margin (dB)Pair A
11.9185
Pair B
11.0298
Pair C
10.9290
Pair D11.4904
Average12.9523

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Return Loss Data gathered on Fluke DSP -4000
60
Standard Limit
Pair A
Pair B
Pair C
Pair D
Average

Return Loss (dB)

50
40
30
20
10
0

0

10

20

30

40

50

60

70

80

90

100

0

Margin (dB)

-10

-20
Limit
A M argin
B M argin
C M argin
D M argin
Average M argin

-30

-40

-50

0

10

20

30

40
50
60
Frequency (Hz)

70

80

90

100

Figure 40.C-6: Return Loss data gathered using Fluke DSP-4000
Table 40.C-7: Minimum margins for each pair
Test
Min. Margin (dB)Pair A
3.8394
Pair B
3.6342
Pair C
2.8881
Pair D4.5000
Average
4.6441

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Return Loss Data gathered on HP 4395A
60
Lim itPair A
Pair B
Pair C
Pair D
Average

Return Loss (dB)

50

40
30

20
10

0

0

10

20

30

40

50

60

70

80

90

100

0
-5
-10

Margin (dB)

-15
-20
-25

Lim itPair A
Pair B
Pair C
Pair D
Average

-30
-35
-40
-45

0

10

20

30

40

50
60
Frequency (Hz)

70

80

90

100

Figure 40.C-7: Return Loss data gathered using Agilent 4395A
Table 40.C-8: Minimum margins for each pair
Test
Min. Margin (dB)Pair A
3.3785
Pair B
3.0998Pair C
2.9915
Pair D
4.7835
Average
4.1805

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Appendix 40.D – Transmitter Specifications
Purpose: To present an example transmitter electrical specification to implement the 1000BASE-T PMA Receiver
test suite.
Last Modification:

January 9, 2004 (Version 1.0)

Discussion:
40.D.1 – Introduction
This appendix describes of the transmitter electrical specifications for the BER verification test suite usedby the University of New Hampshire.
40.D-2 – Transmitter Specifications
Table 40.D-1: Summary of results from 1000BASE-T PMA testing performed on the 4.61ns Rise Time Transmitter
Test
Parameter
BI_DA
BI_DB
BI_DC
BI_DD
Units
40.1.1 Peak Differential Output Voltage andLevel Accuracy
Magnitude of the voltage at point A
681
685
681
682 mV
Magnitude of the voltage at point B
681
684
678
681 mV
Difference between the magnitudes of thevoltages at points A and B
0.000
0.146
0.441
0.147 %
Difference between the magnitude of thevoltage at point C and 0.5 times theaverage of the voltage magnitudes atpoints A and B
0.587
0.292
0.588
0.880 %
Difference between the magnitude of thevoltage at point D and 0.5 times theaverage of the voltage magnitudes atpoints A and B
0.587
0.292
0.000
0.293 %
40.1.240.1.3

Maximum Output Droop
Ratio of the voltage at point G to thevoltage at point F
Ratio of the voltage at point J to thevoltage at point H

95.8

95.0

95.6

95.7

%

96.12

95.72

95.75

95.62

%

Differential Output Templates
Waveform around point A
Waveform around point B
Waveform around point C
Waveform around point D
Waveform around point F
Waveform around point H

Pass
Pass
Pass
Pass
Pass
Pass

Pass
Pass
Pass
Pass
Pass
Pass

Pass
Pass
Pass
Pass
Pass
Pass

Pass
Pass
Pass
Pass
Pass
Pass

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Table 40.D-2: Summary of results from 1000BASE-T PMA testing performed on the 5.12ns Rise Time Transmitter
Test
Parameter
BI_DA
BI_DB
BI_DC
BI_DD
Units
40.1.1 Peak Differential Output Voltage andLevel Accuracy
Magnitude of the voltage at point A
693
696
692
695 mV
Magnitude of the voltage at point B
693
696
688
692 mV
Difference between the magnitudes of thevoltages at points A and B
0.000
0.000
0.578
0.432 %
Difference between the magnitude of thevoltage at point C and 0.5 times theaverage of the voltage magnitudes atpoints A and B
0.578
0.862
0.290
0.576 %
Difference between the magnitude of thevoltage at point D and 0.5 times theaverage of the voltage magnitudes atpoints A and B
0.578
0.000
0.290
0.288 %
40.1.240.1.3

Maximum Output Droop
Ratio of the voltage at point G to thevoltage at point F
Ratio of the voltage at point J to thevoltage at point H

95.8

95.3

95.4

95.6

%

96.14

95.69

95.99

95.66

%

Differential Output Templates
Waveform around point A
Waveform around point B
Waveform around point C
Waveform around point D
Waveform around point F
Waveform around point H

Pass
Pass
Pass
Pass
Pass
Pass

Pass
Pass
Pass
Pass
Pass
Pass

Pass
Pass
Pass
Pass
Pass
Pass

Pass
Pass
Pass
Pass
Pass
Pass

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Appendix 40.E – Rise Time Calculation
Purpose: To present the methodology used to find the rise time of a 1000Base-T transmitter.
Last Modification:

January 9, 2004 (Version 1.0)

Discussion:
40.E.1 – Introduction
This appendix describes of the methodology used by the University of New Hampshire to determine therise time of the transmitter configuration used in the 1000Base-T PMA Receiver Test Suite. This description isintended to be an example for those that wish to implement the test suite in their own lab.
40.E-2 – Rise Time Estimation
Signal rise is defined as a transition from the baseline voltage to +Vout. The signal rise time is defined to be
the time difference between the points where the signal transition crosses 10% and 90% of Vout.
The standard does not define a rise time requirement for 1000Base-T, nor does it describe a method inwhich to measure the rise time. This test suite utilizes the “A” reference pulse in the Test Mode 1 waveform tocalculate the transmitter rise time. The rise time of this pulse is measured from the 10% to 90% marks of the risingedge of the pulse, as shown below in Figure 40.E-1
Sample Positive Rise Time Reference Pulse
1

Volts (V)

0.8

0.6

0.4

0.2

10%-90% levels
crossing times

0
0

5

10

15
Time (ns)

20

25

30

Figure 40.E-1: Sample Positive Rise Time Measurement

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Appendix 40.F – Category 5e Cable Test Environment
Purpose: To examine the specifications of a category 5e cable test environment.
Last Modification:

January 9, 2004 (Version 1.0)

Discussion:
Since equalizers often tend to be optimized for particular cable conditions the test procedure uses both highattenuation and a low attenuation environment. The high attenuation testing is done over a Category 5e compliant
channel attenuated to simulate a worst-case environment equivalent of 60 degrees (Refer to Table 40.F-1). The low
attenuation testing is done over a Category 5e compliant channel specified in Table 40.F-1. Each of these channels
must be tested to ensure that they meet the expected characteristics as defined by their associated standards.
Table 40.F-1: UTP Channel Definitions
Insertion Loss –Low (+/- 1 dB)aTechnology
1000BASE-T

Media Type
Category-5 UTP

32 Mhz14.2
aInsertion loss is the sum of channel attenuation and connector losses.

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16 MHz9.9

57

Insertion Loss –High (+/- 1 dB)a
100 Mhz
25.7

16 MHz0.6

32 MHz1.0

100 MHz
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InterOperability Laboratory
Appendix 40.G – Transmitter Distortion Measurement
Purpose: To provide an alternate measurement method for transmitter distortion
References:[1] IEEE Std. 802.3-2005TM, subclause 40.6.1.2.4
Last Modification: April 11, 2008 (Version 2.0)
Discussion:
Reference [1] outlines the method for performing the transmitter distortion measurement. The peak
distortion, as stated in [1] is determined by sampling the differential Test Mode 4 signal with symbol rate TX_TCLK
at varying phase and processing any 2047 consecutive samples with Matlab. Because not all implementations have
TX_TCLK access available, the Test Mode 4 signal is downloaded and the reference clock is extracted using a
Clock and Data Recovery module written in Matlab.
Across the unit interval, the peak distortion value varies widely, as expected. Each device uses a different
method of TX_TCLK implementation, which amounts to a different amount of jitter, delay and distortion between
the TX_TCLK and Test Mode 4 signal. Since the delay is unknown, the sampling offset is varied from .025 UI to 1
UI in increments of .025 UI. Figure 40.G-1 shows how the peak distortion value varies depending on sample phasefor various test mode 4 waveforms observed.
Peak Distortion vs. Phase offset
7.5
7Peak Distortion (mV)

6.5
6
5.5
5
4.5
4
3.5
3

0

0.1

0.2

0.3
0.4
0.5
0.6
0.7
Sampling Phase Offset (ui)

0.8

0.9

1

Figure 40.G-1: Peak Transmitter Distortion vs. Sampling PhaseTo determine an averaging factor that will produce consistent results over a long enough sample, the peak
distortion was calculated using a fixed phase offset of 0.3 UI and a varying averaging factor of 1 to 380.

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Figure 40.G-2: Peak Transmitter Distortion vs. Average Factor
As figure 40.G-2 shows, the minimum distortion value occurs at different values of averaging factors
depending upon the sample chosen. It was found that the minimum peak distortion value occurred at different
averaging factors for every test case. Because determining the optimal averaging factor for each test case is notpractical, we look to find a value which is consistently within a certain percentage of the minimum. Figure 40.G-2

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InterOperability Laboratoryshows that all values between an averaging factor of 150 and 200 are less than 1mV from the minimum measured
value. For this reason, an averaging factor of 160 is chosen. Figure 40.G-4 shows all the peak distortion difference
from the minimum for 18 DUTs tested.

Peak Distortion (diff from min) vs. DUT for Avgfac of 160
0.7
Avg: 0.33

Distortion difference (mV)

0.6

0.5

0.4

0.3

0.2

0.1

0

0

2

4

6

8

10

12

14

16

18

DUT

Figure 40.G-3: Peak Transmitter Distortion difference from min. vs. DUT (Davg = 160)
W aveform vs. sampling time
Original waveform
Sample points
Ref. Clock

0.2
0.15
0.1

Volts

0.05
0
-0.05
-0.1
-0.15
-0.2
-0.25
1.7

1.8

1.9

2

2.1

2.2
Time (s)

2.3

2.4

2.5

2.6
x 10

-8

Figure 40.G-4: Waveform vs. sampling time

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InterOperability Laboratory
Appendix 40.H – Transmitter Distortion Research
References:[1] IEEE 802.3-2005TM Subclause 40.6.1.1.2 – Test Modes[2] IEEE 802.3-2005TM Subclause 40.6.1.1.3 – Test Fixtures[3] IEEE 802.3-2005TM Subclause 40.6.1.2.4 – Transmitter Distortion[4] IOL 1000BASE-T PMA Test Suite, Appendix 40.G – Transmitter Distortion Measurement[5] IOL 1000BASE-T PMA Test Suite, Appendix 40.A – Test Fixtures
Last Modificaton: October 8, 2004
Abstract
The distortion of a signal can be measured by finding the difference between the ideal signal and the actual
signal. The distortion could come in the form of amplitude difference, jitter, and many other areas. The error may
come from various sources such as outside noise, or it may be due to imperfections in the transmitter.
To measure the distortion of the 1000BASE-T PHY, a pre-defined test mode 4 sequence has been definedin reference [1]. Reference [3] specifies a procedure that uses this test mode 4 waveform as well as a test fixture,
which introduces noise to the device under test (DUT). Reference [3] also provides Matlab code to measure thedistortion between the observed signal and an ideal test mode 4 waveform. This code is inefficient and uses anarbitrary phase to sample the data. Reference [4] explains the IOL’s technique, which uses various phase offsets tosample the data and measure the distortion.
As mentioned before, reference [3] specifies that the measurement must be made using test fixture 3. This
test fixture has been replaced with the one described in reference [5]. While there is less quantization error, the test
fixture must be compensated for and the disturbing signal must be removed. The purpose of this paper is todetermine what is the best way to process the test mode 4 waveform to produce the most accurate distortion results.
Because there are a number of different ways the sine removal, clock recovery, test fixture compensation
and waveform processing size can be implemented, some research was needed to find which combination produced
the lowest peak distortion value. The research involved changing the size of the block the clock was recovered
from, including or excluding sine removal, whether the test fixture was compensated for on the entire waveform orindividual blocks, and several other variables. All the tests performed are shown in table 1.
All data was sampled at 1.25GS/s with Test Fixture 3 in place.

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A - Discussion
Table A-1: Combinations for distortion processing
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Process whole wfm, no sine removal, compensation
Process whole wfm, sine removal, compensation
Process first 1 million points, no sine removal, compensation
Process first 1 million points, sine removal, compensation
Process second 1 million points, no sine removal, compensation
Process second 1 million points, sine removal, compensation
Process third 1 million points, no sine removal, compensation
Process third 1 million points, sine removal, compensation
Process fourth 1 million points, no sine removal, compensation
Process fourth 1 million points, sine removal, compensation
Process whole wfm in blocks, no sine removal, compensation on whole wfm
Process whole wfm in blocks, no sine removal, compensation in each block
Process whole wfm in blocks, do sine removal on whole wfm, compensation on whole wfm
Process whole wfm in blocks, do sine removal on whole wfm, compensation in each block
Process first 1 million points in blocks, no sine removal, compensation on whole wfm
Process first 1 million points in blocks, no sine removal, compensation in each block
Process first 1 million points in blocks, do sine removal on whole wfm, compensation on whole wfm
Process first 1 million points in blocks, do sine removal on whole wfm, compensation in each block
Process second 1 million points in blocks, no sine removal, compensation on whole wfm
Process second 1 million points in blocks, no sine removal, compensation in each block
Process second 1 million points in blocks, do sine removal on whole wfm, compensation on whole wfm
Process second 1 million points in blocks, do sine removal on whole wfm, compensation in each block
Process third 1 million points in blocks, no sine removal, compensation on whole wfm
Process third 1 million points in blocks, no sine removal, compensation in each block
Process third 1 million points in blocks, do sine removal on whole wfm, compensation on whole wfm
Process third 1 million points in blocks, do sine removal on whole wfm, compensation in each block
Process fourth 1 million points in blocks, no sine removal, compensation on whole wfm
Process fourth 1 million points in blocks, no sine removal, compensation in each block
Process fourth 1 million points in blocks, do sine removal on whole wfm, compensation on whole wfm
Process fourth 1 million points in blocks, do sine removal on whole wfm, compensation in each block

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InterOperability Laboratory
Distortion Findings:
Distortion Stats for HP_4395A_TM4_FIX3_125GS_BI_DC
30
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29

25

20

15

10

5

0
0.2

0.3

0.4

0.5

0.6
Best PK 3.31, Best I 2

0.7

0.8

0.9

1

Figure A-1: Distortion Testing for all 30 test cases on one DUT.
All lines within the box are tests that compensate for the test fixture within each block processed. As figure
1 shows, compensation in each block is not a viable possibility. With this option removed and lowering the block
size to 3 million points (the averaging factor of 100 fits well within a 3 million point sample), we are left with theoptions shown in table 2.

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InterOperability Laboratory
Table A-2: Final distortion combinations
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

Process whole wfm, no sine removal, compensation
Process whole wfm, sine removal, compensation
Process first 1 million points, no sine removal, compensation
Process first 1 million points, sine removal, compensation
Process second 1 million points, no sine removal, compensation
Process second 1 million points, sine removal, compensation
Process third 1 million points, no sine removal, compensation
Process third 1 million points, sine removal, compensation
Process whole wfm in blocks, no sine removal, compensation on whole wfm
Process whole wfm in blocks, do sine removal on whole wfm, compensation on whole wfm
Process first 1 million points in blocks, no sine removal, compensation on whole wfm
Process first 1 million points in blocks, do sine removal on whole wfm, compensation on whole wfm
Process second 1 million points in blocks, no sine removal, compensation on whole wfm
Process second 1 million points in blocks, do sine removal on whole wfm, compensation on whole wfm
Process third 1 million points in blocks, no sine removal, compensation in each block
Process third 1 million points in blocks, do sine removal on whole wfm, compensation in each block

These 16 tests were performed on 18 different sets of data. Each test calculated the peak distortion whilechanging the sampling phase offset from 0.05 to 1 UI from the recovered clock. The results from the testing aredisplayed in figures 1 though 36. Figures 1 through 18 contain the results from tests 1-9 in table 2, and figures 19
through 36 contain results from tests 9-18. Breaking them apart hopefully allows for a less confusing picture.
B – Results

The results from 22 different DUTs is shown on pages 4 through 23.

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InterOperability Laboratory
Figure B−1: Distortion Stats for DUT 1
11
1
2
3
4
5
6
7
8

10

9

Distortion (mV)

8

7

6

5

4

3

0

0.1

0.2

0.3

0.4
0.5
0.6
Best PK 3.74, Best test case 6

0.7

0.8

0.9

1

Figure B−2: Distortion Stats for DUT 1 (Block Processing)
20
1
2
3
4
5
6
7
8

18

16

Distortion (mV)

14

12

10

8

6

4

0

0.1

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0.4
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0.6
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InterOperability Laboratory
Figure B−3: Distortion Stats for DUT 3
10
1
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3
4
5
6
7
8

9

Distortion (mV)

8

7

6

5

4

3

0

0.1

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0.4
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0.6
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Figure B−4: Distortion Stats for DUT 3 (Block Processing)
13
1
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5
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8

12

11

10

Distortion (mV)

9

8

7

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4

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0

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InterOperability Laboratory
Figure B−5: Distortion Stats for DUT 5
13
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8

12

11

Distortion (mV)

10

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4

0

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0.4
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0.6
Best PK 4.24, Best test case 8

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1

Figure B−6: Distortion Stats for DUT 5 (Block Processing)
16
1
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7
8

14

Distortion (mV)

12

10

8

6

4

0

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InterOperability Laboratory
Figure B−7: Distortion Stats for DUT 7
11
1
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7
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9

Distortion (mV)

8

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3

0

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Figure B−8: Distortion Stats for DUT 7 (Block Processing)
12
1
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11

10

Distortion (mV)

9

8

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Figure B−9: Distortion Stats for DUT 9
9
1
2
3
4
5
6
7
8

8

Distortion (mV)

7

6

5

4

3

0

0.1

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Best PK 3.29, Best test case 1

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Figure B−10: Distortion Stats for DUT 9 (Block Processing)
20
1
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3
4
5
6
7
8

18

16

Distortion (mV)

14

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10

8

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4

2

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Figure B−11: Distortion Stats for DUT 11
11
1
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4
5
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7
8

10

9

Distortion (mV)

8

7

6

5

4

3

0

0.1

0.2

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0.4
0.5
0.6
Best PK 3.28, Best test case 1

0.7

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Figure B−12: Distortion Stats for DUT 11 (Block Processing)
16
1
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3
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8

14

Distortion (mV)

12

10

8

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2

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Figure B−13: Distortion Stats for DUT 13
9
1
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4
5
6
7
8

8

Distortion (mV)

7

6

5

4

3

0

0.1

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0.3

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Best PK 3.37, Best test case 1

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Figure B−14: Distortion Stats for DUT 13 (Block Processing)
13
1
2
3
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8

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11

10

Distortion (mV)

9

8

7

6

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3

0

0.1

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Figure B−15: Distortion Stats for DUT 15
10
1
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4
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6
7
8

9

Distortion (mV)

8

7

6

5

4

3

0

0.1

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0.3

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Best PK 3.47, Best test case 6

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Figure B−16: Distortion Stats for DUT 15 (Block Processing)
13
1
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Distortion (mV)

9

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Figure B−17: Distortion Stats for DUT 17
10
1
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4
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7
8

9.5

9

8.5

Distortion (mV)

8

7.5

7

6.5

6

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0

0.1

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0.3

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Best PK 5.34, Best test case 2

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Figure B−18: Distortion Stats for DUT 17 (Block Processing)
14
1
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12

Distortion (mV)

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Figure B−19: Distortion Stats for DUT 19
13
1
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12

11

Distortion (mV)

10

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Figure B−20: Distortion Stats for DUT 19 (Block Processing)
18
1
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16

Distortion (mV)

14

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Figure B−21: Distortion Stats for DUT 21
13
1
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8

12

11

Distortion (mV)

10

9

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Figure B−22: Distortion Stats for DUT 21 (Block Processing)
14
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Distortion (mV)

10

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Figure B−23: Distortion Stats for DUT 23
15
1
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14

Distortion (mV)

13

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Figure B−24: Distortion Stats for DUT 23 (Block Processing)
16
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Distortion (mV)

13

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Figure B−25: Distortion Stats for DUT 25
12
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11

Distortion (mV)

10

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Figure B−26: Distortion Stats for DUT 25 (Block Processing)
16
1
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Distortion (mV)

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Clause 40 PMA Test Suite v2.5

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InterOperability Laboratory
Figure B−27: Distortion Stats for DUT 27
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Figure B−28: Distortion Stats for DUT 27 (Block Processing)
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The University of New Hampshire
InterOperability Laboratory
Figure B−29: Distortion Stats for DUT 29
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Figure B−30: Distortion Stats for DUT 29 (Block Processing)
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Clause 40 PMA Test Suite v2.5

The University of New Hampshire
InterOperability Laboratory
Figure B−31: Distortion Stats for DUT 31
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Figure B−32: Distortion Stats for DUT 31 (Block Processing)
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Clause 40 PMA Test Suite v2.5

The University of New Hampshire
InterOperability Laboratory
Figure B−33: Distortion Stats for DUT 33
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Figure B−34: Distortion Stats for DUT 33 (Block Processing)
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Clause 40 PMA Test Suite v2.5

The University of New Hampshire
InterOperability Laboratory
Figure B−35: Distortion Stats for DUT 35
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Figure B−36: Distortion Stats for DUT 35 (Block Processing)
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Clause 40 PMA Test Suite v2.5

The University of New Hampshire
InterOperability Laboratory
As one can observe, in most cases, the best option is to use test 1 or 2. These produce not only the lowest
overall peak distortion, but a phase offset curve which is consistently lower than the average of the rest. Test option
1 is to run the test without disturber removal, while option 2 is to remove the disturbing waveform. The clear option
between these two options is to remove the disturbing waveform, as reference [1] specifies that it must be done.
If the device under test has access to the TX_TCLK, this is used as a reference for computing distortion.
These test cases were verified for devices both with and without TX_TCLK access.

C - Conclusion
From all the test cases performed in the computation of transmitter distortion, the option chosen by the
IOL:






Uses a 4 million point block
Uses an averaging factor of 160
Compensates for test fixture 3 using the entire 4 million point block
Removes the disturbing waveform using the entire 4 million point block
Extracts the reference clock from the entire 4 million point block

Gigabit Ethernet Consortium

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Clause 40 PMA Test Suite v2.5