Data Communications Family

Z380 Microprocessor

Product Specification
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Copyright ©2008 by Zilog®, Inc. All rights reserved.
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Z380 Microprocessor
Product Specification

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Z380 Microprocessor
Product Specification

Revision History
Each instance in Revision History reflects a change to this document from its previous
revision. For more details, refer to the corresponding pages and appropriate links in thetable below.

Date

Revision Level

Description

Page No

July 2008

02

Updated format to the latest PS
template

All

March 2001

01

Original Issue

All

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Revision History

Z380 Microprocessor
Product Specification

FEATURES

PS010002-0708•••

Static CMOS Design with Low-Power Standby Mode Option•

Enhanced Instruction Set that Maintains Object-Code Compatibility with Z80® andZ180 Microprocessors

•
•
•
•
•
•
•

16-Bit (64K) or 32-Bit (4G) Linear Address Space•

100-Pin QFP Package

32-Bit Internal Data Paths and ALU
Operating Frequency– DC-to-18 MHz at 5V– DC-to-10 MHz at 3.3V

16-Bit Data Bus with Dynamic Sizing
Two-Clock Cycle Instruction Execution Minimum
Four Banks of On-Chip Register Files
Enhanced Interrupt Capabilities, Including 16-Bit Vector
Undefined Opcode Trap for Z380™ Instruction Set
On-Chip I/O Functions:– Six-Memory Chip Selects with Programmable Waits– Programmable I/O Waits– DRAM Refresh Controller

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Z380 Microprocessor
Product Specification

GENERAL DESCRIPTIONThe Z380 Microprocessor is an integrated high-performance microprocessor with fast andefficient throughput and increased memory addressing capabilities. The Z380 offers a continuing growth path for present Z80-or Z180-based designs, while maintaining Z80® CPU
and Z180 MPU object-code compatibility. The Z380 MPU enhancements include an
improved 280 CPU, expanded 4-Gbyte space and flexible bus interface timing.
An enhanced version of the Z80 CPU is key to the Z380 MPU. The basic addressing
modes of the Z80 microprocessor have been augmented as follows: Stack Pointer Relative
loads and stores, 16-bit and 24-bit indexed offsets, and more flexible Indirect Register
addressing, with all of the addressing modes allowing access to the entire 32-bit address
space. Additions made to the instruction set, include a full complement of 16-bit arithmetic and logical operations, 16-bit I/O operations, multiply and divide, plus a complete setof register-to-register loads and exchanges.
The expanded basic register file of the Z80 MPU microprocessor includes alternate register versions of the IX and IY registers. There are four sets of this basic Z80 microprocessor register file present in the Z380 MPU, along with the necessary resources to manage
switching between the different register sets. All of the register-pairs and index registers inthe basic Z80 microprocessor register file are expanded to 32 bits.
The Z380 MPU expands the basic 64 Kbyte Z80 and Z180 address space to a full 4 Gbyte(32-bit) address space. This address space is linear and completely accessible to the user
program. The I/O address space is similarly expanded to a full 4 Gbyte (32-bit) range and16-bit I/O, and both simple and block move are added.
Some features that have traditionally been handled by external peripheral devices havebeen incorporated in the design of the Z380 microprocessor. The on-chip peripherals
reduce system chip count and reduce interconnection on the external bus. The Z380 MPU
contains a refresh controller for DRAMs that employs a /CAS-before-/RAS refresh cycle
at a programmable rate and burst size.
Six programmable memory-chip selects are available, along with programmable waitstate generators for each chip-select address range.
The Z380 MPU provides flexible bus interface timing, with separate control signals andtiming for memory and I/O. The memory bus control signals provide timing references
suitable for direct interface to DRAM, static RAM, EPROM, or ROM. Full control of thememory bus timing is possible because the /WAIT signal is sampled three times during amemory transaction, allowing complete user control of edge-to-edge timing between thereference signals provided by the Z380 MPU. The I/O bus control signals allow directinterface to members of the Z80 family of peripherals, the Z8000 family of peripherals, or
the Z8500 series of peripherals. Figure 1 shows the Z380 block diagram; Figure 2 shows
the pin assignments.

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Z380 Microprocessor
Product Specification

All signals with a preceding front slash, "/", are active Low e.g., B//W (WORD is activeLow); B/W is active Low, only)

Note:

Clock withStandby Control

External Interface Logic/INT3-0/NMI/RESET

/BACK

/BREQ

I/O BUS CNTLS

MEM BUS CNTLS

VSS

/WAIT

GND

MSIZE

Ground

D15-0

VDD

A31-0

VCC

/LMCS/UMCS/MCS3-0

Power

/HALT

Device/STNBY

Circuit

IOCLK

Connection

BUSCLK

CLKO

CLKI

CLKSELPower connections follow conventional descriptions below:

Interrupts

Chip Selectsand Waits

CPU
RefreshConrol/EV
Data (16)VDD
Address (32)

VSS

Figure 1. Z380 Functional Block Diagram

Figure 1. Z380 Functional Block Diagram

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Z380 Microprocessor
Product Specification

A5
A4
A3

1

100

90

95

85

80

A24

2

A25
A26

A2
A1
A0

5
75

VSS

A31
VSS

10
70

D1
D2

Z380
100-Pin QFP

15

65

/MRD
/MWR
/MSIZE/WAIT
BUSCLK
IOCLK

VDD
VSS
D0

/TREFA/TREFC
/BHEN
/BLEN

A27
A28
A29
A30

VDD
VSS
VDD
/TREFR

A23

D3
D4
D5
D6
D7

20
60

/M1

D8
D9

/IORQ

D10

/IORD
CLKI
CLKO

D11
D12

25
55

/IOWR

D13
D14

VSS

D15

VDD
VSS

VDD

30

35

40

45

50

VSS

Figure 2. 100-Pin QFP Pin Assignments

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Z380 Microprocessor
Product Specification

PIN DESCRIPTION
A31-A0 Address Bus (outputs, activeHigh, tri-state).These non-multiplexed address signals provide a linear memory address space of four gigabytes. The 32-address signals arealso used to access I/O devices.
/BACK Bus Acknowledge (output, active Low, tri-state). This signal, when asserted, indi-cates that the Z380 MPU has accepted an external bus request and has tri-stated its output
drivers for the address bus, data bus and the bus control signals /TREFR, /TREFA, /TREFC, /BHEN, /BLEN, /MRD, /MWR, /IORQ, /IORD, and /IOWR. Note that the Z380
MPU cannot provide any DRAM refresh transactions while it is in the bus acknowledge
state.
/BHEN Byte High Enable (output, active Low, tri-state). This signal is asserted at the
beginning of a memory, or refresh transaction to indicate that an operation on D15-D8 isrequested. For a 16-bit memory transaction, if /MSIZE is asserted, indicating a byte-wide
memory, another memory transaction is performed to transfer the data on D15-D8, thistime through D15-D8.
/BLEN Byte Low Enable (output, active Low, tri-state). This signal is asserted at the
beginning of a memory or refresh transaction to indicate that an operation on D7-D0 isrequested. For a 16-bit memory transaction, if /MSIZE is asserted, indicating a byte-wide
memory, only the data on D7-D0 will be transferred during this transaction, and anothertransaction will be performed to transfer the data on D15-D8, this time through D7-D0.
/BREQ Bus Request (input, active Low). When this signal is asserted, an external bus

master is requesting control of the bus. /BREQ has higher priority than all nonmaskableand maskable interrupt requests.
BUSCLK Bus Clock (output, active High, tri-state). This signal, output by the Z380 MPU,
is the reference edge for the majority of other signals generated by the Z380 MPU. BUSCLK is a delayed version of the CLK input.
CLKI Clock/Crystal (input, active High). An externally generated direct clock can be input

at this pin and the Z380 MPU would operate at the CLKI frequency. Alternatively, a crystal up to 20 MHz can be connected across CLKI and CLKO, and the Z380 MPU would
operate at half of the crystal frequency. The two clocking options are controlled by the
CLKsel input.
CLKO Crystal (output, active High). Crystal oscillator connection. This pin should be left

open if an externally generated direct clock is input at the CLKI pin.
CLKsel Clock Option Select (input, active High). This input should be connected to VDD
to select the direct clock option and should be connected to VSS for the crystal option.
D15-D0 Data Bus (input/outputs, active High, tri-state). This bi-directional 16-bit databus is used for data transfer between the Z380 MPU and memory or I/O devices. Note thatfor a memory word transfer, the even-addressed (A0 = 0) byte is generally transferred on
D15-D8, and the odd-addressed (A0 = 1) byte on D7-D0 (see the /MSIZE pin description).

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Z380 Microprocessor
Product Specification/EV Evaluation Mode (input, active Low). This input should be left unconnected for nor-mal operation. When it is driven to logic 0, the Z380 MPU conditions itself in the resetmode and tri-states all of its output pin drivers.
/HALT Halt Status (output, active Low, tri-state). If the Z380 MPU standby mode option
is not selected, a Sleep instruction is executed no different than a Halt instruction, and theone HALT signal goes active to indicate the CPU's HALT state. If the standby mode
option is selected, this signal goes active only at the Halt instruction execution.
/STNBY Standby Status (output, active Low, tri-state). If the Z380 MPU standby mode isselected, executing a sleep instruction stops clocking within the Z380 MPU and at BUSCLK and IOCLK after which this signal is asserted. The Z380 MPU is then in the low
power standby mode, with all operations suspended.
/INT3-0 Interrupt Requests (inputs, active Low). These signals are four asynchronousmaskable interrupt inputs.
IOCLK I/O Clock (output, active High, tri-state). This signal is a program controlled
divided-down version of BUSCLK. The division factor can be two, four, six or eight with
I/O transactions and interrupt-acknowledge transactions occurring relative to IOCLK.
/INTAK Interrupt Acknowledge Status (output, active Low, tri-state). This signal is used to

distinguish between I/O and interrupt acknowledge transactions. This signal is High during I/O read and I/O write transactions and Low during interrupt acknowledge transactions.
/IORQ Input/Output Request (output, active Low, tri-state). This signal is active during all
I/O read and write transactions and interrupt acknowledge transactions.
/M1 Machine Cycle One (output, active Low, tri-state). This signal is active during inter-rupt acknowledge and RETI transactions.
/IORD Input, Output Read Strobe (output, active Low, tri-state). This signal is used strobe

data from the peripherals during I/O read transactions. In addition, /IORD is active during
the special RETI transaction and the I/O heartbeat cycle in the Z80 protocol case.
/IOWR Input/Output Write Strobe (output, active Low, tri-state). This signal is used to
strobe data into the peripherals during I/O write transactions.
/LMCS Low Memory Chip Select (output, active Low, tri-state). This signal is activatedduring a memory read or memory write transaction when accessing the lower portion of
the linear address space within the first 16 Mbytes, but only if this chip select function isenabled.
/MCS3-/MCS0 Mid-range Memory Chip Selects (output, active Low, tri-state). These sig-

nals are individually active during memory read or write transactions when accessing the
mid-range portions of the linear address space within the first 16 Mbytes. These signals
can be individually enabled or disabled.
/MRD Memory Read (output, active Low, tri-state). This signal indicates that theaddressed memory location should place its data on the data bus as specified by the /PS010002-0708

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Z380 Microprocessor
Product Specification

BHEN and /BLEN control signals. /MRD is active from the end of T1 until the end of T4
during memory read transactions.
/MSIZE Memory Size (input, active Low). This input, from the addressed memory location, indicates if it is word size (logic High) or byte size (logic Low). In the latter case, theaddressed memory should be connected to the D15-D8 portion of the data bus, and an
additional memory transaction will automatically be generated to complete a word size
data transfer.
/MWR Memory Write (output, active Low, tri-state). This signal indicates that theaddressed memory location should store the data on the data bus, as specified by the /BHEN and /BLEN control signals. /MWR is active from the end of T2 until the end of T4
during memory write transactions.
/NMI Nonmaskable Interrupt(input, falling edge-triggered). This input has higher priority

than the maskable interrupt inputs /INT3-INT0.
/RESET Reset (input, active Low). This input must be active for a minimum of five BUSCLK periods to initialize the Z380 MPU. The effect of /RESET is described in detail in
the Reset section.
/TREFA Timing Reference A (output, active Low, tri-state). This timing reference signal
goes Low at the end of T2 and returns High at the end of T4 during a memory read, memory write or refresh transaction. It can be used to control the address multiplexer for a
DRAM interface or as the /RAS signal at higher processor clock rates.
/TREFC Timing Reference C (output, activeLow, tri-state). This timing reference signal
goes Low at the end of T3 and returns High at the end of T4 during a memory read, memory write or refresh transaction. It can be used as the /CAS signal for DRAM accesses.
/TREFR Timing Reference R (output, active Low, tri-state). This timing reference signal
goes Low at the end of T1 and returns High at the end of T4 during a memory read, memory write or refresh transaction. It can be used as the /RAS signal for DRAM accesses.
/UMCS Upper Memory ChipSelect (output, active Low, tri-state). This signal is activatedduring a memory read, memory write, or optionally a refresh transaction when accessing
the highest portion of the linear address space within the first 16 Mbytes, but only if thischip select function is enabled.
VDD Power Supply. These eight pins carry power to the device. They must be tied to thesame voltage externally.
VSS Ground. These eight pins are the ground references for the device. They must be tied
to the same voltage externally.
/WAIT Wait (input, active Low). This input is sampled by BUSCLK or IOCLK, as appropriate, to insert Wait states into the current bus transaction.

The conditioning and characteristics of the Z380 MPU pins under various operation
modes are defined in Table 1.

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Z380 Microprocessor
Product Specification

Table 1. Z380 MPU Pin ConditioningpCharacteristics Operation Mode Conditions
Pin
Names

Normal/BREQ=1,/BACK=1,/EV=NCBus Relinquish/BREQ=0,/BACK=0,/EV=NC

Evaluation

CLKI
CLKO
CLKSEL
BUSCLKIOCLK
A31-A0

Input
Output/No Connection
Input
OutputOutputOutputInput
Output/No Connection
Input
OutputOutputTri-state

Input
No Connection
Input
Tri-state
Tri-state
Tri-state

D15-D0/TREFR,/TREFA,/TREFC/MRD,/MWR/BHEN,/BLEN/LMCS,/UMCS,/MCS3-MCS0

Input/Output
OutputTri-state
Tri-state

Tri-state
Tri-state

OutputOutputOutputTri-state
Tri-state
Tri-state

Tri-state
Tri-state
Tri-state/MSIZE,/WAIT/HALT,/STNBY/M1,/INTAK/IORQ,/IORD,
/IOWR
/BREQ
/BACK

Input
OutputOutputOutputInput
OutputOutputTri-state

Input
Tri-state
Tri-state
Tri-state

Input
OutputInput
OutputInput
Tri-state/NMI,/INT3-/INT0/RESET
/EV
VDD
VSS

Input
Input
No Connection
Power
GroundInput
Input
No Connection
Power
Ground

Input
Input
Input
Power
GroundEXTERNAL INTERFACE
Two kinds of operations can occur on the system bus: transactions and requests. At any
given time, one device (either the CPU or a bus master) has control of the bus and is
known as the bus master.
This section shows all of the transaction and request timing for the device. For the sake ofclarity, there are more figures than are actually necessary. This should aid the reader rather
than confuse. In all of the timing diagram figures, the row labelled STATUS encompasses/BHEN, /BLEN, and the chip select signals.

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Z380 Microprocessor
Product Specification

Transactions
A transaction is initiated by the bus master and is responded to by some other device on
the bus. Only one transaction can proceed at a time; six kinds of transactions can occur:
Memory, Refresh, I/O, Interrupt Acknowledge, RETI (Return from Interrupt), and Halt.
The Z380 MPU is unique in that memory and I/O bus transactions use separate control
signals. This allows the memory interface to be optimized independently of the I/O interface.
Memory Transactions
Memory transactions move instructions or data to or from memory when the Z380 MPU
performs a memory access. Thus, they are generated during program execution to fetch
instructions from memory and to fetch and store memory data. They are also generated tostore old program status and fetch new program status during interrupt and trap handling,
and are used by DMA peripherals to transfer information. A memory transaction is twoclock cycles long unless extended with wait states. Wait states may be inserted between
each of the four T states in a memory transaction and are one BUSCLK cycle long per
wait state. The external /WAIT input is sampled only after any internally-generated waitstates are inserted. Memory transactions may transfer either bytes or words. If the Z380
MPU attempts to transfer a word to a byte-wide memory, the /MSIZE signal should beasserted Low to force this transaction to be byte-wide dynamically. The Z380 MPU willthen perform another memory transaction to transfer the byte that was not transferred during the first transaction.
Read memory transactions are shown without wait states, with wait states between T1 andT2, between T2 and T3, and between T3 and T4 (Figures 3 - 6). The data bus is driven by
the memory being addressed, and the memory data is latched immediately before the rising edge of BUSCLK which terminates T4.

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Z380 Microprocessor
Product Specification

T1

T2

T3

T4

BUSCLKADDRESSDATASTATUS/WAIT/MSIZE/TREFR/TREFA/TREFC/MRD/MWR

Figure 3. Read Cycle, No Waits

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Z380 Microprocessor
Product Specification

T1

T1L

T1H

T2

T3

T4

BUSCLKADDRESSDATASTATUS/WAIT/MSIZE/TREFR/TREFA/TREFC/MRD/MWR

Figure 4. Read Cycle, T1 Wait

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Z380 Microprocessor
Product Specification(Continued)
T1

T2

T2H

T2L

T3

T4

BUSCLKADDRESSDATASTATUS/WAIT/MSIZE/TREFR/TREFA/TREFC/MRD/MWR

Figure 5. Read Cycle, T2 Wait

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Z380 Microprocessor
Product Specification

T1

T2

T3

T3L

T3H

T4

BUSCLKADDRESSDATASTATUS/WAIT/MSIZE/TREFR/TREFA/TREFC/MRD/MWR

Figure 6. Read Cycle, T3 Wait

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Z380 Microprocessor
Product Specification

EXTERNAL INTERFACE (Continued)
Write memory transactions are shown without wait states, with wait states between T1 andT2, between T2 and T3, and between T3 and T4 (Figures 7-10). The /MWR strobe is activated at the end of T1, to allow write data setup time for the memory since the write data isdriven on to the data bus at the beginning of T1.
T1

T2

T3

T4

BUSCLKADDRESSDATASTATUS/WAIT/MSIZE/TREFR/TREFA/TREFC/MRD/MWR

Figure 7. Write Cycle, No Waits

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Z380 Microprocessor
Product Specification

T1

T1L

T1H

T2

T3

T4

BUSCLKADDRESSDATASTATUS/WAIT/MSIZE/TREFR/TREFA/TREFC/MRD/MWR

Figure 8. Write Cycle, T1 Wait

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Z380 Microprocessor
Product Specification

T1

T2

T2H

T2L

T3

T4

BUSCLKADDRESSDATASTATUS/WAIT/MSIZE/TREFR/TREFA/TREFC/MRD/MWR

Figure 9. Write Cycle, T2 Wait

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Z380 Microprocessor
Product Specification

T1

T2

T3

T3L

T3H

T4

BUSCLKADDRESSDATASTATUS/WAIT/MSIZE/TREFR/TREFA/TREFC/MRD/MWR

Figure 10. Write Cycle, T3 Wait

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Z380 Microprocessor
Product Specification

EXTERNAL INTERFACE (Continued)
Refresh Transactions
A memory refresh transaction is generated by the Z380 MPU refresh controller and canoccur immediately after the final clock cycle of any other transaction. The address during
the refresh transaction is not defined as the CAS-before-RASrefresh cycle is assumed,which uses the on-chip refresh address generator present on DRAMs. Prior to the firstrefresh transaction, a refresh setup cycle is performed to guarantee that the /CAS precharge time is met. This refresh setup cycle is present only prior to the first refresh transaction in a burst (Figure 11). Refresh transactions are shown without wait states, with waitstates between T1 and T2, between T2 and T3, and between T3 and T4 (Figures 12-15).
Note that during the refresh cycle the data bus is continuously driven, /MRD and /MWR
remain inactive, /BHEN and /BLEN are active to enable all /CAS signals to the DRAMS,
and those Chip Select signals enabled for DRAM refresh transactions are active.
TPH

TPL

BUSCLKADDRESSDATASTATUS/WAIT/MSIZE/TREFR/TREFA/TREFC/MRD/MWR

Figure 11. Refresh Setup

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Z380 Microprocessor
Product Specification

T1

T2

T3

T4

BUSCLKADDRESSDATASTATUS/WAIT/MSIZE/TREFR/TREFA/TREFC/MRD/MWR

Figure 12. Refresh Cycle, No Waits

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Z380 Microprocessor
Product Specification

T1

T1L

T1H

T2

T3

T4

BUSCLKADDRESSDATASTATUS/WAIT/MSIZE/TREFR/TREFA/TREFC/MRD/MWR

Figure 13. Refresh Cycle, T1 Wait

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Z380 Microprocessor
Product Specification

T1

T2

T2H

T2L

T3

T4

BUSCLKADDRESSDATASTATUS/WAIT/MSIZE/TREFR/TREFA/TREFC/MRD/MWR

Figure 14. Refresh Cycle, T2 Wait

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Z380 Microprocessor
Product Specification

T1

T2

T3

T3L

T3H

T4

BUSCLKADDRESSDATASTATUS/WAIT/MSIZE/TREFR/TREFA/TREFC/MRD/MWR

Figure 15. Refresh Cycle, T3 Wait

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Z380 Microprocessor
Product Specification

I/O Transactions
I/O transactions move data to or from an external peripheral when the Z380 MPU performs an I/O access. All I/O transactions occur referenced to the IOCLK signal, when it isa divided-down version of the BUSCLKsignal. BUSCLK may be divided by a factor offrom two to eight to form the IOCLK, under program control. An example of this division
is shown, for the four possible divisors, in Figure 16. Note that the IOCLK divider is synchronized (i.e., starts with a known timing relationship) at the trailing edge of /RESET.
This is discussed in the Reset Section.

BUSCLKIOCLK (X2)

IOCLK (X4)

IOCLK (X6)

IOCLK (X8)

Figure 16. IOCLK Timing

EXTERNAL INTERFACE (Continued)
The Z380 MPU is unique in that it employs separate control signals for accessing thememory and I/O. This allows the two interfaces to be optimized independent of one
another. The I/O bus control signals allow direct connection to members of the Z80 familyof peripherals or the Z8500 family of peripherals.
Note that because all I/O bus transactions start on a rising edge of IOCLK, there may be
up to n BUSCLK cycles of latency between the execution unit request for the transaction
and the transaction actually starting, where n is the programmed clock divisor for IOCLK.
This implies that the lowest possible divisor should always be used for IOCLK.
All I/O transactions are four IOCLK cycles long unless extended by Wait states. Waitstates may be inserted between the third and fourth IOCLK cycles in an I/O transaction
and are one IOCLK cycle per wait state. The external /WAIT input is sampled only after
internally-generated wait states are inserted.

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Z380 Microprocessor
Product Specification

I/O Read transactions are shown with and without a wait state (Figures 17-18). The contents of the data bus is latched immediately before the falling edge of IOCLK during thelast IOCLK cycle of the transaction.
IOCLK

ADDRESS

DATA

/WAIT

/MI

/IORQ

/IORD

/IOWR

/INTAKFi
8A I/O R d C l N W it
Figure 17. I/0Read Cycle, No Waits

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Z380 Microprocessor
Product Specification

IOCLK

ADDRESS

DATA

/WAIT

/MI
/IORQ

/IORD

/IOWR
/INTAKFi

8B I/O R

dCl

T1 W itFigure 18. I/O Read Cycle, T1 Wait

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Z380 Microprocessor
Product Specification

EXTERNAL INTERFACE (Continued)
I/O Write transactions are shown with and without a wait state (Figures 19-20). The databus is driven throughout the transaction.
IOCLK

ADDRESS

DATA

/WAIT

/MI
/IORQ

/IORD
/IOWR

/INTAK

Figure 19. I/O Write Cycle, No Waits

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Z380 Microprocessor
Product Specification

ZILOG

MICROPROCEIOCLK

ADDRESS

DATA

/WAIT

/MI

/IORQ

/IORD

/IOWR

/INTAK

Figure 20. I/O Write Cycle, T1 Wait

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Z380 Microprocessor
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EXTERNAL INTERFACE (Continued)
Interrupt Acknowledge Transactions
An interrupt acknowledge transaction is generated by the Z380 MPU in response to anunmasked external interrupt request. Figure 21 shows an interrupt acknowledge transaction in response to /INT0 and Figure 22 shows an interrupt acknowledge transaction in
response to either one of /INT-3. Note that because all I/O bus transactions start on a risingedge of IOCLK, there may be up to n BUSCLK cycles of latency between the execution
unit request for the transaction and the transaction actually starting (where n is the programmed clock divisor for IOCLK).

IOCLK

ADDRESS

DATA

/WAIT

/M1

/IORQ

/IORD

/IOWR

/INTAK

Figure 21. Interrupt Acknowledge Cycle, /INT0

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IOCLK

ADDRESS

DATA

/WAIT

/MI
/IORQ
/IORD
/IOWR
/INTAK

Figure 22. Interrupt Acknowledge Cycle, /INT3-1

An interrupt acknowledge transaction for /INT0 is five IOCLK cycles long unlessextended by Wait states. /WAIT is sampled at two separate points during the transaction.
/WAIT is first sampled at the end of the first IOCLK cycle during the transaction. Waitstates inserted here allow the external daisy-chain between peripherals with a longer timeto settle before the interrupt vector is requested. /WAIT is then sampled at the end of the
fourth IOCLK cycle to delay the point at which the interrupt vector is read by the Z380
MPU, after it has been requested.
The interrupt vector may be either eight or sixteen bits, under program control, and islatched by the falling edge of IOCLK in the last cycle of the interrupt acknowledge transaction. When using Mode 0 interrupts, where the Z380 MPU fetches an instruction fromthe interrupting device, these fetches are always eight bits wide and are transferred over
D7-D0.

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An interrupt acknowledge transaction in response to one of /INT3-/INT1 is also five
IOCLK cycles long, unless extended by wait states. The waits are sampled and inserted atsimilar locations as an interrupt acknowledge transaction is for /INT0. Note, however,
only the /INTAK signal is active with /MI, /IORQ, /IORD and /IOWR held inactive.
For either type of INTACK transaction the address bus is driven with a value which indicates the type of interrupt being acknowledged as follows: A31-A6 are all one, and A3-A0
are one except for a single zero corresponding to the maskable interrupt being acknowledged. Thus an /INT3 acknowledge is signaled by A3 being zero during the interrupt
acknowledge transaction, /INT2 acknowledge is signalled by A2 being zero, etc.
RETI Transactions
The RETI transaction is generated whenever an RETI instruction is executed by the Z380
MPU. This transaction is necessary because Z80 family peripherals are designed to watch
instruction fetches and take special action upon seeing a RETI instruction (this is the only
instruction that the Z80 family peripherals watch for). Since the Z380 MPU fetches
instructions using the memory control signals, a simulated RETI instruction fetch must beplaced on the bus with the appropriate I/O bus control signals. This is shown in Figure 23.
Again, note that because all I/O bus transactions start on a rising edge of IOCLK, there
may be up to n BUSCLK cycles of latency between the execution unit request for thetransaction and the transaction actually starting, where n is the programmed clock divisor
for IOCLK.

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1

2

3

4

5

6

7

8

9

10

IOCLK

ADDRESS

DATA

EDED

4D4D

/WAIT

/M1

/IORQ

/IORD

/IOWR

/INTAK

Figure 23. Return From Interrupt Cycle

The RETI transaction is ten IOCLK cycles long unless extended by Wait states, and/WAIT is sampled at three separate points during the transaction. /WAIT is first sampled in
the middle of the third IOCLK cycle to allow for longer/IORDLow-time requirements.
/WAIT is then sampled again during the middle of the fifth IOCLK cycle to allow for longer internal daisy-chain settling time within the peripheral. Wait states inserted here havethe effect of separating what the peripheral sees as two separate instruction fetch cycles.
Finally, /WAIT is sampled in the middle of the ninth IOCLK cycle, again to allow for longer /IORD Low-time requirements.
The Z380 MPU drives the data bus throughout the RETI transaction, with EDEDH during
the first half of the transaction (the first byte of a RETI instruction is EDH) and with
4D4DH during the second half of the transaction (the second byte of an RETI instruction
is 4DH).

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HALT Transactions
A HALT transaction occurs whenever the Z380 MPU executes a Halt instruction, with the/HALT signal activated on the falling edge of BUSCLK. If the standby mode is notenabled, executing a Sleep instruction would also cause a Halt transaction to occur. Whilein the Halt state, the Z380 MPU continues to drive the address and data buses, and the/HALT signal remains active until either an interrupt request is acknowledged or a reset isreceived. Refresh transactions may occur while in the halt state and the bus can be granted.
The timing of entry into the Halt state is shown in Figure 24, while the timing of exitingfrom Halt state is shown in Figure 25.
T5

THL

THH

THL

BUSCLKADDRESSDATASTATUS/WAIT/MSIZE/TREFR/TREFA/TREFC

/MRD

/MWR

/HALT

Figure 24. HALT Entry

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THH

THL

THH

THL

THH

T6

BUSCLKADDRESSDATASTATUS/WAIT/MSIZE/TREFR/TREFA/TREFC

/MRD

/MWR

/HALT
/INT or /NMI

Figure 25. HALT Exit

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Requests
A request can be initiated by a device that does not have control of the bus. Two types ofrequest can occur: Bus request and Interrupt request. When an interrupt or bus request is
made, it is answered by the CPU according to its type. For an interrupt request, the CPU
initiates an interrupt acknowledge transaction and for bus requests, the CPU enters the bus
disconnect state, relinquishes the bus, and activates an Acknowledge signal.
BUS Requests
To generate transactions on the bus, a potential bus master (such as a DMA controller)
must gain control of the bus by making a bus request. A bus request is initiated by driving/BREQ Low. Several bus requesters may be wired-OR to the /BREQ pin; priorities areresolved externally to the CPU, usually by a priority daisy chain.
The asynchronous /BREQ signal generates an internal /BUSREQ, which is synchronous.
If the /BREQ is active at the beginning of any transaction, the internal /BUSREQ causes
the /BACK signal to be asserted after the current transaction is completed. The Z380 MPU
then enters the Bus Disconnect state and gives up control of the bus. All Z380 MPU control signals, except /BACK, /MI and /INTAK are tri-stated. Note that release of the bus
may be inhibited under program control to allow the Z380 MPU exclusive access to ashared resource; this is controlled by the SETC LCK and RESC LCK instructions. Entry
into the Bus Disconnect state is shown in Figure 26. The Z380 MPU regains control of thebus after /BREQ is deasserted. This is shown in Figure 27.
Interrupt Requests
The Z380 MPU supports two types of interrupt requests, maskable /INT3-INT0 and nonmaskable (/NMI). The interrupt request line of a device that is capable of generating aninterrupt can be tied to either /NMI or one of the maskable interrupt request lines, and several devices can be connected to one interrupt request line with the devices arranged in apriority daisy chain. However, because of the need for Z80 family peripheral devices to
see the RETI instruction, only one daisy chain of Z80-family peripherals can be used. The
Z380 MPU handles maskable and nonmaskable interrupt requests somewhat differently,
as follows:
Any High-to-Low transition on the /NMI input is asynchronously edge-detected, and theinternal NMI latch is set. At the beginning of the last clock cycle in the last internal
machine cycle of any instruction, the maskable interrupts are sampled along with the stateof the NMI latch.
If an enabled maskable interrupt is requested, at the next possible time (the next risingedge of IOCLK) an interrupt acknowledge transaction is generated to fetch the interruptvector from the interrupting device.For a nonmaskable interrupt, no interrupt acknowledgetransaction is generated; the NMI service routine always starts at address 00000066H.

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Transaction in progress

T7

TBL

BUSCLKADDRESSDATASTATUS/WAIT/MSIZE/TREFR/TREFA/TREFC

/MRD

/MWR

/BREQ

/BACK

/MI

/IORQ

/IORD

/IOWR

/INTAK

Figure 26. Bus Request/Acknowledge Cycle

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TBH

TBL

TBH

TBL

TBH

TIL

BUSCLKADDRESSDATASTATUS/WAIT/MSIZE/TREFR/TREFA/TREFC

/MRD

/MWR

/BREQ
/BACK

/MI

/IORQ

/IORD

/IOWR

/INTAK

Figure 27. Bus Request/Acknowledge End Cycle

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EXTERNAL INTERFACE (Continued)
Miscellaneous Timing
There are two cases where a specific transaction is not taking place on the bus which areillustrated in this section: the bus idle cycle and the I/O heartbeat cycle.
Idle Cycles
When no transactions are being performed on the bus, an idle cycle occurs (Figure 16). All
control signals, for both memory and I/O, are inactive during the Idle cycle.
TiH

TiL

BUSCLKADDRESSDATASTATUS/WAIT/MSIZE/TREFR/TREFA/TREFC/MRD/MWR

Figure 28. Idle Cycle

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I/O Heartbeat Cycle
The Z380 MPU is capable of generating an I/O heartbeat cycle on the I/O bus in responseto an I/O write to an on-chip control register. This cycle is most useful with Z80 family
peripherals, where some members require a transaction that looks like a Z80 CPU instruction fetch to perform certain interrupt functions (Figure 29).

IOCLK

ADDRESSDATAAll Zeros

/WAIT

/MI

/IORQ

/IORD

/IOWR
/ INTAKFigure 29. I/O Heartbeat Cycle

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EXTERNAL INTERFACE (Continued)
Reset Timing
The timing for entering and exiting the reset state is shown in Figures 30 and 31. The
effects of reset on the internal state of the Z380 MPU are detailed in the Reset section.
The synchronization of IOCLK at the end of the reset state is shown in Figure 32. Notethat the IOCLK divisor is set to the maximum value (eight) by /RESET and is only synchronized at the end of the reset state.
Transaction in progress

T9

TRL

BUSCLKADDRESSDATASTATUS/WAIT/MSIZE/TREFR/TREFA/TREFC/MRD/MWR/IOCTL3-0/RESET

Figure 30. Reset Entry

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TRH

TRL

TRH

TRL

TRH

TiL

BUSCLKADDRESSDATASTATUS/WAIT/MSIZE/TREFR/TREFA/TREFC/MRD/MWR/IOCTL3-0/RESET

Figure 31. Reset Exit

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EXTERNAL INTERFACE (Continued

BUSCLK/RESET

IOCLK

Figure 32. IOCLK Reset Start-up

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CPU ARCHITECTURE
The Central Processing Unit (CPU) of the Z380 MPU is a binary-compatible extension of
the Z80 CPU and Z180 CPU architectures. High throughput rates for the Z380 CPU areachieved by a high clock rate, high bus bandwidth and instruction fetch/execute overlap.
Communicating to the external world through an 8-or 16-bit data bus, the Z380 CPU is afull 32-bit machine internally, with a 32-bit ALU and 32-bit registers.
Modes Of Operation
The Z380 CPU can operate in either Native or Extended mode, as controlled by a bit in the
Select Register (SR). In Native mode (the Reset configuration), all address manipulations
are performed modulo 65536 (16 bits). In this mode the Program Counter (PC) only increments across 16 bits, all address manipulation instructions (increment, decrement, add,
subtract, indexed, stack relative, and PC relative) only operate on 16 bits, and the Stack
Pointer (SP) only increments and decrements across 16 bits. The program counter highorder word is left at all zeros, as is the high-order words of the stack pointer and the I register. Thus Native mode is fully compatible with the Z80 CPU's 64 Kbyte address space. It
is still possible to address memory outside of the 64 Kbyte address space for data storage
and retrieved in Native mode, however, direct addresses, indirect addresses, and the highorder word of the SP, I and the IX and IY registers may be loaded with non-zero values.
But executed code and interrupt service routines must reside in the lowest 64 Kbytes of theaddress space.
In Extended mode, however, all address manipulation instructions operate on 32 bits,
allowing access to the entire 4 Gbyte address space of the Z380 MPU. In both Native andExtended modes, the Z380 CPU drives all 32 bits of the address onto the external address
bus; only the width of manipulated addresses distinguish Native from Extended mode.
The Z380 CPU implements one instruction to allow switching from Native to Extendedmode, but once in Extended mode, only Reset returns the Z380 MPU to Native mode. This
restriction applies because of the possibility of "misplacing" interrupt service routines orvector tables during the translation from Extended mode back to Native mode.
In addition to Native and Extended mode, which is specific to memory space addressing,the Z380 MPU can operate in either Word or Long Word mode specific to data load andexchange operations. In Word mode (the reset configuration), all word load and exchange
operations manipulate 16-bit quantities. For example, only the low-order words of thesource and destination are exchanged in an exchange operation, with the high-order words
unaffected. In Long Word mode, all 32 bits of the source and destination are directives toallow switching between Word and Long Word mode; SETC LW (Set Control Long
Word) and RESC LW (Reset Control Long Word) perform a global switch, while DDIR
W, DDIR LW and their variants are decoder directives that select a particular mode only
for the instruction that they precede.
Note that all word data arithmetic (as opposed to address manipulation arithmetic), rotate,shift and logical operations are always in 16-bit quantities. They are not controlled byeither the Native/Extended or Word/Long Word selections. The exceptions to the 16-bit

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quantities are, of course, those multiply and divide operations with 32-bit products or dividends.
Lastly, all word Input/Output operations are performed on 16-bit values.
Address Spaces
The Z380 CPU architecture supports five distinct address spaces corresponding to the different types of locations that can be accessed by the CPU. These five address spaces are:CPU register space, CPU control register space, memory address space, and I/O address
space (on-chip and external).
CPU Register Space
The CPU register space is shown in Figure 33 and consists of all of the registers in the
CPU register file. These CPU registers are used for data and address manipulation, and are
an extension of the Z80 CPU register set, with four sets of this extended Z80 CPU registerset present in the Z380 CPU. Access to these registers is specified in the instruction, withthe active register set selected by bits in the Select Register (SR) in the CPU control register space.
4 Sets of Registers

BCz
DEz

A

F

B
D

C
E

HLz

H

L

IXz

IXU

IXL

IYz

IYU

IYL

A'

F'

BCz'

B'

C'

DEz'

D'

E'

HLz'

H'

L'

IXz'

IXU'

IXL'

IYz'

IYU'

IYL'

R
Iz

I

SPz

SP

PCz

PC

Figure 33. Register Set

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Each register set includes the primary registers A, F, B, C, D, E, H, L, IX, and IY, as wellas the alternate registers A’, F’, B’, C’, D’, E’, H’, L’, IX’, and IY’. These byte registers
can be paired B with C, D with E, H with L, B’ with C’, D’ with E’ and H’ with L’ to form
word registers. These word registers are extended to 32 bits with the z extension to theregister. This register extension is only accessible when using the register as a 32-bit register (the Long Word mode) or when swapping between the most-significant and least-significant word of a 32-bit register. Whenever an instruction refers to a word register, theimplicit size is controlled by the Word or Long Word mode. Also included are the R, I andSP registers, as well as the PC.
CPU Control Register Space
The CPU control register space consists of the 32-bit Select Register (SR), Figure 34. The
SR may be accessed as a whole or the upper three bytes of the SR may be accessed individually as the YSR, XSR, and DSR. In addition, these upper three bytes can be loadedwith the same byte value. The SR may also be PUSHed and POPed and is cleared to all
zeros on Reset.
YSR

XSR

Reserved (0)
31

30

29

28

27

IYBANK

IYP

Reserved (0)

26

25

24

23

22

21

MAINBANK

ALT

XM

LW

IEF1

10

8

7

6

5

20

19

IXBANK

IXP

18

17

16

0

LCK

AFP

2

1

0

DSR

Reserved (0)
15

14

13

12

11

9

IM
4

3

Figure 34. Select Register
IYBANK (IY Bank Select). This 2-bit field selects the register set to be used for the IY and

IY' registers. This field can be set independently of the register set selection for the otherZ380 CPU registers. Reset selects Bank 0 for IY and IY'.
IYP (IYPrime Register Select). This bit controls and reports whether IY or IY' is the cur-rently active register. IY is selected when this bit is cleared and IY' is selected when this
bit is set. Reset clears this bit and selects IY.
IXBANK (IX Bank Select). This 2-bit field selects the register set to be used for the IX andIX' registers. This field can be set independently of the register set selection for the otherZ380 CPU registers. Reset selects Bank 0 for IX and IX'.

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IXP (IXPrime Register Select). This bit controls and reports whether IX or IX' is the cur-rently active register. IX is selected when this bit is cleared and IX' is selected when this
bit is set. Reset clears this bit and selects IX.
MAINBANK (Main Bank Select). This 2-bit field selects the register set to be used for theA, F, BC, DE, HL, A', F', BC', DE' and HL' registers. This field can be set independentlyof the register set selection for the other Z380 CPU registers. Reset selects Bank 0 forthese registers.
ALT (BC/DE/HL or BC'/DE'/HL' Register Select). This bit controls and reports whether

BC/DE/HL or BC'/DE'/HL' is the currently active bank of registers. BC/DE/HL areselected when this bit is cleared and BC'/DE'/HL' are selected when this bit is set. Resetclears this bit, selecting BC/DE/HL.
XM (Extended Mode). This bit controls the Extended/ Native mode selection for the Z380

CPU. This bit is set by the SETC XM instruction, and once set, it can be cleared only by areset on the /RESET pin. When this bit is set, the Z380 CPU is in Extended mode. Resetclears this bit and the Z380 CPU is in Native mode.
LW (Long Word Mode). This bit controls the Long Word/ Word mode selection for the

Z380 CPU. This bit is set by the SETC LW instruction and cleared by the RESC LW
instruction. When this bit is set, the Z380 CPU is in Long Word mode; when this bit iscleared, the Z380 CPU is in Word mode. Reset clears this bit. Note that individual instructions may be executed in either Word or Long Word load and exchange mode, using the
DDIR W and DDIR LW decoder directives.
IEF1 (Interrupt Enable Flag). This bit is the master Interrupt Enable for the Z380 CPU.
This bit is set by the EI instruction and cleared by the DI instruction. When this bit is set,interrupts are enabled; when this bit is cleared, interrupts are disabled. Reset clears this bit.
IM (Interrupt Mode). This 2-bit field controls the interrupt mode for the /INT0 interrupt

request. These bits are controlled by the IM instructions (00 = IM 0, 01 = IM 1, 10 = IM 2,
11 = IM 3). Reset clears both of these bits, selecting Interrupt Mode 0.
LCK (Lock). This bit controls the Lock/Unlock status of the Z380 CPU. This bit is set by

the SETC LCK instruction and cleared by the RESC LCK instruction. When this bit is set,no bus requests are accepted, providing exclusive access to the bus by the Z380 CPU.
When this bit is cleared the Z380 CPU will grant bus requests in the normal fashion. Resetclears this bit.
AFP (AF Prime Register Select). This bit controls and reports whether AF or AF' is thecurrently active pair of registers. AF is selected when this bit is cleared and AF' is selected
when this bit is set. Reset clears this bit and selects AF.

Memory Address SpaceThe memory address space can be viewed as a string of 4 Gbyte numbered consecutively
in ascending order. The 8-bit byte is the basic addressable element in the Z380 MPU memory address space. However, there are other addressable data elements; bits, 2-byte words,
bytestrings, and 4-byte words.

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The size of the data element being addressed depends on the instruction being executed aswell as the Word/Long Word mode. A bit can be addressed by specifying a byte, and a bitwithin that byte. Bits are numbered from right to left, with the least significant bit being bit
0 (Figure 35).
The address of a multiple-byte entity is the same as the address of the byte with the lowest
memory address in the entity. Multiple-byte entities can be stored beginning with either
even or odd memory addresses. A word (either 2-byte or 4-byte entity) is aligned if its
address is even; otherwise, it is unaligned. Multiple bus transactions, which may berequired to access multiple-byte entities, can be minimized if alignment is maintained.
The formats of multiple-byte data types are also shown in Figure 35. Note that when aword is stored in memory, the least significant byte precedes the more significant byte of
the word, as in the Z80 CPU architecture. Also, the lower-addressed byte is present on theupper byte of the external data bus.
Bits within a byte:
7

6

5

4

3

2

1

0

16-bit word at address n:
Least Significant Byte

Address n

Most Significant Byte

Address n+1

32-bit word at address n:
D7-0 (Least Significant Byte)

Address n

D15-8

Address n+1

D23-16

Address n+2

D31-24 (Most Significant Byte)

Address n+3

Memory addresses:
Even address (A0=0)

Odd address (A0=1)

Least Significant Byte

Most Significant Byte

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Figure 35. Bit/Byte Ordering Conventions

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CPU ARCHITECTURE (Continued)
External I/O Address Space
External I/O addresses are generated by I/O instructions, except those reserved for on-chip
I/O address space accesses, and can take a variety of forms (Table 2). An I/O read or write
is always one transaction, regardless of the bus size and the type of I/O instruction.
On-chip I/O Address Space
The Z380 MPU's on-chip peripheral functions and a portion of its interrupt functions arecontrolled by several on-chip registers, which occupy an On-chip I/O Address Space. This
on-chip I/O address space can be accessed only with the following reserved on-chip I/O
instructions.

IN0

R, (n)

OTIM

IN0

(n)

OTIMR

OUT0

(n), R

OTDM

TSTIO

n

OTDMR

When one of these I/O instructions is executed, the Z380 MPU outputs the register address
being accessed in a pseudo transaction of two BUSCLK cycles duration, with the addresssignals A31-A8 all at zeros. In the pseudo transaction, all bus control signals are at theirinactive states.
Table 2. External I/O Addressing Options
I/O Instruction

A31-A24

Address Bus
A23-A16

A15-A8A7-A0

IN A, (n)IN dst,(C)IN0 dst,(n)INA(W) dst,(mn)DDIR IB INA(W) dst,(lmn)
DDIR IW INA(W) dst,(klmn)
Block Input

00000000
BC31-BC24
00000000
00000000
00000000k
BC31-BC24

00000000
BC23-BC16
00000000
00000000llBC23-BC16

Contents of A reg
BC15-BC800000000m
m
m
BC15-BC8n
BC7-BC0nnnnBC7-BC0

OUT (n),AOUT (C),dst
OUT0 (n),dst
OUTA(W) (mn),dst
DDIR IB OUTA(W) (lmn),dst
DDIR IW OUTA(W) (klmn),dst
Block output

00000000
BC31-BC24
00000000
00000000
00000000k
BC31-BC24

00000000
BC23-BC16
00000000
00000000llBC23-BC16

Contents of A reg
BC15-BC800000000m
m
m
BC15-BC8n
BC7-BC0nnnnBC7-BC0

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DATA TYPESThe Z380 CPU can operate on bits, Binary-Coded Decimal (BCD) digits (4 bits), bytes (8bits), words (16 bits or 32 bits), byte strings, and word strings. Bits in registers can be set,cleared, and tested. BCD digits, packed two to a byte, can be manipulated with the Decimal Adjust Accumulator instruction (in conjunction with binary addition and subtraction)and the Rotate Digit instructions. Bytes are operated on by 8-bit load, arithmetic, logical,
and shift and rotate instructions. Words are operated on in a similar manner by the wordload, arithmetic, logical, and shift and rotate instructions. Block move and search operations can manipulate byte strings and word strings up to 64 Kbytes or words long. Block I/
O instructions have identical capabilities.
CPU Registers
The Z380 CPU contains abundant register resources (Figure 33). At any given time, theprogram has immediate access to both the primary and alternate registers in the selected
register set. Changing register sets is a simple matter of a LDCTL instruction.
Primary and Working Registers
The working register set is divided into the two register files; the primary file and the alternate (designated by ‘) file. Each file contains an 8-bit Accumulator (A), a Flag register (F),and six general-purpose registers (B, C, D, E, H, and L). Only one file can be active at any
given time, although data in the inactive file can still be accessed. Upon reset, the primary
register file in register set 0 is active. Exchange instructions allow the programmer toexchange the active file with the inactive file.
The accumulator is the destination register for 8-bit arithmetic and logical operations. The
six general-purpose registers can be paired (BC, DE, and HL), and are extended to 32 bitsby the z extension to the register, to form three 32-bit general-purpose registers. The HLregister serves as the 16-bit or 32-bit accumulator for word operations.
CPU Flag Register
The Flag register contains six flags that are set or reset by various CPU operations. This
register is illustrated in Figure 36 and the various flags are described below.

S

Z

X

H

X

P/V N

C

7

6

5

4

3

2

0

1

Figure 36. CPU Flag Register

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Carry (C). This flag is set when an add instruction generates a carry or a subtract instruction generates a borrow. Certain logical, rotate and shift instructions affect the Carry flag.
Add/Subtract (N). This flag is used by the Decimal Adjust Accumulator instruction to
distinguish between add and subtract operations. The flag is set for subtract operations andcleared for add operations.
Parity/Overflow (P/V). During arithmetic operations this flag is set to indicate a two’s

complement overflow. During logical and rotate operations, this flag is set to indicate evenparity of the result or cleared to indicate odd parity.
Half Carry (H). This flag is set if an 8-bit arithmetic operation generates a carry or borrow

between bits 3 and 4, or if a 16-bit operation generates a carry or borrow between bits 11
and 12, or if a 32-bit operation generates a carry or borrow between bits 27 and 28. Thisbit is used to correct the result of a packed BCD addition or subtract operation.
Zero (Z). This flag is set if the result of an arithmetic or logical operation is a zero.
Sign (S). This flag stores the state of the most significant bit of the accumulator.

Index Registers
The four index registers, IX, IX’, IY and IY’, each hold a 32-bit base address that is usedin the Indexed addressing mode. The Index registers can also function as general-purpose
registers with the upper and lower byte of the lower 16 bits being accessed individually.
These byte registers are called IXU, IXU’, IXL and IXL’ for the IX and IX’ registers, andIYU, IYU’, IYL and IYL’ for the IY and IY’ registers.
Interrupt Register
The Interrupt register (I) is used in interrupt modes 2 and 3 for /INT0 to generate a 32-bit
indirect address to an interrupt service routine. The I register supplies the upper twentyfour or sixteen bits of the indirect address and the interrupting peripheral supplies thelower eight or sixteen bits. In the Assigned Vectors mode for /INT1-3 the upper sixteen
bits of the vector are supplied by the I register; bits 15-9 are the assigned vector base andbits 8-0 are the assigned vector unique to each of /INT1-3.
Program Counter
The Program Counter (PC) is used to sequence through instructions in the currently executing program and to generate relative addresses. The PC contains the 32-bit address ofthe current instruction being fetched from memory. In the Native mode, the PC is effectively only 16 bits long, as carries from bit 15 to bit 16 are inhibited in this mode. In
Extended mode, the PC is allowed to increment across all 32 bits.
R Register
The R register can be used as a general-purpose 8-bit read/write register. The R register is
not associated with the refresh controller and its contents are changed only by the user.

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Z380 Microprocessor
Product Specification

Stack PointerThe Stack Pointer (SP) is used for saving information when an interrupt or trap occurs andfor supporting subroutine calls and returns. Stack Pointer relative addressing allows
parameter passing using the SP.
Select Register
The Select Register (SR) controls the register set selection and the operating modes of the
Z380 CPU. The reserved bits in the SR are for future expansion; they will always read as
zeros and should be written with zeros for future compatibility. The SR is shown in
Figure 34.

Addressing Modes
Addressing modes are used by the Z380 CPU to calculate the effective address of an operand needed for execution of an instruction. Seven addressing modes are supported by theZ380 CPU. Of these seven, one is an addition to the Z80 CPU addressing modes (Stack
Pointer Relative) and the remaining six modes are either existing or extensions to the Z80
CPU addressing modes.
Register. The operand is one of the 8-bit registers (A, B, C, D, E, H, L, IXU, IXL, IYU,
IYL, A', B', C', D', E', H' or L'); or is one of the 16-bit or 32-bit registers (BC, DE, HL, IX,
IY, BC', DE', HL', IX', IY' or SP) or one of the special registers (I or R).
Immediate. The operand is in the instruction itself and has no effective address. The

DDIR IB and DDIR IW decoder directives allow specification of 24-bit and 32-bit immediate operands, respectively.
Indirect Register. The contents of a register specify the effective address of an operand.
The HL register is the primary register used for memory accesses, but BC and DE can also
be used. (For the JP instruction, IX and IY can also be used for indirection.) The BC register is used for I/O space accesses.
Direct Address. The effective address of the operand is the location whose address is

contained in the instruction. Depending on the instruction, the operand is either in the I/Oor memory address space. Sixteen bits of direct address is the norm, but the DDIR IB andDDIR IW decoder directives allow 24-bit and 32-bit direct addresses, respectively.
Indexed. The effective address of the operand is the location computed by adding the
two's-complement signed displacement contained in the instruction to the contents of the
IX or IY register. Eight bits of index is the norm, but the DDIR IB and DDIR IW decoder
directives allow 16-bit and 24-bit indexes, respectively.
Program Counter Relative. An 8-, 16-or 24-bit displacement contained in the instruction is added to the Program Counter to generate the effective address. This mode is available only for Jump and Call instructions.

PS010002-0708

Page 53 of 125

Z380 Microprocessor
Product Specification

Stack Pointer Relative. The effective address of the operand is the location computed byadding the two's-complement signed displacement contained in the instruction to the contents of the Stack Pointer. Eight bits of index is the norm, but the DDIR IB and DDIR IW
decoder directives allow 16-and 24-bit indexes, respectively.

PS010002-0708

Page 54 of 125

Z380 Microprocessor
Product Specification

INSTRUCTION SETThe Z380 CPU’s instruction set is a superset of the Z80 CPU’s; the Z380 CPU is opcode
compatible with the Z80 CPU. Thus a Z80 program can be executed on a Z380 MPU without modification. The instruction set is divided into seventeen groups by function:
The instructions are divided into the following categories.

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

8-bit load group16/32 bit load group
Push/Pop group
Exchanges, block transfers, and searches
8-bit arithmetic and logic operations
General purpose arithmetic and CPU control
Decoder Directive Instructions
16/32 bit arithmetic operations
Multiply/Divide Instruction group
8-bit Rotates and shifts
16-bit Rotates and shifts
8-bit bit set, reset, and test operations
Jumps
Calls, returns, and restarts
8-bit input and output operations for External I/O address space
8-bit input and output operations for Internal I/O address space
16-bit input and output operations

Instruction Set
The following is a summary of the Z380 instruction set which shows the assembly language mnemonic, the operation, the flag status, and gives comments on each instructions.
Note:

Mnemonic and object code assignment for newly added instructions (instructions in Italicface) are preliminary and subject to change without notice.
The Z380 Technical Manual will contain significantly more details for programming use.
A list of instructions, as well as encoding is included in Appendix A of this document.

PS010002-0708

Page 55 of 125

Z380 Microprocessor
Product Specification

Instruction Set Notation Symbols.
The following symbols are used to describe the instruction set.
n

An 8-bit constantnn

A 16-bit constantdAn 8-bit offset. (2’s complement)r

Any one of the CPU register A, B, C, D, E, H, Ls

Any 8-bit location for all the addressing modes allowed for the particular
instruction.

dd,qq,ss,tt,uu

Any 16-bit location for all the addressing modes allowed for theparticular instruction.

xxh

MS Byte of the specified 16-bit locationxxl

LS Byte of the specified 16-bit locationSR

Select Register

XY

Index register (IX or IY)

XYz

Index Register Extend (IXz or IYz)

XYU

MS Byte of index register (IXU or IYU)XYLLS Byte of index register (IXL or IYL)SP

Current Stack Pointer(C)

I/O Port pointed by C registercc

Condition Code[]

Optional field()

Indirect Address Pointer or Direct Address

INSTRUCTION SET (Continued)
Assignment of a value is indicated by the symbol
For example,
dst

dst + src

indicates that the source data is added to the destination data and the result is stored in thedestination location. The notation “dst (b)” is used to refer bit “b” of a given location,“dst(m-n) is used to refer bit location m to n of the destination. For example,
HL(7) specifies bit 7 of the destination, andHL(23-16) specifies bit location 23 to 16 of the HL register.

PS010002-0708

Page 56 of 125

Z380 Microprocessor
Product Specification

Flags. The F register contains the following flags followed by symbols.
S

Sign flag

Z

Zero flag

H

Half carry flag

P/V

Parity/Overflow flag

N

Add/Subtract flag

C

Carry Flag
The flag is affected according to the result of theoperation.

•

The flag is unchanged by the operation.

0

The flag is reset to 0 by operation.

1

The flag is set to 1 by operation.

V

P/V flag affected according to the overflow result of theoperation.

P

P/V flag affected according to the parity result of theoperation.

Condition Codes. The following symbols describe the condition codes.
Z

Zero*

NZ

Not Zero*C

Carry*

NC

No carry*

S

Sign

NS

No SignNV

No overflow

V

OverflowPE

Parity evenPO

Parity odd

P

Positive

M

Minus*Abbreviated set

PS010002-0708

Page 57 of 125

Z380 Microprocessor
Product Specification

Field Encoding
The convention for opcode binary format is shown in the following Tables. For example,
to get the opcode format on the instruction LD (IX+12h), C; first find out the entry for LD(XY+d),r. That entry has an opcode format of:
11 y11 101
01 110r

d

At the bottom of each Table (between Table and Notes), the binary format is the following:r,r’ Reg

s

Regs

y

XY

000 B

000

B

0

IX

001 C

001

C

1

1Y

010 D

010

D

011 E

011

E

100 H

100

IXU (x = 0),IYU(x = 1)

101 L

101

IXL (x = 0),IYL(x = 1)

111 A

111

A

To form the opcode first look for the y field value for the IX register, which is 0. Then findr field value for the C register, which is 001. Replace the y and r fields with the value fromthe table; replace d value with the real number. The results are:

PS010002-0708

76 543 210

Hex

11 011 101

DD

01 110 001

71

00 010 010

12Page 58 of 125

Z380 Microprocessor
Product Specification

8-BIT LOAD GROUP

Mnemonic

Symbolic
Operation

Flags
P/
S Z x H x V N C

Opcode76 543 210

LD r,r’
LD r,nr ← r’r←n• • x • x • • •• • x • x • • •LD XYU,nXYU ← n• • x • x • • •

01
r
r’
00
r
110
←⎯ n ⎯→
11 y11 101
00 100 110←⎯ n ⎯→
11 y11 101
00 101 110←⎯ n ⎯→
01r
110
11 y11 101
01
r
110←⎯ d ⎯→
01 110r
11 y11 101
01 110r←⎯ d ⎯→
00 110 110←⎯ n ⎯→
11 y11 101
00 110 110←⎯ d ⎯→←⎯ n ⎯→
00 001 010
00 011 010
00 111 010←⎯ n ⎯→←⎯ n ⎯→
00 000 010
00 010 010
00 110 010←⎯ n ⎯→←⎯ n ⎯→LD XYL,nXYL ← n• • x • x • • •LD r,(HL)
LD r,(XY+d)r ← (HL)r ← (XY+d)• • x • x • • •• • x • x • • •LD (HL),rLD (XY+d),r(HL) ← r(XY+d) ← r• • x • x • • •• • x • x • • •LD (HL),n(HL) ← n• • x • x • • •LD (XY+d),n(XY+d) ← n• • x • x • • •LD A,(BC)LD A,(DE)LD A,(nn)A ← (BC)A ← (DE)A ← (nn)• • x • x • • •• • x • x • • •• • x • x • • •LD (BC),ALD (DE),ALD (nn),A(BC) ← A(DE) ← A(nn) ← A• • x • x • • •• • x • x • • •• • x • x • • •PS010002-0708

HEX# of Execute
Bytes Time
Notes
1
2

2
2

3

2

3

2

1
3

2+r
4+r

I

1
3

3+w
5+w

I

2

3+w

4

5+w

I

0A
1A
3A

1
1
3

2+r
2+r
3+r

I

02
12
32

1
1
3

3+w
3+w
4+w

I

26

2E

36

36

Page 59 of 125

Z380 Microprocessor
Product Specification

8-BIT LOAD GROUP (Continued)

Mnemonic

Symbolic
Operation

Flags
P/
S Z x H x V N C

Opcode76 543 210

LD XYU,sXYU ← s• • x • x • • •LD XYL,sXYL ← s• • x • x • • •LD s,XYU

s ← XYU• • x • x • • •LD s,XYLs ← XYL• • x • x • • •LD A,IA←I↕ ↕ x 0 x IEF 0 •LD A,RA←R↕ ↕ x 0 x IEF 0 •LD I,AI←A• • x • x • • •LD R,AR←A• • x • x • • •

11
01
11
01
11
01
11
01
11
01
11
01
11
01
11
01

r,r
000
001
010
011
100
101
111

Reg
B
C
D
E
H
L
A

s
000
001
010
011
100
101
111

y11
100
y11
101
y11
s
y11
s
101
010
101
011
101
000
101
001

HEX

101
s
101
s
101
100
101
101
101
111
101
111
101
111
101
111

ED
57
ED
5F
ED
47
ED
4F

# of Execute
Bytes Time Notes
2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

Regs
y
XY
B
0
IX
C
1
IY
D
E
IXU (x = 0),IYU(x = 1)
IXL (x = 0),IYL(x = 1)
A

Notes:
Instructions in Italic face are Z380 new instructions, instructions with underline are Z180 original instructions.
I: This instruction may be used with DDIR Immediate instructions.

PS010002-0708

Page 60 of 125

16/32 BIT LOAD GROUP

Mnemonic

Symbolic
Operation

Flags
P/
S Z x H x V N C

Opcode76 543 210

LD dd,nndd ← nn• • x • x • • •LD XY,nn

XY ← nn• • x • x • • •00 dd0 001← n →← n →11 y11 101
00 100 001← n →← n →00 101 010← n →← n →11 101 101
01 dd1 011← n →← n →11 y11 101
00 101 010← n →← n →00 100 010← n →← n →11 101 101
01 dd0 011← n →← n →11 y11 101
00 100 010← n →← n →11 101 101
00 pp0 110← n →← n →11 011 101
00 pp1 1uu
11 111 101
00 pp1 1uu
11 111 001
11 y11 101
11 111 001
11 UU1 101
00 pp0 010
11 y11 101
00 pp0 111
11 011 101
00 100 111

LD HL,(nn)H ← (nn+1)
L ← (nn)• • x • x • • •LD dd,(nn)ddh ← (nn+1)
ddl ← (nn)• • x • x • • •LD XY,(nn)XYU ← (nn+1)
XYL ← (nn)• • x • x • • •LD (nn),HL(nn+1) ← H(nn) ← L• • x • x • • •LD (nn),dd(nn+1) ← ddh(nn) ← ddl• • x • x • • •LD (nn),XY(nn+1) ← XYU(nn) ← XYL• • x • x • • •LD W(pp),nn(pp+1) ← nh(pp) ← nl• • x • x • • •LD pp,(uu)• • x • x • • •LD SP,HLLD SP,XY

pph ← (uu+1)
ppl ← (uu)(pp+1) ← uuh(pp) ← uul
SP ← HLSP ← XY

LD pp,UU

pp ← UU• • x • x • • •LD XY,pp

XY ← pp• • x • x • • •LD IX,IY

IX ← IY• • x • x • • •LD (pp),uu• • x • x • • •• • x • x • • •• • x • x • • •HEX# of Execute
Bytes Time Notes
3

2

L1,I

4

2

L1,I

2A

3

3+r

L1,I

ED

4

3+r

L1,I

4

3+r

L1,I

22

3

4+w

L1,I

ED

4

4+w

L1,I

4

4+w

L1,I

ED

4

3+w

L1,I

DD

2

2+r

L1

FD

2

3+w

L1

F9

1
2

2
2

L1
L1

2

2

L1

2

2

L1

2

2

L1

21

2A

22

F9

DD
27

Page 61 of 125

MICROPROCESSOR

16/32 BIT LOAD GROUP (Continued)

Mnemonic

Symbolic
Operation

Flags
S Z x

P/
H x V N C

Opcode76 543 210

LD IY,IX

IY ← IX•• x• x • • •LD pp,XY

pp ← XY•• x• x • • •LD (pp),XY(pp+1) ← XYU(pp) ← XYL
XYU ← (pp+1)
XYL ← (pp)pph ← (XY+d)hppl ← (XY+d)l•• x• x • • ••• x

• x • • ••• x

• x • • •LD IX,(IY+d)

IXU ← (IY+d)h
IXL ← (IY+d)l•• x• x • • •LD IY,(IX+d)IYU ← (IX+d)h
IYL ← (IX+d)l•• x• x • • •LD pp,(SP+d)

pph ← (SP+d)hppl ← (SP+d)l•• x• x • • •LD XY,(SP+d)

XYU ← (SP+d)h
XYL ← (SP+d)l•• x• x • • •(XY+d)h ← pph(XY+d)l ← ppl•

LD (IX+d),IY(IX+d)h ← IYU(IX+d)l ← IYL•• x• x • • •LD (IY+d),IX(IY+d)h ← IXU(IY+d)l ← IXL•• x• x • • •11 111 101
00 100 111
11 y11 101
00 pp1 011
11 y11 101
00 pp0 001
11 y11 101
00 pp0 011
11 y11 101
11 001 011← d →00 pp0 011
11 111 101
11 001 011← d →00 100 011
11 011 101
11 001 011← d →00 100 011
11 011 101
11 001 011← d →00 pp0 001
11 y11 101
11 001 011← d →00 100 001
11 y11 101
11 001 011← d →00 pp1 011
11 011 101
11 001 011← d →00 101 011
11 111 101
11 001 011← d →00 101 011

LD XY,(pp)LD pp,(XY+d)LD (XY+d),pp• x• x • • •

HEX
FD
27

# of Execute
Bytes Time Notes
2

2

L1

2

2

L1

2

3+w

L1

2

2+r

L1

4

4+r

L1,I

4

4+r

L1,I

23
DD
CB

4

4+r

L1,I

23
DD
CB

4

4+r

L1,I

4

4+r

L1, I

4

5+w

L1, I

4

5+w

L1, I

4

5+w

L1, I

CB

FD
CB

CB
21
CB

DD
CB
2B
FD
CB
2B

Page 62 of 125

SymbolicOperation

Flags
S Z x

P/
H x V N C

Opcode76 543 210

LD (SP+d),pp(SP+d)h ← pph(SP+d)l ← ppl•• x• x • • •LD (SP+d),XY(SP+d)h ← XYU(SP+d)l ← XYL•• x• x • • •LD [W] I,HL

I ← HL•• x• x • • •LD [W] HL,I

HL ← I•• x• x • • •11 011 101
11 001 011← d →00 pp1 001
11 y11 101
11 001 011← d →00 101 001
11 011 101
01 000 111
11 011 101
01 010 111

Mnemonic

dd
00
01
10
11

Pair
BC
DE
HL
SP

qq
00
01
10
11

Pair
BC
DE
HL
AF

pp,uu
00
01
11

Pair
BC
DE
HL

y
0
1

HEX
DD
CB

# of Execute
Bytes Time Notes
4

5+w

L1, I

4

5+w

L1, I

2

2

L1

2

2

L1

CB
29
DD
47
DD
57

XY
IX
IY

Notes:
Instructions in Italic face are Z380 new instructions, instructions with underline are Z180 original instructions.
I:
This instruction may be used with DDIR Immediate instructions.
L1: In Long Word mode, this instruction loads in 32 bits; dst(31-0) ← src(31-0)

Page 63 of 125

PUSH/POP INSTRUCTIONS

Mnemonic
PUSH qq

PUSH XY

PUSH nn

PUSH SR

POP qqPOP XYPOP SR

qq
00
01
10
11

Pair
BC
DE
HL
AF

Symbolic
Operation

Flags
P/
S Z x H x V N C

Opcode76 543 210(SP-2) ← qql(SP-1) ← qqh
SP ← SP-2(SP-2) ← XYL(SP-1) ← XYU
SP ← SP-2(SP-2) ← nnl(SP-1) ← nnh
SP ← SP-2• • x • x • • •11 qq0 101• • x • x • • •11 y11
11 100• • x • x • • •(SP-2) ← SR(7-0)•(SP-1) ← SR(15-8)
SP ← SP-2
qqh ← (SP+1)•
qql ← (SP)SP ← SP+2
XYU ← (SP+1)•
XYL ← (SP)SP ← SP+2
SR(6-0) ← (SP)•SR(15-8) ← (SP+1)
SR(23-16) ← (SP+1)
SR(31-24) ← (SP+1)
SP ← SP+2y01• x • x • • •

101
101

11 111 101
11 110 101← n →← n →11 101 101
11 000 101# of Execute
HEX Bytes Time Notes
1

3+w N,L2,L4

2

3+w

N, L2

FD
F5

4

3+w

N, L4,I

ED
C5

2

3+w

N, L2

1

2+r N, L3, L5

2

1+r

N, L3

2

3+r

N, L6

E5

• x • x • • •11 qq0 001• x • x • • •11 y11
11 100

101
001

E1

11 101
11 000

101
001

ED
C1

• x • x • • •

XY
IX
IY

Notes:
Instructions in Italic face are Z380 new instructions, instructions with underline are Z180 original instructions.
I:
This instruction may be used with DDIR Immediate instructions.
L2: In Long Word mode, this instruction PUSHes the register’s extended portion (register with “z” suffix) before pushing the contents of the registerto the stack.
L3: In Long Word mode, this instruction POPs the register’s extended portion (register with “z” suffix) after popping the contents of the register to thestack.
L4: In Long Word mode, PUSH AF and PUSH nn instructions push 0000h onto stack in the place of the extended register portion.
L5: In Long Word mode, POP AF instruction increments SP by two after POPing 1 word of data from stack.
L6: In Long Word mode, this instruction POPs one more word from stack and loads into SR(31-16), instead of duplicating (SP+1) location into SR(3116).
N: In Native mode, this instruction uses addresses modulo 65536.
(10): In case of AF register pair, execute time is one clock less.

Page 64 of 125

EXCHANGE, BLOCK TRANSFER, BLOCK SEARCH GROUPS

Mnemonic

Symbolic
Operation

Flags
P/
S Z x H x V N C

Opcode76 543 210# of Execute
HEX Bytes Time Notes

EX AF, AF’
EX DE,HL
EX BC,DE

SR(0) ← NOT SR(0)DE(15-0) ↔ HL(15-0)
BC(15-0) ↔ DE(15-0)↕ ↕ x ↕ x ↕ ↕ ↕
• • x • x • • •• • x • x • • •EX BC,HL

BC(15-0) ↔ HL(15-0)• • x • x • • •EXX
EX (SP),HL• • x • x • • •• • x • x • • •

001
101
101
000
101
001
011
100

08
EB
ED
05
ED
0D
D9
E3

EX A,rSR(8) ← NOT SR(8)H ↔ (SP+1)
L ↔ (SP)XYU ↔ (SP+1)
XYL ↔ (SP)
A↔r

00
11
11
00
11
00
11
11

EX A,(HL)A ↔ (HL)• • x • x • • •EX r,r’r ↔ r’• • x • x • • •EX pp,pp’pp(15-0) ↔ pp’(15-0)• • x • x • • •EX XY,XY’

XY(15-0) ↔ XY’(15-0)• • x • x • • •EX pp,XY

pp(15-0) ↔ XY(15-0)• • x • x • • •EX IX,IY

IX(15-0) ↔ IY(15-0)• • x • x • • •EXALL• • x • x • • •y11 101
100 011101 101r
111
101 101
110 111001 011110
r
101 101
001 011110 0pp
101 101
001 011110 10y101 101
ppy 011101 101
101 011101 101
011 001

EXXX

SR(24) ← NOT SR(24)SR(16) ← NOT SR(16)SR(8) ← NOT SR(8)SR(16) ← NOT SR(16)

11
11
11
00
11
00
11
00
11
11
00
11
11
00
11
00
11
00
11
11

EXXY

SR(24) ← NOT SR(24)• • x • x • • •SWAP pppp(31-16) ↔ pp(15-0)• • x • x • • •XY(31-16) ↔ XY(15-0)• • x • x • • •• • x 0 x V 0 •
(1)

011
011
111
011
101
pp1
y11
111
111
100

101
001
101
001
101
110
101
110
101
000

DD
D9
FD
D9
ED

SWAP XY

11
11
11
11
11
00
11
00
11
10

• • x 0 x 0 0 •(2)

11 101
10 110101000• • x 0 x V 0 •(1)

11 10110 101101000

EX (SP),XY

LDI

LDIR

LDD

(DE) ← (HL)DE ← DE+1
HL ← HL+1
BC(15-0) ← BC(15-0)-1(DE) ← (HL)DE ← DE+1
HL ← HL+1
BC(15-0) ← BC(15-0)-1
Repeat until BC = 0(DE) ← (HL)DE ← DE-1
HL ← HL-1
BC(15-0) ← BC(15-0)-1• • x • x • • •• • x • x • • •• • x • x • • •

000
011
101
101
101
101
001
011

1
1
2

3
3
3

L7
L7

2

3

L7

1
1

3
3+r+w

N ,L7

2

3+r+w

N ,L7

2

3

2

3+r+w

2

3

ED
CB

3

3

L7

ED
CB

3

3

L7

ED

2

3

L7

ED
2B
ED
D9

2

3

L7

2

3

2

3

2

3

2

2

2

2

2

3+r+w

N

ED
B0

2 (3+r+w)n

N

ED
A8

2

N

E3
ED
ED
37
CB

3E
FD
A0

3+r+w

Page 65 of 125

EXCHANGE, BLOCK TRANSFER, BLOCK SEARCH GROUPS (Continued)
Symbolic
Operation

Flags
P/
S Z x H x V N C

Opcode76 543 210# of Execute
HEX Bytes Time• • x 0 x 0 0 •(2)

11 101 101
10 111 000

ED
B8

2

(3+r+w)nN

CPI(DE) ← (HL)DE ← DE-1
HL ← HL-1
BC(15-0) ← BC(15-0)-1
Repeat until BC = 0
A-(HL)

11 101 101
10 100 001

ED
A1

2

3+r

N

CPIR

HL ← HL+1
BC(15-0) ← BC(15-0)-1
A-(HL)↕ ↕ x ↕ x V 1 •(3)(1)↕ ↕ x ↕ x 0 1 •(3)(2)

11 101 101
10 110 001

ED
B1

2

(3+r)nN↕ x V 1 •(1)

11 101 101
10 101 001

ED
A9

2

3+r

N

↕ x 0 1 •(2)

11 101 101
10 111 001

ED
B9

2

(3+r)nN

0 x V 0 •(1)

11 101 101
11 100 000

ED
E0

2

(3+r+w)n N,L8(4)0 x 0 0 •(2)

11 101 101
11 110 000

ED
F0

2

(3+r+w)n N,L8(4)Mnemonic
LDDR

CPD

CPDR

LDIW

LDIRW

HL ← HL+1
BC(15-0) ← BC(15-0)-1
Repeat until A = (HL) or BC = 0
A-(HL)↕ ↕ x(3)
HL ← HL-1
BC(15-0) ← BC(15-0)-1
A-(HL)↕ ↕ x(3)
HL ← HL-1
BC(15-0) ← BC(15-0)-1
Repeat until A = (HL) or BC = 0(DE) ← (HL)• • x
(DE+1) ← (HL+1)
DE ← DE+2
HL ← HL+2
BC(15-0) ← BC(15-0)-2(DE) ← (HL)• • x
(DE+1) ← (HL+1)
DE ← DE+2
HL ← HL+2
BC(15-0) ← BC(15-0)-2
Repeat until BC = 0

Notes

Page 66 of 125

Mnemonic
LDDW

LDDRW

r
000
001
010
011
100
101
111

Reg
B
C
D
E
H
L
A

Symbolic
Operation

Flags
S Z x

(DE) ← (HL)•
(DE+1) ← (HL+1)
DE ← DE-2
HL ← HL-2
BC(15-0) ← BC(15-0)-2(DE) ← (HL)•
(DE+1) ← (HL+1)
DE ← DE-2
HL ← HL-2
BC(15-0) ← BC(15-0)-2
Repeat until BC = 0
pp
00
00
11

Regs
BC
DE
HL

P/
H x V N C

Opcode76 543 210

HEX

• x

0 x V 0 •(1)

11 101
11 101

101
000

ED
E8

1

3+r+w N,L8(4)• x0 x 0 0 •(2)

11 10111 111

101
000

ED
F8

1

(3+r+w)nN,L8(4)y01# of Execute
Bytes Time Notes

XY
IX
IY

Notes:
Instructions in Italic face are Z380 new instructions, instructions with underline are Z180 original instructions.
L7: In Long Word mode, this instruction exchanges in 32-bits;
src(31-0) ↔ dst(31-0)
L8: In Long Word mode, this instruction transfers in 2 words and BC modified by 4 instead of 2
N: In Native mode, this instruction uses addresses modulo 65536.

(1):
(2):
(3):
(4):

P/V flag is 0 if the result of BC-1 = 0, otherwise P/V = 1.
P/V flag is 0 only at completion of instruction.
Z Flag is 1 if A = (HL), otherwise Z = 0
Source, Destination address, count value must be even numbers.

Page 67 of 125

8-BIT ARITHMETIC AND LOGICAL GROUP

Mnemonic

Symbolic
Operation

Flags
P/
S Z x H x V N C

ADD A,rADD A,n

A←A+r
A←A+n

↕ ↕ x ↕ x V 0 ↕
↕ ↕ x ↕ x V 0 ↕

INCr
INC (HL)
INC (XY+d)r←r+1↕ ↕ x ↕ x V 0 •(HL) ← (HL) + 1↕ ↕ x ↕ x V 0 •(XY + d) ← (XY + d) + 1 ↕ ↕ x ↕ x V 0 •Opcode76 543 210

HEX# of Execute
Bytes Time Notes

10 (000) r
1
2
11 (000) 110
22← n →ADD A,(HL)A ← A + (HL)↕ ↕ x ↕ x V 0 ↕
10 (000) 110
12+r
ADD A,(XY+d)A ← A + (XY + d)
↕ ↕ x ↕ x V 0 ↕
11 y11 101
34+r
I
10 (000) 110← d →ADD A,XYU
A ← A + XYU↕ ↕ x ↕ x V 0 ↕
11 y11 101
2
2
10 (000) 100
ADD A,XYLA ← A + XYL↕ ↕ x ↕ x V 0 ↕
11 y11 101
2
2
10 (000) 101
ADC A,sA ← A + s + CY
↕ ↕ x ↕ x V 0 ↕
(001)
SUB s
A←A-s
↕ ↕ x ↕ x V 1 ↕
(010)
SBC A,sA ← A - s - CY
↕ ↕ x ↕ x V 1 ↕
(011)
AND s
A ← A AND s↕ ↕ x 1 x P 0 0
(100)
OR s
A ← A OR s
↕ ↕ x 0 x P 0 0
(110)
XOR s
A ← A XOR s↕ ↕ x 0 x P 0 0
(101)
CP s
A-s
↕ ↕ x ↕ x V 1 ↕
(111)
s is any of r, n, XYU, XYL, (HL), (IX+d), (IY+d) as shown for ADD instruction. The indicated bits replace the (000) in the
ADD set above.
00 r (100)
1
2/3
(5)
00 110 (100)
1 2+r+w
11 y11 101
3 4+r+w
I
00 110 (100)← d →INC XYUXYU ← XYU + 1↕ ↕ x ↕ x V 0 •11 y11 101
2
2
00 100 (100)
INC XYLXYL ← XYL + 1↕ ↕ x ↕ x V 0 •11 y11 101
2
2
00 101 (100)
DEC m
m←m-1
↕ ↕ x ↕ x V 1 •(101)
m is any of r, XYU, XYL, (HL), (IX+d), (IY+d) as shown for INC instructions. The indicated bits replace (100) with (101) in
operand.

Page 68 of 125

Mnemonic

Symbolic
Operation

Flags
S Z x H x V

TST r

A AND r

TST n

TST (HL)

r
000
001
010
011
100
101
111

Reg
B
C
D
E
H
L
A

P/
N C

Opcode76 543 210↕ ↕ x 1 x

P 0 0

A AND n↕ ↕ x 1 x

P 0 0

A AND (HL)↕ ↕ x 1 x

P 0 0

11 101 101
00 r
100
11 101 101
01 100 100← n →11 101 101
00 110 100

y
0
1

HEX

# of
Bytes

Execute
Time
Notes

ED

2

2

ED
64

3

2

ED
34

2

2+r

XY
IX
IY

Notes:
Instructions in Italic face are Z380 new instructions, instructions with underline are Z180 original instructions.
I: This instruction may be used with DDIR Immediate instructions.
(5): Two cycles to execute for Accumulator, three cycles to execute for any other registers.

Page 69 of 125

GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUP
Symbolic
Operation

Flags
P/
S Z x H x V N C

Opcode76 543 210# of Execute
HEX Bytes Time
Notes@
A ← NOT A
One’s complement
HL ← NOT HL
One’s complement
A ← 0-A
Two’s complement
HL ← 0-HL
Two’s complement
L←A
H ← 00 if D7 = 0
H ← FF if D7 = 1
HLz ← 0000 if H[7] = 0
HLz ← FFFF if H[7] = 1
CY ← NOT CY
Complement carry flag
CY ← 1
No operation
CPU halted
Sleep↕ ↕ x ↕ x P • ↕
• • x 1 x • 1 •00 100 111
00 101 111

27
2F

1
1

3
2

• • x 1 x • 1 •

11
00
11
01
11
01
11
01

011 101
101 111101 101000 100
101 101
010 100
101 101
100 101

DD
2F
ED
44
ED
54
ED
65

2

2

1

2

1

2

2

3

11 101 101
01 110 101
00 111 111

ED
75
3F

DI #
DI n #

SR(5) ← 0
IER(i) ← 0 if n(i) = 1
SR(5) ← 0 if n(0) = 1• • x • x • • •• • x • x • • •EI #EI n #

SR(5) ← 1
IER(i) ← 1 if n(i) = 1
SR(5) ← 1 if n(0) = 1• • x • x • • •• • x • x • • •IM 0

Set INT mode 0• • x • x • • •IM 1

Set INT mode 1• • x • x • • •IM 2

Set INT mode 2• • x • x • • •IM 3

Set INT mode 3• • x • x • • •LDCTL SR,A

SR(31-24) ← A
SR(23-16) ← A
SR(15-8) ← A
SR(31-24) ← n
SR(23-16) ← n
SR(15-8) ← n
HL(15-0) ← SR(15-0)• • x • x • • •00 110 111
00 000 000
01 110 110
11 101 101
01 110 110
11 110 011
11 011 101
11 110 011← n →11 111 011
11 011 101
11 111 011← n →11 101 101
01 000 110
11 101 100
01 010 101
11 101 101
01 011 110
11 101 101
01 001 110
11 011 101
11 001 000

MnemonicDAA
CPL[A]CPLW[HL]
NEG[A]
NEGW[HL]
EXTS [A]

EXTSW [HL]
CCF
SCF
NOP
HALT
SLP

LDCTL SR,nLDCTL HL,SR↕ ↕ x ↕ x V 1 ↕
↕ ↕ x ↕ x V 1 ↕
• • x • x • • •• • x • x • • •• • x ↕ x • 0 ↕
•
•
•
•

•
•
•
•

x
x
x
x

0
•
•
•

x
x
x
x

•
•
•
•

0
•
•
•

1
•
•
•

• • x • x • • •• • x • x • • •11 011 101
11 001 010← n →11 101 101
11 000 000

L9

3
1

2

37
00
76
ED
76
F3
DD
F3

1
1
1
2

2
2
2
2

1
3

2
2

FB
DD
FB

1
3

2
2

ED
46
ED
56
ED
5E
ED
4E
DD
C8

2

4

2

4

2

4

2

4

2

4

DD
CA

3

4

ED
C0

2

2

Page 70 of 125

L1

SymbolicOperation

Mnemonic
LDCTL SR,HL

LDCTL A,v
LDCTL v,A
LDCTL v,n

SETC LCKSETC LW
SETC XMRESC LCKRESC LW
BTEST

MTEST

vv
01
10
11

Flags
P/
S Z x H x V N C

SR(15-8) ← HL(15-8)• • x • x • • •SR(0) ← HL(0)if (LW)
SR(31-16) ← HL(31-16)
else
SR(31-24) ← HL(15-8)
SR(23-16) ← HL(15-8)v←A• • x • x • • •A←vv←nSR(1) ← 1
Set Lock mode
SR(6) ← 1
Set Long word mode
SR(7) ← 1
Set Extend mode
SR(1) ← 0
Reset Lock mode
SR(6) ← 0
Reset Long word mode
Bank Test
S ← SR(16)Z ← SR(24)V ← SR(0)C ← SR(8)Mode test
S ← SR(7)Z ← SR(6)C ← SR(1)• • x • x • • •• • x • x • • •• • x • x • • •• • x • x • • •• • x • x • • •• • x • x • • •• • x • x • • •↕ ↕ x • x ↕ • ↕

↕ ↕ x • x • • ↕

Opcode# of
76 543 210 HEX Bytes
11 101 101
11 001 000

ED
C8ExecuteTime Notes

2

4

2

2

2

4

3

4

11 vv1 101
11 010 000
11 vv1 101
11 011 000
11 vv1 101
11 011 010← n →11 101 101
11 110 111
11 011 101
11 110 111
11 111 101
11 110 111
11 101 101
11 111 111
11 011 101
11 111 111
11 101 01
11 001 111

ED
F7
DD
F7
FD
F7
ED
FF
DD
FF
ED
CF

2

4

2

4

2

4

2

4

2

4

2

2

11 011 101
11 001 111

DD
CF

2

2

D0
D8
DA

Control Regs
XSR
DSR
YSR

Notes:
Instructions in Italic face are Z380 new instructions, instructions with underline are Z180 original instructions.
L1:
L9:
@:
#:

In Long Word mode, this instruction loads in 32 bits; dst(31-0) ← src(31-0)
In Long Word mode, this instruction operates in 32-bits; If A(7) = 0 then HL(31-16) = 0000h else FFFFh
Converts accumulator content into packed BCD following add or subtract with packed BCD operands.
Interrupts are not sampled at the end of EI and DI.

Page 71 of 125

L1

DECODER DIRECTIVE INSTRUCTIONS

Mnemonic

Operation

DDIR W

Operate following inst in word mode.

DDIR IB,W

DDIR IBOperate following inst in word mode.
Fetching additional byte data.
Operate following inst in word mode.
Fetching additional word data.
Fetching additional byte data.

DDIR LW

Operate following inst in Long Word mode.

DDIR IB,LW

Operate following inst in Long Word mode.
Fetching additional byte data.
Operate following inst in word mode.
Fetching additional word data.
Fetching additional word data.

DDIR IW,W

DDIR IW,LW
DDIR IW

Opcode
76
543

210

# of
HEX

11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11

101
000
101
001
101
010
101
011
101
000
101
001
101
010
101
011

DD
C0
DD
C1
DD
C2
DD
C3
FD
C0
FD
C1
FD
C2
FD
C3

011
000
011
000
011
000
011
000
111
000
111
000
111
000
111
000

Bytes

ExecuteTime Notes

+2

0

+3

0

+4

0

+3

0

+2

0

+3

0

+4

0

+4

0

Page 72 of 125

16/32 BIT ARITHMETIC AND LOGICAL GROUP

Mnemonic

Symbolic
Operation

Flags
S Z x

P/
H x V N C

Opcode76 543 210

ADD HL,dd
ADC HL, dd

HL ← HL+ dd
HL ← HL+ dd + CY

•
↕

• x
↕ x

↕ x • 0 ↕
↕ x V 0 ↕

SBC HL,dd

HL ← HL - dd - CY↕

↕ x

↕ x V 1 ↕

ADD XY,qq

XY ← XY + qq•

• x

↕ x • 0 ↕

ADD XY,XY

XY ← XY + XY•

• x

↕ x • 0 ↕

00 dd1 001
11 101 101
01 dd1 010
11 101 101
01 dd0 010
11 y11 101
00 qq1 001
11 y11 101
00 101 001
00 dd0 011
11 y11 101
00 100 011
00 dd1 011
11 y11 101
00 101 011
11 101 101
10 000 010← n →← n →11 101 101
10 010 010← n →← n →11 101 101
10 (000) 1pp

INC[W] dd
INC[W] XY

dd ← dd + 1
XY ← XY + 1

•
•

• x
• x

• x • • •• x • • •DEC[W] dd
DEC[W] XY

dd ← dd - 1
XY ← XY - 1

•
•

• x
• x

• x • • •• x • • •ADD SP,nn

SP ← SP + nn•

• x

↕ x • 0 ↕

SUB SP,nn

SP ← SP - nn•

• x

↕ x • 1 ↕

ADDW [HL,]pp

HL← HL + pp↕

↕ x

↕ x V 0 ↕

HEX

# of Execute
Bytes Time Notes

ED

1
2

2
2

X1

ED

2

2

2

2

2

X1

1
2

2
2

X1
X1

1
2

2
2

X1
X1

4

2

X1, I

ED
92

4

2

X1, I

ED

2

2

X1

29

23

2B
ED
82

Page 73 of 125

16/32 BIT ARITHMETIC AND LOGICAL GROUP (Continued)

Mnemonic

Symbolic
Operation

Flags
P/
S Z x H x V N C

Opcode# of Execute76 543 210 HEX Bytes Time Notes

ADDW [HL,]nn

HL← HL + nn

↕ ↕ x ↕ x V 0 ↕

ADDW [HL,]XY

HL ← HL+XY↕ ↕ x ↕ x V 0 ↕

11 101 101
10 (000) 110← n →← n →11 y11 101
10 (000) 111
11 y11 101
11 (000) 110

ADDW [HL,](XY+d)

HL ← HL+(XY+d)↕ ↕ x ↕ x V 0 ↕

ADCW [HL,]uu
SUBW [HL,]uu
SBCW [HL,]uu
ANDW [HL,]uu
ORW [HL,]uu
XORW [HL,]uu
CPW [HL,]uu

HL ← HL+uu+CY
HL ← HL-uu
HL ← HL - uu - CY
HL ← HL AND uu
HL ← HL OR uu
HL ← HL XOR uu
HL - uu

↕
↕
↕
↕
↕
↕
↕

ADD HL, (nn)HL ← HL+(nn)• • x ↕ x • 0 ↕

SUB HL, (nn)HL ← HL- (nn)• • x ↕ x • 0 ↕

↕
↕
↕
↕
↕
↕
↕

x
x
x
x
x
x
x

↕
↕
↕
1
0
0
↕

x
x
x
x
x
x
x

V
V
V
P
P
P
V

0
1
1
0
0
0
1

↕
↕
↕
0
0
0
↕

ED
86

4

2

I

2

2

I

4

4+r

I

ED
C6

4

2+r

I, X1

ED
D6

4

2+r

I, X1

87
C6

(001)
(010)
(011)
(100)
(110)
(101)
(111)
11 101 101
11 010 110← n →← n →11 101 101
11 010 110← n →← n →uu is any of rr, nn, t, (IX+d), (IY+d) as shown for ADDW instruction. The indicated bits replace the (000) is the ADD set
above.

dd
00
01
10
11

Pair
BC
DE
HL
SP

pp
00
01
11

Pair
BC
DE
HL

qq
00
01
11

Pair
BC
DE
SP

y
0
1

XY
IX
IY

Notes:
Instructions in Italic face are Z380 new instructions, instructions with underline are Z180 original instructions.
I: This instruction may be used with DDIR Immediate instructions.
X1: In Extend mode, this instruction operates in 32-bits;
src(31-0) ← src(31-0) opr dst(31-0)

Page 74 of 125

MULTIPLY/DIVIDE INSTRUCTION GROUP

Mnemonic

Symbolic
Operation

Flags
P/
S Z x H x V N C

Opcode# of Execute76 543 210 HEX Bytes Time Notes

MLT dddd ← ddH * ddL• • x • x • • •MULTW [HL,]pp

HL(31-0)← HL(15-0) * pp(15-0)↕ ↕ x • x 0 • ↕

MULTW [HL,]XY

HL(31-0)← HL(15-0) * XY(15-0)↕ ↕ x • x 0 • ↕

MULTW [HL,]nn

HL(31-0)← HL(15-0) * nn

↕ ↕ x • x 0 • ↕

MULTW (XY+d)

HL(31-0)← HL(15-0) * (XY+d)↕ ↕ x • x 0 • ↕

HL(31-0)← HL(15-0) * uu

↕ ↕ x • x 0 • ↕

11 101 101
01 dd1 100
11 101 101
11 001 011
10 (010) 0pp
11 101 101
11 001 011
10 (010) 10y
11 101 101
11 001 011
10 (010) 111← n →← n →11 y11 101
11 001 011← d →10 (010) 010(011)

MULTUW uu

ED

2

7

ED
CB

3

10

ED
CB

3

10

ED
CB
97

5

10

I

4

12+r

I

CB
92

MULTUW uu instructions, uu is any of pp, nn, XY, (nn), (XY+d) as shown for MULTW instruction with replacing (010) by(010). Execute time is time required for MUTW with one more clock.

Page 75 of 125

MULTIPLY/DIVIDE INSTRUCTION GROUP (Continued)
Symbolic
Operation

Flags
P/
S Z x H x V N C

Opcode76 543 210# of Execute
HEX Bytes Time Notes

DIVUW [HL,]pp

HL(15-0)← HL(31-0)/pp
HL(31-16) ← remainder

0 ↕ x • x V • •

ED
CB

3

20

DIVUW [HL,]XY

HL(15-0)← HL(31-0)/XY
HL(31-16) ← remainder
HL(15-0)← HL(31-0)/nn
HL(31-16) ← remainder

0 ↕ x • x V • •

ED
CB

3

20

ED
CB
BF

5

20

DIVUW [HL,](XY+d) HL(15-0)← HL(31-0)/(XY+d)
HL(31-16) ← remainder

0 ↕ x • x V • •11 101 101
11 001 011
10 111 0pp← d →11 101 101
11 001 011
10 111 10y
11 101 101
11 001 011
10 111 111← n →← n →11 y11 101
11 001 011← d →10 111 010

4

22+r

Mnemonic

DIVUW [HL,]nn

r
000
001
010
011
100
101
111

Reg
B
C
D
E
H
L
A

pp
00
00
11

Regs
BC
DE
HL

0 ↕ x • x V • •

y
0
1

XY
IX
IY

CB
BA

dd
00
01
10
11

Regs
BC
DE
HL
SP

Notes:
Instructions in Italic face are Z380 new instructions, instructions with underline are Z180 original instructions.
I:
This instruction may be used with DDIR Immediate instructions.

Page 76 of 125

II

8-BIT ROTATE AND SHIFT GROUP

Mnemonic
RLCA
RLA
RRCA
RRA
RLC r

Symbolic
Operation

Flags
P/
S Z x H x V N C

Opcode76 543 210# of Execute
HEX Bytes Time Notes

Rotate Left Circular
Accumulator
Rotate Left Accumulator
Rotate Right Circular
Accumulator
Rotate Right Accumulator
Rotate Left Circularregister r
Rotate Left Circular• • x 0 x • 0 ↕

00 000 111

07

1

2

• • x 0 x • 0 ↕
• • x 0 x • 0 ↕

00 010 111
00 001 111

17
0F

1
1

2
2

• • x 0 x • 0 ↕
↕ ↕ x 0 x P 0 ↕

00 011 111
1F
1
2
11 001 011 CB22
00 (000) r
RLC (HL)↕ ↕ x 0 x P 0 ↕
11 001 011 CB
22+r
00 (000) 110
06
RLC (XY+d)
Rotate Left Circular↕ ↕ x 0 x P 0 ↕
11 y11 101
44+r
I
11 001 011 CB← d →00 (000) 110
RL m
Rotate Left↕ ↕ x 0 x P 0 ↕
(010)
RRC m
Rotate Right Circular↕ ↕ x 0 x P 0 ↕
(001)
RR m
Rotate Right↕ ↕ x 0 x P 0 ↕
(011)
SLA m
Shift Left Arithmetic↕ ↕ x 0 x P 0 ↕
(100)
SRA m
Shift Right Arithmetic↕ ↕ x 0 x P 0 ↕
(101)
SRL m
Shift Right Logical0 ↕ x 0 x P 0 ↕
(111)
Above instruction’s format and states are as shown for RLC’s. To form new opcode replace (000) of RLCs with shown
code.
RLD

Rotate Left Digit
between the accumulator
and location (HL)
Rotate Right Digit
between the accumulator
and location (HL)

RRD

r
000
001
010
011
100
101
111

Reg
B
C
D
E
H
L
A

pp
00
00
11

Regs
BC
DE
HL

y
0
1

↕ ↕ x 0 x P 0 •11 101 101
01 101 111

ED
6F

2

3+r

(6)

↕ ↕ x 0 x P 0 •11 101 101
01 100 111

ED
67

2

3+r

(6)

XY
IX
IY

Notes:
Instructions in Italic face are Z380 new instructions, instructions with underline are Z180 original instructions.
I:
This instruction may be used with DDIR Immediate instructions.
(6): The contents of the upper half of the accumulator is unaffected.

Page 77 of 125

16/32 BIT ROTATE AND SHIFT GROUP

Mnemonic

Symbolic
Operation

Flags
P/
S Z x H x V N C

Rotate Left Circular↕ ↕ x 0 x P 0 ↕

Opcode76 543 210# of
HEX Bytes

ExecuteTime Notes

11 101 101 ED
3
2
11 001 011 CB
00 (000) 0pp
RLCW XY
Rotate Left Circular↕ ↕ x 0 x P 0 ↕
11 101 101 ED
3
2
11 001 011 CB
00 (000) 10y
RLCW (HL)
Rotate Left Circular↕ ↕ x 0 x P 0 ↕
11 101 101 ED
32+r
11 001 011 CB
00 (000) 010
RLCW (XY+d) Rotate Left Circular↕ ↕ x 0 x P 0 ↕
11 y11 101
44+r
I
11 001 011 CB← d →00 (000) 010
RLW m
Rotate Left↕ ↕ x 0 x P 0 ↕
(010)
RRCW mRotate Right Circular↕ ↕ x 0 x P 0 ↕
(001)
RRW m
Rotate Right↕ ↕ x 0 x P 0 ↕
(011)
SLAW mShift Left Arithmetic↕ ↕ x 0 x P 0 ↕
(100)
SRAW mShift Right Arithmetic↕ ↕ x 0 x P 0 ↕
(101)
SRLW mShift Right Logical0 ↕ x 0 x P 0 ↕
(111)
Instruction format and states are as shown for RLCW. To form new opcode replace (000) or RLCW with shown code.
RLCW pp

pp
00
00
11

Regs
BC
DE
HL

y
0
1

XY
IX
IY

Notes:
Instructions in Italic face are Z380 new instructions, instructions with underline are Z180 original instructions.
I:
This instruction may be used with DDIR Immediate instructions.

Page 78 of 125

8-BIT BIT SET, RESET, AND TEST GROUP

Mnemonic

Symbolic
Operation

Flags
P/
S Z x H x V N C

BIT b,r

Z ← rb• ↕ x 1 x • 0 •BIT b,(HL)Z ← (HL)b• ↕ x 1 x • 0 •BIT b,(XY+d)Z ← (XY+d)b• ↕ x 1 x • 0 •SET b,rrb ← 1• • x • x • • •SET b,(HL)(HL)b ← 1

• • x • x • • •SET b,(XY+d)(XY+d)b ← 1• • x • x • • •mb ← 0

RES b,m76

Opcode543 21011 001 011
01br
11 001 011
01b110
11 y11 101
11 001 011← d →01b110
11 001 011(11) br
11 001 011(11) b110
11 y11 101
11 001 011← d →(11) b110(10)# of Execute
HEX Bytes Time Notes
CB

2

CB

2
4

CB

2

CB

2
4

CB

To form new opcode replace (11) of SET b,s with (10). s is any of r,(HL), (XY+d).
The notation mb indicates location m, bit b(0~7)
r
000
001
010
011
100
101
111

Reg
B
C
D
E
H
L
A

y
0
1

I

CB

XY
IX
IY

Notes:
Instructions in Italic face are Z380 new instructions, instructions with underline are Z180 original instructions.
I: This instruction may be operate with DDIR Immediate instructions.

Page 79 of 125

I

JUMP GROUP

Mnemonic

Symbolic
Operation

Flags
P/
S Z x H x V N C

Opcode76 543 210

JP nn

PC(15-0) ← nn

• • x • x • • •JP (HL)JP (XY)PC(15-0) ← HL(15-0)
PC(15-0) ← XY(15-0)• • x • x • • •• • x • x • • •JP cc,nn

If condition cc is true
then PC ← nnotherwise continue
PC ← PC + e• • x • x • • •If C = 0 continue
If C = 1, PC ← PC + e
If C = 1 continue
If C = 0, PC ← PC + e
If Z = 0 continue
If Z = 1, PC ← PC + e
If Z = 1 continue
If Z = 0, PC ← PC + e
PC ← PC + ee

• • x • x • • •11 000 011← n →← n →11 101 001
11 y11 101
11 101 001
11 cc 010
← n →← n →00 011 000← e-2 →
00 111 000← e-2 →
00 110 000← e-2 →
00 101 000← e-2 →
00 100 000← e-2 →
11 011 101
00 011 000← (ee-4)L →← (ee-4)H →11 011 101
00 111 000← (ee-4)L →← (ee-4)H →11 011 101
00 110 000← (ee-4)L →← (ee-4)H →11 011 101
00 101 000← (ee-4)L →← (ee-4)H →11 011 101
00 100 000← (ee-4)L →← (ee-4)H →11 111 101
00 011 000←(eee-5)L→←(eee-5)M→←(eee-5)H→11 111 101
00 111 000←(eee-5)L→←(eee-5)M→←(eee-5)H→JR e
JR C,eJR NC,eJR Z,e
JR NZ,eJR ee• • x • x • • •• • x • x • • •• • x • x • • •• • x • x • • •• • x • x • • •JR C,ee

If C = 0 continue
If C = 1, PC ← PC + ee

• • x • x • • •JR NC,eeIf C = 1 continue
If C = 0, PC ← PC + ee

• • x • x • • •JR Z,ee

If Z = 0 continue
If Z = 1, PC ← PC + ee

• • x • x • • •JR NZ,eeIf Z = 1 continue
If Z = 0, PC ← PC + ee

• • x • x • • •JR eeePC ← PC + eee• • x • x • • •JR C,eee

If C = 0 continue
If C = 1, PC ← PC + eee• • x • x • • •HEX# of Execute
Bytes Time
Notes

C3

3

2

X2, I

E9

1
2

2
2

X2
X2

3

2

X2, I

18

2

2

N, (7)38

2

2

N, (7)30

2

2

N, (7)

28

2

2

N, (7)

20

2

2

N, (7)

DD
18

4

2

N, (8)

DD
38

4

2

N, (8)

DD
30

4

2

N, (8)

DD
28

4

2

N, (8)

DD
20

4

2

N, (8)

FD
18

5

2

N, (9)

FD
38

5

2

N, (9)

E9

Page 80 of 125

SymbolicOperation

Flags
P/
S Z x H x V N C

Opcode76 543 210

JR NC,eee

If C = 1 continue
If C = 0, PC ← PC + eee• • x • x • • •

FD
30

5

2

N, (9)

JR Z,eee

If Z = 0 continue
If Z = 1, PC ← PC + eee• • x • x • • •

FD
28

5

2

N, (9)JR NZ,eee

If Z = 1 continue
If Z = 0, PC ← PC + eee• • x • x • • •

FD
20

5

2

N, (9)

DJNZ eB←B-1
If B = 0 continue
If B↔0, PC ← PC + e
B←B-1
If B = 0 continue
If B ≠ 0, PC ← PC + ee

• • x • x • • •11 111 101
00 110 000←(eee-5)L→←(eee-5)M→←(eee-5)H→11 111 101
00 101 000←(eee-5)L→←(eee-5)M→←(eee-5)H→11 111 101
00 100 000←(eee-5)L→←(eee-5)M→←(eee-5)H→00 010 000← e-2 →

10

2

3/4

N, (7)

DD
10

4

3/4

N, (8)B←B-1
If B = 0 continue
If B ≠ 0, PC ← PC + eee• • x • x • • •11 011 101
00 010 000←(ee-4)L→←(ee-4)H→11 111 101
00 010 000←(eee-5)L→←(eee-5)M →←(eee-5)H →

FD
10

5

3/4

N, (9)

Mnemonic

DJNZ ee

DJNZ eee

cc
000
001
010
011
100
101
110
111

• • x • x • • •HEX# of Execute
Bytes Time Notes

Condition
NZ (Non-zero)
Z (Zero)NC (Non-carry)
C (Carry)
PO (Parity Odd), or NV (Non-Overflow)
PE (Parity Even), or V (Overflow)
P (Sign positive), or NS (No sign)
M (Sign negative), or S (Sign)

Notes:
Instructions in Italic face are Z380 new instructions, instructions with underline are Z180 original instructions.
I:
This instruction may be used with DDIR Immediate instructions.
N: In Native mode, this instruction uses addresses modulo 65536.
X2: In Extend mode, this instruction loads bit 31-16 portion of the operand into PC(31-16).
(7): e is a signed two’s complement number in the range [-126, 129], e-2 in the opcode provides an effective address of pc+e as PC is incremented
by 2 prior to the addition of e.
(8): ee is a signed two’s complement number in the range [-32765, 32770], ee-4 in the opcode provides an effective address of pc+e as PC is
incremented by 4 prior to the addition of e.
(9): eee is a signed two’s complement number in the range [-8388604, 8388611], eee-5 in the opcode provides an effective address of pc+e as PC
is incremented by 5 prior to the addition of e.

Page 81 of 125

CALL AND RETURN GROUP
Symbolic
Operation

Flags
P/
S Z x H x V N C

Opcode# of Execute76 543 210 HEX Bytes Time
Notes

(SP-1) ← PCh(SP-2) ← PCl
SP ← SP-2
PC ← nnIf condition cc
is false continue
otherwise same as CALL nn(SP-1) ← PCh(SP-2) ← PCl
SP ← SP-2
PC ← PC + e
If condition cc
is false continue
otherwise same as CALR e(SP-1) ← PCh(SP-2) ← PCl
SP ← SP-2
PC ← PC + ee
If condition cc
is false continue
otherwise same as
CALR ee(SP-1) ← PCh(SP-2) ← PCl
SP ← SP-2
PC ← PC + eee• • x • x • • •11 001 101← n →← n →• • x • x • • •11 cc 100
← n →← n →11 101 101
11 001 101

CALR cc,eee

If condition cc
is false continue
otherwise same as
CALR eee• • x • x • • •RET

PCL ← (SP)PCH ← (SP + 1)
SP ← SP+2
If condition cc
is false continue
otherwise same as RET
Return from Interrupt• • x • x • • •← e-3 →
11 101 101 ED
11 cc 100← e-3 →
11 011 101 DD
11 001 101 CD← (ee-4)L →← (ee-4)H →11 011 101 DD
11 cc 100← (ee-4)L →← (ee-4)H →11 111 101 FD
11 001 101 CD← (eee-5)L →← (eee-5)M →← (eee-5)H →11 111 101 FD
11 cc 100← (eee-5)L →← (eee-5)M →← (eee-5)H →11 001 001 C9• • x • x • • •11• • x • x • • •11 101 101
01 001 101

Mnemonic
CALL nn

CALL cc,nn

CALR eCALR cc,e

CALR ee

CALR cc,ee

CALR eee

RET ccRETI• • x • x • • •• • x • x • • •• • x • x • • •• • x • x • • •• • x • x • • •

CD

ED
CD

cc 000

ED
4D

3

4+w

X3, I

3

2/4+w

X3, I

3

4+w N,X3,(11)32/4+w N,X3,(11)

4

4+w

4

2/4+w N,X3,(8)

5

4+w

5

2/4+w N,X3,(9)

1

2+r

N, X4

1

2/2+r

N, X4

2

2+r

N, X4

N,X3,(8)N,X3,(9)Page 82 of 125

Mnemonic

Symbolic
Operation

Flags
P/
S Z x H x V N C

RETN

Return from NMI• • x • x • • •RST p(SP-1) ← PCh(SP-2) ← PCl
SP ← SP-2
PCh ← 0PCl ← p• • x • x • • •

cc
000
001
010
011
100
101
110
111

Condition
NZ (Non-zero)
Z (Zero)NC (Non-carry)
C (Carry)
PO (Parity Odd), or NV (Non-Overflow)
PE (Parity Even), or V (Overflow)
P (Sign positive), or NS (No sign)
M (Sign negative), or S (Sign)

t
000
001
010
011
100
101
110
111

76
11
01
11

Opcode543 210
101
000
t

101
101
111

HEX
ED
45

# of
Bytes

Execute
Time

Notes

2

2+r

N,X4,(10)1

4+w

N,X3,X5

p
00H
08H
10H
18H
20H
28H
30H
38H

Notes:
Instructions in Italic face are Z380 new instructions, instructions with underline are Z180 original instructions.
I:
N:
X3:
X4:
X5:
(2)
(8):
(9):
(10)
(11):

This instruction may be used with DDIR Immediate instructions.
In Native mode, this instruction uses addresses modulo 65536.
In Extended mode, this instruction pushes PC(31-16) into the stack before pushing PC(15-0) into the stack.
In Extended mode, this instruction pops PC(31-16) from the stack after poping PC(15-0) from the stack.
In Extended mode, this instruction loads 00h into PC(31-16).
In Extended mode, all return instructions pops PCz from the stack after poping PC from the stack.
ee is a signed two’s complement number in the range [-32765, 32770], ee-4 in the opcode provides an effective address of pc+e as PC is
incremented by 4 prior to the addition of e.
eee is a signed two’s complement number in the range [-8388604, 8388611], eee-5 in the opcode provides an effective address of pc+e as
PC is incremented by 5 prior to the addition of e.
RETN loads IFF2 to IFF1.
e is a signed two’s complement number in the range [-127, 128], e-3 in the opcode provides an effective address of pc+e as PC is incremented
by 3 prior to the addition of e.

Page 83 of 125

8-BIT INPUT AND OUTPUT GROUP

Mnemonic

Symbolic
Operation

Flags
P/
S Z x H x V N C

Opcode76 543 210# of Execute
HEX Bytes
Time
Notes

IN A,(n)A ← (n)• • x • x • • •DB

2

IN r,(C)r ← (C)↕ ↕ x 0 x P 0 •ED

2

INA A,(nn)A ← (nn)• • x • x • • •

ED
DB

2

3+i

INI

• ↕ x • x • 1 •
(1)

ED
A2

2

2+i+w

• 1 x • x • 1 •(2)

11 101
10 110

101
010

ED
B2

2

(2+i+w)• ↕ x • x • 1 •(1)

11 10110 101

101
010

ED
AA

2

2+i+w

• 1 x • x • 1 •(2)

11 101
10 111

101
010

ED
BA

2

(2+i+w)nOUT (n),A(HL) ← (C)B←B-1
HL ← HL + 1(HL) ← (C)B ← B-1
HL ← HL + 1
Repeat until B = 0(HL) ← (C)B←B-1
HL ← HL - 1(HL) ← (C)B ← B-1
HL ← HL - 1
Repeat until B = 0(n) ← A

11 011 011← n →11 101 101
01
r000
11 101 101
11 011 011← n →← n →11 101 101
10 100 010• • x • x • • •

D3

2

3+o

OUT (C),r(C) ← r• • x • x • • •

ED

2

3+o

OUT (C),n(C) ← r• • x • x • • •

ED
71

3

3+o

OUTA (nn),A(nn) ← A• • x • x • • •11 010 011← n →11 101 101
01
r001
11 101 101
01 110 001← n →11 101 101
11 010 011← n →← n →

ED
D3

4

2+o

INIR

IND

INDR

3+i

Page 84 of 125

I

I

Mnemonic
OUTI

OTIR

OUTD

OTDR

r
000
001
010
011
100
101
111

Symbolic
Operation

Flags
P/
S Z x H x V N C

Opcode76 543 210# of Execute
HEX Bytes
Time
Notes

B ¨ B-1(C) ← (HL)HL ← HL + 1
B ← B-1(C) ← (HL)HL ¨ HL + 1
Repeat until B = 0
B ← B-1(C) ← (HL)HL ¨ HL - 1
Repeat until B = 0
B ← B-1(C) ← (HL)HL ¨ HL - 1
Repeat until B = 0• ◊ x • x • 1 •(1)

11 10110 100

101
011

ED
A3

2

2+r+o

N

•

1 x •
(2)

x •

1 •

11 101
10 110

101
011

ED
B3

2

2+r+o

N

•

1 x •
(2)

x •

1 •

11 101
10 111

101
011

ED
BB

2

2+r+o

N

•

1 x •
(2)

x •

1 •

11 101
10 111

101
011

ED
BB

2

2+r+o

N

Reg
B
C
D
E
H
L
A

Notes:
Instructions in Italic face are Z380 new instructions, instructions with underline are Z180 original instructions.
I:
This instruction may be used with DDIR Immediate instructions.
N: In Native mode, this instruction address modulo 65536.
(1): P/V flag is 0 if the result of BC-1 = 0, otherwise P/V = 1/.
(2): P/V flag is 0 only at completion of instruction.

Page 85 of 125

INPUT AND OUTPUT INSTRUCTIONS FOR ON-CHIP I/O SPACE

Mnemonic

Symbolic
Operation

Flags
S Z x H x

P/
V N C

Opcode76 543 210

INO r,(n)r ← (n)↕ ↕ x 0 x

P 0 •

ED

3

3+i

(3)

INO (n)r ← (n)Changes Flag only.

↕ ↕ x 0 x

P 0 •

ED
30

3

3+i

(3)

OUT0 (n),r(n) ← r• • x • x

• • •

ED

3

3+o

(3)

TSTIO n(C) AND n↕ ↕ x 1 x

P 0 0

ED
74

3

3+i

(3)

OTIIM

(C) ← (HL)HL ← HL + 1
C ← C+1B←B-1(C) ← (HL)HL ← HL + 1
C←C+1B ← B -1
Repeat until B = 0(C) ← (HL)HL ← HL - 1
C←C-1
B←B-1
(C) ← (HL)HL ← HL - 1
C←C-1
B←B-1
Repeat until B = 0↕ ↕ x ↕ xP ↕ ↕

11 101 10100
r000← n →11 101 10100
r000← n →11 101 10100
r001← n →11 101 101
01 110 100← n →11 101 101
10 000 011

ED
83

3

2+r+o

(3),N

0 1 x 0 x
(2)

1 ↕ 0

11 101
10 010

101
011

ED
93

3

2+r+o

(3),N

↕ ↕ x ↕ xP ↕ ↕

11 101
10 001

101
011

ED
8B

3

2+r+o

(3),N

0 1 x 0 x
(2)

1 ↕ 0

11 101
10 011

101
011

ED
9B

3

2+r+o

(3),N

OTIIMR

OTDM

OTDMR

r
010
011
100
101
111

HEX

# of Execute
Bytes Time Notes

Reg
D
E
H
L
A

Notes:
Instructions in Italic face are Z380 new instructions, instructions with underline are Z180 original instructions.
I:
This instruction may be used with DDIR Immediate instructions.
N: In Native mode, this instruction address modulo 65536.
(1): P/V flag is 0 if the result of BC-1 = 0, otherwise P/V = 1/.
(2): P/V flag is 0 only at completion of instruction.

Page 86 of 125

16-BIT INPUT AND OUTPUT GROUP

Mnemonic

Symbolic
Operation

Flags
P/
S Z x H x V N C

Opcode# of Execute76 543 210 HEX Bytes Time Notes

INW pp,(C)pp ← (C)↕ ↕ x 0 x P 0 •DD

2

INAW HL,(nn)HL(15-0) ← (nn)• • x • x • • •

FD
DB

4

3+i

I

INIW

• ↕ x • x • 1 •
(1)

ED
E2

2

2+i+w

N

• 1 x • x • 1 •(2)

11 101 101
11 110 010

EDF2

2 (2+i+w)nN• ↕ x • x • 1 •(1)

11 101 101
11 101 010

ED
EA

2

2+i+w

N

• 1 x • x • 1 •(2)

11 101 101
11 111 010

EDFA

2 (2+i+w)nN

OUTW (C),pp(HL) ← (DE)BC(15-0) ← BC(15-0) - 1
HL ← HL+2(HL) ← (DE)BC(15-0) ← BC(15-0) - 1
HL ← HL+2
Repeat until BC = 0(HL) ← (DE)BC(15-0) ← BC(15-0) - 1
HL ← HL - 2(HL) ← (DE)BC(15-0) ← BC(15-0) - 1
HL ← HL - 2
Repeat until BC = 0(C) ← pp

11 011 101
01 ppp 000
11 111 101
11 011 011← n →← n →11 101 101
11 100 010• • x • x • • •

DD

2

2+o

OUTW (C),nn(C) ← nn

• • x • x • • •

FD
79

4

2+o

OUTAW (nn),HL(nn) ← HL(15-0)• • x • x • • •

FD
D3

4

2+o

I

OUTIW

(DE) ← (HL)
BC(15-0) ← BC(15-0) - 1
HL ← HL + 2
BC(15-0) ← BC(15-0) - 1(DE) ← (HL)HL ← HL + 2
Repeat until B = 0• ↕ x • x • 1 •(1)

11 011 101
01 ppp 001
11 111 101
01 111 001← n →← n →11 111 101
11 010 011← n →← n →11 101 101
11 100 011

ED
E3

2

2+o

N

• 1 x • x • 1 •(2)

11 101 101
11 110 011

ED
F3

2

2+o

N

INIRW

INDW

INDRW

OTIRW

Page 87 of 125

16-BIT INPUT AND OUTPUT GROUP (Continued)

Mnemonic
OUTDW

OTDRW

ppp
000
010
111

Symbolic
Operation

Flags
P/
S Z x H x V N C

Opcode76 543 210# of Execute
HEX Bytes Time
Notes

BC(15-0) ← BC(15-0) - 1(DE) ← (HL)HL ← HL - 2
BC(15-0) ← BC(15-0) - 1(DE) ← (HL)HL ← HL - 2
Repeat until B = 0• ↕ x • x • 1 •(1)

11 101 101
11 101 011

ED
EB

2

2+r+o

• 1 x • x • 1 •(2)

11 101 101
11 111 011

ED
FB

2

2+r+o

Reg
BC
DE
HL

Notes:
Instructions in Italic face are Z380 new instructions, instructions with underline are Z180 original instructions.
I:
This instruction may be used with DDIR Immediate instructions.
N: In Native mode, this instruction uses addresses modulo 65536.
(1) If the result of B-1 is zero, the Z flag is set; otherwise it is reset.
(2) Z flag is set upon instruction completion only.

I/O Instruction

A31-A24

Address Bus
A23-A16

A15-A8A7-A0

IN A, (n)IN dst,(C)INA(W) dst,(mn)DDIR IB INA(W) dst,(lmn)
DDIR IW INA(W) dst,(klmn)
Block Input

00000000
BC31-BC24
00000000
00000000k
BBC31-BC24

00000000
BC23-BC16
00000000llBC23-BC16

Contents of A reg
BC15-BC8m
m
m
BC15-BC8n
BC7-BC0nnnBC7-BC0

OUT (n),AOUT (C),dst
OUTA(W) (mn),dst
DDIR IB OUTA(W) (lmn),dst
DDIR IW OUTA(W) (klmn),dst
Block output

00000000
BC31-BC24
00000000
00000000k
BC31-BC24

00000000
BC23-BC16
00000000llBC23-BC16

Contents of A reg
BC15-BC8m
m
m
BC15-BC8n
BC7-BC0nnnBC7-BC0

Page 88 of 125

INTERRUPTSThe Z380 MPU’s interrupt structure provides compatibility
with the existing Z80 and Z180 MPUs with the following
exception: The undefined opcode trap’s occurrence iswith respect to the Z380 instruction set, and its response
is improved (vs the Z180) to make trap handling easier.
The Z380 MPU also offers additional features to enhanceflexibility in system design.
Of the five external interrupt inputs provided, the /NMI is anonmaskable interrupt. The remaining inputs, /INT3-/INT0,
are four asynchronous maskable interrupt requests.
In an Interrupt Acknowledge transaction, address outputs
A31-A0 are driven to logic 1's. One output among A3-A0 isdriven to logic 0 to indicate the maskable interrupt request
being acknowledged. If /INT0 is being acknowledged,
A3-A1, is at logic 1's and A0 is at logic 0.
Interrupt modes 0 through 3 are supported for the externalmaskable interrupt request /INT0. Modes 0, 1 and 2 havethe same schemes as those in the Z80 and Z180 MPUs.
Mode 3 is similar to mode 2, except that 16-bit interrupt
vectors are expected from the I/O devices. Note that 8-bit
and 16-bit I/O devices can be intermixed in this mode byhaving external pull up resistors at the data bus signals
D15-D8, for example.
The external maskable interrupt requests /INT3-/INT1 arehandled in an assigned interrupt vectors mode.

As discussed in the CPU Architecture section, the Z380
MPU can operate in either the Native or Extended Mode.
In Native Mode, PUSHing and POPing of the stack to saveand retrieve interrupted PC values in interrupt handling aredone in 16-bit sizes, and the stack pointer rolls over at the
64 Kbyte boundary. In Extended Mode, the PC PUSHes
and POPs are done in 32-bit sizes, and the stack pointerrolls over at the 4 Gbyte memory space boundary. The
Z380 MPU provides an Interrupt Register Extension, whose
contents are always outputted as the address bus signals
A31-A16 when fetching the starting addresses of service
routines from memory in interrupt modes 2, 3 and theassigned vectors mode. In Native Mode, such fetches areautomatically done in 16-bit sizes and in Extended Mode,in 32-bit sizes. These starting addresses should be evenaligned in memory locations. That is, their least significant
bytes should have addresses with A0 = 0.

Interrupt Priority Ranking
The Z380 MPU assigns a fixed priority ranking to handle its
interrupt sources, as shown in Table 2.
Table 2. Interrupt Priority Ranking
Priority

Interrupt Sources

HighestTrap (undefined opcode)
/NMI
/INT0
/INT1
/INT2
/INT3

↓
LowestPage 89 of 125

Interrupt Control
The Z380 MPU’s flags and registers associated with interrupt processing are listed in Table 4. As discussed in the
CPU Architecture section, some of the registers reside in

the on-chip I/O address space and can be accessed onlywith reserved on-chip I/O instructions.

Table 3. Interrupt Flags and Registers
Names

Mnemonics

Access Methods

Interrupt Enable Flags
Interrupt Register
Interrupt Register Extension

IEF1, IEF2
I
Iz

Interrupt Enable Register

IER

Assigned Vectors Base Register

AVBR

Trap and Break Register

TRPBK

EI and DI instructions
LD I,A and LD A,I instructions
LD I,HL and LD HL,I instructions(accessing both Iz and I)
On-chip I/O instructions, addr
00000017H, EI and DI instructions
On-chip I/O instructions, addr
00000018H
On-chip I/O instructions, addr
00000019H

IEF1, IEF2
IEF1 controls the overall enabling and disabling of all onchip peripheral and external maskable interrupt requests.
If IEF1 is at logic 0, all such interrupts are disabled. The
purpose of IEF2 is to correctly manage the occurrence of/NMI. When /NMI is acknowledged, the state of IEF1 iscopied to IEF2 and then IEF1 is cleared to logic 0. At theend of the /NMI interrupt service routine, execution of the
Return From Nonmaskable Interrupt instruction, RETN,
automatically copies the state of IEF2 back to IEF1. This isa means to restore the interrupt enable condition existing
before the occurrence of /NMI. Table 5 summarizes thestates of IEF1 and IEF2 resulting from various operations.

Table 4. Operation Effects on IEF1 and IEF2
Operation

IEF1

IEF2

Comments/RESET
Trap
/NMI
RETN
/INT3-/INT0
RETI
RET
EI
DI
LD A,I or LD R,I
LD HL,I

0
0
0
IEF2
0
NC
NC
1
0
NC
NC

0
0
IEF1
NC
0
NC
NC
1
0
NC
NC

Inhibits all interrupts except Trap and /NMI.
Disables interrupt nesting.
IEF1 value copied to IEF2, then IEF1 is cleared.
Returns from /NMI service routine.
Disables interrupt nesting.
Returns from service routine, Z80 I/O device.
Returns from service routine, non-Z80 I/O device.

IEF2 value is copied to P/V Flag.

Note:
NC = No Change

I, I Extend
The 8-bit Interrupt Register and the 16-bit Interrupt
Register Extension are cleared during reset.

Page 90 of 125

Interrupt Enable Register
IE3-IE0 (Interrupt Request Enable Flags). These flags
individually indicate F /INT3, /INT2, /INT1 or /INT0 isenabled. Note that these flags are conditioned with enable
and disable interrupt instructions (with arguments).

Reserved bits 7-4. Read as 0s, should write to as 0s.

IER: 00000017H
Read Only
0

7
--

--

--

--

IE3

IE2

IE1

IE0

0

0

0

0

0

0

0

1

Reset Value

Encoded Interrupt
Requests
Interrupt Requests
EnableFigure 25. Interrupt Enable Register

Assigned Vectors Base RegisterAB15-AB9 (Assigned Vectors Base). The Interrupt Register Extension, Iz, together with AB15-AB9, define the baseaddress of the assigned interrupt vectors table in memory
space (Figure 26).

Reserved Bit 0. Read as 0, should write to as 0.

AVBR: 00000018H
R/W
07
AB15 AB14 AB13 AB12 AB11 AB10 AB9
0

0

0

0

0

0

0

-0

Reset ValueReserved
Program as 0
Read as 0
Assigned Vectors
Base

Figure 26. Assigned Vectors Base Register

Page 91 of 125

Trap and Break Register
Reserved bits 7-2. Some of these bits are reserved forbreakpoint functions, including a Break-on-Halt feature.

Refer to the Z380 ICE specifications for details. Read as 0s,
should write to as 0s.

TRPBK: 00000019H
R/W
7

0

--

--

--

--

--

--

TF

TV

0

0

0

0

0

0

0

0

Reset Value
Trap on Interrupt Vector
Trap on Instruction Fetch
Reserved
Program as 0
Read as 0

Figure 27. Trap and Break Register

TF (Trap on Instruction Fetch). TF goes active to logic 1
when an undefined opcode fetched in the instruction
stream is detected. TF can be reset under program control
by writing it with a logic 0. However, it cannot be written witha logic 1.

TV (Trap on Interrupt Vector). TV goes active to logic 1
when an undefined opcode is returned as a vector in aninterrupt acknowledge transaction in mode 0. TV can bereset under program control by writing it with a logic 0.
However, it cannot be written with a logic 1.

Trap Interrupt
The Z380 MPU generates a trap when an undefined
opcode is encountered. The trap is enabled immediately
after reset, and it is not maskable. This feature can be used
to increase software reliability or to implement extended
instructions. An undefined opcode can be fetched fromthe instruction stream, or it can be returned as a vector in
an interrupt acknowledge transaction in interrupt mode 0.
When a trap occurs, the Z380 MPU operates as follows.
1. The TF or TV bit in the Assigned Vectors Base and Trap
Register goes active, to indicate the source of the
undefined opcode.
2. If the undefined opcode was fetched from instruction
stream, the starting address of the trap causing instruction is pushed onto the stack. (Note that thestarting address of a decoder directive preceding an
instruction encoding is considered the starting address of the instruction.)If the undefined opcode was a returned interrupt
vector (in interrupt mode 0), the interrupted PC value
is pushed onto the stack.
3. The states of IEF1 and IEF2 are cleared.
4. The Z380 MPU commences to fetch and execute
instructions from address 00000000H.
Note that instruction execution resumes at address 0,
similar to the occurrence of a reset. Testing the TF and TV
bits in the Assigned Vectors Base and Trap Register will
distinguish the two events. Even if trap handling is not inplace, repeated restarts from address 0 is an indicator of
possible illegal instructions at system debugging.

Page 92 of 125

Nonmaskable Interrupt
The nonmaskable interrupt input /NMI is edge sensitive,
with the Z380 MPU internally latching the occurrence of its
falling edge. When the latched version of /NMI is recognized, the following operations are performed.
1. The interrupted PC (Program Counter) value is pushed
onto the stack.
2. The state of IEF1 is copied to IEF2, then IEF1 is cleared.
3. The Z380 MPU commences to fetch and execute instructions from address 00000066H.

Interrupt Mode 0 Response For
Maskable Interrupt /INT0
During the interrupt acknowledge transaction, the external
I/O device being acknowledged is expected to output avector onto the lower portion of the data bus, D7-D0. The
Z380 MPU interprets the vector as an instruction opcode,
which is usually one of the single-byte Restart (RST)
instructions that pushes the interrupted PC (Program
Counter) value onto the stack and resumes execution at a
fixed memory location. However, the Z380 MPU will generate multiple transactions to capture vectors that form a
multi-byte instruction. IEF1 and IEF2 are reset to logic 0’s,
disabling all further maskable interrupt requests. Note that
unlike the other interrupt responses, the PC is not automatically PUSHed onto the stack. Note also that a trap occurs
if an undefined opcode is supplied by the I/O device as avector.

Interrupt Mode 1 Response For
Maskable Interrupt /INT0
An interrupt acknowledge transaction is generated, during
which the data bus contents are ignored by the Z380 MPU.
The interrupted PC value is PUSHed onto the stack. IEF1
and IEF2 are reset to logic 0’s so as to disable further
maskable interrupt requests. Instruction fetching and execution restarts at memory location 00000038H.

Interrupt Mode 2 Response For
Maskable interrupt /INT0
During the interrupt acknowledge transaction, the external
I/O device being acknowledged is expected to output avector onto the lower portion of the data bus, D7-D0. Theinterrupted PC value is PUSHed onto the stack and IEF1
and IEF2 are reset to logic 0’s so as to disable further
maskable interrupt requests. The Z380 MPU then reads anentry from a table residing in memory and loads it into the
PC to resume execution. The address of the table entry iscomposed of the I Extend contents as A31-A16, the IRegister contents as A15-A8 and the vector supplied by
the I/O device as A7-A0. Note that the table entry iseffectively the starting address of the interrupt service
routine designed for the I/O device being acknowledged.
The table, composed of starting addresses for all theinterrupt mode 2 service routines, can be referred to as theinterrupt mode two vector table. Each table entry should
be word-sized if the Z380 MPU is in the Native Mode andlongword-sized if in the Extended Mode, in either case it iseven-aligned (least significant byte with address A0 = 0).

Interrupt Mode 3 Response For
Maskable Interrupt /INT0
Interrupt mode 3 is similar to mode 2 except that a 16-bit
vector is expected to be placed on the data bus D15-D0 by
the I/O device during the interrupt acknowledge transaction. The interrupted PC is PUSHed onto the stack. IEF1
and IEF2 are reset to logic 0’s so as to disable further
maskable interrupt requests. The starting address of theservice routine is fetched and loaded into the PC to resume
execution from the memory location with an addresscomposed of the I Extend contents as A31-A16 and thevector supplied by the I/O device as A15-A0. Again thestarting address of the service routine is word-sized if the
Z380 MPU is in the Native Mode and longword-sized if in
the Extend Mode, in either case even-aligned.

Page 93 of 125

Assigned Interrupt Vectors Mode For
Maskable interrupt INT3-/INT1
When the Z380 MPU recognizes one of the externalmaskable interrupts it generates an Interrupt Acknowledge transaction which is different than that for /INT0. The
Interrupt Acknowledge transaction for /INT3-/INT1 has the
I/O bus signal /INTAK active, with /MI, /IORQ, /IORD and/IOWR inactive. The interrupted PC value is PUSHed onto
the stack. IEF1 and IEF2 are reset to logic 0s, disabling
further maskable interrupt requests. The starting addressof an interrupt service routine is fetched from a table entry
and loaded into the PC to resume execution. The addressof the table entry is composed of the I Extend contents as
A31-A16, the AB bits of the Assigned Vectors Base Register as A15-A9 and an assigned interrupt vector specificto the request being recognized as A8-A0. The assigned
vectors are defined in Table 5.

RETI Instruction
The Z80 family I/O devices are designed to monitor the
Return from Interrupt opcodes in the instruction stream(RETI-EDH, 4DH), signifying the end of the current interrupt service routine. When detected, the daisy chain within
and among the device(s) resolves and the appropriate
interrupt-under-service condition clears. The Z380 MPU
reproduces the opcode fetch transactions on the I/O bus
when the RETI instruction is executed. Note that the Z380
MPU outputs the RETI opcodes onto both portions of thedata bus (D15-D8 and D7-D0) in the transactions.

Table 5. Assigned Interrupt Vectors
Interrupt Source

Assigned Interrupt Vector

/INT1
/INT2
/INT3

00H
04H
08H

Page 94 of 125

ON-CHIP PERIPHERAL FUNCTIONSThe Z380 MPU incorporates a number of functions to ease
its interface with external I/O devices and with various
types of memories. The Z380 MPU's I/O bus can be
programmed to run at a slower rate than its memory bus.
In addition, a heartbeat transaction can be generated on
the I/O bus that emulates a Z80 CPU instruction fetch
cycle. Such a transaction is useful for a particular Z80
family I/O device to perform its interrupt functions. Memory
chip select signals can be activated to access the lowest
16 Mbytes of the Z380 MPU's memory address space, withwait state insertions. Lastly, a DRAM refresh function isincorporated, with programmable refresh transaction burst
size. The above functions are controlled by several onchip registers. As described in the CPU Architecture
section, these registers together with several other registers that control a portion of the interrupt functions, occupy
an on-chip I/O address space. This on-chip I/O address
can be accessed only by the following reserved on-chip
I/O instructions.

IN0
IN0
OUT0
TSTIO

OTIM
OTIMR
OTDM
OTDMR

When one of the above instructions is executed, the Z380
MPU outputs the register address being accessed in a
pseudo transaction of two BUSCLK cycles duration, withthe address signals A31-A8 at logic 0s. In the pseudotransaction, all bus control signals are at their inactive
states. It is to be emphasized that the Z380 MPU adopts an
instruction specific scheme to access on-chip I/O registers, with their unique address space. This is in contrast to
mapping such registers with external peripherals in acommon I/O address space, as is done in the Z180 MPU.

I/O Bus Control Register 0
CR2-CR0 (I/O Clock Rate). BUSCLK is divided down to
produce IOCLK as defined in the following.

Some on-chip peripherals are capable of generating interrupt requests, which are always handled in the assigned
interrupt vectors mode.

000
010
100
110

I/O Bus Control
The Z380 MPU is designed to interface easily with external
I/O devices that can be of either the Z80 or Z8500 productfamily by supplying five I/O bus control signals: /M1,
/IORQ, /IORD, /IOWR and /INTAK. In addition, the Z380
MPU is supplying an IOCLK that is a divided down versionof its BUSCLK. Programmable wait states can be inserted
in the various I/O transactions. The External Interface
section details all the I/O transactions.

R, (n)(n)(n), Rndivided-by-8
divided-by-2
divided-by-4
divided-by-6

001
011
101
111

divided-by-1
divided-by-1
divided-by-1
divided-by-1

Note that if a clock divide rate of 1 is specified, BUSCLK
should be used to connect to I/O devices that require aclock input, since the Z380 MPU outputs a constant logic
1 at IOCLK.
Reserved bits 7-3. Read as 0s, should write to as 0s.

IOCR0: 00000011H
R/W
0

7
--

--

--

--

--

CR2

0

0

0

0

0

0

CR1 CR0
00<- Reset ValueI/O ClockReserved Program as 0
Read as 0

Figure 28. I/O Bus Control Register 0

Page 95 of 125

I/O Bus Control Register 1
When this phantom register IOCR1 with address
00000012H is accessed with one of the on-chip I/O write
instructions, a heartbeat transaction that emulates a Z80
CPU instruction fetch is performed on the I/O bus. Thistransaction provides a /M1 pulse which is necessary as
part of an interrupt enable sequence for a Z80 PIO product.
In the on-chip I/O write instruction, the data being "written"
can be of any value. In case of an on-chip I/O read with the
IOCR1 address, the data returned is unpredictable.

states are also inserted in each of the opcode fetchtransactions of the Return from Interrupt (RETI) instruction
reproduced on the I/O bus. When programmed with 0s, theI/O waits are disabled.

I/O Waits Register

DCW2-DCW0 (Interrupt Daisy Chain Waits). This binary
field defines up to seven wait states to be inserted at theearly portions of interrupt acknowledge transactions, for
the interrupt daisy chain through the external I/O devices
to settle.

RTW1-RTW0 (RETI Waits). This binary field defines up to
three wait states to be inserted between opcode fetchtransactions of the Return from Interrupt instruction reproduced on the I/O bus.

OW2-IOW0 (I/O Waits). This binary field defines up toseven wait states to be inserted in external I/O read andwrite transactions, and at the latter portions of interrupt
transactions to capture interrupt vectors. The defined wait

IOWR: 0000000EH
R/W
7

0

IOW2 IOW1 IOW0 RTW1 RTW0 DCW2 DCW1 DCW0

1

1

1

1

1

1

1

1

<- Reset Value
Interrupt Daisy
Chain Waits
RET I Waits
I/O Waits

Figure 29. I/O Waits Register

Page 96 of 125

MEMORY CHIP SELECTS AND WAITSThe Z380 MPU offers two schemes to generate chip selectsignals to access the lowest 16 Mbytes of its memory
address space. The first scheme provides six chip selectsignals, with the address space partitioned as shown in
Figure 30. The second scheme provides three chip selectsignals, and the address space partitioning is shown in
Figure 31. Note that the /MCS0 signal is used to indicate
accesses to the entire mid-range memory in the second
scheme.

A flexible wait state insertion scheme is incorporated in thechip select logic. A user can program T1, T2 and T3 waits
separately for accesses to the lower, upper and mid-range
memory areas. If chip select scheme one is in effect,different wait states can be defined for each of the midrange memory areas 3 through 0.
00FFFFFF

/UMCS

Upper
Memory/MCS

Mid-range
Memory00FFFFFF
/UMCS

Upper
MemoryUnused/MCS3Mid-range
Memory3/MCS2

Mid-range
Memory2/MCS1

Mid-range
Memory1/MCS0

Mid-range
Memory0

Unused

/LMCS

Lower
Memory00000000
Memory Chip Select Scheme 2

/LMCS

Lower
Memory00000000

Figure 31. Chip Select Address Space

Memory Chip Select Scheme 1

Figure 30. Chip Select Address Space

Page 97 of 125

Lower Memory Chip Select Control

Lower Memory Chip Select Register 1

This memory area has its lower boundary at address
000000000H. A user can define the size to be an integer
power of two, starting at 4 Kbytes. For example, the lower
memory area can be either 4 Kbytes, 8 Kbytes, 16 Kbytes,
etc., starting from address 0. The /LMCS signal can be
enabled to go active during refresh transactions.

MA23-MA16 (Match Address Bits 23-16). If amatch address bit is at logic 1, the corresponding addresssignal of a memory transaction is compared for a logic 0,
as a condition for /LMCS to become active. If the match
address bit is at logic 0, the corresponding address signal
is not compared (don't care). For example, MA23 determines if A23 should be tested for a logic 0 in memorytransactions. Note that in order for /LMCS to go active in amemory transaction, the /LMCS function has to be enabledin the Memory Selects Master Enable Register (describedlater), all the address signals A31-A24 at logic 0s, and all
the address signals A23-A12 programmed for address
matching in the above registers have to be at logic 0s. To
define the lower memory area as 4 Kbytes, MA23-MA12
should be programmed with 1s. For an area larger than 4
Kbytes, MA23-MA12 (in that order) should be programmedwith contiguous 1s followed by contiguous 0s. This is theintended usage to maintain the lower memory area as asingle block. Note also that /LMCS can be enabled forrefresh transactions independent of the value programmed
into the Memory Selects Master Enable Register.

Lower Memory Chip Select Register 0
MA15-MA12 (Match Address Bits 15-12). If a match address bit is at logic 1, the corresponding address signal ofa memory transaction is compared for a logic 0, as acondition for /LMCS to become active. If the match address bit is at logic 0, the corresponding address signal is
not compared (don't care). For example, MA12 determines if A12 should be tested for a logic 0 in memorytransactions.
Reserved bits 3-1. Read as 0s, should write to as 0s.
ERF (Enable for Refresh transactions). If this bit is programmed to a logic one, /LMCS goes active during refreshtransactions.

LMCSR1: 00000001H
R/W
7

LMCSR0: 00000000H
R/W
7

MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16

MA15 MA14 MA13 MA12

--

--

--

ERF

0

0

0

0

1
0

0

0

0

0

0

<- Reset Value
Enable for Refresh

1

1

1

0

0

0

0

<- Reset Value
Match Address
Bits 23-16

Reserved
Program as 0
Read as 0
Match Address Bits 15-12

Figure 33. Lower Memory Chip Select Register 1

Figure 32. Lower Memory Chip Select Register 0

Page 98 of 125

Upper Memory Chip Select Control

Upper Memory Chip Select Register 1

The upper boundary for this memory area is address
00FFFFFFH. A user can define the area immediately below
this boundary with a size that is an integer power of two,
starting at 4 Kbytes. That is, the upper memory area can beeither 4 Kbytes, 8 Kbytes, 16 Kbytes and so on. The /UMCS
signal can be enabled to go active during refresh transactions.

MA23-MA16 (Match Address Bits 23-16). If a match address bit is at logic 1, the corresponding address signal ofa memory transaction is compared for a logic 1, as acondition for /UMCS to become active. If the mask address
bit is at logic 0, the corresponding address signal is notcompared (don't care). For example, MA23 determines if
A23 should be tested for a logic 1 in memory transactions.
Note that in order for/UMCS to go active in a memorytransaction, the /UMCS function has to be enabled in the
Memory Selects Master Enable Register (described later),
all the address signals A31-A24 at logic 0s, and all theaddress signals A23-A12 programmed for address matching in the above registers have to be at logic 1s. To define
the upper memory area as 4 Kbytes, MA23-MA12 should
be programmed with 1s. For an area larger than 4 Kbytes,
MA23-MA12 (in that order) should be programmed with
contiguous 1s followed by contiguous 0s. This is theintended usage to maintain the upper memory area as asingle block. Note also that /UMCS can be enabled forrefresh transactions independent of the value programmed
into the Memory Selects Master Enable Register.

Upper Memory Chip Select Register 0
MA15-MA12 (Match Address Bits 15-12). If a match address bit is at logic 1, the corresponding address signal ofa memory transaction is compared for a logic 1, as acondition for /UMCS to become active. If the match address bit is at logic 0, the corresponding address signal is
not compared (don't care). For example, MA12 determines if A12 should be tested for a logic 1 in memorytransactions.
Reserved bits 3-1. Read as 0s, should write to as 0s.
ERF (Enable for Refresh Transactions). If this bit is programmed to a logic 1, /UMCS goes active during
refresh transactions.

UMCSR1: 00000003H
R/W
7

UMCSR0: 00000002H
R/W
7

0

MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA1601MA15 MA14 MA13 MA12
0

0

0

0

--

--

--

ERF

0

0

0

0

<- Reset Value

1

1

1

0

0

0

0

<- Reset Value
Match Address
Bits 23-16

Enable for RefreshReserved
Program as 0
Read as 0

Figure 35. Upper Memory Chip Select Register 1

Match Address Bits 15-12

Figure 34. Upper Memory Chip Select Register 0

Page 99 of 125

Mid-range Memory Chip Select(s) Control

Mid-range Memory Chip Select Register 1

In chip select scheme 1, a user can define the baseaddress and the total size of the mid-range memory area.
The /MCS0 signal would be active for the lowest quarter
portion of the area defined, starting from the base address.
Each of the /MCS1-/MCS3 signals would be active, corresponding to the successively higher quarter portions of thetotal mid-range memory area. In chip select scheme 2, themid-range memory area is between the lower and upper
memory areas. The /MCS3-/MCS0 signals can be individually enabled to go active in refresh transactions.

MA23-MA16 (Match Address bits). In chip select scheme
1, if a match address bit is at logic 1, the corresponding
address signal of a memory transaction is compared withthe corresponding base address bit for a match, as acondition for one of /MCS3-/MCS0 to become active. If thematch address bit is at logic 0, the corresponding addresssignal and base address bit are not compared (don'tcare). For example, MA23 determines if A23 should becompared for a match with BA23. The contents of thisregister have no effects in chip select scheme 2.

Mid-range Memory Chip Select Register 0
MA15-MA14 (Match Address Bits 15-14). In chip selectscheme 1, if a match address bit is at logic 1, the corresponding address signal of a memory transaction is compared with the corresponding base address bit for amatch, as a condition for one of /MCS3-/MCS0 to become
active. If the match address bit is at logic 0, the corresponding address signal and base address bit are notcompared (don't care). For example, MA14 determines if
A14 should be compared for a match with BA14. The
values of MA15-MA14 have no effects in chip selectscheme 2.
Reserved bits 5-4. Read as 0s, should write to as 0s.
ERF3-ERF0 (Enable for Refresh Transactions). The midrange memory chip select signals can be individuallyenabled to go active during refresh transactions. As an
example, /MCS0 goes active in refresh transactions if
ERF0 is programmed at logic 1.

MMCSR1: 00000005H
R/W
7
MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16
0

0

0

0

0

0

0

0

<- Reset Value
Match Address
Bits 23-16

Figure 37. Mid-range Memory Chip Select Register 1

Mid-range Memory Chip SelectRegister 2 & 3
MMCSR2: 00000006H
R/W
07
BA15 BA14

MMCSR0: 00000004H
R/W

0

0

0

--

--

--

--

--

--

0

0

0

0

0

0

<- Reset Value

0

7
MA15 MA14
0

0

--

--

0

0

ERF3 ERF2 ERF1 ERF0
0

0

0

0

<- Reset Value

Figure 38. Mid-range Memory Chip Select Register 2

Enable for RefreshTransactions
Reserved Bits
Match Address
Bits 15-14

Figure 36. Mid-range Memory Chip Select Register 0

Page 100 of 125

BA23-BA14 (Base Address 23-14). In chip select scheme
1, the address signals A23-A16 of a memory transaction
are compared with BA23-BA16 for a match, for those bits
programmed for address matching in the Mid-range
Memory Chip Select Register 1. The contents of thisregister have no effects in chip select scheme 2. Note thatin order for one of /MCS3-/MCS0 to go active in a memorytransaction in chip select scheme 1, the ENM1 bit in the
Memory Selects Master Enable Register (described later)
has to be at logic 1, all the address signals A31-A24 at logic
0s, and for those bits programmed for address matching,
A23-A14 matching BA23-BA14. For the intended usage tomaintain the mid-range memory area as a single block,MA23-MA14 (in that order) should be programmed for
address matching with contiguous 1s followed by contiguous 0s. Note also that /MCS3-/MCS0 can be individuallyenabled to go active during refresh transactions, independent of the value programmed into the Memory Selects
Master Enable Register.

0

BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16
0

0

0

0

0

0

0

0

0

T1W2 T1W1 T1W0 T2W1 T2W0 T3W2 T3W1 T3W0
1

1

1

1

1

1

1

1

<- Reset Value
T3 Waits
T2 Waits
T1 Waits

Figure 40. Lower Memory Waits Register

Upper Memory Wait Register
T1W2-T1W0 (T1 Waits). This binary field defines up toseven T1 wait states to be inserted in transactions accessing the upper memory area.
T2W1-T2W0 (T2 Waits). This binary field defines up to
three T2 wait states to be inserted in transactions accessing the upper memory area.

MMCSR3: 00000007H
R/W
7

LMWR: 00000008H
R/W
7<- Reset Value

T3W2-T3W0 (T3 Waits). This binary field defines up toseven T3 wait states to be inserted in transactions accessing the upper memory area.

Figure 39. Mid-range Memory Chip Select Register 3

Lower Memory Wait Register
T1W2-T1W0 (T1 Waits). This binary field defines up toseven T1 wait states to be inserted in transactions accessing the lower memory area.
T2W1-T2W0 (T2 Wait States). This binary field defines up
to three T2 wait states to be inserted in transactions
accessing the lower memory area.
T3W2-T3W0 (T3 Waits). This binary field defines up toseven T3 wait states to be inserted in transactions accessing the lower memory area.

UMWR: 00000009H
R/W
7

0

T1W2 T1W1 T1W0 T2W1 T2W0 T3W2 T3W1 T3W0
1

1

1

1

1

1

1

1

<- Reset Value
T3 Waits
T2 Waits
T1 Waits

Figure 41. Upper Memory Waits Register

Page 101 of 125

Mid-range Memory Wait Register 0

Mid-Range Memory Wait Register 1

T1W2-T1W0 (T1 Waits). This binary field defines up toseven T1 wait states to be inserted in transactions
accessing the mid-range memory area 0 in chip selectscheme 1, or the entire mid-range memory area in chip
select scheme 2.

T1W2-T1W0 (T1 Waits). This binary field defines up toseven T1 wait states to be inserted in transactions
accessing the mid-range memory area 1 in chip selectscheme 1.

T2W1-T2W0 (T2 Waits). This binary field defines up to
three T2 wait states to be inserted in transactions accessing the mid-range memory area 0 in chip select scheme 1,or the entire mid-range memory area in chip selectscheme 2.
T3W2-T3W0 (T3 Waits). This binary field defines up toseven T3 wait states to be inserted in transactions accessing the mid-range memory area 0 in chip select scheme 1,or the entire mid-range memory area in chip selectscheme 2.
MMWR0: 0000000AH
R/W
7

1

1

T3W2-T3W0 (T3 Waits). This binary field defines up toseven T3 wait states to be inserted in transactions accessing the mid-range memory area 1 in chip select scheme 1.
The contents of this register have no effects in chip selectscheme 2.
MMWR1: 0000000BH
R/W
7

0

T1W2 T1W1 T1W0 T2W1 T2W0 T3W2 T3W1 T3W00

1

T1W2 T1W1 T1W0 T2W1 T2W0 T3W2 T3W1 T3W0
1

T2W1-T2W0 (T2 Waits). This binary field defines up to
three T2 wait states to be inserted in transactions accessing the mid-range memory area 1 in chip select scheme 1.

1

1

1

1

1

1

1

1

1

1

1

1

<- Reset Value
T3 Waits<- Reset Value
T3 Waits

T2 Waits
T1 Waits

T2 Waits
T1 Waits

Figure 43. Mid-range Memory Waits Register 1

Figure 42. Mid-range Memory Waits Register 0

Page 102 of 125

Mid-Range Memory Wait Register 2

Mid-range Memory Waits Register 3

T1W2-T1W0 (T1 Waits). This binary field defines up toseven T1 wait states to be inserted in transactions
accessing the mid-range memory area 2 in chip selectscheme 1.

T1W2-T1W0 (T1 Waits). This binary field defines up toseven T1 wait states to be inserted in transactions
accessing the mid-range memory area 3 in chip selectscheme 1.

T2W1-T2W0 (T2 Waits). This binary field defines up to
three T2 wait states to be inserted in transactions accessing the mid-range memory area 2 in chip select scheme 1.

T2W1-T2W0 (T2 Waits). This binary field defines up to
three T2 wait states to be inserted in transactions accessing the mid-range memory area 3 in chip select scheme 1.

T3W2-T3W0 (T3 Waits). This binary field defines up toseven T3 wait states to be inserted in transactions accessing the mid-range memory area 2 in chip select scheme 1.
The contents of this register have no effects in chip selectscheme 2.

T3W2-T3W0 (T3 Waits). This binary field defines up toseven T3 wait states to be inserted in transactions accessing the mid-range memory area 3 in chip select scheme 1.
The contents of this register have no effects in chip selectscheme 2.

MMWR2: 0000000CH
R/W
7

MMWR3: 0000000DH
R/W
7

0

T1W2 T1W1 T1W0 T2W1 T2W0 T3W2 T3W1 T3W0
1

1

1

1

1

1

1

1

0

T1W2 T1W1 T1W0 T2W1 T2W0 T3W2 T3W1 T3W0<- Reset Value

1

1

1

1

1

1

1

1

<- Reset Value

T3 Waits

T3 Waits

T2 Waits

T2 Waits

T1 Waits

T1 Waits

Figure 44. Mid-Range Memory Waits Register 2

Figure 45. Mid-range Memory Waits Register 3

Page 103 of 125

Memory Selects Master Enable Register

Memory Chip Selects and Waits Master
ControlA user can set or reset the desired bits 7-4 in this register
without modifying the states of the remaining bits, with the
SR bit defining the set or reset function.

The memory chip selects and their associated waits areenabled or disabled by writing to a single register described in the following:
MSMER: 00000010H
R/W
7

0

ENLM ENUM ENM1 ENM2
1

1

0

0

--

--

--

SR

0

0

0

0

<- Reset Value
Set Reset Control
Reserved
Enable Mid-range Memory Chip
Select Scheme 2 and Waits
Enable Mid-range Memory Chip
Select Scheme 1 and Waits
Enable Upper Memory Chip
Select and Waits
Enable Lower Memory Chip
Select and Waits

Figure 46. Memory Selects Master Enable Register

ENLM (Enable Lower Memory Chip Select and Waits). Thisbit at logic 1 enables the /LMCS signal to go active startingat T1 cycle time of a memory transaction accessing thelower memory area. The associated programmed waitstates are automatically inserted in the transaction.
ENUM (Enable Upper Memory Chip Select and Waits).
This bit at logic 1 enables the /UMCS signal to go active
starting at T1 cycle time of a memory transaction accessing the upper memory area. The associated programmed
wait states are automatically inserted in the transaction.
ENM1 (Enable Mid-range Memory Chip Select Scheme 1
and Waits). This bit at logic 1 enables one of /MCS3/MCS0 to go active starting at T1 cycle time of a memorytransaction, depending on which of the mid-range memoryareas 3-0 is being accessed. The corresponding programmed wait states are automatically inserted in thetransaction.
ENM2 (Enable Mid-range Memory Chip Select Scheme 2
and Waits). This bit at logic 1 enables the /MCS0 to go
active starting at T1 cycle time of a memory transactionaccessing the mid-range memory area. The corresponding programmed wait states are automatically inserted in
the transaction.
Reserved bits 3-1. Read as 0s, should write to as 0s.

SR (Set Reset Control). When writing to the Memory
Selects Master Enable Register with SR = 1, bits 7-4
that are selected with logic 1s are set. When writing with
SR = 0, bits 7-4 that are selected with logic 1s are cleared.
In either case, the bits not selected are not modified. The
SR bit is always read as a logic 0.
Additional Comments. In either chip select scheme, if thechip select and waits functions are enabled, or theirmemory areas are defined to cause overlaps, the precedence of conflict resolution is /LMCS, then /UMCS, then
/MCS3-/MCS0. As an example, consider the case where
both the lower and mid-range memory area 0 are defined
to occupy the same address space. With ENLM = 1 in
the Memory Selects Master Enable Register (ENM1 canbe either 0 or 1), /LMCS goes active in the memorytransaction that accesses the overlapped address space.
With ENLM = 0 and ENM1 = 1, /MCS0 would go active inthe transaction instead. Regardless of the state of
the address bus, the chip select signals are at their inactive logic 1s when the corresponding enable bits in the
Memory Selects Master Enable Register (MSMER) are at
logic 0s, except during DRAM refresh transactions if soenabled, or the Z380 MPUs CPU is in its halt state, except
during DRAM refresh transactions if so enabled, or the
Z380 MPU relinquishes the system bus with its /BREQ
input active, or the Z380 MPU is in the low power standby
mode.

Page 104 of 125

DRAM Refresh

Refresh Register 1

The Z380 MPU is capable of providing refresh transactions
to dynamic memories that have internal refresh address
counters. A user can select how often refresh requests
should be made to the Z80 MPU's External Interface Logic,
as well as the burst size (number of refresh transactions)for each request iteration. The External Interface Logic
grants these requests by performing refresh transactions
with CAS-before-RAS timing on the /TREFR, /TREFA and/TREFC bus control signals. In these transactions, /BHEN,/BLEN and the user specified chip select signal(s) are
driven active to facilitate refreshing all the DRAM modules
at the same time. A user can also specify the T1, T2 and T3
waits to be inserted. Note that the Z380 MPU cannot
provide refresh transactions when it relinquishes the system bus, with its /BREQ input active. In that situation, thenumber of missed refresh requests are accumulated in acounter, and when the Z80 MPU regains the system bus,
the missed refresh transactions will be performed.

MR7-MR0 (Missed Requests Count). This count increments by 1 when a refresh request is made, to a maximum
value of 255. Refresh requests over the maximum value
would be lost. When the Z380 MPU's External Interface
Logic completes each burst of refresh transactions, thecount decrements by 1. A user can read the count status,
and if necessary, take corrective actions such as adjusting
the burst size. When refresh function is disabled, this countis held at 0.

Refresh Register 0
RI7-RI0 (Request Interval). RI7-RI0 defines the interval
between refresh requests to the Z380 MPU's ExternalInterface Logic. A value n specified in this field denotes therequest interval to be (4 x n) BUSCLK periods. If RI7-RI0
are programmed as 0s, the request interval is 1024 BUSCLK
periods.

RFSHR1: 00000014H
R Only0

7
MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0
0

0

0

0

0

0

0

0

<- Reset Value
Missed Requests
Count

Figure 48. Refresh Register 1

RFSHR0: 00000013H
R/W
0

7
RI7

RI6

RI5

RI4

RI3

RI2

RI1

RI0

0

0

0

0

0

0

0

0

<- Reset Value
Request Interval

Figure 47. Refresh Register 0

Page 105 of 125

Refresh Register 2

Refresh Wait Register

RFEN (Refresh Enable). Enables the refresh function when
programmed to logic 1.

T1W2-T1W0 (T1 Waits). This binary field defines up toseven T1 wait states to be inserted in refresh transactions.

Reserved bit 6. Read as 0, should write to as 0.

T1W1-T2W0 (T2 Waits). This binary field defines up to
three T2 wait states to be inserted in refresh transactions.

BS5-BS0 (Burst Size). This field defines the number ofrefresh transactions per refresh request made to the Z380
MPU's External Interface Logic. The burst size ranges from
1 to 64, with the highest size specified with BS5-BS0 equal
to 0s.
RFSHR2: 00000015H
R/W
0

7
RFEN

--

BS5

BS4

BS3

BS2

BS1

BS0

0

0

0

0

0

0

0

0

T3W2-T3W0 (T3 Waits). This binary field defines up toseven T3 wait states to be inserted in refresh transactions.
Note that care should be exercised in defining refresh
burst size and request intervals to avoid over-burdening
the system bus with refresh transactions. The memory chip
select signals can be selectively enabled to go active
during refresh transactions, such enabling is described in
the Memory Chip Selects and Waits section.

Burst Size

RFWR: 0000000FH
R/W
7Reserved

T1W2 T1W1 T1W0 T2W1 T2W0 T3W2 T3W1 T3W0<- Reset Value0

Refresh Enable

1

Figure 49. Refresh Register 2

1

1

1

1

1

1

1

<- Reset Value
T3 Waits
T2 Waits
T1 Waits

Figure 50. Refresh Waits Register

Page 106 of 125

LOW POWER STANDBY MODE
The Z380 MPU provides an optional standby mode tominimize power consumption during system idle time. If
this option is enabled, executing the Sleep instruction
would stop clocking internal to the Z380 MPU, as well as at
the BUSCLK and IOCLK outputs. The /STNBY signal goesto active logic 0, indicating the Z380 MPU is entering thestandby mode. All Z380 MPU operations are suspended,
the bus control signals are driven inactive and the address
bus is driven to logic 1s. Note that if an external crystal
oscillator is used to drive the Z380 MPU’s CLKI input,/STNBY can be used to stop its operation. This is a means

to further reduce power dissipation for the overall system.
The standby mode can be exited by asserting any of the/RESET, /NMI, /INT3-/INT0 (if enabled), or optionally,/BREQ inputs.
If the standby mode option is not enabled, the Sleep
instruction is interpreted and executed no different thanthe HALT instruction, stopping the Z30 MPU from further
instruction execution. In this case, /HALT goes to active
logic 0 to indicate the Z380 MPU's halt status.

Standby Mode Control and Entering
STBY (Enable Standby Mode Option). Enables the Z380
MPU to go into low power standby mode when the Sleep
instruction is executed.

WM2-WM0 (Warm-up Time Selection). WM2-WM0 determines the approximate running duration of a warm-up
counter that provides a delay before the Z380 MPU
resumes its clocking and operations, from the time aninterrupt or bus request (if so enabled) is asserted to exit
standby mode. In a system where an external crystal
oscillator is used to drive the Z380 MPU’s CLK input, an
appropriate warm-up time can be selected for the oscillator to stabilize.

BRXT (Bus Request to Exit Standby Mode). If BRXT is at
logic 1, standby mode can be exited by asserting /BREQ.
Reserved Bits 5-3. Read as 0s, should write to as 0s.

SMCR: 00000016H
R/W
70
STBY BRXT
0

0

0

0

0

WM2

WM1

WM0

0

0

0

Reset Value
Warmup Time Selection
No Warmup

0
0
0
1

0
0
1
0

0
1
0
0

2 16 BUSCLK Cycles
2 17 BUSCLK Cycles
2 19 BUSCLK Cycles
Reserved
Program as 0s
Read as 0s
Bus Request to Exit Standby Mode
Enable Standby Mode Option

Figure 51. Standby Mode Control Register

Page 107 of 125

Standby Mode Exit With Bus Request
Optionally, if the BRXT bit of the Standby Mode Control
Register (SMCR) was previously set, /STNBY goes to logic
1 when the /BREQ input is asserted, allowing the external
crystal oscillator that drives the Z380 MPU’s CLK input torestart. A warm-up counter internal to the Z380 MPU
proceeds to count, for a duration long enough for theoscillator to stabilize, which was selected with the WM bitsin the SMCR. When the counter reaches its end-count,clocking resumes within the Z380 MPU and at the BUSCLK
and IOCLK outputs.

The Z380 MPU relinquishes the system bus after clocking
resumes, with the normal /BREQ, /BACK handshake procedure. The Z380 MPU regains the system bus when
/BREQ goes inactive, again going through a normal handshake procedure.
Note that clocking continues, and the Z380 MPU is at thehalt state.

Halt
State

Bus Release
BUSCLKIOCLK/STNBY

/BREQ

/BACK

ADDRESSFFFFFFFFH

DATA
BUS
CNTLS

Figure 52. Standby Mode Exit with Bus Request Timing

Page 108 of 125

Standby Mode Entering Timing
Figure 53 shows standby mode entering timing in an
example where IOCLK was programmed to be BUSCLK

divided-by-2. Note that clocking stops only after IOCLK
has changed to logic 0.

BUSCLKIOCLK/STNBYADDRESSFFFFFFFFH

DATA

BUS
CNTLS

(/TREFR, /TREFA, /TREFC,/MRD, /MWR, /BHEN,/BLEN, /IOCTL3-0)

Figure 53. Standby Mode Entering Timing

Standby Mode Exit With Reset
When /RESET is asserted, /STNBY goes to logic 1, allowing
the external crystal oscillator that drives the Z380 MPU’s
CLKI input to restart. The /RESET pulse provided should
be of a duration long enough for oscillator stabilization. The
Z380 MPU exits standby mode, and when /RESET isdeasserted, it goes through the normal reset timing to start
instruction execution at address 00000000H. Note thatclocking resumes within the Z380 MPU and at the BUSCLK
and IOCLK outputs soon after /RESET is asserted, when
the crystal oscillator is not yet stabilized.
OPCODE
FETCH

BUSCLKIOCLK/STNBY/RESET

ADDRESSFFFFFFFFH

000000H

DATA

Figure 54. Standby Mode Exit with Reset Timing

Page 109 of 125

Standby Mode Exit With External Interrupts
Standby mode can be exited by asserting input /NMI.
Asserting the maskable interrupt inputs /INT3-/INT0 may
also exit standby mode, if the global interrupt flag IEF1 waspreviously enabled at logic 1, and for those requests
individually enabled, as indicated in the Interrupt Enable
Register.

The Z380 MPU’s internal warm-up counter proceeds tocount, for a duration long enough for the oscillator tostabilize, as selected by the WM bits in the Standby ModeControl Register. When the counter reaches its end-count,clocking resumes within the Z380 MPU, as well as at the
BUSCLK and IOCLK outputs. The Z380 MPU performs aninterrupt acknowledge procedure appropriate to the interrupt request that initiated the standby mode exit.

When exit conditions are met, /STNBY goes to logic 1,
allowing the external crystal oscillator that drives the Z380
MPU’s CLK input to restart.
Appropriate
Acknowledge
BUSCLKIOCLK/STNBY/NMI/INT3,2,1,0

ADDRESSFFFFFFFFH

Figure 55. Standby Mode Exit with External Interrupts Timing

Page 110 of 125

Standby Mode for On-chip Crystal
Oscillator
The previous discussions have been focused on situations
where a direct clock is supplied to the Z380 MPU's CLKI
input. Such a clock may be sourced by an external crystal
with its oscillation circuit. In the case where a crystal isconnected to the Z380 MPU's on-chip oscillator, all standby
functions described earlier apply. Items worth noting are
as follows.

1. When standby mode is entered, the feedback path forthe on-chip oscillator is disabled, reducing power consumption.
2. A user can select a warm-up time appropriate for the
crystal being used, by programming the WM2-WM0
bits in the Standby Mode Control Register (SMCR).

Table 6. Z380 MPU On-chip I/O Registers
RegisterMnemonic

On-Chip I/O Address

Lower Memory Chip Select Register 0
Lower Memory Chip Select Register 1
Upper Memory Chip Select Register 0Upper Memory Chip Select Register 1
Midrange Memory Chip Select Register 0
Midrange Memory Chip Select Register 1
Midrange Memory Chip Select Register 2
Midrange Memory Chip Select Register 3

LMCS0
LMCS1
UMCS0
UMCS1
MMCS0
MMCS1
MMCS2
MMCS3

00000000H
00000001H
00000002H
00000003H
00000004H
00000005H
00000006H
00000007H

Lower Memory Waits Register
Upper Memory Waits Register
Midrange Memory Waits Register 0
Midrange Memory Waits Register 1
Midrange Memory Waits Register 2
Midrange Memory Waits Register 3
I/O Waits Register
Refresh Waits Register

LMWR
UMWR
MMWR0
MMWR1
MMWR2
MMWR3
IOWR
RFWR

00000008H
00000009H
0000000AH
0000000BH
0000000CH
0000000DH
0000000EH
0000000FH

Memory Selects Master Enable Register
I/O Bus Control Register 0
I/O Bus Control Register 1
Refresh Register 0
Refresh Register 1
Refresh Register 2Standby Mode Control Register
Interrupt Enable Register

MSMER
IOCR0
IOCR1
RFSHR 0RFSHR1RFSHR2SMCR
IER

00000010H
00000011H
00000012H
00000013H
00000014H
00000015H
00000016H
00000017H

Assigned Vectors Base Register
Trap and Break Register

AVBR
TRPBK

00000018H
00000019H

Page 111 of 125

RESETThe Z380 MPU is placed in a dormant state when the/RESET input is asserted. All its operations are terminated,
including any interrupt, bus request or bus transaction that
may be in progress. Its IOCLK goes Low on the next
BUSCLK rising edge, and enters into the BUSCLK divideddown-by-eight mode. The address and data buses are tristated, and the bus control signals are driven to theirinactive states. The effect of a reset on the Z380 CPU andrelated I/O registers is depicted in Table 6, and the effecton the on-chip peripheral functions is summarized inTable 8.
The /RESET input may be asynchronous to BUSCLK,
though it is sampled internally at BUSCLK’s falling edges.
For proper initialization of the Z380 MPU, VDD must bewithin operating specification and its BUSCLK must be
stable for more than five cycles with /RESET held Low. The/RESET input has a built-in Schmitt trigger buffer to facilitate power-on reset generation through an RC network.

Note that if a user system has devices external to the Z380
MPU that are clocked by IOCLK, these devices may
require a /RESET pulse width that spans over a number of
IOCLK cycles (now at BUSCLK/8) for proper initialization.
The Z380 MPU proceeds to fetch its first instruction 3.5
BUSCLK cycles after /RESET is deasserted, provided
such deassertion meets the proper setup and hold times
with reference to the falling edge of BUSCLK, as depicted
in Figure 20 in the External Interface Section. Figure 19 in
the same section indicates a synchronization of IOCLK
when /RESET is deasserted. Again with the proper setup
and hold times being met, IOCLK’s first rising edge is 11.5
BUSCLK cycles after the /RESET deassertion, precededby a minimum of 4 BUSCLK cycles where IOCLK is at Low.
Note that if /BREQ is active when /RESET is deasserted, theZ380 MPU would relinquish the bus instead of fetching its
first instruction. IOCLK synchronization would still takeplace as described before.

Page 112 of 125

Table 7. Effect of a Reset on Z380 CPU and Related I/O Registers
Register

Reset Value

Comments

Program Counter

00000000

PCz, PC

Stack Pointer00000000

SPz, SP

I
R

00000000

Iz, I

Select Register

00000000

Register Bank 0 Selected:
AF, Main Bank, IX, IY
Native Mode
Maskable Interrupts Disabled, in Mode 0
Bus Request Lock-Off

A and F Registers

Register Banks 3-0:
A, F, A’, F’ Unaffected

Register Extensions

0000

Register Bank 0:BCz, DEz, HLz, IYz,
BCz’, DEz’, HLz’, IYz’
(All “non-extended” portions unaffected.)
Register Bank 3-1 Unaffected.

I/O Bus Control Register 000

IOCLK = BUSCLK/8

Interrupt Enable Register01/INT0 Enabled

Assigned Vector Base Register00

Trap and Break Register00

Table 8. Effect of a Reset on On-chip Peripheral Functions
Peripheral Functions

Reset Conditions

Memory Chip Selects and Waits

Lower Memory Chip Select Signal enabled for lowest 1 MBytes(00000000H-000FFFFFH), with 7 T1, 3 T2, and 7 T3 waits.
Upper Memory Chip Select Signal enabled for highest
16th MBytes (00F00000H - 00FFFFFFH),
with 7 T1, 3 T2, and 7 T3 waits.
Midrange Memory Chip Select Signal and waits disabled.

I/O Waits

External I/O read, write -- 7 waits.
RETI -- 3 waits.
Interrupt daisy chain -- 7 waits.

DRAM Refresh Controller

Disabled

Standby Mode

Disabled

Page 113 of 125

ABSOLUTE MAXIMUM RATINGS
Voltage on VDD with respect to VSS .......... –0.3V to +7.0V
Voltage on all pins,with respect to VSS .................... –0.3V to (VDD + 0.3)V
Operating Ambient Temperature: .................. 0 to +70°C
Storage Temperature: ........................... –55°C to +150°C

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at
any condition above those indicated in the operational
sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods
may affect device reliability.

STANDARD TEST CONDITIONSThe AC and DC Characteristics sections below apply forthe following standard test conditions, unless otherwise
noted. All voltages are referenced to VSS (0V). Positive
current flows into the referenced pin.

Standard conditions are as follows:
4.75V < VDD < 5.25V
Low Voltage 3.15 <3.3 <3.45
VSS = 0V
Standard test load on all outputs.

DC CHARACTERISTICS
Z380™ Version
SymbolParameter

Min

Max

Unit

Note

VIH
VIL
VOH1
VOH2
VOL

Input High Voltage
Input Low Voltage
Output High Voltage (-4 mA IOH)
Output High Voltage (-250 µA IOH)
Output Low Voltage (4 mA IOL)

3.0
-0.3
2.4
VDD – 0.8 V–

VDD + 0.3
0.8
–
–
0.5

V
V
V
V
V

IIL
ITL
IDD1
IDD3

Input Leakage Current
Tri-State Leakage Current
Power Supply Current (@ 18 MHz)
Standby Power Supply Current

-10
-10

10
10
TBS
TBS

µA
µA
mA
µA

1
2
3
4

CIN
COUT
CIO
CL
CLD

Input Capacitance (f =1 MHz)
Output Capacitance (f =1 MHz)I/O Capacitance (f =1 MHz)
Output Load CapacitanceAC Output Derating (Above 100 pF)

15
15
15
100
50

pF
pF
pF
pF
pS/pF

5
5
5

Notes:
1. 0.4 V < VIN < 2.4 V
2. 0.4 V < VOUT < 2.4 V
3. VDD = 5.0 V, VIH = 4.8 V, VIL = 0.2 V
4. VDD = 5.0 V, VIH = 4.8 V, VIL = 0.2 V
5. Unmeasured pins returned to VSS.

Page 114 of 125

AC CHARACTERISTICS
Z380™ Version
Z8038018
No.

SymbolParameter

Min

Max

Note

1
2
3
4
5

TcC
TwCh
TwCl
TrC
TfC

CLK Cycle Time
CLK Width HighCLK Width Low
CLK Rise Time
CLK Fall Time

55
24.5
24.5

6
7
8
9
10
11

TdCf(BCr)
TdCr(BCf)
TdBCr(OUT)
TdBCf(OUT)
TsIN(BCr)ThIN(BCr)

CLK Fall to BUSCLK Rise Delay
CLK Rise to BUSCLK Fall Delay
BUSCLK Rise to Output Valid Delay
BUSCLK Fall to Output Valid Delay
Input to BUSCLK Rise Setup Time
Input to BUSCLK Rise Hold Time

16
0

1
1

12
13
14
15
16
17

TsBR(BCf)
ThBR(BCf)
TsMW(BCr)
ThMW(BCr)
TsMW(BCf)
ThMW(BCf)/BREQ to BUSCLK Fall Setup Time
/BREQ to BUSCLK Fall Hold TimeMem Wait to BUSCLK Rise Setup TimeMem Wait to BUSCLK Rise Hold TimeMem Wait to BUSCLK Fall Setup TimeMem Wait to BUSCLK Fall Hold Time

16
0
16
0
24
0

2
2
3
3
3
3

18
19
20
21

TsIOW(BCr)ThIOW(BCr)TsIOW(BCf)ThIOW(BCf)

IO Wait to BUSCLK Rise Setup TimeIO Wait to BUSCLK Rise Hold TimeIO Wait to BUSCLK Fall Setup TimeIO Wait to BUSCLK Fall Hold Time

24
0
24
0

3
3
3
3

22
23
24
25

TwNMI1TwRES1
Tx01(02)
Tx01(03)/NMI Low Width
Reset Low Width
Output Skew (Same Clock Edge)
Output Skew (Opposite Clock Edge)

25
10
–2
–3

3
3
30
27
6.5
6.5

+2
+3

4
5

Notes:
1. Applicable for Data Bus and /MSIZE inputs
2. /BREQ can also be asserted/deasserted asynchronously
3. External waits asserted at /WAIT input
4. Tx01(02)=[Output 1] TdBCr(OUT) - [Output 2] TdBCr(OUT)
or [Output 1] TdBCf(OUT) - [Output 2] TdBCf(OUT)
5. Tx01(03)=[Output 1] TdBCr(OUT) - [Output 3] TdBCf(OUT)
or [Output 1] TdBCf(OUT) - [Output 3] TdBCr(OUT)

Page 115 of 125

DC CHARACTERISTICS
Low Voltage Z380™ Version
SymbolParameter

Min

Max

Unit

Note

VIH
VIL
VOH1
VOL

Input High Voltage
Input Low Voltage
Output High Voltage (–200 µA IOH)
Output Low Voltage (1.6 mA IOL)

2.0
–0.5
2.15
-

VDD + 0.5
0.8
0.4

V
V
V
V

IIL
ITL
IDD1
IDD3

Input Leakage Current
Tri-State Leakage Current
Power Supply Current (@ 10 MHz)
Standby Power Supply Current

–10
–10

10
10
TBS
20

µA
µA
mA
µA

1
2
3
4

CIN
COUT
CIO
CL
CLD

Input Capacitance (f =1 MHz)
Output Capacitance (f =1 MHz)I/O Capacitance (f =1 MHz)
Output Load CapacitanceAC Output Derating (Above 100 pF)

15
15
15
100
250

pF
pF
pF
pF
pS/pF

5
5
5

Notes:
1. VIN = 0.4 V
2. 0.4 V < VOUT < 2.15 V
3. VDD = 3.3 V, VIH = 3.0 V, VIL = 0.2 V
4. VDD = 3.3 V, VIH = 3.0 V, VIL = 0.2 V
5. Unmeasured pins returned to VSS.

Page 116 of 125

AC CHARACTERISTICS
Low Voltage Z380™
Z8L38010
Max

No.

SymbolParameter

Min

Note

1
2
3
4
5

TcC
TwCh
TwCl
TrC
TfC

CLK Cycle Time
CLK Width HighCLK Width Low
CLK Rise Time
CLK Fall Time

100
40
40

6
7
8
9
10
11

TdCf(BCr)
TdCr(BCf)
TdBCr(OUT)
TdBCf(OUT)
TsIN(BCr)ThIN(BCr)

CLK Fall to BUSCLK Rise Delay
CLK Rise to BUSCLK Fall Delay
BUSCLK Rise to Output Valid Delay
BUSCLK Fall to Output Valid Delay
Input to BUSCLK Rise Setup Time
Input to BUSCLK Rise Hold Time

30
0

1
1

12
13
14
15
16
17

TsBR(BCf)
ThBR(BCf)
TsMW(BCr)
ThMW(BCr)
TsMW(BCf)
ThMW(BCf)/BREQ to BUSCLK Fall Setup Time
/BREQ to BUSCLK Fall Hold TimeMem Wait to BUSCLK Rise Setup TimeMem Wait to BUSCLK Rise Hold TimeMem Wait to BUSCLK Fall Setup TimeMem Wait to BUSCLK Fall Hold Time

30
0
30
0
45
0

2
2
3
3
3
3

18
19
20
21

TsIOW(BCr)ThIOW(BCr)TsIOW(BCf)ThIOW(BCf)

IO Wait to BUSCLK Rise Setup TimeIO Wait to BUSCLK Rise Hold TimeIO Wait to BUSCLK Fall Setup TimeIO Wait to BUSCLK Fall Hold Time

45
0
45
0

3
3
3
3

22
23
24
25

TwNMI1TwRES1
Tx01(02)
Tx01(03)/NMI Low Width
Reset Low Width
Output Skew (Same Clock Edge)
Output Skew (Opposite Clock Edge)

50
10
–4
–6

5
5
60
55
15
15

+4
+6

4
5

Notes:
1. Applicable for Data Bus and /MSIZE inputs
2. /BREQ can also be asserted/deasserted asynchronously
3. External waits asserted at /WAIT input
4. Tx01(02)=[Output 1] TdBCr(OUT) - [Output 2] TdBCr(OUT)
or [Output 1] TdBCf(OUT) - [Output 2] TdBCf(OUT)
5. Tx01(03)=[Output 1] TdBCr(OUT) - [Output 3] TdBCf(OUT)
or [Output 1] TdBCf(OUT) - [Output 3] TdBCr(OUT)

Page 117 of 125

AC CHARACTERISTICS (Continued)

1
3

2

CLK
5

4

BUSCLK
6

7

OUTPUT
8
OUTPUT
9
INPUT
10 14 18

11 15 19

INPUT
12 16 20

13 17 21/NMI
22
/RESET
23

Figure 56. Z380™ CPU Timing

Page 118 of 125

APPENDIX A

00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30

no escED escDD escFD escCB esc

ED-CB

DD-CB

FD-CB

NOP
LD BC,nn
LD (BC),AINC BC **
INC B
DEC B
LD B,nRLCA
EX AF,AF’
ADD HL,BC **LD A,(BC)DEC BC **
INC C
DEC C
LD C,nRRCA
DJNZ eLD DE,nn
LD (DE),AINC DE **
INC D
DEC D
LD D,nRLA
JR e
ADD HL,DE **LD A,(DE)DEC DE **
INC E
DEC E
LD E,nRRA
JR NZ,eLD HL,nn
LD (nn),HL
INC HL **
INC H
DEC H
LD H,nDAA
JR Z,eADD HL,HL **LD HL,(nn)DEC HL **
INC L
DEC L
LD L,nCPLJR NC,eIN0 B,(n)OUT0 (n),BLD BC,BCEX BC,IX
TST B
EX BC,DELD (BC),nn
EX A,BIN0 C,(n)OUT0 (n),CEX BC,IY
TST C
EX BC,HL
SWAP BC
EX A,CIN0 D,(n)OUT0 (n),DLD DE,BC
EX DE,IX
TST D
LD (DE),nn
EX A,DIN0 E,(n)OUT0 (n),E
EX DE,IY
TST E
SWAP DEEX A,E
IN0 H,(n)OUT0 (n),H
TST H
EX A,H
IN0 L,(n)OUT0 (n),LEX IX,IY
TST L
EX A,LIN0 (n)LD (BC),IXLD BC,DELD IX,(BC)LD IX,BCADD IX,BC **LD BC,IXLD BC,(BC)LD BC,(DE)LD BC,(HL)
DJNZ eeLD (DE),IX
LD DE,DELD IX,(DE)LD IX,DEJR ee
ADD IX,DE **LD DE,IXLD DE,(BC)LD DE,(DE)LD DE,(HL)JR NZ,eeLD IX,nn
LD (nn),IX
INC IX **INC IXUDEC IXULD IXU,nLD IX,IY
JR Z,eeADD IX,IX **LD IX,(nn)DEC IX **INC IXLDEC IXLLD IXL,nCPLW
JR NC,eeLD (BC),IY
LD BC,HLLD IY,(BC)LD IY,BCADD IY,BC **LD BC,IY
LD (BC),BCLD (DE),BCLD (HL),BC
DJNZ eee
LD (DE),IY
LD DE,HLLD IY,(DE)LD IY,DE
JR eeeADD IY,DE **LD DE,IY
LD (BC),DELD (DE),DELD (HL),DE
JR NZ,eee
LD IY,nn
LD (nn),IY
INC IY **INC IYUDEC IYULD IYU,nLD IY,IX
JR Z,eee
ADD IY,IY **LD IY,(nn)DEC IY **INC IYLDEC IYLLD IYL,n
JR NC,eee

RLC B
RLC C
RLC D
RLC E
RLC H
RLC L
RLC (HL)
RLC A
RRC B
RRC C
RRC D
RRC E
RRC H
RRC L
RRC (HL)
RRC A
RL B
RL C
RL D
RL E
RL H
RL L
RL (HL)
RL A
RR B
RR C
RR D
RR E
RR H
RR L
RR (HL)
RR A
SLA B
SLA C
SLA D
SLA E
SLA H
SLA L
SLA (HL)
SLA A
SRA B
SRA C
SRA D
SRA E
SRA H
SRA L
SRA (HL)
SRA A
EX B,B’RLCW BCRLCW DE
RLCW (HL)
RLCW HLRLCW IXRLCW IY
RRCW BCRRCW DE
RRCW (HL)
RRCW HLRRCW IXRRCW IY
RLW BCRLW DERLW (HL)RLW HLRLW IXRLW IYRRW BCRRW DERRW (HL)RRW HLRRW IXRRW IYSLAW BCSLAW DESLAW (HL)
SLAW HLSLAW IXSLAW IYSRAW BCSRAW DESRAW (HL)
SRAW HLSRAW IXSRAW IY
EX BC,BC’

LDBC,(SP+d)RLCW (IX+d)LD BC,(IX+d)RLC (IX+d)LD (SP+d),BCRRCW (IX+d)LD (IX+d),BCRRC (IX+d)LD DE,(SP+d)RLW (IX+d)LD DE,(IX+d)RL (IX+d)LD (SP+d),DE
RRW (IX+d)LD (IX+d),DE
RR (IX+d)LD IX,(SP+d)SLAW (IX+d)LD IY,(IX+d)SLA (IX+d)LD (SP+d),IX
SRAW (IX+d)LD (IX+d),IY
SRA (IX+d)-RLCW (IY+d)LDBC,(IY+d)
RLC (IY+d)
RRCW (IY+d)LD (IY+d),BCRRC (IY+d)
RLW (IY+d)LD DE,(IY+d)
RL (IY+d)RRW (IY+d)LD (IY+d),DE
RR (IY+d)LD IY,(SP+d)SLAW (IY+d)LD IX,(IY+d)SLA (IY+d)LD (SP+d),IY
SRAW (IY+d)LD (IY+d),IX
SRA (IY+d)-Page 119 of 125

APPENDIX A (Continued)

31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65

no escED escDD escFD escCB esc

ED-CB

DD-CB

FD-CB

LD SP,nn
LD (nn),AINC SP **INC (HL)
DEC (HL)
LD (HL),nSCF
JR C,eADD HL,SP **LD A,(nn)
DEC SP **
INC A
DEC A
LD A,nCCF
LD B,BLD B,CLD B,DLD B,ELD B,HLD B,LLD B,(HL)LD B,ALD C,BLD C,CLD C,D
LD C,ELD C,HLD C,LLD C,(HL)LD C,ALD D,BLD D,CLD D,D
LD D,E
LD D,HLD D,LLD D,(HL)
LD D,ALD E,BLD E,CLD E,DLD E,ELD E,HLD E,LLD E,(HL)LD E,ALD H,BLD H,CLD H,DLD H,ELD H,HLD H,LLD HL,BCEX HL,IX
TST (HL)
LD (HL),nn
EX A,(HL)
IN0 A,(n)OUT0 (n),AEX HL,IY
TST A
SWAP HL
EX A,AIN B,(C)OUT (C),B
SBC HL,BC
LD (nn),BC
NEG
RETN
IM 0
LD I,AIN C,(C)OUT (C),CADC HL,BC
LD BC,(nn)MLT BCRETI
IM 3LD R,AIN D,(C)OUT (C),DSBC HL,DE
LD (nn),DE
NEGW
RETB
IM 1
LD A,I
IN E,(C)OUT (C),E
ADC HL,DE
LD DE,(nn)MLT DEIM 2
LD A,R
IN H,(C)OUT (C),H
SBC HL,HL
LD (nn),HL
TST m
EXTS

LD (HL),IX
LD HL,DELD IX,(HL)
INC (IX+d)DEC (IX+d)LD (IX+d),nLD IX,HL
JR C,eeADD IX,SP **LD HL,IXLD HL,(BC)LD HL,(DE)SWAP IXLD HL,(HL)
INW BC,(C)OUTW (C),BCLD B,IXULD B,IXLLD B,(IX+d)LD I,HL
LD C,IXULD C,IXLLD C,(IX+d)INW DE,(C)OUTW (C),DELD D,IXULD D,IXLLD D,(IX+d)LD HL,ILD E,IXULD E,IXLLD E,(IX+d)LD IXU,BLD IXU,CLD IXU,DLD IXU,E
LD IXU,IXULD IXU,IXLLD (HL),IY
LD HL,HLLD IY,(HL)
INC (IY+d)
DEC (IY+d)LD (IY+d),nLD IY,HL
JR C,eee
ADD IY,SP **LD HL,IY
LD (BC),HLLD (DE),HL
SWAP IYLD (HL),HL
LD B,IYULD B,IYLLD B,(IY+d)
LD C,IYULD C,IYLLD C,(IY+d)
LD D,IYU
LD D,IYL
LD D,(IY+d)
LD E,IYULD E,IYL
LD E,(IY+d)LD IYU,BLD IYU,CLD IYU,DLD IYU,E
LD IYU,IYULD IYU,IYL

EX C,C’
EX D,D’
EX E,E’
EX H,H’
EX L,L’
EX A,A’
SRL B
SRL C
SRL D
SRL E
SRL H
SRL L
SRL (HL)
SRL A
BIT 0,B
BIT 0,C
BIT 0,DBIT 0,E
BIT 0,H
BIT 0,L
BIT 0,(HL)
BIT 0,A
BIT 1,B
BIT 1,C
BIT 1,D
BIT 1,E
BIT 1,H
BIT 1,L
BIT 1,(HL)
BIT 1,A
BIT 2,B
BIT 2,C
BIT 2,DBIT 2,E
BIT 2,H
BIT 2,L
BIT 2,(HL)
BIT 2,A
BIT 3,B
BIT 3,C
BIT 3,DBIT 3,E
BIT 3,H
BIT 3,L
BIT 3,(HL)
BIT 3,A
BIT 4,B
BIT 4,C
BIT 4,DBIT 4,E
BIT 4,H
BIT 4,L

EX DE,DE’EX HL,HL’
EX IX,IX’EX IY,IY’
SRLW BCSRLW DE
SRLW (HL)
SRLW HLSRLW IXSRLW IY-LD HL,(SP+d)LD HL,(IX+d)LD (SP+d),HLSLRW (IX+d)LD (IX+d),HL
SRL (IX+d)
BIT 0,(IX+d)BIT 1,(IX+d)
BIT 2,(IX+d)BIT 3,(IX+d)-LD HL,(IY+d)
SRLW (IY+d)LD (IY+d),HL
SRL (IY+d)
BIT 0,(IY+d)
BIT 1,(IY+d)
BIT 2,(IY+d)
BIT 3,(IY+d)-Page 120 of 125

66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97

no escED escDD escFD escCB esc

ED-CB

DD-CB

FD-CB

LD H,(HL)LD H,A
LD L,B
LD L,CLD L,D
LD L,E
LD L,H
LD L,LLD L,(HL)LD L,A
LD (HL),B
LD (HL),CLD (HL),DLD (HL),E
LD (HL),H
LD (HL),LHALT
LD (HL),A
LD A,BLD A,CLD A,D
LD A,ELD A,HLD A,LLD A,(HL)LD A,AADD A,BADD A,CADD A,DADD A,EADD A,HADD A,LADD A,(HL)ADD A,AADC A,BADC A,CADC A,DADC A,E
ADC A,HADC A,LADC A,(HL)ADC A,A
SUB B
SUB C
SUB D
SUB E
SUB H
SUB L
SUB (HL)SUB A

RRD
IN L,(C)OUT (C),LADC HL,HLLD HL,(nn)MLT HLRLD
OUT (C),n
SBC HL,SPLD (nn),SPTSTIO mEXTSW
SLP
IN A,(C)OUT (C),AADC HL,SPLD SP,(nn)MLT SPADD SP,nn **OTIM
ADDW BCADDW DEADDW nn
ADDW HLOTDMADCW BCADCW DE
ADCW nn
ADCW HLSUB SP,nn **OTIMRSUBW BCSUBW DE
SUBW nn
SUBW HLLD H,(IX+d)LD IXU,ALD IXL,B
LD IXL,CLD IXL,D
LD IXL,E
LD IXL,IXULD IXL,IXL
LD L,(IX+d)LD IXL,A
LD (IX+d),B
LD (IX+d),C
LD (IX+d),D
LD (IX+d),E
LD (IX+d),H
LD (IX+d),LLD (IX+d),AINW HL,(C)OUTW (C),HL
LD A,IXULD A,IXLLD A,(IX+d)ADD IXUADD IXLADD A,(IX+d)ADDW IX
ADC A,IXU
ADC A,IXLADC A,(IX+d)
ADCW IXSUB IXUSUB IXLSUB (IX+d)SUBW IXLD H,(IY+d)LD IYU,ALD IYL,B
LD IYL,CLD IYL,D
LD IYL,E
LD IYL,IYU
LD IYL,IYL
LD L,(IY+d)LD IYL,A
LD (IY+d),B
LD (IY+d),C
LD (IY+d),D
LD (IY+d),E
LD (IY+d),H
LD (IY+d),LLD (IY+d),A
OUTW (C),nn
LD A,IYULD A,IYLLD A,(IY+d)
ADD IYUADD IYLADD A,(IY+d)
ADDW IY
ADC A,IYU
ADC A,IYL
ADC A,(IY+d)
ADCW IYSUB IYUSUB IYLSUB (IY+d)
SUBW IY

BIT 4,(HL)
BIT 4,A
BIT 5,B
BIT 5,C
BIT 5,DBIT 5,E
BIT 5,H
BIT 5,L
BIT 5,(HL)
BIT 5,A
BIT 6,B
BIT 6,C
BIT 6,DBIT 6,E
BIT 6,H
BIT 6,LBIT 6,(HL)
BIT 6,A
BIT 7,B
BIT 7,C
BIT 7,DBIT 7,E
BIT 7,H
BIT 7,L
BIT 7,(HL)
BIT 7,ARES 0,BRES 0,CRES 0,DRES 0,E
RES 0,HRES 0,LRES 0,(HL)
RES 0,ARES 1,BRES 1,CRES 1,DRES 1,E
RES 1,HRES 1,LRES 1,(HL)
RES 1,ARES 2,BRES 2,CRES 2,DRES 2,ERES 2,HRES 2,LRES 2,(HL)RES 2,A

MULTW BCMULTW DE
MULTW HLMULTW IXMULTW IY
MULTW nn

BIT 4,(IX+d)BIT 5,(IX+d)BIT 6,(IX+d)BIT 7,(IX+d)
RES 0,(IX+d)RES 1,(IX+d)
MULTW (IX+d)RES 2,(IX+d)-

BIT 4,(IY+d)
BIT5,(IY+d)
BIT 6,(IY+d)
BIT 7,(IY+d)
RES 0,(IY+d)
RES 1,(IY+d)
MULTW (IY+d)RES 2,(IY+d)-Page 121 of 125

APPENDIX A (Continued)

98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9

no escED escDD escFD escCB esc

ED-CB

DD-CB

FD-CB

SBC A,BSBC A,CSBC A,DSBC A,E
SBC A,H
SBC A,LSBC A,(HL)
SBC A,A
AND B
AND C
AND D
AND E
AND H
AND L
AND (HL)
AND A
XOR B
XOR C
XOR D
XOR E
XOR H
XOR L
XOR (HL)
XOR A
OR B
OR C
OR D
OR E
OR H
OR L
OR (HL)
OR A
CP B
CP C
CP D
CP E
CP H
CP L
CP (HL)CP A
RET NZ
POP BCJP NZ,nn
JP nn
CALL NZ,nn
PUSH BCADD A,n
RST 0
RET Z
RET

OTDMR
SBCW BCSBCW DE
SBCW nn
SBCW HL
LDI
CPI
INI
OUTI
ANDW BC
ANDW DE
ANDW nn
ANDW HL
LDD
CPD
IND
OUTD
XORW BCXORW DE
XORW nn
XORW HL
LDIR
CPIR
INIR
OTIR
ORW BCORW DE
ORW nnORW HL
LDDR
CPDR
INDR
OTDR
CPW BCCPW DECPW nnCPW HLLDCTL HL,SR
POP SRCALR NZ,ePUSH SRADD HL,(nn) **LDCTL SR,HL-

SBC A,IXU
SBC A,IXL
SBC A,(IX+d)
SBCW IXAND IXU
AND IXLAND (IX+d)ANDW IXXOR IXUXOR IXLXOR (IX+d)
XORW IX
OR IXUOR IXLOR (IX+d)
ORW IXCP IXUCP IXLCP (IX+d)CPW IXDDIR W
DDIR IB,W
DDIR IW,W
DDIR IBCALR NZ,ee
ADDW (IX+d)LDCTL SR,A-

SBC A,IYU
SBC A,IYL
SBC A,(IY+d)
SBCW IY
AND IYUAND IYL
AND (IY+d)
ANDW IY
XOR IYUXOR IYLXOR (IY+d)
XORW IY
OR IYUOR IYLOR (IY+d)ORW IYCP IYUCP IYLCP (IY+d)CPW IYDDIR LW
DDIR IB,LW
DDIR IW,LW
DDIR IWCALR NZ,eee
ADDW (IY+d)-RES 3,BRES 3,CRES 3,DRES 3,ERES 3,HRES 3,LRES 3,(HL)RES 3,ARES 4,BRES 4,CRES 4,DRES 4,ERES 4,HRES 4,LRES 4,(HL)RES 4,ARES 5,BRES 5,CRES 5,DRES 5,ERES 5,HRES 5,LRES 5,(HL)RES 5,ARES A,BRES 6,CRES 6,DRES 6,ERES 6,HRES 6,LRES 6,(HL)RES 6,ARES 7,BRES 7,CRES 7,DRES 7,ERES 7,HRES 7,LRES 7,(HL)RES 7,ASET 0,B
SET 0,CSET 0,DSET 0,E
SET 0,H
SET 0,LSET 0,(HL)
SET 0,ASET 1,B
SET 1,C

MULTUW BCMULTUW DE
MULTUW HL
MULTUW IX
MULTUW IY
MULTUW nn
DIVUW BCDIVUW DEDIVUW HLDIVUW IXDIVUW IYDIVUW nn-

MULTUW (IX+d)RES 3,(IX+d)RES 4,(IX+d)RES 5,(IX+d)RES 6,(IX+d)DIVUW (IX+d)RES 7,(IX+d)
SET 0,(IX+d)-MULTUW(IY+d)RES 3,(IY+d)
RES 4,(IY+d)
RES 5,(IY+d)
RES 6,(IY+d)DIVUW (IY+d)
RES 7,(IY+d)
SET 0,(IY+d)-Page 122 of 125

CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF

no escED escDD escFD escCB escJP Z,nnescapeCALL Z,nn
CALL nn
ADC A,n
RST 1
RET NCPOP DEJP NC,nn
OUT (n),A
CALL NC,nn
PUSH DE
SUB n
RST 2
RET C
EXX
JP C,nn
IN A,(n)CALL C,nnescapeSBC A,n
RST 3
RET POPOP HLJP PO,nn
EX (SP),HLCALL PO,nn
PUSH HLAND n
RST 4
RET PE
JP (HL)JP PE,nn
EX DE,HL
CALL PE,nnescape
XOR n
RST 5
RET P
POP AF
JP P,nn
DI
CALL P,nn
PUSH AF
OR n
RST 6
RET M
LD SP,HL
JP M,nn
EI
CALL M,nnescapeCP n
RST 7

escapeCALR Z,e
CALR eBTEST
LDCTL A,DSR
OUTA (nn),A
CALR NC,eSUB HL,(nn) **LDCTL DSR,A
EXALL
LDCTL DSR,nINA A,(nn)CALR C,ereserved
LDIW
INIW
OUTIW
CALR PO,e
LDDW
INDW
OUTDW
CALR PE,ereserved
LDIRW
INIRW
OTIRW
CALR P,e
SETC LCK
LDDRW
INDRW
OTDRW
CALR M,ereserved
RESC LCKLDCTL SR,nescapeCALR Z,ee
CALR ee
ADCW (IX+d)MTEST
LDCTL A,XSRCALR NC,ee
SUBW (IX+d)LDCTL XSR,A
EXXX
LDCTL XSR,nCALR C,ee
reserved
SBCW (IX+d)POP IX
EX (SP),IXCALR PO,ee
PUSH IX
ANDW (IX+d)JP (IX)CALR PE,eereserved
XORW (IX+d)DI n
CALR P,ee
ORW (IX+d)SETC LWLD SP,IXEI nCALR M,eereserved
CPW (IX+d)RESC LW

escapeCALR Z,eee
CALR eee
ADCW (IY+d)LDCTL A,YSROUTAW (nn),HL
CALR NC,eee
SUBW (IY+d)LDCTL YSR,A
EXXY
LDCTL YSR,nINAW HL,(nn)CALR C,eee
reserved
SBCW (IY+d)
POP IY
EX (SP),IY
CALR PO,eee
PUSH IY
ANDW (IY+d)
JP (IY)CALR PE,eee
reserved
XORW (IY+d)CALR P,eee
PUSH nn
ORW (IY+d)SETC XMLD SP,IY
CALR M,eee
reserved
CPW (IY+d)-SET 1,DSET 1,E
SET 1,HSET 1,LSET 1,(HL)SET 1,ASET 2,BSET 2,CSET 2,DSET 2,E
SET 2,HSET 2,LSET 2,(HL)SET 2,ASET 3,BSET 3,CSET 3,DSET 3,E
SET 3,HSET 3,LSET 3,(HL)SET 3,ASET 4,BSET 4,CSET 4,DSET 4,ESET 4,HSET 4,LSET 4,(HL)SET 4,ASET 5,BSET 5,CSET 5,DSET 5,ESET 5,HSET 5,LSET 5,(HL)SET 5,ASET 6,BSET 6,CSET 6,DSET 6,E
SET 6,HSET 6,LSET 6,(HL)SET 6,ASET 7,BSET 7,CSET 7,DSET 7,E
SET 7,HSET 7,LSET 7,(HL)SET 7,A

ED-CB
-

DD-CB

FD-CB

SET 1,(IX+d)SET 2,(IX+d)SET 3,(IX+d)SET 4,(IX+d)SET 5,(IX+d)SET 6,(IX+d)SET 7,(IX+d)-SET 1,(IY+d)SET 2,(IY+d)SET 3,(IY+d)SET 4,(IY+d)SET 5,(IY+d)SET 6,(IY+d)SET 7,(IY+d)-Page 123 of 125

PACKAGE INFORMATION

100-Lead QFP Package Diagram

Page 124 of 125

ORDERING INFORMATIONZ380 MPU
18 MHZ
100-Pin QFP
Z8038018FSC

10 MHz, 3 Volts
100-Pin QFP
Z8L38010FSC

Package
F = Plastic Quad Flat Pack
Temperature
S = 0°C to +70°C
Environmental
C = Plastic Standard Flow

Example:Z 80380 18 F S C

is a Z380, 18 MHz, Plastic Quad Flat Pack, 0°C to +70°C, Plastic Standard Flow
Environmental Flow
Temperature
Package
Speed
Product Number
Zilog Prefix© 1997 by Zilog, Inc. All rights reserved. No part of this document
may be copied or reproduced in any form or by any means
without the prior written consent of Zilog, Inc. The information inthis document is subject to change without notice. Devices soldby Zilog, Inc. are covered by warranty and patent indemnification
provisions appearing in Zilog, Inc. Terms and Conditions of Sale
only.
ZILOG, INC. MAKES NO WARRANTY, EXPRESS, STATUTORY,IMPLIED OR BY DESCRIPTION, REGARDING THE INFORMATION SET FORTH HEREIN OR REGARDING THE FREEDOM OF
THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTYINFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE.
Zilog, Inc. shall not be responsible for any errors that may appear
in this document. Zilog, Inc. makes no commitment to update or
keep current the information contained in this document.

Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific writtenagreement pertaining to such intended use is executed between
the customer and Zilog prior to use. Life support devices orsystems are those which are intended for surgical implantation
into the body, or which sustains life whose failure to perform,
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result insignificant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
Telex 910-338-7621
FAX 408 370-8056
Internet: http://www.zilog.co

Page 125 of 125