Feasibility Studies on Next-Generation
Supercomputing Infrastructures:
System Software and Library Research
Takahiro Katagiri (Information Technology Center, Nagoya University, E-mail: katagiri@cc.nagoya-u.ac.jp/ RIKEN R-CCS, Visiting Researcher)
The next-generation computational infrastructure is expected to become a platform for realizing SDGs and Society 5.0
by providing advanced digital twins that will bring "Research DX" in the science. Aiming to realize a versatile computing
infrastructure that can execute entire workflow by making full use of wide range of computational methods, simulation
techniques, and BigData at scale, we conduct a holistic investigation on architecture, system software and library
technologies through co-design with applications.
As a basic principle of system design, we practice the "FLOPS to Byte" concept from architecture development toalgorithm or application design to streamline data transfer and computation under power constraints, while taking
necessary computing accuracy into consideration. Under the ALL JAPAN team composition, we will investigate system
Wider application area
configurations and elementary technologies which improve effective performance of the next-generation computing
infrastructure.

Higher performance

Aim of the Project

Research DX platformby digital-twins

System Software and Library Research Investigate technological trend of system software and draw R&D roadmap based on it Holistic studies on 8 system SW areas, cross-cutting technologies (security, auto-tuning, etc.) and platforming

 Prioritize SW / tools to develop domestically by considering usage on flagship and 1-tier machines, development cost, proficiencyof existing ecosystem, and other factors
 Study new technological area in system software for industrialization
 Investigate new areas of development to encourage use in a wide range of applications
 Providing a platformed digital twin environment for industrial use, promotion of data utilization, fusion of machine learning &first-principles simulation, advanced large-scale real-time data processing, high security, etc.
 ALL JAPAN team organization with industry-academia collaboration
 Expect future ripple effect on HPCI supercomputer centers
1. Scheduler/
Runtime sub-G

8. AI framework
sub-G

2. IO/Storage/
Filesystem subGG

Cross-cutting
technologies (security,auto-tuning, etc.)

7. Numerical
Library sub-G

6. Compiler/Programming model sub-G

Survey of system SW trend &draw development roadmap

3. OS/Virtualization/
Cloud sub-G

Examine new system SW areas forindustrialization

4. HPC Env. Usage
Investigation sub-G

5. Communication
Library sub-G

ALL Japan team organization with industry-academia collaboration

Adaptation of Auto-tuning to Quantum-Inspired Annealing Machine Quantum-inspired computers are being developed.
 Procedure of Auto-tuning CMOS Annealing Machine (Hitachi), Digital Annealer (Fujitsu), etc.

 Solving procedure using CMOS annealing machine.

 Results
Minimum Vertex Cover Problem
Find V′, which is the vertex covering set (where |𝑉𝑉′| isthe minimum, Graph 𝐺𝐺=(𝑉𝑉,𝐸𝐸), V′⊆𝑉𝑉)
The optimal solution ratio [%] with default values

𝑁𝑁 = 3 Parameters to be tuned on CMOS Annealing Machine

𝑤𝑤𝑎𝑎

1.00

𝑤𝑤𝑏𝑏

1.00

𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐_𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠

Optimalsolution ratio

1.00

𝟓𝟓%

The optimal solution ratio [%] with auto-tuned settings

Parameters

Overview

Wa

Coefficient of constraint term

Wb

Coefficient of cost term

chain_strength

Strength of chain

temperature_num_steps

Number of steps in annealing

temperature_step_length

Length of steps in annealing

temperature_initial

Initial temperature in annealing

temperature_target

Final temperature in annealing

𝑁𝑁 = 3

𝑤𝑤𝑎𝑎

9.76

𝑤𝑤𝑏𝑏

0.01

Information Technology Center, Nagoya University
http://www.icts.nagoya-u.ac.jp/en/center/

𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐_𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠
6.42

Optimalsolution ratio
𝟖𝟖𝟖𝟖𝟖