Control Strategy for a Hybrid Five-level
Three-phase PWM Rectifier Using Twelve
Switching Devices
Jun-ichi Itoh, Taketo Adachi
Nagaoka University of Technology
1603-1 Kamitomioka-cho Nagaoka City
Niigata, Japan
Abstract-This paper proposes a new circuit topology for a
multilevel PWM rectifier. The proposed circuit combines a
diode clamp type topology with a flying capacitor type topology.
As a result, the proposed circuit uses only 12 switches, despite
the use of a five-level three-phase PWM rectifier. Further, theproposed circuit can obtain good performance as same as to aconventional multilevel circuit. This paper describes thefeatures of the proposed topology; the control strategy and loss
analysis using circuit simulation. In addition, the basic
operation of the proposed method is confirmed by simulationand experimental results. The proposed converter achieved
3.4% THD for the input current and 97.4% efficiency for a 1
kW class experimental setup.

I.

INTRODUCTION

Recently, the harmonics current in power grids havecaused various problems, such as line voltage distortion andheating of power factor correction capacitors. The harmonics
current in power grids is mainly generated by a dioderectifier which is used as a front converter of an inverter. In
order to reduce the harmonics current of the power grid,
power factor correction (PFC) rectifier is still a very
important technology. A PWM rectifier, which consists ofthree switching legs, is one of the popular PFC rectifiers. A
PWM rectifier can strongly reduce the harmonics current
because the grid current can be controlled.
A PWM rectifier requires high voltage rating devices inorder to be applied to medium voltage applications. The highvoltage rating devices have problems, such as low switching
speed and large saturation voltage between collector andemitter. The low switching speed causes the large volume ofa boost reactor and filter since the high switching frequency
does not achieved. As a result, it is difficult to apply the
PWM rectifier to a medium voltage power grid.
For a medium voltage power grid, multi-level converter
technology is one of the solutions for high voltage
rectification application [1-3]. In general, a n-level converter
can reduce the voltage stress of a switching device to 1/(n–1)
of the DC output voltage. There are many circuit
configurations for a multi-level converter, such as the diodeclamp (DCLP) type [4][5] that uses clamp diodes andcapacitors for the DC output voltage, the flying capacitor(FC) type [6][7] that uses clamping capacitors floating on the
DC output voltage, and the chain link (CL) type [8][9] thatuses isolated power supplies to clamp each level. With
respect to cost reduction and downsizing, the DCLP and FC

types are better solutions than the CL type, since CL typerequires a large transformer and many switching devices.
However, for over three-level rectifiers, the DCLP typerequires balance circuits in the DC part, in order to control
the clamping capacitor voltage [10]. In contrast, the FC typerequires several capacitors for clamping capacitors. In
addition, both methods use many switches. For example, inthe case of a five-level three-phase rectifier, 24 switching
devices are required. In conclusion, the problems of multilevel converters are the number of switching devices andcontrol of the clamping capacitor voltage.
This paper proposes a novel five-level three-phase rectifier
topology, which combines the DCLP and FC type converters,
and its control strategy. The proposed converter requires
only half the number of switches in comparison with the
DCLP and FC types, that is, only 12 switches are used forthe five-level rectifier. The point of the proposed topology isthat high voltage diodes can be more easily to be utilized
than high voltage switching devices. The features of the
proposed circuit are described, and the control strategy isusing by space vector modulation. The used of space vector
modulation can result in a good sinusoidal current of thepower grid. In addition, a loss analysis method based on the
PSIM circuit simulator is introduced [11]. The validity of the
proposed rectifier, the control strategy, and the loss analysis
are confirmed by experimental results.
II. PROPOSED CIRCUIT TOPOLOGY
A. Conventional Circuit
Figure 1 (a) shows the DCLP and (b) shows the FC typefive-level PWM rectifier topology. The switching devices ofboth topologies are of the same voltage rating. Bothconverters can use a voltage rating 1/4 of that for the DC
output voltage; however, these converters use 24 switching
devices. As a result, cost is increased and the control strategy
becomes complicated. For example, the control strategy for
the FC type five-level PWM rectifier is described in thefollowing.
The FC type five-level PWM rectifier has 16 switchingpatterns. The switching patterns and its rectifier input voltage,
which is the voltage point between the rectifier and the boost
up reactor based on the neutral point of the power grid, areshown as follows
1) Vconv = Vdc
Turn on all upper switches S1, S2, S3, and S4 .
2) Vconv = 3Vdc/4

a) S1, S2, S3, S4' (Vconv = Vdc – Vdc/4)b) S1', S2, S3, S4 (Vconv = 3Vdc/4)c) S1, S2', S3, S4 (Vconv = Vdc – 3Vdc/4 + Vdc/2)d) S1, S2, S3', S4 (Vconv = Vdc – Vdc/2 + Vdc/4)
3) Vconv = Vdc/2
a) S1, S2, S3', S4' (Vconv = Vdc – Vdc/2)b) S1', S2', S3, S4 (Vconv = Vdc/2)c) S1, S2', S3, S4' (Vconv = Vdc – 3Vdc/4 + Vdc/2 – Vdc/4)d) S1, S2', S3', S4 (Vconv = Vdc – 3Vdc/4 + Vdc/4)e) S1', S2, S3', S4 (Vconv = 3Vdc/4 – Vdc/2 + Vdc/4)f) S1', S2, S3, S4' (Vconv = 3Vdc/4 – Vdc/4)
4) Vconv = Vdc/4a) S1, S2', S3', S4' (Vconv = Vdc – 3Vdc/4)b) S1', S2', S3', S4 (Vconv = Vdc/4)c) S1', S2', S3, S4' (Vconv = Vdc/2 – Vdc/4)d) S1', S2, S3', S4' (Vconv = 3Vdc/4 – Vdc/2)
5) Vconv = 0
Turn on all lower switches S1', S2', S3', and S4' .
There are many switch patterns which can charge ordischarge to the flying capacitor in disregard of the same
voltage level. These switch patterns should be selected inorder to control the voltage of each flying capacitor inconstant. In addition, many voltage sensors are required todetect the voltage of the flying capacitors.
On the other hand, for the DCLP type, the clamping
capacitor voltage can not be controlled without an auxiliary
circuit. Additional voltage regulators, such as DC chopper,
are required to maintain each clamping capacitor voltage inthe quarter of the DC output voltage.
B. Proposed Circuit
Figure 2 shows the proposed five-level PWM rectifier
using only 12 switches. The proposed converter combines
both the DCLP and FC types into one. High voltage rating
diodes are required in the proposed circuit; however, a fast
recovery diode is unnecessary, because there is no recovery
mode for the high voltage diode in the proposed circuit. Thus,
the high voltage low speed diode is cheaper than the highvoltage switching devices. It should be noted that if theregeneration mode is required, then high voltage switching
devices can be used instead of the high voltage diode. In thiscase, low speed switching devices, such as a thyristor or agate turn off thyristor (GTO), can be applied, because thehigh voltage switching devices do not switch at highfrequency, but only switch at the same frequency of thepower grid.
Table I shows a comparison among the DCLP, FC andproposed rectifier. The largest advantage of the proposed
circuit is that the proposed circuit allows the number of theswitches and capacitors to be reduced, so that the number ofswitching devices becomes 12, which is half of theconventional circuit. It should be noted that if the proposed
concept is applied for other multi-level rectifier topology,
then the number of switching devices can always be reduced
to half of the conventional topology, because the outside
diode can take half of the DC output voltage.
The other large advantage of the proposed circuit is thatthe proposed circuit can control each clamping capacitor
voltage. The voltage of the inner clamping capacitor C1 canbe controlled, because the structure of the inside part is thesame as that of the FC type. The voltage of the middle
capacitors (C2 and C3) also can also be controlled, because
this part is the same as the three-level rectifier.
Figure 3 shows the current path of the proposed rectifier ineach switching pattern. The proposed rectifier has eightswitching patterns. However, the available switching patterns
are constrained by the direction of grid current because theproposed circuit uses diodes in the main current path.
The switching patterns and rectifier input voltage level atthat pattern are described as follows. Note that the neutral
point of the DC side is defined as the zero voltage level inthis discussion.

(a) Diode Clamp (DCLP)(b) Flying Capacitor (FC)
Figure 1. Conventional five-level PWM rectifier topologies (single leg).

Figure 2. Proposed hybrid PWM rectifier.
TABLE ICOMPARISON OF THE DCLP, FC AND PROPOSED CONVERTER
DCLP

FC

ProposedcircuitSwitch

24

24

12

*

60

24

36

Capacitor

Diode

4

30

13

Control of thecapacitor voltage

impossible

possiblepossible*

including FWD

(a)When half period of input voltage is positive:1) Vconv = +Vdc/2
S1 and S2 are turned on.
2) Vconv = +Vdc/2 –Vc
S1 and S3 are turned on.
3) Vconv = +Vc
S2 and S4 are turned on.
4) Vconv = +0
S3 and S4 are turned on.
(b)When half period of input voltage is negative:5) Vconv = –0
S1 and S2 are turned on.
6) Vconv = –Vc
S1 and S3 are turned on.
7) Vconv = –Vdc/2 +Vc
S2 and S4 are turned on.
8) Vconv = –Vdc/2
S3 and S4 are turned on.
In principle, the proposed circuit can output seven voltage
levels to the AC side of the converter. However, in order tocontrol the inner clamping capacitor (C1) voltage Vc, twoswitching patterns for charge or discharge mode are required.
Therefore, to keep the two switching patterns, the voltage
levels +Vdc/2 –Vc and +Vc, -Vc and –Vdc/2 +Vc are set to thesame of each voltage level. That is, Vc is set to Vdc/4. As aresult, Vc can be controlled by switching pattern of 2) and 3)or 6) and 7), respectively.

+Vdc/2

S1

S1

S2

S2
Vc

⎧ V1 = V1α + V1β⎪⎨V2 = V2α + V2 β
⎪V = V + V
3α
3β
⎩ 3

S3

S3

S4

S4

1)

The subscripts α and β are the horizontal and verticalcomponents of the selected vectors, respectively. The
relation between the selected vectors and the output vector is
obtained by (2).
⎧voα = V1α T1 + V2α T2 + V3α T3⎪⎨voβ = V1β T1 + V2 β T2 + V3 β T3
⎪ 1= T +T +T
1
2
3
⎩

(2)

–Vdc/20

2)+Vdc/2

S1

S2

S2
Vc

0

S3
S4

–Vdc/2+Vdc/2

S1

Vc

0

S3
S4

3)

(1)

Vc

0

III. CONTROL STRATEGY
A. Space Vector Modulation
Figure 4 shows the space vector for the proposed five-levelrectifier, where “x” represents the top of the voltage vector.
In the case of the proposed rectifier, there are 61 kinds of thevoltage vectors, except for the charge or discharge switchingpatterns to the inner clamping capacitor in the proposed
circuit. Firstly, the three nearest space vectors V1, V2, and V3,
where surrounding the top of the output voltage vector vo of
the rectifier, are selected. Note that the output vector
represents the input voltage of the power converter. The
charge or discharge mode vector is selected according to theinner clamping capacitor voltage and the neutral point
voltage of the DC output part. The selected vectors V1, V2,
and V3 are expressed by (1) using the α-axis (horizontal) and
β-axis (vertical) components.

+Vdc/2–Vdc/2

4)–Vdc/2(a) Positive period of the input voltage.

+Vdc/2+Vdc/2

S1

S1

S2

S2
Vc

Vc

0

S3

S3

S4

S4

5)

–Vdc/2

0

6)+Vdc/2+Vdc/2

S1

S1

S2

S2
Vc

0

S3
S4

–Vdc/2

Vc

0

S3
S4

7)

–Vdc/28)(b) Negative period of the input voltage.
Figure 3. Current path of the proposed rectifier.

–Vdc/2

T1, T2, and T3 are the output time ratio on a carrier period
for each of the selected vector. Therefore, the output periodof each vector is calculated using (3) from (2).
T1 =1{(V2 β − V3β )(voα − V3α ) + (V3α − V2α )(voβ − V3β )}
A

T2 =

1
{(V3 β − V1β )(voα − V3α ) + (V1α − V3α )(voβ − V3β )}
A

T3 =

1
{(V2 β − V1β )(voα − V3α ) + (V1α − V2α )(voβ − V3β )}
A

(3)

where

Figure 5. Control block diagram for the proposed circuit.

A = (V1α − V3α )(V2 β − V3β ) − (V1β − V3 β )(V2α − V3α )The inner clamping capacitor voltage is controlled by theselection of the switching pattern, since the proposed
rectifier can output the same voltage level using different
switching patterns that achieved charge or discharge to theinner clamping capacitor. For example, when the polarity of
the input voltage is positive, a quarter voltage level of theDC output voltage is obtained by having both switches S2, S4
turned on and switches S1, S3 turned on, provided the inner
clamping capacitor C1 voltage is set to quarter of the DC
output voltage. While the switches S2 are S4 are turned on,
the inner clamping capacitor can be charged. In contrast,
while the switches S1 are S3 are turned on, the inner clamping
capacitor can be discharged.
B. Control Block Diagram
Figure 5 shows the control block diagram for the space
vector modulation of the proposed rectifier. The DC output
voltage and the input current are controlled by a PI regulator
on a rotating frame, the same as that in a conventional PWM
rectifier. In the switching table, the output vector isdetermined by the magnitude of the vector, the phase angleof the power grid, and the capacitor voltage control
conditions using a hysteresis controller.
Figure 6 shows the voltage waveform of the rectifier input
voltage. It is noted that the zero level of the rectifier input
voltage is defined as the neutral point voltage of the DC
output part. Five-step stairs waveform is obtained as therectifier input voltage, which is divided into six sectors by
voltage levels.

Figure 4. Space vector map.

Figure 6. Rectifier input voltage waveform.
TABLE IISWITCHING TABLE OF THE PROPOSED RECTIFIER
SectorVoltage levelTurn-on switches

I+Vdc/4 , +0

S2-S4 (S1-S3)*, S3-S4

II+Vdc/2 , +Vdc/4

S1-S2, S2-S4 (S1-S3)*

III+Vdc/4 , +0

S2-S4 (S1-S3)*, S3-S4

IV–0 , –Vdc/4

S1-S2 , S1-S3 (S2-S4)*

V–Vdc/4 , –Vdc/2

S1-S3 (S2-S4)*, S3-S4

VI–0 , –Vdc/4

S1-S2 , S1-S3 (S2-S4)**

Charge mode (Discharge mode)

Figure 7. Simulation result of the proposed rectifier.

Table II indicates the switching pattern table of the
proposed rectifier. For example, in the sector II, when therectifier input voltage is +Vdc/2 or +Vdc/4, if the inner
clamping capacitor voltage Vc is lower than its command Vc*,
the charge mode (S2 and S4 are turned on) will be selected.
On the other hand, if Vc is higher than Vc*, the discharge
mode (S1 and S3 are turned on) will be selected. Thus, theinner clamping capacitor voltage can be controlled
constantly at all sectors.
Additionally, the neutral point voltage of the DC part iscontrolled by the zero levels as the same as a conventional
three-level inverter. The zero level output switching patternis selected by the input voltage polarity. When the input
voltage is positive, the +0 is selected for the zero level toincrease the neutral point voltage. On the other hand, the –0
is selected when the input voltage is negative to decrease theneutral point voltage. As a result, the DC part capacitor (C3)
voltage can be balanced by the zero level selection.
IV. SIMULATION RESULT
Figure 7 and Table III show the simulation results of the
proposed rectifier and the simulation parameters. Clean
sinusoidal input current waveforms were obtained, and thetotal harmonic distortion (THD) for the input current was
2.6%. However, there is a distortion at the zero-cross pointof the input current. The reason of the distortion is a phaseshift of the input current depends on the input inductor. The
DC output voltage agreed with its command of 320 V. In
addition, the switching voltage of each switching device isreduced to 80 V, that is, Vdc/4.
V. EXPERIMENTAL RESULT
Figure 8 shows the operation waveforms for the
proposed rectifier. The input voltage is 200 V, 50 Hz, theoutput power is 1 kW (rating), and the DC output voltage
command is set to 320 V, that is, the inner clamping
capacitor voltage command is set to 80 V (the circuit
parameter is the same as Table III). Clean sinusoidal input
current waveforms were obtained and the THD of that was
3.4% (the 40th or less order components harmonics wereconsidered). In addition, the DC output voltage and theinner clamping capacitor voltage agreed with commands ofthat respectively. In Figure 8 (b), a five-step voltage
waveform is observed in the rectifier input voltage of the

proposed converter, which agrees with the expectation. Itshould be noted that the spike voltage in the rectifier input
voltage is caused by the commutation of the diode at theedge of the sectors. However, the each switching device
voltage is clamped by the inner or outer clamping capacitor.
Therefore, the low voltage rating switching device can be
used.
Figure 9 shows the harmonic current analysis at 1 kW load.
Each component of harmonics current of the input current isreduced to less than 2 %.
Figure 10 shows the step load response of the proposed
rectifier. Although the load is increased by step shape asshown at the dash line, The DC output voltage and the inner
clamping capacitor voltage can be kept constantly.
Figure 11 shows the efficiency and input power factor of
the proposed rectifier. The maximum efficiency is 97.6% at a
0.5 kW load, and an input power factor of over 98% wasachieved at over 0.5 kW load. The proposed circuit canobtain efficiency of over 97% in a wide load condition
because the switching frequency of the outer diode is thesame as the power grid frequency even if that of the innerswitching device is high.
Figure 12 shows the input current THD of the proposed
rectifier. The proposed rectifier achieved 3.4% THD for the
input current. It should be noted that the THD increase in thelight load condition because the magnitude of the harmonics
component is almost constant. Therefore, the ratio between
the fundamental and harmonics component becomes larger
in the light load condition
Figure 13 illustrates the loss analysis result for 1 kW load.

(a) Input current and DC output voltage.

TABLE IIISIMULATION PARAMETERS OF THE PROPOSED RECTIFIER
Output power

1 [kW]

Input voltage

200 [V]

Input voltage frequency

50 [Hz]Carrier frequency

10 [kHz]*DC output voltage command (Vdc )320 [V]

Load resistance(RL)

100 [Ω]

Input inductor (Lin)2 [mH]

Inner clamping capacitor(C1)100 [µF]

Clamping capacitor(C2)100 [µF]

DC part capacitor(C3)1800 [µF](b) Rectifier input voltage
Figure 8. Experimental results of the proposed rectifier at 1 kW.

The power loss is composed by linking a circuit simulator(PSIM, Powersim Technologies Inc.) and a DLL (Dynamic
Link Library) file. The DLL file has a loss table regarding
the switching and conduction losses based on the
instantaneous values of the current and the voltage of thepower device, as written in [11]. This method can estimate
the power semiconductor loss, regardless of the circuit
configuration. The loss simulation results are in good
agreement with the efficiency of experimental results. In the
proposed circuit, the conduction loss is the most dominantsection of the power losses. In order to improve efficiency, a
low conduction loss device should be selected.
VI. CONCLUSIONS
A novel five-level PWM rectifier and its control strategy
were proposed. Features of the proposed circuit are thereduction in the number of switching devices, and acontrollable clamping capacitor voltage. The proposed
converter achieved 3.4% THD for the input current at 1 kWload and 97.6% efficiency at 0.5 kW load for a 1 kW classexperimental setup.

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Figure 11. Input power factor and efficiency of the proposed rectifier.
100

10

1

0.1
1

3

5

7

9

11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41

Figure 9. Harmonic current analysis at 1kW load.
Figure 12. Input current THD of the proposed rectifier.

Figure 10. Experimental result of load step response.

Figure 13. Loss analysis results by loss simulation at 1 kW load.