High Power Density Design for a Modular Multilevel
Converter with an H-bridge Cell
based on a Volume Evaluation of Each Component
Toshiki Nakanishi, Student Member, IEEE, and Jun-ichi Itoh, Member, IEEE
Abstract— This paper presents a high power density design fora step-down rectifier incorporating a modular multilevel
converter (MMC) in a power system connected to a 6.6 kV AC
grid. In particular, the relationship among the number of cells, theoutput voltage of the MMC and the overall volume is clarified. A
proposed design flowchart focuses on minimizing volumes of cell
capacitors, heat sinks and arm inductors by using optimal
number of cells. Moreover, the commercial electrolytic capacitors
are used as the cell capacitor. Besides, the formulae used todetermine the ripple currents in the electrolytic capacitor and thearm inductor are presented, along with that for the semiconductor
loss. Each of these formulae were verified experimentally using a
miniature model and theoretical values from all formulae agreewith the measured values within minimal deviations that are
discussed with regard to the design of a practical converter for a
6.6 kV system. Finally, the conditions necessary to achieve highpower density in an MMC are provided, based on volume
evaluations of the electrolytic capacitor, the arm inductor and theheat sink. Using this optimization process, an MMC design
achieved a volume reduction of approximately 90% compared toa conventional system.
Index Terms— Modular multilevel converter, Pareto front,
High power density design, H-bridge cell, Step-down
rectifierI. INTRODUCTION

R

ecently, DC micro-grids have been actively researched as
next generation power distribution system [1]-[6]. In DC
micro-grids which have been considered so far, a power system
which is connected to an AC power grid has the isolationtransformer in order to convert 6.6 kV to several hundred volts[5]. However, the isolation transformer operating at acommercial frequency is bulky. In addition, bulky static
capacitors for power factor correction as well as series reactors
for reduction of the harmonic distortion of the grid current arealso requires in the above system [7].
In order to avoid the utilization of the bulky transformer, theneutral-point-clamped (NPC) converter or the diode-clamped
converter has been researched [8]. In the three-level
diode-clamped converter, the high voltage IGBTs with the

Toshiki Nakanishi is with Nagaoka University of Technology, Niigata Japan(e-mail: nakanishi@stn.nagaokaut.ac.jp).
Jun-ichi Itoh is with Nagaoka University of Technology, Niigata, Japan(e-mail: itoh@vos.nagaokaut.ac.jp).

voltage rating more than 6.5 kV are required. However, it isgenerally difficult to employ the IGBTs with the voltage rating
more than 6.5 kV due to their specifications. Moreover, if the
five-level diode-clamped converter is applied to solve theproblem with the switching devices, the voltage balancing
circuit is required as the auxiliary circuit in order to correct theunbalanced voltage among four capacitors in the DC link.
Besides, the switching frequency cannot be set more thanseveral kilohertz because the switching loss is large in the highvoltage switching device which is applied to the three-level orthe five-level diode-clamped converter. As a result, the volumeof the interconnected inductor is bulky. In addition, the bothconverters cannot achieve step-down rectification. Thus, thespecification of the NPC converter are different from therequirements of the proposed system.
On the other hand, a modular multilevel converter (MMC)
has been actively researched as next generation high voltage
power converters that does not require a bulky transformer[9]-[16]. In particular, an H-bridge cell type MMC is suitablefor use as the front-end converter in a DC micro-grid in terms ofvolume reduction and step-down rectification from 6.6 kV AC
voltage to several hundred volts of DC voltage [17]-[18].
In many AC-DC converters incorporating MMC topology,
high power density is obtained by careful consideration of thevolume and by setting specific design criteria [19]-[25].
However, the criteria necessary to reduce the overall volumesof (i) capacitors, (ii) heat sinks and (iii) arm inductors in thedesign of a step-down rectifier with an H-bridge cell type MMC
have not yet been reported in detail.
Firstly, evaluations of the correlations between capacitor
volume, the capacitance and electrostatic energy of the device
have been reported [26]-[28]. Volumes of various capacitors
such as customized film or ceramic with a fixed number of cells
have been also shown [28]-[29]. However, the relationshipbetween the number of cells and the capacitor volume has notbeen thoroughly considered. Additionally, it is difficult tocompare the volumes of the above capacitors in a practicalmanner because film or ceramic capacitors are customized withvarying numbers of cells according to desired performanceparameters. On the other hand, an electrolytic capacitor has theuseful feature such as high capacitance per unit volume or thevoltage rating of several hundred volts. In addition, it is easy toconsider and design the capacitor volume when electrolytic
capacitors are applied to the MMC because cell capacitors canbe designed based on data of commercial electrolytic capacitors.

In contrast, the lifetime of the electrolytic capacitor is shortcompared to film or ceramic capacitors as the drawback.
However, electrolytic capacitors are widely applied to many
power converters such as grid-tied inverters or PWM rectifiers
after the lifetime of the electrolytic capacitors is considered
carefully. Besides, in the prototype of the MMC for the medium
voltage grid or the miniature model, electrolytic capacitors arealso applied [30]-[36]. These examples show the usability ofelectrolytic capacitors. Thus, it is very important to consider theuse of electrolytic capacitors including the lifespan in order topromote the discussion for the cell capacitor design. However,
not only the design method of electrolytic capacitors in the
MMC but also volume comparisons of electrolytic capacitors,
film capacitors or ceramic capacitors have not been discussed.
Secondly, as the heat sink design, the calculation of thesemiconductor loss have been reported [37]-[40]. In addition,
heat sink volumes have been evaluated when insulated gate
bipolar transistors (IGBTs) with voltage rating from 600 V to
6.5 kV were applied [41]. Despite this, the relationship among
the number of cells, the output voltage of the MMC and the heatsink volume has not been considered. As the output voltage isvaried, both the capacitor voltage and the circulating current
will change, even at a same power rating. Moreover, thecapacitor voltage is also changed by varying the number ofcells. Thus, the semiconductor loss varies drastically because
the voltage rating and the rated current of the switching device
are modified by the capacitor voltage and circulating current.
Besides, the switching loss changes based on the number ofcells because the switching frequency is determined by theequivalent frequency which is affected by the number of cells.
Hence, the relationship among the number of cells, the output
voltage of the MMC and the heat sink volume has to beclarified in order to achieve minimization of the heat sinkvolume.
Thirdly, with regard to the arm inductor volume, theinductance has been determined to be several percent of the
impedance rating of the MMC [42]-[44]. In addition, design
criteria that focus on the harmonic components of thecirculating current and the resonance phenomenon between thearm inductor and the capacitors in cells have also been
discussed [45]-[46]. In the case of the inductor in a general
power converter, the inductance is determined based on the
ripple factor of the inductor current [47]-[49]. In an MMC, themagnitude and the frequency of the ripple current will change
in response to the switching frequency and the number of cells
because these factors vary the equivalent switching frequency.
As well, the inductor current includes the circulating current,
which changes based on the output voltage of the MMC. Thus,
the ripple current factor varies even when the magnitude andthe frequency of the ripple current are constant. However, therelationship among the number of cells, the output voltage ofthe MMC and the arm inductor volume has not been considered.
In particular, the total volume of the heat sink and the arm
inductor has to be considered because the semiconductor loss
also changes when the number of cells or the output voltage
varies.
As a problem of the conventional design method for the

MMC, the relationship among the number of cells, the output
voltage of the MMC and the overall volume has not been
considered, although the design criteria for each component
have been assessed independently. However, it is required toclarify the above relationship in order to obtain high power
density. In particular, the parameters that are significantly
affected by the number of cells and the output voltage of the
MMC are: (i) the voltage rating, the current rating and theswitching frequency of the switching device, (ii) the voltage
rating and the rated ripple current of the electrolytic capacitorand (iii) the inductance of the arm inductor. Hence, the volumeof the MMC is changed by variations in the required parametersof these components.
This paper proposes the design criteria in order to obtain highpower density in the H-bridge cell type MMC. In particular, themain aim of this paper is to clarify the conditions based on thenumber of cells and the output voltage of the MMC forachieving the volume reduction of the cell capacitor, the heatsink and the arm inductor. The original contribution of thispaper is to determine the number of cells associated with thesmallest possible overall MMC volume based on the evaluationof the relationship among each component volume, the numberof cells and the output voltage. Moreover, the validity of
formulae for the design are verified by the experiment.
As a first step, a design flowchart was proposed to achieve
the highest possible power density. Secondly, in the design ofthe electrolytic capacitor focusing on lifespan and the voltage
rating, the number of parallel connection and the number ofseries connection are determined for the volume reduction.
Besides, the relationship between the electrolytic capacitor
volume, the rated ripple current and the voltage rating areevaluated. In addition, the relationship between the number ofcells and the electrolytic capacitor volume was also clarified.
Thirdly, the heat sink volume was evaluated by calculating the
conduction and the switching losses of the switching devices.
Fourthly, as the arm inductor design, a formula of the ripple
current was derived in order to determine the inductance basedon the ripple current factor. Finally, the relationship among thenumber of cells, the output voltage of the MMC and the volumeof the electrolytic capacitor was clarified. In addition, therelationship between the number of cells, the output voltage ofthe MMC and the total volume of the arm inductor and the heatsink was evaluated by Pareto front optimization [50]. The
above evaluations generates design criteria that reduce theoverall volume of the MMC. As a result, the overall volume of
the capacitors, heat sinks and arm inductors in an H-bridge cell
type MMC equals to equal 10% of the overall volume of aconventional power system including an isolated transformer,
static capacitors and a series reactor.
II. CIRCUIT CONFIGURATION AND CONTROL STRATEGY
A. Conventional Power System Connected to a Utility Grid
Fig. 1 shows the structure of a conventional 200 kVA powersystem connected to a 6.6 kV AC power grid [7]. This
conventional system has isolated transformers to convert thegrid voltage of 6.6 kV into an AC distribution voltage of 200 or6600 V

100 V. The power system also includes static capacitors tocorrect the input power factor and a series reactor to reduce theharmonic distortion of the grid current. The component volume,
defined as the total volume of the transformers, static capacitors
and the series reactor, is 1605 dm3, i.e. the main factors that
increase the system volume.

C. Control Strategy for the Step-Down MMC
Fig. 3 shows a control block diagram of the step-down
rectifier with an H-bridge cell type MMC [18]. The control
block is constructed by an averaging voltage control, an arm
current control, an output voltage control and a voltage
balancing control. In the proposed voltage balancing control,
the output DC voltage of each cell is varied depending on thecapacitor voltage [36]. The advantage of the proposed voltage
balancing control system is that it is not necessary to design
control parameters because the dividing ratio is adjusted
automatically depending on the capacitor voltage.
III. DESIGN FLOWCHART FOR A STEP-DOWN RECTIFIER WITH
MMC TOPOLOGY
Fig. 4 presents a flowchart summarizing the design of thestep-down rectifier with MMC. The flowchart is divided into
three parts: the capacitor, the arm inductor and the heat sink.
The efficiency and power density of the converter are shown as

LBS

LBS
※LBS:
Load Break Switch

Isolatedtransformer

Isolatedtransformer

Series reactor(Suppression ofharmonic distortion)

3f100 kVA
6600 V/210 V/105 V

3f100 kVA
6600 V/210 V

210 V

Static capacitor(Power factor
correction)

210 V/105 V(a) Circuit configuration of conventional system

2390 mm

B. Front-end Converter with MMC and Isolated DC-DC
Converter
Fig. 2 presents the configuration of the front-end converter
using an H-bridge cell type MMC. Each arm of the MMC that
operates as the step-down rectifier consists of an arm inductor,
La, and H-bridge cells [17]. Because the MMC is able to reducethe voltage rating of the devices on each cell due to the cascade
cell connections. Therefore, lower voltage switching devices
can be utilized with the MMC. The output DC voltage of theMMC, Vmmc, depends on the sum of the output average voltagesof cells per leg, meaning that the cell output voltage includes
both AC and DC components to control the input current andthe output voltage. Besides, the arm current such as iAr or iBr
also includes both AC and DC components. The MMC first
converts a high AC voltage to a DC voltage of several hundred
volts, then 400 V DC is supplied to the DC bus of the DC
distribution by the isolated DC-DC converter, which also
provides the isolation between the AC power grid and the DC
micro-grid. Hence, the high step-down from 6.6 kV to several
hundred volts is accomplished by the operations of both the
MMC and the isolated DC-DC converter. Thus, the output
voltage rating of the MMC can be designed with a high degreeof freedom. Moreover, the DC component of the arm current
which flows from each leg to the output side of the MMC can
be changed based on the output voltage of the MMC, Vmmc evenat a same power rating. The ripple current of the cell capacitor
or the semiconductor loss changes according to the variation of
the DC component. Thus, it is necessary to employ a variety of
combinations of the output voltage and the circulating current
to reduce volumes of the MMC and the isolated DC-DC
converter.

LBS

LBS

LBS

LBS

IsolatedTransformer

IsolatedTransformer

3f100 kVA
6600 V/210 V

3f100 kVA
6600 V/210 V/105 V

Static capacitor(Power factor
correction)
Series reactor

1900 mm3200 mm※LBS:
Total volume : 14531 dm3
Load Break Switch
3
Component volume : 1605 dm(b) Volume of conventional system
Fig. 1. Conventional power system of 200 kVA connected to utility gird of 6.6
kV. The conventional power system is constructed of several bulkytransformers, a high capacity static capacitor and a series reactor.

vAr1
cell

vcAr1
vcAr(n/2)

vAr v

Ar(n/2)cell

iAr
6.6 kV,
50 Hz

ir
is
it

La

iBr

La

DC bus ofMicro-gridvArs
Isolated
DC-DC
conv.

Vmmc
(DC)

cell

vcBr1

cell

vBr

vBr1

vcBr(n/2)

S1

S3

S2

S4 C

cell

vBr(n/2)

H-bridge cellFig. 2. Circuit configuration of front-end converter with H-bridge cell type
MMC and isolated DC-DC converter.
Capacitor Voltage
Averaging Control

vc* +

－

PI

vcmk_ave

Arm Current Control-1

imk_ph*2－

vmk_unit

Index

31
－－
2E

m : A, Bk : r, s, t
k' : other than kk'' : other than k and k'
j : cell number
Input phase voltage(Detection value)

vk

+

imk

imk_ph++imk' +
+
imk''

1/3

－

Elimination ofzero phase component

Kacr

+
+

* Kacr :Control gain of
Arm Current Control

2/n +

vmkj*

－

A:―
Vmmc_mkj*
B : + (+)
1 vcmkj
2 n/2

v
x1

cmkx

Vmmc*

Variable
Dividing ratio

MMC Output
Voltage Control
andCapacitor Voltage
Balancing Control

Fig. 3. Control block diagram for each arm in H-bridge cell type MMC. Notethat m is the index of the arm group A or B, k, k´ or k´´ is the index of the phasesuch as r, s and t, and j is the index of the cell number.

outputs. The purpose of this work is to miniaturize theconverter, and so it is necessary to determine the design
parameters associated with obtaining high power density. In

StartCalculation of required voltage rating andripple current of capacitors in each number of cells
Selection of electrolytic capacitor(Voltage rating, Rated ripple current, Endurance)
Calculation of the number of series connected capacitors
Calculation of the number of parallel connected capacitors
Calculation of total volume of electrolytic capacitors

Volume calculationin all numbers of cells which IGBTs
with voltage rating from 3.3 kV to 1.2 kV
are available is finished?

No

Yes
Database
Relationship between the number of cells andcapacitor volume

Selection of the number of cells
Selection of switching device
Calculation of semiconductor losses
Calculation of volume of heat-sink with CSPI
Calculation of inductance based on ripple current
in arm inductor
Calculation of volume of arm inductor with Area ProductDrawing pareto-front
Input parameter: Carrier frequency fC
Output parameter: Efficiency, Power density
Decision of carrier frequency fC
at maximum power density
Selection of heat-sink and arm inductor
at maximum power density
Overall volume is minimized?

No

Yes
FinishFig. 4. Design flowchart for a step-down rectifier with MMC.

particular, the carrier frequency and the number of cells at
which the overall volume of the capacitor, the heat sink and theinductor are minimized is determined.
In the capacitor design, the ripple current and the voltage

Voltage rating ratio 

rating are calculated from the MMC output voltage and thepower rating. A capacitor having a low rated ripple current isadvisable in order to reduce the capacitor volume. The numberof parallel connected capacitors increases when a capacitor
with a low rated ripple current is employed. However, when alow rated ripple current capacitor is selected, the capacitor
volume is small compared to that of device with a high rated
ripple current. When considering the voltage rating, a capacitor
for which the voltage rating per single capacitor is over 400 V
should be selected. The number of series connected capacitors
varies from two to three when a 1.7 or 1.2 kV IGBT is applied
to the converter. When the number of series connected
capacitors is greater than this, a balancing resistance is required
for each capacitor and so the volume increases. From the above,
the quantity of series connected capacitors is optimized basedon the desired voltage rating, while the number of parallel
capacitors is chosen by considering the ripple current and thelifespan of the device. The capacitor volume is calculated fromthe number of series connections, the number of parallel
connections and the cell quantity. The capacitor volume
associated with each cell quantity is stored in database. In thecase of high power converter, IGBTs with voltage rating from
1.2 to 3.3 kV are generally applied, and so it is particularly
important to store the relationship between the volume and thenumber of cells when using IGBTs with voltage ratings in thisrange. It is possible to reduce the capacitor volume by varying
the number of cells when the voltage rating ratio is high. This isdefined as the ratio of the required voltage rating to the voltage
rating with the series connected capacitors, and is calculatedusing equation (1). A high ratio implies that the capacitor isutilized without any waste.
In the heat sink design, based on two goals of reducing theheat sink volume and obtaining high efficiency, it is desirable toselect 1.7 or 1.2 kV IGBTs with low loss characteristics.
Following this, the number of cells for the available device iscalculated. After the calculation of the semiconductor loss, theheat sink volume is calculated based on the concept of thecooling system performance index (CSPI), defined as theinverse of the thermal resistance per unit volume, such that ahigh CSPI indicates the high cooling performance per unit
volume [51].
In the case of the arm inductor design, the inductance isdesigned by considering the relationship between the ripple
current and the arm current. Additionally, the volume of thearm inductor is designed by Area Product. Area product is theevaluation method for the volume of a core, which can bequantitatively calculated from the effective cross section andthe window section.
Following the design of the heat sink and the arm inductor,
the carrier frequency that minimizes the total volume of theheat sink and the arm inductor is determined by the Pareto front
optimization. In addition, the available heat sink and theinductor are selected at the point of maximum power density.
Finally, in order to determine the number of cells for which

Re quired voltage rating in each number of cells
Voltage rating per one capacitor  The number of series connected capacitors(1): 200 kVA

Input line voltage E

Input voltage frequency f: 50 Hz

Output voltage Vmmc

: 1200 V

Number of cell per leg n: 18

Cell capacitor C: 9000 F

Capacitor voltage VC0: 740 V

Input active power P: S cosf

0.045: 6600 Vrms

1 p.u. = Average value of capacitor voltage

0.040

0.004

0.035
0.030

0.003

0.025
Second-orderfrequency
component

0.020
0.015

0.002

0.010

0.001
Fundamental frequency
component

0.005

0.000

0.000
0

IV. EVALUATION OF THE VOLUME OF THE ELECTROLYTICCAPACITORIn the case of the cell capacitor of the MMC, highcapacitance is required to reduce the ripple voltage of thecapacitor, because the ripple voltage disturbs the voltage
control of the cell capacitor. Therefore, the use of anelectrolytic capacitor should be considered because it has thehigh capacitance per unit volume. On the other hand, the ripple
current that flows to the electrolytic capacitor affects thelifespan of the capacitor. Thus, the ripple current of thecapacitor is one of the most important factors in the design of
the MMC when electrolytic capacitors are applied. In this work,
the relationship between the capacitor volume and the ripple
current is examined, using a database of commonly-marketed
electrolytic capacitors that are often included in various devices.
Moreover, the relationship between the number of cells and thecapacitor volume is also considered because the voltage ratingof the capacitor drastically changes according to the number ofcells.
A. Determination of the Charge Voltage Command
In the MMC, an output DC voltage, Vmmc, is applied to eachcell of leg because each leg is connected to the load in parallel.
In addition, the maximum value of the input phase voltage isapplied to each arm. Thus, the capacitor voltage depends on the
input voltage and the output voltage. A capacitor voltage
command, vc*, is given by equation (2) [18].
vC

*


1 
2

2
E  Vmmc 

n 
3


(2)

where E is the effective input line-to-line voltage, Vmmc is theoutput DC voltage of the MMC and n is the number of cells ineach leg. Note that the modulation index, , which is set to 0.95
or less and the voltage drop of the arm inductor is ignored
because its value is negligible compared to the input phasevoltage and the output voltage of the MMC.
B. Relationship between the Ripple Voltage and the Input
Phase Difference
As a first step in the design of the lifespan of the electrolytic
capacitor, the relationship between the ripple voltage and the
input phase difference is clarified in order to determine theworst case when the ripple voltage is maximum. The capacitor

30

60

90

120

Input phase difference f[°]

150

Second-order frequency componentof ripple voltage [p.u.]

Input apparent power S

Fundamental frequency componentof ripple voltage [p.u.]

the overall volume of the capacitor, the heat sink and the arm
inductor is at a minimum, the above calculations and design
process are repeated. In the volume calculation, the relationshipbetween the number of cells and the capacitor volume isobtained from the database. As a result, it is not necessary toredesign the capacitor and recalculate the capacitor volume.
When the number of cells is selected, several points are taken
into account. Firstly, when designing the capacitor, the numberof cells for which the voltage rating ratio is at its maximum isselected. Secondly, during the design of the heat sink and thearm inductor, the minimum number of cells for which theselected switching device is available is employed. The designprinciples and the volume evaluation process are explained in
the following chapter.

180

Fig. 5. Relationship between input phase difference f and ripple voltage.
The fundamental frequency component is maximum when fis 0 or .

voltage, vc(t), is given by equation (3) [36].
v c t   VC 0 

1
2

2 Vmmc S
sin t
3 nCE VC 0

2
EP
sin t  f 
3 nC VmmcVC 0



2
3



S
sin 2 t  f
6nCVC 0(3)

Here, VC0 is the average value of the capacitor voltage, S is the
input apparent power, f is the input phase difference.
The ripple voltage includes a fundamental frequency
component, whose frequency is the same as that of the input
voltage, and a second-order frequency component with twice
the frequency of the input frequency.
Fig. 5 shows the relationship between the input phasedifference, f, and the ripple voltage based on equation (3). The
second-order frequency component does not change, evenwhen the input phase difference varies because S is constant. In
contrast, the fundamental frequency component reaches its
maximum when fis either 0 or . Thus, it is necessary todesign the capacitance considering the ripple voltage when fis
0 as the worst case.
C. Clarification of Ripple Current
The ripple current values of commercially-available
capacitors are normally readily obtained from the
manufacturer’s specifications. The capacitor should be selected
such that the ripple current value that flows to each capacitor issufficiently small compared with the specified value so as toimprove the device lifetime. Additionally, the number ofcapacitors connected in parallel in each cell should be increased
so as to obtain the specified ripple current, a process that candramatically change the capacitor volume. Hence, it isnecessary to clarify the relationship between the ripple current
and the capacitor volume before the relationship between thenumber of cells and the capacitor volume is evaluated. The
relationship between the capacitor current, ic, and the capacitor
voltage, vc, is given by equation (4).

(4)Endurance : 85 °C, 5000h

Volume of capacitors [dm3]2250000
2.25

From equations (3) and (4), it can be seen that therelationship between f and the maximum value of theamplitude is not changed by the differential of the ripple
voltage. Therefore, the ripple current reaches its maximum
when f is 0, and the maximum effective value of thefundamental frequency component in the ripple current, IC_1, isgiven by equation (5). Note that VC0 is calculated by equation
2500000(2).
2250000
2 E
(5)
1
P
1 Vmmc 
2000000


1750000
1.75

1.50
1500000
1.25
1250000
1.00
1000000
0.75
7500000.50
5000000.25
250000
0.00
0

E 

This equation shows that the1250000
maximum effective value of theripple current will not change1000000
as the number of cells or the
750000capacitance are varied.
5000001600000
1.6

F. Relationship between the Number of Cells and Capacitor
VolumeFig. 7 plots the relationship among the number of cells, theoverall volume of the capacitor and the voltage rating ratio.
Note that the number of series connected capacitors increases
as the required voltage rating increases above the voltage ratingof a single capacitor, making it necessary to use a seriesconnection of capacitors. The required voltage rating in thiscase is designed to be 30% more than the value calculated byequation (2). The capacitor volume is determined by the

00

45

15

20

Endurance : 105 °C, 3000h

1 A Rated ripple current of
5A
2 A one capacitor @ 50Hz
10A
4A
15A
8A
20A
13 A
25A
15 A
30A

1000000
1.0
8000000.8

1010Voltage rating : 100 V

1200000
1.2

40

55

5A
10A
15A
20A
Rated ripple current of
25A
one capacitor @ 50Hz
30A
25
30 35 40 45 50 55 60
25 30 35 40 45 50 55 60

15 20
Ripplecurrent (effective value) [A](a) Voltage rating: 400 V, Endurance: 85 °C, 5000h

1400000
1.4

D. Conditions for Evaluation of the Capacitor Volume
250000The overall volume of the capacitors
is evaluated by using a005electrolytic
10 15 20
25 30 35
database of commonly-used commercial
capacitors.
This database is composed of capacitors whose manufacturers(Nippon Chemi-Con, Nichicon and Rubycon) arerecommended as suppliers for inverters and high power
applications and for which the voltage ratings are from 100 to
600 V [36]. In this database, each capacitor volume is theaverage of all capacitors with different ripple current values,
rounded to the nearest one.

50

55

60

0.6
6000000.44000000.2
200000
0
0.0

0
0

5
5

10

15

20

25

30
30

15
20
Ripple10current (effective
value) [A]25(b) Voltage rating: 100 V, Endurance: 105 °C, 3000h
Fig. 6. Relationship between ripple current and capacitor volume. The
parallel connection of capacitors with small rated ripple currents rather than
only one capacitor with a large rated ripple current results in size reduction.
Voltage rating ratio =Total volume of capacitors [dm3]E. Relationship between Ripple Current and Capacitor
VolumeFig. 6 shows the relationship between the ripple current andthe capacitor volume using values from the database as an
example. In this graph, the amperages indicate the ripple
current of a single capacitor, and the number of capacitors
connected in parallel in one cell will increase with the required
ripple current values. As well, the starting point of each line
indicates the ripple current and the volume of the single
capacitor. These data demonstrate that the overall volume of
the capacitors is reduced by connecting capacitors with small
rated ripple currents in parallel, compared to using only one
capacitor with a large rated ripple current and so the parallel
connection scenario is preferable. Moreover, the ripple current
does not change with variations in the capacitance or thenumber of cells. Thus, the minimum value of capacitor volume
against the number of cells is equivalent to the minimum
overall volume.

Volume of capacitors [dm3]3   3 Vmmc 2
1750000
 2 2 E  Vmmc  31500000


2.00
2000000(Only parallel connection of capacitors)

I C _1 

Voltage rating : 400 V

2500000
2.50(Only parallel connection of capacitors)

dvC
dt

Required voltage rating in each number of cells
Voltage rating of one capacitor × Series connected number
504
800

Voltage rating of one capacitor : 400V

19
(Only series connection of capacitors)iC  C

807
1200

18
17
16
1615
2000

15
14
13
12

0

4

734
800

1153
1200

2691
2800

8073
8400

8

12

16

20

24

28

32

Number of cells [1/leg]Fig. 7. Relationship between the number of cells and the capacitor volume.
The capacitor volume becomes small when the voltage rating ratio is close
to 1.0.

quantity of series connected capacitors multiplied by the
number of cells under the same ripple current conditions. The
voltage rating ratio is defined as the ratio between the required
voltage rating and the actual voltage rating when the capacitors
are connected in series. As depicted in Fig. 7, the capacitor
volume becomes small when the voltage rating ratio at eachpoint is close to 1.0. Hence, it is possible to achieve the desired
volume minimization by designing a device for which thevoltage rating ratio is close to 1.0. In conclusion, it is necessary
to meet several conditions in order to achieve volume
minimization of the capacitors. Firstly, capacitors with low
rated ripple currents must be connected, and secondly, thevoltage rating ratio should be close to its maximum value of
1.0.

S1

S2

3


3 E
cos f 
2 Vmmc(6)

On the other hand, adding or subtracting the offset by the DC
component is required depending on the switching device suchas S1, or S2. In addition, it is also possible to calculate the dutyof the free wheeling diode (FWD) such as D1 or D2 based on the
duty of the switching device. Besides, in the H-bridge cell, S1and S4, which are shown in Fig. 8, operate as a pair, as so do S2and S3. Thus, the semiconductor losses are the same in thesepaired switching devices [18]. Therefore, in this paper, theformulae of the semiconductor losses in only one leg of the
H-bridge cell are shown.
The conduction losses of S1, S2, D1 and D2 are calculatedusing equations (7), (8), (9) and (10), respectively [18].

D4Fig. 8. Circuit model of the H-bridge cell for loss analysis.

 a 0

In this chapter, the equations for semiconductor losses in the
H-bridge cell are determined to allow for the design of the heatsink. Following this, the theoretical formulae and simulation
results are compared.

2

S4
D2

THE HEAT SINK DESIGN 0  cos 1 

D3 VC

D1
vcell

V. CLARIFICATION OF THE SEMICONDUCTOR LOSSES FOR

A. Calculation of Conduction Losses
Fig. 8 presents a circuit model for the H-bridge cell thatallows analysis of the semiconductor losses. The capacitor is
replaced with an ideal voltage source to remove the effect of theripple voltage and the inductor is replaced with an ideal current
source to remove the effects of the ripple current and theharmonic distortion.
The cell output voltage and the arm current include DC and
AC components. Thus, the magnitudes and the periods of thecurrents which flow to each switching device in the H-bridge
cell are different. The differences of the switching device
currents have been considered by defining the duty of theswitching device and analyzing the arm current [18].
Fig. 9 shows the relationship between the cell output voltage
and the arm current. Each offset of the cell output voltage andthe arm current varies according to the input voltage, the output
voltage and the output power. Besides, the output power varies
according to the input phase difference. Moreover, the angle, a,is the period when the direction of the arm current is positive,
whereas the angle, b, is the period when the direction of thearm current is negative. Note that the current direction was
defined as shown in Fig. 2. In the definition of each duty, theoffset by the DC component in the cell output voltage should beconsidered. In addition, the angle, 0, indicating the direction inwhich the arm current changes is defined by equation (6) when
the arm current is AC [18].

S3

iarm

b

iBr
(iarm)

0 a 0

vB_cell(vcell)f0Fig. 9. Relationship between the cell output voltage and the arm current in thelower side of the MMC.

PB _ S 1 _ Con 
V0 _ SW  Vmmc   2 S
2 P
 1    0 
sin 0 4 
nVC   3 E
3 Vmmc


2 PE
 
cosf sin 0  
3 Vmmc 1  P4  2   0   sin 2 0  
nVC  3
3



R SW  Vmmc   1 S 22   0   sin 2 0 
 1 
4 
nVC   12 E 2



2
3


2 PS
2 P
   0 
sin 0 
2
3 EVmmc
9 Vmmc1  1 2 PS 1
 3 sin 0  sin 3 0 
nVC  6 3 E 3

4 P2 
1
 4
    0   sin 2 0  
9 Vmmc 2 9

PB _ S 2 _ Con 

(7)

2

2 P2E
 
cosf sin 0  
2
3 Vmmc V0 _ SW  Vmmc   2 S
2 P
 1 sin 0 
0 

4 
nVC   3 E
3 Vmmc 

2 PE
 
cosf sin 0  
3 Vmmc 1  P4 2 0  sin 2 0  
nVC  33

RSW  Vmmc   1 S 2
2 0  sin 2 0   2
 1 2
4 
nVC   12 E
3




2 P2
1  1 2 PS 1
0  
 3 sin 0  sin 3 0 2
9 Vmmc3
 nVC  6 3 E 

4 P2 
1
 4
  0  sin 2 0  
9 Vmmc 
2
 9

2 PS
sin 03 EVmmc 
2 P2E
cosf sin 0  
2
3 Vmmc
 

(8)


V0 _ FWD  Vmmc   2 S
2 P
 1 sin 0 
0 

4 
nVC   3 E
3 Vmmc  
1  P
4 2 PE
cosf sin 0   2 0  sin 2 0  
nVC  3
3 3 Vmmc
 

Input apparent power S : 200 kVA Input active power P : S cosf

PB _ D1 _ Con 




2
3


2 PS
2 P2
sin 0 0 
2
3 EVmmc
9 Vmmc(9)1  1 2 PS 1
 3 sin 0  sin 3 0 
nVC  6 3 E 
3

4 P2 
1
 4

  0  sin 2 0  
9 Vmmc 2
 9: 6600 V

Output voltage Vmmc

: 1200 V: 740 V

Carrier frequency: 8 kHz

Number of cell per leg n : 18

 
2 P2E
cosf sin 0  
2
3 Vmmc 

Semiconductor loss per cell [p.u.] V   1 S 2
R2 0  sin 2 0 
 FWD  1  mmc  
4 
nVC   12 E 2Input line voltage ECapacitor voltage VC

300
0.0015

Switching device : FF150R17KE4

ACDCLine : Theoretical value
Mark : Simulation value

250

200
0.0010S1_Switching loss
D2_Recovery loss

150

100
0.0005

D2_Conduction loss
S1_Conduction loss

50

00.0000
0.00
0.0

0.10

0.20
0.2

0.30

0.40
0.4

0.50

0.60
0.6

0.70

0.80
0.8

0.90

1.00
1.0

Input power factor
V0 _ FWD  Vmmc   2 S
2 P
 1    0 
sin 0 
4 
nVC   3 E
3 Vmmc 
1  P
4 2 PE
cosf sin 0    2   0   sin 2 0  
nVC  3
3 3 Vmmc
 
 V   1 S 2R2   0   sin 2 0 
 FWD  1  mmc  
4 
nVC   12 E 2(10)(a) S1 and D2

2

3


2 PS
2 P2
   0 
sin 0 
3 EVmmc
9 Vmmc 2


1  1 2 PS 1
 3 sin 0  sin 3 0 
nVC  6 3 E 
3




4 P 
1
 4
    0   sin 2 0  
9 Vmmc 
2
 9
2

 
2 P E
cosf sin 0  
2
3 Vmmc 

Semiconductor loss per cell [p.u.]

PB _ D 2 _ Con 

AC

DC

20
0.00010

S2_Switching loss
D1_Recovery loss

15

Line : Theoretical value
Mark : Simulation value
100.00005

S2_Conduction loss ()

D1_Conduction loss ()

500.00000
0.00
0.0

0.10

0.20
0.2

0.30

0.40
0.4

0.50

0.60
0.6

0.70

0.80
0.8

0.90

1.00
1.0

Input power factor

2

Here V0 is the voltage drop at zero current, R is theon-resistance of the switching device, VC is the capacitor
voltage. Both V0 and R are calculated from values in thedatasheets of switching devices.
B. Calculation of Switching and Recovery Losses
The switching losses from S1 and S2 are calculated using
equations (11) and (12), respectively. Similarly, the recovery
losses from D1 and D2 are given by equations (13) and (14),respectively [18].

PB _ S1 _ SW 

w w
VC  1 2 S
P   0  on off f csin 0   2 3 E
3Vmmc
 Vdcd I md

(11)

PB _ S 2 _ SW 

VC  1 2 SP won  woffsin 0 0 fc
  2 3 E
3Vmmc  Vdcd I md

(12)

PB _ D1 _ Re c  w
VC  1 2 S
Psin 0 
 0  rr f c  2 3 E
3Vmmc  Vdcd I md

(13)

PB _ D 2 _ Re c VC  1 2 S
P   0  wrr f csin 0   2 3 E
3Vmmc
 Vdcd I md

(14)

where w is the loss energy value provided in the datasheet, Vdcd
and Imd are the voltage and the current at which w is measured,(b) S2 and D1
Fig. 10. Comparison result of theoretical formula of semiconductor loss
and simulation.

and fc is the carrier frequency.
C. Relationship between Input Power Factor andSemiconductor Losses
Here, the relationship between the input power factor and thetotal loss of the H-bridge cell is clarified in order to design aheat sink according to the worst-case scenario.
Fig. 10 presents a comparison of the results of theoretical
calculations of the semiconductor losses and those from thesimulation. The theoretical values agree with the simulation
values within a maximum error of 1.0% or less, even though thearm current changes from AC to DC at an input power factor of
0.22. Moreover, the losses of S1 and D2 increase as the input
power factor is raised. In contrast, the losses of S2 and D1
decrease. The semiconductor losses change because the DC
component in the arm current is varied according to the input
power factor. When the input power factor is zero, thesemiconductor loss is generated by only the AC component
because the active input power (the output power) is zero. The
semiconductor loss generated by the DC component increases
gradually as the input power factor approaches 1.0. Thus, thelosses of S1 and D2 increase with increases in the DC

component. In contrast, the losses of S2 and D1 decrease to zero
because the arm current does not flow to S2 and D1.
From the results in Fig. 10, the total loss is at its maximum
when the input power factor is 1.0. Thus, it is necessary todesign the heat sink for the worst-case semiconductor losses atthis input power factor.

vAr1

cell

vAr(n/2)cell

Vmmc/2

iAr

La

iBr

La

VI. DETERMINATION OF THE RIPPLE CURRENT FORMULA
FOR THE ARM INDUCTOR DESIGN

vcell t  1  22 E cost  f   Vmmc n  3
(15)

From equation (15), the total output voltage of the cells in thearm is equal to the summation of the input voltage and half thevalue of the MMC output voltage. Hence, only the ripple
component is extracted.
Fig. 12 presents a frequency analysis of the ripple current,with the carrier frequency of the cell set to 1.5 kHz. As shown
here, the fundamental component is 12 kHz, whereas thefrequencies of the second and the third-order components are
24 and 36 kHz.
In the H-bridge cell, employing unipolar modulation gives an
output voltage with twice the frequency of the carrier frequency.
Additionally, the equivalent switching frequency of the cell
total output voltage, vAr, in each arm, ftc_eq, is given by equation(16).
f tc _ eq n
* 2 f c  nfc
2(16)

This equation indicates that using eight cells and a carrier
frequency of 1.5 kHz gives an ftc_eq value of 12 kHz. It is
confirmed that the theoretical value given by equation (16) isequal to the result of the frequency analysis. Moreover, theabove result implies that the frequency of the ripple current ineach arm inductor is determined by the equivalent switchingfrequency, ftc_eq. As a result, when assessing the ripple current,
only the lower arm in Fig. 11 is considered.

Vmmc/2

vBr1

cell

VDC

vBr(n/2)

cell

VDC

Fig. 11. Equivalent circuit model of the single phase circuit in the MMC.
The cell capacitor is replaced by an ideal voltage source.
0.20
0.20

Carrier frequency fc : 1.5 [kHz]The number of cells per leg n : 8
Equivalent switching frequency : 12 [kHz]( = nfc (Unipolar modulation) )

0.18
0.18
0.16
0.16
0.14
0.14

0.12
0.12
0.10
0.10

0.08
0.08
0.06
0.06

0.04
0.04
0.02
0.02
0.00
0.00
0

12 kHz5

24 kHz1015

36 kHz
20

25

30

35

40

0
1000
2000
3000
4000
5000
6000
7000
8000
9000
10000
11000
12000
13000
14000
15000
16000
17000
18000
19000
20000
21000
22000
23000
24000
25000
26000
27000
28000
29000
30000
31000
32000
33000
34000
35000
36000
37000
38000
39000
40000

A. Analysis of the Ripple Current on Each Arm Inductor by theEquivalent Circuit Model
As a first step in the arm inductor design, it is necessary to
clarify the relationship between the ripple current and thenumber of cells.
Fig. 11 shows the equivalent circuit model of the single
phase circuit in the MMC. The circuit operation and thechanges in the ripple current are readily determined from thesingle phase circuit. In the equivalent circuit, the cell capacitor
is replaced by an ideal voltage source to remove voltage controlof the capacitor voltage. In addition, the output voltage of thecell is determined by equation (15) [18].

VDC

vBr

Ripple current [A]In this chapter, the formula for the ripple current in the arm
inductor is determined to allow for the design of the arm
inductor, which is based on the ripple factor of the inductor
current. The ripple current varies drastically in association withthe multilevel converter when the number of cells or theswitching frequency changes. Hence, it is necessary to clarify
the relationship between the number of cells, the switchingfrequency and the ripple current.

VDC

vAr

Frequency [kHz]Fig. 12. Frequency analysis of the ripple current. The frequency of theripple current on each arm inductor is determined by the equivalentswitching frequency ftc_eq = nfc.

B. Relationship between the Duty of the Switching Device andthe Ripple Current in the Chopper Circuit
In a general power converter, the ripple current of theinductor is varied by the duty. As an example, in the chopper
circuit, the maximum value, iLm_ch, is given via equations (17)[53].
 i Lpp_ ch Vout_ ch(17)
 iLm_ ch TDon 1  Don 
2

2L

where Vin_ch is the input voltage in the chopper circuit, Vout_ch is
the output voltage, L is the inductance, T is the switching cycle,
Don is the duty of the lower switching device in the chopper
circuit. Note that the average value of the ripple current is set tozero in order to calculate only the ripple component.
C. Definition of Duty in Each Multilevel-voltage Step for
Clarification of the Ripple Current Formula
Equation (17) determines the relationship between the dutyof the switching device and the ripple current of the inductor in
the chopper circuit. In the same way, it is possible to determine
the equation for the ripple current in the MMC based on the
duty of the multilevel voltage. However, the general duties
cannot express the variation of the pulse width in each step of
the multilevel voltage.
As discussed above, the ripple current is varied by changes in
the pulse width, and so it is necessary to define a duty based on

Command5000

D

5 msecMultilevel
voltage1
1  2
2 E cos  f   Vmmc 
1 


2  nVC  3



(20)

[V] 0

D. Clarification of the Ripple Current Formula
In order to determine the formula for the ripple current in thearm inductor, each parameter of equation (21) is replaced asfollows.

Basic level
voltage-5000(is -1)(a) Cell total output voltage on arm

1.000
7
0.875
6
0.750 5
0.625
4
0.500
3
0.375 20.250
10.125 00.000

Duty ofCommand

Vout_ ch  VC , T 

Duty of
Basic level
voltage i Lm (b) Duty of cell total output voltage on arm

0.5

0.0
(c) Duty of cell total output voltage in each step

Fig. 13. Command for the cell total output voltage, the multilevel waveform
for the total output voltage and the basic level voltage. Each duty of the cell
total output voltage and basic level are also shown, as are the duty of the cell
total output voltage in each step, dmlvs.

variations in the pulse width in each step of the multilevel
voltage waveform. Initially, the basic level in each step of themultilevel voltage is applied in order to consider the variationof the pulse width in each of these steps.
Fig. 13(a) shows the multilevel waveform for the cell total
output voltage, vBr, the command waveform for the cell total
output voltage and the basic level voltage. First, the multilevel
waveform is obtained by the command, while the basic level ofthe multilevel voltage in each step is obtained as the lower limitof each step. In other words, in each step, the MMC outputs thepulse voltage based on the basic level.
Fig. 13(b) shows the command duty of vBr as well as the dutyof the basic level voltage. It is also possible to calculate the dutyof the basic level voltage, dmlbl, by equation (18).
1 iS  1
niS  1,2 ,3 n(21)

The maximum value of the ripple current on the arm
inductor,iLm, is given by equation (22).

1.0

d mlbl 

1, Don  d mlvs, , L  La
nfC

(18)

Here is is an index that is varied from 1 to n.
As an example, at n = 8, the step of the multilevel voltage
varies periodically when dmlbl is 0.125, 0.250 or 0.375. Fromequation (18) and Fig. 13, it is apparent that the variation of the
duty in each step, such as at 0.125 and 0.250, is determinedsolely by the number of cells, n.
Fig. 13(c) plots the duty, dmlvs, at each step of the cell total
output voltage, such that dmlvs varies from 0.0 to 1.0 in each step.
This value is derived by taking the difference between thecommand voltage and the basic level, then dividing by thecapacitor voltage. As a result, dmlvs is defined by equation (19).
d mlvs   is  1  nD
(19)
where D is the cell duty which defined by equation (20). Notethat is should be modified according to the number of voltage
levels when the number of voltage levels is changed by themodulation.

VC
d mlvs 1  d mlvs 
2nfC La(22)

In equation (22), the maximum value of the ripple current isvaried by dmlvs, which changes frequently. Therefore, equation(22) generates an envelope of maximum ripple current values.
In addition, the peak value of the ripple current is obtained bydifferentiating equation (22) with respect to dmlvs anddetermining the extremum.
d i Lm
VC1  2 d mlvs (23)
d d mlvs

2nfC La

From equation (23), when dmlvs is 0.5, the formula has anextremum, and iLm reaches its peak value at dmlvs = 0.5.
Fig. 14 shows the multilevel voltage waveform for the cell
total output voltage in one arm, vBr, the duty of the cell total
output voltage in each level, dmlvs, and the waveforms for theripple current, the envelope of the ripple current and thereversed envelope of the ripple current. These data confirm thatthe ripple current envelope calculated by equation (22) traces
the maximum values. The ripple current is also seen to peakwhen dmlvs is 0.5.
Thus, in the design of the arm inductor, the peak value at a
dmlvs of 0.5 is applied as the worst-case design scenario.
VII. EXPERIMENTAL RESULTS FROM A MINIATURE MODEL
A. Verification of the Fundamental Operation of a Step-down
Rectifier Using an MMC
This paper includes the aim of clarifying the validity of
formulae in experiments. Thus, expected circuit operations are
required for the miniature model and experimental waveforms
are shown to confirm fundamental operations.
Table I summarizes the experimental conditions. The
miniature model was constructed using four cells per leg.
Because this was a fundamental experiment, a resister was usedas the MMC load without a smoothing capacitor.
Fig. 15 shows the waveforms for the input phase voltage, theinput R-phase current and the DC output voltage. The
waveforms for the input phase voltage and the input current
confirm that a unity power factor was obtained in the input
stage. The total harmonic distortion (THD) of the input current
was 3.2% when the normalized impedance, %Z, of the arm
inductor was 6.1%. It can also be seen that the output DC
voltage waveform in the lower side of Fig. 15 indicates that the
step-down rectifier converted the input voltage of 200 V into a
constant output DC voltage of 75 V. Therefore, the proposed

Cell total output voltage on arm [V]5000

TABLE IEXPERIMENTAL CONDITIONS

5 msec0-5000
Duty of cell total output voltage in each step
1.0
0.5
0.0
Ripple current on arm inductor [A]Envelope of ripple current

2.0

Rated output powerPO

1000 W

Input line voltage

E

200 Vrms

Input voltage frequency

f

50 Hz

Output voltage

Vmmc

75 V

Number of cell per legn4

DC capacitor

C

1300 F

Load

R

5.3 

Carrier frequency

fC

8 kHz

Arm inductor

La

8 mH (%Z = 6.1%)

Input phase voltage (R-phase) [250 V/div]

10 msec

0

0.0
-2.0

Input phase current (R-phase) [5 A/div]
Ripple current

Reversed envelope of ripple current(a) One cycle

0

Cell total output voltage on arm [V]5000

MMC output voltage [25 V/div]
0500 sec-5000
Duty of cell total output voltage in each step
1.0

0
Fig. 15. Waveforms for input voltage, input current and output voltage.
The unity power factor is obtained in the input stage. The THD of the
input current is 3.2% when the %Z of the inductor is 6.1%.

0.5

Output voltage of all cells in upper side vAr,vAs [250 V/div]

0
0.0
Ripple current on arm inductor [A]Envelope of ripple current0

2.0Line voltage of upper side (A side) vArs [250 V/div]

0.0

0

-2.0
Ripple current

Reversed envelope of ripple current(b) Expanded waveforms
Fig. 14. Multilevel voltage waveform of cell total output voltage in one
arm, duty of cell total output voltage in each step and waveforms of ripple
current, envelope of ripple current and reversed envelope of ripple current.

rectifier for the MMC generated step-down rectification.
Fig. 16 presents the arm voltage waveforms, representing thesum of the output voltages of all cells in each arm, and the
waveform for the line voltage between the R-phase and S-phasein the upper side. The system produces five levels of arm
voltage because one of the H-bridge cells, having unipolar
modulation, produces three levels of voltage and the arm has
two cells. In addition, the waveforms are not symmetricalbetween the positive and negative sides because the output
voltage of the H-bridge cell includes a DC component.

4msec
Fig. 16. Waveforms for arm voltage which is the summation of output
voltage of all cells in each arm and waveforms of line voltage between
R-phase and S-phase in upper side. The arm voltage is five levels andthe line voltage is nine levels.

The waveform for the line voltage between the R-phase andS-phase in the upper side exhibits nine levels. However, themultilevel voltage waveform becomes non-uniform. Thisoccurs because the arm voltage is not symmetrical between
positive and negative, since the cell command voltage includes
the bias of the MMC output voltage control. However, thevoltage fluctuation is still small compared to that obtains whenemploying chopper cells or H-bridge cells with bipolar
modulation. Thus, the MMC allows size reduction of the arm

Capacitor voltage (R-phase) [50 V/div]
vcAr1, vcAr2, vcBr1, vcBr2,

130 V

10 msec0
Fig. 17. Waveforms for the capacitor voltage in the R-phase leg. The
proposed system maintains the capacitor voltage of each H-bridge cell tothe voltage command of 130 V. In addition, the maximum voltage error
between the capacitor voltage command and the measured voltage is 2%
or less.

Capacitor voltage (R-phase) [50 V/div]
vcAr1, vcAr2, vcBr1, vcBr2,

130 V

0

5 msecFig. 18. Waveforms for the ripple voltages of all capacitors that areconnected to the R-phase leg. In principle, each capacitor in the MMC has
a low frequency ripple voltage because the frequency of the ripple voltage
is based on the frequency of the input voltage source.

inductor s.
Fig. 17 plots the waveforms for all cell capacitor voltages
that are connected to the R-phase leg. The cell capacitor voltage
is controlled by the capacitor voltage command, vc*. As a result,the proposed step-down rectifier maintains the capacitor
voltage of each H-bridge cell to the voltage command level of
130 V. Therefore, the proposed rectifier also achieves capacitor
voltage control. In addition, the maximum voltage error
between the voltage command of the cell capacitor and themeasured voltage is 2% or less.
Fig. 18 shows the waveforms for the ripple voltages of all
capacitors that are connected to the R-phase leg. In principle,
each capacitor has a ripple voltage whose frequency is based on
the frequency of the input voltage. From the waveforms for theripple voltages, the low frequency waveforms for the ripple
voltages are shown, as in the above discussion. In addition,
there is some error among the capacitor voltages. However, as
already discussed in Fig. 17, the voltage errors among all thecapacitors are negligibly small compared to the average valueof the capacitor voltages.
B. Verifications of the Theoretical Formula for the Ripple
Current in the Capacitor
In this section, the results obtained from the theoreticalformula for the capacitor ripple current are presented. In orderto evaluate the ripple current of the capacitor, a frequency
analysis of the capacitor voltage was conducted because it isdifficult to measure the ripple current of the capacitor directlyin the miniature model. However, because the ripple voltage iscaused by the ripple current, the validity of the formula can still
be verified if the measured ripple voltage and the theoreticalvalue obtained from equation (3) are shown to be the same. The
fundamental frequency component and the second-orderfrequency component of the ripple voltage which is given byequation (3) are compared with the measured values.
Fig. 19 shows a comparison of the theoretical and measured
values of the fundamental frequency component in the ripple
voltage. The experimental data agree with the theoretical values
in a small error, with a maximum error of 4.3 %.
Fig. 20 compares the theoretical and measured second-orderfrequency components. Here, the difference between thetheoretical and experimental values is large, with a maximum
error of 34.2%. This is significant error results from themismatch of the input active power and the output power due tothe semiconductor loss and the inductor loss.
Fig. 21 shows a comparison of the theoretical and measured
second-order frequency components based on the input active
power. The value of input active power is assigned to thevariable P in equation (3). Here, the maximum error is reduced
to 4.1%, and this establishes that the high error in Fig. 20 wascaused by the mismatch of the input active power and theoutput power due to the semiconductor loss and the inductor
loss. In the design of a practical converter, all losses must be
minimized in order to obtain high efficiency. Thus, the error in
the second-order frequency component based on the output
power is small because of the low loss.
The above results demonstrate the validity of the formula forthe capacitor voltage ripple. These data also confirm that the
ripple current of the capacitor can be calculated exactly by thetheoretical formula.
C. Verification of the Theoretical Formula for the Ripple
Current in the Arm Inductor
In this section, the results for the ripple current in the arm
inductor are assessed.
Fig. 22 shows the expanded waveforms for the lower arm
voltage in the R-phase and the arm current. The arm voltage isthe total output voltage of the two cells. The expanded
waveform focuses on the output voltage, for which the duty ineach step of the cell total output voltage, dmlvs, is 0.5 (equivalent
to the point at which the ripple current reaches its maximum).
As shown in Fig. 22, the measured peak-to-peak value of theripple current was 118 mA. The theoretical value obtained bydoubling the result from equation (22) is 124 mA, the doubling
being applied because the peak-to-peak value is twice themaximum value. Thus, the error between the theoretical andmeasured values is 4.9%. Note that the inductance used inequation (22) is determined at a frequency of 32 kHz because
this is the equivalent frequency of one arm in the miniaturemodel. Moreover, unipolar modulation is applied to each cell.

Ripple voltage offundamental frequency component [V]

7.0
7.0

Capacitor voltage : 104 V, Inductance : 6.6 mH @ 32 kHz
The number of cells per leg : 4
Carrier frequency : 8 kHz (Output frequency of cell : 16 kHz)

Theoretical value

6.0
6.0
5.0
5.0

Voltage of lower arm on R-phase [100 V/div]

Measured value

4.0
4.0

0

3.0
3.0

10 sec

2.0
2.0

Maximum error :
4.3%

1.0
1.0
0.0
0.0

00

200
200

0

400
600
800
400
600
800
Output power [W]

1000
1000

Ripple current in arm current [50 mA/div]

Ripple voltage of
second-order frequency component [V]Fig. 19. Comparison of theoretical values and measured data for thefundamental frequency component of the ripple voltage. The maximum
error between the theoretical and measured values is 4.3%.

1.0
1.0
Measured value

Fig. 22. Waveforms for lower arm voltage in R-phase and arm current.
The expanded waveforms focus on the output voltage of which the duty ineach step of the cell total output voltage, dmlvs, is 0.5. The error between
the theoretical value and the measured value is 4.9%.
0.18
0.18

0.8
0.8

0.16
0.16

Ripple current [A]

0.6
0.6

0.14
0.14

Theoretical value

0.4
0.4

Theoretical value

0.12
0.12

0.2
0.2
0.0
0.0

iLpp=118 mA

1200
1200

0.10
0.10

Maximum error : 34.2%

00

200
200

400
600
800
400
600
800
Output power [W]Maximum
error :
11.8%

1000
1000

1200
1200

Fig. 20. Comparison of theoretical and measured values for thesecond-order frequency component in the ripple voltage. The maximum
error between the theoretical value and the measured value is 34.2%. The
cause of the large error is the mismatch of the input active power and theoutput power due to the semiconductor loss and the inductor loss.

Measured value

0.08
0.08
0.06
0.06
80
80

90
90

100
110
100
110
Capacitor voltage [V]

120
120

130
130

Fig. 23. Comparison of the theoretical and measured ripple currents in thearm inductor against capacitor voltage. The maximum error is 11.8%.
This error results because the inductance decreases due to the decrease of
the permeability as the core temperature is raised.

Ripple voltage of
second-order frequency component [V]1.0
1.0
Measured value

0.8
0.8
0.6
0.6
Theoretical value

0.4
0.4
0.2
0.2
0.0
0.0

Maximum error :
4.1%

00

200
200

800
600
400
400
600
800 1000
1000
Input active power [W]

1200
1200

Fig. 21. Comparison of the theoretical and measured values of thesecond-order frequency component based on input active power. The
maximum error between the theoretical and measured values is 4.1%.

Fig. 23 compares the theoretical and experimentally
determined ripple currents in the arm inductor against thecapacitor voltage. In the low voltage region, the error is 10% orless while, in the high voltage region, the error is increased to a
maximum value of 11.8%. Although the theoretical values
increase linearly, the measured values exhibit non-linear

growth. Note that, at higher voltages, the experimental values
are larger than the theoretical values. This is caused by adecrease in the inductance due to the characteristics of the core.
In general, the permeability of the core will vary withtemperature. In the experimental trials, the magnetic flux
values increased due to the increase in the capacitor voltage,
thus elevating the iron loss of the core. As a result, the coretemperature was higher at high voltage. Thus, the inductancedecreased due to the decreased permeability at higher coretemperatures.
D. Verification of the Theoretical Formulae for
Semiconductor Losses
In this section, the theoretical values of the semiconductor
losses are assessed. In these experiments, the semiconductor,
the arm inductor and no-load losses were considered. The
no-load loss was measured as the MMC operated without theconverter being connected to the load. In this state, the input
power is defined as the no-load loss. The input power, output
power and inductor loss were measured simultaneously as the
MMC was operated with the converter connected to the load.
By subtracting the output power, the inductor loss and theTABLE II
CIRCUIT PARAMETERS AND LOSS PARAMETERS FOR VERIFICATION
Input line voltage
E
200 Vrms The number of cells n 4 /legCapacitor voltage VC
135 V
Load resistanceR 5.2 Carrier frequency
fC
8 kHz
Output powerPO
200 - 1000 W
Switching device
FGW30N60VD
Drop voltage of switch
V0_SW
0.74 V @ Tj =25 °C
Resistance of switch
RSW
0.0536 @ Tj =25 °C
Drop voltage of FWD
V0_FWD
0.8 V @ Tj =25 °C
Resistance of FWD
RFWD
0.0492 @ Tj =25 °C
Turn-on energy of switch
won
52.98 J@Vdcd=135 V Imd=6.7 A
Turn-off energy of switch
woff
31.97 J@Vdcd=135 V Imd=8.3A
Turn-on energy of FWD
wrr
6.21 J@Vdcd=135 V Imd=0.6 A

Semiconductor loss [W]

160
160

140
140

Maximum
error :
6.1%

120
120

100
100

Measured value

80
80

Theoretical value

60
60
40
40

00

200
200

400
600
800
400
600
800
Output power [W]

1000
1000

Fig. 24. Comparison of theoretical and measured semiconductor losses.
The maximum error is 6.1%. This error is attributed to losses from theequivalent series resistance (ESR) of the capacitor and the wiring loss,
which are not considered in the calculations.

200
200

180
180
160
160
140
140

Loss [W]no-load loss from the input power, the semiconductor loss isobtained.
Table II summarizes the circuit and loss parameters usedduring the verification of the semiconductor loss equations. The
loss parameters relating to the conduction loss were obtained
from the datasheets for the switching devices, whereas theswitching and recovery loss parameters were obtained from theexperimental values generated by switching tests.
Fig. 24 compares the experimental and theoretical values.
The theoretical value is defined as the sum of the conduction,
switching and recovery losses in all cells. The maximum error
is seen to be 6.1%. However, over the entire range, themeasured values are larger than the theoretical results. This is
attributed to losses via the equivalent series resistance (ESR) of
the capacitor and the wiring loss, neither of which areconsidered in the measurements. Thus, the experimentally
determined semiconductor losses include losses that are notconsidered, and so these measured values are greater than thetheoretical ones. The differences between the measured andtheoretical data are also seen to increase as the output powerincreases. This occurs because both the loss in the capacitor andthe wiring loss increase with increasing the output power, due
to greater values of the ripple current of the capacitor and thearm current.
Fig. 25 shows a breakdown of the losses in the MMC. The
no-load loss is constant against changes in the output power,
while the semiconductor and inductor losses both increase withincreases in the output power because the arm current is higher.
From these results, it is evident that the semiconductor loss
represents the majority of the overall losses. Therefore, thedesign should attempt to minimize the semiconductor loss inorder to achieve the highest possible efficiency and volume
reduction because the semiconductor loss and the volume of theheat sink are simultaneously reduced. One means of reducing
the semiconductor loss is to decrease the arm current by raising
the MMC output voltage, because the semiconductor loss isgreatly affected by the arm current.

120
120

Semiconductor
loss

100
100
80
80

VIII. VOLUME EVALUATION OF THE MMC AND

60
60

CLARIFICATION OF CONDITIONS FOR VOLUME REDUCTION40
40

In this chapter, the volumes of the capacitor, the arm inductor
and the heat sink are evaluated. Moreover, based on the results,
the conditions required to obtain the highest power density are
established.
With regard to evaluating the capacitor volume, thediscussion in Chapter IV has already established that it isimportant to select the number of cells for which the voltage
rating ratio is maximized in order to achieve volume reduction.
In addition, the changes in the capacitor volume must be
evaluated as the MMC output voltage is varied.
In this stage of the work, the total volume of the arm inductor
and the heat sink were evaluated by the Pareto front
optimization. It is often possible to reduce the inductor volume
when the carrier frequency increases because this lowers the
ripple current. However, the heat sink volume actually
increases in the present scenario because the switching loss

20
20
00

Inductorloss

No-load
loss
1

200
2

400
600
800
3
4
5
Output power [W]1000
6

Fig. 25. Breakdown of losses in the MMC. The no-load loss is constantdespite varying the output power. In contrast, the semiconductor andinductor losses increase with increases in the output power because thearm current is elevated.

increases as a result of the high switching frequency. Hence, theheat sink volume and the inductor volume have a trade-off
relationship. Furthermore, the efficiency also decreases due tothe high switching loss, although the power density increases
because the inductor volume is lowered. Therefore, in thisstudy, the maximum power density was assessed based onusing the Pareto front optimization [50].

B. Evaluation of the Overall Volume
In this section, the capacitor volume, the heat sink volume
and the volume of the arm inductor are evaluated to establish
the necessary conditions for volume reduction. Note that the
curve of the Pareto front includes only the total volume of theheat sink and the arm inductor so as to evaluate only the change
in the total volume. The overall volume including the capacitor
volume is subsequently evaluated.
Fig. 26 shows the capacitor volume as a function of the
MMC output voltage. The numbers under the graph indicate thenumber of cells for which a 1.7 kV IGBT is available. The
capacitor volume is seen to decrease as the MMC output
voltage increases even when the number of cells is kept
constant. This is attributed to the decrease in the ripple current
as the arm current decreases even at the same power rating. As aresult, it is possible to reduce the capacitor volume bydecreasing the required number of parallel connected
capacitors. Moreover, the capacitor volume is small when thevoltage rating ratio is high, as explained in Chapter IV. Thus,
the number of cells should be determined based on the voltage
rating ratio in order to reduce the capacitor volume.
Fig. 27 presents the Pareto front curve when the MMC

Table III
CONDITIONS OF OVERALL VOLUME EVALUATIONPower capacity
S
200 kVA
Input line voltage
E
6.6 kV
Input frequencyf
50 Hz
Input power factor f
1.0Electrolytic capacitor
Model number
ERWF401LGC182MC85M
Voltage rating
30% margin against charge voltage
Raise value of inside temperature
25 °C (Recommended value)
Arm inductor
Ripple current factor
5%
Flux density
1.56 T
Constant value
17.9
Current density
4 A/mm2
Window utilization factor
0.3Core type
C coreHeat sink
Switching device
Infineon FF, FZ series and Hitachi 2.5 kV IGBT
Operation junction temperature
80% of maximum temperature.
Voltage rating
80% more than capacitor voltage
Current rating
Twice value as rated current.
CSPI
3.0 (Natural air cooling)

Total volume of capacitors [dm3]

250
250

1153

1009
1200

897
1200

Capacitor : ERWF401LGC182MC85M(NIPPON-CHEMICON)
Inside temperature raise : 25 °C or less
Switching device : 1.7 kV-IGBT

200
200
1200

150
150

1195
1200

929
1200

1045
1200

100
100

1081
1200

961
1200

50
50

00

1
14
The numberof cells

2
16
400 V

3
18

4
14

5
16
800 V

6
18

7
8
16
18
1200 V

MMC output voltage

Fig. 26. Change in the capacitor volume against the MMC output voltage. The
values under the graph indicate the number of cells for which a 1.7 kV IGBT isavailable. At the same output voltage, the capacitor volume is small when thevoltage rating ratio is high.
2.5 kV
12 10

96
95

Efficiency [%]A. Conditions for Evaluation of the Overall Volume
Table III shows the conditions of the overall volume
evaluation. The detailed design conditions employed whenevaluating the overall volume consisted of the following:(1) an input line voltage of 6.6 kV and an MMC power capacityof 200 kVA,(2) the capacitor was the NIPPON-CHEMICON model
ERWF401LGC182MC85M and the voltage rating of the single
capacitor was 400 V with a rated ripple current of 5 A at afrequency of 50 Hz [54],(3) the increase in the internal temperature was limited to 25 °C
based on the manufacturer’s recommendations,(4) the number of parallel connected capacitors was selected so
as to ensure a capacitor lifespan of at a least decade,(5) the charge voltage of the capacitor was calculated byequation (2) and the voltage rating included a 30% margin
against the charge voltage while the number of series connected
capacitors was determined based on the voltage rating,(6) the voltage rating of the switching device was set at 80%
more than the charge voltage of the capacitor and the current
rating was set at twice the rated value of the arm current,(7) the carrier frequency was varied from 10 Hz to 190 kHz,(8) the loss data at the maximum junction temperature wasobtained from each datasheet and the allowable junction
temperature was set at 80% of the maximum allowable value[55]-[56],(9) the heat sink was designed based on the CSPI [51] and the
CSPI value was assumed to be 3.0 (natural air cooling),(10) the loss data for the SiC-MOSFET was obtained from theloss characteristics of a single chip [57]-[58], so that the parallel
connection number of the chip was determined in order to meetthe conditions of the current rating, and(11) the maximum junction temperature of the SiC-MOSFET
was set at 175 °C.

5.2 kHz18 16 14

1.7 kV94
93

1.2 kV
20
22

92

24

3.3 kV SiC
8

91
90
89
0.0

3.3 kV
8

0.5

1.0

1.5

2.0

2.5

3.0

3.5

Power density [kw/dm3]
Fig. 27. Pareto front curve for an MMC output voltage of 800 V. The power
density of the converter applied to the 3.3 kV SiC is approximately two times
higher compared to the converter applied to other switching devices.

output voltage is 800 V. The power density of the converter
applied to the 3.3 kV SiC is approximately two times higher
than that of a converter applied to other switching devices. A
high efficiency is also obtained at a switching frequency of 5.2
kHz because the converter applied to the 3.3 kV SiC reduces

14 12 10 2.5 kV

5.9 kHz97
18 16

1.7 kV

Efficiency [%]

96
20
22
24
1.2 kV95

3.3 kV SiC
894
3.3 kV
8

93
92
0.0

0.5

1.5

1.0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

Power density [kw/dm3]
Fig. 28. Pareto front curve at an MMC output voltage of 1200 V. All
switching devices achieve higher power density and higher efficiency
compared to the evaluation result with the MMC output voltage of 800 V.
14 12 10 2.5 kV

97

1.7 kV18 16
400 HzEfficiency [%]96

360 Hz540 Hz500 Hz470 Hz20
22
24
1.2 kV95
94

3.3 kV
8

93
92
0.0

0.5

1.0

1.5

2.0

2.5

3.5

3.0

Power density [kw/dm3]
Fig. 29. Expanded Pareto front curve at an MMC output voltage of 1200 V
without a 3.3 kV SiC. The converter applied to a 1.7 or 1.2 kV IGBT
produces a higher power density except for the 3.3 kV SiC. Moreover, both
1.7 and 1.2 kV IGBT produce the highest power density when the lowest
number of cells is employed.
1081
1200

160
160

961
1200

865
1200

786
800

721
800

140
140
120
120

Volume [dm3]the volumes of both the heat sink and the arm inductor, since
SiC devices exhibit especially low losses and can operate at
higher switching frequencies.
Fig. 28 plots the Pareto front curve at an MMC output
voltage of 1200 V. The converter applied to the 3.3 kV SiC also
generates a higher power density and obtains high efficiency
relative to that of other high voltage IGBTs, for the same
reasons as outlined when discussing the MMC output voltageof 800 V. Higher power density and greater efficiency areachieved in all switching devices compared to the results in thecase of an MMC output voltage of 800 V. The main reason forthis is the decreased semiconductor loss and the heat sinkvolume decrease because of the decrease in the arm current
upon raising the MMC output voltage.
Fig. 29 shows the expanded Pareto front curve at an MMC
output voltage of 1200 V without a 3.3 kV SiC. The 3.3 kV SiC
has the highest performance in terms of a low switching loss
and high frequency switching. However, it is still difficult toapply a 3.3 kV SiC to a practical system because theseswitching devices are not yet readily available. The voltage
stress of the arm inductor should be kept low for isolation
protection because this stress is high when a 3.3 kV SiC isapplied to the MMC. In the case that a 3.3 kV SiC is excluded
from consideration, a 1.7 or 1.2 kV IGBT is the most preferable
selection if the aim is to achieve high power density. In order toapply a 1.7 kV IGBT, the number of cells should be 16 or 18,
whereas there should be 20, 22 or 24 cells in the leg when using
1.2 kV IGBT. Both IGBTs produce the highest power density
when the design quantity of cells is kept to a minimum. A
feature of multilevel converters is that it is possible to decrease
the switching loss and the recovery loss by increasing thenumber of cells. However, within the range of cell quantities
that can be employed in the same switching device, thepotential decreases in the switching and recovery losses islimited because the charge voltage of the capacitor does notchange drastically, which leads to a small volume reduction. To
sum up, it is possible to slightly reduce the volume of a single
heat sink by increasing the number of cells, but the total volumeof the heat sink increases upon increasing the total number ofcells. It is also difficult to reduce the volume of the arm
inductor when using the same switching devices, even if thenumber of cells changes, because the ripple current in the arm
inductor does not change drastically. Therefore, in order toreduce the total volume of the heat sink and the arm inductor, itis necessary to select the smallest number of cells for which theselected switching device is available.
Fig. 30 presents a breakdown of the overall volume when the
MMC output voltage is 1200 V and a 1.7 or 1.2 kV IGBT isused. Comparing the volumes of the conventional powersystem and the MMC, it can be concluded that the MMC allows
a 90% volume reduction if the 1.2 kV IGBT is employed inconjunction with 22 cells per leg. Furthermore, it is apparent
that the capacitor volume is the largest component of theoverall volume and that the variation in the capacitor volume
with different devices and numbers of cells is remarkably high.
These results demonstrate that, as the first step of the design of
the MMC, it is necessary to focus on selecting the number of

100
100

Capacitor

80
80
60
60

Inductor

40
40
20
20

00

Heat-sink
The number
1of cells

16
18
24
20
22
2
3
4
5
6
1.7 kV IGBT
1.2 kV IGBT
Fig. 30. Breakdown of the overall volume for an MMC output voltage of1200 V and a 1.7 or 1.2 kV IGBT. The change in the capacitor volume isparticularly large. From the above results, the first step in the design of the
MMC should focus on the number of cells for which the capacitor volume
is small based on the voltage rating ratio.

cells at which the capacitor volume is small based on thevoltage rating ratio. Subsequently, the number of cells forwhich the volumes of both the heat sink and the arm inductor
are minimized should be considered. Finally, these data
confirm the effectiveness of the design flow proposed inChapter III as a means obtaining high power density with an
MMC.
IX. CONCLUSION
This paper presented a design criteria to obtain the highpower density in a step-down rectifier incorporating an MMC.
Readily available commercial electrolytic capacitors were used.
The work focused on the relationship between the volume andthe number of cells. The major contributors to the overall
volume of the MMC were found to be the heat sink, thecapacitor and the arm inductor.
A flowchart for the high power density design process wasconstructed, based on assessing the capacitor, the heat sink andthe arm inductor. This process omitted recalculation of thecapacitor volume by employing a database containing capacitor
volumes as functions of the number of cells.
In the evaluation of each component, theoretical formulae
were generated and their validity confirmed based on
experimental data obtained from a miniature model of the
MMC. The following results were produced.
(a) When verifying the ripple voltage of the capacitor, there
was a maximum error of 4.3% between the theoretical andmeasured values. Because the ripple voltage is caused by theripple current, it is possible to accurately calculate the ripple
current of an electrolytic capacitor using the theoreticalformula.
(b) With regard to the ripple current in the arm inductor,
there was a maximum error of 11.8%, caused by changes in thecore characteristics. Therefore, it is possible to calculate theripple current with a high degree of accuracy by considering theinductance changes resulting from the variations in the corecharacteristic.
(c) In the case of the semiconductor losses, there was a
maximum error of 6.1%, showing that it is possible to calculate
the semiconductor losses while designing the heat sink.
The overall volume of circuit devices, including thecapacitor, the heat sink and the arm inductor, was evaluated. In
particular, the capacitor volume was examined against the
number of cells and the MMC output voltage. In addition, thetotal volume of the heat sink and the arm inductor wasinvestigated using the Pareto front optimization. It wasdetermined that the following conditions must be satisfied inorder to achieve high power density:(i) employing a capacitor with a small rated ripple current
and increasing the quantity of parallel connected capacitors,(ii) maximizing the voltage rating ratio, whose maximum
value is 1.0,(iii) selecting a 1.7 or 1.2 kV IGBT as the high voltage
switching devices, and(iv) using the smallest number of cells for which a selectedswitching device such as 1.7 or 1.2 kV IGBT is available.
Finally, when a 3.3 kV SiC is applied to the MMC, it ispossible to obtain a higher power density compared to the useof other high voltage IGBTs. In the future, the cost reduction of
the 3.3 kV SiC may allow this design to be considered and sofurther miniaturization is expected when a high performanceswitching device such as a 3.3 kV SiC is applied to the MMC.
It is expected that the results of this paper promote thediscussion of the design criteria focused on the number of cells
and the output voltage of the MMC for the high power density.
In particular, the design criteria of the electrolytic capacitor, thevolume comparison of the electrolytic capacitors and the film
or ceramic capacitor and the usability of the electrolytic
capacitor in the MMC will be promoted by this paper.
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Toshiki Nakanishi received the B.S.
degrees in electrical, electronics andinformation engineering from Nara
National College of Technology (NNCT),
in 2011. He received master degrees in
Nagaoka University of Technology (NUT).
And he has been in doctoral course of NUT.
He is the student member of IEEJ and IEEE.
His main research interests include multilevel converters.
Jun-ichi Itoh received his M.S. and PhD
degrees in electrical and electronic systems
engineering from Nagaoka University ofTechnology, Niigata, Japan in 1996 and2000, respectively. From 1996 to 2004, he
was with Fuji Electric Corporate Researchand Development Ltd., Tokyo, Japan. Since
2004, He has been with Nagaoka Universityof Technology as an associate professor. He received the IEEJ
Academic Promotion Award (IEEJ Technical Development
Award) in 2007 and the Isao Takahashi Power Electronics
Award in 2010. His research interests include matrix converters,
DC/DC converters, power factor correction techniques andmotor drives. He is a senior member of the Institute ofElectrical Engineers of Japan and the Society of Automotive
Engineers of Japan.