D21m System

6.3

Digital I/O Cards

6.3.1

AES/EBU M2 Cards (,,)

A949.0454/.0455/.0456		
A949.0454xx
A949.0455xx
A949.0456xx		

AES/EBU input/output card with 16 Ch I/O, available in 3 different versions:
without SRCs (Vista only)with input SRCs onlywith input and output SRCs (see adjacent picture).
Selectable output sampling rates: 96 kHz, 48 kHz, 44.1 kHz, or external reference (22-108 kHz). Input and output SRCs can individually be bypassed perchannel pair. Output dither and word length is selectable for every AES/EBUoutput to 24, 20, 18 or 16 bit (when the output SRC is enabled). Settings are
made with DIP switches. Inputs and outputs are on standard 25-pin D-typeconnectors (female).

SRC Delay

Enabled input and output SRCs each cause a delay (D) that depends on theSRC’s input and output sampling rate (fS_IN and fS_OUT). Input and output delays
can be calculated using the following formulas.

[1] fS_IN > fS_OUT : D = 16 + 32 [s]fS_IN fS_OUT		

[2] fS_OUT > fS_IN : D = 48 [s]fS_IN

Examples:For a 96 kHz input signal and a 48 kHz system clock (i.e., the ‘output signal’of the input SRC), input delay is 40 output samples or 0.833 ms (formula [1]).		
For a 48 kHz system clock (i.e., the ‘input signal’ of the output SRC) and a
96 kHz output signal, output delay is 96 output samples or 1 ms (formula [2]).

AES Out 1

AES Out 8

AES Tx 1

SRC Out 1*

AES Tx 8

SRC Out 8*

Clock Selection*
96 k, 48 k, 44.1 k, ext.

AES In 1

AES In 8

AES Sync In *36

AES Rx 1SRC In 1**

AES Rx 8

SRC In 8**

AES Rx Sync*

Word Length Sel.*24, 20, 18, 16 bit

SRC Bypass*** for A949.0456xx only

Z, C, U bit location

Backplane Connector		
Input / output impedance
110 Ω		 Input sensitivity		
min. 0.2 V		 Output level (into 110 Ω)
4.0 V		 THD + noise		max. –115 dB		 SRC range		
22-108 kHz		 Current consumption (3.3 V) A949.0454: 0.43 A/.0455: 0.67 A/.0456: 0.94 A			(5 V)
0.45 A		 Operating temperature
0-40 °C** for A949.0455xx and A949.0456xx onlyDocument generated: 04.03.15

D21m System

Factory Default Setting:

LEDs

LOCK 1-8

DIP Switches
S1 (C+U Bits in Audio)

not fitted

OFFOFFOFF

OFFOFF

OFF

OFF

OFF

not fitted
OFFOFF

OFF

OFF

OFF

These green LEDs are on if a valid AES/EBU signal is available at the inputs.
Specifies the usage of the ZCU bits. If OFF, the audio is standard 24 bit PCM;
if ON, the LSBs of the audio carry the ZCU bits. This setting both defines atwhat position the ZCU bits are inserted (receiver) and which bits are used togenerate the transmitted ZCU bits (transmitter). Default setting: all OFF.

S2 (C+U Bits Source)

If OFF, a static, default ZCU pattern is generated at the transmitter side. IfON, the ZCU bits of the routed source (position depending on setting of S1)
are used. Default setting: all OFF.

S3 (Input SRC Bypass)(A949.0455 and A949.0456 only) Bypassing (ON) or enabling (OFF) of theSRCs for individual AES/EBU input channels (i.e. audio channel pairs 1+2,3+4, etc.). Default setting: all OFF.

S4 (Output SRC Bypass)(A949.0456 only) Bypassing (ON) or enabling (OFF) of the SRCs for individual AES/EBU output channels (i.e. audio channel pairs 1+2, 3+4, etc.).
For output word length reduction the output SRCs must be enabled. Refer tothe paragraph below. Default setting: all OFF.

S5, S6 (Output Sample Rate)(A949.0456 only) Used for setting the sample rate for the AES/EBU outputchannels (i.e. audio channel pairs 1+2, 3+4, etc.). Corresponding switches
on S5 and S6 are used in pairs for each AES/EBU channel, according to thefollowing table and the silkscreen on the PCB. Default setting: All OFF, corresponding to 48 kHz.
S5.x
OFFOFFONON				
Document generated: 04.03.15

S6.x
OFFONOFFONOutput Sample Rate
48 kHz96 kHz44.1 kHz
External AES sync

If no valid signal is provided at the AES EXT SYNC IN connector but external sync is selected, the output sampling rate will be set to the system clock.
Outputs set to ‘external’ can therefore be used in a very flexible way: Connect
37D21m Systemno external sync signal if not necessary, and the output will be clocked with
the internal system clock. As soon as an external sync signal is provided tothe AES EXT SYNC IN connector, the output will automatically be clocked
by the extermal sync signal.
S7, S8 (Output Word Length)(A949.0456 only) Used for setting the resolution (output word length) for
the AES/EBU output channels (i.e. audio channel pairs 1+2, 3+4, etc.). Corresponding switches on S7 and S8 are used in pairs for each AES/EBU channel, according to the following table and the silkscreen on the PCB. Default
setting: All OFF, corresponding to 24 bit.
S7.x
OFFOFFONONNoteS8.x
OFFONOFFONOutput Word Length
24 bit20 bit18 bit16 bitFor word length reduction the output SRCs must be set to enabled’; if so, theoutput word length is always 21 bit maximum. Whenever an SRC is enabled,
the three least significant bits (LSB) are set to digital zero. This results in thespecified dynamic range of 120 dB.

Special Channel Status and User Bits Data Management		 Some intercom systems use a standard AES stream to link control panels tothe main base station. In addition to the audio, control data is encoded into
the user bits of the AES stream. In order to allow an intercom remote control
panel to be transmitted from a Studer stagebox to the base station, a special
mode is available on these AES cards.		

The channel status and users bits (CU bits) are extracted at the receiver side.
Depending on the setting of DIP switch S1, the CU bits are either embedded into the two bottom LSBs of the audio (S1 = ON) or sent to the D21m
backplane (S1 = OFF). In addition, the channel status data block start (Z bit)is also embedded into the bottom LSB of the audio to allow recovery of theblock start at the destination AES transmitter. If the ZCU bits are embedded
into the audio, the audio word length is reduced to 20 bits.

Note

The resulting audio data contains non-audio information in the four bottom
bits of the 24 bit audio word and thus is no longer fully PCM. This non-PCM
signal may be routed through Studer routers and the routing part of all Studer
audio mixing systems, but will not pass through any active processing suchas a channel path or sample rate converter.		

At the output side, an additional DIP switch (S2) allows the selection of thesource of the transmitted ZCU bits. Either a default, static pattern (S2 = OFF)or the ZCU bits available from the backplane are encoded (S2 = ON). If S2
is ON then the bits from the position specified with S1 are encoded.		 The following diagram illustrates the various DIP switches and their effectupon the data path.

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Document generated: 04.03.15

D21m System

Insert ZCU bits either in the LSB of the audio
or in the spare bits (dedicated position)
OFFZCU in Audio
S3SRCAudioZCU in Ded.Pos.

ONTo Backplane

OFFC+U Bit in audio

ZCU

RX SRC Bypass

S7/8

24 bit20 bit18 bit16 bitTX SRC Bypass

48 kHz96 kHz44.1 kHzExt.

SRC

S4AudioOFF

S5/6

AES/EBU Output

ON
S2

ZCU

OFF

C+U Bit Source

ONAudioON

S1AES/EBU Input

ON
S10000

ZCU
ZCU
Gen.

OFF

ZCU in Audio

From Backplane

ZCU in Ded.Pos.

Extract ZCU bits either from the LSB of the audio
or from the spare bits (dedicated position)‘Not indicated’ except:- Professional Mode
- No Emphasis

Connector Pin Assignment		
AES IN/OUT (2 × 25pin D-type, female, UNC 4-40 thread)2513

Solder/Crimp View
(or Socket View)

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Document generated: 04.03.15

1Pin
12345678910111213

Signal ‘CH 1-8’
CH 7/8 out +CH 7/8 out screen
CH 5/6 out –CH 3/4 out +CH 3/4 out screen
CH 1/2 out –CH 7/8 in +CH 7/8 in screen
CH 5/6 in –CH 3/4 in +CH 3/4 in screen
CH 1/2 in –n.c.

Signal ‘CH 9-16’
CH 15/16 out +CH 15/16 out screen
CH 13/14 out –CH 11/12 out +CH 11/12 out screen
CH 9/10 out –CH 15/16 in +CH 15/16 in screen
CH 13/14 in –CH 11/12 in +CH 11/12 in screen
CH 9/10 in –n.c.

Pin Signal ‘CH 1-8’
14 CH 7/8 out –15 CH 5/6 out +16 CH 5/6 out screen
17 CH 3/4 out –18 CH 1/2 out +19 CH 1/2 out screen
20 CH 7/8 in –21 CH 5/6 in +22 CH 5/6 in screen
23 CH 3/4 in –24 CH 1/2 in +25 CH 1/2 in screen

Signal ‘CH 9-16’
CH 15/16 out –CH 13/14 out +CH 13/14 out screen
CH 11/12 out –CH 9/10 out +CH 9/10 out screen
CH 15/16 in –CH 13/14 in +CH 13/14 in screen
CH 11/12 in –CH 9/10 in +CH 9/10 in screen

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