TECHNICAL DATA SHEET

Quartz 5953
3U VPX 8-channel A/D & D/A board
with Xilinx Zynq UltraScale+ RFSoC - Gen 3

Data conversion andprocessing solution
on a single chip

▪ High-bandwidth data streaming▪ Waveform signal generator▪ Analog I/O for digital recording andplayback▪ Communication receiver and transmitter▪ Sensor interfaces▪ Electronic Warfare transponder

The Quartz® 5953 is a high-performance 3U OpenVPX board basedon the Xilinx Zynq UltraScale+ RFSoC FPGA. The RFSoC integrates
eight RF-class A/D and D/A converters into the Zynq’s multiprocessor
architecture, creating a multichannel data conversion and processing
solution on a single chip. The 5953 brings RFSoC performance to 3U VPX
with a complete system on a board.
Complementing the RFSoC’s on-chip resources are the 5953’s sophisticated clocking
section for single board and multiboard synchronization, a low-noise front end for RF
input and output, up to 16 GB of DDR4, a PCIe interface, a gigabit serial optical interface
capable of supporting dual 100 GigE connections, and general-purpose serial and parallel
signal paths to the FPGA.

BOARD ARCHITECTURE
The 5953 board design places the RFSoC as the cornerstone of the architecture. All control anddata paths are accessible by the RFSoC’s programmable logic and processing system. A fullsuite of IP and software functions utilize this architecture to provide data capture, timing, andinterface solutions for many of the most common application requirements.

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TECHNICAL DATA SHEET
Quartz 5953

FEATURES

EXTENDABLE IP DESIGN▪ Incorporates Xilinx® Zynq® UltraScale+™

For applications that require specialized functions, users caninstall their own custom IP for data processing. The Navigator
FPGA Design Kit (FDK) includes the board’s entire FPGA design
as a block diagram that can be edited in Xilinx’s Vivado® IP
Integrator. In addition to the IP Integrator block diagrams, allsource code and complete IP core documentation is included.
Developers can integrate their own IP along with the factoryinstalled functions or use the Navigator kit to completely
replace the IP provided by Mercury with their own.

Gen 3 RFSoC▪ 16 GB of DDR4 SDRAM▪ On-board GPS receiver▪ PCI Express (Gen. 1, 2 and 3) interface up to x8▪ LVDS connections to the RFSoC for custom I/O▪ Optional VITA 66.4 optical interface for backplane gigabit
serial communication▪ Dual 100 GigE UDP interface▪ Compatible with several VITA standards including: VITA 46,
VITA 48, VITA 66.4, VITA 57.4 and VITA 65 (OpenVPXTM
System Specification)▪ Ruggedized and conduction-cooled versions available▪ Unique QuartzXM eXpress Module enables migration to otherform factors▪ Navigator® BSP for software development▪ Navigator® FDK for custom IP development▪ 3U VPX development chassis available▪ Free lifetime applications support

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The Navigator Board Support Package (BSP), the companion
product to the Navigator FDK, provides a complete C-callable
library for control of the 5953’s hardware and IP. The Navigator
FDK and BSP libraries mirror each other where each IP function
is controlled by a matching software function, simplifying thejob of keeping IP and software development synchronized.
The Navigator BSP includes support for Xilinx's PetaLinux runningon the ARM Cortex-A53 processors. When running under
PetaLinux, the Navigator BSP libraries enable complete control of
the 5953 either from applications running locally or on the ARMs,
or using the Navigator API control and command from remotesystem computers.

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Sample Clk

RF Out 6

JTAG

Antenna In

Balun

Balun

Balun

Balun

RF Out 5

RF Out 7Balun

RF Out 4

RF Out 8

Balun

Balun

RF In 8

Balun

Balun

RF In 7

RF Out 3Balun

RF In 6

Balun

Balun

RF In 5

RF Out 1Balun

RF Out 2Balun

RF In 3Balun

RF In 4Balun

RF In 1

Timing Bus
Generator

RF In 2Gate / Trigger

Reference Sync

Reference Clk

Frequency
Synthesizer

A/D Clocks

RF Out 2
through 7

RF In 2through 7

SysRef

D/A Clocks

GPS

D/A Output
1 -8

A/D Input
1 -8

Programmable
Logic

ZYNQ
UltraScale+
RFSoC FPGA

64

DDR4
SDRAM
4/8 GB

GTY

LVDS

GTY

Processing
System

GTR

GTR

GTR

GTR

JTAG

POWER
Battery
MANAGEMENTManagement

Model 5953 Quartz 3U VPXVPX VBAT

Battery

X8
X8

JTAG

X8 25 Gb/sec Optical
Transceiver(Optional)

Dual
100 GigE

LVDS GPIO

Model 5901-950
Quartz 3U VPX
RTM
3U VPX
Backplane

VITA
66.4

22

Gate

AXI4 Stream Clk
Sync

SysRef

VPX
P2
AXI4-Stream Clk VPX
(1/2)
Sync
P2
(1/2)
Gate

Sample Clk

JTAG

SysRef

VPX
P2
VPX
(1/2)
RP2
(1/2)

VPX
P2
(1/2)
VPX
RP1

VPX
VPX
RP0
P2
(1/2)

Sample Clk

VPX
P2
(1/2)
VPX
P1

VPX
VPX
P0
P2
(1/2)

ConfigFLASH

VPX VBAT

RS-232

1 GigE

DisplayPort

1 GigEUSB 3

VPX RefClk

12 V
VPX AuxClk

PCIe
Gen. 3 X8

X24

64

12 V

DDR4
SDRAM
4/8 GB

RS-232

1 GigE

1 GigE
DisplayPort

USB 3

Power
Management

Model 6003 QuartzXM eXpress Module9.85 GHz
14-BIT
D/A & DUC
Channels
1-8

5 GHz
14-bitA/D & DDC
Channels
1-8

RF Signal
Chain

Clock
Management

SD
Card

LVDS GPIO(50-pin SMC)

Sync Bus

RS-232(Micro USB)

DisplayPort(Mini DisplayPort)1 GigE(RJ45)

USB 3(Type-A)TECHNICAL DATA SHEET
Quartz 5953

5953 BLOCK DIAGRAM

Click on a block for more information.

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TECHNICAL DATA SHEET
Quartz 5953

A/D CONVERTER STAGE

MEMORY RESOURCES

The 5953 accepts analog IF or RF inputs on eight front panel
coax connectors. These inputs are transformer-coupling into
the RF signal chain of the RFSoC. Inside the RFSoC, the analog
signals are routed to eight 5 GSPS, 14-bit A/D converters. Eachconverter has built-in digital downconverters with
programmable 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, or 40x
decimation and independent tuning. The A/D digital outputs aredelivered into the Zynq’s programmable logic and processor
system for signal processing, data capture or for routing toother resources.

The 5953 architecture supports 8 GB bank of DDR4 SDRAM
memory accessible from the Programmable Logic. Userinstalled IP, along with the Mercury-supplied DDR4 controller
core within the FPGA, can take advantage of the memory forcustom applications.

In addition to the A/D’s built-in decimation, an additional stageof IP-based decimation provides another 16x stage of data
reduction, ideal for applications that need to stream data fromall eight A/Ds.

D/A CONVERTER STAGE
The RFSoC’s eight D/A converters accept baseband real orcomplex data streams from the FPGA’s programmable logic.
Each 9.85 GSPS, 14-bit D/A includes a digital upconverter withindependent tuning and interpolations of 1, 2, 3, 4, 5, 6, 8, 10, 12,
16, 20, 24, or 40x. Each D/A output is transformer coupled to acoax connection located on the front panel.

CLOCKING AND SYNCHRONIZATION
The 5953 front panel includes inputs for sample clock,reference clock, reference sync, and gate/trigger. In addition to
the front panel, Sync Bus signals are available on the VPX P2
connector for use with the Model 9103 High- Speed System
Synchronization and Distribution Amplifier for synchronizing up
to 8 5953s in larger, multi-channel systems with single sample
accuracy across all channels.
The on-board timing bus generator uses these signals, inaddition to a frequency synthesizer, to create the required A/D
and D/A clocks and a SysRef for operation of the data
converters. The timing bus generator supports an internal clockmode where the sample clock is driven by the programmablefrequency synthesizer and no additional clock needs to beprovided. In an alternate mode, the on-board sample clock canbe synchronized to a 10 MHz reference clock received through afront panel connector.

An 8 GB bank of DDR4 SDRAM is available to the Processing
System as program memory and storage.

PCI EXPRESS INTERFACEThe 5953 includes an industry-standard interface fully compliant
with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting
PCIe links up to x8, the interface includes multiple DMA
controllers for efficient transfers to and from the module.

GPS
A GPS receiver provides time and position information to the
FPGA and ARM processors. This information can be used for
precise data tagging. The GPS provides a 1 PPS and a reference
clock to the FPGA.

EXPANDABLE I/O
The 5953 supports the VITA 66.4 standard providing eight 25
Gb/sec full duplex optical lanes to the backplane. With the builtin 100 GigE UDP interface or installation of user-provided serial
protocol, the VITA 66.4 interface enables gigabit
communications between boards independent of the PCIeinterface.
Eleven pairs of LVDS connections are provided between the
FPGA and the VPX P2 connector for custom I/O.

REAR TRANSITION MODULE
The Model 5901 RTM complements the 5953 by providing rear
backplane access to standard interfaces including: JTAG, USB
3, 1 GigE, DisplayPort, and RS-232. The RTM also includes amultisignal Sync Bus connector for synchronizing multiple 5953s
with the Model 5903 Quartz® Synchronization 3U VPX board, anda general-purpose FPGA I/O connector is also provided foraccess to 11 LVDS pairs from the FPGA.

The 5953 can also accept an external sample clock through afront panel connector. This mode bypasses the on-board
sample clock. A multifunction gate/trigger input is available on
the front panel for external control of data acquisition andplayback.

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TECHNICAL DATA SHEET
Quartz 5953

OPTIMIZED IP
Xilinx has created an integrated processing solution in the RFSoC
that is unprecedented. The key to unlocking the potential of the
RFSoC is efficient operation using optimized IP and application
software. Mercury helps streamline the process from development
to deployed application by providing a full suite of built-in functions.
These address the data flow and basic processing needed for someof the most common applications.

EXAMPLE 1 - HIGH BANDWIDTH DATA STREAMING
The RFSoC’s eight A/Ds are capable of producing an aggregate data
rate of 80 GB/sec when all channels are enabled. While capturing

and storing this much raw data is not feasible, the A/Ds built-in
digital downconverters can reduce this data throughput in many
applications to a rate reasonable for the data streaming andstorage components downstream in the system. In some
applications capturing the raw, full bandwidth data is crucial. The
5953’s dual 100 GigE UDP engine provides a high bandwidth pathfor moving data off of the board. Along with the built-in dataacquisition IP, the 5953 can stream raw data from two A/Dchannels running at 4 GSPS over optical cable to a downstream
storage or processing subsystem.

DDR
SDRAM
RF In

A/Ds
Data
Acquisition
IP Block

Dual
100 GigE
UDP
IP Block

D/As
Zync UltraScale+ RFSoC

8x 25 Gb/sec
OpticalTransceivers

VPX

100 GigE Out 1
VITA
66.4

100 GigE Out 2

Model 5953

EXAMPLE 2 - WAVEFORM GENERATOR
The 5953’s IP supports multiple D/A signal source options. A
simple loopback path allows samples received by the A/Ds to be
output through the D/As. A CW signal generator produces a sine
output with programmable frequency. A chirp generator, ideal

RF In

RF OutDDR
SDRAM

CW Signal
Generator
IP Block

A/Ds

D/As

for radar applications, outputs sweep signals with
programmable frequency, ramp, phase offset, gain offset, andlength. The generators also include flexible trigger options withboth internal and external triggering.

M
U
X

VPX

PCIe
Gen. 3x8

Chirp
Generator
IP Block
VITA
66.4

Zync UltraScale+ RFSoC
Model 5953

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TECHNICAL DATA SHEET
Quartz 5953

EXAMPLE 3 - MULTIMODE DATA ACQUISITION SYSTEM
processor while yet other A/D channels are down converted
using the A/Ds’ built-in DDCs and streamed over PCIe. The 5953
provides these modes with built-in IP supporting complex data
streaming scenarios without the need for creating custom IP.

In some applications multiple data acquisition modes may need
to be operated at the same time. A required dataflow could be
full bandwidth streaming of a single A/D channel over 100 GigE toa data recorder while another channel of A/D data is stored assnapshots in the board's DDR4 SDRAM and read by the ARM

RF In

DDR SDRAM
Memory Control
IP Block

A/Ds
Data
Acquisition
IP Block

DDR
SDRAM

VPX

PCIe
Gen. 3
x8

VITA
66.4

100 GigE Out

PCIeGen. 3 X8
IP Block

D/As
Dual 100 GigE
UDP IP Block

Zync UltraScale+ RFSoC

8x 25 Gb/sec
OpticalTransceivers

Model 5953

FLEXIBLE MODULAR DESIGN
While the Quartz 5953 follows the form factor of a standard 3U
OpenVPX board, the unique modular design of Mercury’s 6001
QuartzXM eXpress Module provides the flexibility to deploy thissolution in many different situations. The heart of the QuartzXM
is a system on module containing all of the key components
including the RFSoC FPGA, DDR4 SDRAM, and power and clock
management.
In the case of the 5953, the QuartzXM is mounted on a 3U
OpenVPX carrier which complements the design with a timing
bus generator, analog signal conditioning, a GPS receiver and an
8x 28 Gbps optical transceiver. As a module and carrier board
set, the 5953 becomes a complete, ready to deploy 3U OpenVPX

solution available for a range of operating environments fromcommercial to rugged and conduction-cooled.
The 6001 QuartzXM can also be mounted on other carriers
available from Mercury to support standard form factors; or for
applications that require a non-standard footprint, Mercury
supports the module with a design kit for users to engineer andbuild their own custom carrier. As a complete and tested
module, the QuartzXM encapsulates best-in-class electrical andmechanical design, eliminating some of the most challenging
aspects of embedded circuit design and allowing the user tofocus on the application specific carrier design.

QuartzXM eXpress Module

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TECHNICAL DATA SHEET
Quartz 5953

NAVIGATOR DESIGN SUITE
For applications that require specialized functions, the Navigator
Design Suite allows customers to fully utilize the processing
power of the FPGA. It includes an FPGA design kit for integrating
custom IP into the factory-shipped design, and a board support
package for creating host applications for control of all hardware
and FPGA IP-based functions.
The Navigator FPGA Design Kit (FDK) for the Xilinx® Vivado® Design
Suite includes the complete Vivado project folder for each Jade
product with all design files for the factory-installed FPGA IP.
Vivado’s IP Integrator is a graphical design entry tool that visuallypresents the complete block diagram of all IP blocks so thedeveloper can access every component of the Jade design.
Developers can quickly import, delete, and modify IP blocks andchange interconnection paths using simple mouse operations.

Navigator FDK includes an IP core library of more than 100
functions representing a wealth of resources for DSP, data
formatting, timing, and streaming operations, all based on the
powerful AXI4 standard. multilevel documentation for each IP coreis a mouse click away, and fully consistent with Xilinx IP cores.
The Navigator Board Support Package (BSP) provides
software support for Jade boards. It enables operational
control of all hardware functions on the board and IP functionsin the FPGA. The BSP structure is designed to complement thefunctions of the FDK by maintaining a one-to-one relationshipbetween FDK and BSP components. For each IP block found in
the FDK library, a matching software module can be found in
the BSP. This organization simplifies the creation and editingof software to support new IP functions and modifications toexisting IP cores.

Navigator IP FPGA Design viewed in IP Integrator

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TECHNICAL DATA SHEET
Quartz 5953

Because all Jade boards are shipped with a full suite of built-in
IP functions and numerous software examples, new applications
can be developed by building on the provided software
examples or built entirely new with the BSP extensive libraries.
All BSP libraries are provided as C-language source for fullaccess and code transparency.

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The Navigator BSP includes the Signal Viewer, a full-featured
analysis tool, that displays data in time and frequency domains.
Built-in measurement functions display 2nd and 3rd harmonics,
THD (total harmonic distortion), and SINAD (signal to noise anddistortion). Interactive cursors allow users to mark data points
and instantly calculate amplitude and frequency of displayed
signals. With the Signal Viewer users can install the Jade board
and Navigator BSP and start viewing analog signals immediately.

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TECHNICAL DATA SHEET
Quartz 5953

FRONT PANEL CONNECTIONS
The 5953 is available in air- andconduction-cooled configurations. The
picture below shows the front panel ofthe air-cooled 5953.
▪ GPS Safeboot
Power Up Button(Factory Use
Only): The whitebutton, labeled
GPS UTIL,
provides a resetand safe reboot of
the onboard GPS
receiver.
▪ Front Panel
Reset Button:
The white button,labeled PS RST,
provides a reset of
the ARM
processors.
▪ GPS Antenna
Connector: thefront panel has aconnector, labeled
GPS ANT, for
input of anantenna RF signal
for the onboard
GPS receiver.
▪ PCIe Link Up
LED: The green
PCI LEDilluminates when avalid PCIe link has been establishedover the VPX interface.
▪ Link 1 LED: The green E1 LED
illuminates when a link is establishedon 100G Ethernet link #1.
▪ Link 2 LED: The green E2 LED
illuminates when a link is establishedon 100G Ethernet link #2.
▪ JTAG Connector: The 5953 includes
a JTAG connector on the front panel.

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This is used to download to the FPGA
and program QSPI configuration
memory.

RTM PANEL CONNECTIONS
The picture below shows the Model 5901950 Rear Transition Module panel.

▪ 8 A/D Input Connectors:The 8
MMCX connectors labeled IN 1-8
provide A/D input to the A/DConverters on the 5953.

▪ COM: RS-232
interface theprocessor over Micro
USB connector▪ 8 D/A Output Connectors: The 8
MMCX connectors labeled OUT 1-8
provide D/A output from D/AConverters on the 5953.

▪ DisplayPort: Mini
DisplayPort
connection toprocessor (currently
not supported)▪ Sample Clock Connector: The
MMCX connector labeled SMP CLK
provides an input for an external
sample clock when external sample
clock mode is selected.

▪ USB 3.0: Type-A
USB 3.0 interface tothe processor.

▪ Trigger Connector: The MMCX
connector labeled TRIG provides a
trigger input. This trigger input is DC
coupled and compatible with the
LVTTL levels, but is 5V tolerant. This
trigger, being an LVTTL signal, is notmeant for high accuracy in relation to
the sample clock as its rise time is on
the order of nanoseconds.
▪ Reference Clock In Connector:The
MMCX connector labeled REF IN
provides an input for an external 10 MHz
reference. This signal can be used tolock the on-board sample clock
synthesizer to an external reference. It
is optimally a sinewave signal.
▪ Reference Clock Sync Connector:
The MMCX connector labeled REF
SYNC provides an input for reference
clock synchronization.
▪ User LED: The yellow USR LED isavailable for user applications.
▪ Over Temperature LED: The red TMP
LED illuminates when an over−temperature or over−voltage condition
is indicated by the temperature/voltage
sensors on the 5953.

▪ Ethernet: RJ45
1GigE interface tothe processor▪ Sync: Multi-pin,high-speed
connector for
multiboard
synchronization▪ FPGA GPIO: 11 pairsof LVDS connections
to the programmablefabric for custom I/O

SPECIFICATIONS
Field Programmable Gate Array
Type: (standard) Xilinx Zynq
UltraScale+ RFSoC XCZU47DR▪ Option -048: RFSoC XCZU48DR
Speed: (standard) -1 speed grade▪ Option -002: -2 speed grade

RFSoC RF Signal Chain
Analog Inputs▪ Quantity: 8▪ Connectors: MMCX
▪ Location: Front panel▪ Input Type: Transformer-coupled

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TECHNICAL DATA SHEET
Quartz 5953

▪ Transformer Type: Mini-Circuits
TCM1-83X+▪ Filter: 80% pass band, 89 dB stopband attenuation▪ Full Scale Input: +10 dBm into
50 ohms

Sample Clock

A/D Converters▪ Quantity: 8▪ Sampling Rate: 5.0 GHz▪ Resolution: 14 bits
Digital Downconverters▪ Quantity: 1 per A/D▪ Decimation Range: 1, 2, 3, 4, 5, 6,
8, 10, 12, 16, 20, 24, and 40x (not all
decimations are supported bydefault IP)▪ LO Tuning Freq. Resolution:
48 bits, 0 to ƒs▪ Source: On-board programmableclock source or external clock
source▪ Connector Type: Multi-pin, highspeed differential (on RTM)

RFSoC Processing System
ARM Cortex-A53:▪ Quantity: 4▪ Speed: 1.5 GHz▪ Location: Front panel (for externalsource)

ARM Cortex-R5:▪ Connector Type: MMCX

▪ Quantity: 2▪ Level: -10 dBm to +10 dBm frontpanel▪ Speed: 600 MHz
Processor I/O:

Reference Clock▪ Interface: USB 3.0▪ Source: On-board oscillator, onboard GPS, or external source▪ Location: Front panel (for externalsource)▪ Location: VPX-P1 or RTM▪ Connector Type: USB Type-A(on RTM)▪ Interface: 1 GigE

▪ Filter: 80% passband, 89 dB stopband attenuation▪ Connector Type: MMCX

▪ Location: VPX-P1 or RTM▪ Level: -10 dBm to +24 dBm▪ Connector Type: RJ45 (on RTM)

Analog Outputs

Reference Sync

▪ Quantity: 8▪ Source: Programmable throughsoftware or external source▪ Connectors: MMCX
▪ Location: Front panel▪ Input Type: Transformer-coupled▪ Transformer Type: Mini-Circuits
TCM1-83X+▪ Full Scale Output: +0 dBm into
50 ohms
D/A Converters▪ Quantity: 8▪ Sampling Rate: (standard) 8.92 GHz▪ With -2 speed grade(option -002): 9.85 GHz▪ Location: Front panel (for externalsource)▪ Connector Type: MMCX▪ Interface: RS-232▪ Location: VPX-P1 or RTM▪ Connector Type: Micro USB(on RTM)▪ Interface: DisplayPort (notcurrently supported)▪ Level: TTL▪ Location: VPX-P1 or RTM

Gate/Trigger▪ Connector Type: Mini
DisplayPort (on RTM)

▪ Source: Programmable throughsoftware or external source▪ Location: Front panel (for externalsource)▪ Connector Type: MMCX
▪ Level: TTLFPGA I/O
Interface: GPIO
▪ Quantity: 11 Pairs▪ Type: LVDS Location: VPX-P2
or RTM▪ Resolution: 14 bits

GPS

Digital Upconverters▪ Source: On-board▪ Quantity: 1 per D/A▪ Antenna Connector Location:
Front panel

Interface: Optical (Option -110)▪ Connector Type: SMA▪ Speed: 25 Gb/sec

Sync Bus▪ Laser: 850 nm▪ Signals: Sample Clock, Reference
Clock, Reference Sync,
Gate/Trigger▪ Location: Lower 1/2 of VPX-P2▪ Interpolation Range: 1, 2, 3, 4, 5, 6,
8, 10, 12, 16, 20, 24, and 40x (not allinterpolations are supported bydefault IP)▪ LO Tuning Freq. Resolution:
48 bits▪ Connector Type: 50-pin SMC(on RTM)▪ Quantity: 8 full duplex lanes▪ Connector Type: VITA 66.4

▪ Location: VPX-P2 or RTM

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TECHNICAL DATA SHEET
Quartz 5953

▪ Protocol: Factory-installed dual
100 GigE UDP IP cores provides
greater than 24 GB/sec datatransfers, other protocols
supported with user-installed IP

JTAG
Location: Front panel and VPX-P0
or RTM
Connector Type: Standard 14-pin
header (on front panel and RTM)

MemoryProcessing System:

Option -702: L2 (air-cooled)

ORDERING INFORMATION▪ Operating Temp: –20° to 65° C▪ Storage Temp: –40° to 100° C▪ Relative Humidity: 0 to 95%,
non-condensing

Model

Description

5953

3U VPX 8-channel A/D & D/Aboard with Zynq UltraScale+
RFSoC Processor - Gen 3

Option -763: L3 (conduction-cooled)▪ Operating Temp: –40° to 70° C▪ Storage Temp: –50° to 100° C▪ Relative Humidity: 0 to 95%,
non-condensing

PhysicalOptions

Description-002-2 FPGA speed grade, -1
standard-048

XCZU48DR FPGA (XCZU47DR
is standard)▪ Type: DDR4 SDRAM

Dimensions: VPX board-110

VITA 66.4 8X optical interface▪ Size: 8 GB

▪ Depth: 170.61 mm (6.717 in)-702

Air-cooled, Level L2▪ Speed: 1200 MHz (2400 MHz DDR)

▪ Height: 100 mm (3.937 in)-763

Conduction-cooled, Level L3

Programmable Logic:

Weight: 22 oz (624 grams)▪ Type: DDR4 SDRAM▪ Size: 8 GB
▪ Speed: 1200 MHz (2400 MHz DDR)FPGA Configuration FLASH▪ Type: QSPI NOR FlashOpenVPX Compatibility

Contact Mercury for compatible option
combinations.

The 5953 is compatible with thefollowing module profile, as defined by
the VITA 65 OpenVPX Specification:
SLT3-PAY-2F2U1E-14.6.10-n▪ Size: 2 x 1 Gbit

PCI-Express Interface
PCI Express Bus: Gen. 1, 2 or 3:x4 or x8

Environmental
Standard: L0 (air-cooled)▪ Operating Temp: 0° to 50° C▪ Storage Temp: –20° to 90° C▪ Relative Humidity: 0 to 95%,
non-condensing

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TECHNICAL DATA SHEET
Quartz 5953

ACCESSORY PRODUCTS

LIFETIME SUPPORT FOR QUARTZ PRODUCTS

OptionDescription-950

Support for Model 5950

Model

Description

5901

Rear Transition Module - 3U VPX

5903

High-Speed Synchronizer and Distribution Board

8257

3U VPX Development Chassis

Mercury offers worldwide customers shorter development time,
reliable, rugged solutions for a variety of environments, reduced
costs, and mature software development tools. We offer freelifetime support from our engineering staff, which customers
can depend on through phone and email, as well as software
updates. Take advantage of our 40 years of experience indelivering high-performance radar, communications, SIGINT,
EW, and data acquisition MIL-Aero solutions worldwide.

MODEL 8257
The Model 8257 is a 3U VPX chassis ideal for application
development. Offered as a convenient, low cost solution for
hosting the 5953, it includes power and cooling to match the5953’s requirements in a portable desktop package.

Corporate Headquarters
50 Minuteman Road
Andover, MA 01810 USA+1 978.967.1401 tel+1 866.627.6951 tel+1 978.256.3599 fax

International Headquarters
Mercury International

Learn more

Avenue Eugène-Lance, 38
PO Box 584
CH-1212 Grand-Lancy 1
Geneva, Switzerland

For technical details, contact:mrcy.com/go/CF5953

Visit: mrcy.com/go/MP5953+41 22 884 5100 tel

The Mercury Systems logo and the following are trademarks or registered trademarks of Mercury Systems, Inc.: Mercury Systems, Innovation That
Matters, Quartz and Navigator. Other marks used herein may be trademarks or registered trademarks of their respective holders. Mercury believes
this information is accurate as of its publication date and is not responsible for any inadvertent errors. The information contained herein is subject
to change without notice.
© 2022 Mercury Systems, Inc. 1-0-110922-DS-Q5953

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