66-16AISS8AO4
16-Bit, 12-Channel, 2-MSPS PMC Analog Input/Output Board
With Eight Simultaneously Sampled Analog Inputs, Four Analog Outputs,and Input Sampling Rates to 2.0 MSPS per channel
Available in PMC, PCI, cPCI and PC104-Plus and PCI Express form factors as:
PMC66-16AISS8AO4:

PMC, Single-width

PCI66-16AISS8AO4:

PCI, short length

Cpci66-16AISS8AO4:

cPCI, 3U

PC104P66-16AISS8AO4:

PC104-Plus

PCIe66-16AISS8AO4:PCI Express

PCIe10466-16AISS8AO4:

PCIe, one-lane on PC/104 form factor

See Ordering Information for details.
Call for availability of other form factors, such as XMC, CCPMC, etc.

FEATURES: Analog Inputs:
 8 Differential Analog Inputs with Dedicated 16-Bit ADC per Channel True Simultaneous Sampling of all Inputs to 2.0 MSPS per channel
 SAR Architecture; No Minimum Sample Rate
 Analog Outputs:
 4 Single-Ended Analog Outputs with Dedicated 16-Bit DAC per Channel
 Simultaneous Output Clocking Rates to 1.0 MSPS per Channel
 Selectable Direct-Write or FIFO-Buffered Access Buffer Configurable as Open for Data Streaming, or Circular for Periodic Functions
 Common Analog I/O Features:
 Selectable Input/Output Ranges: ±10V, ±5V, ±2.5V
 Independent 256-Ksample Input and Output FIFO Data Buffers
 Hardware Clock and Sync I/O for Multiboard Operation
 Internal Power Conversion; Single 5-Volt Power Requirement
 DMA Engine Minimizes Bus Congestion
 Timing Controlled by Internal Rate Generator, by Software Clocking, or Externally Three Independent 24-Bit frequency dividers.
 Internal Autocalibration
 16-Bit Bidirectional TTL Digital I/O Port
 66 MHz 32-Bit PCI Support, with Universal 5V/3.3V Signaling Single-Width PMC Form Factor with Integral EMI Shield.
 Extended-temperature version available.
 I/O Connector Pin-Compatible with PMC-12AISS8AO4, PMC-12AISS44AO4. Alternate I/Oavailable with two SMA coaxial input connectors.

TYPICAL APPLICATIONS:
 High Performance Data Acquisition
 Arbitrary Waveform Generation

 Event Capture Ultrasound Robotics
 Positioning Systems
REV: 081510

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FUNCTIONAL DESCRIPTION
The 16-Bit PMC-16AISS8AO4 analog I/O module samples and digitizes eight input channels
simultaneously at rates up to 2.0 million samples per second for each channel. The resulting
16-bit sampled data is available to the PCI bus through a 256K-Sample FIFO buffer. Sampling
can be controlled in groups of 1 through 8 channels, and the sample clock can be generated
either from an internal rate generator, or through software, or by external hardware. Both burst
and continuous sampling modes are supported. Input ranges are software-selectable as ±10V,±5V, or ±2.5V. The inputs can be divided into two channel groups, with independent range
assignments for both groups.
Four analog output channels provide software-selected output ranges of ±2.5V, ±5V or ±10V, andare accessed either directly through dedicated control registers, or output data can be routed
through a 256K-Sample FIFO buffer for waveform generation. A 16-Bit bidirectional digital port
can be configured as two independent byte-wide ports.
On-demand autocalibration determines and applies offset and gain correction values for all input
and output channels. A selftest input switching network routes output channels or calibrationreference signals to the analog inputs, and permits board integrity to be verified by the host..

Analog Outputs (4)±10V, 5V, 2.5V
Chan-00 of 8 Identical Input Channels
Analog Inputs

Selftest
Switching±10V, 5V, 2.5V

Diff
Amp

16-BitADC

SystemI/O Conn
Inputs 01-07

Channels 01 to 07

Voltage
Reference

Input
DataInput Control

External Clock and Sync I/O
16-BitDAC (4)

Sample-Rate
Generators (3)+5VDC

PowerConversion

LocalController

Regulated
Power VoltagesPCIConn66MHz, 33MHzPCIInterface
Adapter

Local BusFigure 1. PMC-16AISS8AO4; Functional Organization
This product is functionally compatible with the IEEE PCI local bus specification Revision 2.3, andsupports the "plug-n-play" initialization concept. System connections are made at the front panel
through a high-density dual-ribbon 80-pin connector, or alternative I/O is available with two SMA
coaxial input channels. Power requirements consist of +5 VDC in compliance with the PCI
specification, and analog power voltages are generated internally. All operational parameters aresoftware configurable. Operation over the specified temperature range is achieved withconventional air cooling.
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PERFORMANCE SPECIFICATIONS
At +25 OC, with specified operating voltages

Analog Input Characteristics:
Configuration:

Voltage Ranges:
Input Impedance:
Bias Current:
Crosstalk Rejection:
Signal/Noise Ratio (SNR):
Common Mode Rejection:
Overvoltage Protection:

Eight differential analog input channels; Dedicated 16-Bit ADC per channel.
Optional 4-Channel version available. (Two external and two internal input
channels if the SMA Inputs I/O ordering option is specified).
Independently assignable between two groups of input channels as:±10V, ±5V or ±2.5V full scale.
2 Megohms Line-Line in parallel with 40pF.
100 nanoamps typical all ranges
84dB, DC-10kHz. 70dB at 100kHz.
82dB typical; 10Hz to 500kHz
65dB DC-10kHz; 53dB at 100kHz. Typical with CMV = ±10V, Vin = Zero.
±25V with power applied, ±15 Volts with power removed.

Analog Input Transfer Characteristics:
Resolution:

16 Bits (0.0015 percent of FSR)

Sample Rate:

Zero to 2.0 MSPS per channel

Sampling Mode::

Simultaneous; all active input channels

DC Accuracy:(Maximum composite error
after autocalibration)

Range
±10V
±5V
±2.5V

Small Signal Bandwidth:

Zero to 5MHz, -3dB, all ranges

Settling Time:

500ns to 0.1%; halfscale step; typical; all ranges.

Power Bandwidth:

3MHz, 10Vp-p, -3dB

Integral Nonlinearity:±0.007 percent FSR

Differential Nonlinearity:±0.003 percent FSR.

Midscale Accuracy
± 2mV
± 1mV
± 0.8mV

Fullscale Accuracy± 5mV
± 3mV
± 2mV

(FSR = fullscale range; e.g.: 20Von ±10Vrange).

Analog Input Operating Modes and Controls
Input Data Buffer:

256K-sample FIFO

Sample Clock Sources:

Internal rate generator; External Hardware Clock I/O, Software clock.

Sampling Modes:

Continuous sampling, and triggered burst.

Internal Rate Generators:

Two independent rate generators, one for ADC clocking; one for burst
triggering.
Both programmable from 3-2,000,000 sample clocks per
second, using 24-Bit dividers from the master clock frequency.

External Clock I/O:

TTL, bidirectional. Zero to 2,000,000 sample clocks per second.

Principal Status Register:

Consolidates critical status flags at a single Longword location.

Input Data Format:

16 Bits. Selectable as offset binary or two's complement. First-channel
and end of-burst tagged.

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Analog Output Characteristics:
Configuration:
Voltage Ranges:
Output Resistance:
Output protection:
Load Current:
Load Capacitance:
Noise:
Glitch Impulse:

Four single-ended output channels. (Two external and two internal output
channels if the SMA inputs I/O ordering option is specified).
±10, ±5 or ±2.5 Volts; Independent of analog input ranges.
1.0 Ohm maximum at I/O connector pins.
Withstands sustained short-circuiting to ground
Zero to ±3ma per channel
Stable with any load capacitance
2.0mV-RMS, 10Hz-100KHz typical
7 nV-s, typical on ±5V range

Analog Output Transfer Characteristics:
Resolution:
Output Access:DC Accuracy:(Max error, no-load)Settling Time:
Crosstalk Rejection:
Integral Nonlinearity:
Differential Nonlinearity:
Output Data Format:

16 Bits (0.0015 percent of FSR)
Direct register access or 256K-Sample FIFO buffer.
RangeMidscale Accuracy±Fullscale Accuracy±10V±4mV
±8mV
±5V
±2mV
±6mV
±2.5V
±1.5mV±4mV
2us to 0.1 percent, typical with halfscale step, no-load.
70 dB minimum, DC-100 kHz±0.007 percent of FSR, maximum±0.002 percent of FSR, maximum
16 Bits. Same format as selected for analog inputs.

Analog Output Operating Modes and Controls
Output Data Buffer:
Sample Clock Sources:Burst Triggering Sources:
Clocking Modes:
Internal Rate Generator:
External Clock I/O:
Output Data Format:

256K-sample FIFOInternal rate generator; External Clock I/O, Software clock.
TTL external Trigger I/O (shared with analog inputs), Software trigger.
Continuous or periodic clocking, and triggered burst.
Programmable from 3-1,000,000 output clocks per second.
Divides Master Clock frequency to clocking rate using a 24-bit divider.
TTL, bidirectional. Zero to 1,000,000 sample clocks per second.
16-Bits. Selectable as offset binary or two's complement.

Digital I/O Port:
Dual Independent 8-Bit bidirectional I/O ports. Standard TTL levels. Direct register Access.
±8 mA loading when configured as outputs. 0.15 mA source when configured as inputs. (Fourdigital I/O lines if the SMA inputs I/O ordering option is specified).

PCI Compatibility:
Conforms to PCI Specification 2.3, D32 read/write, 33/66MHz, universal (5V/3.3V) signaling,
Supports block-mode and demand-mode DMA data transfers in two channels as bus master.

Power Requirements+5VDC ±0.25 VDC at 1.5 Amp maximum, 1.1 Amp typical.
Maximum Power Dissipation:
Side-1: 6.5 Watts. Side 2: 1.0 Watt.


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PHYSICAL PARAMETERS
Mechanical Characteristics (PMC Form Factor)
Height:Depth:
Width:
Shield:13.5 mm (0.53 in)
149.0 mm (5.87 in)
74.0 mm (2.91 in)
Side-1 is protected by an EMI shield.

Environmental Specifications
Ambient Temperature Range:
Standard Temperature:

Operating: 0 to +70 Degrees Celsius *Storage: -40 to +85 Degrees Celsius

Extended Temperature:

Operating: -40 to +85 Degrees Celsius *Storage: -40 to +85 Degrees Celsius* Air temperature at board surface.

Relative Humidity:

0 to 95%, non-condensing

Altitude:Operation to 10,000 ft.

Cooling:

Conventional air cooling; 150 LFPM

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ORDERING INFORMATION
Specify the basic product model number followed by an option suffix "-A-B-C-D", as indicated below. For example,
model number PMC66-16AISS8AO4-8-4 -40.32M describes a PMC module with eight input channels, four outputchannels, a 40.320MHz master clock frequency, and no custom features.
To obtain the alternate I/O connector version with two SMA coaxial input channels, two analog outputs and four
digital I/O lines, specify the basic product model number with the suffix "SMA". For example, model number
PMC66-16AISS8AO4SMA describes a PMC module with two SMA coaxial input channels, and a DB9 subminiature
I/O connector containing two analog outputs and four digital I/O lines.

Basic Model Number

Form Factor

PMC66-16AISS8AO4PMC (Native)

PCI66-16AISS8AO41

PCI, short length

Cpci66-16AISS8AO4

1cPCI, 3U

1cPCI, 3U

PCIe66-16AISS8AO4PC104-Plus

PC104P66-16AISS8AO4
PCIe10466-16AISS8AO4
121,2PCIe, one-lane on PC/104 form factor

Module installed and tested on an adapter, with mechanical and functional equivalency.
Contact factory for availability in native form factors.
PCIe104 supports only the PCIe bus.

Optional Parameter(Standard I/O version)
Number of Input Channels
Number of Output Channels
Master Clock Frequency *Custom Feature

Value

Specify Option As:

8 Input Channels

A=84 Input Channels

A=44 Output Channels

B=4No Analog Outputs

B=040.320MHz

C = 40.32M
D **---* 40.320MHz if both 'C' and 'D' fields are blank.

Custom frequencies available from 40-44MHz.
Contact Sales for details.
** Numeric code, determined by specific feature. Blank or zero (0) if no custom feature applies.

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SYSTEM INTERFACE CONNECTOR (Standard I/O)
Table 1. System I/O Connector
ROW-A
PIN
12345678910111213141516171819202122232425262728293031323334353637383940

SIGNALOUTPUT RTN
ANA OUT 00
OUTPUT RTN
ANA OUT 01
OUTPUT RTN
ANA OUT 02
OUTPUT RTN
ANA OUT 03
INPUT RTN
INPUT RTN
INP00 LO *INP00 HI *INPUT RTN
INPUT RTN
INP01 LO *INP01 HI *INPUT RTN
INPUT RTN
INP02 LO **INP02 HI **INPUT RTN
INPUT RTN
INP03 LO **INP03 HI **INPUT RTN
INPUT RTN
INP04 LO *INP04 HI *INPUT RTN
INPUT RTN
INP05 LO *INP05 HI *INPUT RTN
INPUT RTN
INP06 LO **INP06 HI **INPUT RTN
INPUT RTN
INP07 LO **INP07 HI **

ROW-B
PIN
12345678910111213141516171819202122232425262728293031323334353637383940

SIGNALDIGITAL RTN
DIO 00
DIGITAL RTN
DIO 01
DIGITAL RTN
DIO 02
DIGITAL RTN
DIO 03
DIGITAL RTN
DIO 04
DIGITAL RTN
DIO 05
DIGITAL RTN
DIO 06DIGITAL RTN
DIO 07
DIGITAL RTN
DIO 08
DIGITAL RTN
DIO 09DIGITAL RTN
DIO 10
DIGITAL RTN
DIO 11
DIGITAL RTN
DIO 12
DIGITAL RTN
DIO 13
DIGITAL RTN
DIO 14
DIGITAL RTN
DIO 15VTEST RTN
VTEST
DIGITAL RTN
OUTPUT CLK I/O
DIGITAL RTN
TRIGGER I/O
DIGITAL RTN
INPUT CLK I/O

ROW A

ROW B

PIN 40

I/O
CONN

PWB

PIN 1

Panel Pin-view

Figure 2. System I/O Connector

System Mating Connector:
Standard 80-pin 0.050" dual-ribbon socket:
Robinson Nugent P50E-080S-TG, or equivalent.

* Input Group-A. ** Input Group-B.
4 input-channel modules contain input Channels 00-03.

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SYSTEM INTERFACE CONNECTOR (SMA inputs I/O)

J1 (SMA) INP01.
J2 (SMA) INP03.

PWB

J1(SMA)J3 (DB9):Table 2. J3: DB9 Connector
PIN

SIGNALASSIGNMENT

1

DIGITAL OUT #1

DIO 002

DIGITAL OUT #2

DIO 01

3

DIGITAL OUT #3

DIO 02

4

DIGITAL INP #1

DIO 085GND

DIGITAL RTN6DAC OUT #1

ANA OUT 00 and INP00

7GND

OUTPUT RTN

8DAC OUT #2

ANA OUT 02 and INP02

9GND

OUTPUT RTN

J2(SMA)ORIGINAL SIGNAL(S)from Table 1

Pin 9J3(DB9)
Pin 1

Optional SMA Input I/O
System Connections

Figure 3. Alternate System I/O

NOTE: The following system I/O lines are not available in the alternate SMA system I/O configuration:
Analog inputs INP04-07,
Analog outputs ANA OUT 01, ANA OUT 03,
Digital I/O DIO03-DIO07.
Analog inputs INP00 and INP02 are available internally only, and are connected to ANA OUT 00 andANA OUT 02, respectively.

General Standards Corporation assumes no responsibility for the use of any circuits i n this product. No circuit patent licenses are implied.
Information included herein supersedes previously published specifications on this product and is subject to change without n otice.

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Phone: (256) 880-8787 or (800) 653-9970 FAX: (256) 880-8788 Email: Solutions@GeneralStandards.com