Product Summary
Digital Signal Driver/Timing Generator

CXD3555GG
1. Description
The CXD3555GG incorporates digital signal processor type RGB driver, gamma correction (panel gamma), color shadingcorrection, geometry correction and timing generator functions onto a single IC. The input supports LVDS and V-by-One®
HS I / F, and the output supports V-by-One® HS. The CXD3555GG can output timing signals for driving various Sony LCD
panels from XGA to WUXGA standards. This IC can support a wide range of resolutions such as WQXGA, 4K2K, and 4K2.4K
standards. This IC has a keystone correction and distortion correction function.
(Applications: LCD projectors and other video equipment)

2. Features◆

LVDS RX I/F (for input) supported 1.05Gbps◆

V-by-One HS® RX I/F (for input) supported 4Gbps◆

V-by-One HS® TX I/F (for output) supported 4Gbps◆

Supports I2C bus and 3-wire bus◆

Controls various ICs I2C master◆Drives various Sony projector LCD panels such as XGA, WXGA and WUXGA◆Supports various resolution standards such as WQXGA, 4K2K, 4K2.4K◆

Supports PU ARM926EJS (4K I-cache / 4K D-cache, JTAG ICE interface and Watchdog timer)

3. Package
625pn FCBGA 21mm□PKG 0.8mm Ball Pitch

4. Structure
Silicon gate CMOS IC※V-by-One® is a registered trademark of THine Electronics Corporation.
※ARM is a registered trademark of ARM Limited

CXD3555GG
15. Operating Conditions

Item

Symbol

Min.

Typ.

Max.

Unit

0.72

0.80.88※

V

1.62

1.8

1.98

V

VDD33_GPIO

2.97

3.3

3.63

VTopr-20-75℃

AVDD08_VBO_TX, AVDD08_VBO_RX1,AVDD08_VBO_RX2, AVDD08_PLL1,
AVDD08_PLL2, AVDD08_PLL3,
AVDD08_PLL4, VDD, AVDD08_TESTTP
AVDD18_VBO_TX,
AVDD18_VBO_TX_PLL,
AVDD18_VBO_RX1, AVDD18_VBO_RX2,
AVDD18_LVDS_RX0,
Supply voltage

AVDD18_LVDS_RX1,
AVDD18_LVDS_RX2,
AVDD18_LVDS_RX3,
AVDD18_LVDS_BUF0,
AVDD18_LVDS_BUF1,
AVDD18_LVDS_BUF2,
AVDD18_LVDS_BUF3, AVDD18_PLL,VDD18_TESTT, VDD18_TESTTP,
VDD18_TESTR

Operatingtemperature※In case of the maximum power consumption under high load use case, use this IC with 0.8V power system lowering by the maximum range to0.8V so that power consumption (Po) is allowable dissipation (Pd) or less.

6. Operation Frequency◆Video I/F

LVDS RX175 ~ 1050

Mbps

V-by-One® HS RX

0.6 ~ 4.0

Gbps

V-by-One® HS TX

0.6 ~ 4.0Gbps◆Input CLKXTALIN25±1.5%, 33±1.5%

MHz◆Ouput CLK

PCLK

6 ~ 37.5

MHz

CXD3555GG
2

7. Block diagram

CXD3555GG
3.3V
1.8V
0.8V

Input
SelectLVDS
5ch x 4 Link

LVDS
Rx

Pre Image
Processing

Frame Rate
Converter

Post Image
Processing

SharpnessGammaColor
Gamut

Uniformity
Correction

V-By-One®
Tx

V-By-One®
24 Lanes

Edge
Blending
V-By-One®
16 Lanes

V-By-One®
Rx

Shift4K
KeyStone
Warping

X’tal

Frame
MemoryTG

Clock controlTiming
Signals

I2C
HOST I/F
SPI

MCU

I2CM

CXD3555GG
3

8. Package Outline(Unit: mm)

CXD3555GG
4©2022 Sony Semiconductor Solutions Corporation. All rights reserved.

Product Summary
LCD Driver

CXD3861GL
1. Description
CXD3861GL is a driver IC developed for Sony high-temperature polysilicon TFT LCD and SXRD panels. It supports
V-By-One® Input, and the input data is demultiplexed into 48 parallel and output. The CXD3861GL can directly drive an
LCD panel, and also incorporates the VCOM setting circuit and precharge pulse waveform generation circuit needed forpanel drive.
(Application: LCD projectors and other video equipment)

2. Features◆

Supports V-By-One® input I/F 4lane◆

48 parallel demultiplexed output (Support 16 parallel x RGB output)◆

Supports using multiple CXD3861GLs◆

Supports 10bit input◆

240Hz Drive◆

Low output deviation◆

Various adjustment functions using I2C bus interface◆

VCOM voltage generation circuit (Inversed operation)◆Precharge pulse waveform generation circuit◆Supports power-on/off sequence

3. Package
204Pin VFLGA(Plastic)

4. Structure
Monolithic CMOS IC※V-by-One® is trademark registration by THine Electronics Corporation.

CXD3861GL
1

5. Operating Conditions

ItemCondition

Min.

Typ.

Max.

Unit

1.5

1.55

1.6

V

3.0

3.3

3.6

V

HTPS

9.5

10.0

10.5

V

SXRD

10.8

-

11.3

V-20-75℃

VDD15D, VDD15A
VDD33D, VDD33A_R(G/B), VDD33A_BGR,
VDD33A_REFDAC
Supply voltage

VDD120A_R(G/B),
VDD120A_BGR
PVDD120A_R(G/B),
PVDD120A_VCOMR(G/B)1,
PVDD120A_VCOMR(G/B)2

OperatingtemperatureTopr※For guaranteed temperature and thermal resistance, see “Notes on Operation”

6. Operation Frequency◆External I/F

V-by-One® HS RX

1160~2720

Mbps◆Input CLK

PCLK

6~37.5MHzCXD3861GL
2

7. Block diagram

CXD3861GL
10V
3.3V
1.55V
10bit DACVCOMOUT_G1

10bit DACVCOMOUT_G2

10bit DACVSIGOUT 01

10bit DACVSIGOUT 02

10bit DACVSIGOUT 03

10bit DACVSIGOUT 04

10bit DACVSIGOUT 05

10bit DACVSIGOUT 06

10bit DACVSIGOUT 07

10bit DACVSIGOUT4510bit DAC

VSIGOUT46

10bit DACVSIGOUT47

10bit DACVSIGOUT4810bit DAC

PISG

Latch

V-By-One®
8 Lanes

PCLK

V-By-One®
Rx

Clock control

I2C
HOST I/FCXD3861GL
3

8. Package Outline(Unit: mm)

CXD3861GL
4©2022 Sony Semiconductor Solutions Corporation. All rights reserved.