TECHNICAL DATA SHEETJade 78841
1-channel 3.6 GHz A/D with DDC,
2-channel 1.8 GHz A/D with DDC
PCIe board with Kintex UltraScale FPGA

Complete radarand software radiointerface solution▪ Radar and software radio receiver▪ Remote monitoring▪ Communications receiver▪ Sensor interfaces▪ Analog signal interface for data recording▪ Wideband data acquisition

Jade® 78841 78841 is a high-speed data converter with
programmable DDCs (digital downconverters). It is suitable forconnection to HF or IF ports of a communications or radar system. Its
built-in data capture feature offers an ideal turnkey solution as well as aplatform for developing and deploying custom FPGA-processing IPIt includes a 3.6 GHz, 12-bit A/D converter and a large DDR4 memory. In addition tosupporting PCI Express Gen. 3 as a native interface, the 78841 includes optional highbandwidth connections to the Kintex UltraScale FPGA for custom digital I/O.

FEATURES▪ Xilinx® Kintex® UltraScale™ FPGA▪ One-channel mode with 3.6 GHz, 12-bit A/D▪ Two-channel mode with 1.8 GHz, 12-bit A/Ds
▪ Programmable one- or two-channel DDC (Digital Downconverter)▪ 5 GB of 2400 MHz DDR4 SDRAM▪ µSync clock/sync bus for multiboard synchronization▪ PCI Express interface (Gen. 1, 2 & 3) up to x8▪ Optional LVDS port and gigabit serial connections for custom FPGA I/O

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TECHNICAL DATA SHEETJade 78841

78841 BLOCK DIAGRAM
Click on a block for more information.

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TECHNICAL DATA SHEETJade 78841

THE JADE ARCHITECTURE

A/D ACQUISITION IP MODULES

Evolved from the proven designs of Mercury’s Cobalt® and Onyx®
families, Jade® raises the processing performance while loweringthe overall power requirements by building on the Xilinx family ofKintex UltraScale FPGAs. As the central feature of the board
architecture, the FPGA has access to all data and control paths,
enabling factory-installed functions as well as providing an ideal
platform for user-created intellectual property (IP).

The 78841 features an A/D Acquisition IP Module for easy
capture and data moving. The IP module can receive data fromthe A/D, or a test signal generator. The IP module has anassociated 5 GB memory bank for buffering data in FIFO modeor for storing data in transient capture mode.

Each member of the Jade family is delivered with factoryinstalled applications ideally matched to the board’s analog
interfaces. The 78841 factory-installed functions include an A/Dacquisition IP module and a programmable digital
downconverter (DDC). In addition, IP modules for DDR4 SDRAM
memories, a controller for all data clocking and synchronization
functions, a test signal generator and a PCIe interface complete
the factory-installed functions and enable the 78841 to operate
as a complete turnkey solution, without the need to develop anyFPGA IP.

XILINX KINTEX ULTRASCALE FPGAS
Depending on the requirements of the processing task, the Kintex
Ultrascale can be selected from a range of FPGAs: KU035 through
KU115. The KU115 features 5520 DSP48E2 slices and is ideal formodulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals betweentransmission and reception. For applications not requiring large
DSP resources or logic, a lower-cost FPGA can be installed.

A/D CONVERTER STAGE
The board's analog interface accepts analog HF or IF inputs on apair of front panel SSMC connectors with transformer coupling
into a Texas Instruments ADC12D1800 12-bit A/D. The converter
operates in single-channel interleaved mode with a sampling
rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dualchannel mode with a sampling rate of 1.8 GHz and input
bandwidth of 2.8 GHz.
The full-scale input level of the ADC12D1800 can be digitallytrimmed from +2 dBm to +4 dBm to simplify system calibration.
A built-in AutoSync feature supports A/D synchronization
across multiple boards.
The A/D digital outputs are delivered into the Kintex UltraScale
FPGA for signal processing, data capture or for routing to otherboard resources.

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In single-channel mode, all of 5 GB are used to store the singlechannel of input data. In dual-channel mode, one half of thememory stores data from input channel 1 and the other halfstores data from input channel 2. In both modes, continuous,full-rate transient capture of 12-bit data is supported.
The memory bank is supported with a DMA engine for moving
A/D data through the PCIe interface. This powerful linked-list
DMA engine is capable of a unique Acquisition Gate Drivenmode. In this mode, the length of a transfer performed by a link
definition need not be known prior to data acquisition; rather, it
is governed by the length of the acquisition gate. This isextremely useful in applications where an external gate drives
acquisition and the exact length of that gate is not known or is
likely to vary.
For each transfer, the DMA engine can automatically construct
metadata packets containing a sample-accurate time stampand data length information. These actions simplify the hostprocessor’s job of identifying and executing on the data.

DDC IP CORES
Within the FPGA is a powerful DDC IP core. The core supports asingle-channel mode, accepting data samples from the A/D atthe full 3.6 GHz rate. Additionally, a dual-channel mode supports
the A/D 1.8 GHz two-channel operation.
▪ In single-channel mode, decimation can be programmed
to 8 or 16 to 512 in steps of 16.
▪ In dual-channel mode, decimation can be programmed to4 or 8 to 256 in steps of 8 and both channels share thesame decimation rate.
▪ In either mode, the DDC can be bypassed completely.
The decimating filter for each DDC accepts a unique set ofuser-supplied 16-bit coefficients. The 80% default filters deliver
an output bandwidth of 0.8*ƒs/N, where N is the decimation
setting. The rejection of adjacent-band components within the80% output bandwidth is better than 100 dB. Each DDC delivers
a complex output stream consisting of 16-bit I + 16-bit Q
samples at a rate of ƒs/N.

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TECHNICAL DATA SHEETJade 78841

CLOCKING AND SYNCHRONIZATIONMEMORY RESOURCES

The 78841 accepts a 1.8 GHz dual-edge sample clock via a frontpanel SSMC connector. A second front panel SSMC accepts aTTL signal that can function as Gate, PPS or Sync.

The 78841 architecture supports a 5 GB bank of DDR4 SDRAM
memory. User-installed IP along with the Mercury-supplied
DDR4 controller core within the FPGA can take advantage of thememory for custom applications.

A front panel µSync bus connector allows multiple boards to besynchronized, ideal for multichannel systems. The µSync bus
includes gate, reset, and in and out reference clock signals. Two78841s can be synchronized with a simple cable. For larger
systems, multiple 71841’s can be synchronized using the Model
7892 high-speed sync module to drive the sync bus.

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PCI EXPRESS INTERFACEThe 78841 includes an industry standard interface fully compliant
with PCI Express Gen. 1, 2, and 3 bus specifications. Supporting PCIe
links up to x8, the interface includes multiple DMA controllers for
efficient transfers to and from the module.

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TECHNICAL DATA SHEETJade 78841

NAVIGATOR DESIGN SUITE
For applications that require specialized functions, the Navigator
Design Suite allows customers to fully utilize the processing
power of the FPGA. It includes an FPGA design kit for integrating
custom IP into the factory-shipped design, and a board support
package for creating host applications for control of all hardware
and FPGA IP-based functions.

Navigator FDK includes an IP core library of more than 100
functions representing a wealth of resources for DSP, data
formatting, timing, and streaming operations, all based on thepowerful AXI4 standard. multilevel documentation for each IP
core is a mouse click away, and fully consistent with Xilinx IPcores.

The Navigator FPGA Design Kit (FDK) for the Xilinx® Vivado®
Design Suite includes the complete Vivado project folder foreach Jade product with all design files for the factory-installed
FPGA IP. Vivado’s IP Integrator is a graphical design entry toolthat visually presents the complete block diagram of all IP blocks
so the developer can access every component of the Jade
design. Developers can quickly import, delete, and modify IP
blocks and change interconnection paths using simple mouse
operations.

The Navigator Board Support Package (BSP) provides
software support for Jade boards. It enables operational control of all
hardware functions on the board and IP functions in the FPGA. The
BSP structure is designed to complement the functions of the FDK bymaintaining a one-to-one relationship between FDK and BSP
components. For each IP block found in the FDK library, a matchingsoftware module can be found in the BSP. This organization simplifies
the creation and editing of software to support new IP functions andmodifications to existing IP cores.

Navigator IP FPGA Design viewed in IP Integrator

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TECHNICAL DATA SHEETJade 78841

Because all Jade boards are shipped with a full suite of built-in
IP functions and numerous software examples, new applications
can be developed by building on the provided software
examples or built entirely new with the BSP extensive libraries.
All BSP libraries are provided as C-language source for fullaccess and code transparency.

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The Navigator BSP includes the Signal Viewer, a full-featured
analysis tool, that displays data in time and frequency domains.
Built-in measurement functions display 2nd and 3rd harmonics,
THD (total harmonic distortion), and SINAD (signal to noise anddistortion). Interactive cursors allow users to mark data points
and instantly calculate amplitude and frequency of displayedsignals. With the Signal Viewer users can install the Jade board
and Navigator BSP and start viewing analog signals immediately.

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TECHNICAL DATA SHEETJade 78841

FRONT PANEL CONNECTIONSSPECIFICATIONS

The front panel includes four SSMC coaxial connectors forclock, PPS, and analog input signals, and a 19-pin µSync
input/output connector. The front panel also includes five LEDindicators.

Front Panel Analog Signal Inputs▪ PPS Input Connector: One SSMC coaxial
connector, labeled PPS IN, for input of an
external PPS or Gate signal.
▪ PPS LED: The green PPS IN LED illuminates
when a valid PPS signal is detected. This LED
will blink at the rate of the PPS signal.
▪ Sync Bus Connector: A µSync 19−pinconnector, labeled SYNC\GATE, provides
clock reset, reference clock, and gate inputs
for A/D processing, and a reference clock
output for synchronizing multiple boards
using an external sync module.
▪ Over Temperature LED: The red TMP LEDilluminates when an over−temperature orover−voltage condition is indicated by any of
the temperature/voltage sensors on the PCB.
▪ Link LED: The green LNK LED illuminates inthe following ways when a valid link has been
established over the PCIe interface: Gen 1 −the LED blinks slowly (less than once persecond); Gen 2 − the LED blinks about onceper second; Gen 3 − the LED is constantly on.
▪ Analog Input Connectors: Two SSMC coaxial connectors,labeled IN 1 and IN 2, for analog signal inputs to theADC12D1800 A/D converter. IN 1 is connected to the Q inputof the ADC12D1800; IN 2 is connected to the I input.
▪ ADC Overload LED: There is one red OV overload LED forthe A/D input. This LED indicates an overload detection inthe ADC12D1800, or an ADC FIFO overrun.
▪ Clock Input Connector: One SSMC coaxial connector,
labeled EXT CLK IN, for input of an external sample clock
for the ADC12D1800 A/D converter.
▪ Clock LED: The green EXT CLK IN LED illuminates when avalid sample clock signal is detected. If the LED is notilluminated, no clock has been detected and no data fromthe input stream can be processed.

Input Type: Transformer-coupled, front panel female SSMC
connectors

A/D Converters
Type: Texas Instruments ADC12D1800
Sampling Rate: Single-channel mode: 500 MHz to 3.6 GHz;
dual-channel mode: 150 MHz to 1.8 GHz
Resolution: 12 bits
Input Bandwidth: single-channel mode: 1.75 GHz; dualchannel mode: 2.8 GHz
Full Scale Input Level: may be trimmed from +2 dBm to+4 dBm with a 15-bit integer

Digital Downconverters
Modes: One or two channels, programmable
Supported Sample Rate: One-channel mode: 3.6 GHz, twochannel mode: 1.8 GHz
Single-channel mode: decimation can be programmed to 8 or
16 to 512 in steps of 16
Dual-channel mode: decimation can be programmed to 4 or 8
to 256 in steps of 8; both channels share the same
decimation value
Either mode: the DDC can be bypassed completely
LO Tuning Freq. Resolution: 32 bits, 0 to ƒs
LO SFDR: >120 dB
Phase Offset Resolution: 32 bits, 0 to 360 degrees
FIR Filter: User-programmable 18-bit coefficients
Default Filter Set: 80% bandwidth, <0.3 dB passband ripple,>100 dB stopband attenuation

Sample Clock Source
Front panel SSMC connector

Timing Bus
19-pin µSync bus connector includes sync and gate/trigger
inputs, CML

External Trigger Input
Type: Front panel female SSMC connector, LVTTL
Function: Programmable functions include: trigger, gate,
sync and PPS

Field Programmable Gate Array
Standard: Xilinx Kintex UltraScale XCKU035-2
Option -084: Xilinx Kintex UltraScale XCKU060-2
Option -087: Xilinx Kintex UltraScale XCKU115-2

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TECHNICAL DATA SHEETJade 78841

Custom I/O

ORDERING INFORMATION

Option -104: Installs a connector with 24 LVDS pairs to theFPGAModel

Description

Option -105: Installs a connector for one 8X gigabit serial linkto the FPGA

78841

1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D with Wideband
DDC, Kintex UltraScale FPGA - x8 PCIeMemory
Type: DDR4 SDRAM
Size: 5 GB

Options:-084

XCKU060-2 FPGA-087

XCKU115-2 FPGA-104

LVDS FPGA I/O-105

Gigabit serial FPGA I/OStandard: L0 (air-cooled)-702

Air-cooled, Level 2▪ Operating Temp: 0° to 50° C

Contact Mercury for compatible option combinations and complete
specifications of rugged and conduction-cooled versions. Options maychange, so be sure to contact Mercury for the latest information.

Speed: 1200 MHz (2400 MHz DDR)

PCI-Express Interface
PCI Express Bus: Gen. 1, 2 or 3: x4 or x8

Environmental▪ Storage Temp: -20° to 90° C▪ Relative Humidity: 0 to 95%, non-condensing
Option -702: L2 (air-cooled)

ACCESSORY PRODUCTS▪ Operating Temp: -20° to 65° C

Model

Description

2171

Cable Kit: SSMC to SMA

7892

High-Speed Synchronizer and Distribution Board▪ Storage Temp: -40° to 100° C▪ Relative Humidity: 0 to 95%, non-condensing

PhysicalDimensions: Half-length PCIe card
▪ Depth: 181.10 mm (7.13 in)▪ Height: 111.25 mm (4.38 in)
Weight: Approximately 14 oz (400 grams)

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TECHNICAL DATA SHEETJade 78841

DEVELOPMENT SYSTEMSLIFETIME SUPPORT FOR JADE PRODUCTS

Mercury offers development systems for Jade products. They
come with all pre-tested software and hardware ready for
immediate operation. These systems are intended to saveengineers and system integrators the time and expense
associated with building and testing a development system thatensures optimum performance of Jade boards. Please contact
Mercury to configure a system that matches your requirements.

Mercury offers worldwide customers shorter development time,
reliable, rugged solutions for a variety of environments, reduced
costs, and mature software development tools. We offer freelifetime support from our engineering staff, which customers
can depend on through phone and email, as well as software
updates. Take advantage of our 40 years of experience indelivering high-performance radar, communications, SIGINT,
EW, and data acquisition MIL-Aero solutions worldwide.

FORM FACTORSJade products are available in standard form factors including
3U VPX, 6U VPX, PCIe, and XMC. The Jade Model 71841 XMC (1Channel 3.6 GHz or 2-Channel 1.8 GHz 12-bit A/D with DDC,
Kintex UltraScale FPGA) has the following variants:
Model
52841

3U VPX board (single XMC)

57841

6U VPX board (single XMC)

58841

6U VPX board (dual XMC)

71841

XMC module78841

PCIe board (single XMC)

Corporate Headquarters
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Andover, MA 01810 USA+1 978.967.1401 tel+1 866.627.6951 tel+1 978.256.3599 fax

International Headquarters
Mercury International

Learn more

Avenue Eugène-Lance, 38PO Box 584
CH-1212 Grand-Lancy 1Geneva, Switzerland

For technical details, contact:mrcy.com/go/CF78841

Visit: mrcy.com/go/MP78841+41 22 884 5100 tel

The Mercury Systems logo and the following are trademarks or registered trademarks of Mercury Systems, Inc.: Mercury Systems, Innovation That
Matters, Jade and Navigator. Other marks used herein may be trademarks or registered trademarks of their respective holders. Mercury believes
this information is accurate as of its publication date and is not responsible for any inadvertent errors. The information contained herein is subject
to change without notice.
© 2023 Mercury Systems, Inc. 1-0-020623-DS-J78841

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