DATASHEETFMC150
Dual 14-bit A/D & Dual 16-bit D/ADual 14-bit A/D & Dual 16-bit D/A
FEATURES:• Quad Channel Operation-- 2-channels 14-bit A/D up to250 Msps-- 2-channels 16-bit D/A up to800 Msps

• VITA 57.1-2010 compliant• Conduction Cooled - StandardOption• Single ended AC-coupled
analog signals• 6 MMCX/SSMC connectors
available from the front panel• Clock Source, Sampling
Frequency, and Calibration
settings through SPI
communication busses

The FMC150 is a dual channel A/D and dualchannel D/A FMC daughter card. The cardprovides two 14-bit A/D channels and two
16-bit D/A channels which can be clocked
by an internal clock source (optionally lockedto an external reference) or an externallysupplied sample clock. In addition there is one
trigger input for customized sampling control.
The FMC150 daughter card is mechanicallyand electrically compliant with FMC standard(ANSI/VITA 57.1).
The LPC (low-pin count)-compatible FMC150
has front panel I/O and can be used in
conduction-cooled environment. The designis based on TI’s ADS62P49 dual channel
14-bit 250Msps ADC and TI’s DAC3283 dual

ANSI/VITA 47• Flexible clock tree enables:-- internal clock source (VCXO)-- external sampling or
reference clock• Power-down modes to switch
off unused functions for
system power savings

The FMC150 allows flexible control onclock source, analog input gain, and offset
correction through serial communication
busses. Furthermore the card is equippedwith power supply and temperaturemonitoring and offers several power-downmodes to switch off unused functions,
reducing system level power and heat andis well suited for software defined radio(SDR), battery or other low power source
applications. This is ideal for applications suchas airborne where power demand effects
mission range and on-station mission time.

Air-cooled

Conduction-cooled

EAC4

EAC6

ECC1

ECC4

Operatingtemperature

0C to +55C

-40C to +70C

0C to +55C

-40C to +85C

Storagetemperature-40C to +85C

-50C to +100C-40C to +85C

-55C to +105C

Humidity

95%

95%

95%

95%

Operating vibration

5Hz to 100Hz PSD =0.04g2/Hz

5Hz to 100H PSD =0.04g2/Hz

100 Hz to 1000 Hz
PSD = 0.04 gs^2/Hz

100 Hz to 1000 Hz
PSD = 0.04 gs^2/Hz

5 Hz to 100 Hz PSD
increasing at 3 dB/octave

5 Hz to 100 Hz PSD
increasing at 3 dB/octave

1000 Hz to 2000 Hz
PSD decreasing at 6dB/octave

1000 Hz to 2000 Hz
PSD decreasing at 6dB/octave

100 Hz to 1000 Hz
PSD = 0.1 g2/Hz

100 Hz to 1000 Hz
PSD = 0.1 g2/Hz

1000 Hz to 2000 Hz
PSD decreasing at 6dB/octave

1000 Hz to 2000 Hz
PSD decreasing at 6dB/octave

Operating shock

20g, 11 millisecond,
half-sine or 20g, 11
millisecond, terminal
sawtooth shock
pulses in all threeaxes

20g, 11 millisecond,half-sine or 20g, 11millisecond, terminal
sawtooth shock
pulses in all threeaxes

40g, 11 millisecond
shock half-sine or
40g, 11 millisecond,
terminal sawtooth
shock pulses in all
three axes

40g, 11 millisecond
shock half-sine or
40g, 11 millisecond,
terminal sawtooth
shock pulses in all
three axes

Operating altitude-1500 ft to 60,000 ft(with airflow)-1500 ft to 60,000 ft(with airflow)-1500 ft to 60,000 ft-1500 ft to 60,000 ft

Conformal coating

Optional

Optional

Optional

Optional• Mil-I-46058c ConformalCoating Compliant (optional)• LPC (low-pin count)compatible• LVDS and 1.65V to 3.3V IO
signalling

channel 16-bit 800Msps DAC. The analog
signals are AC coupled connecting to MMCXor SSMC coax connectors on the front panel.

DATASHEETFMC150 Dual 14-bit A/D & Dual 16-bit D/A Dual 14-bit A/D & Dual 16-bit D/ASpecifications

Support• Stellar IP available for this product. A
simple way to design FPGA firmware with
automated code and bitstream generation.
• Reference firmware design (VHDL)• Reference designs available for multiple
FPGA carriers• User Manual
AS9100 Certified

Channel A
A/DACCoupling

Channel B

ACCoupling

LVDS Clo ck [1]

ADS62P49/
ADS4249
250 Msps, 14-bit

LVDS Data [14]Control

FMC Low-pin Count 160-pins
LVDS / LVCMOS 2.5V

Application• Direct RF Down Conversion• Software defined radio (SDR)• RADAR/SONAR• Ultra Wideband Satellite Digital Receiver• Medical equipment• Aerospace and test instrumentation

Block diagram

Monitoring
AMC7823

Clock tree
CDCE72010

External Clock/
Reference
ExternalTrigger

LVDS Clo ck [1]Control
LVDS Trigger [1]ACCoupling

Channel CD/A
Channel DACCoupling

DAC3283
800 Msps
16-bit

LVDS Clo ck [1]
LVDS Data [8]
LVDS Frame [1]Control

Ordering information
Talk to us about your algorithmic requirements, Abaco Systems is a full-service firmware and software development house. We are a specialist at high performance FFT and Video Processing. Check with us, we may have IP
Cores that meet requirements for your application, right off the shelf.

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