TECHNICAL DATA SHEET

Quartz 6353S
8-channel RF A/D & D/A small form factor subsystemwith Xilinx Zynq UltraScale+ RFSoC - Gen 3

Ideal for integration
into custom enclosures▪ High-bandwidth data streaming▪ Waveform signal generator▪ Analog I/O for digital recording andplayback▪ Communication receiver and transmitter▪ Sensor interfaces▪ Electronic Warfare transponder

The Quartz ® 6353S is a high-performance RF converter andprocessing subsystem in a small, rugged module. Designed to be
integrated into larger systems with minimal design effort, the 6353S
delivers the performance and high-channel density of RFSoC in a small,convenient footprint.
Complementing the RFSoC’s on-chip resources are the 6353S’s sophisticated clocking
section, a low-noise front end for RF input and output, 16 GBytes of DDR4, an 8-lane
gigabit serial interface operating at 28 Gbits/sec, and general-purpose I/O signal paths tothe FPGA.

FEATURES▪ Complete RF converter and processing subsystem▪ Rugged and conduction-cooled▪ Ideal for integration into custom enclosures▪ Incorporates Xilinx® Zynq® UltraScale+™ Gen 3 RFSoC▪ 16 GB of DDR4 SDRAM▪ Navigator® BSP for software development▪ Navigator® FDK for custom IP development▪ Free lifetime applications support

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Sample ClkBalun

Balun

Balun

Balun

Balun

RF Out 4

RF Out 5

RF Out 6

RF Out 7

RF Out 8

Antenna InBalun

Balun

RF In 8

RF Out 3Balun

RF In 7Balun

Balun

RF In 6Balun

Balun

RF In 5

RF Out 1Balun

RF Out 2Balun

RF In 3Balun

RF In 4Balun

RF In 1

Timing BusGenerator

RF In 2Gate / Trigger

Reference Sync

Reference ClkFrequency
Synthesizer

A/D Clocks

RF Out 2through 7

RF In 2through 7SysRef

D/A Clocks

GPS

D/A Output
1 -8

A/D Input
1 -8

Programmable
Logic

ZYNQ
UltraScale+
RFSoC FPGA64

DDR4SDRAM
4/8 GB

GTY

LVDS

Processing
SystemGTR

JTAG

POWER
Battery
MANAGEMENTManagement

Model 6353S Quartz

VPX VBAT

Battery

X81264

ConfigFLASH

DDR4SDRAM
4/8 GBUSS 2.0

RS-232

SGMII

Power
Management

Model 6003 QuartzXM eXpress Module

10 GHz14-BIT
D/A & DUC
Channels
1-8

5 GHz
14-bitA/D & DDC
Channels
1-8

RF Signal
Chain

Clock
Management

EMMC
Memory12 V

X812 V

DriverDriverDriverCircularConnector

RS-485Connector

CircularConnector

Circular
JTAG Connector

RS-232

1 GigEUSB 2.0

ENET PHYConnector

TECHNICAL DATA SHEET
Quartz 6353S6353S BLOCK DIAGRAM

Click on a block for more information.

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Quartz 6353S

ARCHITECTURE
The 6353S design places the RFSoC as the cornerstone of thearchitecture. All control and data paths are accessible by theRFSoC’s programmable logic and processing subsystem. A fullsuite of Mercury-developed IP and software functions utilize
this architecture to provide data capture, processing andwaveform generating solutions for many of the most common
application requirements.

EXTENDABLE IP DESIGNFor applications that require specialized functions, users caninstall their own custom IP for data processing. The Navigator
FPGA Design Kit (FDK) includes the board’s entire FPGA design
as a block diagram that can be edited in Xilinx’s Vivado® IP
Integrator. In addition to the IP Integrator block diagrams, allsource code and complete IP core documentation is included.
Developers can integrate their own IP along with the factoryinstalled functions or use the Navigator kit to completely
replace the IP provided by Mercury with their own.
The Navigator Board Support Package (BSP), the companion
product to the Navigator FDK, provides a complete C-callable
library for control of the 6353S’s hardware and IP. The Navigator
FDK and BSP libraries mirror each other where each IP function
is controlled by a matching software function, simplifying thejob of keeping IP and software development synchronized.
The Navigator BSP includes support for Xilinx's PetaLinux runningon the ARM Cortex-A53 processors. When running underPetaLinux, the Navigator BSP libraries enable complete control ofthe 6353S either from applications running locally or on the ARMs,or using the Navigator API control and command from remotesystem computers.

A/D CONVERTER STAGE
The 6353S accepts analog IF or RF inputs on eight coax
connectors. These inputs are transformer-coupled into the RF
signal chain of the RFSoC. Inside the RFSoC, the analog signals
are routed to eight 5 GSPS, 14-bit A/D converters. Eachconverter has built-in digital downconverters with
programmable 1x, 2x, 3x, 4x, 5x, 6x, 8x, 10x, 12x, 16x, 20x, 24x, or40x decimation and independent tuning. The A/D digital outputs
are delivered into the Zynq’s programmable logic and processor
subsystem for signal processing, data capture, or for routing toother resources.

reduction, ideal for applications that need to stream data fromall eight A/Ds.

D/A CONVERTER STAGE
The RFSoC’s eight D/A converters accept baseband real orcomplex data streams from the FPGA’s programmable logic.
Each 9.85 GSPS, 14-bit D/A includes a digital upconverter withindependent tuning and interpolations of 1x, 2x, 3x, 4x, 5x, 6x,8x, 10x, 12x, 16x, 20x, 24x, or 40x. Each D/A output istransformer-coupled to a coax connection located on the edgeof the module.

CLOCKING AND SYNCHRONIZATION
An on-board timing bus generator uses a programmablefrequency synthesizer to generate the sample clock and all
required timing signals. The on-board sample clock can also belocked to a reference clock received through a coax connector.
A multifunction gate/trigger input is also available for external
control of data acquisition and playback.

MEMORY RESOURCES
The 6353S architecture supports 8 GBytes of DDR4 SDRAM memoryaccessible from the Programmable Logic. User-installed IP, whichalong with the Mercury-supplied DDR4 controller core within theFPGA, can take advantage of the memory for custom applications.
An additional 8 GByte bank of DDR4 SDRAM is available to theProcessing Subsystem as program memory and storage.

HIGH-SPEED GIGABIT SERIAL INTERFACEThe 6353S supports eight 28 Gb/sec full duplex lanes. Users canchoose to connect to other serial-enabled devices with highspeed copper cables or connect to a copper-to-opticalinterface for enabling long transfer distances. With the 100 GigEUDP interfaces provided with the Navigator FPGA Design Kit, orinstallation of a user-provided serial protocol, this opticalinterface enables a high-speed gigabit data streaming path
between the module and data storage or other processing
components.

GPSA GPS receiver provides time and position information to theFPGA and ARM processors. This information can be used for
precise data tagging. The GPS provides a 1 PPS signal and areference clock to the FPGA.

In addition to the A/D’s built-in decimation, an additional stageof IP-based decimation provides another 16x stage of datamrcy.com

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TECHNICAL DATA SHEET
Quartz 6353S

DESIGNED FOR STREAMLINED INTEGRATION
Model 6353S is a complete RF converter and processing system in a small,rugged module. Requiring only a single 12V power supply, the module can be
integrated as a component in a larger system with minimal design effort.

All analog I/O and control and communication interfaces
are easily accessible, simplifying connections to othersystem components.

The bottom surface of the module provides an efficient
thermal interface, enabling conduction-cooling andallowing fan-less operation in most installations.

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TECHNICAL DATA SHEET
Quartz 6353S

NAVIGATOR DESIGN SUITE
For applications that require specialized functions, the Navigator
Design Suite allows customers to fully utilize the processing
power of the FPGA. It includes an FPGA design kit for integrating
custom IP into the factory-shipped design, and a board support
package for creating host applications for control of all hardware
and FPGA IP-based functions.
The Navigator FPGA Design Kit (FDK) for the Xilinx® Vivado® Design
Suite includes the complete Vivado project folder for each Jadeproduct with all design files for the factory-installed FPGA IP.
Vivado’s IP Integrator is a graphical design entry tool that visuallypresents the complete block diagram of all IP blocks so thedeveloper can access every component of the Jade design.
Developers can quickly import, delete, and modify IP blocks andchange interconnection paths using simple mouse operations.

Navigator FDK includes an IP core library of more than 100
functions representing a wealth of resources for DSP, data
formatting, timing, and streaming operations, all based on thepowerful AXI4 standard. multilevel documentation for each IP coreis a mouse click away, and fully consistent with Xilinx IP cores.
The Navigator Board Support Package (BSP) provides
software support for Jade boards. It enables operational
control of all hardware functions on the board and IP functionsin the FPGA. The BSP structure is designed to complement thefunctions of the FDK by maintaining a one-to-one relationshipbetween FDK and BSP components. For each IP block found in
the FDK library, a matching software module can be found in
the BSP. This organization simplifies the creation and editingof software to support new IP functions and modifications toexisting IP cores.

Navigator IP FPGA Design viewed in IP Integrator

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Quartz 6353S

Because all Jade boards are shipped with a full suite of built-in
IP functions and numerous software examples, new applications
can be developed by building on the provided software
examples or built entirely new with the BSP extensive libraries.
All BSP libraries are provided as C-language source for fullaccess and code transparency.

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The Navigator BSP includes the Signal Viewer, a full-featured
analysis tool, that displays data in time and frequency domains.
Built-in measurement functions display 2nd and 3rd harmonics,
THD (total harmonic distortion), and SINAD (signal to noise anddistortion). Interactive cursors allow users to mark data points
and instantly calculate amplitude and frequency of displayed
signals. With the Signal Viewer users can install the Jade boardand Navigator BSP and start viewing analog signals immediately.

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TECHNICAL DATA SHEET
Quartz 6353S

SPECIFICATIONS

Digital Upconverters

Field Programmable Gate Array▪ Quantity: 1 per D/A

Type: (standard) Xilinx Zynq UltraScale+ RFSoC XCZU47DR▪ Option -048: Xilinx Zynq UltraScale+ RFSoC XCZU48DRSpeed: (standard) -1 speed grade▪ Option -002: -2 speed grade

RFSoC RF Signal Chain
Analog Inputs▪ Quantity: 8▪ Location: Front edge (A/D In Channels 1-8)

▪ Interpolation Range: 1x, 2x, 3x, 4x, 5x, 6x, 8x, 10x, 12x, 16x,20x, 24x, and 40x (not all interpolations are supported bydefault IP)▪ LO Tuning Freq. Resolution: 48 bits
▪ Filter: 80% pass band, 89 dB stop-band attenuation
Sample Clock▪ Source: On-board programmable clock
Reference Clock▪ Connector Type: U.FL

▪ Source: On-board oscillator, on-board GPS, or externalsource▪ Input Type: Transformer-coupled▪ External Source Location: Top panel (Reference Clock In)▪ Transformer Type: Mini-Circuits TCM1-83X+▪ Connector Type: U.FL

▪ Full Scale Input: +10 dBm into 50 ohms

▪ Level: -10 dBm to +24 dBm

A/D Converters

Gate/Trigger▪ Quantity: 8▪ Sampling Rate: 5.0 GHz▪ Source: Programmable through software or externalconnector▪ Resolution: 14 bits

▪ External Source Location: Top panel (Reference Clock In)

Digital Downconverters▪ Connector Type: U.FL

▪ Quantity: 1 per A/D▪ Level: TTL▪ Decimation Range: 1x, 2x, 3x, 4x, 5x, 6x, 8x, 10x, 12x, 16x,20x, 24x, and 40x (not all decimations are supported bydefault IP)▪ LO Tuning Freq. Resolution: 48 bits, 0 to ƒs▪ Filter: 80% pass band, 89 dB stop-band attenuation
Analog Outputs▪ Quantity: 8▪ Location: Front edge (D/A Out Channels 1-8)
▪ Connector Type: U.FL
▪ Output Type: Transformer-coupled▪ Transformer Type: Mini-Circuits TCM1-83X+▪ Full Scale Output: 0 dBm into 50 ohms
D/A Converters▪ Quantity: 8▪ Sampling Rate: (standard) 8.92 GHz▪ With -2 speed grade (option -002): 9.85 GHz▪ Resolution: 14 bits

GPSSource: On-board
Antenna Connector Location: Top panel (GPS Antenna)
Connector Type: U.FL

RFSoC Processing System
ARM Cortex-A53:▪ Quantity: 4▪ Speed: 1.5 GHz
ARM Cortex-R5:▪ Quantity: 2▪ Speed: 600 MHz
Processor I/O:
▪ Interfaces: USB 2.0 and RS-485▪ Location: Rear edge (USB & RS485)▪ Connector Type: Circular, Glenair Mighty Mouse Series▪ Interface: 1 GigE
▪ Location: Rear edge (1000 Base-T)▪ Connector Type: Circular, Glenair Mighty Mouse Series

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TECHNICAL DATA SHEET
Quartz 6353S▪ Interface: RS-232

Physical▪ Location: Rear edge (JTAG & RS-232)

Dimensions:▪ Connector Type: Circular, Glenair Mighty Mouse Series▪ Depth: 170 mm (6.7 in)

FPGA I/O▪ Height: 38 mm (1.5 in)Interface: GTY▪ Width: 117 mm (4.6 in)Quantity: 8 full duplex lanes

Weight: 29.8 oz.

Speed: 8 Gb/sec

PowerLocation: Top panel (GTY 1-4 & GTY 5-8)Voltage: +12Connector Type: Samtec ARF6Location: Top panel (+12V)

Protocol: 100 GigE UDP IP core provided in Navigator FPGA
Design Kit or user-suppliedConnector Type: Molex IPL1

JTAG

Maximum Power Consumption: 46.62 Watts

Location: Rear edge (JTAG/RS-232)
Connector Type:Circular, Glenair Mighty Mouse Series

MemoryProcessing System:▪ Type: DDR4 SDRAM▪ Size: 8 GB
▪ Speed: 1200 MHz (2400 MHz DDR)
Type: eMMC
▪ Size: 64 GB
Programmable Logic:▪ Type: DDR4 SDRAM▪ Size: 8 GB
▪ Speed: 1200 MHz (2400 MHz DDR)FPGA Configuration FLASH:▪ Type: QSPI NOR Flash▪ Size: 2x 1 Gb

Environmental
Option -703: Level L3 (conduction-cooled)▪ Operating Temp: –20° to 60° C (with 50° C cold plate)▪ Storage Temp: –50° to 100° C▪ Relative Humidity: 0 to 100%

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TECHNICAL DATA SHEET
Quartz 6353S

ORDERING INFORMATION

LIFETIME SUPPORT FOR QUARTZ PRODUCTS

Model

Description

6353S

8-Channel RF A/D & D/A Subsystem in a small form
factor with Xilinx Zynq UltraScale+ RFSoC - Gen 3Options

Description-002-2 FPGA speed grade, -1 standard-048XCZU48DR FPGA (XCZU47DR is standard)-703

Air-cooled, Level L3

Mercury offers worldwide customers shorter development time,
reliable, rugged solutions for a variety of environments, reduced
costs, and mature software development tools. We offer freelifetime support from our engineering staff, which customers
can depend on through phone and email, as well as software
updates. Take advantage of our 40 years of experience indelivering high-performance radar, communications, SIGINT,
EW, and data acquisition MIL-Aero solutions worldwide.

Contact Mercury for compatible option combinations.

ACCESSORY PRODUCTS
ModelDescription

21876353S Accessories

OptionDescription-150

Development cable set without optical cable-151

Development cable set with optical cable-701

Top cover plate with built-in fan, replaces standard top
plate for benchtop cooling

Corporate Headquarters
50 Minuteman Road
Andover, MA 01810 USA+1 978.967.1401 tel+1 866.627.6951 tel+1 978.256.3599 fax

International Headquarters
Mercury International

Learn more

Avenue Eugène-Lance, 38
PO Box 584
CH-1212 Grand-Lancy 1Geneva, Switzerland

For technical details, contact:mrcy.com/go/CF6353S

Visit: mrcy.com/go/MP6353S+41 22 884 5100 tel

The Mercury Systems logo and the following are trademarks or registered trademarks of Mercury Systems, Inc.: Mercury Systems, Innovation ThatMatters, Quartz and Navigator. Other marks used herein may be trademarks or registered trademarks of their respective holders. Mercury believes
this information is accurate as of its publication date and is not responsible for any inadvertent errors. The information contained herein is subject
to change without notice.
© 2022 Mercury Systems, Inc. 1-0-101822-DS-Q6353S

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