Selected Papers

Silicon Single-Electron Devices
Yasuo Takahashi†, Yukinori Ono, Akira Fujiwara, andHiroshi Inokawa
Abstract
Single-electron devices (SEDs) are attracting a lot of attention as devices for future large-scale integration because of their inherent low power and small size. We have developed a novel method of fabricating small Si single-electron transistors (SETs) called pattern-dependent oxidation (PADOX) and used
it to make many kinds of SEDs. The low power consumption of SEDs is useful for logic circuits. In addition, SETs have two unique features that conventional transistors do not have: multi-input gate capability and conductance that oscillates as a function of gate voltage. We exploit these features to achievecomplicated functions for logic circuits, such as multiple-valued logic.

Recent rapid progress in silicon CMOS (complementary metal oxide semiconductor) LSIs (largescale integrated circuits) has made possible highlysophisticated information processing and communication tools, such as personal computers and cellular
phones, which enable us to process a great deal of
information. This progress is enabled by the miniaturization of Si MOS transistors, which proceeds
according to Moore’s law. Figure 1 shows predictedfeature sizes of transistors. Within 15 years, the device
size will be on the nanometer order [1]. However,higher levels of integration produce greater power
dissipation in a small Si chip. Even now, the power
consumption of some microprocessor chips used inpersonal computers is more than 50 W. This rise inpower will suppress further integration, which will
limit the functionality of information processing andcommunication tools. That is to say, the device temperature cannot exceed the cooling limit. In addition,
for mobile applications, which are going to become
more widespread and important, we must extend battery life [2]. Therefore, we must develop new devices† NTT Basic Research Laboratories
Atsugi-shi, 243-0198 Japan
E-mail: ytaka@aecl.ntt.co.jp

Vol. 2 No. 2 Feb. 2004

for future information technology that enable us toachieve low power consumption as well as high functionality. Single-electron devices (SEDs) are the key
to minimizing power consumption because they cancontrol the transfer of individual electrons [3]-[5]. In
addition, such devices have high functionality thatconventional transistors do not have; for example,
they can support multiple gates and exhibit conductance characteristics that oscillate as a function ofgate voltage. We can exploit these special features toachieve high performance with low power dissipation.
200
Gate length of MOSFETs (nm)1. Introduction

100

10

2
2000

2005

2010
Year

2015

2020

Fig. 1. Gate lengths of MOSFETs predicted inInternational Technology Roadmap for
Semiconductors [1].

21Selected Papers

Gate

SET island

Gate

Vg
SET islandisland should be small to maintain the Coulomb
blockade condition, i.e., e2/(2Ctotal) > 3.5 kT, where
Ctotal is the total capacitance of the SET island. The
SET island must be smaller than 10 nm for room-temperature operation. The most difficult issue in fabricating such a SET is attaching two tunnel capacitors
to the nanometer-scale island. We have already developed a controllable fabrication method called patterndependent oxidation (PADOX) [8]-[10], which converts a small Si wire pattern on an SOI (silicon on
insulator) wafer into a single-electron island with atunnel capacitor at each end. In this method, special
phenomena that occur during the oxidation of Si
nanostructures on SiO2 play a crucial role.
3. SET fabrication by PADOXThe operating principle of the SET allows us to use
any conductive material—metal or semiconductor—
as a base material. Among the available materials, silicon is one of the best candidates because we can utilize sophisticated fabrication processes developed forrecent CMOS LSIs. In addition, the Si/SiO2 system isthe most reliable one, as demonstrated in Si LSIs.
PADOX [8]-[10] uses thermal oxidation, which iswell known as the most dependable and simplest
method of obtaining a stable Si/SiO2 interface. The
initial structure of the SET is a narrow, short onedimensional Si wire fabricated on a thin SOI wafer asshown in Fig. 4. The typical wire width is about 30
nm. The wire height, which is the thickness of the
SOI layer, is also about 30 nm. The wire length is varied to control the island size. The SET fabrication
mechanism is as follows. When a narrow Si wire isthermally oxidized in dry oxygen ambient, the oxidation is suppressed due to the huge stress accumulated

Drain current Id

2. Single-electron transistor (SET)The most primitive SED [6], [7] has a simple threeterminal structure, as shown in Fig. 2. The device
must have a small island together with a gate electrode coupled to the island with gate capacitance Cg.
Source and drain electrodes are attached to the island
via a tunnel barrier. Due to the three-terminal structure, we call this device a single-electron transistor(SET).
The operating principle of the device is based on
the balance of charge between the gate electrode andthe island. When the source and drain terminals are
grounded for simplicity, and when a voltage Vg isapplied to the gate, charge CgVg accumulates in thegate electrode. However, since tunnel barriers isolate
the island from the source and drain, the number ofelectrons in the island should be a fixed integer. The
total charge in the island –Ne, where N is the numberof electrons and e the elementary charge, is balancedwith that in the gate when CgVg = Ne is satisfied. In
this condition, the number of electrons is stable, so N
cannot change. That is, current does not flow throughthe SET island. This is the Coulomb-blockade condition. As the gate voltages increase, the total charge in
the gates increases, and the charges become unbalanced. Then, when CgVg = (N+1/2)e, the electrostatic
potentials of two states (for N and for N+1 electrons)
become equal, which means that the island can contain either N or N+1 electrons. Therefore, electrons
flow one at a time when a small voltage is applied
between the source and drain electrodes. The numberof electrons in the island is N+1 after a single electron
tunnels from the source to the island. The number
returns to N after an electron tunnels from the island
to the drain. When this sequence is repeated, a current
due to single-electron tunneling flows. If the gate
voltages increase further, the number of electrons
becomes stable at N+1. As a result, the source-drain
conductance oscillates as a function of gate voltages,
as shown in Fig. 3.
For a SET to operate at high temperature T, theCg
SourceDrain

SourceDrain

SiO2
Tunnel barrier(tunnel capacitor)

Tunnel barrier(tunnel capacitor)

Fig. 2. Schematic structure and equivalent circuit of a SET.

22

0

1
2
Number of electrons (Cg • Vg/e)3

Fig. 3. Gate-voltage vs. drain current characteristics of a SET.

NTT Technical Review

Selected Papers

1-dimensional Si wire

Accumulation of strong stress
Drain

Gate

Wire region

SourceTop Si layer
SOI wafer

Bandgap reduced by stress

Potential

Buried SiO2
Si substrate

Bandgap increased byquantum confinement

Fig. 4. Initial device structure of the SET before PADOX.
Distance

Vol. 2 No. 2 Feb. 2004

Fig. 5. Schematic plane view of the device and potential
diagram along the Si wire.
0.8

T=40 K

0.6
Drain current (A)in the grown SiO2, which completely surrounds thewire. It has been reported that a compressive stresslarger than 20,000 atm accumulates in the SiO2 whena 10-nm-diameter Si wire is formed by oxidizing a
30-nm-diameter Si wire [11]. When the Si wire structure shown in Fig. 4 is subjected to thermal oxidation,
a compressive stress is exerted on the middle part of
the wire. The 20,000-atm stress produces strain in thewire and reduces the bandgap by about 150 meV. This
reduction cancels out the effective bandgap increaseof about 50 meV due to the quantum size effect in a
5–10-nm Si wire [12], [13]. As a result, the potential
profile is as schematically shown in Fig. 5. The twopotential hills serve as tunnel barriers: a tunnel capacitor is formed between the Si island and the wider Si
layer. This mechanism enables us to make a SET in aself-aligned manner.
The typical electrical characteristics of an Si SET
fabricated by PADOX are shown in Fig. 6. The conductance or current varies depending on the numberof electrons in the SET island, which is different fromthe characteristics shown in Fig. 3. The reason is asfollows. In the case of SETs fabricated from a semiconductor, since there are only a few electrons in theisland, the wave function distribution changes
according to the number of electrons, which affects
the tunnel resistance. This is one of the phenomena ina few-electron regime. It is quite interesting to investigate SETs from the physics viewpoint because
quantum effects play an important role in 10-nmsized Si islands [14]. In this report, however, we focus
on the device application of SETs.
It has generally been said that the greatest drawback of SETs is that the operating characteristics
sometimes change due to the offset charge effect.
However, SETs fabricated by using Si MOS processes are definitely stable against long-term drift, which

0.4

0.2

0

0

0.5

1
Gate voltage (V)1.5

2

Fig. 6. Drain current vs. gate-voltage characteristics
measured at drain voltage of 1 mV.

is essential if they are actually to be used [15], [16].
We have confirmed that the characteristics shown in
Fig. 6 did not change over a seven-year period. Thisis the great advantage of Si SETs [7].
4. Logic circuit application of SETs
SEDs have two main applications: memory andlogic circuits. Since their most prominent feature is
low power operation, the application to logic circuits
seems the most promising. Low power operation isessential to future logic LSIs, in which power dissipation will limit integration levels. In addition,
devices for future LSIs should be small to achieve ahigh integration density as well as low power consumption [7]. As discussed above, the operating principle based on the Coulomb blockade allows the23Selected Papers

device to operate more stably as it becomes smaller.
This is the opposite of the situation in MOSFETs,
where a smaller size creates undesirable characteristics, such as punch through or gate leaks.
In addition, SETs have several other special features that conventional transistors (MOSFETs andbipolar transistors) do not have. As described above,the drain current or conductance shows oscillatory
characteristics according to the number of electrons
in the island. Another special feature is that the operating principle lets the device support multiple gates.
Some SET logic circuits fabricated using PADOX, inwhich these features are exploited, are discussed
below.
4.1 Multigate SETSETs inherently have multiple gates as shown in
the equivalent circuit in Fig. 7. Each gate electrodecouples directly to the SET island with gate capacitance Cgi. As described in section 2, since the total
charge accumulated in gates is ∑CgiVgi, the drain current oscillates as a function of ∑CgiVgi. These characteristics give SETs two special features. One is thatthe source-drain current is determined by the sum of
the products of each gate capacitance Cgi and gate
voltage Vgi. The other special feature of the SET isoscillatory characteristics. The periodically oscillating current characteristics are useful to achieve periodical functions, such as adder or parity check circuits, which are widely used in current logic circuits.
As described in section 2, the drain current is minimum when the sum ∑CgiVgi/e is an integer. Conversely, when the sum is a half integer, the current ismaximum. Conventional devices do not have thesekinds of features.
If all gate capacitances (Cgi) of the SET are thesame Cg0, and if we use an input voltage (Vgi) for
high-level e/(2Cg0), we can obtain the functions of amulti-input exclusive-OR gate. Each high input-gate
can switch the current level from high to low and viceversa. This means that an even number of “HIGH”
gates creates the “LOW state” and an odd number
creates the “HIGH state”. This is exactly the functionof the Exclusive-OR (XOR) gate in a binary logic circuit. We fabricated such a device having two equalgates [17]. SEM images of the device are shown in
Figs. 8(a) and (b). A small one-dimensional Si wire
fabricated on an SOI wafer (Fig. 8(a)) was converted
into a small SET by PADOX. Then, using an electron-beam exposure system with a high overlay accuracy, we attached two ultrafine poly-Si gates so as tocover part of the island as shown in Fig. 8(b). The
24

Gates

Cg1

Cg2

Cg3

Drain

SourceSET island

Cs

Cd
Tunnel capacitanceFig. 7. Equivalent circuit of a multigate SET.
SET island(1D-Si wire)

SET island(1D-Si wire)
(a)

(b)

Fig. 8. SEM image of a dual gate SET before (a) and after(b) the formation of two ultra-fine gate electrodes.

capacitances of the two gates were almost equal dueto the symmetrical configuration. The drain current
oscillation characteristics as a function of one of thegate voltages are shown in Fig. 9(a). Since both gateshave almost the same capacitance of 0.4 aF, the oscillation phase shifts by about π in the negative voltage
direction when one of the gate voltages V g2 ischanged from 0 V to 0.2 V. Figure 9(b) shows thedrain current switching measured at 40 K in responseto the switching of the two input-gate voltages (Vg1and Vg2) between 0 and 0.2 V. Low current levels
were obtained only when the input voltages wereboth high or both low. This represents an XOR-gate
operation, which can be implemented with just one
SET.
This functionality of the multigate SET enables us
to make multibit adders with a small number of transistors without any wire crossing [18]. This is advantageous not only for reducing device area but also forachieving high-speed operation, despite the low drivability of SETs.
4.2 Multiple-valued operation
It is widely known that multiple-valued logic
allows us to reduce the number of transistors and theamount of wiring in LSIs. This is another effective
way to reduce the power dissipation and chip size of
NTT Technical Review

Selected Papers

LSIs. SETs, which have oscillatory conductancecharacteristics, are highly suitable for multiple-valued applications [19], [20], in which the number ofelectrons in the island represents multiple values. To
achieve several stable points, we must attain multipeak negative differential resistance (NDR) characteristics in which the current oscillates as a functionof drain voltage. As shown in Fig. 6, the SET current
oscillating as a function of input gate voltage cannot
be used for a multiple-valued operation, because theSET cannot generate output voltages proportional to
the number of electrons in the SET island. The problem is that the Coulomb blockade is lifted when Vds ishigher than e/Ctotal, which limits the voltage Vds thatcan be applied to the drain terminal.

4

Vg2 =0.2V

Id (nA)3

To overcome this problem, we developed a SETMOSFET combined circuit. We can convert the horizontal axis of current characteristics oscillating as afunction of gate voltage to ones oscillating as a function of drain voltage by connecting a small MOSFET
in series with the SET. One of the great advantages of
the PADOX method is that the basic fabrication
process is compatible with that for conventional
MOSLSIs, which enables us to easily combine SETs
and MOSFETs [19]. The equivalent circuit of thedevice is shown in Fig. 10(a). The gate of a SET isconnected to the drain of a MOSFET. The MOSFET
connected in series keeps the Vds at nearly Vgg – Vth,where Vth is the threshold voltage of the MOSFET. If
Vgg – Vth is set lower than e/Ctotal, clear current oscillation can be retained even when a higher voltage V isapplied at the drain of the MOSFET. By connecting
the SET gate to the MOSFET drain, we obtain multipeak current oscillation as a function of V, resulting
in NDR characteristics such as those schematicallyshown in Fig. 10(b).

V

2

I
Vgg
1
MOSFETVg2 =0V
0
–0.2

–0.1

0

0.1
Vg1 (V)

0.2

0.3

SET

(a)

Vgs

0.2V

Vds〜Vgg–Vth

Vg2
0V
0.2V

(a)
Stability points

Vg1
0V

4

Drain current I

Id (nA)

3

Id

2
1
0

Io

0.4

0

5

10

15

20

25

30

35

1

2

3

4

5

6

Io

40

Time (s)(b)

Fig. 9. Drain current Id vs. gate voltage characteristics ofa dual gate SET (a) and drain current switching
characteristics (b).

Vol. 2 No. 2 Feb. 2004

Numberofelectrons
0

V (V)
(b)

Fig. 10. Equivalent circuit composed of a MOSFET and
SET (a) and schematic two-terminal I-V
characteristics of the circuit (b).

25Selected Papers

Input

Vin
1

analog-to-digital converter [21]. These are advantageous not only for circuit size reduction but also for
low-power operation.

CLK

5. Conclusion

2
3

Output–500-5-4-3-2-100Time (ms)-5-4-3-2-10

Vout

500

Fig. 11. Measured quantizer operation. The operating
speed is not limited by the intrinsic performanceof the device, but by the large capacitanceexisting at Vout.

If a current source I0 is connected to the circuit,many points (indicated by arrows in Fig. 10(b))
become stable. Each stability point corresponds to thenumber of electrons in the island at a particularapplied voltage V. It is advantageous that just twotransistors can provide a multipeak NDR device inwhich the number of the peaks is infinite in principle
within the breakdown voltages of the MOSFET drainor the SET gate. These characteristics can also be
applied to multiple-valued memories [19], [21]. In
conventional multipeak NDR devices, such as resonant tunneling diodes, the same number of devices as
peaks is required.
The most important use of this NDR device withmultiple stability points is to build multiple-valued
logic circuits. One of the basic circuits of multiplevalued logic is a quantizer that discriminates an analog input signal into predefined voltage levels. By
using the circuit shown in Fig. 10(a), we have built aquantizer [18]. Figure 11 shows measured waveforms for Vin, CLK, and Vout of the quantizer. Input
triangular wave Vin, transferred to the drain terminal(V in Fig. 10(a)) according to short clock pulses(CLK), settles down to the stability points, and output
voltage Vout is quantized to the levels 0–5, as shownin the figure. This demonstrates the operation of aquantizer with a six-valued output voltage. Although
the operating speed is rather slow, it is not limited by
the intrinsic performance of the device, but by thelarge capacitance existing at the Vout terminal for themeasurement with an oscilloscope. Based on the circuit shown in Fig. 10(a), we have proposed a fulladder for redundant number representation with avery small number of transistors, and a high-speed
26Single-electron transistors (SETs) have high potential for future large-scale integration because of their
low power consumption and small size. Although it is
not easy to fabricate them because of their small size,
we have developed a novel fabrication method for Si
SETs called pattern-dependent oxidation (PADOX),
which is simple and compatible with the conventional fabrication processes for CMOS LSIs. We havedemonstrated some logic-circuit applications ofdevices fabricated by PADOX. In these applications,
we use the special functional features of the SET,
such as multiple-gate capability and multiple-peakoscillatory characteristics. By exploiting these special features, we can achieve complicated functions
with a small number of transistors, which will reduce
the size and power dissipation of circuits.
References[1]

P. A. Gargini, “Global route to future semiconductor technology,”IEEE Circuits and Devices Magazine, Vol. 18, No. 2, pp. 13-17, 2002,
Home page of International Technology Roadmap for Semiconductors: http://public.itrs.net/.
[2] S. Suzuki, “Research and development to achieve total power management,” NTT Review, Vol. 11, No. 3, pp. 56-61, 1999.
[3] Y. Takahashi, “Single-electron Device—An Ultimate Device That
Operates on Just a Single Electron,” NTT Review, Vol. 12, No. 1, pp.
12-16, 2000.
[4] A. Fujiwara, Y. Takahashi, K. Yamazaki, and K. Murase, “Si singleelectron device with integrated Si islands,” NTT Review, Vol. 10, No.
6, pp. 114-118 , 1998.
[5] A. Fujiwara and Y. Takahashi, “Si single-electron CCD,” NTT
Review, Vol. 13, No. 6, pp. 56-60, 2001.
[6] K. K. Likharev, “Single-electron devices and their applications,” Proceedings of IEEE, Vol. 87, pp. 606-632, 1999.
[7] Y. Takahashi, Y. Ono, A. Fujiwara, and H. Inokawa, “Silicon SingleElectron Devices,” Journal of Physics: Condensed Matter, Vol. 14,
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[8] Y. Takahashi, M. Nagase, H. Namatsu, K. Kurihara, K. Iwadate, Y.
Nakajima, S. Horiguchi, K. Murase, and M. Tabe, “Fabrication technique for Si single-electron transistor operating at room temperature,”
Electronics Letters, Vol. 31, pp. 136-137, 1995.
[9] Y. Takahashi, H. Namatsu, K. Kurihara, K. Iwadate, M. Nagase, andM. Murase, “Size dependence of the characteristics of Si single-electron transistors on SIMOX substrates,” IEEE Transaction of Electron
Devices, Vol. ED-43, pp. 1213-1217, 1996.
[10] Y. Ono, Y. Takahashi, K. Yamazaki, M. Nagase, H. Namatsu, K.
Kurihara, and K. Murase, “Fabrication method for IC-oriented Si single-electron transistors,” IEEE Transaction of Electron Devices, Vol.
ED-47, pp. 147-153, 2000.
[11] H. I. Liu, D. K. Biegelsen, N. M. Johnson, F. A. Ponce, and R. F. W.
Pease, “Self-limiting oxidation of Si nanowires,” Journal of Vacuum
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[12] K. Shiraishi, M. Nagase, S. Horiguchi, H. Kageshima, M. Uematsu,
Y. Takahashi, and K. Murase, “Designing of silicon effective quan-

NTT Technical Review

Selected Papers

tum dots by using the oxidation-induced strain: a theoretical
approach,” Physica E, Vol. 7, pp. 337-341, 2000.
[13] S. Horiguchi, M. Nagase, K. Shiraishi, H. Kageshima, Y. Takahashi,
and K. Murase, “Mechanism of potential profile formation of silicon
single-electron transistors fabricated using pattern-dependent oxidation,” Japanese Journal of Applied Physics, Vol. 40, pp. L29-L32,
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[14] T. Fujisawa, “Quantum Information Technology based on Single
Electron Dynamics,” NTT Technical Review, Vol. 1, No. 3, pp. 4145, 2003.
[15] N. M. Zimmerman, W. H. Huber, A. Fujiwara, and Y. Takahashi,“Excellent charge offset stability in a Si-based single-electron tunneling transistor,” Applied Physics Letters, Vol. 79, pp. 3188-3190,
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and K. Murase, “Multi-gate single-electron transistors and their application to an exclusive-OR gate,” Applied Physics Letters, Vol. 76, pp.
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[18] Y. Ono, H. Inokawa, and Y. Takahashi, “Binary Adders of Multigate
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[19] H. Inokawa, A. Fujiwara, and Y. Takahashi, “A multipeak negative
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Yasuo Takahashi
Executive Manager of the Device Physics Laboratory and Group Leader of the Silicon Nanodevice Research Group, NTT Basic Research Laboratories.
He received the B.E., M.E., and Ph.D. degrees
in electronics from Tohoku University, Sendai,
Miyagi in 1977, 1979, and 1982, respectively. In
1982, he joined the Musashino Electrical Communication Laboratories, Nippon Telegraph andTelephone Public Corporation (now NTT),
Tokyo, Japan. Since then, he has been engaged inresearch on the physics and chemistry of semiconductor surfaces and interfaces. His current
work includes research on quantum physics ofsilicon nanostructures and their electronic device
applications particularly to silicon single-electron devices. He is a member of the Japan Society of Applied Physics (JSAP), the Institute ofElectrical Engineers (IEE) of Japan, and IEEE.

Yukinori Ono
Senior Research Engineer, NTT Basic
Research Laboratories.
He received the B.E., M.S., and Ph.D. degrees
in physics and applied physics from Waseda University, Tokyo in 1986, 1988, and 1996, respectively. In 1988, he joined NTT Atsugi ElectricalCommunication Laboratories, Kanagawa, Japan.
Since then, he has been engaged in research on
the physics and technologies of SiO2/Si interfaces. From November 1996 to November 1997,
he was a Visiting Scientist at the Massachusetts
Institute of Technology, Cambridge. His current
research interests include the physics and technology of Si nanodevices, including single-electron devices for LSI applications. He is a memberof JSAP, IEE, and IEEE.

Akira Fujiwara
Senior Research Engineer, NTT Basic
Research Laboratories.
He received the B.E., M.E., and Ph.D. degrees
in applied physics from the University of Tokyo,
Tokyo in 1989, 1991, and 1994, respectively. In
1994, he joined NTT LSI Laboratories, Kanagawa, Japan. Since then, he has been engaged inresearch on the physics of silicon nanostructures
and their applications to single-electron devices.
He is a member of JSAP and IEEE.

Hiroshi Inokawa
Senior Research Engineer, Supervisor, NTT
Basic Research Laboratories.
He received the B.E., M.E., and Ph.D. degrees
in electrical engineering from Kyoto University
in 1980, 1982, and 1985, respectively. In 1985,
he joined NTT Atsugi Electrical Communications Laboratories, Kanagawa, Japan. Since then,he has been engaged in R&D of scaled-down
MOS devices, including those with reduced parasitic effects, and fully-depleted bulk MOSFETs.
His current work includes research on silicon
nanodevices, particularly single-electron
devices, and their applications. He is a memberof IEEE, the Institute of Electronics, Information
and Communication Engineers of Japan, andJSAP.

Vol. 2 No. 2 Feb. 200427