ColdFire® V4 Core & SPP C2The ColdFire V4 Core & Standard Product Platform (SPP) C2(CFV4SPPC2) combines the ColdFire V4 Core with industryproven platform peripherals to form a complete highperformance micro-controller subsystem supported by a vast
ecosystem of development tools and runtime software. With the
CFV4SPPC2, you get:
• Performance—over 500 DMIPS at 345 MHz• Reliability—from processor and peripheral IP alreadydeployed in millions of embedded systems worldwide

Standard Peripherals and Interconnect
The CFV4SPPC2 includes the ColdFire V4 Core, plus thefully integrated peripherals shown in Figure 1, implementing
functions commonly needed for embedded systems including
Ethernet, interrupt control, DMA, timers, and various serialinterfaces. An AMBA 2 AHB Crossbar Switch provides thesystem interconnect, supporting simultaneous transfers
between multiple AHB masters and slaves, including externallyconnected AHB masters and slaves.

• Rapid time-to-market—in just a few hours you can be
developing software on your own FPGA implementation of
the CFV4SPPC2

Variations of the CFV4SPPC2 with different combinations of
onboard peripherals are also available. For example, you canomit either one or both of the Fast Ethernet Controllers, or add
one or more instances of the other on-board peripherals.

ColdFire V4 Performance

Peripherals Features

The ColdFire V4 Core is a high-performance implementationof the ColdFire architecture with 1.54 DMIPS/MHz instruction
throughput and high-speed Harvard local buses with tightlycoupled instruction and data caches and local SRAM. The
ColdFire V4 Core also features an MMU for full operating system
support plus pecial arithmetic hardware including a divider andenhanced MAC (EMAC) for faster execution of DSP algorithms,
and an FPU for single and double-precision floating-point
calculations.

On-board peripherals and their features include:

Like all ColdFire architecture processors, the ColdFire V4
Core features a variable-length instruction set for maximum
code density, industry-standard AMBA 2 AHB system bus
interface for rapid system integration, and a wide selection ofdevelopment tools, operating systems, drivers, and libraries
from both commercial and open source providers.

Example SoC Using
CFV4SPPC2.

• FlexBus Controller• Connects up to 6 on-chip or off-chip memories/devices• Independently programmable transfer characteristics foreach device (wait states, address setup/hold)• Enhanced DMA (eDMA) Controller• 16 independently programmable DMA channels• Programmable channel arbitration modes• Support for channel linking and scatter/gather operation• Two Fast Ethernet Controllers, each of which provides• 10/100 Mbps Ethernet support• Half and full-duplex modes• Media Independent Interface (MII) or 7-wire interface toEthernet PHY• Interrupt Controller• 64 programmable interrupt sources, 7 of which areavailable for external interrupts• Unique vector for each interrupt source• Support for low-power mode wake-up• Queued SPI (QSPI) module• Programmable queue for up to 16 SPI transfers• Four chip-select lines for up to 16 devices• Programmable baud rate, before-and-after transfer
delays, clock phase and polarity• I2C interface module• Support for the original Philips I2C bus protocol• Support for baud rates up to 3.4 Mbps
• 3 UARTS• Programmable clock source, data formats, and modes(normal/loopback)• Error detection• Four maskable interrupt conditions• 4 DMA Timer modules• Programmable clock source• Programmable prescaler• Programmable interrupt or DMA request upon timer event• Miscellaneous Control Module (MCM)• Software watchdog timer• Reset status, low-power mode control, and core fault
status registers

Debug Support
The CFV4SPPC2 supports ColdFire Debug Architecture Revision
D+, including:• Background Debug Mode (BDM)• Real-Time Trace (RTT)• Real-Time Debug (RTD)• On-chip, 128-entry trace buffer for low-cost trace over
BDM

Development Support
The ColdFire architecture, including the ColdFire V2 Core, issupported by a vast assortment of development systems/tools
and run-time software including libraries, stacks, drivers, andoperating systems from providers such as NXP, Green Hills
Software, Wind River Systems, and many more. A free versionof the GNU compiler supporting ColdFire V2 targets is alsoavailable from www.gnu.org.
NXP offers development boards, software, and CodeWarrior
Development Tools (including a free version. In addition, there
are several operating systems supporting the ColdFire V2architecture, including uClinux and several RTOS’s, such as theMQX RTOS from Embedded Access, Inc.

Deliverables• Verilog source code• Integration testbench and tests• Documentation• Scripts for simulation and synthesis with commonly-used
EDA tools

Power Saving Features
The CFV4SPPC2 features software-controlled shutdown ofselected clocks to support a variety of chip-level low-power
modes:• Independent shutdown of selected peripheral clocks• Shutdown of the ColdFire V4 Core CPU clock in response
to a ColdFire STOP instruction; the ColdFire V4 Core local
SRAM Controller clock may optionally be kept running in
STOP mode to support access to local SRAM from external
AHB masters

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