論文 / 著書情報
Article / Book Information
題目(和文)
Title(English)

A study of charge sensing techniques in physically defined siliconquantum dots

著者(和文)

溝口来成

Author(English)

Raisei Mizokuchi

出典(和文)

学位:博士（工学）,学位授与機関:東京工業大学,
報告番号:甲第12144号,
授与年月日:2021年12月31日,
学位の種別:課程博士,
審査員:小寺 哲夫,波多野 睦子,宮本 恭幸,若林 整,鈴木 左文,河野 行雄,小田 俊理,小林 正治

Citation(English)

Degree:Doctor (Engineering),
Conferring organization: Tokyo Institute of Technology,
Report number:甲第12144号,
Conferred date:2021/12/31,
Degree Type:Course doctor,
Examiner:,,,,,,,

学位種別(和文)

博士論文

Type(English)

Doctoral Thesis

Powered by T2R2 (Tokyo Institute Research Repository)

A study of charge sensing
techniques in physically definedsilicon quantum dots
14D14045
Raisei Mizokuchi
A dissertation submitted
for the degree of Doctor of Engineering
Supervised by
Associate Professor Tetsuo Kodera

Tokyo Institute of Technology
November 2021

Abstract
Qubits based on various quantum systems have been studied to build large-scale
qubit systems. One promising qubit for larger-scale integration is a spin qubit in asilicon quantum dot, which has a small structure, long coherence time, and compatibility with existing CMOS technology. For the readout of a spin qubit, one measuresspin-dependent charge distribution from the impedance change of the charge sensor via spin-to-charge conversion techniques. For quantum error correction, a fast
(wide-bandwidth) measurement within the coherence time (about 10 µs) is of particular importance. On the other hand, a wide bandwidth will inevitably increase
the noise; hence, it is not easy to achieve high-speed spin detection.
In this thesis, we study charge sensing techniques applied to silicon quantum
dots. At first, we explore the low-temperature transport properties of two types of
triple quantum dot devices: linear and triangular ones. The linear device has threetunnel-coupled quantum dots in line while the triangular device at each vertex ofa triangle. This quantum dot system has the following advantages for large scale
integration: 1) it is fabricated from an industry-standard silicon-on-insulator wafer;and 2) it is physically defined by the shape of the silicon channel layer itself, sothat there is no need to use gate electrodes to define the quantum dot structure. In
experiment, we studied charge transport through the systems by directly measuring
the current and by charge sensing technique using additional QD structures. The
results reveal the formation of each triple quantum dot system without unintentional
QDs as expected. The present work realized a triangular triple quantum dot insilicon, which may pave a way for two-dimensional silicon QD system.
Next, we detect single tunneling events in a physically defined silicon triple
quantum dot system. In measurements, we observe single-shot tunneling events byusing a charge sensor; however, it turned out that the signals are too weak to acquire
tunneling statistics by binary thresholding. To overcome this problem, we apply
numerical treatments, one of which utilizes the maximum log-likelihood ratio test,
and thereby, the step position is precisely indicated. Its superiority is confirmed bycomparing a digital filtering in the simulation. The results demonstrate its potential
for spin readouts from noisy environments.
Finally, we apply radio-frequency reflectometry technique to a physically defined silicon quantum dot system. To readout spins in this system, as in many otherquantum dot systems, the radio-frequency reflectometry will be of a significant importance; however, measuring clear reflectometry signals depending on quantum
states has so far been elusive. This is likely attributed to the top gate structure
overlapping reservoirs, which causes leakage of radio-frequency signals. To avoidIthis common problem of insensitivity, here we employ physically defined quantum
dots without the top gate structure, leading to successful reflectometry as expected.
Moreover, we observe large phase shifts corresponding to conductance peak of quantum dot (∼ 45 degree). To reveal the mechanism, we analyze the data based on an
equivalent circuit consisting of an inductor, a capacitor, a quantum dot impedance,
and their parasitic components which are typically neglected in previous reflectometry studies. By a simulation with the equivalent circuit, the measurement data is
successfully reproduced, which allows us to conclude that reflectometry phase signals can be greatly enhanced by a good impedance matching and an appropriate
frequency detuning.
In conclusion, we have developed elemental technologies for fast charge detection using physically-defined silicon quantum dots: detection of charge states ina triangular triple quantum dot structure, which is the smallest unit of integration; single-shot measurement of single tunneling events of electrons supported bylog-likelihood ratio test; realization of radio-frequency reflectometry in physicallydefined quantum dot for broadband sensing and the analysis using equivalent circuit. We believe that this work paves the way for large-scale QD integration andfast spin readout.

II

Contents
1 Introduction
1
1.1 Quantum computation . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Semiconductor quantum dot qubits . . . . . . . . . . . . . . . . . . . 3
1.3 Three eras for quantum computing . . . . . . . . . . . . . . . . . . . 4
1.4 Silicon quantum dot structures . . . . . . . . . . . . . . . . . . . . . 9
1.5 This thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 Theoretical background12
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2 Single quantum dot . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.1 Charge states in a quantum dot . . . . . . . . . . . . . . . . . 13
2.2.2 Transport through a quantum dot . . . . . . . . . . . . . . . . 15
2.3 Multi-quantum dot structure . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.1 Double quantum dot . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.2 Triple quantum dot . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4 Charge sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.5 RF reflectometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.5.1 LCR circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.5.2 Capacitance for RF-SET . . . . . . . . . . . . . . . . . . . . . 27
2.5.3 RF components . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3 Device fabrication31
3.1 SOI thinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.2 Quantum dot patterning . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.3 Top gate deposition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.4 Ion implantation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.5 Contact pad deposition . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4 Physically defined triple quantum dot systems in silicon on insulator
40
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.2 Device structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.3 Linear triple quantum dot . . . . . . . . . . . . . . . . . . . . . . . . 43
4.4 Triangular triple quantum dot . . . . . . . . . . . . . . . . . . . . . . 44
4.5 Quadruple point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
III

4.6

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

5 Tunneling event detection using single-shot measurements improved by numerical treatments
49
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.2 Measurement setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.3 Charge sensing and the position of the quantum dot . . . . . . . . . . 51
5.4 Single-shot tunneling detection . . . . . . . . . . . . . . . . . . . . . 53
5.5 Digital low-pass filtering . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.6 Change point detection . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.7 Simulation for comparison of the digital signal process techniques . . 59
5.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6 Radio-frequency single electron transistors with a sensitive phase
response63
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.2 Device fabrication and measurement setup . . . . . . . . . . . . . . . 64
6.3 Frequency dependence and electrical circuit analysis . . . . . . . . . . 65
6.4 Fitting with additional parasitic components . . . . . . . . . . . . . . 68
6.5 Estimation of parasitic components of the inductor at liquid heliumtemperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.6 Back gate voltage sweeping . . . . . . . . . . . . . . . . . . . . . . . . 71
6.7 Side gate voltage sweeping . . . . . . . . . . . . . . . . . . . . . . . . 73
6.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7 Conclusions77
7.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
7.2 Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
References

83

Acknowledgements

100

Publications

102

IV

Chapter 1
Introduction
1.1

Quantum computation

General-purpose quantum computers are considered to enable solving problems
which cannot be solved by classical computers on a practical time scale.[1] They
are formed by minimum units called quantum bits or qubits. The qubits have
two-level quantum states, and in analogy with bits in ordinary computers, the twolevels of each qubit are encoded to "0" or "1"; in addition, superposition of the twodigits is allowed, |Ψ⟩ = α|0⟩ + β|1⟩, where α and β are complex constants, and|0⟩ and |1⟩ are the quantum states. For a well-known quantum error correction
code, two-dimensional arrays of several tens of million physical qubits are required
to solve practical problems.[2] So far, various quantum systems have been developed
as qubits: photons,[3] superconducting circuits,[4] spins in semiconductor quantum
dots,[5] etc.
Following recent progresses in the quantum information field, major information
technology companies like Google, IBM, and Intel have started to join this field. In
2019, Google demonstrated the quantum supremacy, the supremacy over classicalcomputers, using 53 superconducting qubits.[6] In the paper, they claim that aproblem which takes ten thousand years with supercomputer was solved in two

1

CHAPTER 1. INTRODUCTION
hundred seconds by quantum computer. The calculation by the quantum computer
also demonstrated that the energy consumption is lower by a factor of 105 thanfor the same calculation by a supercomputer, due to the shorter calculation timeand smaller power consumption. This result lets us envision the reality of practicalquantum computation.
One of the reasons for the recent success of superconducting qubits is its structural similarity to classical circuits that facilitates the qubit design; the structure
is an LC resonator that consists of a capacitor and a non-linear inductor using
superconductor-insulator-superconductor junction (Josephson junction). When focusing on the most popular type of superconducting qubit called transmon, theenergy contained in capacitance is designed to be much smaller than that of theJosephson junction, making the qubit insensitive to charge noise. This improves
qubit characteristics and enables multiple qubit integrations. However, the footprint of one qubit (∼ 1 mm2 ) is relatively larger than of other qubit systems. In
addition, the qubit operation temperature is typically in tens of millikelvins to keep
noise small. The combination of these two obstacles will limit further qubit integrations because of the restriction of cryogenic space with respect to size and coolingpower. Hence, smaller qubits possibly working at higher temperature where coolingpower is higher are more preferable.
Trapped ion qubits are one of candidates for quantum computation. This qubit
utilizes charged ions trapped in a vacuum by oscillating electromagnetic field, having
long coherence time due to almost no external disturbances. In addition, this qubit
can be realized even at room temperature, and cryogenic operation (at ∼ 4 K)
improves the characteristics. Integration of several tens of trapped ion qubits havebeen reported recently.[7] However, large-scale qubit integration with this system
may be challenging because of relatively large footprint per one qubit (∼ 1 µm2 )and because standard trapping techniques limits qubit arrays to one-dimensional
ones. Therefore, other quantum systems suitable for two-dimensional integration
2

CHAPTER 1. INTRODUCTION
are desirable.

1.2

Semiconductor quantum dot qubits

Aiming towards the million-qubit systems, spin qubits based on semiconductor
quantum dots (QDs) are promising because of the physical smallness and electricaltunability.[8, 9] A QD is a nano-size semiconductor block (10 ∼ 100 nm) and canconfine electrons or holes whose spins can be regarded as qubits.
The QD structure is superior to other spin qubits like dopant qubits, which utilizes sharp, identical quantum confinements of single dopants (phosphorus donor,
typically) in silicon. Even though such dopant qubits show the significantly long coherence times, the sharp confinement prevents controlling couplings between dopant
qubits, leading to difficulty in two-qubit gates.
As the semiconductor material for QDs, GaAs/AlGaAs heterostructures had
been intensively studied in 2000s thanks to its low-disorder quantum well and low
electron effective mass leading to clear quantum effects. However, it turned out that
nuclear spins significantly degrade the coherence time of spin qubit, and hence, in2010s, silicon, whose dominant isotopes are spinless, began to be preferred instead of
GaAs, all of whose isotopes have nuclear spins. On the other hand, higher effective
mass in silicon decreases energy level spacings in QD than in GaAs, so that smaller
silicon QDs are required to compensate it. By overcoming these challenges, siliconQD spin qubits have been realized, and the long coherence times have been observed
as expected,[10] further boosted by isotopically purification.[11, 12]
Recently, integration of silicon QDs has been investigated. For quantum error correction, two-dimensional qubit integration will be important. A well-known
error correction scheme [2] allows high error probability (around 1%) by considering nearest-neighbor couplings of two-dimensional qubit array. Taking into accountthe present state-of-the-art fidelity ([fidelity] = 1 – [error probability], roughly) of
spin qubit operations, thousands of (physical) qubits are required to encode a (log3CHAPTER 1. INTRODUCTION
ical) qubit. Recently, integrations of nine QDs and three qubits in linear arrays
were reported, respectively.[13, 14] In addition, CEA-LETI, a research institute forelectronics and information technologies in France, fabricated a two-by-four QD
array with standard CMOS process.[15] For large-scale integration, such matured,present semiconductor technologies should play important roles. In these days, Inteland IBM also has fabricated their own QD qubit systems with their semiconductor
technologies.[16, 17] However, these structures are dedicated to one-dimensional QD
arrays, so that the development of expandable two-dimensional qubit array has still
been anticipated.
Turning to the readout of spin qubits, charge sensing plays a crucial role. Readout of qubit is necessary for quantum computation, but, in addition to fragility of
qubit, spin readout by a sensor is not easy, because spins do not couple with electrical environment directly. In the literature, spin-to-charge conversion techniques
were developed,[18, 19] via which “spin” states are read out by “charge” sensing.
The charge sensing is desired to be performed within spin operation time (e.g.,∼ 1 µs for electron spins) not to limit the quantum computation speed. To speed
up qubit readouts, software and hardware techniques have been developed. Froma software aspect, digital signal processing techniques can support readout, e.g., byprecise step signal detection from noisy measurement results.[20] From a hardware
aspect, radio-frequency (RF) reflectometry is commonly used to avoid low-frequency
noise.[21] The technique is that RF signal is applied to device, and the reflected signal, related to device impedance, is measured. Here, RF is typically on the orderof 100 MHz, so that the technique is immune from low-frequency noise such as 1/f
noise.

1.3

Three eras for quantum computing

Aiming towards fault-tolerant quantum computing, there are three eras: 1.
small-scale integration of qubits, 2. Noisy Intermediate-Scale Quantum devices
4

CHAPTER 1. INTRODUCTION(NISQ), and 3. large-scale fault-tolerant quantum systems. Here, we briefly discusseach of them with possible milestones for silicon-QD spin qubits.

1. Small-scale integration of qubits (with ∼ 10 qubits)• Expandable qubit structure• Qubit initialization• Long coherence time
• Single-qubit gate
• Two-qubit gate
• Qubit readout
Era when researchers have been developing different qubits and seeking their futurearchitecture. As of now, research for spin qubits is here. The above milestones aredescribed by DiVicenzo’s criteria.[22] State-of-the-art techniques realized a linear
three spin qubit array in silicon, with agreement on the criteria.[14] Unlike thisbottom-up approach, there are attempts based on a top-down one. In this approach,QDs are integrated with cryogenic electronics in a large-scale first, and then, eachsystem component will be elaborated. [23]2. Noisy Intermediate-Scale Quantum devices (NISQ) (with 50 ∼ 100 qubits):• Intermediate-scale integration with a simple structure• Moderately high fidelity• High yield ratio of working qubit• Cryogenic electronics• Suppression of crosstalk between qubits
Era for quantum computing without error corrections; therefore, cumulative errors(mainly) limit the size of quantum calculations. Nevertheless, it is considered to be5CHAPTER 1. INTRODUCTION
meaningful for some practical calculations like quantum simulations.[24] For integration, the number of gate electrodes should be at minimum. In addition, threedimensional gate electrodes and multilayer fan-out will be necessary. Spin readout
with gate electrodes will further simplify the structure.[25] This gate-based readout
utilizes RF reflectometry to read out small capacitance changes corresponding tospin states, so that signal multiplexing techniques enable simultaneous multi-qubit
readout. A fast gate-based readout with a superconducting resonator (∼ µs [26])was reported, which is comparable to qubit operation sequences (< coherence time,∼ 10 µs). In addition, gate-based charge sensing within 50 ns has recently been performed by circuit improvement and using devices with strong gate-QD coupling,[27]so that hopefully it will not become the burden for NISQ calculation in future.
Yield ratio should be high enough, and its improvement may be the most challenging part in this era. This is because single atoms in tunnel barriers and/or asingle atomic layer of silicon channel strongly affect the qubit characteristics. Simply thinking, the probability of > 99% that a qubit works will be required to obtaina working one from ten fabricated NISQ chips each including 100 qubits. It is notclear whether this value is feasible or not as of now, but industrial MOSFET fabrication techniques will be applicable and improve the yield ratio, as shown by thefact that ten billion of MOSFETs work in a latest CPU.
To realize dense spin qubit arrays, cryogenic electronics is important. For example, if each qubit has an LC resonator for RF reflectometry, the footprint of the LC
resonators will be problematic. Cryogenic architectures in analogy with dynamic
random access memory have been proposed, which can facilitate this problem.[28]The architectures enable time-domain multiplexing of RF signals and thereby reduces the number of LC resonators. The architectures can decrease the number ofwires for potential controlling as well, leading to reduction of thermal budget froma bunch of cables (Fig. 1.1).[29, 30] Electronics like microwave generator and arbitrary waveform generator are also preferable to be located at cryogenic temperature
6

CHAPTER 1. INTRODUCTION
stages to reduce the thermal budget. The central challenge of cryo-electronics is thepower dissipation. At 20 mK in a dilution refrigerator, cooling power of only 10 µW
is available. One way to avoid this problem is placing the control chip at a higher
temperature stage with a larger cooling power. Intel has been developing such acontrol chip, code-named “Horse Ridge”.[31] This chip can output IQ-modulated
microwave signals for spin qubit manipulations at cryogenic temperature (at 3 K,
with 384 mW power consumption as described in Ref. 31). This signal generator
works well so that the qubit performance keeps so high as with a room-temperature
controller (99.7% fidelity). Another approach is integrating cryogenic controllers
on the same chip as of qubits, further reducing the number of wires. This has a
trade-off with power consumption. As mentioned above, cooling power of a mKstage is limited to µW, so that high temperature operation of qubit is needed. In
the literature, it has demonstrated that spin qubits in silicon QDs works at 1 K,
[32, 33] where the cooling power is several tens of milliwatt.

Figure 1.1: A two-dimensional qubit array with an architecture based on dynamic
random access memory to control the potential of the qubits with a reduced numberof wires. The number of wires are proportional to the square root of the number of
qubits. This figure is adopted from Ref. 30.

QD arrays may suffer from crosstalk more strongly than other qubit systems
7

CHAPTER 1. INTRODUCTION
due to its high density of gate electrodes. Here, the crosstalk has two components;
unintended qubit rotation by intended qubit operations via capacitive cross couplings and signal leakage from one line to others through capacitive couplings. The
former can be suppressed by setting the operation resonance frequencies of qubitsaway from each others. Recently, results with 0.02% crosstalk has been reported.[34]The latter crosstalk component will also be suppressed by shielding of each highfrequency lines although it may take a lot of effort to develop device fabrication
techniques.

3. Large-scale fault-tolerant quantum systems (> 10 million qubits):• Higher fidelity than error-correction threshold• Quantum non-demolition measurement• Long-range interaction• ...
Era for practical quantum computing with quantum error correction. In error correction schemes, a (logical) qubit state is spread onto a state of multiple (physical)
qubits. Such a redundancy makes a qubit robust against noises by checking errors
in each physical qubit. For the correction, the fidelity of each physical qubit should
be high enough, and it is theoretically demonstrated that 99% fidelity of several
thousand of qubits in a two-dimensional array is required for error correction.[2]Even though 99.9% fidelity has been realized using spin qubits in silicon,[11] it isapparently a formidable task to expand it on a large scale.
Actually, there will still be a lot of milestones to realize fault-tolerant quantum
computation. For example, non-demolition measurement plays an important roleto feedback qubit error information,[35, 36] and long-range interaction can bridge
different qubit arrays and make spaces for on-chip cryo-electronics.[29, 37, 38] Such

8

CHAPTER 1. INTRODUCTION
underlying techniques have been developed one by one in these days, so that merging
them into a large quantum system will be one of main tasks in this era.

1.4

Silicon quantum dot structures

There are several structures to form silicon QD structures. We introduce threeof them below: Gate-defined, Si nanowire, and physically defined QDs.
The gate-defined QDs are the conventional structure following standard GaAs
QDs. This structure has fine gates on the surface of the Si/SiGe heterostructure
or silicon substrate typically covered with an insulator layer. Small gates above a
two-dimensional electron gas in silicon quantum well enable precise local control ofthe potential around the electrons, leading to almost ideal QD structures. In fact,
so far, a lot of essential ingredients for general-purpose quantum computers havebeen established in this type of devices: high-fidelity single spin qubit,[11, 12] twoqubit operation,[39–42] spin-photon coupling for distant qubit coupling,[38] qubit
operation at high temperature,[33] and quantum non-demolition measurement which
is demanded for quantum error correction.[35, 36] On the other hand, the numberof gates tends to be larger than other QD structures; large-scale integration withthis structure is challenging.[43]As another type of silicon QDs, Si nanowire QDs are well known. This structure has basically the same structure as MOSFETs; it consists of a drain and asource of a Si nanowire and a gate per one QD. Thanks to the thin effective oxide
thickness of gate oxide, the gate-QD coupling is very strong, enabling fast gatebased sensing.[25] The gate-based sensing utilizes gate electrodes which can tune
the potential of QDs for qubit readout and therefore is the most promising way toreadout densely integrated QDs. In addition, the Si nanowire structure is completely
compatible to classical circuits, which is advantageous for realization of on-chip cryogenic controller.[44] In these points, the structure is advantageous but, problematicin the respect of two-qubit gate operations where an additional gate between two
9CHAPTER 1. INTRODUCTION
QDs is practically required to tune the QD-QD coupling. In addition, the structure
based on a Si nanowire is one-dimensional-like, and therefore, there are difficulty
for two-dimensional qubit integration.
As the third type of Si QDs, we introduce here physically defined QD (PD-QD)
structure. A PD-QD is fabricated from an industry-standard silicon-on-insulator
wafer and physically defined by electron beam lithography and dry etching processes, therefore having a good compatibility to CMOS techniques as well as Si
nanowire QDs. This is advantageous for the integration because of no need to define
quantum dot structure by gates and affording flexibility in QD arrangement.[45–51]
This physical quantum confinement forms sharp, fine potential wells, which enlarges
feature energy and will be thus suitable for high temperature operation. The realization of spin qubits with PD-QDs are in progress.
In this thesis, we develop charge sensing techniques by using PD-QDs. As mentioned above, two-dimensional integration of silicon QDs has been proposed andshown having an importance for error correction, but had not yet succeeded experimentally. This is possibly because of weak tunnel couplings due to low effective
mass in silicon. In the present work, we first fabricate a unit of two-dimensional
array, triangular triple QDs (TTQDs), by overcoming the difficulty with strong,
sharp quantum confinements of physically defined QD structures. After confirming
formation of TTQD, we developed readout techniques from the aspects of softwareand hardware using the QDs. The techniques are applicable to other QD systems,
and we anticipate that it paves the way to improve readout in speed and accuracy.

1.5This thesis

This thesis consists of seven chapters.

Next to this chapter (Chapter 1"Introduction"), we shall describe a theory for the charge transport through quantum dots and charge configuration (Chapter 2 "Theoretical background"). Here,the basics of an important charge sensing technique called RF reflectometry is ex10

CHAPTER 1. INTRODUCTION
plained as well. In Chapter 3 "Device fabrication," processes for fabrication of the
PD-QDs are explained one by one. In the three following chapters, measurement
results for charge sensing of the PD-QDs are presented. Chapter 4 "Physicallydefined triple quantum dot systems in silicon on insulator" reports realization of multiple-QD systems with three QDs. It shows the possibility of dense
two-dimensional integration of spin qubits. Chapter 5 "Tunneling event detection using single-shot measurements improved by numerical treatments"
focuses on detection of single-shot tunneling events, but the signals are weak andhidden in noise. To overcome this, log-likelihood ratio test is applied, and the capability of precise signal detection is demonstrated. Chapter 6 "Radio-frequency
single electron transistors with a sensitive phase response" is devoted to
RF reflectometry in a PD-QD. In the results, huge signals are observed, which are
attributed to good impedance matching and a small frequency detuning from theresonance frequency. Finally, research perspectives towards qubit integration andfast qubit readout are given in the last chapter (Chapter 7 "Conclusions").

11

Chapter 2Theoretical backgroundIn this chapter, we explain characteristics of single, double, and triple
quantum dot structures. In addition, the basic idea of single-shot spin
readout by charge sensing is also mentioned. Finally, radio-frequency
reflectometry, which plays an important role for fast charge sensing, isdescribed from the point of view of electrical circuit theory.

2.1

Introduction

A quantum dot (QD) is a sub-µm-order semiconductor island charged with electrons or holes. Due to its three-dimensional quantum confinement, the structure iszero-dimensional, so that the eigenenergy is completely discretized. In the structure,
charges are locally concentrated, and therefore, Coulomb interaction dominates theenergy scale, and then the number of charges contained in a QD is restricted to be
integer. When two and three QDs are connected, the structures are called double
and triple QDs (DQD and TQD), respectively. In this chapter, first, we theoreticallycharacterize these basic QD structures. Next, the basic ideas for charge sensing andradio frequency (RF) reflectometry are explained as well.

12CHAPTER 2. THEORETICAL BACKGROUND

2.2

Single quantum dot

2.2.1

Charge states in a quantum dot

Spectroscopy of QD system has an importance to acquire the energy levels.
Tunnel-coupled reservoirs facilitate the spectroscopy because the spectra are probed
by current through the QD (Fig. 2.1(a)). Charges can tunnel one by one fromone reservoir to the other through the discrete energy levels in QD, resulting incurrent peaks corresponding to the levels. From the transport behavior, QD system
is sometimes referred to as single electron/hole transistor (SET/SHT). At first,
we explain the discrete energy levels in a single QD (SQD) from a semi-classicaldescription. Here, for simplicity, we shall consider a constant interaction model
where Coulomb repulsion is independent of the number of electrons in the QD.
Then, the total energy of electrons in the QD , U (N ), is

U (N ) =

Gate

(a)

SourceN(eN − Cd Vd − Cs Vs − Cg Vg )2 X
εj ,
+
2C
j=1

𝐶𝑠
𝑅s

𝐶g
𝐶𝑑

(b)

Γ+L

Drain

𝜇L

Γ−R
𝜇(1)
Γ−L

(2.1)

𝜇R

Γ+R 𝑒𝑉𝑅dFigure 2.1: (a) An equivalent circuit for a SQD. SQD and gate are capacitively
coupled (Cg ), while drain and source reservoirs are tunnel-coupled to the SQD. A
tunnel coupling is described parallel RC circuit (Ra and Ca where a = d, or s). (b)A toy model for master equation to estimate SQD conductance. Charges tunnel on
and off the SQD with tunneling rates Γ. Here, only a single energy level in the SQD
is assumed.
13

CHAPTER 2. THEORETICAL BACKGROUND
where e is a single electron charge, N the number of electrons in the QD, C the total
capacitance of the QD, Ci the capacitance of electrode i, Vi the voltage applied toelectrode i, and i = d, s, g corresponds to drain, source, and gate. εj is j-th
eigenenergy of a single-particle Schrödinger equation for the QD confinement. From
Eq. 2.1, the electrochemical potential required for adding N-th electron, µ(N ), is
obtained:1µ(N ) = U (N ) − U (N − 1) = N −EC − αd Vd − αs Vs − αg Vg + εN
2




(2.2)

where EC = e2 /C and αi = e(Ci /C). EC and α are important parameters to characterize QD, and thus named as charging energy and conversion factor, respectively.
From Eq. 2.2, the energy spacing between two sequential electrochemical potentials,
referred to as addition energy Eadd (N ), is

Eadd (N ) = µ(N + 1) − µ(N ) = EC + (εN +1 − εN ).

(2.3)

Therefore, it turns out that the energy levels are mainly determined by EC .
In a simple case, C is described by summation of gate, drain, and source capacitances; in reality, self-capacitance Cself should also affects. A self-capacitanceis a capacitance of the object itself, in other words, capacitance between the object
and the infinitely away reference point. The value is a function of the radius of theobject. For a two-dimensional disk, which corresponds to our silicon QDs in thisthesis, Cself = 4ϵr ϵ0 d, where ϵ0 is the vacuum permittivity, ϵr the relative permittivity of the material, d the diameter of the disk.[52] When Cself is dominant in C, thediameters of QDs can be estimated from measured EC by the rough approximationthat C ∼ Cself .

14

CHAPTER 2. THEORETICAL BACKGROUND

2.2.2

Transport through a quantum dot

Next, we shall derive steady current through a SQD from a classical master equations for a toy model where a single electrochemical potential in QD and two reservoirs are tunnel-coupled with energy-dependent tunneling rates (Fig. 2.1(b)).[53, 54]
We therefore assume two states in QD, with and without a single electron, and hence
we define two possibilities whether one finds the electron or not, P1 and P0 , respectively. Considering the tunneling rates for adding an electron and removing anelectron, Γ+ and Γ− , respectively, one obtains a classical master equation as below:

P0 + P1 = 1,

(2.4)

dP1
dP0
= −Γ+ P0 + Γ− P1 = −
.
dt
dt

(2.5)

where Γσ = ΓσL + ΓσR , σ = + or −, and ΓσL and ΓσR are tunneling rate for left andright barriers, respectively. Current through the QD, I, is equal to currents throughleft and right barriers (IL and IR ) when the polarity is ignored, and then, in thelimit that dP0 /dt = 0,−
I = IL = −IR = e(Γ+L P0 − ΓL P1 )
−
− +
e(Γ+
L ΓR − ΓL ΓR )Γ− Γ+2e γL γR=(fL (ε) − fR (ε)),ℏ γL + γR

=

(2.6)
(2.7)
(2.8)

−
where e is a single electron charge, Γ+
α = 2γα /ℏ ∗ fα (ε), Γα = 2γα /ℏ ∗ (1 − fα (ε)),

fα (ε) = 1/(1 + exp((ε − µα )/kB T )) is a Fermi distribution function, ℏ is the Dirac
constant, ε is the energy of the QD state, µα is the Fermi level in the reservoir, T is
the temperature of charges and α = L or R. To obtain Eq. 2.7, we have substituted
Eq. 2.4 and have assumed a steady current where Eq. 2.5 is equal to zero. Here, γ
includes a tunnel coupling between the QD and a reservoir and density of states in15

CHAPTER 2. THEORETICAL BACKGROUND
the reservoir.[53] Eq. 2.8 for multiple charge states is plotted as a function of ε andas a function of bias voltage V = µR − µL , where peaks and a current blockade area
appear, respectively (Fig. 2.2(a) and (b)). The peaks are called Coulomb peaks,
while the current blockade is called Coulomb blockade. When multiple energy
levels are taken into account, and the QD current is plotted as a function of V
and gate voltage Vg , the blockade areas seems diamond-like in V -Vg plane, which
are referred to as Coulomob diamonds (Fig. 2.2(c)). One can obtain the additionenergy and conversion factor of a SQD from this Coulomb diamond measurement.
At the vertexes of the diamond for Vds ̸= 0 V, the bias voltage aligns with energy
spacing between QD electrochemical potentials with charge numbers different by
one. Thus, the height of the diamond from zero bias voltage is equal to additionenergy: Eadd = e∆Vds . The diagonal length of the diamond at Vds = 0 V, ∆Vg ,also coincides the addition energy. Therefore, α = e∆Vds /∆Vg . We note that ∆Vg
directly relates with the gate capacitance Cg due to the single electron behavior;
Cg ∼ e/∆Vg
We now turn back to Eq. 2.8, and then differential conductance G can be derived
from it:

2e2
dI
=
G=
dV
ℏ

1
1
+
γL γR

!−1

1
,
4kB T cosh ((ε − eV )/2kB T )
2

(2.9)

where we have utilized ∂f /∂µ = −1/{4kB T cosh2 ((ε − µ)/2kB T )}. We have also setµL = 0 without losing the generality, and then, bias voltage V = µR /e. Figure 2.3
shows a plot of Eq. 2.9 as a function of ε, where a peak appears as well as QD current.
Actually, Eq. 2.9 can also be obtained from quantum mechanics as a limit of kB T ≫Γ = ΓR + ΓL . Note that the width of the peak in energy is determined by thermalenergy, and thereby, the temperature of the charges can be acquired. Practically,
zero bias conductance is used for that, because other levels can contribute to the
conductance when a bias voltage is applied. In this limitation, as seen in Eq. 2.9,
16

CHAPTER 2. THEORETICAL BACKGROUND

0

Current(b)(c)

Gate voltage

00Bias voltage

Current

Gate voltage

Current

(a)

−

0

+

Δ𝑉ds
Δ𝑉g

0
Bias voltage

Figure 2.2: (a) Simulated current through a SQD as a function of gate voltage.
Here, multiple charge states are taken into account. (b) Simulated current througha SQD as a function of bias voltage. Current is suppressed around zero bias voltage.
(c) Simulated current through a SQD as a function of gate voltage and bias voltage.
Current is suppressed in characteristic diamond-shaped areas. Here, ∆Vg is the
diagonal length of the diamond at Vds = 0 V in Vg . ∆Vds indicates the height of the
diamond from zero bias voltage.
QD resistance 1/G can be regarded as two series resistors, meaning that each tunnel
barrier has a resistance (sequential tunneling). Meanwhile, in the opposite limitationthat kB T ≪ Γ,G=

4ΓL ΓR2e2,h (ε − µ)2 + Γ2

(2.10)

where V is set to be zero. In this case, the width of the Lorentzian peak is determinedby Γ (resonant tunneling).
In reality, finite conductance can exist even in Coulomb blockade conditions,which can be caused by co-tunneling (Fig. 2.4).[55] This tunneling is named after
the fact that high-order tunneling events with multiple charges contribute to thetunneling. For the explanation, we shall consider two-electron processes, the sim17

Conductance

CHAPTER 2. THEORETICAL BACKGROUND

𝑉=0

FWHM
∼ 3.5𝑘B 𝑇𝑒𝜀Figure 2.3: A simulated conductance peak of a SQD at V = 0 V. Its full width at
half maximum (FWHM) corresponds to the electron temperature.
plest case, which is the leading-order term and describe the co-tunneling in a QD
with two tunnel-coupled reservoirs (Fig. 2.4). Here, we assume three energies ofstates for zero to two charges: E0 = 0, E1 = ε0 , and E2 = 2ε0 + U , where ε is theenergy of the (first) orbital and U is the charging energy. Therefore, two energies foradding and removing an electron are calculated: E+ = (E2 − E1 ) − µ = ε0 + U − µand E− = µ − (E1 − E0 ) = µ − ε0 , where µ is the Fermi energy of the reservoirs. If
an charge tunnels out of the QD, the system energy increases by E− (Fig. 2.4(a)). In
classical physics, this transition is completely restricted; however, quantum physics
allow it for a short time, ∆t ∼ ℏ/E− based on uncertainty principle. During ∆t,another charge tunnels into QD, and thereby, the violation of the law of conservationof energy is compensated. This happens also for E+ in analogy (Fig. 2.4(b)).

2.3

Multi-quantum dot structure

2.3.1

Double quantum dot

Next, we explain DQD characteristics (Fig. 2.5(a)). One can also obtain theelectrochemical potential for DQDs in analogy with single QD:

18

CHAPTER 2. THEORETICAL BACKGROUND

(a)

𝜇(2)
𝜇(1)

(b)

E−

𝜇0

𝜇(2)

E+
𝜇(1)

𝜇0

Figure 2.4: Co-tunneling through a QD. Here, tunneling events occur disregarding
energy conservation, which is allowed by the uncertainty principle. (a) Co-tunneling
via lower energy level. (b) Co-tunneling via higher energy level.

µ1 (N1 , N2 ) =U (N1 , N2 ) − U (N1 − 1, N2 )1=(N1 − )EC1 + N2 ECm
2
EC1 X
ECm X
−
C1j Vj +C2j Vj ,
|e| j
|e| j

(2.11)

2
where ECi = e2 /{Ci (1 − Cm
/C1 C2 )} is the charging energy of QDi, ECm =2e2 /{Cm (C1 C2 /Cm− 1)} is the coupling energy, j is an index for electrodes (j =g1, g2, s, d), and single-particle levels are here ignored. µ2 (N1 , N2 ) can be obtainedin analogy with µ1 (N1 , N2 ). One can map out the DQD stability diagram by sweeping voltages of two gates, g1 and g2 (Fig. 2.5(b)). As seen in Fig. 2.5(b), each
Coulomb blockade area is bordered by three different slopes, forming a honeycomb
structure. µ1 (µ2 ) corresponds to a line with the most nearly vertical (horizontal)
negative slope, reflecting the different gate-QD couplings. Interdot charge transitions occur across the lines with the positive slope. Focusing on a single honeycomb19CHAPTER 2. THEORETICAL BACKGROUND
structure, two lines with the same negative slope corresponds to electrochemical
potentials with the charge numbers different by one. One can therefore obtain gate
QDi
QDi
QDi
capacitances between gate k and QD i, Cgk
in an approximation; Cgk∼ e/∆Vgk(Fig. 2.5(b)).
Current through DQD is suppressed except for the conditions that energy levels for each QD are in bias window and ordered not to prevent current flowing(Fig. 2.5(c)). Without bias voltage, current can flow at points where energy levels ofboth QDs are aligned with the Fermi levels of the reservoirs. Figures. 2.5(d) and (e)shows two examples of current-flow points for four energy levels, µ1 (1, 0), µ1 (1, 0),µ2 (0, 1), and µ2 (1, 1) (Fig. 2.5(c)). At the black dot in Fig. 2.5(c), single electrons
can tunnel through the DQD via a cycle of charge configurations: (0,0) → (1,0)→ (0,1) → (0,0) (Fig. 2.5(d)). On the other hand, at the white dot in Fig. 2.5(c),another cycle transports charges: (1,1) → (1,0) → (0,1) → (1,1) (Fig. 2.5(e)). Eachcycle has three charge configurations, so that the points are called (charge) triple
points. It is known that a finite bias voltage expands the points into triangles,
so-called bias triangles (Fig. 2.5(c)). The size of the triangle is proportional to theapplied bias voltage, and thereby, one can acquire the conversion factor between
gate k and QD i from measurements with two different bias voltages in an approxQDi
QDi
QDi
is
, where δVds is different in bias voltages and δVgk
imation; αgk∼ eδVds /δVgk

shift of a charge transition line in Vgk .

2.3.2

Triple quantum dot

It is also possible to calculate energy levels for TQDs in analogy with DQD(Fig. 2.6(a)). Here, we skip the formulation because of its complexity, but instead,mention the general features. As predicted from DQD characteristics, TQD shows
three different negative slopes each corresponding to charge transitions in a QD
of TQD as a function of two gate voltages (Fig. 2.6(b)). This behavior can beunderstood by three-dimensional charge stability diagram in a space spanned by
20

CHAPTER 2. THEORETICAL BACKGROUND

(a)

Gate1

(b) 𝑉𝑔2

Gate2

𝑄𝐷2

Δ𝑉g2

𝑄𝐷1

Δ𝑉g2

Source

QD1

QD2

Drain

𝑚
Δ𝑉g2

𝑉𝑔1

(d)

(c)
𝜇1 (1,1) = 0

𝑉𝑔2

𝜇𝑠

𝜇2 0,1= −𝑒(𝑉𝑑𝑠 + 𝛿𝑉𝑑𝑠 )
𝑄𝐷1

𝛿𝑉g2

𝜇2 0,1= −𝑒𝑉𝑑𝑠

(e)

∝ 𝑉ds

𝜇2 (0,1) = 0

Electron transport
𝜇1 (1,0)𝜇2 (0,1)𝜇𝑑

𝜇1 (1,1)

𝜇2 (1,1)𝜇𝑑

𝜇1 (1,0)𝜇2 (0,1)

𝜇1 (1,1)

𝜇2 (1,1)

𝜇1 (1,0)𝜇2 (0,1)

𝜇1 (1,1)

𝜇2 (1,1)

𝜇1 (1,0)𝜇2 (0,1)Hole transport
𝜇𝑠

𝜇𝑠

𝜇𝑑

𝜇2 (1,1) = 0𝜇𝑠𝜇1 (1,0) = 0

𝜇𝑑

𝑉𝑔1

Figure 2.5: (a) Schematic of DQD. Each of gate1, gate2, drain, and source is capacitively coupled to QD1 and QD2, respectively. (b) Schematic of charge stability
diagram for DQD as a function of two gate voltages. Two negative slopes appear
corresponding to charge transitions in each QD. Coulomb blockade areas are bordered like honeycomb structures by charge transition lines. The distance between
adjacent charge transition lines can be used to calculate characteristic energies.
∆Vg2m corresponds to shift in energy of QD1 by a charge transition in QD2. ∆Vg2QD1(∆Vg2QD2 ) corresponds to the distance between QD1 (QD2) charge transitions with
one charge difference without charge transition in QD2 (QD1). (c) Schematic ofcurrent through DQD as a function of two gate voltages. The figure focuses on acharge degeneracy point in (b). Solid lines corresponds to the charge transition linesin (b). Without bias voltage, current flows at black and white points, while, with afinite bias voltage, current-flowing area forms triangles, called triple point. Because
the size of the triangles proportional to bias voltage, one can know the conversion
factors from the triple points with different bias voltages. (d,e) Charge transport
at black and white points in (c), respectively. At the black point, electrons passthrough the tunnel barriers one by one ((d)); on the other hand, at white point,holes transport ((e)).
21

CHAPTER 2. THEORETICAL BACKGROUND
three gate voltages, which is composed by three types of charge transition planes
corresponding to the charge transitions in TQD (Fig. 2.6(c)). Current through TQD
is restricted as well as DQD. For TQD, the current-flow point is referred to as
quadruple point where four charge states contributes to the current: e.g., (0,0,0) →(1,0,0) → (0,1,0) → (0,0,1) → (0,0,0). When all the three QDs have tunnel-coupledreservoirs, the restriction is mitigated, and then, current through triple points flows.
[56]

(a)
(c)

(b)

Figure 2.6: (a)Equivalent circuit diagram for linear TQD. (b) Numerically calculated stability diagram of the TQD device in (a). (c) Simulated three-dimensionalcharging diagram of a TQD. The figures are adapted from Ref. 57.

2.4

Charge sensing

As shown in the previous section, the conductance of a QD has sharp peaks as afunction of electrical potential, meaning that it is sensitive to electrical environment.
This is useful to detect charge transitions in other QDs. In measurement, a chargetransition shifts the conductance of charge sensor (CS) via the capacitive coupling,
resulting in a kink (Fig. 2.7(a)). In other words, the positions of kinks indicate the22CHAPTER 2. THEORETICAL BACKGROUND

(a)

(c)

Conductance

(b)

(d)
𝜀

Figure 2.7: (a) Schematic of charge sensing. Compared with Fig. 2.3, a charge
sensing kink appears,corresponding to a charge transition in a target QD. (b-d) A
scheme for spin readout. See main text for detail. Figures (b-d) are adapted from
Ref. 18.
positions of charge transitions in target QDs. When one takes a map as a functionof two gate voltages, kinks appear as lines in the map. This is one way to confirm
whether a kink relates to a charge transition or noise.
By using charge sensing, spin qubit states can be acquired via spin-to-charge conversion techniques.[19, 18] The techniques enables spin-dependent tunneling events
where QD charge configurations changes depending on spin states. We shall briefly
explain a single-shot spin readout sequence for a system consisting of a SQD withtunnel-coupled reservoir and a CS (Figs. 2.7(b), (c), and (d)). Here, "single-shot"means measurement of a single event (for example, a single tunneling of a single
electron) unlike measurements of QD current which is an ensemble of many tunneling events. The single-shot measurement is required to acquire spin states because
the spin state can be stochastically obtained due to quantum superposition of theparallel spin states. One of the easiest ways to demonstrate the spin readout is re23

CHAPTER 2. THEORETICAL BACKGROUND
peatedly applying a three-step sequence: initialization, (random spin) preparation,and spin readout. This can be performed by applying corresponding three-steppulses by, e.g., arbitrary waveform generator. Fig. 2.7(b), applied gate voltage pulse
is displayed. There are three levels which are to empty a QD, to load an electron
into QD, and to read out the spin state, respectively. In this case, the spin in eachsequence is randomly loaded. Fig. 2.7 (c) shows a schematic for the CS response to
the pulse. As highlighted by red circle, a pulse-like signal appears in the read-out
level depending on the spin state. As explained in Fig. 2.7 (d), if the spin state is inhigher energy level, spin can tunnel out of the QD, and then, another one tunnels
into the QD, while it does not happen if the spin state is in lower energy level.
This measurement should be performed within a spin relaxation time (∼ 100 ms);otherwise, spin information will be lost.

2.5

RF reflectometry

2.5.1

LCR circuit

RF reflectometry is commonly used for fast charge sensing. In the circuit, device
electrode (reservoirs of CS or gates) is connected to transmission line (coaxial linefrom low temperature stage to outside of fridge) through impedance conversion
circuit, and the RF reflection is measured. The impedance of a QD (∼ 1 MΩ) ismuch higher than the characteristic impedance of a coaxial line Z0 = 50 Ω, so thatthe impedance is converted by LC tank circuit. An equivalent circuit for the RFreflectometry is an LCR circuit as shown in Fig. 2.8. Hereafter, we formulate theRF reflectometry from electrical circuit and transmission theories. The impedanceof the load circuit Zload is24

CHAPTER 2. THEORETICAL BACKGROUND

𝐿
𝐺

Figure 2.8: LCR circuit for RF reflectometry. G and C include
QD impedance and parasitic components likedielectric loss of printed
circuit board.

𝐶1
jωC + G2
1 − ω LC + jωLG,=
G + jωC

Zload = jωL +(2.12)

where L, C, and G are inductance, capacitance, and conductance of the LCR circuit, respectively, and ω is angular frequency of carrier wave. In reality, G comprises
device conductance and dielectric loss, and C include parasitic capacitance in addition to device capacitance. L actually has parasitic components; however, they are
ignored here for simplicity.
LC circuit at resonance has no reactance (which means that power consumptionof the impedance is at maximum); therefore, the resonance angular frequency ω0 of
Eq. 2.12 is

s

ω0 =

1
C − LG2
1
×
≃√
,
LC
C
LC

(2.13)

where C ≫ LG2 is assumed because (parasitic) capacitance, (quantum dot) conductance, and (chip) inductance are typically in the order of 1 pF, 1 µS, and 100 nF,
respectively. Then, Zload at resonance is turned out
25CHAPTER 2. THEORETICAL BACKGROUND√
jLG/ LCLG√,
Zres =≃C
G + jC/ LC(2.14)

where C ≫ LG2 is assumed again.
The reflection coefficient of the load impedance Γ is defined asΓ=

Zload − Z0,
Zload + Z0

(2.15)

where Z0 is the characteristic impedance of transmission line, normally equal to50 Ω. When Zload = Z0 , no reflection occurs, which is feasible by tuning circuit
parameters. When G belongs to a charge sensor, Γ senses charge transition intarget QDs via charge sensor conductance. This technique is called RF-SET. TheΓ shift at resonance, ∆Γres , can be derived as follows. Assuming that a chargetransition in target QD shifts Zres by a small value ∆Zres , reflection coefficient atresonance in this condition, Γ′res , isZres + ∆Zres − Z0
Zres + ∆Zres + Z0
2∆Zres Z0,∼ Γres +(Zres + Z0 )2

Γ′res =

(2.16)

where Zres + Z0 ≫ ∆Zres and Γres = (Zres − Z0 )/(Zres + Z0 ), and then, normalized
shift in Γres is∆ΓresΓ′ − Γres2∆Zres Z0= res=.
2 − Z 2)
Γres
Γres
(Zres
0

(2.17)

Eq. 2.17 indicates that a good impedance matching Zres ∼ Z0 significantly contributes a large reflection change.
The RF-SET allows multiplexing of signals, meaning simultaneous readouts ofmultiple qubits. So far, frequency-domain and time-domain multiplexing techniques
have been investigated.[58, 28] These techniques will be essential for fault-tolerant
quantum computing where millions of qubits are corrected in parallel.
26

CHAPTER 2. THEORETICAL BACKGROUND

2.5.2

Capacitance for RF-SET

In the community, the capacitance for the LC tank circuit is referred to as parasitic capacitance because parasitic capacitance is always used to make the RF reflectometry sensitive to impedance change in the QD as described in Eq. 2.14. However,the capacitance is essential for the best performance of practical RF reflectometry
as seen below. Figure 2.9(a) shows a simulation result of |∆Γ|, the difference between two conductance conditions which correspond to a Coulomb blockade and a
Coulomb peak, respectively. The equivalent circuit used in the simulation has the
conductance (capacitance) the same as in Fig. 2.8, however consisting of QD one,
GQD (CQD ) and an offset value, G0 (C0 ). Assuming G0 comes from the dielectric lossof printed circuit board, G0 = ωC0 tanδ, where ω is the carrier angular frequency
and tanδ is the loss-tangent. As seen in the Fig. 2.9(a), |∆Γ| as a function of C0
shows a maximum at a small C0 ∼ 4 fF, indicating the necessity of capacitance ofthe circuit. Typically, C0 is in the order of 100 fF due to parasitic capacitances ofprinted circuit board (PCB) and two-dimensional electron gas. The tanδ of 0.001,
used for the simulation, is close to the value of one of PCB materials with the lowest dielectric constants, and C0 for maximum |∆Γ| does not change so much evenwhen tanδ increases from the simulation value (Fig. 2.9(b)). Therefore, a finite C0
is always needed for an optimal RF-SET condition.

2.5.3

RF components

Here, we briefly describe electric RF components for RF reflectometry. Practically, in order to measure the reflected signal, it is necessary to derive the reflectedsignal from incident signal. Typically, directional couplers are used for this purpose.
Directional couplers are passive devices with four ports, and the four ports have two
types: transmission, and coupled ports. Two of the four ports are the transmission
ports. On the other hand, the other two ports are coupled ports which weakly27

CHAPTER 2. THEORETICAL BACKGROUND(b) 5.0|ΔΓ|𝐶0,max (fF)(a) 1.6

0.0

0𝐶0 (fF)

100

2.5
0.00

tan 𝛿

0.01

Figure 2.9: (a) Difference in Γ between Coulomb peak and blockade, |∆Γ| as afunction of the capacitance of an RF-SET circuit. It shows a maximum at a finite
capacitance value. (b) The capacitance for the maximum value of |∆Γ| as a functionof tan δ .
couples to each transmission port.
In the RF reflectometry, to extract reflected signal, incident wave is applied toa coupled port (CPL) which couples a transmission port (IN). This IN port is connected to a device under test (DUT), and hence, the signal is reflected. The reflectedsignal (mainly) passes from the IN port to the other transmission port (OUT) instead of the CPL port because the coupling between CPL-IN (20 dB, typically) is
designed to be much weaker than for IN-OUT (< 1 dB). Finally, only the reflectedsignal is obtained by monitoring the OUT output. (The other coupled port is notneeded, so that it is terminated with 50 Ω, or three-terminal directional coupler isused.) Note that CPL-OUT leakage (40 dB, typically) is inevitable and interfereswith the reflected signal, resulting in undesired frequency dependence (See Ch. 6).
The weak CPL-IN coupling strongly attenuates the incident signal, which actually matches a requirement for suppression of heat transfer. Weak power input isessential (∼ −100 dBm) at DUT located at a cryogenic temperature. In addition,
attenuators are located at different cold stages and also works as thermal anchors
which cool down transporting electrons step by step. This is needed to lower theelectron temperature and to observe clear quantum effects. Directional coupler also28

CHAPTER 2. THEORETICAL BACKGROUND
plays a role such that reflected signal avoids the strong attenuations.
In measurements, RF amplifiers are needed because of the low RF power of thereflected signals. In addition to the low power applied to DUT (< −100 dBm),
reflection coefficient at DUT has another attenuation because of the impedance
matching, further lowering the signal power. RF amplifiers can recover the power
even though it deteriorates the signal-to-noise ratio (SNR) compared with the one
at DUT, which is inherent in amplifier. One way to suppress this effect is use ofcryogenic amplifiers. The amplifier has been developed for cryogenic use, which isimportant to reduce thermal noise. The thermal noise in voltage Vn is expressed by√
4kB T BR, where kB is the Boltzmann constant, T a temperature, B a bandwidth,
and R a resistance which is the source of the noise. Comparing Vn at inputs ofroom temperature amplifier and cryogenic amplifier, the ratio is estimated to ∼ 5
by taking into account the voltage division between the device impedance and the
input impedance of the amplifier and assuming the device impedance close to thecharacteristic impedance. In addition, the noise figures of the amplifiers (the figure
indicating how much times larger output noise power is than that for the input) are
different, resulting in 16 dB improvement of power SNR in total. This value can beinterpreted into ∼ 6 times improvement of voltage SNR. .

2.6

Summary

In this chapter, we explained the characteristics of QD systems and charge sensing techniques. Even though we did not describe them here because they are outof scope of this thesis, the QD systems can show an abundant physical phenomena and interactions such as Kondo effect, Aharonov-Bohm effect, spin resonance,
exchange coupling, spin-orbit interaction, some of which directly relates with spin
qubit operations. This is also interesting aspect of QD systems.
Regarding spin readout, readout within coherence time (∼ 1 µs) is required for
fault-tolerant quantum computing, which is challenging but recently start to be29

CHAPTER 2. THEORETICAL BACKGROUND
realized.[26, 59] Still, development of faster readout technique is required.

30

Chapter 3
Device fabrication
In this thesis, physically defined quantum dots are studied. The devices
are fabricated utilizing the mature CMOS technologies. This chapter
describes the fabrication process flow step by step.

3.1

SOI thinning

Thin silicon quantum well is preferable from the point of view of the quantum
confinement. When the out-of-plane confinement of a quantum dot (QD) is determined by the thickness of quantum well, thinner quantum wells give rise to strong
out-of-plane confinements, and thereby, qubit states can be isolated from undesiredquantum states. On the other hand, thinner silicon on SOI layers will have larger
channel resistances, which will prevent fast charge sensing. Multi-step SOI thinningwill enable thin QD and thick electrodes but we do not adapt the technique forsimplicity.[60] Then, we chose a moderate thickness ∼ 30 nm. The wafer used here
has a 100-nm thick SOI layer and a 145-nm thick buried oxide (BOX) layer before
any processes.
Chip cleaning:- Pure water cleaning with ultra sonic cleaner 1 min- SPM (H2 SO4 : H2 O2 = 1 : 1) cleaning at 120 °C, 10 min for removing

31

CHAPTER 3. DEVICE FABRICATION
organic and metallic impurities- Running water cleaning 5 min- SC1 (NH4 OH : H2 O2 : H2 O = 1 : 5 : 25) cleaning at 150 °C, 10 min forremoving organic impurities and silicon particles- Running water cleaning 5 min- 1.5 % HF cleaning, 1 min for removing the oxide of SOI surface and metal
impurities- Running water cleaning 30 sec- SC2 (HCl : H2 O2 : H2 O = 1 : 1 : 5) cleaning at 150 °C, 10 min for removing metallic impurities- Running water cleaning 5 min
Thermal oxidation:
At 1000°C, 100 min; by this process, SOI layer thickness decreases from
100 nm to ∼ 30 nm.
Oxide removal:- Pure water cleaning with ultra sonic cleaner 1 min- Buffered HF (BHF) cleaning 3 min; the etching rate for SiO2 is∼ 70 nm/min.
- Pure water cleaning with ultra sonic cleaner 1 min

3.2

Quantum dot patterning

Electron beam lithography (EBL) and reactive ion etching (RIE) are used toform the QDs as well as side gates and charge sensors in the SOI substrate. The
pattern around the quantum dots is a nano-size structure, but patterning in microsize areas is also required to make disconnections between electrodes and between
devices. Therefore, we separately applied electron beams with the small-current
exposure for the nanostructure and with the large-current exposure for the pad
32CHAPTER 3. DEVICE FABRICATION
for the micro-size electrode. The electron beam exposures are continuously carriedout without removing the sample from the chamber and without alignment for the
exposures. Possible position shifts between the two exposure are compensated bytaking alignment margins in the patterns.
Chip cleaning:- Pure water cleaning with ultra sonic cleaner 1 min- SPM (H2 SO4 : H2 O2 = 1 : 1) cleaning at 120 °C, 10 min- Pure water cleaning with ultra sonic cleaner 1 min- HF cleaning, 1 min for removing the native oxide of SOI surface- Pure water cleaning with ultra sonic cleaner, 1 min
EBL resist coating:- Baking in oven at 180 °C, 10 min- Spin coating of an EBL resist (ZEP520A : ZEP-A = 1 : 1 containing
fullerene), 1st step 1000 rpm, 5 sec, 2nd step 3000 rpm, 60 sec-Prebake on a hot plate at 180 °C, 10 min
EBL:- 1st exposure: 50 kV, 60 pA for fine patterns- 2nd exposure: 50 kV, 7500 pA for device isolation patterns
Developpment:
ZED-N50 30 sec, IPA 30 sec
SEM:
To confirm whether EBL fine patters are formed as expected or not byobserving dummy patterns. Carbon tapes are used to fix the chips.
RIE:
Cl2 = 50 sccm, 50 W, ∼ 40 sec; The etching rate is ∼ 80 nm/min. The
etching time is chosen so that etching depth is roughly twice of SOI thickness.

33

CHAPTER 3. DEVICE FABRICATIONEBL resist removal:-ZD-MAC 10 min-IPA cleaning 3 min- Pure water cleaning with ultra sonic cleaner 1 min- Acetone 3 min- Pure water cleaning with ultra sonic cleaner 1 min- SPM (H2 SO4 : H2 O2 = 3 : 1) cleaning at 120 °C, 10 min- Pure water cleaning with ultra sonic cleaner 1 min
SEM:
To confirm whether physical fine patters are formed as expected or not byobserving dummy patterns. Carbon tapes are used to fix the chips.
Chip cleaning:- Pure water cleaning with ultra sonic cleaner 1 min- SPM (H2 SO4 : H2 O2 = 3 : 1) cleaning at 120 °C, 10 min- Pure water cleaning with ultra sonic cleaner 1 min- HF cleaning, 1 min for removing the native oxide of SOI surface- Pure water cleaning with ultra sonic cleaner 1 min

3.3

Top gate deposition

Before forming top gate structure used for charge accumulation, SOI layer isthermally oxidized for a better interface quality. Although poly-silicon is depositedfor the top gate, the poly-silicon layer can screen electric fields from side gates when
it gets into the gap between side gates and QD. Therefore, SiO2 is deposited by
Low Pressure Chemical Vapor Deposition (LP-CVD). (This LP-CVD was done by
Hiramoto group in Tokyo Univ.) Then, poly-silicon doped with a high concentration of phosphorus is separately deposited by LP-CVD. After the depositions,photolithography and plasma etching are performed to form the top gate.

34

CHAPTER 3. DEVICE FABRICATION
Chip cleaning:- Pure water cleaning with ultra sonic cleaner 1 min- SPM (H2 SO4 : H2 O2 = 1 : 1) cleaning at 120 °C, 10 min- Running water cleaning 5 min- 1.5 % HF cleaning, 1 min- Running water cleaning 30 sec- SC2 (HCl : H2 O2 : H2 O = 1 : 1 : 5) cleaning at 150 °C, 10 min- Running water cleaning 5 min
Surface passivation:
At 1000°C, 5 min; By this process, The surface of SOI layer is passivatedby covering 10-nm thick SiO2 .
Gate oxide deposition:
SiO2 deposition by LP-CVD at 840 °C, SiH2 SO4 + N2 O; ∼ 50-nm thick
SiO2 is deposited.
Chip cleaning:- Pure water cleaning with ultra sonic cleaner 1 min- SPM (H2 SO4 : H2 O2 = 1 : 1) cleaning at 120 °C, 10 min- Pure water cleaning with ultra sonic cleaner 1 min- 1.5 % HF cleaning, 3 min for removing the oxide of SOI surface and metal
impurities- Pure water cleaning with ultra sonic cleaner 1 min
Poly-silicon deposition:
Highly P+ -doped poly-Si deposition by LP-CVD, Si2 H6 0.3 sccm,
PH3 7 sccm, 500 °C, 40 min; ∼ 200-nm thick poly-silicon is deposited.
Photolithography for top gate pattening:- Baking in oven at 120 °C, 10 min- Spin coating of hexamethyldisilazane (HDMS) which works as an adhesion promoter for photoresist, 1st step 1000 rpm, 3 sec, 2nd step 2000 rpm,35

CHAPTER 3. DEVICE FABRICATION
30 sec- Spin coating of photoresist (S1818), 1st step 1000 rpm, 5 sec, 2nd step
3000 rpm, 60 sec- Prebake on a hot plate at 110 °C, 1 min - Photolithography 100 mJ- Development MF320 90 sec, pure water 30 sec
Plasma etching:CF4 100 sccm (max), O2 11 sccm, 250 W, 50 sec
Photoresist removal:- O2 ashing, O2 30 sccm, 50 W, 60 sec- Pure water cleaning with ultra sonic cleaner 1 min- SPM (H2 SO4 : H2 O2 = 1 : 1) cleaning at 120 °C, 10 min- Pure water cleaning with ultra sonic cleaner 1 min

3.4

Ion implantation

In order to make ohmic contact at cryogenic temperature, the SOI substrateneeds to be doped with a high concentration of impurities. Therefore, impurity
doping is carried out by ion implantation. Ion implantation is a low-temperatureprocess in which dopants are injected into the substrate with high energies. The
ion concentration can be made to have a peak at a desired depth by adjusting theacceleration energy. In our case, phosphorus is used as the dopant for electrontransport. The SiO2 formed as the gate insulator can moderate the irradiation
damage in SOI layer, but it may still remain. In addition, if the implanted impurities
are not at the lattice positions, the impurities do not work as dopants. Thermal
annealing, here referred to as drive-in annealing, restores the crystalline state of the
SOI layer and introduces the injected impurities into the lattice positions, making
it electrically active. If impurities are doped into the QD, their nuclear spins will
disturb spins in QD. Therefore, the top gate is used as a mask for the channel,
36

CHAPTER 3. DEVICE FABRICATION
resulting in self-aligned source and drain formation. For device without top gate
structure, resist mask is used to protect QD during ion implantation instead. The
drive-in also plays a role in the recrystallization of poly-silicon.
(Photolithography for resist mask:)- Baking in oven at 120 °C, 10 min- Spin coating of HDMS, 1st step 1000 rpm, 3 sec, 2nd step 2000 rpm, 30 sec- Spin coating of S1818, 1st step 1000 rpm, 5 sec, 2nd step 3000 rpm, 60 sec- Prebake on a hot plate at 110 °C, 1 min- Photolithography 100 mJ- Development MF320 90 sec, pure water 30 sec
Ion implantation:
Phosphorus (P+ ) doping, 1 × 1015 cm−2 ; The silicon substrate of a backgate device is also doped with P+ .
Chip cleaning- Pure water cleaning with ultra sonic cleaner 1 min- SPM (H2 SO4 : H2 O2 = 1 : 1) cleaning at 120 °C, 10 min- Running water cleaning 5 min- SC1 (NH4 OH : H2 O2 : H2 O = 1 : 5 : 25) cleaning at 150 °C, 10 min- Running water cleaning 5 min- 1.5 % HF cleaning, 1 min- Running water cleaning 30 sec- SC2 (HCl : H2 O2 : H2 O = 1 : 1 : 5) cleaning at 150 °C, 10 min- Running water cleaning 5 min
Drive-in annealing:
At 1000 °C, 30 min

37

CHAPTER 3. DEVICE FABRICATION

3.5

Contact pad deposition

Next, aluminum pads for wire bonding are fabricated using photolithography
and vacuum evaporator, and as the last step of device fabrication, the device isannealed in forming gas atmosphere to terminate dangling bonds at the interface of
the SOI layer.
Photolithography for resist mask:- Baking in oven at 120 °C, 10 min- Spin coating of HDMS, 1st step 1000 rpm, 3 sec, 2nd step 2000 rpm, 30 sec- Spin coating of S1818, 1st step 1000 rpm, 5 sec, 2nd step 3000 rpm, 60 sec- Prebake on a hot plate at 110 °C, 1 min- Photolithography 100 mJ- Hardening the resist surface by soaking the chip into chlorobenzene for
135 sec; The chip should immediately be dried after picking it up fromchlorobenzene.
- Development MF320 90 sec, pure water 30 sec- Postbake on a hot plate at 110 °C, 1 min
Oxide removal:- Pure water cleaning with ultra sonic cleaner 1 min- BHF cleaning, 90 sec- Pure water cleaning with ultra sonic cleaner 1 min
Thermal metal deposition:- Deposition of 300-nm thick aluminum, deposition of 100-nm thick aluminum only for devices without top gates- Lift-off of aluminum as follows: soaking the chip into acetone overnight;
ultra sonic cleaning with acetone- Optical micrography to check if lift-off works well.

38

CHAPTER 3. DEVICE FABRICATION
Forming gas annealing:
At 400 °C, 10 min, NH2 : O2 = 95 : 5, 100 sccm

39

Chapter 4
Physically defined triple quantum
dot systems in silicon on insulator
In this chapter, we report characterizations of two types of Si triple quantum dot (TQD) devices with charge sensors, with the aim of integrating
spin qubits. The QDs of a linear TQD device are connected in line toadjacent QD(s), while all QDs are tunnel-coupled to each other in theother device to form a triangle. Both TQD systems are physically defined on silicon-on-insulator substrates using electron beam lithography
and dry etching. From electron transport measurements of each type of
TQD system at 4.2 K, we demonstrate the formation of tunnel-coupled
TQD systems and the tunability of their electric potentials. This work
is published in Applied P hysics Letters.[49]4.1

Introduction

In this chapter, we demonstrate the integration of Si quantum dot (QD) structures by examining linear triple QD (LTQD) and triangular triple QD (TTQD)
structures. In the TQD structures, three QDs have the tunnel couplings that are
required to perform quantum operations between two spin qubits via an exchangeinteraction. [5] In addition, the TQD structures can be considered as exchange-only
qubits, which enable fast single-qubit operations using the exchange interaction.
[22, 61] Moreover, theoretical studies have revealed the existence of various physi40

CHAPTER 4. PHYSICALLY DEFINED TRIPLE QUANTUM DOT SYSTEMSIN SILICON ON INSULATOR
cal phenomena in TTQD structures, e.g., spin/charge frustration, [62, 63] chirality
qubits, [64–66] quantum cellular automata, [67, 68] and the Aharonov–Bohm effect.
[69–71] These studies were motivated by the fact that a TTQD is the minimum
QD configuration for many-body physics, a closed-loop system. Moreover, for wellknown quantum error correction codes,[2] two-dimensional qubit arrays of millionsof qubits are considered to be needed. [72–76]
In previous studies, complicated structures were used to form TTQD devices(except for the device described in Ref. 74), e.g., by combining etching and deposition of fine gates, [77] by bridge gate structures, [63] or by a special gate in anotherlayer. [71, 76] It would be very difficult to form a deep potential barrier at thecenter of a TTQD in order to separate the QDs while maintaining the inter-dot
couplings. Except for the lithographic patterning, our simple fabrication process toform a deep potential barrier is the same as that used for more fundamental QD
systems, such as a single QD system. It is expected that such a simple fabrication
process may help realize two-dimensional spin qubit systems in combination withthree-dimensional gate structures.

4.2

Device structure

Scanning electron micrographs of the LTQD and TTQD are shown in Figs. 4.1(a)and (b), respectively. Both types of TQD have three QDs (QD1, QD2, and QD3:
the numbered white dotted circles), and the dots of the TTQD form a triangle. A
set of SG structures is used to tune the potential around each TQD structure. A
CS utilizing a QD is integrated next to each TQD structure to detect changes in
the number of electrons in the dots. [78]In the measurements, currents through the QD systems were investigated as afunction of gate voltages. The currents show characteristic peaks due to singleelectron transport (SET). SET through a (multi-) QD system is allowed when thequantized levels in each QD are in a voltage bias window. When electrons pass41

CHAPTER 4. PHYSICALLY DEFINED TRIPLE QUANTUM DOT SYSTEMSIN SILICON ON INSULATOR
through two sequential QDs one by one, the condition is referred to as a triple point
because the current path involves three charge states, namely, (N, M ), (N + 1, M ),and (N, M + 1), where the parentheses indicate the charge configuration of the
double QD system, and N and M are integers. Analogously, for electrons passing
through three sequential QDs, the point is referred to as a quadruple point. In an
LTQD, a current path through all the dots is possible only at quadruple points,
while a TTQD has two paths from one reservoir to another reservoir, at triple andquadruple points, as shown in Fig. 4.1(b) by the green and blue arrows, respectively.

(a)

BG

VD V1 V2 V S

CS

1

3

2

VD

VScs
100 nm

TG V3

Vm

V1

VDcs

VCcs

(b)

VL

VC

VR

V2

1
2

V4

3

CS

VS

VScs

VDcs 100 nm

Figure 4.1: Scanning electron micrographs of (a) linear triple quantum dot (LTQD)
and (b) triangular TQD (TTQD). QDs in these TQDs are indicated by white dotted
circles. The QD located next to the TQD is used as a charge sensor (CS). Silicongate electrodes to which Vx is applied are also placed near the QDs to modify thepotential of the systems (x = 1, 2, 3, 4, L, C, or R). Drain and source reservoirs
are connected to each TQD and each CS. VD and VS (VDcs and VScs ) are applied to
the TQD (CS) drain and source reservoirs, respectively. In the TTQD, there is anadditional reservoir connected to another QD; however, the connection is electrically
restricted by voltages applied to the two upper gates (V3 and V4 ). Blue and/or green(pink) arrows show the current paths through the TQD (CS). In the LTQD system(a), a back gate (BG) is used to accumulate electrons, while the TTQD system (b)has a top gate structure (TG) for electron accumulation.

42

CHAPTER 4. PHYSICALLY DEFINED TRIPLE QUANTUM DOT SYSTEMSIN SILICON ON INSULATOR

4.3

Linear triple quantum dot

First, we focus on the LTQD device (Fig. 4.1(a)). Numerical derivatives of currents through the LTQD and its CS with respect to a gate voltage V2 at 4.2 K areshown as functions of gate voltages V1 and V2 in Figs. 4.2(a) and 4.2(b). V1 andV2 primarily control the potential of the nearest QD (QD1 and QD3, respectively).
Note that the cross-couplings with other QDs and tunnel barriers are not negligible;
thus, the number of electrons in QD2 and the CS change with V1 and V2 . Other gate
voltages (VL , VC , VR , and the back gate voltage) are fixed during the measurements
presented here. No current flows through the LTQD in almost the entire area ofFig. 4.2(a), because V1 and V2 are below their thresholds, while charge transitions in
the LTQD are detected by the CS (Fig. 4.2(b)). The transitions appear as lines withdifferent slopes in Fig. 4.2(b), indicating differences between couplings of each QD

-4.2

-4.2

-4.2

V2 (V)-3.2

dICS/dV2 (a.u.)-1.5 1.5

(c)

V1

(b)
-3.2
V1 (V)

2

V1 (V)(a) dI /dV (a.u.) -2
LTQD
2
-3.2

-4.2

V2 (V)-3.2

V2

Figure 4.2: Derivatives of currents through (a) an LTQD (dILTQD /dV2 ) and (b) a
CS (dICS /dV2 ) as functions of two gate voltages V2 and V1 at 4.2 K. VD = 1 mV,
VDcs = 5 mV, VL = VR = −3.25 V, VC = VCcs = VS = VScs = 0 V, and VBG = 5 V,
where VBG is the back gate voltage. For clarity, ILTQD and ICS are differentiatednumerically with respect to V2 . In (a), the LTQD current is almost suppressed,
while, in (b), charge transitions in the LTQD can be detected by the CS as lines on
the red/blue background. (c) Charge transition lines manually extracted from (b).
The lines have three different slopes (blue, green, and red), each corresponding toa change in the number of electrons in one QD in the TQD (QD1, QD2, and QD3,
respectively). The number of electrons in the LTQD is indicated by parentheses(N1 , N2 , N3 ), where Ni (i = 1, 2, 3) is the relative number of electrons in QDi,
counted from the (0, 0, 0) region, revealing the charge transitions. The (1, 1, 1) and(1, 2, 1) configurations should be in the orange region, even though this is not obviousin (b) owing to the low CS sensitivity.
43

CHAPTER 4. PHYSICALLY DEFINED TRIPLE QUANTUM DOT SYSTEMSIN SILICON ON INSULATOR
with the two swept SG voltages (V1 and V2 ). For example, among the three dots,
QD1 (QD3) is the closest to the gate to which V1 (V2 ) is applied and should result inthe most nearly horizontal (vertical) transition lines in V1 –V2 space. QD2 is locatedbetween QD1 and QD3; thus, the transition lines are expected to have the mostnearly diagonal gradient. For clarity, the transitions are extracted and classified bycolor according to the hypothesis explained above and the relative number of charges
in the LTQD are indicated in parentheses (N1 , N2 , N3 ) where Ni (i = 1, 2, 3) is theelectron number of QDi (Fig. 4.2(c)). The blue, green, and red lines correspond tothe changes in the number of electrons in QD1, QD2, and QD3, respectively. In
the orange region, QD1 and QD3 lines could exist; however, they are not visible
because of the low sensitivity. Owing to the fact that only three different slopes arefound, we conclude that no unintended QD is formed. The few-electron regime is
not achieved, because strong cross-coupling to tunnel barriers suppresses tunneling
events before the QDs become empty (not shown). Optimization of the QD design
will enable the few-electron regime in a physically defined LTQD.

4.4

Triangular triple quantum dot

We also studied electron transport through the TTQD with a CS at 4.2 K. Although each dot of the TTQD has a tunnel-coupled reservoir, the one with QD1
is electrically disconnected by the application of V3 and V4 to simplify the system.
This disconnection is confirmed by monitoring the current through the reservoir.
Figure 4.3(a) shows the current through the TTQD, ITTQD , and Fig. 4.3(b) thenumerical derivative of the current through CS, dICS /dV1 at 4.2 K. These were
measured at the same time as functions of V1 and V2 . As shown in Fig. 4.3(b), there
are lines with three different slopes, each corresponding to charge transitions in adot, which is the same as in the target LTQD system. Again, three clear slopes
indicate no additional dot formation (Fig. 4.3(c)).
Standard bias dependence measurements on the TTQD were also performed to44CHAPTER 4. PHYSICALLY DEFINED TRIPLE QUANTUM DOT SYSTEMSIN SILICON ON INSULATOR
estimate the addition energies: (E1 , E2 , E3 ) = (5.3, 4.4, 4.5) in meV, where Ei is the
addition energy of QDi in the range of the measurements. From the addition energy, the diameter of a quantum dot can be estimated approximately. By using theclassical two-dimensional disk self-capacitance C, we have Eadd ∼ e2 /C = e2 /4ϵr ϵ0 d
(Ref. 52), where Eadd is the addition energy, e is the elementary charge, ϵr is thedielectric constant of a QD, ϵ0 is the vacuum permittivity, and d is the diameter ofthe dot. The diameters of the QDs are estimated as (dQD1 , dQD2 , dQD3 ) = (73, 89, 87)
in nm, where ϵSi = 11.68. These values roughly agree with those estimated from
Fig. 4.1(b) (about 60 nm), which implies that the charge transitions occur as expected in the physically defined QDs, not in unintentional dots. The discrepancy
between the estimated diameters can be attributed to capacitance couplings withgates and reservoirs.

V2 (V)

A

-3.3
-3.3

2

A
B

V1 (V)

30

(b)
-2.3

dIcs/dV1 (a.u.)

-5

5

B

-2.3

-3.3
-3.3

(c)

V2

|ITTQD|(pA)

V2 (V)(a)-2.3

V1 (V)-2.3

V1

Figure 4.3: (a) Current through a TTQD (ITTQD ) and (b) derivative of CS current
with respect to V2 (dICS /dV2 ) as functions of gate voltages V1 and V2 at 4.2 K.
VD = −0.5 mV, VDcs = 10 mV, V3 = V4 = −3 V, VS = VScs = 0 V, and VTG = 1.2 V,
where VTG is the top gate voltage. Two types of triple points A and B can be found(white dotted triangle). (b) dICS /dV2 shows charge transition lines of the TTQD.
(c) Extracted charge transition lines. Parentheses indicate the relative electron
numbers in the TTQD. Some lines show a discrepancy with those found in (b)because the charge sensing lines are not straight around charge degeneracy points
owing to strong tunnel coupling between QDs.

45

CHAPTER 4. PHYSICALLY DEFINED TRIPLE QUANTUM DOT SYSTEMSIN SILICON ON INSULATOR

4.5

Quadruple point

To prove the existence of couplings between each two quantum dots, we focus
on two types of charge triple points (TPs), namely, a pair of apparent TPs (“A” in
Figs. 4.3(a) and 4.4) and a pair of TPs with a vague peak (“B”). The weak current at
point B can be considered as a TP where current flows through three quantum dots,with one QD being skipped via co-tunneling processes owing to the strong tunnel
couplings of QD3 with the dots and the reservoir (Fig. 4.4(b)).[79–81] The strong
couplings can be acquired from a non-resonance current on the charge transitionlines of a QD (the white dashed line in Fig. 4.4).
We repeated the same measurements at different V3 = V4 (Figs. 4.4(d) and 4.4(e))
and observed the change in TPs. As V3 = V4 increases negatively, TP B becomescloser to TP A, which indicates that TPs A and B are current peaks through different
sets of two serial QDs (Fig. 4.4(d)). Thus, we conclude that all the QDs are tunnelcoupled, because TP A indicates one of three inter-dot couplings (QD2–QD3) andTP B indicates the others (QD1–QD2 and QD1–QD3).
At further increased V3 = V4 , TP A merges with TP B, resulting in a quadruple
point (QP) (Fig. 4.4(e)). At a QP, all the energy levels of the three dots align witheach other.[82, 83] The observation of this QP demonstrates the tunability of the
proposed system.

4.6

Summary

To perform fault-tolerant quantum computing, two-dimensional integration of
millions of qubits will be important. In this chapter, two types of physically defined
TQD systems, each with a charge sensor, have been studied. One of these hasa linear TQD while the other has a triangular TQD. Both were fabricated on asilicon-on-insulator wafer using standard fabrication techniques for Si MOSFETs.
The TQD configuration was achieved easily, by simply modifying the lithographic
46

CHAPTER 4. PHYSICALLY DEFINED TRIPLE QUANTUM DOT SYSTEMSIN SILICON ON INSULATOR
pattern for a simpler QD system using electron beam lithography and dry etching
techniques. The current through these systems was measured at 4.2 K as a functionof SG voltages and clearly showed the realization of a TQD without unintentional
QDs in each system. This work demonstrates the realization of a promising QD-(b)

V2 (V)(a) |I | (pA) 0.0
TTQD
-2.3

-2.8
-2.8

40.0

μD

Co-tunneling
QD2 QD1 QD3
μS

A
A
B

(c)

B
-2.3

V1 (V)

(d)
-2.3

μD

μS

(e)
-2.3

A
B
V1 (V)V2 (V)V2 (V)

A

-2.8
-2.8

TP B
Co-tunneling
QD2 QD3

B
-2.3

-2.8
-2.8

QP

V1 (V)-2.3

Figure 4.4: (a) Current through a TTQD shows TPs close to a QP as a functionof V1 and V2 at V3 = V4 = −3.00 V. The voltages applied to the other gates are thesame as those shown in Fig. 4.3. TPs between QD2 and QD3 are observed (“A”;
blue dotted triangle). One of the TPs between QD1 and QD2 (“B”; black dotted
triangle) is unclear because high-order tunneling is dominant. (b, c) Schematicenergy diagrams of the TTQD: (b) at TP B (white dot in (a)) and (c) along the line
corresponding to a charge transition in QD2 (white dashed line in (a)) where nonresonant current flows. The Fermi levels of the reservoirs, µD and µS , are broadenedby thermal energy. (d, e) Current measured at (d) V3 = V4 = −3.05 V and (e)−3.10 V. The color scale and range of V1 and V2 are the same as in (a). (d) As
V3 = V4 becomes more negative, TP B (QD1–QD2) becomes closer to TP A. (e)TPs A and B merge, resulting in a QP (white dotted circle).
47

CHAPTER 4. PHYSICALLY DEFINED TRIPLE QUANTUM DOT SYSTEMSIN SILICON ON INSULATOR
array unit for the two-dimensional integration of millions of spin qubits.

48

Chapter 5
Tunneling event detection using
single-shot measurements
improved by numerical treatments
In this chapter, we report detection of single tunneling event of electron
in a physically defined silicon quantum dot system using numerical treatments. In the measurement, we observed single-shot tunneling events ina quantum dot using a charge sensor; however the tunneling statistics are
difficult to acquire because of their weak signals. Hence, two numericaltreatments using a digital filter and a change point detection techniqueare applied, and the latter enables precise signal detection, which is confirmed in the simulation. We expect the combination of such digitalprocessing with integrated circuits to enable a fast qubit readout from anoisy system. This work is published in Applied P hysics Express.[84]5.1

Introduction

Qubit readout is an important component of quantum computing. Digital signal
processing can facilitate qubit readout which often requires detection of two-level
step signals. In the literature, a step detection technique known as Canny’s edge
detection has been demonstrated to enable more precise edge detections than simple
thresholding.[85–88] Moreover, change point detection techniques are useful for pre49

CHAPTER 5. TUNNELING EVENT DETECTION USING SINGLE-SHOT
MEASUREMENTS IMPROVED BY NUMERICAL TREATMENTS
cisely detecting steps, where the maximum log-likelihood ratio (LLR) is estimatedbetween likelihoods for two conditions with and without a change point.[89, 20]
Furthermore, it has been reported that the maximum LLR technique improves spin
detection in the nitrogen-vacancy center.[90–92] These studies indicate the possibility that numerical treatments improve readout of spin qubit states. In the present
study, we observed single tunneling events in a physically defined silicon quantum
dot (PD-QD) system. We performed detection of tunneling events in a PD-QD system by monitoring current through a charge sensor (CS). However, the CS distantfrom the target QD resulted in low signal-to-noise ratio (SNR), preventing clear
acquisition of tunneling events. To overcome this, we applied posterior numerical treatments and demonstrated the capability of one of the treatments to detecttunneling events from noisy signal.

5.2

Measurement setup

Figure 5.1 shows the PD-QD system used in this study. The QD device compriseda triangular triple QD (TTQD), CS, a top gate (TG), and four side gates (SGs).
Two of the four SGs (R1 and R2) were open as well as the reservoir of the TTQD
(T3) because of the limited number of available DC lines. DC voltages from floating
voltage sources were applied to the other SGs (L1 and L2), TG, CS drain (DCS ),and other reservoirs of the TTQD (T1 and T2). A voltage, VTTQD , was applied
to both T1 and T2 to tune the potential of the TTQD in an offset bias voltage
manner.[46] The PD-QD system was mounted on a printed circuit board together
with RC LPFs for noise suppression. For TG, T1, and T2, RC filters with a low
cut-off frequency fc were used (R = 390 kΩ, C = 4.7 nF, fc ∼ 87 Hz). On the other
hand, RC filters for reservoirs of the CS were set to have higher frequencies not toprevent step detections (R = 3 kΩ, C = 220 pF, fc ∼ 240 kHz for DCS , R = 510 Ω,
C = 220 pF, fc ∼ 1.42 MHz for SCS ). Moreover, AC voltages from an arbitrary
waveform generator (AWG) were combined with the DC voltages applied to L1
50

CHAPTER 5. TUNNELING EVENT DETECTION USING SINGLE-SHOT
MEASUREMENTS IMPROVED BY NUMERICAL TREATMENTS
and L2 using resistive voltage adders. The current flowing through the source ofCS (SCS ), ICS , was measured using an oscilloscope after the following treatments:
conversion into voltage, further filtering with an active Bessel LPF with a cutoff
frequency of 10 kHz, and amplification by a factor of 5. The Bessel filter determines
the cutoff frequency of the system.
Trigger

AWG

Voltage sources

Oscilloscope

Voltage amplifier
VoltageaddersLow-pass filter

IV converter

RT

LT

3 dB
attenuators

RC filters

TG L2
L1

T1 R2

T3

100 nm

R1
T2

Dcs

Scs

Figure 5.1: Measurement setup with scanning electron micrograph of quantum dot(QD) device nominally identical to measured one. White dotted circles indicate of
the supposed positions of the target QD and charge sensor, respectively. See main
text for details.

5.3

Charge sensing and the position of thequantum dot

We measured CS characteristics at 300 mK in advance to measurements for tunneling event detection. Here, only DC voltage sources and DC current monitor wereused. Fig. 5.2 shows numerical differential conductance dICS /dVDSCS as a function

51

CHAPTER 5. TUNNELING EVENT DETECTION USING SINGLE-SHOT
MEASUREMENTS IMPROVED BY NUMERICAL TREATMENTS

dICS/dVDSCS (a.u.)

080

Figure 5.2: Coulomb diamond measurements on CS at 300 mK. VL1 = VL2 = 0 V.
of CS bias voltage VDSCS and VTG . There are clear Coulomb diamonds, indicating
a formation of a well-defined single QD as expected.
Next, we tried charge sensing with the sensor by applying DC voltages.
Fig. 5.3(a) shows dICS /dVSG as a function of VTG and DC voltage commonly applied to L1 and L2, VSG . In Fig. 5.3(a), charge sensing lines with a single slope
appear in a wide range of voltage, indicating the formation of a single QD against
expectation from QD design (Fig. 5.1). This may be because of strong QD-reservoir
coupling of two of three QDs in TTQD. We also measured CS current as a functionof VL1 and VL2 (not shown), but no charge sensing lines were recognized , possibly
because of large steps for the voltage sweep and the charge sensing lines almost
parallel to Coulomb peaks of CS. These results show the system was not ideal but
still single-shot readout was possible as seen as follows. Another charge sensing
measurement was performed with the setup in Fig. 5.1 except for voltage adders.
In this measurement, voltage adders were omitted for wider AWG voltage range.
We measured ICS as a function of voltages applied to L1 and L2, i.e., VL1 and VL2 ,respectively (Fig. 5.3 (b)) at 300 mK. In the measurement, a ramped voltage from
−0.5 to 0.0 V was applied to L2, and the ICS response was averaged 16 times at VL1 ,52

CHAPTER 5. TUNNELING EVENT DETECTION USING SINGLE-SHOT
MEASUREMENTS IMPROVED BY NUMERICAL TREATMENTS
while VL1 was changed step by step. As shown in the results, clear charge sensing
lines appeared where charge transition occurred in one QD of the TTQD. To infer
the position of the target QD, We checked the distance of the two lines in VL1 (inVL2 ), and thereby the gate-QD capacitance is estimated to ∼ 0.38 aF (∼ 0.29 aF) bytaking into account 3 dB attenuation for L1 (L2). The capacitance for L1 is close
to the one between a gate and its closest QD estimated for a TTQD used in ourprevious study (∼ 0.4 aF).[49] Hence, we conclude that the target quantum dot was
located at the QD connected to T3.

(a)dICS/dVSG (a.u.)-10 -50

5(b)

ICS (nA)

4

5

0.0

Figure 5.3: Charge sensing lines in a wide voltage range. (a) dICS /dVSG as afunction of VTG and DC voltage commonly applied to L1 and L2, VSG . VDSCS =−10 mV, VTTQD = 0 V. Charge sensing lines with a single slope appeared, implying
a formation of a single QD in the TTQD. (b) ICS as a function of VL1 (step) andVL2 (ramp). In the measurement, voltage adders for L1 and L2 were not used, sothat actual gate voltages were twice as high as with the voltage adders. From the
distance of the two sensing lines, gate-QD capacitances were estimated.

5.4

Single-shot tunneling detection

To identify a favorable condition for the single-shot readout, we measured ICS
as a function of VL1 and VL2 with a different parameters in the setup in Fig. 5.1
53

CHAPTER 5. TUNNELING EVENT DETECTION USING SINGLE-SHOT
MEASUREMENTS IMPROVED BY NUMERICAL TREATMENTS(Fig. 5.4(a)). In the measurement, a ramped voltage from −1.0 to 0.0 V was applied
to L2 in addition to a DC constant voltage of −0.5 V via a voltage adder while VL1
was changed step by step from −1.0 to 0.0 V. For tunneling detection measurements,
we fixed VL2 = −0.21 V because of the excellent sensitivity.
Next, we applied voltage pulses to L2 and observed single tunneling events in asingle-shot manner (Figs. 5.4(c) and (d)). The applied pulse comprised three levels,
as shown in Fig. 5.4(c), each corresponding to the position of the same symbol in
Fig. 5.4(a). The functions of the three levels were to load an electron into the QD(“load” level, VL2 = −0.5 V), to read a tunneling event from the QD to its reservoir(“read” level, VL2 = −1.0 V), and to ensure that the QD was empty (“empty” level,
VL2 = −1.5 V). The “read” level was selected as a voltage sufficiently close to thecharge transition point with a moderate tunneling rate.
An example of the pulse response is shown in Fig.. 5.4(d). As indicated by theorange arrow, a time-dependent step signal appeared owing to single electron’s tunneling out of the QD. We repeated the pulse measurement 864 times under the same
DC voltage to acquire the statistics of the tunneling events. The inset of Fig. 5.4(d)shows the averaged current in the “read” level over all the pulse measurements. As
expected for a Poisson distribution with a rate Γ within the tunneling time, theaveraged current exhibited an exponential decay, with a distortion. From the latter
half of the averaged current, Γ was estimated to be ∼ 100 Hz.
To acquire the tunneling rate around the charge sensing line in Fig. 5.4(a), we
measured averaged pulse response as a function of VL1 . In the measurement, thepulse voltage in Fig. 5.4(c) was applied to L2 while VL1 was changed step bystep. Here, ICS was averaged 16-times by a built-in function of the oscilloscope
instead of numerical averaging which was used in the inset of Fig. 5.4(d). In the VL1range, “load” and “empty” levels were always far away from the charge sensing line.
Thereby, the measured current at “read” level shows exponential curves reflecting
the single tunneling events as a function of distance from the charge sensing line
54

CHAPTER 5. TUNNELING EVENT DETECTION USING SINGLE-SHOT
MEASUREMENTS IMPROVED BY NUMERICAL TREATMENTS

0.0

𝐼CS (nA)−-0.5

𝑉L2 (V)𝑉L1 (V)

−

−

−
−

−

-0.4

(b)
−

−

−1.1 − 9 − 7 -0.5

𝑉L2 (V)

empty

(d)

𝐼CS (nA)−

𝐼CS (nA)

-0.2

(a)

read

(c)

-1.5

−

−

load

Γ ∼ 100 Hz
0

20

40

60

Time (ms)80

Figure 5.4: (a) 16-times averaged charge sensor current ICS as a function of twoside-gate voltages VL2 and VL1 . A clear charge-sensing line appeared. Symbols
on dashed line (circle, triangle, and square) represent three levels of pulse used in
the single-shot measurement in (c) and (d). VTG = 1.795 V, VDcs = 30 mV, andVTTQD = 25 mV. (b) Horizontal cut of (a) at VL1 = −0.21 V (white dashed linein (a)). Kink indicates the position where electron transition occurred in one QDof the TTQD. (c, d) Three-level voltage pulse (c) and response (d). As indicatedby the orange arrow in (d), a time-dependent tunneling event was obtained. Inset:
ICS at the “read” level averaged over 864 pulse measurements (blue). Latter half ofcurrent was fitted with an exponential function (red), and Γ was estimated to be∼ 100 Hz.
(Fig. 5.5(a)). As a result, the exponential decays around VL1 = −0.25 V show different amplitudes and decay times, corresponding to changes in sensor sensitivity
and tunneling time, respectively (Fig. 5.5(b)). Even though we would have liked
to set the condition with maximum sensitivity and a good tunneling rate, shifts ofapplied voltage prevented it. The cause of the shifts is unclear, but it may comefrom measurement system rather than device characteristics. This is because theshift was reproducible and depended on the start voltage of a measurement.

55

CHAPTER 5. TUNNELING EVENT DETECTION USING SINGLE-SHOT
MEASUREMENTS IMPROVED BY NUMERICAL TREATMENTS

(a)

-0.4
ICS (nA)

-0.3

(b)

Figure 5.5: (a) Averaged pulse response of ICS at “read” level at different VL1 . The
current was averaged by a built-in function of the oscilloscope. (b) Horizontal cut of(a) at VL1 = −0.23 V (blue), −0.26 V (red), −0.29 V (green), and −0.32 V (purple).
VL1 for each trace corresponds to the position indicated by an arrow with the samecolor in (a). The exponential decays show different amplitudes and decay times,
corresponding to changes in sensor sensitivity and tunneling time, respectively.

5.5

Digital low-pass filtering

As shown in Fig. 5.4(d), the SNR of the step signals was not sufficiently high forsingle-shot tunneling event detection, at least, by a simple thresholding. Hence, weapplied two posterior treatments separately to extract the location where tunneling
events occurred: digital LPF and change point detection using LLR. First, we applied a digital LPF to the data for noise suppression. The filter was applied after
subtracting the average current in the “empty” level for each single-shot trace tosuppress fluctuations among all the repeated measurements. As the digital filter, weselected a 10th-order digital Bessel LPF with a −3-dB cutoff frequency fc = 500 Hz
using Python package “scipy.” Figure 5.6(a) shows a comparison of the pulse response at the “read” level before and after the LPF treatment. As shown, the LPF
suppressed the noise significantly. After the LPF treatment, tunneling positions in
the pulse measurements were detected by thresholding each pulse response at the56

CHAPTER 5. TUNNELING EVENT DETECTION USING SINGLE-SHOT
MEASUREMENTS IMPROVED BY NUMERICAL TREATMENTS“read” level. To obtain the optimal threshold, we referred to a histogram of ICS
at the “read” level including all the repetitions, and it indicated a clear bimodal
characteristic (Fig. 5.6(b)). Therefore, we set the threshold current for tunnelingdetection to the minimum count position between the two peaks. By detecting thefalling edge with the threshold, a histogram for the tunneling time was obtained,
and a fitting over the whole x-axis range of the data points with an exponentialfunction revealed Γ to be ∼ 180 Hz (Fig. 5.6(c)). However, this value was almost
twice larger than that obtained from the averaged current in the inset of Fig. 5.4(d),and the fitting exhibited a clear exponential decay without distortion, unlike theaveraged current, implying errors in the step detection. These discrepancies may
be attributed to slow fluctuations during each pulse measurement, whose frequency
was supposed to be significantly lower than the cutoff frequency and hence difficult
to suppress.

(a)

(b)

(c)

60

-80

Γ ∼ 180 Hz

40

-100

20

-120

20

80

Count

Δ𝐼𝐶𝑆 (pA)

-60

25

30

35

Time (ms)

40

0

2

0

4

Count (× 10 )
4

20

25

30

35

Time (ms)40

Figure 5.6: (a) Example of comparison between pulse responses at “read” level
before and after digital LPF treatment (blue and red traces, respectively). Offset
due to the filtering was compensated by subtracting the difference between averaged
currents before and after digital filtering at the “read” level. (b) Histogram of pulse
measurements after LPF treatment. LPF treatment elongated transient responses,
as shown in gray shades in (a); therefore, the histogram was used for the data points
between the shades. (c) Histogram of tunneling times obtained by thresholding
digitally filtered single-shot data (blue). It was fitted with an exponential function(red), and Γ was estimated to be ∼ 180 Hz.

57

CHAPTER 5. TUNNELING EVENT DETECTION USING SINGLE-SHOT
MEASUREMENTS IMPROVED BY NUMERICAL TREATMENTS

5.6

Change point detection

Next, we applied the other numerical treatment based on change point detection
theory.[89, 20] In the present study, we used the simplest one involving the LLR,
which is effective for step detection.[93, 94] This technique has been utilized insome studies using GaAs QDs to count tunnel events or to study hidden Markov
models.[95, 96] Meanwhile, we applied this technique to investigate noisy tunneling
event signals in a silicon QD. The LLR can be calculated by taking the logarithm of
the ratio of a likelihood L(H1 ) for a single change point hypothesis H1 to anotherlikelihood L(H0 ) for a null hypothesis H0 is estimated. Each likelihood can be
expressed as below:

L(H0 ) = p(X|H0 ) =L(H1 ) = p(X|H1 ) =

N
Y
i=1
r
Y
i=1

p(x[i]|x̄N ),p(x[i]|x̄r )

(5.1)
N
Y

p(x[j]|x̄N −r ),

(5.2)

j=r+1

where p(x|θ) is a probability density function for x given θ, r is an assumed change
point, x̄N =

PN −1
i=0

x[i]/N , x̄r =i=0 x[i]/(r+1), and x̄N −r =

Pr

PN −1

i=r+1 x[i]/(N −r−1).

When p(x|θ) is a Gaussian distribution function with a standard deviation σ as seen(x−θ)2

1
in Fig. 5.6(b), p(x|θ) = √2πσ
e− 2σ2 , the log-likelihood R is2

L(H1 )
R[r] = ln
L(H0 )

!





r
N
−1
N
−1

X
X
1 X
(x[j] − x̄N −r )2 −= − 2  (x[i] − x̄r )2 +(x[k] − x̄N )2 
2σ i=0
j=r+1
k=0

o
1 n
2
2
2
−(r
+
1)x̄
−
(N
−
r
−
1)x̄
+
N
x̄
r
N −r
N
2σ 2
2
(x̄N −r − x̄r )=− 2.
2σ ((r + 1)−1 + (N − r − 1)−1 )

=−

(5.3)

Then, the index whose R shows a maximum value, r̂ = argmax(R), is most0≤r≤N −1

likely to be the change point.
58

CHAPTER 5. TUNNELING EVENT DETECTION USING SINGLE-SHOT
MEASUREMENTS IMPROVED BY NUMERICAL TREATMENTS

3ℛ (a.u.)

(a)

(b)

Γ∼
100 Hz

2
1

0
20

25

30

35

40

20

25

30

35

40

Figure 5.7: (a) Raw data at “read” level (blue) and its log-likelihood ratio (LLR),
R (red). Maximum position of R indicates step position. (b) Histogram of tunnelingtime obtained by LLR estimation (green). It exhibited an exponential decay witha distortion, as expected. From an exponential fitting of the latter half of thehistogram (purple dashed line), Γ was estimated to be ∼ 100 Hz, which agrees wellwith that estimated from the averaged current (inset in Fig. 5.4(d)).
Figure 5.7(a) shows the measured pulse response, ICS , and the corresponding
LLR result. As shown in the figure, the maximum position in R detected the step
position of the noisy raw data. We repeated the LLR calculation over all the pulse
responses and obtained a histogram of the tunneling times (Fig. 5.7(b)). Unlike thedigital LPF result, the distortion was qualitatively reproduced, implying its better
validity. By fitting the histogram, Γ was estimated to be ∼ 100 Hz. This value
corresponds to that estimated from the averaged current and is therefore supposed
to be more reliable than that for the digital LPF treatment.

5.7

Simulation for comparison of the digital
signal process techniques

To confirm the significance of the maximum LLR test, we compared the two numerical treatments in the simulation. For the simulation, noisy steps corresponding
to the measured responses were generated. Each signal had a step with a height of 2,59

CHAPTER 5. TUNNELING EVENT DETECTION USING SINGLE-SHOT
MEASUREMENTS IMPROVED BY NUMERICAL TREATMENTS
2000 data points corresponding to a time scale from 20 to 40 ms in the measurements,
and a step length determined probabilistically using a Poisson distribution. First,
we tried adding white noise and 1/f noise to the ideal steps using a python package“colorednoise”. The results are shown in the Fig. 5.8(a-d). Fig. 5.8(a) shows a fast
Fourier transform (FFT) of squares of measurement and simulation results. By tuning the balance between white noise and 1/f noise, the simulation has a qualitatively
good agreement with measurement result. Figs. 5.8(b) and (c) show comparisons insingle step and in histogram of all the single-shot traces. In Fig. 5.8(c), the peak
position of measurement result is shifted by 337 pA, and the amplitude of the simulation is divided by a factor of 0.7 for obvious comparison between simulation andmeasurement. It reveals that the standard deviations for both histogram peaks arealmost the same. On the other hand, after digital LPF treatments, the histogram ofthe simulation result could not reproduce the measurement result (Fig. 5.8(d)). Thismay be attributed to the effect from other types of noise such as Brownian noise.[97]Brownian noises can have Lorentzian spectra which deviate from and become weaker
than 1/f 2 characteristics for low frequencies.
Next, we added noise comprised white Gaussian noise (mean = 0; standard deviation = 1) and different offsets for step signals that mimicked the slow fluctuationin the measurements, resulting in an SNR of ∼ 1 in the step signals, as observed in
the measurements (Fig. 5.9). The offsets exhibited a Gaussian distribution (mean= 0; standard deviation = 0.55) and qualitatively reproduced the histogram in
Fig. 5.6(b) (Fig. 5.9(a)). In Fig. 5.9(b), we compare the histograms of step positions
detected using the two numerical treatments with the histogram of the original step
positions. Even though the digital LPF result (green solid line) agreed well withthe original step histogram (red dotted line), unlike the measurement result, themaximum LLR test result (blue solid line) indicated a better result with an almost
complete agreement with the original one, revealing its strong ability in detecting
steps.
60

CHAPTER 5. TUNNELING EVENT DETECTION USING SINGLE-SHOT
MEASUREMENTS IMPROVED BY NUMERICAL TREATMENTS(b) 40Current (pA)

10-5
10-6
meas.
sim.

10-7
101

Counts (×104)

(c)

20
15

102
103
104
Frequency (Hz)

meas.

-40
-80
20

105

10

5

40

Time (ms)

(d)

meas.
sim.*0.7

sim.

0Counts (×104)

Noise (V2/Hz)(a) 10-4

meas.
sim.

4
2
0

0
-40

0
Current (pA)

40

-30

0
Current (pA)30

Figure 5.8: Simulation including 1/f noise. (a) Noise spectra in the measurement(blue) and simulation (orange). To obtain each spectrum, fast Fourier transforms
were performed on squared single traces separately and averaged over all the obtained FFT spectra. The simulation agrees with the measurement result well. (b)Comparison of single signals from simulation and measurement results. (c) Comparison of histograms from simulation and measurement results. For visibility of peakwidth, the height of the histogram for simulation decreased by a factor of 0.7, andthe peak position of the histogram for measurement result was shifted by 337 pA.
(d) Comparison of histograms from simulation and measurement results after digital
LPF treatments. The peak position of the histogram for measurement result was
shifted by 100 pA. A single peak appeared in the histogram for simulation, whilea bimodal peak appeared in the histogram for measurement results in Fig. 5.6(b).
This discrepancy may be attributed to difference between simulation and measurement in 1/f noise.

5.8

Summary

In this chapter, we successfully observed tunneling events in a single-shot mannerin PD-QDs. Even though the SNR of the charge sensor signal was lower thanunity, the digital LPF treatment and the change point detection technique applied
enabled tunneling event detection. For the digital LPF, a 10th-order Bessel LPF was

61

CHAPTER 5. TUNNELING EVENT DETECTION USING SINGLE-SHOT
MEASUREMENTS IMPROVED BY NUMERICAL TREATMENTS

(b)
100

2

Count

Signal

(a) 4
0
0

2

4

6

Count (×104)

50
0
20

25

30

35

40

Figure 5.9: (a) Histogram of data points in all step signals after digital LPF
treatment. Noise was selected such that the histogram resembled that in Fig. 5.6(b).
(b) Comparison between histograms of step positions obtained from two numericaltreatments in simulation. First, we generated the same 1000 step signals except
for the step lengths determined probabilistically via a Poisson distribution. At
this point, a histogram of tunneling time was created from the data (red dottedline). Subsequently, noise was added to the signals, and histograms of step positions
detected after a digital LPF (green solid line) and by change point detection using
LLR (blue solid line) were obtained.
utilized, and its noise suppression facilitated step detection even though Γ appeared
to be overestimated, likely owing to slow fluctuations in the signals. Meanwhile, achange point detection technique using the LLR was applied to the raw measurement
data; it was discovered that the LLR precisely indicated the step position as its
maximum position. Finally, we compared the two techniques by applying themto generated step signals and demonstrated the significance of the maximum LLR
test technique. This step detection may be useful for spin readouts where the step
signal appears.[98–100] In addition, according to Ref. 94, the technique is applicable
to pulse detection, which is often required for a spin readout using tunneling between
a QD and its reservoir.[101, 18, 41] We expect that this technique facilitates qubit
characterizations, and that its combination with an integrated circuit enables a fast
qubit readout from a noisy system.

62

Chapter 6
Radio-frequency single electrontransistors with a sensitive phase
response
Radio-frequency reflectometry techniques are instrumental for spin qubit
readout in semiconductor quantum dots. However, a large phase response is difficult to achieve in practice. In this chapter, we reportradio-frequency single electron transistors using physically defined quantum dots in silicon-on-insulator. We study quantum dots which do nothave the top gate structure considered to hinder radio frequency reflectometry measurements using physically defined quantum dots. Based on
the model which properly takes into account the parasitic components,
we precisely determine the gate-dependent device admittance. Clear
Coulomb peaks are observed in the amplitude and the phase of the reflection coefficient, with a remarkably large phase signal of ∼ 45 degree.
Electrical circuit analysis indicates that it can be attributed to a good
impedance matching and a detuning from the resonance frequency. We
anticipate that our results will be useful in designing and simulatingreflectometry circuits to optimize qubit readout sensitivity and speed.
This work is published in Scientif ic Reports.[102]63CHAPTER 6. RADIO-FREQUENCY SINGLE ELECTRON TRANSISTORSWITH A SENSITIVE PHASE RESPONSE

6.1

Introduction

To adapt to the requirements for fast and quantum-non-demolition spin readout
for fault-tolerant quantum computing,[2, 29, 30] radio-frequency (RF) reflectometry
has been widely studied in the QD systems.[59, 103, 25, 104, 105, 35, 106] This
technique utilizes impedance matching between the transmission line and the QD
system within a resonator.[21] Therefore, modifications are often necessary to apply
this technique to nanostructures with different designs. Recently, fast spin readout
within coherence times was realized in a gate-defined silicon QD with a RF single
electron transistor (RF-SET) charge sensor.[59]Physically defined silicon QDs (PD-QDs) based on the silicon-on-insulator (SOI)
technology[45–51, 84] would offer high flexibility in QD arrangement and suitability
to dense two-dimensional QD integration without the need of gates for quantum
confinement.[49] However, the PD-QD with the top gate structure is yet to be
successfully combined with the RF-SET, possibly because of formation of a RC
filter due to the reservoir of a resistive silicon channel and the capacitance of a
20-µm square top gate.[59, 103, 107, 108] One way to avoid this problem is tosimply reduce the size of the top gate.[59, 108] An alternative solution would be tocompletely remove the top gate structure, made possible thanks to the SOI-based
QD structures.[49, 109] In this work, we report a large phase response and a detailed
circuit analysis of RF-SET measurement in PD-QDs without the top gate structure.

6.2

Device fabrication and measurement setup

The PD-QD devices were fabricated in line with our previous studies.[49] In eachdevice, the top gate structure is omitted to avoid RF leakage to the top gate; instead,the back gate is used to accumulate electrons. A scanning electron micrograph(SEM) of a PD-QD nominally identical to the ones used in this work is shown in
Fig. 6.1. A charge sensor and side gates (SGs) are also formed in the same SOI
64

CHAPTER 6. RADIO-FREQUENCY SINGLE ELECTRON TRANSISTORSWITH A SENSITIVE PHASE RESPONSE
layer as the QDs. However, some of them are set to be floating and do not play arole in the following experiments. A positive back gate voltage is applied to the Si
substrate of the SOI wafer across the 145-nm thick buried oxide layer to accumulate
electrons. The device is mounted on a printed circuit board (PCB) along withcomponents for the bias tee and for the LC resonance circuit for RF-SET (Fig. 6.1).
Parasitic capacitances of the PCB and the device form part of the LC circuit. All
measurements in this paper are performed with devices immersed in liquid helium
and hence at 4.2 K. We use a vector network analyzer (VNA) and apply the RF
power output from port 1 of the VNA to the device after 60-dB attenuation. The
signal reflected at the device is input into port 2 of the VNA after amplificationof 35 dB. We note that the signal is amplified only at room temperature, not at
cryogenic temperature.

6.3

Frequency dependence and electrical circuit
analysis

We also perform fitting of frequency dependence of the RF-SET without additional parasitic components (Fig. 6.2). The equivalent circuit consisting of the inductance L, capacitance C, and conductance G is shown in Fig. 6.2(a). In Figs. 6.2(b)and (c), the amplitudes and the phases of the measured reflection coefficient areplotted, respectively, along with the simulated results. Here, the measurement results are the same as the ones in Fig. 6.3 in the main text. We fit the data without
introducing the additional parasitic components (red dotted lines in Figs. 6.2(b) and(c)). The results agree well with the measurement result; however, (the value of) L
used for the fitting is 2.36 µH which is 3.5 times larger than the nominal inductance.
This can be understood by the same mechanism as the self-resonance of the inductor
due to its parasitic capacitance. As the frequency approaches the self-resonance, theinductance increases until the inductor starts to behave like a capacitor above the65CHAPTER 6. RADIO-FREQUENCY SINGLE ELECTRON TRANSISTORSWITH A SENSITIVE PHASE RESPONSE

VNA
1

2

DC
block

DC
block
Amp.
35 dB

Att.
40 dB

at room temperature
at helium liquid temperature

BG

VGL1 VD

VGR1

𝐶b
𝑅b VS

VGL2

𝐿

100 nm𝐶p

Figure 6.1: Measurement setup with a scanning electron micrograph of a physicallydefined quantum dot (PD-QD) device nominally identical to the measured ones.
The PD-QDs do not have top gates. Drain voltage, VD , source voltage, VS , sidegate voltages, VGL1 , VGL2 , and VGR1 , and back gate voltage, VBG , can be applied.
Shadowed areas indicate unused floating electrodes: a side gate, a single QD charge
sensor, and a reservoir. An LC resonance circuit for impedance matching, which
comprises a surface mount wire-wound inductor with an inductance L = 680 nH
and parasitic capacitance Cp , is connected to the source of the QD. In addition, an
RC bias tee (Rb = 5 kΩ and Cb = 4.7 µF) is connected to the LC circuit in series
to apply a DC voltage VS . For RF measurement, a vector network analyzer (VNA)
outputs the RF signal from port 1, which is applied to the device after attenuation
to suppress heating up the QD. The signal reflected from the device is branched bydirectional coupler and input to port 2 of VNA after amplification.

66

CHAPTER 6. RADIO-FREQUENCY SINGLE ELECTRON TRANSISTORSWITH A SENSITIVE PHASE RESPONSE
resonance frequency. This result indicates the necessity of introducing the additional
parasitic components for the fitting.
For the completeness, we also simulate the characteristics with L fixed to thenominal value, 680 nH (green dotted lines in Figs. 6.2(b) and (c)). G and C are
estimated from the load impedance calculated from the reflection at the resonanceand from the resonance frequency. The result apparently deviates from the measurement data, also indicating requirements for additional parasitic components forthe fitting.

(a)𝐶

Phase (deg.)

Amp. (dB)

𝐺

𝐿

-25

-40

(b)

200

Frequency (MHz)250

0-300 (c)200250Frequency (MHz)Figure 6.2: An equivalent circuit without additional parasitic components for RF
reflectometry. (b,c) Amplitude and phase of the reflection coefficients as a functionof carrier frequency. Measurement results (blue solid line) which are also shownin Fig. 6.3 in the main text are fitted based on the equivalent circuit in (a) (reddotted line), yielding L = 2.36 µH, C = 214 fF, and G = 3.43 µS. Green dotted line
shows a simulation result for which L is fixed to its nominal value, 680 nH, while
the other parameters are obtained from the resonance frequency and the amplitude
of reflection coefficient at resonance: G = 40 µS and C = 740 fF.

67

CHAPTER 6. RADIO-FREQUENCY SINGLE ELECTRON TRANSISTORSWITH A SENSITIVE PHASE RESPONSE

6.4

Fitting with additional parasitic components

First, we study the frequency dependence of the reflection coefficient at thedevice, Γ, without carrier accumulation using the back gate voltage VBG = 0 V(blue solid lines in Fig. 6.3(a) and (b)). Here, the charge sensor and all SGs are set
to be floating for simplicity. A dip appears at a frequency which corresponds to
the resonance of the circuit (fr = 224.063 MHz). In a simple description of the LC
resonance circuit, the load impedance, Zload , is proportional to device conductanceat resonance; this would suggest that Zload should be close to zero in this case,which would result in almost complete reflection. This apparent discrepancy canbe explained by the dielectric loss in the PCB which contributes as a conductanceparallel to the device.[25] Given this, Zload has a finite value (at frequencies aroundthe resonance) and Γ = (Zload −Z0 )/(Zload +Z0 ) can approach zero, where Z0 = 50Ω
is the characteristic impedance of the external signal line.
As we will see below, the frequency dependence of observed reflection can be
described by the equivalent circuit shown in Fig. 6.3(c). The circuit mainly consistsof an inductance, L, a parasitic capacitance, Cp , and a QD impedance composedof a parallel circuit of a conductance GQD and a capacitance CQD ; however, eachcomponent has additional parasitic components in reality. Here, we take into account the parasitic capacitance and resistance in the coil, CL and RL , and theparasitic conductance in the capacitor, Gp . Gp and RL are due to dielectric loss andskin effect, respectively, so that each has a frequency dependence: Gp = ωCp tanδ√and RL = ρL ω, where ω = 2πf is the angular frequency, tanδ is loss tangent,and ρL denotes a coefficient.[110] In addition, the effects of external components are
considered, such as coaxial cables, attenuators, and amplifiers. Attenuation and amplification offset the amplitude of the reflected signal, and the coaxial cable causes
a linear phase shift as a function of frequency due to its propagation constant.
Figures 6.3(b) and (c) show fitting results for the amplitude and the phase of68CHAPTER 6. RADIO-FREQUENCY SINGLE ELECTRON TRANSISTORSWITH A SENSITIVE PHASE RESPONSE
the observed reflection at VBG = 0 V based on the equivalent circuit with followingqparameters (red dotted lines): L = 680 nH, ρL = 190 µΩ/ rad/s, CL = 348 fF,
Cp = 394 fF, and tanδ = 0.00614. Here, to reduce the number of fitting parameters,
the nominal value of L is assumed, and ρL is separately estimated from the measured transmission characteristic of an inductor nominally identical to the one usedin these measurements (supporting information). The fittings have good agreementswith the measurement results, proving the validity of the equivalent circuit model.
The small deviation at off-resonance frequencies can be attributed to a backgroundfrequency dependence due to interference between the reflected signal and the isolation leakage in the directional coupler.[110] The necessity for additional parasitic
components can be confirmed from fitting with a simple LCR circuit without taking
into account additional parasitic components, where an inductance 3.5 times larger
than L is required for a good fitting (see supporting information for details).

6.5

Estimation of parasitic components of theinductor at liquid helium temperature

To analyze the RF-SET characteristics, we obtain parasitic components of nominally the same inductor as used in the main text separately and in advance. Valuesof such parasitic components at room temperature are available in the datasheet of
the inductor, but they will change at cryogenic temperatures due, e.g., to a decreasein copper wire resistance and a change in the permeability of the core.
The inductor impedance including parasitic components, ZL , are extracted fromtransmission measurement at 4 K using a nominally identical inductor to that usedin the main text (LQW2BASR68J00L, Murata Electronics). To do this, we firstsolder the inductor on a PCB to make a transmission path through the inductor.
Next, we connect the PCB to a vector network analyzer (VNA) and then measure
the transmission from port 1 to port 2, S21 , with the inductor at helium liquid
69

-25

-40

(a)

200

(c)

250

Phase (deg.)

Amp. (dB)

CHAPTER 6. RADIO-FREQUENCY SINGLE ELECTRON TRANSISTORSWITH A SENSITIVE PHASE RESPONSE

0-300 (b)200

Frequency (MHz)

Quantum dot
device𝑌dev 𝐺QD
+
𝐺2D

𝐶QD
+
𝐶2D

250

Frequency (MHz)Parasitic
capacitance
𝐺p

𝐶p

Coil

𝐿

𝑅L
𝐶L

Figure 6.3: (a,b) Amplitude and phase of the measured transmission signal fromport 1 to port 2 at liquid helium temperature as a function of carrier frequency(blue solid lines). No DC voltages are applied to the device. Results from fitting
based on the equivalent circuit in (c) are shown as well (red dotted lines). (c) An
equivalent circuit for the load impedance, in which additional parasitic components
are also taken into account.
temperature (blue solid lines in Figs. 6.4(b) and (c)). As expected, |S21 | shows a dip
corresponding to self-resonance due to parasitic capacitance of the inductor.
To fit the results, S21 is formulated as follows. The voltage at each point in
Fig. 6.4(a) can be described by:

V A = Vi + Vr

(6.1)

VB = (1 + ΓB )Vi e−iβl(6.2)

VC = VB Z0 /(ZL + Z0 )(6.3)

VD = VC e−iβl

′

(6.4)

where Vi and Vr are incident and reflected voltages at point A, ΓB = ZL /(ZL +70

CHAPTER 6. RADIO-FREQUENCY SINGLE ELECTRON TRANSISTORSWITH A SENSITIVE PHASE RESPONSE
2Z0 ) is the reflection coefficient at point B seen from left-hand side, Z0 = 50 Ω isthe characteristic impedance, l(l′ ) is the length of the coaxial cable between points
A and B (C and D), and β is the propagation constant without attenuation of thecoaxial cables which is proportional to carrier frequency. In addition, it is assumed
that reflection at each VNA port does not occur thanks to impedance matching.
Thereby, the transmission coefficient S21 is′S21 = VD /Vi = 2Z0 /(ZL + 2Z0 )e−iβ(l+l ) .

(6.5)

Using this equation, we perform a fitting with ZL including the parasitic capac√
itance CL and resistance RL = ρL ω. In Figs. 6.4(b) and (c), the fitting results
are shown, which agree well with the measurements (red dotted lines). Here, theinductance is fixed to the nominal value of the inductor. From the fitting, followingqparameters are obtained: CL = 0.30 pF, and ρL = 190µΩ/ rad/s. The estimatedvalue of ρL is utilized for the fitting in the main text while that of CL is not because
it depends on soldering condition.
At frequencies higher than the self-resonance frequency, a deviation from thefitting in the transmission appears, which may be attributed to other parasitic
components such as the inductance of bonding wires. Here, their contributions are
ignored because they are effective outside the frequency range used in the main text.

6.6

Back gate voltage sweeping

Next, we investigate the reflection dependence on back gate voltage, VBG , at aconstant frequency, f = 223.464 MHz which corresponds to the resonance frequency
at VBG = 5.4 V. Figures 6.5(a) and (b) show the DC QD current, IQD , and theamplitude of Γ, |Γ|, as a function of VBG . Hereafter, the amplitude and the phase ofΓ as a function of a gate voltage are corrected in a similar manner described aboveby taking into account the external components. The QD device can also have par-71

|𝑆21 | (dB)

VNA port 1

𝑍0 A

-20
-40
-60 (b)
200

𝑙

B

Coil
𝑅L 𝐿
𝐶L

𝑍𝐿

Phase (deg.)

(a)

100

400
Frequency (MHz)

C

𝑙′

D
𝑍0

VNA port 2

CHAPTER 6. RADIO-FREQUENCY SINGLE ELECTRON TRANSISTORSWITH A SENSITIVE PHASE RESPONSE

(c)

0
-100
200

400
Frequency (MHz)Figure 6.4: (a) An equivalent circuit for transmission measurement of an inductor
at helium liquid temperature. Parasitic components in the PCB are ignored becauseof their large impedance compared to characteristic impedance Z0 = 50 Ω. Transmission through the inductor with L = 680 nH was measured using vector network
analyzer. (b,c) Amplitude and phase of the transmission through the inductor as afunction of carrier frequency. Measurement results (blue solid lines) are fitted withan equation from the equivalent circuit model (red dotted lines).
asitic components such as gate capacitance, C2D , and its dielectric loss, G2D . We
derive the device admittance, Ydev = Gdev + iωCdev , where Gdev = GQD + G2D and
Cdev = CQD + C2D , from the VBG dependence by subtracting impedances of inductance and parasitic capacitance together with their additional parasitic components(Figs. 6.5(c) and (d)). As seen in Fig. 6.5(c), Cdev qualitatively agrees with a resultin standard CV measurements of MOS capacitors,[104] which is reasonable because
the only difference is the direction of signal: from gate to semiconductor (CV measurement of MOS capacitors) or from semiconductor to gate (RF reflectometry of
QDs). The peak in Gdev around VBG = 2.5 V is also similar to the one for CV
measurements which can be explained by the effect of dielectric loss related to oxide(Fig. 6.5(d)).[111–113] In addition to being useful for establishing a detailed device
model, understanding this in-situ tunability can potentially provide an on-chip implementation of gate-tunable reflectometry circuits previously achieved via external

72

CHAPTER 6. RADIO-FREQUENCY SINGLE ELECTRON TRANSISTORSWITH A SENSITIVE PHASE RESPONSE
components such as varactors.[114–116] At higher voltages, oscillations appear in|Γ|, corresponding to Coulomb peaks in IQD , which implies the successful realization-10

𝐶dev (fF)

6

-15
-20

-25 (a)0.4(b)𝐺dev (S)

𝐼QD (nA)|Γ| (dB)of RF-SET.

0.2

0.0
0

1

2

3

4

5

(c)

4
2
0
3

(d)

0

0

𝑉BG (V)

1

2

3

4

5

𝑉BG (V)

Figure 6.5: (a,b) Amplitude of the reflection coefficient, |Γ|, and QD current,
IQD , as a function of VBG at liquid helium temperature. Carrier frequency f =223.464 MHz, VDS = 5 mV. VGL1 , VGL2 , and VGR1 are floating. As VBG is increased,a large dip appears in |Γ| around VBG = 2.5 V, implying electron accumulation in
the reservoir. At VBG higher than 4 V, several small dips appear in the amplitude,
corresponding to Coulomb peaks seen in (b). (c,d) Extracted device capacitance Cdev
and conductance Gdev as a function of VBG . These are obtained by subtracting theinductor and capacitance impedances with parasitic components from the measured
load impedance.

6.7

Side gate voltage sweeping

We can expect the conductance sensitivity to further increase, when a SG voltage
is swept instead of a back gate to suppress these changes in the device admittance
related to the turn-on process. To perform such an experiment, we use another QD
device with a nominally identical design and set the charge sensor and one of the side
gates to be floating to avoid unintended RF paths. The measured RF reflectometry73CHAPTER 6. RADIO-FREQUENCY SINGLE ELECTRON TRANSISTORSWITH A SENSITIVE PHASE RESPONSE
signals as a function of a SG voltage, VGR1 are shown in Figs. 6.6(a) and (b). We findthat peaks (dips) in amplitude (phase) of Γ nicely reproduce the Coulomb peaks of
IQD in Fig. 6.6(c). Strikingly, the observed phase shift (∼ 45 deg.) is significantly
larger than those observed in other RF-SETs.[117, 105]To understand the origin of the large phase shifts, we simulate the VGR1 dependence of the reflected signal. In Fig. 6.6(d), the simulation results are plotted ina Smith chart (orange dotted circle and purple dashed circles) together with the
VGR1 dependence (blue solid line). For the one shown by the purple dashed circle,
GQD is set to be higher than for the other one represented by the orange dotted
circle by 3.7 µS, in order to approximately simulate the Coulomb peak conductance,with the other parameters obtained by fitting the frequency dependence. Bothsimulation results show constant resistance circles as expected from the equivalentcircuit in Fig. 6.3(c). Remarkably, the orange one passes through almost the center of the Smith chart, meaning that the load impedance at resonance is closely
matched to Z0 . The results at given frequencies are indicated by the red triangles(223.464 MHz) and the green dots (224.157 MHz) in the Smith chart: the red ones
are for the frequency used in the measurement (223.464 MHz) and the green ones
for the resonance frequency for the orange circle condition (224.157 MHz). As expected, the red triangles agree with the VGR1 dependence experimentally observed.
We also calculate the frequency dependence of the phase difference ∆φ expected
for the same (3.7 µS) conductance change in Fig. 6.6(e), with a red triangle and agreen dot highlighting the same two frequencies as in Fig. 6.6(d). It turns out that
there are two maximums in the absolute value of ∆φ. We note that the resonancefrequency (marked by the green dot) is located in between the two maximum points
and has a small phase shift (∼ 2 deg.). On the other hand, the frequency used in
the measurement (the red triangle) is located close to one of the maximums, andthe large phase shift (∼ 45 deg.) agrees excellently with data. This large phase shift
will not occur if the load impedance at resonance is away from impedance match74

CHAPTER 6. RADIO-FREQUENCY SINGLE ELECTRON TRANSISTORSWITH A SENSITIVE PHASE RESPONSE
ing, where larger or smaller constant resistance circles would appear. Therefore, we
conclude that a good impedance matching and a small frequency detuning from theresonance frequency are the necessary ingredients for the large phase shift caused by
Coulomb oscillations. We note that this large phase shift is caused by a conductancechange, rather than a change in quantum or tunnel capacitances, for which muchsmaller phase shifts are typically reported (e.g. Refs. 117 and 105). Observation ofreflectometry phase shift due to a conductance change is scarce. However, in theory, the phase change can be as large as 180 degree when the system passes exactly
across the matching condition. To the best of our knowledge, our result is one of
the closest to this ideal situation in the literature.

6.8

Summary

RF reflectometry is a promising method for fast spin readouts. Understanding of
RF-reflectometry circuits is important to adopt this technique to various nanostructures. In this chapter, we have performed RF-SET using PD-QDs without the top
gate structure, and, based on an equivalent circuit for load impedance, the parasitic
circuit parameters are estimated from the frequency dependence of RF reflection
coefficient. Our method will be useful when one needs to modify the RF reflectometry technique to apply to new device structures. Furthermore, we find huge phaseshifts corresponding to Coulomb peaks (∼ 45 deg.), as a result of the combinationof a good impedance matching and a detuning from resonance frequency. The large
signals will be useful to charge sensing by combining them with a cryogenic amplifier
and/or a strong CS-QD coupling. Assuming a strong CS-QD coupling such that acharge transition in the target QD causes a shift of a CS Coulomb peak by a half
width of the peak, a 100-kHz spin readout will be possible as expected from thephase response in Fig. 6.6(b). The large phase shifts are confirmed by simulation
using the equivalent circuit model. We believe that our results will be helpful in designing reflectometry circuits through simulation in order to improve the sensitivity
75

|Γ| (dB)

80

(d)

(a)

-25

40

2

(b)
Δ𝜑 (deg.)

𝐼QD (nA)-20

𝜑 (deg.)CHAPTER 6. RADIO-FREQUENCY SINGLE ELECTRON TRANSISTORSWITH A SENSITIVE PHASE RESPONSE

(c)

0
-3

𝑉GR1 (V)040 (e)

0
-40
200

250

Frequency (MHz)Figure 6.6: (a-c) Amplitude and phase of Γ = |Γ|eiφ , and IQD as a function of
SG voltage, VGR1 , at liquid helium temperature. VBG = 6 V, VDS = 1 mV, VGL1 =VGL2 = 0 V, and f = 224.3 MHz. IF bandwidth is 100 kHz. (d) Smith chart
for the Γ dependence together with frequency dependences of simulated reflection
coefficient using the equivalent circuit in Fig. 6.3(c) (orange dottedq circle and purple
dashed circle). For the simulations, L = 680 nH, ρL = 190µΩ/ rad/s, CL = 350 fF,
Cp + Cdev = 391 fF, and tanδ = 0.00614. Gdev is set to be 4.73 µS for the orange
circle and 8.43 µS for the purple circle. Red triangles (green dots) indicate Γ at f =223.464 MHz (224.157 MHz). Red triangles qualitatively reproduce the Γ change
by Coulomb peaks. (e) Frequency dependence of phase difference between the two
device conductance values, ∆φ. A red triangle and a green dot correspond to thetwo frequency values used in (d).
and speed of spin qubit readout.

76

Chapter 7
Conclusions
7.1

Summary

In this PhD thesis, we have presented experimental research on LTQD and
TTQD and development of charge sensing techniques. Integration of QDs is essential for large-scale spin qubit systems. A TTQD structure can be regarded as
the minimum unit cell for dense two-dimensional integration.[118] In the first partof this thesis, we focused on the fabrication of TQDs. Although the basic techniques
had already been developed previously, it was still necessary to optimize quantum
dot designs. We developed designs for linear and triangular TQDs by repeating
EBL test and SEM observation for different patterns. Especially, the hole at thecenter of TTQD is difficult to make and therefore, the realization of working devices
took time. The potential barrier of the center hole may be a difficult part of device
fabrication also in other QD systems, and that is possibly why only a few studies for
TTQDs have been reported. Our fabricated devices were evaluated from currents
through them and charge sensors at helium temperature. Both structures are confirmed to have three quantum dots as expected. In addition, tunnel couplings in the
TTQD structure were successfully confirmed from two- and three-QD transports.
We demonstrated that the sharp quantum confinement by physical etching, which

77CHAPTER 7. CONCLUSIONS
is difficult for gate-defined devices because of QD confinements by electric fields,
may be the key ingredient in expanded two-dimensional QD array.
Charge sensing is also essential part of spin qubit systems. Spin states can beread out by charge sensors via spin-to-charge conversion techniques. To achieve
qubit readout within a coherence time, a fast charge readout in single-shot manneris desired. We tried the single-shot charge sensing with TTQD structure. Unlike charge sensing with DC current, the single-shot measurements requires a large
enough bandwidth to pass fast signals and also high-frequency noises inevitably.
The simple way to remove noise with wide bandwidth is to remove the origin ofnoise. To do this, we mainly worked on breaking ground loops, one main source ofnoise, by trying cutting ground connection point by point. Moreover, we also madesignificant efforts to make programs to control measurement equipment such as arbitrary waveform generator and oscilloscope. In the measurements, we repeatedly
applied voltage pulse sequences to a gate such that only a single electron tunnels
out of the target QD in each sequence. In the result, we observed step signals in CS
current corresponding to the tunnel events; however, the SNR was too low to detect
the step by simply thresholding. We then applied a statistics theory using LLR andconfirmed the capability of detecting the step position, or in other words, precise
charge sensing. This work demonstrated the importance of numerical treatmentsfor quantum information field.
In order to reduce noise, we also attempted a homodyne measurement technique called RF reflectometry, which utilizes RF signal (∼ 200 MHz) to avoid lowfrequency noise like 1/f noise. The RF-SET results of this thesis are the firstsuccessful observations of RF reflectometry in PD-QD devices after years of development in our group. While the exact mechanism remains unknown, this may be
attributed to top gate structure which can make RC low-pass filter for the channelof SOI layer. Based on this idea, we tried PD-QDs without top gate structuresand confirmed that it worked out expectedly. In the measurements reflected RF
78

CHAPTER 7. CONCLUSIONS
signals were monitored as functions of gate voltages, and it was confirmed thatpeak-like conductance characteristics of QDs were reflected in the RF signals. The
signals showed large phase shifts, reproduced by simulation with equivalent circuit
including parasitic components. We believe that the analysis is useful for design ofreflectometry circuits.
These readout techniques, numerical treatment and RF reflectometry, can be
combined to further improve the charge sensing. In addition, the SNR for RF
reflectometry whose can be easily improved by a factor of 6 by using cryogenic
amplifier. A tunnel coupling between a CS and its target QD will also improve the
SNR. We anticipate that careful device designs and optimized setups enable spin
readout even for a dense QD structures like TTQDs.

7.2

Perspective

Before we conclude, we would like to discuss the possible prospects of my research work. This work showed a unit structure for dense two-dimensional QD arrayas described in Ch. 4, whose structure is expandable to a rectangle QD array. The
rectangle array is suitable to the well-known fault-tolerant scheme,[2] possibly witha dynamic random-access memory (DRAM) architecture.[28] In another scenario,
the TTQD structure can be directly expanded because the TTQD lattice may be
more powerful as a two-dimensional array unit than rectangle QD arrangement.
For example, the TTQD structure can be a unit for another fault-tolerant scheme
possibly facilitating decoherence error thresholds.[118] In any case, QD structure
itself can easily be expanded even though the in-plane gate structures have to be
replaced with out-of-plane ones by three-dimensional wiring. Figure 7.1 shows anexample of such a structure. There is a two-dimensional QD array with two typesof out-of-plane gates which control QD potentials and QD-QD tunnel couplings,
respectively. By applying microwave and RF signals to the former gates, it is possible to control single-qubit states and read out the qubits, respectively. The digital
79CHAPTER 7. CONCLUSIONS

Figure 7.1: A two-dimensional
QD array based on TTQD structure with out-of-plane gates. Yellow cylinders correspond to gatesto control each qubit potential,
and blue prisms correspond to
gates to control two-qubit couplings.

signal processing technique in Ch. 5 and the equivalent circuit analysis described in
Ch. 6 will be useful to make the gate-based readout highly sensitive to qubit states.
The other type of gates is used for two-qubit gates by tuning tunnel couplings. We
confirmed the existence of tunneling couplings in our two-dimensional QD array as
explained in Ch. 4, which are partly defined by physical confinements. The combination of such physical confinements and out-of-plane gates may lead to a good
ON/OFF ratio in the couplings. Recently, Hughes Research Laboratories group, in
USA, has fabricated silicon spin qubits by using standard CMOS fabrication techniques, where out-of-plane gate structures are formed.[119] This structure may befurther extended by stacking multi-layers to fan out gates.
Another possibility is replacement of silicon with other materials where the effective mass of charges are lower than ones in silicon, which facilitates qubit integration.
Germanium which comprises 92.3 % spinless isotopes is one of such materials whereholes in germanium has lighter effective mass than charges in silicon and also strong
spin-orbit interaction useful for fast spin manipulation. In these days, it has been
demonstrated that the advantages result in single-qubit operations[100] and fast
two-qubit operations with high fidelity.[120] Recently, a four-qubit system in germanium QDs was reported.[121] The fast progress in germanium spin qubit lets us
envision realization of large-scaled spin qubit system in the near future.

80

CHAPTER 7. CONCLUSIONS
Turning to the charge sensing techniques in this thesis, we believe that they works
irrespectively of device structure. The LLR may be useful for fast measurementwith wide bandwidth where signal-to-noise ratio becomes lower. The LLR enablesprecise step detection but takes wait time until a set of data points is acquired
as well as calculation time. Segmentation of measurement data points can makethe technique more “real-time” at the expense of detection preciseness. In anotherway, field-programmable gate array (FPGA) can enable fast calculation, benefitingfrom its real-time and parallel processing. By FPGA, the LLR technique may evenbe performed within several clocks corresponding to several tens of nanoseconds
with 100 MHz clock. The calculation time is ignorable compared to the single
measurement time (40 ms), so that the combination of FPGA and the segmentation
may realize a “real-time” detection.
The findings from the RF reflectometry results can be applicable to other systems. In the results, we have considered a parasitic capacitance of the inductorin the RF reflectometry circuit. The capacitance is typically neglected in previous
reflectometry studies but can significantly modify the effective inductance due toits self-resonance effect. We have also confirmed that RF leakage from one electrode to the other affects the sensitivity of RF signal. Removing top gate structureleads to successful RF reflectometry, and further improvement will be possible. As
mentioned in Ch. 6, a CS and a side gate adjacent to QD have been set to be floating because of RF leakages, indicating capacitive couplings of the electrodes to the
RF channel. Suppression of the couplings may enable further large signal in RFreflectometry.[122] Actually, by increasing the gap between electrodes, charge sensing by an RF-SET with PD-QD structure has been performed. In addition, these
PD-QDs have TGs with reduced areas, therefore enabling RF reflectometry with agood controllability as before.
In closing, we conclude this PhD work.

In this work, we realized a two-

dimensional QD array expandable to the one like the integrated QD structure in81CHAPTER 7. CONCLUSIONS
Fig. 7.1 (red circles) and also developed readout techniques which can be applied
to gate sensing, for example, using local gates in Fig. 7.1. Expansion of the TTQD
structure to a large two-dimensional QD array is promising for quantum information
processing. Aiming toward this, a lot of improvements are required. We are now
in the first step toward quantum computer based on PD-QDs. In this thesis, wedeveloped readout techniques for an expandable qubit system. The techniques arefrom software and hardware aspects and therefore, complementary to each other,hopefully enabling fast spin readout by combination with spin-to-charge conversion.
In another study, spin operation in a p-type PD-QD succeeded. Merging thesetechniques to establish a spin qubit is the short-term next step for PD-QD based
qubits.

82

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Acknowledgements
First of all, I would like to thank Associate prof. Tetsuo Kodera for supervising
my PhD thesis. He has been my mentor since I was a bachelor student. He always
guided me to the correct direction. I would also like to express my gratitude toEmeritus Prof. Shunri Oda for his supervision. Since my bachelor thesis which hesupervised, he has always encouraged me. I thank him also for joining the committeeof this thesis.
My deepest appreciations go to Prof. Mutsuko Hatano, Prof. Yasuyuki
Miyamoto, Prof. Hitoshi Wakabayashi, Associate Prof. Safumi Suzuki, AssociateProf. Yukio Kawano, and Associate Prof. Masaharu Kobayashi for examining thisthesis.
I thank Prof. Toshiro Hiramoto for his kindness that his group deposited SiO2
with LPCVD for our devices. I am also grateful to Prof. Yasuhiko Arakawa for
his generous permission to use the cryostat, which was indispensable to realize thepresent thesis.
I owe a very important debt to Project Associate Prof. Jun Yoneda. His insightful
and inspiring comments and suggestions helped me a lot.
I want to thank Dr. Tomohiro Kambara and Dr. Kousuke Horibe from whom I
took over the device fabrication techniques and the measurement methods during
my bachelor and master theses. As for the device fabrication, I am also indebted to
Dr. Koichi Usami for his support.
Special thanks to Dr. Tomohiro Noguchi, Dr. Daichi Suzuki, Jun Kamioka,100

CHAPTER 7. CONCLUSIONS
Nobuhiro Kondo, Ko Yamada, and Takayoshi Kuga, with whom I worked when
I was a student in Oda lab. The time I spent with them and the discussion we had
has always been valuable, intellectually and mentally.
I also thank the other ex- and present lab members. Especially, I am deeply
grateful to Mizuki Kobayashi, Masahiro Tadokoro, and Masaru Hirayama for fruitful
discussions.
Last but not least, I thank my family for supporting me during the years.

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Publications
Scientific articles relating to this PhD thesis
1. R. Mizokuchi, S. Oda, T. Kodera,“Physically defined triple quantum dot systems in silicon on insulator,”
Applied Physics Letters 114, 073104 (2019).
2. R. Mizokuchi, M. Tadokoro, T. Kodera,“Detection of tunneling events in physically defined silicon quantum dot using
single-shot measurements improved by numerical treatments,”
Applied Physics Express 13, 121004 (2020).
3. R. Mizokuchi, S. Bugu, M. Hirayama, J. Yoneda, and T. Kodera“Radio-frequency single electron transistors in physically defined silicon quantum dots with a sensitive phase response,”
Scientific Reports 11, 5863 (2021).

Scientific articles before this PhD
1. R. Mizokuchi, P. Torresani, R. Maurand, Z. Zeng, Y.-M. Niquet, M. Myronov,
S. De Franceschi,“Hole weak anti-localization in a strained-Ge surface quantum well.”Applied Physics Letters 111, 063102 (2017).

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CHAPTER 7. CONCLUSIONS
2. R. Mizokuchi, R. Maurand, F. Vigneau, M. Myronov, S. De Franceschi,“Ballistic One-Dimensional Holes with Strong g - Factor Anisotropy in Germanium.”
Nano Letters 18, 4861 (2018).

Co-authored scientific articles
1. F. Vigneau, R. Mizokuchi, D. C. Zanuz, X. Huang, S. Tan, R. Maurand, S.
Frolov, A. Sammak, G. Scappucci, F. Lefloch, and S. De Franceschi“Germanium Quantum-Well Josephson Field-Effect Transistors and Interferometers,”
Nano Letters 19, 1023 (2019)
2. N. Lee, R. Tsuchiya, G. Shinkai, Y. Kanno, T. Mine, T. Takahama,
R. Mizokuchi, T. Kodera, D. Hisamoto, and H. Mizuno,“Enhancing electrostatic coupling in silicon quantum dot array by dual gate
oxide thickness for large-scale integration,”
Applied Physics Letters 116, 162106 (2020).
3. M. Tadokoro, R. Mizokuchi, and T. KODERA,“Pauli spin blockade in a silicon triangular triple quantum dot,”
Japanese Journal of Applied Physics 59, SGGI01 (2020).
4. H. Wei, S. Mizoguchi, R. Mizokuchi, and T. Kodera,“Estimation of hole spin g-factors in p-channel silicon single and double quantum dots towards spin manipulation,”
Japanese Journal of Applied Physics 59, SGGI10 (2020).
5. 米田 淳,

溝口

来成,

小寺

哲夫,

“シリコン量子ドット単一キャリアスピンの高周波反射計測,”
固体物理 56, 265 (2021).
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CHAPTER 7. CONCLUSIONSInternational conference presentations
1. R. Mizokuchi, T. Kodera, K. Horibe, Y. Kawano, and S. Oda“Charge sensing of a Si triple quantum dot system using single electron transistors,”
IEEE Silicon Nanoelectronics Workshop, June 2012, Honolulu (poster)
2. R. Mizokuchi, T. Kodera, K. Horibe, Y. Kawano, Y. Arakawa, and S. Oda“Observation of electron transitions in triple quantum dot by using charge
sensor,”IEEE EDS WIMNACT-37, February 2013, Tokyo (poster)
3. R. Mizokuchi, T. Kodera, K. Horibe and S. Oda"Perpendicular magnetic field dependence of triangular triple silicon quantum
dot system,"2014 Silicon Nanoelectronics Workshop, June 2014, Honolulu (poster)
4. R. Mizokuchi, S. Bugu, M. Hirayama, M. Tadokoro, and T. Kodera”RF reflectometry on physically defined triangular triple quantum dot,”
Topical Conference on Quantum Computing 2019, December 2019, Kyoto(poster)
5. R. Mizokuchi, M. Hirayama, S. Nishiyama, K. Kato, Y. Liu, S. Murakami, T.
Mori, J. Yoneda, T. Kodera”Equivalent Circuit Analysis of RF Reflectometry of Physically Defined Quantum Dot Systems,”
Joint Conference EP2DS-24/MSS-20, November 2021, Online (oral)

104