SHF Communication Technologies AGWilhelm-von-Siemens-Str. 23 • Aufgang D • 12277 Berlin – Marienfelde • Germany
Phone ++49 30 / 772 05 10 • Fax ++49 30 / 753 10 78
E-Mail: sales@shf.biz • Web: http://www.shf.biz

Datasheet
SHF 5002 A
60 Gbps 1:4 Demultiplexer

Description
The SHF 5002 A demultiplexer extracts four output data streams from a 60 GBit/s input signal at arate of a quarter of the input signal data rate.
All features of the demultiplexer are controlled by push button using a menu system on the frontpanel. The half clock (1/4 Bit rate) output allows perfect sychronization of a 15 GBit/s error
analyzer to the individual four output signals.
A high output signal level of over 2.5 Vamp allows resistive splitting, leaving enough signal to drive
multiple digital circuits. Very high sensitivity and a clock phase margin of more than 200° makethis instrument suitable for measurements of the highest precision.
The SHF 5002 A demultiplexer is a result of SHFs many years experience in the development andproduction of ultra high speed components and their assembly to more complex systems.

Features••
••••
•
•••

High amplitude data output @ 15 GBit/s
Ruggedized 1.85 mm male input connectors for data input
External master clock input at half of the bitrate
Clock output at half the input frequency
High precision computer controlled delay line to adjust the clock phase
External GPIB control
Very high sensitivity
Large angle clock phase margin
Wide band operation up to more than 60 GBit/s
High amplitude data output @ 15 GBit/sOption•Option DS: Internal 4:1 data selector – allows each output signal to be selected and sent to asingle output.

Functional Block Diagram

Data

Data

SHF 100AP
Amplifier

Data ASHF 100AP
Amplifier

Data BSHF 100AP
Amplifier

Data CSHF 100AP
Amplifier

Data DSHF
Amplifier

Clock/2

Data A
Data BSHF 1:4
DEMUX
Clock

Delay 0 ... 160ps

Clock

Data C
Data D
Clock/2

SHF reserves the right to change specifications and design without notice - SHF 5002 A – Rev. 2.0 – 16/DEC/2002

Page 2/6

Specifications
Parameter
Clock input

Unit

Min.

Typ.

Max.

1AC coupled

Frequency range

GHzS11dB

Input level

Vpp

0.40.8Clock delay rangeps0160

Max. AC input

Conditions

130

half bit rate

-10

V pp (dBm)

in 1ps steps

1 (4)Data inputs 2

AC coupled

Bit rate

Gbps

260

S11dB-10

Sensitivity

mV

60
100

Clock phase margin°

Max. AC input

Vpp

1Max. DC input

V pp (dBm)

1 (4)

200
150

<0.1 Vpp<50 Gbps<60 Gbps<50 Gbps<60 Gbps
see page 4

Clock output 1

AC coupled

Output level

Vpp

S22

dB

0.4

0.8-10Electrical data outputs 3

AC coupled

Frequency range

GHz

0.5

Output level

Vamp

1.5

Rise/fall time

psPower supplyVPower consumption

W100Weightkg

15Dimensions (WxHxD)

mmOperating temperature°C

90
180

1521102302.5
3020%...80%

13527047…63 Hz

472x110x365
10Storage temperature°C-20
150 Ω ruggedized 2.9 mm precision female connector.
250 Ω ruggedized 1.85 mm precision male connector
350 Ω SMA female connector

3570

SHF reserves the right to change specifications and design without notice - SHF 5002 A – Rev. 2.0 – 16/DEC/2002

Page 3/6

Output Waveforms
Clock Phase Margin Measurement
BER Limit 10-9, PRBS 231-1, Eye Height 100 mV, Input Data Jitter1 5 pspp
Input Signal provided by SHF BPG 44350300250200Specification limit

150100500010203040506070

Subrate output at 10 GBit/s from a 40 GBit/s 100 mV input signal

SHF reserves the right to change specifications and design without notice - SHF 5002 A – Rev. 2.0 – 16/DEC/2002

Page 4/6

Subrate output at 12.5 GBit/s from a 50 GBit/s 100 mV input signal

Subrate output at 15 GBit/s from a 60 GBit/s 100 mV input signal

SHF reserves the right to change specifications and design without notice - SHF 5002 A – Rev. 2.0 – 16/DEC/2002

Page 5/6

Clock outputs

10 GHz12.5 GHz

15 GHzSHF reserves the right to change specifications and design without notice - SHF 5002 A – Rev. 2.0 – 16/DEC/2002

Page 6/6