linear gradicnt crror in thc E)AC.This correspOnds to a lllldrange
crror of O.4シ6 Finitc(54dB)1)C gain br all opamps and ran‐dody mdsmatchcd capacitors(珈ith O.1%standal・d de宙ation)、vere
assullled in all circuits.OSR=4 wasuscd A O.45V pcak midband
two‐tonc input signal″l was applied to DSl,and a sccond‐ordcr
single―bit ΔΣ ADC Кaliscd D島.TO dCmonstratc the high linea五け
achicvablc、vith thc proposcd correction,DSl was clnbcddcd in a2‐
O MASH containing a 10 bit ADC asits sccond Stagc.The lllls―
match bctwccn thc MASII stagcs、
vas not considered;it can also
bc corrected by dijtal mcthods[9]Ｅ コ﹂ ０００ ０ ヨ０ う０︵０２ざ９ｏう ｏｏ︺︵ ｏｃ つｏも ｏＬ ｏ●︶

Ｅ Ｄ﹂︶
００この ヨ０ つ０．
６ｏもｏ﹂
ｂま ３．

Ｅ ョＬ● Ｏα ∽ う０︶うＯ３︶︵０く０罵ｏＥ っＬ０ ００∽ ︺ぅ０デコ０

BAIRD,RT, and FIEZ,TS: ̀A lo、v oversampling ratio 14‑b delta―
sigma ADC with selicalibrated multibit DAC',■EEE工Sο ′′グーsrα′ac″ ε j′s, 1996,31,(3),pp 312‑320
PETRIE,C, andヽ
41LLER,M: ̀A background calibration tcchniquc
for multibit delta― sigma modulators' Proc IEEE Int Symp
Circuits and Systcms,2000,pp I1 29‑I132
BAIRD,RT, and FIEZ.TS: ̀Improved delta―sitta I)AC linearity
using data weighted averaging' PrOc IEEE Int Symp Circuits
and Systcms, 1995,pp 113‑116
GALTON,I: ̀Noise― shaping ヽD/A converters for sigma―
delta
modulation' Proc IEEE Int Symp Circuits and Systcms, 1996,
pp 441‑444
KWAN.T,ADAMS,R,and LIBERT、R:̀A sterco multibit sigma― dclta
D A C w i t h a s y n c h r o n o u s m a s t e r ― c l o c k i n t e r f a c e ' E, E■E 工S ο′′″―Srα′′Cr7̀ ′お, 1996,31,(12),pp 1881‑1887
M00N,U,SILVA,J,STEENSGAARD,J,and TEMES,GC:̀A switched―capacitor DAC with analoguc mismatch corrcction', Elec′″ο″L′′
̀,
1999,35,(22),pp
1903‑1904
FOGLEMAN.E, GALTON,1, HUFF,W, and JENSEN,H: ̀A 33‑V
poly CMOS audio AI)C dclta‐
singlc‐sigma modulator with 98‐dBpeak SINAD and 105‑dB peak SFDR',■EEE工Sο ′′″―S′α′ιCirr′J̀s,2000,35,(3),pp 297‑307
KISS,P,SILVA,J,WIESBAUER,A,SUN,T,M00N,U,and TEMES,GC:̀ A d a p t 市e c o r r e c t i o n o f a n a l o g e r r o r s i n M A S H A D C s P a r t I I

５Corrcction using tcst‐
signal illJcction',■EEE「 /α″s Cirι″″s sysr〃f И″α/ a g D な′′S な″αノP ″ο ss,2000,47,(7),pp 629‑638
norma‖sed frequency lf/fs]
d77612

norma‖ sed frequency lf/fsI

g6イ′″″
α ″yにο
×′
グ
ンJ″
αピ彎′
グ
FFA″″,bλβ
用協:sギ げαForideal DAC
わFor nonlinear DAC without correction
ιFor nonlincar DAC with proposed correction
グヽVith corrcction,but using ttLス =)=‑1

Reconfigurable phase… locked ioops on FPGAutiiising intrinsic synchronisabi:ity‑― ―Jら=/ノ 8,inband limit for OSR=4

H.Tanaka,A.Hascgawa and S.Haruyama

ne computcd spcctrum of thc systeln operating with an idcal
DAC but with nonideal opamps and capacitors(desc五bed above)is shown in Fig. 力 .Fig. 2ι sho、vs thc spcctrum using thc nonlin―
ear DAC without crror corα 3tion.Large hannonics arc gcncratcd
and thc spur―free dynamc rangc(SFDR)is ottly 52dB Fig 2̀
shows thc rcsult whcn using the digltal corrcction dcsc五
bed in thisLcttcr:an SFDR> 100dB was achicvcd.To obtain suf「ldcntlya∝untc cstllnatcs of′D nccdcd for such a higll SFDR,D&prOC―
csscd 218 samplcs for cach lcvcl of thc DAC(a complctc back‐ground calibration cycle then nccds about 4s if D52 iS C10ckcd
Withノζ=5MHz)Finally,Fig 2 shows the detimcntal cffcct ofusing力 Zflz)=‑1(aS Car五 cd out in carlier work[1,3]),thC drOp
in thc SFDR bcing from 101 to 60dB
Gο776Ms′ο″s An on― linc digital corrcction method was proposcd
for ΔΣ AE》Cs with multibit intcmal quantiscrs lt is applicablecvcn for ADCs with vew low ovcrSampling ratios,where the com‐monly used nlismatch‐ shaping tcchniques bccomc lcss cffcc・tive.
Sinlulations indicate that cxccllcnt lincanty can be obtaincd using
the proposcd proccss.

Anぃ v di」
tal phase̲locked loop(PLL),utiliSing thesynchronisability of electHcal oscillators,onprogranlmablea flcld‐
gate anay has been developed By interconnecting such PLLs,adynanlicaly reconflgurable clock network was fonncd,whcll has
bccn diFlcult nith conventional PLL tcЮ
hniques177″οttα わ″ Digltal LSIs havc gcncnlly bccn based on a syncllro―nous scheme in whlch a global clock slgllal is dist五 butcd through‐out thc chip Howcvcr, circuit sレc and clock frequencies arc
increasing, therefore it is harder to distributc thc clock signal(hCrCaftcr̀thc clock')within an allowablc phasc delay Asynchro―nous circuit dcsign or locally synchronous circuits is a rcasonablc
way to avoid this difflculty.Clock net、 vorks ushg dist五 butcd volt―
agc―controled osc11lators[1, 2]can alSO bC uscd. In contrast tolockcd loop
thcsc dcsigns,wc havc dcvclopcd a newtal di」
phasc‐(PLL)whn waS tested on a icld‐
progranlmable gate array(FPGA).ThiS PLL utiliscs intHnsic sy■ lchronisability of clcct五caloscllators,and it can be smaply implcmcntcd on an FPGA.It canp r o v i d c d y n a m i craclcけOnflgllrable clock nctworks,w
not been realised by conventional PLL tcchniqucs.
input port

ИcたIο″Icを開4/1′
SI This rcscarch was suppOrtcd by thc NSF
Center for Dcslgn of Analog― Di」 tal lntcgatcd Circuits Uscful
discussions with G Cau、vcnbcrghs of Johns Hopkins Umvcrsity＼and T.Kttita Of Orcgon Statc Univcrsity arc ratcfl11ly acknowl―
cdgcd◎ IEE 2001
E々 ″″ο″たsL′ ″′ぉ 0″″″ピⅣο」2θθ′θθ69
DO′ :ノθノθイ)ヽ
tた2θθノθθ69

ノイИ glrs′2θθθ

P Kiss, U MoOn, J T Stonick andG C Tcmcs(D"α″′777′″′げElec′″たα′α″グ Cο 771p″
rc2r E71g加′οr772g, 0″鱈ο″S′α′
ア
οこ″
ブッ′
rsJ4ソ, θR97Jθノ,C7S/)｀E‐mail kpeter@ece Orst cdu,′
J Stccnsgaard (D"α ″′722′″′ のr Eたて″たα′E″g777′′r771g, Cο
/17777ら
υ″ル′rsプ
rl,Ⅳ yノ θθ27,1/SИ )'αReferenceslSARHANC― NEJAD M, and TEMES C C: ̀A high―rcsOlution multibit
sigma―delta ADC with digital correction and rclaxed ampliflcr
rcquirements',IEEE工SοliふS′α′′Cノ″ε″Jお,1993,28,(6),pp 648‑
660

fと[CttROA〃 CSと fTTERS 7θ

fr7 Janυa r/2θθ77o′.3アhぃぐ03Fig.1物″お′g′″ι鵞″Йg PLtt rIPLニgル ″ ′rα″″ο′″″r
ル siη
ソ ″′ル7″ おag′″ι″′74g IりLι rIP」 Lノr Expcrimental rcsults on the dis‐v thcyperforlllancc circuits sho、
tributcd clock oscllators for high―trcc likc)clock nct̲havc some advantages over convcntional(H―works[1,コ SuCh distributed oscillators arc based on thc convcn‐
tional PLLs and require analoguc clemcnts in the drcuits We

rvο.277

havc dcveloped a ncw,reconflgurable PLL dr鼠(on an FPGA)、vhch providcs intemal clock synchl・ onisation. Fig. l shows thesh■,lcst conflguration of this IPLL for a singlc input and output.
(For rnultiplc inputs and outputs,the salnc circuit call be obtaincd
slnply by adding thc input ports.)The extemal clock is suppliedat thc input nodc The intcmal clock is gcneratcd in the loop of
the invcrtcr array and the C)R‐gate.Thc input port consists of aphasc colmparison pan(EXOR― gatc)alld a pulsc gcnerator(PG:sli乱 rcglons in the ISF.The fast acquisition shown h Figs.2α
and b is considered to be due to the dtt phase shift which does
not requlrc the control voltage in∞ nventional PLLs.Wc havethercfore shown how a singlc IPLL uttscs the intrinsic synchro‐nisabilty in electncal oscillators that comes from thdr analogue
naturc. Next, wc study the mutual synchronisation of intercon‐
nected IPLLs

gato.ThS drcuit does not rcquire an analoguc
invertcr and AND‐elcmcnt(suCh as̀control voltar')and can be easily IInplementcd
on an FPGA

↓

２ＣＳＯ

↓

３Ｃ
Ｓ０↓

００Ｃ ０＞ ５０︺う０ｍ

ＯＯ● ０＞ ﹈う０一コ０︲ＣＳＯinieCted puiseｏＯ● ｏ＞ ヨαう０一０ヽ＞０︶＞＾output signallme,ns 125ns/diV)037/3″励ヽＯＣ
一 ∽ ０●● ０凱 ′が 解κα°ツ あの グ ル″ιIPL島"Й

加 ′グ腱聰 「W e V e m e d t h e m u t u a l s y n
M′ ′ッ″ κわ̀ 閉 ablity of ̀networks
dsationof IPLLs in the smplcst conflgura‐pulse timing,nsC□

SS″おα′
わ77′″Oε′Fig.2sソ 77̀/2rο
α Forward shiftb Backward shifta ISF

雌 ″ ,雅務tion,i.e.threc IPLLs hterconnectcd in a tumdirectory)Singlc loop
wherc c¨ h IPLL outputs to the input port of the ncxt IPLL andno cxtemal clock is requrcd.Fig.3 shows the output waveformthe五 Sing and fallingfrom each IPLL(OSCl,OSC2,and OSC3ゝ
sadon is robust(withedgcs are sharp and the mutud synchro面
small phasc lago.From simulations with HSPICE,we found ths
small phase lag is an efFect from the intcmal delay of each IPLL
rather than from thc sig7.lal delay bctween IPLLs.Largcr neng twoices宙th IPLLs●ach haⅥangl■ar or square la■of t五mputs and two outputo were also studicd with HSPICE androbust synchrodsadon was observed. IIowever, in non― Ш」Forlnlarge networks on an FPGA a long signal dclay between someattaCent IPLLs makcs the systcm beyond thc synchronisability ofcach IPLL.Thus,a unfbHn layout of IPLLs that avoids a longg″」
PLι
:Itisknown
that
theintHnsic″αι訪sЙn訪ο″″おッsignal dclay is rcquired for large networks. Largcr networks of̀ノ1la‐』 oまnonlincar naturc of electHcal oscillators provides a robustIPLLs arc currendy bchg developcd.
t i o n i n t h c w a v e f o r l n a n d f r e qhutehn ciySけu s c f u l f o r c l o c k g c n ―eration)ThiS nOnlineanty,on the othcr hand,produccs a phascθθι
shift(which iS Sensitivc to the ti血ng of the pcrturbation)in the27 0ι
◎ IEE 2001̀ὸr2θ
oscillation. This t面ng sensitivc phase shift can be charactcHsedrο′′′″s04/J″ιNo,2θ θfθθ5fE′ι
ι′″Jcs Lι
as an血 pulse scnsitive function(ISF)[3],whiCh deflncs the phascθθ5fDOi′ θ′θイ9/a″2θθ′
shi as a function of thc timing of thc illpulse inicctiOn tO thc cir‐
οッ,た″ι
′ Lαιο″′″ッ Cο″′″たr SC・and S Haruyama(Sοc d f o r j i t t c r a n a l y s i s , b u t h e r eH wTanakaca l l y d CS宙c u i t . T h c I S F w a s o Hn」
乃 り ο,Jηα″)use it for the synchroisability analysis of thc IPLL as follows.

pE‐
mail:htan@csl sOny co」
In thc IPLL,if thc input signal and output signal arc syn力 ro‐n i s c d ( w i t h n 0 1 a g ) , t h e p u l s e g e l l e r a t o r ( P G ) o u t p u t S n O m p u lAs cHasegawa(D″′ι
r力′
ιr″ο″た E72g″
Jι
α′α″グ E′
rr7′″′げ Eルα′α″T,and thc oscillation in the loop is not pcrturbcd. Convcrscly, r′パノG7/yし″ッ)
ク,Gル ,Лηακ
therc is a phase diffcrcnce bctwcen the input and output signals,
thc PG is actlvatcd by thc signal from thc EXOR‐ gatc The t血 ng
Referencesof the mpulse gencration depcnds on the phasc ofthe input(、 Vithrespcct to the Output phasc)Figs. 2α and b show thc advanccd
l GUTNIK,V, and cHANDRAKASAN,A: ̀A 300MHz 4‑Mb wave―and retardcd input phase,respcctivcly ln both cases,thc output
phase PLL'. ISSCC Digpipcline CMOS SRAM using a multi‐
phasc is entraincd to thc input phasc(after a few cycles)In thS
Francisco,February 2000,pp 174‑175
p a r t i c u l a r I P L L , t l l e s t t o f t h e L t t u l s e ( f r o m t h C P G ) i s f l X C Techd , b uPapers,Sant
clock
iminune GHz‐
2 MIzuNO,H, and ISHlBASHI,K: ̀A noise―
the tmllng tan bc va五 ed.Thc ISF can thus be dir∝ tly measurcd
distribution schemc using synchronous distributed oscillators'
by i●eCung this(flXed sセc)impulsc cxtemally at the node of theISSCC Dig Tech Papers,San Francisco,February 1998,pp 404‑
(diSabled)PG output,with the mput nOde behg connected to the405
for onc
output node ln this way,thc ISF is obtaincd as in Fig. 2ι
cyclc of the oscillation.It is clear that the output signal phasc is3 HAIIMIRI,A, and LEE,TH: ̀A general theory of phase noise inι Cirι″′お, 1998,33,pp′′―S′α′electrical oscillators',IEEE工 Sο′shifted backward(fow/ard)if thC impulse is applied aftcr the fall―
179‑194h g c d g e ( b c f O r e t h se i五n g c d g e ) o f t h C O u t p u t s i g n a l ( s e e F i g s . 2 α
4 3EST, RE: ̀Phase‑locked loops: design, simulation, andand b)Thus,thc only sttblc state is thc synchroniscd stateけ ithHill,1997)
applications'(MCGraw―d shi■ alld backwardth thc forwal・
n01a9,WhiCh is blocked宙78

fLEθ TROrV′ CSと fTTEPS

78オ

わJar7υar/2θ θ7

1/o′.37

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