IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 49, NO. 9, SEPTEMBER 2002

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Synchronizability of Distributed Clock Oscillators
Hisa-Aki Tanaka, Akio Hasegawa, Hiroyuki Mizuno, and Tetsuro Endo, Senior Member, IEEE

Abstract—We analyze the synchronizability of synchronous distributed oscillators (SDOs) [3], a novel clocking scheme for microprocessors. A computer-aided perturbation analysis is developed for such systems, where analytically tractable equations of
the clock phases are reduced from experimental data reflecting all
circuit details. Using this reduction, a theory is constructed to explain the underlying mechanism of the synchronization in SDOs.
It systematically explains the observed phenomena, the existence
and stability of the (mutually) synchronized states, and the transition from the in-phase synchronized state to the out-of-phase (butstill synchronized) state. Furthermore, the present theory of phasereduction provides a new design principle of coupled oscillators
based on “the equation”; a precise delay control (less than the gate
delay) circuit can be designed in a simple and general form.
Index Terms—Clock distribution network, impulse sensitive function, phase equation, ring oscillator, synchronization,
voltage-controlled oscillator.

I. INTRODUCTIONDIGITAL large-scale-integrated circuits (LSIs) are generally based on a synchronous scheme: a global clock signal
acts as the “conductor of the orchestra,” and each computing element acts as a “member of the orchestra,” performing its operations synchronously at the command of the “conductor.” Distribution of the clock signal in an LSI is thus an issue directly affecting the computing power of the LSI. However, the increasing
size of circuits and rising clock frequencies are making it harderfor only one “conductor” to distribute the clock signal (hereafter “the clock” for short) within an allowable phase error due
to the skew and jitter. Clock networks using distributed voltagecontrolled oscillators are good candidates for overcoming thisdifficulty because they can make multiple, mutually synchronized “conductors” that distribute the clock to all the “members”
in unison [1]–[3]. Namely, this synchronous distributed oscillator (SDO) approach has advantages: it reduces skew and jittercoming from clock buffers and inter-line coupling in the conventional clock distribution approaches. Also, in [3], static jitterand skew caused by variation in the threshold voltage (as wellas the supply voltage at one of the oscillators) is numericallyinvestigated, where both jitter and skew are always reduced,
compared to those in the conventional (noncoupled) multiple
phase-locked loop (PLL) method. Although experimental data
Manuscript received July 5, 2000; revised June 17, 2002. This paper was recommended by Associate Editor R. Sridhar.
H.-A. Tanaka is with the Department of Electronic Engineering, University ofElectro-Communications, Tokyo, 182-8585 Japan (e-mail: htan@ee.uec.ac.jp).
A. Hasegawa is with the Department of Electrical and Electronic Engineering,
Gifu University, Gifu 501-1193, Japan.
H. Mizuno is with the ULSI Research Department, Hitachi Central ResearchLaboratory, Tokyo 185-8601, Japan.
T. Endo is with the Department of Electronics and Communication, Meiji
University, Kawasaki 214-8571, Japan.
Publisher Item Identifier 10.1109/TCSI.2002.802361.

[2], [3] supports the feasibility of such distributed clock oscillators for high-performance circuits working at gigahertz frequencies, there is still insufficient understanding of the ability andlimit of their synchronization. For this purpose, a general andpractical theory of such distributed systems is required. However, in such experimental environments, even though synchronization phenomena can be observed clearly, neither the governing equation nor an analytically tractable model is available
from the system, and this hampers theoretical insights into thesynchronization.
Here, a method is developed to cope with such situations. We
derive a set of simple equations for the clock phases, from experimental data reflecting all circuit details. This derivation is basedon the phase response curve theory and the averaging method,which has been established in studies of nonlinear physics andmathematical biology [10]–[14]. What is new and important in
the present study is the use of the experimental data about thephase response from the (weak) impulsive perturbations to theoscillating element. Such impulsive perturbation analysis has
been recently devised in the insightful study by Hajimiri andLee [4] on the phase noise in electrical oscillators. The present
study, on the other hand, focuses on the effect of certain regular perturbations applied to the oscillator, rather than on statistical properties derived from random perturbation. The resulting phase equation of the clock explains the synchronization ability of SDOs and predicts the limit of synchronization
due to signal delay and distortion. This prediction agrees withobservations by Mizuno and Ishibashi [3], and it shows the validity of the phase reduction method for this system. The phasereduction method developed for SDOs can also be used as adesign methodology for certain coupled oscillators; we can design a circuit of coupled oscillators from its phase equation withdesired properties, and time-consuming exploration for circuitswith circuit simulators can be eliminated.
In Section II, we briefly review the background and some observations for an SDO circuit. Section III introduces basic ideas
and definitions required for the analysis of the system. In Section IV, a computer-aided impulsive perturbation analysis is developed for the phase equation of the system. As a natural consequence, a systematic explanation is obtained for the synchronization observed in SDOs. Furthermore, based on the phaseequation, we are led to a new design methodology for coupledmultiple oscillators; a precise phase resolution (less than thegate delay) generator is proposed as an example.
II. SDOS AND EXPERIMENTAL RESULTS
The core circuit of the SDO is simple: it consists of CMOS
oscillators and wires interconnecting them (Fig. 1). The oscillators can be ring oscillators (ROs) or differential ring oscillators
depending on the application.

1057-7122/02$17.00 © 2002 IEEE

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 49, NO. 9, SEPTEMBER 2002

(a)

(b)

Fig. 2. Mizuno and Ishibashi numerically considered a linear array case forvarious values of l (l = 4; . . . ; 20 mm) (originally shown in [3]). The abscissa
indicates the number of clock cycles (clock number) after two ROs initiate
the oscillation with a 90 phase difference. The ordinate indicates the phasedifference (phase error) between two ROs at each clock cycle. A transition
between states was observed at l = 14 mm: below l , the phase difference
tended to zero and above l , it tended to a constant. The change was observed
to be sharp at around l = l . A 0.25-m CMOS technology was used, and each
17-stage RO operated at around 600 MHz.

(c)Fig. 1. (a) Core circuit of the SDO scheme in a linear array case. ROs areinterconnected by wire. Each RO is a loop with an odd number of CMOS
inverters. The dotted rectangles indicate the “cells” for which the sensitivity to
weak impulsive perturbations was measured. (b) Wire modeled as an RC chain.
(c) Inverter formed by a pair of pMOS and nMOS gates.

As shown in Fig. 1(a), such oscillators generally have an odd
number of inverting devices (e.g., NOT-gates) in a closed loop.
This creates an unstable state, resulting in robust oscillation witha rectangular waveform being used as the clock signal. Qualitatively, each inverting device can be roughly modeled as aswitch (with a finite delay) that inverts a digital HIGH ‘1’/LOW‘0’ input to a LOW ‘0’/HIGH ‘1’ output. However, modeling thiswith quantitative accuracy is not an easy task because each inverter is a highly nonlinear device, reflecting the physics ofsolid-state circuits. Here we consider an RO with a CMOS inverter [i.e., a pair consisting of a pMOS gate and an nMOS
gate; see Fig. 1(c)], as used in the experiments of Mizuno andIshibashi [3]. Semi-empirical models are used in the circuit simulator for the gates to reflect the measured characteristics of thedevices (we used the LEVEL3 model in HSPICE [5], [6]), so anumerical transient analysis of the system can be done, taking
into account the details of the gates. Mizuno and Ishibashi [3]used 0.25- m CMOS gates in their simulations, but we used
1.6/1.2- m (pMOS/nMOS) CMOS gates to make it easier toreproduce the simulation.
Also, the interconnection between oscillators is a dynamicalsystem. In the simplest case, it can be modeled as a chainof resistors and capacitors [an RC chain shown in Fig. 1(b)]described by linear ordinary differential equations (ODEs).
However, the interconnection between oscillators often includes
multiple inverters for waveform regeneration, and nonlinear
ODEs are required for this case. Thus, a precise description of
the core circuit of the SDO requires a large number of lines ofcode in the circuit simulator, which can have an “if then,else” structure.

Thus, the detailed description of the circuit itself is quite complicated and far from analytically tractable. However, certain
clear patterns of mutual synchronization were observed in theexperiments done by Mizuno and Ishibashi (using a test chip operating at 200–400 MHz [3]). They also made systematic (transistor-level) circuit simulations to explore the synchronization
ability of the SDOs. We followed their simulations (with different CMOS parameters as mentioned above) and obtained thesame patterns of the mutual synchronization, which are summarized as follows.
1) The interaction between oscillators did not alter the original waveform in each (uncoupled) oscillating element 1 ;the waveform itself was robust under the interaction.
between ad2) Depending on the length of the wire
jacent oscillators, the system showed two different stabilized states: complete synchronization with zero phasedifference (for shorter ) and synchronization with a constant phase difference (for longer ) (Fig. 2).
3) The above two different synchronized states showed asharp transition at a certain wire length (Fig. 2).
The mechanism underlying these phenomena will be clarified
in Section IV.
III. BASIC IDEAS AND DEFINITIONS
To make the description simpler, we focus on the case of aone-dimensional (1-D) SDO [Fig. 1(a)] here. This simplification is not essential and the same analysis can be made for any
network topology.
While the system can be analyzed by dividing it into oscillators (ROs) and interconnections (wires), we use virtual “cells”[the dotted rectangles in Fig. 1(a)] to group oscillators and wires
together. This simple idea turns out to be powerful; it enables
1Precisely, the oscillating element is a combination of the oscillator and theadjacent wires (defined as “cell” in Section III).

TANAKA et al.: SYNCHRONIZABILITY OF DISTRIBUTED CLOCK OSCILLATORS

(a)

(b)
Fig. 3. Numerical data for cell shown in the inset. (a) Phase shifts (+) due
to impulsive perturbations; the dotted rectangle in the center includes a LRR
at the (fixed) rising part of the periodic waveform. (b) The impulse sensitivity(0( 1 ) 1 q ) for four different wire lengths l. The abscissa indicates the phase(of one oscillation cycle) at which the impulse was injected. The ordinate
indicates the amount of the phase shifted by the impulse. Four curves represent
the interpolation of the impulse sensitivity (for l = 20; 40; 60, and 80 mm)
using a Fourier series (ninth-order). The height of the injected impulse is
50 mA, and the charge displacement q is about 0.5 pC.

the following impulsive perturbation analysis and facilitates its
extension to higher dimensional networks and to more complex
interconnections having nonlinear effects.
Given a cell, we need information about its phase response toimpulsive perturbations,2 i.e.
1) the linear response region (LRR) [Fig. 3(a)];2) the impulse sensitivity function (ISF) [Fig. 3(b)] definedin the LRR.
LRR and ISF are defined as follows. If we have a stable periodic oscillation, an impulsive perturbation (e.g., a current injection) can be applied at any phase (timing) of the one-cycle
oscillation. The perturbed oscillator is pulled back to the original oscillation immediately after the impulse hits it, but a small
phase shift (compared to the nonperturbed oscillator) remains.
Thus, we can define a function of the phase shift with respect
to the timing at which the impulse is applied, and this function
is periodic with the period of the clock signal. We call it the
ISF here. If we fix the timing of the perturbation, the amount of
the phase shift is determined by the amount of the perturbation(the pulse height). For all the cases (of circuits, circuit parameters, and the timing of perturbation) that we considered, a linear
2The system in this study is not linear time-invariant (LTI) and the relationshipbetween the phase shift and the injected impulse height comes from the (local)
structure of the limit-cycle oscillator (in other words, Floquet theory). Namely,
the relationship between the phase shift and the injected impulse height is not
given analytically as in the LTI case, but given numerically as follows.

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relationship held between the phase shift and the pulse height,
in a certain region around the zero pulse height [see the dotted
central region in Fig. 3(a)]. We call this region with linear characteristics the linear response region, and it can be numerically(or experimentally) identified. Because of this linearity, the ISF
is uniquely defined in the LRR. Interestingly, the ideas of ISF
and LRR have been used in studies related to limit-cycle oscillators in nonlinear physics and theoretical biology [9]–[13].
In those cases, the ISF is commonly called the phase response
curve (PRC), and the LRR is considered as the neighborhood of
the limit-cycle where an isochrone (i.e., a manifold having thesame phase) can be defined.
The notions of LRR and ISF for the voltage-controlled oscillator (VCO) are devised in the recent study of phase noise by
Hajimiri and Lee. They first showed that a combination of circuit simulators and the notions of LRR and ISF provide a qualitatively and quantitatively powerful tool for jitter analysis andfor designing VCOs with low jitter. More recently, Demir et al.
presented a rigorous nonlinear analysis of phase noise based on
the Floquet theory [14]. They pointed out that the (small) perturbation to the limit-cycle oscillator can be decomposed into thetangential direction of the limit-cycle and the subspace spannedby the remaining Floquet eigenvectors. Thus, for a weakly perturbed single VCO (limit-cycle oscillator), an experimental approach by Hajimiri and Lee and a mathematical foundation by
Demir et al. is now established. Then, we are naturally led tothe analysis of interacting multiple VCOs. In the next section,
we consider the phase dynamics of the distributed, interacting
VCOs.
IV. PHASE MODEL AND ITS IMPLICATIONSIn an LSI, the interconnecting wires have high resistance(more than 100 /cm), and the maximum current in them is sosmall (less than a few milliamperes) that the interacting oscillating elements in the SDO fall into the LRR. Here we consider
the LRR and ISF of the virtual cell shown in Fig. 1(a). As
discussed in Section III, the LRR is defined by the relationshipbetween the injected impulse height and the phase shift of theis defined by theoscillator in the cell, and the ISF
timing of the impulse and the corresponding phase shift. Then,the (normalized) phase shift at time (due to the unit impulse
injected at time ) is given by(1)
is the maximum charge displacement across the cawhereis the unit step at, andispacitor on the node,.3 Because each oscillator
the ISF, which has a period of
has a robust oscillation (a limit-cycle), the waveform of the oscillation (and the natural angular frequency ) is robust under
the weak interaction between oscillators. However, the instantaneous phase of each ( th) oscillator can be gradually shifted

3We used the same notation as in [4] for easier comparison between our theoretical results and those in [4]. In (1), 0(!  ) is defined as the maximum phaseshift (due to q
) at time  .

1274IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 49, NO. 9, SEPTEMBER 2002

by the perturbation, and this accumulated phase shiftexpressed bycan be(2)is the current injected into the cell andis thewhere(fixed) time delay for the injected impulse to reach the oscilis determined by the current.
lator.4 Thus, the phaseis determined by the interaction
Conversely, this current
andas folof the adjacent cells, the phaseslows. In each cell ( th cell), the oscillator has a robust waveform(i.e., the clock signal) and drives the voltages on the interconnecting wire. Then, the oscillating voltage on the outer nodesof the th cell is a certain function of the instantaneous oscilla, as far as the oscillation
tion phase of the oscillator:
is stable and the interconnection is fixed. It should be noted thatthe waveform is not exactly the same as the clock signal on
the oscillator, since the clock is delayed and distorted along thewire until it reaches the outer node. As the outer nodes of the(from the thcells are resistively connected, the current, where is thecell to the th cell) is given byresistance between adjacent cells [Fig. 1(a)]. Then, (2) becomes(3)
or equivalently(4)
andwhich implies that a closed relationship holds between. By setting
we obtainHlFig. 4. Nonlinear phase characteristics ( ( 1 ) in (8)) for different wire
lengths. All curves pass through zero. The slope at zero is positive for= 20 mm, nearly zero but still positive for = 40, and negative for = 60
and 80 mm.

l

l

and
(7)
where is a (small) frequency deviation from the synchronized; this frequency deviation comes from the infrequency
teraction (perturbation) effect as well as the threshold voltage
and the supply voltage variation. Process variation may possibly
slightly. However, as we will see, introaffect the shape ofas well as
does not alter theducing a small variation insystem’s synchronization ability.
requires and. Although
As in (6), computing
has been defined by the maximum charge displacement,
is not necessarily needed for computing
the exact value of. Instead of, we considered a fixed charge displacement(that corresponds to the pulse size) and systematicallyobtained the phase shift for different cases as in Fig. 6 (later). It
should be noted that the time delay of the impulse (the phaseanddelay ) vanishes in (6) and (7). However,contain information about the effects of the time delay, and thereflects the signal delay and distortion.
shape ofA. Synchronization Limit of the SDO(5)
is small (less than a few mA), andIn (5),
is very large (several hundred megahertz–1 GHz); the time
is much slower than that of. This situation
evolution ofleads naturally to an application of the averaging method [6][well-known in the ordinary differential (ODE) theory], where
can be reduced by integrating
the slow motion ofwith. This integration can be handled by using theone cycle ofand, which(numerically obtained) Fourier series ofleads to the following form:(6)
4In [4], this time delay is assumed to be 0, because the impulse is applied
directly to the oscillator.

In the 1-D linear SDO, the interconnecting wire (RC chain)
fromhas a symmetric bidirectional nature, and the currents
both (left and right) adjacent cells do not interact with eachother. Thus, for this particular case, the phase equation (7) takes
the following form:(8)strongly depends on wire
As shown in Fig. 4, the form ofholds for any wire length (thelength . Althoughin-phase state always exists, see Appendix I), the slope at
can be positive or negative. For wire lengths less than 40 mm,mm),
this slope is positive, and for longer cases (it becomes negative and another zero crossing point appears asshown in Fig. 4.
In Mizuno and Ishibashi’s study [3], the global effect ofvariation (as well as supply voltage variation) at one of the oscillators is numerically investigated, where it is observed thatdeviation. The static skew
the static skew is proportional tois the phase difference between oscillators and it corresponds toTANAKA et al.: SYNCHRONIZABILITY OF DISTRIBUTED CLOCK OSCILLATORSin (8). Also, the natural frequency deis proportional todeviation. From (8), it is clear
viationis proportional to if the oscillathat the static skew
. Thus, the presented
tors are mutually synchronizedtheory is consistent to the observation in [3] regarding the effectdeviation.
ofIf we consider a 1-D circular network of SDO, a synchronizedstate with uniform phase differences:with( : integer) is possible. For
such a solution of (7), linear stability theory proves that for posthe synchronized state is stable and for negative
itive
it becomes unstable (see Appendix II). For example,
let’s consider circular SDOs with five or six (an odd or evennumber of) oscillators. Numerical simulations (with HSPICE)
mm, only in-phase synchronized statesshow that, for
are observed for both cases. This can be explained, andtheoretically as follows: for
implies that this state is stable. On the other hand, for a, a certain amount of the frequency(formal) solution withdeviation is required becausemust be satisfied. However, is restricted to some small range
because in ROs the oscillation period is proaround
portional to the gate delay of each invertor and this cannot be. Then, such aaltered much by the weak interaction due tophase-lagged solution is not realized. Thus, the in-phase solution
is the only stable state for the shorter wire case.
withmm), only
In contrast to the shorter wire case, for larger (are observed numerphase-lagged synchronized states. Although the in-phase state is posically for the case of, as shown in Fig. 4), the slope ofis negasible (tive and this implies that the in-phase state is unstable and cannot
be realized. On the other hand, the phase-lagged (anti-phase) stateis realized for the case of, becausewithare positive, andhas a zero crossing point close toandbecomes small (as observed in the case, the phase-laggedof 80 mm in Fig. 4). For the case ofdoes not exist, and neither the in-phase nor thestate withphase-lagged synchronized states are observed.
mm)
As we have observed, there is a critical length (between the stable in-phase state and the phase-lagged state,holds. This critical length is unpractiat whichcally large for the CMOS parameters we considered. However,it scales down as the CMOS gates are scaled. As shown in Fig. 2,
is around 14 mm for 0.25- m CMOS parameters (with an operating frequency of around 600 MHz), where the value of isin the “practical” range. Although we have chosen a particularparameter set for the computer-assisted derivation of the phasemodels, the predicted in-phase to phase-lagged state transition
does not depend on a particular set of parameters. Our theory
thus agrees with Mizuno and Ishibashi’s results [3]. Although
gradually approaches a sinusoidal wave as
the shape of
becomes larger, the position of the (on these curves) is observed to gradually shift to the right as becomes larger. This
andreflect the incan be understood by the fact thatternal delay of the cell and this delay is mapped to the phase. Thus, the emergence of the phase-lagged synshift of,chronized state can be explained by the deformation ofand the underlying mechanism of a sharp transition at (butstill supposed to be continuous) is clarified.

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Fig. 5. Core circuit of CPG-like circuit incorporating the asymmetricinteraction of adjacent oscillators. The dotted area defines a cell. Instead ofa long wire between oscillators, resistor R is inserted. In the steady state,adjacent nodes show rectangular voltage waveforms with phase difference of =M radian. Because the oscillation frequency is nearly the same as that
=M can be obtained at
in a single (uncoupled) RO, a precise delay of 
nodes (a) and (b).

0

The above predictions guarantee the correct function of the, that is, there is a unique, stable, in-phase state.
SDO for
The theory also predicts that a limit of the SDO appears at .
Beyond , there is no stable in-phase state, which means that the
SDO no longer provides correct synchronous clocking for LSIs.
Although we have not proved that matches half the wavelengthof the clock signal on the wire, we do have numerical evidence forit. Therefore, for the SDO to function correctly, the wire length
should be shorter than a certain length, which is thought to be
inversely proportional to the clock frequency, that is, there is anupper limit on the operating frequency in the SDO.
B. Novel Circuit Design
Having obtained a method for reducing the interacting oscillators into a set of equations in terms of the phases, it is now
possible to design and analyze circuits based on “the equation.”
We consider here a precise delay generating circuit as a practicalexample. In a single RO, the delay resolution (minimum phasedifference between two voltage signals on the nodes) is bounded. However, if multiple
ROsby a single gate delay
are coupled in a certain manner, the delay resolution can be of. In the previous (and first) circuit proposed
the order offor this purpose, special 2-input, 1-output buffers (instead ofusual CMOS inverters) were developed, and the resulting circuit
had two-dimenisonal network topology with many interconnections [8]. Their circuit seems beautiful and somewhat ingenious.
However, a question arises: if certain good oscillators (in particular, ones having noise immunity) are available, is it not possible
to achieve the function by simply interconnecting those oscillators (instead of developing a special buffer)?
Based on “the equation” discussed above and an analogy to thecentral pattern generator (CPG) circuit [11], a simpler and generalformulation of circuits is possible, where the network topology is
1-D (fewer interconnections), and each oscillator can be any typeof oscillator (in practice, noise immunity is essential). As a realization of the above idea, we consider here the simplest case, i.e.,
ROs and one inverter on the wire (Fig. 5). The cell can be defined
as in Fig. 5. For this choice of the cell, we have checked that thevoltage waveforms at nodes (l), (a), and (r) in the isolated cell (see

1276IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 49, NO. 9, SEPTEMBER 2002(a)Fig. 7.

100

Nonlinear phase characteristics (.

H( 1 ) in (9)) with resistance R =(b)Fig. 6. Numerical data for cell shown in the inset. (a) Phase shifts due toimpulsive perturbations; the injection from the left node (!) and the right node( ) are measured separately. (b) The impulse sensitivity (0( 1 ) 1 ) for both
directions; impulse from the left node (!) and right node ( ). The impulse
height is 50 mA, and the charge displacement is about 0.5 pC.

q

q

Fig. 5) coincide with those in the full system (when the cells are interconnected). Thus, this choice of cell is well defined. In contrast
to the symmetric interaction in the SDO, in this CPG-like circuit,the interaction is highly asymmetric; the LRR and ISF must be defined separately for the impulses from the left and right directions.
Then, the phase equation for this system takes the following form:(9)
from the left
In (9), unlike (8) for the SDO, the effect)th cell dominates andfrom the right (th)(
cell is negligible, because the phase shift is negligible for any
hastiming of the perturbation from the node (r).
multi-modal characteristics and there are two zero crossing
as shown in Fig. 7; one is very close
pointsto (this is analytically obtained in Appendix I). At this point,
is negative, and the other one is close to
the slopeandand hereis positive andcan be close tofor a certain . This implies thatin (9), so the phase-lagged stateis the only stablesynchronized state (see Appendix II). Numerical simulation ofthis system verifies this prediction (as shown in Fig. 8 for thecase).
Thus, a difference between our CPG-like circuit and the SDO
can be clarified from their phase equations (8) and (9). For the
CPG-like circuit in Fig. 5, the phase-lagged state (uniform phaseradian) is the only stable state, as opposed todifference of
the in-phase state (no phase difference) for the SDO. This prediction was verified using HSPICE under the same simulation

Fig. 8. Oscillation waveforms in the CPG-like circuit (Fig. 5), having fivecoupled (15-stage) ROs.

protocol used in the above SDO case (Fig. 8), including the simulation in a slightly noisy environment.
V. CONCLUSION
This study has presented a computer-aided phase reduction
method for coupled oscillators; the SDO. The method is basedon the fact that the oscillators interact weakly in a practicalsituation on an LSI chip, and on the use of the ISF (or PRC) fromexperimental data. Explicit dynamical phase equations for ROs
and coupled ROs can be derived in the first place, which enables
theoretical insights into their synchronization ability as well assynchronization limit. The presented phase reduction has generalapplicability, and this benefits an “equation-based” design of coupled oscillator systems that have a simple and general structure.
APPENDIX IANALYTICAL DESCRIPTION OF THE PHASE
COMPARISON CHARACTERISTICS
This appendix shows an analytical approach to describe some
: a zero crossing point ofand the slope
properties ofat that point.
ofFrom the definition (6), the phase comparison characteristics
can be determined byand . For the 1-D SDO,andare exactly the same and can be
the waveforms ofgiven by(10)

TANAKA et al.: SYNCHRONIZABILITY OF DISTRIBUTED CLOCK OSCILLATORS

and the corresponding ISF becomes
(11)
with

. Then,is obtained as

1277

where
denotes the time derivative ofand it is tangential to . If we consider the situation where the statevariables are node voltages and an impulse is applied to theth node, then, andare respectively given as,, whereanddenotes the derivative with respect to phase . Then, the phaseshift (16) becomes

(12)
(17)

From (12), we have
, which explains why all phase comparisonin Fig. 4 (obtained from the experimental
characteristics
data of the ISFs) pass the .
are slightly
For the CPG-like circuit, the waveforms ofdifferent and the phase shift due to the inverter should be taken
into account as follows:
(13)
and
(14)
with
have

. Then we(15)
and, thenholds. However, as
and , and and are slightly different, the zero crossing
point of (15) is slightly shifted from . This explains why thezero crossing point in the experimental data is close to , asshown in Fig. 7.
Now we consider the situation where a “cell” (defined in
Section III) is perturbed by an external impulse. For this cell,a limit cycle is defined in the (high-dimensional) state space
and the external impulse is given by a perturbation vector
at some point of the limit cycle . In the neighborhood of ,a local coordinate is given by the tangential direction of andthe “isochrone: which defines the phase of the oscillation. On
is decomposed into two
this coordinate, the perturbation
elements: one is tangential to and the remaining is tangential
to the isochrone. In the present situation we consider, the limit
cycle is strongly attractive and the remaining element dies out
immediately (after a signal delay in the cell). It is noted thatthe tangential direction of is not necessarily orthogonal to theisochrone. (A simple model is analyzed to consider this naturein [15].) However, if this orthogonality is satisfied (at least approximately), a great deal of simplification can be made in the. Here we will consider such a hypotheticalexpression ofsituation and see what can be concluded.
(due toIf the orthogonality is assumed, the phase shift) is simply given by
If

(16)

correBy the definition of the ISF in (1),.
sponds to
In our particular examples (1-D SDO and CPG-like circuit),
corresponds to the interaction of the adjacent cells;. It should be noted that the cell in thesecases is spatially extended and the denominator
contains information about the signal delay due to the spatiallyextended interconnections.
is a constant, thenIf the denominatorholds, soand
is obtained. This implies
that the phase comparison characteristics are an odd function
and do not match the experimental data shown in Fig. 4.
reflects the spatially
Here, the above insight that
extended nature of the cell is essential to explain the charac. This insight and (12) predict that the slope
teristics ofis positive for shorter wire lengths (where
can be considered to be nearly a constant and)can be negative for longer wire lengths because
andreflects a larger signal delay in the cell anddeviates from a constant. This prediction is consistent with thechanges from positive
experimental data in Fig. 4 whereto negative as the wire length becomes larger.
APPENDIX IIThis appendix shows a criterion for the linear stability of themutually synchronized states. We assume a synchronized stateand introduce a small pertur. Then, (8) becomesbation to such that(18)
After removing the synchronized part in (18), we obtain thelinear ODE for as
..
.
..
.

..
.
..
.

..

.

..

.

..

.

..

.

..
.
(19)

in which, and. The matrix in (19) is known as a circulant matrix and1278

its eigenvaluesasIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 49, NO. 9, SEPTEMBER 2002

and eigenvectors

can be explicitly obtained[15] A. Demir, A. Mehrotra, and J. Roychowdhury, “Phase noise in oscillators: A unifying theory and numerical methods for characterization,”
IEEE Trans. Circuits Syst. I, vol. 47, pp. 655–674, May 2000.
[16] C. Kurrer, “Synchronization and desynchronization of weakly coupledoscillators,” Phys. Rev. E, vol. 56, pp. 3799–3802, Oct. 1997.

(20)
holds for any, and , and the stability
Then,in (19).
of the synchronized states can be determined by
For the in-phase state withandimplies it is stable, and for
it isunstable. Also, if the phase-lagged synchronized state satisfies, then it is stable(unstable). The same analysis can be made for the stability forterm in (9) is neglected, the linear ODE for(9). If the, andthe perturbation is obtained from (19) by setting
thethe same stability criterion is obtained. For, it is unstable.
synchronized state is stable and for
ACKNOWLEDGMENT
The authors would like to thank T. Ohira and S. Haruyama(Sony Computer Science Laboratory) and T. Murayama and
M. Takahashi (Sony Semiconductor Company) for their helpfulcomments and support.

Hisa-Aki Tanaka (S’94) received the B.E. degree inelectrical engineering and the M.E. and D.E. degrees
in electronics and communication engineering fromWaseda University, Tokyo, Japan, in 1990, 1992, and1995, respectively.
From 1997 to 2001, he was with the Sony
Computer Science Laboratory. In 2001, he joined
the Department of Electronic Engineering, Faculty of Electro-Communications, University ofElectro-Communications, Tokyo, Japan, as an Associate Professor. His current research interests are insynchronization issues in computing systems as well as nonlinear physics.
Dr. Tanaka received the 1995–1997 Research Fellowships of the Japan Society for the Promotion for Young Scientists.

Akio Hasegawa received the B.E., M.E., and D.E.
degrees from Meiji University, Kawasaki, Japan, in
1995, 1997, and 2000, respectively.
In 2000, he joined the Department of Electrical andElectronic Engineering, Gifu University, Gifu, Japan,
as a Research Associate. His research interests arechaos and synchronization phenomena in electronic
circuits.

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Hiroyuki Mizuno received the B.S., M.S., and Dr.Eng. degrees in electronicengineering from Osaka University, Osaka, Japan, in 1991, 1993, and 2001,
respectively.
In 1993, he joined the Central Research Laboratory, Hitachi, Ltd., Tokyo,
Japan, where he has been engaged in the research and development of highspeed and low-voltage circuits for SRAMs, microprocessors, and embedded
DRAMs. His current research interests are in low-power, high-performance circuits and system design for system-on-a-chip devices.

Tetsuro Endo (M’77–SM’98) received the B.E.,
M.E., and Dr.Eng. degrees in electrical engineeringfrom Keio University, Yokohama, Japan, in 1972,
1974, and 1977, respectively.
From 1977 to 1992, he was with the Department of Electrical Engineering, National Defense
Academy, Yokosuka, Japan, where he was an
Assistant Professor, a Lecturer, and an Associate
Professor. In April 1992, he joined the Department ofElectronics and Communication, Faculty of Scienceand Technology, Meiji University, Kawasaki, Japan,
as a Professor. His research interests include multimode oscillations of coupledoscillators, and nonlinear dynamics and chaos of phase-locked loops. From1986 to 1989, he served as a Secretary of the Technical Group on Nonlinear
Problems of the Institute of Electronics, Information, and Communication
Engineers (IEICE).
Dr. Endo is a member of the Institution of Electrical Engineers and the
IEICE of Japan. From 1995 to 1997, he was an Associate Editor of IEEE
TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I: FUNDAMENTAL THEORYAND APPLICATIONS. From 1996 to 1998, he served as the Vice President andPresident of the Technical Group on Nonlinear Problems of the IEICE.