SHF Communication Technologies AG
Wilhelm-von-Siemens-Str. 23D • 12277 Berlin • Germany
Phone +49 30 772051-0 • Fax ++49 30 7531078
E-Mail: sales@shf.de • Web: http://www.shf.deDatasheet
SHF 19120 A
2.85 GSa/s Arbitrary Waveform
Generator with
4x 10.3125 Gbps BPG Outputs

For illustration only, actual product may vary

SHF reserves the right to change specifications and design without notice – SHF 19120 A - V002 – Mai 22, 2017

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Description
The SHF 19120 A is a 2.85 GSa/s, 14 bit Arbitrary Waveform Generator with four 10.3125 Gbps bit pattern outputs. Its
high AWG bandwidth (>1.2 GHz), high output amplitude (1.2 V on DC output, +8.2 dBm on the AC output) and large
sample memory size (1 Giga Sample) make it a versatile arbitrary generator.
Three outputs (Direct, DC and AC) cover a wide range of test scenarios (jitter, glitched signal, modulation andmodulated signal generation, etc).
Two markers with a 2-sample resolution can be used to trigger external equipment. Two edge/level trigger inputs startor pause the signal generation.
Two or more SHF 19120 A instruments can be synchronized together via their 10 MHz references.
A sample sequencer allows the creation of complex waveforms with memory-saving repeated patterns (to be enabledin the future with a software update).
In addition to the three analog outputs, the SHF 19120 A can generate up to four 10.3125 Gbps PRBS signals withpre-emphasis on the rear panel, driven by the DAC clock, or by an external clock.
The SHF Control Center software allows a complete control of the SHF 19120 A, including a waveform editor with awaveform library and an equation editor. When connecting a keyboard, a mouse and a monitor, the SHF 19120 A canbe controlled without a computer, via the embedded version of the SHF Control Center.

SHF 19120 A : actual waveform and GUIFeatures•Arbitrary Waveform Generator
ooooooooo•

Bit Pattern Generatorooooo•••

Sampling frequency fDAC up to 2.85 GHz
1 GSa ̶ sample memory
Three types of outputs: Direct, DC coupled (1.2 Vpp) and AC coupled (+8 dBm max, in 0.1 dB steps)
High output bandwidth: DC to 1.2 GHz for the direct and DC outputs, 20 MHz to 500 MHz for the ACoutput
Up-sampling: Double Interpolation Mode, the signal spectrum is shifted to fDAC, doubling the effective
DAC update rate
Two sample-synchronous marker outputs
Two sample-synchronous trigger (edge/level) inputs
Output skew control in combination with triggers and markers delays help the synchronization of several
SHF 19120 A AWGs
Outputs and inputs for the DAC clock and the 10 MHz reference
Four PRBS differential outputs with lane bitrates from 1 Gbps to 10.3125 Gbps (with the possibility ofoverclocking to 12.5 Gbps)731
Nine PRBS patterns (from PRBS -1 to PRBS -1), plus two square wave patterns of half line rate
(SQUARE2) and line rate ÷ 32 (SQUARE32).
Frame trigger output
Bit skew adjustment
Pre and post cursor pre-emphasis

Computer controlled via a 1 G Ethernet link orStand-alone operation, with keyboard, mouse and monitor
Modern and user-friendly software

SHF reserves the right to change specifications and design without notice – SHF 19120 A - V002 – Mai 22, 2017

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Applications•Jitter source•

Development of Test and Measure Equipment•

Wideband signals•

Wireless communications•Radar signals•

Multilevel signals•

High speed serial link testing•Backplane characterization

Block Diagram

SHF reserves the right to change specifications and design without notice – SHF 19120 A - V002 – Mai 22, 2017

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Absolute Maximal Ratings
Parameter

Unit

Symbol

Min.

Typ.

Max.

Power Supply Voltage

V

13

Trigger Inputs

V

2.5

DAC Clock Input

dBm

3

PRBS Clock Input

dBm

3

10 MHz Input

V

3Comment

Peak-to-PeakSpecifications – SHF 19120 A
Unless specified, all measurements are taken with fDAC = 2.85 GHz, single-ended.
Parameter

UnitSymbol

Min.

Typ.

Max.

Comment

General characteristics - AWG
Resolution

bits

Sample Rate

GSa/sfDAC

1.4

RF Connectors
Output Adjustable Delay
Output Adjustable Delay StepMarkers do not decrease
resolution or memory size.

14the2.85
SMA

Sample Clock
Periods
Sample Clockperiods

0254

2

General characteristics - BPG
Channels
Bit Rate

4Gbps

0.372

RF Connectors

SMA

External Clock Input
Multiplier Factor
Adjustable Delay Length

10.3125bit

Overclocking up to 12.5 Gbps
possible. See bit rate ranges, page
12Differential

180127The BPG bitrate will be the externalclock frequency multiplied by thisfactor
With a 1 bit step

SHF reserves the right to change specifications and design without notice – SHF 19120 A - V002 – Mai 22, 2017

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Direct Output
Parameter

Unit

Symbol

Min.

Typ.

Max.

Comment

Impedance

Ohm

Voltage Window Minimum

mV

65

75

Single-ended. Includes the output
offset from internal biasing

Voltage Window Maximum

mV

800

810

Single-ended. Includes the output
offset from internal biasing

Adjustable Full-Scale
Amplitude Minimum

mV

220

225

Single-ended, Peak-to-Peak

Adjustable Full-Scale
Amplitude Maximum

mV720

725Single-ended, Peak-to-Peak

Full-Scale Amplitude StepmV5

Full-Scale Amplitude
AccuracymV±50

Random Jitter RMS

ps3

Rise/Fall Time

ps3dB BandwidthGHz

Calculated Bandwidth

GHzSFDR
Spurious Free DynamicRange

dBc

-38

285 MHz 0 dB Output, harmonics
excluded, 40 dB interpolation filter
enabled.

Two-Tone IMD
Inter Modulation Distortion

dBc

59

f1= 19.9 MHz f2= 20.1 MHz ; 700mVpp ; 2f2-f1

1%

310 MHz Output, 730 mVpp ; 5 firstharmonics.

Harmonic Distortion

505Measured with PRBS-7, sample
clock for trigger.

1100.7V, 1.425 GHz square signal,
from 20% to 80%

1.2
3.1

0.35 / Rise time

Direct output: Differential or Single-ended output (Unused output must be terminated with a 50 Ω load), DC-coupled.

SHF reserves the right to change specifications and design without notice – SHF 19120 A - V002 – Mai 22, 2017

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DC Output
Parameter

Unit

Symbol

Min.

Typ.

Max.

Comment

Impedance

Ohm

Voltage Window Minimum

mV

-100

-200

Voltage Window Maximum

mV

1200

1400

Adjustable Full-Scale
Amplitude Minimum

mV

250

400

Single-ended, Peak-to-Peak

Adjustable Full-ScaleAmplitude Maximum

mV

1200

1400

Single-ended, Peak-to-Peak

Full-Scale Amplitude StepmV

5

Full-Scale Amplitude
AccuracymV±50

Adjustable Offset

mVOffset StepmV

5Offset Accuracy

mV

±50

Random Jitter RMS

ps2

Rise/Fall Timeps

3dB Bandwidth (from DC)

GHz

Calculated Bandwidth

GHz

SFDR
Spurious Free Dynamic
Range

dBc

-60

285 MHz 0 dB Output, harmonics
excluded, 40 dB interpolation filter
enabled.

Two-Tone IMD
Inter Modulation Distortion

dBc

-54

f1= 19.9 MHz f2= 20.1 MHz ; 700mVpp ; 2f2-f1

0.2%

310 MHz Output, 350 mVpp, 400 mV
offset ; 5 first harmonics.

Harmonic Distortion

50100

The signal will be clipped outside
the voltage window±1001000

Limited by the output voltage
window

5

Measured with PRBS-7, 0.7 Vpp,sample clock for trigger.

110

Measured with PRBS-7, 0.7 Vpp,sample clock for trigger, from 20%
to 80%
Measured with the 40 dB
interpolation filter enabled

1.2
3.1

0.35 / Rise time

DC output: Differential or Single-ended output (Unused output must be terminated with a 50 Ω load), DC-coupled

SHF reserves the right to change specifications and design without notice – SHF 19120 A - V002 – Mai 22, 2017

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AC Output
Parameter

Unit

Symbol

Min.

Typ.

Max.

Comment

Impedance

Ohm

50

Adjustable Full Scale
Amplitude Minimum

dBm

-28.2

-28

Adjustable Full Scale
Amplitude Maximum

dBm

88.2

Adjustable Amplitude Step

dB

0.1

AccuracydBm

0.2

Adjustable Offset

V

Adjustable Offset StepmV

50

Offset Accuracy

mV

±50

3dB Bandwidth(starting at 20 MHz)

MHz

550

6dB Bandwidth(starting at 20 MHz)MHzSFDR
Spurious Free DynamicRange

dBc

-49

275 MHz 0 dB Output, harmonics
excluded, 40 dB interpolation filter
enabled. DC to fDAC.

Two-Tone IMD
Inter Modulation Distortion

dBc-56

f1= 91.8 MHz f2= 93.6 MHz ; 0 dBm ;2f2-f100,44.5

Integrated bias tee±1000dB sinus, 40 dB interpolation filter
enabled, sweep 20 MHz to 600 MHz

0dB sinus, 40 dB interpolation filter
enabled, sweep 20 MHz to 1425 MHz

1425

Harmonic distortion

0.31%

310 MHz Output, 0 dBm ; 5 firstharmonics.

Double Interpolation mode
-10 dBm Output, 40 dB interpolation
filter enabled. fDAC/2. to fDAC.

3dB BandwidthMHz650

SFDR
Spurious Free DynamicRange

dBc

-41

2.75 GHz -10 dBm Output, harmonics
and f= 275 MHz excluded, 40 dB
interpolation filter enabled. DC to fDAC.

Two-Tone IMD
Inter Modulation Distortion

dBc

-69

f1= 1.63 GHz f2= 1.66 GHz ; -10 dBm; 2f2-f1

AC output: Single-ended output, AC coupled, with adjustable offset

SHF reserves the right to change specifications and design without notice – SHF 19120 A - V002 – Mai 22, 2017

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Markers – Two markers outputs – Front panelParameterUnit

Symbol

Min.

Typ.

Max.

Comment

2.1

2.5

LVCMOS25

Amplitude

VImpedance

Ohm50

Match to 50 Ohms for best signal.

Resolution

Sample2*Sample synchronousWidthSample

11G

Maximum Repeatability

Sa

3

Maximum Frequency

MHz475Jitterps500

Adjustable Delay

Sample Clockperiods

Adjustable Delay Step

Sample Clockperiods0

A single marker will be automaticallyextended to a width of 1ns
Each marker must have a dead timeof 3 samples before the nextmarker.
With fDAC =2.85 GSa/s

600

With an even count of samples

254
2*2 samples position uncertainty when generating a repeating signal with an odd sample count period and a marker on each period.
The SHF Control Center will issue a warning when this situation happens.

Triggers – Two triggers inputs – Front panel
Parameter
TypeUnit

Symbol

Min.

Typ.

Max.

Comment

Rising edge, falling edge, gated high, gated low.

Amplitude Threshold Low

V

VIL

-0.3

0.7

LVCMOS25

Amplitude Threshold HighV

VIH

1.7

2.8

LVCMOS25

Sample Clockperiods

DelayPulse WidthFrom Trigger in to Signal present onoutput200ns1

Adjustable DelaySample Clockperiods

0Adjustable Delay Step

Sample Clockperiods

126
2

Internal reference
Parameter

Unit

FrequencyMHz

Accuracyppm

Stabilityppb

Output Level

V

Output Impedance

Ohms

Symbol

Min.

Typ.

Max.

Comment

10-1

1
280

0.6

1

Over the operational range
Over the operational range
External, back panel

50

SHF reserves the right to change specifications and design without notice – SHF 19120 A - V002 – Mai 22, 2017

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External reference input
Parameter

Unit

Frequency

MHz

Level

V

Impedance

Symbol

Min.

Typ.

Max.

Comment100.5

Ohms

3

Peak-to-Peak50

Sample clockParameter

Unit

Frequency

GHzAccuracy%

Output Level

mV

Output Impedance

Ohms

Symbol

Min.

Typ.

1.4

Max.

Comment

2.85
1200

Rear panel, Peak-to-PeakMax.

Comment

50

Sample sequencer (future software update)Parameter
Sample Granularity

Unit

SymbolSampleSample Length

Min.
1024

1G

1024

1G

Segments

1Loops1Sample Memory

Parameter

Typ.

GSa

Unit

1Symbol

Min.

Typ.

Max.

1 Sample = 14 bits + 2 Markers

Comment

General characteristics
Power Supply Voltage

V

11.6

1212.4

Power Supply Current

A

22.8

3

Power Consumption

W

Operating Temperature°C

External power adapter

361035

SHF reserves the right to change specifications and design without notice – SHF 19120 A - V002 – Mai 22, 2017

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dBc/Hz

Phase Noise Sample Clock-20-30-40-50-60-70-80-90-100-110-120-130
1101001000

Frequency Offset (KHz)
DAC clk out, fDAC=1.4 GHz

DAC clk out, fDAC=2.85 GHz

Measured on the DAC Clock SMA Output.

dBc/HzPhase Noise Direct Output-20-30-40-50-60-70-80-90-100-110
110100Frequency Offset (KHz)
730 mVpp @1MHz730 mVpp @100MHz730 mVpp @500MHz

SHF reserves the right to change specifications and design without notice – SHF 19120 A - V002 – Mai 22, 2017

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Phase Noise DC Output-20-30-40
dBc/Hz-50-60-70-80-90-100-110
110100Frequency Offset (KHz)

1 Vpp @1MHz

1 Vpp @100MHz

1 Vpp @500MHzdBc/Hz

Phase Noise AC Output-20-30-40-50-60-70-80-90-100-110
110100Frequency Offset (KHz)

0 dBm @1MHz0 dBm @100MHz

0 dBm @500MHz

SHF reserves the right to change specifications and design without notice – SHF 19120 A - V002 – Mai 22, 2017Page 11/21

BPG Outputs
Parameter

Unit

Symbol

Min.

Typ.

Max.

CommentImpedanceΩOutput Level Minimum

mV230

270

Single Ended, Peak-to-Peak, at 5Gbps

Output Level Maximum

mV

700

730

Single Ended, Peak-to-Peak, at 5Gbps

50

Output Level Steps

16Pre-Emphasis

dB

06.02

20 steps

Post-EmphasisdB

012.9631 steps

Jitter RMS

ps

5

6

At 5 Gbps, PRBS31, SQUARE2 fortrigger.

Rise/Fall Time

ps66

70

At 5 Gbps, PRBS31, SQUARE2 fortrigger.

Crossing%

5052

At 5 Gbps, full output swing.

Duty Cycle%50

Inter-Channel Skew

ps20Output pattern

At 5 Gbps, full output swing.

3020 ps max at 12.5 Gbps.

ITU-T (CCITT) conform PRBS patterns at a length of:
7910111315
20
23
31
2 -1, 2 -1, 2 -1, 2 -1, 2 -1, 2 -1, 2 -1, 2 -1, 2 -1
Additional SQUARE2 and SQUARE32 0-1 patterns: line rate divided by
2 and 32.

Bit Rate (Range 1)

Gbps

0.372

0.5

Bit Rate (Range 2)

Gbps

0.613

1

Bit Rate (Range 3)

Gbps

1.225

2

Bit Rate (Range 4)

Gbps

2.454

Bit Rate (Range 5)

Gbps4.98

Bit Rate (Range 6)Gbps

9.810.3125

Overclock up to 12.5 Gbps possible.

Bitrate resolution

Kbps

32Of internal clock cycles. 32 means
32 x (pattern length).

Wordrame Trigger Division

100

32
2.12 -1

Wordrame Trigger Level

V

Wordframe Jitterps

PRBS Clock Input Level

dBm-5

10

PRBS Clock Input Frequency

Mhz

602800Uses the AWG Trigger 2 as anoutput.

2.5

LVCMOS25

150

Peak-to-Peak
50 Ω, AC coupled
Using the internal divider

SHF reserves the right to change specifications and design without notice – SHF 19120 A - V002 – Mai 22, 2017

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Bit Rate Ranges

0.371 Gbps

1 Gbps1.225 Gbps

4 Gbps

4.9 Gbps

8 Gbps

0.5 Gbps 0.613 Gbps

9.8 Gbps

12.5 Gbps

10.3125 Gbps

2 Gbps 2.45 Gbps

Pseudo Random Binary Sequence Pattern Types
Name
7
PRBS2 -1
9
PRBS2 -1
10
PRBS2 -1
11
PRBS2 -1
13
PRBS2 -1
15
PRBS2 -1
20
PRBS2 -1
23
PRBS2 -1
31
PRBS2 -1

Polynomial
6
71+X +X
951+X +X
10
7
1+X +X
11
91+X +X
131211
81+X +X +X +X
14
151+X +X
1720
1+X +X
18
231+X +X
28
31
1+X +X

Length7
2 - 1 bits
92 - 1 bits
10
2 - 1 bits
11
2 - 1 bits
13
2 - 1 bits
15
2 - 1 bits
20
2 - 1 bits
23
2 - 1 bits
31
2 - 1 bits

SHF reserves the right to change specifications and design without notice – SHF 19120 A - V002 – Mai 22, 2017

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Typical Output Waveforms (AWG)

2.8 Gbps PAM-4 signal, DC Output

Frequency and phase synchronization of three SHF
19120 A

Edge-triggered signal generation.

Level-gated trigger signal generation.

“SHF” writing

Burst mode of three synchronized SHF 19120 A

SHF reserves the right to change specifications and design without notice – SHF 19120 A - V002 – Mai 22, 2017

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Signal with markers: marker output 1 for eachrising part of signal, marker output 2 for thesignal start.

Screenshot from the SHF Control Center preview ofthe signal shown on the left.

Multiple-Carrier Signal Noise-Power Ratio, AC
OutputMultiple-Carrier Signal Noise-Power Ratio in Double
Interpolation Mode, AC Output.
Delta marker shows the sin(x)/x bandwidth drop

Original (yellow) and AWG waveform (green)
after import. Inductor voltage of a Ćukconverter.
SHF reserves the right to change specifications and design without notice – SHF 19120 A - V002 – Mai 22, 2017

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Typical Output Waveforms (BPG)31

31

1 Gbps PRBS -1

5 Gbps PRBS -1

POST cursor = 0dB PRE cursor = 0dB, Amplitude = 715 mVpp

POST cursor = 0dB PRE cursor = 0dB, Amplitude = 715 mVpp31

31

10.3125 Gbps PRBS -1

12.5 Gbps PRBS -1

POST cursor = 0dB PRE cursor = 0dB, Amplitude = 715 mVpp

POST cursor = 0dB PRE cursor = 0dB, Amplitude = 715 mVpp

3131

10.3125 Gbps PRBS -1

12.5 Gbps PRBS -1

POST cursor = 1.6dB PRE cursor = 1.6dB, Amplitude = 635 mVpp

POST cursor = 1.6dB PRE cursor = 1.6dB, Amplitude = 635 mVpp

SHF reserves the right to change specifications and design without notice – SHF 19120 A - V002 – Mai 22, 2017

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SQUARE 2 pattern on the 5 Gbps line rate

SQUARE 2 pattern on the 10.3125 Gbps line rate

SQUARE 2 pattern on the 12.5 Gbps line rate

PRE Emphasis – Max. value (1 Gbps, PRBS -1)

7POST Emphasis – Max. value (1 Gbps, PRBS -1)

7

7

1 Bit Pattern Shift (1 Gbps, PRBS -1 ; ch1 and ch2)

SHF reserves the right to change specifications and design without notice – SHF 19120 A - V002 – Mai 22, 2017

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Software
The SHF 19120 A is operated via an Ethernet connection with the SHF Control Center software. An
embedded version of the software comes pre-installed on the instrument. It can be used without a PC, simply
by connecting an HDMI monitor, a keyboard and a mouse (USB) to the rear panel.

SHF Control Center Software

SHF reserves the right to change specifications and design without notice – SHF 19120 A - V002 – Mai 22, 2017

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SHF Control Center Software: Trigger Settings and Waveform Library pop-up

SHF Control Center Software: Waveform Editor.

SHF reserves the right to change specifications and design without notice – SHF 19120 A - V002 – Mai 22, 2017

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SHF Control Center Software: Equation Editor

SHF Control Center Software: Detail of the BPG Controls

SHF reserves the right to change specifications and design without notice – SHF 19120 A - V002 – Mai 22, 2017

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Outline Drawing

All dimensions are specified in millimeters (mm).

SHF reserves the right to change specifications and design without notice – SHF 19120 A - V002 – Mai 22, 2017

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