Allwinner A64 User Manual
Version 1.0
Mar.30,2015

Copyright© 2015 Allwinner Technology Co.,Ltd. All Rights Reserved.

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Declaration
THIS DOCUMENTATION IS THE ORIGINAL WORK AND COPYRIGHTED PROPERTY OF ALLWINNER TECHNOLOGY(“ALLWINNER”). REPRODUCTION IN WHOLE OR IN PART MUST OBTAIN THE WRITTEN APPROVAL OF ALLWINNER
AND GIVE CLEAR ACKNOWLEDGEMENT TO THE COPYRIGHT OWNER.
THE INFORMATION FURNISHED BY ALLWINNER IS BELIEVED TO BE ACCURATE AND RELIABLE. ALLWINNERRESERVES THE RIGHT TO MAKE CHANGES IN CIRCUIT DESIGN AND/OR SPECIFICATIONS AT ANY TIME WITHOUTNOTICE. ALLWINNER DOES NOT ASSUME ANY RESPONSIBILITY AND LIABILITY FOR ITS USE. NOR FOR ANY
INFRINGEMENTS OF PATENTS OR OTHER RIGHTS OF THE THIRD PARTIES WHICH MAY RESULT FROM ITS USE. NO
LICENSE IS GRANTED BY IMPLICATION OR OTHERWISE UNDER ANY PATENT OR PATENT RIGHTS OF ALLWINNER.
THIS DOCUMENTATION NEITHER STATES NOR IMPLIES WARRANTY OF ANY KIND, INCLUDING FITNESS FOR ANY
PARTICULAR APPLICATION.
THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT. CUSTOMERS SHALL BE
SOLELY RESPONSIBLE TO OBTAIN ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES. ALLWINNER SHALLNOT BE LIABLE FOR ANY LICENCE FEE OR ROYALTY DUE IN RESPECT OF ANY REQUIRED THIRD PARTY LICENCE.
ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
COVERED UNDER ANY REQUIRED THIRD PARTY LICENCE.

A64 User Manual(Revision 1.0)

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Revision History
VersionDate

Description

V1.0

Mar.30,2015

Initial Release Version

A64 User Manual(Revision 1.0)

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Table of Contents
Declaration................................................................................................................................................................. 2
Revision History ......................................................................................................................................................... 3
Table of Contents ....................................................................................................................................................... 4
Chapter 1

About This Documentation .............................................................................................................. 58

1.1.

Documentation Overview ................................................................................................................ 58

1.2.

Acronyms and Abbreviations ........................................................................................................... 58

Chapter 2

Overview .......................................................................................................................................... 60

2.1.

Processor Features ........................................................................................................................... 61
2.1.1.

CPU Architecture...................................................................................................................... 61

2.1.2.

GPU Architecture ..................................................................................................................... 61

2.1.3.

Memory Subsystem ................................................................................................................. 61

2.1.3.1. Boot ROM ........................................................................................................................ 61
2.1.3.2.

SDRAM ............................................................................................................................. 62

2.1.3.3.

NAND Flash ...................................................................................................................... 62

2.1.3.4.

SD/MMC .......................................................................................................................... 62

2.1.4.

System Peripheral .................................................................................................................... 62

2.1.4.1.

Timer ................................................................................................................................ 62

2.1.4.2. High Speed Timer............................................................................................................. 63
2.1.4.3.

RTC ................................................................................................................................... 63

2.1.4.4.

GIC ................................................................................................................................... 63

2.1.4.5.

DMA ................................................................................................................................. 63

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2.1.4.6.

CCU .................................................................................................................................. 63

2.1.4.7.

PWM ................................................................................................................................ 64

2.1.4.8.

Thermal Sensor ................................................................................................................ 64

2.1.4.9.

KEYADC ............................................................................................................................ 64

2.1.4.10. Crypto Engine(CE) .......................................................................................................... 64
2.1.4.11. Security ID ...................................................................................................................... 64
2.1.4.12. CPU Configuration ......................................................................................................... 65
2.1.5.

Display Subsystem.................................................................................................................... 65

2.1.5.1.

DE ..................................................................................................................................... 65

2.1.5.2.

Display Output ................................................................................................................. 65

2.1.6.

Video Engine ............................................................................................................................ 65

2.1.6.1.

Video Decoding ................................................................................................................ 65

2.1.6.2.

Video Encoding ................................................................................................................ 66

2.1.7.

Image In ................................................................................................................................... 66

2.1.7.1.
2.1.8.

CSI .................................................................................................................................... 66

Audio Subsystem...................................................................................................................... 66

2.1.8.1.

Audio Codec ..................................................................................................................... 66

2.1.8.2.

One Wire Audio(OWA) .................................................................................................... 67

2.1.8.3.

I2S/PCM ........................................................................................................................... 67

2.1.9.

External Peripherals ................................................................................................................. 68

2.1.9.1.

USB................................................................................................................................... 68

2.1.9.2.

EMAC ............................................................................................................................... 68

2.1.9.3.

UART ................................................................................................................................ 68

2.1.9.4.

SPI .................................................................................................................................... 68

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2.1.9.5.

Two Wire Interface(TWI) ................................................................................................. 69

2.1.9.6.

CIR .................................................................................................................................... 69

2.1.9.7.

Reduced Serial Bus(RSBTM) .............................................................................................. 69

2.1.9.8.

TS ..................................................................................................................................... 69

2.1.9.9.

SCR ................................................................................................................................... 70

2.1.10.

Package .................................................................................................................................... 70

2.2.

System Block Diagram ...................................................................................................................... 71

Chapter 3

System .............................................................................................................................................. 72

3.1.

Memory Mapping ............................................................................................................................ 73

3.2.

Boot System ..................................................................................................................................... 76

3.3.

CCU .................................................................................................................................................. 77
3.3.1.

Overview .................................................................................................................................. 77

3.3.2.

Functionalities Description ...................................................................................................... 77

3.3.2.1.

System Bus ....................................................................................................................... 77

3.3.2.2.

Bus clock tree ................................................................................................................... 79

3.3.2.3.

Module clock tree ............................................................................................................ 79

3.3.3.

Typical Applications ................................................................................................................. 81

3.3.4.

Register List .............................................................................................................................. 81

3.3.5.

Register Description ................................................................................................................. 84

3.3.5.1.

PLL_CPUX Control Register (Default Value: 0x00001000) ............................................... 84

3.3.5.2.

PLL_Audio Control Register (Default Value: 0x00035514) ............................................... 85

3.3.5.3.

PLL_VIDEO0 Control Register (Default Value: 0x03006207) ............................................ 86

3.3.5.4.

PLL_VE Control Register (Default Value: 0x03006207) .................................................... 87

3.3.5.5.

PLL_DDR0 Control Register (Default Value: 0x00001000) ............................................... 88

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3.3.5.6.

PLL_PERIPH0 Control Register (Default Value: 0x00041811)........................................... 89

3.3.5.7.

PLL_PERIPH1 Control Register (Default Value: 0x00041811)........................................... 90

3.3.5.8.

PLL_VIDEO1 Control Register (Default Value: 0x03006207) ............................................ 91

3.3.5.9.

PLL_GPU Control Register (Default Value: 0x03006207) ................................................. 92

3.3.5.10. PLL_MIPI Control Register (Default Value: 0x00000515) ............................................... 93
3.3.5.11. PLL_HSIC Control Register (Default Value: 0x03001300) ............................................... 95
3.3.5.12. PLL_DE Control Register (Default Value: 0x03006207) .................................................. 96
3.3.5.13. PLL_DDR1 Control Register (Default Value: 0x00001800) ............................................. 97
3.3.5.14. CPUX/AXI Configuration Register (Default Value: 0x00010300) .................................... 98
3.3.5.15.

AHB1/APB1 Configuration Register (Default Value: 0x00001010) ................................. 98

3.3.5.16.

APB2 Configuration Register (Default Value: 0x01000000) ........................................... 99

3.3.5.17.

AHB2 Configuration Register (Default Value: 0x00000000) ......................................... 100

3.3.5.18. Bus Clock Gating Register0 (Default Value: 0x00000000)............................................ 100
3.3.5.19. Bus Clock Gating Register1 (Default Value: 0x00000000)............................................ 102
3.3.5.20.

Bus Clock Gating Register2 (Default Value: 0x00000000)............................................ 103

3.3.5.21. Bus Clock Gating Register3 (Default Value: 0x00000000)............................................ 104
3.3.5.22. Bus Clock Gating Register4 (Default Value: 0x00000000)............................................ 105
3.3.5.23. THS Clock Register (Default Value: 0x00000000) ......................................................... 105
3.3.5.24. NAND Clock Register (Default Value: 0x00000000) ..................................................... 106
3.3.5.25.

SMHC0 Clock Register (Default Value: 0x00000000) ................................................... 107

3.3.5.26.

SMHC1 Clock Register (Default Value: 0x00000000) ................................................... 107

3.3.5.27.

SMHC2 Clock Register (Default Value: 0x00000000) ................................................... 108

3.3.5.28. TS Clock Register (Default Value: 0x00000000)............................................................ 109
3.3.5.29. CE Clock Register (Default Value: 0x00000000) ........................................................... 109
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3.3.5.30. SPI0 Clock Register (Default Value: 0x00000000) ........................................................ 110
3.3.5.31. SPI1 Clock Register (Default Value: 0x00000000) ........................................................ 110
3.3.5.32. I2S/PCM 0 Clock Register (Default Value: 0x00000000) .............................................. 111
3.3.5.33. I2S/PCM 1 Clock Register (Default Value: 0x00000000) .............................................. 112
3.3.5.34. I2S/PCM 2 Clock Register (Default Value: 0x00000000) .............................................. 112
3.3.5.35. OWA Clock Register (Default Value: 0x00000000) ....................................................... 112
3.3.5.36. USBPHY Configuration Register (Default Value: 0x00000000)..................................... 113
3.3.5.37.

DRAM Configuration Register (Default Value: 0x00000000) ....................................... 114

3.3.5.38. PLL_DDR Configuration Register (Default Value: 0xCCCA0000) .................................. 115
3.3.5.39. MBUS Reset Register (Default Value: 0x80000000) ..................................................... 115
3.3.5.40. DRAM Clock Gating Register (Default Value: 0x00000000) ......................................... 116
3.3.5.41. DE Clock Gating Register (Default Value: 0x00000000) ............................................... 116
3.3.5.42. TCON0 Clock Register (Default Value: 0x00000000) .................................................... 117
3.3.5.43. TCON1 Clock Register (Default Value: 0x00000000) .................................................... 117
3.3.5.44. DEINTERLACE Clock Register (Default Value: 0x00000000) ......................................... 117
3.3.5.45. CSI_MISC Clock Register (Default Value: 0x00000000) ................................................ 118
3.3.5.46. CSI Clock Register (Default Value: 0x00000000) .......................................................... 118
3.3.5.47. VE Clock Register (Default Value: 0x00000000) ........................................................... 119
3.3.5.48.

AC Digital Clock Register (Default Value: 0x00000000) ............................................... 119

3.3.5.49.

AVS Clock Register (Default Value: 0x00000000) ......................................................... 120

3.3.5.50. HDMI Clock Register (Default Value: 0x00000000)...................................................... 120
3.3.5.51.

HDMI Slow Clock Register (Default Value: 0x00000000) ............................................. 121

3.3.5.52.

MBUS Clock Register (Default Value: 0x00000000) ..................................................... 121

3.3.5.53.

MIPI_DSI Clock Register (Default Value: 0x00000000) ................................................ 121

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3.3.5.54. GPU Clock Register (Default Value: 0x00000000) ........................................................ 122
3.3.5.55.

PLL Stable Time Register0 (Default Value: 0x000000FF) ............................................. 122

3.3.5.56. PLL Stable Time Register1 (Default Value: 0x000000FF) ............................................. 123
3.3.5.57.

PLL_PERIPH1 Bias Register (Default Value: 0x10100010) ............................................ 123

3.3.5.58. PLL_CPUX Bias Register (Default Value: 0x08100200) ................................................. 123
3.3.5.59. PLL_AUDIO Bias Register (Default Value: 0x10100000) ............................................... 124
3.3.5.60. PLL_VIDEO0 Bias Register (Default Value: 0x10100000) ............................................. 124
3.3.5.61. PLL_VE Bias Register (Default Value: 0x10100000) ..................................................... 125
3.3.5.62.

PLL_DDR0 Bias Register (Default Value: 0x81104000)................................................. 125

3.3.5.63. PLL_PERIPH0 Bias Register (Default Value: 0x10100010) ............................................ 126
3.3.5.64. PLL_VIDEO1 Bias Register (Default Value: 0x10100000) ............................................. 126
3.3.5.65. PLL_GPU Bias Register (Default Value: 0x10100000)................................................... 126
3.3.5.66. PLL_MIPI Bias Register (Default Value: 0XF8100400) .................................................. 127
3.3.5.67.

PLL_HSIC Bias Register (Default Value: 0x10100000) .................................................. 127

3.3.5.68. PLL_DE Bias Register (Default Value: 0x10100000) ..................................................... 128
3.3.5.69. PLL_DDR1 Bias Register (Default Value: 0x10010000)................................................. 128
3.3.5.70.

PLL_CPUX Tuning Register (Default Value: 0x0A101000) ............................................ 128

3.3.5.71. PLL_DDR0 Tuning Register (Default Value: 0x14880000) ............................................ 129
3.3.5.72.

PLL_MIPI Tuning Register (Default Value: 0x8A002000) .............................................. 130

3.3.5.73.

PLL_PERIPH1 Pattern Control Register (Default Value: 0x00000000) .......................... 131

3.3.5.74.

PLL_CPUX Pattern Control Register (Default Value: 0x00000000) ............................... 131

3.3.5.75. PLL_AUDIO Pattern Control Register(Default Value: 0x00000000).............................. 132
3.3.5.76.

PLL_VIDEO0 Pattern Control Register (Default Value: 0x00000000) ........................... 132

3.3.5.77. PLL_VE Pattern Control Register (Default Value: 0x00000000) ................................... 133
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3.3.5.78.

PLL_DDR0 Pattern Control Register (Default Value: 0x00000000) .............................. 133

3.3.5.79. PLL_VIDEO1 Pattern Control Register (Default Value: 0x00000000) ........................... 134
3.3.5.80. PLL_GPU Pattern Control Register (Default Value: 0x00000000) ................................ 134
3.3.5.81. PLL_MIPI Pattern Control Register (Default Value: 0x00000000) ................................ 135
3.3.5.82.

PLL_HSIC Pattern Control Register (Default Value: 0x00000000) ................................ 136

3.3.5.83. PLL_DE Pattern Control Register (Default Value: 0x00000000) ................................... 136
3.3.5.84. PLL_DDR1 Pattern Control Register0 (Default Value: 0x00000000) ............................ 137
3.3.5.85. PLL_DDR1 Pattern Control Register1 (Default Value: 0x00000000) ............................ 137
3.3.5.86. Bus Software Reset Register 0 (Default Value: 0x00000000)....................................... 138
3.3.5.87.

Bus Software Reset Register 1 (Default Value: 0x00000000)....................................... 140

3.3.5.88. Bus Software Reset Register 2 (Default Value: 0x00000000)....................................... 141
3.3.5.89. Bus Software Reset Register 3 (Default Value: 0x00000000)....................................... 141
3.3.5.90. Bus Software Reset Register 4 (Default Value: 0x00000000)....................................... 142
3.3.5.91. CCU Security Switch Register (Default Value: 0x00000000) ........................................ 143
3.3.5.92.

PS Control Register (Default Value: 0x00000000) ........................................................ 144

3.3.5.93. PS Counter Register (Default Value: 0x00000000) ....................................................... 145
3.3.5.94. PLL Lock Control Register (Default Value: 0x00000000) .............................................. 145
3.3.6.

Programming Guidelines........................................................................................................ 146

3.3.6.1.

PLL .................................................................................................................................. 146

3.3.6.2.

BUS................................................................................................................................. 146

3.3.6.3. Clock Switch ................................................................................................................... 147
3.3.6.4. Gating and reset ............................................................................................................. 147
3.4.

CPU Configuration.......................................................................................................................... 148
3.4.1.

Overview ................................................................................................................................ 148

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3.4.2.

Block Diagram ........................................................................................................................ 148

3.4.3.

Functionalities Description .................................................................................................... 149

3.4.3.1.

Signal Description .......................................................................................................... 149

3.4.3.2.

L2 Idle Mode .................................................................................................................. 149

3.4.3.3. CPU Reset System .......................................................................................................... 149
3.4.3.4. Operation Principle ........................................................................................................ 149
3.4.4.

Register List ............................................................................................................................ 149

3.4.5.

Register Description ............................................................................................................... 150

3.4.5.1. Cluster Control Register0 (Default Value: 0x80000000) ................................................ 150
3.4.5.2. Cluster Control Register1 (Default Value: 0x00000000) ................................................ 151
3.4.5.3. Cache Parameter Control Register0 (Default Value: 0x22222222) ................................ 151
3.4.5.4. Cache Parameter Control Register1 (Default Value: 0x02022020) ................................ 152
3.4.5.5. General Control Register0 (Default Value: 0x00000010) ............................................... 152
3.4.5.6. Cluster CPU Status Register (Default Value: 0x000E0000) ............................................. 153
3.4.5.7.

L2 Status Register(Default Value: 0x00000000) ............................................................. 153

3.4.5.8. Cluster Reset Control Register (Default Value: 0x11101101) ......................................... 154
3.4.5.9.

Reset Vector Base Address Register0_L (Default Value: 0x00000000) .......................... 155

3.4.5.10. Reset Vector Base Address Register0_H (Default Value: 0x00000000)........................ 155
3.4.5.11. Reset Vector Base Address Register1_L (Default Value: 0x00000000) ........................ 155
3.4.5.12. Reset Vector Base Address Register1_H (Default Value: 0x00000000)........................ 155
3.4.5.13. Reset Vector Base Address Register2_L (Default Value: 0x00000000) ........................ 156
3.4.5.14. Reset Vector Base Address Register2_H (Default Value: 0x00000000)........................ 156
3.4.5.15. Reset Vector Base Address Register3_L (Default Value: 0x00000000) ........................ 156
3.4.5.16. Reset Vector Base Address Register3_H (Default Value: 0x00000000)........................ 156
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3.5.

System Control ............................................................................................................................... 157
3.5.1.

Overview ................................................................................................................................ 157

3.5.2.

System Control Register List ................................................................................................... 157

3.5.3.

System Control Register Description ...................................................................................... 157

3.5.3.1. Version Register ............................................................................................................. 157
3.5.3.2.
3.6.

EMAC Clock Register (Default Value: 0x00000000) ....................................................... 158

Timer.............................................................................................................................................. 159
3.6.1.

Overview ................................................................................................................................ 159

3.6.2.

Block Diagram ........................................................................................................................ 159

3.6.3.

Operation Principle ................................................................................................................ 160

3.6.3.1. Timer reload and enable bit........................................................................................... 160
3.6.3.2. Timing requirement for Timer command ...................................................................... 160
3.6.3.3. Watchdog restart ........................................................................................................... 161
3.6.4.

Timer Register List ................................................................................................................. 161

3.6.5.

Timer Register Description .................................................................................................... 161

3.6.5.1. Timer IRQ Enable Register (Default Value: 0x00000000)............................................... 161
3.6.5.2. Timer IRQ Status Register (Default Value: 0x00000000)................................................ 162
3.6.5.3. Timer 0 Control Register (Default Value: 0x00000004) ................................................. 162
3.6.5.4. Timer 0 Interval Value Register ...................................................................................... 163
3.6.5.5. Timer 0 Current Value Register ...................................................................................... 163
3.6.5.6. Timer 1 Control Register (Default Value: 0x00000004) ................................................. 164
3.6.5.7. Timer 1 Interval Value Register ...................................................................................... 165
3.6.5.8. Timer 1 Current Value Register ...................................................................................... 165
3.6.5.9.

AVS Counter Control Register (Default Value: 0x00000000).......................................... 165

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3.6.5.10.

AVS Counter 0 Register (Default Value: 0x00000000) ................................................. 166

3.6.5.11.

AVS Counter 1 Register (Default Value: 0x00000000) ................................................. 166

3.6.5.12.

AVS Counter Divisor Register (Default Value: 0x05DB05DB) ....................................... 166

3.6.5.13. Watchdog IRQ Enable Register (Default Value: 0x00000000) ...................................... 167
3.6.5.14. Watchdog Status Register (Default Value: 0x00000000).............................................. 167
3.6.5.15. Watchdog Control Register (Default Value: 0x00000000)............................................ 168
3.6.5.16. Watchdog Configuration Register (Default Value: 0x00000001) ................................. 168
3.6.5.17. Watchdog Mode Register (Default Value: 0x00000000) .............................................. 168
3.6.6.

Programming Guidelines........................................................................................................ 169

3.6.6.1. Timer .............................................................................................................................. 169
3.6.6.2. Watchdog ....................................................................................................................... 169
3.7.

R_Trusted Watchdog Timer ........................................................................................................... 170
3.7.1.

Overview ................................................................................................................................ 170

3.7.2.

Block Diagram ........................................................................................................................ 170

3.7.3.

Functionalities Description .................................................................................................... 170

3.7.3.1. TWD Reset ...................................................................................................................... 170
3.7.3.2.

NV-Counter .................................................................................................................... 171

3.7.4.

TWD Register List ................................................................................................................... 171

3.7.5.

R_TWD Register Description .................................................................................................. 172

3.7.5.1.

R_TWD Status Register (Default Value: 0x00000000).................................................... 172

3.7.5.2.

R_TWD Control Register (Default Value: 0x00000000).................................................. 172

3.7.5.3.

R_TWD Restart Register (Default Value: 0x00000000) .................................................. 173

3.7.5.4.

R_TWD Low Counter Register (Default Value: 0x00000000) ......................................... 173

3.7.5.5.

R_TWD High Counter Register (Default Value: 0x00000000) ........................................ 173

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3.7.5.6.

R_TWD Interval Value Register (Default Value: 0x00000000) ....................................... 173

3.7.5.7.

R_TWD Low Counter Compare Register (Default Value: 0x00000000) ......................... 174

3.7.5.8.

R_TWD High Counter Compare Register (Default Value: 0x00000000) ......................... 174

3.7.5.9.

Secure Storage NV-Counter Register (Default Value: 0x00000000) ............................... 174

3.7.5.10. Synchronize Data Counter Register 0 (Default Value: 0x00000000) ............................ 174
3.7.5.11. Synchronize Data Counter Register 1 (Default Value: 0x00000000) ............................ 174
3.7.5.12. Synchronize Data Counter Register 2 (Default Value: 0x00000000) ............................ 175
3.7.5.13. Synchronize Data Counter Register 3 (Default Value: 0x00000000) ............................ 175
3.8.

RTC ................................................................................................................................................. 176
3.8.1.

Overview ................................................................................................................................ 176

3.8.2.

RTC Register List ..................................................................................................................... 176

3.8.3.

RTC Register Description ........................................................................................................ 177

3.8.3.1.

LOSC Control Register (Default Value: 0x00004000)...................................................... 177

3.8.3.2.

LOSC Auto Switch Status Register (Default Value: 0x00000000) ................................... 178

3.8.3.3.

Internal OSC Clock Prescalar Register (Default Value: 0x0000000F).............................. 178

3.8.3.4.

RTC YY-MM-DD Register (Default Value: 0x00000000) .................................................. 179

3.8.3.5.

RTC HH-MM-SS Register (Default Value: 0x00000000).................................................. 179

3.8.3.6.

Alarm 0 Counter Register (Default Value: 0x00000000) ................................................ 180

3.8.3.7.

Alarm 0 Current Value Register...................................................................................... 180

3.8.3.8.

Alarm 0 Enable Register (Default Value: 0x00000000) .................................................. 180

3.8.3.9.

Alarm 0 IRQ Enable Register (Default Value: 0x00000000) ........................................... 181

3.8.3.10.

Alarm 0 IRQ Status Register (Default Value: 0x00000000) .......................................... 181

3.8.3.11.

Alarm 1 Week HH-MM-SS Register (Default Value: 0x00000000) ............................... 181

3.8.3.12.

Alarm 1 Enable Register (Default Value: 0x00000000) ................................................ 182

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3.8.3.13.

Alarm 1 IRQ Enable Register (Default Value: 0x00000000) ......................................... 183

3.8.3.14.

Alarm 1 IRQ Status Register (Default Value: 0x00000000) .......................................... 183

3.8.3.15.

Alarm Config Register (Default Value: 0x00000000).................................................... 184

3.8.3.16. LOSC Output Gating Register (Default Value: 0x00000000) ........................................ 184
3.8.3.17. General Purpose Register (Default Value: 0x00000000) .............................................. 184
3.8.3.18. GPL Hold Output Register (Default Value: 0x00000000) ............................................. 184
3.8.3.19. VDD RTC Regulation Register (Default Value: 0x00000004) ........................................ 186
3.8.3.20.

IC Characteristic Register (Default Value: 0x00000000) .............................................. 187

3.8.3.21. Crypt Configuration Register (Default Value: 0x00000000) ......................................... 187
3.8.3.22. Crypt Key Register (Default Value: 0x00000000) ......................................................... 187
3.8.3.23. Crypt Enable Register (Default Value: 0x00000000) .................................................... 187
3.9.

High-speed Timer .......................................................................................................................... 188
3.9.1.

Overview ................................................................................................................................ 188

3.9.2.

Operation Principle ................................................................................................................ 188

3.9.2.1.

HSTimer clock gating and software reset ...................................................................... 188

3.9.2.2.

HSTimer reload bit ......................................................................................................... 188

3.9.3.

HSTimer Block Diagram ......................................................................................................... 189

3.9.4.

HSTimer Register List ............................................................................................................. 189

3.9.5.

HSTimer Register Description ................................................................................................ 189

3.9.5.1.

HS Timer IRQ Enable Register (Default Value: 0x00000000) ......................................... 189

3.9.5.2.

HS Timer IRQ Status Register (Default Value: 0x00000000) .......................................... 190

3.9.5.3.

HS Timer Control Register (Default Value: 0x00000000) ............................................... 190

3.9.5.4.

HS Timer Interval Value Lo Register ............................................................................... 191

3.9.5.5.

HS Timer Interval Value Hi Register ............................................................................... 191

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3.9.5.6.

HS Timer Current Value Lo Register ............................................................................... 192

3.9.5.7.

HS Timer Current Value Hi Register ............................................................................... 192

3.9.6.
3.10.

Programming Guidelines........................................................................................................ 192

PWM .............................................................................................................................................. 193

3.10.1.

Overview ................................................................................................................................ 193

3.10.2.

PWM Block Diagram .............................................................................................................. 193

3.10.3.

PWM Register List .................................................................................................................. 194

3.10.4.

PWM Register Description ..................................................................................................... 194

3.10.4.1. PWM Control Register(Default Value: 0x00000000).................................................... 194
3.10.4.2. PWM Channel 0 Period Register .................................................................................. 195
3.11.

DMA ............................................................................................................................................... 196

3.11.1.

Overview ................................................................................................................................ 196

3.11.2.

Functionalities Description .................................................................................................... 196

3.11.2.1. Block Diagram .............................................................................................................. 196
3.11.2.2. DRQ Type and Corresponding Relation........................................................................ 197
3.11.2.3. DMA Descriptor ........................................................................................................... 197
3.11.3.

DMA Register List ................................................................................................................... 198

3.11.4.

DMA Register Description ...................................................................................................... 199

3.11.4.1. DMA IRQ Enable Register (Default Value: 0x00000000) .............................................. 199
3.11.4.2. DMA IRQ Pending Status Register0 (Default Value: 0x00000000) ............................... 201
3.11.4.3. DMA Security Register (Default Value: 0x00000000) .................................................. 203
3.11.4.4. DMA Auto Gating Register (Default Value: 0x00000000) ............................................ 204
3.11.4.5. DMA Status Register (Default Value: 0x00000000) ..................................................... 205
3.11.4.6. DMA Channel Enable Register (Default Value: 0x00000000) ...................................... 206
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3.11.4.7. DMA Channel Pause Register (Default Value: 0x00000000) ........................................ 206
3.11.4.8. DMA Channel Descriptor Address Register (Default Value: 0x00000000) ................... 206
3.11.4.9. DMA Channel Configuration Register (Default Value: 0x00000000) ........................... 207
3.11.4.10. DMA Channel Current Source Address Register (Default Value: 0x00000000) ......... 208
3.11.4.11. DMA Channel Current Destination Address Register (Default Value: 0x00000000) .. 208
3.11.4.12. DMA Channel Byte Counter Left Register (Default Value: 0x00000000) ................... 208
3.11.4.13. DMA Channel Parameter Register (Default Value: 0x00000000) .............................. 208
3.11.4.14. DMA Mode Register (Default Value: 0x00000000) .................................................... 209
3.11.4.15. DMA Former Descriptor Address Register (Default Value: 0x00000000) .................. 209
3.11.4.16. DMA Package Number Register (Default Value: 0x00000000) .................................. 209
3.12.

GIC.................................................................................................................................................. 210

3.12.1.
3.13.

Interrupt Source ..................................................................................................................... 210

Message Box .................................................................................................................................. 214

3.13.1.

Overview ................................................................................................................................ 214

3.13.2.

Functionalities Description .................................................................................................... 214

3.13.2.1. Typical Applications ...................................................................................................... 215
3.13.2.2. Functional Block Diagram ............................................................................................ 216
3.13.3.

Operation Principle ................................................................................................................ 216

3.13.3.1. Message Queue Assignment........................................................................................ 216
3.13.3.2. Interrupt request ......................................................................................................... 217
3.13.4.

Message Box Register List ...................................................................................................... 217

3.13.5.

Message Box Register Description ......................................................................................... 218

3.13.5.1. MSGBox Control Register 0(Default Value: 0x10101010) ............................................ 218
3.13.5.2. MSGBox Control Register 1(Default Value: 0x10101010) ............................................ 219
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3.13.5.3. MSGBox IRQ Enable Register u(Default Value: 0x00000000) ...................................... 220
3.13.5.4. MSGBox IRQ Status Register u(Default Value: 0x0000AAAA) ...................................... 222
3.13.5.5. MSGBox FIFO Status Register m(Default Value: 0x00000000) ..................................... 223
3.13.5.6. MSGBox Message Status Register m(Default Value: 0x00000000) .............................. 223
3.13.5.7. MSGBox Message Queue Register (Default Value: 0x00000000) ................................ 224
3.14.

Spinlock .......................................................................................................................................... 225

3.14.1.

Overview ................................................................................................................................ 225

3.14.2.

Functionalities Description .................................................................................................... 226

3.14.2.1. Typical Applications ...................................................................................................... 226
3.14.2.2. Functional Block Diagram ............................................................................................ 226
3.14.3.

Operation Principle ................................................................................................................ 227

3.14.3.1. Spinlock clock gating and software reset ..................................................................... 227
3.14.3.2. Take and free a spinlock ............................................................................................... 227
3.14.4.

Spinlock Register List.............................................................................................................. 227

3.14.5.

Spinlock Register Description................................................................................................. 228

3.14.5.1. Spinlock System Status Register (Default Value: 0x10000000) .................................... 228
3.14.5.2. Spinlock Register Status (Default Value: 0x00000000) ................................................ 228
3.14.5.3. Spinlock Lock Register N (N=0 to 31)(Default Value: 0x00000000) ............................. 228
3.14.6.
3.15.

Programming Guidelines........................................................................................................ 229

Crypto Engine................................................................................................................................. 230

3.15.1.

Overview ................................................................................................................................ 230

3.15.2.

Functionalities Description .................................................................................................... 230

3.15.2.1. Block Diagram .............................................................................................................. 230
3.15.2.2. Crypto Engine with keysram ........................................................................................ 231
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3.15.2.3. Crypto Engine Task Descriptor ..................................................................................... 233
3.15.3.

Crypto Engine Register List .................................................................................................... 236

3.15.4.

Crypto Engine Register Description ....................................................................................... 237

3.15.4.1. Crypto Engine Task Descriptor Queue Register(Default Value: 0x00000000) ............. 237
3.15.4.2. Crypto Engine Control Register(Default Value: 0x00000000) ...................................... 237
3.15.4.3. Crypto Engine Interrupt Control Register(Default Value: 0x00000000) ...................... 237
3.15.4.4. Crypto Engine Interrupt Status Register(Default Value: 0x00000000) ........................ 237
3.15.4.5. Crypto Engine Task Load Register(Default Value: 0x00000000) .................................. 238
3.15.4.6. Crypto Engine Task Status Register(Default Value: 0x00000000) ................................ 238
3.15.4.7. Crypto Engine Error Status Register(Default Value: 0x00000000)............................... 238
3.15.4.8. Crypto Engine Current Source Address Register(Default Value: 0x00000000) ............ 239
3.15.4.9. Crypto Engine Current Destination Address Register(Default Value: 0x00000000) .... 239
3.15.4.10. Crypto Engine Throughput Register(Default Value: 0x00000000)............................. 239
3.15.5.

Crypto Engine Clock Requirement ......................................................................................... 239

3.15.6.

Programming Guidelines........................................................................................................ 239

3.16.

Secure Memory Controller ............................................................................................................ 242

3.16.1.

Overview ................................................................................................................................ 242

3.16.2.

Functionalities Description .................................................................................................... 242

3.16.2.1. DRM Block Diagram ..................................................................................................... 243
3.16.2.2. Master ID Table ............................................................................................................ 243
3.16.2.3. Region Size Table.......................................................................................................... 244
3.16.2.4. Security inversion is disabled ....................................................................................... 244
3.16.2.5. Security inversion is enabled ....................................................................................... 245
3.16.3.

SMC Register List .................................................................................................................... 245

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3.16.4.

SMC Register Description ....................................................................................................... 246

3.16.4.1. SMC Configuration Register(Default Value: 0x00001F0F) ........................................... 246
3.16.4.2. SMC Action Register(Default Value: 0x00000001) ...................................................... 246
3.16.4.3. SMC Lockdown Range Register(Default Value: 0x00000000) ...................................... 247
3.16.4.4. SMC Lockdown Select Register(Default Value: 0x00000000) ...................................... 247
3.16.4.5. SMC Interrupt Status Register(Default Value: 0x00000000) ....................................... 248
3.16.4.6. SMC Interrupt Clear Register(Default Value: 0x00000000) ......................................... 248
3.16.4.7. SMC Master Bypass Register(Default Value: 0xFFFFFFFF) ........................................... 248
3.16.4.8. SMC Master Secure Register(Default Value: 0x00000000).......................................... 249
3.16.4.9. SMC Fail Address Register(Default Value: 0x00000000).............................................. 249
3.16.4.10. SMC Fail Control Register(Default Value: 0x00000000) ............................................ 249
3.16.4.11. SMC Fail ID Register(Default Value: 0x00000000) ..................................................... 250
3.16.4.12. SMC Speculation Control Register(Default Value: 0x00000000) ............................... 250
3.16.4.13. SMC Security Inversion Enable Register(Default Value: 0x00000000) ...................... 251
3.16.4.14. SMC Master Attribute Register(Default Value: 0x00000000) .................................... 251
3.16.4.15. DRM Master Enable Register(Default Value: 0x00000000) ....................................... 251
3.16.4.16. DRM Illegal Access Register(Default Value: 0x00000000) ......................................... 252
3.16.4.17.

DRM Start Address Register(Default Value: 0x00000000) ......................................... 252

3.16.4.18. DRM End Address Register(Default Value: 0x00000000) .......................................... 252
3.16.4.19. SMC Region Setup Low Register(Default Value: 0x00000000) .................................. 252
3.16.4.20.

SMC Region Setup High Register(Default Value: 0x00000000) ................................. 253

3.16.4.21. SMC Region Attributes Register(Default Value: 0x00000000) ................................... 253
3.17.

Secure Peripherals Controller ........................................................................................................ 255

3.17.1.

Overview ................................................................................................................................ 255

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3.17.2.

Functionalities Description .................................................................................................... 255

3.17.2.1. Peripherals Security Feature Table .............................................................................. 255
3.17.2.2. SPC Configuration Table ............................................................................................... 256
3.17.3.

SPC Register List ..................................................................................................................... 257

3.17.4.

SPC Register Description ........................................................................................................ 257

3.17.4.1. SPC DECPORT0 Status Register(Default Value: 0x00000000) ...................................... 257
3.17.4.2. SPC DECPORT0 Set Register(Default Value: 0x00000000) ........................................... 258
3.17.4.3. SPC DECPORT0 Clear Register(Default Value: 0x00000000) ........................................ 258
3.17.4.4. SPC DECPORT1 Status Register(Default Value: 0x00000000) ...................................... 258
3.17.4.5. SPC DECPORT1 Set Register(Default Value: 0x00000000) ........................................... 258
3.17.4.6. SPC DECPORT1 Clear Register(Default Value: 0x00000000) ........................................ 259
3.17.4.7. SPC DECPORT2 Status Register(Default Value: 0x00000000) ...................................... 259
3.17.4.8. SPC DECPORT2 Set Register(Default Value: 0x00000000) ........................................... 259
3.17.4.9. SPC DECPORT2 Clear Register(Default Value: 0x00000000) ........................................ 260

3.18.

3.17.4.10.

SPC DECPORT3 Status Register(Default Value: 0x00000000) .................................... 260

3.17.4.11.

SPC DECPORT3 Set Register(Default Value: 0x00000000) ......................................... 260

3.17.4.12.

SPC DECPORT3 Clear Register(Default Value: 0x00000000) ...................................... 261

3.17.4.13.

SPC DECPORT4 Status Register(Default Value: 0x00000000) .................................... 261

3.17.4.14.

SPC DECPORT4 Set Register(Default Value: 0x00000000) ......................................... 261

3.17.4.15.

SPC DECPORT4 Clear Register(Default Value: 0x00000000) ...................................... 261

3.17.4.16.

SPC DECPORT5 Status Register(Default Value: 0x00000000) .................................... 262

3.17.4.17.

SPC DECPORT5 Set Register(Default Value: 0x00000000) ......................................... 262

3.17.4.18.

SPC DECPORT5 Clear Register(Default Value: 0x00000000) ...................................... 262

Thermal Sensor Controller ............................................................................................................. 264

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3.18.1.

Overview ................................................................................................................................ 264

3.18.2.

Clock and Timing Requirements ............................................................................................ 264

3.18.3.

Temperature Conversion Formula ......................................................................................... 265

3.18.4.

Thermal Sensor Register List .................................................................................................. 265

3.18.5.

Thermal Sensor Register Description ..................................................................................... 265

3.18.5.1. THS Control Register0 (Default Value: 0x00000000) .................................................... 265
3.18.5.2. THS Control Register1 (Default Value: 0x00000000) .................................................... 266
3.18.5.3.

ADC calibration Data Register (Default Value: 0x00000000) ....................................... 266

3.18.5.4. THS Control Register2 (Default Value: 0x00040000) .................................................... 266
3.18.5.5. THS Interrupt Control Register (Default Value: 0x00000000) ...................................... 267
3.18.5.6. THS status Register (Default Value: 0x00000000) ........................................................ 268
3.18.5.7.

Alarm threshold Control Register0 (Default Value: 0x05a00684) ................................ 269

3.18.5.8.

Alarm threshold Control Register1 (Default Value: 0x05a00684) ................................ 269

3.18.5.9.

Alarm threshold Control Register2 (Default Value: 0x05a00684) ................................ 270

3.18.5.10. Shutdown threshold Control Register0 (Default Value: 0x04e90000) ....................... 270
3.18.5.11. Shutdown threshold Control Register1 (Default Value: 0x04e90000) ....................... 270
3.18.5.12. Shutdown threshold Control Register2 (Default Value: 0x04e90000) ....................... 270
3.18.5.13.

Average filter Control Register (Default Value: 0x00000001) .................................... 271

3.18.5.14. Thermal Sensor 0&1 calibration Data Register (Default Value: 0x08000800) ........... 271
3.18.5.15. Thermal Sensor 2 calibration Data Register (Default Value: 0x00000800) ................ 271
3.18.5.16. THS0 Data Register (Default Value: 0x00000000) ...................................................... 272
3.18.5.17. THS1 Data Register (Default Value: 0x00000000) ...................................................... 272
3.18.5.18. THS2 Data Register (Default Value: 0x00000000) ...................................................... 272
3.19.

KEYADC ........................................................................................................................................... 273

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3.19.1.

Overview ................................................................................................................................ 273

3.19.2.

Clock Source ........................................................................................................................... 273

3.19.3.

Operation Principle ................................................................................................................ 273

3.19.4.

KEY_ADC Register List ............................................................................................................ 274

3.19.5.

KEYADC Register Description ................................................................................................. 275

3.19.5.1. KEYADC Control Register (Default Value: 0x01000168) ............................................... 275
3.19.5.2. KEYADC Interrupt Control Register (Default Value: 0x00000000)................................ 276
3.19.5.3. KEYADC Interrupt Status Register (Default Value: 0x00000000).................................. 276
3.19.5.4. KEYADC Data Register (Default Value: 0x00000000).................................................... 277
3.20.

Audio Codec ................................................................................................................................... 278

3.20.1.

Overview ................................................................................................................................ 278

3.20.2.

Power and Signal Description ................................................................................................ 279

3.20.2.1.

Analog I/O Pins ............................................................................................................ 279

3.20.2.2. Filter/Reference ........................................................................................................... 279
3.20.2.3. Power/Ground ............................................................................................................. 280
3.20.3.

Data Path Diagram ................................................................................................................. 280

3.20.4.

Audio Codec Register List ....................................................................................................... 280

3.20.5.

Audio Codec Register Description .......................................................................................... 286

3.20.5.1. 0x00 I2S_AP Control Register(Default Value: 0x00000000) ......................................... 286
3.20.5.2. 0x04 I2S_AP Format Register0(Default Value: 0x0000000C) ....................................... 287
3.20.5.3. 0x08 I2S_AP Format Register1(Default Value: 0x00004020) ....................................... 288
3.20.5.4. 0x0C I2S_AP Interrupt Status Register(Default Value: 0x00000010) ........................... 289
3.20.5.5. 0x10 I2S_AP RX FIFO Register(Default Value: 0x00000000) ........................................ 290
3.20.5.6. 0x14 I2S_AP FIFO Control Register(Default Value: 0x000400F0) ................................. 290
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3.20.5.7. 0x18 I2S_AP FIFO Status Register(Default Value: 0x10800000)................................... 291
3.20.5.8. 0x1C I2S_AP DMA&Interrupt Control Register(Default Value: 0x00000000) .............. 292
3.20.5.9. 0x20 I2S_AP TX FIFO Register(Default Value: 0x00000000) ........................................ 293
3.20.5.10.

0x24 I2S_AP Clock Divide Register(Default Value: 0x00000000) ............................... 293

3.20.5.11.

0x28 I2S_AP TX Counter Register(Default Value: 0x00000000) ................................. 294

3.20.5.12.

0x2C I2S_AP RX Counter Register(Default Value: 0x00000000) ................................ 294

3.20.5.13.

0x30 I2S_AP TX Channel Select Register(Default Value: 0x00000001) ...................... 295

3.20.5.14.

0x34 I2S_AP TX Channel Mapping Register(Default Value: 0x76543210) ................. 295

3.20.5.15.

0x38 I2S_AP RX Channel Select Register(Default Value: 0x00000001) ...................... 296

3.20.5.16.

0x3C I2S_AP RX Channel Mapping Register(Default Value: 0x00003210) ................. 296

3.20.5.17.

0x200 Codec Reset Register(Default Value: 0x00000101) ......................................... 297

3.20.5.18.

0x20C System Clock Control Register(Default Value: 0x00000000) ........................... 297

3.20.5.19.

0x210 Module Clock Control Register(Default Value: 0x00000000) .......................... 298

3.20.5.20.

0x214 Module Reset Control Register(Default Value: 0x00000000).......................... 299

3.20.5.21. 0x218 System Sample rate & SRC Configuration Register(Default Value: 0x00000000)
299
3.20.5.22.

0x21C System SRC Clock Source Select Register(Default Value: 0x00000000) .......... 300

3.20.5.23.

0x220 System DVC Mode Select Register(Default Value: 0x00000000) .................... 301

3.20.5.24.

0x240 AIF1 BCLK/LRCK Control Register(Default Value: 0x00000000) ...................... 301

3.20.5.25.

0x244 AIF1 ADCDAT Control Register(Default Value: 0x00000000)........................... 302

3.20.5.26.

0x248 AIF1 DACDAT Control Register(Default Value: 0x00000000) ........................... 304

3.20.5.27.

0x24C AIF1 Digital Mixer Source Select Register(Default Value: 0x00000000).......... 305

3.20.5.28.

0x250 AIF1 Volume Control 1 Register(Default Value: 0x0000A0A0) ........................ 306

3.20.5.29.

0x254 AIF1 Volume Control 2 Register(Default Value: 0x0000A0A0) ........................ 307

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3.20.5.30.

0x258 AIF1 Volume Control 3 Register(Default Value: 0x0000A0A0) ........................ 307

3.20.5.31.

0x25C AIF1 Volume Control 4 Register(Default Value: 0x0000A0A0) ........................ 308

3.20.5.32.

0x260 AIF1 Digital Mixer Gain Control Register(Default Value: 0x00000000) ........... 309

3.20.5.33.

0x264 AIF1 Receiver Data Discarding Control Register(Default Value: 0x00000000) 309

3.20.5.34.

0x280 AIF2 BCLK/LRCK Control Register(Default Value: 0x00000000) ...................... 310

3.20.5.35.

0x284 AIF2 ADCDAT Control Register(Default Value: 0x00000000)........................... 311

3.20.5.36.

0x288 AIF2 DACDAT Control Register(Default Value: 0x00000000) ........................... 312

3.20.5.37.

0x28C AIF2 Digital Mixer Source Select Register(Default Value: 0x00000000).......... 313

3.20.5.38.

0x290 AIF2 Volume Control 1 Register(Default Value: 0x0000A0A0) ........................ 313

3.20.5.39.

0x298 AIF2 Volume Control 2 Register(Default Value: 0x0000A0A0) ........................ 314

3.20.5.40.

0x2A0 AIF2 Digital Mixer Gain Control Register(Default Value: 0x00000000) ........... 315

3.20.5.41.

0x2A4 AIF2 Receiver Data Discarding Control Register(Default Value: 0x00000000) 315

3.20.5.42.

0x2C0 AIF3 BCLK/LRCK Control Register(Default Value: 0x00000000) ...................... 315

3.20.5.43.

0x2C4 AIF3 ADCDAT Control Register(Default Value: 0x00000000) .......................... 316

3.20.5.44.

0x2C8 AIF3 DACDAT Control Register(Default Value: 0x00000000)........................... 316

3.20.5.45.

0x2CC AIF3 Signal Path Control Register(Default Value: 0x00000000) ...................... 317

3.20.5.46.

0x2E4 AIF3 Receiver Data Discarding Control Register(Default Value: 0x00000000) 318

3.20.5.47.

0x300 ADC Digital Control Register(Default Value: 0x00000000) .............................. 318

3.20.5.48.

0x304 ADC Volume Control Register(Default Value: 0x0000A0A0) ........................... 319

3.20.5.49.

0x308 ADC Debug Control Register(Default Value: 0x00000000).............................. 319

3.20.5.50.

0x310 HMIC Control 1 Register(Default Value: 0x00000020) .................................... 321

3.20.5.51.

0x314 HMIC Control 2 Register(Default Value: 0x00000000) .................................... 322

3.20.5.52.

0x318 HMIC Status Register(Default Value: 0x00000000) ......................................... 322

3.20.5.53.

0x320 DAC Digital Control Register(Default Value: 0x00000000) .............................. 323

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3.20.5.54.

0x324 DAC Volume Control Register(Default Value: 0x0000A0A0) ........................... 324

3.20.5.55.

0x328 DAC Debug Control Register(Default Value: 0x00000000) .............................. 325

3.20.5.56.

0x330 DAC Digital Mixer Source Select Register(Default Value: 0x00000000) .......... 325

3.20.5.57.

0x334 DAC Digital Mixer Gain Control Register(Default Value: 0x00000000) ........... 326

3.20.5.58.

0x400 ADC DAP Left Status Register(Default Value: 0x00000000) ............................ 326

3.20.5.59.

0x404 ADC DAP Right Status Register(Default Value: 0x00000000) .......................... 327

3.20.5.60.

0x408 ADC DAP Left Channel Control Register(Default Value: 0x00000000) ............ 327

3.20.5.61.

0x40C ADC DAP Right Channel Control Register(Default Value: 0x00000000) .......... 328

3.20.5.62.

0x410 ADC DAP Left Target Level Register(Default Value: 0x00002C28) ................... 328

3.20.5.63.

0x414 ADC DAP Right Target Level Register(Default Value: 0x00002C28) ................. 329

3.20.5.64.

0x418 ADC DAP Left High Average Coef Register(Default Value: 0x00000005) ......... 329

3.20.5.65.

0x41C ADC DAP Left Low Average Coef Register(Default Value: 0x00001EB8) ......... 329

3.20.5.66.

0x420 ADC DAP Right High Average Coef Register(Default Value: 0x00000005) ...... 329

3.20.5.67.

0x424 ADC DAP Right Low Average Coef Register(Default Value: 0x00001EB8) ....... 330

3.20.5.68.

0x428 ADC DAP Left Decay Time Register(Default Value: 0x0000001F).................... 330

3.20.5.69.

0x42C ADC DAP Left Attack Time Register(Default Value: 0x00000000) ................... 330

3.20.5.70.

0x430 ADC DAP Right Decay Time Register(Default Value: 0x0000001F) ................. 330

3.20.5.71. 0x434 ADC DAP Right Attack Time Register(Default Value: 0x00000000) ................. 331
3.20.5.72.

0x438 ADC DAP Noise Threshold Register(Default Value: 0x00001E1E) ................... 331

3.20.5.73. 0x43C ADC DAP Left Input Signal High Average Coef Register(Default Value:
0x00000005) .................................................................................................................................. 332
3.20.5.74. 0x440 ADC DAP Left Input Signal Low Average Coef Register(Default Value:
0x00001EB8) .................................................................................................................................. 332
3.20.5.75. 0x444 ADC DAP Right Input Signal High Average Coef Register(Default Value:
0x00000005) .................................................................................................................................. 332

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3.20.5.76. 0x448 ADC DAP Right Input Signal Low Average Coef Register(Default Value:
0x00001EB8) .................................................................................................................................. 332
3.20.5.77. 0x44C ADC DAP High HPF Coef Register(Default Value: 0x000000FF)....................... 333
3.20.5.78.

0x450 ADC DAP Low HPF Coef Register(Default Value: 0x0000FAC1) ....................... 333

3.20.5.79.

0x454 ADC DAP Optimum Register(Default Value: 0x00000000) .............................. 333

3.20.5.80.

0x480 DAC DAP Control Register(Default Value: 0x00000000) ................................. 334

3.20.5.81.

0x4D0 AGC Enable Register(Default Value: 0x00000000) ......................................... 334

3.20.5.82.

0x4D4 DRC Enable Register(Default Value: 0x00000000) .......................................... 335

3.20.5.83.

0x4D8 SRC Bist Control Register(Default Value: 0x00000000)................................... 336

3.20.5.84.

0x4DC SRC Bist Status Register(Default Value: 0x00000202) .................................... 337

3.20.5.85.

0x4E0 SRC1 Control 1 Register(Default Value: 0x00000000) ..................................... 338

3.20.5.86.

0x4E4 SRC1 Control 2 Register(Default Value: 0x00000000) ..................................... 338

3.20.5.87.

0x4E8 SRC1 Control 3 Register(Default Value: 0x00000040) ..................................... 338

3.20.5.88.

0x4EC SRC1 Control 4 Register(Default Value: 0x00000000) ..................................... 338

3.20.5.89.

0x4F0 SRC2 Control 1 Register(Default Value: 0x00000000) ..................................... 339

3.20.5.90.

0x4F4 SRC2 Control 2 Register(Default Value: 0x00000000) ..................................... 339

3.20.5.91.

0x4F8 SRC2 Control 3 Register(Default Value: 0x00000040) ..................................... 339

3.20.5.92.

0x4FC SRC2 Control 4 Register(Default Value: 0x00000000) ..................................... 339

3.20.5.93.

0x600 DRC0 High HPF Coef Register(Default Value: 0x000000FF)............................. 340

3.20.5.94.

0x604 DRC0 Low HPF Coef Register(Default Value: 0x0000FAC1) ............................. 340

3.20.5.95.

0x608 DRC0 Control Register(Default Value: 0x00000080) ....................................... 340

3.20.5.96. 0x60C DRC0 Left Peak Filter High Attack Time Coef Register(Default Value:
0x0000000B) .................................................................................................................................. 341
3.20.5.97. 0x610 DRC0 Left Peak Filter Low Attack Time Coef Register(Default Value:
0x000077BF) .................................................................................................................................. 342

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3.20.5.98. 0x614 DRC0 Right Peak Filter High Attack Time Coef Register(Default Value:
0x0000000B) .................................................................................................................................. 342
3.20.5.99.

0x618 DRC0 Peak Filter Low Attack Time Coef Register(Default Value: 0x000077BF)342

3.20.5.100. 0x61C DRC0 Left Peak Filter High Release Time Coef Register(Default Value:
0x000000FF) 342
3.20.5.101. 0x620 DRC0 Left Peak Filter Low Release Time Coef Register(Default Value:
0x0000E1F8) 342
3.20.5.102. 0x624 DRC0 Right Peak filter High Release Time Coef Register(Default Value:
0x000000FF) 343
3.20.5.103. 0x628 DRC0 Right Peak filter Low Release Time Coef Register(Default Value:
0x0000E1F8) 343
3.20.5.104.

0x62C DRC0 Left RMS Filter High Coef Register(Default Value: 0x00000001) ......... 343

3.20.5.105.

0x630 DRC0 Left RMS Filter Low Coef Register(Default Value: 0x00002BAF) ......... 343

3.20.5.106.

0x634 DRC0 Right RMS Filter High Coef Register(Default Value: 0x00000001)....... 343

3.20.5.107.

0x638 DRC0 Right RMS Filter Low Coef Register(Default Value: 0x00002BAF) ....... 344

3.20.5.108. 0x63C DRC0 Compressor Theshold High Setting Register(Default Value:
0x000006A4) 344
3.20.5.109. 0x640 DRC0 Compressor Theshold Low Setting Register(Default Value:
0x0000D3C0) 344
3.20.5.110.

0x644 DRC0 Compressor Slope High Setting Register(Default Value: 0x00000080) 344

3.20.5.111.

0x648 DRC0 Compressor Slope Low Setting Register(Default Value: 0x00000000) 344

3.20.5.112. 0x64C DRC0 Compressor High Output at Compressor Threshold Register(Default
Value: 0x0000F95B) ....................................................................................................................... 345
3.20.5.113. 0x650 DRC0 Compressor Low Output at Compressor Threshold Register(Default
Value: 0x00002C3F) ....................................................................................................................... 345
3.20.5.114.

0x654 DRC0 Limiter Theshold High Setting Register(Default Value: 0x000001A9) . 345

3.20.5.115.

0x658 DRC0 Limiter Theshold Low Setting Register(Default Value: 0x000034F0) .. 345

3.20.5.116.

0x65C DRC0 Limiter Slope High Setting Register(Default Value: 0x00000005) ....... 345

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A64
3.20.5.117.

0x660 DRC0 Limiter Slope Low Setting Register(Default Value: 0x00001EB8) ........ 346

3.20.5.118. 0x664 DRC0 Limiter High Output at Limiter Threshold Register(Default Value:
0x0000FBD8) 346
3.20.5.119. 0x668 DRC0 Limiter Low Output at Limiter Threshold Register(Default Value:
0x0000FBA7) 346
3.20.5.120.

0x66C DRC0 Expander Theshold High Setting Register(Default Value: 0x00000BA0)346

3.20.5.121.

0x670 DRC0 Expander Theshold Low Setting Register(Default Value: 0x00007291)346

3.20.5.122.

0x674 DRC0 Expander Slope High Setting Register(Default Value: 0x00000500) .... 347

3.20.5.123.

0x678 DRC0 Expander Slope Low Setting Register(Default Value: 0x00000000) .... 347

3.20.5.124. 0x67C DRC0 Expander High Output at Expander Threshold Register(Default Value:
0x0000F45F) 347
3.20.5.125. 0x680 DRC0 Expander Low Output at Expander Threshold Register(Default Value:
0x00008D6E) 347
3.20.5.126.

0x684 DRC0 Linear Slope High Setting Register(Default Value: 0x00000100) ......... 348

3.20.5.127.

0x688 DRC0 Linear Slope Low Setting Register(Default Value: 0x00000000).......... 348

3.20.5.128. 0x68C DRC0 Smooth filter Gain High Attack Time Coef Register(Default Value:
0x00000002) 348
3.20.5.129. 0x690 DRC0 Smooth filter Gain Low Attack Time Coef Register(Default Value:
0x00005600) 348
3.20.5.130. 0x694 DRC0 Smooth filter Gain High Release Time Coef Register(Default Value:
0x00000000) 348
3.20.5.131. 0x698 DRC0 Smooth filter Gain Low Release Time Coef Register(Default Value:
0x00000F04) 349
3.20.5.132.

0x69C DRC0 MAX Gain High Setting Register(Default Value: 0x0000FE56) ............. 349

3.20.5.133.

0x6A0 DRC0 MAX Gain Low Setting Register(Default Value: 0x0000CB0F) ............. 349

3.20.5.134.

0x6A4 DRC0 MIN Gain High Setting Register(Default Value: 0x0000F95B) ............. 349

3.20.5.135.

0x6A8 DRC0 MIN Gain Low Setting Register(Default Value: 0x00002C3F) .............. 349

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3.20.5.136. 0x6AC DRC0 Expander Smooth Time High Coef Register(Default Value:
0x00000000) 350
3.20.5.137. 0x6B0 DRC0 Expander Smooth Time Low Coef Register(Default Value: 0x0000640C)
350
3.20.5.138.

0x6B4 DRC0 Optimum Register(Default Value: 0x00000000).................................. 350

3.20.5.139.

0x6B8 DRC0 HPF Gain High Coef Register(Default Value: 0x00000100).................. 351

3.20.5.140.

0x6BC DRC0 HPF Gain Low Coef Register(Default Value: 0x00000000) .................. 351

3.20.5.141.

0x700 DRC1 High HPF Coef Register(Default Value: 0x000000FF)........................... 351

3.20.5.142.

0x704 DRC1 Low HPF Coef Register(Default Value: 0x0000FAC1) ........................... 352

3.20.5.143.

0x708 DRC1 Control Register(Default Value: 0x00000080) ..................................... 352

3.20.5.144. 0x70C DRC1 Left Peak Filter High Attack Time Coef Register(Default Value:
0x0000000B) 353
3.20.5.145. 0x710 DRC1 Left Peak Filter Low Attack Time Coef Register(Default Value:
0x000077BF) 353
3.20.5.146. 0x714 DRC1 Right Peak Filter High Attack Time Coef Register(Default Value:
0x0000000B) 354
3.20.5.147.

0x718 DRC1 Peak Filter Low Attack Time Coef Register(Default Value: 0x000077BF)354

3.20.5.148. 0x71C DRC1 Left Peak Filter High Release Time Coef Register(Default Value:
0x000000FF) 354
3.20.5.149. 0x720 DRC1 Left Peak Filter Low Release Time Coef Register(Default Value:
0x0000E1F8) 354
3.20.5.150. 0x724 DRC1 Right Peak filter High Release Time Coef Register(Default Value:
0x000000FF) 354
3.20.5.151. 0x728 DRC1 Right Peak filter Low Release Time Coef Register(Default Value:
0x0000E1F8) 355
3.20.5.152.

0x72C DRC Left RMS Filter High Coef Register(Default Value: 0x00000001) ........... 355

3.20.5.153.

0x730 DRC1 Left RMS Filter Low Coef Register(Default Value: 0x00002BAF) ......... 355

3.20.5.154.

0x734 DRC1 Right RMS Filter High Coef Register(Default Value: 0x00000001)....... 355

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3.20.5.155.

0x738 DRC1 Right RMS Filter Low Coef Register(Default Value: 0x00002BAF) ....... 355

3.20.5.156. 0x73C DRC1 Compressor Theshold High Setting Register(Default Value:
0x000006A4) 356
3.20.5.157.

0x740 DRC1 Compressor Slope High Setting Register(Default Value: 0x0000D3D0)356

3.20.5.158.

0x744 DRC1 Compressor Slope High Setting Register(Default Value: 0x00000080) 356

3.20.5.159.

0x748 DRC1 Compressor Slope Low Setting Register(Default Value: 0x00000000) 356

3.20.5.160. 0x74C DRC1 Compressor High Output at Compressor Threshold Register(Default
Value: 0x0000F95B) ....................................................................................................................... 356
3.20.5.161. 0x750 DRC1 Compressor Low Output at Compressor Threshold Register(Default
Value: 0x00002C3F) ....................................................................................................................... 357
3.20.5.162.

0x754 DRC1 Limiter Theshold High Setting Register(Default Value: 0x000001A9) . 357

3.20.5.163.

0x758 DRC1 Limiter Theshold Low Setting Register(Default Value: 0x000034F0) .. 357

3.20.5.164.

0x75C DRC1 Limiter Slope High Setting Register(Default Value: 0x00000005) ....... 357

3.20.5.165.

0x760 DRC1 Limiter Slope Low Setting Register(Default Value: 0x00001EB8) ........ 357

3.20.5.166. 0x764 DRC1 Limiter High Output at Limiter Threshold Register(Default Value:
0x0000FBD8) 358
3.20.5.167. 0x768 DRC1 Limiter Low Output at Limiter Threshold Register(Default Value:
0x0000FBA7) 358
3.20.5.168.

0x76C DRC1 Expander Theshold High Setting Register(Default Value: 0x00000BA0)358

3.20.5.169.

0x770 DRC1 Expander Theshold Low Setting Register(Default Value: 0x00007291)358

3.20.5.170.

0x774 DRC1 Expander Slope High Setting Register(Default Value: 0x00000500).... 358

3.20.5.171. 0x778 DRC1 Expander Slope Low Setting Register(Default Value: 0x00000000) .... 359
3.20.5.172. 0x77C DRC1 Expander High Output at Expander Threshold Register(Default Value:
0x0000F45F) 359
3.20.5.173. 0x780 DRC1 Expander Low Output at Expander Threshold Register(Default Value:
0x00008D6E) 359
3.20.5.174.

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0x784 DRC1 Linear Slope High Setting Register(Default Value: 0x00000100) ......... 359

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A64
3.20.5.175.

0x788 DRC1 Linear Slope Low Setting Register(Default Value: 0x00000000).......... 360

3.20.5.176. 0x78C DRC1 Smooth filter Gain High Attack Time Coef Register(Default Value:
0x00000002) 360
3.20.5.177. 0x790 DRC1 Smooth filter Gain Low Attack Time Coef Register(Default Value:
0x00005600) 360
3.20.5.178. 0x794 DRC1 Smooth filter Gain High Release Time Coef Register(Default Value:
0x00000000) 360
3.20.5.179. 0x798 DRC1 Smooth filter Gain Low Release Time Coef Register(Default Value:
0x00000F04) 360
3.20.5.180.

0x79C DRC1 MAX Gain High Setting Register(Default Value: 0x0000FE56) ............. 361

3.20.5.181.

0x7A0 DRC1 MAX Gain Low Setting Register(Default Value: 0x0000CB0F) ............. 361

3.20.5.182.

0x7A4 DRC1 MIN Gain High Setting Register(Default Value: 0x0000F95B) ............. 361

3.20.5.183.

0x7A8 DRC1 MIN Gain Low Setting Register(Default Value: 0x00002C3F) .............. 361

3.20.5.184. 0x7AC DRC1 Expander Smooth Time High Coef Register(Default Value:
0x00000000) 361
3.20.5.185. 0x7B0 DRC1 Expander Smooth Time Low Coef Register(Default Value: 0x0000640C)
362
3.20.5.186.

0x7B8 DRC1 HPF Gain High Coef Register(Default Value: 0x00000100).................. 362

3.20.5.187.

0x7BC DRC1 HPF Gain Low Coef Register(Default Value: 0x00000000) .................. 362

3.20.5.188.

AC_PR Configuration Register .................................................................................. 362

3.20.5.189.

0x00 Headphone Amplifier Control Register(Default Value: 0x00) ......................... 363

3.20.5.190.

0x01 Output Left Mixer Control Register(Default Value: 0x00) ............................... 363

3.20.5.191.

0x02 Output Right Mixer Control Register(Default Value: 0x00) ............................. 363

3.20.5.192.

0x03 Earpiece Control Register 0 (Default Value: 0x00) .......................................... 364

3.20.5.193.

0x04 Earpiece Control Register 1 (Default Value: 0x00) .......................................... 364

3.20.5.194.

0x05 LINEOUT Control Register 0 (Default Value: 0x00) .......................................... 365

3.20.5.195.

0x06 LINEOUT Control Register 1 (Default Value: 0x00) .......................................... 365

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3.20.5.196.

0x07 MIC1 Control Register (Default Value: 0x34)................................................... 365

3.20.5.197.

0x08 MIC2 Control Register (Default Value: 0x11) .................................................. 366

3.20.5.198.

0x09 Linein Control Register (Default Value: 0x03) ................................................. 366

3.20.5.199.

0x0A Mixer and DAC Control Register (Default Value: 0x00) ................................... 366

3.20.5.200.

0x0B Left ADC Mixer Control Register (Default Value: 0x00) ................................... 367

3.20.5.201.

0x0C Right ADC Mixer Control Register (Default Value: 0x00) ................................. 368

3.20.5.202.

0x0D ADC Control Register (Default Value: 0x03) .................................................... 368

3.20.5.203.

0x0E Headset Microphone Bias Control Register (Default Value: 0x21) .................. 368

3.20.5.204.

0x0F Analog Performance Tuning Register (Default Value: 0xD6) ........................... 369

3.20.5.205.

0x10 OP BIAS Control Register0 (Default Value: 0x55) ............................................ 369

3.20.5.206.

0x11 OP BIAS Control Register1 (Default Value: 0x55) ............................................ 370

3.20.5.207.

0x12 USB Bias & Volume Change Control Register (Default Value: 0x02) ............... 370

3.20.5.208.

0x13 Bias Calibration Data Register (Default Value: 0x00) ...................................... 370

3.20.5.209.

0x14 Bias Calibration Set Data Register (Default Value: 0x20) ................................ 371

3.20.5.210.

0x15 Bias & DA16 Calibration Control Register (Default Value: 0x00) ..................... 371

3.20.5.211.

0x16 Headphone PA Control Register (Default Value: 0xF1).................................... 371

3.20.5.212.

0x17 Headphone Calibration Control Register (Default Value: 0x04) ...................... 372

3.20.5.213.

0x18 Right Headphone Calibration DAT Register (Default Value: 0x00) .................. 373

3.20.5.214.

0x19 Right Headphone Calibration Setting Register (Default Value: 0x80) ............. 373

3.20.5.215.

0x1A Left Headphone Calibration DAT Register (Default Value: 0x00) .................... 373

3.20.5.216. 0x1B Left Headphone Calibration Setting Register (Default Value: 0x80) ............... 373
3.20.5.217.

0x1C Mic detect Control Register (Default Value: 0x40) .......................................... 373

3.20.5.218.

0x1D Jack & Mic detect Control Register (Default Value: 0x00) .............................. 374

3.20.5.219.

0x1E Phone Output Register (Default Value: 0x60) ................................................. 375

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A64
3.20.5.220.
3.21.

0x1F Phone Input Register (Default Value: 0x34) .................................................... 375

Port Controller(CPUx-PORT)........................................................................................................... 376

3.21.1.

Port Controller Register List ................................................................................................... 376

3.21.2.

Port Controller Register Description ...................................................................................... 377

3.21.2.1. PB Configure Register 0 (Default Value: 0x77777777) ................................................. 377
3.21.2.2. PB Configure Register 1 (Default Value: 0x00000077) ................................................. 378
3.21.2.3. PB Configure Register 2 (Default Value: 0x00000000) ................................................. 378
3.21.2.4. PB Configure Register 3 (Default Value: 0x00000000) ................................................. 378
3.21.2.5. PB Data Register (Default Value: 0x00000000) ............................................................ 379
3.21.2.6. PB Multi-Driving Register 0 (Default Value: 0x00055555) ........................................... 379
3.21.2.7. PB Multi-Driving Register 1 (Default Value: 0x00000000) ........................................... 379
3.21.2.8. PB PULL Register 0 (Default Value: 0x00000000) ........................................................ 379
3.21.2.9. PB PULL Register 1 (Default Value: 0x00000000) ........................................................ 380
3.21.2.10. PC Configure Register 0 (Default Value: 0x77777777) ............................................... 380
3.21.2.11. PC Configure Register 1 (Default Value: 0x77777777) ............................................... 381
3.21.2.12. PC Configure Register 2 (Default Value: 0x00000777) ............................................... 382
3.21.2.13. PC Configure Register 3 (Default Value: 0x00000000) ............................................... 383
3.21.2.14. PC Data Register (Default Value: 0x00000000) .......................................................... 383
3.21.2.15. PC Multi-Driving Register 0 (Default Value: 0x55555555) ......................................... 383
3.21.2.16. PC Multi-Driving Register 1 (Default Value: 0x00000015) ......................................... 383
3.21.2.17.

PC PULL Register 0 (Default Value: 0x00005140) ...................................................... 384

3.21.2.18. PC PULL Register 1 (Default Value: 0x00000014) ...................................................... 384
3.21.2.19. PD Configure Register 0 (Default Value: 0x77777777) .............................................. 384
3.21.2.20.
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PD Configure Register 1 (Default Value: 0x77777777) .............................................. 385
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A64
3.21.2.21. PD Configure Register 2 (Default Value: 0x77777777) .............................................. 387
3.21.2.22. PD Configure Register 3 (Default Value: 0x00000007) .............................................. 388
3.21.2.23. PD Data Register (Default Value: 0x00000000).......................................................... 388
3.21.2.24. PD Multi-Driving Register 0 (Default Value: 0x55555555) ......................................... 388
3.21.2.25.

PD Multi-Driving Register 1 (Default Value: 0x00015555) ......................................... 389

3.21.2.26.

PD PULL Register 0 (Default Value: 0x00000000) ...................................................... 389

3.21.2.27.

PD PULL Register 1 (Default Value: 0x00000000) ...................................................... 389

3.21.2.28. PE Configure Register 0 (Default Value: 0x77777777) ............................................... 389
3.21.2.29. PE Configure Register 1 (Default Value: 0x77777777) ............................................... 391
3.21.2.30. PE Configure Register 2 (Default Value: 0x00000077) ............................................... 392
3.21.2.31. PE Configure Register 3 (Default Value: 0x00000000) ............................................... 392
3.21.2.32. PE Data Register (Default Value: 0x00000000) .......................................................... 392
3.21.2.33. PE Multi-Driving Register 0 (Default Value: 0x55555555) ......................................... 393
3.21.2.34. PE Multi-Driving Register 1 (Default Value: 0x00000005) ......................................... 393
3.21.2.35. PE PULL Register 0 (Default Value: 0x00000000) ....................................................... 393
3.21.2.36. PE PULL Register 1 (Default Value: 0x00000000) ....................................................... 393
3.21.2.37.

PF Configure Register 0 (Default Value: 0x07777777) ............................................... 394

3.21.2.38. PF Configure Register 1 (Default Value: 0x00000000) ............................................... 395
3.21.2.39. PF Configure Register 2(Default Value: 0x00000000) ................................................ 395
3.21.2.40. PF Configure Register 3(Default Value: 0x00000000) ................................................ 395
3.21.2.41. PF Data Register (Default Value: 0x00000000) .......................................................... 395
3.21.2.42. PF Multi-Driving Register 0 (Default Value: 0x00001555) ......................................... 396
3.21.2.43. PF Multi-Driving Register 1 (Default Value: 0x00000000) ......................................... 396
3.21.2.44. PF PULL Register 0 (Default Value: 0x00000000) ....................................................... 396
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A64
3.21.2.45. PF PULL Register 1 (Default Value: 0x00000000) ....................................................... 396
3.21.2.46. PG Configure Register 0 (Default Value: 0x77777777) .............................................. 396
3.21.2.47.

PG Configure Register 1 (Default Value: 0x00777777) .............................................. 398

3.21.2.48. PG Configure Register 2 (Default Value: 0x00000000) .............................................. 399
3.21.2.49. PG Configure Register 3 (Default Value: 0x00000000) .............................................. 399
3.21.2.50. PG Data Register (Default Value: 0x00000000) ......................................................... 399
3.21.2.51.

PG Multi-Driving Register 0 (Default Value: 0x05555555) ......................................... 399

3.21.2.52.

PG Multi-Driving Register 1 (Default Value: 0x00000000) ......................................... 400

3.21.2.53.

PG PULL Register 0 (Default Value: 0x00000000) ...................................................... 400

3.21.2.54. PG PULL Register 1 (Default Value: 0x00000000) ...................................................... 400
3.21.2.55.

PH Configure Register 0 (Default Value: 0x77777777) .............................................. 400

3.21.2.56.

PH Configure Register 1 (Default Value: 0x00007777) .............................................. 401

3.21.2.57.

PH Configure Register 2 (Default Value: 0x00000000) .............................................. 402

3.21.2.58. PH Configure Register 3 (Default Value: 0x00000000) .............................................. 402
3.21.2.59.

PH Data Register (Default Value: 0x00000000).......................................................... 402

3.21.2.60. PH Multi-Driving Register 0 (Default Value: 0x00555555) ......................................... 403
3.21.2.61. PH Multi-Driving Register 1 (Default Value: 0x00000000) ......................................... 403
3.21.2.62.

PH PULL Register 0 (Default Value: 0x00000000) ...................................................... 403

3.21.2.63. PH PULL Register 1 (Default Value: 0x00000000) ...................................................... 403
3.21.2.64. PB External Interrupt Configure Register 0 (Default Value: 0x00000000) ................. 404
3.21.2.65. PB External Interrupt Configure Register 1 (Default Value: 0x00000000) ................. 404
3.21.2.66. PB External Interrupt Configure Register 2 (Default Value: 0x00000000) ................. 404
3.21.2.67.

PB External Interrupt Configure Register 3 (Default Value: 0x00000000) ................. 404

3.21.2.68. PB External Interrupt Control Register (Default Value: 0x00000000) ........................ 405
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3.21.2.69. PB External Interrupt Status Register (Default Value: 0x00000000) .......................... 405
3.21.2.70.

PB External Interrupt Debounce Register (Default Value: 0x00000000) ................... 405

3.21.2.71. PG External Interrupt Configure Register 0 (Default Value: 0x00000000) ................. 406
3.21.2.72.

PG External Interrupt Configure Register 1 (Default Value: 0x00000000) ................. 406

3.21.2.73.

PG External Interrupt Configure Register 2 (Default Value: 0x00000000) ................. 406

3.21.2.74.

PG External Interrupt Configure Register 3 (Default Value: 0x00000000) ................. 406

3.21.2.75. PG External Interrupt Control Register (Default Value: 0x00000000) ....................... 407
3.21.2.76.

PG External Interrupt Status Register (Default Value: 0x00000000) ......................... 407

3.21.2.77. PG External Interrupt Debounce Register (Default Value: 0x00000000) ................... 407
3.21.2.78.

PH External Interrupt Configure Register 0 (Default Value: 0x00000000) ................. 407

3.21.2.79.

PH External Interrupt Configure Register 1 (Default Value: 0x00000000) ................. 408

3.21.2.80. PH External Interrupt Configure Register2 (Default Value: 0x00000000) .................. 408
3.21.2.81. PH External Interrupt Configure Register3 (Default Value: 0x00000000) .................. 408
3.21.2.82.

PH External Interrupt Control Register (Default Value: 0x00000000) ....................... 408

3.21.2.83. PH External Interrupt Status Register (Default Value: 0x00000000) ......................... 409
3.21.2.84. PH External Interrupt Debounce Register (Default Value: 0x00000000) ................... 409
3.22.

Port Controller(CPUs-PORT) ........................................................................................................... 410

3.22.1.

Port Controller Register List ................................................................................................... 410

3.22.2.

Port Controller Register Description ...................................................................................... 410

3.22.2.1. PL Configure Register 0 (Default Value: 0x77777777) ................................................. 410
3.22.2.2. PL Configure Register 1 (Default Value: 0x00077777) ................................................. 412
3.22.2.3. PL Configure Register 2 (Default Value: 0x00000000) ................................................. 413
3.22.2.4. PL Configure Register 3 (Default Value: 0x00000000) ................................................. 413
3.22.2.5. PL Data Register (Default Value: 0x00000000) ............................................................ 413
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3.22.2.6. PL Multi-Driving Register 0 (Default Value: 0x01555555)............................................ 413
3.22.2.7. PL Multi-Driving Register 1 (Default Value: 0x00000000)............................................ 413
3.22.2.8. PL PULL Register 0 (Default Value: 0x00000005) ......................................................... 414
3.22.2.9. PL PULL Register 1 (Default Value: 0x00000000) ......................................................... 414
3.22.2.10. PL External Interrupt Configure Register 0 (Default Value: 0x00000000).................. 414
3.22.2.11. PL External Interrupt Configure Register 1 (Default Value: 0x00000000).................. 414
3.22.2.12. PL External Interrupt Configure Register 2 (Default Value: 0x00000000).................. 415
3.22.2.13. PL External Interrupt Configure Register 3 (Default Value: 0x00000000).................. 415
3.22.2.14. PL External Interrupt Control Register (Default Value: 0x00000000) ........................ 415
3.22.2.15. PL External Interrupt Status Register (Default Value: 0x00000000) .......................... 415
3.22.2.16. PL External Interrupt Debounce Register (Default Value: 0x00000000) .................... 416
Chapter 4

Memory ......................................................................................................................................... 417

4.1.

SDRAM ........................................................................................................................................... 417
4.1.1.

4.2.

Overview ................................................................................................................................ 417

NAND Flash Controller(NDFC) ........................................................................................................ 418
4.2.1.

Overview ................................................................................................................................ 418

4.2.2.

Block Diagram ........................................................................................................................ 419

4.2.3.

NDFC Timing Diagram ............................................................................................................ 419

4.2.4.

NDFC Operation Guide ........................................................................................................... 426

4.2.5.

NDFC Register List .................................................................................................................. 427

4.2.6.

NDFC Register Description ..................................................................................................... 428

4.2.6.1.

NDFC Control Register(Default Value: 0x00000000) ..................................................... 428

4.2.6.2.

NDFC Status Register(Default Value: 0x00000000) ....................................................... 430

4.2.6.3.

NDFC Interrupt and DMA Enable Register(Default Value: 0x00000000) ....................... 431

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4.2.6.4.

NDFC Timing Control Register(Default Value: 0x00000000) ......................................... 432

4.2.6.5.

NDFC Timing Configure Register(Default Value: 0x00000095) ..................................... 432

4.2.6.6. NDFC Address Low Word Register(Default Value: 0x00000000) ................................... 434
4.2.6.7.

NDFC Address High Word Register(Default Value: 0x00000000) .................................. 434

4.2.6.8.

NDFC Data Block Number Register(Default Value: 0x00000000) .................................. 434

4.2.6.9.

NDFC Data Counter Register(Default Value: 0x00000000) ............................................ 435

4.2.6.10. NDFC Command IO Register(Default Value: 0x00000000) .......................................... 435
4.2.6.11. NDFC Command Set Register 0(Default Value: 0x00E00530) ...................................... 437
4.2.6.12. NDFC Command Set Register 1(Default Value: 0x70008510)...................................... 437
4.2.6.13. NDFC IO Data Register(Default Value: 0x00000000) ................................................... 438
4.2.6.14. NDFC ECC Control Register(Default Value: 0x4a800008) ............................................ 438
4.2.6.15. NDFC ECC Status Register(Default Value: 0x00000000) .............................................. 439
4.2.6.16. NDFC Enhanced Feature Register(Default Value: 0x00000000) .................................. 439
4.2.6.17.

NDFC Error Counter Register 0(Default Value: 0x00000000) ...................................... 440

4.2.6.18. NDFC Error Counter Register 1(Default Value: 0x00000000) ...................................... 440
4.2.6.19. NDFC Error Counter Register 2(Default Value: 0x00000000) ...................................... 440
4.2.6.20.

NDFC Error Counter Register 3(Default Value: 0x00000000) ...................................... 441

4.2.6.21. NDFC User Data Register [n]( Default Value: 0xffffffff)................................................ 441
4.2.6.22. NDFC EFNAND STATUS Register(Default Value: 0x00000000) ..................................... 441
4.2.6.23. NDFC Spare Area Register(Default Value: 0x00000400) .............................................. 442
4.2.6.24. NDFC Pattern ID Register(Default Value: 0x00000000) ............................................... 442
4.2.6.25.

NDFC Read Data Status Control Register(Default Value: 0x01000000)....................... 442

4.2.6.26.

NDFC Read Data Status Register 0(Default Value: 0x00000000)................................. 443

4.2.6.27.

NDFC Read Data Status Register 1(Default Value: 0x00000000)................................. 443

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4.2.6.28. NDFC MBUS DMA Address Register(Default Value: 0x00000000)............................... 443
4.2.6.29. NDFC MBUS DMA Byte Counter Register(Default Value: 0x00000000) ...................... 443
4.2.6.30. NDFC Normal DMA Mode Control Register(Default Value: 0x000000A5)................... 443
4.3.

SD-MMC Host Controller ............................................................................................................... 444
4.3.1.

Overview ................................................................................................................................ 444

4.3.2.

Block Diagram ........................................................................................................................ 444

4.3.3.

SMHC Controller Timing Diagram .......................................................................................... 445

4.3.4.

SMHC Operation Description ................................................................................................. 445

4.3.4.1.

External Signal List ......................................................................................................... 445

4.3.4.2. Calibrate Delay Chain ..................................................................................................... 446
4.3.5.

SMHC DMA Controller Description ........................................................................................ 446

4.3.5.1.

IDMAC Descriptor Structure .......................................................................................... 447

4.3.5.2.

DES0 definition .............................................................................................................. 447

4.3.5.3.

DES1 definition .............................................................................................................. 448

4.3.5.4.

DES2 definition .............................................................................................................. 448

4.3.5.5.

DES3 definition .............................................................................................................. 448

4.3.6.

SMHC Register List ................................................................................................................. 448

4.3.7.

SMHC Register Description .................................................................................................... 450

4.3.7.1.

SMHC Global Control Register(Default Value: 0x00000100) ......................................... 450

4.3.7.2.

SMHC Clock Control Register(Default Value: 0x00000000) ........................................... 451

4.3.7.3.

SMHC Timeout Register (Default Value: 0xFFFFFF40) ................................................... 452

4.3.7.4.

SMHC Bus Width Register (Default Value: 0x00000000)............................................... 452

4.3.7.5.

SMHC Block Size Register (Default Value: 0x00000200)................................................ 452

4.3.7.6.

SMHC Block Count Register (Default Value: 0x00000200) ............................................ 452

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4.3.7.7.

SMHC Command Register (Default Value: 0x00000000) ............................................... 453

4.3.7.8.

SMHC Command Argument Register (Default Value: 0x00000000) .............................. 454

4.3.7.9.

SMHC Response 0 Register (Default Value: 0x00000000) ............................................. 455

4.3.7.10. SMHC Response 1 Register (Default Value: 0x00000000) ........................................... 455
4.3.7.11. SMHC Response 2 Register (Default Value: 0x00000000) ........................................... 455
4.3.7.12. SMHC Response 3 Register (Default Value: 0x00000000) ........................................... 455
4.3.7.13. SMHC Interrupt Mask Register (Default Value: 0x00000000) ..................................... 456
4.3.7.14. SMHC Masked Interrupt Status Register (Default Value: 0x00000000)....................... 457
4.3.7.15. SMHC Raw Interrupt Status Register (Default Value: 0x00000000) ............................ 458
4.3.7.16. SMHC Status Register (Default Value: 0x00000006) ................................................... 460
4.3.7.17.

SMHC FIFO Water Level Register (Default Value: 0x000F0000) .................................. 461

4.3.7.18. SMHC Function Select Register (Default Value: 0x00000000) ..................................... 462
4.3.7.19. SMHC Transferred Byte Count Register0 (Default Value: 0x00000000) ...................... 463
4.3.7.20.

SMHC Transferred Byte Count Register1 (Default Value: 0x00000000) ...................... 463

4.3.7.21. SMHC CRC Status Detect Control Register (Default Value: 0x00000003) .................... 463
4.3.7.22. SMHC Auto Command 12 Register (Default Value: 0x0000ffff) .................................. 464
4.3.7.23. SMHC NewTiming Set Register (Default Value: 0x00000000) ..................................... 464
4.3.7.24. SMHC Hardware Reset Register (Default Value: 0x00000001) .................................... 464
4.3.7.25.

SMHC DMAC Control Register (Default Value: 0x00000000) ...................................... 465

4.3.7.26.

SMHC Descriptor List Base Address Register (Default Value: 0x00000000) ................ 465

4.3.7.27.

SMHC DMAC Status Register (Default Value: 0x0000_0000) ...................................... 466

4.3.7.28. SMHC DMAC Interrupt Enable Register (Default Value: 0x00000000) ........................ 467
4.3.7.29. SMHC Card Threshold Control Register (Default Value: 0x00000000) ........................ 468
4.3.7.30. SMHC eMMC4.5 DDR Start Bit Detection Control Register (Default Value:
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0x00000000) .................................................................................................................................. 468
4.3.7.31. SMHC Response CRC Register (Default Value: 0x00000000) ....................................... 469
4.3.7.32. SMHC Data7 CRC Register (Default Value: 0x00000000)............................................. 469
4.3.7.33. SMHC Data6 CRC Register (Default Value: 0x00000000)............................................. 469
4.3.7.34. SMHC Data5 CRC Register (Default Value: 0x00000000)............................................. 470
4.3.7.35. SMHC Data4 CRC Register (Default Value: 0x00000000)............................................. 470
4.3.7.36. SMHC Data3 CRC Register (Default Value: 0x00000000)............................................. 470
4.3.7.37.

SMHC Data2 CRC Register (Default Value: 0x00000000)............................................. 471

4.3.7.38. SMHC Data1 CRC Register (Default Value: 0x00000000)............................................. 471
4.3.7.39. SMHC Data0 CRC Register (Default Value: 0x00000000)............................................. 471
4.3.7.40. SMHC CRC Status Register (Default Value: 0x00000000) ............................................ 472
4.3.7.41. SMHC Drive Delay Control Register (Default Value: 0x00000000) .............................. 472
4.3.7.42. SMHC Sample Delay Control Register (Default Value: 0x00002000) ........................... 473
4.3.7.43. SMHC Data Strobe Delay Control Register (Default Value: 0x00002000).................... 473
4.3.7.44. SMHC FIFO Register (Default Value: 0x00000000) ...................................................... 474
Chapter 5

Image ............................................................................................................................................. 475

5.1.

CSI .................................................................................................................................................. 475
5.1.1.

Overview ................................................................................................................................ 475

5.1.2.

Functionalities Description .................................................................................................... 476

5.1.2.1.

Block Diagram ................................................................................................................ 476

5.1.2.2. CSI FIFO Distribution ...................................................................................................... 477
5.1.2.3. CSI Timing ...................................................................................................................... 477
5.1.2.4. CCIR656 Header Code .................................................................................................... 478
5.1.2.5. Camera Communication Interface ................................................................................. 478
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5.1.3.

CSI Register list ....................................................................................................................... 480

5.1.4.

CSI Register Description ......................................................................................................... 481

5.1.4.1.

CSI Enable Register (Default Value: 0x00000000) ......................................................... 481

5.1.4.2.

CSI Interface Configuration Register (Default Value: 0x00000000) ............................... 482

5.1.4.3.

CSI Capture Register (Default Value: 0x00000000) ....................................................... 483

5.1.4.4.

CSI Synchronization Counter Register (Default Value: 0x00000000)............................. 484

5.1.4.5.

CSI FIFO Threshold Register (Default Value: 0x040f0400) ............................................. 484

5.1.4.6.

CSI Pattern Generation Length Register (Default Value: 0x00000000) ......................... 484

5.1.4.7.

CSI Pattern Generation Address Register (Default Value: 0x00000000)........................ 484

5.1.4.8.

CSI Version Register (Default Value: 0x00000000) ........................................................ 485

5.1.4.9.

CSI Channel_0 configuration Register (Default Value: 0x00300200)............................. 485

5.1.4.10. CSI Channel_0 scale Register (Default Value: 0x00000000) ........................................ 487
5.1.4.11. CSI Channel_0 FIFO 0 output buffer-A address Register (Default Value: 0x00000000)488
5.1.4.12. CSI Channel_0 FIFO 1 output buffer-A address Register (Default Value: 0x00000000)488
5.1.4.13. CSI Channel_0 FIFO 2 output buffer-A address Register (Default Value: 0x00000000)488
5.1.4.14. CSI Channel_0 status Register (Default Value: 0x00000000) ...................................... 488
5.1.4.15. CSI Channel_0 interrupt enable Register (Default Value: 0x00000000) ...................... 489
5.1.4.16. CSI Channel_0 interrupt status Register (Default Value: 0x00000000) ....................... 490
5.1.4.17.

CSI Channel_0 horizontal size Register (Default Value: 0x05000000) ......................... 490

5.1.4.18. CSI Channel_0 vertical size Register (Default Value: 0x01E00000) ............................. 490
5.1.4.19. CSI Channel_0 buffer length Register (Default Value: 0x01400280) ........................... 491
5.1.4.20.

CSI Channel_0 flip size Register (Default Value: 0x01E00280) .................................... 491

5.1.4.21. CSI Channel_0 frame clock counter Register (Default Value: 0x00000000) ................ 491
5.1.4.22. CSI Channel_0 accumulated and internal clock counter Register (Default Value:
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0x00000000) .................................................................................................................................. 492
5.1.4.23. CSI Channel_0 FIFO Statistic Register (Default Value: 0x00000000) ........................... 492
5.1.4.24. CSI Channel_0 PCLK Statistic Register (Default Value: 0x00007FFF) ........................... 492
5.1.4.25.

CCI Control Register (Default Value: 0x00000000) ...................................................... 493

5.1.4.26.

CCI Transmission Configuration Register (Default Value: 0x10000000) ...................... 494

5.1.4.27.

CCI Packet Format Register (Default Value: 0x00110001) ........................................... 495

5.1.4.28. CCI Bus Control Register (Default Value: 0x00002500) ............................................... 495
5.1.4.29. CCI Interrupt Control Register (Default Value: 0x00000000) ...................................... 496
5.1.4.30. CCI Line Counter Trigger Control Register (Default Value: 0x00000000) .................... 496
5.1.4.31. CCI FIFO Acess Register (Default Value: 0x00000000) ................................................. 496
Chapter 6

Display............................................................................................................................................ 498

6.1.

DE2.0 .............................................................................................................................................. 499
6.1.1.

6.2.

Overview ................................................................................................................................ 499

TCON .............................................................................................................................................. 500
6.2.1.

Overview ................................................................................................................................ 500

6.2.2.

Block Diagram ........................................................................................................................ 500

6.2.3.

Functionalities Description .................................................................................................... 501

6.2.3.1.

Panel Interface ............................................................................................................... 501

6.2.3.2.

RGB gamma correction .................................................................................................. 506

6.2.3.3. CEU module ................................................................................................................... 506
6.2.3.4. CMAP module ................................................................................................................ 507
6.2.4.

TCON0 Module Register List .................................................................................................. 507

6.2.5.

TCON0 Module Register Description ..................................................................................... 508

6.2.5.1.

TCON Global Control Register (Default Value: 0x00000000) ......................................... 508

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6.2.5.2.

TCON Global Interrupt Register0 (Default Value: 0x00000000) .................................... 509

6.2.5.3.

TCON Global Interrupt Register1 (Default Value: 0x00000000) .................................... 510

6.2.5.4.

TCON FRM Control Register0 (Default Value: 0x00000000) .......................................... 510

6.2.5.5.

TCON FRM Seed Register0 (Default Value: 0x00000000) .............................................. 511

6.2.5.6.

TCON FRM Table Register0 (Default Value: 0x00000000) ............................................. 511

6.2.5.7.

TCON 3D FIFO Register0 (Default Value: 0x00000000) ................................................. 512

6.2.5.8.

TCON0 Control Register (Default Value: 0x00000000) .................................................. 512

6.2.5.9.

TCON0 Data Clock Register (Default Value: 0x00000000) ............................................. 513

6.2.5.10. TCON0 Basic0 Register (Default Value: 0x00000000) .................................................. 514
6.2.5.11. TCON0 Basic1 Register (Default Value: 0x00000000) .................................................. 514
6.2.5.12. TCON0 Basic2 Register (Default Value: 0x00000000) .................................................. 514
6.2.5.13. TCON0 Basic3 Register (Default Value: 0x00000000) .................................................. 515
6.2.5.14. TCON0 HV Panel Interface Register (Default Value: 0x00000000) .............................. 515
6.2.5.15. TCON0 CPU Panel Interface Register (Default Value: 0x00000000) ............................ 516
6.2.5.16. TCON0 CPU Panel Write Data Register (Default Value: 0x00000000) ......................... 517
6.2.5.17.

TCON0 CPU Panel Read Data 0 Register (Default Value: 0x00000000) ....................... 517

6.2.5.18. TCON0 CPU Panel Read Data 1 Register (Default Value: 0x00000000) ....................... 518
6.2.5.19. TCON0 LVDS Panel Interface Register (Default Value: 0x00000000) ........................... 518
6.2.5.20.

TCON0 IO Polarity Register (Default Value: 0x00000000) ........................................... 519

6.2.5.21. TCON0 IO Trigger Register (Default Value: 0x0FFFFFFF) .............................................. 520
6.2.5.22. TCON CEU Control Register (Default Value: 0x00000000)........................................... 520
6.2.5.23. TCON CEU Coefficient Mul Register (Default Value: 0x00000000) .............................. 520
6.2.5.24. TCON CEU Coefficient Add Register (Default Value: 0x00000000) .............................. 521
6.2.5.25.

TCON CEU Coefficient Range Register (Default Value: 0x00000000) .......................... 521

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6.2.5.26.

TCON0 CPU Panel Trigger0 Register (Default Value: 0x00000000).............................. 521

6.2.5.27.

TCON0 CPU Panel Trigger1 Register (Default Value: 0x00000000).............................. 522

6.2.5.28. TCON0 CPU Panel Trigger2 Register (Default Value: 0x00000000).............................. 522
6.2.5.29. TCON0 CPU Panel Trigger3 Register (Default Value: 0x00000000).............................. 522
6.2.5.30. TCON0 CPU Panel Trigger4 Register (Default Value: 0x00000000).............................. 523
6.2.5.31. TCON0 CPU Panel Trigger5 Register (Default Value: 0x00000000).............................. 523
6.2.5.32. TCON Color Map Control Register (Default Value: 0x00000000) ................................ 523
6.2.5.33. TCON Color Map Odd Line0 Register (Default Value: 0x00000000) ............................ 524
6.2.5.34. TCON Color Map Odd Line1 Register (Default Value: 0x00000000) ............................ 524
6.2.5.35. TCON Color Map Even0 Register (Default Value: 0x00000000)................................... 524
6.2.5.36. TCON Color Map Even1 Register (Default Value: 0x00000000)................................... 525
6.2.5.37.

TCON Safe Period Register (Default Value: 0x00000000) ............................................ 525

6.2.5.38. TCON0 LVDS ANA0 Register (Default Value: 0x00000000) .......................................... 525
6.2.6.

TCON1 Module Register List .................................................................................................. 526

6.2.7.

TCON1 Module Register Description ..................................................................................... 527

6.2.7.1.

TCON Global Control Register (Default Value: 0x00000000) ......................................... 527

6.2.7.2.

TCON Global Interrupt Register0 (Default Value: 0x00000000) .................................... 527

6.2.7.3.

TCON Global Interrupt Register1 (Default Value: 0x00000000) .................................... 528

6.2.7.4.

TCON1 Control Register (Default Value: 0x00000000) .................................................. 528

6.2.7.5.

TCON1 Basic Timing 0 Register (Default Value: 0x00000000) ....................................... 529

6.2.7.6.

TCON1 Basic Timing 1 Register (Default Value: 0x00000000) ....................................... 529

6.2.7.7.

TCON1 Basic Timing 2 Register (Default Value: 0x00000000) ....................................... 529

6.2.7.8.

TCON1 Basic Timing 3 Register (Default Value: 0x00000000) ....................................... 530

6.2.7.9. TCON1 Basic Timing Register (Default Value: 0x00000000) .......................................... 530
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6.2.7.10. TCON1 Basic Timing 5 Register (Default Value: 0x00000000) ..................................... 530
6.2.7.11. TCON1 PS SYNC Register (Default Value: 0x00000000) ............................................... 531
6.2.7.12. TCON1 IO Polarity Register (Default Value: 0x00000000) ........................................... 531
6.2.7.13. TCON1 IO Polarity Register (Default Value: 0x0FFFFFFF) ............................................ 531
6.2.7.14. TCON CEU Control Register (Default Value: 0x00000000) ........................................... 532
6.2.7.15. TCON CEU Coefficient Mul Register (Default Value: 0x00000000) .............................. 532
6.2.7.16. TCON CEU Coefficient Add Register (Default Value: 0x00000000) .............................. 533
6.2.7.17.

TCON CEU Coefficient Rang Register (Default Value: 0x00000000) ............................ 533

6.2.7.18. TCON Safe Period Register (Default Value: 0x00000000) ............................................ 533
6.2.7.19. TCON1 Fill Control Register (Default Value: 0x00000000) .......................................... 534
6.2.7.20.

TCON1 Fill Begin Register (Default Value: 0x00000000) ............................................. 534

6.2.7.21. TCON1 Fill End Register (Default Value: 0x00000000) ................................................ 534
6.2.7.22. TCON1 Fill Data Register (Default Value: 0x00000000) ............................................... 534
Chapter 7

Interfaces ....................................................................................................................................... 535

7.1.

TWI ................................................................................................................................................. 536
7.1.1.

Overview ................................................................................................................................ 536

7.1.2.

Timing Diagram ...................................................................................................................... 536

7.1.3.

TWI Controller Special Requirement ..................................................................................... 537

7.1.3.1.

TWI Pin List .................................................................................................................... 537

7.1.3.2.

TWI Controller Operation .............................................................................................. 537

7.1.4.

TWI Controller Register List ................................................................................................... 538

7.1.5.

TWI Controller Register Description ...................................................................................... 538

7.1.5.1.

TWI Slave Address Register(Default Value: 0x00000000) ............................................. 538

7.1.5.2.

TWI Extend Address Register(Default Value: 0x00000000) .......................................... 539

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7.1.5.3.

TWI Data Register(Default Value: 0x00000000) ............................................................ 539

7.1.5.4.

TWI Control Register(Default Value: 0x00000000)........................................................ 539

7.1.5.5.

TWI Status Register(Default Value: 0x000000F8) .......................................................... 541

7.1.5.6.

TWI Clock Register(Default Value: 0x00000000) ........................................................... 542

7.1.5.7.

TWI Soft Reset Register(Default Value: 0x00000000) ................................................... 542

7.1.5.8.

TWI Enhance Feature Register(Default Value: 0x00000000)......................................... 542

7.1.5.9.

TWI Line Control Register(Default Value: 0x0000003A) ................................................ 543

7.1.5.10. TWI DVFS Register(Default Value: 0x00000000) ......................................................... 544
7.2.

SPI .................................................................................................................................................. 545
7.2.1.

Overview ................................................................................................................................ 545

7.2.2.

SPI Block Diagram .................................................................................................................. 545

7.2.3.

SPI Timing Diagram ................................................................................................................ 546

7.2.4.

SPI Pin Lists............................................................................................................................. 547

7.2.5.

SPI Register List ...................................................................................................................... 548

7.2.6.

SPI Register Description ......................................................................................................... 548

7.2.6.1.

SPI Global Control Register(Default Value: 0x00000080) .............................................. 548

7.2.6.2.

SPI Transfer Control Register(Default Value: 0x00000087) ........................................... 549

7.2.6.3.

SPI Interrupt Control Register(Default Value: 0x00000000) .......................................... 551

7.2.6.4.

SPI Interrupt Status Register(Default Value: 0x00000022) ............................................ 553

7.2.6.5.

SPI FIFO Control Register(Default Value: 0x00400001) ................................................. 554

7.2.6.6.

SPI FIFO Status Register(Default Value: 0x00000000) ................................................... 555

7.2.6.7.

SPI Wait Clock Register(Default Value: 0x00000000) .................................................... 556

7.2.6.8.

SPI Clock Control Register(Default Value: 0x00000002) ................................................ 557

7.2.6.9.

SPI Master Burst Counter Register(Default Value: 0x00000000)................................... 557

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7.2.6.10. SPI Master Transmit Counter Register(Default Value: 0x00000000) ........................... 557
7.2.6.11. SPI Master Burst Control Counter Register(Default Value: 0x00000000) .................... 558
7.2.6.12. SPI Normal DMA Mode Control Register(Default Value: 0x000000A5)....................... 559
7.2.6.13. SPI TX Data Register(Default Value: 0x00000000) ....................................................... 559
7.2.6.14. SPI RX Data Register(Default Value: 0x00000000)....................................................... 559
7.3.

UART .............................................................................................................................................. 560
7.3.1.

Overview ................................................................................................................................ 560

7.3.2.

UART Timing Diagram ............................................................................................................ 561

7.3.3.

UART Pin List .......................................................................................................................... 561

7.3.4.

UART Controller Register List ................................................................................................. 562

7.3.5.

UART Register Description ..................................................................................................... 563

7.3.5.1. UART Receiver Buffer Register(Default Value: 0x00000000) ......................................... 563
7.3.5.2. UART Transmit Holding Register(Default Value: 0x00000000) ...................................... 563
7.3.5.3. UART Divisor Latch Low Register(Default Value: 0x00000000) ..................................... 564
7.3.5.4. UART Divisor Latch High Register(Default Value: 0x00000000) .................................... 564
7.3.5.5. UART Interrupt Enable Register(Default Value: 0x00000000) ....................................... 565
7.3.5.6. UART Interrupt Identity Register(Default Value: 0x00000001) ..................................... 565
7.3.5.7. UART FIFO Control Register(Default Value: 0x00000000) ............................................. 567
7.3.5.8. UART Line Control Register(Default Value: 0x00000000) .............................................. 568
7.3.5.9. UART Modem Control Register(Default Value: 0x00000000) ........................................ 569
7.3.5.10. UART Line Status Register(Default Value: 0x00000060) .............................................. 571
7.3.5.11. UART Modem Status Register(Default Value: 0x00000000) ........................................ 573
7.3.5.12. UART Scratch Register(Default Value: 0x00000000).................................................... 575
7.3.5.13. UART Status Register(Default Value: 0x00000006) ..................................................... 575
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7.3.5.14. UART Transmit FIFO Level Register(Default Value: 0x00000000) ................................ 576
7.3.5.15. UART Receive FIFO Level Register(Default Value: 0x00000000).................................. 576
7.3.5.16. UART Halt TX Register(Default Value: 0x00000000) .................................................... 576
7.4.

CIR Receiver ................................................................................................................................... 578
7.4.1.

Overview ................................................................................................................................ 578

7.4.2.

CIR Receiver Register List ....................................................................................................... 578

7.4.3.

CIR Receiver Register Description .......................................................................................... 579

7.4.3.1. CIR Receiver Control Register(Default Value: 0x00000000) .......................................... 579
7.4.3.2. CIR Receiver Configure Register(Default Value: 0x00000004)....................................... 579
7.4.3.3. CIR Receiver FIFO Register(Default Value: 0x00000000) ............................................... 579
7.4.3.4. CIR Receiver Interrupt Control Register(Default Value: 0x00000000) ........................... 580
7.4.3.5. CIR Receiver Status Register(Default Value: 0x00000000) ............................................ 580
7.4.3.6. CIR Receiver Configure Register(Default Value: 0x00001828)....................................... 581
7.5.

USB ................................................................................................................................................. 583
7.5.1.

USB Controller Block Diagram................................................................................................ 583

7.5.2.

USB OTG ................................................................................................................................. 584

7.5.2.1. Overview ........................................................................................................................ 584
7.5.3.

USB Host ................................................................................................................................ 584

7.5.3.1. Overview ........................................................................................................................ 584
7.5.3.2. USB Host Timing Diagram .............................................................................................. 585
7.5.3.3. USB Host Register List .................................................................................................... 585
7.5.3.4.

EHCI Register Description .............................................................................................. 586

7.5.3.5. OHCI Register Description ............................................................................................. 601
7.5.3.6.

HCI Interface Control and Status Register Description .................................................. 618

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7.5.3.7. USB Host Clock Requirement ......................................................................................... 620
7.6.

I2S/PCM ......................................................................................................................................... 621
7.6.1.

Overview ................................................................................................................................ 621

7.6.2.

Signal Description .................................................................................................................. 621

7.6.2.1.

I2S/PCM Pin List ............................................................................................................. 621

7.6.2.2.

Digital Audio Interface Clock Source and Frequency ..................................................... 622

7.6.3.

Functionalities Description .................................................................................................... 622

7.6.3.1. Typical Applications ........................................................................................................ 622
7.6.3.2.

Functional Block Diagram .............................................................................................. 622

7.6.4.

Timing Diagram ...................................................................................................................... 623

7.6.5.

Operation Modes ................................................................................................................... 625

7.6.5.1.

System setup and I2S/PCM initialization ....................................................................... 625

7.6.5.2. The channel setup and DMA setup ................................................................................ 625
7.6.5.3.

Enable and disable the I2S/PCM .................................................................................... 625

7.6.6.

I2S/PCM Register List ............................................................................................................. 626

7.6.7.

I2S/PCM Register Description ................................................................................................ 626

7.6.7.1.

I2S/PCM Control Register(Default Value: 0x00060000) ................................................ 626

7.6.7.2.

I2S/PCM Format Register0 (Default Value: 0x00000033).............................................. 628

7.6.7.3.

I2S/PCM Format Register1 (Default Value: 0x00000030).............................................. 629

7.6.7.4.

I2S/PCM Interrupt Status Register(Default Value: 0x00000010) ................................... 630

7.6.7.5.

I2S/PCM RX FIFO Register(Default Value: 0x00000000) ................................................ 631

7.6.7.6.

I2S/PCM FIFO Control Register (Default Value: 0x000400F0) ....................................... 631

7.6.7.7.

I2S/PCM FIFO Status Register (Default Value: 0x10800000) ......................................... 632

7.6.7.8.

I2S/PCM DMA & Interrupt Control Register(Default Value: 0x00000000) .................... 632

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7.6.7.9.

I2S/PCM TX FIFO Register(Default Value: 0x00000000) ................................................ 633

7.6.7.10. I2S/PCM Clock Divide Register(Default Value: 0x00000000)....................................... 634
7.6.7.11. I2S/PCM TX Counter Register(Default Value: 0x00000000) ........................................ 635
7.6.7.12. I2S/PCM RX Counter Register(Default Value: 0x00000000) ........................................ 635
7.6.7.13. I2S/PCM Channel Configuration Register(Default Value: 0x00000000) ...................... 635
7.6.7.14. I2S/PCM TXn Channel Select Register(Default Value: 0x00000000) ........................... 636
7.6.7.15. I2S/PCM TXn Channel Mapping Register(Default Value: 0x00000000) ....................... 636
7.6.7.16. I2S/PCM RX Channel Select Register(Default Value: 0x00000000) ............................. 638
7.6.7.17.
7.7.

I2S/PCM RX Channel Mapping Register(Default Value: 0x00000000)......................... 638

OWA ............................................................................................................................................... 640
7.7.1.

Overview ................................................................................................................................ 640

7.7.2.

Functional Description ........................................................................................................... 640

7.7.2.1. OWA Interface Pin List ................................................................................................... 640
7.7.2.2. OWA Clock Requirement ............................................................................................... 640
7.7.2.3. OWA Block Diagram ....................................................................................................... 640
7.7.2.4. OWA Frame Format ....................................................................................................... 641
7.7.2.5. Operation Modes ........................................................................................................... 642
7.7.3.

OWA Register List ................................................................................................................... 643

7.7.4.

OWA Register Description ...................................................................................................... 644

7.7.4.1. OWA General Control Register(Default Value : 0x00000080) ........................................ 644
7.7.4.2. OWA TX Configure Register(Default Value: 0x000000F0) .............................................. 644
7.7.4.3. OWA RX Configure Register(Default Value: 0x00000000) ............................................. 645
7.7.4.4. OWA Interrupt Status Register(Default Value: 0x00000010) ......................................... 646
7.7.4.5. OWA RX FIFO Register(Default Value: 0x00000000) ...................................................... 647
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7.7.4.6. OWA FIFO Control Register(Default Value: 0x00001078) .............................................. 647
7.7.4.7. OWA FIFO Status Register(Default Value: 0x00006000) ................................................ 648
7.7.4.8. OWA Interrupt Control Register(Default Value: 0x00000000) ....................................... 648
7.7.4.9. OWA TX FIFO Register(Default Value: 0x00000000) ...................................................... 650
7.7.4.10. OWA TX Counter Register(Default Value: 0x00000000) .............................................. 650
7.7.4.11. OWA RX Counter Register(Default Value: 0x00000000) .............................................. 650
7.7.4.12. OWA TX Channel Status Register0(Default Value: 0x00000000) ................................. 650
7.7.4.13. OWA TX Channel Status Register1(Default Value: 0x00000000) ................................. 652
7.7.4.14. OWA RX Channel Status Register0(Default Value: 0x00000000) ................................. 653
7.7.4.15. OWA RX Channel Status Register1(Default Value: 0x00000000) ................................. 654
7.8.

SCR ................................................................................................................................................. 656
7.8.1.

Overview ................................................................................................................................ 656

7.8.2.

Block Diagram ........................................................................................................................ 656

7.8.3.

SCR Timing Diagram ............................................................................................................... 657

7.8.4.

SCR Special Requirement ....................................................................................................... 657

7.8.4.1. Clock Generator ............................................................................................................. 657
7.8.4.2.

SCIO Pad Configuration .................................................................................................. 658

7.8.5.

SCR Register List ..................................................................................................................... 659

7.8.6.

SCR Register Description ........................................................................................................ 659

7.8.6.1.

Smart Card Reader Control and Status Register(Default Value: 0x00000000) .............. 659

7.8.6.2.

Smart Card Reader Interrupt Enable Register(Default Value: 0x00000000).................. 661

7.8.6.3.

Smart Card Reader Interrupt Status Register(Default Value: 0x00000000) .................. 662

7.8.6.4.

Smart Card Reader FIFO Control and Status Register(Default Value: 0x00000101) ...... 663

7.8.6.5.

Smart Card Reader FIFO Counter Register(Default Value: 0x00000000) ....................... 664

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7.8.6.6.

Smart Card Reader Repeat Control Register(Default Value: 0x00000000) .................... 664

7.8.6.7.

Smart Card Reader Clock Divisor Register(Default Value: 0x00000000)........................ 665

7.8.6.8.

Smart Card Reader Line Time Register(Default Value: 0x00000000) ............................ 665

7.8.6.9.

Smart Card Reader Character Time Register(Default Value: 0x00000000) ................... 666

7.8.6.10. Smart Card Reader Line Control Register(Default Value: 0x00000000) ....................... 666
7.8.6.11. Smart Card Reader FIFO Data Register(Default Value: 0x00000000)........................... 667
7.9.

EMAC ............................................................................................................................................. 668
7.9.1.

Overview ................................................................................................................................ 668

7.9.2.

Block Diagram ........................................................................................................................ 668

7.9.3.

EMAC Core Register List ......................................................................................................... 669

7.9.4.

EMAC Core Register Description ............................................................................................ 670

7.9.4.1.

Basic Control 0 Register(Default Value: 0x00000000) ................................................... 670

7.9.4.2.

Basic Control 1 Register(Default Value: 0x08000000) ................................................... 671

7.9.4.3.

Interrupt Status Register(Default Value: 0x00000000).................................................. 671

7.9.4.4.

Interrupt Enable Register(Default Value: 0x00000000)................................................. 672

7.9.4.5. Transmit Control 0 Register(Default Value: 0x00000000).............................................. 673
7.9.4.6. Transmit Control 1 Register(Default Value: 0x00000000).............................................. 673
7.9.4.7. Transmit Flow Control Register(Default Value: 0x00000000) ........................................ 674
7.9.4.8. Transmit DMA Descriptor List Address Register(Default Value: 0x00000000)............... 675
7.9.4.9.

Receive Control 0 Register(Default Value: 0x00000000) ............................................... 675

7.9.4.10. Receive Control 1 Register(Default Value: 0x00000000) ............................................. 676
7.9.4.11. Receive DMA Descriptor List Address Register(Default Value: 0x00000000) .............. 677
7.9.4.12. Receive Frame Filter Register(Default Value: 0x00000000) ........................................ 677
7.9.4.13. Receive Hash Table 0 Register(Default Value: 0x00000000) ....................................... 678
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7.9.4.14. Receive Hash Table 1 Register(Default Value: 0x00000000) ....................................... 679
7.9.4.15. MII Command Register(Default Value: 0x00000000) .................................................. 679
7.9.4.16. MII Data Register(Default Value: 0x00000000) ........................................................... 680
7.9.4.17.

MAC Address 0 High Register(Default Value: 0x0000FFFF) ......................................... 680

7.9.4.18. MAC Address 0 Low Register(Default Value: 0xFFFFFFFF) ........................................... 680
7.9.4.19. MAC Address x High Register(Default Value: 0x0000FFFF) ......................................... 680
7.9.4.20.

MAC Address x Low Register(Default Value: 0xFFFFFFFF) ........................................... 681

7.9.4.21. Transmit DMA Status Register(Default Value: 0x00000000) ....................................... 681
7.9.4.22. Transmit DMA Current Descriptor Register(Default Value: 0x00000000) ................... 681
7.9.4.23. Transmit DMA Current Buffer Address Register(Default Value: 0x00000000)............. 681
7.9.4.24. Receive DMA Status Register(Default Value: 0x00000000) ......................................... 682
7.9.4.25.

Receive DMA Current Descriptor Register(Default Value: 0x00000000) ..................... 682

7.9.4.26.

Receive DMA Current Buffer Address Register(Default Value: 0x00000000) .............. 682

7.9.4.27.

RGMII Status Register(Default Value: 0x00000000) .................................................... 682

7.9.5.

EMAC RX/TX Descriptor ......................................................................................................... 683

7.9.5.1. Transmit Descriptor ........................................................................................................ 683
7.9.5.2.
7.10.

Receive Descriptor ......................................................................................................... 685

TSC ................................................................................................................................................. 687

7.10.1.

Overview ................................................................................................................................ 687

7.10.2.

Transport Stream Input Timing Diagram ............................................................................... 688

7.10.3.

Transport Stream Controller Register List .............................................................................. 690

7.10.4.

Transport Stream Controller Register Description ................................................................. 691

7.10.4.1. TSC Control Register(Default Value: 0x00000000)....................................................... 691
7.10.4.2. TSC Status Register(Default Value: 0x00000000) ......................................................... 691
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7.10.4.3. TSC Port Control Register(Default Value: 0x00000000) ............................................... 691
7.10.4.4. TSC Port Parameter Register(Default Value: 0x00000000) .......................................... 691
7.10.4.5. TSC TSF Input Multiplex Control Register(Default Value: 0x00000000) ....................... 692
7.10.4.6. TSC Port Output Multiplex Control Register(Default Value: 0x00000000) ................... 692
7.10.4.7. TSC Port Output Multiplex Control Register(Default Value: 0x00000000) ................... 693
7.10.4.8. TSG Packet Parameter Register(Default Value: 0x00470000) ...................................... 694
7.10.4.9. TSG Interrupt Enable and Status Register(Default Value: 0x00000000) ...................... 694
7.10.4.10. TSG Clock Control Register(Default Value: 0x00000000) ........................................... 695
7.10.4.11. TSG Buffer Base Address Register(Default Value: 0x00000000) ................................ 695
7.10.4.12. TSG Buffer Size Register(Default Value: 0x00000000) ............................................... 696
7.10.4.13. TSG Buffer Point Register(Default Value: 0x00000000) ............................................. 696
7.10.4.14. TSF Control and Status Register(Default Value: 0x00000000) ................................... 696
7.10.4.15. TSF Packet Parameter Register(Default Value: 0x00470000) ..................................... 696
7.10.4.16. TSF Interrupt Enable and Status Register(Default Value: 0x00000000) ..................... 697
7.10.4.17. TSF DMA Interrupt Enable Register(Default Value: 0x00000000) .............................. 698
7.10.4.18. TSF Overlap Interrupt Enable Register(Default Value: 0x00000000) ......................... 698
7.10.4.19. TSF DMA Interrupt Status Register(Default Value: 0x00000000) ............................... 699
7.10.4.20. TSF Overlap Interrupt Status Register(Default Value: 0x00000000) .......................... 699
7.10.4.21. TSF PCR Control Register(Default Value: 0x00000000) .............................................. 699
7.10.4.22. TSF PCR Data Register(Default Value: 0x00000000) .................................................. 700
7.10.4.23. TSF Channel Enable Register(Default Value: 0x00000000) ........................................ 700
7.10.4.24. TSF PES Enable Register(Default Value: 0x00000000)................................................ 700
7.10.4.25. TSF Channel Descramble Enable Register(Default Value: 0x00000000) .................... 700
7.10.4.26. TSF Channel Index Register(Default Value: 0x00000000) .......................................... 701
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7.10.4.27. TSF Channel Control Register(Default Value: 0x00000000) ....................................... 701
7.10.4.28. TSF Channel Status Register(Default Value: 0x00000000) ......................................... 701
7.10.4.29. TSF Channel CW Index Register(Default Value: 0x00000000) .................................... 701
7.10.4.30. TSF Channel PID Register(Default Value: 0x1FFF0000) .............................................. 702
7.10.4.31. TSF Channel Buffer Base Address Register(Default Value: 0x00000000) ................... 702
7.10.4.32. TSF Channel Buffer Size Register(Default Value: 0x00000000) .................................. 702
7.10.4.33. TSF Channel Write Pointer Register(Default Value: 0x00000000) ............................. 703
7.10.4.34. TSF Channel Read Pointer Register(Default Value: 0x00000000) .............................. 703
7.10.4.35. TSD Control Register(Default Value: 0x00000000)..................................................... 703
7.10.4.36. TSD Status Register(Default Value: 0x00000000)....................................................... 703
7.10.4.37. TSD Control Word Index Register(Default Value: 0x00000000) ................................. 704
7.10.4.38. TSD Control Word Register(Default Value: 0x00000000) ........................................... 704
Appendix ................................................................................................................................................................ 705

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About This Documentation

Chapter 1 About This Documentation
1.1. Documentation Overview
This documentation provides an overall description of the Allwinner quad-core A64 application processor,
which will provide instructions to programmers from several sections, including overview,system,memory,
image,display and interfaces.

1.2. Acronyms and Abbreviations
The table below contains acronyms and abbreviations used in this document.
AES

Advanced Encryption Standard

ADC

Analog-to-digital converter

AGC

Automatic Gain Control

AHB

AMBA High-speed Bus

APB

Advanced Peripheral Bus

ARM

Advanced RISC Machine

AVS

Audio Video Standard

CIR

Consumer Infrared

CP15

Coprocessor 15

CPU

Central processing unit

CRC

Cyclic Redundancy Check

CSI

Camera Serial Interface

DES

Data Encryption Standard

DLL

Delay-Locked Loop

DMA

Direct Memory Access

DRC

Dynamic Range Compression

DSI

MIPI Display Serial Interface

DVFS

Dynamic Voltage and Frequency Scaling

eFuse

Electrical Fuse,A one-time programmable memory

EHCI

Enhanced Host Controller Interface

eMMC

Embedded Multi-Media CardFBGA

Fine Ball Grid ArrayFIFOFirst in First out

GIC

Generic Interrupt Controller

GPIO

General Purpose Input Output

HDMI

High-Definition Multimedia Interface

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About This Documentation
I2S

Inter IC SoundJEDEC

Joint Electron Device Engineering Council

JPEG

Joint Photographic Experts GroupJTAG

Joint Test Action GroupKEYADC

Analog to Digital Converter

LCD

Liquid-Crystal Display

LSB

Least Significant Bit

LVDS

Low Voltage Differential Signaling

MAC

Media Access Control

MII

Media Independent Interface

MIPI

Mobile Industry Processor Interface

MIPI DSIMIPI Display Serial Interface

MMC

Multimedia Card

MPEG

Motion Pictures Expert GroupMPEG1The First MPEG Compression Scheme Specification

MPEG4

The Most Current MPEG Compression Scheme Specification

MSB

Most Significant Bit

NTSC

National Television System Committee

OHCI

Open Host Controller Interface

OWA

One Wire Audio

PAL

Phase Alternating LinePCM

Pulse Code Modulation

PHY

Physical Layer Controller

PID

Packet Identifier

PLL

Phase-Locked LoopTM

RSB

Reduced Serial Bus

SDIO

Secure Digital Input Output

SOC

System on a chip

SPI

Serial Peripheral Interface

TWI

Two Wire Interface

USB OTG

Universal Serial Bus On The Go

UART

Universal Asynchronous Receiver Transmitter
Transmitter

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Page 59Overview

Chapter 2 Overview
Allwinner’s A64 is a quad-core,64bit SoC targeted for high performance tablets.A64 integrates a higher energy
efficiency ARM Cortex-A53 CPU architecture, and also includes advanced 3D graphics processing unit,
high-definition video encoding/decoding, low power audio codec, excellent display controllers and a broad
range of interfaces.
The processor has some very exciting features:CPU Quad-core ARM Cortex-A53 Processor, a power-efficient ARM v8 architecture, it has 64 and 32bit
execution states for scalable high performance ,which includes a NEON multimedia processing engine.
Graphics ARM Mali400MP2 graphics acceleration provides mobile users with superior experience in web
browsing, video playback and gaming effects; OpenGL ES2.0 ,OpenVG1.1 standards are supported.
Video A64 provides almost full motion playback of up to 4K high-definition video, and supports H.265
decoder by 4K@30fps , H.264 decoder by 1080p@60fps, MPEG1/2/4 decoder by 1080p@60fps, VP8 decoder by
1080p@60fps, AVS/AVS+ decoder by 1080p@60fps,VC1 decoder by 1080p@30fps, H.264 encoder by
1080p@60fps with dedicated hardware.

Audio An integrated audio subsystem delivers extremely low power audio playback and exceptional highquality sound.

Display A64 features Allwinner’s SmartColor2.0TM technology with an integrated display engine. Content
can be displayed on 4-lane MIPI DSI displays up to 1920x1200@60fps, or a RGB panel interface up to
1920x1200@60fps, or LVDS panel up to 1366x768@60fps , or HDMI v1.4 is also supported up to 4K@30fps.
External Memory Many types of external memory devices are supported, including LPDDR2, LPDDR3,
DDR2, DDR3 ,DDR3L, NAND Flash(MLC,SLC,TLC,EF),Nor Flash, SD/SDIO/MMC including eMMC up to rev5.0,and
also supports booting from RAW NAND,eMMC,SD/TF Card or Nor Flash.
Security A64 delivers hardware security features that enable trustzone security system, Digital Rights
Management(DRM), information encryption/decryption, secure boot, secure JTAG and secure efuse.
Connectivity A64 has a broad range of hardware interfaces such as parallel CMOS sensor interface,
10/100/1000Mbps EMAC,USB OTG v2.0 operating at high speed(480Mbps) with PHY, USB Host with PHY and avariety of other popular interfaces(SPI,UART,CIR,TS,TWI,RSB,SCR).

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Overview

2.1. Processor Features
2.1.1. CPU ArchitectureQuad-core ARM Cortex-A53 Processor
A power-efficient ARM v8 architecture
64 and 32bit execution states for scalable high performance
Trustzone technology supported
3~10x better software encryption performanceSupport NEON Advanced SIMD(Single Instruction Multiple Data)instruction for acceleration of media andsignal processing functionsSupport Large Physical Address Extensions(LPAE)

VFPv4 Floating Point Unit32KB L1 Instruction cache and 32KB L1 Data cache
512KB L2 cache

2.1.2. GPU Architecture

ARM Mali400MP2 GPU
Support OpenGL ES 2.0 and OpenVG 1.1 standard

2.1.3. Memory Subsystem
2.1.3.1. Boot ROM





•

On-chip memory
Size:112KB(non secure ROM:48KB,secure ROM:64KB)
Support secure and non-secure access bootSupport system boot from the following devices:- NAND Flash- SD/TF card
- eMMC- Nor Flash
Support system code download through USB OTG

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2.1.3.2. SDRAM








Compatible with JEDEC standard DDR2/DDR3/DDR3L/LPDDR2/LPDDR3 SDRAM
Support clock frequency up to 667MHz(DDR3-1333)
Up to 3GB address space
Support 2 chip select16 address signal lines and 3 bank signal lines
32-bits data width
Support Memory Dynamic Frequency Scale(MDFS)

2.1.3.3. NAND Flash









Up to 2 flash chips
8-bit data bus width
Up to 64-bit ECC per 1024 bytes
Support 1024, 2048, 4096, 8192, 16K bytes size per page
Support SLC/MLC/TLC flash and EF-NAND memory
Support SDR, ONFI DDR and Toggle DDR NAND
Embedded DMA to do data transfer
Support data transfer together with normal DMA

2.1.3.4. SD/MMC
Up to three SD/MMC controller interfacesComply to eMMC standard specification V5.0, SD physical layer specification V2.0, SDIO card specification
V3.0
1-bit or 4-bit data bus transfer mode for SD cards

1-bit or 4-bit data bus transfer mode for SDIO interface
1-bit ,4-bit or 8-bit data bus transfer mode for MMC cards
Embedded special DMA to do data transfer
Support hardware CRC generation and error detection

2.1.4. System Peripheral
2.1.4.1. Timer

Two on-chip timers with interrupt-based operation
One watchdogs to generate reset signal or interrupts
Two AVS Counter to synchronize video and audio in the player

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24MHz or 32KHz clock input

2.1.4.2. High Speed Timer

One high speed timer with 56bit counter
Clock source is synchronized with AHB1 clock, much more accurate than other timers

2.1.4.3. RTCCalendar :Counters second,minutes,hours,day,week,month and year with leap year generator
Alarm:general alarm and weekly alarm
One 32768Hz fanout

2.1.4.4. GIC
Support 16 Software Generated Interrupts(SGIs), 16 Private Peripheral Interrupts(PPIs) and 125 Shared
Peripheral Interrupts(SPIs)

2.1.4.5. DMA






Up to 8-channels DMA
Interrupt generated for each DMA channel
Flexible data width of 8/16/32/64-bits
Support linear and IO address modes
Support data transfer types with memory-to-memory, memory-to-peripheral, peripheral-to-memory

2.1.4.6. CCU






13 PLLs
One on-chip RC oscillator
Support a external 24MHz oscillator and a external32.768KHz oscillator
Support clock configuration and clock generated for corresponding modules
Support software-controlled clock gating and software-controlled reset for corresponding modules

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Overview
2.1.4.7. PWMSupport outputting two kinds of waveform: continuous waveform and pulse waveform
0% to 100% adjustable duty cycle
Up to 24MHz output frequency

2.1.4.8. Thermal Sensor
Temperature Accuracy : ±3℃ from 0℃ to +100℃, ±5℃ from -20℃ to +125℃
Support over-temperature protection interrupt and over-temperature alarm interrupt
Averaging filter for thermal sensor reading
Support 3 sensors:sensor0 for CPU,sensor1/2 for GPU

2.1.4.9. KEYADC

ADC with 6-bit resolution for key
Support hold key and continuous key
Support single key, normal key and continuous key

2.1.4.10. Crypto Engine(CE)









Support Symmetrical algorithm: AES,DES,TDES
Support AES 128/192/256-bits with ECB,CBC,CTS,CTR mode
Support DES/TDES with ECB,CBC,CTR mode
Support Hash algorithm: MD5,SHA1,SHA224,SHA256,HMAC
Support Asymmetrical algorithm:RSA512/1024/2048bit
Support 160-bits hardware PRNG with 175-bits seed
Support 256-bits hardware TRNGInternal Embedded DMA to do data transfer
Support secure and non-secure interfaces respectively

2.1.4.11. Security ID
Support 2K-bits EFUSE for chip ID and security application

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2.1.4.12. CPU ConfigurationSupport power clamp
Flexible CPU configuration

2.1.5. Display Subsystem
2.1.5.1. DEOutput size up to 4096x4096
Support four alpha blending channel for main display, two channel for aux display
Support four overlay layers in each channel, and has a independent scalerSupport potter-duff compatible blending operation
Support input format YUV422/YUV420/YUV411/ARGB8888/XRGB8888/RGB888/ARGB4444/ARGB1555 and
RGB565Support Frame Packing/Top-and-Bottom/Side-by-side Full/Side-by-Side Half 3D format dataSupport SmartColorTM 2.0 for excellent display experience- Adaptive edge sharping- Adaptive color enhancement- Adaptive contrast enhancement and fresh tone rectifySupport writeback and rotation for high efficient dual display and miracast

2.1.5.2. Display Output






Support LVDS interface with single link, up to 1366x768@60fps
Support RGB interface with DE/SYNC mode, up to 1920x1200@60fps
Dither function from RGB666/RGB565 to RGB888
Support 4-lanes MIPI DSI up to 1920x1200@60fps
Support HDMI1.4 with HDCP1.2 up to 4K@30fps

2.1.6. Video Engine
2.1.6.1. Video DecodingSupport multi-format video playback, including:- H.265:4K@30fps- H.264:1080p@60fps- MPEG1/2/4:1080p@60fps

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Overview- VP8:1080p@60fps- VC1:1080p@30fps- AVS/AVS+: 1080p@60fps- JPEG/MJPEG:1080p@30fps
Support 1080P blu-ray 3D
Support frame compatible 3D format,size:3840x1080,1920x2160

2.1.6.2. Video EncodingSupport H.264 video encoding up to 1080p@60fps

JPEG baseline: picture size up to 8192x8192
Support input format: YU12/YV12/NV12/NV21/YUYV/YVYU/UYVY/VYUY/ARGB/BGRA/RGBA/ABGR/YU16/YV16/TILE32/TILE128
Support Alpha blendingSupport thumb generation
Support 4x2 scaling ratio: from 1/16 to 64 arbitrary non-integer ratioSupport rotated input

2.1.7. Image In
2.1.7.1. CSISupport 8bit YUV422 CMOS sensor interface
Support CCIR656 protocol for NTSC and PAL
Maximum still capture resolution to 5M
Maximum video capture resolution to 1080p@30fps

2.1.8. Audio Subsystem
2.1.8.1. Audio Codec







Two audio digital-to-analog(DAC) channels
Stereo capless headphone drivers:- 100dB SNR@A-weight- Support DAC Sample Rates from 8KHz to 192KHz
Support analog/ digital volume control
Differential earpiece driver
Analog low-power loop from line-in /microphone to headphone/earpiece outputs

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Overview













Support Dynamic Range Controller(DRC) adjusting the DAC playback output
Accessory button press detection
Four audio inputs:
Two differential microphone inputs
One differential Phone input
Stereo Line-in L/R input
Four audio outputs:
Earpiece amplifier differential output
Phone amplifier differential output
Headphone amplifier L/R channel output
Line-out L/R output
Two audio analog-to-digital(ADC) channels
96dB SNR@A-weight
Supports ADC Sample Rates from 8KHz to 48KHz
Support Automatic Gain Control(AGC) and Dynamic Range Control(DRC) adjusting the ADC recording input
Two PCM interface connected with BB and BT
One 128x24-bits FIFO for data transmit, one 64x24-bits FIFO for data receive
Support Audio HUB

2.1.8.2. One Wire Audio(OWA)








IEC-60958 transmitter functionality
Complies with SPDIF Interface
Support channel status insertion for the transmitter
Hardware Parity generation on the transmitter
One 32×24bits FIFO (TX) for audio data transfer
Programmable FIFO thresholds
Support Audio HUB

2.1.8.3. I2S/PCM











Up to two I2S/PCM controllers
Compliant with standard Inter-IC sound(I2S) bus specification
Compliant with left-justified, right-justified, PCM mode, and TDM(Time Division Multiplexing) format
Full-duplex synchronous work mode
Mater and slave mode configured
Adjustable audio sample resolution from 8-bit to 32-bit
Sample rate from 8KHz to 192KHz
Support 8-bits u-law and 8-bits A-law companded sample
Support programmable PCM frame width:1 BCLK width(short frame) and 2 BCLKs width(long frame)
Support Audio HUB

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2.1.9. External Peripherals
2.1.9.1. USBOne USB 2.0 OTG,with integrated one USB 2.0 analog PHY
Complies with USB2.0 Specification
Support High-Speed (HS,480Mbps),Full-Speed(FS,12Mbps) and Low-Speed(LS,1.5Mbps) in host mode
Complies with Enhanced Host Controller Interface(EHCI)Specification, Version 1.0, and the Open Host
Controller Interface(OHCI) Specification, Version 1.0a for host mode
Up to 10 User-Configurable Endpoints for Bulk,Isochronous and Interrupt bi-directional transfers(Endpoint1, Endpoint2, Endpoint3, Endpoint4, Endpoint5)
Support 8KB FIFO for EPs(excluding EP0)HCI(EHCI+OHCI) and USB2.0 OTG SIE share USB analog PHY
One EHCI/OHCI Host, multiplexed with one USB 2.0 analog PHY and one HSIC PHY
Complies with Enhanced Host Controller Interface(EHCI)Specification, Version 1.0, and the Open Host
Controller Interface(OHCI) Specification, Version 1.0a.

2.1.9.2. EMAC







Support 10/100/1000Mbps data transfer rate
Support RGMII/RMII interface
Support full-duplex and half-duplex operation
Support linked-list descriptor list structure
Programmable frame length to support Standard or Jumbo Ethernet frames with sizes up to 16 KB
Supports a variety of flexible address filtering modes

2.1.9.3. UART







Up to six UART controllers
Two of six UART controllers support 2-wire while others support 4-wire
64-Bytes Transmit and receive data FIFOs for all UART
Compatible with industry-standard 16550 UARTs
Support Infrared Data Association(IrDA) 1.0 SIR
Support speed up to 3MHz

2.1.9.4. SPI•

Up to two SPI controllers

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•
•
•
•
•
•
•

Full-duplex synchronous serial interface
Master/Slave configurable
Mode0~3 are supported for both transmit and receive operations
Two 64-Bytes FIFO for SPI-TX and SPI-RX operation
DMA-based or interrupt-based operation
Polarity and phase of the chip select(SPI_SS) and SPI_Clock(SPI_SCLK) are configurable
Support single and dual IO mode

2.1.9.5. Two Wire Interface(TWI)
•
•
•
•
•
•

Up to four TWI controllers
Support Standard mode(up to 100K bps) and Fast mode(up to 400K bps)
Master/Slave configurable
Allows 10-bit addressing transactions
Perform arbitration and clock synchronization
Allow operation from a wide range of input clock frequencies

2.1.9.6. CIRA flexible receiver for IR remote
Programmable FIFO threshold
64x8bits FIFO for data buffer

2.1.9.7. Reduced Serial Bus(RSBTM)






Up to 20MHz speed with ultra low power
Support push-pull bus
Support host mode and multi-devices
Programmable output delay of CD signal
Support parity check for address and data transmission

2.1.9.8. TSCompliant with the industry-standard AMBA Host Bus(AHB) Specification, Revision 2.0.Support 32-bit Little
Endian bus.
Support DVB-CSA V1.1 DescramblerOne external Synchronous Parallel Interface(SPI) or one external Synchronous Serial Interface(SSI)
Configurable SPI and SSI timing parametersHardware packet synchronous byte error detecting

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Hardware PCR packet detecting

2.1.9.9. SCR








Supports APB slave interface for easy integration with AMBA-based host systems
Supports the ISO/IEC 7816-3:1997(E) and EMV2000 (4.0) Specifications
Supports adjustable clock rate and bit rate
Configurable automatic byte repetition
Support asynchronous half-duplex character transmission and block transmission
Supports synchronous and any other non-ISO 7816 and non-EMV cards
Performs functions needed for complete smart card sessions, including:- Card activation and deactivation- Cold/warm reset- Answer to Reset (ATR) response reception- Data transfers to and from the card

2.1.10. Package

FBGA 396 balls, 0.65mm ball pitch,15 x 15mm

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2.2. System Block Diagram
The following figure shows the block diagram of A64 processor.

Image
Parallel CSI
5M pixel
8-bit bus

DisplayDE
SmatColor 2.0

Decoder
Multi-format
H.265 4K@30fps

Encoder
H.264
1080p@60fps

Cortex-A53
Quad-coreGPU

32KB L1 I-cache + 32KB
L1 D-cache per core
512KB L2 cache

LVDS
1366x768@60fps
RGB
1920x1200@60fps

4-lanes MIPI DSI
1920x1200@60fps
HDMI 1.4 withHDCP1.2
4K@30fps

Connectivity

Video Engine

Mali400MP2
OpenGL ES 2.0 and
OpenVG 1.1

USB Host with USB 2.0
PHY and HSIC PHYTS Demux x1
SPI/SSI mode with
CSA1.1
SDIO3.0
SCR

External Memory
DDR2/DDR3/DDR3L/
LPDDR2/ LPDDR3
32-bits bus
667MHz(DDR3-1333)

System
CLOCK
24MHz/32.768KHz
CCU
Thermal Sensor

NDFC
8bits bus
64bits ECC

TWI x4

CIR Rx
SPI x2Timer
UART x6
DMA
PWM

SD2.0/eMMC5.0
1/4/8-bits bus

RSB

GPIO

Audio
I2S/PCM x 2

USB2.0 OTG with USB
2.0 PHY

KEYADC

Security System

OWA output

Security Boot

TrustZone

Ethernet

Audio Codec

Crypto Engine

Efuse

10/100/1000M EMAC

Figure 2-1. A64 Block Diagram

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Chapter 3 System
The chapter describes the A64 system from following sections:























Memory Mapping
Boot System
CCU
CPU Configuration
System Control
Timer
R_Trusted Watchdog Timer
RTC
High-speed Timer
PWM
DMA
GIC
Message Box
Spinlock
Crypto Engine
Secure Memory Controller
Secure Peripherals Controller
Thermal Sensor Controller
KEYADC
Audio Codec
Port Controller(CPUx-PORT)Port Controller(CPUs-PORT)A64 User Manual(Revision 1.0)

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3.1. Memory Mapping
ModuleAddress (It is for Cluster CPU)

Size (byte)

N-BROM

0x0000 0000---0x0000 BFFF

48K

S-BROM

0x0000 0000---0x0000 FFFF

64K

SRAM A1

0x0001 0000---0x0001 7FFF

32K

SRAM A2

0x0004 4000---0x0005 3FFF

64K

SRAM C

0x0001 8000---0x0003 FFFF

160K

DE

0x0100 0000---0x013F FFFF

4M

Core Sight Debug

0x0140 0000---0x0141 FFFF

128K

CPU MBIST

0x0150 2000---0x0150 2FFF

4K

CPUX_CFG

0x0170 0000---0x0170 03FF

1K

System Control

0x01C0 0000---0x01C0 0FFF

4K

DMA

0x01C0 2000---0x01C0 2FFF

4K

NFDC

0x01C0 3000---0x01C0 3FFF

4K

TS

0x01C0 6000---0x01C0 6FFF

4K

Key Memory Space

0x01C0 B000---0x01C0 BFFF

4K

TCON 00x01C0 C000---0x01C0 CFFF

4K

TCON 10x01C0 D000---0x01C0 DFFF

4K

VE

0x01C0 E000---0x01C0 EFFF

4K

SMHC 00x01C0 F000---0x01C0 FFFF

4K

SMHC 10x01C1 0000---0x01C1 0FFF

4K

SMHC 20x01C1 1000---0x01C1 1FFF

4K

SID

0x01C1 4000---0x01C1 43FF

1K

Crypto Engine

0x01C1 5000---0x01C1 5FFF

4K

MSG_BOX

0x01C1 7000---0x01C1 7FFF

4K

SPINLOCK

0x01C1 8000---0x01C1 8FFF

4K

USB-OTG-Device

0x01C1 9000---0x01C1 9FFF

4K

USB-OTG-EHCI/OHCI

0x01C1 A000---0x01C1 AFFF

4K

USB-EHCI0/OHCI0

0x01C1 B000---0x01C1 BFFF

4K

SMC

0x01C1 E000---0x01C1 EFFF

4K

CCU

0x01C2 0000---0x01C2 03FF

1K

PIO

0x01C2 0800---0x01C2 0BFF

1K

TIMER

0x01C2 0C00---0x01C2 0FFF

1K

OWA

0x01C2 1000---0x01C2 13FF

1K

PWM

0x01C2 1400---0x01C2 17FF

1K

KEYADC

0x01C2 1800---0x01C2 1BFF

1K

I2S/PCM 0

0x01C2 2000---0x01C2 23FF

1K

I2S/PCM 1

0x01C2 2400---0x01C2 27FF

1K

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I2S/PCM 2

0x01C2 2800---0x01C2 2BFF

1K

AC

0x01C2 2C00---0x01C2 33FF

2K

SPC

0x01C2 3400---0x01C2 37FF

1K

THS

0x01C2 5000---0x01C2 53FF

1K

UART 00x01C2 8000---0x01C2 83FF

1K

UART 10x01C2 8400---0x01C2 87FF

1K

UART 20x01C2 8800---0x01C2 8BFF

1K

UART 30x01C2 8C00---0x01C2 8FFF

1K

UART 40x01C2 9000---0x01C2 93FF

1K

TWI 0

0x01C2 AC00---0x01C2 AFFF

1K

TWI 1

0x01C2 B000---0x01C2 B3FF

1K

TWI 2

0x01C2 B400---0x01C2 B7FF

1K

SCR

0x01C2 C400---0x01C2 C7FF

1K

EMAC

0x01C3 0000---0x01C3 FFFF

64K

GPU

0x01C4 0000---0x01C4 FFFF

64K

HSTMR

0x01C6 0000---0x01C6 0FFF

4K

DRAMCOM

0x01C6 2000---0x01C6 2FFF

4K

DRAMCTL0

0x01C6 3000---0x01C6 3FFF

4K

DRAMPHY00x01C6 5000---0x01C6 5FFF

4K

SPI0

0x01C6 8000---0x01C6 8FFF

4K

SPI1

0x01C6 9000---0x01C6 9FFF

4K

SCU space,
CPUS can’t access

0x01C80000
GIC_DIST: 0x01C80000 + 0x1000
GIC_CPUIF:0x01C80000 + 0x2000

MIPI DSI

0x01CA 0000---0x01CA 0FFF

4K

MIPI DSI-PHY

0x01CA 1000---0x01CA 1FFF

4K

CSI

0x01CB 0000---0x01CF FFFF

320K

De-interlaced

0x01E0 0000---0x01E1 FFFF

128K

HDMI

0x01EE 0000---0x01EF FFFF

128K

RTC

0x01F0 0000---0x01F0 03FF

1K

R_TIMER

0x01F0 0800---0x01F0 0BFF

1K

R_INTC

0x01F0 0C00---0x01F0 0FFF

1K

R_WDOG

0x01F0 1000---0x01F0 13FF

1K

R_PRCM

0x01F0 1400---0x01F0 17FF

1K

R_TWD

0x01F0 1800---0x01F0 1BFF

1K

R_CPUCFG

0x01F0 1C00---0x01F0 1FFF

1K

R_CIR-RX

0x01F0 2000---0x01F0 23FF

1K

R_TWI

0x01F0 2400---0x01F0 27FF

1K

R_UART

0x01F0 2800---0x01F0 2BFF

1K

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R_PIO

0x01F0 2C00---0x01F0 2FFF

1K

R_RSB

0x01F0 3400---0x01F0 37FF

1K

R_PWM

0x01F0 3800---0x01F0 3BFF

1K

SDRAM

0x4000 0000---0xFFFF FFFF

3G

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3.2. Boot System
The system will boot in different ways based on whether its security features are enabled.
The Boot System includes the following features:•Support CPU-0 boot process and CPU-0+ boot process•
Support super standby wakeup process•
Support mandatory upgrade process through SDC0 and USB OTG•
Support fast boot process from Raw NAND,eMMC,SD/TF card ,and SPI NOR FlashA64 User Manual(Revision 1.0)

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3.3. CCU
3.3.1. Overview
The CCU controls the PLLs configuration and most of the clock generation, division, distribution,synchronization and gating. CCU input signals include the external clock for the reference frequency (24MHz).
The outputs from CCU are mostly clocks to other blocks in the system.
The CCU includes the following features:
13 PLLs, independent PLL for CPUXBus Source and Divisions

PLLs Bias Control
PLLs Tunning Control
PLLs Pattern Control
Configuring Modules ClockBus Clock Gating
Bus Software Reset

3.3.2. Functionalities Description
3.3.2.1. System Bus

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CPUS

CORE0

CORE1

CORE2

CORE3
Arbiter
AHBS BUS

Cache, GIC

AXIS1SRAM A2

BridgeAHB2AHBAHB2AHBAXIS2APBS BUS

DRAM

X2H

GPU

SMHC

CE

USB-OTG

TH

CPUS

USB-HOST

DE

VE

NAND

CSI

R_TIMER

R_INTC

R_WDOG

R_PRCM

RTC

R_PWM

R_TWI

R_UART

R_GPIO

R_CPUCFG

R_CIR_RX

R_RSB

DMA

AHB

AHB

AHB

Arbiter
AHB1 BUS

SYS_CTRLSRAM A1

HS TIMER

SRAM CAHB1

TCON

SPINLOCKDRAMCMSGBOX

AHB1

AHB1
Bridge

DE

GPU

HDMI

VE

DMA

TSGEN

NAND

CSI

SDRCTL

SMHC

CE

SPI

SID

SMC

MIPI_DSI

BridgeBridge
AHB2

APB2

APB1

APB2 BUS
APB1 BUS

UART

TWI

AHB2 BUS

EMAC
USB

CCM

TIMER

DAUDIOGPIO

KEYADC

THS

BROM

SID

SMTA

PWM

OWA

Figure 3-1. System Bus Tree

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3.3.2.2. Bus clock tree

32.768KHz
X

System APB
ExternalOSC
MUX

16MHz

CPU_APB_CLK_DIV(/1 /2 /4)

LOSC

/512

CPU

MUX

PLL_CPUX

L2 Cache/1

AXI

AXI_CLK_DIV_RATIO(1/(1~4))

OSC24M
MUX

X

AHB1_CLK_DIV_RATIO(/1 /2 /4 /8)

AHB1

AHB1_PRE_DIV
1/(1~4)

PLL-PERH0(1X)

AHB2

MUX

/2

MUX

CLK_RAT_N(/1 /2 /4 /8)

APB1_CLK_RATIO(/2 /2 /4 /8)

APB1

CLK_RAT_M
1/(1~32)

APB2

PLL-PERH0(2X)

Figure 3-2. Bus Clock Tree

3.3.2.3. Module clock tree

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LOSC
M
UX

24MOSCCPUX

PLL_C0_CPUX

PLL_AUDIODAUDIO0/DAUDIO1/DAUDIO2/
OWA/AC_DIGITAL

PLL_VIDEO0

TCON0/TCON1/HDMI/MIPI_DSI/
CSI

TCON0

PLL_MIPI

PLL_VIDEO1

TCON1/HDMI/CSI

PLL_VEVE

PLL_PERIPH0

NAND/SMHC0/SMHC1/SMHC2/CE/SPI0/SPI1/DE/CSI/MBUS/
MIPI_DSI

PLL_PERIPH1

NAND/SMHC0/SMHC1/SMHC2/
SPI0/SPI1/CSI/MIPI_DSI

PLL_GPUGPU

PLL_HSICUSB

PLL_DEDE

PLL_DDR0

DRAM/MBUS

PLL_DDR1

DRAM/MBUS

24 MHz

PLLOsciallor/750

Watchdog

24MOSCM
U
X

ExternalOSC
X

16MHz

M
U
X

Timer

LOSC

/512

Figure 3-3.Module Clock Diagram

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3.3.3. Typical Applications(1). Clock output of PLL_CPUX is used only for CPU;and the frequency factor can be dynamically modified for
DVFS;(2). Clock output of PLL_AUDIO (24.571MHz or 24.5792MHz)can be used for I2S/PCM 0,I2S/PCM 1,I2S/PCM 2,
AC DIGITAL,OWA ;and dynamic frequency scaling is not supported;(3). Clock output of PLL_VIDEO0 (1X) can be used for TCON1,HDMI,MIPI_DSI;clock output of PLL_VIDEO0 (2X)
can be used for TCON0;dynamic frequency scaling is not supported for PLL_VIDEO0(1X) and PLL_VIDEO0(2X);(4). Clock output of PLL_VIDEO1 (1X) can be used for TCON1,HDMI,CSI; and dynamic frequency scaling is notsupported;(5). Clock output of PLL_VE can be only used for VE;and dynamic frequency scaling is not supported;(6). Clock output of PLL_DDR0 can be used for MBUS and DRAM;and dynamic frequency scaling is notsupported;(7). Clock output of PLL_PERIPH0 (2X) can be used for APB2,MBUS,SMHC0,SMHC1,SMHC2,CE,DE; Clock outputof PLL_PERIPH0(1X) can be used for AHB1,APB1,AHB2,MBUS and NAND,SPI0,SPI1,CSI,MIPI_DSI,De-interlace,
CPUS; dynamic frequency scaling is not supported for PLL_PERIPH0(2X) and PLL_PERIPH0(1X);(8). Clock output of PLL_PERIPH1(2X) can be used for SMHC0,SMHC1,SMHC2,CE;Clock output of
PLL_PERIPH1(1X) can be used for NAND,SPI0,SPI1,CSI,MIPI_DSI,De-interlace;dynamic frequency scaling is notsupported for PLL_PERIPH1(2X) and PLL_PERIPH1(1X);(9). Clock output of PLL_GPU can be used for GPU;and dynamic frequency scaling is not supported;(10). Clock output of PLL_MIPI can be used for TCON0;and dynamic frequency scaling is not supported;(11). Clock output of PLL_HSIC can be used for USB;and dynamic frequency scaling is not supported;(12). Clock output of PLL_DE can be used for DE;and dynamic frequency scaling is not supported;(13). Clock output of PLL_DDR1 can be used for MBUS and DRAM;and dynamic frequency scaling is notsupported;

3.3.4. Register List
Module Name

Base Address

CCU

0x01C20000

Register Name

OffsetDescription

PLL_CPUX_CTRL_REG

0x0000

PLL_CPUX Control Register

PLL_AUDIO_CTRL_REG

0x0008

PLL_AUDIO Control Register

PLL_VIDEO0_CTRL_REG

0x0010

PLL_VIDEO0 Control Register

PLL_VE_CTRL_REG

0x0018

PLL_VE Control Register

PLL_DDR0_CTRL_REG

0x0020

PLL_DDR0 Control Register

PLL_PERIPH0_CTRL_REG

0x0028

PLL_PERIPH0 Control Register

PLL_PERIPH1_CTRL_REG

0x002C

PLL_PERIPH1 Control Register

PLL_VIDEO1_CTRL_REG

0x0030

PLL_VIDEO1 Control Register

PLL_GPU_CTRL_REG

0x0038

PLL_GPU Control Register

PLL_MIPI_CTRL_REG

0x0040

PLL_MIPI Control Register

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PLL_HSIC_CTRL_REG

0x0044

PLL_HSIC Control Register

PLL_DE_CTRL_REG

0x0048

PLL_DE Control Register

PLL_DDR1_CTRL_REG

0x004CPLL_DDR1 Control Register

CPU_AXI_CFG_REG

0x0050

CPUX/AXI Configuration Register

AHB1_APB1_CFG_REG

0x0054

AHB1/APB1 Configuration Register

APB2 _CFG_REG

0x0058APB2 Configuration Register

AHB2_CFG_REG

0x005CAHB2 Configuration Register

BUS_CLK_GATING_REG0

0x0060Bus Clock Gating Register 0

BUS_CLK_GATING_REG1

0x0064Bus Clock Gating Register 1

BUS_CLK_GATING_REG2

0x0068Bus Clock Gating Register 2

BUS_CLK_GATING_REG3

0x006CBus Clock Gating Register 3

BUS_CLK_GATING_REG40x0070Bus Clock Gating Register 4

THS_CLK_REG

0x0074

THS Clock Register

NAND_CLK_REG

0x0080

NAND Clock Register

SDMMC0_CLK_REG

0x0088SDMMC0 Clock Register

SDMMC1_CLK_REG

0x008CSDMMC1 Clock Register

SDMMC2_CLK_REG

0x0090SDMMC2 Clock Register

TS_CLK_REG

0x0098TS Clock Register

CE_CLK_REG

0x009CCE Clock Register

SPI0_CLK_REG

0x00A0

SPI0 Clock Register

SPI1_CLK_REG

0x00A4

SPI1 Clock Register

I2S/PCM-0_CLK_REG

0x00B0I2S/PCM-0 Clock Register

I2S/PCM-1_CLK_REG

0x00B4

I2S/PCM-1 Clock Register

I2S/PCM-2_CLK_REG

0x00B8I2S/PCM-2 Clock Register

OWA_CLK_REG

0x00C0OWA Clock Register

USBPHY_CFG_REG

0x00CCUSBPHY Configuration Register

DRAM_CFG_REG

0x00F4

DRAM Configuration Register

PLL_DDR_CFG_REG

0x00F8

PLL_DDR Configuration Register

MBUS_RST_REG

0x00FCMBUS Reset Register

DRAM_CLK_GATING_REG

0x0100DRAM Clock Gating Register

DE_CLK_REG

0x0104DE Clock Register

TCON0_CLK_REG

0x0118

TCON0 Clock Register

TCON1_CLK_REG

0x011CTCON1 Clock Register

DEINTERLACE_CLK_REG

0x0124

DEINTERLACE Clock Register

CSI_MISC_CLK_REG

0x0130

CSI_MISC Clock Register

CSI_CLK_REG

0x0134

CSI Clock Register

VE_CLK_REG

0x013CVE Clock Register

AC_DIG_CLK_REG

0x0140AC Digital Clock Register

AVS_CLK_REG

0x0144AVS Clock Register

HDMI_CLK_REG

0x0150

HDMI Clock Register

HDMI_SLOW_CLK_REG

0x0154

HDMI Slow Clock Register

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MBUS_CLK_REG

0x015CMBUS Clock Register

MIPI_DSI_CLK_REG

0x0168

MIPI_DSI Clock Register

GPU_CLK_REG

0x01A0GPU Clock Register

PLL_STABLE_TIME_REG0

0x0200PLL Stable Time Register0

PLL_STABLE_TIME_REG1

0x0204

PLL Stable Time Register1

PLL_PERIPH1_BIAS_REG

0x021C

PLL_PERIPH1 Bias Register

PLL_CPUX_BIAS_REG

0x0220

PLL_CPUX Bias Register

PLL_AUDIO_BIAS_REG

0x0224

PLL_AUDIO Bias Register

PLL_VIDEO0_BIAS_REG

0x0228

PLL_VIDEO0 Bias Register

PLL_VE_BIAS_REG

0x022C

PLL_VE Bias Register

PLL_DDR0_BIAS_REG

0x0230

PLL_DDR0 Bias Register

PLL_PERIPH0_BIAS_REG

0x0234

PLL_PERIPH0 Bias Register

PLL_VIDEO1_BIAS_REG

0x0238

PLL_VIDEO1 Bias Register

PLL_GPU_BIAS_REG

0x023CPLL_GPU Bias Register

PLL_MIPI_BIAS_REG

0x0240

PLL_MIPI Bias Register

PLL_HSIC_BIAS_REG

0x0244

PLL_HSIC Bias Register

PLL_DE_BIAS_REG

0x0248

PLL_DE Bias Register

PLL_DDR1_BIAS_REG

0x024CPLL_DDR1 Bias Register

PLL_CPUX_TUN_REG

0x0250

PLL_CPUX Tuning Register

PLL_DDR0_TUN_REG

0x0260

PLL_DDR0 Tuning Register

PLL_MIPI_TUN_REG

0x0270

PLL_MIPI Tuning Register

PLL_PERIPH1_PAT_CTRL_REG

0x027C

PLL_PERIPH1 Pattern Control Register

PLL_CPUX_PAT_CTRL_REG

0x0280

PLL_CPUX Pattern Control Register

PLL_AUDIO_PAT_CTRL_REG

0x0284

PLL_AUDIO Pattern Control Register

PLL_VIDEO0_PAT_CTRL_REG

0x0288

PLL_VIDEO0 Pattern Control Register

PLL_VE_PAT_CTRL_REG

0x028C

PLL_VE Pattern Control Register

PLL_DDR0_PAT_CTRL_REG

0x0290

PLL_DDR0 Pattern Control Register

PLL_VIDEO1_PAT_CTRL_REG

0x0298

PLL_VIDEO1 Pattern Control Register

PLL_GPU_PAT_CTRL_REG

0x029CPLL_GPU Pattern Control Register

PLL_MIPI_PAT_CTRL_REG

0x02A0

PLL_MIPI Pattern Control Register

PLL_HSIC_PAT_CTRL_REG

0x02A4

PLL_HSIC Pattern Control Register

PLL_DE_PAT_CTRL_REG

0x02A8

PLL_DE Pattern Control Register

PLL_DDR1_PAT_CTRL_REG0

0x02ACPLL_DDR1 Pattern Control Register0

PLL_DDR1_PAT_CTRL_REG1

0x02B0

PLL_DDR1 Pattern Control Register1

BUS_SOFT_RST_REG0

0x02C0Bus Software Reset Register 0

BUS_SOFT_RST_REG1

0x02C4Bus Software Reset Register 1

BUS_SOFT_RST_REG2

0x02C8Bus Software Reset Register 2

BUS_SOFT_RST_REG3

0x02D0Bus Software Reset Register 3

BUS_SOFT_RST_REG4

0x02D8Bus Software Reset Register 4

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CCM_SEC_SWITCH_REG

0x02F0

CCM Security Switch Register

PS_CTRL_REG

0x0300PS Control Register

PS_CNT_REG

0x0304

PS Counter Register

PLL_LOCK_CTRL_REG

0x0320

PLL Lock Control Register

3.3.5. Register Description
3.3.5.1. PLL_CPUX Control Register (Default Value: 0x00001000)
Offset: 0x0000

Register Name: PLL_CPUX_CTRL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

PLL_ENABLE.
0: Disable
1: Enable
The PLL Output= (24MHz*N*K)/(M*P).
The PLL output is for the CPUX Clock.
Note: 10≤N*K≤88,The P factor only can be used when PLL output
frequency is less than 240MHz.
The PLL output clock must be in the range of 240MHz~2.1GHz.
The default of CPUX Clock is 408MHz.

30:29

/

/

/

28

R

0x0

LOCK
0: Unlocked
1: Locked (It indicates that the PLL has been stable.)

27:25

/

/

/

24

R/W

0x0

CPUX_SDM_EN.
0: Disable
1: Enable

23:18

/

/

/

17:16

R/W

0x0

PLL_OUT_EXT_DIVPPLL Output external divider P
00: /1
01: /2
10: /4
11: /

15:13

/

/

/

12:8

R/W

0x10

PLL_FACTOR_N
PLL Factor N.
Factor=0, N=1
Factor=1, N=2
Factor=2, N=3

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Factor=31, N=32
7:6

/

/

/

5:4

R/W

0x0

PLL_FACTOR_K.
PLL Factor K.(K=Factor + 1 )The range is from 1 to 4.

3:2

/

/

/

1:0

R/W

0x0

PLL_FACTOR_M.
PLL Factor M. (M=Factor + 1)
The range is from 1 to 4.

3.3.5.2. PLL_Audio Control Register (Default Value: 0x00035514)
Offset: 0x0008

Register Name: PLL_AUDIO_CTRL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

PLL_ENABLE.
0: Disable
1: Enable.
The PLL is for Audio.
The PLL_AUDIO= (24MHz*N)/(M*P).
The PLL_AUDIO(8X) = (24MHz*N*2)/M
Note: 3≤N/M≤21.
(24MHz*N)/P must be in the range of 72MHz~504MHz.
PLL_AUDIO default is 24.571MHz.

30:29

/

/

/

28

R

0x0

LOCK.
0: Unlocked
1: Locked (It indicates that the PLL has been stable.)

27:25

/

/

/

24

R/W

0x0

PLL_SDM_EN.
0: Disable
1: Enable.
In this case, the PLL_FACTOR_N only low 4 bits are valid (N: The range isfrom 1 to 16).

23:20

/

/

/

19:16

R/W

0x3

PLL_POSTDIV_P.
Post-div factor (P= Factor+1)
The range is from 1 to 16.

14:8

R/W

0x55

PLL_FACTOR_N.
PLL Factor N.
Factor=0, N=1

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Factor=1, N=2……
Factor=127, N=128.
7:5

/

/

/

4:0

R/W

0x14

PLL_PREDIV_M.
PLL Pre-div Factor(M = Factor+1).
The range is from 1 to 32.

3.3.5.3. PLL_VIDEO0 Control Register (Default Value: 0x03006207)
Offset: 0x0010

Register Name: PLL_VIDEO0_CTRL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

PLL_ENABLE.
0: Disable
1: Enable.
In the integer mode,
PLL_VIDEO0(1X) = (24MHz*N)/M.
PLL_VIDEO0(2X) =( (24MHz*N)/M)*2.
In the fractional mode, the PLL Output is select by bit 25.
Note: 8≤N/M≤25(24MHz*N)/M must be in the range of 192MHz~600MHz.
PLL_VIDEO0(1X) default is 297MHz.

30

/

/

/

29

/

/

/

28

R

0x0

LOCK.
0: Unlocked
1: Locked (It indicates that the PLL has been stable.)

27:26

/

/

/

25

R/W

0x1

FRAC_CLK_OUT.
PLL clock output when PLL_MODE_SEL=0(PLL_PREDIV_M factor must be
set to 0); No meaning when PLL_MODE_SEL =1.
0: PLL Output=270MHz
1: PLL Output =297MHz.

24

R/W

0x1

PLL_MODE_SEL.
0: Fractional Mode
1: Integer Mode.
Note: When in Fractional mode, the Per Divider M should be set to 0.

23:21

/

/

/

20

R/W

0x0

PLL_SDM_EN.
0: Disable
1: Enable.

19:15

/

/

/

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14:8

R/W

0x62

PLL_FACTOR_N.
PLL Factor N.
Factor=0, N=1
Factor=1, N=2
Factor=2, N=3……
Factor=127,N=128.

7:4

/

/

/

3:0

R/W

0x7

PLL_PREDIV_M.
PLL Pre-div Factor(M = Factor+1).
The range is from 1 to 16.

3.3.5.4. PLL_VE Control Register (Default Value: 0x03006207)
Offset: 0x0018

Register Name: PLL_VE_CTRL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

PLL_ENABLE.
0: Disable
1: Enable.
In the integer mode, The PLL_VE = (24MHz*N)/M.
In the fractional mode, the PLL Output is select by bit 25.
Note: 8≤N/M≤25(24MHz*N)/M must be in the range of 192MHz~600MHz.
PLL_VE default is 297MHz.

30:29

/

/

/

28

R

0x0

LOCK
0: Unlocked
1: Locked (It indicates that the PLL has been stable.)

27:26

/

/

/

25

R/W

0x1

FRAC_CLK_OUT.
PLL clock output when PLL_MODE_SEL=0(PLL_PREDIV_M factor must be
set to 0); No meaning when PLL_MODE_SEL =1.
0: PLL Output=270MHz
1: PLL Output =297MHz.

24

R/W

0x1

PLL_MODE_SEL.
0: Fractional Mode
1: Integer Mode.
Note: When in Fractional mode, the Per Divider M should be set to 0.

23:21

/

/

/

20

R/W

0x0

PLL_SDM_EN.
0: Disable
1: Enable.

19:15

/

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14:8

R/W

0x62

PLL_FACTOR_N.
PLL Factor N.
Factor=0, N=1
Factor=1, N=2
Factor=2, N=3……
Factor=31,N=32…
Factor=127,N=128.

7:4

/

/

/

3:0

R/W

0x7

PLL_PREDIV_M.
PLL Pre Divider (M = Factor+1).
The range is from 1 to 16.

3.3.5.5. PLL_DDR0 Control Register (Default Value: 0x00001000)
Offset: 0x0020

Register Name: PLL_DDR0_CTRL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

PLL_ENABLE.
0: Disable
1: Enable.
The PLL_DDR0 = (24MHz*N*K)/M.
Note: 10≤N*K≤77(give priority to the choice of K≥2)
(24MHz*N*K) must be in the range of 240MHz~1.8GHz.
PLL_DDR0 default is 408MHz.

30:29

/

/

/

28

R

0x0

LOCK
0: Unlocked
1: Locked (It indicates that the PLL has been stable.)

27:25

/

/

/

24

R/W

0x0

PLL_SDM_EN.
0: Disable
1: Enable.

23:21

/

/

/

20

R/W

0x0

PLL_DDR0_CFG_UPDATE.
PLL_DDR0 Configuration Update.
When PLL_DDR0 has been changed, this bit should be set to 1 to validate
the PLL, otherwise the change would be invalid. And this bit would becleared automatically after the PLL change is valid.
0: No effect
1: Validating the PLL_DDR0.

19:13

/

/

/

12:8

R/W

0x10

PLL_FACTOR_N.

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PLL Factor N.
Factor=0, N=1
Factor=1, N=2
Factor=2, N=3……
Factor=31,N=32.
7:6

/

/

/

5:4

R/W

0x0

PLL_FACTOR_K.
PLL Factor K.(K=Factor + 1 )The range is from 1 to 4.

3:2

/

/

/

1:0

R/W

0x0

PLL_FACTOR_M.
PLL Factor M.(M = Factor + 1 )The range is from 1 to 4.

3.3.5.6. PLL_PERIPH0 Control Register (Default Value: 0x00041811)
Offset: 0x0028

Register Name: PLL_PERIPH0_CTRL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

PLL_ENABLE.
0: Disable
1: Enable.
The PLL_PERIPH0(1X) = 24MHz*N*K/2.
The PLL_PERIPH0(2X) = 24MHz*N*K.
Note: 21≤N*K≤58(give priority to the choice of K≥2)
The PLL_PERIPH0(2X) should be fixed to 1.2GHz, it is not recommended
to vary this value arbitrarily.
24MHz*N*K clock must be in the range of 504MHz~1.4GHz.
PLL_PERIPH0(2X) default is 1.2GHz.

30:29

/

/

/

28

R

0x0

LOCK.
0: Unlocked
1: Locked (It indicates that the PLL has been stable.)

27:26

/

/

/

25

R/W

0x0

PLL_BYPASS_EN.
PLL Output Bypass Enable.
0: Disable
1: Enable
If the bypass is enabled, the PLL output is 24MHz.

24

R/W

0x0

PLL_CLK_OUT_EN.
PLL clock output enable.
0: Disable
1: Enable

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23:19

/

/

/

18

R/W

0x1

Reserved

17:16

/

/

/

15:13

/

/

/

12:8

R/W

0x18

PLL_FACTOR_N.
PLL Factor N.
Factor=0, N=1
Factor=1, N=2
Factor=2, N=3……
Factor=31, N=32

7:6

/

/

/

5:4

R/W

0x1

PLL_FACTOR_K.
PLL Factor K.(K=Factor + 1 )The range is from 1 to 4.

3:2

/

/

/

1:0

R/W

0x1

PLL_FACTOR_M.
PLL Factor M (M = Factor + 1) is only valid in plltest debug.
The PLL_PERIPH back door clock output =24MHz*N*K/M.
The range is from 1 to 4.

3.3.5.7. PLL_PERIPH1 Control Register (Default Value: 0x00041811)
Offset: 0x002C

Register Name: PLL_PERIPH1_CTRL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

PLL_ENABLE.
0: Disable
1: Enable.
The PLL_PERIPH0(1X) = 24MHz*N*K/2.
The PLL_PERIPH0(2X) = 24MHz*N*K.
Note: 21≤N*K≤58(give priority to the choice of K≥2)
The PLL_PERIPH1(2X) should be fixed to 1.2GHz, it is not recommended
to vary this value arbitrarily.
24MHz*N*K clock must be in the range of 504MHz~1.4GHz.
PLL_PERIPH0(2X) default is 1.2GHz.

30:29

/

/

/

28

R

0x0

LOCK.
0: Unlocked
1: Locked (It indicates that the PLL has been stable.)

27:26

/

/

/

25

R/W

0x0

PLL_BYPASS_EN.
PLL Output Bypass Enable.

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0: Disable
1: Enable.
If the bypass is enabled, the PLL output is 24MHz.
24

/

/

/

23:21

/

/

/

20

R/W

0x0

PLL_SDM_EN
0: Disable
1: Enable.

19

/

/

/

18

R/W

0x1

Reserved

17:16

/

/

/

15:13

/

/

/

12:8

R/W

0x18

PLL_FACTOR_N.
PLL Factor N.
Factor=0, N=1
Factor=1, N=2
Factor=2, N=3……
Factor=31,N=32.

7:6

/

/

/

5:4

R/W

0x1

PLL_FACTOR_K.
PLL Factor K.(K=Factor + 1 )The range is from 1 to 4.

3:2

/

/

/

1:0

R/W

0x1

PLL_FACTOR_M.
PLL Factor M (M = Factor + 1) is only valid in plltest debug.
The PLL_PERIPH back door clock output =24MHz*N*K/M.
The range is from 1 to 4.

3.3.5.8. PLL_VIDEO1 Control Register (Default Value: 0x03006207)
Offset: 0x0030

Register Name: PLL_VIDEO1_CTRL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

PLL_ENABLE.
0: Disable
1: Enable.
In the integer mode,
PLL_VIDEO1(1X) = (24MHz*N)/M.
PLL_VIDEO1(2X) =( (24MHz*N)/M)*2.
In the fractional mode, the PLL Output is select by bit 25.
Note: 8≤N/M≤25(24MHz*N)/M must be in the range of 192MHz~600MHz.

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PLL_VIDEO1(1X) default is 297MHz.
30

R/W

0x0

PLL_MODE.
0: Manual Mode
1: Auto Mode (Controlled by DE).

29

/

/

/

28

R

0x0

LOCK.
0: Unlocked
1: Locked (It indicates that the PLL has been stable.)

27:26

/

/

/

25

R/W

0x1

FRAC_CLK_OUT.
PLL clock output when PLL_MODE_SEL=0(PLL_PREDIV_M factor must be
set to 0); No meaning when PLL_MODE_SEL =1.
0: PLL Output=270MHz
1: PLL Output =297MHz.

24

R/W

0x1

PLL_MODE_SEL.
0: Fractional Mode
1: Integer Mode.
Note: When in Fractional mode, the Per Divider M should be set to 0.

23:21

/

/

/

20

R/W

0x0

PLL_SDM_EN.
0: Disable
1: Enable.

19:15

/

/

/

14:8

R/W

0x62

PLL_FACTOR_N.
PLL Factor N.
Factor=0, N=1
Factor=1, N=2
Factor=2, N=3……
Factor=127,N=128.

7:4

/

/

/

3:0

R/W

0x7

PLL_PREDIV_M.
PLL Pre-div Factor(M = Factor+1).
The range is from 1 to 16.

3.3.5.9. PLL_GPU Control Register (Default Value: 0x03006207)
Offset: 0x0038

Register Name: PLL_GPU_CTRL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

PLL_ENABLE.
0: Disable
1: Enable.

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SystemIn the integer mode, The PLL_GPU = (24MHz*N)/M.
In the fractional mode, the PLL Output is select by bit 25.
Note: 8≤N/M≤25(24MHz*N)/M must be in the range of 192MHz~600MHz.
PLL_GPU default is 297MHz.
30:29

/

/

/

28

R

0x0

LOCK.
0: Unlocked
1: Locked (It indicates that the PLL has been stable.)

27:26

/

/

/

25

R/W

0x1

FRAC_CLK_OUT.
PLL clock output when PLL_MODE_SEL=0(PLL_PREDIV_M factor must be
set to 0); no meaning when PLL_MODE_SEL =1.
0: PLL Output=270MHz
1: PLL Output=297MHz.

24

R/W

0x1

PLL_MODE_SEL.
0: Fractional Mode.
1: Integer Mode.
Note: When in Fractional mode, the Per Divider M should be set to 0.

23:21

/

/

/

20

R/W

0x0

PLL_SDM_EN.
0: Disable
1: Enable.

19:15

/

/

/

14:8

R/W

0x62

PLL_FACTOR_N
PLL Factor N.
Factor=0, N=1
Factor=1, N=2
Factor=2, N=3……
Factor=127,N=128.

7:4

/

/

/

3:0

R/W

0x7

PLL_PRE_DIV_M.
PLL Pre Divider (M = Factor+1).
The range is from 1 to 16.

3.3.5.10. PLL_MIPI Control Register (Default Value: 0x00000515)
Offset: 0x0040

Register Name: PLL_MIPI_CTRL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

PLL_ENABLE.
0: Disable

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System
1: Enable.
The PLL_MIPI= (PLL_VIDEO0(1X)*N*K)/M when VFB_SEL=0 (MIPI mode).
When VFB_SEL=1, the PLL Output is depend on these bits: sint_frac,sdiv2,
s6p25_7p5 , pll_feedback_div.6
Note: K≥2;M/N≤3;(PLL_VIDEO0)/M≥24MHz;
PLL_MIPI must be in the range of 500MHz~1.4GHz.
PLL_MIPI default value is 594MHz.
30:29

/

/

/

28

R

0x0

LOCK.
0: Unlocked
1: Locked (It indicates that the PLL has been stable.)

27

R/W

0x0

SINT_FRAC.
When VFB_SEL=1, PLL mode control, otherwise no meaning.
0: Integer Mode
1: Fractional Mode.

26

R/W

0x0

SDIV2.
PLL clock output when VFB_SEL=1; no meaning when VFB_SEL =0
0: PLL Output
1: PLL Output X2.

25

R/W

0x0

S6P25_7P5.
PLL Output is selected by this bit when VFB_SEL=1 and SINT_FRAC=1,
otherwise no meaning.
0: PLL Output=PLL Input*6.25
1: PLL Output= PLL Input *7.5.

24

/

/

/

23

R/W

0

LDO1_EN.
On-chip LDO1 Enable.

22

R/W

0

LDO2_EN.
On-chip LDO2 Enable.

21

R/W

0

PLL_SRC.
PLL Source Select.
0: VIDEO0 PLL
1: /.

20

R/W

0x0

PLL_SDM_EN.
0: Disable
1: Enable.

19:18

/

/

/

17

R/W

0x0

PLL_FEEDBACK_DIV.
PLL feed-back divider control. PLL clock output when VFB_SEL=1; nomeaning when VFB_SEL =0
0:Divided by 5
1:Divided by 7.

16

R/W

0x0

VFB_SEL.

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System
0: MIPI Mode(N, K, M valid)
1:HDMI Mode(sint_frac,sdiv2,s6p25_7p5 , pll_feedback_div valid)
15:12

/

/

/

11:8

R/W

0x5

PLL_FACTOR_N
PLL Factor N.
Factor=0, N=1
Factor=1, N=2……
Factor=15,N=16;

7:6

/

/

/

5:4

R/W

0x1

PLL_FACTOR_K.
PLL Factor K.(K=Factor + 1 )The range is from 2 to 4.

3:0

R/W

0x5

PLL_PRE_DIV_M.
PLL Pre Divider (M = Factor+1).
The range is from 1 to 16.

3.3.5.11. PLL_HSIC Control Register (Default Value: 0x03001300)
Offset: 0x0044

Register Name: PLL_HSIC_CTRL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

PLL_ENABLE.
0: Disable
1: Enable.
In the integer mode, The PLL_HSIC = (24MHz*N)/M.
In the fractional mode, the PLL Output is select by bit 25.
Note: 8≤N/M≤25(24MHz*N)/M must be in the range of 192MHz~600MHz.
PLL_HSIC default is 480MHz.

30:29

/

/

/

28

R

0x0

LOCK
0: Unlocked
1: Locked (It indicates that the PLL has been stable.)

27:26

/

/

/

25

R/W

0x1

FRAC_CLK_OUT.
PLL clock output when PLL_MODE_SEL=0(PLL_PREDIV_M factor must be
set to 0); no meaning when PLL_MODE_SEL =1.
0: PLL Output=270MHz
1: PLL Output=297MHz.

24

R/W

0x1

PLL_MODE_SEL.
0: Fractional Mode
1: Integer Mode.
Note: When in Fractional mode, the Per Divider M should be set to 0.

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System
23:21

/

/

/

20

R/W

0x0

PLL_SDM_EN.
0: Disable
1: Enable.

19:15

/

/

/

14:8

R/W

0x13

PLL_FACTOR_N
PLL Factor N.
Factor=0, N=1
Factor=1, N=2
Factor=2, N=3……
Factor=0x7F,N=128.

7:4

/

/

/

3:0

R/W

0x0

PLL_PRE_DIV_M.
PLL Per Divider (M = Factor+1).
The range is from 1 to 16.

3.3.5.12. PLL_DE Control Register (Default Value: 0x03006207)
Offset: 0x0048

Register Name: PLL_DE_CTRL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

PLL_ENABLE.
0: Disable
1: Enable
In the integer mode, The PLL Output= (24MHz*N)/M.
In the fractional mode, the PLL Output is select by bit 25.
Note: 8≤N/M≤25(24MHz*N)/M must be in the range of 192MHz~600MHz.
Its default is 297MHz.

30:29

/

/

/

28

R

0x0

LOCK
0: Unlocked
1: Locked (It indicates that the PLL has been stable.)

27:26

/

/

/

25

R/W

0x1

FRAC_CLK_OUT.
PLL clock output when PLL_MODE_SEL=0(PLL_PREDIV_M factor must be
set to 0); no meaning when PLL_MODE_SEL =1.
0: PLL Output=270MHz
1: PLL Output =297MHz

24

R/W

0x1

PLL_MODE_SEL.
0: Fractional Mode
1: Integer Mode
Note: When in Fractional mode, the Pre Divider M should be set to 0.

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System
23:21

/

/

/

20

R/W

0x0

PLL_SDM_EN.
0: Disable
1: Enable

19:15

/

/

/

14:8

R/W

0x62

PLL_FACTOR_N
PLL Factor N.
Factor=0, N=1
Factor=1, N=2
Factor=2, N=3……
Factor=0x7F, N=128

7:4

/

/

/

3:0

R/W

0x7

PLL_PRE_DIV_M.
PLL Per Divider (M = Factor+1).
The range is from 1 to 16.

3.3.5.13. PLL_DDR1 Control Register (Default Value: 0x00001800)
Offset: 0x004C

Register Name: PLL_DDR1_CTRL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

PLL_ENABLE.
0: Disable
1: Enable.
The PLL_DDR1 = 24MHz*N/M.
Note: 16≤N≤75.
24MHz*N/M must be in the range of 192MHz~1.6GHz.
Its default is 600 MHz.

30

R/W

0x0

SDRPLL_UPD.
SDRPLL Configuration Update.
Note: When PLL_DDR1 has changed, this bit should be set to 1 to validate
the PLL, otherwise the change is invalid. It will be auto cleared after the
PLL is valid.
0: No effect
1: To validate the PLL_DDR1.

29

/

/

/

28

R

0x0

LOCK
0:Unlocked
1: Locked (It indicates that the PLL has been stable.)

27:25

/

/

/

24

R/W

0x0

PLL_SDM_EN.
0: Disable
1: Enable.

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System
23:15

/

/

/

14:8

R/W

0x18

PLL_FACTOR_N.
N= Factor +1.
The range is from 0 to 127

7:2

/

/

/

1:0

R/W

0x0

PLL_FACTOR_M.
M= Factor +1.
The range is from 0 to 4

3.3.5.14. CPUX/AXI Configuration Register (Default Value: 0x00010300)
Offset: 0x0050

Register Name: CPUX_AXI_CFG_REG

Bit

R/W

Default/Hex

Description

31:18

/

/

/

17:16

R/W

0x1

CPUX_CLK_SRC_SEL.
CPUX Clock Source Select.
CPUX Clock = Clock Source
00: LOSC
01: OSC24M
1X: PLL_CPUX
If the clock source is changed, at most to wait for 8 present running clock
cycles.

15:10

/

/

/

9:8

R/W

0x0

CPU_APB_CLK_DIV.
00: /1
01: /2
10: /3
11: /4
Note: System APB clock source is CPU clock source.

7:2

/

/

/

1:0

R/W

0x0

AXI_CLK_DIV_RATIO.
AXI Clock Divide Ratio.
AXI Clock source is CPU clock source.
00: /1
01: /2
10: /3
11: /43.3.5.15. AHB1/APB1 Configuration Register (Default Value: 0x00001010)
Offset: 0x0054

A64 User Manual(Revision 1.0)

Register Name: AHB1_APB1_CFG_REG

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System
Bit

R/W

Default/Hex

Description

31:14

/

/

/

13:12

R/W

0x1

AHB1_CLK_SRC_SEL.
00: LOSC
01: OSC24M
10: AXI
11: PLL_PERIPH0(1X)/ AHB1_PRE_DIV.

11:10

/

/

/

9:8

R/W

0x0

APB1_CLK_RATIO.
APB1 Clock Divide Ratio. APB1 clock source is AHB1 clock.
00: /2
01: /2
10: /4
11: /8.

7:6

R/W

0x0

AHB1_PRE_DIV
AHB1 Clock Pre Divide Ratio
00: /1
01: /2
10: /3
11: /4.

5:4

R/W

0x1

AHB1_CLK_DIV_RATIO.
AHB1 Clock Divide Ratio.
00: /1
01: /2
10: /4
11: /8.

3:0

/

/

/

3.3.5.16. APB2 Configuration Register (Default Value: 0x01000000)
Offset: 0x0058

Register Name: APB2_CFG_REG

Bit

R/W

Default/Hex

Description

31:26

/

/

/

25:24

R/W

0x1

APB2_CLK_SRC_SEL.
APB2 Clock Source Select
00: LOSC
01: OSC24M
1X: PLL_PERIPH0(2X).
This clock is used for some special module apbclk(UART、TWI). Because
these modules need special clock rate even if the apb1clk changed.

23:18

/

/

/

17:16

R/W

0x0

CLK_RAT_N
Clock Per Divide Ratio (n)A64 User Manual(Revision 1.0)

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System
00: /1
01: /2
10: /4
11: /8.
15:5

/

/

/

4:0

R/W

0x0

CLK_RAT_M.
Clock Divide Ratio (m)The pre-divided clock is divided by (m+1). The divider is from 1 to 32.

3.3.5.17. AHB2 Configuration Register (Default Value: 0x00000000)
Offset: 0x005C

Register Name: AHB2_CFG_REG

Bit

R/W

Default/Hex

Description

31:2

/

/

/

1:0

R/W

0x0

AHB2_CLK_CFG.
00: AHB1 Clock
01: PLL_PERIPH0(1X)/2
1X: /EMAC ,USB HCI0 default clock source is AHB2 Clock.
Its default value is 300Mhz.

3.3.5.18. Bus Clock Gating Register0 (Default Value: 0x00000000)
Offset: 0x0060

Register Name: BUS_CLK_GATING_REG0

Bit

R/W

Default/Hex

Description

31:30

/

/

/

29

R/W

0x0

USBOHCI0_GATING.
Gating Clock for USB OHCI0
0: Mask
1: Pass

28

R/W

0x0

USB-OTG-OHCI_GATING.
Gating Clock for USB-OTG-OHCI
0: Mask
1: Pass

27:26

/

/

/

25

R/W

0x0

USBEHCI0_GATING.
Gating Clock For USB EHCI0
0: Mask
1: Pass

24

R/W

0x0

USB-OTG-EHCI_GATING.
Gating Clock For USB-OTG-EHCI

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System
0: Mask
1: Pass
23

R/W

0x0

USB-OTG-Device_GATING.
Gating Clock For USB OTG Device
0: Mask
1: Pass

22

/

/

/

21

R/W

0x0

SPI1_GATING.
Gating Clock For SPI1
0: Mask
1: Pass.

20

R/W

0x0

SPI0_GATING.
Gating Clock For SPI0
0: Mask
1: Pass.

19

R/W

0x0

HSTMR_GATING.
Gating Clock For High Speed Timer
0: Mask
1: Pass.

18

R/W

0x0

TS_GATING.
Gating Clock For TS
0: Mask
1: Pass

17

R/W

0x0

EMAC_GATING.
Gating Clock For EMAC
0: Mask
1: Pass

16:15

/

/

/

14

R/W

0x0

DRAM_GATING.
Gating Clock For DRAM
0: Mask
1: Pass.

13

R/W

0x0

NAND_GATING.
Gating Clock For NAND
0: Mask
1: Pass.

12:11

/

/

/

10

R/W

0x0

SMHC2_GATING.
Gating Clock For SMHC2
0: Mask
1: Pass.

9

R/W

0x0

SMHC1_GATING.
Gating Clock For SMHC1
0: Mask

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System
1: Pass.
8

R/W

0x0

SMHC0_GATING.
Gating Clock For SMHC0
0: Mask
1: Pass.

7

/

/

/

6

R/W

0x0

DMA_GATING.
Gating Clock For DMA
0: Mask
1: Pass.

5

R/W

0x0

CE_GATING.
Gating Clock For CE
0: Mask
1: Pass.

4:2

/

/

/

1

R/W

0x0

MIPIDSI_GATING.
Gating Clock For MIPI DSI
0: Mask
1: Pass.

0

/

/

/

3.3.5.19. Bus Clock Gating Register1 (Default Value: 0x00000000)
Offset: 0x0064

Register Name: BUS_CLK_GATING_REG1

Bit

R/W

Default/Hex

Description

31:23

/

/

/

22

R/W

0x0

SPINLOCK_GATING.
0: Mask
1: Pass.

21

R/W

0x0

MSGBOX_GATING.
0: Mask
1: Pass.

20

R/W

0x0

GPU_GATING.
0: Mask
1: Pass.

19:13

/

/

/

12

R/W

0x0

DE_GATING.
0: Mask
1: Pass.

11

R/W

0x0

HDMI_GATING.
0: Mask
1: Pass.

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System
10:9

/

/

/

8

R/W

0x0

CSI_GATING.
0: Mask
1: Pass.

7:6

/

/

/

5

R/W

0x0

DEINTERLACE_GATING.
Gating Clock For DEINTERLACE
0: Mask
1: Pass

4

R/W

0x0

TCON1_GATING.
Gating Clock For TCON1
0: Mask
1: Pass.

3

R/W

0x0

TCON0_GATING.
Gating Clock For TCON0
0: Mask
1: Pass.

2:1

/

/

/

0

R/W

0x0

VE_GATING.
Gating Clock For VE
0: Mask
1: Pass.

3.3.5.20. Bus Clock Gating Register2 (Default Value: 0x00000000)
Offset: 0x0068

Register Name: BUS_CLK_GATING_REG2

Bit

R/W

Default/Hex

Description

31:15

/

/

/

14

R/W

0x0

I2S/PCM-2_GATING.
Gating Clock For I2S/PCM-2
0: Mask
1: Pass.

13

R/W

0x0

I2S/PCM-1_GATING.
Gating Clock For I2S/PCM-1
0: Mask
1: Pass.

12

R/W

0x0

I2S/PCM-0_GATING.
Gating Clock For I2S/PCM-0
0: Mask
1: Pass.

11:9

/

/

/

8

R/W

0x0

THS_GATING.

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SystemGating Clock For THS
0: Mask
1: Pass
6:7

/

/

/

5

R/W

0x0

PIO_GATING.
Gating Clock For PIO
0: Mask
1: Pass.

4:2

/

/

/

1

R/W

0x0

OWA_GATING.
Gating Clock For OWA
0: Mask
1: Pass

0

R/W

0x0

AC_DIG_GATING.
Gating Clock For AC Digital
0: Mask
1: Pass

3.3.5.21. Bus Clock Gating Register3 (Default Value: 0x00000000)
Offset: 0x006C

Register Name: BUS_CLK_GATING_REG3

Bit

R/W

Default/Hex

Description

31:21

/

/

/

20

R/W

0x0

UART4_GATING.
Gating Clock For UART4
0: Mask
1: Pass.

19

R/W

0x0

UART3_GATING.
Gating Clock For UART3
0: Mask
1: Pass.

18

R/W

0x0

UART2_GATING.
Gating Clock For UART2
0: Mask
1: Pass.

17

R/W

0x0

UART1_GATING.
Gating Clock For UART1
0: Mask
1: Pass.

16

R/W

0x0

UART0_GATING.
Gating Clock For UART0
0: Mask
1: Pass.

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15:6

/

/

/

5

R/W

0x0

SCR_GATING.
Gating Clock For SCR
0: Mask
1: Pass

4:3

/

/

/

2

R/W

0x0

TWI2_GATING.
Gating Clock For TWI2
0: Mask
1: Pass.

1

R/W

0x0

TWI1_GATING.
Gating Clock For TWI1
0: Mask
1: Pass.

0

R/W

0x0

TWI0_GATING.
Gating Clock For TWI0
0: Mask
1: Pass.

3.3.5.22. Bus Clock Gating Register4 (Default Value: 0x00000000)
Offset: 0x0070

Register Name: BUS_CLK_GATING_REG4

Bit

R/W

Default/Hex

Description

31:8

/

/

/

7

R/W

0x0

DBGSYS_GATING.
Gating Clock For DBGSYS
0: Mask
1: Pass

6:0

/

/

/

3.3.5.23. THS Clock Register (Default Value: 0x00000000)
Offset: 0x0074

Register Name: THS_CLK_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

SCLK_GATING.
Gating Special Clock.
0: Clock is OFF
1: Clock is ON
This special clock = Clock Source/CLK_DIV_RATIO.

30:26

/

/

/

25:24

R/W

0x0

THS_CLK_SRC_SEL.

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System
Clock Source Select
00: OSC24M
01: /
10: /
11: /
23:2

/

/

/

1:0

R/W

0x0

THS_CLK_DIV_RATIO.
THS clock divide ratio.
00: /1
01: /2
10: /4
11: /6

3.3.5.24. NAND Clock Register (Default Value: 0x00000000)
Offset: 0x0080

Register Name: NAND_CLK_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

SCLK_GATING.
Gating Special Clock(Max Clock = 200MHz)
0: Clock is OFF
1: Clock is ON.
SCLK = Clock Source/Divider N/Divider M.

30:26

/

/

/

25:24

R/W

0x0

CLK_SRC_SEL.
Clock Source Select
00: OSC24M
01: PLL_PERIPH0
10: PLL_PERIPH1
11: /

23:18

/

/

/

17:16

R/W

0x0

CLK_DIV_RATIO_N.
Clock Pre Divide Ratio (n)00: /1
01: /2
10: /4
11: /8.

15:4

/

/

/

3:0

R/W

0x0

CLK_DIV_RATIO_M
Clock Divide Ratio (m)The pre-divided clock is divided by (m+1). The divider M is from 1 to 16.

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3.3.5.25. SMHC0 Clock Register (Default Value: 0x00000000)
Offset: 0x0088

Register Name: SMHC0_CLK_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

SCLK_GATING.
Gating Special Clock(Max Clock = 384MHz)
0: Clock is OFF
1: Clock is ON.
SCLK = Clock Source/Divider N/Divider M.

30:26

/

/

/

25:24

R/W

0x0

CLK_SRC_SEL.
Clock Source Select
00: OSC24M
01: PLL_PERIPH0(2X)
10: PLL_PERIPH1(2X)
11: /.

23:18

/

/

/

17:16

R/W

0x0

CLK_DIV_RATIO_N.
Clock Pre Divide Ratio (n)00: /1
01: /2
10: /4
11: /8.

15:4

/

/

/

3:0

R/W

0x0

CLK_DIV_RATIO_M.
Clock Divide Ratio (m)The pre-divided clock is divided by (m+1). The divider is from 1 to 16.

3.3.5.26. SMHC1 Clock Register (Default Value: 0x00000000)
Offset: 0x008C

Register Name: SMHC1_CLK_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

SCLK_GATING.
Gating Special Clock(Max Clock = 384MHz)
0: Clock is OFF
1: Clock is ON.
SCLK = Clock Source/Divider N/Divider M.

30:26

/

/

/

25:24

R/W

0x0

CLK_SRC_SEL.
Clock Source Select
00: OSC24M
01: PLL_PERIPH0(2X)

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10: PLL_PERIPH1(2X)
11: /.
23:18

/

/

/

17:16

R/W

0x0

CLK_DIV_RATIO_N.
Clock Pre Divide Ratio (n)00: /1
01: /2
10: /4
11: /8.

15:4

/

/

/

3:0

R/W

0x0

CLK_DIV_RATIO_M.
Clock Divide Ratio (m)The pre-divided clock is divided by (m+1). The divider is from 1 to 16.

3.3.5.27. SMHC2 Clock Register (Default Value: 0x00000000)
Offset: 0x0090

Register Name: SMHC2_CLK_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

SCLK_GATING.
Gating Special Clock(Max Clock = 384MHz)
0: Clock is OFF
1: Clock is ON.
SCLK = Clock Source/Divider N/Divider M.

30:26

/

/

/

25:24

R/W

0x0

CLK_SRC_SEL.
Clock Source Select
00: OSC24M
01: PLL_PERIPH0(2X)
10: PLL_PERIPH1(2X)
11: /.

23:18

/

/

/

17:16

R/W

0x0

CLK_DIV_RATIO_N.
Clock Pre Divide Ratio (n)00: /1
01: /2
10: /4
11: /8.

15:4

/

/

/

3:0

R/W

0x0

CLK_DIV_RATIO_M.
Clock Divide Ratio (m)The pre-divided clock is divided by (m+1). The divider is from 1 to 16.

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3.3.5.28. TS Clock Register (Default Value: 0x00000000)
Offset: 0x0098

Register Name: TS_CLK_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

SCLK_GATING.
Gating of SCLK (Max Clock = 200MHz).
0: Clock is OFF
1: Clock is ON
SCLK = Clock Source/Divider N/Divider M.

30:28

/

/

/

27:24

R/W

0x0

CLK_SRC_SEL.
Clock Source Select0000: OSC24M
0001: PLL_PERIPH0(1X)
Others: /

23:18

/

/

/

17:16

R/W

0x0

CLK_DIV_RATIO_N.
Clock pre-divide ratio (n)The select clock source is pre-divided by 2^n. The divider is 1/2/4/8.

15:4

/

/

/

3:0

R/W

0x0

CLK_DIV_RATIO_M.
Clock divide ratio (m)The pre-divided clock is divided by (m+1). The divider is from 1 to 16.

3.3.5.29. CE Clock Register (Default Value: 0x00000000)
Offset: 0x009C

Register Name: CE_CLK_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

SCLK_GATING.
Gating Special Clock(Max Clock = 400MHz)
0: Clock is OFF
1: Clock is ON.
SCLK = Clock Source/Divider N/Divider M.

30:26

/

/

/

25:24

R/W

0x0

CLK_SRC_SEL.
Clock Source Select
00: OSC24M
01: PLL_PERIPH0（2X）
10: PLL_PERIPH1（2X）
11: /.

23:18

/

/

/

17:16

R/W

0x0

CLK_DIV_RATIO_N.

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Clock Pre Divide Ratio (n)00: /1
01: /2
10: /4
11: /8.
15:4

/

/

/

3:0

R/W

0x0

CLK_DIV_RATIO_M.
Clock divide ratio (m)The pre-divided clock is divided by (m+1). The divider is from 1 to 16.

3.3.5.30. SPI0 Clock Register (Default Value: 0x00000000)
Offset: 0x00A0

Register Name: SPI0_CLK_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

SCLK_GATING.
Gating Special Clock(Max Clock = 200MHz)
0: Clock is OFF
1: Clock is ON.
SCLK = Clock Source/Divider N/Divider M.

30:26

/

/

/

25:24

R/W

0x0

CLK_SRC_SEL.
Clock Source Select
00: OSC24M
01: PLL_PERIPH0(1X)
10: PLL_PERIPH1(1X)
11: /

23:18

/

/

/

17:16

R/W

0x0

CLK_DIV_RATIO_N.
Clock Pre Divide Ratio (n)00: /1
01: /2
10: /4
11: /8.

15:4

/

/

/

3:0

R/W

0x0

CLK_DIV_RATIO_M.
Clock Divide Ratio (m)The pre-divided clock is divided by (m+1). The divider M is from 1 to 16.

3.3.5.31. SPI1 Clock Register (Default Value: 0x00000000)
Offset: 0x00A4

A64 User Manual(Revision 1.0)

Register Name: SPI1_CLK_REG

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System
Bit

R/W

Default/Hex

Description

31

R/W

0x0

SCLK_GATING.
Gating Special Clock(Max Clock = 200MHz)
0: Clock is OFF
1: Clock is ON.
SCLK= Clock Source/Divider N/Divider M.

30:26

/

/

/

25:24

R/W

0x0

CLK_SRC_SEL.
Clock Source Select
00: OSC24M
01: PLL_PERIPH0(1X)
10: PLL_PERIPH1(1X)
11: /

23:18

/

/

/

17:16

R/W

0x0

CLK_DIV_RATIO_N.
Clock Pre Divide Ratio (n)00: /1
01: /2
10: /4
11: /8.

15:4

/

/

/

3:0

R/W

0x0

CLK_DIV_RATIO_M.
Clock Divide Ratio (m)The pre-divided clock is divided by (m+1). The divider M is from 1 to 16.

3.3.5.32. I2S/PCM 0 Clock Register (Default Value: 0x00000000)
Offset: 0x00B0

Register Name: I2S/PCM 0_CLK_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

SCLK_GATING.
Gating Special Clock(Max Clock = 200MHz)
0: Clock is OFF
1: Clock is ON.

30:18

/

/

/

17:16

R/W

0x0

CLK_SRC_SEL.
00: PLL_AUDIO (8X)
01: PLL_AUDIO(8X)/2
10: PLL_AUDIO(8X)/4
11: PLL_AUDIO

15:0

/

/

/

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3.3.5.33. I2S/PCM 1 Clock Register (Default Value: 0x00000000)
Offset: 0x00B4

Register Name: I2S/PCM 1_CLK_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

SCLK_GATING.
Gating Special Clock(Max Clock = 200MHz)
0: Clock is OFF
1: Clock is ON.

30:18

/

/

/

17:16

R/W

0x0

CLK_SRC_SEL.
00: PLL_AUDIO (8X)
01: PLL_AUDIO(8X)/2
10: PLL_AUDIO(8X)/4
11: PLL_AUDIO

15:0

/

/

/

3.3.5.34. I2S/PCM 2 Clock Register (Default Value: 0x00000000)
Offset: 0x00B8

Register Name: I2S/PCM 2_CLK_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

SCLK_GATING.
Gating Special Clock(Max Clock = 200MHz)
0: Clock is OFF
1: Clock is ON.

30:18

/

/

/

17:16

R/W

0x0

CLK_SRC_SEL.
00: PLL_AUDIO(8X)
01: PLL_AUDIO(8X)/2
10: PLL_AUDIO(8X)/4
11: PLL_AUDIO

15:0

/

/

/

3.3.5.35. OWA Clock Register (Default Value: 0x00000000)
Offset: 0x00C0

Register Name: OWA_CLK_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

SCLK_GATING.
Gating Special Clock(Max Clock = 200MHz)
0: Clock is OFF
1: Clock is ON.
SCLK= PLL_AUDIO/Divider M.

30:4

/

/

/

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3:0

R/W

0x0

CLK_DIV_RATIO_M.
Clock Divide Ratio (m)The pre-divided clock is divided by (m+1). The divider M is from 1 to 16.

3.3.5.36. USBPHY Configuration Register (Default Value: 0x00000000)
Offset: 0x00CC

Register Name: USBPHY_CFG_REG

Bit

R/W

Default/Hex

Description

31:24

/

/

/

23:22

R/W

0x0

OHCI1_12M_SRC_SEL.
OHCI1 12M Source Select00: 12M divided from 48M
01: 12M divided from 24M
10: LOSC
11: /

21:20

R/W

0x0

OHCI0_12M_SRC_SEL.
OHCI0 12M Source Select00: 12M divided from 48M
01: 12M divided from 24M
10: LOSC
11: /

19:18

/

/

/

17:16

R/W

0x0

SCLK_GATING_OHCI.
Gating Special Clock For OHCI(48M and 12M)
00: Clock is OFF
01: OTG-OHCI Clock is ON
10: Clock is OFF
11:OTG-OHCI and OHCI0 Clock is ON

15:12

/

/

/

11

R/W

0

SCLK_GATING_12M
Gating Special 12M Clock For HSIC
0: Clock is OFF
1: Clock is ON.
The special 12M clock = OSC24M/2.

10

R/W

0

SCLK_GATING_HSIC
Gating Special Clock For HSIC
0: Clock is OFF
1: Clock is ON.
The special clock is from PLL_HSIC.

9

R/W

0x0

SCLK_GATING_USBPHY1.
Gating Special Clock For USB PHY1
0: Clock is OFF
1: Clock is ON

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8

R/W

0x0

SCLK_GATING_USBPHY0.
Gating Special Clock For USB PHY0
0: Clock is OFF
1: Clock is ON

7:3

/

/

/

2

R/W

0x0

USBHSIC_RST.
USB HSIC Reset Control
0: Assert
1: De-assert.

1

R/W

0x0

USBPHY1_RST.
USB PHY1 Reset Control
0: Assert
1: De-assert

0

R/W

0x0

USBPHY0_RST.
USB PHY0 Reset Control
0: Assert
1: De-assert

3.3.5.37. DRAM Configuration Register (Default Value: 0x00000000)
Offset: 0x00F4

Register Name: DRAM_CFG_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

DRAM_CTR_RST.
DRAM Controller Reset For AHB Clock Domain.
0: Assert
1: De-assert.

30:22

/

/

/

21:20

R/W

0x0

DDR_SRC_SELECT.
00: PLL_DDR0
01: PLL_DDR1
1X: /.

19:17

/

/

/

16

R/W

0x0

SDRCLK_UPD.
SDRCLK Configuration Update.
0:Invalid
1:Valid.
Note: Set this bit will validate Configuration . It will be auto cleared after
the Configuration is valid.
The DRAMCLK Source is from PLL_DDR.

15:2

/

/

/

1:0

R/W

0x0

DRAM_DIV_M.
DRAMCLK Divider of Configuration.
The clock is divided by (m+1). The divider M should be from 1 to 4.

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3.3.5.38. PLL_DDR Configuration Register (Default Value: 0xCCCA0000)
Offset: 0x00F8

Register Name: PLL_DDR_CFG_REG

Bit

R/W

Default/Hex

Description

31:16

R/W

0xCCCA

PLL_SSCThe amplitude of SSC must be the integer times of (2^Step).
Spread Frequency Amplitude =(SSC Amplitude +2^Step)*24/(2^17),unit is
Mhz

15:13

/

/

/

12

R/W

0x0

PLL_DDR1_MODE.
0: Normal Mode
1: Continuously Frequency Scale.

11:7

/

/

/

6:4

R/W

0x0

PLL_DDR1_PHASE_COMPENSATE.
The value of bit[6:4] is based on 24M clock, then the default PLL_DDR
phase compensate is (3/24000000) s.

3:0

R/W

0x0

PLL_DDR1_STEP.
0000: 0.00439MHz/us (576/2^17)0001: 0.00879MHz/us (576/2^16)0010: 0.01758MHz/us (576/2^15)0011: 0.03516MHz/us (576/2^14)0100: 0.07031MHz/us (576/2^13)0101: 0.14062MHz/us (576/2^12)0110: 0.28125MHz/us (576/2^11)0111: 0.56250MHz/us (576/2^10)
1000: 1.12500MHz/us (576/2^9)1001: 2.25000MHz/us (576/2^8)1010: 4.50000Mhz/us (576/2^7)
1011: 9.00000Mhz/us (576/2^6)
Others: 0.00439MHz/us (576/2^17).

3.3.5.39. MBUS Reset Register (Default Value: 0x80000000)
Offset: 0x00FC

Register Name: MBUS_RST_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x1

MBUS_RESET.
0: Assert
1: De-assert.

30:0

/

/

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3.3.5.40. DRAM Clock Gating Register (Default Value: 0x00000000)
Offset: 0x0100

Register Name: DRAM_CLK_GATING_REG

Bit

R/W

Default/Hex

Description

31:4

/

/

/

3

R/W

0x0

TS_DCLK_GATING.
Gating DRAM Clock For TS
0: Mask
1: Pass

2

R/W

0x0

DEINTERLACE_DCLK_GATING.
Gating DRAM SCLK(1X) For DEINTERLACE
0: Mask
1: Pass

1

R/W

0x0

CSI_DCLK_GATING.
Gating DRAM Clock For CSI
0: Mask
1: Pass

0

R/W

0x0

VE_DCLK_GATING.
Gating DRAM Clock For VE
0: Mask
1: Pass

3.3.5.41. DE Clock Gating Register (Default Value: 0x00000000)
Offset: 0x0104

Register Name: DE_CLK_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

SCLK_GATING.
Gating Special Clock
0: Clock is OFF
1: Clock is ON
This special clock = Clock Source/Divider M.

30:27

/

/

/

26:24

R/W

0x0

CLK_SRC_SEL.
Clock Source Select000: PLL_PERIPH0(2X)
001: PLL_DE
Others: /

23:4

/

/

/

3:0

R/W

0x0

CLK_DIV_RATIO_M.
Clock Divide Ratio (m)The pre-divided clock is divided by (m+1). The divider is from 1 to 16.

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3.3.5.42. TCON0 Clock Register (Default Value: 0x00000000)
Offset: 0x0118

Register Name: TCON0_CLK_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

SCLK_GATING.
Gating Special Clock
0: Clock is OFF
1: Clock is ON.

30:27

/

/

/

26:24

R/W

0x0

CLK_SRC_SEL.
Clock Source Select000: PLL_MIPI
001: /
010: PLL_VIDEO0(2X)
011~111: /.

23:0

/

/

/

3.3.5.43. TCON1 Clock Register (Default Value: 0x00000000)
Offset: 0x011C

Register Name: TCON1_CLK_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

SCLK_GATING.
Gating Special Clock
0: Clock is OFF
1: Clock is ON.
SCLK = Clock Source/ Divider M.

30:26

/

/

/

25:24

R/W

0x0

SCLK_SEL.
Special Clock Source Select00: PLL_VIDEO0(1X)
01: /10: PLL_VIDEO1(1X)
11: /.

23:4

/

/

/

3:0

R/W

0x0

CLK_DIV_RATIO_M.
Clock divide ratio (m)The pre-divided clock is divided by (m+1). The divider is from 1 to 16.

3.3.5.44. DEINTERLACE Clock Register (Default Value: 0x00000000)
Offset: 0x0124
A64 User Manual(Revision 1.0)

Register Name: DEINTERLACE_CLK_REG
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System
Bit

R/W

Default/Hex

Description

31

R/W

0x0

SCLK_GATING.
Gating Special Clock
0: Clock is OFF
1: Clock is ON
SCLK = Clock Source/ Divider M

30:27

/

/

/

26:24

R/W

0x0

CLK_SRC_SEL.
Clock Source Select000: PLL_PERIPH0(1X)
001: PLL_PERIPH1(1X)
Others: /

23:4

/

/

/

3:0

R/W

0x0

CLK_DIV_RATIO_M.
Clock Divide Ratio (m)The pre-divided clock is divided by (m+1). The divider is from 1 to 16.

3.3.5.45. CSI_MISC Clock Register (Default Value: 0x00000000)
Offset: 0x0130

Register Name: CSI_MISC_CLK_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

CSI_MISC_SCLK_GATING.
Gating Special Clock
0: Clock is OFF
1: Clock is ON
SCLK = OSC24M.

30:0

/

/

/

3.3.5.46. CSI Clock Register (Default Value: 0x00000000)
Offset: 0x0134

Register Name: CSI_CLK_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

CSI_SCLK_GATING.
Gating Special Clock
0: Clock is OFF
1: Clock is ON.
SCLK= Special Clock Source/CSI_SCLK_DIV_M.

30:27

/

/

/

26:24

R/W

0x0

SCLK_SRC_SEL.
Special Clock Source Select000: PLL_PERIPH0(1X)

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System
001: PLL_PERIPH1(1X)
Others: /
23:20

/

/

/

19:16

R/W

0x0

CSI_SCLK_DIV_M.
CSI Clock Divide Ratio (m)The pre-divided clock is divided by (m+1). The divider M is from 1 to 16.

15

R/W

0x0

CSI_MCLK_GATING.
Gating Master Clock
0: Clock is OFF
1: Clock is ON
This clock =Master Clock Source/ CSI_MCLK_DIV_M.

14:11

/

/

/

10:8

R/W

0x0

MCLK_SRC_SEL.
Master Clock Source Select000: OSC24M
001: PLL_VIDEO1(1X)
010: PLL_PERIPH1
Others: /

7:5

/

/

/

4:0

R/W

0x0

CSI_MCLK_DIV_M.
CSI Master Clock Divide Ratio (m)The pre-divided clock is divided by (m+1). The divider is from 1 to 32.

3.3.5.47. VE Clock Register (Default Value: 0x00000000)
Offset: 0x013C

Register Name: VE_CLK_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

VE_SCLK_GATING.
Gating Special Clock
0: Clock is OFF
1: Clock is ON.
SCLK = PLL_VE /Divider N.

30:19

/

/

/.

18:16

R/W

0x0

CLK_DIV_RATIO_N.
Clock Pre Divide Ratio (N)The select clock source is pre-divided by n+1. The divider N is from 1 to 8.

15:0

/

/

/

3.3.5.48. AC Digital Clock Register (Default Value: 0x00000000)
Offset: 0x0140

A64 User Manual(Revision 1.0)

Register Name: AC_DIG_CLK_REG

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System
Bit

R/W

Default/Hex

Description

31

R/W

0x0

SCLK_1X_GATING.
Gating Special Clock
0: Clock is OFF
1: Clock is ON.
SCLK = 1X Clock Output.

30

R/W

0x0

SCLK_4X_GATING.
Gating Special Clock
0: Clock is OFF
1: Clock is ON.
SCLK=4X Clock Output.

29:0

/

/

/

3.3.5.49. AVS Clock Register (Default Value: 0x00000000)
Offset: 0x0144

Register Name: AVS_CLK_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

SCLK_GATING.
Gating Special Clock
0: Clock is OFF
1: Clock is ON.
SCLK= OSC24M.

30:0

/

/

/

3.3.5.50. HDMI Clock Register (Default Value: 0x00000000)
Offset: 0x0150

Register Name: HDMI_CLK_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

SCLK_GATING.
Gating Special Clock
0: Clock is OFF
1: Clock is ON.
SCLK= Clock Source/ Divider M.

30:26

/

/

/

25:24

R/W

0x0

SCLK_SEL.
Special Clock Source Select00: PLL_VIDEO0(1X)
01:PLL_VIDEO1(1X)
Others: /

23:4

/

/

/

3:0

R/W

0x0

CLK_DIV_RATIO_M.

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Clock Divide Ratio (m)The pre-divided clock is divided by (m+1). The divider M is from 1 to 16.

3.3.5.51. HDMI Slow Clock Register (Default Value: 0x00000000)
Offset: 0x0154

Register Name: HDMI_SLOW_CLK_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

HDMI_DDC_CLK_GATING.
0: Clock is OFF
1: Clock is ON.
SCLK = OSC24M.

30:0

/

/

/

3.3.5.52. MBUS Clock Register (Default Value: 0x00000000)
Offset: 0x015C
Bit

R/W

Register Name: MBUS_CLK_REG
Default/Hex

Description

31

R/W

0x0

MBUS_SCLK_GATING.
Gating Clock for MBUS
0: Clock is OFF
1: Clock is ON.
MBUS_CLOCK = Clock Source/Divider M

30:26

/

/

/

25:24

R/W

0x0

MBUS_SCLK_SRC
Clock Source Select
00: OSC24M
01: PLL_PERIPH0(2X)
10: PLL_DDR0
11: PLL_DDR1.

23:3

/

/

/

0x0

MBUS_SCLK_RATIO_M
Clock Divide Ratio (m)The pre-divided clock is divided by (m+1). The divider M is from 1 to 8.
Note: If the clock has been changed ,it must wait for at least 16 cycles.

2:0

R/W

3.3.5.53. MIPI_DSI Clock Register (Default Value: 0x00000000)
Offset: 0x0168

Register Name: MIPI_DSI_CLK_REG

Bit

R/W

Default/Hex

Description

31:16

/

/

/

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15

R/W

0x0

DSI_DPHY_GATING.
Gating DSI DPHY Clock
0: Clock is OFF
1: Clock is ON.
This DSI DPHY clock =Clock Source/ DPHY_CLK_DIV_M.

14:10

/

/

/

9:8

R/W

0x0

DSI_DPHY_SRC_SEL.
DSI DPHY Clock Source Select.
00: PLL_VIDEO0(1X)
01: /10: PLL_PERIPH0(1X)
11: /.

7:4

/

/

/.

3:0

R/W

0x0

DPHY_CLK_DIV_M.
DSI DPHY Clock divide ratio (m)The pre-divided clock is divided by (m+1). The divider is from 1 to 16.

3.3.5.54. GPU Clock Register (Default Value: 0x00000000)
Offset: 0x01A0

Register Name: GPU_CLK_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

SCLK_GATING.
0: Clock is OFF
1: Clock is ON.
SCLK= PLL_GPU/Divider N.

30:3

/

/

/.

2:0

R/W

0x0

CLK_DIV_RATIO_N.
Clock Pre Divide Ratio (N)The select clock source is pre-divided by( n+1). The divider N is from 1 to
8.

3.3.5.55. PLL Stable Time Register0 (Default Value: 0x000000FF)
Offset: 0x0200

Register Name: PLL_STABLE_TIME_REG0

Bit

R/W

Default/Hex

Description

31:16

/

/

/

15:0

R/W

0x00FF

PLL_LOCK_TIME
PLL Lock Time (Unit: us).
Note: When any PLL (except PLL_CPU) is enabled or changed, thecorresponding PLL lock bit will be set after the PLL STABLE Time.

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3.3.5.56. PLL Stable Time Register1 (Default Value: 0x000000FF)
Offset: 0x0204

Register Name: PLL_STABLE_TIME_REG1

Bit

R/W

Default/Hex

Description

31:16

/

/

/

15:0

R/W

0x00FF

PLL_CPU_LOCK_TIME
PLL_CPU Lock Time (Unit: us).
Note: When PLL_CPU is enabled or changed, the PLL_CPU lock bit will be
set after the PLL_CPU STABLE Time.

3.3.5.57. PLL_PERIPH1 Bias Register (Default Value: 0x10100010)
Offset: 0x021C

Register Name: PLL_PERIPH1_BIAS_REG

Bit

R/W

Default/Hex

Description

31:29

/

/

/

28:24

R/W

0x10

PLL_VCO_BIAS_CTRL.
PLL VCO Bias Control[4:0].

23:21

/

/

/

20:16

R/W

0x10

PLL_CUR_BIAS_CTRL.
PLL Current Bias Control[4:0].

15:5

/

/

/

4

R/W

0x1

PLL_BANDW_CTRL.
PLL Band Width Control.
0: Narrow
1: Wide.

3:2

/

/

/

1:0

R/W

0x0

PLL_DAMP_FACTOR_CTRL.
PLL Damping Factor Control[1:0].

3.3.5.58. PLL_CPUX Bias Register (Default Value: 0x08100200)
Offset: 0x0220

Register Name: PLL_CPUX_BIAS_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

VCO_RST.
VCO reset in.

30:29

/

/

/

28

R/W

0x0

EXG_MODE.
Exchange Mode.
Note: CPU PLL source will select PLL_PERIPH0 instead of PLL_CPU

27:24

R/W

0x8

PLL_VCO_BIAS_CTRL.

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PLL VCO Bias Control[3:0].
23:21

/

/

/

20:16

R/W

0x10

PLL_CUR_BIAS_CTRL.
PLL Current Bias Control[4:0].

15:11

/

/

/

10:8

R/W

0x2

PLL_LOCK_CTRL.
PLL Lock Time Control[2:0].

7:4

/

/

/

3:0

R/W

0x0

PLL_DAMP_FACT_CTRL.
PLL Damping Factor Control[3:0].

3.3.5.59. PLL_AUDIO Bias Register (Default Value: 0x10100000)
Offset: 0x0224

Register Name: PLL_AUDIO_BIAS_REG

Bit

R/W

Default/Hex

Description

31:29

/

/

/

28:24

R/W

0x10

PLL_VCO_BIAS.
PLL VCO Bias Current[4:0].

23:21

/

/

/

20:16

R/W

0x10

PLL_CUR_BIAS_CTRL.
PLL Current Bias Control[4:0].

15:0

/

/

/

3.3.5.60. PLL_VIDEO0 Bias Register (Default Value: 0x10100000)
Offset: 0x0228

Register Name: PLL_VIDEO0_BIAS_REG

Bit

R/W

Default/Hex

Description

31:29

/

/

/

28:24

R/W

0x10

PLL_VCO_BIAS_CTRL.
PLL VCO Bias Control[4:0].

23:21

/

/

/

20:16

R/W

0x10

PLL_CUR_BIAS_CTRL.
PLL Current Bias Control[4:0].

15:3

/

/

/

2:0

R/W

0x0

PLL_DAMP_FACTOR_CTRL.
PLL Damping Factor Control[2:0].

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3.3.5.61. PLL_VE Bias Register (Default Value: 0x10100000)
Offset: 0x022C

Register Name: PLL_VE_BIAS_REG

Bit

R/W

Default/Hex

Description

31:29

/

/

/

28:24

R/W

0x10

PLL_VCO_BIAS_CTRL.
PLL VCO Bias Control[4:0].

23:21

/

/

/

20:16

R/W

0x10

PLL_CUR_BIAS_CTRL.
PLL Current Bias Control[4:0].

15:3

/

/

/

2:0

R/W

0x0

PLL_DAMP_FACTOR_CTRL.
PLL Damping Factor Control[2:0].

3.3.5.62. PLL_DDR0 Bias Register (Default Value: 0x81104000)
Offset: 0x0230

Register Name: PLL_DDR0_BIAS_REG

Bit

R/W

Default/Hex

Description

31:28

R/W

0x8

PLL_VCO_BIAS.
PLL VCO Bias Control[3:0].

27:26

/

/

/.

25

R/W

0x0

PLL_VCO_GAIN_CTRL_EN.
PLL VCO Gain Control Enable.
0: Disable
1: Enable.

24

R/W

0x1

PLL_BANDW_CTRL.
PLL Band Width Control.
0: Narrow
1: Wide.

23:21

/

/

/

20:16

R/W

0x10

PLL_CUR_BIAS_CTRL.
PLL Current Bias Control[4:0].

15

/

/

/

14:12

R/W

0x4

PLL_VCO_GAIN_CTRL.
PLL VCO Gain Control Bit[2:0].

11:4

/

/

/

3:0

R/W

0x0

PLL_DAMP_FACTOR_CTRL.
PLL Damping Factor Control[3:0].

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3.3.5.63. PLL_PERIPH0 Bias Register (Default Value: 0x10100010)
Offset: 0x0234

Register Name: PLL_PERIPH0_BIAS_REG

Bit

R/W

Default/Hex

Description

31:29

/

/

/

28:24

R/W

0x10

PLL_VCO_BIAS.
PLL VCO Bias[4:0].

23:21

/

/

/

20:16

R/W

0x10

PLL_BIAS_CUR_CTRL.
PLL Bias Current Control.

15:5

/

/

/

4

R/W

0x1

PLL_BANDW_CTRL.
PLL Band Width Control.
0: Narrow
1: Wide

3:2

/

/

/

1:0

R/W

0x0

PLL_DAMP_FACTOR_CTRL.
PLL Damping Factor Control[1:0].

3.3.5.64. PLL_VIDEO1 Bias Register (Default Value: 0x10100000)
Offset: 0x0238

Register Name: PLL_VIDEO1_BIAS_REG

Bit

R/W

Default/Hex

Description

31:29

/

/

/

28:24

R/W

0x10

PLL_VCO_BIAS_CTRL.
PLL VCO Bias Control[4:0].

23:21

/

/

/

20:16

R/W

0x10

PLL_CUR_BIAS_CTRL.
PLL Current Bias Control[4:0].

15:3

/

/

/

2:0

R/W

0x0

PLL_DAMP_FACTOR_CTRL.
PLL Damping Factor Control[2:0].

3.3.5.65. PLL_GPU Bias Register (Default Value: 0x10100000)
Offset: 0x023C

Register Name: PLL_GPU_BIAS_REG

Bit

R/W

Default/Hex

Description

31:29

/

/

/

28:24

R/W

0x10

PLL_VCO_BIAS_CTRL.
PLL VCO Bias Control[4:0].

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23:21

/

/

/

20:16

R/W

0x10

PLL_CUR_BIAS_CTRL.
PLL Current Bias Control[4:0].

15:3

/

/

/

2:0

R/W

0x0

PLL_DAMP_FACTOR_CTRL.
PLL Damping Factor Control[2:0].

3.3.5.66. PLL_MIPI Bias Register (Default Value: 0XF8100400)
Offset: 0x0240

Register Name: PLL_MIPI_BIAS_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x1

VCO_RST.
VCO Reset In.

30:28

R/W

0x7

PLLVDD_LDO_OUT_CTRL.
PLLVDD LDO Output Control.
PLL_IN_POWER_SEL=1
PLL_IN_POWER_SEL=0
000:1.00v
000:1.20v
001:1.02v
001:1.225v
010:1.04v
010:1.25v
011:1.06v
011:1.275v
100: 1.08v
100:1.30v
101:1.10v
101:1.325v
110:1.12v
110:1.35v
111:1.14v.
111:1.375v
The PLL_IN_PWR_SEL is in the PLL_MIPI Tuning Register.

27:24

R/W

0x8

PLL_VCO_BIAS_CTRL.
PLL VCO Bias Control [3:0].

23:21

/

/

/

20:16

R/W

0x10

PLL_CUR_BIAS_CTRL.
PLL Current Bias Control[4:0].

15:11

/

/

/

10:8

R/W

0x4

PLL_LOCK_CTRL.
PLL Lock Time Control[2:0].

7:1

/

/

/

0

R/W

0x0

PLL_DAMP_FACT_CTRL.
PLL Damping Factor Control.

3.3.5.67. PLL_HSIC Bias Register (Default Value: 0x10100000)
Offset: 0x0244
Bit

R/W

Register Name: PLL_HSIC_BIAS_REG
Default/Hex

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Description

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31:29

/

/

/

28:24

R/W

0x10

PLL_VCO_BIAS.
PLL VCO Bias[4:0].

23:21

/

/

/

20:16

R/W

0x10

PLL_CUR_BIAS_CTRL.
PLL Current Bias Control[4:0].

15:3

/

/

/.

2:0

R/W

0x0

PLL_DAMP_FACTOR_CTRL.
PLL Damping Factor Control[2:0].

3.3.5.68. PLL_DE Bias Register (Default Value: 0x10100000)
Offset: 0x0248

Register Name: PLL_DE_BIAS_REG

Bit

R/W

Default/Hex

Description

31:29

/

/

/

28:24

R/W

0x10

PLL_VCO_BIAS_CTRL.
PLL VCO Bias Control[4:0].

23:21

/

/

/

20:16

R/W

0x10

PLL_CUR_BIAS_CTRL.
PLL Current Bias Control[4:0].

15:3

/

/

/

2:0

R/W

0x0

PLL_DAMP_FACTOR_CTRL.
PLL Damping Factor Control[2:0].

3.3.5.69. PLL_DDR1 Bias Register (Default Value: 0x10010000)
Offset: 0x024C

Register Name: PLL_DDR1_BIAS_REG

Bit

R/W

Default/Hex

Description

31:29

/

/

/

28:24

R/W

0x10

PLL_VCO_BIAS_CTRL.
PLL VCO Bias Control[4:0].

23:21

/

/

/

20:16

R/W

0x01

PLL_CUR_BIAS_CTRL.
PLL Current Bias Control[4:0].

15:0

/

/

/

3.3.5.70. PLL_CPUX Tuning Register (Default Value: 0x0A101000)
Offset: 0x0250

A64 User Manual(Revision 1.0)

Register Name: PLL_CPUX_TUN_REG

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Bit

R/W

Default/Hex

Description

31:28

/

/

/

27

R/W

0x1

PLL_BAND_WID_CTRL.
PLL Band Width Control.
0: Narrow
1: Wide

26

R/W

0x0

VCO_GAIN_CTRL_EN.
VCO Gain Control Enable.
0: Disable
1: Enable

25:23

R/W

0x4

VCO_GAIN_CTRL.
VCO Gain Control Bits[2:0].

22:16

R/W

0x10

PLL_INIT_FREQ_CTRL.
PLL Initial Frequency Control[6:0].

15

R/W

0x0

C_OD.
C-Reg-Od For Verify.

14:8

R/W

0x10

C_B_IN.
C-B-In[6:0] For Verify.

7

R/W

0x0

C_OD1.
C-Reg-Od1 For Verify.

6:0

R

0x0

C_B_OUT.
C-B-Out[6:0] For Verify.

3.3.5.71. PLL_DDR0 Tuning Register (Default Value: 0x14880000)
Offset: 0x0260

Register Name: PLL_DDR0_TUN_REG

Bit

R/W

Default/Hex

Description

31:29

/

/

/

28

R/W

0x1

VREG1_OUT_EN.
Vreg1 Out Enable.
0: Disable
1: Enable

27

/

/

/

26:24

R/W

0x4

PLL_LTIME_CTRL.
PLL Lock Time Control[2:0].

23

R/W

0x1

VCO_RST.
VCO Reset In.

22:16

R/W

0x08

PLL_INIT_FREQ_CTRL.
PLL Initial Frequency Control[6:0].

15

R/W

0x0

OD1.
Reg-Od1 For Verify.

14:8

R/W

0x0

B_IN.

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B-In[6:0] For Verify.
7

R/W

0x0

OD.
Reg-Od For Verify.

6:0

R

0x0

B_OUT.
B-Out[6:0] For Verify.

3.3.5.72. PLL_MIPI Tuning Register (Default Value: 0x8A002000)
Offset: 0x0270

Register Name: PLL_MIPI_TUN_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x1

PLL_INPUT_POWER_SEL.
0:2.5V
1:3.0V.

30

/

/

/

29:28

R/W

0x0

VREG_OUT_EN.
For Verify

27

R/W

0x1

PLL_BAND_WID_CTRL.
PLL Band Width Control.
0: Narrow
1: Wide.

26

R/W

0x0

VCO_GAIN_CTRL_EN.
VCO Gain Control Enable.
0: Disable
1: Enable.

25:23

R/W

0x4

VCO_GAIN_CTRL.
VCO Gain Control Bits[2:0].

22

/

/

/

21:16

R/W

0x0

CNT_INT.
For Verify[5:0].

15

R/W

0x0

C_OD.
C-Reg-Od For Verify

14

/

/

/

13:8

R/W

0x20

C_B_IN.
C-B-In[5:0] For Verify

7

R/W

0x0

C_OD1.
C-Reg-Od1 For Verify

6

/

/

/

5:0

R

A64 User Manual(Revision 1.0)

C_B_OUT.
C-B-Out[5:0] For Verify

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3.3.5.73. PLL_PERIPH1 Pattern Control Register (Default Value: 0x00000000)
Offset: 0x027C

Register Name: PLL_PERIPH1_PAT_CTRL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

SIG_DELT_PAT_EN.
Sigma-Delta Pattern Enable.

30:29

R/W

0x0

SPR_FREQ_MODE.
Spread Frequency Mode.
00: DC=0
01: DC=1
1X: Triangular.

28:20

R/W

0x0

WAVE_STEP.
Wave Step.

19

/

/

/

18:17

R/W

0x0

FREQ.
Frequency.
00: 31.5KHz
01: 32KHz
10: 32.5KHz
11: 33KHz.

16:0

R/W

0x0

WAVE_BOT.
Wave Bottom.

3.3.5.74. PLL_CPUX Pattern Control Register (Default Value: 0x00000000)
Offset: 0x0280

Register Name: PLL_CPUX_PAT_CTRL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

SIG_DELT_PAT_EN.
Sigma-delta Pattern Enable.

30:29

R/W

0x0

SPR_FREQ_MODE.
Spread Frequency Mode.
00: DC=0
01: DC=1
1X: Triangular

28:20

R/W

0x0

WAVE_STEP.
Wave Step.

19

/

/

/

18:17

R/W

0x0

FREQ.
Frequency.
00: 31.5KHz
01: 32KHz
10: 32.5KHz

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11: 33KHz
16:0

R/W

0x0

WAVE_BOT.
Wave Bottom.

3.3.5.75. PLL_AUDIO Pattern Control Register(Default Value: 0x00000000)
Offset: 0x0284

Register Name: PLL_AUDIO_PAT_CTRL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

SIG_DELT_PAT_EN.
Sigma-delta Pattern Enable.

30:29

R/W

0x0

SPR_FREQ_MODE.
Spread Frequency Mode.
00: DC=0
01: DC=1
1X: Triangular

28:20

R/W

0x0

WAVE_STEP.
Wave Step.

19

/

/

/

18:17

R/W

0x0

FREQ.
Frequency.
00: 31.5KHz
01: 32KHz
10: 32.5KHz
11: 33KHz

16:0

R/W

0x0

WAVE_BOT.
Wave Bottom.

3.3.5.76. PLL_VIDEO0 Pattern Control Register (Default Value: 0x00000000)
Offset: 0x0288

Register Name: PLL_VIDEO0_PAT_CTRL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

SIG_DELT_PAT_EN.
Sigma-delta Pattern Enable.

30:29

R/W

0x0

SPR_FREQ_MODE.
Spread Frequency Mode.
00: DC=0
01: DC=1
1X: Triangular

28:20

R/W

0x0

WAVE_STEP.
Wave Step.

19

/

/

/

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18:17

R/W

0x0

FREQ.
Frequency.
00: 31.5KHz
01: 32KHz
10: 32.5KHz
11: 33KHz

16:0

R/W

0x0

WAVE_BOT.
Wave Bottom.

3.3.5.77. PLL_VE Pattern Control Register (Default Value: 0x00000000)
Offset: 0x028C

Register Name: PLL_VE_PAT_CTRL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

SIG_DELT_PAT_EN.
Sigma-delta Pattern Enable.

30:29

R/W

0x0

SPR_FREQ_MODE.
Spread Frequency Mode.
00: DC=0
01: DC=1
1X: Triangular

28:20

R/W

0x0

WAVE_STEP.
Wave Step.

19

/

/

/

18:17

R/W

0x0

FREQ.
Frequency.
00: 31.5KHz
01: 32KHz
10: 32.5KHz
11: 33KHz

16:0

R/W

0x0

WAVE_BOT.
Wave Bottom.

3.3.5.78. PLL_DDR0 Pattern Control Register (Default Value: 0x00000000)
Offset: 0x0290

Register Name: PLL_DDR0_PAT_CTRL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

SIG_DELT_PAT_EN.
Sigma-delta Pattern Enable.

30:29

R/W

0x0

SPR_FREQ_MODE.
Spread Frequency Mode.
00: DC=0

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System
01: DC=1
1X: Triangular
28:20

R/W

0x0

WAVE_STEP.
Wave step.

19

/

/

/

18:17

R/W

0x0

FREQ.
Frequency.
00: 31.5KHz
01: 32KHz
10: 32.5KHz
11: 33KHz

16:0

R/W

0x0

WAVE_BOT.
Wave Bottom.

3.3.5.79. PLL_VIDEO1 Pattern Control Register (Default Value: 0x00000000)
Offset: 0x0298

Register Name: PLL_VIDEO1_PAT_CTRL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

SIG_DELT_PAT_EN.
Sigma-Delta Pattern Enable.

30:29

R/W

0x0

SPR_FREQ_MODE.
Spread Frequency Mode.
00: DC=0
01: DC=1
1X: Triangular.

28:20

R/W

0x0

WAVE_STEP.
Wave Step.

19

/

/

/

18:17

R/W

0x0

FREQ.
Frequency.
00: 31.5KHz
01: 32KHz
10: 32.5KHz
11: 33KHz.

16:0

R/W

0x0

WAVE_BOT.
Wave Bottom.

3.3.5.80. PLL_GPU Pattern Control Register (Default Value: 0x00000000)
Offset: 0x029C
Bit

R/W

Register Name: PLL_GPU_PAT_CTRL_REG
Default/Hex

A64 User Manual(Revision 1.0)

Description

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Page 134

System
31

R/W

0x0

SIG_DELT_PAT_EN.
Sigma-Delta Pattern Enable.

30:29

R/W

0x0

SPR_FREQ_MODE.
Spread Frequency Mode.
00: DC=0
01: DC=1
1X: Triangular

28:20

R/W

0x0

WAVE_STEP.
Wave Step.

19

/

/

/

18:17

R/W

0x0

FREQ.
Frequency.
00: 31.5KHz
01: 32KHz
10: 32.5KHz
11: 33KHz

16:0

R/W

0x0

WAVE_BOT.
Wave Bottom.

3.3.5.81. PLL_MIPI Pattern Control Register (Default Value: 0x00000000)
Offset: 0x02A0

Register Name: PLL_MIPI_PAT_CTRL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

SIG_DELT_PAT_EN.
Sigma-Delta Pattern Enable.

31

R/W

0x0

SIG_DELT_PAT_EN.
Sigma-Delta Pattern Enable.

30:29

R/W

0x0

SPR_FREQ_MODE.
Spread Frequency Mode.
00: DC=0
01: DC=1
1X: Triangular.

28:20

R/W

0x0

WAVE_STEP.
Wave Step.

19

/

/

/

18:17

R/W

0x0

FREQ.
Frequency.
00: 31.5KHz
01: 32KHz
10: 32.5KHz
11: 33KHz.

16:0

R/W

0x0

WAVE_BOT.

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3.3.5.82. PLL_HSIC Pattern Control Register (Default Value: 0x00000000)
Offset: 0x02A4

Register Name: PLL_HSIC_PAT_CTRL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

SIG_DELT_PAT_EN.
Sigma-Delta Pattern Enable.

30:29

R/W

0x0

SPR_FREQ_MODE.
Spread Frequency Mode.
00: DC=0
01: DC=1
1X: Triangular

28:20

R/W

0x0

WAVE_STEP.
Wave Step.

19

/

/

/

18:17

R/W

0x0

FREQ.
Frequency.
00: 31.5KHz
01: 32KHz
10: 32.5KHz
11: 33KHz

16:0

R/W

0x0

WAVE_BOT.
Wave Bottom.

3.3.5.83. PLL_DE Pattern Control Register (Default Value: 0x00000000)
Offset: 0x02A8

Register Name: PLL_DE_PAT_CTRL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

SIG_DELT_PAT_EN.
Sigma-Delta Pattern Enable.

30:29

R/W

0x0

SPR_FREQ_MODE.
Spread Frequency Mode.
00: DC=0
01: DC=1
1X: Triangular

28:20

R/W

0x0

WAVE_STEP.
Wave Step.

19

/

/

/

18:17

R/W

0x0

FREQ.
Frequency.

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00: 31.5KHz
01: 32KHz
10: 32.5KHz
11: 33KHz
16:0

R/W

0x0

WAVE_BOT.
Wave Bottom.

3.3.5.84. PLL_DDR1 Pattern Control Register0 (Default Value: 0x00000000)
Offset: 0x02AC

Register Name: PLL_DDR1_PAT_CTRL_REG0

Bit

R/W

Default/Hex

Description

31

R/W

0x0

SIG_DELT_PAT_EN.
Sigma-Delta Pattern Enable.

30:29

R/W

0x0

SPR_FREQ_MODE.
Spread Frequency Mode.
00: DC=0
01: DC=1
10: /11: Triangular.

28:20

R/W

0x0

WAVE_STEP.
Wave Step.

19

/

/

/

18:17

R/W

0x0

FREQ.
Frequency.
00: 31.5KHz
01: 32KHz
10: 32.5KHz
11: 33KHz.

16:0

R/W

0x0

WAVE_BOT.
Wave Bottom.

3.3.5.85. PLL_DDR1 Pattern Control Register1 (Default Value: 0x00000000)
Offset: 0x02B0

Register Name: PLL_DDR1_PAT_CTRL_REG1

Bit

R/W

Default/Hex

Description

30:25

/

/

/

24

R/W

0x0

DITHER_EN.

23:21

/

/

/

20

R/W

0x0

FRAC_EN.

19:17

/

/

/

16:0

R/W

0x0

FRAC_IN.

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3.3.5.86. Bus Software Reset Register 0 (Default Value: 0x00000000)
Offset: 0x02C0

Register Name: BUS_SOFT_RST_REG0

Bit

R/W

Default/Hex

Description

31:30

/

/

/

29

R/W

0x0

USB-OHCI0_RST.
USB-OHCI0 Reset Control
0: Assert
1: De-assert

28

R/W

0x0

USB-OTG-OHCI_RST.
USB-OTG-OHCI Reset Control
0: Assert
1: De-assert

27:26

/

/

/

25

R/W

0x0

USB-EHCI0_RST.
USB-EHCI0 Reset Control
0: Assert
1: De-assert.

24

R/W

0x0

USB-OTG-EHCI_RST.
USB-OTG-EHCI Reset Control
0: Assert
1: De-assert

23

R/W

0x0

USB-OTG-Device_RST.
USB-OTG-Device Reset Control
0: Assert
1: De-assert

22

/

/

/

21

R/W

0x0

SPI1_RST.
SPI1 Reset.
0: Assert
1: De-assert

20

R/W

0x0

SPI0_RST.
SPI0 Reset.
0: Assert
1: De-assert

19

R/W

0x0

HSTMR_RST.
HSTMR Reset.
0: Assert
1: De-assert

18

R/W

0x0

TS_RST.
TS Reset.
0: Assert

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1: De-assert
17

R/W

0x0

EMAC_RST.
EMAC Reset.
0: Assert
1: De-assert

16:15

/

/

/

14

R/W

0x0

SDRAM_RST.
SDRAM AHB Reset.
0: Assert
1: De-assert

13

R/W

0x0

NAND_RST.
NAND Reset.
0: Assert
1: De-assert

12:11

/

/

/

10

R/W

0x0

SMHC2_RST.
SMHC2 Reset.
0: Assert
1: De-assert.

9

R/W

0x0

SMHC1_RST.
SMHC1 Reset.
0: Assert
1: De-assert.

8

R/W

0x0

SMHC0_RST.
SMHC0 Reset.
0: Assert
1: De-assert.

7

/

/

/

6

R/W

0x0

DMA_RST.
DMA Reset.
0: Assert
1: De-assert

5

R/W

0x0

CE_RST.
CE Reset.
0: Assert
1: De-assert

4:2

/

/

/

1

R/W

0x0

MIPI_DSI_RST.
MIPI DSI Reset.
0: Assert
1: De-assert.

0

/

/

/

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3.3.5.87. Bus Software Reset Register 1 (Default Value: 0x00000000)
Offset: 0x02C4

Register Name: BUS_SOFT_RST_REG1

Bit

R/W

Default/Hex

Description

31

R/W

0x0

DBGSYS_RST.
DBGSYS Reset.
0: Assert
1: De-assert

30:23

/

/

/

22

R/W

0x0

SPINLOCK_RST.
SPINLOCK Reset.
0: Assert
1: De-assert.

21

R/W

0x0

MSGBOX_RST.
MSGBOX Reset.
0: Assert
1: De-assert.

20

R/W

0x0

GPU_RST.
GPU Reset.
0: Assert
1: De-assert.

19:13

/

/

/

12

R/W

0x0

DE_RST.
DE Reset.
0: Assert
1: De-assert.

11

R/W

0x0

HDMI1_RST.
HDMI1 Reset.
0: Assert
1: De-assert.

10

R/W

0x0

HDMI0_RST.
HDMI0 Reset.
0: Assert
1: De-assert.

9

/

/

/

8

R/W

0x0

CSI_RST.
CSI Reset.
0: Assert
1: De-assert.

7:6

/

/

/

5

R/W

0x0

DEINTERLACE_RST.
DEINTERLACE Reset.
0: Assert

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1:De-assert
4

R/W

0x0

TCON1_RST.
TCON1 Reset.
0: Assert
1: De-assert.

3

R/W

0x0

TCON0_RST.
TCON0 Reset.
0: Assert
1: De-assert.

2:1

/

/

/

0

R/W

0x0

VE_RST.
VE Reset.
0: Assert
1: De-assert.

3.3.5.88. Bus Software Reset Register 2 (Default Value: 0x00000000)
Offset: 0x02C8

Register Name: BUS_SOFT_RST_REG2

Bit

R/W

Default/Hex

Description

31:1

/

/

/

0

R/W

0x0

LVDS_RST.
LVDS Reset.
0: Assert
1: De-assert.

3.3.5.89. Bus Software Reset Register 3 (Default Value: 0x00000000)
Offset: 0x02D0

Register Name: BUS_SOFT_RST_REG3

Bit

R/W

Default/Hex

Description

31:15

/

/

/

14

R/W

0x0

I2S/PCM 2_RST.
I2S/PCM 2 Reset.
0: Assert
1: De-assert.

13

R/W

0x0

I2S/PCM 1_RST.
I2S/PCM 1 Reset.
0: Assert
1: De-assert.

12

R/W

0x0

I2S/PCM 0_RST.
I2S/PCM 0 Reset.
0: Assert

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1: De-assert.
11:9

/

/

/

8

R/W

0x0

THS_RST.
THS Reset.
0: Assert
1: De-assert

7:2

/

/

/

1

R/W

0x0

OWA_RST.
OWA Reset.
0: Assert
1: De-assert

0

R/W

0x0

AC_RST.
AC Reset.
0: Assert
1: De-assert

3.3.5.90. Bus Software Reset Register 4 (Default Value: 0x00000000)
Offset: 0x02D8

Register Name: BUS_SOFT_RST_REG4

Bit

R/W

Default/Hex

Description

31:21

/

/

/

20

R/W

0x0

UART4_RST.
UART4 Reset.
0: Assert
1: De-assert.

19

R/W

0x0

UART3_RST.
UART3 Reset.
0: Assert
1: De-assert.

18

R/W

0x0

UART2_RST.
UART2 Reset.
0: Assert
1: De-assert.

17

R/W

0x0

UART1_RST.
UART1 Reset.
0: Assert
1: De-assert.

16

R/W

0x0

UART0_RST.
UART0 Reset.
0: Assert
1: De-assert.

15:6

/

/

/

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System
5

R/W

0x0

SCR_RST.
SCR Reset.
0: Assert
1: De-assert

4:3

/

/

/

2

R/W

0x0

TWI2_RST.
TWI2 Reset.
0: Assert
1: De-assert.

1

R/W

0x0

TWI1_RST.
TWI1 Reset.
0: Assert
1: De-assert.

0

R/W

0x0

TWI0_RST.
TWI0 Reset.
0: Assert
1: De-assert.

3.3.5.91. CCU Security Switch Register (Default Value: 0x00000000)
Offset: 0x02F0

Register Name: CCU_SEC_SWITCH_REG

Bit

R/W

Default/Hex

Description

31:3

/

/

/

2

R/W

0x0

MBUS_SEC
MBUS clock register security
0:Secure
1:Non-secure
Including MBUS Reset Register and MBUS Clock Register

1

R/W

0x0

BUS_SECBus relevant registers’ security
0:Secure
1:Non-secure
Including AXI/AHB/APB relevant registers,such as CPUX/AXI Configuration
Register,AHB1/APB1 Configuration Register,APB2 Configuration Register,
AHB2 Configuration Register.

0

R/W

0x0

PLL_SEC
PLL relevant registers’ security.
0:Secure
1:Non-secure
Including PLL_CPUX Control Register, PLL_AUDIO Control Register,
PLL_VIDEO0 Control Register, PLL_VIDEO1 Control Register, PLL_VE
Control Register, PLL_DDR0 Control Register,PLL_DDR1 Control Register,
PLL_PERIPH0 Control Register, PLL_PERIPH1 Control Register,PLL_GPU

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SystemControl Register, PLL_MIPI Control Register, PLL_HSIC Control Register,
PLL_DE Control Register and offset from 0x200 to 0x2B0 relevant
registers.

3.3.5.92. PS Control Register (Default Value: 0x00000000)
Offset: 0x0300

Register Name: PS_CTRL_REG

Bit

R/W

Default/Hex

Description

31:10

/

/

/

9:8

R/W

0x0

DEC_SEL
Device Select

7

R/W

0x0

DET_FIN.
Detect Finish.
0: Unfinished
1: FinishedSet 1 to this bit will clear it.

6

R/W

0x0

DLY_SEL.
Delay Select0: 1 Cycle
1: 2 Cycles

5:4

R/W

0x0

OSC_SELOSC Select.
00: IDLE
01: SVT
10: LVT
11: ULVT

3:1

R/W

0x0

TIME_DET.
Time detect.
000: 0.5/4 us
001: 0.5/2 us
002: 0.5/1 us
003: 0.5*2us.................
111:0.5*2^5us

0

R/W

0x0

MOD_EN.
Module enable.
0: Disable
1: Enable

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3.3.5.93. PS Counter Register (Default Value: 0x00000000)
Offset: 0x0304

Register Name: PS_CNT_REG

Bit

R/W

Default/Hex

Description

31:16

/

/

/

15:0

R/W

0x0

PS_CNT.
PS Counter.

3.3.5.94. PLL Lock Control Register (Default Value: 0x00000000)
Offset: 0x0320

Register Name: PLL_LOCK_CTRL_REG

Bit

R/W

Default/Hex

Description

31:29

/

/

/

28

R/W

0x0

MODE_SEL
Mode Select0: Old Mode
1: New Mode

27:25

/

/

/

24

R/W

0x0

DBG_EN
Debug Enable
0: Disable
1: Enable

23:20

R/W

0x0

DBG_SEL
Debug Select0000: PLL_CPUX
0001: PLL_AUDIO
0010: PLL_VIDEO00011: PLL_VE
0100: PLL_DDR00101: PLL_PERIPH00110: PLL_VIDEO1
0111: PLL_GPU
1000: PLL_MIPI
1001: PLL_HSIC
1010: PLL_DE
1011: PLL_DDR1
1100: PLL_PERIPH1
Others: /

19

/

/

/

18:17

R/W

0x0

UNLOCK_LEVEL
Unlock Level
00: 21-29 Clock Cycles

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01: 22-28 Clock Cycles
1X: 20-30 Clock Cycles
16

R/W

0x0

LOCK_LEVEL
Lock Level
0: 24-26 Clock Cycles
1: 23-27 Clock Cycles

15:13

/

/

/

12:0

R/W

0x0

LOCK_EN
Lock Enable
Bit12: PLL_PERIPH1
Bit11: PLL_DDR1
Bit10: PLL_DE
Bit9: PLL_HSIC
Bit8: PLL_MIPI
Bit7: PLL_GPU
Bit6: PLL_VIDEO1
Bit5: PLL_PERIPH0
Bit4: PLL_DDR0
Bit3: PLL_VE
Bit2: PLL_VIDEO0
Bit1: PLL_AUDIO
Bit0: PLL_CPUX

3.3.6. Programming Guidelines
3.3.6.1. PLL
1)
2)
3)
4)

In practical application, other PLLs doesn’t support dynamic frequency scaling except for PLL_CPUX and
PLL_DDR1;
After the PLL_DDR0 frequency changes, the 20-bit of PLL_DDR0 Control Register should be written 1 tomake it valid;
After the PLL_DDR1 frequency changes, the 30-bit of PLL_DDR1 Control Register should be written 1 tomake it valid;
When configured PLL_MIPI,LDO1 and LDO2 must be enable at first,and delay 100us ,configure thedivision factor, then enable and delay 500us, PLL_MIPI can be output to use.

3.3.6.2. BUS
1) When setting the Bus Clock , you should set the division factor first, and after the division factor
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Systemavailable ,switch the clock source. The switching of clock source will be available after at least three clock
cycles;2) The Bus Clock should not be dynamically changed in most applications.

3.3.6.3. Clock Switch
Make sure that the clock source output is valid before the clock source switch, and then set a proper divide
ratio; after the division factor becomes valid, switch the clock source.

3.3.6.4. Gating and reset
Make sure that the reset signal has been released before the release of module clock gating;

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3.4. CPU Configuration
3.4.1. Overview
CPUCFG module is used to configure related CPU parameters,including power on,reset,cache,debug etc,andcheck the status of CPU. It will be used when you want to disable/enable the CPU, cluster switch, CPU statuscheck, and debug, etc.
It features:•••

Capable of CPU reset, including core reset, debug circuit rest, etc
Capable of other CPU-related control, including interface control, CP15 control, and power control, etc
Capable of checking CPU status, including idle status, SMP status, and interrupt status, etc

3.4.2. Block Diagram

Figure 3-4. CPUCFG Block Diagram
The figure above lists the power domain of CPU reset. All power switch of CPU core are default to be closed.
Since each CPU core and its appended circuits have the same power domain,the processor and related L1
cache,neon and vfp should be taken as a whole when it comes to the CPU core enable/disable.

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3.4.3. Functionalities Description
3.4.3.1. Signal Description
For the detail of CPU Signal, please refer to ARM Cortex-A53 TRM.

3.4.3.2. L2 Idle Mode
When the L2 of Cluster needs to enter WFI mode, firstly make sure the CPU0/1/2/3 of Cluster enter WFI mode,
which can be checked through Cluster CPU Status Register, and then pull the ACINACTM of Cluster high by
writing related register bit to 1, and then check whether L2 enters idle status by checking whether the
STANDBYWFIL2 is high. Remember to set the ACINACTM to low when exiting the L2 idle mode.

3.4.3.3. CPU Reset System
The CPU reset includes core reset, power-on reset and H_Reset. And their scopes rank: core reset < power-on
Reset < H_Reset.For the detail description,please refer to 3.4.5 Register Description.

3.4.3.4. Operation Principle
The CPU-related operation needs proper configuration of CPUCFG related register, as well as related system
control resource including BUS, clock ,reset and power control.

3.4.4. Register List
Module Name

Base Address

CPUCFG

0x01700C00

Register Name

OffsetDescription

C_CTRL_REG0

0x0000Cluster Control Register0

C_CTRL_REG1

0x0004Cluster Control Register1

CACHE_CFG_REG0

0x0008

Cache parameters configuration register0

CACHE_CFG_REG1

0x000C

Cache parameters configuration register1

GENER_CTRL_REG0

0x0028General Control Register0

C_CPU_STATUS

0x0030Cluster CPU Status Register

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L2_ STATUS_REG

0x003C

L2 Status Register

C_RST_CTRL

0x0080Cluster Reset Control Register

RVBARADDR0_L

0x00A0Reset Vector Base Address Register0_L

RVBARADDR0_H

0x00A4

Reset Vector Base Address Register0_H

RVBARADDR1_L

0x00A8Reset Vector Base Address Register1_L

RVBARADDR1_H

0x00AC

Reset Vector Base Address Register1_H

RVBARADDR2_L

0x00B0Reset Vector Base Address Register2_L

RVBARADDR2_H

0x00B4

Reset Vector Base Address Register2_H

RVBARADDR3_L

0x00B8Reset Vector Base Address Register3_L

RVBARADDR3_H

0x00BC

Reset Vector Base Address Register3_H

3.4.5. Register Description
3.4.5.1. Cluster Control Register0 (Default Value: 0x80000000)
Offset: 0x00

Register Name: C_CTRL_REG0

Bit

R/W

Default/Hex

Description

31

R/W

0x1

SYSBAR_DISABLE.
Disable broadcasting of barriers onto system bus:
0: Barriers are broadcast onto system bus,this requires an AMBA4interconnect.
1: Barriers are not broadcast onto the system bus.This is compatible withan AXI3 interconnect.

30

R/W

0x0

BROADCAST_INNER.
Enable broadcasting of Inner Shareable transactions:
0: Inner shareable transactions are not broadcasted externally.
1: Inner shareable transactions are broadcasted externally.

29

R/W

0x0

BROADCAST_OUTER.
Enable broadcasting of outer shareable transactions:0: Outer Shareable transactions are not broadcasted externally.
1: Outer Shareable transactions are broadcasted externally.

28

R/W

0x0

BROADCAST_CACHE_MAINT
Enable broadcasting of cache maintenance operations to downstream
caches:0: Cache maintenance operations are not broadcasted to downstream
caches.
1: Cache maintenance operations are broadcasted to downstream
caches.

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27:24

R/W

0x0

AA64nAA32
Register width state.Determines which execution state the processor
boots into after a cold reset.
0: AArch32
1: AArch64

23:10

/

/

/

11:8

R/W

0x0

CP15S_DISABLE.
Disable write access to some secure CP15 register.

7:5

/

/

/

4

R/W

0x0

L2_RST_DISABLE.
Disable automatic L2 cache invalidate at reset:
0: L2 cache is reset by hardware.
1: L2 cache is not reset by hardware.

3:0

/

/

/

3.4.5.2. Cluster Control Register1 (Default Value: 0x00000000)
Offset: 0x04

Register Name: C_CTRL_REG1

Bit

R/W

Default/Hex

Description

31:1

/

/

/

0

R/W

0x0

ACINACTM.
Snoop interface is inactive and no longer accepting requests.
0: snoop interface is active
1: Snoop interface is inactive

3.4.5.3. Cache Parameter Control Register0 (Default Value: 0x22222222)
Offset: 0x08

Register Name: CACHE_CFG_REG0

Bit

R/W

Default/Hex

Description

31

/

/

/

30:28

R/W

0x2

L1SDT_DELAY

27

/

/

/

26:24

R/W

0x2

L1TLB_DELAY

23

/

/

/

22:20

R/W

0x2

BTAC_DELAY

19

/

/

/

18:16

R/W

0x2

L1DY_DELAY

15

/

/

/

14:12

R/W

0x2

L1DT_DELAY

11

/

/

/

10:8

R/W

0x2

L1DD_DELAY

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7

/

/

/

6:4

R/W

0x2

L1IT_DELAY

3

/

/

/

2:0

R/W

0x2

L1ID_DELAY

3.4.5.4. Cache Parameter Control Register1 (Default Value: 0x02022020)
Offset: 0x0C

Register Name: CACHE_CFG_REG1

Bit

R/W

Default/Hex

Description

31:26

/

/

/

25:24

R/W

0x2

EMAW

23:19

/

/

/

18:16

R/W

0x2

EMA

15

/

/

/

14:12

R/W

0x2

L2V_DELAY

11:8

/

/

/

7

/

/

/

6:4

R/W

0x2

L2T_DELAY

3:0

/

/

/

3.4.5.5. General Control Register0 (Default Value: 0x00000010)
Offset: 0x28

Register Name: GENER_CTRL_REG0

Bit

R/W

Default/Hex

Description

31:25

/

/

/

24

R/W

0x0

EVENTI
Event input for processor wake-up from WFE state.This bit must remain
HIGH for at least one clock cycle to be visible by the cores.

23:20

R/W

0x0

EXM_CLR[3:0]

19:17

/

/

/

16

R/W

0x0

CLREXMONREQ
Clearing of the external global exclusive monitor request.When this bit isasserted, it acts as a WFE wake-up event to all the cores in the MPCore
device.

15:12

R/W

0x0

CRYPTODISABLE
Disable the Cryptography Extensions.

11:9

/

/

/

8

R/W

0x0

L2FLUSHREQ
L2 hardware flush request.

7:5

/

/

/

4

R/W

0x1

GICCDISABLE.

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SystemGlobally disables the CPU interface logic and routes the "External" signals
directly to the processor:
0: Enable the GIC CPU interface logic.
1: Disable the GIC CPU interface logic.
3:0

/

/

/

3.4.5.6. Cluster CPU Status Register (Default Value: 0x000E0000)
Offset: 0x30

Register Name: C_CPU_STATUS

Bit

R/W

Default/Hex

Description

31:28

/

/

/

27:24

R

0x0

SMP
Indicates whether a core is taking part in coherency.
0: Disable
1: Enable

23:20

/

/

/

19:16

R

0xE

STANDBYWFI.
Indicates if a core is in WFI standby mode:
0: Processor not in WFI standby mode.
1: Processor in WFI standby mode

15:12

/

/

/

11:8

R

0x0

STANDBYWFE.
Indicates if a core is in the WFE standby mode:
0: Processor not in WFE standby mode
1: Processor in WFE standby mode

7:1

/

/

/

0

R

0x0

STANDBYWFIL2.
Indicates if the Cluster L2 memory system is in WFI standby mode.
0:active
1:idle3.4.5.7. L2 Status Register(Default Value: 0x00000000)
Offset: 0x3C

Register Name: L2_STATUS_REG

Bit

R/W

Default/Hex

Description

31:11

/

/

/

10

R

0x0

L2FLUSHDONE
L2 hardware flush complete

9

R

0x0

EVENTO
Event output.This bit is asserted HIGH for 3 clock cycles when any core in
the cluster executes an SEV instruction.

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System
8R

0x0

CLREXMONACK
Clearing of the external global exclusive monitor acknowledge.

7:0

/

/

/

3.4.5.8. Cluster Reset Control Register (Default Value: 0x11101101)
Offset: 0x80

Register Name: C_RST_CTRL

Bit

R/W

Default/Hex

Description

31:29

/

/

/

28

R/W

0x1

DDR_RST
AXI2MBUS logic circuit Reset.
0: assert
1: de-assert

27:25

/

/

/

24

R/W

0x1

SOC_DBG_RST.
Cluster SOC Debug P_Reset. Clear this bit will reset the SOC Debug Bus
Logic and it will auto change to 1 after 64 p_cycles.
0: assert
1: de-assert.

23:21

R/W

0x0

20

R/W

0x1

MBIST_RSTCPUBIST Reset. The reset signal for test.
0: assert
1: de-assert

19:16

R/W

0x0

/

15:13

/

/

/

12

R/W

0x1

HRESET.
Cluster H_Reset. Reset all the Cluster Logic and Cluster Interface Logic.
0: assert
1: de-assert.

11:9

/

/

/

8

R/W

0x1

L2_RST.
Cluster L2 Cache Reset
0: assert
1: de-assert.

7:4

/

/

/

3:0

R/W

0x1

CORE_RESET.
Control a core reset assert.
0: assert
1: de-assert.

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3.4.5.9. Reset Vector Base Address Register0_L (Default Value: 0x00000000)
Offset: 0xA0

Register Name: RVBARADDR0_L

Bit

R/W

Default/Hex

Description

31:2

R/W

0x0

RVBARDDR[31:2]
Reset Vector Base Address[39:2] for executing in 64-bit state (AArch64)of
CPU0.

1:0

/

/

/

3.4.5.10. Reset Vector Base Address Register0_H (Default Value: 0x00000000)
Offset: 0xA4

Register Name: RVBARADDR0_H

Bit

R/W

Default/Hex

Description

31:8

/

/

/

7:0

R/W

0x0

RVBARDDR[39:32]
Reset Vector Base Address[39:2]for executing in 64-bit state (AArch64) of
CPU0.

3.4.5.11. Reset Vector Base Address Register1_L (Default Value: 0x00000000)
Offset: 0xA8

Register Name: RVBARADDR1_L

Bit

R/W

Default/Hex

Description

31:2

R/W

0x0

RVBARDDR[31:2]
Reset Vector Base Address[39:2] for executing in 64-bit state (AArch64)of
CPU1.

1:0

/

/

/

3.4.5.12. Reset Vector Base Address Register1_H (Default Value: 0x00000000)
Offset: 0xAC

Register Name: RVBARADDR1_H

Bit

R/W

Default/Hex

Description

31:8

/

/

/

7:0

R/W

0x0

RVBARDDR[39:32]
Reset Vector Base Address[39:2]for executing in 64-bit state (AArch64) of
CPU1.

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System
3.4.5.13. Reset Vector Base Address Register2_L (Default Value: 0x00000000)
Offset: 0xB0

Register Name: RVBARADDR2_L

Bit

R/W

Default/Hex

Description

31:2

R/W

0x0

RVBARDDR[31:2]
Reset Vector Base Address[39:2] for executing in 64-bit state (AArch64)of
CPU2.

1:0

/

/

/

3.4.5.14. Reset Vector Base Address Register2_H (Default Value: 0x00000000)
Offset: 0xB4

Register Name: RVBARADDR2_H

Bit

R/W

Default/Hex

Description

31:8

/

/

/

7:0

R/W

0x0

RVBARDDR[39:32]
Reset Vector Base Address[39:2]for executing in 64-bit state (AArch64) of
CPU2.

3.4.5.15. Reset Vector Base Address Register3_L (Default Value: 0x00000000)
Offset: 0xB8

Register Name: RVBARADDR3_L

Bit

R/W

Default/Hex

Description

31:2

R/W

0x0

RVBARDDR[31:2]
Reset Vector Base Address[39:2] for executing in 64-bit state (AArch64)of
CPU3.

1:0

/

/

/

3.4.5.16. Reset Vector Base Address Register3_H (Default Value: 0x00000000)
Offset: 0xBC

Register Name: RVBARADDR3_H

Bit

R/W

Default/Hex

Description

31:8

/

/

/

7:0

R/W

0x0

RVBARDDR[39:32]
Reset Vector Base Address[39:2]for executing in 64-bit state (AArch64) ofCPU3.

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System

3.5. System Control
3.5.1. Overview
Area

Size(Bytes)

A1

32K

A2

64K

C

172K

CPUX I-Cache

32K (X=0,1,2,3)

CPUX D-Cache

32K (X=0,1,2,3)

CPU L2 Cache

512K

Total

1036K

3.5.2. System Control Register List
Module Name

Base Address

System Control

0x01C00000

Register Name

OffsetDescription

VER_REG

0x24

Version Register

EMAC_CLK_REG

0x30

EMAC Clock Register

3.5.3. System Control Register Description
3.5.3.1. Version Register
Offset:0x24

Register Name: VER_REG

Bit

R/W

Default/Hex

Description

31:9

/

/

/

8

R

x

UBOOT_SEL_PAD_STA.
U_boot Select Pin Status.
0: U_Boot;
1: Normal Boot.

7:0

R

0x0

VER_BITS.
This read-only bit field always reads back the mask revision level of thechip.

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System
3.5.3.2. EMAC Clock Register (Default Value: 0x00000000)
Offset:0x30

Register Name: EMAC_CLK_REG

Bit

R/W

Default/Hex

Description

31:14

/

/

/

13

R/W

0x0

RMII_EN
0 : Disable RMII Module
1 : Enable RMII Module
When this bit assert, MII or RGMII interface is disabled( This means bit13
is prior to bit2)

12:10

R/W

0x0

ETXDC.
Configure EMAC Transmit Clock Delay Chain.

9:5

R/W

0x0

ERXDC.
Configure EMAC Receive Clock Delay Chain.

4

R/W

0x0

ERXIE
Enable EMAC Receive Clock Invertor.
0: Disable
1: Enable

3

R/W

0x0

ETXIE
Enable EMAC Transmit Clock Invertor.
0: Disable
1: Enable

2

R/W

0x0

EPIT
EMAC PHY Interface Type
0: MII
1: RGMII

1:0

R/W

0x0

ETCS.
EMAC Transmit Clock Source
00: Transmit clock source for MII
01: External transmit clock source for GMII and RGMII
10: Internal transmit clock source for GMII and RGMII
11: Reserved

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System

3.6. Timer
3.6.1. Overview
Timer 0/1 can take their inputs from 32K or OSC24M. They provide the operating system’s scheduler interrupt.
It is designed to offer maximum accuracy and efficient management, even for systems with long or short
response time. They provide 32-bit programmable overflow counter and work in auto-reload mode or
no-reload mode. When the current value in Timer 0 Current Value Register or Timer 1 Current Value Register
is counting down to zero, the timer will generate interrupt if set interrupt enable bit.
The watchdog is used to resume the controller operation when it had been disturbed by malfunctions such as
noise and system errors. It features a down counter that allows a watchdog period of up to 16 seconds (512000
cycles). It can generate a general reset or interrupt request.
Audio-Video-Sync(AVS) counter is used to synchronize video and audio in the player.
The timer module includes the following features:

2 Timers for system scheduler counting using 24MHz or 32KHz clock
Each Timer could general individual interrupt
1 Watchdog for resetting whole system or interrupt
2 AVS counters used for synchronize video and audio in the player

3.6.2. Block Diagram
Timer counter' clock input comes from one of the two clock sources that could be pre-scaled up to 128 division.
In single mode, when current value is counted down to 0, enable bit would be cleared automatically and Timerstops working. But in continuous mode, Interval Value will be auto-reloaded into Timer 0 Current Value
Register/Timer 1 Current Value Register and then counter counts from the new interval value again whencurrent value is counted down to 0. Every time current value is counted down to 0, a pending will be generated.
Pending could be sent to GIC or R_INTC only if IRQ enable bit is set.
Generally watchdog could not count down to 0 because it would be restart inside Interval Value. Otherwise themalfunction makes the watchdog counts down to 0 and a pending will be generated, which causes a
reset(Watchdog Configuration Register is configured for whole system) or an interrupt(Watchdog
Configuration Register is configured for only interrupt).
AVS has two counters which are both up-counted. The counter’ clock source comes from 24MHz/Divisor_N
and Divisor_N is set in AVS Counter Divisor Register. AVS counter could be changed to pause or enable at any
time,so are the Interval Value set in AVS Counter 0 Register or AVS Counter 1 Register and Divisor Value set in
AVS Counter Divisor Register. When you enable the AVS counter,it counts up from Interval Value until you
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Systempause it. It doesn't general any pending.

/1/2

IRQ EN/4/8Timer 024M

Single
yes

/16
32K

Interval Value

EnableWhole System

EnableIV=0?

Pending

IRQ

Pending

Reset

/32
/64

Timer 1

Continuous/128

16k cycles
32k cycles

yes

Reset

64k cycles

Time
out?

96k cycles
24M/750128k cycles

Restart

Watchdog

160k cycles
192k cycles
others cycles

Interrupt

Enable

Time
out?

yes

Pending

IRQ

RestartFigure 3-5. Timer Block Diagram

3.6.3. Operation Principle
3.6.3.1. Timer reload and enable bit
Generally the operation of setting both reload bit and enable bit and writing them into Timer 0 Control
Register/Timer 1 Control Register moreover could cause a risk. It had better to enable Timer after Interval
Value has been loaded into Timer 0 Current Value Register/Timer 1 Current Value Register. Only in timer
pause time, when you hope that counter starts working from a new interval value, reload bit and enable bit
should be set 1 and wrote into TMR0_CTRL_REG/ TMR1_CTRL_REG at the same time.

3.6.3.2. Timing requirement for Timer command
For reload and enable operation of Timer, it is necessary to wait some cycles between the same continuous
operations. It indicates that from pause state to start or from start state to pause it has to wait for 2 cycles atlease. And to reload operation, it could not be implemented immediately again until the reload bit had beencleared automatically of the last operation.

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System

3.6.3.3. Watchdog restart
Watchdog restart function should be enable inside Interval Value. Writing Watchdog Restart to 1 andWatchdog Key Field to 0xA57 at the same time make a restart, but writing Watchdog Key Field to other values
is ignored.

3.6.4. Timer Register List
Module Name

Base Address

TIMER

0x01C20C00

Register Name

OffsetDescription

TMR_IRQ_EN_REG

0x0

Timer IRQ Enable Register

TMR_IRQ_STA_REG

0x4

Timer Status Register

TMR0_CTRL_REG

0x10

Timer 0 Control Register

TMR0_INTV_VALUE_REG

0x14

Timer 0 Interval Value Register

TMR0_CUR_VALUE_REG

0x18

Timer 0 Current Value Register

TMR1_CTRL_REG

0x20

Timer 1 Control Register

TMR1_INTV_VALUE_REG

0x24

Timer 1 Interval Value Register

TMR1_CUR_VALUE_REG

0x28

Timer 1 Current Value Register

AVS_CNT_CTL_REG

0x80

AVS Control Register

AVS_CNT0_REG

0x84

AVS Counter 0 Register

AVS_CNT1_REG

0x88

AVS Counter 1 Register

AVS_CNT_DIV_REG

0x8C

AVS Divisor Register

WDOG0_IRQ_EN_REG

0xA0

Watchdog 0 IRQ Enable Register

WDOG0_IRQ_STA_REG

0xA4

Watchdog 0 Status Register

WDOG0_CTRL_REG

0xB0

Watchdog 0 Control Register

WDOG0_CFG_REG

0xB4

Watchdog 0 Configuration Register

WDOG0_MODE_REG

0xB8

Watchdog 0 Mode Register

3.6.5. Timer Register Description
3.6.5.1. Timer IRQ Enable Register (Default Value: 0x00000000)
Offset:0x0

Register Name: TMR_IRQ_EN_REG

Bit

R/W

Default/Hex

Description

31:2

/

/

/

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System
1

R/W

0x0

TMR1_IRQ_EN.
Timer 1 Interrupt Enable.
0: No effect;
1: Timer 1 Interval Value reached interrupt enable.

0

R/W

0x0

TMR0_IRQ_EN.
Timer 0 Interrupt Enable.
0: No effect;
1: Timer 0 Interval Value reached interrupt enable.

3.6.5.2. Timer IRQ Status Register (Default Value: 0x00000000)
Offset:0x04

Register Name: TMR_IRQ_STA_REG

Bit

R/W

31:2

/

Default/Hex

Description

/

/

1

R/W

0x0

TMR1_IRQ_PEND.
Timer 1 IRQ Pending. Set 1 to the bit will clear it.
0: No effect;
1: Pending, timer 1 interval value is reached.

0

R/W

0x0

TMR0_IRQ_PEND.
Timer 0 IRQ Pending. Set 1 to the bit will clear it.
0: No effect;
1: Pending, timer 0 interval value is reached.

3.6.5.3. Timer 0 Control Register (Default Value: 0x00000004)
Offset:0x10

Register Name: TMR0_CTRL_REG

Bit

R/W

Default/Hex

Description

31:8

/

/

/

7

R/W

0x0

TMR0_MODE.
Timer 0 mode.
0: Continuous mode. When interval value reached, the timer will notdisable automatically.
1: Single mode. When interval value reached, the timer will disable
automatically.

6:4

R/W

0x0

TMR0_CLK_PRES.
Select the pre-scale of timer 0 clock source.
000: /1
001: /2
010: /4
011: /8
100: /16

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System
101: /32
110: /64
111: /128
3:2

R/W

0x1

TMR0_CLK_SRC.
Timer 0 Clock Source.
00: 32K
01: OSC24M.
10: /
11: /

1

R/W

0x0

TMR0_RELOAD.
Timer 0 Reload.
0: No effect
1: Reload timer 0 Interval value.
After the bit is set, it can not be written again before it’s cleared
automatically.

0

R/W

0x0

TMR0_EN.
Timer 0 Enable.
0: Stop/Pause
1: Start.
When the timer is started, it will reload the interval value to internalregister, and the current counter will count from interval value to 0. If
the current counter does not reach the zero, the timer enable bit is set
to “0”, the current value counter will pause. At least wait for 2 cycles,
the start bit can be set to 1.In timer pause state; the interval value
register can be modified. If the timer is started again, and the Software
hope the current value register to down-count from the new intervalvalue, the reload bit and the enable bit should be set to 1 at the sametime.

3.6.5.4. Timer 0 Interval Value Register
Offset:0x14

Register Name: TMR0_INTV_VALUE_REG

Bit

R/W

Default/Hex

Description

31:0

R/W

0x0

TMR0_INTV_VALUE.
Timer 0 Interval Value.

Note:The value setting should consider the system clock and the timer clock source.

3.6.5.5. Timer 0 Current Value Register
Offset:0x18
Bit

R/W

Register Name: TMR0_CUR_VALUE_REG
Default/Hex

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System
31:0

R/W

0x0

TMR0_CUR_VALUE.
Timer 0 Current Value.

Note: Timer0 current value is a 32-bit down-counter (from interval value to 0).

3.6.5.6. Timer 1 Control Register (Default Value: 0x00000004)
Offset:0x20

Register Name: TMR1_CTRL_REG

Bit

R/W

Default/Hex

Description

31:8

/

/

/

7

R/W

0x0

TMR1_MODE.
Timer 1 mode.
0: Continuous mode. When interval value reached, the timer will notdisable automatically.
1: Single mode. When interval value reached, the timer will disable
automatically.

6:4

R/W

0x0

TMR1_CLK_PRES.
Select the pre-scale of timer 1 clock source.
000: /1
001: /2
010: /4
011: /8
100: /16
101: /32
110: /64
111: /128

3:2

R/W

0x1

TMR1_CLK_SRC.
00: 32K
01: OSC24M.
10: /
11: /.

1

R/W

0x0

TMR1_RELOAD.
Timer 1 Reload.
0: No effect
1: Reload timer 1 Interval value.
After the bit is set, it can not be written again before it’s cleared
automatically.

0

R/W

0x0

TMR1_EN.
Timer 1 Enable.
0: Stop/Pause
1: Start.
If the timer is started, it will reload the interval value to internal register,and the current counter will count from interval value to 0.
If the current counter does not reach the zero, the timer enable bit is set

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Systemto “0”, the current value counter will pause. At least wait for 2 cycles, thestart bit can be set to 1.
In timer pause state, the interval value register can be modified. If thetimer is started again, and the Software hope the current value register todown-count from the new interval value, the reload bit and the enable bit
should be set to 1 at the same time.

3.6.5.7. Timer 1 Interval Value Register
Offset:0x24

Register Name: TMR1_INTV_VALUE_REG

Bit

R/W

Default/Hex

Description

31:0

R/W

0x0

TMR1_INTV_VALUE.
Timer 1 Interval Value.

Note: The value setting should consider the system clock and the timer clock source.

3.6.5.8. Timer 1 Current Value Register
Offset:0x28

Register Name: TMR1_CUR_VALUE_REG

Bit

R/W

Default/Hex

Description

31:0

R/W

0x0

TMR1_CUR_VALUE.
Timer 1 Current Value.

Note: Timer1 current value is a 32-bit down-counter (from interval value to 0).

3.6.5.9. AVS Counter Control Register (Default Value: 0x00000000)
Offset:0x80

Register Name: AVS_CNT_CTL_REG

Bit

R/W

Default/Hex

Description

31:10

/

/

/

9

R/W

0x0

AVS_CNT1_PS.
Audio/Video Sync Counter 1 Pause Control
0: Not pause
1: Pause Counter 1.

8

R/W

0x0

AVS_CNT0_PS.
Audio/Video Sync Counter 0 Pause Control
0: Not pause
1: Pause Counter 0.

7:2

/

/

/

1

R/W

0x0

AVS_CNT1_EN.
Audio/Video Sync Counter 1 Enable/ Disable. The counter source is
OSC24M.

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System
0: Disable
1: Enable.
0

R/W

0x0

AVS_CNT0_EN.
Audio/Video Sync Counter 1 Enable/ Disable. The counter source is
OSC24M.
0: Disable
1: Enable.

3.6.5.10. AVS Counter 0 Register (Default Value: 0x00000000)
Offset:0x84

Register Name: AVS_CNT0_REG

Bit

R/W

Default/Hex

Description

31:0

R/W

0x0

AVS_CNT0.
Counter 0 for Audio/ Video Sync Application
The high 32 bits of the internal 33-bits counter register. The initial value ofthe internal 33-bits counter register can be set by software. The LSB bit of
the 33-bits counter register should be zero when the initial value isupdated. It will count from the initial value. The initial value can be
updated at any time. It can also be paused by setting AVS_CNT0_PS to ‘1’.
When it is paused, the counter won’t increase.

3.6.5.11. AVS Counter 1 Register (Default Value: 0x00000000)
Offset:0x88

Register Name: AVS_CNT1_REG

Bit

R/W

Default/Hex

Description

31:0

R/W

0x0

AVS_CNT1.
Counter 1 for Audio/ Video Sync Application
The high 32 bits of the internal 33-bits counter register. The initial value ofthe internal 33-bits counter register can be set by software. The LSB bit of
the 33-bits counter register should be zero when the initial value isupdated. It will count from the initial value. The initial value can be
updated at any time. It can also be paused by setting AVS_CNT1_PS to ‘1’.
When it is paused, the counter won’t increase.

3.6.5.12. AVS Counter Divisor Register (Default Value: 0x05DB05DB)
Offset:0x8C

Register Name: AVS_CNT_DIV_REG

Bit

R/W

Default/Hex

Description

31:28

/

/

/

27:16

R/W

0x5DB

AVS_CNT1_D.

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System
Divisor N for AVS Counter 1
AVS CN1 CLK=24MHz/Divisor_N1.
Divisor N1 = Bit [27:16] + 1.
The number N is from 1 to 0x7ff. The zero value is reserved.
The internal 33-bits counter engine will maintain another 12-bits counter.
The 12-bits counter is used for counting the cycle number of one 24Mhz
clock. When the 12-bits counter reaches (>= N) the divisor value, theinternal 33-bits counter register will increase 1 and the 12-bits counter
will reset to zero and restart again.
15:12

/

/

/

11:0

R/W

0x5DB

AVS_CNT0_D.
Divisor N for AVS Counter 0
AVS CN0 CLK=24MHz/Divisor_N0.
Divisor N0 = Bit [11:0] + 1
The number N is from 1 to 0x7ff. The zero value is reserved.
The internal 33-bits counter engine will maintain another 12-bits counter.
The 12-bits counter is used for counting the cycle number of one 24Mhz
clock. When the 12-bits counter reaches (>= N) the divisor value, theinternal 33-bits counter register will increase 1 and the 12-bits counter
will reset to zero and restart again.

Note: Divisor N can be configured by software at any time.

3.6.5.13. Watchdog IRQ Enable Register (Default Value: 0x00000000)
Offset:0xA0

Register Name: WDOG_IRQ_EN_REG

Bit

R/W

Default/Hex

Description

31:1

/

/

/

0

R/W

0x0

WDOG_IRQ_EN.
Watchdog Interrupt Enable.
0: No effect
1: Watchdog interrupt enable.

3.6.5.14. Watchdog Status Register (Default Value: 0x00000000)
Offset:0xA4

Register Name: WDOG_IRQ_STA_REG

Bit

R/W

Default/Hex

Description

31:1

/

/

/

0

R/W

0x0

WDOG_IRQ _PEND.
Watchdog n IRQ Pending. Set 1 to the bit will clear it.
0: No effect,
1: Pending, watchdog interval value is reached.

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3.6.5.15. Watchdog Control Register (Default Value: 0x00000000)
Offset:0xB0

Register Name: WDOG_CTRL_REG

Bit

R/W

Default/Hex

Description

31:13

/

/

/

12:1

R/W

0x0

WDOG_KEY_FIELD.
Watchdog Key Field.
Should be written at value 0xA57. Writing any other value in this fieldaborts the write operation.

0

R/W

0x0

WDOG_RSTART.
Watchdog Restart.
0: No effect,
1: Restart watchdog0.

3.6.5.16. Watchdog Configuration Register (Default Value: 0x00000001)
Offset:0xB4

Register Name: WDOG_CFG_REG

Bit

R/W

Default/Hex

Description

31:2

/

/

/

1:0

R/W

0x1

WDOG_CONFIG.
Watchdog generates a reset signal
00: /01: To whole system
10: Only interrupt
11: /

3.6.5.17. Watchdog Mode Register (Default Value: 0x00000000)
Offset:0xB8

Register Name: WDOG_MODE_REG

Bit

R/W

Default/Hex

Description

31:8

/

/

/

7:4

R/W

0x0

WDOG_INTV_VALUE.
Watchdog Interval Value
Watchdog clock source is OSC24M / 750. If the clock source is turned off,
Watchdog will not work.
0000: 16000 cycles (0.5s)
0001: 32000 cycles (1s)0010: 64000 cycles (2s)0011: 96000 cycles (3s)
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0101: 160000 cycles (5s)0110: 192000 cycles (6s)0111: 256000 cycles (8s)
1000: 320000 cycles (10s)1001: 384000 cycles (12s)1010: 448000 cycles (14s)
1011: 512000 cycles (16s)others: /
3:1

/

/

/

0

R/W

0x0

WDOG_EN.
Watchdog Enable.
0: No effect;
1: Enable watchdog.

3.6.6. Programming Guidelines
3.6.6.1. Timer
Take making a Timer0 1ms delay for an example, 24M clock source, single mode and 2 pre-scale will beselected in the instance.
writel(0x2EE0, TMR0_INTV_VALUE_REG);//Set interval value
writel(0x94, TMR0_CTRL_REG);//Select Single mode,24MHz clock source,2 pre-scale
writel(readl(TMR0_CTRL_REG)|(1<<1), TMR0_CTRL_REG); //Set Reload bit
while((readl(TMR0_CTRL_REG)>>1)&1);//Waiting Reload bit turns to 0
writel(readl(TMR0_CTRL_REG)|(1<<0), TMR0_CTRL_REG); //Enable Timer0
3.6.6.2. Watchdog
In the following instance making configurations for Watchdog: configurate clock source as 24M/750,
configurate Interval Value as 1s and configurate Watchdog Configuration as To whole system. This instanceindicates that restarting Watchdog after 0.5s inside Interval Value.
writel(0x1, WDOG_CFG_REG);//To whole systemwritel(0x10, WDOG_MODE_REG);//Interval Value set 1s
writel(readl(WDOG_MODE_REG)|(1<<0), WDOG_MODE_REG); //Enable Watchdog
delay_ms(500);//Delay 500ms
writel(readl(WDOG_CTRL_REG)|(0xA57<<1)|(1<<0)，WDOG_CTRL_REG); //Writel 0xA57 at Key Field andRestart Watchdog……………After 1s, Watchdog will general a pending, which would reset the system……………

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3.7. R_Trusted Watchdog Timer
3.7.1. Overview
The r_trusted watchdog timer is primarily used to protect the trusted world operations from denial of service
when secure services are dependent to the RichOS scheduler. For example, if the trusted world is not enteredafter a defined time limit the SoC is re-started to perform an authentication of the system.
The r_trusted watchdog timer can also be used to mask the real cause of a security error thanks to the delayed
warm reset it generates.

3.7.2. Block Diagram
Hi/Low Counter
Stop Rolling-overDefualt Status
Read Latch Enable

Hi/Low Counter
Continue Rolling-overResum?

Stop Enable
Reset Flag
After
Warm
Reset

Stop?
Read Value?

Cold
Reset

24M

TWD

Hi/Low Counter
Rolling-over

CMP Counter Value =Hi/Low Counter Value + Interval Value

Clear
Counter?

Interval Value
RegisterLOSC

CMP Counter
Value ==
Hi/Low Counter
Value ?

yes

Reset
EnableReset

IRQ
EnableIRQ

Pending

RestartCounter Value and Interval Value are
ClearedClear Enable

Interval Value

Figure 3-6. TWD Block Diagram
The trusted watchdog timer must always be running when the SoC wakes up from cold reset and can berefreshed, suspended, or reset only by secure accesses. And a clock of at least 32 kHz is used when the device is
not a power saving cycles.

3.7.3. Functionalities Description
3.7.3.1. TWD Reset
The trusted watchdog timer is able to generate a SoC warm reset after a duration programmed into the timer
or set by default in hardware. And the flag indicating the occurrence of a watchdog triggered warm reset has

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Clock sources driving the watchdog timer must be controlled or managed by a trusted entity. This means that
non-trusted world accesses are not permitted to turn on, turn off or modify the characteristics of clock source.
The clear enable bit will reset relevant bits in R_TWD_CTRL_REG, except the reset flag.

3.7.3.2. NV-Counter
After a firmware image is validated, the image revision number taken from the certificate extension field, forexample, Trusted Firmware NV-Counter is compared with the corresponding NV-Counter stored in hardware. If
the value is: Less than the associated NV-Counter, then the authentication fail.
 Identical to the NV-Counter, then the authentication is successful.
 More than the NV-Counter, then the authentication are successful and the NV-Counter is updated.
The 2^32 monotonic counter does not need to be e-Fuses, but it does need to be fully secure. Using the SoC
embedded NVM, or external secure element, or a trusted register, which is always on power.
The Secure Storage NV-Counter Register is used for protecting the trusted world Secure Storage (SST) file from
replay attacks, since SST contains subsidiary relay attacks protection counters for each Trusted Application.
Four 32-bit counters are used for counting 2^32 states for synchronizing data stores against replay attacks.
These counters are optionally required since they can be handled by a Trusted OS service using the securestorage at boot time or using eMMC v4.4x Replay Protected Memory Block (RPMB).

3.7.4. TWD Register List
Module Name

Base Address

TWD

0x01F01800

Register Name

OffsetDescription

R_TWD_STA_REG

0x0

R_TWD Status Register

R_TWD_CTRL_REG

0x10

R_TWD Control Register

R_TWD_RESTA_REG

0x14

R_TWD Restart Register

R_TWD_LOW_COUNTER_REG

0x20

R_TWD Low Counter Register

R_TWD_HI_COUNTER_REG

0x24

R_TWD High Counter Register

R_TWD_INTV_VAL_REG

0x30

R_TWD Interval Value Register

R_TWD_LOW_CMP_REG

0x40

R_TWD Low Counter Compare Register

R_TWD_HI_CMP_REG

0x44

R_TWD High Counter Compare Register

SST_NV_COUNTER_REG

0x100

Secure Storage NV-Counter Register

SYN_DATA_COUNTER_REG0

0x110

Synchronize Data Counter Register 0

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SYN_DATA_COUNTER_REG1

0x114

Synchronize Data Counter Register 1

SYN_DATA_COUNTER_REG2

0x118

Synchronize Data Counter Register 2

SYN_DATA_COUNTER_REG3

0x11c

Synchronize Data Counter Register 3

3.7.5. R_TWD Register Description
3.7.5.1. R_TWD Status Register (Default Value: 0x00000000)
Offset: 0x0000

Register Name: R_TWD_STATUS_REG

Bit

R/W

Default/Hex

Description

31:1

/

/

/

0

R/W

0x0

R_TWD_PEND_FLAG.
Trusted watchdog timer’s interrupt pending. Set 1 to the bit will clear it.
0: No effect
1: Pending

3.7.5.2. R_TWD Control Register (Default Value: 0x00000000)
Offset: 0x0010

Register Name: R_TWD_CTRL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

CNT64_CLK_SRC_SEL.
64-bit counter clock source select.
0: LOSC.
1: OSC24M.

30:10

/

/

/

9

R/W

0x0

R_TWD_RESET_EN.
R_TWD reset enable.
0: Reset disable.
1: Reset enable.

8

R/W

0x0

R_TWD_INT_EN.
R_TWD Interrupt Enable.
0: Interrupt disable.
1: Interrupt enable.

7:2

/

/

/

1

R/W

0x0

R_TWD_STOP_EN.
R_TWD stop enable.
0: Resume rolling-over.
1: Stop rolling-over.

0

R/W

0x0

R_TWD_CLR_EN.
R_TWD clear enable.

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0: No effect.
1: To clear relevant registers and it will change to zero after the registers
are cleared.

3.7.5.3. R_TWD Restart Register (Default Value: 0x00000000)
Offset: 0x0014

Register Name: R_TWD_RESTART_REG

Bit

R/W

Default/Hex

Description

31:28

/

/

/

27:16

WO

0x0

R_TWD_RESTART_KEYFILED.
Should be written at value 0xD14. Writing any other value in this fieldaborts the write operation.

15:1

/

/

/

0

WO

0x0

R_TWD_RESTART_EN.
If writing ‘1’ in this bit, the value of Counter Compare Register wouldchange.
0: No effect.
1: Restart enable.

3.7.5.4. R_TWD Low Counter Register (Default Value: 0x00000000)
Offset: 0x0020

Register Name: R_TWD_LOW_CNT_REG

Bit

R/W

Default/Hex

Description

31:0

RO

0x0

R_TWD_LOW_CNT.
The TWD low 32-bit counter.

3.7.5.5. R_TWD High Counter Register (Default Value: 0x00000000)
Offset: 0x0024

Register Name: R_TWD_HIGH_CNT_REG

Bit

R/W

Default/Hex

Description

31:0

RO

0x0

R_TWD_HIGH_CNT.
The TWD high 32-bit counter.

3.7.5.6. R_TWD Interval Value Register (Default Value: 0x00000000)
Offset: 0x0030

Register Name: R_TWD_INTV_VAL_REG

Bit

R/W

Default/Hex

Description

31:0

R/W

0x0

R_TWD_INTV_VAL.

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The TWD interval value.

3.7.5.7. R_TWD Low Counter Compare Register (Default Value: 0x00000000)
Offset: 0x0040

Register Name: R_TWD_LOW_CNT_CMP_REG

Bit

R/W

Default/Hex

Description

31:0

RO

0x0

R_TWD_LOW_CMP.
The TWD low 32-bit compare counter.

3.7.5.8. R_TWD High Counter Compare Register (Default Value: 0x00000000)
Offset: 0x0044

Register Name: R_TWD_HIGH_CNT_CMP_REG

Bit

R/W

Default/Hex

Description

31:0

RO

0x0

R_TWD_HIGH_CMP.
The TWD high 32-bit compare counter.

3.7.5.9. Secure Storage NV-Counter Register (Default Value: 0x00000000)
Offset: 0x0100

Register Name: SST_NV_CNT_REG

Bit

R/W

Default/Hex

Description

31:0

R/W

0x0

SST_NV_CNT.
This counter protects the trusted world Secure Storage file from replay
attacks.

3.7.5.10. Synchronize Data Counter Register 0 (Default Value: 0x00000000)
Offset: 0x0110

Register Name: SYN_DATA_CNT_REG0

Bit

R/W

Default/Hex

Description

31:0

R/W

0x0

SYN_DATA_CNT0.
This counter is used for synchronizing data stores against replay attacks.

3.7.5.11. Synchronize Data Counter Register 1 (Default Value: 0x00000000)
Offset: 0x0114

Register Name: SYN_DATA_CNT_REG1

Bit

R/W

Default/Hex

Description

31:0

R/W

0x0

SYN_DATA_CNT1.
This counter is used for synchronizing data stores against replay attacks.

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3.7.5.12. Synchronize Data Counter Register 2 (Default Value: 0x00000000)
Offset: 0x0118

Register Name: SYN_DATA_CNT_REG2

Bit

R/W

Default/Hex

Description

31:0

R/W

0x0

SYN_DATA_CNT2.
This counter is used for synchronizing data stores against replay attacks.

3.7.5.13. Synchronize Data Counter Register 3 (Default Value: 0x00000000)
Offset: 0x011C

Register Name: SYN_DATA_CNT_REG3

Bit

R/W

Default/Hex

Description

31:0

R/W

0x0

SYN_DATA_CNT3.
This counter is used for synchronizing data stores against replay attacks.

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3.8. RTC
3.8.1. Overview
The real time clock (RTC) is for calendar usage. It is built around a 30-bit counter and used to count elapsed
time in YY-MM-DD and HH-MM-SS. The unit can be operated by the backup battery while the system power isoff. It has a built-in leap year generator and a independent power pin (RTC_VIO).
The alarm generates an alarm signal at a specified time in the power-off mode or normal operation mode. In
normal operation mode, both the alarm interrupt and the power management wakeup are activated. In
power-off mode, the power management wakeup signal is activated. In this section, there are two kinds ofalarm. Alarm 0 is a general alarm, its counter is based on second. Alarm 1 is a weekly alarm, its counter isbased on the real time.
The 32768Hz oscillator is used only to provide a low power, accurate reference for the RTC.
General Purpose Register can be flag register, and it will save the value all the time when the VDD_RTC is not
power off.

3.8.2. RTC Register List
Module Name

Base Address

RTC

0x01F00000

Register Name

OffsetDescription

LOSC_CTRL_REG

0x0

Low Oscillator Control Register

LOSC_AUTO_SWT_STA_REG

0x4

LOSC Auto Switch Status Register

INTOSC_CLK_PRESCAL_REG

0x8

Internal OSC Clock Prescalar Register

RTC_YY_MM_DD_REG

0x10

RTC Year-Month-Day Register

RTC_HH_MM_SS_REG

0x14

RTC Hour-Minute-Second Register

ALARM0_COUNTER_REG

0x20

Alarm 0 Counter Register

ALARM0_CUR_VLU_REG

0x24

Alarm 0 Counter Current Value Register

ALARM0_ENABLE_REG

0x28

Alarm 0 Enable Register

ALARM0_IRQ_EN

0x2C

Alarm 0 IRQ Enable Register

ALARM0_IRQ_STA_REG

0x30

Alarm 0 IRQ Status Register

ALARM1_WK_HH_MM-SS

0x40

Alarm 1 Week HMS Register

ALARM1_ENABLE_REG

0x44

Alarm 1 Enable Register

ALARM1_IRQ_EN

0x48

Alarm 1 IRQ Enable Register

ALARM1_IRQ_STA_REG

0x4C

Alarm 1 IRQ Status Register

ALARM_CONFIG_REG

0x50

Alarm Config Register

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LOSC_OUT_GATING_REG

0x60

LOSC output gating register

GP_DATA_REG

0x100 + N*0x4

General Purpose Register (N=0~3)

GPL_HOLD_OUTPUT_REG

0x180

GPL Hold Output Register

VDD_RTC_REG

0x190

VDD RTC Regulate Register

IC_CHARA_REG

0x1F0

IC Characteristic Register

Crypt Configuration Register

0x210

CRY_CONFIG_REG

Crypt Key Register

0x214

CRY_KEY_REG

Crypt Enable Register0x218

CRY_CONFIG_REG

3.8.3. RTC Register Description
3.8.3.1. LOSC Control Register (Default Value: 0x00004000)
Offset:0x0

Register Name: LOSC_CTRL_REG

Bit

R/W

Default/Hex

Description

31:16

W

0x0

KEY_FIELD.
Key Field. This field should be filled with 0x16AA, and then the bit 0 can be
written with the new value.

15

/

/

/

14

R/W

0x1

LOSC_AUTO_SWT_EN.
LOSC auto switch enable.
0: Disable, 1: Enable.

13:10

/

/

/

9

R/W

0x0

ALM_DDHHMMSS_ACCE.
ALARM DD-HH-MM-SS access.
After writing the ALARM DD-HH-MM-SS register, this bit is set and it will
be cleared until the real writing operation is finished.

8

R/W

0x0

RTC_HHMMSS_ACCE.
RTC HH-MM-SS access.
After writing the RTC HH-MM-SS register, this bit is set and it will becleared until the real writing operation is finished.
After writing the RTC HH-MM-SS register, the HH-MM-SS register will be
refreshed for at most one second.

7

R/W

0x0

RTC_YYMMDD_ACCE.
RTC YY-MM-DD access.
After writing the RTC YY-MM-DD register, this bit is set and it will becleared until the real writing operation is finished.
After writing the RTC YY-MM-DD register, the YY-MM-DD register will be
refreshed for at most one second.

6:4

/

/

/

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System
3:2

R/W

0x0

EXT_LOSC_GSM.
External 32768Hz Crystal GSM.
00: low01:/
10:/
11:high

1

/

/

/

0

R/W

0x0

LOSC_SRC_SEL.
LOSC Clock source Select. ‘N’ is the value of Internal OSC Clock Prescalarregister.
0: InternalOSC /32/ N
1: External 32.768KHz OSC.

Note1: Any bit of [9:7] is set, the RTC HH-MM-SS, YY-MM-DD and ALARM DD-HH-MM-SS register can’t bewritten.
Note2: Internal OSC is about 16MHz.

3.8.3.2. LOSC Auto Switch Status Register (Default Value: 0x00000000)
Offset:0x4

Register Name: LOSC_AUTO_SWT_STA_REG

Bit

R/W

Default/Hex

Description

31:2

/

/

/

1

R/W

0x0

LOSC_AUTO_SWT_PEND.
LOSC auto switch pending.
0: No effect
1: Auto switches pendingSet 1 to this bit will clear it.

0

RO

0x0

LOSC_SRC_SEL_STA.
Checking LOSC Clock Source Status. ‘N’ is the value of Internal OSC Clock
Prescalar register.
0: InternalOSC / N
1: External 32.768KHz OSC

3.8.3.3. Internal OSC Clock Prescalar Register (Default Value: 0x0000000F)
Offset:0x8

Register Name: INTOSC_CLK_PRESCAL_REG

Bit

R/W

Default/Hex

Description

31:5

/

/

/

4:0

R/W

0xF

INTOSC_CLK_PRESCAL.
Internal OSC Clock Prescalar value N.
00000: 100001: 2

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00010: 3............
11111: 32

3.8.3.4. RTC YY-MM-DD Register (Default Value: 0x00000000)
Offset:0x10

Register Name: RTC_YY_MM_DD_REG

Bit

R/W

Default/Hex

Description

31:23

/

/

/

22

R/W

0x0

LEAP.
Leap Year.
0: not, 1: Leap year.
This bit can not set by hardware. It should be set or clear by software.

21:16

R/W

x

YEAR.
Year.
Range from 0~63.

15:12

/

/

/

11:8

R/W

x

MONTH.
Month.
Range from 1~12.

7:5

/

/

/

4:0

R/W

x

DAY.
Day.
Range from 1~31.

Note1: If the written value is not from 1 to 31 in Day Area, it turns into 31 automatically. Month Area and Year
Area are similar to Day Area.
Note2: The number of days in different month may be different.

3.8.3.5. RTC HH-MM-SS Register (Default Value: 0x00000000)
Offset:0x14

Register Name: RTC_HH_MM_SS_REG

Bit

R/W

Default/Hex

Description

31:29

R/W

0x0

WK_NO.
Week number.
000: Monday
001: Tuesday
010: Wednesday
011: Thursday
100: Friday
101: Saturday
110: Sunday

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111: /
28:21

/

/

/

20:16

R/W

x

HOUR.
Range from 0~23

15:14

/

/

/

13:8

R/W

x

MINUTE.
Range from 0~59

7:6

/

/

/

5:0

R/W

x

SECOND.
Range from 0~59

Note: If the written value is not from 0 to 59 in Second Area, it turns into 59 automatically. Minute Area andHour Area are similar to Second Area.

3.8.3.6. Alarm 0 Counter Register (Default Value: 0x00000000)
Offset:0x20

Register Name: ALARM0_COUNTER_REG

Bit

R/W

Default/Hex

Description

31:0

R/W

0x0

ALARM0_COUNTER.
Alarm 0 Counter is Based on Second.

Note: If the second is set to 0, it will be 1 second in fact.

3.8.3.7. Alarm 0 Current Value Register
Offset:0x24

Register Name: ALARM0_CUR_VLU_REG

Bit

R/W

Default/Hex

Description

31:0

RO

x

ALARM0_CUR_VLU.
Check Alarm 0 Counter Current Values.

Note: If the second is set to 0, it will be 1 second in fact.

3.8.3.8. Alarm 0 Enable Register (Default Value: 0x00000000)
Offset:0x28

Register Name: ALARM0_ENABLE_REG

Bit

R/W

Default/Hex

Description

31:1

/

/

/

0

R/W

0x0

ALM_0_EN
Alarm 0 Enable.
If this bit is set to “1”, the Alarm 0 Counter register’s valid bits will down

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Systemcount to zero, and the alarm pending bit will be set to “1”.
0: Disable
1: Enable

3.8.3.9. Alarm 0 IRQ Enable Register (Default Value: 0x00000000)
Offset:0x2C

Register Name: ALARM0_IRQ_EN

Bit

R/W

Default/Hex

Description

31:1

/

/

/

0

R/W

0x0

ALARM0_IRQ_EN.
Alarm 0 IRQ Enable.
0: Disable
1: Enable

3.8.3.10. Alarm 0 IRQ Status Register (Default Value: 0x00000000)
Offset:0x30

Register Name: ALARM0_IRQ_STA_REG

Bit

R/W

Default/Hex

Description

31:1

/

/

/

0

R/W

0x0

ALARM0_IRQ_PEND.
Alarm 0 IRQ Pending bit.
0: No effect
1: Pending, alarm 0 counter value is reached
If alarm 0 irq enable is set to 1, the pending bit will be sent to theinterrupt controller.

3.8.3.11. Alarm 1 Week HH-MM-SS Register (Default Value: 0x00000000)
Offset:0x40

Register Name: ALARM1_WK_HH_MM_SS

Bit

R/W

Default/Hex

Description

31:21

/

/

/

20:16

R/W

x

HOUR.
Range from 0~23.

15:14

/

/

/

13:8

R/W

x

MINUTE.
Range from 0~59.

7:6

/

/

/

5:0

R/W

x

SECOND.
Range from 0~59.

Note: If the written value is not from 0 to 59 in Second Area, it turns into 59 automatically. Minute Area and
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3.8.3.12. Alarm 1 Enable Register (Default Value: 0x00000000)
Offset:0x44

Register Name: ALARM1_EN_REG

Bit

R/W

Default/Hex

Description

31:7

/

/

/

6

R/W

0x0

WK6_ALM1_EN.
Week 6 (Sunday) Alarm 1 Enable.
0: Disable
1: Enable
If this bit is set to “1”, only when the bit[20:0] of Alarm 1 Week
HH-MM-SS Register are equal to the bit[20:0] of RTC HH-MM-SS Registerand the bit [31:29] of RTC HH-MM-SS Register is 6, the week 6 alarm irq
pending bit will be set to “1”.

5

R/W

0x0

WK5_ALM1_EN.
Week 5 (Saturday) Alarm 1 Enable.
0: Disable
1: Enable
If this bit is set to “1”, only when the bit[20:0] of Alarm 1 Week
HH-MM-SS Register are equal to the bit[20:0] of RTC HH-MM-SS Registerand the bit [31:29] of RTC HH-MM-SS Register is 5, the week 5 alarm irq
pending bit will be set to “1”.

4

R/W

0x0

WK4_ALM1_EN.
Week 4 (Friday) Alarm 1 Enable.
0: Disable
1: Enable
If this bit is set to “1”, only when the bit[20:0] of Alarm 1 Week
HH-MM-SS Register are equal to the bit[20:0] of RTC HH-MM-SS Registerand the bit [31:29] of RTC HH-MM-SS Register is 4, the week 4 alarm irq
pending bit will be set to “1”.

3

R/W

0x0

WK3_ALM1_EN.
Week 3 (Thursday) Alarm 1 Enable.
0: Disable
1: Enable
If this bit is set to “1”, only when the bit[20:0] Alarm 1 Week HH-MM-SS
Register valid bits are equal to the bit[20:0] of RTC HH-MM-SS Registerand the bit [31:29] of RTC HH-MM-SS Register is 3, the week 3 alarm irq
pending bit will be set to “1”.

2

R/W

0x0

WK2_ALM1_EN.
Week 2 (Wednesday) Alarm 1 Enable.
0: Disable

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1: Enable
If this bit is set to “1”, only when the bit[20:0] Alarm 1 Week HH-MM-SS
Register valid bits are equal to the bit[20:0] of RTC HH-MM-SS Registerand the bit [31:29] of RTC HH-MM-SS Register is 2, the week 2 alarm irq
pending bit will be set to “1”.
1

R/W

0x0

WK1_ALM1_EN.
Week 1 (Tuesday) Alarm 1 Enable.
0: Disable
1: Enable
If this bit is set to “1”, only when the bit[20:0] Alarm 1 Week HH-MM-SS
Register valid bits are equal to the bit[20:0] of RTC HH-MM-SS Registerand the bit [31:29] of RTC HH-MM-SS Register is 1, the week 1 alarm irq
pending bit will be set to “1”.

0

R/W

0x0

WK0_ALM1_EN.
Week 0 (Monday) Alarm 1 Enable.
0: Disable
1: Enable
If this bit is set to “1”, only when the bit[20:0] Alarm 1 Week HH-MM-SS
Register valid bits are equal to the bit[20:0] of RTC HH-MM-SS Registerand the bit [31:29] of RTC HH-MM-SS Register is 0, the week 0 alarm irq
pending bit will be set to “1”.

3.8.3.13. Alarm 1 IRQ Enable Register (Default Value: 0x00000000)
Offset:0x48

Register Name: ALARM1_IRQ_EN

Bit

R/W

Default/Hex

Description

31:1

/

/

/

0

R/W

0x0

ALARM1_IRQ_EN.
Alarm 1 IRQ Enable.
0: Disable
1: Enable

3.8.3.14. Alarm 1 IRQ Status Register (Default Value: 0x00000000)
Offset:0x4C

Register Name: ALARM1_IRQ_STA_REG

Bit

R/W

Default/Hex

Description

31:1

/

/

/

0

R/W

0x0

ALARM1_WEEK_IRQ_PEND.
Alarm 1 Week (0/1/2/3/4/5/6) IRQ Pending.
0: No effect
1: Pending, week counter value is reached

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If alarm 1 week irq enable is set to 1, the pending bit will be sent to theinterrupt controller.

3.8.3.15. Alarm Config Register (Default Value: 0x00000000)
Offset:0x50

Register Name: ALARM_CONFIG_REG

Bit

R/W

Default/Hex

Description

31:1

/

/

/

0

R/W

0x0

ALARM_WAKEUP.
Configuration of alarm wake up output.
0: Disable alarm wake up output
1: Enable alarm wake up output

3.8.3.16. LOSC Output Gating Register (Default Value: 0x00000000)
Offset:0x60

Register Name: LOSC_OUT_GATING_REG

Bit

R/W

Default/Hex

Description

31:1

/

/

/

0

R/W

0x0

LOSC_OUT_GATING.
Configuration of LOSC output, and no LOSC output by default.
0: Enable LOSC output gating
1: Disable LOSC output gating

3.8.3.17. General Purpose Register (Default Value: 0x00000000)
Offset:0x100+N *0x4
(N=0~7)

Register Name: GP_DATA_REGn

Bit

R/W

Default/Hex

Description

31:0

R/W

0x0

GP_DATA.
Data [31:0].

Note: General purpose register 0~7 value can be stored if the VCC-RTC is larger than 1.0v.

3.8.3.18. GPL Hold Output Register (Default Value: 0x00000000)
Offset:0x180

Register Name: GPL_HOLD_OUTPUT_REG

Bit

R/W

Default/Hex

Description

31:12

/

/

/

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11

R/W

0x0

GPL11_HOLD_OUTPUT.
Hold the output of GPIOL11 when system’s power is changing. The
output must be low level (0) or high level (1) or High-Z; any other
outputs may not hold on.
0: Hold disable
1: Hold enable

10

R/W

0x0

GPL10_HOLD_OUTPUT.
Hold the output of GPIOL10 when system’s power is changing. The
output must be low level (0) or high level (1) or High-Z; any other
outputs may not hold on.
0: Hold disable
1: Hold enable

9

R/W

0x0

GPL9_HOLD_OUTPUT.
Hold the output of GPIOL9 when system’s power is changing. The output
must be low level (0) or high level (1) or High-Z; any other outputs may
not hold on.
0: Hold disable
1: Hold enable

8

R/W

0x0

GPL8_HOLD_OUTPUT.
Hold the output of GPIOL8 when system’s power is changing. The output
must be low level (0) or high level (1) or High-Z; any other outputs may
not hold on.
0: Hold disable
1: Hold enable

7

R/W

0x0

GPL7_HOLD_OUTPUT.
Hold the output of GPIOL7 when system’s power is changing. The output
must be low level (0) or high level (1) or High-Z; any other outputs may
not hold on.
0: Hold disable
1: Hold enable

6

R/W

0x0

GPL6_HOLD_OUTPUT.
Hold the output of GPIOL6 when system’s power is changing. The output
must be low level (0) or high level (1) or High-Z; any other outputs may
not hold on.
0: Hold disable
1: Hold enable

5

R/W

0x0

GPL5_HOLD_OUTPUT.
Hold the output of GPIOL5 when system’s power is changing. The output
must be low level (0) or high level (1) or High-Z; any other outputs may
not hold on.
0: Hold disable
1: Hold enable

4

R/W

0x0

GPL4_HOLD_OUTPUT.
Hold the output of GPIOL4 when system’s power is changing. The

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outputs must be low level (0) or high level (1) or High-Z; any other
output may not hold on.
0: Hold disable
1: Hold enable
3

R/W

0x0

GPL3_HOLD_OUTPUT.
Hold the output of GPIOL3 when system’s power is changing. The output
must be low level (0) or high level (1) or High-Z; any other outputs may
not hold on.
0: Hold disable
1: Hold enable

2

R/W

0x0

GPL2_HOLD_OUTPUT.
Hold the output of GPIOL2 when system’s power is changing. The output
must be low level (0) or high level (1) or High-Z; any other outputs may
not hold on.
0: Hold disable
1: Hold enable

1

R/W

0x0

GPL1_HOLD_OUTPUT.
Hold the output of GPIOL1 when system’s power is changing. The output
must be low level (0) or high level (1) or High-Z; any other outputs may
not hold on.
0: Hold disable
1: Hold enable

0

R/W

0x0

GPL0_HOLD_OUTPUT.
Hold the output of GPIOL0 when system’s power is changing. The output
must be low level (0) or high level (1) or High-Z; any other outputs may
not hold on.
0: Hold disable
1: Hold enable

3.8.3.19. VDD RTC Regulation Register (Default Value: 0x00000004)
Offset:0x190

Register Name: VDD_RTC_REG

Bit

R/W

Default/Hex

Description

31:3

/

/

/

2:0

R/W

0x100

VDD_RTC_REGU.
These bits are useful for regulating the RTC_VIO from 0.7v to 1.4v, andthe regulation step is 0.1v.
000: 0.7v
001: 0.8v
010: 0.9v
011: 1.0v
100: 1.1v
101: 1.2v

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110: 1.3v
111: 1.4v

3.8.3.20. IC Characteristic Register (Default Value: 0x00000000)
Offset:0x1F0

Register Name: IC_CHARA_REG

Bit

Read/Write

Default/Hex

Description

31:16

R/W

0x0

IC_CHARA.
Key Field.
Should be written at value 0x16AA. Writing any other value in this fieldaborts the write operation.

15:0

R/W

0x0

ID_DATA.
Return 0x16AA only if the KEY_FIELD is set as 0x16AA when read thosebits, otherwise return 0x0.

3.8.3.21. Crypt Configuration Register (Default Value: 0x00000000)
Offset:0x210

Register Name: CRY_CONFIG_REG

Bit

Read/Write

Default/Hex

Description

31:16

/

/

/

15:0

R/W

0x0

KEY_FIELDKey Field

3.8.3.22. Crypt Key Register (Default Value: 0x00000000)
Offset:0x214

Register Name: CRY_KEY_REG

Bit

Read/Write

Default/Hex

Description

31:0

R/W

0x0

CRY_KEY
Crypt Key

3.8.3.23. Crypt Enable Register (Default Value: 0x00000000)
Offset:0x218

Register Name: CRY_CONFIG_REG

Bit

Read/Write

Default/Hex

Description

31:1

/

/

/

0

R/W

0x0

CRY_EN
Crypt enable

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3.9. High-speed Timer
3.9.1. Overview
High Speed Timer' clock source is fixed to AHBCLK, which is much higher than OSC24M and so this kind oftimer is called High Speed Timer. Compared with other timers, High Speed Timer calculates much moreaccurately. When the relevant bit in the Control Register is set 1, hstimer goes into the test mode, which isused to System Simulation. While the current value in both LO and HI Current Value Register are counting
down to zero, the timer will generate interrupt if set interrupt enable bit.
The High Speed Timer includes the following features:

1 HSTimer with individual 56-bit counter
HSTimer could generate a pending
Clock source is synchronized with AHB clock, which means calculating much more accurate than othertimersSupport Test Mode for System Simulation

3.9.2. Operation Principle
3.9.2.1. HSTimer clock gating and software reset
By default the HSTimer clock gating is mask. When it is necessary to use HSTimer, it’s clock gating should be
open in Bus Clock Gating Register0 and then de-assert the software reset in Bus Software Reset Register 0 on
CCU module. If it is no need to use HSTimer, both the gating bit and software reset bit should be set 0.

3.9.2.2. HSTimer reload bit
Differing from the reload of Timer, when interval value is reloaded into HS Timer Current Value Lo Registerand HS Timer Current Value Hi Register, the Reload bit would not turn to 0 automatically until you clear it. If
software hopes the HS Timer Current Value Lo Register and HS Timer Current Value Hi Register todown-count from the new Interval Value in pause status, the Reload bit and the Enable bit should be written 1
at the same time.

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3.9.3. HSTimer Block Diagram
n _modeSinglemode

IRQ EN/1/2/4

AHBCLKInterval Value

HSTimer

EnableIV=0?

Yes

Pending/8/16

Test mode

Continuousmode

Figure 3-7. HSTimer function structure and work flow
HSTimer has two work modes and two count modes. n_mode is used for normal counting and Test mode isused in System Simulation. Each work mode has the two count mode: Single mode and Continuous mode.
These two count modes have the same principle with Timers’, which means when Current Value counts down
to 0, HSTimer will be disable in Single mode ,but HSTimer will not be disable and counts from Interval value
again in Continuous mode. About HSTimer 56-bit counter, it is combined with a high 24-bit counter(HS Timer
Current Value Hi Register) and a low 32-bit counter(HS Timer Current Value Lo Register).

3.9.4. HSTimer Register List
Module Name

Base Address

High Speed Timer

0x01C60000

Register Name

OffsetDescription

HS_TMR_IRQ_EN_REG

0x00

HS Timer IRQ Enable Register

HS_TMR_IRQ_STAS_REG

0x04

HS Timer Status Register

HS_TMR_CTRL_REG

0x10

HS Timer Control Register

HS_TMR_INTV_LO_REG

0x14

HS Timer Interval Value Low Register

HS_TMR_INTV_HI_REG

0x18

HS Timer Interval Value High Register

HS_TMR_CURNT_LO_REG

0x1C

HS Timer Current Value Low Register

HS_TMR_CURNT_HI_REG

0x20

HS Timer Current Value High Register

3.9.5. HSTimer Register Description
3.9.5.1. HS Timer IRQ Enable Register (Default Value: 0x00000000)
Offset:0x0
Bit

Register Name: HS_TMR_IRQ_EN_REG
R/W

Default/Hex

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IRQ

System
31:1

/

/

/

0

R/W

0x0

HS_TMR_INT_EN.
High Speed Timer Interrupt Enable.
0: No effect;
1: High Speed Timer Interval Value reached interrupt enable.

3.9.5.2. HS Timer IRQ Status Register (Default Value: 0x00000000)
Offset:0x4

Register Name: HS_TMR_IRQ_STAS_REG

Bit

R/W

Default/Hex

Description

31:1

/

/

/

0

R/W

0x0

HS_TMR_IRQ_PEND.
High Speed Timer IRQ Pending. Set 1 to the bit will clear it.
0: No effect;
1: Pending, High speed timer interval value is reached.

3.9.5.3. HS Timer Control Register (Default Value: 0x00000000)
Offset:0x10

Register Name: HS_TMR_CTRL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

HS_TMR_TEST.
High speed timer test mode. In test mode, the low register should be set
to 0x1, the high register will down counter. The counter needs to bereloaded.
0: normal mode;
1: test mode.

30:8

/

/

/

7

R/W

0x0

HS_TMR_MODE.
High Speed Timer mode.
0: Continuous mode. When interval value reached, the timer will notdisable automatically.
1: Single mode. When interval value reached, the timer will disable
automatically.

6:4

R/W

0x0

HS_TMR_CLK
Select the pre-scale of the high speed timer clock sources.
000: /1
001: /2
010: /4
011: /8
100: /16
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110: /
111: /
3:2

/

/

/

1

R/W

0x0

HS_TMR_RELOAD.
High Speed Timer Reload.
0: No effect
1: Reload High Speed Timer Interval Value.

0

R/W

0x0

HS_TMR_EN.
High Speed Timer Enable.
0: Stop/Pause
1: Start.
If the timer is started, it will reload the interval value to internal register,and the current counter will count from interval value to 0.
If the current counter does not reach the zero, the timer enable bit is set
to “0”, the current value counter will pause. At least wait for 2 cycles, thestart bit can be set to 1.
In timer pause state, the interval value register can be modified. If thetimer is started again, and the Software hope the current value register todown-count from the new interval value, the reload bit and the enable bit
should be set to 1 at the same time.

3.9.5.4. HS Timer Interval Value Lo Register
Offset:0x14

Register Name: HS_TMR_INTV_LO_REG

Bit

R/W

Default/Hex

Description

31:0

R/W

x

HS_TMR_INTV_VALUE_LO.
High Speed Timer Interval Value [31:0].

3.9.5.5. HS Timer Interval Value Hi Register
Offset:0x18

Register Name: HS_TMR_INTV_HI_REG

Bit

R/W

Default/Hex

Description

31:24

/

/

/

23:0

R/W

x

HS_TMR_INTV_VALUE_HI.
High Speed Timer Interval Value [55:32].

Note:The interval value register is a 56-bit register. When read or write the interval value, the Lo registershould be read or write first. And the Hi register should be written after the Lo register.

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3.9.5.6. HS Timer Current Value Lo Register
Offset:0x1C

Register Name: HS_TMR_CURNT_LO_REG

Bit

R/W

Default/Hex

Description

31:0

R/W

x

HS_TMR_CUR_VALUE_LO.
High Speed Timer Current Value [31:0].

3.9.5.7. HS Timer Current Value Hi Register
Offset:0x20

Register Name: HS_TMR_CURNT_HI_REG

Bit

R/W

Default/Hex

Description

31:24

/

/

/

23:0

R/W

x

HS_TMR_CUR_VALUE_HI.
High Speed Timer Current Value [55:32].

Note1:HSTimer current value is a 56-bit down-counter (from interval value to 0).
Note2:The current value register is a 56-bit register. When read or write the current value, the Lo registershould be read or write first.

3.9.6. Programming Guidelines
Take making a 1us delay using HSTimer for an instance as follow, AHB1CLK will be configurated as 100MHz and
n_mode, Single mode and 2 pre-scale will be selected in this instance.
writel(0x0, HS_TMR_INTV_HI_REG);//Set interval value Hi 0x0
writel(0x32, HS_TMR_INTV_LO_REG);//Set interval value Lo 0x32
writel(0x90, HS_TMR_CTRL_REG);//Select n_mode,2 pre-scale,single mode
writel(readl(HS_TMR_CTRL_REG)|(1<<1), HS_TMR_CTRL_REG);//Set Reload bit
writel(readl(HS_TMR_CTRL_REG)|(1<<0), HS_TMR_CTRL_REG);//Enable HSTimer
While(!(readl(HS_TMR_IRQ_STAS_REG)&1));//Wait for HSTimer to generate pending
Writel(1, HS_TMR_IRQ_STAS_REG);//Clear HSTimer pending

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3.10. PWM
3.10.1. Overview
The output of the PWM is a toggling signal whose frequency and duty cycle can be modulated by its
programmable registers. Each channel has a dedicated internal 16-bit up counter. If the counter reaches thevalue stored in PWM Channel 0 Period Register, it resets. At the beginning of a count period cycle, thePWMOUT is set to active state and count from 0x0.
The PWM includes the following features:Support outputting 2 kinds of waveform: continuous waveform and pulse waveform
0% to 100% adjustable duty cycle
0Hz to 24MHz output frequency

3.10.2. PWM Block Diagram
Entire cycles

Cycle Mode
Active low
Active cycles

Pulse Mode

Active highActive cycles

Figure 3-8. PWM Block Diagram
The PWM divider divides the clock (24MHz) by 1-64 according to the pre-scalar bits in the PWM control
register. The PWM output Frequency can be divided by 65536 at most. In PWM cycle mode, the output will bea square waveform; the frequency is set to the period register. In PWM pulse mode, the output will be apositive pulse or a negative pulse.
In cycle mode PWM outputs continuous waveform and in pulse mode it outputs a pulse waveform. Each PWM
channel has 2 16-bit up counters exiting in corresponding Period Register, whose [31:16] bits indicate one
16-bit up counter for counting entire cycles and [15:0] bits indicate the other 16-bit up counter for counting
active cycles.

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3.10.3. PWM Register List
Module Name

Base Address

PWM

0x01C21400

Register Name

OffsetDescription

PWM_CH_CTRL

0x00

PWM Control Register

PWM_CH0_PERIOD

0x04

PWM Channel 0 Period Register

3.10.4. PWM Register Description
3.10.4.1. PWM Control Register(Default Value: 0x00000000)
Offset:0x0

Register Name: PWM_CTRL_REG

Bit

R/W

Default/Hex

Description

31:29

/

/

/.

28

RO

0x0

PWM0_RDY.
PWM0 period register ready.
0: PWM0 period register is ready to write,
1: PWM0 period register is busy.

27:10

/

/

/

9

R/W

0x0

PWM0_BYPASS.
PWM CH0 bypass enable.
If the bit is set to 1, PWM0’s output is OSC24MHz.
0: disable,
1: enable.

8

R/W

0x0

PWM_CH0_PUL_START.
PWM Channel 0 pulse output start.
0: no effect,
1: output 1 pulse.
The pulse width should be according to the period 0 register[15:0],and
the pulse state should be according to the active state.
After the pulse is finished,the bit will be cleared automatically.

7

R/W

0x0

PWM_CHANNEL0_MODE.
0: cycle mode,
1: pulse mode.

6

R/W

0x0

SCLK_CH0_GATING.
Gating the Special Clock for PWM0(0: mask, 1: pass).

5

R/W

0x0

PWM_CH0_ACT_STA.
PWM Channel 0 Active State.
0: Low Level,

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1: High Level.
4

R/W

0x0

PWM_CH0_EN.
PWM Channel 0 Enable.
0: Disable,
1: Enable.

3:0

R/W

0x0

PWM_CH0_PRESCAL.
PWM Channel 0 Prescalar.
These bits should be setting before the PWM Channel 0 clock gate on.
0000: /120
0001: /180
0010: /240
0011: /360
0100: /480
0101: /
0110: /
0111: /
1000: /12k
1001: /24k
1010: /36k
1011: /48k
1100: /72k
1101: /
1110: /
1111: /1

3.10.4.2. PWM Channel 0 Period Register
Offset:0x4

Register Name: PWM_CH0_PERIOD

Bit

R/W

Default/Hex

Description

31:16

R/W

x

PWM_CH0_ENTIRE_CYS
Number of the entire cycles in the PWM clock.
0 = 1 cycle
1 = 2 cycles……
N = N+1 cycles
If the register need to be modified dynamically, the PCLK should befaster than the PWM CLK (PWM CLK = 24MHz/pre-scale).

15:0

R/W

x

PWM_CH0_ENTIRE_ACT_CYS
Number of the active cycles in the PWM clock.
0 = 0 cycle
1 = 1 cycles……
N = N cycles

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3.11. DMA
3.11.1. Overview
There are 8 DMA channels in the chip. Each DMA channel can generate interrupts. According to different
pending status, the referenced DMA channel generates corresponding interrupt. And, the configuration
information of every DMA channel are storing in the DDR or SRAM. When start a DMA transferring, the DMA
Channel Descriptor Address Register contains the address information in the DDR or SRAM, where has therelevance configuration information of the DMA transferring.

3.11.2. Functionalities Description
3.11.2.1. Block Diagram

DMA
Request DMA
After transferring a half data of a pkg, the pkg half pending bit would set up
Configuration

After transferring all data of pkg, the pkg end pending bit would set up

SourceAddress

After finishing a transmission, the queue end pending bit would set up

Pkg-pend
End-pend

Half-pend

Pkf-pend

Half-pend

Pkg-pend

Half-pend

Pkg-pend

Byte Counter

Link is used to storing next descriptor address or transmission end flag (0xfffff800)

Half-pend

Destination
Address

No
Any
Idle?

Prepare Descriptor Data

CommityParameter
Link

1

2

3

4

Link

Link

Link

0xfffff 800

Descriptor information

Write Descriptor
Address and Start DMA

Pending Status

DMAC obtains
Descriptor information

Half-pend
Transferring Package

Pkg-pend

ResumePause?

YesNo

Link=fffff 800?

End-pend

Transmission Finish

DMA Transfer Progress

Figure 3-9. DMA Block Diagram

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3.11.2.2. DRQ Type and Corresponding Relation
Table 3-1. DMA DRQ Table
Source DRQ Type

Destination DRQ TypePort NO.

Module NamePort NO.

Module NamePort 0SRAM

Port 0SRAM

Port 1SDRAM

Port 1SDRAM

Port 2/

Port 2

OWA_TXPort 3

I2S/PCM_0_RX

Port 3

I2S/PCM_0_TX

Port 4

I2S/PCM_1_RX

Port 4

I2S/PCM_1_TX

Port 5NAND

Port 5NAND

Port 6

UART0_RX

Port 6

UART0_TXPort 7

UART1_RX

Port 7

UART1_TXPort 8

UART2_RX

Port 8

UART2_TXPort 9

UART3_RX

Port 9

UART3_TXPort 10

UART4_RX

Port 10

UART4_TXPort 11/

Port 11/

Port 12/

Port 12/

Port 13/

Port 13/

Port 14/

Port 14/

Port 15

Audio Codec

Port 15

Audio Codec

Port 16/

Port 16/

Port 17

USB OTG_EP1

Port 17

USB OTG_EP1

Port 18

USB OTG_EP2

Port 18

USB OTG_EP2

Port 19

USB OTG_EP3

Port 19

USB OTG_EP3

Port20USB OTG_EP4

Port 20

USB OTG_EP4

Port 21

USB OTG_EP5

Port 21

USB OTG_EP5

Port 22/

Port 22/

Port 23

SPI0_RXPort 23

SPI0_TX

Port 24

SPI1_RXPort 24

SPI1_TX

Port 25

Port 25

Port 26

Port 26

Port 27

Port 27

Port 28

Port 28

Port 29

Port 29

Port 30

Port 30

I2S/PCM_2_TX

3.11.2.3. DMA Descriptor
In this section, the DMA descriptor registers will be introduced in detail.
When starting a DMA transmission, the module data are transferred as packages, which have the link data
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information. And, by reading the DMA Status Register, the status of a DMA channel could be known. Reading
back the DMA Channel Descriptor Address Register, the value is the link data in the transferring package. If
only the value is equal to 0x1ffff800, then it can be regarded as NULL, which means the package is the lastpackage in this DMA transmission. Otherwise, the value means the start address of the next package. AndDMA Channel Descriptor Address Register can be changed during a package transferring.
When transferring the half of a package, the relevant pending bit will be set up automatically, and if thecorresponding interrupt is enabled, DMA generates an interrupt to the system. The similar thing would occur
when transferring a package completely. Meanwhile, if DMA have transferred the last package in the data, therelevant pending bit would be set up, and generates an interrupt if the corresponding interrupt is enabled. The
flow-process diagram is showed in Block Diagram section.
During a DMA transmission, the configuration could be obtained via DMA Channel Configuration Register. And,behind the address of the config register in DDR or SRAM, there are some registers including other informationof a DMA transmission. The structure chart is showed in Block Diagram section. Also, other information of atransferring data can be obtained by reading the DMA Channel Current Source Address Register, DMA
Channel Current Destination Address Register and DMA Channel Byte Counter Left Register. The
configuration must be word-aligning.
The transferring data would be paused when setting up the relevant Pause Register, if coming up emergency.
And the pausing data could be presumable when set 0 to the same bit in Pause Register.

3.11.3. DMA Register List
Module Name

Base Address

DMA

0x01C02000

Register Name

OffsetDescription

DMA_IRQ_EN_REG

0x00

DMA IRQ Enable Register

DMA_IRQ_PEND_REG

0x10

DMA IRQ Pending Register

DMA_SEC_REG

0x20

DMA Security Register

DMA_AUTO_GATE_REG

0x28

DMA Auto Gating Register

DMA_STA_REG

0x30

DMA Status Register

0x100+N*0x40

DMA Channel Enable Register(N=0~7)0x100+N*0x40+0x4

DMA Channel Pause Register(N=0~7)0x100+N*0x40+0x8

DMA Channel Start Address Register(N=0~7)

DMA_CFG_REG

0x100+N*0x40+0xC

DMA Channel Configuration Register(N=0~7)

DMA_CUR_SRC_REG

0x100+N*0x40+0x10

DMA Channel Current Source Register

DMA_EN_REG
DMA_PAU_REG
DMA_DESC_ADDR_REG

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DMA_CUR_DEST_REG
DMA_BCNT_LEFT_REG
DMA_PARA_REG
DMA Mode Register
DMA_FDESC_ADDR_REG
DMA_PKG_NUM_REG

0x100+N*0x40+0x14

DMA Channel Current Destination Register(N=0~7)0x100+N*0x40+0x18

DMA Channel Byte Counter Left Register(N=0~7)0x100+N*0x40+0x1C

DMA Channel Parameter Register(N=0~7)0x100+N*0x40+0x28

DMA_MODE_REG(N=0~7)0x100+N*0x40+0x2C

DMA Formar Descriptor Address Register(N=0~7)0x100+N*0x40+0x30

DMA Package Number Register(N=0~7)3.11.4. DMA Register Description
3.11.4.1. DMA IRQ Enable Register (Default Value: 0x00000000)
Offset: 0x0000

Register Name: DMA_IRQ_EN_REG

Bit

R/W

Default/Hex

Description

31

/

/

/

30

R/W

0x0

DMA7_QUEUE_IRQ_EN
DMA 7 Queue End Transfer Interrupt Enable.
0: Disable, 1: Enable.

29

R/W

0x0

DMA7_PKG_IRQ_EN
DMA 7 Package End Transfer Interrupt Enable.
0: Disable, 1: Enable.

28

R/W

0x0

DMA7_HLAF_IRQ_EN
DMA 7 Half Package Transfer Interrupt Enable.
0: Disable, 1: Enable.

27

/

/

/

26

R/W

0x0

DMA6_QUEUE_IRQ_EN
DMA 6 Queue End Transfer Interrupt Enable.
0: Disable, 1: Enable.

25

R/W

0x0

DMA6_PKG_IRQ_EN
DMA 6 Package End Transfer Interrupt Enable.
0: Disable, 1: Enable.

24

R/W

0x0

DMA6_HLAF_IRQ_EN
DMA 6 Half Package Transfer Interrupt Enable.
0: Disable, 1: Enable.

23

/

/

/

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22

R/W

0x0

DMA5_QUEUE_IRQ_EN
DMA 5 Queue End Transfer Interrupt Enable.
0: Disable, 1: Enable.

21

R/W

0x0

DMA5_PKG_IRQ_EN
DMA 5 Package End Transfer Interrupt Enable.
0: Disable, 1: Enable.

20

R/W

0x0

DMA5_HLAF_IRQ_EN
DMA 5 Half package Transfer Interrupt Enable.
0: Disable, 1: Enable.

19

/

/

/

18

R/W

0x0

DMA4_QUEUE_IRQ_EN
DMA 4 Queue End Transfer Interrupt Enable.
0: Disable, 1: Enable.

17

R/W

0x0

DMA4_PKG_IRQ_EN
DMA 4 Package End Transfer Interrupt Enable.
0: Disable, 1: Enable.

16

R/W

0x0

DMA4_HLAF_IRQ_EN
DMA 4 Half Package Transfer Interrupt Enable.
0: Disable, 1: Enable.

15

/

/

/

14

R/W

0x0

DMA3_QUEUE_IRQ_EN
DMA 3 Queue End Transfer Interrupt Enable.
0: Disable, 1: Enable.

13

R/W

0x0

DMA3_PKG_IRQ_EN
DMA 3 Package End Transfer Interrupt Enable.
0: Disable, 1: Enable.

12

R/W

0x0

DMA3_HLAF_IRQ_EN
DMA 3 Half Package Transfer Interrupt Enable.
0: Disable, 1: Enable.

11

/

/

/

10

R/W

0x0

DMA2_QUEUE_IRQ_EN
DMA 2 Queue End Transfer Interrupt Enable.
0: Disable, 1: Enable.

9

R/W

0x0

DMA2_PKG_IRQ_EN
DMA 2 Package End Transfer Interrupt Enable.
0: Disable, 1: Enable.

8

R/W

0x0

DMA2_HLAF_IRQ_EN
DMA 2 Half Package Transfer Interrupt Enable.
0: Disable, 1: Enable.

7

/

/

/

6

R/W

0x0

DMA1_QUEUE_IRQ_EN
DMA 1 Queue End Transfer Interrupt Enable.
0: Disable, 1: Enable.

5

R/W

0x0

DMA1_PKG_IRQ_EN

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DMA 1 Package End Transfer Interrupt Enable.
0: Disable, 1: Enable.
4

R/W

0x0

DMA1_HLAF_IRQ_EN
DMA 1 Half Package Transfer Interrupt Enable.
0: Disable, 1: Enable.

3

/

/

/

2

R/W

0x0

DMA0_QUEUE_IRQ_EN
DMA 0 Queue End Transfer Interrupt Enable.
0: Disable, 1: Enable.

1

R/W

0x0

DMA0_PKG_IRQ_EN
DMA 0 Package End Transfer Interrupt Enable.
0: Disable, 1: Enable.

0

R/W

0x0

DMA0_HLAF_IRQ_EN
DMA 0 Half Package Transfer Interrupt Enable.
0: Disable, 1: Enable

3.11.4.2. DMA IRQ Pending Status Register0 (Default Value: 0x00000000)
Offset:0x10

Register Name: DMA_IRQ_PEND_REG0

Bit

R/W

Default/Hex

Description

31

/

/

/

30

R/W

0x0

DMA7_QUEUE_IRQ_PEND.
DMA 7 Queue End Transfer Interrupt Pending. Set 1 to the bit will clear
it.
0: No effect, 1: Pending.

29

R/W

0x0

DMA7_PKG_IRQ_ PENDDMA 7 Package End Transfer Interrupt Pending. Set 1 to the bit will clear
it.
0: No effect, 1: Pending.

28

R/W

0x0

DMA7_HLAF_IRQ_PEND.
DMA 7 Half Package Transfer Interrupt Pending. Set 1 to the bit will clear
it.
0: No effect, 1: Pending.

27

/

/

/

26

R/W

0x0

DMA6_QUEUE_IRQ_PEND.
DMA 6 Queue End Transfer Interrupt Pending. Set 1 to the bit will clear
it.
0: No effect, 1: Pending.

25

R/W

0x0

DMA6_PKG_IRQ_ PENDDMA 6 Package End Transfer Interrupt Pending. Set 1 to the bit will clear
it.
0: No effect, 1: Pending.

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24

R/W

0x0

DMA6_HLAF_IRQ_PEND.
DMA 6 Half Package Transfer Interrupt Pending. Set 1 to the bit will clear
it.
0: No effect, 1: Pending.

23

/

/

/

22

R/W

0x0

DMA5_QUEUE_IRQ_PEND.
DMA 5 Queue End Transfer Interrupt Pending. Set 1 to the bit will clear
it.
0: No effect, 1: Pending.

21

R/W

0x0

DMA5_PKG_IRQ_ PEND
DMA 5 Package End Transfer Interrupt Pending. Set 1 to the bit will clear
it.
0: No effect, 1: Pending.

20

R/W

0x0

DMA5_HLAF_IRQ_PEND.
DMA 5 Half Package Transfer Interrupt Pending. Set 1 to the bit will clear
it.
0: No effect, 1: Pending.

19

/

/

/

18

R/W

0x0

DMA4_QUEUE_IRQ_PEND.
DMA 4 Queue End Transfer Interrupt Pending. Set 1 to the bit will clear
it.
0: No effect, 1: Pending.

17

R/W

0x0

DMA4_PKG_IRQ_ PENDDMA 4 Package End Transfer Interrupt Pending. Set 1 to the bit will clear
it.
0: No effect, 1: Pending.

16

R/W

0x0

DMA4_HLAF_IRQ_PEND.
DMA 4 Half Package Transfer Interrupt Pending. Set 1 to the bit will clear
it.
0: No effect, 1: Pending.

15

/

/

/

14

R/W

0x0

DMA3_QUEUE_IRQ_PEND.
DMA 3 Queue End Transfer Interrupt Pending. Set 1 to the bit will clear
it.
0: No effect, 1: Pending.

13

R/W

0x0

DMA3_PKG_IRQ_ PENDDMA 3 Package End Transfer Interrupt Pending. Set 1 to the bit will clear
it.
0: No effect, 1: Pending.

12

R/W

0x0

DMA3_HLAF_IRQ_PEND.
DMA 3 Half Package Transfer Interrupt Pending. Set 1 to the bit will clear
it.
0: No effect, 1: Pending.

11

/

/

/

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10

R/W

0x0

DMA2_QUEUE_IRQ_PEND.
DMA 2 Queue End Transfer Interrupt Pending. Set 1 to the bit will clear
it.
0: No effect, 1: Pending.

9

R/W

0x0

DMA2_PKG_IRQ_ PENDDMA 2 Package End Transfer Interrupt Pending. Set 1 to the bit will clear
it.
0: No effect, 1: Pending.

8

R/W

0x0

DMA2_HLAF_IRQ_PEND.
DMA 2 Half Package Transfer Interrupt Pending. Set 1 to the bit will clear
it.
0: No effect, 1: Pending.

7

/

/

/

6

R/W

0x0

DMA1_QUEUE_IRQ_PEND.
DMA 1 Queue End Transfer Interrupt Pending. Set 1 to the bit will clear
it.
0: No effect, 1: Pending.

5

R/W

0x0

DMA1_PKG_IRQ_ PEND
DMA 1 Package End Transfer Interrupt Pending. Set 1 to the bit will clear
it.
0: No effect, 1: Pending.

4

R/W

0x0

DMA1_HLAF_IRQ_PEND.
DMA 1 Half Package Transfer Interrupt Pending. Set 1 to the bit will clear
it.
0: No effect, 1: Pending.

3

/

/

/

2

R/W

0x0

DMA0_QUEUE_IRQ_PEND.
DMA 0 Queue End Transfer Interrupt Pending. Set 1 to the bit will clear
it.
0: No effect, 1: Pending.

1

R/W

0x0

DMA0_PKG_IRQ_ PEND
DMA 0 Package End Transfer Interrupt Pending. Set 1 to the bit will clear
it.
0: No effect, 1: Pending.

0

R/W

0x0

DMA0_HLAF_IRQ_PEND.
DMA 0 Half Package Transfer Interrupt Pending. Set 1 to the bit will clear
it.
0: No effect, 1: Pending.

3.11.4.3. DMA Security Register (Default Value: 0x00000000)
Offset:0x20
Bit

R/W

Register Name: DMA_SECURE_REG
Default/Hex

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31:8

/

/

/

7

R/W

0x0

DMA7_SECDMA channel 7 security.
0: Secure,
1: Non-secure.

6

R/W

0x0

DMA6_SECDMA channel 6 security.
0: Secure,
1: Non-secure.

5

R/W

0x0

DMA5_SECDMA channel 5 security.
0: Secure,
1: Non-secure.

4

R/W

0x0

DMA4_SECURE.
Indicating DMA 4 security.
0: Secure,
1: Non-secure.

3

R/W

0x0

DMA3_SECURE.
Indicating DMA 3 security.
0: Secure,
1: Non-secure.

2

R/W

0x0

DMA2_SECURE.
Indicating DMA 2 security.
0: Secure,
1: Non-secure.

1

R/W

0x0

DMA1_SECURE.
Indicating DMA 1 security.
0: Secure,
1: Non-secure.

0

R/W

0x0

DMA0_SECURE.
Indicating DMA 0 security.
0: Secure,
1: Non-secure.

3.11.4.4. DMA Auto Gating Register (Default Value: 0x00000000)
Offset:0x28

Register Name: DMA_AUTO_GATE_REG

Bit

R/W

Default/Hex

Description

31:3

/

/

/

2

R/W

0x0

DMA_MCLK_CIRCUIT.
DMA MCLK interface circuit auto gating bit.
0: Auto gating enable
1: Auto gating disable.

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1

R/W

0x0

DMA_COMMON_CIRCUIT.
DMA common circuit auto gating bit.
0: Auto gating enable
1: Auto gating disable.

0

R/W

0x0

DMA_CHAN_CIRCUIT.
DMA channel circuit auto gating bit.
0: Auto gating enable
1: Auto gating disable.

3.11.4.5. DMA Status Register (Default Value: 0x00000000)
Offset:0x30

Register Name: DMA_STA_REG

Bit

R/W

Default/Hex

Description

31

/

/

/

30

RO

0x0

MBUS FIFO Status
0:Empty
1:Not Empty

29:8

/

/

/

7

RO

0x0

DMA7_STATUSDMA Channel 7 Status.
0: Idle1: Busy

6

RO

0x0

DMA6_STATUSDMA Channel 6 Status.
0: Idle1: Busy

5

RO

0x0

DMA5_STATUSDMA Channel 5 Status.
0: Idle1: Busy

4

RO

0x0

DMA4_STATUSDMA Channel 4 Status.
0: Idle1: Busy.

3

RO

0x0

DMA3_STATUSDMA Channel 3 Status.
0: Idle1: Busy.

2

RO

0x0

DMA2_STATUSDMA Channel 2 Status.
0: Idle,1: Busy.

1

RO

0x0

DMA1_STATUS

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DMA Channel 1 Status.
0: Idle,1: Busy.
0

RO

0x0

DMA0_STATUSDMA Channel 0 Status.
0: Idle,1: Busy.

3.11.4.6. DMA Channel Enable Register (Default Value: 0x00000000)
Offset: 0x100+N*0x40+0x0(N=0~7)

Register Name: DMA_EN_REG

Bit

R/W

Default/Hex

Description

31:1

/

/

/

0

R/W

0x0

DMA_EN.
DMA Channel Enable
0: Disable
1: Enable.

3.11.4.7. DMA Channel Pause Register (Default Value: 0x00000000)
Offset: 0x100+N*0x40+0x4(N=0~7)

Register Name: DMA_PAU_REG

Bit

R/W

Default/Hex

Description

31:1

/

/

/

0

R/W

0x0

DMA_PAUSE.
Pausing DMA Channel Transfer Data.
0: Resume Transferring,
1: Pause Transferring.

3.11.4.8. DMA Channel Descriptor Address Register (Default Value: 0x00000000)
Offset: 0x100+N*0x40+0x8(N=0~7)

Register Name: DMA_DESC_ADDR_REG

Bit

R/W

Default/Hex

Description

31:1

R/W

0x0

DMA_DESC_ADDRDMA Channel Descriptor Address.
The Descriptor Address must be half-word aligned before DMA enable.

0

R/W

0x0

DMA_DESCPT_ADDR_HIGH.
This bit would be used to storing [32] bits of the descriptor address, if it
is necessary. Otherwise, it should be 0.

Note:After DMA channel completed all data transmission,the final value of the register is 0xFFFFF800.

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3.11.4.9. DMA Channel Configuration Register (Default Value: 0x00000000)
Offset: 0x100+N*0x40+0xC(N=0~7)

Register Name: DMA_CFG_REG

Bit

R/W

Default/Hex

Description

31:27

/

/

/

26:25

RO

0x0

DMA_DEST_DATA_WIDTH.
DMA Destination Data Width.
00: 8-bit
01: 16-bit
10: 32-bit
11: 64-bit

24

/

/

/

23:22

RO

0x0

DMA_DEST_BLOCK_SIZE.
DMA Destination Block Size.
00: 1
01: 4
10: 8
11: 16

21

RO

0x0

DMA_ADDR_MODE.
DMA Destination Address Mode
0: Linear Mode
1: IO Mode

20:16

RO

0x0

DMA_DEST_DRQ_TYPE.
DMA Destination DRQ TypeThe details in DRQ Type and Port Corresponding Relation.

15:11

/

/

/

10:9

RO

0x0

DMA_SRC_DATA_WIDTH.
DMA Source Data Width.
00: 8-bit
01: 16-bit
10: 32-bit
11: 64-bit

8

/

/

/

7:6

RO

0x0

DMA_SRC_BLOCK_SIZE.
DMA Source Block Size.
00: 1
01: 4
10: 8
11: 165

RO

0x0

DMA_SRC_ADDR_MODE.
DMA Source Address Mode
0: Linear Mode

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1: IO Mode
4:0

RO

3.11.4.10.

0x0

DMA_SRC_DRQ_TYPE.
DMA Source DRQ TypeThe details in DRQ Type and Port Corresponding Relation.

DMA Channel Current Source Address Register (Default Value: 0x00000000)

Offset: 0x100+N*0x40+0x10(N=0~7)

Register Name: DMA_CUR_SRC_REG

Bit

R/W

Default/Hex

Description

31:0

RO

0x0

DMA_CUR_SRC.
DMA Channel Current Source Address, read only.

3.11.4.11.

DMA Channel Current Destination Address Register (Default Value: 0x00000000)

Offset: 0x100+N*0x40+0x14(N=0~7)

Register Name: DMA_CUR_DEST_REG

Bit

R/W

Default/Hex

Description

31:0

RO

0x0

DMA_CUR_DEST.
DMA Channel Current Destination Address, read only.

3.11.4.12.

DMA Channel Byte Counter Left Register (Default Value: 0x00000000)

Offset: 0x100+N*0x40+0x18(N=0~7)

Register Name: DMA_BCNT_LEFT_REG

Bit

R/W

Default/Hex

Description

31:25

/

/

/

24:0

RO

0x0

DMA_BCNT_LEFT.
DMA Channel Byte Counter Left, read only.

3.11.4.13.

DMA Channel Parameter Register (Default Value: 0x00000000)

Offset: 0x100+N*0x40+0x1C(N=0~7)

Register Name: DMA_PARA_REG

Bit

R/W

Default/Hex

Description

31:19

/

/

/

18

RO

0x0

DMA_DST_HBIT_ADDR.

17

/

/

/

16

RO

0x0

DMA_SRC_HBIT_ADDR.

15:8

/

/

/

7:0

RO

0x0

WAIT_CLK_CYCLE.
Wait clock cycle.

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3.11.4.14.

DMA Mode Register (Default Value: 0x00000000)

Offset: 0x100+N*0x40+0x28(N=0~7)

Register Name: DMA_MODE_REG

Bit

R/W

Default/Hex

Description

31:4

/

/

/

3

R/W

0x0

DMA_DST_MODE.
0: Wait mode.
1: Handshake mode.

2

R/W

0x0

DMA_SRC_MODE.
0: Wait mode.
1: Handshake mode.

1:0

/

/

/

3.11.4.15.

DMA Former Descriptor Address Register (Default Value: 0x00000000)

Offset: 0x100+N*0x40+0x2C(N=0~7)

Register Name: DMA_FDESC_ADDR_REG

Bit

R/W

Default/Hex

Description

31:0

RO

0x0

DMA_FDESC_ADDR.
This register is used to storing the former value of DMA Channel
Descriptor Address Register.

3.11.4.16.

DMA Package Number Register (Default Value: 0x00000000)

Offset: 0x100+N*0x40+0x30(N=0~7)

Register Name: DMA_PKG_NUM_REG

Bit

R/W

Default/Hex

Description

31:0

RO

0x0

DMA_PKG_NUM.
This register will record the number of packages which has been
completed in one transmission.

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3.12. GIC
For details about GIC, please refer to the GIC PL400 technical reference manual and ARM GIC Architecture
Specification V2.0.

3.12.1. Interrupt Source
Interrupt Source

SRC

VectorDescription

SGI 0

0

0x0000

SGI 0 interrupt

SGI 1

1

0x0004

SGI 1 interrupt

SGI 2

2

0x0008

SGI 2 interrupt

SGI 3

3

0x000C

SGI 3 interrupt

SGI 4

4

0x0010

SGI 4 interrupt

SGI 5

5

0x0014

SGI 5 interrupt

SGI 6

6

0x0018

SGI 6 interrupt

SGI 7

7

0x001CSGI 7 interrupt

SGI 8

8

0x0020

SGI 8 interrupt

SGI 9

9

0x0024

SGI 9 interrupt

SGI 10100x0028

SGI 10 interrupt

SGI 11

110x002CSGI 11 interrupt

SGI 12120x0030

SGI 12 interrupt

SGI 13130x0034

SGI 13 interrupt

SGI 14140x0038

SGI 14 interrupt

SGI 15150x003CSGI 15 interrupt

PPI 0

16

0x0040

PPI 0 interrupt

PPI 1

17

0x0044

PPI 1 interrupt

PPI 2

18

0x0048

PPI 2 interrupt

PPI 3

19

0x004CPPI 3 interrupt

PPI 4

20

0x0050

PPI 4 interrupt

PPI 5

21

0x0054

PPI 5 interrupt

PPI 6

22

0x0058

PPI 6 interrupt

PPI 7

23

0x005CPPI 7 interrupt

PPI 8

24

0x0060

PPI 8 interrupt

PPI 9

25

0x0064

PPI 9 interrupt

PPI 1026

0x0068

PPI 10 interrupt

PPI 1127

0x006CPPI 11 interrupt

PPI 1228

0x0070

PPI 12 interrupt

PPI 1329

0x0074

PPI 13 interrupt

PPI 1430

0x0078

PPI 14 interrupt

PPI 1531

0x007CPPI 15 interrupt

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UART 032

0x0080UART 0 interrupt

UART 133

0x0084

UART 1 interrupt

UART 234

0x0088UART 2 interrupt

UART 335

0x008CUART 3 interrupt

UART 436

0x0090UART 4 interrupt

37

0x0094TWI 0

380x0098

TWI 0 interrupt

TWI 1

39

0x009CTWI 1 interrupt

TWI 2

40

0x00A0

TWI 2 interrupt

41

0x00A442

0x00A8PB_EINT

430x00ACPB_EINT interrupt

OWA

44

0x00B0OWA interrupt

I2S/PCM-045

0x00B4

I2S/PCM-0 interrupt

I2S/PCM-1

46

0x00B8I2S/PCM-1 interrupt

I2S/PCM-2

47

0x00BCI2S/PCM-2 interrupt

48

0x00C0PG_EINT49

0x00C4

PG_EINT interrupt

Timer 050

0x00C8Timer 0 interrupt

Timer 151

0x00CC

Timer 1 interrupt

52

0x00D053

0x00D454

0x00D855

0x00DC56

0x00E057

0x00E458

0x00E859

0x00EC

AC_DET60

0x00F0

Audio Codec earphone detect interrupt

Audio Codec

61

0x00F4

Audio Codec interrupt

KEYADC

62

0x00F8KEYADC interrupt

Thermal Sensor

63

0x00FC

Thermal Sensor interrupt

External NMI

64

0x100

External Non-Mask Interrupt

R_timer 0

65

0x104

R_timer 0 interrupt

R_timer 1

66

0x108

R_timer 1 interrupt

67

0x010CR_watchdog

68

0x0110

R_watchdog interrupt

R_CIR_RX

69

0x00E8

R_CIR_RX interrupt

R_UART70

0x0118

R_UART interrupt

R_RSB

71

0x011CR_RSB interrupt

R_Alarm 072

0x0120

R_Alarm 0 interrupt

R_Alarm 1

73

0x0124

R_Alarm 1 interrupt

R_timer 2

74

0x0128R_timer 2 interrupt

PH_EINT

Watchdog

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Watchdog interrupt

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R_timer 3

750x012C

R_timer 3 interrupt

R_TWI

76

0x0130

R_TWI interrupt

R_PL_EINT

77

0x0134

R_PL_EINT interrupt

R_TWD

78

0x0138

R_TWD interrupt

79

0x013C80

0x0140MSGBOX

81

0x0144MSGBOX interrupt

DMA

82

0x0148DMA channel interrupt

HS Timer

83

0x014CHS Timer interrupt

84

0x015085

0x015486

0x015887

0x015C88

0x016089

0x0164900x016891

0x016C

SD/MMC 092

0x0170SD/MMC Host Controller 0 interrupt

SD/MMC 193

0x0174SD/MMC Host Controller 1 interrupt

SD/MMC 294

0x0178

SD/MMC Host Controller 2 interrupt

95

0x017C96

0x0180SPI 097

0x0184

SPI 0 interrupt

SPI 1

98

0x0188

SPI 1 interrupt

99

0x018C100

0x0190

DRAM_MDFS

101

0x0194

DRAM MDFS interrupt

NAND

102

0x0198

NAND Flash Controller interrupt

USB-OTG103

0x019C

USB-OTG interrupt

USB-OTG-EHCI

104

0x01A0USB-OTG-EHCI interrupt

USB-OTG-OHCI

105

0x01A4USB-OTG-OHCI interrupt

USB-EHCI0106

0x01A8USB-EHCI0 interrupt

USB-OHCI0107

0x01AC

USB-OHCI0 interrupt

108

0x01B0109

0x01B4110

0x01B8111

0x01BC

CE0112

0x01C0CE interrupt

TS

113

0x01C4TS interrupt

EMAC

114

0x01C8EMAC interrupt

SCR

115

0x01CCSCR interrupt

CSI

116

0x01D0

CSI interrupt

CSI_CCI

117

0x01D4

CSI_CCI interrupt

SMC
VE

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SMC interrupt
VE interrupt

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TCON0

118

0x01D8

TCON0 interrupt

TCON1

119

0x01DCTCON1 interrupt

HDMI

120

0x01E0

HDMI interrupt

MIPI DSI

121

0x01E4

MIPI DSI interrupt

122

0x01E8123

0x01EC124

0x01F0DIT

1250x01F4De-interlace interrupt

CE1

126

0x01F8CE1 interrupt

DE

127

0x01FCDE interrupt

ROT

128

0x0200

DE_RORATE interrupt

GPU-GP

129

0x0204

GPU-GP interrupt

GPU-GPMMU

130

0x0208GPU-GPMMU interrupt

GPU-PP0131

0x020C

GPU-PP0 interrupt

GPU-PP0MMU

132

0x0210GPU-PPMMU0 interrupt

GPU-PMU

133

0x0214

GPU-PMU interrupt

GPU-PP1

134

0x0218

GPU-PP1 interrupt

GPU-PPMMU1

135

0x021C

GPU-PPMMU1 interrupt

136

0x0220137

0x0224138

0x0228139

0x022C

CTI0

1400x0230

CTI0 interrupt

CTI1

141

0x0234

CTI1 interrupt

CTI2

142

0x0238

CTI2 interrupt

CTI3

143

0x023CCTI3 interrupt

COMMTX0144

0x0240

COMMTX0 interrupt

COMMTX1

145

0x0244

COMMTX1 interrupt

COMMTX2

146

0x0248COMMTX2 interrupt

COMMTX3

147

0x024CCOMMTX3 interrupt

COMMRX0148

0x0250COMMRX0 interrupt

COMMRX1

149

0x0254

COMMRX1 interrupt

COMMRX2

150

0x0258COMMRX2 interrupt

COMMRX3

151

0x025CCOMMRX3 interrupt

PMU0

152

0x0260

PMU0 interrupt

PMU1

153

0x0264

PMU1 interrupt

PMU2

154

0x0268PMU2 interrupt

PMU3

155

0x026CPMU3 interrupt

AXI_ERROR

156

0x0270AXI_ERROR interrupt

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3.13. Message Box
3.13.1. Overview
Message Box provides an MSGBox-interrupt mechanism for on-chip processors intercommunication.It allows aprocessor transmit messages to the other one or receive messages from the other through a series of Message
Queues,each of which is a four 32-bits depth FIFO.An intercommunication channel could be established byconfiguring Message Box registers and it works under MSGBox-interrupt mechanism.
The Message Box includes the following features:•
Two users for Message Box instance(User0 for CPUS and User1 for CPUX)•
Eight Message Queues for the MSGBox instance•
Each of Queues has four 32-bits depth FIFO for establishing intercommunication channel•
Each of Queues could be configured as transmitter or receiver for user•
Message reception and queue-not-full notification interrupt mechanism

3.13.2. Functionalities Description

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3.13.2.1. Typical Applications

Typical Application Flow Chart
START

Set a MSG Queue as aTransmitter or a receiver?

As a transmitter

As a receiver

Enable the
RECEPTION IRQ
N

A new message hasreceived?
Check the MSG status or
FIFO status if it is not full?
Y
N

Read the MSG REG
to fetch the message

Y

IF the Message QueueFIFO is empty?
Write a message to
the MSG REG

NYClear the Reception
IRQ Pending

FINISHFINISH

Figure 3-10. Message Box Typical Application Chart

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3.13.2.2. Functional Block Diagram

MSGBoxMSGBOX_CTRL_REG0
MSGBOX_CTRL_REG1
For user0

MSGBOX_IRQ_EN_REG_0
MSGBOX_IRQ_STATUS_REG_0
For user1

MSGBOX_IRQ_EN_REG_1
MSGBOX_IRQ_STATUS_REG_1

USER0

USER1

MSGBox Message Queue m (m: from 0 to 7)
MSGBOX_FIFO_STATUS_REG_M

MSGBOX_MSG_STATUS_REG_M
Four Message FIFO

MSGBOX_MSG_REG_M

Figure 3-11. Message Box Functional Block Diagram
Message Box supports a set of registers for a processor to establish an interconnection channel with theothers.The processor determines message queue numbers for interconnection and the used queues to thetransmitter or receiver for itself and the interconnectible one.Every queue has a MSGBox FIFO Status Registerfor processor to check out queue FIFO full status and a MSGBox Message Status Register for processor tocheck out message numbers in queue FIFO.Otherwise,every queue has a corresponding IRQ status bit and acorresponding IRQ enable bit,which used for requesting interrupt.

3.13.3. Operation Principle
3.13.3.1. Message Queue Assignment
To transmit messages from a user to the other user through any Message Queue, set the corresponding bit in
the MSGBox Control Register 0 or MSGBox Control Register 1 register.
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When a 32-bit message is written to the MSGBOX_MSG_REG_M register, the message is appended into the
FIFO queue. This queue holds 4 messages. If the queue is full, the message is discarded. The receiver user
could read the MSGBox Message Queue Register (m is the message queue number, where m=0 to 7) toretrieve a message from the corresponding Message Queue FIFO.
It is recommended that register polling be used for a user to send a message:•
Set a Message Queue as a transmitter (in the MSGBox Control Register 0 /MSGBox Control Register 1).
•
Check the FIFO status or the message status (in the MSGBox FIFO Status Register m or MSGBox
Message Status Register m).
•
Write the message to the corresponding MSGBox Message Queue Register, if space is available.
The transmit interrupt might be used when the initial MSGBox status indicates that the Message Queue is full.
In this case, the sender can enable the corresponding MSGBox IRQ Enable Register u interrupt for the user.
This allows the user to be notified by interrupt when the message queue is not full.

3.13.3.2. Interrupt request
An interrupt request allows the user of the MSGBox to be notified when a new message is received or whenthe message queue is not full.
An event can generate an interrupt request when enable the corresponding bit in the MSGBox IRQ Enable
Register u (u is the user number, where u=0 or 1) register. Events are reported in the appropriate MSGBox IRQ
Status Register u register.
An event stops generating interrupt requests when disable the corresponding bit in the MSGBox IRQ Enable
Register u register.
In case of the MSGBox IRQ Status Register u, the event is reported in the corresponding bit even if theinterrupt request generation is disabled for this event.

3.13.4. Message Box Register List
Module Name

Base Address

MSGBOX

0x01C17000

Register Name

OffsetDescription

MSGBOX_CTRL_REG0

0x0000

Message Queue Attribute Control Register 0

MSGBOX_CTRL_REG1

0x0004

Message Queue Attribute Control Register 1

MSGBOXU_IRQ_EN_REG

0x0040+N*0x20

IRQ Enable For User N(N=0,1)

MSGBOXU_IRQ_STATUS_REG

0x0050+N*0x20

IRQ Status For User N(N=0,1)

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MSGBOXM_FIFO_STATUS_REG

0x0100+N*0x4

FIFO Status For Message Queue N(N = 0~7)

MSGBOXM_MSG_STATUS_REG

0x0140+N*0x4

Message Status For Message Queue N(N=0~7)

MSGBOXM_MSG_REG

0x0180+N*0x4

Message Register For Message Queue N(N=0~7)

3.13.5. Message Box Register Description
3.13.5.1. MSGBox Control Register 0(Default Value: 0x10101010)
Offset: 0x00

Register Name: MSGBOX_CTRL_REG0

Bit

R/W

Default/Hex

Description

31:29

/

/

/

28

R/W

0x1

TRANSMIT_MQ3.
Message Queue 3 is a Transmitter of user u.
0: user0
1: user1

27:25

/

/

/

24

R/W

0x0

RECEPTION_MQ3.
Message Queue 3 is a Receiver of user u.
0: user0
1: user1

23:21

/

/

/

20

R/W

0x1

TRANSMIT_MQ2.
Message Queue 2 is a Transmitter of user u.
0: user0
1: user1

19:17

/

/

/

16

R/W

0x0

RECEPTION_MQ2.
Message Queue 2 is a Receiver of user u.
0: user0
1: user1

15:13

/

/

/

12

R/W

0x1

TRANSMIT_MQ1
Message Queue 1 is a Transmitter of user u.
0: user0
1: user1

11:9

/

/

/

8

R/W

0x0

RECEPTION_MQ1.
Message Queue 1 is a Receiver of user u.
0: user0
1: user1

7:5

/

/

/

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4

R/W

0x1

TRANSMIT_MQ0.
Message Queue 0 is a Transmitter of user u.
0: user0
1: user1

3:1

/

/

/

0

R/W

0x0

RECEPTION_MQ0.
Message Queue 0 is a Receiver of user u.
0: user0
1: user1

3.13.5.2. MSGBox Control Register 1(Default Value: 0x10101010)
Offset: 0x04

Register Name: MSGBOX_CTRL_REG1

Bit

R/W

Default/Hex

Description

31:29

/

/

/

28

R/W

0x1

TRANSMIT_MQ7.
Message Queue 7 is a Transmitter of user u.
0: user0
1: user1

27:25

/

/

/

24

R/W

0x0

RECEPTION_MQ7.
Message Queue 7 is a Receiver of user u.
0: user0
1: user1

23:21

/

/

/

20

R/W

0x1

TRANSMIT_MQ6.
Message Queue 6 is a Transmitter of user u.
0: user0
1: user1

19:17

/

/

/

16

R/W

0x0

RECEPTION_MQ6.
Message Queue 6 is a Receiver of user u.
0: user0
1: user1

15:13

/

/

/

12

R/W

0x1

TRANSMIT_MQ5
Message Queue 5 is a Transmitter of user u.
0: user0
1: user1

11:9

/

/

/

8

R/W

0x0

RECEPTION_MQ5.
Message Queue 5 is a Receiver of user u.

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0: user0
1: user1
7:5

/

/

/

4

R/W

0x1

TRANSMIT_MQ4.
Message Queue 4 is a Transmitter of user u.
0: user0
1: user1

3:1

/

/

/

0

R/W

0x0

RECEPTION_MQ4.
Message Queue 4 is a Receiver of user u.
0: user0
1: user1

3.13.5.3. MSGBox IRQ Enable Register u(Default Value: 0x00000000)
Offset:0x40+N*0x20 (N=0,1)

Register Name: MSGBOXU_IRQ_EN_REG

Bit

R/W

Default/Hex

Description

31:16

/

/

/

15

R/W

0x0

TRANSMIT_MQ7_IRQ_EN.
0: Disable
1: Enable (It will notify user u by interrupt when Message Queue 7 is not
full.)

14

R/W

0x0

RECEPTION_MQ7_IRQ_EN.
0: Disable
1: Enable (It will notify user u by interrupt when Message Queue 7 hasreceived a new message.)

13

R/W

0x0

TRANSMIT_MQ6_IRQ_EN.
0: Disable
1: Enable (It will Notify user u by interrupt when Message Queue 6 is not
full.)

12

R/W

0x0

RECEPTION_MQ6_IRQ_EN.
0: Disable
1: Enable (It will notify user u by interrupt when Message Queue 6 hasreceived a new message.)

11

R/W

0x0

TRANSMIT_MQ5_IRQ_EN.
0: Disable
1: Enable (It will notify user u by interrupt when Message Queue 5 is not
full.)

10

R/W

0x0

RECEPTION_MQ5_IRQ_EN.
0: Disable
1: Enable (It will notify user u by interrupt when Message Queue 5 hasreceived a new message.)

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9

R/W

0x0

TRANSMIT_MQ4_IRQ_EN.
0: Disable
1: Enable (It will notify user u by interrupt when Message Queue 4 is not
full.)

8

R/W

0x0

RECEPTION_MQ4_IRQ_EN.
0: Disable
1: Enable (It will notify user u by interrupt when Message Queue 4 hasreceived a new message.)

7

R/W

0x0

TRANSMIT_MQ3_IRQ_EN.
0: Disable
1: Enable (It will notify user u by interrupt when Message Queue 3 is not
full.)

6

R/W

0x0

RECEPTION_MQ3_IRQ_EN.
0: Disable
1: Enable (It will notify user u by interrupt when Message Queue 3 hasreceived a new message.)

5

R/W

0x0

TRANSMIT_MQ2_IRQ_EN.
0: Disable
1: Enable (It will notify user u by interrupt when Message Queue 2 is not
full.)

4

R/W

0x0

RECEPTION_MQ2_IRQ_EN.
0: Disable
1: Enable (It will notify user u by interrupt when
received a new message.)

Message Queue 2 has

3

R/W

0x0

TRANSMIT_MQ1_IRQ_EN.
0: Disable
1: Enable (It will notify user u by interrupt when Message Queue 1 is not
full.)

2

R/W

0x0

RECEPTION_MQ1_IRQ_EN.
0: Disable
1: Enable (It will notify user u by interrupt when Message Queue 1 hasreceived a new message.)

1

R/W

0x0

TRANSMIT_MQ0_IRQ_EN.
0: Disable
1: Enable (It will notify user u by interrupt when Message Queue 0 is not
full.)

0

R/W

0x0

RECEPTION_MQ0_IRQ_EN.
0: Disable
1: Enable (It will notify user u by interrupt when Message Queue 0 hasreceived a new message.)

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3.13.5.4. MSGBox IRQ Status Register u(Default Value: 0x0000AAAA)
Offset:0x50+N*0x20 (N=0,1)

Register Name: MSGBOXU_IRQ_STATUS_REG

Bit

R/W

Default/Hex

Description

31:16

/

/

/

15

R/W

0x1

TRANSMIT_MQ7_IRQ_PEND.
0: No effect,
1: Pending. This bit will be pending for user u when Message Queue 7 is
not full. Set one to this bit will clear it.

14

R/W

0x0

RECEPTION_MQ7_IRQ_PEND.
0: No effect,
1: Pending. This bit will be pending for user u when Message Queue 7 hasreceived a new message. Set one to this bit will clear it.

13

R/W

0x1

TRANSMIT_MQ6_IRQ_PEND.
0: No effect,
1: Pending. This bit will be pending for user u when Message Queue 6 is
not full. Set one to this bit will clear it.

12

R/W

0x0

RECEPTION_MQ6_IRQ_PEND.
0: No effect,
1: Pending. This bit will be pending for user u when Message Queue 6 hasreceived a new message. Set one to this bit will clear it.

11

R/W

0x1

TRANSMIT_MQ5_IRQ_PEND.
0: No effect,
1: Pending. This bit will be pending for user u when Message Queue 5 is
not full. Set one to this bit will clear it.

10

R/W

0x0

RECEPTION_MQ5_IRQ_PEND.
0: No effect,
1: Pending. This bit will be pending for user u when Message Queue 5 hasreceived a new message. Set one to this bit will clear it.

9

R/W

0x1

TRANSMIT_MQ4_IRQ_PEND.
0: No effect,
1: Pending. This bit will be pending for user u when Message Queue 4 is
not full. Set one to this bit will clear it.

8

R/W

0x0

RECEPTION_MQ4_IRQ_PEND.
0: No effect,
1: Pending. This bit will be pending for user u when Message Queue 4 hasreceived a new message. Set one to this bit will clear it.

7

R/W

0x1

TRANSMIT_MQ3_IRQ_PEND.
0: No effect,
1: Pending. This bit will be pending for user u when Message Queue 3 is
not full. Set one to this bit will clear it.

6

R/W

0x0

RECEPTION_MQ3_IRQ_PEND.
0: No effect,

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1: Pending. This bit will be pending for user u when Message Queue 3 hasreceived a new message. Set one to this bit will clear it.
5

R/W

0x1

TRANSMIT_MQ2_IRQ_PEND.
0: No effect,
1: Pending. This bit will be pending for user u when Message Queue 2 is
not full. Set one to this bit will clear it.

4

R/W

0x0

RECEPTION_MQ2_IRQ_PEND.
0: No effect,
1: Pending. This bit will be pending for user u when Message Queue 2 hasreceived a new message. Set one to this bit will clear it.

3

R/W

0x1

TRANSMIT_MQ1_IRQ_PEND.
0: No effect,
1: Pending. This bit will be pending for user u when Message Queue 1 is
not full. Set one to this bit will clear it.

2

R/W

0x0

RECEPTION_MQ1_IRQ_PEND.
0: No effect,
1: Pending. This bit will be pending for user u when Message Queue 1 hasreceived a new message. Set one to this bit will clear it.

1

R/W

0x1

TRANSMIT_MQ0_IRQ_PEND.
0: No effect,
1: Pending. This bit will be pending for user u when Message Queue 0 is
not full. Set one to this bit will clear it.

0

R/W

0x0

RECEPTION_MQ0_IRQ_PEND.
0: No effect,
1: Pending. This bit will be pending for user u when Message Queue 0 hasreceived a new message. Set one to this bit will clear it.

3.13.5.5. MSGBox FIFO Status Register m(Default Value: 0x00000000)
Offset:0x100+N*0x4 (N=0~7)

Register Name: MSGBOXM_FIFO_STATUS_REG

Bit

R/W

Default/Hex

Description

31: 1

/

/

/

0

RO

0x0

FIFO_FULL_FLAG.
0: The Message FIFO queue is not full (space is available),
1: The Message FIFO queue is full.
This FIFO status register has the status related to the message queue.

3.13.5.6. MSGBox Message Status Register m(Default Value: 0x00000000)
Offset:0x140+N*0x4 (N=0~7)

Register Name: MSGBOXM_MSG_STATUS_REG

Bit

Description

R/W

Default/Hex

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31:3

/

/

/

2:0

RO

0x0

MSG_NUM.
Number of unread messages in the message queue. Here, limited to four
messages per message queue.
000: There is no message in the message FIFO queue.
001: There is 1 message in the message FIFO queue.
010: There are 2 messages in the message FIFO queue.
011: There are 3 messages in the message FIFO queue.
100: There are 4 messages in the message FIFO queue.
101~111:/3.13.5.7. MSGBox Message Queue Register (Default Value: 0x00000000)
Offset:0x180+N*0x4 (N=0~7)

Register Name: MSGBOXM_MSG_REG

Bit

R/W

Default/Hex

Description

31:0

R/W

0x0

The message register stores the next to be read message of the message
FIFO queue. Reads remove the message from the FIFO queue.

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3.14. Spinlock
3.14.1. Overview
Spinlock provides hardware assistance for synchronizing the processes running on multiple processors in thedevice. The SpinLock module implements thirty-two 32-bit spinlocks (or hardware semaphores), which provide
an efficient way to perform a lock operation of a device resource using a single read access, thus avoiding theneed for a ‘read-modify-write’ bus transfer that not all the programmable cores are capable of.
Spinlocks are present to solve the need for synchronization and mutual exclusion between heterogeneous
processors and those not operating under a single, shared operating system. There is no alternative
mechanism to accomplish these operations between processors in separate subsystems. However, Spinlocks
do not solve all system synchronization issues. They have limited applicability and should be used with care to
implement higher level synchronization protocols.
A spinlock is appropriate for mutual exclusion for access to a shared data structure. It should be used only
when:
1)
2)
3)

The time to hold the lock is predictable and small (for example, a maximum hold time of less than 200
CPU cycles may be acceptable).
The locking task cannot be preempted, suspended, or interrupted while holding the lock (this would makethe hold time large and unpredictable).
The lock is lightly contended, that is the chance of any other process (or processor) trying to acquire thelock while it is held is small.

If the conditions are not met, then a spinlock is not a good candidate. One alternative is to use a spinlock forcritical section control (engineered to meet the conditions) to implement a higher level semaphore that can
support preemption, notification, timeout or other higher level properties.
The Spinlock includes the following features:•
Spinlock module includes 32 spinlocks•
Two kinds of status of lock register: TAKEN and NOT TAKEN

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3.14.2. Functionalities Description
3.14.2.1. Typical Applications

Start
N

Take a LockIs the Lock Taken?
(SPINLOCK_LOCK_REG_i[0]=0?)Y
Take the Lock
Critical code section
Free a Lock
SPINLOCK_LOCK_REG_i[0]=0Free the LockEnd

Figure3-11. Spinlock Typical Application Flow Chart

3.14.2.2. Functional Block Diagram

Write 0/1

Read:

1

Write 0Unlocked State(TAKEN_bit=0)

Locked State(TAKEN_bit=1)
Read:0
Write 1

Reset

Figure 3-12. Spinlock Lock Register State Diagram
Every lock register has two kinds of states: TAKEN(locked) or NOT TAKEN(Unlocked). Only read-0-access andwrite-0-access could change lock register’ state and the other accesses has no effect. Just 32-bit reads and

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3.14.3. Operation Principle
3.14.3.1. Spinlock clock gating and software reset
Spinlock clock gating should be open before using it. Setting the bit[22] of Bus Clock Gating Register1 to 1
could activate Spinlock and then de-asserting it's software reset. Setting the bit[22] of Bus Software ResetRegister 1 to 1 could de-assert the software reset of Spinlock. If it is no need to use spinlock, both the gating
bit and software reset bit should be set 0.

3.14.3.2. Take and free a spinlock
Checking out Spinlock Register Status is necessary when a processor would like to take a spinlock. This register
stores all 32 lock registers’ status: TAKEN or NOT TAKEN(free).
In order to request to take a spinlock, a processor has to do a read-access to the corresponding lock register. If
lock register returns 0, the processor takes this spinlock. And if lock register returns 1, the processor must
retry.
Writing 0 to a lock register frees the corresponding spinlock. If the lock register is not taken, write-access has
no effect. For a taken spinlock, every processor has the privilege to free this spinlock. But it is suggested thatthe processor which has taken the spinlock free it for strictness.

3.14.4. Spinlock Register List
Module Name

Base Address

SPINLOCK

0x01C18000

Register Name

OffsetDescription

SPINLOCK_SYSTATUS_REG

0x0000Spinlock System Status Register

SPINLOCK_STATUS_REG

0x0010Spinlock Status Register

SPINLOCK_LOCK_REGN

0x100+N*0x4

Spinlock Lock Register N (N=0~31)

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3.14.5. Spinlock Register Description
3.14.5.1. Spinlock System Status Register (Default Value: 0x10000000)
Offset: 0x0

Register Name: SPINLOCK_SYSTATUS_REG

Bit

R/W

Default/Hex

Description

31:30

/

/

/

29:28

RO

0x1

LOCKS_NUM.
Number of lock registers implemented.
0x1: This instance has 32 lock registers.
0x2: This instance has 64 lock registers.
0x3: This instance has 128 lock registers.
0x4: This instance has 256 lock registers.

27:16

/

/

/

15:9

/

/

/

8

RO

0x0

IU0.
In-Use flag0, covering lock register0-31.
0: All lock register 0-31 are in the Not Taken state.
1: At least one of the lock register 0-31 is in the Taken state.

7:0

/

/

/

3.14.5.2. Spinlock Register Status (Default Value: 0x00000000)
Offset: 0x10

Register Name: SPINLOCK_STATUS_REG

Bit

R/W

Default/Hex

Description[i](i=0~31)

RO

0x0

LOCK_REG_STATUS.
SpinLock[i] status (i=0~31)
0: The Spinlock is free,
1: The Spinlock is taken.

3.14.5.3. Spinlock Lock Register N (N=0 to 31)(Default Value: 0x00000000)
Offset:0x100+N*0x4 (N=0~31)

Register Name: SPINLOCKN_LOCK_REG

Bit

R/W

Default/Hex

Description

31:1

/

/

/

0

R/W

0x0

TAKEN.
Lock State.
Read 0x0: The lock was previously Not Taken (free).The requester isgranted the lock.
Write 0x0: Set the lock to Not Taken (free).

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Read 0x1: The lock was previously Taken. The requester is not granted
the lock and must retry.
Write 0x1: No update to the lock value.

3.14.6. Programming Guidelines
Take CPU0's synchronization with CPUS with Spinlock0 for an example, CPU0 takes the spinlock0 firstly in the
instance：
CPU0
Step 1: CPU0 initializes Spinlock
writel(readl(BUS_CLK_GATING_REG1)|(1<<22) , BUS_CLK_GATING_REG1); //open Spinlock clock gating
writel (readl(BUS_SOFT_RST_REG1)|(1<<22) , BUS_SOFT_RST_REG1);//software reset Spinlock
Step 2: CPU0 requests to take spinlock0
rdata=readl(SPINLOCK_SYSTATUS_REG0);//check lock register0 status, if it is taken, check tillif(rdata != 0) rdata=readl(SPINLOCK_SYSTATUS_REG0);// lock register0 is freerdata=readl(SPINLOCKN_LOCK_REG0);
if(rdata != 0) rdata=readl(SPINLOCKN_LOCK_REG0);//request to take spinlock0, if fail, retry till// lock register0 is taken---------- CPU0 critical code section ---------Step 3: CPU0 free spinlock0
writel (0, SPINLOCKN_LOCK_REG0);//CPU0 frees spinlock0

Step 4: CPU0 waits for CPUS’ freeing spinlock0
writel (readl(SPINLOCK_SYSTATUS_REG0) == 1);// CPU0 waits for CPUS’freeing spinlock0

CPUS
Step 1: CPU0 has taken spinlock0, CPUS waits for CPU0’ freeing spinlock0
while(readl(SPINLOCK_SYSTATUS_REG0) == 1);// CPUS waits for CPU0’freeing spinlock0
Step 2: CPUS takes spinlock0 and go on---------- CPUS critical code section ---------Step 3: CPUS frees spinlock0
writel (0, SPINLOCKN_LOCK_REG0);

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3.15. Crypto Engine
3.15.1. Overview
The Crypto Engine(CE) is one encrypt/ decrypt function accelerator. It is suitable for a variety of applications. It
can support both encryption/decryption and signature/verification, calculate the hash value. Several modes
are supported by the Crypto Engine. The Crypto Engine has a special internal DMA(IDMA) controller to transfer
data .
It includes the following features:












Support symmetrical algorithm :AES, DES, TDES
Support asymmetrical algorithm :RSA512/1024/2048-bits
Support secure Hash algorithm: MD5, SHA-1,SHA-224,SHA-256, HMAC-SHA1,HMAC-SHA256
Support 160-bits hardware PRNG with 175-bits seed
Support 256-bits hardware TRNG
Support ECB, CBC, CTR modes for DES/TDES
Support ECB, CBC, CTR, CTS modes for AES
Support 128-bits, 192-bits and 256-bits key size for AES
Support multi-package mode for MD5/SHA-1/SHA-224/SHA-256/HMAC
Support IDMA mode
Support secure and non-secure interface respectively

3.15.2. Functionalities Description
3.15.2.1. Block Diagram
Figure 3-13 shows the block diagram of Crypto Engine.

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NS interrupt

S interrupt

TRNG

PRNG

AHB
RegisterHMAC
SHA256

SHA224
Task
management(T)DES
SHA1
AES
MD5

Efuse keys
symmetric

MBUS

RXFIFORSA512

RSA1024

TXFIFORSARSA2048

Figure 3-13. Crypto Engine Block Diagram

3.15.2.2. Crypto Engine with keysram
In Figure 3-14, keysram space composed by HDCP key,EK and BSSK.AES and RSA belong to CE,RSSK in efuse
directly links to CE,and Only CE in secure mode can be read RSSK .
The path between CE and keysram explain as following:(1) CE in secure mode uses RSSK as key,The ciphertext of HDCP key in external memory is decrypted by AES,theresult writes in HDCP key memory of keysram.AES has only the writing privilege for HDCP key memory.
(2) In order to verify that HDCP key in external memory has not been tampered,after the plaintext of HDCP key
writed in keysram,the digest of HDCP key can be obtained by MD5.We can compare the value and the digest
that in advance wrote to efuse, if the compared result is consistency,it explains that HDCP key has not been
tampered.
(3) CE in secure mode uses RSSK as key, The ciphertext of EK in external memory is decrypted by AES,the result
writes in EK memory of keysram.AES has only the writing privilege for EK memory.
(4) In order to verify that EK in external memory has not been tampered,after the plaintext of EK writed in
keysram,the digest of EK can be obtained by MD5.We can compare the value and the digest that in advance

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wrote to efuse, if the compared result is consistency,it explains that EK has not been tampered.
(5) CE in secure mode uses RSSK as key, The ciphertext of EK in external memory is decrypted by AES,the result
writes in EK memory of keysram.At the same time,AES could use BSSK as key to encrypt and decrypt.So AES
has the reading and writing privilege for BSSK.
(6) HDMI and HDCP key memory have the dedicated channe,HDMI has the reading privilege for HDCP key
memory at any time.
(7) RSA has only the reading privilege for EK memory.

CE

5

EK

RSA

7

2

3

HDCP key

4

MD5

AES

1

RSSK

BSSK

6

keysram

HDMI

Figure 3-14. Crypto Engine with Keysram

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3.15.2.3. Crypto Engine Task Descriptor
Figure 3-15 shows the block diagram of Crypto Engine Task Chaining.

…

task chaining id=0
common ctl
symmetric ctl
asymmetric ctl
key descriptor
iv descriptor
ctr descriptor
data lensrc adr0
src len0………… taskn

task chaining id=0
common ctl
symmetric ctl
asymmetric ctl
key descriptor
iv descriptor
ctr descriptor
data lensrc adr0
src len0src adr7
src len7
dst adr0
dst len0…

src adr7
src len7
dst adr0
dst len0

dst adr7
dst len7
next descriptor(task1)
reserved[3]dst adr7
dst len7
next descriptor(task2)
reserved[3]dst adr7
dst len7
next descriptor(taskn)
reserved[3]task0task chaining id=1
common ctl
symmetric ctl
asymmetric ctl
key descriptor
iv descriptor
ctr descriptor
data lensrc adr0
src len0

task1
task chaining id=1
common ctl
symmetric ctl
asymmetric ctl
key descriptor
iv descriptor
ctr descriptor
data lensrc adr0
src len0…

src adr7
src len7
dst adr0
dst len0…

…
src adr7
src len7
dst adr0
dst len0src adr7
src len7
dst adr0
dst len0

…

…

…

task2
………… taskn
task chaining id=1
common ctl
symmetric ctl
asymmetric ctl
key descriptor
iv descriptor
ctr descriptor
data lensrc adr0
src len0src adr7
src len7
dst adr0
dst len0
dst adr7
dst len7
next descriptor(task1)
reserved[3]dst adr7
dst len7
next descriptor(task2)
reserved[3]dst adr7
dst len7
next descriptor(taskn)
reserved[3]…

Task chaining1

task2

…

…

Task chaining0

task chaining id=0
common ctl
symmetric ctl
asymmetric ctl
key descriptor
iv descriptor
ctr descriptor
data lensrc adr0
src len0

task1

…

task0

Task chaining id=2…

Task chaining2…………

Task chaining id=3…

Task chaining3…………

Figure 3-15. Crypto Engine Task Chaining Block Diagram

In the above figure,Every CE task deccriptor is 44*4Byte memory.

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design are the same.CE supports 4 task channels,every task chain correspond one task id,every task channel
could do multiple tasks,which is based on whether the next descriptor of every task descriptor is 0.The task id
in the same task channel is the same.
data len= src len0 + src len1 +……+src len7,they are word in unit,when src len0 = data len,others(src len1……srclen7)must be wrote to 0;but for AES CTS,data len is byte in unit,src len0~7 are word in unit.
Next descriptor = 0, it denotes that there are not the new tasks; Next descriptor != 0,it denotes that there are
the new tasks,which is the head address of the next task descriptor.
When the source of symmetrical algorithm divide into multiple packages to encrypt or decrypt, the iv value ofthe next package store at the ctr descriptor address for ctr/cfb/ofb mode;the iv value of the next package are
the result of the last ciphertext.
The address of src/dst/key/iv/ctr in the descriptor align with word.
For the bit description of commom ctl,symmetric ctl,asymmetric ctl descriptor are as following:task_descriptor_queue common control bitmap(32bit)
Bit

Description

31

interrupt enable for current task
0: disable interrupt
1: enable interrupt

30:17

/

16

IV_ModeIV Steady of SHA-1/SHA-224/SHA-256/MD5
0: use initial constants defined in FIPS-180
1: Arbitrary IV

15

HMAC plaintext last
0: not the last HMAC plaintext package
1: the last HMAC plaintext package

14:9

/

8

SS_OP_DIR
SS Operation Direction
0: Encryption
1: Decryption

7

/

6:0

SS_Method
0: AES
1: DES
2: Triple DES (3DES)
3~15: reserved
16: MD5

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17: SHA-1
18: SHA-224
19: SHA-256
20: /
21: /
22: HMAC-SHA1
23:HMAC-SHA256
24~31: reserved
32: RSA
33~47: reserved
48: TRNG
49: PRNG
others: reserved

task_descriptor_queue symmetric control(32bit)
Bit

Description

31:24

/

23:20

SKEY_Selectkey select for AES
0: Select input SS_KEYx (Normal Mode)
1: Select {SSK}
2: Select {HUK}
3: Select {RSSK}
4-7: Reserved
8-15: Select internal Key n (n from 0 to 7)

19:18

/

17

/

16

AES_CTS_Last_Block_Flag
When set to "1", it means this is the last package for AES-CTS mode. (the size of the last
block >128bit)

15:12

/

11:8

SS_OP_Mode
SS Operation Mode
0: Electronic Code Book (ECB) mode
1: Cipher Block Chaining (CBC) mode
2: Counter (CTR) mode
3: Ciphertext Stealing (CTS) mode
Others: reserved

7:4

/

3:2

CTR_Width
Counter Width for CTR Mode
0: 16-bits Counter

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1: 32-bits Counter
2: 64-bits Counter
3: 128-bits Counter
1:0

AES_Key_Size
0: 128-bits
1: 192-bits
2: 256-bits
3: Reserved

task_descriptor_queue asymmetric control(32bit)
Bit

Description

31

/

30:28

RSA_Pubic_Modular_Width
0:512 bit
1:1024 bit
2:2048 bit
Others: reserved

27:0

/

3.15.3. Crypto Engine Register List
Module Name

Base Address

CE_NS

0x01C15000

CE_S

0x01C15800

Register Name

OffsetDescription

CE_TDQ

0x00

Task Descriptor Queue Address

CE_CTR

0x04

Gating Control Register

CE_ICR

0x08

Interrupt Control Register

CE_ISR

0x0c

Interrupt Status Register

CE_TLR

0x10

Task Load Register

CE_TSR

0x14

Task Status Register

CE_ESR

0x18

Task Error type Register

CE_CSAR

0x24

Current Source Address Register

CE_CDAR

0x28

Current Destination Address Register

CE_TPR

0x2c

Throughput Register

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3.15.4. Crypto Engine Register Description
3.15.4.1. Crypto Engine Task Descriptor Queue Register(Default Value: 0x00000000)
Register Name: CE_TDQ

Offset: 0x00
Bit

R/W

Default/Hex

Description

31:0

R/W

0x0

Task_Descriptor_Queue_Address

3.15.4.2. Crypto Engine Control Register(Default Value: 0x00000000)
Register Name:CE_CTR

Offset: 0x04
Bit

R/W

Default/Hex

Description

31:4

/

/

/

0x0

RSA_CLK_Gating_Enable(read only for NS world)
0: RSA clk gating enable
1: RSA clk gating disablex

DIE_IDDie Bonding ID

3
2:0

R/W
R

3.15.4.3. Crypto Engine Interrupt Control Register(Default Value: 0x00000000)
Register Name: CE_ICR

Offset: 0x08
Bit

R/W

Default/Hex

Description

31:4

/

/

/

0x0

Task chaining0-3_interrupt_enable
0: interrupt disable
1: interrupt enable

3:0

R/W

3.15.4.4. Crypto Engine Interrupt Status Register(Default Value: 0x00000000)
Register Name: CE_ISR

Offset: 0x0C
Bit

R/W

Default/Hex

Description

31:4

/

/

/

0x0

Task chaining0-3_End_Pending
0: busy
1: task end
It indicates that the processing of encrypt /signing or decrypt/verification
has been completed .

3:0

R/W

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Notes: Write ‘1’ to clear it.

3.15.4.5. Crypto Engine Task Load Register(Default Value: 0x00000000)
Offset: 0x10

Register Name: CE_TLR

Bit

R/W

Default/Hex

Description

31:1

/

/

/

0x0

Task_Load
When set , CE starts to load the configure of task from task descriptor
queue and start to perform the task if task FIFO is not full.

0R/W

3.15.4.6. Crypto Engine Task Status Register(Default Value: 0x00000000)
Offset: 0x14

Register Name: CE_TSR

Bit

R/W

Default/Hex

Description

31:2

/

/

/

0x0

Current task in run
0: task chaining0
1: task chaining1
2: task chaining2
3: task chaining3

1:0

R

3.15.4.7. Crypto Engine Error Status Register(Default Value: 0x00000000)
Offset: 0x18

Register Name: CE_ESR

Bit

R/W

Default/Hex

Description

31:16

/

/

/

0x0

Task channel3 error typexxx1: algorithm not support
xx1x: data length error
x1xx: keysram access error for AES. Write ‘1’ to clear.
1xxx: reserved

0x0

Task channel2 error typexxx1: algorithm not support
xx1x: data length error
x1xx: keysram access error for AES. Write ‘1’ to clear.
1xxx: reserved

0x0

Task channel1 error typexxx1: algorithm not support
xx1x: data length error

15:12

11:8

7:4

R

R

R

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1xxx: reserved

3:0

R

0x0

Task channel0 error typexxxlgorithm not support
xx1x: data length error
x1xx: keysram access error for AES. Write ‘1’ to clear.
1xxx: reserved

3.15.4.8. Crypto Engine Current Source Address Register(Default Value: 0x00000000)
Offset: 0x24

Register Name: CE_CSAR

Bit

R/W

Default/Hex

Description

31:0

R

0x0

Current source address of the executing task

3.15.4.9. Crypto Engine Current Destination Address Register(Default Value: 0x00000000)
Offset: 0x28

Register Name: CE_CDAR

Bit

R/W

Default/Hex

Description

31:0

R

0x0

Current destination address of the executing task

3.15.4.10.

Crypto Engine Throughput Register(Default Value: 0x00000000)

Offset: 0x2C
Bit
31:0

Register Name: CE_TPR
R/W
R/W

Default/Hex

Description

0x0

It indicates the throughput of data from the whole processing.
Write ‘0’ to clear it.

3.15.5. Crypto Engine Clock Requirement
Clock Name

Description

Requirement

ahb_clk

AHB bus clock>=24MHz

m_clk

MBUS clock>=24MHz

ce_clkCrypto Engine serial clock<= 300MHz && >=24MHz

3.15.6. Programming Guidelines(1) The module provides two interfaces to software.Secure CPU uses the interface of 0x800 offset,non-secure
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CPU uses the interface of 0x0 offset.
(2) The task is approached by the task descriptor mode,so before start to the load bit,the task descriptor iswrote in the specified address,and the task descriptor address register is configured.After the load bit isensure to be low,the next task could be configured.
(3) The writing/reading function of the data is completed by the internal DMA,if the data is in cache,the cacheneed refresh before the task loaded,so that the data in the address is latest.
(4) The task descriptor supports 8 source scatters and 8 destination scatters.When configuring the scatter
address and size,the continue scatter address and size should be used.Except the active scatters,the size ofother scatter need be configured to 0.
(5) data len= src len0 + src len1 +……+src len7,they are word in unit,when src len0 = data len,others(srclen1……src len7)must be wrote to 0;but for AES CTS,data len is byte in unit,src len0~7 are word in unit.
(6) Secure CPU and non-secure CPU support separately 4 task channels, every task channel has a interrupt
enable bit and interrupt status bit.
(7) The enable bit of the interrupt register represents channel interrupt,the 31bit of the first word in the task
descriptor represents the interrupt enable of every task,only the two bits are 1 at the same time,theinterrupt could pend when the task is completed.
(8) The input data sequence of RSA is that the low word store in the low address.
(9) SSK/HUK/RSSK in efuse directly links to CE,and Only CE in secure mode can read SSK/HUK/RSSK.
(10) CE in secure mode uses RSSK as key,The ciphertext of HDCP/EK/BSSK key in external memory is decrypted
by AES,the result writes in HDCP/EK/BSSK key memory of keysram.AES has only the writing privilege forthe keysram ,and to prevent the key leaked, the result only can be wrote in the keysram address when
AES decrypt by RSSK.
(11) For SHA1/SHA224/SHA256/SHA384/SHA512,It should be noted the sequence of the initial hash value.
SHA1/SHA224/SHA256/SHA384/SHA512 is the big-endian algorithm, within each word,the most significant
bit is stored in the left-most bit position.For example,the initial hash value of SHA1 in Fips180-2,H(0) shallconsist of the following five 32-bit words,in hex:
H0(0) = 67452301
H1(0) = efcdab89
H2(0) = 98badcfe
H3(0) = 10325476
H4(0) = c3d2e1f0
address increasing direction

little-endianBig-endian

address A+1

address A

High-order byte

Low-order byte

MSB

LSB

High-order byte

Low-order byte

address A

address A+1

address increasing direction

The default access mode of ARM is litter-endian.So When we write the initial value in the IV descriptor
address, according to the following array input sequence:
For SHA1:
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unsigned char iv_sha1[20]={
0x67,0x45,0x23,0x01,0xef,0xcd,0xab,0x89,
0x98,0xba,0xdc,0xfe,0x10,0x32,0x54,0x76,
0xc3,0xd2,0xe1,0xf0};
Then:
IV descriptor address :0x01234567
IV descriptor address +0x4:
0x89abcdef
IV descriptor address +0x8:
0xfedcba98
IV descriptor address +0xC:
0x76543210
IV descriptor address +0x10: 0xf0e1d2c3
For SHA224:
unsigned char iv_sha224[32]={
0xc1,0x05,0x9e,0xd8,0x36,0x7c,0xd5,0x07,
0x30,0x70,0xdd,0x17,0xf7,0x0e,0x59,0x39,
0xff,0xc0,0x0b,0x31,0x68,0x58,0x15,0x11,
0x64,0xf9,0x8f,0xa7,0xbe,0xfa,0x4f,0xa4};
For SHA256:
unsigned char iv_sha256[32]={
0x6a,0x09,0xe6,0x67,0xbb,0x67,0xae,0x85,
0x3c,0x6e,0xf3,0x72,0xa5,0x4f,0xf5,0x3a,
0x51,0x0e,0x52,0x7f,0x9b,0x05,0x68,0x8c,
0x1f,0x83,0xd9,0xab,0x5b,0xe0,0xcd,0x19};
For SHA384:
unsigned char iv_sha384[64]={
0xcb,0xbb,0x9d,0x5d,0xc1,0x05,0x9e,0xd8,
0x62,0x9a,0x29,0x2a,0x36,0x7c,0xD5,0x07,
0x91,0x59,0x01,0x5a,0x30,0x70,0xdd,0x17,
0x15,0x2f,0xec,0xd8,0xf7,0x0e,0x59,0x39,
0x67,0x33,0x26,0x67,0xff,0xc0,0x0b,0x31,
0x8e,0xb4,0x4a,0x87,0x68,0x58,0x15,0x11,
0xdb,0x0c,0x2e,0x0d,0x64,0xf9,0x8f,0xa7,
0x47,0xb5,0x48,0x1d,0xbe,0xfa,0x4f,0xa4};
For SHA512:
unsigned char iv_sha512[64]={
0x6a,0x09,0xe6,0x67,0xf3,0xbc,0xc9,0x08,
0xbb,0x67,0xae,0x85,0x84,0xca,0xa7,0x3b,
0x3c,0x6e,0xf3,0x72,0xfe,0x94,0xf8,0x2b,
0xa5,0x4f,0xf5,0x3a,0x5f,0x1d,0x36,0xf1,
0x51,0x0e,0x52,0x7f,0xad,0xe6,0x82,0xd1,
0x9b,0x05,0x68,0x8c,0x2b,0x3e,0x6c,0x1f,
0x1f,0x83,0xd9,0xab,0xfb,0x41,0xbd,0x6b,
0x5b,0xe0,0xcd,0x19,0x13,0x7e,0x21,0x79};

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3.16. Secure Memory Controller
3.16.1. Overview
The SMC is an Advanced Microcontroller Bus Architecture compliant System-on-Chip peripheral. It is ahigh-performance, area-optimized address space controller with on-chip AMBA bus interfaces that conform to
the AMBA Advanced extensible Interface protocol and the AMBA Advanced Peripheral Bus protocol.
You can configure the SMC to provide the optimum security address region control functions required for yourintended application.
The SMC includes the following features:Enables you to program security access permissions each address region.
Permits the transfer of data between master and slave only if the security status of the AXI transaction
matches the security settings of the memory region it addresses.

3.16.2. Functionalities Description
By default, the SMC performs read or write speculative that means it forwards an AXI transaction address to aslave, before it verifies that the AXI transaction is permitted to read address or write address respectively.
The SMC only permits the transfer of data between its AXI bus interfaces, after verifying the access that theread or write access is permitted respectively. If the verification fails, then it prevents the transfer of data
between the master and slave as Denied AXI transactions.
When the speculative accesses are disabled, the SMC verifies the permissions of the access before it forwards
the access to the slave. If the SMC:

Permits the access, it commences an AXI transaction to the slave, and it adds one clock latency.
Denies the access, it prevents the transfer of data between the master and slave. In this situation, theslave is unaware when the SMC prevents the master from accessing the slave.

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3.16.2.1. DRM Block Diagram

G. NS.M stands for General Non-secure Master
D. NS.M stands for Non-secure Master appointed by DRM
S.M. stands for Secure Mater
Non-secure
Zone

G.NS.M only can read data from NSZ and write data into NSZ

DRM

Secure Zone

D.NS.M can read data from NSZ and DRM, but only can write data into DRM
S.M can read data from the whole DRAM SPACEDRAM SPACE

DRM

NSZ

DRM

G.NS.M

SZ

DRM

NSZ

D.NS.M

SZ

NSZ

S.M

SZ

Figure 3-16. DRM Block Diagram

3.16.2.2. Master ID Table
Table 3-2. Master and Master ID
ID

MasterID

Master

0

CPU

12

VE

1

GPU

13

CSI

2

CPUS

14

NAND

3

ATH (test interface for
AHB)

15

Crypto Engine

4

USB-OTG/USB-OTG-HCI

16

DE_RT-MIXER0

5

SMHC0

17

DE_RT-MIXER1

6

SMHC1

18

DE_RT-WB

7

SMHC2

19

DE_ROT

8

USB-HCI0

20

9

21

TS
DE Interlace

10

EMAC

22

11

DMA

23

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3.16.2.3. Region Size Table
Table 3-3. Region Size
Size<n>Size of region<n>Base address constraints

b000000-b001101

Reserved-

b00111032KB-

b00111164KB

Bit [15] must be zerob010000

128KB

Bits [16:15] must be zerob010001

256KB

Bits [17:15] must be zerob010010512KB

Bits [18:15] must be zerob010011

1MB

Bits [19:15] must be zerob010100

2MB

Bits [20:15] must be zerob010101

4MB

Bits [21:15] must be zerob0101108MB

Bits [22:15] must be zerob010111

16MB

Bits [23:15] must be zerob011000

32MB

Bits [24:15] must be zerob011001

64MB

Bits [25:15] must be zerob011010128MB

Bits [26:15] must be zerob011011256MB

Bits [27:15] must be zerob011100

512MB

Bits [28:15] must be zerob011101

1GB

Bits [29:15] must be zerob0111102GB

Bits [30:15] must be zerob0111114GB

Bits [31:15] must be zero

B100000

8GB

Bits [32:15] must be zero

3.16.2.4. Security inversion is disabled
Table 3-4. Region security permissions
SPN field

Secure Read

Secure Write

Non-secure Read

Non-secure Write

4b0000

No

No

No

No

4b0100

No

Yes

No

No

4b0001, 4b0101

No

Yes

No

Yes

4b1000

Yes

No

No

No

4b0010, 4b1010

Yes

No

Yes

No

4b1100

Yes

Yes

No

No

4b1001, 4b1101

Yes

Yes

No

Yes

4b0110, 4b1110

Yes

Yes

Yes

No

4b0011-4b1111

Yes

Yes

Yes

Yes

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3.16.2.5. Security inversion is enabled
If you enable security inversion, the SMC permits you to program any combination of security permissions as
Table 3-5 shows.
Table 3-5. Region security permissions
SPN field

Secure Read

Secure Write

Non-secure Read

Non-secure Write

4b0000

No

No

No

No

4b0001

No

No

No

Yes

4b0010

No

No

Yes

No

4b0011

No

No

Yes

Yes

4b0100

No

Yes

No

No

4b0101

No

Yes

No

Yes

4b0110

No

Yes

Yes

No

4b0111

No

Yes

Yes

Yes

4b1000

Yes

No

No

No

4b1001

Yes

No

No

Yes

4b1010

Yes

No

Yes

No

4b1011

Yes

No

Yes

Yes

4b1100

Yes

Yes

No

No

4b1101

Yes

Yes

No

Yes

4b1110

Yes

Yes

Yes

No

4b1111

Yes

Yes

Yes

Yes

3.16.3. SMC Register List
Module Name

Base Address

SMC

0x01C1E000

Register Name

OffsetDescription

SMC_CONFIG_REG

0x0

SMC Configuration Register

SMC_ACTION_REG

0x4

SMC Action Register

SMC_LD_RANGE_REG

0x8

SMC Lock Down Range Register

SMC_LD_SELECT_REG

0xC

SMC Lock Down Select Register

SMC_INT_STATUS_REG

0x10

SMC Interrupt Status Register

SMC_INT_CLEAR_REG

0x14

SMC Interrupt Clear Register

SMC_MST_BYP_REG

0x18

SMC Master Bypass Register

SMC_MST_SEC_REG

0x1C

SMC Master Secure Register

SMC_FAIL_ADDR_REG

0x20

SMC Fail Address Register

SMC_FAIL_CTRL_REG

0x28

SMC Fail Control Register

SMC_FAIL_ID_REG

0x2C

SMC Fail ID Register

SMC_SPECU_CTRL_REG

0x30

SMC Speculation Control Register

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SMC_SEC_INV_EN_REG

0x34

SMC Security Inversion Enable Register

SMC_MST_ATTRI_REG

0x48

SMC Master Attribute Register

DRM_MASTER_EN_REG

0x50

DRM Master Enable Register

DRM_ILLACCE_REG

0x58

DRM Illegal Access Register

DRM_STATADDR_REG

0x60

DRM Start Address Register

DRM_ENDADDR_REG

0x68

DRM End Address Register

SMC_REGION_SETUP_LO_REG

0x100+N*0x10

Region Setup Low Register N(N=0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15)

SMC_REGION_SETUP_HI_REG

0x104+N*0x10

Region Setup High Register N(N=0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15)

SMC_REGION_ATTR_REG

0x108+N*0x10

Region Attribute Register N(N=0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15)

3.16.4. SMC Register Description
3.16.4.1. SMC Configuration Register(Default Value: 0x00001F0F)
Offset: 0x0

Register Name: SMC_CONFIG_REG

Bit

R/W

Default/Hex

Description

31:14

/

/

/

13:8

R

0x1F

ADDR_WIDTH_RTN.
Address width. Return the width of the AXI address bus.
6’b 000000-6’b011110 reserved.
6’b 011111 = 32-bit……
6’b 111111 = 64-bit

7:4

/

/

/

3:0

R

0xF

REGIONS_RTN.
Returns the number of the regions that the SMC provides.
4’b0000 = reserved
4’b0001 = 2 regions……
4’b1111 = 16 regions.

3.16.4.2. SMC Action Register(Default Value: 0x00000001)
Offset: 0x4

Register Name: SMC_ACTION_REG

Bit

R/W

Default/Hex

Description

31:2

/

/

/

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1:0

R/W

0x1

SMC_INT_RESP.
Control how the SMC uses the bresps[1:0], rresps[1:0], and smc_int
signals when a region permission failure occurs:
2’b00 = sets smc_int LOW and issues an OKEY response
2’b01 = sets smc_int LOW and issues a DECERR response
2’b10 = sets smc_int HIGH and issues an OKEY response
2’b11 = sets smc_int HIGH and issues a DECERR response

Note:This action is only valid for CPU access, not for MBUS and DMA access.

3.16.4.3. SMC Lockdown Range Register(Default Value: 0x00000000)
Offset: 0x8

Register Name: SMC_LD_RANGE_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

LOCKDOWN_EN.
When set to 1, it enables the lockdown_regions field to control theregions that are to be locked.

30:4

/

/

/

3:0

R/W

0x0

NO_REGIONS_LOCKDOWN.
Control the number of regions to lockdown when the enable bit is set to1.
4’b0000 = region no_of_regions-1 is locked
4’b0001 = region no_of_regions-1 to region no_of_regions-2 are locked……
4’b1111 = region no_of_regions-1 to region no_of_regions-16 are locked

Note1: No_of_regions is the value of the no_of_regions field in the configuration register.
Note2: The value programmed in lockdown_range register must not be greater than no_of_regions-1 ,else all
regions are locked.

3.16.4.4. SMC Lockdown Select Register(Default Value: 0x00000000)
Offset: 0xC

Register Name: SMC_LD_SELECT_REG

Bit

R/W

Default/Hex

Description

31:3

/

/

/

2

R/W

0x0

ACCESS_TYPE_SPECU.
Modify the access type of the speculation_control register:
0: no effect. The speculation register remains RW.
1: speculation_control register is RO

1

R/W

0x0

ACCESS_TYPE_SEC_INV_EN.
Modify the access type of the security_inversion_en register.
0: no effect. Security_inversion_en register remains RW.
1: security_inversion_en register is RO

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0

R/W

0x0

ACCESS_TYPE_LOCKDOWN_RANGE.
Modify the access type of the lockdown_range register.
0: no effect. Lockdown_range register remains RW
1: lockdown_range register is RO.

3.16.4.5. SMC Interrupt Status Register(Default Value: 0x00000000)
Offset: 0x10

Register Name: SMC_INT_STATUS_REG

Bit

R/W

Default/Hex

Description

31:2

/

/

/

1

R

0x0

INT_OVERRUN.
When set to 1, it indicates the occurrence of two or more region
permission failure since the interrupt was last cleared.

0

R

0x0

INT_STATUS.
Return the status of the interrupt.
0: interrupt is inactive.
1: interrupt is active.

3.16.4.6. SMC Interrupt Clear Register(Default Value: 0x00000000)
Offset: 0x14

Register Name: SMC_INT_CLEAR_REG

Bit

R/W

Default/Hex

Description

31:0

R/W

0x0

SMC_CLR_REG.
Write any value to the int_clear register sets the :Status bit to 0 in the int_status register
Overrun bit to 0 in the int_status register.
Note: It will be auto cleared after the write operation.

3.16.4.7. SMC Master Bypass Register(Default Value: 0xFFFFFFFF)
Offset: 0x18

Register Name: SMC_MST_BYP_REG

Bit

R/W

Default/Hex

Description

31:0

R/W

0xFFFFFFFF

SMC_MASTER_BYPASS_EN.
SMC Master n Bypass Enable.
(n = 0~31, see theTable 3-2. MASTER and MASTER ID for detail.)
Note: Bit[31:0] stand for Master ID [31:0]
If the master n bypass enable is set to 0, the master n access must be
through the SMC.
0: Bypass Disable
1: Bypass Enable.

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3.16.4.8. SMC Master Secure Register(Default Value: 0x00000000)
Offset: 0x1C

Register Name: SMC_MST_SEC_REG

Bit

R/W

Default/Hex

Description

31:0

R/W

0x0

SMC_MASTER_SEC.
SMC Master n Secure Configuration.(n = 0~31，see the Table 3-2 fordetail)0: secure
1: non-secure.

3.16.4.9. SMC Fail Address Register(Default Value: 0x00000000)
Offset: 0x20

Register Name: SMC_FAIL_ADDR_REG

Bit

R/W

Default/Hex

Description

31:0

R

0x0

FIRST_ACCESS_FAIL.
Return the address bits [31:0] of the first access to fail a region
permission check after the interrupt was cleared.
For external 16-bit DDR2, the address [2:0] is fixed to zero.
For external 32-bit DDR2 and 16-bit DDR3, the address [3:0] is fixed tozero.
For external 32-bit DDR3, the address [4:0] is fixed to zero.

Note:If the master ID=”SRAM” and the register value is between 0x80000 to 0xBFFFF, the real address should
be divide by 4.

3.16.4.10.

SMC Fail Control Register(Default Value: 0x00000000)

Offset: 0x28

Register Name: SMC_FAIL_CTRL_REG

Bit

R/W

Default/Hex

Description

31:25

/

/

/

24

R

0x0

READ_WRITE.
This bit indicates whether the first access to fail a region permission check
was a write or read as:
0 = read access
1 = write access.

23:22

/

/

/

21

R

0x0

NON_SECURE.
After clearing the interrupt status, this bit indicates whether the first accessto fail a region permission check was non-secure. Read as:
0 = secure access

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1 = non-secure access
20

R

0x0

PRIVILEGED.
After clearing the interrupt status, this bit indicates whether the first accessto fail a region permission check was privileged. Read as:
0 = unprivileged access.
1 = privileged access

19:0

/

/

/

3.16.4.11.

SMC Fail ID Register(Default Value: 0x00000000)

Offset: 0x2C

Register Name: SMC_FAIL_ID_REG

Bit

R/W

Default/Hex

Description

31:24

/

/

/

23:16

R

0x0

FAIL_BST_LEN.
Fail burst length.
0 = 1 word length……
0xf =16 words length

15:8

/

/

/

7:0

R

0x0

FAIL_MASTER_ID.
Fail Master ID.
The value stands for master id, see the Table 3-2 MASTER and MASTER ID
for detail.

3.16.4.12.

SMC Speculation Control Register(Default Value: 0x00000000)

Offset: 0x30

Register Name: SMC_SPECU_CTRL_REG

Bit

R/W

Default/Hex

Description

31:2

/

/

/

1

R/W

0x0

WRITE_SPECU.
Write_speculation. Control the write access speculation:
0 = write access speculation is enabled
1 = write access speculation is disabled.

0

R/W

0x0

READ_SPECU.
Read_speculation. Control the read access speculation:
0 = read access speculation is enabled
1 = read access speculation is disabled.

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3.16.4.13.

SMC Security Inversion Enable Register(Default Value: 0x00000000)

Offset: 0x34

Register Name: SMC_SEC_INV_EN_REG

Bit

R/W

Default/Hex

Description

31:1

/

/

/

0

R/W

0x0

SEC_INV_EN.
Security_inversion_en. Controls whether the SMC permits security inversion
to occur.
0 = security inversion is not permitted.
1 = security inversion is permitted. This enables a region to be accessible tomasters in Non-secure state but not accessible to masters in Secure state.
See Table 3-4 and Table 3-5.

3.16.4.14.

SMC Master Attribute Register(Default Value: 0x00000000)

Offset: 0x48

Register Name: SMC_MST_ATTRI_REG

Bit

R/W

Default/Hex

Description

31:0

R/W

0x0

MST_ATTRI.
0: The secure attribute of master is up to master security extensions;
1: The secure attribute of master is up to SMC Master Secure Register.

3.16.4.15.

DRM Master Enable Register(Default Value: 0x00000000)

Offset: 0x50

Register Name: DRM_MASTER_EN_REG

Bit

R/W

Default/Hex

Description

31

R/W

0x0

DRM_EN.
DRM enable.

30:12

/

/

/

13

R/W

0x0

GPU_WRITE_EN
GPU write enable.

12

R/W

0x0

GPU_READ_EN
GPU read enable.

11

R/W

0x0

GPU_ENGPU enable
When setted the bit to 1,bit12 and bit13 will be invalid.

10:9

/

/

/

8

R/W

0x0

DE_ROT
DE_ROT enable

7

R/W

0x0

DE_INTERLACE
DE_ INTERLACE enable.

6

R/W

0x0

DE_RT-WB

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DE_RT-WB enable.
5

R/W

0x0

DE_RT-MIXER1
DE_RT-MIXER1 enable.

4

R/W

0x0

DE_RT-MIXER0
DE_RT-MIXER0 enable.

3:1

/

/

/

0

R/W

0x0

VE_DECODE_EN
VE decode enable

3.16.4.16.

DRM Illegal Access Register(Default Value: 0x00000000)

Offset: 0x58

Register Name: DRM_ILLACCE_REG0

Bit

R/W

Default/Hex

Description

31:0

RO

0x0

DRM_ILLACCE_REG.
When a master, which is non-secure, accesses the DRM space, then therelevant bit will be set up. See Table 3-2 for detail.

3.16.4.17.

DRM Start Address Register(Default Value: 0x00000000)

Offset: 0x60

Register Name: DRM_STATADDR_REG

Bit

R/W

Default/Hex

Description

31:15

R/W

0x0

DRM_STATADDR_REG.

14:0

/

/

/

3.16.4.18.

DRM End Address Register(Default Value: 0x00000000)

Offset: 0x68

Register Name: DRM_ENDADDR_REG

Bit

R/W

Default/Hex

Description

31:15

R/W

0x0

DRM_ENDADDR_REG.

14:0

/

/

/

3.16.4.19.

SMC Region Setup Low Register(Default Value: 0x00000000)

Offset: 0x100+N*0x10(N=0~15)

Register Name: SMC_REGION_SETUP_LO_REG

Bit

R/W

Default/Hex

Description

31:15

R/W

0x0

BASE_ADDRESS_LOW.
Controls the base address [31:15] of region<n>.
The SMC only permits a region to start at address 0x0, or at a multiple of its

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Systemregion size. For example, if the size of a region is 512MB, and it is not ataddress 0x0, the only valid settings for this field are:17’b00100000000000000
17’b01000000000000000
17’b01100000000000000
17’b10000000000000000
17’b10100000000000000
17’b11000000000000000
17’b11100000000000000
14:0

/

/

/

Note1:For region 0, this field is Read Only (RO). The SMC sets the base address of region 0 to 0x0.
Note2:The base address should be equal to the DRAM absolutely address.

3.16.4.20.

SMC Region Setup High Register(Default Value: 0x00000000)

Offset: 0x104+N*0x10(N=0~15)

Register Name: SMC_REGION_SETUP_HI_REG

Bit

R/W

Default/Hex

Description

31:0

R/W

0x0

BASE_ADDRESS_HIGHThe SMC only permits a region to start at address 0x0, or at a multiple of its
region size. If you program a region size to be 8GB or more, then the SMC
might ignore certain bits depending on the region size.

3.16.4.21.

SMC Region Attributes Register(Default Value: 0x00000000)

Offset: 0x108+N*0x10(N=0~15)

Register Name: SMC_REGION_ATTR_REG

Bit

R/W

Default/Hex

Description

31:28

R/W

0x0

REGION_ATTR_SPN.
SP<n>. Permission setting for region <n>. if an AXI transaction occurs toregion n, the value in the sp<n> field controls whether the SMC permits thetransaction to proceed. . See Table 3-4 and Table 3-5.

27:16

/

/

/.

15:8

R/W

0x0

SUB_REGION_DISABLE.
Subregion_disable. Regions are split into eight equal-sized sub-regions, andeach bit enables the corresponding subregion to be disabled.
Bit [15] = 1 subregion 7 is disabled.
Bit [14] = 1 subregion 6 is disabled.
Bit [13] = 1 subregion 5 is disabled.
Bit [12] = 1 subregion 4 is disabled.
Bit [11] = 1 subregion 3 is disabled.
Bit [10] = 1 subregion 2 is disabled.
Bit [9] = 1 subregion 1 is disabled.

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7

/

/

/

6:1

R/W

0x0

REGION_ATTR_SIZE.
Size<n>. Size of region<n>, see Table 3-3 for detail.

0

R/W

0x0

REGION_ATTR_EN.
EN<n>. Enable for region<n>.
0 = region < n> is disabled.
1 = region < n> is enabled.

Note:For region 0,this field is reserved except SPN field.

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3.17. Secure Peripherals Controller
3.17.1. Overview
Secure Peripherals Controller(SPC) provides a software interface to the protection bits in a secure system in a
TrustZone design. It provides system flexibility that enables to configure different areas of memory as secure or
non-secure.
The SPC includes the following features:It has protection bits to enable you to program some areas of memory as secure or non–secure.

3.17.2. Functionalities Description
3.17.2.1. Peripherals Security Feature Table
SPC contains secure peripherals,non-secure peripherals and switchable peripherals.Table 3-6 shows the
security feature of A64 peripherals in CPUX and CPUS domain.
Table 3-6. Peripherals Security Feature Table
CPUX Domain
Module Name

Security

Module Name

Security

SRAM A1

Switchable

DMA

Switchable/Trust Capabilities

DE-TOP

Switchable

CS DEBUG

Trust Capabilities

DE-MIXER0

Switchable

GIC

Trust Capabilities

DE-MIXER1

Switchable

MSG_BOX

Non-secure

DE-WB

Switchable

SPINLOCK

Non-secure

DE-ROT

Switchable

OWA

Non-secure

SMHC0

Switchable

PWM

Non-secure

SMHC1

Switchable

KEYADC

Non-secure

SMHC2

Switchable

I2S/PCM-0

Non-secure

System Control

Switchable

I2S/PCM-1

Non-secure

NAND

Switchable

I2S/PCM-2

Non-secure

CE

Switchable

Audio Codec

Non-secure

USB-OTG

Switchable

Thermal Sensor

Non-secure

USB-OTG-HCI

Switchable

EMAC

Non-secure

USB-HCI0

SwitchableGPU

Non-secure

CCU

Switchable

HSTIMER

Non-secure

GPIO

Switchable

MIPI DSI

Non-secure

TWI0

Switchable

CSI

Non-secure

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TWI1

Switchable

HDMI

Non-secure

TWI2

Switchable

DE-interlace

Non-secure

DRAMC

SwitchableTS

Non-secure

SPI0

Switchable

TCON0

Non-secure

SPI1

Switchable

TCON1

Non-secure

VE SRAM

Switchable

VE

Non-secure

UART0

Switchable

TIMER

Non-secure

UART1

Switchable

SID

SecureUART2

Switchable

SMC

SecureUART3

Switchable

SPC

Secure

UART4

Switchable

SCR

Switchable

CPUX_CFG

Switchable

DE-TOP

Switchable
CPUS Domain

Module Name

Security

Module Name

Security

PRCM

Switchable

R_UART

Switchable

R_CPUCFG

Switchable

R_CIR_RX

Switchable

R_INTC

Switchable

R_GPIO

Switchable

RTC

Switchable

R_RSB

Switchable

R_TIMER0

Switchable

R_PWM

Non-secure

R_TIMER1

Switchable

R_TWD

SecureR_TIMER2

Switchable

R_WDOG

SecureR_TIMER3

Switchable

SRAM A2

Secure

R_TWI

Switchable

3.17.2.2. SPC Configuration Table
The table 3-7 shows the configuration region of the switchable peripherals.
Table 3-7. SPC Configuration Table
Bit

SPC0

SPC1

SPC2

SPC3

SPC4

SPC5

[0]

TWI0

NAND

VE SRAM

R_UART

UART0

DE-TOP

[1]

TWI1

DMA

R_CPUCFG

R_CIR_RX

UART1

DE-MIXER0

[2]

TWI2

Crypto Engine

SystemControl

R_GPIO

UART2

DE-MIXER1

[3]

SPI0

SRAM A1

CCU

R_RSB

UART3

DE-WB

[4]

SPI1

USB-OTG

USB HCI0

R_TIMER0

UART4

DE-ROT[5]

GPIO

USB-OTG-HCI

RTC

R_TIMER1

SMHC0

[6]

CPUX_CFGDRAMC

R_INTC

R_TIMER2

SMHC1

[7]

SCR

PRCM

R_TWI

R_TIMER3SMHC2

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3.17.3. SPC Register List
Module Name

Base Address

SPC

0x01C23400

Register Name

OffsetDescription

SPC_DECPORT0_STA_REG

0x4

SPC Decode Port0 Status Register

SPC_DECPORT0_SET_REG

0x8

SPC Decode Port0 Set Register

SPC_DECPORT0_CLR_REG

0xC

SPC Decode Port0 Clear Register

SPC_DECPORT1_STA_REG

0x10

SPC Decode Port1 Status Register

SPC_DECPORT1_SET_REG

0x14

SPC Decode Port1 Set Register

SPC_DECPORT1_CLR_REG

0x18

SPC Decode Port1 Clear Register

SPC_DECPORT2_STA_REG

0x1C

SPC Decode Port2 Status Register

SPC_DECPORT2_SET_REG

0x20

SPC Decode Port2 Set Register

SPC_DECPORT2_CLR_REG

0x24

SPC Decode Port2 Clear Register

SPC_DECPORT3_STA_REG

0x28

SPC Decode Port3 Status Register

SPC_DECPORT3_SET_REG

0x2C

SPC Decode Port3 Set Register

SPC_DECPORT3_CLR_REG

0x30

SPC Decode Port3 Clear Register

SPC_DECPORT4_STA_REG

0x34

SPC Decode Port4 Status Register

SPC_DECPORT4_SET_REG

0x38

SPC Decode Port4 Set Register

SPC_DECPORT4_CLR_REG

0x3C

SPC Decode Port4 Clear Register

SPC_DECPORT5_STA_REG

0x40

SPC Decode Port5 Status Register

SPC_DECPORT5_SET_REG

0x44

SPC Decode Port5 Set Register

SPC_DECPORT5_CLR_REG

0x48

SPC Decode Port5 Clear Register

3.17.4. SPC Register Description
3.17.4.1. SPC DECPORT0 Status Register(Default Value: 0x00000000)
Offset: 0x4

Register Name: SPC_DECPORT0_STA_REG

Bit

R/W

Default/Hex

Description

31:8

/

/

/

7:0

RO

0x0

STA_DEC_PROT0_OUT.
Show the status of the decode protection output:
0: = Decode region corresponding to the bit is secure
1: = Decode region corresponding to the bit is non-secure.
There is one bit of the register for each protection output (See the SPC
Configuration Table 3-7 in detail).

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3.17.4.2. SPC DECPORT0 Set Register(Default Value: 0x00000000)
Offset: 0x8

Register Name: SPC_DECPORT0_SET_REG

Bit

R/W

Default/Hex

Description

31:8

/

/

/.

7:0

WO

0x0

SET_DEC_PORT0_OUT.
Sets the corresponding decode protection output:
0: = No effect
1: = Set decode region to non-secure.
There is one bit of the register for each protection output (See the SPC
Configuration Table 3-7 in detail).

3.17.4.3. SPC DECPORT0 Clear Register(Default Value: 0x00000000)
Offset: 0xC

Register Name: SPC_DECPORT0_CLR_REG

Bit

R/W

Default/Hex

Description

31:8

/

/

/

7:0

WO

0x0

CLR_DEC_PROT0_OUT.
Clears the corresponding decode protection output:
0: = No effect
1: = Set decode region to secure.
There is one bit of the register for each protection output (See the SPC
Configuration Table 3-7 in detail).

3.17.4.4. SPC DECPORT1 Status Register(Default Value: 0x00000000)
Offset: 0x10

Register Name: SPC_DECPORT1_STA_REG

Bit

R/W

Default/Hex

Description

31:8

/

/

/

7:0

RO

0x0

STA_DEC_PROT1_OUT.
Show the status of the decode protection output:
0: = Decode region corresponding to the bit is secure
1: = Decode region corresponding to the bit is non-secure.
There is one bit of the register for each protection output (See the SPC
Configuration Table 3-7 in detail).

3.17.4.5. SPC DECPORT1 Set Register(Default Value: 0x00000000)
Offset: 0x14

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Register Name: SPC_DECPORT1_SET_REG

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Bit

R/W

Default/Hex

Description

31:8

/

/

/

7:0

WO

0x0

SET_DEC_PORT1_OUT.
Sets the corresponding decode protection output:
0: = No effect
1: = Set decode region to non-secure.
There is one bit of the register for each protection output (See the SPC
Configuration Table 3-7 in detail).

3.17.4.6. SPC DECPORT1 Clear Register(Default Value: 0x00000000)
Offset: 0x18

Register Name: SPC_DECPORT1_CLR_REG

Bit

R/W

Default/Hex

Description

31:8

/

/

/

7:0

WO

0x0

CLR_DEC_PROT1_OUT.
Clears the corresponding decode protection output:
0: = No effect
1: = Set decode region to secure.
There is one bit of the register for each protection output (See the SPC
Configuration Table 3-7 in detail).

3.17.4.7. SPC DECPORT2 Status Register(Default Value: 0x00000000)
Offset: 0x1C

Register Name: SPC_DECPORT2_STA_REG

Bit

R/W

Default/Hex

Description

31:8

/

/

/

7:0

RO

0x0

STA_DEC_PROT2_OUT.
Show the status of the decode protection output:
0: = Decode region corresponding to the bit is secure
1: = Decode region corresponding to the bit is non-secure.
There is one bit of the register for each protection output (See the SPC
Configuration Table 3-7 in detail).

3.17.4.8. SPC DECPORT2 Set Register(Default Value: 0x00000000)
Offset: 0x20

Register Name: SPC_DECPORT2_SET_REG

Bit

R/W

Default/Hex

Description

31:8

/

/

/

7:0

WO

0x0

SET_DEC_PORT2_OUT.
Sets the corresponding decode protection output:

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0: = No effect
1: = Set decode region to non-secure.
There is one bit of the register for each protection output (See the SPC
Configuration Table 3-7 in detail).

3.17.4.9. SPC DECPORT2 Clear Register(Default Value: 0x00000000)
Offset: 0x24

Register Name: SPC_DECPORT2_CLR_REG

Bit

R/W

Default/Hex

Description

31:8

/

/

/

7:0

WO

0x0

CLR_DEC_PROT2_OUT.
Clears the corresponding decode protection output:
0: = No effect
1: = Set decode region to secure.
There is one bit of the register for each protection output (See the SPC
Configuration Table 3-7 in detail).

3.17.4.10.

SPC DECPORT3 Status Register(Default Value: 0x00000000)

Offset: 0x28

Register Name: SPC_DECPORT3_STA_REG

Bit

R/W

Default/Hex

Description

31:8

/

/

/

7:0

RO

0x0

STA_DEC_PROT3_OUT.
Show the status of the decode protection output:
0: = Decode region corresponding to the bit is secure
1: = Decode region corresponding to the bit is non-secure
There is one bit of the register for each protection output (See the SPC
Configuration Table 3-7 in detail).

3.17.4.11.

SPC DECPORT3 Set Register(Default Value: 0x00000000)

Offset: 0x2C

Register Name: SPC_DECPORT3_SET_REG

Bit

R/W

Default/Hex

Description

31:8

/

/

/

7:0

WO

0x0

SET_DEC_PORT3_OUT.
Sets the corresponding decode protection output:
0: = No effect
1: = Set decode region to non-secure
There is one bit of the register for each protection output (See the SPC
Configuration Table 3-7 in detail).

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3.17.4.12.

SPC DECPORT3 Clear Register(Default Value: 0x00000000)

Offset: 0x30

Register Name: SPC_DECPORT3_CLR_REG

Bit

R/W

Default/Hex

Description

31:8

/

/

/

7:0

WO

0x0

CLR_DEC_PROT3_OUT.
Clears the corresponding decode protection output:
0: = No effect
1: = Set decode region to secure
There is one bit of the register for each protection output (See the SPC
Configuration Table 3-7 in detail).

3.17.4.13.

SPC DECPORT4 Status Register(Default Value: 0x00000000)

Offset: 0x34

Register Name: SPC_DECPORT4_STA_REG

Bit

R/W

Default/Hex

Description

31:8

/

/

/

7:0

RO

0x0

STA_DEC_PROT4_OUT.
Show the status of the decode protection output:
0: = Decode region corresponding to the bit is secure
1: = Decode region corresponding to the bit is non-secure
There is one bit of the register for each protection output (See the SPC
Configuration Table 3-7 in detail).

3.17.4.14.

SPC DECPORT4 Set Register(Default Value: 0x00000000)

Offset: 0x38

Register Name: SPC_DECPORT4_SET_REG

Bit

R/W

Default/Hex

Description

31:8

/

/

/

7:0

WO

0x0

SET_DEC_PORT4_OUT.
Sets the corresponding decode protection output:
0: = No effect
1: = Set decode region to non-secure
There is one bit of the register for each protection output (See the SPC
Configuration Table 3-7 in detail).

3.17.4.15.

SPC DECPORT4 Clear Register(Default Value: 0x00000000)

Offset: 0x3C

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Register Name: SPC_DECPORT4_CLR_REG

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Bit

R/W

Default/Hex

Description

31:8

/

/

/

7:0

WO

0x0

CLR_DEC_PROT4_OUT.
Clears the corresponding decode protection output:
0: = No effect
1: = Set decode region to secure
There is one bit of the register for each protection output (See the SPC
Configuration Table 3-7 in detail).

3.17.4.16.

SPC DECPORT5 Status Register(Default Value: 0x00000000)

Offset: 0x40

Register Name: SPC_DECPORT5_STA_REG

Bit

R/W

Default/Hex

Description

31:8

/

/

/

7:0

RO

0x0

STA_DEC_PROT5_OUT.
Show the status of the decode protection output:
0: = Decode region corresponding to the bit is secure
1: = Decode region corresponding to the bit is non-secure
There is one bit of the register for each protection output (See the SPC
Configuration Table 3-7 in detail).

3.17.4.17.

SPC DECPORT5 Set Register(Default Value: 0x00000000)

Offset: 0x44

Register Name: SPC_DECPORT5_SET_REG

Bit

R/W

Default/Hex

Description

31:8

/

/

/

7:0

WO

0x0

SET_DEC_PORT5_OUT.
Sets the corresponding decode protection output:
0: = No effect
1: = Set decode region to non-secure
There is one bit of the register for each protection output (See the SPC
Configuration Table 3-7 in detail).

3.17.4.18.

SPC DECPORT5 Clear Register(Default Value: 0x00000000)

Offset: 0x48

Register Name: SPC_DECPORT5_CLR_REG

Bit

R/W

Default/Hex

Description

31:8

/

/

/

7:0

WO

0x0

CLR_DEC_PROT5_OUT.
Clears the corresponding decode protection output:

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0: = No effect
1: = Set decode region to secure
There is one bit of the register for each protection output (See the SPC
Configuration Table 3-7 in detail).

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3.18. Thermal Sensor Controller
3.18.1. Overview
The thermal sensors have become common elements in wide range of modern system on chip (SOC) platform.
Thermal sensors are used to constantly monitor the temperature on the chip.
A64 embeds three thermal sensors in possible hot spots on the die, sensor0 located in the CPU, sensor1 andsensor2 located in the GPU. The thermal sensor Generates interrupt to SW to lower temperature via DVFS, on
reaching a certain thermal threshold.
The Thermal Sensor Controller includes the following features:Supports APB 32-bits bus widthPower supply voltage:3.0V

Low power dissipation
Periodic temperature measurement
Averaging filter for thermal sensor readingSupport over-temperature protection interrupt and over-temperature alarm interrupt

3.18.2. Clock and Timing Requirements
CLK_IN = 24MHz/M, M can be set in the CCU
Conversion Time = 1/(24MHz/M/14Cycles) =0.583 * M (us)
THERMAL_PER (configured by the value of THERMAL_PER) is must be greater than (ACQ1 + ACQ0+Conversion
Time)
THERMAL_PER > ACQ1 + ACQ0+Conversion Time

Figure 3-17. Thermal Conversion phase

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3.18.3. Temperature Conversion FormulaTemp=-8.56*Data + 2170 ℃
Val is the value that read from THS0_DATA_REG/THS1_DATA_REG/THS2_DATA_REG.

3.18.4. Thermal Sensor Register List
Module Name

Base Address

Thermal Sensor

0x01C25000

Register Name

OffsetDescription

THS_CTRL00x00

THS Control Register0

THS_CTRL1

0x04

THS Control Register1

ADC_CDAT

0x14

ADC calibration data Register

THS_CTRL2

0x40

THS Control Register2

THS_INT_CTRL

0x44

THS Interrupt Control Register

THS_STAT

0x48

THS Status Register

THS0_ALARM_CTRL

0x50

Alarm threshold Control Register0

THS1_ALARM_CTRL

0x54

Alarm threshold Control Register1

THS2_ALARM_CTRL

0x58

Alarm threshold Control Register2

THS0_SHUTDOWN_CTRL

0x60

Shutdown threshold Control Register0

THS1_SHUTDOWN_CTRL

0x64

Shutdown threshold Control Register1

THS2_SHUTDOWN_CTRL

0x68

Shutdown threshold Control Register2

THS_FILTER

0x70

Median filter Control Register

THS0_1_CDATA

0x74

Thermal Sensor 0 1 Calibration Data

THS2_CDATA

0x78

Thermal Sensor2 Calibration Data

THS0_DATA0x80

THS0 Data Register

THS1_DATA

0x84

THS1 Data Register

THS2_DATA

0x88

THS2 Data Register

3.18.5. Thermal Sensor Register Description
3.18.5.1. THS Control Register0 (Default Value: 0x00000000)
Offset: 0x00

Register Name: THS_CTRL_REG0

Bit

R/W

Default/Hex

Description

31:16

/

/

/

15:0

R/W

0x0

SENSOR_ACQ0

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ADC acquire time
CLK_IN/(N+1)

3.18.5.2. THS Control Register1 (Default Value: 0x00000000)
Offset: 0x04

Register Name: THS_CTRL_REG1

Bit

R/W

Default/Hex

Description

31:22

/

/

/

21:20

R/W

0x0

THS_OP_BIAS.
THS OP Bias

19:18

/

/

/

17

R/W

0x0

ADC_CALI_EN.
ADC Calibration
1: start Calibration, it is clear to 0 after calibration

16:0

/

/

/

3.18.5.3. ADC calibration Data Register (Default Value: 0x00000000)
Offset: 0x14

Register Name: ADC_CDAT_REG

Bit

R/W

Default/Hex

Description

31:12

/

/

/

11:0

R/W

0xxxx

ADC_CDAT.
ADC calibration data

3.18.5.4. THS Control Register2 (Default Value: 0x00040000)
Offset: 0x40

Register Name: THS_CTRL_REG2

Bit

R/W

Default/Hex

Description

31:16

R/W

0x4

SENSOR_ACQ1.
Sensor acquire time
CLK_IN/(N+1)

15:3

/

/

/

2

R/W

0x0

SENSE2_EN.
Enable temperature measurement sensor2
0:Disable
1:Enable

1

R/W

0x0

SENSE1_EN.
Enable temperature measurement sensor1
0:Disable
1:Enable

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0

R/W

0x0

SENSE0_EN.
Enable temperature measurement sensor0
0:Disable
1:Enable

3.18.5.5. THS Interrupt Control Register (Default Value: 0x00000000)
Offset: 0x44

Register Name: THS_INT_CTRL_REG

Bit

R/W

Default/Hex

Description

31:12

R/W

0x0

THERMAL_PER.
4096*(n+1)/CLK_IN

11

/

/

/

10

R/W

0x0

THS2_DATA_IRQ_EN.
Selects Temperature measurement data of sensor2
0: No select
1: Select

9

R/W

0x0

THS1_DATA_IRQ_EN.
Selects Temperature measurement data of sensor1
0: No select
1: Select

8

R/W

0x0

THS0_DATA_IRQ_EN.
Selects Temperature measurement data of sensor0
0: No select
1: Select

7

/

/

/

6

R/W

0x0

SHUT_INT2_EN.
Selects shutdown interrupt for sensor2
0: No select
1: Select

5

R/W

0x0

SHUT_INT1_EN.
Selects shutdown interrupt for sensor1
0: No select
1: Select

4

R/W

0x0

SHUT_INT0_EN.
Selects shutdown interrupt for sensor0
0: No select
1: Select

3

/

/

/

2

R/W

0x0

ALARM_INT2_EN.
Selects Alert interrupt for sensor2
0: No select
1: Select

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1

R/W

0x0

ALARM_INT1_EN.
Selects Alert interrupt for sensor1
0: No select
1: Select

0

R/W

0x0

ALARM_INT0_EN.
Selects Alert interrupt for sensor0
0: No select
1: Select

3.18.5.6. THS status Register (Default Value: 0x00000000)
Offset: 0x48

Register Name: THS_STAT_REG

Bit

R/W

Default/Hex

Description

31:15

/

/

/

14

R/W

0x0

ALARM_OFF2_STS.
Alarm interrupt off pending for sensor2
Write ‘1’ to clear this interrupt or automatic clear if interrupt condition
fails

13

R/W

0x0

ALARM_OFF1_STS.
Alarm interrupt off pending for sensor1
Write ‘1’ to clear this interrupt or automatic clear if interrupt condition
fails

12

R/W

0x0

ALARM_OFF0_STS.
Alarm interrupt off pending for sensor0
Write ‘1’ to clear this interrupt or automatic clear if interrupt condition
fails

11

/

/

/

10

R/W

0x0

THS2_DATA_IRQ_STS.
Data interrupt status for sensor2
Write ‘1’ to clear this interrupt or automatic clear if interrupt condition
fails

9

R/W

0x0

THS1_DATA_IRQ_STS.
Data interrupt status for sensor1
Write ‘1’ to clear this interrupt or automatic clear if interrupt condition
fails

8

R/W

0x0

THS0_DATA_IRQ_STS.
Data interrupt status for sensor0
Write ‘1’ to clear this interrupt or automatic clear if interrupt condition
fails

7

/

/

/

6

R/W

0x0

SHUT_INT2_STS.
Shutdown interrupt status for sensor2
Write ‘1’ to clear this interrupt or automatic clear if interrupt condition

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fails
5

R/W

0x0

SHUT_INT1_STS.
Shutdown interrupt status for sensor1
Write ‘1’ to clear this interrupt or automatic clear if interrupt condition
fails

4

R/W

0x0

SHUT_INT0_STS.
Shutdown interrupt status for sensor0
Write ‘1’ to clear this interrupt or automatic clear if interrupt condition
fails

3

/

/

/

2

R/W

0x0

ALARM_INT2_STS.
Alarm interrupt pending for sensor2
Write ‘1’ to clear this interrupt or automatic clear if interrupt condition
fails

1

R/W

0x0

ALARM_INT1_STS.
Alarm interrupt pending for sensor1
Write ‘1’ to clear this interrupt or automatic clear if interrupt condition
fails

0

R/W

0x0

ALARM_INT0_STS.
Alarm interrupt pending for sensor0
Write ‘1’ to clear this interrupt or automatic clear if interrupt condition
fails

3.18.5.7. Alarm threshold Control Register0 (Default Value: 0x05a00684)
Offset: 0x50

Register Name: THS0_ALARM_CTRL_REG

Bit

R/W

Default/Hex

Description

31:28

/

/

/

27:16

R/W

0x5A0

ALARM0_T_HOT.
Thermal sensor0 Alarm Threshold for hot temperature

15:12

/

/

/

11:0

R/W

0x684

ALARM0_T_HYSTThermal sensor0 Alarm threshold for hysteresis temperature

3.18.5.8. Alarm threshold Control Register1 (Default Value: 0x05a00684)
Offset: 0x54

Register Name: THS1_ALARM_CTRL_REG

Bit

R/W

Default/Hex

Description

31:28

/

/

/

27:16

R/W

0x5A0

ALARM1_T_HOT.
Thermal sensor1 Alarm Threshold for hot temperature

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15:12

/

/

/

11:0

R/W

0x684

ALARM1_T_HYSTThermal sensor1 Alarm threshold for hysteresis temperature

3.18.5.9. Alarm threshold Control Register2 (Default Value: 0x05a00684)
Offset: 0x58

Register Name: THS2_ALARM_CTRL_REG

Bit

R/W

Default/Hex

Description

31:28

/

/

/

27:16

R/W

0x5A0

ALARM2_T_HOT.
Thermal sensor2 Alarm Threshold for hot temperature

15:12

/

/

/

11:0

R/W

0x684

ALARM2_T_HYSTThermal sensor2 Alarm threshold for hysteresis temperature

3.18.5.10.

Shutdown threshold Control Register0 (Default Value: 0x04e90000)

Offset: 0x60

Register Name: THS0_SHUTDOWN_CTRL_REG

Bit

R/W

Default/Hex

Description

31:28

/

/

/

27:16

R/W

0x4E9

SHUT0_T_HOT.
Thermal sensor0 Shutdown Threshold for hot temperature

15:0

/

/

/

3.18.5.11.

Shutdown threshold Control Register1 (Default Value: 0x04e90000)

Offset: 0x64

Register Name: THS1_SHUTDOWN_CTRL_REG

Bit

R/W

Default/Hex

Description

31:28

/

/

/

27:16

R/W

0x4E9

SHUT1_T_HOT.
Thermal sensor1 Shutdown Threshold for hot temperature

15:0

/

/

/

3.18.5.12.

Shutdown threshold Control Register2 (Default Value: 0x04e90000)

Offset: 0x68

Register Name: THS2_SHUTDOWN_CTRL_REG

Bit

R/W

Default/Hex

Description

31:28

/

/

/

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27:16

R/W

0x4E9

SHUT2_T_HOT.
Thermal sensor2 Shutdown Threshold for hot temperature

15:0

/

/

/

3.18.5.13.

Average filter Control Register (Default Value: 0x00000001)

Offset: 0x70

Register Name: THS_FILTER_REG

Bit

R/W

Default/Hex

Description

31:3

/

/

/

2

R/W

0x0

FILTER_EN.
Filter Enable
0: Disable
1: Enable

1:0

R/W

0x1

FILTER_TYPE.
Average Filter Type
00: 2
01: 4
10: 8
11: 16

3.18.5.14.

Thermal Sensor 0&1 calibration Data Register (Default Value: 0x08000800)

Offset: 0x74

Register Name: THS0_1_CDATA_REG

Bit

R/W

Default/Hex

Description

31:28

/

/

/

27:16

R/W

0x800

THS1_CDATA.
Thermal Sensor1 calibration data

15:12

/

/

/

11:0

R/W

0x800

THS0_CDATA.
Thermal Sensor0 calibration data

3.18.5.15.

Thermal Sensor 2 calibration Data Register (Default Value: 0x00000800)

Offset: 0x78

Register Name: THS2_CDATA_REG

Bit

R/W

Default/Hex

Description

31:12

/

/

/

11:0

R/W

0x800

THS2_CDATA.
Thermal Sensor2 calibration data

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3.18.5.16.

THS0 Data Register (Default Value: 0x00000000)

Offset: 0x80

Register Name: THS0_DATA_REG

Bit

R/W

Default/Hex

Description

31:12

/

/

/

11:0

R

0x0

THS0_DATA.
Temperature measurement data of sensor0

3.18.5.17.

THS1 Data Register (Default Value: 0x00000000)

Offset: 0x84

Register Name: THS1_DATA_REG

Bit

R/W

Default/Hex

Description

31:12

/

/

/

11:0

R

0x0

THS1_DATA.
Temperature measurement data of sensor1

3.18.5.18.

THS2 Data Register (Default Value: 0x00000000)

Offset: 0x88

Register Name: THS2_DATA_REG

Bit

R/W

Default/Hex

Description

31:12

/

/

/

11:0

R

0x0

THS2_DATA.
Temperature measurement data of sensor2

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3.19. KEYADC
3.19.1. Overview
KEYADC is 6-bit resolution ADC for key application. The KEYADC can work up to 250Hz conversion rate.
The KEYADC includes the following features:Supports APB 32-bits bus width,reference voltage is 2.0V
Support interrupt
Support Hold Key and General Key
Support Single Key and Continue Key modeSupport 6-bits resolution
Voltage input range between 0V to 2.0V

Sample rate up to 250Hz

3.19.2. Clock Source
The following diagram shows the clock source of KEYADC.

InternalOSC

DIV

32KHz KeyADC

Figure 3-18. KEYADC Clock Source

3.19.3. Operation Principle
The KEYADC converted data can accessed by interrupt and polling method. If software can’t access the lastconverted data instantly, the new converted data would update the old one at new sampling data.

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Figure 3-19. KEY_ADC Converted Data Diagram
When ADC_IN Signal change from 1.8V to less than 1.35V (Level A), the comparator24 send first interrupt tocontrol logic; When ADC_IN Signal change from 1.35V to less than certain level (Program can set), thecomparator25 give second interrupt. If the control Logic get the first interrupt, In a certain time range (program
can set), doesn’t get second interrupt, it will send hold key interrupt to the host; If the control Logic get thefirst interrupt, In a certain time range (program can set), get second interrupt, it will send key down interrupt
to the host; If the control logic only get the second interrupt, doesn’t get the first interrupt, it will send alreadyhold interrupt to the host.
The KEYADC have three mode, Normal Mode、Single Mode and Continue Mode. Normal Mode is that the
KEYADC will report the result data of each convert all the time when the key is down. Single Mode is that the
KEYADC will only report the first convert result data when the key is down. Continue Mode is that the KEYADC
will report one of 8*(N+1) (N is program can set) sample convert result data when key is down.
The KEYADC is support four sample rate such as 250Hz、125Hz、62.5Hz and 32.25Hz, you can configure thevalue of KEYADC_SAMPLE_RATE to select the fit sample rate.

3.19.4. KEY_ADC Register List
Module Name

Base Address

KEYADC

0x01C21800

Register Name

OffsetDescription

KEYADC_CTRL

0x00

KEYADC Control Register

KEYADC_INTC

0x04

KEYADC Interrupt Control Register

KEYADC_INTS

0x08

KEYADC Interrupt Status Register

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KEYADC_DATA

0x0C

KEYADC Data Register

3.19.5. KEYADC Register Description
3.19.5.1. KEYADC Control Register (Default Value: 0x01000168)
Offset: 0x00

Register Name: KEYADC_CTRL_REG

Bit

R/W

Default/Hex

Description

31: 24

R/W

0x1

FIRST_CONVERT_DLY.
ADC First Convert Delay setting, ADC conversion is delayed by n samples

23:22

R/W

0x0

Reserved to 0

21:20

/

/

/

19:16

R/W

0x0

CONTINUE_TIME_SELECT.
Continue Mode time select, one of 8*(N+1) sample as a valuable sample
data

15:14

/

/

/

13:12

R/W

0x0

KEY_MODE_SELECT.
Key Mode Select:
00: Normal Mode
01: Single Mode
10: Continue Mode

11:8

R/W

0x1

LEVELA_B_CNT.
Level A to Level B time threshold select, judge ADC convert value in level
A to level B in n+1 samples

7

R/W

0X0

KEYADC_HOLD_KEY_EN
KEYADC Hold Key Enable
0: Disable
1: Enable

6

R/W

0x1

KEYADC_HOLD_EN.
KEYADC Sample hold Enable
0: Disable
1: Enable

5: 4

R/W

0x2

LEVELB_VOL.
Level B Corresponding Data Value setting (the real voltage value)
00: 0x3C (~1.9v)
01: 0x39 (~1.8v)
10: 0x36 (~1.7v)
11: 0x33 (~1.6v)

3: 2

R/W

0x2

KEYADC_SAMPLE_RATE.
KEYADC Sample Rate
00: 250 Hz
01: 125 Hz

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10: 62.5 Hz
11: 32.25 Hz
1

/

/

/

0

R/W

0x0

KEYADC_EN.
KEYADC enable
0: Disable
1: Enable

3.19.5.2. KEYADC Interrupt Control Register (Default Value: 0x00000000)
Offset: 0x04

Register Name: KEYADC_INTC_REG

Bit

R/W

Default/Hex

Description

31:5

/

/

/

4

R/W

0x0

ADC_KEYUP_IRQ_EN.
ADC Key Up IRQ Enable
0: Disable
1: Enable

3

R/W

0x0

ADC_ALRDY_HOLD_IRQ_EN.
ADC Already Hold IRQ Enable
0: Disable
1: Enable

2

R/W

0x0

ADC_HOLD_IRQ_EN.
ADC Hold Key IRQ Enable
0: Disable
1: Enable

1

R/W

0x0

ADC_KEYDOWN_EN
ADC Key Down Enable
0: Disable
1: Enable

0

R/W

0x0

ADC_DATA_IRQ_EN.
ADC Data IRQ Enable
0: Disable
1: Enable

3.19.5.3. KEYADC Interrupt Status Register (Default Value: 0x00000000)
Offset: 0x08

Register Name:KEYADC_INTS_REG

Bit

R/W

Default/Hex

Description

31:5

/

/

/

4

R/W

0x0

ADC_KEYUP_PENDING.
ADC Key up pending Bit

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When general key pull up, it the corresponding interrupt is enabled.
0: No IRQ
1: IRQ Pending
Notes: Writing 1 to the bit will clear it and its corresponding interrupt if
the interrupt is enable
3

R/W

0x0

ADC_ALRDY_HOLD_PENDING.
ADC Already Hold Pending Bit
When hold key pull down and pull the general key down, if thecorresponding interrupt is enabled.
0: No IRQ
1: IRQ Pending
Notes: Writing 1 to the bit will clear it and its corresponding interrupt if
the interrupt is enable

2

R/W

0x0

ADC_HOLDKEY_PENDING.
ADC Hold Key pending Bit
When Hold key pull down, the status bit is set and the interrupt line is set
if the corresponding interrupt is enabled.
0: NO IRQ
1: IRQ Pending
Notes: Writing 1 to the bit will clear it and its corresponding interrupt if
the interrupt is enable.

1

R/W

0x0

ADC_KEYDOWN_PENDING.
ADC Key Down IRQ Pending Bit
When General key pull down, the status bit is set and the interrupt line is
set if the corresponding interrupt is enabled.
0: No IRQ
1: IRQ Pending
Notes: Writing 1 to the bit will clear it and its corresponding interrupt if
the interrupt is enable.

0

R/W

0x0

ADC_DATA_PENDING.
ADC Data IRQ Pending Bit
0: No IRQ
1: IRQ Pending
Notes: Writing 1 to the bit will clear it and its corresponding interrupt if
the interrupt is enable.

3.19.5.4. KEYADC Data Register (Default Value: 0x00000000)
Offset: 0x0C

Register Name: KEYADC_DATA_REG

Bit

R/W

Default/Hex

Description

31:6

/

/

/

5:0

R

0x0

KEYADC_DATA.
KEYADC Data

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3.20. Audio Codec
3.20.1. Overview
The Audio CODEC has two I2S/PCM interface, 2 channels DAC and 2 channels ADC with a high level of
mixed-signal integration which ideal for smart phone and other portable devices. The two sets of audio interface
pins are available in order to provide synchronous connections to multiple processors such as baseband
processor and wireless headset transceiver.
The Codec integrates true-ground capless headphone driver to deliver high quality and power-efficient
headphone playback without any requirement for DC block capacitors.
The integrated hardware DSP engine capable of AGC and DRC can be used in record and playback paths formaintaining a constant signal level,maximizing the loudness.
The features of Audio Codec:


















Two audio digital-to-analog(DAC) channels
Stereo capless headphone drivers:
100dB SNR@A-weight
Supports DAC Sample Rates from 8KHz to 192KHz
Support analog/digital volume control
Differential earpiece driver
Analog low-power loop from line-in /microphone to headphone/earpiece outputs
Support Dynamic Range Controller(DRC) adjusting the DAC playback output.
Accessory button press detection
Four audio inputs:
Two differential microphone inputs
One differential Phone input
Stereo Line-in L/R input
Four audio outputs:
Earpiece amplifier differential output
Phone amplifier differential output
Headphone amplifier L/R channel output
Line-out L/R output
Two audio analog-to-digital(ADC) channels
96dB SNR@A-weight
Supports ADC Sample Rates from 8KHz to 48KHz
Support Automatic Gain Control(AGC) and Dynamic Range Control(DRC) adjusting the ADC recording
outputTwo PCM interface connected with BB and BT
One 128x24-bits FIFO for data transmit, one 64x24-bits FIFO for data receive

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Interrupt and DMA Support
Support Audio HUB

3.20.2. Power and Signal Description
3.20.2.1. Analog I/O Pins
MIC1P

I

Positive differential input for MIC1

MIC1N

I

Negative differential input for MIC1

MIC2P

I

Positive differential input for MIC2

MIC2N

I

Negative differential input for MIC2

LINEINLI

Left single-end input for LINE-IN

LINEINRI

Right single-end input for LINE-IN

PHONEINPI

Positive differential input for Phone

PHONEINN

I

Negative differential input for Phone

HPOUTLO

Headphone amplifier left channel output

HPOUTRO

Headphone amplifier right channel output

LINEOUTLO

Left single-end output for LINE-OUT

LINEOUTRO

Right single-end output for LINE-OUT

EAROUTPO

Earpiece amplifier positive differential output

EAROUTNO

Earpiece amplifier negative differential output

PHONEOUTPO

Positive differential output for Phone

PHONEOUTN

O

Negative differential output for Phone

MIC-DETI

Headphone MIC Detect

HP-DET

I

Headphone Jack Detect

3.20.2.2. Filter/Reference
MBIAS

O

First bias voltage output for main microphone

HBIAS

O

Second bias voltage output for headset microphone

HP-FB

I

Pseudo differential headphone ground feedback

CPN

O

charge pump flying-back capacitor

CPPO

charge pump flying-back capacitor

VRA1

O

internal reference voltage

VRA2

O

internal reference voltage

VRP

O

internal reference voltage

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3.20.2.3. Power/Ground
AVCC

P

Analog power

AGND

G

Analog ground

CPVDD

P

Analog power for headphone charge pump

CPVEE

P

Charge pump negative voltage output

VEE

P

PA negative voltage input

3.20.3. Data Path Diagram
BB

BT

FIFO
SYNC

PHONEOUTN

PHONEOUTP

APB

G

+

L

R

I2S/PCM Interface
L
R
L
R

L

R

I2S/PCM Interface
L
R
L
R

PCM Interface

m

m
m

m
L/R Source Select/Mono Mix Control

Slot0

Slot1

Slot0

Slot1

DAP

DAP

DAP

DAP

L/R Source Select/MonoMix Control

DAP

NO SRC

DAP

SRC
+
MIC1P
MIC1N

+
-G

MIC2P
MIC2N

+
-G

PHONEINP
PHONEINNLINEINL
LINEINR

+
-G

+
-G

m
m
m
m
m
m
m
m
m
m
m
m
m
m

+

+ +

DACL
MIXL
MIXR
DACR

m

MIXL
MIXR

m

EAROUTPGEAROUTNLINEOUTL

G
-1

G

ADCL

D
A
P

G

ADCR

D
A
P

m
MIXR

D
A
P

DACL

D
A
P

DACR

m

DACL

m

m

G

m

G

m

G

LINEOUTR

HPOUTL

MIXL
m mmm mDACR

mm

HPOUTR

MIXR

Figure 3-20. Audio Codec Data Path Diagram

3.20.4. Audio Codec Register List
Module Name

Base Address

AC

0X01C22C00

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Register Name

OffsetDescription

DA_CTL

0x000

Digital Audio Control Register

DA_FAT0

0x004

Digital Audio Format Register 0

DA_FAT1

0x008

Digital Audio Format Register 1

DA_ISTA

0x00C

Digital Audio Interrupt Status Register

DA_RXFIFO

0x010

Digital Audio RX FIFO Register

DA_FCTL

0x014

Digital Audio FIFO Control Register

DA_FSTA

0x018

Digital Audio FIFO Status Register

DA_INT

0x01C

Digital Audio Interrupt Control Register

DA_TXFIFO

0x020

Digital Audio TX FIFO Register

DA_CLKD

0x024

Digital Audio Clock Divide Register

DA_TXCNT

0x028

Digital Audio RX Sample Counter Register

DA_RXCNT

0x02C

Digital Audio TX Sample Counter Register

DA_TXCHSEL

0x030

Digital Audio TX Channel Select register

DA_TXCHMAP

0x034

Digital Audio TX Channel Mapping Register

DA_RXCHSEL

0x038

Digital Audio RX Channel Select register

DA_RXCHMAP

0x03C

Digital Audio RX Channel Mapping Register

Codec_RST

0x200

Chip Soft Reset Register

SYSCLK_CTL

0x20C

System Clock Control Register

MOD_CLK_ENA

0x210

Module Clock Control Register

MOD_RST_CTL

0x214

Module Reset Control Register

SYS_SR_CTRL

0x218

System Sample rate & SRC Configuration Register

SYS_SRC_CLK

0x21C

System SRC Clock Source Select Register

SYS_DVC_MOD

0x220

System DVC Mode Select Register

AIF1CLK_CTRL

0x240

AIF1 BCLK/LRCK Control Register

AIF1_ADCDAT_CTRL

0x244

AIF1 ADCDAT Control Register

AIF1_DACDAT_CTRL

0x248

AIF1 DACDAT Control Register

AIF1_MIXR_SRC

0x24C

AIF1 Digital Mixer Source Select Register

AIF1_VOL_CTRL1

0x250

AIF1 Volume Control 1 Register

AIF1_VOL_CTRL2

0x254

AIF1 Volume Control 2 Register

AIF1_VOL_CTRL3

0x258

AIF1 Volume Control 3 Register

AIF1_VOL_CTRL4

0x25C

AIF1 Volume Control 4 Register

AIF1_MXR_GAIN

0x260

AIF1 Digital Mixer Gain Control Register

AIF1_RXD_CTRL

0x264

AIF1 Receiver Data Discarding Control Register

AIF2_CLK_CTRL

0x280

AIF2 BCLK/LRCK Control Register

AIF2_ADCDAT_CTRL

0x284

AIF2 ADCDAT Control Register

AIF2_DACDAT_CTRL

0x288

AIF2 DACDAT Control Register

AIF2_MXR_SRC

0x28C

AIF2 Digital Mixer Source Select Register

AIF2_VOL_CTRL1

0x290

AIF2 Volume Control 1 Register

AIF2_VOL_CTRL2

0x298

AIF2 Volume Control 2 Register

AIF2_MXR_GAIN

0x2A0

AIF2 Digital Mixer Gain Control Register

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AIF2_RXD_CTRL

0x2A4

AIF2 Receiver Data Discarding Control Register

AIF3_CLK_CTRL

0x2C0

AIF3 BCLK/LRCK Control Register

AIF3_ADCDAT_CTRL

0x2C4

AIF3 ADCDAT Control Register

AIF3_DACDAT_CTRL

0x2C8

AIF3 DACDAT Control Register

AIF3_SGP_CTRL

0x2CC

AIF3 Signal Path Control Register

AIF3_RXD_CTRL

0x2E4

AIF3 Receiver Data Discarding Control Register

ADC_DIG_CTRL

0x300

ADC Digital Control Register

ADC_VOL_CTRL

0x304

ADC Volume Control Register

ADC_DBG_CTRL

0x308

ADC Debug Control Register

HMIC_CTRL1

0x310

HMIC Control 1 Register

HMIC_CTRL2

0x314

HMIC Control 2 Register

HMIC_STS

0x318

HMIC Status Register

DAC_DIG_CTRL

0x320

DAC Digital Control Register

DAC_VOL_CTRL

0x324

DAC Volume Control Register

DAC_DBG_CTRL

0x328

DAC Debug Control Register

DAC_MXR_SRC

0x330

DAC Digital Mixer Source Select Register

DAC_MXR_GAIN

0x334

DAC Digital Mixer Gain Control Register

AC_ADC_DAPLSTA

0x400

ADC DAP Left Status Register

AC_ADC_DAPRSTA

0x404

ADC DAP Right Status Register

AC_ADC_DAPLCTRL

0x408

ADC DAP Left Channel Control Register

AC_ADC_DAPRCTRL

0x40C

ADC DAP Right Channel Control Register

AC_ADC_DAPLTL

0x410

ADC DAP Left Target Level Register

AC_ADC_DAPRTL

0x414

ADC DAP Right Target Level Register

AC_ADC_DAPLHAC

0x418

ADC DAP Left High Average Coef Register

AC_ADC_DAPLLAC

0x41C

ADC DAP Left Low Average Coef Register

AC_ADC_DAPRHAC

0x420

ADC DAP Right High Average Coef Register

AC_ADC_DAPRLAC

0x424

ADC DAP Right Low Average Coef Register

AC_ADC_DAPLDT

0x428

ADC DAP Left Decay Time Register

AC_ADC_DAPLAT

0x42C

ADC DAP Left Attack Time Register

AC_ADC_DAPRDT

0x430

ADC DAP Right Decay Time Register

AC_ADC_DAPRAT

0x434

ADC DAP Right Attack Time Register

AC_ADC_DAPNTH

0x438

ADC DAP Noise Threshold Register

AC_ADC_DAPLHNAC

0x43C

ADC DAP Left Input Signal High Average Coef Register

AC_ADC_DAPLLNAC

0x440

ADC DAP Left Input Signal Low Average Coef Register

AC_ADC_DAPRHNAC

0x444

ADC DAP Right Input Signal High Average Coef Register

AC_ADC_DAPRLNAC

0x448

ADC DAP Right Input Signal Low Average Coef Register

AC_DAPHHPFC

0x44C

ADC DAP High HPF Coef Register

AC_DAPLHPFC

0x450

ADC DAP Low HPF Coef Register

AC_DAPOPT

0x454

ADC DAP Optimum Register

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AC_DAC_DAPCTRL

0x480

DAC DAP Control Register

AGC_ENA

0x4D0

AGC Enable Register

DRC_ENA

0x4D4

DRC Enable Register

SRC_BISTCR

0x4D8

SRC Bist control Register

SRC_BISTST

0x4DC

SRC Bist Status Register

SRC1_CTRL1

0x4E0

SRC1 Control 1 Register

SRC1_CTRL2

0x4E4

SRC1 Control 2 Register

SRC1_CTRL3

0x4E8

SRC1 Control 3 Register

SRC1_CTRL4

0x4EC

SRC1 Control 4 Register

SRC2_CTRL1

0x4F0

SRC2 Control 1 Register

SRC2_CTRL2

0x4F4

SRC2 Control 2 Register

SRC2_CTRL3

0x4F8

SRC2 Control 3 Register

SRC2_CTRL4

0x4FC

SRC2 Control 4 Register

AC_DRC0_HHPFC

0x600

DRC0 High HPF Coef Register

AC_DRC0_LHPFC

0x604

DRC0 Low HPF Coef Register

AC_DRC0_CTRL

0x608

DRC0 Control Register

AC_DRC0_LPFHAT

0x60C

DRC0 Left Peak Filter High Attack Time Coef Register

AC_DRC0_LPFLAT

0x610

DRC0 Left Peak Filter Low Attack Time Coef Register

AC_DRC0_RPFHAT

0x614

DRC0 Right Peak Filter High Attack Time Coef Register

AC_DRC0_RPFLAT

0x618

DRC0 Peak Filter Low Attack Time Coef Register

AC_DRC0_LPFHRT

0x61C

DRC0 Left Peak Filter High Release Time Coef Register

AC_DRC0_LPFLRT

0x620

DRC0 Left Peak Filter Low Release Time Coef Register

AC_DRC0_RPFHRT

0x624

DRC0 Right Peak filter High Release Time Coef Register

AC_DRC0_RPFLRT

0x628

DRC0 Right Peak filter Low Release Time Coef Register

AC_DRC0_LRMSHAT

0x62C

DRC0 Left RMS Filter High Coef Register

AC_DRC0_LRMSLAT

0x630

DRC0 Left RMS Filter Low Coef Register

AC_DRC0_RRMSHAT

0x634

DRC0 Right RMS Filter High Coef Register

AC_DRC0_RRMSLAT

0x638

DRC0 Right RMS Filter Low Coef Register

AC_DRC0_HCT

0x63C

DRC0 Compressor Theshold High Setting Register

AC_DRC0_LCT

0x640

DRC0 Compressor Slope High Setting Register

AC_DRC0_HKC

0x644

DRC0 Compressor Slope High Setting Register

AC_DRC0_LKC

0x648

DRC0 Compressor Slope Low Setting Register

0x64C

DRC0 Compressor High Output at Compressor Threshold
Register

AC_DRC0_LOPC

0x650

DRC0 Compressor Low Output at Compressor Threshold
Register

AC_DRC0_HLT

0x654

DRC0 Limiter Theshold High Setting Register

AC_DRC0_LLT

0x658

DRC0 Limiter Theshold Low Setting Register

AC_DRC0_HKl

0x65C

DRC0 Limiter Slope High Setting Register

AC_DRC0_LKl

0x660

DRC0 Limiter Slope Low Setting Register

AC_DRC0_HOPC

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AC_DRC0_HOPL

0x664

DRC0 Limiter High Output at Limiter Threshold

AC_DRC0_LOPL

0x668

DRC0 Limiter Low Output at Limiter Threshold

AC_DRC0_HET

0x66C

DRC0 Expander Theshold High Setting Register

AC_DRC0_LET

0x670

DRC0 Expander Theshold Low Setting Register

AC_DRC0_HKE

0x674

DRC0 Expander Slope High Setting Register

AC_DRC0_LKE

0x678

DRC0 Expander Slope Low Setting Register

AC_DRC0_HOPE

0x67C

DRC0 Expander High Output at Expander Threshold

AC_DRC0_LOPE

0x680

DRC0 Expander Low Output at Expander Threshold

AC_DRC0_HKN

0x684

DRC0 Linear Slope High Setting Register

AC_DRC0_LKN

0x688

DRC0 Linear Slope Low Setting Register

AC_DRC0_SFHAT

0x68C

DRC0 Smooth filter Gain High Attack Time Coef Register

AC_DRC0_SFLAT

0x690

DRC0 Smooth filter Gain Low Attack Time Coef Register

AC_DRC0_SFHRT

0x694

DRC0 Smooth filter Gain High Release Time Coef
Register

AC_DRC0_SFLRT

0x698

DRC0 Smooth filter Gain Low Release Time Coef Register

AC_DRC0_MXGHS

0x69C

DRC0 MAX Gain High Setting Register

AC_DRC0_MXGLS

0x6A0

DRC0 MAX Gain Low Setting Register

AC_DRC0_MNGHS

0x6A4

DRC0 MIN Gain High Setting Register

AC_DRC0_MNGLS

0x6A8

DRC0 MIN Gain Low Setting Register

AC_DRC0_EPSHC

0x6AC

DRC0 Expander Smooth Time High Coef Register

AC_DRC0_EPSLC

0x6B0

DRC0 Expander Smooth Time Low Coef Register

AC_DRC0_OPT

0x6AC

DRC0 Optimum Register

AC_DRC1_HHPFC

0x700

DRC1 High HPF Coef Register

AC_DRC1_LHPFC

0x704

DRC1 Low HPF Coef Register

AC_DRC1_CTRL

0x708

DRC1 Control Register

AC_DRC1_LPFHAT

0x70C

DRC1 Left Peak Filter High Attack Time Coef Register

AC_DRC1_LPFLAT

0x710

DRC1 Left Peak Filter Low Attack Time Coef Register

AC_DRC1_RPFHAT

0x714

DRC1 Right Peak Filter High Attack Time Coef Register

AC_DRC1_RPFLAT

0x718

DRC1 Peak Filter Low Attack Time Coef Register

AC_DRC1_LPFHRT

0x71C

DRC1 Left Peak Filter High Release Time Coef Register

AC_DRC1_LPFLRT

0x720

DRC1 Left Peak Filter Low Release Time Coef Register

AC_DRC1_RPFHRT

0x724

DRC1 Right Peak filter High Release Time Coef Register

AC_DRC1_RPFLRT

0x728

DRC1 Right Peak filter Low Release Time Coef Register

AC_DRC1_LRMSHAT

0x72C

DRC1 Left RMS Filter High Coef Register

AC_DRC1_LRMSLAT

0x730

DRC1 Left RMS Filter Low Coef Register

AC_DRC1_RRMSHAT

0x734

DRC1 Right RMS Filter High Coef Register

AC_DRC1_RRMSLAT

0x738

DRC1 Right RMS Filter Low Coef Register

AC_DRC1_HCT

0x73C

DRC1 Compressor Theshold High Setting Register

AC_DRC1_LCT

0x740

DRC1 Compressor Slope High Setting Register

AC_DRC1_HKC

0x744

DRC1 Compressor Slope High Setting Register

AC_DRC1_LKC

0x748

DRC1 Compressor Slope Low Setting Register

AC_DRC1_HOPC

0x74C

DRC1 Compressor High Output at Compressor Threshold

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Register
AC_DRC1_LOPC

0x750

DRC1 Compressor Low Output at Compressor Threshold
Register

AC_DRC1_HLT

0x754

DRC1 Limiter Theshold High Setting Register

AC_DRC1_LLT

0x758

DRC1 Limiter Theshold Low Setting Register

AC_DRC1_HKl

0x75C

DRC1 Limiter Slope High Setting Register

AC_DRC1_LKl

0x760

DRC1 Limiter Slope Low Setting Register

AC_DRC1_HOPL

0x764

DRC1 Limiter High Output at Limiter Threshold

AC_DRC1_LOPL

0x768

DRC1 Limiter Low Output at Limiter Threshold

AC_DRC1_HET

0x76C

DRC1 Expander Theshold High Setting Register

AC_DRC1_LET

0x770

DRC1 Expander Theshold Low Setting Register

AC_DRC1_HKE

0x774

DRC1 Expander Slope High Setting Register

AC_DRC1_LKE

0x778

DRC1 Expander Slope Low Setting Register

AC_DRC1_HOPE

0x77C

DRC1 Expander High Output at Expander Threshold

AC_DRC1_LOPE

0x780

DRC1 Expander Low Output at Expander Threshold

AC_DRC1_HKN

0x784

DRC1 Linear Slope High Setting Register

AC_DRC1_LKN

0x788

DRC1 Linear Slope Low Setting Register

AC_DRC1_SFHAT

0x78C

DRC1 Smooth filter Gain High Attack Time Coef Register

AC_DRC1_SFLAT

0x790

DRC1 Smooth filter Gain Low Attack Time Coef Register

AC_DRC1_SFHRT

0x794

DRC1 Smooth filter Gain High Release Time Coef
Register

AC_DRC1_SFLRT

0x798

DRC1 Smooth filter Gain Low Release Time Coef Register

AC_DRC1_MXGHS

0x79C

DRC1 MAX Gain High Setting Register

AC_DRC1_MXGLS

0x7A0

DRC1 MAX Gain Low Setting Register

AC_DRC1_MNGHS

0x7A4

DRC1 MIN Gain High Setting Register

AC_DRC1_MNGLS

0x7A8

DRC1 MIN Gain Low Setting Register

AC_DRC1_EPSHC

0x7AC

DRC1 Expander Smooth Time High Coef Register

AC_DRC1_EPSLC

0x7B0

DRC1 Expander Smooth Time Low Coef Register

AC_DRC1_OPT

0x7B4

DRC1 Optimum Register

HP_CTRL

0x00

Headphone Amplifier Control Register

OL_MIX_CTRL

0x01

Output Left Mixer Control Register

OR_MIX_CTRL

0x02

Output Right Mixer Control Register

EARPIECE_CTRL0

0x03

Earpiece Control Register 0

EARPIECE_CTRL1

0x04

Earpiece Control Register 1

LINEOUT_CTRL00x05

LINEOUT Control Register 0

LINEOUT_CTRL1

0x06

LINEOUT Control Register 1

MIC1_CTRL

0x07

MIC1 Control Register

MIC2_CTRL

0x08

MIC2 Control Register

LINEIN_CTRL

0x09

Linein Control Register

MIX_DAC_CTRL

0x0A

Mixer and DAC Control Register

L_ADCMIX_SRC

0x0B

Left ADC Mixer Control Register

R_ADCMIX_SRC

0x0C

Right ADC Mixer Control Register

Analog Domain Register

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ADC_CTRL

0x0D

ADC Control Register

HS_MBIAS_CTRL

0x0E

Headset Microphone Bias Control Register

APT_REG

0x0F

Analog Performance Tuning Register

OP_BIAS_CTRL00x10

OP BIAS Control Register 0

OP_BIAS_CTRL1

0x11

OP BIAS Control Register 1

ZC_VOL_CTRL

0x12

USB Bias & Volume Change Control Register

BIAS_CAL_DATA

0x13

Bias Calibration Data Register

BIAS_CAL_SET

0x14

Bias Calibration Set Data Register

BD_CAL_CTRL

0x15

Bias & DA16 Calibration Control Register

HP_PA_CTRL

0x16

Headphone PA Control Register

HP_CAL_CTRL

0x17

Headphone Calibration Control

RHP_CAL_DAT

0x18

Right Headphone Calibration DATERHP_CAL_SET

0x19

Right Headphone Calibration Setting

LHP_CAL_DAT

0x1A

Left Headphone Calibration DATELHP_CAL_SET

0x1B

Left Headphone Calibration Setting

MDET_CTRL

0x1C

Mic detect Control Register

JM_DET_CTRL

0x1D

Jack & Mic detect Control Register

PHOUT_CTRL

0x1E

Phone output Register

PHIN_CTRL

0x1F

Phone input Register

3.20.5. Audio Codec Register Description
3.20.5.1. 0x00 I2S_AP Control Register(Default Value: 0x00000000)
Offset: 0x00

Register Name: DA_CTL

Bit

R/W

Default/Hex

Description

31:9

/

/

/

8

R/W

0

SDO_EN
0: Disable
1: Enable

7

/

/

/

0

ASS
Audio sample select when TX FIFO under run
0: Sending zero
1: Sending last audio sample

0MS
Master Slave Select0: Master
1: Slave0

PCM
0: I2S Interface

6

5
4

R/W

R/W
R/W

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1: PCM Interface

3

2

1

0

R/W

R/W

R/W

R/W

0

LOOP
Loop back test
0: Normal mode
1: Loop back test
When set ‘1’, connecting the SDO with the SDI in Master mode.

0

TXEN
Transmitter Block Enable
0: Disable
1: Enable

0

RXEN
Receiver Block Enable
0: Disable
1: Enable

0

GEN
Globe Enable
A disable on this bit overrides any other block or channel enables andflushes all FIFOs.
0: Disable
1: Enable

3.20.5.2. 0x04 I2S_AP Format Register0(Default Value: 0x0000000C)
Offset: 0x04

Register Name: DA_FAT0

Bit

R/W

Default/Hex

Description

31:8

/

/

/

0

LRCP
Left/ Right Clock Parity
0: Normal
1: Inverted
In DSP/ PCM mode
0: MSB is available on 2nd BCLK rising edge after LRC rising edge
1: MSB is available on 1st BCLK rising edge after LRC rising edge

0

BCP
BCLK Parity
0: Normal
1: Inverted0SR
Sample Resolution
00: 16-bits
01: 20-bits
10: 24-bits
11: Reserved

7

6

5:4

R/W

R/W

R/W

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3:2

1:0

R/W

R/W

0x3

WSS
Word Select Size
00: 16 BCLK
01: 20 BCLK
10: 24 BCLK
11: 32 BCLK0

FMT
Serial Data Format
00: Standard I2S Format
01: Left Justified Format
10: Right Justified Format
11: Reserved

3.20.5.3. 0x08 I2S_AP Format Register1(Default Value: 0x00004020)
Offset: 0x08

Register Name: DA_FAT1

Bit

R/W

Default/Hex

Description

31:15

/

/

/

0x4

PCM_SYNC_PERIODPCM SYNC Period Clock Number
000: 16 BCLK period
001: 32 BCLK period
010: 64 BCLK period
011: 128 BCLK period
100: 256 BCLK period
Others : Reserved

0

PCM_SYNC_OUT
PCM Sync Out
0: Enable PCM_SYNC output in Master mode
1: Suppress PCM_SYNC whilst keeping PCM_CLK running. Some Codec
utilize this to enter a low power state.

0

PCM Out Mute
Write 1 force PCM_OUT to 00

MLS
MSB / LSB First Select0: MSB First
1: LSB First

0

SEXT
Sign Extend (only for 16 bits slot)
0: Zeros or audio gain padding at LSB position
1: Sign extension at MSB position
When writing the bit is 0, the unused bits are audio gain for 13-bit linear
sample and zeros padding for 8-bit companding sample.

14:12

11
10

9

8

R/W

R/W
R/W

R/W

R/W

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When writing the bit is 1, the unused bits are both sign extension.

7:6

5

4

3:2

1:0

R/W

R/W

R/W

R/W

R/W

0

SI
Slot Index
00: the 1st slot
01: the 2nd slot
10: the 3rd slot
11: the 4th slot

1

SW
Slot Width
0: 8 clocks width
1: 16 clocks width
Notes: For A-law or u-law PCM sample, if this bit is set to 1, eight zero bits
are following with PCM sample.

0

SSYNC
Short Sync Select0: Long Frame Sync
1: Short Frame Sync
It should be set ‘1’ for 8 clocks width slot.

0

RX_PDMPCM Data Mode00: 16-bits Linear PCM
01: 8-bits Linear PCM
10: 8-bits u-law
11: 8-bits A-law

0

TX_PDMPCM Data Mode00: 16-bits Linear PCM
01: 8-bits Linear PCM
10: 8-bits u-law
11: 8-bits A-law

3.20.5.4. 0x0C I2S_AP Interrupt Status Register(Default Value: 0x00000010)
Offset: 0x0C

Register Name: DA_ISTA

Bit

R/W

Default/Hex

Description

31:7

/

/

/

0

TXU_INTTX FIFO Under run Pending Interrupt
0: No Pending Interrupt
1: FIFO Under run Pending Interrupt

0

TXO_INTTX FIFO Overrun Pending Interrupt
0: No Pending Interrupt

6

5

R/W

R/W

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1: FIFO Overrun Pending Interrupt
Write ‘1’ to clear this interrupt

4

R/W

1

TXE_INTTX FIFO Empty Pending Interrupt
0: No Pending IRQ
1: FIFO Empty Pending Interrupt
Write ‘1’ to clear this interrupt or automatic clear if interrupt condition
fails.

3:2

/

/

/

0

RXU_INTRX FIFO Under run Pending Interrupt
0: No Pending Interrupt
1:FIFO Under run Pending Interrupt
Write 1 to clear this interrupt

0

RXO_INTRX FIFO Overrun Pending Interrupt
0: No Pending IRQ
1: FIFO Overrun Pending IRQ
Write ‘1’ to clear this interrupt

0

RXA_INTRX FIFO Data Available Pending Interrupt
0: No Pending IRQ
1: Data Available Pending IRQ
Write ‘1’ to clear this interrupt or automatic clear if interrupt condition
fails.

2

1

0

R/W

R/W

R/W

3.20.5.5. 0x10 I2S_AP RX FIFO Register(Default Value: 0x00000000)
Offset: 0x10
Bit

31:0

R/W

R

Register Name: DA_RXFIFODefault/Hex

Description0

RX_DATARX Sample
Host can get one sample by reading this register. The left channel sample
data is first and then the right channel sample.

3.20.5.6. 0x14 I2S_AP FIFO Control Register(Default Value: 0x000400F0)
Offset: 0x14

Register Name: DA_FCTL

Bit

R/W

Default/Hex

Description

31

R/W

0

HUB_EN
Audio Hub Enable

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0: Disable
1: Enable
30:26
25

/
R/W

/

/

0

FTX
Write ‘1’ to flush TX FIFO, self clear to ‘0’.

24

R/W

0

FRX
Write ‘1’ to flush RX FIFO, self clear to ‘0’.

23:19

/

/

/

18:12

R/W

0x40

TXTL
TX FIFO Empty Trigger Level
Interrupt and DMA request trigger level for TXFIFO normal condition
Trigger Level = TXTL

11:10

/

/

/

9:4

R/W

0xF

RXTL
RX FIFO Trigger Level
Interrupt and DMA request trigger level for RXFIFO normal condition
Trigger Level = RXTL + 1

3

/

/

/

0

TXIM
TX FIFO Input Mode (Mode 0, 1)
0: Valid data at the MSB of TXFIFO register
1: Valid data at the LSB of TXFIFO register
Example for 20-bits transmitted audio sample:
Mode 0: FIFO_I[23:0] = {TXFIFO[31:12], 4’h0}Mode 1: FIFO_I[23:0] = {TXFIFO[19:0], 4’h0}0

RXOM
RX FIFO Output Mode (Mode 0, 1, 2, 3)
00: Expanding ‘0’ at LSB of DA_RXFIFO register.
01: Expanding received sample sign bit at MSB of DA_RXFIFO register.
10: Truncating received samples at high half-word of DA_RXFIFO registerand low half-word of DA_RXFIFO register is filled by ‘0’.
11: Truncating received samples at low half-word of DA_RXFIFO registerand high half-word of DA_RXFIFO register is expanded by its sign bit.
Example for 20-bits received audio sample:
Mode 0: RXFIFO[31:0] = {FIFO_O[19:0], 12’h0}Mode 1: RXFIFO[31:0] = {12{FIFO_O[19]}, FIFO_O[19:0]}
Mode 2: RXFIFO[31:0] = {FIFO_O[19:4], 16’h0}Mode 3: RXFIFO[31:0] = {16{FIFO_O[19], FIFO_O[19:4]}

2

1:0

R/W

R/W

3.20.5.7. 0x18 I2S_AP FIFO Status Register(Default Value: 0x10800000)
Offset: 0x18
Bit

R/W

Register Name: DA_FSTA
Default/Hex

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System
31:29

/

/

/

28

R

1

TXE
TX FIFO Empty
0: No room for new sample in TX FIFO
1: More than one room for new sample in TX FIFO (>= 1 word)

27:24

/

/

/

23:16

R

0x80

TXE_CNTTX FIFO Empty Space Word Counter

15:9

/

/

/

8

R

0

RXA
RX FIFO Available
0: No available data in RX FIFO
1: More than one sample in RX FIFO (>= 1 word)

7

/

/

/

0

RXA_CNTRX FIFO Available Sample Word Counter

6:0

R

3.20.5.8. 0x1C I2S_AP DMA&Interrupt Control Register(Default Value: 0x00000000)
Offset: 0x1C

Register Name: DA_INT

Bit

R/W

Default/Hex

Description

31:8

/

/

/

0

TX_DRQ
TX FIFO Empty DRQ Enable
0: Disable
1: Enable

0

TXUI_EN
TX FIFO Under run Interrupt Enable
0: Disable
1: Enable

0

TXOI_EN
TX FIFO Overrun Interrupt Enable
0: Disable
1: Enable
When set to ‘1’, an interrupt happens when writing new audio data if TX
FIFO is full.

7

6

5

R/W

R/W

R/W

4

R/W

0

TXEI_EN
TX FIFO Empty Interrupt Enable
0: Disable
1: Enable

3

R/W

0

RX_DRQ
RX FIFO Data Available DRQ Enable

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0: Disable
1: Enable
When set to ‘1’, RXFIFO DMA Request line is asserted if Data is available
in RX FIFO.

2

1

0

R/W

R/W

R/W

0

RXUI_EN
RX FIFO Under run Interrupt Enable
0: Disable
1: Enable

0

RXOI_EN
RX FIFO Overrun Interrupt Enable
0: Disable
1: Enable

0

RXAI_EN
RX FIFO Data Available Interrupt Enable
0: Disable
1: Enable

3.20.5.9. 0x20 I2S_AP TX FIFO Register(Default Value: 0x00000000)
Offset: 0x20

Register Name: DA_TXFIFO

Bit

R/W

Default/Hex

Description

31:0

W

0X0

TX_DATA
Transmitting left, right channel sample data should be written thisregister one by one. The left channel sample data is first and then theright channel sample.

3.20.5.10.

0x24 I2S_AP Clock Divide Register(Default Value: 0x00000000)

Offset: 0x24

Register Name: DA_CLKD

Bit

R/W

Default/Hex

Description

31:8

/

/

/

0

MCLKO_EN
0: Disable MCLK Output
1: Enable MCLK Output
Notes: Whether in Slave or Master mode, when this bit is set to 1, MCLK
should be output.

0

BCLKDIVBCLK Divide Ratio from MCLK
000: Divide by 2 (BCLK = MCLK/2)
001: Divide by 4010: Divide by 6

7

6:4

R/W

R/W

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011: Divide by 8
100: Divide by 12
101: Divide by 16
110: Divide by 32
111: Divide by 64

3:0

R/W

3.20.5.11.

00x28 I2S_AP TX Counter Register(Default Value: 0x00000000)

Offset: 0x28
Bit

31:0

Register Name: DA_TXCNT

R/W

R/W

3.20.5.12.

Default/Hex

Description0

TX_CNT
TX Sample Counter
The audio sample number of sending into TXFIFO. When one sample isput into TXFIFO by DMA or by host IO, the TX sample counter register
increases by one. The TX sample counter register can be set to any initial
valve at any time. After been updated by the initial value, the counterregister should count on base of this initial value.

0x2C I2S_AP RX Counter Register(Default Value: 0x00000000)

Offset: 0x2C
Bit

31:0

MCLKDIVMCLK Divide Ratio from Audio PLL Output
0000: Divide by 1
0001: Divide by 20010: Divide by 40011: Divide by 6
0100: Divide by 8
0101: Divide by 12
0110: Divide by 16
0111: Divide by 24
1000: Divide by 32
1001: Divide by 48
1010: Divide by 64
Others : Reserved

R/W

R/W

Register Name: DA_RXCNT
Default/Hex

Description

0

RX_CNT
RX Sample Counter
The audio sample number of writing into RXFIFO. When one sample iswritten by I2S_AP Engine, the RX sample counter register increases by
one. The RX sample counter register can be set to any initial valve at any

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Systemtime. After been updated by the initial value, the counter register shouldcount on base of this initial value.

3.20.5.13.

0x30 I2S_AP TX Channel Select Register(Default Value: 0x00000001)

Offset: 0x30

Register Name: DA_TXCHSEL

Bit

R/W

Default/Hex

Description

31:3

/

/

/

1

TX_CHSELTX Channel Select0: 1-ch
1: 2-ch2: 3-ch
3: 4-ch

2:0

R/W

3.20.5.14.

0x34 I2S_AP TX Channel Mapping Register(Default Value: 0x76543210)

Offset: 0x34

Register Name: DA_TXCHMAP

Bit

R/W

Default/Hex

Description

31:15

/

/

/

14:12

R/W

3

TX_CH3_MAP
TX Channel3 Mapping
000: 1st sample
001: 2nd sample
010: 3rd sample
011: 4th sample
1xx: Reserved

11

/

/

/

10:8

R/W

2

TX_CH2_MAP
TX Channel2 Mapping
000: 1st sample
001: 2nd sample
010: 3rd sample
011: 4th sample
1xx: Reserved

7

/

/

/

6:4

R/W

1

TX_CH1_MAP
TX Channel1 Mapping
000: 1st sample
001: 2nd sample
010: 3rd sample

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011: 4th sample
1xx: Reserved
3

/

/

/

2:0

R/W

0

TX_CH0_MAP
TX Channel0 Mapping
000: 1st sample
001: 2nd sample
010: 3rd sample
011: 4th sample
1xx: Reserved

3.20.5.15.

0x38 I2S_AP RX Channel Select Register(Default Value: 0x00000001)

Offset: 0x38

Register Name: DA_RXCHSEL

Bit

R/W

Default/Hex

Description

31:3

/

/

/

1

RX_CHSEL
RX Channel Select0: 1-ch
1: 2-ch2: 3-ch
3: 4-chOthers: Reserved

2:0

R/W

3.20.5.16.

0x3C I2S_AP RX Channel Mapping Register(Default Value: 0x00003210)

Offset: 0x3C

Register Name: DA_RXCHMAP

Bit

R/W

Default/Hex

Description

31:15

/

/

/

14:12

R/W

3

RX_CH3_MAP
RX Channel3 Mapping
000: 1st sample
001: 2nd sample
010: 3rd sample
011: 4th sample
1xx: Reserved

11

/

/

/

10:8

R/W

2

RX_CH2_MAP
RX Channel2 Mapping
000: 1st sample
001: 2nd sample

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010: 3rd sample
011: 4th sample
1xx: Reserved
7

/

/

/

6:4

R/W

1

RX_CH1_MAP
RX Channel1 Mapping
000: 1st sample
001: 2nd sample
010: 3rd sample
011: 4th sample
1xx: Reserved

3

/

/

/

2:0

R/W

0

RX_CH0_MAP
RX Channel0 Mapping
000: 1st sample
001: 2nd sample
010: 3rd sample
011: 4th sample
1xx: Reserved

3.20.5.17.

0x200 Codec Reset Register(Default Value: 0x00000101)

Offset: 0x200

Register Name: Codec_RST

Bit

R/W

Default/Hex

Description

31:16

/

/

/

15:0

R/W

/

Reserved

3.20.5.18.

0x20C System Clock Control Register(Default Value: 0x00000000)

Offset: 0x20C

Register Name: SYSCLK_CTL

Bit

R/W

Default/Hex

Description

31:12

/

/

/

11

R/W

0x0

AIF1CLK_ENA
AIF1CLK Enable
0: Disable
1: Enable

10

R/W

0x0

Reserved

0x0

AIF1CLK_SRC
AIF1CLK Source Select
00: MLCK1
01: Reserved

9:8

R/W

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1X: pll2_1x

7

R/W

0x0

AIF2CLK_ENA
AIF2CLK Enable
0: Disable
1: Enable

6

R/W

0x0

Reserved

0x0

AIF2CLK_SRC
AIF2CLK Source Select
00: MLCK1
01: Reserved
1X: pll2_1x

5:4

R/W

3

R/W

0x0

SYSCLK_ENA
SYSCLK Enable
0: Disable
1: Enable

2:1

R/W

0x0

Reserved

0x0

SYSCLK_SRC
System Clock Source Select0: AIF1CLK
1: AIF2CLK

0

R/W

3.20.5.19.

0x210 Module Clock Control Register(Default Value: 0x00000000)

Offset: 0x210

Register Name: MOD_CLK_ENA

Bit

R/W

Default/Hex

Description

31:16

R/W

0x0

Reserved

0x0000Module clock enable control
0-Clock disable
1-Clock enable
BIT15-AIF1
BIT14-AIF2
BIT13-AIF3
BIT12-Reserved
BIT11-SRC1
BIT10-SRC2
BIT9-Reserved
BIT8-Reserved
BIT7-HPF & AGC
BIT6-HPF & DRC0
BIT5-HPF & DRC1
BIT4-Reserved
BIT3-ADC Digital
BIT2-DAC Digital

15:0

R/W

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BIT1-Reserved
BIT0-Reserved

3.20.5.20.

0x214 Module Reset Control Register(Default Value: 0x00000000)

Offset: 0x214

Register Name: MOD_RST_CTL

Bit

R/W

Default/Hex

Description

31:16

R/W

0x0

Reserved

0x0000Module reset control
0-Reset asserted
1-Reset de-asserted
BIT15-AIF1
BIT14-AIF2
BIT13-AIF3
BIT12-Reserved
BIT11-SRC1
BIT10-SRC2
BIT9-Reserved
BIT8-Reserved
BIT7-HPF & AGC
BIT6-HPF & DRC0
BIT5-HPF & DRC1
BIT4-Reserved
BIT3-ADC Digital
BIT2-DAC Digital
BIT1-Reserved
BIT0-Reserved

15:0

R/W

3.20.5.21.

0x218 System Sample rate & SRC Configuration Register(Default Value: 0x00000000)

Offset: 0x218

Register Name: SYS_SR_CTRL

Bit

R/W

Default/Hex

Description

31:16

/

/

/

0x0

AIF1_FSAIF1 Sample Rate
0000: 8KHz
0001: 11.025KHz
0010: 12KHz
0011: 16KHz
0100: 22.05KHz
0101: 24KHz

15:12

R/W

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0110: 32KHz
0111: 44.1KHz
1000: 48KHz
1001: 96KHz
1010: 192KHz
Other: Reserved

11:8

3

2

1

0

R/W

R/W

R/W

R/W

R/W

0x0

AIF2_FSAIF2 Sample Rate
0000: 8KHz
0001: 11.025KHz
0010: 12KHz
0011: 16KHz
0100: 22.05KHz
0101: 24KHz
0110: 32KHz
0111: 44.1KHz
1000: 48KHz
1001: 96KHz
1010: 192KHz
Other: Reserved

0x0

SRC1_ENA
SRC1 Enable. SRC1 Performs sample rate conversion of digital audio input
to the codec.
0: Disable
1: Enable

0x0

SRC1_SRC
From which the input data will come.
0: AIF1 DAC Timeslot 0
1: AIF2 DAC

0x0

SRC2_ENA
SRC2 Enable. SRC2 Performs sample rate conversion of digital audio
output from the codec.
0: Disable
1: Enable

0x0

SRC2_SRC
To which the converted data will be output.
0: AIF1 ADC Timeslot 0
1: AIF2 ADC

3.20.5.22.

0x21C System SRC Clock Source Select Register(Default Value: 0x00000000)

Offset: 0x21C

Register Name: SYS_SRC_CLK

Bit

R/W

Default/Hex

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Description
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31:2

1:0

/

R/W

3.20.5.23.

/

/

0x0

SRC_CLK_SLTSystem SRC module output clock source select
00: normal mode
01: src1 output sample rate select DAC clk
10: src2 input sample rate select ADC clk
11: reserved

0x220 System DVC Mode Select Register(Default Value: 0x00000000)

Offset: 0x220

Register Name: SYS_DVC_CLK

Bit

R/W

Default/Hex

Description

31:2

/

/

/

0x0

AIFDVC_FS_SEL
0 : DVC output to AIF sync
1 : normal

1:0

R/W

3.20.5.24.

0x240 AIF1 BCLK/LRCK Control Register(Default Value: 0x00000000)

Offset: 0x240
Bit

15

14

13

12:9

R/W

R/W

R/W

R/W

R/W

Register Name: AIF1CLK_CTRL
Default/Hex

Description

0x0

AIF1_MSTR_MOD
AIF1 Audio Interface mode select0 = Master mode
1 = Slave mode

0x0

AIF1_BCLK_INVAIF1 BCLK Polarity
0: Normal
1: Inverted

0x0

AIF1_LRCK_INVAIF1 LRCK Polarity
0: Normal
1: Inverted

0x0

AIF1_BCLK_DIV
Select the AIF1CLK/BCLK1 ratio
0000: AIF1CLK/1
0001: AIF1CLK/2
0010: AIF1CLK/40011: AIF1CLK/6
0100: AIF1CLK/8
0101: AIF1CLK/12

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0110: AIF1CLK/16
0111: AIF1CLK/24
1000: AIF1CLK/32
1001: AIF1CLK/48
1010: AIF1CLK/64
1011: AIF1CLK/96
1100: AIF1CLK/128
1101: AIF1CLK/192
1110: Reserved
1111: Reserved

8:6

5:4

3:2

1

0

R/W

R/W

R/W

R/W

R/W

3.20.5.25.

0x0

AIF1_LRCK_DIV
Select the BCLK1/LRCK ratio
000: 16001: 32010: 64011: 128
100: 256
1xx: Reserved

0x0

AIF1_WORD_SIZ
AIF1 digital interface word size
00: 8bit
01: 16bit
10: 20bit
11: 24bit

0x0

AIF1_DATA_FMT
AIF1 digital interface data format
00: I2S mode
01: Left mode
10: Right mode
11: DSP mode

0x0

DSP_MONO_PCM
DSP Mono mode select0: Stereo mode select
1: Mono mode select0x0

AIF1_TDMM_ENA
AIF1 TDM Mode enable
0: Disable
1: Enable

0x244 AIF1 ADCDAT Control Register(Default Value: 0x00000000)

Offset: 0x244
Bit

R/W

Register Name: AIF1_ADCDAT_CTRL
Default/Hex

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15

14

13

12

11:10

9:8

7:6

5:4

3

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0x0

AIF1_ADC0L_ENA
AIF1 ADC Timeslot 0 left channel enable
0: Disable
1: Enable

0x0

AIF1_ADC0R_ENA
AIF1 ADC Timeslot 0 right channel enable
0: Disable
1: Enable

0x0

AIF1_ADC1L_ENA
AIF1 ADC Timeslot 1 left channel enable
0: Disable
1: Enable

0x0

AIF1_ADC1R_ENA
AIF1 ADC Timeslot 1 right channel enable
0: Disable
1: Enable

0x0

AIF1_ADC0L_SRC
AIF1 ADC Timeslot 0 left channel data source select
00: AIF1 ADC0L
01: AIF1 ADC0R
10: (AIF1 ADC0L+AIF1 ADC0R)
11: (AIF1 ADC0L+AIF1 ADC0R)/2

0x0

AIF1_ADC0R_SRC
AIF1 ADC Timeslot 0 right channel data source select
00: AIF1 ADC0R
01: AIF1 ADC0L
10: (AIF1 ADC0L+AIF1 ADC0R)
11: (AIF1 ADC0L+AIF1 ADC0R)/2

0x0

AIF1_ADC1L_SRC
AIF1 ADC Timeslot 1 left channel data source select
00: AIF1 ADC1L
01: AIF1 ADC1R
10: (AIF1 ADC1L+AIF1 ADC1R)
11: (AIF1 ADC1L+AIF1 ADC1R)/2

0x0

AIF1_ADC1R_SRC
AIF1 ADC Timeslot 1 right channel data source select
00: AIF1 ADC1R
01: AIF1 ADC1L
10: (AIF1 ADC1L+AIF1 ADC1R)
11: (AIF1 ADC1L+AIF1 ADC1R)/2

0x0

AIF1_ADCP_ENA
AIF1 ADC Companding enable(8-bit mode only)
0: Disable
1: Enable

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2

1:0

R/W

R/W

3.20.5.26.

0x0

AIF1_ADCUL_ENA
AIF1 ADC Companding mode select0: A-law
1: u-law

0x0

AIF1_SLOT_SIZ
Select the slot size(only in TDM mode)
00: 8
01: 16
10: 32
11: Reserved

0x248 AIF1 DACDAT Control Register(Default Value: 0x00000000)

Offset: 0x248
Bit

15

14

13

12

11:10

9:8

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Register Name: AIF1_DACDAT_CTRL
Default/Hex

Description

0x0

AIF1_DAC0L_ENA
AIF1 DAC Timeslot 0 left channel enable
0: Disable
1: Enable

0x0

AIF1_DAC0R_ENA
AIF1 DAC Timeslot 0 right channel enable
0: Disable
1: Enable

0x0

AIF1_DAC1L_ENA
AIF1 DAC Timeslot 1 left channel enable
0: Disable
1: Enable

0x0

AIF1_DAC1R_ENA
AIF1 DAC Timeslot 1 right channel enable
0: Disable
1: Enable

0x0

AIF1_DAC0L_SRC
AIF1 DAC Timeslot 0 left channel data source select
00: AIF1 DAC0L
01: AIF1 DA0R
10: (AIF1 DAC0L+AIF1 DAC0R)
11: (AIF1 DAC0L+AIF1 DAC0R)/2

0x0

AIF1_DAC0R_SRC
AIF1 DAC Timeslot 0 right channel data source select
00: AIF1 DAC0R
01: AIF1 DAC0L
10: (AIF1 DAC0L+AIF1 DAC0R)
11: (AIF1 DAC0L+AIF1 DAC0R)/2

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7:6

5:4

3

R/W

R/W

R/W

0x0

AIF1_DAC1L_SRC
AIF1 DAC Timeslot 1 left channel data source select
00: AIF1 DAC1L
01: AIF1 DAC1R
10: (AIF1 DAC1L+AIF1 DAC1R)
11: (AIF1 DAC1L+AIF1 DAC1R)/2

0x0

AIF1_DAC1R_SRC
AIF1 DAC Timeslot 1 right channel data source select
00: AIF1 DAC1R
01: AIF1 DAC1L
10: (AIF1 DAC1L+AIF1 DAC1R)
11: (AIF1 DAC1L+AIF1 DAC1R)/2

0x0

AIF1_DACP_ENA
AIF1 DAC Companding enable(8-bit mode only)
00: Disable
01: Enable

2

R/W

0x0

AIF1_DACUL_ENA
AIF1 DAC Companding mode select0: A-law
1: u-law

1

R/W

0x0

Reserved

0x0

AIF1_LOOP_ENA
AIF1 loopback enable
0: No loopback
1: Loopback(ADCDAT1 data output to DACDAT1 data input)

0

R/W

3.20.5.27.

0x24C AIF1 Digital Mixer Source Select Register(Default Value: 0x00000000)

Offset: 0x24C

Register Name: AIF1_MXR_SRC

Bit

15:12

11:8

R/W

R/W

R/W

Default/Hex

Description

0x0

AIF1_ADC0L_MXL_SRC
AIF1 ADC Timeslot 0 left channel mixer source select0: Disable 1: Enable
Bit15: AIF1 DAC0L data
Bit14: AIF2 DACL data
Bit13: ADCL data
Bit12: AIF2 DACR data

0x0

AIF1_ADC0R_MXR_SRC
AIF1 ADC Timeslot 0 right channel mixer source select0: Disable 1: Enable
Bit11: AIF1 DAC0R data
Bit10: AIF2 DACR data
Bit9: ADCR data

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Bit8: AIF2 DACL data

7:6

R/W

0x0

AIF1_ADC1L_MXR_SRC
AIF1 ADC Timeslot 1 left channel mixer source select0: Disable 1: Enable
Bit7: AIF2 DACL data
Bit6: ADCL data

5:4

R/W

0x0

Reserved

3:2

R/W

0x0

AIF1_ADC1R_MXR_SRC
AIF1 ADC Timeslot 1 right channel mixer source select0: Disable 1: Enable
Bit3: AIF2 DACR data
Bit2: ADCR data

1:0

R/W

0x0

Reserved

3.20.5.28.

0x250 AIF1 Volume Control 1 Register(Default Value: 0x0000A0A0)

Offset: 0x250
Bit

15:8

7:0

R/W

R/W

R/W

Register Name: AIF1_VOL_CTRL1
Default/Hex

Description

0xA0

AIF1_ADC0L_VOL
AIF1 ADC Timeslot 0 left channel volume(-119.25dB To 71.25dB, 0.75dB/Step)
0x00: Mute0x01: -119.25dB………………
0x9F = -0.75dB
0xA0 = 0dB
0xA1 = 0.75dB………………
0xFF = 71.25dB

0xA0

AIF1_ADC0R_VOL
AIF1 ADC Timeslot 0 right channel volume(-119.25dB To 71.25dB, 0.75dB/Step)
0x00: Mute0x01: -119.25dB………………
0x9F = -0.75dB
0xA0 = 0dB
0xA1 = 0.75dB………………
0xFF = 71.25dB

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3.20.5.29.

0x254 AIF1 Volume Control 2 Register(Default Value: 0x0000A0A0)

Offset: 0x254
Bit

15:8

7:0

Register Name: AIF1_VOL_CTRL2

R/W

R/W

R/W

3.20.5.30.

Default/Hex

Description

0xA0

AIF1_ADC1L_VOL
AIF1 ADC Timeslot 1 left channel volume(-119.25dB To 71.25dB, 0.75dB/Step)
0x00: Mute0x01: -119.25dB………………
0x9F = -0.75dB
0xA0 = 0dB
0xA1 = 0.75dB………………
0xFF = 71.25dB

0xA0

AIF1_ADC1R_VOL
AIF1 ADC Timeslot 1 right channel volume(-119.25dB To 71.25dB, 0.75dB/Step)
0x00: Mute0x01: -119.25dB………………
0x9F = -0.75dB
0xA0 = 0dB
0xA1 = 0.75dB………………
0xFF = 71.25dB

0x258 AIF1 Volume Control 3 Register(Default Value: 0x0000A0A0)

Offset: 0x258
Bit

15:8

R/W

R/W

Register Name: AIF1_VOL_CTRL3
Default/Hex

Description

0xA0

AIF1_DAC0L_VOL
AIF1 DAC Timeslot 0 left channel volume(-119.25dB To 71.25dB, 0.75dB/Step)
0x00: Mute0x01: -119.25dB………………
0x9F = -0.75dB
0xA0 = 0dB
0xA1 = 0.75dB………………
0xFF = 71.25dB

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7:0

R/W

3.20.5.31.

0xA0

0x25C AIF1 Volume Control 4 Register(Default Value: 0x0000A0A0)

Offset: 0x25C
Bit

15:8

7:0

AIF1_DAC0R_VOL
AIF1 DAC Timeslot 0 right channel volume(-119.25dB To 71.25dB, 0.75dB/Step)
0x00: Mute0x01: -119.25dB………………
0x9F = -0.75dB
0xA0 = 0dB
0xA1 = 0.75dB………………
0xFF = 71.25dB

R/W

R/W

R/W

Register Name: AIF1_VOL_CTRL4
Default/Hex

Description

0xA0

AIF1_DAC0L_VOL
AIF1 DAC Timeslot 0 left channel volume(-119.25dB To 71.25dB, 0.75dB/Step)
0x00: Mute0x01: -119.25dB………………
0x9F = -0.75dB
0xA0 = 0dB
0xA1 = 0.75dB………………
0xFF = 71.25dB

0xA0

AIF1_DAC1R_VOL
AIF1 DAC Timeslot 1 right channel volume(-119.25dB To 71.25dB, 0.75dB/Step)
0x00: Mute0x01: -119.25dB………………
0x9F = -0.75dB
0xA0 = 0dB
0xA1 = 0.75dB………………
0xFF = 71.25dB

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3.20.5.32.

0x260 AIF1 Digital Mixer Gain Control Register(Default Value: 0x00000000)

Offset: 0x260
Bit

15:12

11:8

Register Name: AIF1_MXR_GAIN

R/W

R/W

R/W

Default/Hex

Description

0x0

AIF1_ADC0L_MXR_GAIN
AIF1 ADC Timeslot 0 left channel mixer gain control
0: 0dB 1: -6dB
Bit15: AIF1 DAC0L data
Bit14: AIF2 DACL data
Bit13: ADCL data
Bit12: AIF2 DACR data

0x0

AIF1_ADC0R_MXR_GAIN
AIF1 ADC Timeslot 0 right channel mixer gain control
0: 0dB 1: -6dB
Bit11: AIF1 DAC0R data
Bit10: AIF2 DACR data
Bit9: ADCR data
Bit8: AIF2 DACL data

7:6

R/W

0x0

AIF1_ADC1L_MXR_GAIN
AIF1 ADC Timeslot 1 left channel mixer gain control
0: 0dB 1: -6dB
Bit7: AIF2 DACL data
Bit6: ADCL data

5:4

R/W

0x0

Reserved

3:2

R/W

0x0

AIF1_ADC1R_MXR_GAIN
AIF1 ADC Timeslot 1 right channel mixer gain control
0: 0dB 1: -6dB
Bit3: AIF2 DACR data
Bit2: ADCR data

1:0

R/W

0x0

Reserved

3.20.5.33.

0x264 AIF1 Receiver Data Discarding Control Register(Default Value: 0x00000000)

Offset: 0x264

Register Name: AIF1_RXD_CTRL

Bit

R/W

Default/Hex

Description

15:8

R/W

0x0

After data receiving progress begins, the first N-data will be discarded. N
defined as follows:
0x00: None discarded
0x01: 1-data discarded...
0xFF: 255-data discarded

7:0

R/W

0x0

Reserved

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3.20.5.34.

0x280 AIF2 BCLK/LRCK Control Register(Default Value: 0x00000000)

Offset: 0x280
Bit

15

14

13

12:9

R/W

R/W

R/W

R/W

R/W

Register Name: AIF2_CLK_CTRL
Default/Hex

Description

0x0

AIF2_MSTR_MOD
AIF2 Audio Interface mode select0 = Master mode
1 = Slave mode

0x0

AIF2_BCLK_INVAIF2 BCLK Polarity
0: Normal
1: Inverted

0x0

AIF2_LRCK_INVAIF2 LRCK Polarity
0: Normal
1: Inverted

0x0

AIF2_BCLK_DIV
Select the AIF2CLK/BCLK2 ratio
0000: AIF2CLK/1
0001: AIF2CLK/2
0010: AIF2CLK/40011: AIF2CLK/6
0100: AIF2CLK/8
0101: AIF2CLK/12
0110: AIF2CLK/16
0111: AIF2CLK/24
1000: AIF2CLK/32
1001: AIF2CLK/48
1010: AIF2CLK/64
1011: AIF2CLK/96
1100: AIF2CLK/128
1101: AIF2CLK/192
1110: Reserved
1111: Reserved

8:6

R/W

0x0

AIF2_LRCK_DIV
Select the BCLK2/LRCK2 ratio
000: 16001: 32010: 64011: 128
100: 256
1xx: Reserved

5:4

R/W

0x0

AIF2_WORD_SIZ
AIF2 digital interface world length

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00: 8bit
01: 16bit
10: 20bit
11: 24bit

3:2

R/W

0x0

AIF2_DATA_FMT
AIF digital interface data format
00: I2S mode
01: Left mode
10: Right mode
11: DSP mode

1

R/W

0x0

AIF2_MONO_PCM
AIF2 Mono PCM mode select0: Stereo mode select
1: Mono mode select

0

R/W

0x0

Reserved

3.20.5.35.

0x284 AIF2 ADCDAT Control Register(Default Value: 0x00000000)

Offset: 0x284
Bit

15

R/W

R/W

Register Name: AIF2_ADCDAT_CTRL
Default/Hex

Description

0x0

AIF2_ADCL_EN
AIF2 ADC left channel enable
0: Disable
1: Enable

14

R/W

0x0

AIF2_ADCR_EN
AIF2 ADC right channel enable
0: Disable
1: Enable

13:12

R/W

0x0

Reserved

0x0

AIF2_ADCL_SRC
AIF2 ADC left channel data source select
00: AIF2 ADCL
01: AIF2 ADCR
10: (AIF2 ADCL+AIF2 ADCR)
11: (AIF2 ADCL+AIF2 ADCR)/2

11:10

R/W

9:8

R/W

0x0

AIF2_ADCR_SRC
AIF2 ADC right channel data source select
00: AIF2 ADCR
01: AIF2 ADCL
10: (AIF2 ADCL+AIF2 ADCR)
11: (AIF2 ADCL+AIF2 ADCR)/2

7:4

R/W

0x0

Reserved

3

R/W

0x0

AIF2_ADCP_ENA

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AIF2 ADC Companding enable(8-bit mode only)
00: Disable
01: Enable

2

R/W

0x0

AIF2_ADCUL_ENA
AIF2 ADC Companding mode select0: A-law
1: u-law

1

/

/

/

0x0

AIF2_LOOP_EN
AIF2 loopback enable
0: No loopback
1: Loopback(ADCDAT2 data output to DACDAT2 data input)

0

R/W

3.20.5.36.

0x288 AIF2 DACDAT Control Register(Default Value: 0x00000000)

Offset: 0x288
Bit

15

R/W

R/W

Register Name: AIF2_DACDAT_CTRL
Default/Hex

Description

0x0

AIF2_DACL_ENA
AIF2 DAC left channel enable
0: Disable
1: Enable

14

R/W

0x0

AIF2_DACR_ENA
AIF2 DAC right channel enable
0: Disable
1: Enable

13:12

R/W

0x0

Reserved

0x0

AIF2_DACL_SRC
AIF2 DAC left channel data source select
00: AIF2 DACL
01: AIF2 DACR
10: (AIF2 DACL+AIF2 DACR)
11: (AIF2 DACL+AIF2 DACR)/2

11:10

R/W

9:8

R/W

0x0

AIF2_DACR_SRC
AIF2 DAC right channel data source select
00: AIF2 DACR
01: AIF2 DACL
10: (AIF2 DACL+AIF2 DACR)
11: (AIF2 DACL+AIF2 DACR)/2

7:4

R/W

0x0

Reserved

0x0

AIF2_DACP_ENA
AIF2 DAC Companding enable(8-bit mode only)
00: Disable
01: Enable

3

R/W

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2

R/W

0x0

AIF2_DACUL_ENA
AIF2 DAC Companding mode select0: A-law
1: u-law

1

R/W

0x0

Reserved

0

R/W

0x0

/

3.20.5.37.

0x28C AIF2 Digital Mixer Source Select Register(Default Value: 0x00000000)

Offset: 0x28C

Register Name: AIF2_MXR_SRC

Bit

15:12

R/W

R/W

Default/Hex

Description

0x0

AIF2_ADCL_MXR_SRC
AIF2 ADC left channel mixer source select0: Disable 1:Enable
Bit15: AIF1 DAC0L data
Bit14: AIF1 DAC1L data
Bit13: AIF2 DACR data
Bit12: ADCL data

11:8

R/W

0x0

AIF2_ADCR_MXR_SRC
AIF2 ADC right channel mixer source select0: Disable 1:Enable
Bit11: AIF1 DA0R data
Bit10: AIF1 DA1R data
Bit9: AIF2 DACL data
Bit8: ADCR data

7:0

R/W

0x0

Reserved

3.20.5.38.

0x290 AIF2 Volume Control 1 Register(Default Value: 0x0000A0A0)

Offset: 0x290
Bit

15:8

R/W

R/W

Register Name: AIF2_VOL_CTRL1
Default/Hex

Description

0xA0

AIF2_ADCL_VOL
AIF2 ADC left channel volume(-119.25dB To 71.25dB, 0.75dB/Step)
0x00: Mute0x01: -119.25dB………………
0x9F = -0.75dB
0xA0 = 0dB
0xA1 = 0.75dB………………

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0xFF = 71.25dB

7:0

R/W

3.20.5.39.

0xA0

0x298 AIF2 Volume Control 2 Register(Default Value: 0x0000A0A0)

Offset: 0x298
Bit

15:8

7:0

AIF2_ADCR_VOL
AIF2 ADC right channel volume(-119.25dB To 71.25dB, 0.75dB/Step)
0x00: Mute0x01: -119.25dB………………
0x9F = -0.75dB
0xA0 = 0dB
0xA1 = 0.75dB………………
0xFF = 71.25dB

R/W

R/W

R/W

Register Name: AIF2_VOL_CTRL2
Default/Hex

Description

0xA0

AIF2_ADCL_VOL
AIF2 ADC left channel volume(-119.25dB To 71.25dB, 0.75dB/Step)
0x00: Mute0x01: -119.25dB………………
0x9F = -0.75dB
0xA0 = 0dB
0xA1 = 0.75dB………………
0xFF = 71.25dB

0xA0

AIF2_DACR_VOL
AIF2 DAC right channel volume(-119.25dB To 71.25dB, 0.75dB/Step)
0x00: Mute0x01: -119.25dB………………
0x9F = -0.75dB
0xA0 = 0dB
0xA1 = 0.75dB………………
0xFF = 71.25dB

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3.20.5.40.

0x2A0 AIF2 Digital Mixer Gain Control Register(Default Value: 0x00000000)

Offset: 0x2A0
Bit

15:12

Register Name: AIF2_MXR_GAIN

R/W

R/W

Default/Hex

Description

0x0

AIF2_ADCL_MXR_GAIN
AIF2 ADC left channel mixer gain control
0: 0dB 1: -6dB
Bit15: AIF1 DAC0L data
Bit14: AIF1 DAC1L data
Bit13: AIF2 DACR data
Bit12: ADCL data

11:8

R/W

0x0

AIF2_ADCR_MXR_GAIN
AIF2 ADC right channel mixer gain control
0: 0dB 1: -6dB
Bit11: AIF1 DAC0R data
Bit10: AIF1 DAC1R data
Bit9: AIF2 DACL data
Bit8: ADCR data

7:0

R/W

0x0

Reserved

3.20.5.41.

0x2A4 AIF2 Receiver Data Discarding Control Register(Default Value: 0x00000000)

Offset: 0x2A4

Register Name: AIF2_RXD_CTRL

Bit

R/W

Default/Hex

Description

15:8

R/W

0x0

After data receiving progress begins, the first N-data will be discarded. N
defined as follows:
0x00: None discarded
0x01: 1-data discarded...
0xFF: 255-data discarded

7:0

R/W

0x0

Reserved

3.20.5.42.

0x2C0 AIF3 BCLK/LRCK Control Register(Default Value: 0x00000000)

Offset: 0x2C0

Register Name: AIF3_CLK_CTRL

Bit

R/W

Default/Hex

Description

15

R/W

0x0

Reserved

0x0

AIF3_BCLK_INV
AIF3 BCLK Polarity
0: Normal
1: Inverted

14

R/W

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13

R/W

0x0

AIF3_LRCK_INV
AIF3 LRCK Polarity
0: Normal
1: Inverted

12:6

R/W

0x0

Reserved

5:4

R/W

0x0

AIF3_WORD_SIZ
AIF3 digital interface world length
00: 8bit
01: 16bit
10: 20bit
11: 24bit

3:2

R/W

0x0

Reserved

0x0

AIF3_CLOCK_SRC
AIF3 BCLK/LRCK source control
0: BCLK/LRCK Come from AIF1
1: BCLK/LRCK Come from AIF2
2: BCLK/LRCK is generated by AIF3, and the source clock is AIF1CLK
3: Reserved

1:0

R/W

3.20.5.43.

0x2C4 AIF3 ADCDAT Control Register(Default Value: 0x00000000)

Offset: 0x2C4

Register Name: AIF3_ADCDAT_CTRL

Bit

R/W

Default/Hex

Description

15:4

R/W

0x0

Reserved

0x0

AIF3_ADCP_ENA
AIF3 ADC Companding enable
00: Disable
01: Enable

3

R/W

2

R/W

0x0

AIF3_ADUL_ENA
AIF3 ADC Companding mode select0: A-law
1: u-law

1:0

R/W

0x0

Reserved

3.20.5.44.

0x2C8 AIF3 DACDAT Control Register(Default Value: 0x00000000)

Offset: 0x2C8

Register Name: AIF3_DACDAT_CTRL

Bit

R/W

Default/Hex

Description

15:4

R/W

0x0

Reserved

3

R/W

0x0

AIF3_DACP_ENA
AIF3 DAC Companding enable(8-bit mode only)

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00: Disable
01: Enable

2

R/W

0x0

AIF3_DAUL_ENA
AIF3 DAC Companding mode select
00: u-law
01: A-law

1

R/W

0x0

Reserved

0x0

AIF3_LOOP_ENA
AIF3 loopback enable
0: No loopback
1: Loopback(ADCDAT3 data output to DACDAT3 data input)

0

R/W

3.20.5.45.

0x2CC AIF3 Signal Path Control Register(Default Value: 0x00000000)

Offset: 0x2CC

Register Name: AIF3_SGP_CTRL

Bit

R/W

Default/Hex

Description

15:12

R/W

0x0

Reserved

0x0

AIF3_ADC_SRC
AIF3 PCM output source select00: None
01: AIF2 ADC left channel
10: AIF2 ADC right channel
11: Reserved

0x0

AIF2_DAC_SRC
AIF2 DAC input source select
00: Left and right inputs from AIF2
01: Left input from AIF3; Right input from AIF2
10: Left input from AIF2; Right input from AIF3
11: Reserved

11:10

9:8

R/W

R/W

7

R/W

0x0

AIF3_PINS_TRI
AIF3 Pins Tri-state Control
0 = AIF3 pins operate normally
1 = Tri-state all AIF3 interface pins

6:4

R/W

0x0

reserved

3

R/W

0x0

reserved

2

R/W

0x0

reserved

1

R/W

0x0

reserved

0

R/W

0x0

reserved

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3.20.5.46.

0x2E4 AIF3 Receiver Data Discarding Control Register(Default Value: 0x00000000)

Offset: 0x2E4

Register Name: AIF3_RXD_CTRL

Bit

R/W

Default/Hex

Description

15:8

R/W

0x0

After data receiving progress begins, the first N-data will be discarded. N
defined as follows:
0x00: None discarded
0x01: 1-data discarded...
0xFF: 255-data discarded

7:0

R/W

0x0

Reserved

3.20.5.47.

0x300 ADC Digital Control Register(Default Value: 0x00000000)

Offset: 0x300
Bit

15

14

R/W

R/W

R/W

Register Name: ADC_DIG_CTRL
Default/Hex

Description

0x0

ENAD
ADC Digital part enable
0: Disable
1: Enable

0x0

ENDM
Digital microphone enable
0: Analog ADC mode
1:

13

R/W

0x0

ADFIR32
Enable 32-tap FIR filter
0: 64-tap
1: 32-tap

12:5

R/W

0x0

Reserved

0x0

DOSR
Digital Microphone Oversample Rate Select0：128fs
1：64fs0x0

ADOUT_DTS
ADC Delay Time For transmitting data after ENAD
00:5ms01:10ms
10:20ms
11:30ms

0x0

ADOUT_DLY
ADC Delay Function enable for transmitting data after ENAD
0: Disable

4

3:2

1

R/W

R/W

R/W

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1: Enable

0R/W

3.20.5.48.

0x00x304 ADC Volume Control Register(Default Value: 0x0000A0A0)

Offset: 0x304
Bit

15:8

7:0

Register Name: ADC_VOL_CTRL

R/W

R/W

R/W

3.20.5.49.

Default/Hex

Description

0xA0

ADC_VOL_L
ADC left channel volume(-119.25dB To 71.25dB, 0.75dB/Step)
0x00: Mute0x01: -119.25dB………………
0x9F = -0.75dB
0xA0 = 0dB
0xA1 = 0.75dB………………
0xFF = 71.25dB

0xA0

ADC_VOL_R
ADC left channel volume(-119.25dB To 71.25dB, 0.75dB/Step)
0x00: Mute0x01: -119.25dB………………
0x9F = -0.75dB
0xA0 = 0dB
0xA1 = 0.75dB………………
0xFF = 71.25dB

0x308 ADC Debug Control Register(Default Value: 0x00000000)

Offset: 0x308
Bit

15

DOSR
Digital Microphone Oversampling Rate
0:64 fs
1:128fs

R/W

R/W

Register Name: ADC_DBG_CTRL
Default/Hex

Description

0x0

ADSW
ADC input channel swap enable
0: Disable
1: Enable

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14

R/W

0x0

Reserved

13:12

R/W

0x0

/

11:3

R/W

0x0

Reserved
Interface between ADDA digital part and ADDA analog part debug control.






2:0

R/W

0x0





A64 User Manual(Revision 1.0)

NormalNormalBCLK2/LRCK2/ADCDAT2/DACDAT2
BCLK3/LRCK3/ADCDAT3/DACDAT3
is multiplexed as follows:
BCLK2

CKAD_A input to ADC analog part

LRCK2

NormalADCDAT2

ADIN_L[1] output from ADC analog part

DACDAT2

ADIN_L[0] output from ADC analog part

BCLK3

CKAD_A output from ADC digital part

LRCK3

NormalADCDAT3

ADIN_L/R[1] input to ADC digital part

DACDAT3

ADIN_L/R[0] input to ADC digital part

BCLK2/LRCK2/ADADAT2/DACDAT2
BCLK3/LRCK3/ADCDAT3/DACDAT3
is multiplexed as follows:
BCLK2

CKAD_A input to ADC analog part

LRCK2

NormalADCDAT2

ADIN_R[1] output from ADC analog part

DACDAT2

ADIN_R[0] output from ADC analog part

BCLK3

CKAD_A output from ADC digital part

LRCK3

NormalADCDAT3

ADIN_L/R[1] input to ADC digital part

DACDAT3

ADIN_L/R[0] input to ADC digital part

BCLK2/LRCK2/ADADAT2/DACDAT2
BCLK3/LRCK3/ADCDAT3/DACDAT3
is multiplexed as follows:
BCLK2

CKDA_A output from DAC digital partLRCK2

DAOUT_L[6] output from DAC digital part

ADCDAT2

DAOUT_L[5] output from DAC digital part

DACDAT2

DAOUT_L[4] output from DAC digital part

BCLK3

DAOUT_L[3] output from DAC digital part

LRCK3

DAOUT_L[2] output from DAC digital part

ADCDAT3

DAOUT_L[1] output from DAC digital part

DACDAT3

DAOUT_L[0] output from DAC digital part

BCLK2/LRCK2/ADADAT2/DACDAT2
BCLK3/LRCK3/ADCDAT3/DACDAT3
is multiplexed as follows:

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System

3.20.5.50.

BCLK2

CKDA_A output from DAC digital partLRCK2

DAOUT_R[6] output from DAC digital part

ADCDAT2

DAOUT_R[5] output from DAC digital part

DACDAT2

DAOUT_R[4] output from DAC digital part

BCLK3

DAOUT_R[3] output from DAC digital part

LRCK3

DAOUT_R[2] output from DAC digital part

ADCDAT3

DAOUT_R[1] output from DAC digital part

DACDAT3

DAOUT_R[0] output from DAC digital part

BCLK2/LRCK2/ADADAT2/DACDAT2
BCLK3/LRCK3/ADCDAT3/DACDAT3
is multiplexed as follows:
BCLK2

CKDA_A input to DAC analog partLRCK2

DAOUT_L/R[6] input to DAC analog part

ADCDAT2

DAOUT_L/R[5] input to DAC analog part

DACDAT2

DAOUT_L/R[4] input to DAC analog part

BCLK3

DAOUT_L/R[3] input to DAC analog part

LRCK3

DAOUT_L/R[2] input to DAC analog part

ADCDAT3

DAOUT_L/R[1] input to DAC analog part

DACDAT3

DAOUT_L/R[0] input to DAC analog part

BCLK2/LRCK2/ADADAT2/DACDAT2
BCLK3/LRCK3/ADCDAT3/DACDAT3
is multiplexed as follows:
BCLK2

CKDA_A input to DAC analog partLRCK2

DAOUT_L/R[6] input to DAC analog part

ADCDAT2

DAOUT_L/R[5] input to DAC analog part

DACDAT2

DAOUT_L/R[4] input to DAC analog part

BCLK3

DAOUT_L/R[3] input to DAC analog part

LRCK3

DAOUT_L/R[2] input to DAC analog part

ADCDAT3

DAOUT_L/R[1] input to DAC analog part

DACDAT3

DAOUT_L/R[0] input to DAC analog part

0x310 HMIC Control 1 Register(Default Value: 0x00000020)

Offset: 0x310

Register Name: HMIC_CTRL1

Bit

R/W

Default/Hex

Description

15:12

R/W

0x0

HMIC_M
Debounce when the MIC Key down or up.

11:8

R/W

0x0

Reserved to 0xf

7

/

/

/

0x1

MDATA_Threshold_Debounce
00:0
01:1

6:5

R/W

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10:2
11: Reserve(default 1)

4

R/W

0x0

JACK_IN_IRQ_EN
MIC Detect Interrupt Set
0 : disable
1 : enable

3

R/W

0x0

JACK_OUT_IRQ_EN
MIC Detect Interrupt Set
0 : disable
1 : enable

2:1

/

/

/

0x0

MIC_DET_IRQ_EN
MIC Detect Interrupt Set
0:disable
1:enable

0

R/W

3.20.5.51.

0x314 HMIC Control 2 Register(Default Value: 0x00000000)

Offset: 0x314
Bit

Register Name: HMIC_CTRL2

R/W

Default/Hex

Description

15:14

R/W

0x0

HMIC_SAMPLE_SELECT
Down Sample Setting Select00 : Down by 1, 128Hz
01 : Down by 2, 64Hz
10 : Down by 4, 32Hz
11 : Down by 8, 16Hz

13

/

/

/

12:8

R/W

0x0

MDATA_Threshold
MIC DATA De-Bounce DATAHMIC_SF
Hmic Smooth Filter setting
00: by pass
01: (x1+x2)/2
10: (x1+x2+x3+x4)/4
11: (x1+x2+x3+x4+x5+x6+x7+x8)/8

7:6

R/W

0x0

5:0

/

/

3.20.5.52.

0x318 HMIC Status Register(Default Value: 0x00000000)

Offset: 0x318
Bit

R/W

Register Name: HMIC_STS
Default/Hex

A64 User Manual(Revision 1.0)

Description

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System

15

R/W

0x1

MDATA_Threshold_EN
0 : The MIC Threshold Data write by user
1 : The MIC Threshold Data is auto write

14:13

R/W

0x3

MDATA_DISCARD
After MIC DATA data receiving, the first N-data will be discarded. N
defined as follows:
00 ：0; None discarded
01 ：1; 1-data discarded
10 ：2; 2-data discarded
11 ：4; 4-data discarded

12:8

R

0x0

HMIC_DATAHMIC Average Data

7

/

/

/

6

R/W

0x0

Jack Detect Status
0:Not MIC/Accessory present
1:MIC/Accessory is present(impedance is < 30K ohm)

5

/

/

/

0x0

JACK_DET_OIRQJack output detect pending interrupt
0: No Pending IRQ
1:Pending IRQ
Writing 1 clear pending

4

R/W

3

R/W

0x0

JACK_DET_IIRQJack input detect pending interrupt
0: No Pending IRQ
1: Pending IRQ
Writing 1 clear pending

2:1

/

/

/

0x0

MIC_DET_ST.
MIC Detect Pending interrupt
0:No pending IRQ
1:Pending IRQ
Writing 1 clear pending

0

R/W

3.20.5.53.

0x320 DAC Digital Control Register(Default Value: 0x00000000)

Offset: 0x320
Bit

R/W

Register Name: DAC_DIG_CTRL
Default/Hex

Description

15

R/W

0x0

ENDA.
DAC Digital Part Enable
0: Disabe
1: Enable

14

R/W

0x0

ENHPF

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System
HPF Function Enable
0: Enable
1: Disable

13

R/W

0x0

DAFIR32
Enable 32-tap FIR filter
0: 64-tap
1: 32-tap

12

R/W

0x0

Reserved

11:8

R/W

0x0

MODQU
Internal DAC Quantization Levels
Levels=[7*(21+MODQU[3:0])]/128
Default levels=7*21/128=1.15

7:0

R/W

0x0

Reserved

3.20.5.54.

0x324 DAC Volume Control Register(Default Value: 0x0000A0A0)

Offset: 0x324
Bit

15:8

7:0

R/W

R/W

R/W

Register Name: DAC_VOL_CTRL
Default/Hex

Description

0xA0

DAC_VOL_L
DAC left channel volume(-119.25dB To 71.25dB, 0.75dB/Step)
0x00: Mute0x01: -119.25dB………………
0x9F = -0.75dB
0xA0 = 0dB
0xA1 = 0.75dB………………
0xFF = 71.25dB

0xA0

DAC_VOL_R
DAC right channel volume(-119.25dB To 71.25dB, 0.75dB/Step)
0x00: Mute0x01: -119.25dB………………
0x9F = -0.75dB
0xA0 = 0dB
0xA1 = 0.75dB………………
0xFF = 71.25dB

A64 User Manual(Revision 1.0)

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3.20.5.55.

0x328 DAC Debug Control Register(Default Value: 0x00000000)

Offset: 0x328
Bit

15

14

Register Name: DAC_DBG_CTRL

R/W

R/W

R/W

Default/Hex

Description

0x0

DASW
DAC output channel swap enable
0:Disable
1:Enable

0x0

ENDWA_NDWA Function Disable
0: Enable
1: Disable

13

R/W

0x0

DAC_MOD_DBG
DAC Modulator Debug
0: DAC Modulator Normal Mode
1: DAC Modulator Debug Mode

12:8

R/W

0x0

Reserved

7:6

R/W

0x0

DAC_PTN_SELDAC Pattern Select00: Normal(Audio sample from DAC mixer)
01: -6 dB sin wave
10: -60 dB sin wave
11: zero data

5:0

R/W

0x0

DVC
Digital volume control, ATT=DVC[5:0]*(-1.16dB)
64 steps, -1.16dB/step

3.20.5.56.

0x330 DAC Digital Mixer Source Select Register(Default Value: 0x00000000)

Offset: 0x330

Register Name: DAC_MXR_SRC

Bit

15:12

11:8

R/W

R/W

R/W

Default/Hex

Description

0x0

DACL_MXR_SRC
DAC left channel mixer source select0: Disable 1:Enable
Bit15: AIF1 DAC0L
Bit14: AIF1 DAC1L
Bit13: AIF2 DACL
Bit12: ADCL0x0

DACR_MXR_SRC
DAC right channel mixer source select0: Disable 1:Enable
Bit11: AIF1 DAC0R

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System
Bit10: AIF1 DAC1R
Bit9: AIF2 DACR
Bit8: ADCR
7:0

R/W

3.20.5.57.

0x00x334 DAC Digital Mixer Gain Control Register(Default Value: 0x00000000)

Offset: 0x334
Bit

15:12

Reserved

Register Name: DAC_MXR_GAIN

R/W

R/W

Default/Hex

Description

0x0

DACL_MXR_GAIN
DAC left channel mixer gain control
0: 0dB 1: -6dB
Bit15: AIF1 DAC0L
Bit14: AIF1 DAC1L
Bit13: AIF2 DACL
Bit12: ADCL

11:8

R/W

0x0

DACR_MXR_GAIN
DAC right channel mixer gain control
0: 0dB 1: -6dB
Bit11: AIF1 DAC0R
Bit10: AIF1 DAC1R
Bit9: AIF2 DACR
Bit8: ADCR

7:0

R/W

0x0

Reserved

3.20.5.58.

0x400 ADC DAP Left Status Register(Default Value: 0x00000000)

Offset: 0x400

Register Name: AC_ADC_DAPLSTA

Bit

R/W

Default/Hex

Description

15:10

R

0x0

Reserved

9

R

0x0

Left AGC saturation flag

8

R

0x0

Left AGC noise-threshold flag

0x0

Left Gain applied by AGC(7.1 format 2s complement(-20dB – 40dB), 0.5B/ step)
0x50: 40dB
0x4F: 39.5dB--------------0x00: 00dB
0xFF: -0.5dB

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System
3.20.5.59.

0x404 ADC DAP Right Status Register(Default Value: 0x00000000)

Offset: 0x404

Register Name: AC_ADC_DAPRSTA

Bit

R/W

Default/Hex

Description

11:10

R

0x0

Reserved

9

R

0x0

Right AGC saturation flag

8

R

0x0

Right AGC noise-threshold flag

0x0

Right Gain applied by AGC(7.1 format 2s complement(-20dB – 40dB), 0.5dB /step)
0x50: 40dB
0x4F: 39.5dB--------------0x00: 00dB
0xFF: -0.5dB

7:0R

3.20.5.60.

0x408 ADC DAP Left Channel Control Register(Default Value: 0x00000000)

Offset: 0x408

Register Name: AC_ADC_DAPLCTRL

Bit

R/W

Default/Hex

Description

15

/

/

/

14

R/W

0x0

Left AGC enable
0: disable
1: enable

13

R/W

0x0

Left HPF enable
0: disable
1: enable

12

R/W

0x0

Left Noise detect enable
0: disable
1: enable

11:10

R/W

0x0

Reserved

0x0

Left Hysteresis setting
00: 1dB
01: 2dB
10: 4dB
11: disable;

0x0

Left Noise debounce time
0000: disable
0001: 4/fs
0010: 8/fs-----------1111: 16*4096/fs
T=2(N+1)/fs, except N=0

0x0

Left Signal debounce time
0000: disable
0001: 4/fs

9:8

7:4

3:0

R/W

R/W

R/W

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System
0010: 8/fs-----------1111: 16*4096/fs
T=2(N+1)/fs, except N=03.20.5.61.

0x40C ADC DAP Right Channel Control Register(Default Value: 0x00000000)

Offset: 0x40C

Register Name: AC_ADC_DAPRCTRL

Bit

R/W

Default/Hex

Description

15

/

/

/

14

R/W

0x0

Right AGC enable
0: disable
1: enable

13

R/W

0x0

Right HPF enable
0: disable
1: enable

12

R/W

0x0

Right Noise detect enable
0: disable
1: enable

11:10

R/W

0x0

Reserved

0x0

Right Hysteresis setting
00: 1dB
01: 2dB
10: 4dB
11: disable

0x0

Right Noise debounce time
0000: disable
0001: 4/fs
0010: 8/fs-----------1111: 16*4096/fs
T=2(N+1)/fs ,except N=0

0x0

Right Signal debounce time
0000: disable
0001: 4/fs
0010: 8/fs-----------1111: 16*4096/fs
T=2(N+1)/fs, except N=0

9: 8

7: 4

3: 0

R/W

R/W

R/W

3.20.5.62.

0x410 ADC DAP Left Target Level Register(Default Value: 0x00002C28)

Offset: 0x410
Bit

R/W

Register Name: AC_ADC_DAPLTLDefault/Hex

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Description

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Page 328

System
15:14

/

/

/

13:8

R/W

0x2C(-20dB)

Left channel
complement)

7:0

R/W

0x28(20dB)

Left channel max gain setting(0-40dB).(7.1format 2s complement)

3.20.5.63.

targetlevel

setting(-1dB---30dB).(6.0format

2s0x414 ADC DAP Right Target Level Register(Default Value: 0x00002C28)

Offset: 0x414

Register Name: AC_ADC_DAPRTL

Bit

R/W

Default/Hex

Description

15:14

/

/

/

13:8

R/W

0x2C(-20dB)

Right channel target level setting(-1dB -- -30dB).(6.0format 2scomplement)

7:0

R/W

0x28(20dB)

Right channel max gain setting (0-40dB). (7.1format 2s complement)

3.20.5.64.

0x418 ADC DAP Left High Average Coef Register(Default Value: 0x00000005)

Offset: 0x418

Register Name: AC_ADC_DAPLHAC

Bit

R/W

Default/Hex

Description

15:11

/

/

/

10:0

R/W

0x0005

Left channel output signal average level coefficient setting(the coefficient[reg06[10:0],reg07] is 3.24 format 2s complement)

3.20.5.65.

0x41C ADC DAP Left Low Average Coef Register(Default Value: 0x00001EB8)

Offset: 0x41C

Register Name: AC_ADC_DAPLHAC

Bit

R/W

Default/Hex

Description

15:0

R/W

0x1EB8

Left channel output signal average level coefficient setting(the coefficient[reg07[10:0],reg08] is 3.24 format 2s complement)

3.20.5.66.

0x420 ADC DAP Right High Average Coef Register(Default Value: 0x00000005)

Offset: 0x420

Register Name: AC_ADC_DAPRHAC

Bit

R/W

Default/Hex

Description

15:11

/

/

/

10:0

R/W

0x0005Right channel output signal average level coefficient setting(thecoefficient [reg08[10:0],reg09] is 3.24 format 2s complement)

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System
3.20.5.67.

0x424 ADC DAP Right Low Average Coef Register(Default Value: 0x00001EB8)

Offset: 0x424

Register Name: AC_ADC_DAPRLAC

Bit

R/W

Default/Hex

Description

15:0

R/W

0x1EB8Right channel output signal average level coefficient setting(thecoefficient [reg08[10:0],reg09] is 3.24 format 2s complement)

3.20.5.68.

0x428 ADC DAP Left Decay Time Register(Default Value: 0x0000001F)

Offset: 0x428

Register Name: AC_ADC_DAPLDT

Bit

R/W

Default/Hex

Description

15

/

/

/

0x001F(32x32fs)

Left decay time coefficient setting
0000: 1x32/fs
0001: 2x32/fs-----------------------7FFF: 215 x32/fs
T=(n+1)*32/fs
When the gain increases, the actual gain will increase 0.5dB at every
decay time.

14:0

R/W

3.20.5.69.

0x42C ADC DAP Left Attack Time Register(Default Value: 0x00000000)

Offset: 0x42C

Register Name: AC_ADC_DAPLAT

Bit

R/W

Default/Hex

Description

15

/

/

/

0x0000

Left attack time coefficient setting
0000: 1x32/fs
0001: 2x32/fs-----------------------7FFF: 215 x32/fs
T=(n+1)*32/fs
When the gain decreases, the actual gain will decrease 0.5dB at every
attack time.

14:0

R/W

3.20.5.70.

0x430 ADC DAP Right Decay Time Register(Default Value: 0x0000001F)

Offset: 0x430
Bit

R/W

Register Name: AC_ADC_DAPRDTDefault/Hex

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Description

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Page 330

System
15

14:0

/

R/W

3.20.5.71.

//0x001F(32x32fs)

Right decay time coefficient setting
0000: 1x32/fs
0001: 2x32/fs-----------------------7FFF: 215 x32/fs
T=(n+1)*32/fs
When the gain increases, the actual gain will increase 0.5dB at every
decay time.

0x434 ADC DAP Right Attack Time Register(Default Value: 0x00000000)

Offset: 0x434

Register Name: AC_ADC_DAPRDT

Bit

R/W

Default/Hex

Description

15

/

/

/

0x0000

Right attack time coefficient setting
0000: 1x32/fs
0001: 2x32/fs-----------------------7FFF: 215 x32/fs
T=(n+1)*32/fs
When the gain decreases, the actual gain will decrease 0.5dB at every
attack time.

14:0

R/W

3.20.5.72.

0x438 ADC DAP Noise Threshold Register(Default Value: 0x00001E1E)

Offset: 0x438

Register Name: AC_ADC_DAPNTH

Bit

R/W

Default/Hex

Description

15:13

/

/

/

12:8

R/W

0x1E
(-90dB)

Left channel noise threshold setting.
0x00: -30dB
0x01: -32dB
0x02: -34dB-------------------------------------------0x1D: -88dB
0x1E: -90dB
0x1F: -90dB(the same as 0x1E)

7:5

/

/

/

0x1E(-90dB)

Right channel noise threshold setting(-90 -- -30dB).
0x00: -30dB
0x01: -32dB
0x02: -34dB

4:0

R/W

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System-------------------------------------------0x1D: -88dB
0x1E: -90dB
0x1F: -90dB(the same as 0x1E)

3.20.5.73.

0x43C ADC DAP Left Input Signal High Average Coef Register(Default Value: 0x00000005)

Offset: 0x43C

Register Name: AC_ADC_DAPLHNAC

Bit

R/W

Default/Hex

Description

15:11

/

/

/

0x0005

Left input signal average filter coefficient to check noise or not(thecoefficient [reg0f[10:0],reg10] is 3.24 format 2s complement), always thesame as the left output signal average filter's.

10:0

R/W

3.20.5.74.

0x440 ADC DAP Left Input Signal Low Average Coef Register(Default Value: 0x00001EB8)

Offset: 0x440
Bit
15:0

Register Name: AC_ADC_DAPLHNAC

R/W
R/W

3.20.5.75.

Default/Hex

Description

0x1EB8

Left input signal average filter coefficient to check noise or not(thecoefficient [reg0f[10:0],reg10] is 3.24 format 2s complement) always
the same as the left output signal average filter's

0x444 ADC DAP Right Input Signal High Average Coef Register(Default Value: 0x00000005)

Offset: 0x444

Register Name: AC_ADC_DAPRHNAC

Bit

R/W

Default/Hex

Description

15:11

/

/

/

0x0005Right input signal average filter coefficient to check noise or not(thecoefficient [reg11[10:0],reg12] is 3.24 format 2s complement), always thesame as the right output signal average filter's

10:0

R/W

3.20.5.76.

0x448 ADC DAP Right Input Signal Low Average Coef Register(Default Value: 0x00001EB8)

Offset: 0x448
Bit
15:0

R/W
R/W

Register Name: AC_ADC_DAPRHNAC
Default/Hex

Description

0x1EB8Right input signal average filter coefficient to check noise or not(thecoefficient [reg11[10:0],reg12] is 3.24 format 2s complement), always
the same as the right output signal average filter's

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System

3.20.5.77.

0x44C ADC DAP High HPF Coef Register(Default Value: 0x000000FF)

Offset: 0x44C

Register Name: AC_DAPHHPFC

Bit

R/W

Default/Hex

Description

15:11

/

/

/

10:0

R/W

0x00FFHPF coefficient setting(the coefficient [reg13[10:0],reg14] is 3.24 format
2s complement)

3.20.5.78.

0x450 ADC DAP Low HPF Coef Register(Default Value: 0x0000FAC1)

Offset: 0x450

Register Name: AC_DAPLHPFC

Bit

R/W

Default/Hex

Description

15:0

R/W

0xFAC1

HPF coefficient setting(the coefficient [reg13[10:0],reg14] is 3.24 format
2s complement)

3.20.5.79.

0x454 ADC DAP Optimum Register(Default Value: 0x00000000)

Offset: 0x454

Register Name: AC_DAPOPT

Bit

R/W

Default/Hex

Description

15:11

/

/

/

10

R/W

0

Left energy default value setting(include the input and output)
0: min1: max

9:8

R/W

00

Left channel gain hystersis setting.
The different between target level and the signal level must larger thanthe hystersis when the gain change.
00: 0.4375db
01: 0.9375db
10: 1.9375db
11: 3db

7:6

/

/

/

0

The input signal average filter coefficient setting
0: is the [reg0f[10:0], reg10] and [reg11[1:0], reg12];
1: is the [reg06[10:0], reg07] and [reg08[1:0], reg09];

5

R/W

4

R/W

0

AGC output when the channel in noise state
0: output is zero
1: output is the input data

3

/

/

/

2

R/W

0

Right energy default value setting(include the input and output)

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System
0: min1: max

1:0

R/W

3.20.5.80.

00

Right channel gain hystersis setting.
The different between target level and the signal level must larger thanthe hystersis when the gain change.
00: 0.4375db
01: 0.9375db
10: 1.9375db
11: 3db

0x480 DAC DAP Control Register(Default Value: 0x00000000)

Offset: 0x480

Register Name: AC_DAC_DAPCTRL

Bit

R/W

Default/Hex

Description

15:7

/

/

/

6

R/W

0

DRC1 enable control
0: disable 1: enable

5

R/W

0

DRC1 Left channel HPF enable control
0: disable 1: enable

4

R/W

0

DRC1 Right channel HPF enable control
0: disable 1: enable

3

/

/

/

2

R/W

0

DRC0 enable control
0: disable 1: enable

1

R/W

0

DRC0 Left channel HPF enable control
0: disable 1: enable

0

R/W

0

DRC0 Right channel HPF enable control
0: disable 1: enable

3.20.5.81.

0x4D0 AGC Enable Register(Default Value: 0x00000000)

Offset: 0x4D0
Bit

15

14

R/W

R/W

R/W

Register Name: AGC_ENA
Default/Hex

Description

0x0

AIF1_ADC0L_AGC_ENA
AIF1 ADC timeslot 0 left channel AGC enable
0: Disable
1: Enable

0x0

AIF1_ADC0R_AGC_ENA
AIF1 ADC timeslot 0 right channel AGC enable
0: Disable
1: Enable

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System

13

12

11

10

9

8

7

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0x0

AIF1_ADC1L_AGC_ENA
AIF1 ADC timeslot 1 left channel AGC enable
0: Disable
1: Enable

0x0

AIF1_ADC1R_AGC_ENA
AIF1 ADC timeslot 1 right channel AGC enable
0: Disable
1: Enable

0x0

AIF2_ADCL_AGC_ENA
AIF2 ADC left channel AGC enable
0: Disable
1: Enable

0x0

AIF2_ADCR_AGC_ENA
AIF2 ADC right channel AGC enable
0: Disable
1: Enable

0x0

AIF2_DACL_AGC_ENA
AIF2 DAC left channel AGC enable
0: Disable
1: Enable

0x0

AIF2_DACR_AGC_ENA
AIF2 DAC right channel AGC enable
0: Disable
1: Enable

0x0

ADCL_AGC_ENA
ADC left channel AGC enable
0: Disable
1: Enable

6

R/W

0x0

ADCR_AGC_ENA
ADC right channel AGC enable
0: Disable
1: Enable

5:0

R/W

0x0

Reserved

3.20.5.82.

0x4D4 DRC Enable Register(Default Value: 0x00000000)

Offset: 0x4D4
Bit

R/W

Register Name: DRC_ENA
Default/Hex

Description

15

R/W

0x0

AIF1_DAC0_DRC0_ENA
AIF1 DAC timeslot 0 DRC0 enable
0: Disable
1: Enable

14

R/W

0x0

AIF1_DAC1_DRC0_ENA

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System
AIF1 DAC timeslot 1 DRC0 enable
0: Disable
1: Enable

13

R/W

0x0

AIF2_DAC_DRC0_ENA
AIF2 DAC DRC0 enable
0: Disable
1: Enable

12

R/W

0x0

DAC_DRC0_ENA
DAC DRC0 enable
0: Disable
1: Enable

11:8

/

/

/

0x0

AIF1_ADC0_DRC1_ENA
AIF1 ADC timeslot 0 DRC1 enable
0 : Disable
1 : Enable

0x0

AIF1_ADC1_DRC1_ENA
AIF1 ADC timeslot 1 DRC1 enable
0 : Disable
1 : Enable

0x0

AIF2_ADC_DRC1_ENA
AIF2 ADC DRC1 enable
0 : Disable
1 : Enable

7

6

5

R/W

R/W

R/W

4

R/W

0x0

ADC_DRC1_ENA
ADC_DRC1 enable
0 : Disable
1 : Enable

3:0

/

/

/

3.20.5.83.

0x4D8 SRC Bist Control Register(Default Value: 0x00000000)

Offset: 0x4D8

Register Name: SRC_BISTCR

Bit

R/W

Default/Hex

Description

15:13

R/W

0

SRC1 and SRC2 SRAM BIST Register Select

12

R/W

0

SRC1 and SRC2 SRAM BIST Address MODE Select0

SRC1 and SRC2 SRAM BIST Write Data Pattern
0: 0x0000_0000
1: 0x5555_5555
2: 0x3333_3333
3: 0x0f0f_0f0f
4: 0x00ff_00ff
5: 0x0000_ffff

11:9

R/W

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System
Others, reserved.
8

R/W

0

SRC1 and SRC2 SRAM BIST Enable
A positive edge will trigger the SRAM BIST to start

7

R

0

SRC2 ROM CheckSum Error
0: No Error
1: Error

6

R

0

SRC2 ROM CheckXor Error
0: No Error
1: Error

5

R

0

SRC2 ROM BIST Busy
0: Idle1: Busy4

R/W

0

SRC2 ROM BIST Enable
A positive edge will trigger the ROM BIST to start

3

R

0

SRC1 ROM CheckSum Error
0: No Error
1: Error2

R

0

SRC1 ROM CheckXor Error
0: No Error
1: Error

1

R

0

SRC1 ROM BIST Busy
0: Idle1: Busy0

R/W

0

SRC1 ROM BIST Enable
A positive edge will trigger the ROM BIST to start

3.20.5.84.

0x4DC SRC Bist Status Register(Default Value: 0x00000202)

Offset: 0x4DC

Register Name: SRC_BISTST

Bit

R/W

Default/Hex

Description

15

R

0

SRC2 SRAM BIST Error Status
0: No Error
1: Error

14:12

R

0

SRC2 SRAM BIST Error Pattern

11:10

R

0

SRC2 SRAM BIST Error Cycles

9

R

1

SRC2 SRAM BIST Stop
0: Running
1: Stop

8

R

0

SRC2 SRAM BIST Busy
0: Idle1: Busy7

R0

SRC1 SRAM BIST Error Status
0: No Error
1: Error

6:4

R

0

SRC1 SRAM BIST Error Pattern

3:2

R

0

SRC1 SRAM BIST Error Cycles

1

R

1

SRC1 SRAM BIST Stop
0: Running
1: Stop

0

R

0

SRC1 SRAM BIST Busy
0: Idle1: Busy

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System
3.20.5.85.

0x4E0 SRC1 Control 1 Register(Default Value: 0x00000000)

Offset: 0x4E0
Bit
15

Register Name: SRC1_CTRL1

R/W
R/W

Default/Hex

Description

0x0

SRC1_RATI_ENA
SRC1 Manual setting ratio enable
0-disable 1-enable

14

R

0x0

SRC1_LOCK_STS
SRC1 Ratio lock status
0-not locked 1-locked

13

R

0x0

SRC1_FIFO_OVR
SRC1 FIFO Overflow status
0-normal 1-overflowed

12:10

R

0x0

SRC1_FIFO_LEV_[8:6]
SRC1 FIFO Level high 3-bit

9:0

R/W

0x0

SRC1_RATI_SET_[25:16]
Manual setting ratio high 10-bit

3.20.5.86.

0x4E4 SRC1 Control 2 Register(Default Value: 0x00000000)

Offset: 0x4E4

Register Name: SRC1_CTRL2

Bit

R/W

Default/Hex

Description

15:0

R/W

0x0

SRC1_RATI_SET_[15:0]
Manual setting ratio low 16-bit

3.20.5.87.

0x4E8 SRC1 Control 3 Register(Default Value: 0x00000040)

Offset: 0x4E8

Register Name: SRC1_CTRL3

Bit

R/W

Default/Hex

Description

15:10

R

0x0

SRC1_FIFO_LEV_[5:0]
SRC1 FIFO Level low 6-bit

9:0

R

0x40

SRC1_RATI_VAL_[25:16]
Calculated ratio high 10-bit

3.20.5.88.

0x4EC SRC1 Control 4 Register(Default Value: 0x00000000)

Offset: 0x4EC

Register Name: SRC1_CTRL4

Bit

R/W

Default/Hex

Description

15:0

R

0x0

SRC1_RATI_VAL_[15:0]
Calculated ratio low 16-bit

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System

3.20.5.89.

0x4F0 SRC2 Control 1 Register(Default Value: 0x00000000)

Offset: 0x4F0
Bit
15

14

Register Name: SRC2_CTRL1

R/W
R/W

R

Default/Hex

Description

0x0

SRC2_RATI_ENA
SRC2 Manual setting ratio enable
0-disable 1-enable

0x0

SRC2_LOCK_STS
SRC2 Ratio lock status
0-not locked 1-locked

13

R

0x0

SRC2_FIFO_OVR
SRC2 FIFO Overflow status
0-normal 1-overflowed

12:10

R

0x0

SRC2_FIFO_LEV_[8:6]
SRC2 FIFO Level high 3-bit

9:0

R/W

0x0

SRC2_RATI_SET_[25:16]
Manual setting ratio high 10-bit

3.20.5.90.

0x4F4 SRC2 Control 2 Register(Default Value: 0x00000000)

Offset: 0x4F4

Register Name: SRC2_CTRL2

Bit

R/W

Default/Hex

Description

15:0

R/W

0x0

SRC2_RATI_SET_[15:0]
Manual setting ratio low 16-bit

3.20.5.91.

0x4F8 SRC2 Control 3 Register(Default Value: 0x00000040)

Offset: 0x4F8

Register Name: SRC2_CTRL3

Bit

R/W

Default/Hex

Description

15:10

R

0x0

SRC2_FIFO_LEV_[5:0]
SRC2 FIFO Level low 6-bit

9:0

R

0x40

SRC2_RATI_VAL_[25:16]
Calculated ratio high 10-bit

3.20.5.92.

0x4FC SRC2 Control 4 Register(Default Value: 0x00000000)

Offset: 0x4FC

Register Name: SRC2_CTRL4

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Bit

R/W

Default/Hex

Description

15:0

R

0x0

SRC2_RATI_VAL_[15:0]
Calculated ratio low 16-bit

3.20.5.93.

0x600 DRC0 High HPF Coef Register(Default Value: 0x000000FF)

Offset: 0x600

Register Name: AC_DRC0_HHPFC

Bit

R/W

Default/Hex

Description

15:11

/

/

/

10:0

R/W

0xFF

HPF coefficient setting and the data is 3.24 format.

3.20.5.94.

0x604 DRC0 Low HPF Coef Register(Default Value: 0x0000FAC1)

Offset: 0x604

Register Name: AC_DRC0_LHPFC

Bit

R/W

Default/Hex

Description

15:0

R/W

0xFAC1

HPF coefficient setting and the data is 3.24 format.

3.20.5.95.

0x608 DRC0 Control Register(Default Value: 0x00000080)

Offset: 0x608

Register Name: AC_DRC0_CTRL

Bit

R/W

Default/Hex

Description

15

R

0

DRC delay buffer data output state when drc delay function is enble andthe drc funciton disable. After disable drc function and this bit go to 0, theuser should write the drc delay function bit to 0;
0 : not complete
1 : is complete

14

/

/

/

13:8

R/W

0

Signal delay time setting
6'h00 : (8x1)fs
6'h01 : (8x2)fs
6'h02 : (8x3)fs---------------------------------------6'h2e : (8*47)fs
6'h2f : (8*48)fs
6'h30 -- 6'h3f : (8*48)fs
Delay time = 8*(n+1)fs, n<6'h30;
When the delay function is disable, the signal delay time is unused.

7

R/W

0x1

The delay buffer use or not when the drc disable and the drc buffer data
output completely
0 : don't use the buffer

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1 : use the buffer
6

5

4

3

2

1

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

3.20.5.96.

0x0

DRC gain max limit enable
0 : disable
1 : enable

0x0

DRC gain min limit enable. when this fuction enable, it will overwrite thenoise detect funciton.
0 : disable
1 : enable

0x0

Control the drc to detect noise when ET enable
0 : disable
1 : enable

0x0

Signal function Select0 : RMS filter
1 : Peak filter
When Signal function Select Peak filter, the RMS parameter is unused.
(AC_DRC_LRMSHAT / AC_DRC_LRMSLAT / AC_DRC_LRMSHAT /AC_DRC_LRMSLAT)When Signal function Select RMS filter, the Peak filter parameter isunused.(AC_DRC_LPFHAT / AC_DRC_LPFLAT / AC_DRC_RPFHAT /AC_DRC_RPFLAT / AC_DRC_LPFHRT / AC_DRC_LPFLRT / AC_DRC_RPFHRT/ AC_DRC_RPFLRT)

0x0

Delay function enable
0 : disable
1 : enable
When the Delay function enable is disable, the Signal delay time isunused.

0x0

DRC LT enable
0 : disable
1 : enable
When the DRC LT is disable the LT, Kl and OPL parameter is unused.

0x0

DRC ET enable
0 : disable
1 : enable
When the DRC ET is disable the ET, Ke and OPE parameter is unused.

0x60C DRC0 Left Peak Filter High Attack Time Coef Register(Default Value: 0x0000000B)

Offset: 0x60C

Register Name: AC_DRC0_LPFHAT

Bit

R/W

Default/Hex

Description

15:11

/

/

/

10:0

R/W

0x000BThe left peak filter attack time parameter setting, which determine by theequation that AT = 1-exp(-2.2Ts/ta). The format is 3.24. (1ms)

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System
3.20.5.97.

0x610 DRC0 Left Peak Filter Low Attack Time Coef Register(Default Value: 0x000077BF)

Offset: 0x610

Register Name: AC_DRC0_LPFLAT

Bit

R/W

Default/Hex

Description

15:0

R/W

0x77BFThe left peak filter attack time parameter setting, which determine by theequation that AT = 1-exp(-2.2Ts/ta). The format is 3.24. (1ms)

3.20.5.98.

0x614 DRC0 Right Peak Filter High Attack Time Coef Register(Default Value: 0x0000000B)

Offset: 0x614

Register Name: AC_DRC0_RPFHAT

Bit

R/W

Default/Hex

Description

15:11

/

/

/

10:0

R/W

0x000BThe left peak filter attack time parameter setting, which determine by theequation that AT = 1-exp(-2.2Ts/ta). The format is 3.24. (1ms)

3.20.5.99.

0x618 DRC0 Peak Filter Low Attack Time Coef Register(Default Value: 0x000077BF)

Offset: 0x618

Register Name: AC_DRC0_RPFLAT

Bit

R/W

Default/Hex

Description

15:0

R/W

0x77BFThe left peak filter attack time parameter setting, which determine by theequation that AT = 1-exp(-2.2Ts/ta). The format is 3.24. (1ms)

3.20.5.100.

0x61C DRC0 Left Peak Filter High Release Time Coef Register(Default Value: 0x000000FF)

Offset: 0x61C

Register Name: AC_DRC0_LPFHRT

Bit

R/W

Default/Hex

Description

15:11

/

/

/

10:0

R/W

0x00FFThe left peak filter release time parameter setting, which determine by
the equation that RT = exp(-2.2Ts/tr). The format is 3.24.
(100ms)3.20.5.101.

0x620 DRC0 Left Peak Filter Low Release Time Coef Register(Default Value: 0x0000E1F8)

Offset: 0x620

Register Name: AC_DRC0_LPFLRT

Bit

R/W

Default/Hex

Description

15:0

R/W

0xE1F8The left peak filter release time parameter setting, which determine by
the equation that RT = exp(-2.2Ts/tr). The format is 3.24.
(100ms)

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3.20.5.102.

0x624 DRC0 Right Peak filter High Release Time Coef Register(Default Value: 0x000000FF)

Offset: 0x624

Register Name: AC_DRC0_RPFHRT

Bit

R/W

Default/Hex

Description

15:11

/

/

/

10:0

R/W

0x00FFThe left peak filter attack time parameter setting, which determine by theequation that RT = exp(-2.2Ts/tr). The format is 3.24. (100ms)

3.20.5.103.

0x628 DRC0 Right Peak filter Low Release Time Coef Register(Default Value: 0x0000E1F8)

Offset: 0x628

Register Name: AC_DRC0_RPFLRT

Bit

R/W

Default/Hex

Description

15:0

R/W

0xE1F8The left peak filter release time parameter setting, which determine by
the equation that AT = exp(-2.2Ts/tr). The format is 3.24.
(100ms)3.20.5.104.

0x62C DRC0 Left RMS Filter High Coef Register(Default Value: 0x00000001)

Offset: 0x62C

Register Name: AC_DRC0_LRMSHAT

Bit

R/W

Default/Hex

Description

15:11

/

/

/

10:0

R/W

0x0001The left RMS filter average time parameter setting, which determine by
the equation that AT = 1-exp(-2.2Ts/tav). The format is 3.24.
(10ms)

3.20.5.105.

0x630 DRC0 Left RMS Filter Low Coef Register(Default Value: 0x00002BAF)

Offset: 0x630

Register Name: AC_DRC0_LRMSLAT

Bit

R/W

Default/Hex

Description

15:0

R/W

0x2BAFThe left RMS filter average time parameter setting, which determine by
the equation that AT = 1-exp(-2.2Ts/tav). The format is 3.24.
(10ms)

3.20.5.106.

0x634 DRC0 Right RMS Filter High Coef Register(Default Value: 0x00000001)

Offset: 0x634

Register Name: AC_DRC0_RRMSHAT

Bit

R/W

Default/Hex

Description

15:11

/

/

/

10:0

R/W

0x0001

The right RMS filter average time parameter setting, which determine by
the equation that AT = 1-exp(-2.2Ts/tav). The format is 3.24.
(10ms)A64 User Manual(Revision 1.0)

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3.20.5.107.

0x638 DRC0 Right RMS Filter Low Coef Register(Default Value: 0x00002BAF)

Offset: 0x638

Register Name: AC_DRC0_RRMSLAT

Bit

R/W

Default/Hex

Description

15:0

R/W

0x2BAFThe right RMS filter average time parameter setting, which determine by
the equation that AT = 1-exp(-2.2Ts/tav). The format is 3.24.
(10ms)

3.20.5.108.

0x63C DRC0 Compressor Theshold High Setting Register(Default Value: 0x000006A4)

Offset: 0x63C

Register Name: AC_DRC0_HCT

Bit

R/W

Default/Hex

Description

15:0

R/W

0x06A4The compressor threshold setting, which set by the equation that CTin =-CT/6.0206. The format is 8.24 (-40dB)

3.20.5.109.

0x640 DRC0 Compressor Theshold Low Setting Register(Default Value: 0x0000D3C0)

Offset: 0x640

Register Name: AC_DRC0_LCT

Bit

R/W

Default/Hex

Description

15:0

R/W

0xD3C0The compressor threshold setting, which set by the equation that CTin =-CT/6.0206. The format is 8.24 (-40dB)

3.20.5.110.

0x644 DRC0 Compressor Slope High Setting Register(Default Value: 0x00000080)

Offset: 0x644

Register Name: AC_DRC0_HKC

Bit

R/W

Default/Hex

Description

15:13

/

/

/

0x0080The slope of the compressor which determine by the equation that Kc =1/R, there, R is the ratio of the compressor, which always is interger. The
format is 8.24. (2 : 1)

13:0

R/W

3.20.5.111.

0x648 DRC0 Compressor Slope Low Setting Register(Default Value: 0x00000000)

Offset: 0x648

Register Name: AC_DRC0_LKC

Bit
15:0

R/W
R/W

Default/Hex

Description

0x0000The slope of the compressor which determine by the equation that Kc =1/R, there, R is the ratio of the compressor, which always is interger. The
format is 8.24. (2 : 1)

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3.20.5.112.

0x64C DRC0 Compressor High Output at Compressor Threshold Register(Default Value:
0x0000F95B)

Offset: 0x64C

Register Name: AC_DRC0_HOPC

Bit

R/W

Default/Hex

Description

15:0

R/W

0xF95BThe output of the compressor which determine by the equation-OPC/6.0206 The format is 8.24 (-40dB)

3.20.5.113.

0x650 DRC0 Compressor Low Output at Compressor Threshold Register(Default Value:
0x00002C3F)

Offset: 0x650

Register Name: AC_DRC0_LOPC

Bit

R/W

Default/Hex

Description

15:0

R/W

0x2C3FThe output of the compressor which determine by the equation
OPC/6.0206 The format is 8.24 (-40dB)

3.20.5.114.

0x654 DRC0 Limiter Theshold High Setting Register(Default Value: 0x000001A9)

Offset: 0x654

Register Name: AC_DRC0_HLT

Bit

R/W

Default/Hex

Description

15:0

R/W

0x01A9The limiter threshold setting, which set by the equation that LTin =-LT/6.0206, The format is 8.24. (-10dB)

3.20.5.115.

0x658 DRC0 Limiter Theshold Low Setting Register(Default Value: 0x000034F0)

Offset: 0x658

Register Name: AC_DRC0_LLT

Bit

R/W

Default/Hex

Description

15:0

R/W

0x34F0The limiter threshold setting, which set by the equation that LTin =-LT/6.0206, The format is 8.24. (-10dB)

3.20.5.116.

0x65C DRC0 Limiter Slope High Setting Register(Default Value: 0x00000005)

Offset: 0x65C

Register Name: AC_DRC0_HK1

Bit

R/W

Default/Hex

Description

15:11

/

/

/

13:0

R/W

0x0005The slope of the limiter which determine by the equation that Kl = 1/R,
there, R is the ratio of the limiter, which always is interger. The format is

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System
8.24. (50 :1)

3.20.5.117.

0x660 DRC0 Limiter Slope Low Setting Register(Default Value: 0x00001EB8)

Offset: 0x660

Register Name: AC_DRC0_LK1

Bit
15:0

R/W
R/W

3.20.5.118.

Default/Hex

Description

0x1EB8The slope of the limiter which determine by the equation that Kl = 1/R,
there, R is the ratio of the limiter, which always is interger. The format is
8.24. (50 :1)

0x664 DRC0 Limiter High Output at Limiter Threshold Register(Default Value: 0x0000FBD8)

Offset: 0x664

Register Name: AC_DRC0_HOPL

Bit

R/W

Default/Hex

Description

15:0

R/W

0xFBD8The output of the limiter which determine by equation OPT/6.0206. The
format is 8.24 (-25dB)

3.20.5.119.

0x668 DRC0 Limiter Low Output at Limiter Threshold Register(Default Value: 0x0000FBA7)

Offset: 0x668

Register Name: AC_DRC0_LOPL

Bit

R/W

Default/Hex

Description

15:0

R/W

0xFBA7The output of the limiter which determine by equation OPT/6.0206. The
format is 8.24 (-25dB)

3.20.5.120.

0x66C DRC0 Expander Theshold High Setting Register(Default Value: 0x00000BA0)

Offset: 0x66C

Register Name: AC_DRC0_HET

Bit

R/W

Default/Hex

Description

15:0

R/W

0x0BA0The expander threshold setting, which set by the equation that ETin =-ET/6.0206, The format is 8.24. (-70dB)

3.20.5.121.

0x670 DRC0 Expander Theshold Low Setting Register(Default Value: 0x00007291)

Offset: 0x670

Register Name: AC_DRC0_LET

Bit

R/W

Default/Hex

Description

15:0

R/W

0x7291The expander threshold setting, which set by the equation that ETin =-ET/6.0206, The format is 8.24. (-70dB)

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3.20.5.122.

0x674 DRC0 Expander Slope High Setting Register(Default Value: 0x00000500)

Offset: 0x674

Register Name: AC_DRC0_HKE

Bit

R/W

Default/Hex

Description

15:14

/

/

/

0x0050The slope of the expander which determine by the equation that Ke = 1/R,
there, R is the ratio of the expander, which always is interger and the ke
must larger than 50. The format is 8.24. (1:5)

13:0

R/W

3.20.5.123.

0x678 DRC0 Expander Slope Low Setting Register(Default Value: 0x00000000)

Offset: 0x678

Register Name: AC_DRC0_LKE

Bit
15:0

R/W
R/W

3.20.5.124.

Default/Hex

Description

0x0000The slope of the expander which determine by the equation that Ke = 1/R,
there, R is the ratio of the expander, which always is interger and the ke
must larger than 50. The format is 8.24. (1:5)

0x67C DRC0 Expander High Output at Expander Threshold Register(Default Value:
0x0000F45F)

Offset: 0x67C

Register Name: AC_DRC0_HOPE

Bit

R/W

Default/Hex

Description

15:0

R/W

0xF45FThe output of the expander which determine by equation OPE/6.0206.
The format is 8.24 (-70dB)

3.20.5.125.

0x680 DRC0 Expander Low Output at Expander Threshold Register(Default Value:
0x00008D6E)

Offset: 0x680

Register Name: AC_DRC0_LOPE

Bit

R/W

Default/Hex

Description

15:0

R/W

0x8D6EThe output of the expander which determine by equation OPE/6.0206.
The format is 8.24 (-70dB)

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System
3.20.5.126.

0x684 DRC0 Linear Slope High Setting Register(Default Value: 0x00000100)

Offset: 0x684

Register Name: AC_DRC0_HKN

Bit

R/W

Default/Hex

Description

15:14

/

/

/

0x0100The slope of the linear which determine by the equation that Kn = 1/R,
there, R is the ratio of the linear, which always is interger . The format is
8.24. (1:1)

13:0

R/W

3.20.5.127.

0x688 DRC0 Linear Slope Low Setting Register(Default Value: 0x00000000)

Offset: 0x688
Bit
15:0

Register Name: AC_DRC0_LKN

R/W
R/W

3.20.5.128.

Default/Hex

Description

0x0000The slope of the linear which determine by the equation that Kn = 1/R,
there, R is the ratio of the linear, which always is interger . The format is
8.24. (1:1)

0x68C DRC0 Smooth filter Gain High Attack Time Coef Register(Default Value: 0x00000002)

Offset: 0x68C

Register Name: AC_DRC0_SFHAT

Bit

R/W

Default/Hex

Description

15:11

/

/

/

10:0

R/W

0x0002The smooth filter attack time parameter setting, which determine by theequation that AT = 1-exp(-2.2Ts/tr). The format is 3.24. (5ms)

3.20.5.129.

0x690 DRC0 Smooth filter Gain Low Attack Time Coef Register(Default Value: 0x00005600)

Offset: 0x690

Register Name: AC_DRC0_SFLAT

Bit

R/W

Default/Hex

Description

15:0

R/W

0x5600The smooth filter attack time parameter setting, which determine by theequation that AT = 1-exp(-2.2Ts/tr). The format is 3.24. (5ms)

3.20.5.130.

0x694 DRC0 Smooth filter Gain High Release Time Coef Register(Default Value: 0x00000000)

Offset: 0x694

Register Name: AC_DRC0_SFHRT

Bit

R/W

Default/Hex

Description

15:11

/

/

/

10:0

R/W

0x0000

The gain smooth filter release time parameter setting, which determine

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Systemby the equation that RT = 1-exp(-2.2Ts/tr). The format is 3.24. (200ms)

3.20.5.131.

0x698 DRC0 Smooth filter Gain Low Release Time Coef Register(Default Value: 0x00000F04)

Offset: 0x698

Register Name: AC_DRC0_SFHRT

Bit

R/W

Default/Hex

Description

15:0

R/W

0x0F04

The gain smooth filter release time parameter setting, which determineby the equation that RT = 1-exp(-2.2Ts/tr). The format is 3.24. (200ms)

3.20.5.132.

0x69C DRC0 MAX Gain High Setting Register(Default Value: 0x0000FE56)

Offset: 0x69C

Register Name: AC_DRC0_MXGHS

Bit

R/W

Default/Hex

Description

15:0

R/W

0xFE56The max gain setting which determine by equation MXG/6.0206. The
format is 8.24 and must -20dB <MXG< 30dB (-10dB)

3.20.5.133.

0x6A0 DRC0 MAX Gain Low Setting Register(Default Value: 0x0000CB0F)

Offset: 0x6A0

Register Name: AC_DRC0_MXGLS

Bit

R/W

Default/Hex

Description

15:0

R/W

0xCB0F

The max gain setting which determine by equation MXG/6.0206. The
format is 8.24 and must -20dB <MXG < 30dB (-10dB)

3.20.5.134.

0x6A4 DRC0 MIN Gain High Setting Register(Default Value: 0x0000F95B)

Offset: 0x6A4

Register Name: AC_DRC0_MNGHS

Bit

R/W

Default/Hex

Description

15:0

R/W

0xF95BThe min gain setting which determine by equation MXG/6.0206. The
format is 8.24 and must -60dB ≤MNG ≤ -40dB (-40dB)

3.20.5.135.

0x6A8 DRC0 MIN Gain Low Setting Register(Default Value: 0x00002C3F)

Offset: 0x6A8

Register Name: AC_DRC0_MNGLS

Bit

R/W

Default/Hex

Description

15:0

R/W

0x2C3F

The min gain setting which determine by equation MNG/6.0206. The
format is 8.24 and must -60dB ≤MNG ≤ -40dB (-40dB)

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System
3.20.5.136.

0x6AC DRC0 Expander Smooth Time High Coef Register(Default Value: 0x00000000)

Offset: 0x6AC
Bit
11:0

Register Name: AC_DRC0_EPSHC

R/W
R/W

3.20.5.137.

Default/Hex

Description

0x0000

The gain smooth filter release and attack time parameter setting in
expander region, which determine by the equation that RT =1-exp(-2.2Ts/tr). The format is 3.24. (30ms)

0x6B0 DRC0 Expander Smooth Time Low Coef Register(Default Value: 0x0000640C)

Offset: 0x6B0
Bit
15:0

Register Name: AC_DRC0_EPSLC

R/W
R/W

3.20.5.138.

Default/Hex

Description

0x640CThe gain smooth filter release and attack time parameter setting in
expander region, which determine by the equation that RT =1-exp(-2.2Ts/tr). The format is 3.24. (30ms)

0x6B4 DRC0 Optimum Register(Default Value: 0x00000000)

Offset: 0x6B4

Register Name: AC_DRC0_OPT

Bit

R/W

Default/Hex

Description

15:11

/

/

/

0x0

The gain smooth use the expander coiffcient when the energy inexpander range
0 : use the normal smooth coeffcient
1 : use the expander coeffcient

10

R/W

9

R/W

0x0

The gain normal smooth coefficeint selection mode set
0 : both release and attack coeffcient use hysteresis;
1 : only the attack coeffcient use hysteresis;

8

R/W

0x0

The min of energy set in Peak detect mode
0 : -120dB
1 : -210dB

0x0

The energy mode select in rms detect mode
0 : the energy is RMS
1 : the energy is square of RMS

0x0

DRC data ouput when DRC disable and DRC delay data output complete.
0 : the ouput is the input music data;
1 : the output is 0 ;

7

6

R/W

R/W

5

R/W

0

DRC gain defaut value setting
0: The default gain is 1
1: The default gain is 0

4:0

R/W

0x00

The hysteresis of the gain smooth filter to use the decay time coefficientor the attack time coefficient.

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System
When in the decay time state, if g(n-1)-g(n)>hysteresis, then the state willchange to attack time state, and when in the attack time, if
g(n)-g(n-1)>hysteresis, then the state will change to decay time state.
Note the hysteresis of 0x00 and 0x04 is the same.
00000: 200001: 200010: 200011: 200100: 2

16

19

18

17

16

----------------10011: 2

110100 ~11111: 1
hysteresis = 2

3.20.5.139.

n  20,except n=0x00, and n less 0x14.

0x6B8 DRC0 HPF Gain High Coef Register(Default Value: 0x00000100)

Offset: 0x6B8

Register Name: AC_DRC0_HPFHGAIN

Bit

R/W

Default/Hex

Description

15:11

/

/

/

10:0

R/W

0x0100

The gain of the hpf coefficient setting which format is 3.24.(gain = 1)

3.20.5.140.

0x6BC DRC0 HPF Gain Low Coef Register(Default Value: 0x00000000)

Offset: 0x6BC

Register Name: AC_DRC0_HPFLGAIN

Bit

R/W

Default/Hex

Description

15:0

R/W

0x0000

The gain of the hpf coefficient setting which format is 3.24.(gain = 1)

3.20.5.141.

0x700 DRC1 High HPF Coef Register(Default Value: 0x000000FF)

Offset: 0x700

Register Name: AC_DRC1_HHPFC

Bit

R/W

Default/Hex

Description

15:11

/

/

/

10:0

R/W

0xFF

HPF coefficient setting and the data is 3.24 format.

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System

3.20.5.142.

0x704 DRC1 Low HPF Coef Register(Default Value: 0x0000FAC1)

Offset: 0x704

Register Name: AC_DRC1_LHPFC

Bit

R/W

Default/Hex

Description

15:0

R/W

0xFAC1

HPF coefficient setting and the data is 3.24 format.

3.20.5.143.

0x708 DRC1 Control Register(Default Value: 0x00000080)

Offset: 0x708

Register Name: AC_DRC1_CTRL

Bit

R/W

Default/Hex

Description

15

R

0

DRC delay buffer data output state when drc delay function is enble andthe drc funciton disable. After disable drc function and this bit go to 0, theuser should write the drc delay function bit to 0;
0 : not complete
1 : is complete

14:10

/

/

/

13:8

R/W

0

Signal delay time setting
6'h00 : (8x1)fs
6'h01 : (8x2)fs
6'h02 : (8x3)fs---------------------------------------6'h2e : (8*47)fs
6'h2f : (8*48)fs
6'h30 -- 6'h3f : (8*48)fs
Delay time = 8*(n+1)fs, n<6'h30;
When the delay function is disable, the signal delay time is unused.

7

R/W

0x1

The delay buffer use or not when the drc disable and the drc buffer data
output completely
0 : don't use the buffer
1 : use the buffer

6

R/W

0x0

DRC gain max limit enable
0 : disable
1 : enable

5

R/W

0x0

DRC gain min limit enable. when this fuction enable, it will overwrite thenoise detect funciton.
0 : disable
1 : enable

4

R/W

0x0

Control the drc to detect noise when ET enable
0 : disable
1 : enable

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System

3

2

1

0

R/W

R/W

R/W

R/W

3.20.5.144.

0x0

Signal function Select0 : RMS filter
1 : Peak filter
When Signal function Select Peak filter, the RMS parameter is unused.
(AC_DRC_LRMSHAT / AC_DRC_LRMSLAT / AC_DRC_LRMSHAT /AC_DRC_LRMSLAT)When Signal function Select RMS filter, the Peak filter parameter isunused.(AC_DRC_LPFHAT / AC_DRC_LPFLAT / AC_DRC_RPFHAT /AC_DRC_RPFLAT / AC_DRC_LPFHRT / AC_DRC_LPFLRT / AC_DRC_RPFHRT/ AC_DRC_RPFLRT)

0x0

Delay function enable
0 : disable
1 : enable
When the Delay function enable is disable, the Signal delay time isunused.

0x0

DRC LT enable
0 : disable
1 : enable
When the DRC LT is disable the LT, Kl and OPL parameter is unused.

0x0

DRC ET enable
0 : disable
1 : enable
When the DRC ET is disable the ET, Ke and OPE parameter is unused.

0x70C DRC1 Left Peak Filter High Attack Time Coef Register(Default Value: 0x0000000B)

Offset: 0x70C

Register Name: AC_DRC1_LPFHAT

Bit

R/W

Default/Hex

Description

15:11

/

/

/

10:0

R/W

0x000BThe left peak filter attack time parameter setting, which determine by theequation that AT = 1-exp(-2.2Ts/ta). The format is 3.24. (1ms)

3.20.5.145.

0x710 DRC1 Left Peak Filter Low Attack Time Coef Register(Default Value: 0x000077BF)

Offset: 0x710

Register Name: AC_DRC1_LPFLAT

Bit

R/W

Default/Hex

Description

15:0

R/W

0x77BFThe left peak filter attack time parameter setting, which determine by theequation that AT = 1-exp(-2.2Ts/ta). The format is 3.24. (1ms)

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System
3.20.5.146.

0x714 DRC1 Right Peak Filter High Attack Time Coef Register(Default Value: 0x0000000B)

Offset: 0x714

Register Name: AC_DRC1_RPFHAT

Bit

R/W

Default/Hex

Description

15:11

/

/

/

10:0

R/W

0x000BThe left peak filter attack time parameter setting, which determine by theequation that AT = 1-exp(-2.2Ts/ta). The format is 3.24. (1ms)

3.20.5.147.

0x718 DRC1 Peak Filter Low Attack Time Coef Register(Default Value: 0x000077BF)

Offset: 0x718

Register Name: AC_DRC1_RPFLAT

Bit

R/W

Default/Hex

Description

15:0

R/W

0x77BFThe left peak filter attack time parameter setting, which determine by theequation that AT = 1-exp(-2.2Ts/ta). The format is 3.24. (1ms)

3.20.5.148.

0x71C DRC1 Left Peak Filter High Release Time Coef Register(Default Value: 0x000000FF)

Offset: 0x71C

Register Name: AC_DRC1_LPFHRT

Bit

R/W

Default/Hex

Description

15:11

/

/

/

10:0

R/W

0x00FFThe left peak filter release time parameter setting, which determine by
the equation that RT = exp(-2.2Ts/tr). The format is 3.24.
(100ms)3.20.5.149.

0x720 DRC1 Left Peak Filter Low Release Time Coef Register(Default Value: 0x0000E1F8)

Offset: 0x720

Register Name: AC_DRC1_LPFLRT

Bit

R/W

Default/Hex

Description

15:0

R/W

0xE1F8The left peak filter release time parameter setting, which determine by
the equation that RT = exp(-2.2Ts/tr). The format is 3.24.
(100ms)3.20.5.150.

0x724 DRC1 Right Peak filter High Release Time Coef Register(Default Value: 0x000000FF)

Offset: 0x724

Register Name: AC_DRC1_RPFHRT

Bit

R/W

Default/Hex

Description

15:11

/

/

/

10:0

R/W

0x00FFThe left peak filter attack time parameter setting, which determine by theequation that RT = exp(-2.2Ts/tr). The format is 3.24. (100ms)

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System
3.20.5.151.

0x728 DRC1 Right Peak filter Low Release Time Coef Register(Default Value: 0x0000E1F8)

Offset: 0x728

Register Name: AC_DRC1_RPFLRT

Bit

R/W

Default/Hex

Description

15:0

R/W

0xE1F8The left peak filter release time parameter setting, which determine by
the equation that AT = exp(-2.2Ts/tr). The format is 3.24.
(100ms)3.20.5.152.

0x72C DRC Left RMS Filter High Coef Register(Default Value: 0x00000001)

Offset: 0x72C

Register Name: AC_DRC1_LRMSHAT

Bit

R/W

Default/Hex

Description

15:11

/

/

/

10:0

R/W

0x0001The left RMS filter average time parameter setting, which determine by
the equation that AT = 1-exp(-2.2Ts/tav). The format is 3.24.
(10ms)

3.20.5.153.

0x730 DRC1 Left RMS Filter Low Coef Register(Default Value: 0x00002BAF)

Offset: 0x730

Register Name: AC_DRC1_LRMSLAT

Bit

R/W

Default/Hex

Description

15:0

R/W

0x2BAFThe left RMS filter average time parameter setting, which determine by
the equation that AT = 1-exp(-2.2Ts/tav). The format is 3.24.
(10ms)

3.20.5.154.

0x734 DRC1 Right RMS Filter High Coef Register(Default Value: 0x00000001)

Offset: 0x734

Register Name: AC_DRC1_RRMSHAT

Bit

R/W

Default/Hex

Description

15:11

/

/

/

10:0

R/W

0x0001

The right RMS filter average time parameter setting, which determine by
the equation that AT = 1-exp(-2.2Ts/tav). The format is 3.24.
(10ms)

3.20.5.155.

0x738 DRC1 Right RMS Filter Low Coef Register(Default Value: 0x00002BAF)

Offset: 0x738

Register Name: AC_DRC1_RRMSLAT

Bit

R/W

Default/Hex

Description

15:0

R/W

0x2BAFThe right RMS filter average time parameter setting, which determine by
the equation that AT = 1-exp(-2.2Ts/tav). The format is 3.24.
(10ms)A64 User Manual(Revision 1.0)

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System
3.20.5.156.

0x73C DRC1 Compressor Theshold High Setting Register(Default Value: 0x000006A4)

Offset: 0x73C

Register Name: AC_DRC1_HCT

Bit

R/W

Default/Hex

Description

15:0

R/W

0x06A4The compressor threshold setting, which set by the equation that CTin =-CT/6.0206. The format is 8.24 (-40dB)

3.20.5.157.

0x740 DRC1 Compressor Slope High Setting Register(Default Value: 0x0000D3D0)

Offset: 0x740

Register Name: AC_DRC1_LCT

Bit

R/W

Default/Hex

Description

15:0

R/W

0xD3C0The compressor threshold setting, which set by the equation that CTin =-CT/6.0206. The format is 8.24 (-40dB)

3.20.5.158.

0x744 DRC1 Compressor Slope High Setting Register(Default Value: 0x00000080)

Offset: 0x744

Register Name: AC_DRC1_HKC

Bit

R/W

Default/Hex

Description

15:14

/

/

/

0x0800The slope of the compressor which determine by the equation that Kc =1/R, there, R is the ratio of the compressor, which always is interger. The
format is 8.24. (2 : 1)

13:0

R/W

3.20.5.159.

0x748 DRC1 Compressor Slope Low Setting Register(Default Value: 0x00000000)

Offset: 0x748

Register Name: AC_DRC1_LKC

Bit
15:0

R/W
R/W

3.20.5.160.

Default/Hex

Description

0x0000The slope of the compressor which determine by the equation that Kc =1/R, there, R is the ratio of the compressor, which always is interger. The
format is 8.24. (2 : 1)

0x74C DRC1 Compressor High Output at Compressor Threshold Register(Default Value:
0x0000F95B)

Offset: 0x74C

Register Name: AC_DRC1_HOPC

Bit

R/W

Default/Hex

Description

15:0

R/W

0xF95BThe output of the compressor which determine by the equation

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System-OPC/6.0206 The format is 8.24

3.20.5.161.

(-40dB)

0x750 DRC1 Compressor Low Output at Compressor Threshold Register(Default Value:
0x00002C3F)

Offset: 0x750

Register Name: AC_DRC1_LOPC

Bit

R/W

Default/Hex

Description

15:0

R/W

0x2C3FThe output of the compressor which determine by the equation
OPC/6.0206 The format is 8.24 (-40dB)

3.20.5.162.

0x754 DRC1 Limiter Theshold High Setting Register(Default Value: 0x000001A9)

Offset: 0x754

Register Name: AC_DRC1_HLT

Bit

R/W

Default/Hex

Description

15:0

R/W

0x01A9The limiter threshold setting, which set by the equation that LTin =-LT/6.0206, The format is 8.24. (-10dB)

3.20.5.163.

0x758 DRC1 Limiter Theshold Low Setting Register(Default Value: 0x000034F0)

Offset: 0x758

Register Name: AC_DRC1_LLT

Bit

R/W

Default/Hex

Description

15:0

R/W

0x34F0The limiter threshold setting, which set by the equation that LTin =-LT/6.0206, The format is 8.24. (-10dB)

3.20.5.164.

0x75C DRC1 Limiter Slope High Setting Register(Default Value: 0x00000005)

Offset: 0x75C

Register Name: AC_DRC1_HK1

Bit

R/W

Default/Hex

Description

15:11

/

/

/

0x0005The slope of the limiter which determine by the equation that Kl = 1/R,
there, R is the ratio of the limiter, which always is interger. The format is
8.24. (50 :1)

13:0

R/W

3.20.5.165.

0x760 DRC1 Limiter Slope Low Setting Register(Default Value: 0x00001EB8)

Offset: 0x760

Register Name: AC_DRC1_LK1

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System
Bit
15:0

R/W
R/W

3.20.5.166.

Default/Hex

Description

0x1EB8The slope of the limiter which determine by the equation that Kl = 1/R,
there, R is the ratio of the limiter, which always is interger. The format is
8.24. (50 :1)

0x764 DRC1 Limiter High Output at Limiter Threshold Register(Default Value: 0x0000FBD8)

Offset: 0x764

Register Name: AC_DRC1_HOPL

Bit

R/W

Default/Hex

Description

15:0

R/W

0xFBD8The output of the limiter which determine by equation OPT/6.0206. The
format is 8.24 (-25dB)

3.20.5.167.

0x768 DRC1 Limiter Low Output at Limiter Threshold Register(Default Value: 0x0000FBA7)

Offset: 0x768

Register Name: AC_DRC1_LOPL

Bit

R/W

Default/Hex

Description

15:0

R/W

0xFBA7The output of the limiter which determine by equation OPT/6.0206. The
format is 8.24 (-25dB)

3.20.5.168.

0x76C DRC1 Expander Theshold High Setting Register(Default Value: 0x00000BA0)

Offset: 0x76C

Register Name: AC_DRC1_HET

Bit

R/W

Default/Hex

Description

15:0

R/W

0x0BA0The expander threshold setting, which set by the equation that ETin =-ET/6.0206, The format is 8.24. (-70dB)

3.20.5.169.

0x770 DRC1 Expander Theshold Low Setting Register(Default Value: 0x00007291)

Offset: 0x770

Register Name: AC_DRC1_LET

Bit

R/W

Default/Hex

Description

15:0

R/W

0x7291The expander threshold setting, which set by the equation that ETin =-ET/6.0206, The format is 8.24. (-70dB)

3.20.5.170.

0x774 DRC1 Expander Slope High Setting Register(Default Value: 0x00000500)

Offset: 0x774

Register Name: AC_DRC1_HKE

Bit

R/W

Default/Hex

A64 User Manual(Revision 1.0)

Description

Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.

Page 358

System
15:14
13:0

/
R/W

/

/

0x0050The slope of the expander which determine by the equation that Ke = 1/R,
there, R is the ratio of the expander, which always is interger and the ke
must larger than 50. The format is 8.24. (1:5)

3.20.5.171.

0x778 DRC1 Expander Slope Low Setting Register(Default Value: 0x00000000)

Offset: 0x778

Register Name: AC_DRC1_LKE

Bit
15:0

R/W
R/W

3.20.5.172.

Default/Hex

Description

0x0000The slope of the expander which determine by the equation that Ke = 1/R,
there, R is the ratio of the expander, which always is interger and the ke
must larger than 50. The format is 8.24. (1:5)

0x77C DRC1 Expander High Output at Expander Threshold Register(Default Value:
0x0000F45F)

Offset: 0x77C

Register Name: AC_DRC1_HOPE

Bit

R/W

Default/Hex

Description

15:0

R/W

0xF45FThe output of the expander which determine by equation OPE/6.0206.
The format is 8.24 (-70dB)

3.20.5.173.

0x780 DRC1 Expander Low Output at Expander Threshold Register(Default Value:
0x00008D6E)

Offset: 0x780

Register Name: AC_DRC1_LOPE

Bit

R/W

Default/Hex

Description

15:0

R/W

0x8D6EThe output of the expander which determine by equation OPE/6.0206.
The format is 8.24 (-70dB)

3.20.5.174.

0x784 DRC1 Linear Slope High Setting Register(Default Value: 0x00000100)

Offset: 0x784

Register Name: AC_DRC1_HKN

Bit

R/W

Default/Hex

Description

15:14

/

/

/

0x0100The slope of the linear which determine by the equation that Kn = 1/R,
there, R is the ratio of the linear, which always is interger. The format is
8.24. (1:1)

13:0

R/W

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System

3.20.5.175.

0x788 DRC1 Linear Slope Low Setting Register(Default Value: 0x00000000)
Register Name: AC_DRC1_LKN

Offset: 0x788
Bit
15:0

R/W
R/W

3.20.5.176.

Default/Hex

Description

0x0000The slope of the linear which determine by the equation that Kn = 1/R,
there, R is the ratio of the linear, which always is interger. The format is
8.24. (1:1)

0x78C DRC1 Smooth filter Gain High Attack Time Coef Register(Default Value: 0x00000002)
Register Name: AC_DRC1_SFHAT

Offset: 0x78C
Bit

R/W

Default/Hex

Description

15:11

/

/

/

10:0

R/W

0x0002The smooth filter attack time parameter setting, which determine by theequation that AT = 1-exp(-2.2Ts/tr). The format is 3.24. (5ms)

3.20.5.177.

0x790 DRC1 Smooth filter Gain Low Attack Time Coef Register(Default Value: 0x00005600)

Offset: 0x790

Register Name: AC_DRC1_SFLAT

Bit

R/W

Default/Hex

Description

15:0

R/W

0x5600The smooth filter attack time parameter setting, which determine by theequation that AT = 1-exp(-2.2Ts/tr). The format is 3.24. (5ms)

3.20.5.178.

0x794 DRC1 Smooth filter Gain High Release Time Coef Register(Default Value: 0x00000000)

Offset: 0x794

Register Name: AC_DRC1_SFHRT

Bit

R/W

Default/Hex

Description

15:11

/

/

/

10:0

R/W

0x0000

The gain smooth filter release time parameter setting, which determineby the equation that RT = 1-exp(-2.2Ts/tr). The format is 3.24. (200ms)

3.20.5.179.

0x798 DRC1 Smooth filter Gain Low Release Time Coef Register(Default Value: 0x00000F04)

Offset: 0x798

Register Name: AC_DRC1_SFHRT

Bit

R/W

Default/Hex

Description

15:0

R/W

0x0F04

The gain smooth filter release time parameter setting, which determine

A64 User Manual(Revision 1.0)

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Systemby the equation that RT = 1-exp(-2.2Ts/tr). The format is 3.24. (200ms)

3.20.5.180.

0x79C DRC1 MAX Gain High Setting Register(Default Value: 0x0000FE56)

Offset: 0x79C

Register Name: AC_DRC1_MXGHS

Bit

R/W

Default/Hex

Description

15:0

R/W

0xFE56The max gain setting which determine by equation MXG/6.0206. The
format is 8.24 and must -20dB <MXG< 30dB (-10dB)

3.20.5.181.

0x7A0 DRC1 MAX Gain Low Setting Register(Default Value: 0x0000CB0F)

Offset: 0x7A0

Register Name: AC_DRC1_MXGLS

Bit

R/W

Default/Hex

Description

15:0

R/W

0xCB0F

The max gain setting which determine by equation MXG/6.0206. The
format is 8.24 and must -20dB <MXG < 30dB (-10dB)

3.20.5.182.

0x7A4 DRC1 MIN Gain High Setting Register(Default Value: 0x0000F95B)

Offset: 0x7A4

Register Name: AC_DRC1_MNGHS

Bit

R/W

Default/Hex

Description

15:0

R/W

0xF95BThe min gain setting which determine by equation MXG/6.0206. The
format is 8.24 and must -60dB ≤MNG ≤ -40dB (-40dB)

3.20.5.183.

0x7A8 DRC1 MIN Gain Low Setting Register(Default Value: 0x00002C3F)

Offset: 0x7A8

Register Name: AC_DRC1_MNGLS

Bit

R/W

Default/Hex

Description

15:0

R/W

0x2C3F

The min gain setting which determine by equation MNG/6.0206. The
format is 8.24 and must -60dB ≤MNG ≤ -40dB (-40dB)

3.20.5.184.

0x7AC DRC1 Expander Smooth Time High Coef Register(Default Value: 0x00000000)

Offset: 0x7AC
Bit
11:0

R/W
R/W

Register Name: AC_DRC1_EPSHCDefault/Hex

Description

0x0000

The gain smooth filter release and attack time parameter setting in
expander region, which determine by the equation that RT =1-exp(-2.2Ts/tr). The format is 3.24. (30ms)

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System

3.20.5.185.

0x7B0 DRC1 Expander Smooth Time Low Coef Register(Default Value: 0x0000640C)

Offset: 0x7B0
Bit
15:0

Register Name: AC_DRC1_EPSLC

R/W
R/W

3.20.5.186.

Default/Hex

Description

0x640CThe gain smooth filter release and attack time parameter setting in
expander region, which determine by the equation that RT =1-exp(-2.2Ts/tr). The format is 3.24. (30ms)

0x7B8 DRC1 HPF Gain High Coef Register(Default Value: 0x00000100)

Offset: 0x7B8

Register Name: AC_DRC1_HPFHGAIN

Bit

R/W

Default/Hex

Description

15:11

/

/

/

10:0

R/W

0x0100

The gain of the hpf coefficient setting which format is 3.24.(gain = 1)

3.20.5.187.

0x7BC DRC1 HPF Gain Low Coef Register(Default Value: 0x00000000)

Offset: 0x7BC

Register Name: AC_DRC1_HPFLGAIN

Bit

R/W

Default/Hex

Description

15:0

R/W

0x0000

The gain of the hpf coefficient setting which format is 3.24.(gain = 1)

3.20.5.188.

AC_PR Configuration Register

The Analog domain register can be write/Read through the AC_PR Configuration Register(AC_PR_CFG_REG)
which is in the PRCM Spec. To configure the codec analog domain circuit throught this register.
Reset：Reset signal;
ADDR[4:0] :AC_PR address;
W/R :write/read enable;
WDAT[7:0] :write data;
RDAT[7:0] : read data.
Reset

APB0

W/R
Addr[4:0]

CPUS

0x01F015C0

Data_in[7:0]

25 8-bit
registers

Data_out[7:0]

Bit 31-29
/

28

27-23

24

23-21

20-16

RST

/

WR

/

Addr

7-0
15-8
Data_in Data_out

Figure 3-21. AC_PR Configuration Register function
A64 User Manual(Revision 1.0)

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System

3.20.5.189.

0x00 Headphone Amplifier Control Register(Default Value: 0x00)

Offset: 0x00
Bit

7

Register Name: HP_CTRL

R/W

R/W

Default/Hex

Description

0x0

PA_CLK_GATE
PA clock gating control;when system VDD is off and Audio analog channel is working, this bit
must be set to 1, because the PA clock come from system VDD domain.
When this bit is 1, the Zero cross over function will be disabled
automatically.
0: not gating; 1: gating

6

R/W

0x0

HPPA_EN
Right & Left Headphone PA Enable
0: Disable; 1: Enable

5:0

R/W

0x0

HPVOL
Headphone Volume Control, (HPVOL): Total 64 level, from 0dB to -62dB,
1dB/step, mute when 000000

3.20.5.190.

0x01 Output Left Mixer Control Register(Default Value: 0x00)

Offset: 0x01

Register Name: OL_MIX_CTRL

Bit

R/W

Default/Hex

Description

7

R/W

0x0

/

0x0

LMIXMUTE
Left Output Mixer Mute Control
0-Mute, 1-Not mute
Bit 6: MIC1 Boost stage
Bit 5: MIC2 Boost stage
Bit 4: xxx
Bit 3: xxx
Bit 2: LINEINL
Bit 1: Left channel DAC
Bit 0: Right channel DAC

6:0

R/W

3.20.5.191.

0x02 Output Right Mixer Control Register(Default Value: 0x00)

Offset: 0x02

Register Name: OR_MIX_CTRL

Bit

R/W

Default/Hex

Description

7

R/W

0x0

/

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6:0

R/W

3.20.5.192.

0x00

RMIXMUTE
Right Output Mixer Mute Control, (???rmixs)
0-Mute, 1-Not mute
Bit 6: MIC1 Boost stage
Bit 5: MIC2 Boost stage
Bit 4: xxx
Bit 3: xxx
Bit 2: LINEINR
Bit 1: Right channel DAC
Bit 0: Left channel DAC

0x03 Earpiece Control Register 0 (Default Value: 0x00)

Offset: 0x03

Register Name: EARPIECE_CTRL0

Bit

R/W

Default/Hex

Description

7:6

/

/

/

5:4

R/W

0x0

EAR_RAMP_TIME
Earpiece ramp time select00: 131ms
01: 262ms
10: 395ms
11: 524ms

3:2

/

/

/

0x0

ESPSR
Earpiece input source select00: DACR
01: DACL
10: Right Analog Mixer
11: Left Analog Mixer

1:0

R/W

3.20.5.193.

0x04 Earpiece Control Register 1 (Default Value: 0x00)

Offset: 0x04
Bit
7

R/W
R/W

Register Name: EARPIECE_CTRL1
Default/Hex

Description

0x0

ESPPA_EN
Earspeaker PA Enable
0: Disable; 1: Enable

6

R/W

0x0

ESPPA_MUTE
All input source to Earspeaker PA mute
0: mute; 1: on

5

R/W

0x0

/

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4:0

R/W

0x00

ESP_VOL
Earspeaker VOLume control, total 31 level from 0dB to -43.5dB,
1.5dB/step, mute when 00000&00001

3.20.5.194.

0x05 LINEOUT Control Register 0 (Default Value: 0x00)

Offset: 0x05

Register Name: LINEOUT_CTRL0

Bit
7

6

5

R/W
R/W

R/W

R/W

Default/Hex

Description

0x0

Lineout Left Enable
0: Disable
1: Enable

0x0

Lineout Right Enable
0: Disable
1: Enable

0x0

Left lineout source select0-left output mixer
1-left output mixer + right output mixer

4

R/W

0x0

Right lineout source select0-right output mixer
1-left lineout, for differential output

3:0

/

/

/

3.20.5.195.

0x06 LINEOUT Control Register 1 (Default Value: 0x00)

Offset: 0x06

Register Name: LINEOUT_CTRL1

Bit

R/W

Default/Hex

Description

7:5

/

/

/

4:0

R/W

0x00

Lineout Volume Control, Total 31 level, from 0dB to -43.5dB, 1.5dB/step,
mute when 00000 & 00001

3.20.5.196.

0x07 MIC1 Control Register (Default Value: 0x34)

Offset: 0x07

Register Name: MIC1_CTRL

Bit

R/W

Default/Hex

Description

7

/

/

/

6:4

R/W

0x3

MIC1G, (volm1)
MIC1 BOOST stage to L or R output mixer Gain Control
From -4.5dB to 6dB, 1.5dB/step, default is 0dB

3

R/W

0x0

MIC1AMPEN
MIC1 Boost AMP Enable

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0-Disable; 1-Enable
2:0

R/W

3.20.5.197.

0x4

MIC1BOOSTMIC1 Boost AMP Gain Control
0dB when 000, 24dB to 42dB when 001 to 111, 3dB/step, default is 33dB

0x08 MIC2 Control Register (Default Value: 0x11)

Offset: 0x08

Register Name: MIC2_CTRL

Bit

R/W

Default/Hex

Description

7

R/W

0x1

MIC2 Source select0: MICIN3 1: MICIN2

0x3

MIC2G.
MIC2 BOOST stage to L or R output mixer Gain Control
From -4.5dB to 6dB, 1.5dB/step, default is 0dB

0x0

MIC2AMPEN
MIC2 Boost AMP Enable
0-Disable; 1-Enable

0x4

MIC2BOOSTMIC2 Boost AMP Gain Control
0dB when 000, 24dB to 42dB when 001 to 111, 3dB/step, default is 33dB

6:4

3

2:0

R/W

R/W

R/W

3.20.5.198.

0x09 Linein Control Register (Default Value: 0x03)

Offset: 0x09

Register Name: LINEIN_CTRL

Bit

R/W

Default/Hex

Description

7:3

/

/

/

0x3

LINEING.
LINEINL/R to L/R output mixer Gain Control
From -4.5dB to 6dB, 1.5dB/step, default is 0dB

2:0

R/W

3.20.5.199.

0x0A Mixer and DAC Control Register (Default Value: 0x00)

Offset: 0x0A
Bit
7

6

R/W
R/W

R/W

Register Name: MIX_DAC_CTRL
Default/Hex

Description

0x0

DACAREN
Internal Analog Right channel DAC Enable
0:Disable; 1:Enable

0x0

DACALEN
Internal Analog Left channel DAC Enable
0:Disable; 1:Enable

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5

4

3

2

1

0

R/W

R/W

R/W

R/W

R/W

R/W

3.20.5.200.

0x0

RMIXEN
Right Analog Output Mixer Enable
0:Disable; 1:Enable

0x0

LMIXEN
Left Analog Output Mixer Enable
0:Disable; 1:Enable

0x0

RHPPAMUTE
All input source to Right Headphone PA mute, including Right Output
mixer and Internal Right channel DAC:
0:Mute, 1: Not mute

0x0

LHPPAMUTE
All input source to Left Headphone PA mute, including Left Output mixer
and Internal Left channel DAC:
0:Mute, 1: Not mute

0x0

RHPIS
Right Headphone Power Amplifier (PA) Input Source Select0: Right channel DAC
1: Right Analog Mixer

0x0

LHPIS
Left Headphone Power Amplifier (PA) Input Source Select0: Left channel DAC
1: Left Analog Mixer

0x0B Left ADC Mixer Control Register (Default Value: 0x00)

Offset: 0x0B

Register Name: L_ADCMIX_SRC

Bit

R/W

Default/Hex

Description

7

R/W

0x0

/

0x0

LADCMIXMUTE
Left ADC Mixer Mute Control:
0: Mute; 1:On
Bit 6: MIC1 Boost stage
Bit 5: MIC2 Boost stage
Bit 4: xxx
Bit 3: xxx
Bit 2: LINEINL
Bit 1: Left output mixer
Bit 0: Right output mixer

6:0

R/W

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3.20.5.201.

0x0C Right ADC Mixer Control Register (Default Value: 0x00)

Offset: 0x0C

Register Name: R_ADCMIX_SRC

Bit

R/W

Default/Hex

Description

7

R/W

0x0

/

0x0

RADCMIXMUTE
Right ADC Mixer Mute Control:
0: Mute; 1:On
Bit 6: MIC1 Boost stage
Bit 5: MIC2 Boost stage
Bit 4: xxx
Bit 3: xxx
Bit 2: LINEINR
Bit 1: Right output mixer
Bit 0: Left output mixer

6:0

R/W

3.20.5.202.

0x0D ADC Control Register (Default Value: 0x03)

Offset: 0x0D

Register Name: ADC_CTRL

Bit
7

R/W
R/W

Default/Hex

Description

0x0

ADCRENADC Right Channel Enable
0-Disable; 1-Enable

6

R/W

0x0

ADCLENADC Left Channel Enable
0-Disable; 1-Enable

5:3

R/W

0x0

/

0x3

ADCG
ADC Input Gain Control
From -4.5dB to 6dB, 1.5dB/step default is 0dB

2:0

R/W

3.20.5.203.

0x0E Headset Microphone Bias Control Register (Default Value: 0x21)

Offset: 0x0E
Bit
7

6:5

R/W
R/W

R/W

Register Name: HS_MBIAS_CTRL
Default/Hex

Description

0x0

MMICBIASEN
Master Microphone Bias enable
0: disable, 1: enable

0x1

MBIASSELMMICBIAS voltage level select00: 1.88V

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01: 2.09V
10: 2.33V
11: 2.50V

1:0

R/W

3.20.5.204.

0x1

HBIASSELHMICBIAS voltage level select00: 1.88V
01: 2.09V
10: 2.33V
11: 2.50V

0x0F Analog Performance Tuning Register (Default Value: 0xD6)

Offset: 0x0F

Register Name: APT_REG

Bit

R/W

Default/Hex

Description

7

R/W

0x1

MMIC BIAS chopper enable
0: disable; 1:enable

6:5

R/W

0x10

MMIC BIAS chopper clock select00: 250KHz; 01: 500KHz; 10: 1MHz; 11: 2MHz

0x1

DITHER
ADC dither on/off control
0: dither off; 1: dither on

0x1

DITHER_CLK_SELECT
ADC dither clock select
00: ADC FS * (8/9), about 43KHz when FS=48KHz
01: ADC FS * (16/15), about 51KHz when FS=48KHz
10: ADC FS * (4/3), about 64KHz when FS=48KHz
11: ADC FS * (16/9), about 85KHz when FS=48KHz

0x10

BIHE_CTRL, BIHE control
00: no BIHE
01: BIHE=7.5 HOSC
10: BIHE=11.5 HOSC
11: BIHE=15.5 HOSC

4

3:2

1:0

R/W

R/W

R/W

3.20.5.205.

0x10 OP BIAS Control Register0 (Default Value: 0x55)

Offset: 0x10

Register Name: OP_BIAS_CTRL0

Bit

R/W

Default/Hex

Description

7:6

R/W

0x01

OPDRV_OPEAR_CUR.
OPDRV/OPEAR output stage current setting

5:4

R/W

0x01

OPADC1_BIAS_CUR.

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OPADC1 Bias Current Select
3:2

R/W

0x01

OPADC2_BIAS_CUR.
OPADC2 Bias Current Select

1:0

R/W

0x01

OPAAF_BIAS_CUR.
OPAAF in ADC Bias Current Select3.20.5.206.

0x11 OP BIAS Control Register1 (Default Value: 0x55)

Offset: 0x11

Register Name: OP_BIAS_CTRL1

Bit

R/W

Default/Hex

Description

7:6

R/W

0x01

OPMIC_BIAS_CUR
OPMIC Bias Current Control

5:4

R/W

0x01

OPVR_BIAS_CUR.
OPVR Bias Current Control

3:2

R/W

0x01

OPDAC_BIAS_CUR.
OPDAC Bias Current Control

1:0

R/W

0x01

OPMIX_BIAS_CUR.
OPMIX/OPLPF/OPDRV/OPEAR Bias Current Control

3.20.5.207.

0x12 USB Bias & Volume Change Control Register (Default Value: 0x02)

Offset: 0x12

Register Name: ZC_VOL_CTRL

Bit

R/W

Default/Hex

Description

7:6

R/W

0x0

function enable for master volume change at zero cross over
0: disable; 1: enable

5:4

R/W

0x0

Timeout control for master volume change at zero cross over
0: 32ms;
1: 64ms

3

/

/

/

0x2

USB_BIAS_CUR.
USB bias current tuning
From 23uA to 30uA, Default is 25uA

2:0

R/W

3.20.5.208.

0x13 Bias Calibration Data Register (Default Value: 0x00)

Offset: 0x13

Register Name: BIAS_CAL_DATA

Bit

R/W

Default/Hex

Description

7:6

/

/

/

5:0

R

/

BIASCALI
Bias Calibration Data, 6bit

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3.20.5.209.

0x14 Bias Calibration Set Data Register (Default Value: 0x20)

Offset: 0x14
Bit

Register Name: BIAS_CAL_SET

R/W

Default/Hex

Description

7:6

R/W

00

SELDETADCDY
Select the delay time to pull low the micdet when jack removal
00: 0.5ms
01: 1ms
10: 1.5ms
11: 2ms

5:0

R/W

0x20

BIASVERIFY
Bias Register Setting Data

3.20.5.210.

0x15 Bias & DA16 Calibration Control Register (Default Value: 0x00)

Offset: 0x15

Register Name: BD_CAL_CTRL

Bit

R/W

Default/Hex

Description

7

R/W

0x0

PA_SPEED_SELECT
PA setup speed control (for testing)
0: slow; 1: fast

6

R/W

0x0

CURRENT_TEST_SELECTInternal current sink test enable (from LINEIN pin)0:Normal; 1: For Debug

5:3

/

/

/

2

R/W

0x0

BIAS calibration mode select0: average; 1: single

0x0

BIAS and HP calibration control
Write 1 to this bit, the calibration will be doing again. Then this bit will bereset to zero automatically0x0

BIASCALIVERIFY
Bias Calibration Verify
0: Calibration; 1: Register setting

1

0

R/W

R/W

3.20.5.211.

0x16 Headphone PA Control Register (Default Value: 0xF1)

Offset: 0x16

Register Name: HP_PA_CTRL

Bit

R/W

Default/Hex

Description

7

R/W

0x1

BUFFERENABLE
When this bit is write to 0, the buffer in headphone disabled

6

R/W

0x1

HPMUTENABLE
When this bit is write to 0, all input to headphone is mute

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5

R/W

0x1

HPINPUTENABLE
When this bit is write to 0, the input stage of headphone disabled

4

R/W

0x1

HPOUTPUTENABLE
When this bit is write to 0, the output stage of headphone disabled

0x0

HPPA_DEL
Headphone delay time when start up
00: 4ms
01: 8ms
10: 16ms
11: 32ms

0x1

CP_CLKS
Charge Pump Clock select00: 250k
01: 330k
10: 400k
11: 500k

3:2

1:0

R/W

R/W

3.20.5.212.

0x17 Headphone Calibration Control Register (Default Value: 0x04)

Offset: 0x17

Register Name: HP_CAL_CTRL

Bit

R/W

Default/Hex

Description

7

R/W

0

HPCALIFIRST
When this bit is write to 1 , HEADPHONE Calibration once before enable

6

R/W

0

/

0

HPCALIMODEHEADPHONE calibration equilibration MODE select0: equilibration mode
1: no equilibration

5

R/W

4

R/W

0

HPCALIVERIFYHEADPHONE calibration in verify mode enable
0: Disable; 1: Enable

3

R/W

0

/

100

HPCALICKSHEADPHONE Calibration clock frequency select000: 1k…
100: 16k…
111: 128k

2:0

R/W

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3.20.5.213.

0x18 Right Headphone Calibration DAT Register (Default Value: 0x00)

Offset: 0x18

Register Name: RHP_CAL_DAT

Bit

R/W

Default/Hex

Description

7:0

R

/

HPRCALI
Right Headphone calibration Data

3.20.5.214.

0x19 Right Headphone Calibration Setting Register (Default Value: 0x80)

Offset: 0x19

Register Name: RHP_CAL_SET

Bit

R/W

Default/Hex

Description

7:0

R/W

0x80

HPRCALIVERIFY
Right Headphone calibration Setting Data

3.20.5.215.

0x1A Left Headphone Calibration DAT Register (Default Value: 0x00)

Offset: 0x1A

Register Name: LHP_CAL_DAT

Bit

R/W

Default/Hex

Description

7:0

R

/

HPLCALI
Left Headphone calibration Data

3.20.5.216.

0x1B Left Headphone Calibration Setting Register (Default Value: 0x80)

Offset: 0x1B

Register Name: LHP_CAL_SET

Bit

R/W

Default/Hex

Description

7:0

R/W

0x80

HPLCALIVERIFY
Left Headphone calibration Setting Data

3.20.5.217.

0x1C Mic detect Control Register (Default Value: 0x40)

Offset: 0x1C

Register Name: MDET_CTRL

Bit

R/W

Default/Hex

Description

7

R/W

0

/

100

SELDETADCFS
Select sample interval of the ADC sample
000: 2ms…
100: 32ms

6:4

R/W

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System…
111: 256ms

3:2

1:0

R/W

R/W

3.20.5.218.

00

SELDETADCDB
Select debounce time when jack removal
00: 128ms
01: 256ms
10: 512ms
11: 1024ms

00

SELDETADCBF
Select the time to enable HBIAS before micadc work
00: 2ms
01: 4ms
10: 8ms
11: 16ms

0x1D Jack & Mic detect Control Register (Default Value: 0x00)

Offset: 0x1D
Bit
7

6

5

R/W
R/W

R/W

R/W

Register Name: JACK_MIC_CTRL
Default/Hex

Description

0

JACKDETEN
Jack detect enable
0: disable, 1: enable

0

INNERRESEN
Inner 2.2k resistor between hbias and micdet enable
0: disable, 1: enable

0

HMICBIASEN
Handset Microphone Bias enable
0: disable, 1: enable

4

R/W

0

MICADCEN
Microphone detect ADC enable
0: disable, 1: enable

3

R/W

0

POPFREE
When this bit is 0, HBIAS MICADC is controlled by registor

2

R/W

0

/

1

R/W

0

AUTOPLEN
Enable the function to auto pull low micdet when jack removal
0: disable, 1: enable

0

R/W

0

MICDETPL
When this bit is 1and AUTOPLEN is 0, the micdet is pull to gnd

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System
3.20.5.219.

0x1E Phone Output Register (Default Value: 0x60)

Offset: 0x1E
Bit
7:5

Register Name: PHOUT_CTRL

R/W
R/W

Default/Hex

Description

011

PHONEOUTG
Phone-out Gain Control
From -4.5dB to 6dB, 1.5dB/step, default is 0dB

4

R/W

0

PHONEOUT enable
0: Disable
1: Enable

3

R/W

0

PHONEOUTS3
MIC1 Boost stage to Phone out mute
0: Mute, 1: Not mute0

PHONEOUTS2
MIC2 Boost stage to Phone out mute
0: Mute, 1: Not mute0

PHONEOUTS1
Right Output mixer to Phone out mute
0: Mute, 1: Not mute0

PHONEOUTS0
Left Output mixer to Phone out mute
0: Mute, 1: Not mute

2

1

0

R/W

R/W

R/W

3.20.5.220.

0x1F Phone Input Register (Default Value: 0x34)

Offset: 0x1F

Register Name: PHIN_CTRL

Bit

R/W

Default/Hex

Description

7

R/W

0

/

6:4

R/W

011

PHONEG, (volpn)
PHONEP/N/G to Right output mixer Gain Control
From -4.5dB to 6dB, 1.5dB/step, default is 0dB

4

R/W

0

/

100

PHONEPREG
PHONEP-PHONEN pre-amplifier gain control-12dB to 9dB, 3dB/step, default is 0dB

2:0

R/W

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3.21. Port Controller(CPUx-PORT)The chip has 7 ports for multi-functional input/out pins. They are shown below:
Port B(PB): 10 input/output portPort C(PC): 17 input/output portPort D(PD): 25 input/output portPort E(PE): 18 input/output portPort F(PF): 7 input/output portPort G(PG): 14 input/output portPort H(PH): 12 input/output port
For various system configurations, these ports can be easily configured by software. All these ports can be
configured as GPIO if multiplexed functions are not used. The total 3 group external PIO interrupt sources aresupported and interrupt mode can be configured by software.

3.21.1. Port Controller Register List
Module Name

Base Address

PIO

0x01C20800

Register Name

OffsetDescription

Pn_CFG0

n*0x24+0x00

Port n Configure Register 0 (n from 1 to 7)

Pn_CFG1

n*0x24+0x04

Port n Configure Register 1 (n from 1 to 7)

Pn_CFG2

n*0x24+0x08

Port n Configure Register 2 (n from 1 to 7)

Pn_CFG3

n*0x24+0x0C

Port n Configure Register 3 (n from 1 to 7)

Pn_DAT

n*0x24+0x10

Port n Data Register (n from 1 to 7)

Pn_DRV0n*0x24+0x14

Port n Multi-Driving Register 0 (n from 1 to 7)

Pn_DRV1

n*0x24+0x18

Port n Multi-Driving Register 1 (n from 1 to 7)

Pn_PUL0n*0x24+0x1C

Port n Pull Register 0 (n from 1 to 7)

Pn_PUL1

n*0x24+0x20

Port n Pull Register 1 (n from 1 to 7)

Pn_INT_CFG0

0x200+0*0x20+0x00

PIO Interrrupt Configure Register 0

Pn _INT_CFG1

0x200+0*0x20+0x04

PIO Interrrupt Configure Register 1

Pn _INT_CFG2

0x200+0*0x20+0x08

PIO Interrrupt Configure Register 2

Pn _INT_CFG3

0x200+0*0x20+0x0C

PIO Interrrupt Configure Register 3

Pn _INT_CTL

0x200+0*0x20+0x10

PIO Interrupt Control Register

Pn _INT_STA

0x200+0*0x20+0x14

PIO Interrupt Status Register

Pn_INT_DEB

0x200+0*0x20+0x18

PIO Interrupt Debounce Register

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3.21.2. Port Controller Register Description
3.21.2.1. PB Configure Register 0 (Default Value: 0x77777777)
Offset: 0x24

Register Name: PB_CFG0_REG

Bit

R/W

Default/Hex

Description

31

/

/

/

30:28

R/W

0x7

PB7_SELECT
000: Input
010: AIF2_DIN
100: Reserved
110: PB_EINT7

27

/

/

/

26:24

R/W

0x7

PB6_SELECT
000: Input
010: AIF2_DOUT
100: Reserved
110: PB_EINT6

23

/

/

/

22:20

R/W

0x7

PB5_SELECT
000: Input
010: AIF2_BCLK
100: Reserved
110: PB_EINT5

19

/

/

/

18:16

R/W

0x7

PB4_SELECT
000: Input
010: AIF2_SYNC
100: Reserved
110: PB_EINT4

15

/

/

/

14:12

R/W

0x7

PB3_SELECT
000: Input
010: UART2_CTS
100: JTAG_DI0
110: PB_EINT3

11

/

/

/

10:8

R/W

0x7

PB2_SELECT
000: Input
010: UART2_RTS
100: JTAG_DO0
110: PB_EINT2

7

/

/

/

A64 User Manual(Revision 1.0)

001: Output
011: PCM0_DIN
101: SIM_DET
111: IO Disable

001: Output
011: PCM0_DOUT
101: SIM_RST
111: IO Disable

001: Output
011: PCM0_BCLK
101: SIM_DATA
111: IO Disable

001: Output
011: PCM0_SYNC
101: SIM_CLK
111: IO Disable

001: Output
011: I2S0_MCLK
101: SIM_VPPPP
111: IO Disable

001: Output
011: Reserved
101: SIM_VPPEN
111: IO Disable

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System

6:4

R/W

0x7

PB1_SELECT
000: Input
010: UART2_RX
100: JTAG_CK0
110: PB_EINT1

3

/

/

/

0x7

PB0_SELECT
000: Input
010: UART2_TX
100: JTAG_MS0
110: PB_EINT0

2:0

R/W

001: Output
011: Reserved
101: SIM_PWREN
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

3.21.2.2. PB Configure Register 1 (Default Value: 0x00000077)
Offset: 0x28

Register Name: PB_CFG1_REG

Bit

R/W

Default/Hex

Description

31:7

/

/

/

6:4

R/W

0x7

PB9_SELECT
000: Input
010: Reserved
100: UART0_RX
110: PB_EINT9

3

/

/

/

0x7

PB8_SELECT
000: Input
010: Reserved
100: UART0_TX
110: PB_EINT8

2:0

R/W

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

3.21.2.3. PB Configure Register 2 (Default Value: 0x00000000)
Offset: 0x2C

Register Name: PB_CFG2_REG

Bit

R/W

Default/Hex

Description

31:0

/

/

/

3.21.2.4. PB Configure Register 3 (Default Value: 0x00000000)
Offset: 0x30

Register Name: PB_CFG3_REG

Bit

R/W

Default/Hex

Description

31:0

/

/

/

A64 User Manual(Revision 1.0)

Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.

Page 378

System
3.21.2.5. PB Data Register (Default Value: 0x00000000)
Offset: 0x34

Register Name: PB_DATA_REG

Bit

R/W

Default/Hex

Description

31:10

/

/

/

0x0

PB_DAT
If the port is configured as input, the corresponding bit is the pin state. If
the port is configured as output, the pin state is the same as thecorresponding bit. The read bit value is the value setup by software. If theport is configured as functional pin, the undefined value will be read.

9:0

R/W

3.21.2.6. PB Multi-Driving Register 0 (Default Value: 0x00055555)
Offset: 0x38

Register Name: PB_DRV0_REG

Bit

R/W

Default/Hex

Description

31:20

/

/

/

0x1

PB_DRVPB[n] Multi-Driving Select (n = 0~9)00: Level 0
01: Level 1
10: Level 2
11: Level 3[2i+1:2i](i=0~9)R/W

3.21.2.7. PB Multi-Driving Register 1 (Default Value: 0x00000000)
Offset: 0x3C

Register Name: PB_DRV1_REG

Bit

R/W

Default/Hex

Description

31:0

/

/

/

3.21.2.8. PB PULL Register 0 (Default Value: 0x00000000)
Offset: 0x40

Register Name: PB_PULL0_REG

Bit

R/W

Default/Hex

Description

31:20

/

/

Reserved

0x0

PB_PULL
PB[n] Pull-up/down Select (n = 0~9)00: Pull-up/down disable
01: Pull-up
10: Pull-down
11: Reserved[2i+1:2i](i=0~9)R/W

A64 User Manual(Revision 1.0)

Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.

Page 379

System
3.21.2.9. PB PULL Register 1 (Default Value: 0x00000000)
Offset: 0x44

Register Name: PB_PULL1_REG

Bit

R/W

Default/Hex

Description

31:0

/

/

/

3.21.2.10.

PC Configure Register 0 (Default Value: 0x77777777)

Offset: 0x48

Register Name: PC_CFG0_REG

Bit

R/W

Default/Hex

Description

31

/

/

/

30:28

R/W

0x7

PC7_SELECT
000: Input
010: NAND_RB1
100: Reserved
110: Reserved

27

/

/

/

26:24

R/W

0x7

PC6_SELECT
000: Input
010: NAND_RB0
100: Reserved
110: Reserved

23

/

/

/

22:20

R/W

0x7

PC5_SELECT
000: Input
010: NAND_RE
100: Reserved
110: Reserved

19

/

/

/

18:16

R/W

0x7

PC4_SELECT
000: Input
010: NAND_CE0
100: Reserved
110: Reserved

15

/

/

/

14:12

R/W

0x7

PC3_SELECT
000: Input
010: NAND_CE1
100: SPI0_CS
110: Reserved

11

/

/

/

10:8

R/W

0x7

PC2_SELECT

A64 User Manual(Revision 1.0)

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: SDC2_CMD
101: Reserved
111: IO Disable

001: Output
011: SDC2_CLK
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.

Page 380

System
000: Input
010: NAND_CLE
100: SPI0_CLK
110: Reserved
7

/

/

/

6:4

R/W

0x7

PC1_SELECT
000: Input
010: NAND_ALE
100: SPI0_MISO
110: Reserved

3

/

/

/

0x7

PC0_SELECT
000: Input
010: NAND_WE
100: SPI0_MOSI
110: Reserved001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: SDC2_DS
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

2:0

R/W

3.21.2.11.

PC Configure Register 1 (Default Value: 0x77777777)

Offset: 0x4C

Register Name: PC_CFG1_REG

Bit

R/W

Default/Hex

Description

31

/

/

/

30:28

R/W

0x7

PC15_SELECT
000:Input
010:NAND_DQ7
100:Reserved
110:Reserved

27

/

/

/

26:24

R/W

0x7

PC14_SELECT
000:Input
010:NAND_DQ6
100:Reserved
110:Reserved

23

/

/

/

22:20

R/W

0x7

PC13_SELECT
000:Input
010:NAND_DQ5
100:Reserved
110:Reserved

19

/

/

/

0x7

PC12_SELECT
000:Input

18:16

R/W

A64 User Manual(Revision 1.0)

001:Output
011:SDC2_D7
101:Reserved
111:IO Disable

001:Output
011:SDC2_D6
101:Reserved
111:IO Disable

001:Output
011:SDC2_D5
101:Reserved
111:IO Disable

001:Output

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Page 381

System
010:NAND_DQ4
100:Reserved
110:Reserved
15

/

/

/

14:12

R/W

0x7

PC11_SELECT
000:Input
010:NAND_DQ3
100:Reserved
110:Reserved

11

/

/

/

10:8

R/W

0x7

PC10_SELECT
000:Input
010:NAND_DQ2
100:Reserved
110:Reserved

7

/

/

/

6:4

R/W

0x7

PC9_SELECT
000:Input
010:NAND_DQ1
100:Reserved
110:Reserved

3

/

/

/

0x7

PC8_SELECT
000:Input
010:NAND_DQ0
100:Reserved
110:Reserved

011:SDC2_D4
101:Reserved
111:IO Disable

001:Output
011:SDC2_D3
101:Reserved
111:IO Disable

001:Output
011:SDC2_D2
101:Reserved
111:IO Disable

001:Output
011:SDC2_D1
101:Reserved
111:IO Disable

001:Output
011:SDC2_D0
101:Reserved
111:IO Disable

2:0

R/W

3.21.2.12.

PC Configure Register 2 (Default Value: 0x00000777)

Offset: 0x50

Register Name: PC_CFG2_REG

Bit

R/W

Default/Hex

Description

31:11

/

/

/

10:8

R/W

0x7

/

7

/

/

/

6:4

R/W

0x7

/

3

/

/

/

0x7

PC16_SELECT
000:Input
010:NAND_DQS
100:Reserved
110:Reserved

2:0

R/W

A64 User Manual(Revision 1.0)

001:Output
011:SDC2_RST
101:Reserved
111:IO Disable

Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.

Page 382

System

3.21.2.13.

PC Configure Register 3 (Default Value: 0x00000000)

Offset: 0x54

Register Name: PC_CFG3_REG

Bit

R/W

Default/Hex

Description

31:0

/

/

/

3.21.2.14.

PC Data Register (Default Value: 0x00000000)

Offset: 0x58

Register Name: PC_DATA_REG

Bit

R/W

Default/Hex

Description

31:19

/

/

/

0x0

PC_DAT
If the port is configured as input, the corresponding bit is the pin state. If
the port is configured as output, the pin state is the same as thecorresponding bit. The read bit value is the value setup by software. If theport is configured as functional pin, the undefined value will be read.

18:0

R/W

3.21.2.15.

PC Multi-Driving Register 0 (Default Value: 0x55555555)

Offset: 0x5C
Bit

Register Name: PC_DRV0_REG

R/W

Default/Hex

Description

0x1

PC_DRV
PC[n] Multi-Driving SELECT (n = 0~15)
00: Level 0
01: Level 1
10: Level 2
11: Level 3[2i+1:2i](i=0~15)

R/W

3.21.2.16.

PC Multi-Driving Register 1 (Default Value: 0x00000015)

Offset: 0x60

Register Name: PC_DRV1_REG

Bit

R/W

Default/Hex

Description

31:6

/

/

/

0x1

PC_DRV
PC[n] Multi-Driving Select (n = 16~18)00: Level 0
01: Level 1
10: Level 2
11: Level 3[2i+1:2i](i=0~2)R/W

A64 User Manual(Revision 1.0)

Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.

Page 383

System
3.21.2.17.

PC PULL Register 0 (Default Value: 0x00005140)

Offset: 0x64
Bit

Register Name: PC_PULL0_REG

R/W

Default/Hex

Description

0x5140

PC_PULL
PC[n] Pull-up/down Select (n = 0~15)
00: Pull-up/down disable
01: Pull-up
10: Pull-down
11: Reserved[2i+1:2i](i=0~15)

R/W

3.21.2.18.

PC PULL Register 1 (Default Value: 0x00000014)

Offset: 0x68

Register Name: PC_PULL1_REG

Bit

R/W

Default/Hex

Description

31:6

/

/

Reserved

0x14

PC_PULL
PC[n] Pull-up/down Select (n = 16~18)00: Pull-up/down disable
01: Pull-up
10: Pull-down
11: Reserved[2i+1:2i](i=0~2)

R/W

3.21.2.19.

PD Configure Register 0 (Default Value: 0x77777777)

Offset: 0x6C

Register Name: PD_CFG0_REG

Bit

R/W

Default/Hex

Description

31

/

/

/

30:28

R/W

0x7

PD7_SELECT
000: Input
010: LCD_D11
100: Reserved
110: Reserved

27

/

/

Reserved

26:24

R/W

0x7

PD6_SELECT
000: Input
010: LCD_D10
100: Reserved
110: Reserved

23

/

/

/

0x7

PD5_SELECT
000: Input
010: LCD_D7
100: Reserved
110: Reserved

22:20

R/W

A64 User Manual(Revision 1.0)

001: Output
011: Reserved
101: CCIR_D3
111: IO Disable

001: Output
011: Reserved
101: CCIR_D2
111: IO Disable

001: Output
011: UART4_CTS
101: CCIR_D1
111: IO Disable

Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.

Page 384

System
19

/

/

/

18:16

R/W

0x7

PD4_SELECT
000: Input
010: LCD_D6
100: Reserved
110: Reserved

15

/

/

/

14:12

R/W

0x7

PD3_SELECT
000: Input
010: LCD_D5
100: SPI1_MISO
110: Reserved

11

/

/

/

10:8

R/W

0x7

PD2_SELECT
000: Input
010: LCD_D4
100: SPI1_MOSI
110: Reserved

7

/

/

/

6:4

R/W

0x7

PD1_SELECT
000: Input
010: LCD_D3
100: SPI1_CLK
110: Reserved

3

/

/

/

0x7

PD0_SELECT
000: Input
010: LCD_D2
100: SPI1_CS
110: Reserved

2:0

R/W

3.21.2.20.

PD Configure Register 1 (Default Value: 0x77777777)

Offset: 0x70

001: Output
011: UART4_RTS
101: CCIR_D0
111: IO Disable

001: Output
011: UART4_RX
101: CCIR_VSYNC
111: IO Disable

001: Output
011: UART4_TX
101: CCIR_HSYNC
111: IO Disable

001: Output
011: UART3_RX
101: CCIR_DE
111: IO Disable

001: Output
011: UART3_TX
101: CCIR_CLK
111: IO Disable

Register Name: PD_CFG1_REG

Bit

R/W

Default/Hex

Description

31

/

/

/

30:28

R/W

0x7

PD15_SELECT
000: Input
001: Output
010: LCD_D21
011: LVDS_VN1
100: RGMII_TXD3/MII_TXD3/RMII_NULL 101: CCIR_D6
110: Reserved
111: IO Disable

27

/

/

/

A64 User Manual(Revision 1.0)

Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.

Page 385

System

26:24

R/W

0x7

PD14_SELECT
000: Input
001: Output
010: LCD_D20
011: LVDS_VP1
100: RGMII_NULL/MII_RXERR/RMII_RXER 101: Reserved
110: Reserved
111: IO Disable

23

/

/

/

22:20

R/W

0x7

PD13_SELECT
000: Input
001: Output
010: LCD_D19
011: LVDS_VN0
100: RGMII_RXCTL/MII_RXDV/RMII_CRS_DV 101: Reserved
110: Reserved
111: IO Disable

19

/

/

/

18:16

R/W

0x7

PD12_SELECT
000: Input
001: Output
010: LCD_D18
011: LVDS_VP0
100: RGMII_RXCK/MII_RXCK/RMII_NULL 101: Reserved
110: Reserved
111: IO Disable

15

/

/

/

14:12

R/W

0x7

PD11_SELECT
000: Input
001: Output
010: LCD_D15
011: Reserved
100: RGMII_RXD0/MII_RXD0/RMII_RXD0 101: Reserved
110: Reserved
111: IO Disable

11

/

/

/

10:8

R/W

0x7

PD10_SELECT
000: Input
001: Output
010: LCD_D14
011: Reserved
100: RGMII_RXD1/MII_RXD1/RMII_RXD1 101: Reserved
110: Reserved
111: IO Disable

7

/

/

/

6:4

R/W

0x7

PD9_SELECT
000: Input
001: Output
010: LCD_D13
011: Reserved
100: RGMII_RXD2/MII_RXD2/RMII_NULL 101: CCIR_D5
110: Reserved
111: IO Disable

3

/

/

/

0x7

PD8_SELECT
000: Input
001: Output
010: LCD_D12
011: Reserved
100: RGMII_RXD3/MII_RXD3/RMII_NULL 101: CCIR_D4
110: Reserved
111: IO Disable

2:0

R/W

A64 User Manual(Revision 1.0)

Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.

Page 386

System
3.21.2.21.

PD Configure Register 2 (Default Value: 0x77777777)

Offset: 0x74

Register Name: PD_CFG2_REG

Bit

R/W

Default/Hex

Description

31

/

/

/

30:28

R/W

0x7

PD23_SELECT
000: Input
010: Reserved
100: MDIO
110: Reserved

27

/

/

/

26:24

R/W

0x7

PD22_SELECT
000: Input
010: PWM0100: MDC
110: Reserved

23

/

/

/

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

22:20

R/W

0x7

PD21_SELECT
000: Input
001: Output
010: LCD_VSYNC
011: LVDS_VN3
100: RGMII_CLKIN/MII_COL/RMII_NULL 101: Reserved
110: Reserved
111: IO Disable

19

/

/

/

18:16

R/W

0x7

PD20_SELECT
000: Input
001: Output
010: LCD_HSYNC
011: LVDS_VP3
100: RGMII_TXCTL/MII_TXEN/RMII_TXEN 101: Reserved
110: Reserved
111: IO Disable

15

/

/

/

14:12

R/W

0x7

PD19_SELECT
000: Input
001: Output
010: LCD_DE
011: LVDS_VNC
100: RGMII_TXCK/MII_TXCK/RMII_TXCK 101: Reserved
110: Reserved
111: IO Disable

11

/

/

/

10:8

R/W

0x7

PD18_SELECT
000: Input
001: Output
010: LCD_CLK
011: LVDS_VPC
100: RGMII_TXD0/MII_TXD0/RMII_TXD0 101: Reserved
110: Reserved
111: IO Disable

7

/

/

/

0x7

PD17_SELECT
000: Input

6:4

R/W

A64 User Manual(Revision 1.0)

001: Output

Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.

Page 387

System
010: LCD_D23
011: LVDS_VN2
100: RGMII_TXD1/MII_TXD1/RMII_TXD1 101: Reserved
110: Reserved
111: IO Disable
3

/

/

/

0x7

PD16_SELECT
000: Input
001: Output
010: LCD_D22
011: LVDS_VP2
100: RGMII_TXD2/MII_TXD2/RMII_NULL 101: CCIR_D7
110: Reserved
111: IO Disable

2:0

R/W

3.21.2.22.

PD Configure Register 3 (Default Value: 0x00000007)

Offset: 0x78

Register Name: PD_CFG3_REG

Bit

R/W

Default/Hex

Description

31:3

/

/

/

0x7

PD24_SELECT
000: Input
010: Reserved
100: Reserved
110: Reserved

2:0

R/W

3.21.2.23.

PD Data Register (Default Value: 0x00000000)

Offset: 0x7C

001: Output
011: Reserved
101: Reserved
111: IO Disable

Register Name: PD_DATA _REG

Bit

R/W

Default/Hex

Description

31:25

/

/

/

0

PD_DAT
If the port is configured as input, the corresponding bit is the pin state. If
the port is configured as output, the pin state is the same as thecorresponding bit. The read bit value is the value setup by software. If theport is configured as functional pin, the undefined value will be read.

24:0

R/W

3.21.2.24.

PD Multi-Driving Register 0 (Default Value: 0x55555555)

Offset: 0x80
Bit

[2i+1:2i](i=0~15)

R/W

R/W

Register Name: PD_DRV0_REG
Default/Hex

Description

0x1

PD_DRV
PD[n] Multi-Driving SELECT (n = 0~15)
00: Level 0
01: Level 1
10: Level 2
11: Level 3

A64 User Manual(Revision 1.0)

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Page 388

System

3.21.2.25.

PD Multi-Driving Register 1 (Default Value: 0x00015555)

Offset: 0x84

Register Name: PD_DRV1_REG

Bit

R/W

Default/Hex

Description

31:18

/

/

/

0x1

PD_DRV
PD[n] Multi-Driving Select (n = 16~24)
00: Level 0
01: Level 1
10: Level 2
11: Level 3[2i+1:2i](i=0~8)R/W

3.21.2.26.

PD PULL Register 0 (Default Value: 0x00000000)

Offset: 0x88
Bit

Register Name: PD_PULL0_REG

R/W

Default/Hex

Description

0x0

PD_PULL
PD[n] Pull-up/down Select (n = 0~15)
00: Pull-up/down disable
01: Pull-up
10: Pull-down
11: Reserved[2i+1:2i](i=0~15)

R/W

3.21.2.27.

PD PULL Register 1 (Default Value: 0x00000000)

Offset: 0x8C

Register Name: PD_PULL1_REG

Bit

R/W

Default/Hex

Description

31:18

/

/

Reserved

0x0

PD_PULL
PD[n] Pull-up/down Select (n = 16~24)
00: Pull-up/down disable
01: Pull-up
10: Pull-down
11: Reserved[2i+1:2i](i=0~8)R/W

3.21.2.28.

PE Configure Register 0 (Default Value: 0x77777777)

Offset: 0x90

Register Name: PE_CFG0_REG

Bit

R/W

Default/Hex

Description

31

/

/

/

0x7

PE7_SELECT
000: Input
010: CSI_D3

30:28

R/W

A64 User Manual(Revision 1.0)

001: Output
011: Reserved

Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.

Page 389

System
100: TS_D3
110: Reserved
27

/

/

/

26:24

R/W

0x7

PE6_SELECT
000: Input
010: CSI_D2
100: TS_D2
110: Reserved

23

/

/

/

22:20

R/W

0x7

PE5_SELECT
000: Input
010: CSI_D1
100: TS_D1
110: Reserved

19

/

/

/

18:16

R/W

0x7

PE4_SELECT
000: Input
010: CSI_D0
100: TS_D0
110: Reserved

15

/

/

/

14:12

R/W

0x7

PE3_SELECT
000: Input
010: CSI_VSYNC
100: TS_DVLD
110: Reserved

11

/

/

/

10:8

R/W

0x7

PE2_SELECT
000: Input
010: CSI_HSYNC
100: TS_SYNC
110: Reserved

7

/

/

/

6:4

R/W

0x7

PE1_SELECT
000: Input
010: CSI_MCLK
100: TS_ERR
110: Reserved

3

/

/

/

0x7

PE0_SELECT
000: Input
010: CSI_PCLK
100: TS_CLK
110: Reserved

2:0

R/W

A64 User Manual(Revision 1.0)

101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.

Page 390

System

3.21.2.29.

PE Configure Register 1 (Default Value: 0x77777777)

Offset: 0x94

Register Name: PE_CFG1_REG

Bit

R/W

Default/Hex

Description

31

/

/

/

30:28

R/W

0x7

PE15_SELECT
000: Input
010: Reserved
100: Reserved
110: Reserved

27

/

/

/

26:24

R/W

0x7

PE14_SELECT
000: Input
010: PLL_LOCK_DBG
100: Reserved
110: Reserved

23

/

/

/

22:20

R/W

0x7

PE13_SELECT
000: Input
010: CSI_SDA
100: Reserved
110: Reserved

19

/

/

/

18:16

R/W

0x7

PE12_SELECT
000: Input
010: CSI_SCK
100: Reserved
110: Reserved

15

/

/

/

14:12

R/W

0x7

PE11_SELECT
000: Input
010: CSI_D7
100: TS_D7
110: Reserved

11

/

/

/

10:8

R/W

0x7

PE10_SELECT
000: Input
010: CSI_D6
100: TS_D6
110: Reserved

7

/

/

/

A64 User Manual(Revision 1.0)

001: Output
011: TWI2_SDA
101: Reserved
111: IO Disable

001: Output
011: TWI2_SCK
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.

Page 391

System

6:4

R/W

0x7

PE9_SELECT
000: Input
010: CSI_D5
100: TS_D5
110: Reserved

3

/

/

/

0x7

PE8_SELECT
000: Input
010: CSI_D4
100: TS_D4
110: Reserved

2:0

R/W

3.21.2.30.

PE Configure Register 2 (Default Value: 0x00000077)

Offset: 0x98

001: Output
011: Reserved
101: Reserved
111: IO Disable

Register Name: PE_CFG2_REG

Bit

R/W

Default/Hex

Description

31:7

/

/

/

6:4

R/W

0x7

PE17_SELECT
000: Input
010: Reserved
100: Reserved
110: Reserved

3

/

/

/

0x7

PE16_SELECT
000: Input
010: Reserved
100: Reserved
110: Reserved

2:0

R/W

3.21.2.31.

PE Configure Register 3 (Default Value: 0x00000000)

Offset: 0x9C

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

Register Name: PE_CFG3_REG

Bit

R/W

Default/Hex

Description

31:0

/

/

/

3.21.2.32.

001: Output
011: Reserved
101: Reserved
111: IO Disable

PE Data Register (Default Value: 0x00000000)

Offset: 0xA0

Register Name: PE_DATA _REG

Bit

R/W

Default/Hex

Description

31:18

/

/

/

A64 User Manual(Revision 1.0)

Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.

Page 392

System

0x0

PE_DAT
If the port is configured as input, the corresponding bit is the pin state. If
the port is configured as output, the pin state is the same as thecorresponding bit. The read bit value is the value setup by software. If theport is configured as functional pin, the undefined value will be read.

17:0

R/W

3.21.2.33.

PE Multi-Driving Register 0 (Default Value: 0x55555555)

Offset: 0xA4
Bit

Register Name: PE_DRV0_REG

R/W

Default/Hex

Description

0x1

PE_DRVPE[n] Multi-Driving SELECT (n = 0~15)
00: Level 0
01: Level 1
10: Level 2
11: Level 3[2i+1:2i](i=0~15)

R/W

3.21.2.34.

PE Multi-Driving Register 1 (Default Value: 0x00000005)

Offset: 0xA8

Register Name: PE_DRV1_REG

Bit

R/W

Default/Hex

Description

31:4

/

/

/

0x1

PE_DRVPE[n] Multi-Driving Select (n = 16~17)00: Level 0
01: Level 1
10: Level 2
11: Level 3[2i+1:2i](i=0~1)

R/W

3.21.2.35.

PE PULL Register 0 (Default Value: 0x00000000)

Offset: 0xAC
Bit

Register Name: PE_PULL0_REG

R/W

Default/Hex

Description

0x0

PE_PULL
PE[n] Pull-up/down Select (n = 0~15)
00: Pull-up/down disable
01: Pull-up
10: Pull-down
11: Reserved[2i+1:2i](i=0~15)

R/W

3.21.2.36.

PE PULL Register 1 (Default Value: 0x00000000)

Offset: 0xB0
Bit

R/W

Register Name: PE_PULL1_REG
Default/Hex

A64 User Manual(Revision 1.0)

Description

Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.

Page 393

System
31:4

/

/

/

0x0

PE_PULL
PE[n] Pull-up/down Select (n = 16~17)00: Pull-up/down disable
01: Pull-up
10: Pull-down
11: Reserved[2i+1:2i](i=0~1)

R/W

3.21.2.37.

PF Configure Register 0 (Default Value: 0x07777777)

Offset: 0xB4

Register Name: PF_CFG0_REG

Bit

R/W

Default/Hex

Description

31:27

/

/

/

26:24

R/W

0x7

PF6_SELECT
000: Input
010: Reserved
100: Reserved
110: Reserved

23

/

/

/

22:20

R/W

0x7

PF5_SELECT
000: Input
010: SDC0_D2
100: Reserved
110: Reserved

19

/

/

/

18:16

R/W

0x7

PF4_SELECT
000: Input
010: SDC0_D3
100: Reserved
110: Reserved

15

/

/

/

14:12

R/W

0x7

PF3_SELECT
000: Input
010: SDC0_CMD
100: Reserved
110: Reserved

11

/

/

/

10:8

R/W

0x7

PF2_SELECT
000: Input
010: SDC0_CLK
100: Reserved
110: Reserved

7

/

/

/

6:4

R/W

0x7

PF1_SELECT

A64 User Manual(Revision 1.0)

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: JTAG_CK1
101: Reserved
111: IO Disable

001: Output
011: UART0_RX
101: Reserved
111: IO Disable

001: Output
011: JTAG_DO1
101: Reserved
111: IO Disable

001: Output
011: UART0_TX
101: Reserved
111: IO Disable

Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.

Page 394

System
000: Input
010: SDC0_D0
100: Reserved
110: Reserved
3

/

/

/

0x7

PF0_SELECT
000: Input
010: SDC0_D1
100: Reserved
110: Reserved

2:0

R/W

3.21.2.38.

PF Configure Register 1 (Default Value: 0x00000000)

Offset: 0xB8001: Output
011: JTAG_MS1
101: Reserved
111: IO Disable

Register Name: PF_CFG1_REG

Bit

R/W

Default/Hex

Description

31:0

/

/

/

3.21.2.39.

001: Output
011: JTAG_DI1
101: Reserved
111: IO Disable

PF Configure Register 2(Default Value: 0x00000000)

Offset: 0xBC

Register Name: PF_CFG2_REG

Bit

R/W

Default/Hex

Description

31:0

/

/

/

3.21.2.40.

PF Configure Register 3(Default Value: 0x00000000)

Offset: 0xC0

Register Name: PF_CFG3_REG

Bit

R/W

Default/Hex

Description

31:0

/

/

/

3.21.2.41.

PF Data Register (Default Value: 0x00000000)

Offset: 0xC4

Register Name: PF_DATA_REG

Bit

R/W

Default/Hex

Description

31:7

/

/

/

0x0

PF_DAT
If the port is configured as input, the corresponding bit is the pin state. If
the port is configured as output, the pin state is the same as thecorresponding bit. The read bit value is the value setup by software. If the

6:0

R/W

A64 User Manual(Revision 1.0)

Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.

Page 395

Systemport is configured as functional pin, the undefined value will be read.

3.21.2.42.

PF Multi-Driving Register 0 (Default Value: 0x00001555)

Offset: 0xC8

Register Name: PF_DRV0_REG

Bit

R/W

Default/Hex

Description

31:14

/

/

/

0x1

PF_DRVPF[n] Multi-Driving SELECT (n = 0~6)00: Level 0
01: Level 1
10: Level 2
11: Level 3[2i+1:2i](i=0~6)

R/W

3.21.2.43.

PF Multi-Driving Register 1 (Default Value: 0x00000000)

Offset: 0xCC

Register Name: PF_DRV1_REG

Bit

R/W

Default/Hex

Description

31:0

/

/

/

3.21.2.44.

PF PULL Register 0 (Default Value: 0x00000000)

Offset: 0xD0

Register Name: PF_PULL0_REG

Bit

R/W

Default/Hex

Description

31:14

/

/

/

0x0

PF_PULL
PF[n] Pull-up/down Select (n = 0~6)00: Pull-up/down disable
01: Pull-up
10: Pull-down
11: Reserved[2i+1:2i](i=0~6)

R/W

3.21.2.45.

PF PULL Register 1 (Default Value: 0x00000000)

Offset: 0xD4

Register Name: PF_PULL1_REG

Bit

R/W

Default/Hex

Description

31:0

/

/

/

3.21.2.46.

PG Configure Register 0 (Default Value: 0x77777777)

Offset: 0xD8

A64 User Manual(Revision 1.0)

Register Name: PG_CFG0_REG

Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.

Page 396

System
Bit

R/W

Default/Hex

Description

31

/

/

/

30:28

R/W

0x7

PG7_SELECT
000: Input
010: UART1_RX
100: Reserved
110: PG_EINT7

27

/

/

/

26:24

R/W

0x7

PG6_SELECT
000: Input
010: UART1_TX
100: Reserved
110: PG_EINT6

23

/

/

/

22:20

R/W

0x7

PG5_SELECT
000: Input
010: SDC1_D3
100: Reserved
110: PG_EINT5

19

/

/

/

18:16

R/W

0x7

PG4_SELECT
000: Input
010: SDC1_D2
100: Reserved
110: PG_EINT4

15

/

/

/

14:12

R/W

0x7

PG3_SELECT
000: Input
010: SDC1_D1
100: Reserved
110: PG_EINT3

11

/

/

/

10:8

R/W

0x7

PG2_SELECT
000: Input
010: SDC1_D0
100: Reserved
110: PG_EINT2

7

/

/

/

6:4

R/W

0x7

PG1_SELECT
000: Input
010: SDC1_CMD
100: Reserved
110: PG_EINT1

3

/

/

/

A64 User Manual(Revision 1.0)

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.

Page 397

System

0x7

PG0_SELECT
000: Input
010: SDC1_CLK
100: Reserved
110: PG_EINT0

2:0

R/W

3.21.2.47.

PG Configure Register 1 (Default Value: 0x00777777)

Offset: 0xDC

001: Output
011: Reserved
101: Reserved
111: IO Disable

Register Name: PG_CFG1_REG

Bit

R/W

Default/Hex

Description

31:23

/

/

/

22:20

R/W

0x7

PG13_SELECT
000: Input
010: AIF3_DIN
100: Reserved
110: PG_EINT13

19

/

/

/

18:16

R/W

0x7

PG12_SELECT
000: Input
010: AIF3_DOUT
100: Reserved
110: PG_EINT12

15

/

/

/

14:12

R/W

0x7

PG11_SELECT
000: Input
010: AIF3_BCLK
100: Reserved
110: PG_EINT11

11

/

/

/

10:8

R/W

0x7

PG10_SELECT
000: Input
010: AIF3_SYNC
100: Reserved
110: PG_EINT10

7

/

/

/

6:4

R/W

0x7

PG9_SELECT
000: Input
010: UART1_CTS
100: Reserved
110: PG_EINT9

3

/

/

/

2:0

R/W

0x7

PG8_SELECT

A64 User Manual(Revision 1.0)

001: Output
011: PCM1_DIN
101: Reserved
111: IO Disable

001: Output
011: PCM1_DOUT
101: Reserved
111: IO Disable

001: Output
011: PCM1_BCLK
101: Reserved
111: IO Disable

001: Output
011: PCM1_SYNC
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.

Page 398

System
000: Input
010: UART1_RTS
100: Reserved
110: PG_EINT8

3.21.2.48.

001: Output
011: Reserved
101: Reserved
111: IO Disable

PG Configure Register 2 (Default Value: 0x00000000)

Offset: 0xE0

Register Name: PG_CFG2_REG

Bit

R/W

Default/Hex

Description

31:0

/

/

/

3.21.2.49.

PG Configure Register 3 (Default Value: 0x00000000)

Offset: 0xE4

Register Name: PG_CFG3_REG

Bit

R/W

Default/Hex

Description

31:0

/

/

/

3.21.2.50.

PG Data Register (Default Value: 0x00000000)

Offset: 0xE8

Register Name: PG_DATA_REG

Bit

R/W

Default/Hex

Description

31:14

/

/

/

0x0

PG_DAT
If the port is configured as input, the corresponding bit is the pin state. If
the port is configured as output, the pin state is the same as thecorresponding bit. The read bit value is the value setup by software. If theport is configured as functional pin, the undefined value will be read.

13:0

R/W

3.21.2.51.

PG Multi-Driving Register 0 (Default Value: 0x05555555)

Offset: 0xEC

Register Name: PG_DRV0_REG

Bit

R/W

Default/Hex

Description

31:28

/

/

/

0x1

PG_DRV
PG[n] Multi-Driving SELECT (n = 0~13)00: Level 0
01: Level 1
10: Level 2
11: Level 3[2i+1:2i](i=0~13)R/W

A64 User Manual(Revision 1.0)

Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.

Page 399

System
3.21.2.52.

PG Multi-Driving Register 1 (Default Value: 0x00000000)

Offset: 0xF0

Register Name: PG_DRV1_REG

Bit

R/W

Default/Hex

Description

31:0

/

/

/

3.21.2.53.

PG PULL Register 0 (Default Value: 0x00000000)

Offset: 0xF4

Register Name: PG_PULL0_REG

Bit

R/W

Default/Hex

Description

31:28

/

/

/

0x0

PF_PULL
PF[n] Pull-up/down Select (n = 0~13)00: Pull-up/down disable
01: Pull-up
10: Pull-down
11: Reserved[2i+1:2i](i=0~13)

R/W

3.21.2.54.

PG PULL Register 1 (Default Value: 0x00000000)

Offset: 0xF8

Register Name: PG_PULL1_REG

Bit

R/W

Default/Hex

Description

31:0

/

/

/

3.21.2.55.

PH Configure Register 0 (Default Value: 0x77777777)

Offset: 0xFC

Register Name: PH_CFG0_REG

Bit

R/W

Default/Hex

Description

31

/

/

/

30:28

R/W

0x7

PH7_SELECT
000: Input
010: UART3_CTS
100: Reserved
110: PH_EINT7

27

/

/

/

26:24

R/W

0x7

PH6_SELECT
000: Input
010: UART3_RTS
100: Reserved
110: PH_EINT6

23

/

/

/

A64 User Manual(Revision 1.0)

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.

Page 400

System

22:20

R/W

0x7

PH5_SELECT
000: Input
010: UART3_RX
100: Reserved
110: PH_EINT5

19

/

/

/

18:16

R/W

0x7

PH4_SELECT
000: Input
010: UART3_TX
100: Reserved
110: PH_EINT4

15

/

/

/

14:12

R/W

0x7

PH3_SELECT
000: Input
010: TWI1_SDA
100: Reserved
110: PH_EINT3

11

/

/

/

10:8

R/W

0x7

PH2_SELECT
000: Input
010: TWI1_SCK
100: Reserved
110: PH_EINT2

7

/

/

/

6:4

R/W

0x7

PH1_SELECT
000: Input
010: TWI0_SDA
100: Reserved
110: PH_EINT1

3

/

/

/

0x7

PH0_SELECT
000: Input
010: TWI0_SCK
100: Reserved
110: PH_EINT0

2:0

R/W

3.21.2.56.

PH Configure Register 1 (Default Value: 0x00007777)

Offset: 0x100

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

Register Name: PH_CFG1_REG

Bit

R/W

Default/Hex

Description

31:15

/

/

/

14:12

R/W

0x7

PH11_SELECT

A64 User Manual(Revision 1.0)

Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.

Page 401

System
000: Input
010: MIC_DATA
100: Reserved
110: PH_EINT11
11

/

/

/

10:8

R/W

0x7

PH10_SELECT
000: Input
010: MIC_CLK
100: Reserved
110: PH_EINT10

7

/

/

/

6:4

R/W

0x7

PH9_SELECT
000: Input
010: Reserved
100: Reserved
110: PH_EINT9

3

/

/

/

0x7

PH8_SELECT
000: Input
010: OWA_OUT
100: Reserved
110: PH_EINT8

2:0

R/W

3.21.2.57.

PH Configure Register 2 (Default Value: 0x00000000)

Offset: 0x104

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

Register Name: PH_CFG2_REG

Bit

R/W

Default/Hex

Description

31:0

/

/

/

3.21.2.58.

001: Output
011: Reserved
101: Reserved
111: IO Disable

PH Configure Register 3 (Default Value: 0x00000000)

Offset: 0x108

Register Name: PH_CFG3_REG

Bit

R/W

Default/Hex

Description

31:0

/

/

/

3.21.2.59.

PH Data Register (Default Value: 0x00000000)

Offset: 0x10C

Register Name: PH_DATA_REG

Bit

R/W

Default/Hex

Description

31:12

/

/

/

A64 User Manual(Revision 1.0)

Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.

Page 402

System
PH_DAT
If the port is configured as input, the corresponding bit is the pin state. If
the port is configured as output, the pin state is the same as thecorresponding bit. The read bit value is the value setup by software.
0

If the port is configured as functional pin, the undefined value will
be read.

11:0

R/W

3.21.2.60.

PH Multi-Driving Register 0 (Default Value: 0x00555555)

Offset: 0x110

Register Name: PH_DRV0_REG

Bit

R/W

Default/Hex

Description

31:24

/

/

/

0x1

PH_DRVPH[n] Multi-Driving Select (n = 0~11)00: Level 0
01: Level 1
10: Level 2
11: Level 3[2i+1:2i](i=0~11)

R/W

3.21.2.61.

PH Multi-Driving Register 1 (Default Value: 0x00000000)

Offset: 0x114

Register Name: PH_DRV1_REG

Bit

R/W

Default/Hex

Description

31:0

/

/

/

3.21.2.62.

PH PULL Register 0 (Default Value: 0x00000000)

Offset: 0x118

Register Name: PH_PULL0_REG

Bit

R/W

Default/Hex

Description

31:24

/

/

/

0

PH_PULL
PH[n] Pull-up/down Select (n = 0~11)00: Pull-up/down disable
01: Pull-up
10: Pull-down
11: Reserved[2i+1:2i](i=0~11)

R/W

3.21.2.63.

PH PULL Register 1 (Default Value: 0x00000000)

Offset: 0x11C

Register Name: PH_PULL1_REG

Bit

R/W

Default/Hex

Description

31:0

/

/

/

A64 User Manual(Revision 1.0)

Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.

Page 403

System

3.21.2.64.

PB External Interrupt Configure Register 0 (Default Value: 0x00000000)

Offset: 0x200
Bit

Register Name: PB_EINT_CFG0_REG

R/W

Default/Hex

Description

0

EINT_CFG
External INTn Mode (n = 0~7)
0x0: Positive Edge
0x1: Negative Edge
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/ Negative)
Others: Reserved[4i+3:4i](i=0~7)R/W

3.21.2.65.

PB External Interrupt Configure Register 1 (Default Value: 0x00000000)

Offset: 0x204

Register Name: PB_EINT_CFG1_REG

Bit

R/W

Default/Hex

Description

31:8

/

/

/

0

EINT_CFG
External INTn Mode (n = 8~9)0x0: Positive Edge
0x1: Negative Edge
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/ Negative)
Others: Reserved[4i+3:4i](i=0~1)

R/W

3.21.2.66.

PB External Interrupt Configure Register 2 (Default Value: 0x00000000)

Offset: 0x208

Register Name: PB_EINT_CFG2_REG

Bit

R/W

Default/Hex

Description

31:0

/

/

/

3.21.2.67.

PB External Interrupt Configure Register 3 (Default Value: 0x00000000)

Offset: 0x20C
Bit

R/W

Register Name: PB_EINT_CFG3_REG
Default/Hex

A64 User Manual(Revision 1.0)

Description

Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.

Page 404

System
31:0/

3.21.2.68.

//

PB External Interrupt Control Register (Default Value: 0x00000000)

Offset: 0x210

Register Name: PB_EINT_CTL_REG

Bit

R/W

Default/Hex

Description

31:10

/

/

/

0

EINT_CTL
External INTn Enable (n = 0~9)
0: Disable
1: Enable[n](n=0~9)R/W

3.21.2.69.

PB External Interrupt Status Register (Default Value: 0x00000000)

Offset: 0x214

Register Name: PB_EINT_STATUS_REG

Bit

R/W

Default/Hex

Description

31:10

/

/

/

0

EINT_STATUS
External INTn Pending Bit (n = 0~9)
0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear[n](n=0~9)R/W

3.21.2.70.

PB External Interrupt Debounce Register (Default Value: 0x00000000)

Offset: 0x218

Register Name: PB_EINT_DEB_REG

Bit

R/W

Default/Hex

Description

31:7

/

/

/

6:4

R/W

0

DEB_CLK_PRE_SCALE
Debounce Clock Pre-scale n
The selected clock source is prescaled by 2^n.

3:1

/

/

/

0

PIO_INT_CLK_SELECTPIO Interrupt Clock Select0: LOSC 32Khz
1: HOSC 24Mhz

0

R/W

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System
3.21.2.71.

PG External Interrupt Configure Register 0 (Default Value: 0x00000000)

Offset: 0x220
Bit

Register Name: PG_EINT_CFG0_REG

R/W

Default/Hex

Description

0

EINT_CFG
External INTn Mode (n = 0~7)
0x0: Positive Edge
0x1: Negative Edge
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/ Negative)
Others: Reserved[4i+3:4i](i=0~7)R/W

3.21.2.72.

PG External Interrupt Configure Register 1 (Default Value: 0x00000000)

Offset: 0x224

Register Name: PG_EINT_CFG1_REG

Bit

R/W

Default/Hex

Description

31:24

/

/

/

0

EINT_CFG
External INTn Mode (n = 8~13)
0x0: Positive Edge
0x1: Negative Edge
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/ Negative)
Others: Reserved[4i+3:4i](i=0~5)

R/W

3.21.2.73.

PG External Interrupt Configure Register 2 (Default Value: 0x00000000)

Offset: 0x228

Register Name: PG_EINT_CFG2_REG

Bit

R/W

Default/Hex

Description

31:0

/

/

/

3.21.2.74.

PG External Interrupt Configure Register 3 (Default Value: 0x00000000)

Offset: 0x22C

Register Name: PG_EINT_CFG3_REG

Bit

R/W

Default/Hex

Description

31:0

/

/

/

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System
3.21.2.75.

PG External Interrupt Control Register (Default Value: 0x00000000)

Offset: 0x230

Register Name: PG_EINT_CTL_REG

Bit

R/W

Default/Hex

Description

31:14

/

/

/

0

EINT_CTL
External INTn Enable (n = 0~13)
0: Disable
1: Enable[n](n=0~13)

R/W

3.21.2.76.

PG External Interrupt Status Register (Default Value: 0x00000000)

Offset: 0x234

Register Name: PG_EINT_STATUS_REG

Bit

R/W

Default/Hex

Description

31:14

/

/

/

0

EINT_STATUS
External INTn Pending Bit (n = 0~13)
0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear[n](n=0~13)

R/W

3.21.2.77.

PG External Interrupt Debounce Register (Default Value: 0x00000000)

Offset: 0x238

Register Name: PG_EINT_DEB_REG

Bit

R/W

Default/Hex

Description

31:7

/

/

/

6:4

R/W

0

DEB_CLK_PRE_SCALE
Debounce Clock Pre-scale n
The selected clock source is prescaled by 2^n.

3:1

/

/

/

0

PIO_INT_CLK_SELECTPIO Interrupt Clock Select0: LOSC 32Khz
1: HOSC 24Mhz

0R/W

3.21.2.78.

PH External Interrupt Configure Register 0 (Default Value: 0x00000000)

Offset: 0x240
Bit

R/W

Register Name: PH_EINT_CFG0_REG
Default/Hex

A64 User Manual(Revision 1.0)

Description

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Page 407

System
EINT_CFG
External INTn Mode (n = 0~7)
0x0: Positive Edge
0x1: Negative Edge
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/ Negative)
Others: Reserved[4i+3:4i](i=0~7)R/W

3.21.2.79.

PH External Interrupt Configure Register 1 (Default Value: 0x00000000)

0Offset: 0x244

Register Name: PH_EINT_CFG1_REG

Bit

R/W

Default/Hex

Description

31:16

/

/

/

0

ENT_CFG
External INTn Mode (n = 8~11)0x0: Positive Edge
0x1: Negative Edge
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/ Negative)
Others: Reserved[4i+3:4i](i=0~3)R/W

3.21.2.80.

PH External Interrupt Configure Register2 (Default Value: 0x00000000)

Offset: 0x248

Register Name: PH_EINT_CFG2_REG

Bit

R/W

Default/Hex

Description

31:0

/

/

/

3.21.2.81.

PH External Interrupt Configure Register3 (Default Value: 0x00000000)

Offset: 0x24C

Register Name: PH_EINT_CFG3_REG

Bit

R/W

Default/Hex

Description

31:0

/

/

/

3.21.2.82.

PH External Interrupt Control Register (Default Value: 0x00000000)

Offset: 0x250

A64 User Manual(Revision 1.0)

Register Name: PH_EINT_CTL_REG

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System
Bit

R/W

Default/Hex

Description

31:14

/

/

/

0

EINT_CTL
External INTn Enable (n = 0~11)
0: Disable
1: Enable[n](n=0~11)

R/W

3.21.2.83.

PH External Interrupt Status Register (Default Value: 0x00000000)

Offset: 0x254

Register Name: PH_EINT_STATUS_REG

Bit

R/W

Default/Hex

Description

31:12

/

/

/

0

EINT_STATUS
External INTn Pending Bit (n = 0~11)
0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear[n](n=0~11)

R/W

3.21.2.84.

PH External Interrupt Debounce Register (Default Value: 0x00000000)

Offset: 0x258

Register Name: PH_EINT_DEB_REG

Bit

R/W

Default/Hex

Description

31:7

/

/

/

6:4

R/W

0

DEB_CLK_PRE_SCALE
Debounce Clock Pre-scale n
The selected clock source is prescaled by 2^n.

3:1

/

/

/

0

PIO_INT_CLK_SELECTPIO Interrupt Clock Select0: LOSC 32Khz
1: HOSC 24Mhz

0

R/W

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System

3.22. Port Controller(CPUs-PORT)The chip has 1 port for multi-functional input/out pins. They are shown below:
Port L(PL):13 input/output port
For various system configurations, these ports can be easily configured by software. All these ports can be
configured as GPIO if multiplexed functions not used. The one group external PIO interrupt sources aresupported and interrupt mode can be configured by software.

3.22.1. Port Controller Register List
Module Name

Base Address

PIO

0x01F02C00

Register Name

OffsetDescription

PL_CFG0

0*0x24+0x00

Port L Configure Register 0

PL_CFG1

0*0x24+0x04

Port L Configure Register 1

PL_CFG2

0*0x24+0x08

Port L Configure Register 2

PL_CFG3

0*0x24+0x0C

Port L Configure Register 3

PL_DAT

0*0x24+0x10

Port L Data Register

PL_DRV00*0x24+0x14

Port L Multi-Driving Register 0

PL_DRV1

0*0x24+0x18

Port L Multi-Driving Register 1

PL_PUL00*0x24+0x1C

Port L Pull Register 0

PL_PUL1

0*0x24+0x20

Port L Pull Register 1

PL_INT_CFG0

0x200+0*0x20+0x00

PIO Interrrupt Configure Register 0

PL _INT_CFG1

0x200+0*0x20+0x04

PIO Interrrupt Configure Register 1

PL _INT_CFG2

0x200+0*0x20+0x08

PIO Interrrupt Configure Register 2

PL _INT_CFG3

0x200+0*0x20+0x0C

PIO Interrrupt Configure Register 3

PL _INT_CTL

0x200+0*0x20+0x10

PIO Interrupt Control Register

PL _INT_STA

0x200+0*0x20+0x14

PIO Interrupt Status Register

PL _INT_DEB

0x200+0*0x20+0x18

PIO Interrupt Debounce Register

3.22.2. Port Controller Register Description
3.22.2.1. PL Configure Register 0 (Default Value: 0x77777777)
Offset: 0x00
Bit

R/W

Register Name: PL_CFG0_REG
Default/Hex

A64 User Manual(Revision 1.0)

Description

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Page 410

System
31

/

/

/

30:28

R/W

0x7

PL7_SELECT
000: Input
010: S_JTAG_DI
100: Reserved
110: S_PL_EINT7

27

/

/

/

26:24

R/W

0x7

PL6_SELECT
000: Input
010: S_JTAG_DO
100: Reserved
110: S_PL_EINT6

23

/

/

/

22:20

R/W

0x7

PL5_SELECT
000: Input
010: S_JTAG_CK
100: Reserved
110: S_PL_EINT5

19

/

/

/

18:16

R/W

0x7

PL4_SELECT
000: Input
010: S_JTAG_MS
100: Reserved
110: S_PL_EINT4

15

/

/

/

14:12

R/W

0x7

PL3_SELECT
000: Input
010: S_UART_RX
100: Reserved
110: S_PL_EINT3

11

/

/

/

10:8

R/W

0x7

PL2_SELECT
000: Input
010: S_UART_TX
100: Reserved
110: S_PL_EINT2

7

/

/

/

6:4

R/W

0x7

PL1_SELECT
000: Input
010: S_RSB_SDA
100: Reserved
110: S_PL_EINT1

3

/

/

/

2:0

R/W

0x7

PL0_SELECT

A64 User Manual(Revision 1.0)

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: S_TWI_SDA
101: Reserved
111: IO Disable

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System
000: Input
010: S_RSB_SCK
100: Reserved
110: S_PL_EINT0001: Output
011: S_TWI_SCK
101: Reserved
111: IO Disable

3.22.2.2. PL Configure Register 1 (Default Value: 0x00077777)
Offset: 0x04

Register Name: PL_CFG1_REG

Bit

R/W

Default/Hex

Description

31:19

/

/

/

18:16

R/W

0x7

PL12_SELECT
000: Input
010: Reserved
100: Reserved
110: S_PL_EINT12

15

/

/

/

14:12

R/W

0x7

PL11_SELECT
000: Input
010: S_CIR_RX
100: Reserved
110: S_PL_EINT11

11

/

/

/

10:8

R/W

0x7

PL10_SELECT
000: Input
010: S_PWM
100: Reserved
110: S_PL_EINT10

7

/

/

/

6:4

R/W

0x7

PL9_SELECT
000: Input
010: S_TWI_SDA
100: Reserved
110: S_PL_EINT9

3

/

/

/

0x7

PL8_SELECT
000: Input
010: S_TWI_SCK
100: Reserved
110: S_PL_EINT8

2:0

R/W

A64 User Manual(Revision 1.0)

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

001: Output
011: Reserved
101: Reserved
111: IO Disable

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System
3.22.2.3. PL Configure Register 2 (Default Value: 0x00000000)
Offset: 0x08

Register Name: PL_CFG2_REG

Bit

R/W

Default/Hex

Description

31:0

/

/

/

3.22.2.4. PL Configure Register 3 (Default Value: 0x00000000)
Offset: 0x0C

Register Name: PL_CFG3_REG

Bit

R/W

Default/Hex

Description

31:0

/

/

/

3.22.2.5. PL Data Register (Default Value: 0x00000000)
Offset: 0x10

Register Name: PL_DATA_REG

Bit

R/W

Default/Hex

Description

31:13

/

/

/

0

PL_DAT
If the port is configured as input, the corresponding bit is the pin state. If
the port is configured as output, the pin state is the same as thecorresponding bit. The read bit value is the value setup by software. If theport is configured as functional pin, the undefined value will be read.

12:0

R/W

3.22.2.6. PL Multi-Driving Register 0 (Default Value: 0x01555555)
Offset: 0x14

Register Name: PL_DRV0

Bit

R/W

Default/Hex

Description

31:26

/

/

/

0x1

PL_DRVPL[n] Multi-Driving Select (n = 0~12)00: Level 0
01: Level 1
10: Level 2
11: Level 3[2i+1:2i](i=0~12)R/W

3.22.2.7. PL Multi-Driving Register 1 (Default Value: 0x00000000)
Offset: 0x18

Register Name: PL_DRV1

Bit

R/W

Default/Hex

Description

31:0

/

/

/

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System
3.22.2.8. PL PULL Register 0 (Default Value: 0x00000005)
Offset: 0x1C

Register Name: PL_PULL0

Bit

R/W

Default/Hex

Description

31:26

/

/

/

0x5

PL_PULL
PL[n] Pull-up/down Select (n = 0~12)00: Pull-up/down disable
01: Pull-up
10: Pull-down
11: Reserved[2i+1:2i](i=0~12)R/W

3.22.2.9. PL PULL Register 1 (Default Value: 0x00000000)
Offset: 0x20

Register Name: PL_PULL1

Bit

R/W

Default/Hex

Description

31:0

/

/

/

3.22.2.10.

PL External Interrupt Configure Register 0 (Default Value: 0x00000000)

Offset: 0x200
Bit

Register Name: PL_EINT_CFG0

R/W

Default/Hex

Description

0

EINT_CFG
External INTn Mode (n = 0~7)
0x0: Positive Edge
0x1: Negative Edge
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/ Negative)
Others: Reserved[4i+3:4i](i=0~7)R/W

3.22.2.11.

PL External Interrupt Configure Register 1 (Default Value: 0x00000000)

Offset: 0x204

Register Name: PL_EINT_CFG1

Bit

R/W

Default/Hex

Description

31:20

/

/

/

0

EINT_CFG
External INTn Mode (n = 8~12)
0x0: Positive Edge
0x1: Negative Edge
0x2: High Level[4i+3:4i](i=0~4)R/W

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System
0x3: Low Level
0x4: Double Edge (Positive/ Negative)
Others: Reserved

3.22.2.12.

PL External Interrupt Configure Register 2 (Default Value: 0x00000000)

Offset: 0x208

Register Name: PL_EINT_CFG2

Bit

R/W

Default/Hex

Description

31:0

/

/

/

3.22.2.13.

PL External Interrupt Configure Register 3 (Default Value: 0x00000000)

Offset: 0x20C

Register Name: PL_EINT_CFG3

Bit

R/W

Default/Hex

Description

31:0

/

/

/

3.22.2.14.

PL External Interrupt Control Register (Default Value: 0x00000000)

Offset: 0x210

Register Name: PL_EINT_CTL

Bit

R/W

Default/Hex

Description

31:13

/

/

/

0

EINT_CTL
External INTn Enable (n = 0~12)
0: Disable
1: Enable[n](n=0~12)R/W

3.22.2.15.

PL External Interrupt Status Register (Default Value: 0x00000000)

Offset: 0x214

Register Name: PL_EINT_STATUS

Bit

R/W

Default/Hex

Description

31:13

/

/

/

0

EINT_STATUS
External INTn Pending Bit (n = 0~12)
0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear[n](n=0~12)R/W

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System
3.22.2.16.

PL External Interrupt Debounce Register (Default Value: 0x00000000)

Offset: 0x218

Register Name: PL_EINT_DEB

Bit

R/W

Default/Hex

Description

31:7

/

/

/

6:4

R/W

0

DEB_CLK_PRE_SCALE
Debounce Clock Pre-scale n
The selected clock source is prescaled by 2^n.

3:1

/

/

/

0

PIO_INT_CLK_SELECTPIO Interrupt Clock Select0: LOSC 32KHz
1: HOSC 24MHz

0R/W

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Memory

Chapter 4 Memory
This section describes the A64 memory from three aspects:




SDRAM
NAND Flash
SD-MMC Host Controller

4.1. SDRAM
4.1.1. Overview
The SDRAM Controller (DRAMC) provides a simple, flexible, burst-optimized interface to all industy-standard
SDRAM. It supports up to a 24G bits memory address space.
The DRAMC automatically handles memory management, initialization, and refresh operations. It gives thehost CPU a simple command interface, hiding details of the required address, page, and burst handlingprocedures. All memory parameters are runtime-configurable, including timing, memory setting, SDRAM type,
and Extended-Mode-Register settings. To simplify chip system integration, DDR controller works in half rate
mode.
The DRAMC includes the following features:
32-bits data widthSupport 2 Chip SelectSupport DDR2/DDR3/DDR3L/LPDDR2/LPDDR3 SDRAM
Support Different Memory Device’s Power Voltage of 1.2V 1.35V 1.5V and 1.8V
Support clock frequency up to 667 MHz(DDR3-1333)
Support Memory Capacity up to 24G bits (3G Bytes)
Support 16 address lines and three bank address lines per channel
Automatically generates initialization and refresh sequences

Runtime-configurable parameters setting for application flexibility

Clock frequency can be chosen for different application(MDFS supported)
Priority of transferring through multiple ports is programmable
Random read or write operation is supported

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Memory

4.2. NAND Flash Controller(NDFC)
4.2.1. Overview
The NDFC is the NAND Flash Controller which supports all NAND flash memory available in the market. New
type flash can be supported by software re-configuration.
The On-the-fly error correction code (ECC) is built-in NDFC for enhancing reliability. BCH is implemented and it
can detect and correct up to 64 bits error per 512 or 1024 bytes data. The on chip ECC and parity checking
circuitry of NDFC frees CPU for other tasks. The ECC function can be disabled by software.
The data can be transferred by DMA or by CPU memory-mapped IO method. The NDFC provides automatic
timing control for reading or writing external Flash. The NDFC maintains the proper relativity for CLE, CE# and
ALE control signal lines. Three modes are supported for serial read access. The conventional serial access ismode 0 and mode 1 is for EDO type and mode 2 for extension EDO type. NDFC can monitor the status of R/B#
signal line.
Block management and wear leveling management are implemented in software.
The NDFC includes the following features:Supports all SLC/MLC/TLC flash and EF-NAND memory available in the market
Software configure seed for randomize engineSoftware configure method for adaptability to a variety of system and memory types
Supports 8-bit Data Bus Width
Supports 1024, 2048, 4096, 8192, 16384 bytes size per pageSupports Conventional and EDO serial access method for serial reading FlashOn-the-fly BCH error correction code which correcting up to 64 bits per 512 or 1024 bytes

Corrected Error bits number information report
ECC automatic disable function for all 0xff data
NDFC status information is reported by its’ registers and interrupt is supported
One Command FIFO
Embedded DMA to do data transfer
External DMA is also supported for transferring dataTwo 256x32-bit RAM for Pipeline Procession
Support SDR, ONFI DDR and Toggle DDR NAND
Support self–debug for NDFC debug

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Memory

4.2.2. Block Diagram
The NDFC system block diagram is shown below:

AHB
Slave I/F

Command
FIFO

DMA & INT
Control

FIFO
Control

FIFO
RAM0(256x32)ahb_clk
domainRegister
File

FIFO
RAM1
(256x32)

User Data(8x32)

Sync

nfc_clk
domainNormalCommandFSM

SpareCommandFSM

Batch
Command
FSM
ECC
Control

NAND Flash Basic Operation

CE[7:0] CLE ALE WE RE

RB[1:0]DO[7:0]DI[7:0]Figure 4-1. NDFC Block Diagram

4.2.3. NDFC Timing Diagram
Typically, there are two kinds of serial access method. One method is conventional method which fetching dataat the rise edge of NDFC_RE# signal line. Another one is EDO type which fetching data at the next fall edge of
NDFC_RE# signal line.

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Memory

NDFC_CLEt3

t4

NDFC_CE#
NDFC_WE#

t14
t12

sample n-1

sample 0

NDFC_RE#t13

NDFC_ALEt10
NDFC_RB#
D(0)NDFC_IOx

D(n-1)

Figure 4-2. Conventional Serial Access Cycle Diagram (SAM0)

NDFC_CLEt3

t4

NDFC_CE#
NDFC_WE#t14

NDFC_RE#NDFC_ALE

sample 0

t12
t13
t10

NDFC_RB#
NDFC_IOx

D(0)D(n-1)

Figure 4-3. EDO type Serial Access after Read Cycle (SAM1)

A64 User Manual(Revision 1.0)

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Memory

NDFC_CLEt3
NDFC_CE#t14

NDFC_WE#

sample 0t12
NDFC_RE#t13
NDFC_ALEt10
NDFC_RB#
NDFC_IOx

D(0)D(n-1)

Figure 4-4. Extending EDO type Serial Access Mode (SAM2)

t1

t2

t3

t4

NDFC_CLE
NDFC_CE#t5

NDFC_WE#
NDFC_RE#

t11

t7

NDFC_ALEt8
NDFC_IOx

t9

COMMAND
Figure 4-5. Command Latch Cycle

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Memory

NDFC_CLE
NDFC_CE#

t1
t3

t4

t15
t6

NDFC_WE#t5

NDFC_RE#

t11

t7
NDFC_ALEt8
NDFC_IOxt9
Addr(0)Addr(n-1)

Figure 4-6. Address Latch Cycle

NDFC_CLEt1

NDFC_CE#

t3

t4

t15
t6

NDFC_WE#t5

NDFC_RE#

t11

t7
NDFC_ALEt8
NDFC_IOxt9
D(0)D(n-1)

Figure 4-7. Write Data to Flash Cycle

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Memory

NDFC_CLE
NDFC_CE#
NDFC_WE#
t12

t14

t13

NDFC_RENDFC_ALEt16
NDFC_RB#
NDFC_IOx

D(0)

CMD

D(n-1)

Figure 4-8. Waiting R/B# ready Diagram

NDFC_CLE
NDFC_CE#
NDFC_WE#t17
NDFC_RENDFC_ALE
NDFC_RB#
NDFC_IOx

CMD

D(0)

D(n-1)

Figure 4-9. WE# high to RE# low Timing Diagram

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NDFC_CLE
NDFC_CE#
NDFC_WE#t18
NDFC_RENDFC_ALE
NDFC_RB#
NDFC_IOx

05h Col1 Col2

D(n-2) D(n-1)

Figure 4-10. RE# high to WE# low Timing Diagram

NDFC_CLE
NDFC_CE#t19

NDFC_WE#
NDFC_RENDFC_ALE
NDFC_RB#
NDFC_IOx

Addr2 Addr3

D(0) D(1) D(2)Figure 4-11. Address to Data Loading Timing Diagram

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Timing cycle list:
ID

Parameter

Timing

Notes

t1

NDFC_CLE setup time

2T

t2

NDFC_CLE hold time

2T

t3

NDFC_CE setup time

2T

t4

NDFC_CE hold time

2T

t5

NDFC_WE# pulse width

T

t6

NDFC_WE# hold timeT

t7

NDFC_ALE setup time2T

t8

Data setup timeT

t9

Data hold timeT

t10

Ready to NDFC_RE# low

3T

t11

NDFC_ALE hold time

2T

t12

NDFC_RE# pulse width

T

t13

NDFC_RE# hold timeT

t14

Read cycle time

2T

t15

Write cycle time

2T

t16

NDFC_WE# high to R/B# busy

T_WB

Specifiedbytiming(NDFC_TIMING_CFG)

configureregistert17

NDFC_WE# high to NDFC_RE# low

T_WHR

Specifiedbytiming(NDFC_TIMING_CFG)

configureregistert18

NDFC_RE# high to NDFC_WE# low

T_RHW

Specifiedbytiming(NDFC_TIMING_CFG)

configureregistert19

Address to Data Loading time

T_ADL

Specifiedbytiming(NDFC_TIMING_CFG)

configureregister

Notes: T is the clock period duration of NDFC_CLK (x1).

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4.2.4. NDFC Operation Guide
NDFC_CLE

NDFC_CE#

NDFC_WE#

NDFC_RE

Page Command
cmdio[31:30]=2

NDFC_ALE

NDFC_RB#

NDFC_IOx

00h

First Command
cmdio[22]cmdio[7:0]

Addr(5 cycle)

Address Cycle
cmdio[18:16]
cmdio[19]=1

30h

Data output

Second Command
cmdio[24]Wait RB Signal
cmdio[23]Sequence Read
cmdio[20]=0
cmdio[25]=1

Figure 4-12. Page Read Command Diagram

NDFC_CLE

NDFC_CE#

NDFC_WE#

NDFC_RE

Page Command
cmdio[31:30]=2

NDFC_ALE

NDFC_RB#

NDFC_IOx

80h

First Command
cmdio[22]cmdio[7:0]

Addr(5 cycle)

Address Cycle
cmdio[18:16]
cmdio[19]=1

Data Input

Sequence Write
cmdio[20]=1
cmdio[25]=1

Wait RB Signal
cmdio[23]Figure 4-13. Page Program Diagram

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NDFC_CLE

NDFC_CE#

NDFC_WE#

NDFC_RE

Page Command
cmdio[31:30]=2

NDFC_ALE

NDFC_RB#

NDFC_IOx

00h

First Command
cmdio[22]cmdio[7:0]

col0 col1 row0row1row2 30h

Address Cycle
cmdio[18:16]
cmdio[19]=1

70h

Second Command
cmdio[24]Wait RB Signal
cmdio[23]

d(0)

00h

Third Comand
cmdio[28]Data output

Forth Comand
cmdio[29]Sequence Read
cmdio[20]=0
cmdio[25]=1

Figure 4-14. EF-NAND Page Read Diagram

NDFC_CLE

NDFC_CE#

NDFC_WE#

NDFC_RE

Page Command
cmdio[31:30]=2

NDFC_ALE

NDFC_RB#

NDFC_IOx

Address set by hardware
automatically
00hFirst Command
cmdio[22]cmdio[7:0]

col0 col1 row0row1row2 30h

Address Cycle
cmdio[18:16]
cmdio[19]=1

Second Command
cmdio[24]Data output

Wait RB Signal
cmdio[23]05hcol0 col1

E0h

Data output

Interleave Read
cmdio[20]=0
cmdio[25]=0

Figure 4-15. Interleave Page Read Diagram

4.2.5. NDFC Register List
Module Name

Base Address

NDFC

0x01C03000

Register Name

OffsetDescription

NDFC_CTL

0x00

NDFC Configure and Control Register

NDFC_ST

0x04

NDFC Status Information Register

NDFC_INT

0x08

NDFC Interrupt Control Register

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NDFC_TIMING_CTL

0x0C

NDFC Timing Control Register

NDFC_TIMING_CFG

0x10

NDFC Timing Configure Register

NDFC_ADDR_LOW

0x14

NDFC Low Word Address Register

NDFC_ADDR_HIGH

0x18

NDFC High Word Address Register

NDFC_BLOCK_NUM

0x1C

NDFC Data Block Number Register

NDFC_CNT

0x20

NDFC Data Counter for data transfer Register

NDFC_CMD

0x24

Set up NDFC commands Register

NDFC_RCMD_SET

0x28

Read Command Set Register for vendor’s NAND memory

NDFC_WCMD_SET

0x2C

Write Command Set Register for vendor’s NAND memory

NDFC_ECC_CTL

0x34

ECC Configure and Control Register

NDFC_ECC_ST

0x38

ECC Status and Operation information Register

NDFC_EFR

0x3C

Enhanced Feature Register

NDFC_ERR_CNT0

0x40

Corrected Error Bit Counter Register 0

NDFC_ERR_CNT1

0x44

Corrected Error Bit Counter Register 1

NDFC_USER_DATAn

0x50+4*n

User Data Field Register n (n from 0 to 15)

NDFC_EFNAND_STA

0x90

EFNAND Status Register

NDFC_SPARE_AREA

0xA0

Spare Area Configure Register

NDFC_PAT_ID

0xA4

Pattern ID Register

NDFC_RDATA_STA_CTL

0xA8

Read Data Status Control Register

NDFC_RDATA_STA_0

0xAC

Read Data Status Register 0

NDFC_RDATA_STA_1

0xB0

Read Data Status Register 1

NDFC_MDMA_ADDR

0xC0MBUS DMA Address Register

NDFC_MDMA_CNT

0xC4

MBUS DMA Data Counter Register

NDFC_NDMA_MODE_CTL

0xD0

NDFC Normal DMA Mode Control Register

NDFC_IO_DATA

0x300

Data Input/ Output Port Address Register

RAM0_BASE

0x400

1024 Bytes RAM0 base

RAM1_BASE

0x8001024 Bytes RAM1 base

4.2.6. NDFC Register Description
4.2.6.1. NDFC Control Register(Default Value: 0x00000000)
Offset: 0x00

Register Name: NDFC_CTL

Bit

R/W

Default/Hex

Description

31:28

/

/

/

27:24

R/W

0

NDFC_CE_SEL
Chip Select for 8 NAND Flash Chips
0 -7: NDFC Chip Select Signal 0-7 is selected8-15: NDFC CS[7:0] not selected. GPIO pins can be used for CS.

23:22

/

/

/

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21

20

19:18

17

16

15

R/W

R/W

R/W

R/W

R/W

R/W

0

NDFC_DDR_RM
DDR Repeat data mode
0: Lower byte
1: Higher byte

0

NDFC_DDR_REN
DDR Repeat Enable
0: Disable
1: Enable

0

NF_TYPE
NAND Flash Type0x0: Normal SDR NAND
0x1: Reserved
0x2: ONFI DDR NAND
0x3: Toggle DDR NAND

0

NDFC_CLE_POL
NDFC Command Latch Enable (CLE) Signal Polarity Select0: High active
1: Low active0

NDFC_ALE_POL
NDFC Address Latch Enable (ALE) Signal Polarity Select0: High active
1: Low active0

NDFC_DMA_TYPE
0: Dedicated DMA
1: Normal DMA

14

R/W

0

NDFC_RAM_METHOD
Access internal RAM method
0: Access internal RAM by AHB bus
1: Access internal RAM by DMA bus

13:12

/

/

/

11:8

R/W

0

NDFC_PAGE_SIZE
0x0: 1024 bytes
0x1: 2048 bytes
0x2: 4096 bytes
0x3: 8192 bytes
0x4: 16384 bytes
Notes: The page size is for main field data.

7

/

/

/

0

NDFC_CE_ACTChip Select Signal CE# Control During NAND operation
0: De-active Chip Select Signal NDFC_CE# during data loading, serial
access and other no operation stage for power consumption. NDFC
automatic control Chip Select Signals.
1: Chip select signal NDFC_CE# is always active after NDFC is enabled

6R/W

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5

4:3

2

1

0

/

R/W

R/W

R/W

R/W

/

/

0

NDFC_RB_SEL
NDFC external R/B Signal selectThe value 0-3 selects the external R/B signal. The same R/B signal can beused for multiple chip select flash.

0

NDFC_BUS_WIDTH
0: 8-bit bus
1: 16-bit bus

0

NDFC_RESETNDFC Reset
Write 1 to reset NDFC and clear to 0 after reset

0

NDFC_ENNDFC Enable Control
0: Disable NDFC
1: Enable NDFC

4.2.6.2. NDFC Status Register(Default Value: 0x00000000)
Offset: 0x04

Register Name: NDFC_ST

Bit

R/W

Default/Hex

Description

31:14

/

/

/

0

NDFC_RDATA_STA_0
0: The number of bit 1 during current read operation is greater
threshold value.
1: The number of bit 1 during current read operation is less than orequal to threshold value.
This field only is valid when NDFC_RDATA_STA_EN is 1.
The threshold value is configured in NDFC_RDATA_STA_TH.

0

NDFC_RDATA_STA_1
0: The number of bit 0 during current read operation is greater
threshold value.
1: The number of bit 0 during current read operation is less than orequal to than threshold value.
This field only is valid when NDFC_RDATA_STA_EN is 1.
The threshold value is configured in NDFC_RDATA_STA_TH.

0

NDFC_RB_STATE3
NAND Flash R/B 3 Line State
0: NAND Flash in BUSY State
1: NAND Flash in READY State0

NDFC_RB_STATE2NAND Flash R/B 2 Line State
0: NAND Flash in BUSY State
1: NAND Flash in READY State

13

12

11

10

R

R

R

R

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R

0

NDFC_RB_STATE1NAND Flash R/B 1 Line State
0: NAND Flash in BUSY State
1: NAND Flash in READY State

8

R

0

NDFC_RB_STATE0NAND Flash R/B 0 Line State
0: NAND Flash in BUSY State
1: NAND Flash in READY State

7:5

/

/

/

0

NDFC_STA
0: NDFC FSM in IDLE state
1: NDFC FSM in BUSY state
When NDFC_STA is 0, NDFC can accept new command and process
command.

0

NDFC_CMD_FIFO_STATUS
0: Command FIFO not full and can receive new command
1: Full and waiting NDFC to process commands in FIFO
Since there is only one 32-bit FIFO for command. When NDFC latches
one command, command FIFO is free and can accept another new
command.

0

NDFC_DMA_INT_FLAG
When it is 1, it means that a pending DMA is completed. It will be clear
after writing 1 to this bit or it will be automatically clear before FSM
processing an new command.

0

NDFC_CMD_INT_FLAG
When it is 1, it means that NDFC has finished one Normal Command
Mode or one Batch Command Work Mode. It will be clear after writing 1
to this bit or it will be automatically clear before FSM processing a newcommand.

0

NDFC_RB_B2R
When it is 1, it means that NDFC_R/B# signal is transferred from BUSY
state to READY state. It will be clear after writing 1 to this bit.

4

3

2

1

0

R

R

R/W

R/W

R/W

4.2.6.3. NDFC Interrupt and DMA Enable Register(Default Value: 0x00000000)
Offset: 0x08

Register Name: NDFC_INT

Bit

R/W

Default/Hex

Description

31:3

/

/

/

0

NDFC_DMA_INT_ENABLE
Enable or disable interrupt when a pending DMA is completed.

0

NDFC_CMD_INT_ENABLE
Enable or disable interrupt when NDFC has finished the procession of asingle command in Normal Command Work Mode or one Batch

2

1

R/W

R/W

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Command Work Mode.
0: Disable
1: Enable

0

R/W

0

NDFC_B2R_INT_ENABLE
Enable or disable interrupt when NDFC_RB# signal is transferring from
BUSY state to READY state
0: Disable
1: Enable

4.2.6.4. NDFC Timing Control Register(Default Value: 0x00000000)
Offset: 0x0C

Register Name: NDFC_TIMING_CTL

Bit

R/W

Default/Hex

Description

31:12

/

/

/

11:8

R/W

0

NDFC_READ_PIPE
In SDR mode:
0: Normal
1: EDO
2: E-EDO
Other : Reserved
In DDR mode:
1~15 is valid.(These bits configure the number of clock when data isvalid after RE#’s falling edge)

7:6

/

/

/

0

NDFC_DC_CTL
NDFC Delay Chain Control. (These bits are only valid in DDR datainterface, and configure the relative phase between DQS and DQ[0…7] )

5:0

R/W

4.2.6.5. NDFC Timing Configure Register(Default Value: 0x00000095)
Offset: 0x10

Register Name: NDFC_TIMING_CFG

Bit

R/W

Default/Hex

Description

31:20

/

/

/

0

T_WC
Write Cycle Time
0: 1*2T
1: 2*2T
2: 3*2T
3: 4*2T

0

T_CCS
Change Column Setup Time

19:18
17:16

R/W
R/W

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0: 16*2T
1: 24*2T
2: 32*2T
3: 64*2T

15:14

13:12

11

10:8

7:6

5:4

3:2

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0

T_CLHZ
CLE High to Output Hi-z
0: 2*2T
1: 8*2T
2: 16*2T
3: 31*2T0

T_CS
CE Setup Time
0: 2*2T
1: 8*2T
2: 16*2T
3: 31*2T0

T_CDQSSDQS Setup Time for data input start
0: 8*2T
1: 24*2T0

T_CAD
Command, Address, Data Delay
000: 4*2T
001: 8*2T010: 12*2T
011: 16*2T
100: 24*2T
101: 32*2T
110/111: 64*2T

0x2

T_RHW
RE# high to WE# low cycle number
00: 4*2T
01: 8*2T
10: 12*2T
11: 20*2T

0x1

T_WHR
WE# high to RE# low cycle number
00: 8*2T
01: 16*2T
10: 24*2T
11: 32*2T

0x1

T_ADL
Address to Data Loading cycle number
00: 0*2T

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01: 8*2T
10: 16*2T
11: 24*2T

1:0

R/W

0x1

T_WB
WE# high to busy cycle number
00:14*2T
01:22*2T
10: 30*2T
11:38*2T

4.2.6.6. NDFC Address Low Word Register(Default Value: 0x00000000)
Offset: 0x14
Bit
31:24

Register Name: NDFC_ADDR_LOW
R/W
R/W

Default/Hex

Description

0

ADDR_DATA4NAND Flash 4th Cycle Address Data

23:16

R/W

0

ADDR_DATA3NAND Flash 3rd Cycle Address Data

15:8

R/W

0

ADDR_DATA2NAND Flash 2nd Cycle Address Data0

ADDR_DATA1NAND Flash 1st Cycle Address Data

7:0

R/W

4.2.6.7. NDFC Address High Word Register(Default Value: 0x00000000)
Offset: 0x18
Bit

Register Name: NDFC_ADDR_HIGH
R/W

Default/Hex

Description

31:24

R/W

0

ADDR_DATA8NAND Flash 8th Cycle Address Data

23:16

R/W

0

ADDR_DATA7NAND Flash 7th Cycle Address Data

15:8

R/W

0

ADDR_DATA6NAND Flash 6th Cycle Address Data0

ADDR_DATA5NAND Flash 5th Cycle Address Data

7:0

R/W

4.2.6.8. NDFC Data Block Number Register(Default Value: 0x00000000)
Offset: 0x1C
Bit

R/W

Register Name: NDFC_DATA_BLOCK_NUM
Default/Hex

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31:6

/

/

/

NDFC_DATA_BLOCK_NUM

4:0

R/W

0

DATA BLOCK Number
It is used for batch command procession.
0: no data
1: 1 data blocks
2: 2 data blocks…
16: 16 data blocks
Others: Reserved
Notes: 1 data block = 512 or 1024 bytes main field data

4.2.6.9. NDFC Data Counter Register(Default Value: 0x00000000)
Offset: 0x20

Register Name: NDFC_CNT

Bit

R/W

Default/Hex

Description

31:10

/

/

/

0

NDFC_DATA_CNT
Transfer Data Byte Counter
The length can be set from 1 byte to 1024 bytes. However, 1024 bytes is
set when it is zero.

9:0

R/W

4.2.6.10. NDFC Command IO Register(Default Value: 0x00000000)
Offset: 0x24
Bit

31:30

29

28
27

Register Name: NDFC_CMD
R/W

R/W

R/W

R/W
R/W

Default/Hex

Description0

NDFC_CMD_TYPE
00: Common Command for normal operation
01: Special Command for Flash Spare Field Operation
10: Page Command for batch process operation
11: Reserved0

NDFC_SEND_FOURTH_CMD
0: Don’t send third set command
1: Send it on the external memory’s bus
Notes：It is used for EF-NAND page read.

0

NDFC_SEND_THIRD_CMD
0: Don’t send third set command
1: Send it on the external memory’s bus
Notes：It is used for EF-NAND page read.

0

NDFC_ROW_ADDR_AUTO
Row Address Auto Increase for Page Command

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0: Normal operation
1: Row address increasing automatically

26

25

24

23

22

21

20

19

18:16

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0

NDFC_DATA_METHOD
Data swap method when the internal RAM and system memory
It is only active for Common Command and Special Command.
0: No action
1: DMA transfer automatically
It only is active when NDFC_RAM_METHOD is 1.
If this bit is set to 1, NDFC should setup DRQ to fetching data before
output to Flash or NDFC should setup DRQ to sending out to systemmemory after fetching data from Flash.
If this bit is set to 0, NDFC output the data in internal RAM or do nothing
after fetching data from Flash.

0

NDFC_SEQ
User data & BCH check word position. It only is active for Page
Command, don’t care about this bit for other two commands
0: Interleave Method (on page spare area)
1: Sequence Method (following data block)0

NDFC_SEND_SECOND_CMD
0: Don’t send second set command
1: Send it on the external memory’s bus

0

NDFC_WAIT_FLAG
0: NDFC can transfer data regardless of the internal NDFC_RB wire
1: NDFC can transfer data when the internal NDFC_RB wire is READY;
otherwise it can’t when the internal NDFC_RB wire is BUSY.

0

NDFC_SEND_FIRST_CMD
0: Don’t send first set command
1: Send it on the external memory’s bus

0

NDFC_DATA_TRANS
0: No data transfer on external memory bus
1: Data transfer and direction is decided by the field NDFC_ACCESS_DIR

0

NDFC_ACCESS_DIR
0: Read NAND Flash
1: Write NAND Flash0

NDFC_SEND_ADR
0: Don’t send ADDRESS
1: Send N cycles ADDRESS, the number N is specified by
NDFC_ADR_NUM field

0

NDFC_ADR_NUM
Address Cycles’ Number
000: 1 cycle address field
001: 2 cycles address field
010: 3 cycles address field
011: 4 cycles address field

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100: 5 cycles address field
101: 6 cycles address field
110: 7 cycles address field
111: 8 cycles address field

15:8

7:0

R/W

R/W

0

NDFC_CMD_HIGH_BYTE
NDFC Command high byte data
If 8-bit command is supported, the high byte should be zero for 16-bit
bus width NAND Flash. For 8-bit bus width NAND Flash, high byte
command is discarded.

0

NDFC_CMD_LOW_BYTE
NDFC Command low byte data
This command will be sent to external Flash by NDFC.

4.2.6.11. NDFC Command Set Register 0(Default Value: 0x00E00530)
Offset: 0x28

Register Name: NDFC_CMD_SET0

Bit

R/W

Default/Hex

Description

31:24

/

/

/

23:16

R/W

0xE0

NDFC_RANDOM_READ_CMD1
Used for Batch Read Operation

15:8

R/W

0x05

NDFC_RANDOM_READ_CMD0
Used for Batch Read Operation

0x30

NDFC_READ_CMD
Used for Batch Read Operation

7:0

R/W

4.2.6.12. NDFC Command Set Register 1(Default Value: 0x70008510)
Offset: 0x2C
Bit

R/W

Register Name: NDFC_CMD_SET1
Default/Hex

Description

31:16

R/W

0x70

NDFC_READ_CMD0
Used for EF-NAND Page Read operation

23:16

R/W

0x00

NDFC_READ_CMD1
Used for EF-NAND Page Read operation

0x85

NDFC_RANDOM_WRITE_CMD
Used for Batch Write Operation

0x10

NDFC_PROGRAM_CMD
Used for Batch Write Operation

15:8
7:0

R/W
R/W

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4.2.6.13. NDFC IO Data Register(Default Value: 0x00000000)
Offset: 0x30
Bit

31:0

Register Name: NDFC_IO_DATA
R/W

R/W

Default/Hex

Description0

NDFC_IO_DATA
Read/Write data into internal RAM
Access unit is 32-bit.

4.2.6.14. NDFC ECC Control Register(Default Value: 0x4a800008)
Offset: 0x34

Register Name: NDFC_ECC_CTL

Bit

R/W

Default/Hex

Description

31

/

/

/

0x4a80

NDFC_RANDOM_SEEDThe seed value for randomize engine. It is only active when
NDFC_RANDOM_EN is set to ‘1’.

0

NDFC_ECC_MODE
0x0: BCH-16 for one ECC Data Block0x1: BCH-24 for one ECC Data Block0x2 : BCH-28 for one ECC Data Block
0x3 : BCH-32 for one ECC Data Block
0x4 : BCH-40 for one ECC Data Block
0x5 : BCH-48 for one ECC Data Block
0x6 : BCH-56 for one ECC Data Block
0x7 : BCH-60 for one ECC Data Block
0x8 : BCH-64 for one ECC Data Block
Others: Reserved0

NDFC_RANDOM_SIZE
0: ECC block size
1: Page size0

NDFC_RANDOM_DIRECTION
0: LSB first
1: MSB first

30:16

15:12

11

10

R/W

R/W

R/W

R/W

9

R/W

0

NDFC_RANDOM_EN
0: Disable Data Randomize
1: Enable Data Randomize

8:6

/

/

/

0

NDFC_ECC_BLOCK_SIZE
0: 1024 bytes of one ECC data block
1: 512 bytes of one ECC data block0

NDFC_ECC_EXCEPTION
0: Normal ECC

5
4

R/W
R/W

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1: For ECC, there is an exception. If all data is 0xff or 0x00 for the block.
When reading this page, ECC assumes that it is right. For this case, noerror information is reported.
Notes: It only is active when ECC is ON

3

R/W

0x1

NDFC_ECC_PIPELINE
Pipeline function enable or disable for batch command
0: Error Correction function no pipeline with next block operation
1: Error Correction pipeline

2:1

/

/

/

0

NDFC_ECC_EN
0: ECC is OFF
1: ECC is ON

0

R/W

4.2.6.15. NDFC ECC Status Register(Default Value: 0x00000000)
Offset: 0x38
Bit

31:16

15:0

Register Name: NDFC_ECC_ST
R/W

R

R

Default/Hex

Description0

NDFC_PAT_FOUND
Special pattern (all 0x00 or all x0ff) Found Flag for 16 Data Blocks
0: No Found
1: Special pattern is found
When this field is ‘1’, this means that the special data is found forreading external NAND flash. The register of NDFC_PAT_ID would
indicates which pattern is found.

0

NDFC_ECC_ERR
Error information bit of 16 Data Blocks
0: ECC can correct these error bits or there is no error bit
1: Error bits number beyond of ECC correction capability and can’t
correct themNotes: The LSB of this register is corresponding the 1st ECC data block. 1
ECC Data Block = 512 or 1024 bytes.

4.2.6.16. NDFC Enhanced Feature Register(Default Value: 0x00000000)
Offset: 0x3C

Register Name: NDFC_EFR

Bit

R/W

Default/Hex

Description

31:9

R/W

0

/

0

NDFC_WP_CTRL
NAND Flash Write Protect Control Bit
0: Write Protect is active
1: Write Protect is not active

8

R/W

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Notes: When this bit is ‘0’, WP signal line is low level and external NAND
flash is on protected state.
7

6:0

/

R/W

/

/

0

NDFC_ECC_DEBUG
For the purpose of debugging ECC engine, special bits error are inserted
before writing external Flash Memory.
0: No error is inserted (ECC Normal Operation)n: N bits error are inserted

4.2.6.17. NDFC Error Counter Register 0(Default Value: 0x00000000)
Offset: 0x40
Bit

[8i+7:8i](i=0~3)

Register Name: NDFC_ERR_CNT0
R/W

R

Default/Hex

Description

0

ECC_COR_NUM
ECC Corrected Bits Number for ECC Data Block[n] (n from 0 to 3)
0: No corrected bits
1: 1 corrected bit
2: 2 corrected bits…
64: 64 corrected bits
Others: Reserved
Notes: 1 ECC Data Block = 512 or 1024 bytes

4.2.6.18. NDFC Error Counter Register 1(Default Value: 0x00000000)
Offset: 0x44
Bit

Register Name: NDFC_ERR_CNT1
R/W

Default/Hex

Description

0

ECC_COR_NUM
ECC Corrected Bits Number for ECC Data Block[n] (n from 4 to 7)
0: No corrected bits
1: 1 corrected bit
2: 2 corrected bits…
64: 64 corrected bits
Others: Reserved
Notes: 1 ECC Data Block = 512 or 1024 bytes[8i+7:8i](i=0~3)R

4.2.6.19. NDFC Error Counter Register 2(Default Value: 0x00000000)
Offset: 0x48

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Bit

R/W

Default/Hex

Description

ECC_COR_NUM[8i+7:8i](i=0~3)R

0ECC Corrected Bits Number for ECC Data Block[n] (n from 8 to 11)
0: No corrected bits
1: 1 corrected bit
2: 2 corrected bits…
64: 64 corrected bits
Others: Reserved
Notes: 1 ECC Data Block = 512 or 1024 bytes

4.2.6.20. NDFC Error Counter Register 3(Default Value: 0x00000000)
Offset: 0x4C
Bit

[8i+7:8i](i=0~3)

R/W

R

Register Name: NDFC_ERR_CNT3
Default/Hex

Description

0

ECC_COR_NUM
ECC Corrected Bits Number for ECC Data Block[n] (n from 12 to 15)
0: No corrected bits
1: 1 corrected bit
2: 2 corrected bits…
64: 64 corrected bits
Others: Reserved
Notes: 1 ECC Data Block = 512 or 1024 bytes

4.2.6.21. NDFC User Data Register [n]( Default Value: 0xffffffff)
Offset: 0x50 + 0x4*n
Bit

31:0

R/W

R/W

Register Name: NDFC_USER_DATAn(n=0~15)
Default/Hex

Description

0xffffffff

USER_DATA
User Data for ECC Data Block[n] (n from 0 to 15)
Notes: 1 ECC Data Block = 512 or 1024 bytes

4.2.6.22. NDFC EFNAND STATUS Register(Default Value: 0x00000000)
Offset: 0x90

Register Name: NDFC_EFNAND_STATUS

Bit

R/W

Default/Hex

Description

31:8

/

/

/

0

EF_NAND_STATUS
The Status Value for EF-NAND Page Read operation

7:0

R

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4.2.6.23. NDFC Spare Area Register(Default Value: 0x00000400)
Offset: 0xA0

Register Name: NDFC_SPARE_AREA

Bit

R/W

Default/Hex

Description

31:16

/

/

/

0x400

NDFC_SPARE_ADR
This value indicates the spare area first byte address for NDFC interleave
page operation.

15:0

R/W

4.2.6.24. NDFC Pattern ID Register(Default Value: 0x00000000)
Offset: 0xA4
Bit

[2i+1:2i](i=0~15)

R/W

R

Register Name: NDFC_PAT_ID
Default/Hex

Description

0

PAT_ID
Special Pattern ID for 16 ECC data block
0: All 0x00 is found
1: All 0xFF is found
Others: Reserved

4.2.6.25. NDFC Read Data Status Control Register(Default Value: 0x01000000)
Offset: 0xA8

Register Name: NDFC_RDATA_STA_CTL

Bit

R/W

Default/Hex

31:25

/

/

/

Description

24

R/W

1

NDFC_RDATA_STA_EN
0: Disable to count the number of bit 1 and bit 0 during current read
operation;
1: Enable to count the number of bit 1 and bit 0 during current read
operation;
The number of bit 1 and bit 0 during current read operation can be used
to check whether a page is blank or bad.

23:18

/

/

/

0

NDFC_RDATA_STA_TH
The threshold value to generate data status.
If the number of bit 1 during current read operation is less than or equal
to threshold value, the bit 13 of NDFC_ST register will be set.
If the number of bit 0 during current read operation is less than or equal
to threshold value, the bit 12 of NDFC_ST register will be set.

17:0

R/W

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4.2.6.26. NDFC Read Data Status Register 0(Default Value: 0x00000000)
Offset: 0xAC
Bit

31:0

R/W

R

Register Name: NDFC_RDATA_STA_0
Default/Hex

Description0

BIT_CNT_1
The number of input bit 1 during current command. It will be cleared
automatically when next command is executed.

4.2.6.27. NDFC Read Data Status Register 1(Default Value: 0x00000000)
Offset: 0xB0
Bit

31:0

R/W

R

Register Name: NDFC_RDATA_STA_1
Default/Hex

Description0

BIT_CNT_0
The number of input bit 0 during current command. It will be cleared
automatically when next command is executed.

4.2.6.28. NDFC MBUS DMA Address Register(Default Value: 0x00000000)
Offset: 0xC0
Bit
31:0

R/W
R/W

Register Name: NDFC_MDMA_ADDR
Default/Hex

Description

0

MDMA_ADDR
MBUS DMA address

4.2.6.29. NDFC MBUS DMA Byte Counter Register(Default Value: 0x00000000)
Offset: 0xC4
Bit
14:0

R/W
R/W

Register Name: NDFC_MDMA_CNT
Default/Hex

Description

0

MDMA_CNT
MBUS DMA data counter

4.2.6.30. NDFC Normal DMA Mode Control Register(Default Value: 0x000000A5)
Offset: 0xD0
Bit

7:0

R/W

R/W

Register Name: NDFC_NDMA_MODE_CTL
Default/Hex

Description

0xA5

NDMA_MODE_CTL
0xEA:NDMA handshake mode
Note:NDMA wait mode don't care this value. 0xA5 can be used inhandshake mode, but 0xEA is better.

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4.3. SD-MMC Host Controller
4.3.1. Overview
The SD-MMC Host controller(SMHC) can be configured either as a Secure Digital Multimedia Card controller,
which simultaneously supports Secure Digital memory (SD Memory), UHS-1 Card, Secure Digital I/O (SDIO),
Multimedia Cards (MMC) and eMMC.
The SMHC controller includes the following features:Supports Secure Digital memory protocol commands (up to SD3.0)
Supports Secure Digital I/O protocol commands(up to SDIO2.0)
Supports Multimedia Card protocol commands (up to MMC5.0)
Supports eMMC boot operation
Supports Command Completion signal and interrupt to host processor and Command Completion Signal
disable featureSupports one SD (Verson1.0 to 3.0) or MMC (Verson3.3 to 5.0)
Supports hardware CRC generation and error detectionSupports host pull-up control
Supports SDIO interrupts in 1-bit and 4-bit modesSupports block size of 1 to 65535 bytes

Supports descriptor-based internal DMA controllerInternal 1024 bytes FIFO for data transfer
Support 3.3 and 1.8V IO pad

4.3.2. Block Diagram

Figure 4-16. SD/MMC Controller Block Diagram

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4.3.3. SMHC Controller Timing Diagram
Please refer to relative specifications:

Physical Layer Specification Ver3.00 Final,2009.04.16
SDIO Specification Ver2.00
Multimedia Cards (MMC : version 4.2)
JEDEC Standard – JESD84-B50, Embedded Multimedia Card (eMMC) Card Product Standard

4.3.4. SMHC Operation Description
4.3.4.1. External Signal List
Port Name

Width

Direction

Description

CLK

1

OUT

Clock signal for SD/SDIO/MMC card.

CMD

1

IN/OUT

CMD line.

DATA

4/8

IN/OUT

Data lines, 4bit for SMHC0 and SMHC1, 8bit for SMHC2.

DS

1

OUT

Data strobe signal for SMHC2.

RST

1

OUT

Reset signal for SMHC2.

Figure 4-17 shows a pin diagram of the SMHC.

CLK
CMD
DATA[4:0]/[7:0]
DS

Chip

SD/MMC
Host
Controller

RST

Figure 4-17. SD/MMC Pin Diagram

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4.3.4.2. Calibrate Delay Chain
The sample clock delay chain and Data Strobe delay chain(only in SMHC2) are used to generate delay to makeproper timing between sample clock/Data Strobe and data signals. Each delay chain is made up with 64 delay
cells. The delay time of one delay cell can be estimated through delay chain calibration.
The steps to calibrate delay chain are as follows:
Step1: Enable SMHC. In order to calibrate delay chain by operation registers in SMHC, SMHC must be enabledthrough Bus Software Reset Register 0 and Bus Clock Gating Register0.
Step2: Configure a proper clock for SMHC. Calibration delay chain is based on the clock for SMHC from ClockControl Unit(CCU). Calibration delay chain a internal function in SMHC and don’t need device. So, it isunnecessary to open clock signal for device. The recommended clock frequency is 200MHz.
Step3: Set proper initial delay value. Writing 0xA0 to delay control register enables Delay Software Enable(bit[7]) and sets initial delay value 0x20 to Delay chain(bit[5:0]). Then write 0x0 to delay control register to clear
the value.
Step4: Write 0x8000 to delay control register to start calibrate delay chain.
Step5: Wait until the flag(Bit14 in delay control register) of calibration done is set. The number of delay cells isshown at Bit8~Bit13 in delay control register. The delay time generated by these delay cells is equal to the cycleof SMHC’s clock nearly. This value is the result of calibration.
Step6: Calculate the delay time of one delay cell according to the cycle of SMHC’s clock and the result of
calibration.
Note: In the above descriptions,delay control register contains SMHC Sample Delay Control Register and
SMHC Data Strobe Delay Control Register.Delay Software Enable contains Sample Delay Software Enable
and Data Strobe Delay Software Enable. Delay chain contains Sample Delay Software and Data Strobe Delay
Software.

4.3.5. SMHC DMA Controller Description
SMHC controller has an internal DMA controller (IDMAC) to transfer data between host memory and SDMMC
port. With a descriptor, IDMAC can efficiently move data from source to destination by automatically loading
next DMA transfer arguments, which need less CPU intervention. Before transfer data in IDMAC, host drivershould construct a descriptor list, configure arguments of every DMA transfer, then launch the descriptor andstart the DMA. IDMAC has an interrupt controller, when enabled, it can interrupt the HOST CPU in situations
such as data transmission completed or some errors happened.

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4.3.5.1. IDMAC Descriptor Structure
The IDMAC uses a descriptor with a chain structure, and each descriptor points to a unique buffer and the next
descriptor.
…

DES0

DES0

DES0

DES1

DES1

DES1

DES2

DES2

DES2

DES3

DES3

DES3

This figure illustrates the internal formats of a descriptor. The descriptor addresses must be aligned to the bus
width used for 32-bit buses. Each descriptor contains 16 bytes of control and status information.
DES0 is a notation used to denote the [31:0] bits, DES1 to denote [63:32] bits, DES2 to denote [95:64]bits, andDES3 to denote [127:96]bits in a descriptor.

4.3.5.2. DES0 definition
Bits

Name

Descriptor

HOLD

DES_OWN_FLAG
When set, this bit indicates that the descriptor is owned by the
IDMAC. When this bit is reset, it indicates that the descriptor isowned by the host. This bit is cleared when transfer is over.

30

ERROR

ERR_FLAG
When some error happened in transfer, this bit will be set.

29:6

/

/

5

/

Not used

Chain Flag

CHAIN_MOD
When set, this bit indicates that the second address in descriptor isthe next descriptor address. Must be set 1.

First DES Flag

FIRST_FLAG
When set, this bit indicates that this descriptor contains the firstbuffer of data. Must be set to 1 in first DES.

Last DES Flag

LAST_FLAG
When set, this bit indicates that the buffers pointed to by thisdescriptor are the last data buffer

DisableInterrupt
completion

CUR_TXRX_OVER_INT_DIS
When set, this bit will prevent the setting of the TX/RX interrupt bitof the IDMAC status register for data that ends in the buffer

31

4

3

2

1

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pointed to by this descriptor
0//4.3.5.3. DES1 definition
Bits

Name

Descriptor

31:16

/

/

Buffer size

BUFF_SIZE
These bits indicate the data buffer byte size, which must be amultiple of 4 bytes. If this filed is 0, the DMA ignores this buffer andproceeds to the next descriptor.

15:0

4.3.5.4. DES2 definition
Bits

31:0

Name

Descriptor

Buffer address pointer

BUFF_ADDR
These bits indicate the physical address of data buffer. The IDMAC
ignores DES2[1:0], corresponding to the bus width of 32.

4.3.5.5. DES3 definition
Bits

31:0

Name

Descriptor

Next descriptor address

NEXT_DESP_ADDR
These bits indicate the pointer to the physical memory where thenext descriptor is present.

4.3.6. SMHC Register List
Module Name

Base Address

SMHC0

0x01C0F000

SMHC10x01C10000

SMHC20x01C11000

Register Name

OffsetDescription

SMHC_CTRL

0x00

Control register

SMHC_CLKDIV

0x04

Clock control register

SMHC_TMOUT

0x08

Time out register

SMHC_CTYPE

0x0C

Bus width register

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SMHC_BLKSIZ

0x10

Block size register

SMHC_BYTCNT

0x14

Byte count register

SMHC_CMD

0x18

Command register

SMHC_CMDARG

0x1C

Command argument register

SMHC_RESP0

0x20

Response 0 register

SMHC_RESP1

0x24

Response 1 register

SMHC_RESP2

0x28

Response 2 register

SMHC_RESP3

0x2C

Response 3 register

SMHC_INTMASK

0x30

Interrupt mask register

SMHC_MINTSTS

0x34

Masked interrupt status register

SMHC_RINTSTS

0x38

Raw interrupt status register

SMHC_STATUS

0x3C

Status register

SMHC_FIFOTH

0x40

FIFO water level register

SMHC_FUNS

0x44

FIFO function select register

SMHC_TBC0

0x48

Transferred byte count0 between controller and card

SMHC_TBC1

0x4C

Transferred byte count1 between host memory and internal
FIFO

SMHC_CSDC

0x54

CRC status detect control register(only for SMHC2)

SMHC_A12A

0x58

Auto command 12 argument register

SMHC_NTSR

0x5C

SD new timing set register(only for SMHC0&1)

SMHC_HWRST

0x78

Hardware reset register

SMHC_DMAC

0x80

DMA control register

SMHC_DLBA

0x84

Descriptor list base address register

SMHC_IDST

0x88

DMAC status register

SMHC_IDIE

0x8C

DMAC interrupt enable register

SMHC_THLD

0x100

Card threshold control register

SMHC_EDSD

0x10C

eMMC4.5 DDR start bit detection control register

SMHC_RES_CRC

0x110

Response CRC from device(only for SMHC0&1)

SMHC_D7_CRC

0x114

CRC in data7 form device(only for SMHC0&1)

SMHC_D6_CRC

0x118

CRC in data6 form device(only for SMHC0&1)

SMHC_D5_CRC

0x11C

CRC in data5 form device(only for SMHC0&1)

SMHC_D4_CRC

0x120

CRC in data4 form device(only for SMHC0&1)

SMHC_D3_CRC

0x124

CRC in data3 form device(only for SMHC0&1)

SMHC_D2_CRC

0x128

CRC in data2 form device(only for SMHC0&1)

SMHC_D1_CRC

0x12C

CRC in data1 form device(only for SMHC0&1)

SMHC_D0_CRC

0x130

CRC in data0 form device(only for SMHC0&1)

SMHC_CRC_STA

0x134

CRC status from device in write operation(only for SMHC0&1)

SMHC_DRV_DL

0x140

Drive delay control register

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SMHC_SMAP_DL

0x144

Sample delay control register

SMHC_DS_DL

0x148

Data strobe delay control register

SMHC_FIFO

0x200

Read/ Write FIFO

4.3.7. SMHC Register Description
4.3.7.1. SMHC Global Control Register(Default Value: 0x00000100)
Offset: 0x0000
Bit

R/W

Register Name: SD_CTRL
Default/Hex

Description

31

R/W

0

FIFO_AC_MOD
FIFO Access Mode
1: AHB bus
0: DMA bus

30:13

/

/

/

0

TIME_UNIT_CMD
Time unit for command line
Time unit used to calculate command line time out value defined in
RTO_LMT.
0: 1 card clock period
1: 256 card clock period0

TIME_UNIT_DATTime unit for data line
Time unit used to calculate data line time out value defined in DTO_LMT.
0: 1 card clock period
1: 256 card clock period

12

11

R/W

R/W

10

R/W

0

DDR_MOD_SEL
DDR Mode Select
Although eMMC’s HS400 speed mode is 8-bit DDR, this filed should becleared when HS_MD_EN is set.
0: SDR mode
1: DDR mode

9

/

/

/

8

R/W

1

CD_DBC_ENB
Card Detect (Data[3] status) De-bounce Enable
0: disable de-bounce
1: enable de-bounce

7:6

/

/

/

0

DMA_ENBDMA Global Enable
0: Disable DMA to transfer data, using AHB bus
1: Enable DMA to transfer data

5

R/W

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4

R/W

0

INT_ENB
Global Interrupt Enable
0: Disable interrupts
1: Enable interrupts

3

/

/

/

2

R/W

0

DMA_RSTDMA Reset

0

FIFO_RSTFIFO Reset
0: No change
1: Reset FIFOThis bit is auto-cleared after completion of reset operation.

0

SOFT_RST
Software Reset
0: No change
1: Reset SD/MMC controller
This bit is auto-cleared after completion of reset operation.

1

0

R/W

R/W

4.3.7.2. SMHC Clock Control Register(Default Value: 0x00000000)
Offset: 0x0004
Bit

R/W

Register Name: SD_CLKDIVDefault/Hex

Description

31

R/W

0

MASK_DATA0
0 : Do not mask data0 when updata clock ;1 : Mask data0 when updata clock;Default : 0;

30:18

/

/

/

0

CCLK_CTRL
Card Clock Output Control
0 : Card clock always on
1 : Turn off card clock when FSM in IDLE state

17

R/W

16

R/W

0

CCLK_ENB
Card Clock Enable
0 : Card Clock off
1 : Card Clock on

15:8

/

/

/

0

CCLK_DIV
Card clock dividern : Source clock is divided by 2*n.(n=0~255)
when HS_MD_EN is set, this field must be cleared.

7:0

R/W

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4.3.7.3. SMHC Timeout Register (Default Value: 0xFFFFFF40)
Offset: 0x0008

Register Name: SD_TMOUT

Bit

R/W

Default/Hex

Description

31:8

R/W

0xffffff

DTO_LMT
Data Timeout Limit

7:0

R/W

0x40

RTO_LMT
Response Timeout Limit

4.3.7.4. SMHC Bus Width Register (Default Value: 0x00000000)
Offset: 0x000c

Register Name: SD_CTYPE

Bit

R/W

Default/Hex

Description

31:2

/

/

/

0

CARD_WID
Card width
2’b00 : 1-bit width
2’b01 : 4-bit width
2’b1x : 8-bit width

1:0

R/W

4.3.7.5. SMHC Block Size Register (Default Value: 0x00000200)
Offset: 0x0010

Register Name: SD_BLKSIZ

Bit

R/W

Default/Hex

Description

31:16

/

/

/

15:0

R/W

0x200

BLK_SZ
Block size

4.3.7.6. SMHC Block Count Register (Default Value: 0x00000200)
Offset: 0x0014
Bit

31:0

R/W

R/W

Register Name: SD_BYTCNTDefault/Hex

Description

0x200

BYTE_CNT
Byte counter
Number of bytes to be transferred; should be integer multiple of BlockSize(BLK_SZ) for block transfers.

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4.3.7.7. SMHC Command Register (Default Value: 0x00000000)
Offset: 0x0018
Bit

R/W

Register Name: SD_CMD
Default/Hex

Description

31

R/W

0

CMD_LOAD
Start Command.
This bit is auto cleared when current command is sent. If there is no any
response error happened, a command complete interrupt bit(CMD_OVER) will be set in SMHC_RINTSTS register. You should not write
any other command before this bit is cleared, or when a command busy
interrupt bit (CMD_BUSY) will be set in SMHC_RINTSTS register.

30:29

/

/

/

0

VOL_SW
Voltage Switch
0: normal command
1: Voltage switch command, set for CMD11 only0

BOOT_ABT
Boot Abort
Setting this bit will terminate the boot operation.

0

EXP_BOOT_ACK
Expect Boot Acknowledge.
When Software sets this bit along in mandatory boot operation,
controller expects a boot acknowledge start pattern of 0-1-0 from theselected card.

28

27

26

R/W

R/W

R/W

25:24

R/W

0

BOOT_MOD
Boot Mode
2’b00: Normal command
2’b01: Mandatory Boot operation
2’b10: Alternate Boot operation
2’b11: Reserved

23:22

/

/

/

21

R/W

0

PRG_CLK
Change Clock
0: Normal command
1: Change Card Clock; when this bit is set, controller will change clock
domain and clock output. No command will be sent.

20:16

/

/

/

15

R/W

0

SEND_INIT_SEQ
Send Initialization
0: normal command sending
1: Send initialization sequence before sending this command.

14

R/W

0

STOP_ABT_CMD
Stop Abort Command

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0: normal command sending
1:send Stop or abort command to stop current data transfer inprogress.(CMD12, CMD52 for writing “I/O Abort” in SDIO CCCR)

13

12

11

10

9

8

7

6

5:0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0

WAIT_PRE_OVER
Wait Data Transfer Over
0: Send command at once, do not care of data transferring
1: Wait for data transfer completion before sending current command0

STOP_CMD_FLAG
Send Stop CMD Automatically (CMD12)
0: Do not send stop command at end of data transfer
1: Send stop command automatically at end of data transfer

0

TRANS_MODE
Transfer Mode
0: Block data transfer command
1: Stream data transfer command0

TRANS_DIR
Transfer Direction
0: Read operation
1: Write operation0

DATA_TRANS
Data Transfer
0: without data transfer
1: with data transfer

0

CHK_RESP_CRC
Check Response CRC
0: Do not check response CRC
1: Check response CRC

0

LONG_RESP
Response Type
0:Short Response (48 bits)
1:Long Response (136 bits)

0

RESP_RCV
Response Receive
0: Command without Response
1: Command with Response0

CMD_IDX
CMD Index
Command index value

4.3.7.8. SMHC Command Argument Register (Default Value: 0x00000000)
Offset: 0x001c
Bit

R/W

Register Name: SD_CMDARG
Default/Hex

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31:0

R/W

0

CMD_ARG
Command argument

4.3.7.9. SMHC Response 0 Register (Default Value: 0x00000000)
Offset: 0x0020

Register Name: SD_RESP0

Bit

R/W

Default/Hex

Description

31:0

R

0

CMD_RESP0
response 0
Bit[31:0] of response

4.3.7.10. SMHC Response 1 Register (Default Value: 0x00000000)
Offset: 0x0024

Register Name: SD_RESP1

Bit

R/W

Default/Hex

Description

31:0

R

0

CMD_RESP1
response 1
Bit[63:31] of response

4.3.7.11. SMHC Response 2 Register (Default Value: 0x00000000)
Offset: 0x0028

Register Name: SD_RESP2

Bit

R/W

Default/Hex

Description

31:0

R

0

CMD_RESP2
response 2
Bit[95:64] of response

4.3.7.12. SMHC Response 3 Register (Default Value: 0x00000000)
Offset: 0x002C

Register Name: SD_RESP3

Bit

R/W

Default/Hex

Description

31:0

R

0

CMD_RESP3
response 3
Bit[127:96] of response

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4.3.7.13. SMHC Interrupt Mask Register (Default Value: 0x00000000)
Offset: 0x0030

Register Name: SMHC_INTMASK

Bit

R/W

Default/Hex

Description

31

R/W

0

CARD_REMOVAL_INT_EN
Card Removed Interrupt Enable

30

R/W

0

CARD_INSERT_INT_EN
Card Inserted Interrupt Enable

29:17

/

/

/

16

R/W

0

SDIO_INT_EN
SDIO Interrupt Enable

15

R/W

0

DEE_INT_EN
Data End-bit Error Interrupt Enable

14

R/W

0

ACD_INT_EN
Auto Command Done Interrupt Enable

13

R/W

0

DSE_BC_INT_EN
Data Start Error Interrupt Enable

12

R/W

0

CB_IW_INT_EN
Command Busy and Illegal Write Interrupt Enable

11

R/W

0

FU_FO_INT_EN
FIFO Underrun/Overflow Interrupt Enable

10

R/W

0

DSTO_VSD_INT_EN
Data Starvation Timeout/V1.8 Switch Done Interrupt Enable

9

R/W

0

DTO_BDS_INT_EN
Data Timeout/Boot Data Start Interrupt Enable

8

R/W

0

RTO_BACK_INT_EN
Response Timeout/Boot ACK Received Interrupt Enable

7

R/W

0

DCE_INT_EN
Data CRC Error Interrupt Enable

6

R/W

0

RCE_INT_EN
Response CRC Error Interrupt Enable

5

R/W

0

DRR_INT_EN
Data Receive Request Interrupt Enable

4

R/W

0

DTR_INT_EN
Data Transmit Request Interrupt Enable

3

R/W

0

DTC_INT_EN
Data Transfer Complete Interrupt Enable

2

R/W

0

CC_INT_EN
Command Complete Interrupt Enable

1

R/W

0

RE_INT_EN
Response Error Interrupt Enable

0

/

/

/

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4.3.7.14. SMHC Masked Interrupt Status Register (Default Value: 0x00000000)
Offset: 0x0034

Register Name: SMHC_MINTSTS

Bit

R/W

Default/Hex

Description

31

R/W

0

M_CARD_REMOVAL_INT
Card Removed

30

R/W

0

M_CARD_INSERT
Card Inserted

29:17

/

/

/

16

R/W

0

M_SDIO_INTSDIO Interrupt

0

M_DEE_INT
Data End-bit Error
When set during receiving data, it means that host controller does notreceive valid data end bit.
When set during transmitting data, it means that host controller does notreceive CRC status taken or received CRC status taken is negative.

0

M_ACD_INT
Auto Command Done
When set, it means auto stop command(CMD12) completed.

15

14

R/W

R/W

13

R/W

0

M_DSE_BC_INT
Data Start Error
When set during receiving data, it means that host controller found aerror start bit.
When set during transmitting data, it means that busy signal is cleared.

12

R/W

0

M_CB_IW_INT
Command Busy and Illegal Write

11

R/W

0

M_FU_FO_INTFIFO Underrun/Overflow

10

R/W

0

M_DSTO_VSD_INT
Data Starvation Timeout/V1.8 Switch Done

9

R/W

0

M_DTO_BDS_INT
Data Timeout/Boot Data Start

8

R/W

0

M_RTO_BACK_INT
Response Timeout/Boot ACK Received

7

R/W

0

M_DCE_INT
Data CRC Error
When set during receiving data, it means that the received data havedata CRC error.
When set during transmitting data, it means that the received CRC status
taken is negative.

6

R/W

0

M_RCE_INT
Response CRC Error

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R/W

0

M_DRR_INT
Data Receive Request
When set, it means that there are enough data in FIFO during receiving
data.

4

R/W

0

M_DTR_INT
Data Transmit Request
When set, it means that there are enough space in FIFO duringtransmitting data.

3

R/W

0

M_DTC_INT
Data Transfer Complete

2

R/W

0

M_CC_INT
Command Complete

1

R/W

0

M_RE_INT
Response Error (no response or response CRC error)
When set, Transmit Bit error or End Bit error or CMD Index error may
occurs.

0

/

/

/

4.3.7.15. SMHC Raw Interrupt Status Register (Default Value: 0x00000000)
Offset: 0x0038
Bit
31

R/W
R/W

Register Name: SMHC_RINTSTSDefault/Hex

Description

0

CARD_REMOVAL
Card Removed
This is write-1-to-clear bits.

30

R/W

0

CARD_INSERT
Card InsertedThis is write-1-to-clear bits.

29:17

/

/

/

0

SDIOI_INTSDIO Interrupt
This is write-1-to-clear bits.

0

DEE
Data End-bit Error
When set during receiving data, it means that host controller does notreceive valid data end bit.
When set during transmitting data, it means that host controller does notreceive CRC status taken.
This is write-1-to-clear bits.

0

ACD
Auto Command Done
When set, it means auto stop command(CMD12) completed.
This is write-1-to-clear bits.

16

15

14

R/W

R/W

R/W

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13

R/W

0

DSE_BC
Data Start Error
When set during receiving data, it means that host controller found aerror start bit.
When set during transmitting data, it means that busy signal is cleared.
This is write-1-to-clear bits.

12

R/W

0

CB_IW
Command Busy and Illegal Write
This is write-1-to-clear bits.

11

R/W

0

FU_FO
FIFO Underrun/Overflow
This is write-1-to-clear bits.

0

DSTO_VSD
Data Starvation Timeout/V1.8 Switch Done
This is write-1-to-clear bits.

0

DTO_BDS
Data Timeout/Boot Data Start
This is write-1-to-clear bits.

0

RTO_BACK
Response Timeout/Boot ACK Received
This is write-1-to-clear bits.

0

DCE
Data CRC Error
When set during receiving data, it means that the received data havedata CRC error.
When set during transmitting data, it means that the received CRC status
taken is negative.
This is write-1-to-clear bits.

0

RCE
Response CRC Error
This is write-1-to-clear bits.

0

DRR
Data Receive Request
When set, it means that there are enough data in FIFO during receiving
data.
This is write-1-to-clear bits.

0

DTR
Data Transmit Request
When set, it means that there are enough space in FIFO duringtransmitting data.
This is write-1-to-clear bits.

0

DTC
Data Transfer Complete
This is write-1-to-clear bits.

10

9

8

7

6

5

4

3

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

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2

R/W

0

CC
Command Complete
This is write-1-to-clear bits.

1

R/W

0

RE
Response Error (no response or response CRC error)
When set, Transmit Bit error or End Bit error or CMD Index error may
occurs.
This is write-1-to-clear bits.

0

/

/

/

4.3.7.16. SMHC Status Register (Default Value: 0x00000006)
Offset: 0x003C
Bit

R/W

Register Name: SMHC_STATUS
Default/Hex

Description

31

R

0

DMA_REQDMA Request
DMA request signal state

30:26

/

/

/

25:17

R

0

FIFO_LEVELFIFO Level
Number of filled locations in FIFO

16:11

R

0

RESP_IDX
Response Index
Index of previous response, including any auto-stop sent by controller

0

FSM_BUSY
Data FSM Busy
Data transmit or receive state-machine is busy

0

CARD_BUSY
Card data busy
Inverted version of DATA[0]0: card data not busy
1: card data busy

0

CARD_PRESENT
Data[3] statuslevel of DATA[3]; checks whether card is present
0: card not present
1: card present

0

FSM_STA
Command FSM states:
0: Idle1: Send init sequence
2: TX CMD start bit
3: TX CMD TX bit

10

9

8

7:4

R

R

R

R

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4: TX CMD index + argument
5: TX CMD CRC7
6: TX CMD end bit
7: RX response start bit
8: RX response IRQ response
9: RX response TX bit
10: RX response CMD index
11: RX response data
12: RX response CRC7
13: RX response end bit
14: CMD path wait NCC
15: Wait; CMD-to-response turnaround

3

2

1

0

R

R

R

R

0

FIFO_FULLFIFO full
1: FIFO full
0: FIFO not full1

FIFO_EMPTYFIFO Empty
1 - FIFO Empty
0 - FIFO not Empty

1

FIFO_TX_LEVELFIFO TX Water Level flag
0: FIFO didn’t reach transmit trigger level
1: FIFO reached transmit trigger level

0

FIFO_RX_LEVELFIFO RX Water Level flag
0: FIFO didn’t reach receive trigger level
1: FIFO reached receive trigger level

4.3.7.17. SMHC FIFO Water Level Register (Default Value: 0x000F0000)
Offset: 0x0040

Register Name: SMHC_FIFOTH

Bit

R/W

Default/Hex

Description

31

/

/

/

0

BSIZE_OF_TRANS
Burst size of multiple transaction
3’b000: 1 transfers
3’b001: 4
3’b010: 8
3’b011: 16 (SMHC0 don’t support)
Others: Reserved
Should be programmed same as DMA controller multiple transaction size.
The units for transfers are the DWORD. A single transfer would be

30:28

R/W

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Memory
signaled based on this value. Value should be sub-multiple of (RX_TL + 1)
and (FIFO_DEPTH - TX_TL)
Recommended:
MSize = 16, TX_TL = 240, RX_TL = 15(for SMHC1 and SMHC2)
MSize = 8, TX_TL = 248, RX_TL = 7(for SMHC0)
27:24

R

0

/

23:16

R/W

0xF

RX_TL
RX Trigger Level
0x0~0xFE: RX Trigger Level is 0~254
0xFF reserved
FIFO threshold when FIFO request host to receive data from FIFO. When
FIFO data level is greater than this value, DMA is request is raised if DMA
enabled, or RX interrupt bit is set if interrupt enabled. At the end of
packet, if the last transfer is less than this level, the value is ignored andrelative request will be raised as usual.
Recommended: 15 (means greater than 15, for SMHC1 and SMHC2)
7 (means greater than 7, for SMHC0)

15:8

R

0

/

0

TX_TL
TX Trigger Level
0x1~0xFF: TX Trigger Level is 1~255
0x0: no trigger
FIFO threshold when FIFO requests host to transmit data to FIFO. When
FIFO data level is less than or equal to this value, DMA TX request is
raised if DMA enabled, or TX request interrupt bit is set if interrupt
enabled. At the end of packet, if the last transfer is less than this level, thevalue is ignored and relative request will be raised as usual.
Recommended: 240(means less than or equal to 240, for SMHC1 andSMHC2)
248(means less than or equal to 248,for SMHC0)

7:0

R/W

4.3.7.18. SMHC Function Select Register (Default Value: 0x00000000)
Offset: 0x0044

Register Name: SMHC_CTRL

Bit

R/W

Default/Hex

Description

31:3

/

/

/

0

ABT_RDATA
Abort Read Data
0: Ignored
1: After suspend command is issued during read-transfer, software polls
card to find when suspend happened. Once suspend occurs, software
sets bit to reset data state-machine, which is waiting for next block of
data.

2

R/W

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Used in SDIO card suspends sequence.
This bit is auto-cleared once controller reset to idle state.

1

0

R/W

R/W

0

READ_WAIT
Read Wait
0: Clear SDIO read wait
1: Assert SDIO read wait

0

HOST_SEND_MMC_IRQRESQ
Host Send MMC IRQ Response
0: Ignored
1: Send auto IRQ response
When host is waiting MMC card interrupt response, setting this bit will
make controller cancel wait state and return to idle state, at which time,
controller will receive IRQ response sent by itself.
This bit is auto-cleared after response is sent.

4.3.7.19. SMHC Transferred Byte Count Register0 (Default Value: 0x00000000)
Offset: 0x0048
Bit

31:0

R/W

R

Register Name: SMHC_TBC0
Default/Hex

Description

0

TBC0
Transferred Count 0
Number of bytes transferred between card and internal FIFO.
The register should be accessed in full to avoid read-coherency problems
and read only after data transfer completes.

4.3.7.20. SMHC Transferred Byte Count Register1 (Default Value: 0x00000000)
Offset: 0x004C
Bit

31:0

R/W

R

Register Name: SMHC_TBC1
Default/Hex

Description

0

TBC1
Transferred Count 1
Number of bytes transferred between Host/DMA memory and internal
FIFO.
The register should be accessed in full to avoid read-coherency problems
and read only after data transfer completes.

4.3.7.21. SMHC CRC Status Detect Control Register (Default Value: 0x00000003)
Offset: 0x0054
Bit

R/W

Register Name: SMHC_CSDC
Default/Hex

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31:4
3:0

/
R/W

/

/

0x3

CRC_DET_PARA
0x6:HS400 speed mode
0x3:Other speed mode

Note: The register is for SMHC2 only.

4.3.7.22. SMHC Auto Command 12 Register (Default Value: 0x0000ffff)
Offset: 0x0058

Register Name: SMHC_A12A

Bit

R/W

Default/Hex

Description

31:16

/

/

/

0:15

R/W

0xffff

SD_A12A.
SD_A12A set the argument of command 12 automatically send bycontroller

4.3.7.23. SMHC NewTiming Set Register (Default Value: 0x00000000)
Offset: 0x005C
Bit

R/W

Register Name: SMHC_NTSR_REG
Default/Hex

Description

31

R/W

0

MODE_SELEC
0: Old mode of Sample/Output Timing ;1: New mode of Sample/Output Timing;
Default value : 0;

30:6

/

/

/

5:4

R/W

0x00

SAMPLE_TIMING_PHASE(RX)。
00: Sample timing phase offset 90 ;。
01: Sample timing phase offset 180 ;。
10: Sample timing phase offset 270 ;11: Ignore;
Default value: 00;

3:0

/

/

/

Note: The register is for SMHC0 and SMHC1 only.

4.3.7.24. SMHC Hardware Reset Register (Default Value: 0x00000001)
Offset: 0x0078

Register Name: SMHC_HWRST

Bit

R/W

Default/Hex

Description

31:1

/

/

/

0

R/W

1

HW_RESET.
1 : Active mode

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0 : Reset
These bits cause the cards to enter pre-idle state, which requires them tobe re-initialized.

4.3.7.25. SMHC DMAC Control Register (Default Value: 0x00000000)
Offset: 0x0080
Bit

R/W

Register Name: SMHC_BUS_MODE
Default/Hex

Description

31

W

0

DES_LOAD_CTRL
When DMAC fetches a descriptor, if the valid bit of a descriptor is not set,
DMAC FSM will go to the suspend state. Setting this bit will make DMAC
re-fetch descriptor again and do the transfer normally.

30:11

/

/

/

10:8

R

0

/

7

R/W

0

IDMAC_ENB
IDMAC Enable.
When set, the IDMAC is enabled. DE is read/write.

6:2

R/W

0

/

0

FIX_BUST_CTRL
Fixed Burst.
Controls whether the AHB Master interface performs fixed burst transfers
or not. When set, the AHB will use only SINGLE, INCR4, INCR8 during startof normal burst transfers. When reset, the AHB will use SINGLE and INCR
burst transfer operations.

0

IDMAC_RSTDMA Reset.
When set, the DMA Controller resets all its internal registers. SWR isread/write. It is automatically cleared after 1 clock cycle.

1

0

R/W

R/W

4.3.7.26. SMHC Descriptor List Base Address Register (Default Value: 0x00000000)
Offset: 0x0084
Bit

31:0

R/W

R/W

Register Name: SMHC_DLBA_REG
Default/Hex

Description

0

DES_BASE_ADDRStart of Descriptor List.
Contains the base address of the First Descriptor. The LSB bits [1:0] areignored and taken as all-zero by the IDMAC internally. Hence these LSB
bits are read-only.

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4.3.7.27. SMHC DMAC Status Register (Default Value: 0x0000_0000)
Offset: 0x0088

Register Name: SMHC_IDST

Bit

R/W

Default/Hex

Description

31:17

/

/

/

16:13

R

0

/

0

DMAC_ERR_STA
Error Bits.
Indicates the type of error that caused a Bus Error. Valid only with Fatal
Bus Error Interrupt (SMHC_IDST[2]) set. This field does not generate aninterrupt.
3’b001: Host Abort received during transmission
3’b010: Host Abort received during reception
Others: Reserved EB is read-only.

0

ABN_INT_SUM
Abnormal Interrupt Summary.
Logical OR of the following:
SMHC_IDST[2]: Fatal Bus Interrupt
SMHC_IDST[4]: DU bit Interrupt
SMHC_IDST[5]: Card Error Summary Interrupt
Only unmasked bits affect this bit.
This is a sticky bit and must be cleared each time a corresponding bit thatcauses AIS to be set is cleared. Writing a 1 clears this bit.

12:10

9

R

R/W

8

R/W

0

NOR_INT_SUM
Normal Interrupt Summary.
Logical OR of the following:
SMHC_IDST[0]: Transmit Interrupt
SMHC_IDST[1]: Receive Interrupt
Only unmasked bits affect this bit.
This is a sticky bit and must be cleared each time a corresponding bit thatcauses NIS to be set is cleared. Writing a 1 clears this bit.

7:6

/

/

/

0

ERR_FLAG_SUM
Card Error Summary.
Indicates the status of the transaction to/from the card; also present in
RINTSTS. Indicates the logical OR of the following bits:
EBE: End Bit Error
RTO: Response Timeout/Boot ACK Timeout
RCRC: Response CRC
SBE: Start Bit Error
DRTO: Data Read Timeout/BDS timeout
DCRC: Data CRC for Receive
RE: Response Error
Writing a 1 clears this bit.

5

R/W

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4

R/W

0

DES_UNAVL_INT
Descriptor Unavailable Interrupt.
This bit is set when the descriptor is unavailable due to OWN bit = 0(DES0[31] =0). Writing a 1 clears this bit.

3

/

/

/

0

FATAL_BERR_INT
Fatal Bus Error Interrupt.
Indicates that a Bus Error occurred (SMHC_IDST[12:10]). When this bit isset, the DMA disables all its bus accesses. Writing a 1 clears this bit.

0

RX_INT
Receive Interrupt.
Indicates the completion of data reception for a descriptor. Writing a 1
clears this bit.

0

TX_INT
Transmit Interrupt.
Indicates that data transmission is finished for a descriptor. Writing a ‘1’
clears this bit.

2

1

0

R/W

R/W

R/W

4.3.7.28. SMHC DMAC Interrupt Enable Register (Default Value: 0x00000000)
Offset: 0x008C

Register Name: SD_IDIE_REG

Bit

R/W

Default/Hex

Description

31:10

/

/

/

9

R/W

0

/

8

R/W

0

/

7:6

/

/

/

0

ERR_SUM_INT_ENB
Card Error summary Interrupt Enable.
When set, it enables the Card Interrupt summary.

5

R/W

4

R/W

0

DES_UNAVL_INT_ENB
Descriptor Unavailable Interrupt.
When set along with Abnormal Interrupt Summary Enable, the DU
interrupt is enabled.

3

/

/

/

0

FERR_INT_ENB
Fatal Bus Error Enable.
When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error
Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt isdisabled.

0

RX_INT_ENB
Receive Interrupt Enable.
When set with Normal Interrupt Summary Enable, Receive Interrupt is

2

1

R/W

R/W

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enabled. When reset, Receive Interrupt is disabled.

0

R/W

0

TX_INT_ENB
Transmit Interrupt Enable.
When set with Normal Interrupt Summary Enable, Transmit Interrupt isenabled. When reset, Transmit Interrupt is disabled.

4.3.7.29. SMHC Card Threshold Control Register (Default Value: 0x00000000)
Offset: 0x0100

Register Name: SMHC_THLD_REG

Bit

R/W

Default/Hex

Description

31:28

/

/

/

27:16

R/W

0

CARD_RD_THLD
Card Read Threshold Size

15:3

/

/

/

0

CARD_WR_THLD_ENB(for SMHC2 only)
Card Write Threshold Enable(HS400)
0: Card write threshold disable
1: Card write threshold enabled
Host controller initiates write transfer only if card threshold amount ofdata is available in transmit FIFO.

0

BCIG(for SMHC2 only)
Busy Clear Interrupt Generation
0: Busy Clear Interrupt disabled
1: Busy Clear Interrupt Enabled
The application can disable this feature if it does not want to wait for a
Busy Clear Interrupt.

0

CARD_RD_THLD_ENB
Card Read Threshold Enable
0 : Card Read Threshold Disable
1 : Card Read Threshold Enable
Host controller initiates Read Transfer only if CARD_RD_THLD amount of
space is available in receive FIFO.

2

1

0

R/W

R/W

R/W

4.3.7.30. SMHC eMMC4.5 DDR Start Bit Detection Control Register (Default Value: 0x00000000)
Offset: 0x010C
Bit
31

R/W
R/W

Register Name: EMMC_DDR_SBIT_DET_REG
Default/Hex

Description0

HS_MD_EN
HS400 Mode Enable
0:Disable

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1:Enable
It is required to set this bit to '1' before initiating any data transfer CMD
in HS400 mode.
30:1

0

/

R/W

/

/

0

HALF_START_BIT
Control for start bit detection mechanism inside mstorage based on
duration of start bit.
For eMMC 4.5, start bit can be:
0 : Full cycle
1 : Less than one full cycle
Set HALF_START_BIT=1 for eMMC 4.5 and above; set to 0 for SD
applications.

4.3.7.31. SMHC Response CRC Register (Default Value: 0x00000000)
Offset: 0x0110

Register Name: RESP_CRC_REG

Bit

R/W

Default/Hex

Description

31:7

/

/

/

6:0

R

0

RESP_CRC
Response CRC
Response CRC from device.

Note: The register is for SMHC0 and SMHC1 only.

4.3.7.32. SMHC Data7 CRC Register (Default Value: 0x00000000)
Offset: 0x0114
Bit

31:0

R/W

R

Register Name: DATA7_CRC_REG
Default/Hex

Description0

DAT7_CRC
Data[7] CRC
CRC in data[7] form device.
In 8bit DDR mode, the higher 16 bits indicate the CRC of even data, andthe lower 16 bits indicate the CRC of odd data.
In 4 bit DDR mode,it is not used.
In SDR mode, the higher 16 bits indicate the CRC of all data.

Note: The register is for SMHC0 and SMHC1 only.

4.3.7.33. SMHC Data6 CRC Register (Default Value: 0x00000000)
Offset: 0x0118
Bit

R/W

Register Name: DATA6_CRC_REG
Default/Hex

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Description
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Memory

31:0

R

0

DAT6_CRC
Data[6] CRC
CRC in data[6] form device.
In 8bit DDR mode, the higher 16 bits indicate the CRC of even data, andthe lower 16 bits indicate the CRC of odd data.
In 4 bit DDR mode,it is not used.
In SDR mode, the higher 16 bits indicate the CRC of all data.

Note: The register is for SMHC0 and SMHC1 only.

4.3.7.34. SMHC Data5 CRC Register (Default Value: 0x00000000)
Offset: 0x011c
Bit

31:0

R/W

R

Register Name: DATA5_CRC_REG
Default/Hex

Description0

DAT5_CRC
Data[5] CRC
CRC in data[5] form device.
In 8bit DDR mode, the higher 16 bits indicate the CRC of even data, andthe lower 16 bits indicate the CRC of odd data.
In 4 bit DDR mode,it is not used.
In SDR mode, the higher 16 bits indicate the CRC of all data.

Note: The register is for SMHC0 and SMHC1 only.

4.3.7.35. SMHC Data4 CRC Register (Default Value: 0x00000000)
Offset: 0x0120
Bit

31:0

R/W

R

Register Name: DATA4_CRC_REG
Default/Hex

Description0

DAT4_CRC
Data[4] CRC
CRC in data[4] form device.
In 8 bit DDR mode, the higher 16 bits indicate the CRC of even data, andthe lower 16 bits indicate the CRC of odd data.
In 4 bit DDR mode, the higher 16 bits indicate the CRC of odd data, andthe lower 16 bits indicate the CRC of even data.
In SDR mode, the higher 16 bits indicate the CRC of all data.

Note: The register is for SMHC0 and SMHC1 only.

4.3.7.36. SMHC Data3 CRC Register (Default Value: 0x00000000)
Offset: 0x0124
Bit

R/W

Register Name: DATA3_CRC_REG
Default/Hex

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Memory

31:0

R

0

DATA3_CRC
Data[3] CRC
CRC in data[3] from card/eMMC.
In 8bit DDR mode,the higher 16 bits indicate the CRC of even data,andthe lower 16bits indicate the CRC of odd data.
In 4 bit DDR mode,the higher of 16 bits indicate the CRC of odd data, ,and
the lower 16bits indicate the CRC of even data.
In SDR mode,the higher of 16 bits indicate the CRC of all data.

Note: The register is for SMHC0 and SMHC1 only.

4.3.7.37. SMHC Data2 CRC Register (Default Value: 0x00000000)
Offset: 0x0128
Bit

31:0

R/W

R

Register Name: DATA2_CRC_REG
Default/Hex

Description0

DATA2_CRC
Data[2] CRC
CRC in data[2] from card/eMMC.
In 8bit DDR mode,the higher 16 bits indicate the CRC of even data,andthe lower 16bits indicate the CRC of odd data.
In 4 bit DDR mode,the higher of 16 bits indicate the CRC of odd data, ,and
the lower 16bits indicate the CRC of even data.
In SDR mode,the higher of 16 bits indicate the CRC of all data.

Note: The register is for SMHC0 and SMHC1 only.
4.3.7.38. SMHC Data1 CRC Register (Default Value: 0x00000000)
Offset: 0x012c
Bit

31:0

R/W

R

Register Name: DATA1_CRC_REG
Default/Hex

Description0

DATA1_CRC
Data[1] CRC
CRC in data[1] from card/eMMC.
In 8bit DDR mode,the higher 16 bits indicate the CRC of even data,andthe lower 16bits indicate the CRC of odd data.
In 4 bit DDR mode,the higher of 16 bits indicate the CRC of odd data, ,and
the lower 16bits indicate the CRC of even data.
In SDR mode,the higher of 16 bits indicate the CRC of all data.

Note: The register is for SMHC0 and SMHC1 only.

4.3.7.39. SMHC Data0 CRC Register (Default Value: 0x00000000)
Offset: 0x0130

A64 User Manual(Revision 1.0)

Register Name: DATA0_CRC_REG

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Memory
Bit

31:0

R/W

R

Default/Hex

Description0

DATA0_CRC
Data[0] CRC
CRC in data[0] from card/eMMC.
In 8bit DDR mode,the higher 16 bits indicate the CRC of even data,andthe lower 16bits indicate the CRC of odd data.
In 4 bit DDR mode,the higher of 16 bits indicate the CRC of odd data, ,and
the lower 16bits indicate the CRC of even data.
In SDR mode,the higher of 16 bits indicate the CRC of all data.

Note: The register is for SMHC0 and SMHC1 only.

4.3.7.40. SMHC CRC Status Register (Default Value: 0x00000000)
Offset: 0x0134

Register Name:CRC_STA_REG

Bit

R/W

Default/Hex

Description

31:3

/

/

/

0

CRC_STACRC Status
CRC status from card/eMMC in write operation
Positive CRC status token:3’b010
Negative CRC status token:3’b101

2:0

R

Note: The register is for SMHC0 and SMHC1 only.

4.3.7.41. SMHC Drive Delay Control Register (Default Value: 0x00000000)
Offset: 0x0140

Register Name: SMHC_DDC_REG

Bit

R/W

Default/Hex

Description

31:18

/

/

/

0

DAT_DRV_PH_SEL
Data Drive Phase Select0: Drive phase offset is 900
1: Drive phase select is 1800
In DDR mode, only 900 phase offset is valid.

17

R/W

16

R/W

1

CMD_DRV_PH_SEL
Command Drive Phase Select0: Drive phase offset is 900
1: Drive phase select is 1800

15:0

/

/

/

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Memory
4.3.7.42. SMHC Sample Delay Control Register (Default Value: 0x00002000)
Offset: 0x0144

Register Name: SMHC_SAMP_DL_REG

Bit

R/W

Default/Hex

Description

31:16

/

/

/

0

SAMP_DL_CAL_START
Sample Delay Calibration Start
When set, start sample delay chain calibration.

0

SAMP_DL_CAL_DONE
Sample Delay Calibration Done
When set, it means that sample delay chain calibration is done and theresult of calibration is shown in SAMP_DL.

0x20

SAMP_DL
Sample Delay
It indicates the number of delay cells corresponding to current card clock.
The delay time generated by these delay cells is equal to the cycle of card
clock nearly.
Generally, it is necessary to do drive delay calibration when card clock ischanged.
This bit is valid only when SAMP_DL_CAL_DONE is set.

15

14

13:8

R/W

R

R

7

R/W

0

SAMP_DL_SW_EN
Sample Delay Software Enable
When set, enable smaple delay specified at SAMP_DL_SW.

6

/

/

/

0

SAMP_DL_SW
Sample Delay Software
The relative delay between clock line and command line, data lines.
It can be determined according to the value of SAMP_DL, the cycle ofcard clock and device’s input timing requirement.

5:0

R/W

4.3.7.43. SMHC Data Strobe Delay Control Register (Default Value: 0x00002000)
Offset: 0x0148

Register Name: SMHC_DS_DL_REG

Bit

R/W

Default/Hex

Description

31:16

/

/

/

0

DS_DL_CAL_START
Data Strobe Delay Calibration Start
When set, start sample delay chain calibration.

15

R/W

14

R

0

DS_DL_CAL_DONE
Data Strobe Delay Calibration Done
When set, it means that sample delay chain calibration is done.

13:8

R

0x20

DS_DL

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Memory
Data Strobe Delay
7

R/W

0

DS_DL_SW_EN
Data Strobe Delay Software Enable

6

/

/

/

5:0

R/W

0

DS_DL_SW
Data Strobe Delay Software

Note: The register is for SMHC2 only.

4.3.7.44. SMHC FIFO Register (Default Value: 0x00000000)
Offset: 0x0200

Register Name: SMHC_FIFO_REG

Bit

R/W

Default/Hex

Description

31:0

R/W

0

TX/RX_FIFO
Data FIFO

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ImageChapter 5 Image
This section describes the image input of A64:


CSI

5.1. CSI
5.1.1. Overview
The CSI includes the following feature:
CSI





Support 8bit yuv422 CMOS sensor interface
Support CCIR656 protocol for NTSC and PAL
Maximum still capture resolution to 5M
Maximum video capture resolution to 1080@30fps

CCI








Compatible with i2c transmission in 7 bit slave ID + 1 bit R/W
Automatic transmission
0/8/16/32 bit register address supported
8/16/32 bit data supported
64bytes-FIFO input CCI data supported
Synchronized with CSI signal and delay trigger supported
Repeated transmission with sync signal supported

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Image5.1.2. Functionalities Description
5.1.2.1. Block Diagram

CS Data Clock

FIFO 2
FIFO 1CSI
Formatter

FIFO 0Channel 0

CS Vsync
CS Data

CSI
IF
Converter

YUV Interleaved/Raw IF
MUX

System BUS

CS Hsync

DMA

CCIR656 IF

CS Field

Pattern
Generater

DMA

Figure 5-1. CSI Block Diagram

SDA CTL

CCI FIFO

SDA
PAD
CTL

24MHz CLK

CLD_DIVSCL CTLSCLFMT CTLDLY CNT
CSI0/1 1st HREF
CSI0/1 last HREF
CSI0/1 Line counter

CSI TRIGREGISTER IMMEDIATELY

TRIG
SEL

Figure 5-2. CCI Block Diagram

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Image5.1.2.2. CSI FIFO Distribution
Interface

YUYV422 Interleaved/Raw

Input format

YUV422

BT656 Interface
Raw

Output format

PlanarUV
MB

combined/

CH0_FIFO0

Y pixel data

Y pixel data

CH0_FIFO1

Cb (U) pixel data

Cb (U) Cr (V)pixel data

CH0_FIFO2

Cr (V) pixel data

YUV422

Raw/RGB/PRGB

PlanarUV combined/MB

All pixels data

Y

Y

-

Cb (U)

CbCr (UV)-

Cr (V)-

5.1.2.3. CSI Timing

n frame

VSYNC

n+1 frame…

HSYNC

first line

DATA

second line…

last line

HSYNC
DATA[7/9/11:0]

…

PCLK

…

Figure 5-3. 8-bit CMOS Sensor Interface Timing(clock rising edge sample.vsync valid = positive,hsycn valid = positive)

SAV

D[7:0]FF

00

Pixel2~Pixel3

Pixel0~Pixel1

00

XY

Cb0
[7:0]

Y0
[7:0]

Cr0
Y1
[7:0] [7:0]

Cb2
[7:0]

Y2
[7:0]

Cr2
[7:0]

Y3
[7:0]

...

blank

...

FF

PCLK

Figure 5-4. 8-bit YCbCr4:2:2 with embedded syncs(BT656) Timing

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Image5.1.2.4. CCIR656 Header CodeThe following table shows the data bit definition of CCIR656 Header.
Table 5-1. CCIR656 Header Data Bit definition
Data Bit

First Word(0xFF)

Second Word(0x00)

Third Word(0x00)

Fourth Word

CS D[9] (MSB)

1

0

0

1

CS D[8]

1

0

0

F

CS D[7]

1

0

0

V

CS D[6]

1

0

0

H

CS D[5]

1

0

0

P3

CS D[4]

1

0

0

P2

CS D[3]

1

0

0

P1

CS D[2]

1

0

0

P0

CS D[1]

x

x

x

x

CS D[0]

x

x

x

x

Note: For compatibility with 8-bit interface, CS D[1] and CS D[0] are not defined.
Decode

F

V

H

P3

P2

P1

P0

Field 1 start of active video (SAV)

0

0

0

0

0

0

0

Field 1 end of active video (EAV)

0

0

1

1

1

0

1

Field 1 SAV (digital blanking)

0

1

0

1

0

1

1

Field 1 EAV (digital blanking)

0

1

1

0

1

1

0

Field 2 SAV

1

0

0

0

1

1

1

Field 2 EAV

1

0

1

1

0

1

0

Field 2 SAV (digital blanking)

1

1

0

1

1

0

0

Field 2 EAV (digital blanking)

1

1

1

0

0

0

1

5.1.2.5. Camera Communication Interface
The CCI module support master mode i2c-compatible single read and write access to camera and related
devices.
It reads a series of packet from FIFO (accessed by registers) and transmit with the format defined in specificregister(or packet data).
In compact mode, format register define the slave ID, R/W flag, register address width(0/8/16/32…bit), datawidth(8/16/32…bit) and access counter.
In complete mode, all data and format will be loaded from memory packet.
The access counter should be set to N(N> 0), and it will read N packets from FIFO. The total bytes should not

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Imageexceed 64 for FIFO input mode.
COMPACT MODEMEM STARTMEM END

BYTE0

BYTE1

BYTE2

BYTE3

……

BYTEn

8_8 RDReg0

Data0_rd

Reg1

Data1_rd……

…

8_8 WR

Reg0

Data0

Reg1

Data1

……

...

16_8 RD

Reg0_highReg0_low

Data0_rd

Reg1_high……

...

16_8 WR

Reg0_highReg0_low

Data0

Reg1_high……

...

Total bytes = Packet size * Counter of packet
A packet

COMPLETE MODE
BYTE0

BYTE1

BYTE2

BYTE3

……

BYTEn

8_8 RD

Slave_id

Reg_w/Dat_w

Reg0

Data0

……

…

8_8 WR

Slave_id

Reg_w/Dat_w

Reg0

Data0

……

...

16_8 RD

Slave_id

Reg_w/Dat_w

Reg0_highReg0_low

Data0

...

16_8 WR

Slave_id

Reg_w/Dat_w

Reg0_highReg0_low

Data0

...

Total bytes = Packet size * Counter of packet
A packetA packet is several bytes filled with register address and data(if in complete mode, slave id and width should be
filled too) as the i2c access sequence defined. That is, the low address byte will be transmitted/received first.
Bytes will be sent in write access, while some address will be written back with the data received in readaccess.
Single Access protocol supported by CCI
RS

or

P+S

X

8_8 RD

S

ID+W

ACK

Reg0

RS

ID+R

ACK

8_8 WR

S

ID+W

ACK

Reg0

ACK

Data0_wr

NAC
K

16_8 RD

S

ID+W

ACK

Reg0_high

ACK

Reg0_low

16_8 WR

S

ID+W

ACK

Reg0_high

ACK

Reg0_low

0_16 RD

S

ID+R
ACK
ID+R

0_16 WRS

ID+W

is optional

ACK

is driven by slaveXis driven by CCI

Data0_rd

NAC
K

RS

ID+R

ACK

ACK

Data0_wr

NAC
K

Data0_rd

NAC
K

Data0_rd_hi
Data0_rd_lo NAC
ACK
gh
w
K
Data0_wr_h
Data0_wr_lo NAC
ACK
igh
w
K

After set the execution bit, the module will do the transmission automatically and return the result - success or
fail. If any access fail, the whole transmission will be stopped and returns the number when it fail in the access

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Imagecounter.
Error IRQ
and stop
currenttransmission

Complete IRQ

Whole transmission……
Setting format,
filling packet
data and enabletransmission

CNT_DLY

PACKET1……

PACKETn……

CNT_DLY

PACKET1

Triggeredagain if in
repeat mode

Transmission
Triggered
start

……

PACKETn

Abort
transmission……

Repeattransmission
complete

5.1.3. CSI Register list
Module Name

Base Address

CSI0

0x01CB0000

Register Name

OffsetRegister name

CSI0_EN_REG

0x0000CSI Enable register

CSI0_IF_CFG_REG

0x0004

CSI Interface Configuration Register

CSI0_CAP_REG

0x0008CSI Capture Register

CSI0_SYNC_CNT_REG

0x000CCSI Synchronization Counter Register

CSI0_FIFO_THRS_REG

0x0010CSI FIFO Threshold Register

CSI0_PTN_LEN_REG

0x0030CSI Pattern Generation Length register

CSI0_PTN_ADDR_REG

0x0034

CSI Pattern Generation Address register

CSI0_VER_REG

0x003CCSI Version Register

CSI0_C0_CFG_REG

0x0044

CSI Channel_0 configuration register

CSI0_C0_SCALE_REG

0x004CCSI Channel_0 scale register

CSI0_C0_F0_BUFA_REG

0x0050CSI Channel_0 FIFO 0 output buffer-A address register

CSI0_C0_F1_BUFA_REG

0x0058CSI Channel_0 FIFO 1 output buffer-A address register

CSI0_C0_F2_BUFA_REG

0x0060CSI Channel_0 FIFO 2 output buffer-A address register

CSI0_C0_CAP_STA_REG

0x006CCSI Channel_0 status register

CSI0_C0_INT_EN_REG

0x0070CSI Channel_0 interrupt enable register

CSI0_C0_INT_STA_REG

0x0074

CSI Channel_0 interrupt status register

CSI0_C0_HSIZE_REG

0x0080CSI Channel_0 horizontal size register

CSI0_C0_VSIZE_REG

0x0084

CSI Channel_0 vertical size register

CSI0_C0_BUF_LEN_REG

0x0088CSI Channel_0 line buffer length register

CSI0_C0_FLIP_SIZE_REG

0x008CCSI Channel_0 flip size register

CSI0_C0_FRM_CLK_CNT_REG

0x0090CSI Channel_0 frame clock counter register

CSI0_C0_ACC_ITNL_CLK_CNT_REG

0x0094

CSI Channel_0 accumulated and internal clock counterregister

CSI0_C0_FIFO_STAT_REG

0x0098CSI Channel_0 FIFO Statistic Register

CSI0_C0_PCLK_STAT_REG

0x009CCSI Channel_0 PCLK Statistic Register

CCI_CTRL

0x3000

CCI control register

CCI_CFG

0x3004

CCI transmission config register

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Image
CCI_FMT

0x3008CCI packet format register

CCI_BUS_CTRL

0x300C

CCI bus control register

CCI_INT_CTRL

0x3014

CCI interrupt control register

CCI_LC_TRIG

0x3018

CCI line counter trigger register

CCI_FIFO_ACC

0x3100

CCI FIFO access register

CCI_RSV_REG

0x3200

CCI reserved register

5.1.4. CSI Register Description
5.1.4.1. CSI Enable Register (Default Value: 0x00000000)
Offset: 0x0000

Register Name: CSI0_EN_REG

Bit

R/W

Default/Hex

Description

31

/

/

/

30

R/W

0x0

VER_ENCSI Version Register Read Enable:
0: Disable
1: Enable

29:24

/

/

/

23:16

R/W

0x00

PTN_CYCLE
Pattern generating cycle counter.
The pattern in dram will be generated in cycles of PTN_CYCLE+1.

15:9

/

/

/

8

R/W

0x0

SRAM_PWDN
0: SRAM in normal
1: SRAM in power down

7:5

/

/

/

4

R/W

0x0

PTN_STARTCSI Pattern Generating Start
0: Finishother: Start
Software write this bit to“1” to start pattern generating from DRAM.
When finished, the hardware will clear this bit to“0”automatically.
Generating cycles depends on PTN_CYCLE.

3

R/W

0

CLK_CNT_SPL
Sampling time for clk counter per frame
0: Sampling clock counter every frame done
1: Sampling clock counter every vsync

2

R/W

0

CLK_CNT_EN
clk count per frame enable

1

R/W

0

PTN_GEN_EN

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ImagePattern Generation Enable
0

R/W

0

CSI_EN
Enable0: Reset and disable the CSI module
1: Enable the CSI module

5.1.4.2. CSI Interface Configuration Register (Default Value: 0x00000000)
Offset: 0x0004

Register Name: CSI0_IF_CFG_REG

Bit

R/W

Default/Hex

Description

31:22

/

/

/

21

R/W

0

SRC_TYPE
Source type
0: Progressed
1: Interlaced

20

R/W

0

FPS_DS
Fps down sample
0: no down sample
1: 1/2 fps, only receives the first frame every 2 frames

19

R/W

0

FIELD
For YUV HV timing, Field polarity
0: negative(field=0 indicate odd, field=1 indicate even )1: positive(field=1 indicate odd, field=0 indicate even )For BT656 timing, Field sequence
0: Normal sequence (field 0 first)
1: Inverse sequence (field 1 first)

18

R/W

1

VREF_POL
Vref polarity
0: negative
1: positive
This register is not apply to CCIR656 interface.

17

R/W

0

HERF_POL
Href polarity
0: negative
1: positive
This register is not apply to CCIR656 interface.

16

R/W

1

CLK_POL
Data clock type
0: active in rising edge
1: active in falling edge

15:12

/

/

/

11:10

R/W

0

SEQ_8PLUS2
When select IF_DATA_WIDTH to be 8+2bit, odd/even pixel byte at

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ImageCSI-D[11:4] will be rearranged to D[11:2]+2’b0 at the actual csi data bus
according to these sequences:00: 6’bx+D[9:8], D[7:0]
01: D[9:2], 6’bx+D[1:0]
10: D[7:0], D[9:8]+6’bx
11: D[7:0], 6’bx+D[9:8]
9:8

R/W

0

IF_DATA_WIDTH
00: 8 bit data bus
01: 10 bit data bus
10: 12 bit data bus
11: 8+2bit data bus

7:5

/

/

/

4:0

R/W

0

CSI_IF
YUV:
00000: YUYV422 Interleaved or RAW (All data in one data bus)
CCIR656:00100: YUYV422 Interleaved or RAW (All data in one data bus)
Others: Reserved

5.1.4.3. CSI Capture Register (Default Value: 0x00000000)
Offset: 0x0008

Register Name: CSI0_CAP_REG

Bit

R/W

Default/Hex

Description

31:6

/

/

/

5:2

R/W

0x0

CH0_CAP_MASK
Vsync number masked before capture.

1

R/W

0x0

CH0_VCAP_ON
Video capture control: Capture the video image data stream on channel
0.
0: Disable video capture
If video capture is in progress, the CSI stops capturing image data at theend of the current frame, and all of the current frame data is wrote tooutput FIFO.
1: Enable video capture
The CSI starts capturing image data at the start of the next frame.

0

R/W

0x0

CH0_SCAP_ON
Still capture control: Capture a single still image frame on channel 0.
0: Disable still capture.
1: Enable still capture
The CSI module starts capturing image data at the start of the next
frame. The CSI module captures only one frame of image data. This bit isself clearing and always reads as a 0.

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Image5.1.4.4. CSI Synchronization Counter Register (Default Value: 0x00000000)
Offset: 0x000C

Register Name: CSI0_SYNC_CNT_REG

Bit

R/W

Default/Hex

Description

31:24

/

/

/

23:0

R

0

SYNC_CNTThe counter value between vsync of CSI0 channel 0 and vsync of CSI1
channel 0 , using 24MHz.

5.1.4.5. CSI FIFO Threshold Register (Default Value: 0x040f0400)
Offset: 0x0010

Register Name: CSI0_FIFO_THRS_REG

Bit

R/W

Default/Hex

Description

31:29

/

/

/

28:26

R/W

0x1

FIFO_NEARLY_FULL_TH
The threshold of FIFO being nearly full. Indicates that the ISP should stop
writing. Only valid when ISP is enabled.
0~7:
The smaller the value, the flag of FIFO being nearly full is easier to reach.

25:24

R/W

0x0

PTN_GEN_CLK_DIV
Packet generator clock divider

23:16

R/W

0x0f

PTN_GEN_DLY
Clocks delayed before pattern generating start.

15:12

/

/

/

11:00

R/W

0x400

FIFO_THRS
When CSI0 FIFO occupied memory exceed the threshold, dram frequency
can not change.

5.1.4.6. CSI Pattern Generation Length Register (Default Value: 0x00000000)
Offset: 0x0030

Register Name: CSI0_PTN_LEN_REG

Bit

R/W

Default/Hex

Description

31:0

R/W

0x0

PTN_LEN
The pattern length in byte when generating pattern.

5.1.4.7. CSI Pattern Generation Address Register (Default Value: 0x00000000)
Offset: 0x0034
Bit

R/W

Register Name: CSI0_PTN_ADDR_REG
Default/Hex

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Image
31:0

R/W

0x0

PTN_ADDR
The pattern DRAM address when generating pattern.

5.1.4.8. CSI Version Register (Default Value: 0x00000000)
Offset: 0x003C

Register Name: CSI0_VER_REG

Bit

R/W

Default/Hex

Description

31:0

R

0x0

VER
Version of hardware circuit. Only can be read when version register readenable is on.

5.1.4.9. CSI Channel_0 configuration Register (Default Value: 0x00300200)
Offset: 0x0044

Register Name: CSI0_C0_CFG_REG

Bit

R/W

Default/Hex

Description

31:24

R/W

0

PAD_VAL
Padding value when OUTPUT_FMT is prgb888
0x00~0xff

23:20

R/W

3

INPUT_FMT
Input data format
0000: RAW stream
0001: reserved
0010: reserved0011: YUV422
0100: YUV420
Others: reserved

19:16

R/W

0

OUTPUT_FMT
Output data format
When the input format is set RAW stream
0000: field-raw-8
0001: field-raw-100010: field-raw-120011: reserved
0100: field-rgb565
0101: field-rgb888
0110: field-prgb888
1000: frame-raw-8
1001: frame-raw-10
1010: frame-raw-12
1011: reserved
1100: frame-rgb565

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Image1101: frame-rgb888
1110: frame-prgb888
When the input format is set YUV422
0000: field planar YCbCr 422
0001: field planar YCbCr 420
0010: frame planar YCbCr 420
0011: frame planar YCbCr 422
0100: field planar YCbCr 422 UV combined
0101: field planar YCbCr 420 UV combined
0110: frame planar YCbCr 420 UV combined
0111: frame planar YCbCr 422 UV combined
1000: field MB YCbCr 422
1001: field MB YCbCr 420
1010: frame MB YCbCr 420
1011: frame MB YCbCr 422
1100: field planar YCbCr 422 10bit UV combined
1101: field planar YCbCr 420 10bit UV combined
1110: Reserved
1111: Reserved
When the input format is set YUV420
0000: Reserved
0001: field planar YCbCr 420
0010: frame planar YCbCr 420
0011: Reserved
0100: Reserved
0101: field planar YCbCr 420 UV combined
0110: frame planar YCbCr 420 UV combined
0111: Reserved
1000: Reserved
1001: field MB YCbCr 420
1010: frame MB YCbCr 420
1011: Reserved
1100: Reserved
1101: field planar YCbCr 420 10bit UV combined
1110: Reserved
1111: Reserved
Others: reserved
15:14

/

/

/

13

R/W

0

VFLIP_EN
Vertical flip enable
When enabled, the received data will be arranged in vertical flip.

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Image0:Disable
1:Enable
12

R/W

0

HFLIP_EN
Horizontal flip enable
When enabled, the received data will be arranged in horizontal flip.
0:Disable
1:Enable

11:10

R/W

0

FIELD_SEL
Field selection.
00: capturing with field 1.
01: capturing with field 2.
10: capturing with either field.
11: reserved

09:08

R/W

2

INPUT_SEQ
Input data sequence, only valid for YUV422 and YUV420 input format.
All data interleaved in one channel:
00: YUYV
01: YVYU
10: UYVY
11: VYUY
Y and UV in separated channel:
x0: UVx1: VU

07:02

/

/

/

01:00

R/W

0

MIN_SDR_WR_SIZE
Minimum size of SDRAM block write
0: 256 bytes (if hflip is enable, always select 256 bytes)
1: 512 bytes
2: 1k bytes
3: 2k bytes

5.1.4.10. CSI Channel_0 scale Register (Default Value: 0x00000000)
Offset: 0x004C

Register Name: CSI0_C0_SCALE_REG

Bit

R/W

Default/Hex

Description

31:01

/

/

/

00

R/W

0

QUART_EN
When this bit is set to 1, input image will be decimated to quarter size.
All input format are supported.

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Image5.1.4.11. CSI Channel_0 FIFO 0 output buffer-A address Register (Default Value: 0x00000000)
Offset: 0x0050

Register Name: CSI0_C0_F0_BUFA_REG

Bit

R/W

Default/Hex

Description

31:00

R/W

0

C0F0_BUFAFIFO 0 output buffer-A address

5.1.4.12. CSI Channel_0 FIFO 1 output buffer-A address Register (Default Value: 0x00000000)
Offset: 0x0058

Register Name: CSI0_C0_F1_BUFA_REG

Bit

R/W

Default/Hex

Description

31:00

R/W

0

C0F1_BUFAFIFO 1 output buffer-A address

5.1.4.13. CSI Channel_0 FIFO 2 output buffer-A address Register (Default Value: 0x00000000)
Offset: 0x0060

Register Name: CSI0_C0_F2_BUFA_REG

Bit

R/W

Default/Hex

Description

31:00

R/W

0

C0F2_BUFAFIFO 2 output buffer-A address

5.1.4.14. CSI Channel_0 status Register (Default Value: 0x00000000)
Offset: 0x006C

Register Name: CSI0_C0_CAP_STA_REG

Bit

R/W

Default/Hex

Description

31:03

/

/

/

02

R

0

FIELD_STA
The status of the received field
0: Field 0
1: Field 1

01

R

0

VCAP_STA
Video capture in progress
Indicates the CSI is capturing video image data (multiple frames). The bit
is set at the start of the first frame after enabling video capture. When
software disables video capture, it clears itself after the last pixel of thecurrent frame is captured.

00

R

0

SCAP_STA
Still capture in progress
Indicates the CSI is capturing still image data (single frame). The bit is set

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Imageat the start of the first frame after enabling still frame capture. It clears
itself after the last pixel of the first frame is captured.
For CCIR656 interface, if the output format is frame planar YCbCr 420
mode, the frame end means the field2 end, the other frame end means
filed end.

5.1.4.15. CSI Channel_0 interrupt enable Register (Default Value: 0x00000000)
Offset: 0x0070

Register Name: CSI0_C0_INT_EN_REG

Bit

R/W

Default/Hex

Description

31:08

/

/

/

07

R/W

0

VS_INT_EN
vsync flag
The bit is set when vsync come. And at this time load the buffer address
for the coming frame. So after this irq come, change the buffer address
could only effect next frame

06

R/W

0

HB_OF_INT_EN
Hblank FIFO overflow
The bit is set when 3 FIFOs still overflow after the hblank.

05

R/W

0

MUL_ERR_INT_EN
Multi-channel writing error
Indicates error has been detected for writing data to a wrong channel.

04

R/W

0

FIFO2_OF_INT_EN
FIFO 2 overflow
The bit is set when the FIFO 2 become overflow.

03

R/W

0

FIFO1_OF_INT_EN
FIFO 1 overflow
The bit is set when the FIFO 1 become overflow.

02

R/W

0

FIFO0_OF_INT_EN
FIFO 0 overflow
The bit is set when the FIFO 0 become overflow.

01

R/W

0

FD_INT_EN
Frame done
Indicates the CSI has finished capturing an image frame. Applies to video
capture mode. The bit is set after each completed frame capturing data iswrote to buffer as long as video capture remains enabled.

00

R/W

0

CD_INT_EN
Capture done
Indicates the CSI has completed capturing the image data.
For still capture, the bit is set when one frame data has been wrote tobuffer.
For video capture, the bit is set when the last frame has been wrote tobuffer after video capture has been disabled.

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ImageFor CCIR656 interface, if the output format is frame planar YCbCr 420
mode, the frame end means the field2 end, the other frame end means
field end.

5.1.4.16. CSI Channel_0 interrupt status Register (Default Value: 0x00000000)
Offset: 0x0074

Register Name: CSI0_C0_INT_STA_REG

Bit

R/W

Default/Hex

Description

31:08

/

/

/

07

R/W

0

VS_PD
vsync flag

06

R/W

0

HB_OF_PD
Hblank FIFO overflow

05

R/W

0

MUL_ ERR_PD
Multi-channel writing error

04

R/W

0

FIFO2_OF_PD
FIFO 2 overflow

03

R/W

0

FIFO1_OF_PD
FIFO 1 overflow

02

R/W

0

FIFO0_OF_PD
FIFO 0 overflow

01

R/W

0

FD_PD
Frame done

00

R/W

0

CD_PD
Capture done

5.1.4.17. CSI Channel_0 horizontal size Register (Default Value: 0x05000000)
Offset: 0x0080

Register Name: CSI0_C0_INT_STA_REG

Bit

R/W

Default/Hex

Description

31:29

/

/

/

28:16

R/W

500

HOR_LEN
Horizontal pixel unit length. Valid pixel of a line.

15:13

/

/

/

12:00

R/W

0

HOR_START
Horizontal pixel unit start. Pixel is valid from this pixel.

5.1.4.18. CSI Channel_0 vertical size Register (Default Value: 0x01E00000)
Offset: 0x0084
A64 User Manual(Revision 1.0)

Register Name: CSI0_C0_VSIZE_REG
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ImageBit

R/W

Default/Hex

Description

31:29

/

/

/

28:16

R/W

1E0

VER_LEN
Vertical line length. Valid line number of a frame.

15:13

/

/

/

12:00

R/W

0

VER_START
Vertical line start. data is valid from this line.

5.1.4.19. CSI Channel_0 buffer length Register (Default Value: 0x01400280)
Offset: 0x0088

Register Name: CSI0_C0_BUF_LEN_REG

Bit

R/W

Default/Hex

Description

31:30

/

/

/

29:16

R/W

140

BUF_LEN_C
Buffer length of chroma C in a line. Unit is byte.

15:14

/

/

/

13:00

R/W

280

BUF_LEN
Buffer length of luminance Y in a line. Unit is byte.

5.1.4.20. CSI Channel_0 flip size Register (Default Value: 0x01E00280)
Offset: 0x008C

Register Name: CSI0_C0_FLIP_SIZE_REG

Bit

R/W

Default/Hex

Description

31:29

/

/

/

28:16

R/W

1E0

VER_LEN
Vertical line number when in vflip mode.

15:13

/

/

/

12:00

R/W

280

VALID_LEN
Valid components of a line when in flip mode.

5.1.4.21. CSI Channel_0 frame clock counter Register (Default Value: 0x00000000)
Offset: 0x0090

Register Name: CSI0_C0_FRM_CLK_CNT_REG

Bit

R/W

Default/Hex

Description

31:24

/

/

/

23:00

R

0

FRM_CLK_CNTCounter value between every frame. For instant hardware frame ratestatics.
The internal counter is added by one every 24MHz clock cycle. When

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Imageframe done or vsync comes, the internal counter value is sampled to
FRM_CLK_CNT, and cleared to 0.

5.1.4.22. CSI Channel_0 accumulated and internal clock counter Register (Default Value: 0x00000000)
Offset: 0x0094

Register Name: CSI0_C0_ACC_ITNL_CLK_CNT_REG

Bit

R/W

Default/Hex

Description

31:24

R

0

ACC_CLK_CNT
The accumulated value of FRM_CLK_CNT for software frame rate statics.
Every interrupt of frame done, the software check this accumulated
value and clear it to 0. If the ACC_CLK_CNT is larger than 1, the software
has lost frame.
When frame done or vsync comes, ACC_CLK_CNT = ACC_CLK_CNT + 1,
and cleared to 0 when writing 0 to this register.

23:00

R

0

ITNL_CLK_CNT
The instant value of internal frame clock counter.
When frame done interrupt comes, the software can query this counterfor judging whether it is the time for updating the double buffer address
registers.

5.1.4.23. CSI Channel_0 FIFO Statistic Register (Default Value: 0x00000000)
Offset: 0x0098

Register Name: CSI0_C0_FIFO_STAT_REG

Bit

R/W

Default/Hex

Description

31:12

/

/

/

11:00

R

0

FIFO_FRM_MAX
Indicates the maximum depth of FIFO being occupied for whole frame.
Update at every vsync or framedone.

5.1.4.24. CSI Channel_0 PCLK Statistic Register (Default Value: 0x00007FFF)
Offset: 0x009C

Register Name: CSI0_C0_PCLK_STAT_REG

Bit

R/W

Default/Hex

Description

31

/

/

/

30:16

R

0

PCLK_CNT_LINE_MAX
Indicates maximum pixel clock counter value for each line.
Update at every vsync or framedone.

15

/

/

/

14:00

R

0x7fff

PCLK_CNT_LINE_MIN
Indicates minimum pixel clock counter value for each line.

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ImageUpdate at every vsync or framedone.

5.1.4.25. CCI Control Register (Default Value: 0x00000000)
Offset: 0x3000

Register Name: CCI_CTRL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0

SINGLE_TRAN
0: Transmission idle
1: Start single transmission
Automatically cleared to ‘0’ when finished. Abort current transmission
immediately if changing from ‘1’ to ‘0’. If slave not respond for the
expected status over the time defined by TIMEOUT, current transmission
will stop. PACKET_CNT will return the sequence number whentransmission fail. All format setting and data will be loaded from registers
and FIFO when transmission start.

30

R/W

0

REPEAT_TRAN
0: transmission idle
1: repeated transmission
When this bit is set to 1, transmission repeats when trigger signal (suchas VSYNC/ VCAP done ) repeats.
If changing this bit from ‘1’ to ‘0’ during transmission, the current
transmission will be guaranteed then stop.

29

R/W

0

RESTART_MODE
0: RESTART
1: STOP+START
Define the CCI action after sending register address.

28

R/W

0

READ_TRAN_MODE
0: send slave_id+W
1: do not send slave_id+W
Note:Setting this bit to 1 if reading from a slave which register width isequal to 0.

27:24

R

0

TRAN_RESULT
000: OK
001: FAIL
Other: Reserved

23:16

R

/

CCI_STA
0x00: bus error
0x08: START condition transmitted
0x10: Repeated START condition transmitted
0x18: Address + Write bit transmitted, ACK received
0x20: Address + Write bit transmitted, ACK not received
0x28: Data byte transmitted in master mode, ACK received
0x30: Data byte transmitted in master mode, ACK not received

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Image0x38: Arbitration lost in address or data byte
0x40: Address + Read bit transmitted, ACK received
0x48: Address + Read bit transmitted, ACK not received
0x50: Data byte received in master mode, ACK received
0x58: Data byte received in master mode, ACK not received
0x01: Timeout when sending 9th SCL clk
Other: Reserved
15:2

/

/

/

1

R/W

0

SOFT_RESET
0: normal
1: reset

0

R/W

0

CCI_EN
0: Module disable
1: Module enable

5.1.4.26. CCI Transmission Configuration Register (Default Value: 0x10000000)
Offset: 0x3004

Register Name: CCI_CFG_REG

Bit

R/W

Default/Hex

Description

31:24

R/W

0x10

TIMEOUT_N
When sending the 9th clock, assert fail signal when slave device did not
response after N*FSCL cycles. And software must do a reset to CCI
module and send a stop condition to slave.

23:16

R/W

0x00

INTERVAL
Define the interval between each packet in 40*FSCL cycles. 0~255

15

R/W

0

PACKET_MODE
Select where to load slave id / data width
0: Compact mode
1: Complete mode
In compact mode, slave id/register width / data width will be loaded
from CCI_FMT register, only address and data read from memory.
In complete mode, they will be loaded from packet memory.

14:7

/

/

/

6:4

R/W

0

TRIG_MODE
Transmit mode:
000: Immediately, no trigger
001: Reserved
010: CSI0 int trigger
011: CSI1 int trigger

3:0

R/W

0

CSI_TRIGCSI Int trig signal select:
0000: First HREF start
0001: Last HREF done

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Image0010: Line counter trigger
other: Reserved

5.1.4.27. CCI Packet Format Register (Default Value: 0x00110001)
Offset: 0x3008

Register Name: CCI_FMT_REG

Bit

R/W

Default/Hex

Description

31:25

R/W

0

SLV_ID
7bit address

24

R/W

0

CMD
0: write
1: read

23:20

R/W

1

ADDR_BYTE
How many bytes be sent as address
0~15

19:16

R/W

1

DATA_BYTE
How many bytes be sent/received as data
1~15
Normally use ADDR_DATA with 0_2, 1_1, 1_2, 2_1, 2_2 access mode. If
DATA bytes is 0, transmission will not start. In complete mode, the
ADDR_BYTE and DATA_BYTE is defined in a byte’s high/low 4bit.

15:0

R/W

1

PACKET_CNT
FIFO data be transmitted as PACKET_CNT packets in current format.
Total bytes not exceed 32bytes.

5.1.4.28. CCI Bus Control Register (Default Value: 0x00002500)
Offset: 0x300C

Register Name: CCI_BUS_REG

Bit

R/W

Default/Hex

Description

31:16

R/W

0

DLY_CYC
0~65535 FSCL cycles between each transmission

15

R/W

0

DLY_TRIG
0: disable
1: execute transmission after internal counter delay when triggered

14:12

R/W

0x2

CLK_N
CCI bus sampling clock F0=24MHz/2^CLK_N

11:8

R/W

0x5

CLK_M
CCI output SCL frequency is FSCL=F1/10=(F0/(CLK_M+1))/10

7

R

/

SCL_STASCL current status

6

R

/

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Image
SDA current status
5

R/W

0

SCL_PENSCL PAD enable

4

R/W

0

SDA_PENSDA PAD enable

3

R/W

0

SCL_MOVSCL manual output value

2

R/W

0

SDA_MOVSDA manual output value

1

R/W

0

SCL_MOE
SCL manual output en

0

R/W

0

SDA_MOE
SDA manual output en

5.1.4.29. CCI Interrupt Control Register (Default Value: 0x00000000)
Offset: 0x3014

Register Name: CCI_INT_CTRL_REG

Bit

R/W

Default/Hex

Description

31:18

/

/

/

17

R/W

0

S_TRAN_ERR_INT_EN

16

R/W

0

S_TRAN_COM_INT_EN

15:2

/

/

/

1

R/W

0

S_TRAN_ERR_PD

0

R/W

0

S_TRAN_COM_PD

5.1.4.30. CCI Line Counter Trigger Control Register (Default Value: 0x00000000)
Offset: 0x3018

Register Name: CCI_LC_REG

Bit

R/W

Default/Hex

Description

31:13

/

/

/

12:0

R/W

0

LN_CNT0~8191: line counter send trigger when 1st~8192th line is received.

5.1.4.31. CCI FIFO Acess Register (Default Value: 0x00000000)
Offset: 0x3100~0x313f

Register Name: CCI_FIFO_ACC_REG

Bit

R/W

Default/Hex

Description

31:0

R/W

0

DATA_FIFO
From 0x100 to 0x13f, CCI data fifo is 64bytes, used in fifo input mode. CCI

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Imagetransmission read/write data from/to fifo in byte.

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Display

Chapter 6 Display
This chapter describes the A64 display system from following perspectives:



DE2.0
TCON

The following figure shows the block diagramof display system:

LVDS
DE2.0
TCON0

RT-Mixer
Core 0MIPIDSI

MUX

M
B
U
S

RT-Mixer
Core 1

RGB

TCON1

HDMI

Write-Back

RotateFigure 6-1. Display System Block Diagram

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Display

6.1. DE2.0
6.1.1. Overview

Output size up to 4096x4096
Support four alpha blending channel for main display, two channel for aux display
Support four overlay layers in each channel, and has a independent scalerSupport potter-duff compatible blending operation
Support input format YUV422/YUV420/YUV411/ARGB8888/XRGB8888/RGB888/ARGB4444/ARGB1555 and
RGB565Support Frame Packing/Top-and-Bottom/Side-by-side Full/Side-by-Side Half 3D format dataSupport SmartColor 2.0 for excellent display experience- Adaptive edge sharping- Adaptive color enhancement- Adaptive contrast enhancement and fresh tone rectifySupport writeback and rotation for high effieient dual display and miracast

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Display

6.2. TCON
6.2.1. Overview












Support LVDS interface with single link, up to 1366x768@60fps
Support RGB interface with DE/SYNC mode, up to 1920x1200@60fps
Support serial RGB/dummy RGB/CCIR656 interface, up to 800x480@60fps
Support i80 interface with 18/16/9/8 bit, support TE, up to 800x480@60fps
Support 4-lanes MIPI DSI up to 1920x1200@60fps
Support HDMI1.4 with HDCP1.2 up to4K@30fps
Support pixel format: RGB888, RGB666 and RGB565
Dither function from RGB666/RGB565 to RGB888
Gamma correction with R/G/B channel independence
4 interrupts for programmer LCD output
2 input source: DE sources

6.2.2. Block Diagram
The following figure shows the block diagram of dual TCON controller.

Figure 6-2. TCON0 Block Diagram

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Display

Figure 6-3. TCON1 Block Diagram

6.2.3. Functionalities Description
6.2.3.1. Panel Interface
HV_I/F(Sync+DE mode)
HV I/F is also known as Sync + DE mode, which is widely used in TFT LCD module for PMP/MP4 applications.
Its signals are define as:
Main Signal

I/O type

Definition And Description

Vsync

O

Vertical sync, indicates one new frame

Hsync

O

Horizontal sync, indicate one new scan line

DCLK

O

Dot clock, pixel data are sync by this clock

LDEO

LCD data enable

LD[23..0]O

18Bit RGB/YUV output from input FIFO for panel

HV control signals are active low.
The following figures show the Panel interface timing ,Parallel mode and serial mode timing of TCON0.

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Figure 6-4. Panel Interface Timing of Odd/Even field

Figure 6-5. Panel Interface Timing of Even field

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Figure 6-6.Parallel Mode Horizontal Timing

Figure 6-7. Serial Mode Horizontal Timing

CCIR output SAV/EAV sync signal
When in HV serial YUV output mode, it’s timing is CCIR656/601 compatible. SAV add right before active
area every line; EAV add right after active area every line.

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It logic are:F = “0” for Field 1 F = “1” for Field 2
V = “1” during vertical blanking
H = “0” at SAV H = “1” at EAV
P3–P0 = protection bits
P3 = V ⊕P2 = F ⊕P1 = F ⊕P0 = F ⊕⊕Where ⊕

exclusive-OR function

The 4 byte SAV/EAV sequences are:8-bit Data

10-bit Data

D9
D8

D7

D6

D5

D4

D3

D2

D1

D0

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

F

V

H

P3

P2

P1

P0

0

0

(MSB)
preamble
Status word

CPU_I/FCPU I/F LCD panel is most common interface for small size, low resolution LCD panels.
CPU control signals are active low.
Main Signal

I/O type

Definition And Description

CS

O

Chip select, active low

WRO

Write strobe, active low

RDO

Read strobe, active low

A1

O

Address bit, controlled by "LCD_CPUI/F" BIT26/25

D[23..0]

I/O

Digital RGB output signal

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The following figure relationship between basic timing and CPU timing. WR is 180 degree delay of DCLK; CS is
active when pixel data are valid; RD is always set to 1; A1 are set by “Lcd_CPU I/F”. When CPU I/F is in IDLE
state, it can generate WR/RD timing by setting “Lcd_CPU I/F”. CS strobe is one DCLK width, WR/RD strobe ishalf DCLK width.

Hsync

DCLK

LDE

CS

WR

D[23..0]

Invalid

Valid line data

Invalid line data

Figure 6-8. CPU I/F LCD panel
LVDS_IF

Previous Cycle

Next Cycle

Current Cycle

Clock

RIN0+
RIN0-

R3

R2

G2

R7

R6

R5

R4

R3

R2

G2

RIN1+
RIN1-

G4

G3

B3

B2

G7

G6

G5

G4

G3

B3

RIN2+
RIN2-

B5

B4

DE

VS

HS

B7

B6

B5

B4

DE

RIN3+
RIN3-

R1

R0

NA

B1

B0

G1

G0

R1

R0

NA

Figure 6-9. LVDS_IF JEDIA mode

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Next Cycle

Current Cycle

Clock

RIN0+
RIN0-

R1

R0

G0

R5

R4

R3

R2

R1

R0

G0

RIN1+
RIN1-

G2

G1

B1

B0

G5

G4

G3

G2

G1

B1

RIN2+
RIN2-

B3

B2

DE

VS

HS

B5

B4

B3

B2

DE

RIN3+
RIN3-

R7

R6

NA

B7

B6

G7

G6

R7

R6

NA

Figure 6-10. LVDS_IF NS mode

6.2.3.2. RGB gamma correction
Function: This module correct the RGB input data of DE0 .
A 256*8*3 Byte register file is used to store the gamma table. The following is the layout:
OffsetValue

0x400, 0x401, 0x402{ B0[7:0], G0[7:0], R0[7:0] }0x404,{ B1[7:0], G1[7:0], R1[7:0] }......

......

0x4FC{ B255[7:0], G255[7:0], R255[7:0] }6.2.3.3. CEU module
Function: This module enhance color data from DE0 .
R’ = Rr*R + Rg*G + Rb*B + Rc
G’ = Gr*R + Gg*G + Gb*B +Gc
B’ = Br*R + Bg*G + Bb*B + Bc
Note:Rr, Rg, Rb, ,Gr, Gg, Gb, Br, Bg, Bb s13 (-16,16)
Rc, Gc, Bc
s19 (-16384, 16384)
R, G, Bu8 [0-255]
R’ have the range of [Rmin ,Rmax]
G’ have the range of [Rmin ,Rmax]
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B’ have the range of[Rmin ,Rmax]

6.2.3.4. CMAP module
Function: This module map color data from DE
Every 4 input pixels are as a unit. A unit is divided into 12 bytes. Output byte can select one of those 12
bytes.Note that even line and odd line can be different, and output can be 12 bytes(4 pixels) or reduce to 6
bytes(2 pixels).
Input

Output

r0(2)

r1(6)

r2(a)

r3(d)

D23:16

odd0

g0(1)

g1(5)

g2(9)

g3(c)

D15:08

odd0

b0(0)

b1(4)

b2(8)

b3(b)

D07:00

odd0

In mode: 4 pixels
Out mode: 4 pixels/2 pixels

eve0

odd1

odd2

odd3

eve1

eve2

eve3

6.2.4. TCON0 Module Register List
Module Name

Base Address

TCON0

0x01C0C000

Register Name

OffsetDescription

TCON_GCTL_REG

0x000

TCON global control register

TCON_GINT0_REG

0x004

TCON global interrupt register0

TCON_GINT1_REG

0x008

TCON global interrupt register1

TCON0_FRM_CTL_REG

0x010

TCON FRM control register

TCON0_FRM_SEED_REG

0x014+N*0x04

TCON FRM seed register(N=0,1,2,3,4,5)

TCON0_FRM_TAB_REG

0x02C+N*0x04

TCON FRM table register(N=0,1,2,3)

TCON0_3D_FIFO_REG

0x03C

TCON0 3D fifo register

TCON0_CTL_REG

0x040

TCON0 control register

TCON0_DCLK_REG

0x044

TCON0 data clock register

TCON0_BASIC0_REG

0x048

TCON0 basic timing register0

TCON0_BASIC1_REG

0x04C

TCON0 basic timing register1

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TCON0_BASIC2_REG

0x050

TCON0 basic timing register2

TCON0_BASIC3_REG

0x054

TCON0 basic timing register3

TCON0_HV_IF_REG

0x058

TCON0 hv panel interface register

TCON0_CPU_IF_REG

0x060

TCON0 cpu panel interface register

TCON0_CPU_WR_REG

0x064

TCON0 cpu panel write data register

TCON0_CPU_RD0_REG

0x068

TCON0 cpu panel read data register0

TCON0_CPU_RD1_REG

0x06C

TCON0 cpu panel read data register1

TCON0_LVDS_IF_REG

0x084

TCON0 lvds panel interface register

TCON0_IO_POL_REG

0x088

TCON0 IO polarity register

TCON0_IO_TRI_REG

0x08C

TCON0 IO trigger register

TCON_CEU_CTL_REG

0x100

TCON CEU control register

TCON_CEU_COEF_MUL_REG

0x110+N*0x04

TCON CEU coefficient register0(N=0,1,2,4,5,6,8,9,10)

TCON_CEU_COEF_ADD_REG

0x11C+N*0x10

TCON CEU coefficient register1(N=0,1,2)

TCON_CEU_COEF_RANG_REG

0x140+N*0x04

TCON CEU coefficient register2(N=0,1,2)

TCON0_CPU_TRI0_REG

0x160

TCON0 cpu panel trigger register0

TCON0_CPU_TRI1_REG

0x164

TCON0 cpu panel trigger register1

TCON0_CPU_TRI2_REG

0x168

TCON0 cpu panel trigger register2

TCON0_CPU_TRI3_REG

0x16C

TCON0 cpu panel trigger register3

TCON0_CPU_TRI4_REG

0x170

TCON0 cpu panel trigger register4

TCON0_CPU_TRI5_REG

0x174

TCON0 cpu panel trigger register5

TCON_CMAP_CTL_REG

0x180

TCON color map control register

TCON_CMAP_ODD0_REG

0x190

TCON color map odd line register0

TCON_CMAP_ODD1_REG

0x194

TCON color map odd line register1

TCON_CMAP_EVEN0_REG

0x198

TCON color map even line register0

TCON_CMAP_EVEN1_REG

0x19C

TCON color map even line register1

TCON_SAFE_PERIOD_REG

0x1F0

TCON safe period register

TCON0_LVDS_ANA0_REG

0x220

TCON LVDS analog register0

TCON0_GAMMA_TABLE_REG

0x400-0x7FF

TCON0_3D_FIFO_BIST_REG

0xFF4

TCON_TRI_FIFO_BIST_REG

0xFF8

6.2.5. TCON0 Module Register Description
6.2.5.1. TCON Global Control Register (Default Value: 0x00000000)
Offset: 0x0000
Bit

R/W

Register Name: TCON_GCTL_REG
Default/Hex

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31

R/W

0

TCON_En
0: disable
1: enable
When it’s disabled, the module will be reset to idle state.

30

R/W

0

TCON_Gamma_En
0: disable
1: enable

29:1

/

/

/

0

R/W

0

IO_Map_Sel
0: TCON0
1: TCON1
Note: this bit determined which IO_INV/IO_TRI are valid

6.2.5.2. TCON Global Interrupt Register0 (Default Value: 0x00000000)
Offset: 0x0004

Register Name: TCON_GINT0_REG

Bit

R/W

Default/Hex

Description

31

R/W

0

TCON0_Vb_Int_En
0: disable
1: enable

30

R/W

0

TCON1_Vb_Int_En
0: disable
1: enable

29

R/W

0

TCON0_Line_Int_En
0: disable
1: enable

28

R/W

0

TCON1_Line_Int_En
0: disable
1: enable

27

R/W

0

TCON0_Tri_Finish_Int_En
0: disable
1: enable

26:

R/W

0

TCON0_Tri_Counter_Int_En
0: disable
1: enable

25:16

/

/

/

15

R/W

0

TCON0_Vb_Int_Flag
Asserted during vertical no-display period every frame.
Write 0 to clear it.

14

R/W

0

TCON1_Vb_Int_Flag
Asserted during vertical no-display period every frame.
Write 0 to clear it.

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13

R/W

0

TCON0_Line_Int_Flag
Trigger when SY0 match the current TCON0 scan line
Write 0 to clear it.

12

R/W

0

TCON1_Line_Int_Flag
Trigger when SY1 match the current TCON1 scan line
Write 0 to clear it.

11

R/W

0

TCON0_Tri_Finish_Int_Flag
Trigger when cpu trigger mode finish
Write 0 to clear it.

10

R/W

0

TCON0_Tri_Counter_Int_Flag
Trigger when tri counter reache this value
Write 0 to clear it.

9

R/W

0

TCON0_Tri_Underflow_Flag
Only used in dsi video mode, tri when sync by dsi but not finish
Write 0 to clear it.

8:0

/

/

/

6.2.5.3. TCON Global Interrupt Register1 (Default Value: 0x00000000)
Offset: 0x0008

Register Name: TCON_GINT1_REG

Bit

R/W

Default/Hex

Description

31:28

/

/

/

27:16

R/W

0

TCON0_Line_Int_Num
scan line for TCON0 line trigger(including inactive lines)
Setting it for the specified line for trigger0.
Note: SY0 is writable only when LINE_TRG0 disable.

15:12

/

/

/

11:0

R/W

0

TCON1_Line_Int_Num
scan line for TCON1 line trigger(including inactive lines)
Setting it for the specified line for trigger 1.
Note: SY1 is writable only when LINE_TRG1 disable.

6.2.5.4. TCON FRM Control Register0 (Default Value: 0x00000000)
Offset: 0x0010

Register Name: TCON0_FRM_CTL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0

TCON0_Frm_En
0:disable
1:enable

30:7

/

/

/

6

R/W

0

TCON0_Frm_Mode_R

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0: 6bit frm output
1: 5bit frm output
5

R/W

0

TCON0_Frm_Mode_G
0: 6bit frm output
1: 5bit frm output

4

R/W

0

TCON0_Frm_Mode_B
0: 6bit frm output
1: 5bit frm output

3:2

/

/

/

1:0

R/W

0

TCON0_Frm_Test
00: FRM
01: half 5/6bit, half FRM
10: half 8bit, half FRM
11: half 8bit, half 5/6bit

6.2.5.5. TCON FRM Seed Register0 (Default Value: 0x00000000)
Offset: 0x0014+N*0x04(N=0,1,2,3,4,5)

Register Name: TCON0_FRM_SEED_REG

Bit

R/W

Default/Hex

Description

31:25

/

/

/

24:0

R/W

0

Seed_Value
N=0: Pixel_Seed_R
N=1: Pixel_Seed_G
N=2: Pixel_Seed_B
N=3: Line_Seed_R
N=4: Line_Seed_G
N=5: Line_Seed_B
Note: avoid set it to 0

6.2.5.6. TCON FRM Table Register0 (Default Value: 0x00000000)
Offset: 0x002C+N*0x04(N=0,1,2,3)

Register Name: TCON0_FRM_TAB_REG

Bit

R/W

Default/Hex

Description

31:0

R/W

0

Frm_Table_Value

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6.2.5.7. TCON 3D FIFO Register0 (Default Value: 0x00000000)
Offset: 0x003C

Register Name: TCON0_3D_FIFO_REG

Bit

R/W

Default/Hex

Description

31

R/W

0

3D_FIFO_BIST_EN
0: disable
1: enable

30:14

/

/

/

13:4

R/W

0

3D_FIFO_HALF_LINE_SIZE
Note:
The number of data in half line=3D_FIFO_HALF_LINE_SIZE+1
only valid when 3D_FIFO_SETTING set as 2

3:2

/

/

/

1:0

R/W

0

3D_FIFO_SETTING
0: by pass
1: used as normal FIFO
2: used as 3D interlace FIFO
3: reserved

6.2.5.8. TCON0 Control Register (Default Value: 0x00000000)
Offset: 0x040

Register Name: TCON0_CTL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0

TCON0_En
0: disable
1: enable
Note: It executes at the beginning of the first blank line of TCON0 timing.

30:29

/

/

/

28

R/W

0

TCON0_Work_Mode
0: normal
1: dynamic freq

27:26

/

/

/

25:24

R/W

0

TCON0_IF
00: HV(Sync+DE)
01: 8080 I/F
1x:reservd

23

R/W

0

TCON0_RB_Swap
0: default
1: swap RED and BLUE data at FIFO1

22

/

/

/

21

R/W

0

TCON0_FIFO1_Rst
Write 1 and then 0 at this bit will reset FIFO 1

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20

/

/

/

19:9

/

/

/

8:4

R/W

0

TCON0_Start_Delay
STA delay
NOTE: valid only when TCON0_EN == 1

3

/

/

/

2:0

R/W

0

TCON0_SRC_SEL:
000: DE0001: reserved
010: reserved
011: reserved
100: Test Data all 0
101: Test Data all 1
11x: reserved

6.2.5.9. TCON0 Data Clock Register (Default Value: 0x00000000)
Offset: 0x044

Register Name: TCON0_DCLK_REG

Bit

R/W

Default/Hex

Description

31:28

R/W

0

TCON0_Dclk_En
LCLK_EN[3:0] :TCON0 clock enable
4'h0, 'h4,4'h6,4'ha7:dclk_en=0;dclk1_en=0;dclk2_en=0;dclkm2_en=0;
4'h1: dclk_en = 1; dclk1_en = 0; dclk2_en = 0; dclkm2_en = 0;
4'h2: dclk_en = 1; dclk1_en = 0; dclk2_en = 0; dclkm2_en = 1;
4'h3: dclk_en = 1; dclk1_en = 1; dclk2_en = 0; dclkm2_en = 0;
4'h5: dclk_en = 1; dclk1_en = 0; dclk2_en = 1; dclkm2_en = 0;
4'h8,4'h9,4'ha,4'hb,4'hc,4'hd,4'he,4'hf:
dclk_en= 1;
dclk1_en = 1;
dclk2_en = 1;
dclkm2_en = 1;

27:7

/

/

/

6:0

R/W

0

TCON0_Dclk_Div
Tdclk = Tsclk * DCLKDIV
Note:
1.if dclk1&dclk2 used，DCLKDIV >=6
2.if dclk only，DCLKDIV >=1

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6.2.5.10. TCON0 Basic0 Register (Default Value: 0x00000000)
Offset: 0x048

Register Name: TCON0_BASIC0_REG

Bit

R/W

Default/Hex

Description

31:28

/

/

/

27:16

R/W

0

TCON0_X
Panel width is X+1

15:12

/

/

/

11:0

R/W

0

TCON0_Y
Panel height is Y+1

6.2.5.11. TCON0 Basic1 Register (Default Value: 0x00000000)
Offset: 0x04C

Register Name: TCON0_BASIC1_REG

Bit

R/W

Default/Hex

Description

31

R/W

0

Reservd

30:29

/

/

/

28:16

R/W

0

HT
Thcycle = (HT+1) * Tdclk
Computation
1) parallel:HT = X + BLANK
Limitation:1) parallel :HT >= (HBP +1) + (X+1) +2
2) serial 1: HT >= (HBP +1) + (X+1) *3+2
3) serial 2: HT >= (HBP +1) + (X+1) *3/2+2

15:12

/

/

/

11:0

R/W

0

HBP
horizontal back porch (in dclk)
Thbp = (HBP +1) * Tdclk

6.2.5.12. TCON0 Basic2 Register (Default Value: 0x00000000)
Offset: 0x050

Register Name: TCON0_BASIC2_REG

Bit

R/W

Default/Hex

Description

31:29

/

/

/

28:16

R/W

0

VT
TVT = (VT)/2 * Thsync
Note: VT/2 >= (VBP+1 ) + (Y+1) +2

15:12

/

/

/

11:0

R/W

0

VBP

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Tvbp = (VBP +1) * Thsync

6.2.5.13. TCON0 Basic3 Register (Default Value: 0x00000000)
Offset: 0x054

Register Name: TCON0_BASIC3_REG

Bit

R/W

Default/Hex

Description

31:26

/

/

/

25:16

R/W

0

HSPW
Thspw = (HSPW+1) * Tdclk
Note: HT> (HSPW+1)

15:10

/

/

/

9:0

R/W

0

VSPW
Tvspw = (VSPW+1) * Thsync
Note: VT/2 > (VSPW+1)

6.2.5.14. TCON0 HV Panel Interface Register (Default Value: 0x00000000)
Offset: 0x058

Register Name: TCON0_HV_IF_REG

Bit

R/W

Default/Hex

Description

31:28

R/W

0

HV_Mode0000: 24bit/1cycle parallel mode
1000: 8bit/3cycle RGB serial mode(RGB888)
1010: 8bit/4cycle Dummy RGB(DRGB)
1011: 8bit/4cycle RGB Dummy(RGBD)
1100: 8bit/2cycle YUV serial mode(CCIR656)

27:26

R/W

0

RGB888_SM0
serial RGB888 mode Output sequence at odd lines of the panel (line 1, 3,
5, 7…)
00: R→G→B
01: B→R→G
10: G→B→R
11: R→G→B

25:24

R/W

0

RGB888_SM1
serial RGB888 mode Output sequence at even lines of the panel (line 2, 4,
6, 8…)
00: R→G→B
01: B→R→G
10: G→B→R
11: R→G→B

23:22

R/W

0

YUV_SM
serial YUV mode Output sequence 2-pixel-pair of every scan line

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00: YUYV
01: YVYU
10: UYVY
11: VYUY
21:20

R/W

0

YUV EAV/SAV F line delay
0:F toggle right after active video line
1:delay 2 line(CCIR PAL)
2:delay 3 line(CCIR NTSC)
3:reserved

19

R/W

0

CCIR_CSC_Dis
0: enable
1: disable
Only valid when HV mode is “1100”,
select ‘0’ TCON convert source from RGB to YUV

18:0

/

/

/

6.2.5.15. TCON0 CPU Panel Interface Register (Default Value: 0x00000000)
Offset: 0x060

Register Name: TCON0_CPU_IF_REG

Bit

R/W

Default/Hex

Description

31:28

R/W

0

CPU_Mode
0000: 18bit/256K mode
0010: 16bit mode0
0100: 16bit mode1
0110: 16bit mode2
1000: 16bit mode3
1010: 9bit mode
1100: 8bit 256K mode
1110: 8bit 65K modexxx1: 24bit for DSI

27

/

/

/

26

R/W

0

DA
pin A1 value in 8080 mode auto/flash states

25

R/W

0

CA
pin A1 value in 8080 mode WR/RD execute

24

/

/

/

23

R

0

Wr_Flag
0:write operation is finishing
1:write operation is pending

22

R

0

Rd_Flag
0:read operation is finishing
1:read operation is pending

21:18

/

/

/

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17

R/W

0

AUTO
auto Transfer Mode:
If it’s 1, all the valid data during this frame are write to panel.
Note: This bit is sampled by Vsync

16

R/W

0

FLUSH
direct transfer mode:
If it’s enabled, FIFO1 is regardless of the HV timing, pixels data keep
being transferred unless the input FIFO was empty.
Data output rate control by DCLK.

15:6

/

/

/

5:4

R/W

0

/

3

R/W

0

Trigger_FIFO_Bist_En
0: disable
1: enable
Entry addr is 0xFF8

2

R/W

0

Trigger_FIFO_En
0:enable
1:disable

1

R/W

0

Trigger_Start
write ‘1’ to start a frame flush, write’0’ has no effect.
this flag indicated frame flush is runningsofeware must make sure write ‘1’ only when this flag is ‘0’.

0

R/W

0

Trigger_En
0: trigger mode disable
1: trigger mode enable

6.2.5.16. TCON0 CPU Panel Write Data Register (Default Value: 0x00000000)
Offset: 0x064

Register Name: TCON0_CPU_WR_REG

Bit

R/W

Default/Hex

Description

31:24

/

/

/

23:0

W

0

Data_Wr
data write on 8080 bus, launch a write operation on 8080 bus

6.2.5.17. TCON0 CPU Panel Read Data 0 Register (Default Value: 0x00000000)
Offset: 0x068

Register Name: TCON0_CPU_RD0_REG

Bit

R/W

Default/Hex

Description

31:24

/

/

/

23:0

R

/

Data_Rd0
data read on 8080 bus, launch a new read operation on 8080 bus

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Display

6.2.5.18. TCON0 CPU Panel Read Data 1 Register (Default Value: 0x00000000)
Offset: 0x06C

Register Name: TCON0_CPU_RD1_REG

Bit

R/W

Default/Hex

Description

31:24

/

/

/

23:0

R

/

Data_Rd1
data read on 8080 bus, without a new read operation on 8080 bus

6.2.5.19. TCON0 LVDS Panel Interface Register (Default Value: 0x00000000)
Offset: 0x084

Register Name: TCON0_LVDS_IF_REG

Bit

R/W

Default/Hex

Description

31

R/W

0

TCON0_LVDS_En
0: disable
1: enable

30

/

/

/

29

R/W

0

TCON0_LVDS_Even_Odd_Dir
0: normal
1: reverse

28

R/W

0

TCON0_LVDS_Dir
1: normal
2: reverse
NOTE: LVDS direction

27

R/W

0

TCON0_LVDS_Mode
0: NS mode
1: JEIDA mode

26

R/W

0

TCON0_LVDS_BitWidth
0: 24bit
1: 18bit

25

R/W

0

TCON0_LVDS_DeBug_En
0: disable
1: enable

24

R/W

0

TCON0_LVDS_DeBug_Mode
0: mode0 RANDOM DATA
1: mode1 output CLK period=7/2 LVDS CLK period

23

R/W

0

TCON0_LVDS_Correct_Mode
0: mode0
1: mode1

22:21

/

/

/

20

R/W

0

TCON0_LVDS_Clk_Sel

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Display
0: MIPI PLL
1: TCON0 CLK
19:5

/

/

/

4

R/W

0

TCON0_LVDS_CLK_Polarity
0: reverse
1: normal

3:0

R/W

0

TCON0_LVDS_Data_Polarity
0: reverse
1: normal

6.2.5.20. TCON0 IO Polarity Register (Default Value: 0x00000000)
Offset: 0x088

Register Name: TCON0_IO_POL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0

IO_Output_Sel
0: normal output
1: register output
when set as ‘1’, d[23:0], io0, io1,io3 sync to dclk

30:28

R/W

0

DCLK_Sel
000: used DCLK0(normal phase offset)
001: used DCLK1(1/3 phase offset)
010: used DCLK2(2/3 phase offset)
101: DCLK0/2 phase 0100: DCLK0/2 phase 90
reserved

27

R/W

0

IO3_Inv
0: not invert
1: invert

26

R/W

0

IO2_ Inv
0: not invert
1: invert

25

R/W

0

IO1_Inv
0: not invert
1: invert

24

R/W

0

IO0_Inv
0: not invert
1: invert

23:0

R/W

0

Data_Inv
TCON0 output port D[23:0] polarity control, with independent bit
control:
0s: normal polarity
1s: invert the specify output

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6.2.5.21. TCON0 IO Trigger Register (Default Value: 0x0FFFFFFF)
Offset: 0x08C

Register Name: TCON0_IO_TRI_REG

Bit

R/W

Default/Hex

Description

31:29

/

/

/

28

/

/

RGB_Endian
0: normal
1: bits_invert

27

R/W

1

IO3_Output_Tri_En
1: disable
0: enable

26

R/W

1

IO2_Output_Tri_En
1: disable
0: enable

25

R/W

1

IO1_Output_Tri_En
1: disable
0: enable

24

R/W

1

IO0_Output_Tri_En
1: disable
0: enable

23:0

R/W

0xFFFFFF

Data_Output_Tri_En
TCON0 output port D[23:0] output enable, with independent bit control:
1s: disable
0s: enable

6.2.5.22. TCON CEU Control Register (Default Value: 0x00000000)
Offset: 0x100

Register Name: TCON_CEU_CTL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0

CEU_en0: bypass
1: enable

30:0

/

/

/

6.2.5.23. TCON CEU Coefficient Mul Register (Default Value: 0x00000000)
Offset: 0x110+N*0x04(N=0,1,2,4,5,6,8,9,10)

Register Name: TCON_CEU_COEF_MUL_REG

Bit

R/W

Default/Hex

Description

31:13

/

/

/

12:0

R/W

0

CEU_Coef_Mul_Value

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Displaysigned 13bit value, range of (-16,16)
N=0: Rr
N=1: Rg
N=2: Rb
N=4: Gr
N=5: Gg
N=6: Gb
N=8: Br
N=9: Bg
N=10: Bb

6.2.5.24. TCON CEU Coefficient Add Register (Default Value: 0x00000000)
Offset: 0x11C+N*0x10(N=0,1,2)

Register Name: TCON_CEU_COEF_ADD_REG

Bit

R/W

Default/Hex

Description

31:19

/

/

/

18:0

R/W

0

CEU_Coef_Add_Valuesigned 19bit value, range of (-16384, 16384)
N=0: Rc
N=1: Gc
N=2: Bc

6.2.5.25. TCON CEU Coefficient Range Register (Default Value: 0x00000000)
Offset: 0x140+N*0x04(N=0,1,2)

Register Name: TCON_CEU_COEF_RANGE_REG

Bit

R/W

Default/Hex

Description

31:24

/

/

/

23:16

R/W

0

CEU_Coef _Range_Min
unsigned 8bit value, range of [0,255]

15:8

/

/

/

7:0

R/W

0

CEU Coef _Range_Max
unsigned 8bit value, range of [0,255]

6.2.5.26. TCON0 CPU Panel Trigger0 Register (Default Value: 0x00000000)
Offset: 0x160

Register Name: TCON0_CPU_TRI0_REG

Bit

R/W

Default/Hex

Description

31:28

/

/

/

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Display
27:16

R/W

0

Block_Space
should be set >20*pixel_cycle

15:12

/

/

/

11:0

R/W

0

Block_Size

6.2.5.27. TCON0 CPU Panel Trigger1 Register (Default Value: 0x00000000)
Offset: 0x164

Register Name: TCON0_CPU_TRI1_REG

Bit

R/W

Default/Hex

Description

31:16

R

0

Block_Current_Num

15:0

R/W

0

Block_Num

6.2.5.28. TCON0 CPU Panel Trigger2 Register (Default Value: 0x00000000)
Offset: 0x168

Register Name: TCON0_CPU_TRI2_REG

Bit

R/W

Default/Hex

Description

31:16

R/W

0x20

Start_Delay
Tdly = (Start_Delay +1) * be_clk*8

15

R/W

0

Trans_Start_Mode
0: ecc_fifo+tri_fifo
1: tri_fifo

14:13

R/W

0

Sync_Mode
0x: auto
10: 0
11: 1

12:0

R/W

0

Trans_Start_Set

6.2.5.29. TCON0 CPU Panel Trigger3 Register (Default Value: 0x00000000)
Offset: 0x16C

Register Name: TCON0_CPU_TRI3_REG

Bit

R/W

Default/Hex

Description

31:30

/

/

/

29:28

R/W

0

Tri_Int_Mode
00: disable
01: counter mode
10: te rising mode
11: te falling mode
when set as 01, Tri_Counter_Int occur in cycle of (Count_N+1)×(Count_M+1)×4 dclk.
when set as 10 or 11, io0 is map as TE input.

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Display
27:24

/

/

/

23:8

R/W

0

Counter_N

7:0

R/W

0

Counter_M

6.2.5.30. TCON0 CPU Panel Trigger4 Register (Default Value: 0x00000000)
Offset: 0x170

Register Name: TCON0_CPU_TRI4_REG

Bit

R/W

Default/Hex

Description

31:29

/

/

/

28

R/W

0

Plug_Mode_En
0: disable
1:enable

27:25

/

/

/

24

R/W

0

A1
Valid in first Block

23:0

R/W

0

D23-D0
Valid in first Block

6.2.5.31. TCON0 CPU Panel Trigger5 Register (Default Value: 0x00000000)
Offset: 0x174

Register Name: TCON0_CPU_TRI5_REG

Bit

R/W

Default/Hex

Description

31:25

/

/

/

24

R/W

0

A1
Valid in Block except first

23:0

R/W

0

D23-D0
Valid in Block except first

6.2.5.32. TCON Color Map Control Register (Default Value: 0x00000000)
Offset: 0x180

Register Name: TCON0_CMAP_CTL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0

Color_Map_En
0: bypass
1: enable
This module only work when X is divided by 4

30:1

/

/

/

0

R/W

0

Out_Format
0: 4 pixel output mode: Out0 -> Out1 -> Out2 -> Out3
1: 2 pixel output mode: Out0 -> Out1

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Display

6.2.5.33. TCON Color Map Odd Line0 Register (Default Value: 0x00000000)
Offset: 0x190

Register Name: TCON0_CMAP_ODD0_REG

Bit

R/W

Default/Hex

Description

31:16

R/W

0

Out_Odd1

15:0

R/W

0

Out_Odd0
bit15-12: Reservd
bit11-08: Out_Odd0[23:16]
bit07-04: Out_Odd0[15:8]
bit03-00: Out_Odd0[7:0]0x0: in_b0
0x1: in_g0
0x2: in_r0
0x3: reservd
0x4: in_b1
0x5: in_g1
0x6: in_r1
0x7: reservd
0x8: in_b2
0x9: in_g2
0xa: in_r2
0xb: reservd
0xc: in_b3
0xd: in_g3
0xe: in_r3
0xf: reservd

6.2.5.34. TCON Color Map Odd Line1 Register (Default Value: 0x00000000)
Offset: 0x194

Register Name: TCON0_CMAP_ODD1_REG

Bit

R/W

Default/Hex

Description

31:16

R/W

0

Out_Odd3

15:0

R/W

0

Out_Odd2

6.2.5.35. TCON Color Map Even0 Register (Default Value: 0x00000000)
Offset: 0x198

Register Name: TCON0_CMAP_EVEN0_REG

Bit

R/W

Default/Hex

Description

31:16

R/W

0

Out_Even1

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Display
15:0

R/W

0

Out_Even0

6.2.5.36. TCON Color Map Even1 Register (Default Value: 0x00000000)
Offset: 0x19C

Register Name: TCON_CMAP_EVEN1_REG

Bit

R/W

Default/Hex

Description

31:16

R/W

0

Out_Even3

15:0

R/W

0

Out_Even2

6.2.5.37. TCON Safe Period Register (Default Value: 0x00000000)
Offset: 0x1F0

Register Name: TCON_SAFE_PERIOD_REG

Bit

R/W

Default/Hex

Description

31:29

/

/

/

28:16

R/W

0

Safe_Period_FIFO_Num

15:4

R/W

0

Safe_Period_Line

3

/

/

/

2:0

R/W

0

Safe_Period_Mode
0: unsafe
1: safe
2: safe at ecc_fifo_curr_num > safe_period_fifo_num
3: safe at 2 and safe at sync active
4: safe at line

6.2.5.38. TCON0 LVDS ANA0 Register (Default Value: 0x00000000)
Offset: 0x220

Register Name: TCON0_LVDS_ANA0_REG

Bit

R/W

Default/Hex

Description

31

R/W

0

lvds0_en_mb
enable the bias circuit of the LVDS_Ana module

30

R/W

0

lvds0_en_ldo

29:25

/

/

/

24

R/W

0

lvds0_en_drvc
enable all circuits working when transmitting the data in channel clock of
LVDS_tx0

23:20

R/W

0

lvds0_en_drv
enable all circuits working when transmitting the data in channel<3:0> of
LVDS_tx0

19

R/W

0

Lvds0_reg_dram_test
0:dram test clk disable

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Display
1:dram test clk enable
18:17

R/W

0

lvds0_reg_c
adjust current flowing through Rload of Rx to change the differential
signals amplitude
0:250mV
1:300mV
2:350mV
3:400mV

16

R/W

0

lvds0_reg_denc
choose data output or PLL test clock output in LVDS_tx

15:12

R/W

0

lvds0_reg_denchoose data output or PLL test clock output in LVDS_tx

11:10

/

/

/

9:8

R/W

0

lvds0_reg_v
adjust common mode voltage of the differential signals in five channels
single signal high level:
0:1.1V
1:1.19V
2:1.3V
3:1.43V

7:6

/

/

/

5:4

R/W

0

lvds0_reg_pd
fine adjust the slew rate of output data

3:2

/

/

/

1

R/W

0

lvds0_reg_pwslv
adjust voltage amplitude of low power in LVDS_Ana

0

R/W

0

lvds0_reg_pwsmb
adjust voltage amplitude of mbias voltage reference in LVDS_Ana

6.2.6. TCON1 Module Register List
Module Name

Base Address

TCON1

0x01C0D000

Register Name

OffsetDescription

TCON_GCTL_REG

0x000

TCON global control register

TCON_GINT0_REG

0x004

TCON global interrupt register0

TCON_GINT1_REG

0x008

TCON global interrupt register1

TCON1_CTL_REG

0x090

TCON1 control register

TCON1_BASIC0_REG

0x094

TCON1 basic timing register0

TCON1_BASIC1_REG

0x098

TCON1 basic timing register1

TCON1_BASIC2_REG

0x09C

TCON1 basic timing register2

TCON1_BASIC3_REG

0x0A0

TCON1 basic timing register3

TCON1_BASIC4_REG

0x0A4

TCON1 basic timing register4

TCON1_BASIC5_REG

0x0A8

TCON1 basic timing register5

TCON1_PS_SYNC_REG

0x0B0

TCON1 sync register

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Display
TCON1_IO_POL_REG

0x0F0

TCON1 IO polarity register

TCON1_IO_TRI_REG

0x0F4

TCON1 IO trigger register

TCON_CEU_CTL_REG

0x100

TCON CEU control register

TCON_CEU_COEF_MUL_REG

0x110+N*0x04

TCON CEU coefficient register0(N=0,1,2,4,5,6,8,9,10)

TCON_CEU_COEF_ADD_REG

0x11C+N*0x10

TCON CEU coefficient register1(N=0,1,2)

TCON_CEU_COEF_RANG_REG

0x140+N*0x04

TCON CEU coefficient register2(N=0,1,2)

TCON_SAFE_PERIOD_REG

0x1F0

TCON safe period register

TCON1_FILL_CTL_REG

0x300

TCON1 fill data control register

TCON1_FILL_BEGIN_REG

0x304+N*0x0C

TCON1 fill data begin register(N=0,1,2)

TCON1_FILL_END_REG

0x308+N*0x0C

TCON1 fill data end register(N=0,1,2)

TCON1_FILL_DATA0_REG

0x30C+N*0x0C

TCON1 fill data value register(N=0,1,2)

TCON1_GAMMA_TABLE_REG

0x400-0x7FF

TCON_ECC_FIFO_BIST_REG

0xFFC

6.2.7. TCON1 Module Register Description
6.2.7.1. TCON Global Control Register (Default Value: 0x00000000)
Offset: 0x0000

Register Name: TCON_GCTL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0

TCON_En
0: disable
1: enable
When it’s disabled, the module will be reset to idle state.

30

R/W

0

TCON_Gamma_En
0: disable
1: enable

29:0

/

/

/

6.2.7.2. TCON Global Interrupt Register0 (Default Value: 0x00000000)
Offset: 0x0004
Bit

R/W

Register Name: TCON_GINT0_REG
Default/Hex

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Display
31

/

/

/

30

R/W

0

TCON1_Vb_Int_En
0: disable
1: enable

29

/

/

/

28

R/W

0

TCON1_Line_Int_En
0: disable
1: enable

27:15

/

/

/

14

R/W

0

TCON1_Vb_Int_Flag
Asserted during vertical no-display period every frame.
Write 0 to clear it.

13

/

/

/

12

R/W

0

TCON1_Line_Int_Flag
trigger when SY1 match the current TCON1 scan line
Write 0 to clear it.

11:0

/

0

/

6.2.7.3. TCON Global Interrupt Register1 (Default Value: 0x00000000)
Offset: 0x0008

Register Name: TCON_GINT1_REG

Bit

R/W

Default/Hex

Description

31:12

/

/

/

11:0

R/W

0

TCON1_Line_Int_Num
scan line for TCON1 line trigger(including inactive lines)
Setting it for the specified line for trigger 1.
Note: SY1 is writable only when LINE_TRG1 disable.

6.2.7.4. TCON1 Control Register (Default Value: 0x00000000)
Offset: 0x0090

Register Name: TCON1_CTL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0

TCON1_En
0: disable
1: enable

30:9

/

/

/

8:4

R/W

0

Start_Delay
This is for DE1 and DE2

3:2

/

/

/

1

R/W

0

TCON1_Src_Sel
00: reserved

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Display
01: BLUE data(FIFO2 disable,RGB = 0000FF)
0

/

/

/

6.2.7.5. TCON1 Basic Timing 0 Register (Default Value: 0x00000000)
Offset: 0x0094

Register Name: TCON1_BASIC0_REG

Bit

R/W

Default/Hex

Description

31:28

/

/

/

27:16

R/W

0

TCON1_XI
source width is X+1

15:12

/

/

/

11:0

R/W

0

TCON1_YI
source height is Y+1

6.2.7.6. TCON1 Basic Timing 1 Register (Default Value: 0x00000000)
Offset: 0x0098

Register Name: TCON1_BASIC1_REG

Bit

R/W

Default/Hex

Description

31:28

/

/

/

27:16

R/W

0

LS_XO
width is LS_XO+1

15:12

/

/

/

11:0

R/W

0

LS_YO
width is LS_YO+1
NOTE: this version LS_YO =TCON1_YI

6.2.7.7. TCON1 Basic Timing 2 Register (Default Value: 0x00000000)
Offset: 0x009C

Register Name: TCON1_BASIC2_REG

Bit

R/W

Default/Hex

Description

31:28

/

/

/

27:16

R/W

0

TCON1_XO
width is TCON1_XO+1

15:12

/

/

/

11:0

R/W

0

TCON1_YOheight is TCON1_YO+1

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Display
6.2.7.8. TCON1 Basic Timing 3 Register (Default Value: 0x00000000)
Offset: 0x00A0

Register Name: TCON1_BASIC3_REG

Bit

R/W

Default/Hex

Description

31:29

/

/

/

28:16

R/W

0

HT
horizontal total time
Thcycle = (HT+1) * Thdclk

15:12

/

/

/

11:0

R/W

0

HBP
horizontal back porch
Thbp = (HBP +1) * Thdclk

6.2.7.9. TCON1 Basic Timing Register (Default Value: 0x00000000)
Offset: 0x00A4

Register Name: TCON1_BASIC4_REG

Bit

R/W

Default/Hex

Description

31:29

/

/

/

28:16

R/W

0

VT
horizontal total time (in HD line)
Tvt = VT/2 * Th

15:12

/

/

/

11:0

R/W

0

VBP
horizontal back porch (in HD line)
Tvbp = (VBP +1) * Th

6.2.7.10. TCON1 Basic Timing 5 Register (Default Value: 0x00000000)
Offset: 0x00A8

Register Name: TCON1_BASIC5_REG

Bit

R/W

Default/Hex

Description

31:29

/

/

/

25:16

R/W

0

HSPW
horizontal Sync Pulse Width (in dclk)
Thspw = (HSPW+1) * Tdclk
Note: HT> (HSPW+1)

15:10

/

/

/

9:0

R/W

0

VSPW
vertical Sync Pulse Width (in lines)
Tvspw = (VSPW+1) * Th
Note: VT/2 > (VSPW+1)

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Display
6.2.7.11. TCON1 PS SYNC Register (Default Value: 0x00000000)
Offset: 0x00B0

Register Name: TCON1_PS_SYNC_REG

Bit

R/W

Default/Hex

Description

31:16

R/W

0

SYNC_X

15:0

R/W

0

SYNC_Y

6.2.7.12. TCON1 IO Polarity Register (Default Value: 0x00000000)
Offset: 0x00F0

Register Name: TCON1_IO_POL_REG

Bit

R/W

Default/Hex

Description

31:28

/

/

/

27

R/W

0

IO3_Inv
0: not invert
1: invert

26

R/W

0

IO2 Inv
0: not invert
1: invert

25

R/W

0

IO1_Inv
0: not invert
1: invert

24

R/W

0

IO0_Inv
0: not invert
1: invert

23:0

R/W

0

Data_Inv
TCON1 output port D[23:0] polarity control, with independent bit
control:
0s: normal polarity
1s: invert the specify output

6.2.7.13. TCON1 IO Polarity Register (Default Value: 0x0FFFFFFF)
Offset: 0x00F4

Register Name: TCON1_IO_POL_REG

Bit

R/W

Default/Hex

Description

31:28

/

/

/

27

R/W

1

IO3_Output_Tri_En
1: disable
0: enable

26

R/W

1

IO2_Output_Tri_En
1: disable
0: enable

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25

R/W

1

IO1_Output_Tri_En
1: disable
0: enable

24

R/W

1

IO0_Output_Tri_En
1: disable
0: enable

23:0

R/W

0xFFFFFF

Data_Output_Tri_En
TCON1 output port D[23:0] output enable, with independent bit control:
1s: disable
0s: enable

6.2.7.14. TCON CEU Control Register (Default Value: 0x00000000)
Offset: 0x0100

Register Name: TCON_CEU_CTL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0

CEU_en0: bypass
1: enable

30:0

/

/

/

6.2.7.15. TCON CEU Coefficient Mul Register (Default Value: 0x00000000)
Offset: 0x0110+N*0x04(N=0,1,2,4,5,6,8,9,10)

Register Name: TCON_CEU_COEF_MUL_REG

Bit

R/W

Default/Hex

Description

31:13

/

/

/

12:0

R/W

0

CEU_Coef_Mul_Valuesigned 13bit value, range of (-16,16)
N=0: Rr
N=1: Rg
N=2: Rb
N=4: Gr
N=5: Gg
N=6: Gb
N=8: Br
N=9: Bg
N=10: Bb

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6.2.7.16. TCON CEU Coefficient Add Register (Default Value: 0x00000000)
Offset: 0x011C+N*0x10(N=0,1,2)

Register Name: TCON_CEU_COEF_ADD_REG

Bit

R/W

Default/Hex

Description

31:19

/

/

/

18:0

R/W

0

CEU_Coef_Add_Valuesigned 19bit value, range of (-16384, 16384)
N=0: Rc
N=1: Gc
N=2: Bc

6.2.7.17. TCON CEU Coefficient Rang Register (Default Value: 0x00000000)
Offset: 0x0140+N*0x4(N=0,1,2)

Register Name: TCON_CEU_COEF_RANG_REG

Bit

R/W

Default/Hex

Description

31:24

/

/

/

23:16

R/W

0

CEU_Coef _Range_Min
unsigned 8bit value, range of [0,255]

15:8

/

/

/

7:0

R/W

0

CEU Coef _Range_Max
unsigned 8bit value, range of [0,255]

6.2.7.18. TCON Safe Period Register (Default Value: 0x00000000)
Offset: 0x01F0

Register Name: TCON_SAFE_PERIOD_REG

Bit

R/W

Default/Hex

Description

31:29

/

/

/

28:16

R/W

0

Safe_Period_FIFO_Num

15:4

R/W

0

Safe_Period_Line

3

/

/

/

2:0

R/W

0

Safe_Period_Mode
0: unsafe
1: safe
2: safe at ecc_fifo_curr_num > safe_period_fifo_num
3: safe at 2 and safe at sync active
4: safe at line

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6.2.7.19. TCON1 Fill Control Register (Default Value: 0x00000000)
Offset: 0x0300

Register Name: TCON1_FILL_CTL_REG

Bit

R/W

Default/Hex

Description

31

R/W

0

TCON1_Fill_En
0: bypass
1: enable

30:0

/

/

/

6.2.7.20. TCON1 Fill Begin Register (Default Value: 0x00000000)
Offset: 0x0304+N*0x0C(N=0,1,2)

Register Name: TCON1_FILL_BEGIN_REG

Bit

R/W

Default/Hex

Description

31:24

/

/

/

23:0

R/W

0

Fill_Begin6.2.7.21. TCON1 Fill End Register (Default Value: 0x00000000)
Offset: 0x0308+N*0x0C(N=0,1,2)

Register Name: TCON1_FILL_END_REG

Bit

R/W

Default/Hex

Description

31:24

/

/

/

23:0

R/W

0

Fill_End

6.2.7.22. TCON1 Fill Data Register (Default Value: 0x00000000)
Offset: 0x030C+N*0x0C(N=0,1,2)

Register Name: TCON1_FILL_DATA_REG

Bit

R/W

Default/Hex

Description

31:24

/

/

/

23:0

R/W

0

Fill_Value

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Chapter 7 Interfaces
This chapter describes the A64 interfaces, including:











TWI
SPI
UART
CIR ReceiverUSB
I2S/PCM
OWA
SCR
EMAC
TSC

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7.1. TWI
7.1.1. Overview
This TWI Controller is designed to be used as an interface between CPU host and the serial TWI bus. It can
support all the standard TWI transfer, including Slave and Master. The communication to the TWI bus is carriedout on a byte-wise basis using interrupt or polled handshaking. This TWI Controller can be operated instandard mode (100K bps) or fast-mode, supporting data rate up to 400K bps. Multiple Masters and 10-bit
addressing Mode are supported for this specified application. General Call Addressing is also supported in Slavemode.
The TWI Controller includes the following features:Software-programmable for Slave or MasterSupport Repeated START signal
Multi-master systems supported
Allow 10-bit addressing with TWI bus
Performs arbitration and clock synchronization
Own address and General Call address detectionInterrupt on address detectionSupport speeds up to 400Kbits/s (‘fast mode’)Allow operation from a wide range of input clock frequencies

7.1.2. Timing Diagram
Data transferred are always in a unit of 8-bit (byte), followed by an acknowledge bit. The number of bytes thatcan be transmitted per transfer is unrestricted. Data is transferred in serial with the MSB first. Between eachbyte of data transfer, a receiver device will hold the clock line SCL low to force the transmitter into a wait state
while waiting the response from microprocessor.
Data transfer with acknowledge is obligatory. The clock line is driven by the master all the time, including theacknowledge-related clock cycle, except for the SCL holding between each bytes. After sending each byte, thetransmitter releases the SDA line to allow the receiver to pull down the SDA line and send an acknowledge
signal (or leave it high to send a "not acknowledge") to the transmitter.
When a slave receiver doesn't acknowledge the slave address (unable to receive because of no resource
available), the data line must be left high by the slave so that the master can then generate a STOP condition toabort the transfer. Slave receiver can also indicate not to want to send more data during a transfer by leave theacknowledge signal high. And the master should generate the STOP condition to abort the transfer.
Below diagram provides an illustration the relation of SDA signal line and SCL signal line on the TWI serial bus.

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SDA
IIC1

IIC3

IIC4

IIC5

IIC2

SCL

Figure 7-1. TWI Timing Diagram

7.1.3. TWI Controller Special Requirement
7.1.3.1. TWI Pin List
Port Name

Width

Direction

Description

TWI_SCL1

IN/OUT

TWI Clock line

TWI_SDA1

IN/OUTTWI Serial Data line

7.1.3.2. TWI Controller Operation
There are four operation modes on the TWI bus which dictates the communications method. They are MasterTransmit, Master Receive, Slave Transmit and Slave Receive. In general, CPU host controls TWI by writing
commands and data to its registers. The TWI interrupts the CPU host for the attention each time a byte
transfer is done or a START/STOP conditions is detected. The CPU host can also poll the status register for
current status if the interrupt mechanism is not disabled by the CPU host.
When the CPU host wants to start a bus transfer, it initiates a bus START to enter the master mode by setting
IM_STA bit in the 2WIRE_CNTR register to high (before it must be low). The TWI will assert INT line and
INT_FLAG to indicate a completion for the START condition and each consequent byte transfer. At eachinterrupt, the micro-processor needs to check the 2WIRE_STAT register for current status. A transfer has to beconcluded with STOP condition by setting M_STP bit high.
In Slave Mode, the TWI also constantly samples the bus and look for its own slave address during addressing
cycles. Once a match is found, it is addressed and interruptted the CPU host with the corresponding status.
Upon request, the CPU host should read the status, read/write 2WIRE_DATA data register, and set the
2WIRE_CNTR control register. After each byte transfer, a slave device always halt the operation of remotemaster by holding the next low pulse on SCL line until the microprocessor responds to the status of previous
byte transfer or START condition.

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7.1.4. TWI Controller Register List
Module Name

Base Address

R_TWI

0x01F02400

TWI0

0x01C2AC00

TWI1

0x01C2B000

TWI20x01C2B400

Register Name

OffsetDescription

TWI_ADDR

0x0000TWI Slave address

TWI_XADDR

0x0004TWI Extended slave address

TWI_DATA

0x0008

TWI Data byte

TWI_CNTR

0x000CTWI Control register

TWI_STAT

0x0010TWI Status register

TWI_CCR

0x0014

TWI Clock control register

TWI_SRST

0x0018TWI Software reset

TWI_EFR

0x001CTWI Enhance Feature register

TWI_LCR

0x0020

TWI Line Control register

7.1.5. TWI Controller Register Description
7.1.5.1. TWI Slave Address Register(Default Value: 0x00000000)
Offset: 0x00

Register Name: TWI_ADDR

Bit

R/W

Default/Hex

Description

31:8

/

/

/

7:1

0

R/W

R/W

0

0

SLA
Slave address
7-bit addressing
SLA6, SLA5, SLA4, SLA3, SLA2, SLA1, SLA010-bit addressing
1, 1, 1, 1, 0, SLAX[9:8]
GCE
General call address enable
0: Disable
1: Enable

Notes:For 7-bit addressing:
SLA6 – SLA0 is the 7-bit address of the TWI when in slave mode. When the TWI receives this address after a
START condition, it will generate an interrupt and enter slave mode. (SLA6 corresponds to the first bit received
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from the TWI bus.) If GCE is set to ‘1’, the TWI will also recognize the general call address (00h).
For 10-bit addressing:
When the address received starts with 11110b, the TWI recognizes this as the first part of a 10-bit address and if
the next two bits match ADDR[2:1] (i.e. SLAX9 and SLAX8 of the device’s extended address), it sends an ACK.
(The device does not generate an interrupt at this point.) If the next byte of the address matches the XADDR
register (SLAX7 – SLAX0), the TWI generates an interrupt and goes into slave mode.

7.1.5.2. TWI Extend Address Register(Default Value: 0x00000000)
Offset: 0x04

Register Name: TWI_XADDR

Bit

R/W

Default/Hex

Description

31:8

/

/

/

7:0

R/W

0

SLAX
Extend Slave Address
SLAX[7:0]

7.1.5.3. TWI Data Register(Default Value: 0x00000000)
Offset: 0x08

Register Name: TWI_DATA

Bit

R/W

Default/Hex

Description

31:8

/

/

/

7:0

R/W

0

TWI_DATA
Data byte for transmitting or received

7.1.5.4. TWI Control Register(Default Value: 0x00000000)
Offset: 0x0C

Register Name: TWI_ CNTR

Bit

R/W

Default/Hex

Description

31:8

/

/

/

7

6

R/W

R/W

0

0

A64 User Manual(Revision 1.0)

INT_ENInterrupt Enable
1’b0: The interrupt line always low
1’b1: The interrupt line will go high when INT_FLAG is set.
BUS_EN
TWI Bus Enable
1’b0: The TWI bus inputs ISDA/ISCL are ignored and the TWI Controller
will not respond to any address on the bus
1’b1: The TWI will respond to calls to its slave address – and to the

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general call address if the GCE bit in the ADDR register is set.
Notes: In master operation mode, this bit should be set to ‘1’

5

4

3

2

R/W

R/W

R/W

R/W

0

0

0

0

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M_STA
Master Mode Start
When M_STA is set to ‘1’, TWI Controller enters master mode and willtransmit a START condition on the bus when the bus is free. If the M_STA
bit is set to ‘1’ when the TWI Controller is already in master mode andone or more bytes have been transmitted, then a repeated START
condition will be sent. If the M_STA bit is set to ‘1’ when the TWI is being
accessed in slave mode, the TWI will complete the data transfer in slave
mode then enter master mode when the bus has been released.
The M_STA bit is cleared automatically after a START condition has beensent,writing a ‘0’ to this bit has no effect.
M_STP
Master Mode Stop
If M_STP is set to ‘1’ in master mode, a STOP condition is transmitted on
the TWI bus. If the M_STP bit is set to ‘1’ in slave mode, the TWI will
behave as if a STOP condition has been received, but no STOP condition
will be transmitted on the TWI bus. If both M_STA and M_STP bits areset, the TWI will first transmit the STOP condition (if in master mode)
then transmit the START condition.
The M_STP bit is cleared automatically,writing a ‘0’ to this bit has noeffect.
INT_FLAG
Interrupt Flag
INT_FLAG is automatically set to ‘1’ when any of 28 (out of the possible29) states is entered (see ‘STAT Register’ below). The only state that does
not set INT_FLAG is state F8h. If the INT_EN bit is set, the interrupt line
goes high when IFLG is set to ‘1’. If the TWI is operating in slave mode,
data transfer is suspended when INT_FLAG is set and the low period of
the TWI bus clock line (SCL) is stretched until ‘1’ is written to INT_FLAG.
The TWI clock line is then released and the interrupt line goes low.
A_ACKAssert Acknowledge
When A_ACK is set to ‘1’, an Acknowledge (low level on SDA) will be sent
during the acknowledge clock pulse on the TWI bus if:
1. Either the whole of a matching 7-bit slave address or the first or thesecond byte of a matching 10-bit slave address has been received.
2. The general call address has been received and the GCE bit in the ADDR
register is set to ‘1’.
3. A data byte has been received in master or slave mode.
When A_ACK is ‘0’, a Not Acknowledge (high level on SDA) will be sent
when a data byte is received in master or slave mode.
If A_ACK is cleared to ‘0’ in slave transmitter mode, the byte in the DATA

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register is assumed to be the ‘last byte’. After this byte has beentransmitted, the TWI will enter state C8h then return to the idle state(status code F8h) when INT_FLAG is cleared.
The TWI will not respond as a slave unless A_ACK is set.
1:0

R/W

0

/

7.1.5.5. TWI Status Register(Default Value: 0x000000F8)
Offset: 0x10

Register Name: TWI_STAT

Bit

R/W

Default/Hex

Description

31:8

/

/

/

7:0

R

0xF8

A64 User Manual(Revision 1.0)

STA
Status Information Byte
Code Status
0x00: Bus error
0x08: START condition transmitted
0x10: Repeated START condition transmitted
0x18: Address + Write bit transmitted, ACK received
0x20: Address + Write bit transmitted, ACK not received
0x28: Data byte transmitted in master mode, ACK received
0x30: Data byte transmitted in master mode, ACK not received
0x38: Arbitration lost in address or data byte
0x40: Address + Read bit transmitted, ACK received
0x48: Address + Read bit transmitted, ACK not received
0x50: Data byte received in master mode, ACK transmitted
0x58: Data byte received in master mode, not ACK transmitted
0x60: Slave address + Write bit received, ACK transmitted
0x68: Arbitration lost in address as master, slave address + Write bit
received, ACK transmitted
0x70: General Call address received, ACK transmitted
0x78: Arbitration lost in address as master, General Call address received,
ACK transmitted
0x80: Data byte received after slave address received, ACK transmitted
0x88: Data byte received after slave address received, not ACK
transmitted
0x90: Data byte received after General Call received, ACK transmitted
0x98: Data byte received after General Call received, not ACK transmitted
0xA0: STOP or repeated START condition received in slave mode
0xA8: Slave address + Read bit received, ACK transmitted
0xB0: Arbitration lost in address as master, slave address + Read bit
received, ACK transmitted
0xB8: Data byte transmitted in slave mode, ACK received
0xC0: Data byte transmitted in slave mode, ACK not received
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0xC8: Last byte transmitted in slave mode, ACK received
0xD0: Second Address byte + Write bit transmitted, ACK received
0xD8: Second Address byte + Write bit transmitted, ACK not received
0xF8: No relevant status information, INT_FLAG=0
Others: Reserved

7.1.5.6. TWI Clock Register(Default Value: 0x00000000)
Offset: 0x14

Register Name: TWI_CCR

Bit

R/W

Default/Hex

Description

31:7

/

/

/

6:3

R/W

0

CLK_M

2:0

R/W

0

CLK_N
The TWI bus is sampled by the TWI at the frequency defined by F0:
Fsamp = F 0 = Fin / 2^CLK_N
The TWI OSCL output frequency, in master mode, is F1 / 10:
F1 = F0 / (CLK_M + 1)
Foscl = F1 / 10 = Fin / (2^CLK_N * (CLK_M + 1)*10)
For Example：
Fin = 48Mhz (APB clock input)
For 400kHz full speed 2Wire, CLK_N = 2, CLK_M=2
F0 = 48M/2^2=12Mhz, F1= F0/(10*(2+1)) = 0.4Mhz
For 100Khz standard speed 2Wire, CLK_N=2, CLK_M=11
F0=48M/2^2=12Mhz, F1=F0/(10*(11+1)) = 0.1Mhz

7.1.5.7. TWI Soft Reset Register(Default Value: 0x00000000)
Offset: 0x18

Register Name: TWI_SRST

Bit

R/W

Default/Hex

Description

31:1

/

/

/

0

R/W

0

SOFT_RSTSoft Reset
Write ‘1’ to this bit to reset the TWI and clear to ‘0’ when completing Soft
Reset operation.

7.1.5.8. TWI Enhance Feature Register(Default Value: 0x00000000)
Offset: 0x1C

Register Name: TWI_EFR

Bit

R/W

Default/Hex

Description

31:2

/

/

/

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0:1

R/W

0

DBN
Data Byte number follow Read Command Control
0— No Data Byte to be written after read command
1— Only 1 byte data to be written after read command
2— 2 bytes data can be written after read command
3— 3 bytes data can be written after read command

7.1.5.9. TWI Line Control Register(Default Value: 0x0000003A)
Offset: 0x20

Register Name: TWI_LCR

Bit

R/W

Default/Hex

Description

31:6

/

/

/

1

SCL_STATE
Current state of TWI_SCL
0 – low
1 - high

1

SDA_STATE
Current state of TWI_SDA
0 – low
1 - high

1

SCL_CTLTWI_SCL line state control bit
When line control mode is enabled (bit[2] set), value of this bit decide theoutput level of TWI_SCL
0 – output low level1 – output high level

0

SCL_CTL_EN
TWI_SCL line state control enable
When this bit is set, the state of TWI_SCL is control by the value of bit[3].
0-disable TWI_SCL line control mode
1-enable TWI_SCL line control mode

1

SDA_CTLTWI_SDA line state control bit
When line control mode is enabled (bit[0] set), value of this bit decide theoutput level of TWI_SDA
0 – output low level1 – output high level

0

SDA_CTL_EN
TWI_SDA line state control enable
When this bit is set, the state of TWI_SDA is control by the value of bit[1].
0-disable TWI_SDA line control mode
1-enable TWI_SDA line control mode

5

4

3

2

1

0

R

R

R/W

R/W

R/W

R/W

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7.1.5.10. TWI DVFS Register(Default Value: 0x00000000)
Offset: 0x24

Register Name: TWI_DVFSCR

Bit

R/W

Default/Hex

Description

31:3

/

/

/
MS_PRIORITY
CPU and DVFS BUSY set priority select0: CPU has higher priority
1: DVFS has higher priority

2

R/W

0

1

R/W

0

CPU_BUSY_SETCPU Busy set

0

R/W

0

DVFC_BUSY_SET
DVFS Busy set

Notes:This register is only implemented in TWI0.

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7.2. SPI
7.2.1. Overview
The SPI is the Serial Peripheral Interface which allows rapid data communication with fewer software interrupts.
It can interface with up to four slave external devices or one single external master.The SPI module contains one
64x8 receiver buffer (RXFIFO) and one64x8 transmit buffer (TXFIFO). It can work at two modes: Master modeand Slave mode.
The SPI includes the following features:Full-duplex synchronous serial interface
Master/Slave configurable
Programmable clock granularity

8-bit wide by 64-entry FIFO for both transmit and receive date
Polarity and phase of the Chip Select (SPI_SS) and SPI Clock (SPI_SCLK) are configurable
Interrupt or DMA supported
Support single and dual read mode

7.2.2. SPI Block Diagram
Figure 7-2 shows a block diagram of the SPI.

spi_toptbuf

spi_txtxfifosckt

AHB

TX DMA

spi_cmu

spi_rfspi_mosi_oen
spi_mosi_out
spi_miso_oen
spi_miso_out
spi_ss_oen
spi_ss_out
spi_ss_in
spi_sck_oen
spi_sck_out
spi_sck_in

RX DMAsckr
spi_mosi_in
rbuf

rxfifospi_rxINTC
hclk
domainspi_miso_in

sclk
domainFigure 7-2. SPI Block Diagram
The SPI comprises with:

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spi_rf: Responsible for implementing the internal register,interrupt and DMA Request.
spi_tbuf: The data length transmitted from AHB to txfifo is converted into 8bits,then the data is written into
the rxfifo.
spi_rbuf: The block is used as converted the rxfifo data into read data length of AHB.
txfifo,rxfifo: For transmit and receive transfers,data transmitted from the SPI to the external serial device iswritten into the txfifo;data received from the external serial device into SPI is pushed into the rxfifo.
spi_cmu: Responsible for implementing SPI bus clock,chip select,internal sample and the generation oftransfer clock.
spi_tx: Responsible for implementing SPI data transfer ,the interface of the internal txfifo and status register.
spi_rx: Responsible for implementing SPI data receive, the interface of the internal rxfifo and status register.

7.2.3. SPI Timing Diagram
The serial peripheral interface master uses the SPI_SCLK signal to transfer data in and out of the shift register.
Data is clocked using any one of four programmable clock phase and polarity combinations.
During Phase 0, Polarity 0 and Phase 1, Polarity 1 operations, output data changes on the falling clock edge andinput data is shifted in on the rising edge.
During Phase 1, Polarity 0 and Phase 0, Polarity 1 operations, output data changes on the rising edges of theclock and is shifted in on falling edges.
The POL defines the signal polarity when SPI_SCLK is in idle state. The SPI_SCLK is high level when POL is ‘1’ andit is low level when POL is ‘0’. The PHA decides whether the leading edge of SPI_SCLK is used for setup or sample
data. The leading edge is used for setup data when PHA is ‘1’ and for sample data when PHA is ‘0’. The four kindof modes are listed below:
SPI Mode

POL

PHA

Leading Edge

Trailing Edge

0

0

0

Rising, Sample

Falling, Setup

1

0

1

Rising, Setup

Falling, Sample

2

1

0

Falling, Sample

Rising, Setup

3

1

1

Failing, Setup

Rising, Sample

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SPI_SCLK (Mode 0)
SPI_SCLK (Mode 2)
SPI_MOSISPI_MISOSPI_SS
Sample MOSI/ MISO pin

Phase 0Figure 7-3. SPI Phase 0 Timing Diagram

SPI_SCLK (Mode 1)
SPI_SCLK (Mode 3)
SPI_MOSISPI_MISOSPI_SS
Sample MOSI/ MISO pin

Phase 1Figure 7-4. SPI Phase 1 Timing Diagram

7.2.4. SPI Pin Lists
The direction of SPI pin is different in two work modes: Master Mode and Slave Mode.The following table
describes the external pins of SPI,SPI_MOSI and SPI_MISO are bidirectional I/O,When SPI is configured as
Master device,CLK and CS is output pin;when SPI is configurable as Slave device,CLK and CS is input pin.The
unused SPI ports are used as General Purpose I/O ports.For information about General Purpose I/O ports,seePort Controller(CPUx-PORT)in chapter3.
Port Name

Width

Direction(M)Direction(S)Description

SPI_CLK

1

OUT

IN

SPI Clock

SPI_MOSI

1

OUT

IN

SPI Master Output Slave Input Data Signal

SPI_MISO

1

IN

OUT

SPI Master Input Slave Output Data Signal

SPI_CS1OUTINSPI Chip Select Signal

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7.2.5. SPI Register List
Module Name

Base Address

SPI0

0x01C68000

SPI1

0x01C69000

Register Name

OffsetDescription

SPI_GCR

0x04

SPI Global Control Register

SPI_TCR

0x08

SPI Transfer Control register

/

0x0c

reserved

SPI_IER

0x10

SPI Interrupt Control register

SPI_ISR

0x14

SPI Interrupt Status register

SPI_FCR

0x18

SPI FIFO Control register

SPI_FSR

0x1C

SPI FIFO Status register

SPI_WCR

0x20

SPI Wait Clock Counter register

SPI_CCR

0x24

SPI Clock Rate Control register

/

0x28

reserved/

0x2c

reserved

SPI_MBC

0x30

SPI Burst Counter register

SPI_MTC

0x34

SPI Transmit Counter Register

SPI_BCC

0x38

SPI Burst Control register

SPI_NDMA_MODE_CTL

0x88

SPI Normal DMA Mode Control Register

SPI_TXD

0x200

SPI TX Data register

SPI_RXD

0x300

SPI RX Data register

7.2.6. SPI Register Description
7.2.6.1. SPI Global Control Register(Default Value: 0x00000080)
Offset: 0x04
Bit

Register Name: SPI_CTL
R/W

Default/Hex

Description

31

R/W

0

SRST
Soft reset
Write ‘1’ to this bit will clear the SPI controller, and auto clear to ‘0’ whenreset operation completes
Write ‘0’ has no effect.

30:8

/

/

/

1

TP_EN
Transmit Pause Enable
In master mode, it is used to control transmit state machine to stop smart
burst sending when RX FIFO is full.

7

R/W

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1 – stop transmit data when RXFIFO full0 – normal operation, ignore RXFIFO status
Note: Can’t be written when XCH=1
6:2

1

0

/

R/W

R/W

/

/

0

MODE
SPI Function Mode Select0: Slave Mode
1: Master Mode
Note: Can’t be written when XCH=1

0

EN
SPI Module Enable Control
0: Disable
1: Enable

7.2.6.2. SPI Transfer Control Register(Default Value: 0x00000087)
Offset: 0x08
Bit

Register Name: SPI_INTCTL
R/W

Default/Hex

Description

31

R/W

0x0

XCH
Exchange Burst
In master mode it is used to start SPI burst
0: Idle1: Initiates exchange.
Write “1” to this bit will start the SPI burst, and will auto clear after
finishing the bursts transfer specified by BC. Write “1” to SRST will also
clear this bit. Write ‘0’ to this bit has no effect.
Note：Can’t be written when XCH=1.

30:15

/

/

/

0x0

SDDM
Sending Data Delay Mode
0:normal sending
1:delay sending
Set the bit to"1" to make the data that should be sent with a delay of halfcycle of SPI_CLK in dual io mode for SPI mode 0.

14

R/W

13

R/W

0x0

SDM
Master Sample Data Mode
0 - Delay Sample Mode
1 - Normal Sample Mode
In Normal Sample Mode, SPI master samples the data at the correct edge
for each SPI mode;
In Delay Sample Mode, SPI master samples data at the edge that is halfcycle delayed by the correct edge defined in respective SPI mode.

12

R/W

0x0

FBS

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First Transmit Bit Select0: MSB first
1: LSB first
Note：Can’t be written when XCH=1.

11

10

9

8

7

6

R/W

R/W

R/W

R/W

R/W

R/W

0x0

SDC
Master Sample Data Control
Set this bit to ‘1’ to make the internal read sample point with a delay ofhalf cycle of SPI_CLK. It is used in high speed read operation to reduce theerror caused by the time delay of SPI_CLK propagating between masterand slave.
0 – normal operation, do not delay internal read sample point
1 – delay internal read sample point
Note：Can’t be written when XCH=1.

0x0

RPSM
Rapids mode selectSelect Rapids mode for high speed write.
0: normal write mode
1: rapids write mode
Note：Can’t be written when XCH=1.

0x0

DDB
Dummy Burst Type
0: The bit value of dummy SPI burst is zero
1: The bit value of dummy SPI burst is one
Note：Can’t be written when XCH=1.

0x0

DHB
Discard Hash Burst
In master mode it controls whether discarding unused SPI bursts
0: Receiving all SPI bursts in BC period
1: Discard unused SPI bursts, only fetching the SPI bursts during dummy
burst period. The bursts number is specified by TC.
Note：Can’t be written when XCH=1.

0x1

SS_LEVEL
When control SS signal manually (SPI_CTRL_REG.SS_CTRL==1), set this bit
to ‘1’ or ‘0’ to control the level of SS signal.
0: set SS to low
1: set SS to highNote：Can’t be written when XCH=1.

0x0

SS_OWNER
SS Output Owner SelectUsually, controller sends SS signal automatically with data together. When
this bit is set to 1, software must manually write SPI_CTL_REG.SS_LEVEL
to 1 or 0 to control the level of SS signal.
0: SPI controller
1: Software

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Note：Can’t be written when XCH=1.

5:4

3

2

1

0

R/W

R/W

R/W

R/W

R/W

0x0

SS_SELSPI Chip SelectSelect one of four external SPI Master/Slave Devices
00: SPI_SS0 will be asserted
01: SPI_SS1 will be asserted
10: SPI_SS2 will be asserted
11: SPI_SS3 will be asserted
Note：Can’t be written when XCH=1.

0x0

SSCTL
In master mode, this bit selects the output wave form for the SPI_SSx
signal. Only valid when SS_OWNER = 0.
0: SPI_SSx remains asserted between SPI bursts
1: Negate SPI_SSx between SPI bursts
Note：Can’t be written when XCH=1.

0x1

SPOL
SPI Chip Select Signal Polarity Control
0: Active high polarity (0 = Idle)
1: Active low polarity (1 = Idle)
Note：Can’t be written when XCH=1.

0x1

CPOL
SPI Clock Polarity Control
0: Active high polarity (0 = Idle)
1: Active low polarity (1 = Idle)
Note：Can’t be written when XCH=1.

0x1

CPHA
SPI Clock/Data Phase Control
0: Phase 0 (Leading edge for sample data)
1: Phase 1 (Leading edge for setup data)
Note：Can’t be written when XCH=1.

7.2.6.3. SPI Interrupt Control Register(Default Value: 0x00000000)
Offset: 0x10

Register Name: SPI_IER

Bit

R/W

Default/Hex

Description

31:14

R

0x0

Reserved.

13

R/W

0x0

SS_INT_EN
SSI Interrupt Enable
Chip Select Signal (SSx) from valid state to invalid state
0: Disable
1: Enable

12

R/W

0x0

TC_INT_EN
Transfer Completed Interrupt Enable

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0: Disable
1: Enable

11

10

9

R/W

R/W

R/W

0x0

TF_UDR_INT_EN
TXFIFO under run Interrupt Enable
0: Disable
1: Enable

0x0

TF_OVF_INT_EN
TX FIFO Overflow Interrupt Enable
0: Disable
1: Enable

0x0

RF_UDR_INT_EN
RXFIFO under run Interrupt Enable
0: Disable
1: Enable

8

R/W

0x0

RF_OVF_INT_EN
RX FIFO Overflow Interrupt Enable
0: Disable
1: Enable

7

R

0x0

Reserved.

0x0

TF_FUL_INT_EN
TX FIFO Full Interrupt Enable
0: Disable
1: Enable

0x0

TX_EMP_INT_EN
TX FIFO Empty Interrupt Enable
0: Disable
1: Enable

6

5

R/W

R/W

4

R/W

0x0

TX_ERQ_INT_EN
TX FIFO Empty Request Interrupt Enable
0: Disable
1: Enable

3

R

0x0

Reserved

0x0

RF_FUL_INT_EN
RX FIFO Full Interrupt Enable
0: Disable
1: Enable

0x0

RX_EMP_INT_EN
RX FIFO Empty Interrupt Enable
0: Disable
1: Enable

0x0

RF_RDY_INT_EN
RX FIFO Ready Request Interrupt Enable
0: Disable
1: Enable

2

1

0

R/W

R/W

R/W

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7.2.6.4. SPI Interrupt Status Register(Default Value: 0x00000022)
Offset: 0x14

Register Name: SPI_INT_STA

Bit

R/W

Default/Hex

Description

31:14

/

0x0

/

0

SSI
SS Invalid Interrupt
When SSI is 1, it indicates that SS has changed from valid state to invalid
state. Writing 1 to this bit clears it.

0TC
Transfer Completed
In master mode, it indicates that all bursts specified by BC has been
exchanged. In other condition, When set, this bit indicates that all thedata in TXFIFO has been loaded in the Shift register, and the Shift registerhas shifted out all the bits. Writing 1 to this bit clears it.
0: Busy
1: Transfer Completed

0

TF_UDF
TXFIFO Underrun
This bit is set when if the TXFIFO is underrun. Writing 1 to this bit clears
it.
0: TXFIFO is not underrun
1: TXFIFO is underrun

0

TF_OVF
TXFIFO Overflow
This bit is set when if the TXFIFO is overflow. Writing 1 to this bit clears it.
0: TXFIFO is not overflow
1: TXFIFO is overflowed0

RX_UDF
RXFIFO Underrun
When set, this bit indicates that RXFIFO has underrun. Writing 1 to thisbit clears it.

13

12

11

10

9

R/W

R/W

R/W

R/W

R/W

8

R/W

0

RX_OVF
RXFIFO Overflow
When set, this bit indicates that RXFIFO has overflowed. Writing 1 to thisbit clears it.
0: RXFIFO is available.
1: RXFIFO has overflowed.

7

/

/

/

0

TX_FULLTXFIFO FullThis bit is set when if the TXFIFO is full . Writing 1 to this bit clears it.

6

R/W

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0: TXFIFO is not Full
1: TXFIFO is Full

5

R/W

1

TX_EMPTXFIFO Empty
This bit is set if the TXFIFO is empty. Writing 1 to this bit clears it.
0: TXFIFO contains one or more words.
1: TXFIFO is empty

4

R/W

0

TX_READYTXFIFO Ready
0: TX_WL > TX_TRIG_LEVEL
1: TX_WL <= TX_TRIG_LEVELThis bit is set any time if TX_WL <= TX_TRIG_LEVEL. Writing “1” to this bit
clears it. Where TX_WL is the water level of RXFIFO

3

/

/

reserved

0

RX_FULL
RXFIFO FullThis bit is set when the RXFIFO is full . Writing 1 to this bit clears it.
0: Not Full
1: Full1

RX_EMP
RXFIFO Empty
This bit is set when the RXFIFO is empty . Writing 1 to this bit clears it.
0: Not empty
1: empty0

RX_RDYRXFIFO Ready
0: RX_WL < RX_TRIG_LEVEL
1: RX_WL >= RX_TRIG_LEVELThis bit is set any time if RX_WL >= RX_TRIG_LEVEL. Writing “1” to this bit
clears it. Where RX_WL is the water level of RXFIFO.

2

1

0

R/W

R/W

R/W

7.2.6.5. SPI FIFO Control Register(Default Value: 0x00400001)
Offset: 0x18
Bit

31

30

Register Name: SPI_ FCR
R/W

R/W

R/W

Default/Hex

Description

0

TX_FIFO_RSTTX FIFO Reset
Write ‘1’ to this bit will reset the control portion of the TX FIFO and auto
clear to ‘0’ when completing reset operation, write to ‘0’ has no effect.

0

TF_TEST_ENB
TX Test Mode Enable
0: disable
1: enable

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Note: In normal mode, TX FIFO can only be read by SPI controller, write‘1’ to this bit will switch TX FIFO read and write function to AHB bus. Thisbit is used to test the TX FIFO, don’t set in normal operation and don’t set
RF_TEST and TF_TEST at the same time.
29:26

/

/

/

25

/

/

/

24

R/W

0x0

TF_ DRQ_EN
TX FIFO DMA Request Enable
0: Disable
1: Enable

23:16

R/W

0x40

TX_TRIG_LEVELTX FIFO Empty Request Trigger Level

0x0

RF_RST
RXFIFO Reset
Write ‘1’ to this bit will reset the control portion of the receiver FIFO, andauto clear to ‘0’ when completing reset operation, write ‘0’ to this bit has
no effect.

15

R/W

14

R/W

0x0

RF_TEST
RX Test Mode Enable
0: Disable
1: Enable
Note: In normal mode, RX FIFO can only be written by SPI controller,
write ‘1’ to this bit will switch RX FIFO read and write function to AHB
bus. This bit is used to test the RX FIFO, don’t set in normal operation anddon’t set RF_TEST and TF_TEST at the same time.

13:10

R

0x0

Reserved

0x0

RX_DMA_MODE
SPI RX DMA Mode Control
0: Normal DMA mode
1: Dedicate DMA mode

9

R/W

8

R/W

0x0

RF_ DRQ_EN
RX FIFO DMA Request Enable
0: Disable
1: Enable

7:0

R/W

0x1

RX_TRIG_LEVELRX FIFO Ready Request Trigger Level

7.2.6.6. SPI FIFO Status Register(Default Value: 0x00000000)
Offset: 0x1C

Register Name: SPI_FSR

Bit

R/W

Default/Hex

Description

31

R

0x0

TB_WR
TX FIFO Write Buffer Write Enable

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30:28

R

0x0

TB_CNT
TX FIFO Write Buffer Counter
These bits indicate the number of words in TX FIFO Write Buffer

27:24

R

0x0

Reserved

23:16

R

0x0

TF_CNT
TX FIFO Counter
These bits indicate the number of words in TX FIFO
0: 0 byte in TX FIFO
1: 1 byte in TX FIFO…
64: 64 bytes in TX FIFO

15

R

0x0

RB_WR
RX FIFO Read Buffer Write Enable

14:12

R

0x0

RB_CNT
RX FIFO Read Buffer Counter
These bits indicate the number of words in RX FIFO Read Buffer

11:8

R

0x0

Reserved

0x0

RF_CNT
RX FIFO Counter
These bits indicate the number of words in RX FIFO
0: 0 byte in RX FIFO
1: 1 byte in RX FIFO…
64:64 bytes in RX FIFO

7:0

R

7.2.6.7. SPI Wait Clock Register(Default Value: 0x00000000)
Offset: 0x20

Register Name: SPI_WAIT

Bit

R/W

Default/Hex

Description

31:20

/

/

/

0x0

SWC
Dual mode direction switch wait clock counter (for master mode only).
0: No wait states inserted
n: n SPI_SCLK wait states inserted
Note: These bits control the number of wait states to be inserted before
start dual data transfer in dual SPI mode. The SPI module counts SPI_SCLK
by SWC for delaying next word data transfer.
Note：Can’t be written when XCH=1.

19:16

15:0

R/W

R/W

0

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WCC
Wait Clock Counter (In Master mode)
These bits control the number of wait states to be inserted in datatransfers. The SPI module counts SPI_SCLK by WCC for delaying next word
data transfer.
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0: No wait states inserted
N: N SPI_SCLK wait states inserted

7.2.6.8. SPI Clock Control Register(Default Value: 0x00000002)
Offset: 0x24

Register Name: SPI_CCTL

Bit

R/W

Default/Hex

Description

31:13

/

/

/

0

DRS
Divide Rate Select (Master Mode Only)
0: Select Clock Divide Rate 1
1: Select Clock Divide Rate 20

CDR1
Clock Divide Rate 1 (Master Mode Only)
The SPI_SCLK is determined according to the following equation: SPI_CLK= Source_CLK / 2^n.

0x2

CDR2
Clock Divide Rate 2 (Master Mode Only)
The SPI_SCLK is determined according to the following equation: SPI_CLK= Source_CLK / (2*(n + 1)).

12

11:8

7:0

R/W

R/W

R/W

7.2.6.9. SPI Master Burst Counter Register(Default Value: 0x00000000)
Offset: 0x30

Register Name: SPI_BC

Bit

R/W

Default/Hex

Description

31:24

/

/

/

0

MBC
Master Burst Counter
In master mode, this field specifies the total burst number.
0: 0 burst
1: 1 burst…
N: N bursts

23:0

R/W

7.2.6.10. SPI Master Transmit Counter Register(Default Value: 0x00000000)
Offset: 0x34

Register Name: SPI_TC

Bit

R/W

Default/Hex

Description

31:24

/

/

/

23:0

R/W

0

MWTC

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Master Write Transmit Counter
In master mode, this field specifies the burst number that should be sent
to TXFIFO before automatically sending dummy burst. For saving bus
bandwidth, the dummy burst (all zero bits or all one bits) is sent by SPI
Controller automatically.
0: 0 burst
1: 1 burst…
N: N bursts

7.2.6.11. SPI Master Burst Control Counter Register(Default Value: 0x00000000)
Offset: 0x38

Register Name: SPI_BCC

Bit

R/W

Default/Hex

Description

31:29

R

0x0

Reserved

0x0

DRM
Master Dual Mode RX Enable
0: RX use single-bit mode
1: RX use dual mode
Note：Can’t be written when XCH=1.

0x0

DBC
Master Dummy Burst Counter
In master mode, this field specifies the burst number that should be sent
before receive in dual SPI mode. The data is don’t care by the device.
0: 0 burst
1: 1 burst…
N: N bursts
Note：Can’t be written when XCH=1.

0x0

STC
Master Single Mode Transmit Counter
In master mode, this field specifies the burst number that should be sentin single mode before automatically sending dummy burst. This is the firsttransmit counter in all bursts.
0: 0 burst
1: 1 burst…
N: N bursts
Note：Can’t be written when XCH=1.

28

27:24

23:0

R/W

R/W

R/W

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7.2.6.12. SPI Normal DMA Mode Control Register(Default Value: 0x000000A5)
Offset: 0x88
Bit

7:0

Register Name: SPI_NDMA_MODE_CTL
R/W

R/W

Default/Hex

Description

0xA5

NDMA_MODE_CTL
0xEA:NDMA handshake mode
Note:NDMA wait mode don't care this value.0xA5 can be used inhandshake mode, but 0xEA is better.

7.2.6.13. SPI TX Data Register(Default Value: 0x00000000)
Offset: 0x200
Bit

31:0

R/W

W/R

Register Name: SPI_TXD
Default/Hex

Description

0x0

TDATA
Transmit Data
This register can be accessed in byte, half-word or word unit by AHB. In
byte accessing method, if there are rooms in RXFIFO, one burst data is
written to RXFIFO and the depth is increased by 1. In half-word accessing
method, two SPI burst data are written and the TXFIFO depth is increaseby 2. In word accessing method, four SPI burst data are written and the
TXFIFO depth is increased by 4.
Note: This address is writing-only if TF_TEST is ‘0’, and if TF_TEST is set to‘1’, this address is readable and writable to test the TX FIFO through the
AHB bus.

7.2.6.14. SPI RX Data Register(Default Value: 0x00000000)
Offset: 0x300
Bit

31:0

R/W

R

Register Name: SPI_RXD
Default/Hex

Description

0

RDATA
Receive Data
This register can be accessed in byte, half-word or word unit by AHB. In
byte accessing method, if there are data in RXFIFO, the top word isreturned and the RXFIFO depth is decreased by 1. In half-word accessing
method, two SPI bursts are returned and the RXFIFO depth is decrease by
2. In word accessing method, the four SPI bursts are returned and the
RXFIFO depth is decreased by 4.
Note: This address is read-only if RF_TEST is ‘0’, and if RF_TEST is set to‘1’, this address is readable and writable to test the RX FIFO through the
AHB bus.

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7.3. UART
7.3.1. Overview
The UART is used for serial communication with a peripheral, modem (data carrier equipment, DCE) or data set.
Data is written from a master (CPU) over the APB bus to the UART and it is converted to serial form andtransmitted to the destination device. Serial data is also received by the UART and stored for the master (CPU) toread back.
The UART contains registers to control the character length, baud rate, parity generation/checking, and interrupt
generation. Although there is only one interrupt output signal from the UART, there are several prioritizedinterrupt types that can be responsible for its assertion. Each of the interrupt types can be separately
enabled/disabled with the control registers.
The UART has 16450 and 16550 modes of operation, which are compatible with a range of standard software
drivers. In 16550 mode, transmit and receive operations are both buffered by FIFOs. In 16450 mode, these FIFOs
are disabled.
The UART supports data lengths from five to eight bits, an optional parity bit and 1, 1 ½ or 2 stop bits, and is fully
programmable by an AMBA APB CPU interface. A 16-bit programmable baud rate generator and an 8-bit scratch
register are included, together with separate transmit and receive FIFOs. Eight modem control lines and adiagnostic loop-back mode are provided.
Interrupts can be generated for a range of TX Buffer/FIFO, RX Buffer/FIFO, Modem Status and Line Statusconditions.
For integration in system where Infrared SIR serial data format is required,the UART can be configured to have asoftware-programmable IrDA SIR Mode.If this mode is not selected,only the UART(RS232 standard) serial data
format is available.
The UART includes the following features:Compatible with industry-standard 16550 UARTs

64-Bytes Transmit and receive data FIFOs

DMA controller interfaceSoftware/ Hardware Flow Control
Programmable Transmit Holding Register Empty interrupt
Interrupt support for FIFOs, Status ChangeSupport IrDA 1.0 SIR

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7.3.2. UART Timing Diagram
One Character
Bit Time
TX/RX

Serial Data

S

Data bits 5-8

P

S 1,1.5,2

Figure 7-5. UART Serial Data Format

Data Bits
Bit Time
SIN/SOUT

S

Stop
3/16 Bit Time

3/16 Bit Time

SIR_OUT
3/16 Bit Time
SIR_IN

Figure 7-6. Serial IrDA Data Format

7.3.3. UART Pin List
Port Name

Width

Direction

Description

UART0_TX

1OUT

UART Serial Bit output

UART0_RX

1

IN

UART Serial Bit input

UART1_TX

1OUT

UART Serial Bit output

UART1_RX

1

IN

UART Serial Bit input

UART1_RTS

1OUT

UART Request To Send
This active low output signal informs Modem that the UART is ready tosend data

UART1_CTS

1IN

UART Clear To End
This active low signal is an input showing when Modem is ready toaccept data

UART2_TX

1OUT

UART Serial Bit output

UART2_RX

1

IN

UART Serial Bit input

UART2_RTS

1OUT

UART Request To Send
This active low output signal informs Modem that the UART is ready tosend data

UART2_CTS

1IN

UART Clear To End
This active low signal is an input showing when Modem is ready toaccept data

UART3_TX

1OUT

UART Serial Bit output

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UART3_RX

1

IN

UART Serial Bit input

UART3_RTS

1OUT

UART Request To Send
This active low output signal informs Modem that the UART is ready tosend data

UART3_CTS

1IN

UART Clear To End
This active low signal is an input showing when Modem is ready toaccept data

UART4_TX

1OUT

UART Serial Bit output

UART4_RX

1

IN

UART Serial Bit input

UART4_RTS

1OUT

UART Request To Send
This active low output signal informs Modem that the UART is ready tosend data

UART4_CTS

1IN

UART Clear To End
This active low signal is an input showing when Modem is ready toaccept data

S_UART_TX

1OUT

UART Serial Bit output

S_UART_RX

1

IN

UART Serial Bit input

7.3.4. UART Controller Register List
There are 6 UART controllers. All UART controllers can be configured as Serial IrDA.
Module Name

Base Address

UART00x01C28000

UART1

0x01C28400

UART20x01C28800

UART30x01C28C00

UART4

0x01C29000

R-UART

0x01F02800

Register Name

OffsetDescription

UART_RBR

0x00

UART Receive Buffer Register

UART_THR

0x00

UART Transmit Holding Register

UART_DLL

0x00

UART Divisor Latch Low Register

UART_DLH

0x04

UART Divisor Latch High Register

UART_IER

0x04

UART Interrupt Enable Register

UART_IIR

0x08

UART Interrupt Identity Register

UART_FCR

0x08

UART FIFO Control Register

UART_LCR

0x0C

UART Line Control Register

UART_MCR

0x10

UART Modem Control Register

UART_LSR

0x14

UART Line Status Register

UART_MSR

0x18

UART Modem Status Register

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UART_SCH

0x1C

UART Scratch Register

UART_USR

0x7C

UART Status Register

UART_TFL

0x80

UART Transmit FIFO Level

UART_RFL

0x84

UART_RFLUART_HALT

0xA4

UART Halt TX Register

7.3.5. UART Register Description
7.3.5.1. UART Receiver Buffer Register(Default Value: 0x00000000)
Offset: 0x0000

Register Name: UART_RBR

Bit

R/W

Default/Hex

Description

31:8

/

/

/
RBR
Receiver Buffer Register
Data byte received on the serial input port . The data in this register isvalid only if the Data Ready (DR) bit in the UART Line Status Register(UART_LCR) is set.

7:0

R

0

If in FIFO mode and FIFOs are enabled (UART_FCR[0] set to one), thisregister accesses the head of the receive FIFO. If the receive FIFO is fulland this register is not read before the next data character arrives, thenthe data already in the FIFO is preserved, but any incoming data are lostand an overrun error occurs.

7.3.5.2. UART Transmit Holding Register(Default Value: 0x00000000)
Offset: 0x0000

Register Name: UART_THR

Bit

R/W

Default/Hex

Description

31:8

/

/

/

0

THR
Transmit Holding Register
Data to be transmitted on the serial output port . Data should only be
written to the THR when the THR Empty (THRE) bit (UART_LSR[5]) is set.
If in FIFO mode and FIFOs are enabled (UART_FCR[0] = 1) and THRE is set,
16 number of characters of data may be written to the THR before the
FIFO is full. Any attempt to write data when the FIFO is full results in thewrite data being lost.

7:0

W

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7.3.5.3. UART Divisor Latch Low Register(Default Value: 0x00000000)
Offset: 0x0000

Register Name: UART_DLL

Bit

R/W

Default/Hex

Description

31:8

/

/

/

0

DLL
Divisor Latch Low
Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains
the baud rate divisor for the UART. This register may only be accessed
when the DLAB bit (UART_LCR[7]) is set and the UART is not busy
(UART_USR[0] is zero).
The output baud rate is equal to the serial clock (sclk) frequency divided
by sixteen times the value of the baud rate divisor, as follows: baud rate =(serial clock freq) / (16 * divisor).
Note that with the Divisor Latch Registers (DLL and DLH) set to zero, thebaud clock is disabled and no serial communications occur. Also, once the
DLL is set, at least 8 clock cycles of the slowest UART clock should beallowed to pass before transmitting or receiving data.

7:0

R/W

7.3.5.4. UART Divisor Latch High Register(Default Value: 0x00000000)
Offset: 0x0004

Register Name: UART_DLH

Bit

R/W

Default/Hex

Description

31:8

/

/

/

0

DLH
Divisor Latch High
Upper 8 bits of a 16-bit, read/write, Divisor Latch register that contains
the baud rate divisor for the UART. This register may only be accessed
when the DLAB bit (UART_LCR[7]) is set and the UART is not busy
(UART_USR [0] is zero).
The output baud rate is equal to the serial clock (sclk) frequency divided
by sixteen times the value of the baud rate divisor, as follows: baud rate =(serial clock freq) / (16 * divisor).
Note that with the Divisor Latch Registers (DLL and DLH) set to zero, thebaud clock is disabled and no serial communications occur. Also, once the
DLH is set, at least 8 clock cycles of the slowest UART clock should beallowed to pass before transmitting or receiving data.

7:0

R/W

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7.3.5.5. UART Interrupt Enable Register(Default Value: 0x00000000)
Offset: 0x0004

Register Name: UART_IER

Bit

R/W

Default/Hex

Description

31:8

/

/

/

7

R/W

6:4

/

3

2

1

0

R/W

R/W

R/W

R/W

PTIME
Programmable THRE Interrupt Mode Enable
This is used to enable/disable the generation of THRE Interrupt.
0: Disable
1: Enable
/

/

0

EDSSI
Enable Modem Status Interrupt
This is used to enable/disable the generation of Modem Status Interrupt.
This is the fourth highest priority interrupt.
0: Disable
1: Enable

0

ELSI
Enable Receiver Line Status Interrupt
This is used to enable/disable the generation of Receiver Line Status
Interrupt. This is the highest priority interrupt.
0: Disable
1: Enable

0

ETBEI
Enable Transmit Holding Register Empty Interrupt
This is used to enable/disable the generation of Transmitter Holding
Register Empty Interrupt. This is the third highest priority interrupt.
0: Disable
1: Enable

0

ERBFI
Enable Received Data Available Interrupt
This is used to enable/disable the generation of Received Data Available
Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs
enabled). These are the second highest priority interrupts.
0: Disable
1: Enable

7.3.5.6. UART Interrupt Identity Register(Default Value: 0x00000001)
Offset: 0x0008

Register Name: UART_IIR

Bit

R/W

Default/Hex

Description

31:8

/

/

/

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7:6

R

0

FEFLAG
FIFOs Enable Flag
This is used to indicate whether the FIFOs are enabled or disabled.
00: Disable
11: Enable

5:4

/

/

/

3:0

R

0x1

IID
Interrupt ID
This indicates the highest priority pending interrupt which can be one of
the following types:
0000: modem status
0001: no interrupt pending
0010: THR empty
0100: received data available
0110: receiver line status
0111: busy detect
1100: character timeout
Bit 3 indicates an interrupt can only occur when the FIFOs are enabled
and used to distinguish a Character Timeout condition interrupt.

Interrupt
ID

Priority
Level

Interrupt TypeInterrupt Source

Interrupt Reset

0001

-

None

None

-

0110

HighestReceiverstatusOverrun/parity/framing
errors or break interrupt

Reading UART Line Status Register

0100

SecondReceived data
available

Receiverdata
available(non-FIFO mode or FIFOs
disabled) or RCVR FIFO
trigger level reached (FIFO
mode and FIFOs enabled)

Reading UART Receiver Buffer Register(non-FIFO mode or FIFOs disabled) orthe FIFO drops below the trigger level(FIFO mode and FIFOs enabled)

1100

SecondCharactertimeout
indication

No characters in or out of
the RCVR FIFO during the last
4 character times and there
is at least 1character in it
duringThis time

Reading UART Receiver Buffer Register

0010

Third

Transmitholdingregister empty

Transmitter holding register
empty (Program THRE Modedisabled) or XMIT FIFO at or
below threshold (Program
THRE Mode enabled)

Reading UART Interrupt Identity
Register (if source of interrupt); or,writing into THR (FIFOs or THRE Modenot selected or disabled) or XMIT FIFO
above threshold (FIFOs and THRE Modeselected and enabled).

0000

FourthModem status

Clear to send or data set

Reading the Modem status Register

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ready or ring indicator ordata carrier detect. Note that
if auto flow control mode isenabled, a change in CTS(that is, DCTS set) does notcause an interrupt.
0111

Fifth

Busy
detectindication

UART_16550_COMPATIBLE =NO and master has tried towrite to the Line Control
Register while the UART isbusy (UART_USR[0] is set toone).

Reading the UART status register

7.3.5.7. UART FIFO Control Register(Default Value: 0x00000000)
Offset: 0x0008

Register Name: UART_FCR

Bit

R/W

Default/Hex

Description

31:8

/

/

/

0

RT
RCVR Trigger
This is used to select the trigger level in the receiver FIFO at which the
Received Data Available Interrupt is generated. In auto flow control mode
it is used to determine when the rts_n signal is de-asserted. It also
determines when the dma_rx_req_n signal is asserted in certain modesof operation.
00: 1 character in the FIFO
01: FIFO ¼ full
10: FIFO ½ full
11: FIFO-2 less than full0

TFT
TX Empty Trigger
Writes have no effect when THRE_MODE_USER = Disabled. This is used to
select the empty threshold level at which the THRE Interrupts are
generated when the mode is active. It also determines when the
dma_tx_req_n signal is asserted when in certain modes of operation.
00: FIFO empty
01: 2 characters in the FIFO
10: FIFO ¼ full
11: FIFO ½ full0

DMAM
DMA Mode
0: Mode 0
1: Mode 1

7:6

5:4

3

W

W

W

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2

1

0

W

W

W

0

XFIFORXMIT FIFO ResetThis resets the control portion of the transmit FIFO and treats the FIFO as
empty. This also de-asserts the DMA TX request.
It is 'self-clearing'. It is not necessary to clear this bit.

0

RFIFOR
RCVR FIFO ResetThis resets the control portion of the receive FIFO and treats the FIFO as
empty. This also de-asserts the DMA RX request.
It is 'self-clearing'. It is not necessary to clear this bit.

0

FIFOE
Enable FIFOs
This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs.
Whenever the value of this bit is changed both the XMIT and RCVR
controller portion of FIFOs is reset.

7.3.5.8. UART Line Control Register(Default Value: 0x00000000)
Offset: 0x000C

Register Name: UART_LCR

Bit

R/W

Default/Hex

Description

31:8

/

/

/

0

DLAB
Divisor Latch Access Bit
It is writeable only when UART is not busy (UART_USR[0] is zero) andalways readable. This bit is used to enable reading and writing of theDivisor Latch register (UART_DLL and UART_DLH) to set the baud rate of
the UART. This bit must be cleared after initial baud rate setup in order toaccess other registers.
0: Select UART Receiver Buffer Register(UART_RBR) / UART Transmit
Holding Register (UART_THR) and UART Interrupt Enable
Register(UART_IER)
1: Select UART Divisor Latch Low Register(UART_DLL) and UART Divisor
Latch High Register (UART_DLH)

7

R/W

6

R/W

0

BC
Break Control Bit
This is used to cause a break condition to be transmitted to the receiving
device. If set to one the serial output is forced to the spacing (logic 0)
state. When not in Loop Back Mode, as determined by UART_MCR[4],the sout line is forced low until the Break bit is cleared. If SIR_MODE =Enabled and active (UART_MCR[6] set to one) the sir_out_n line iscontinuously pulsed. When in Loop Back Mode, the break condition isinternally looped back to the receiver and the sir_out_n line is forced low.

5:4

R/W

0

EPS

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Even Parity Select
It is writeable only when UART is not busy (UART_USR[0] is zero) andalways writable readable. This is used to select between even and odd
parity, when parity is enabled (PEN set to one). Setting the UART_LCR[5]is to reverse the UART_LCR[4].
00: Odd Parity
01: Even Parity
1X: Reverse LCR[4]

3

2

1:0

R/W

R/W

R/W

0

PEN
Parity Enable
It is writeable only when UART is not busy (UART_USR[0] is zero) andalways readable. This bit is used to enable and disable parity generationand detection in transmitted and received serial character respectively.
0: parity disabled
1: parity enabled

0

STOP
Number of stop bits
It is writeable only when UART is not busy (UART_USR[0] is zero) andalways readable. This is used to select the number of stop bits per
character that the peripheral transmits and receives. If set to zero, onestop bit is transmitted in the serial data. If set to one and the data bits are
set to 5 (UART_LCR[1:0] set to zero) one and a half stop bits istransmitted. Otherwise, two stop bits are transmitted. Note thatregardless of the number of stop bits selected, the receiver checks only
the first stop bit.
0: 1 stop bit
1: 1.5 stop bits when DLS (UART_LCR[1:0]) is zero, else 2 stop bit

0

DLS
Data Length Select
It is writeable only when UART is not busy (UART_USR[0] is zero) andalways readable. This is used to select the number of data bits per
character that the peripheral transmits and receives. The number of bitthat may be selected areas follows:
00: 5 bits
01: 6 bits
10: 7 bits
11: 8 bits

7.3.5.9. UART Modem Control Register(Default Value: 0x00000000)
Offset: 0x0010

Register Name: UART_MCR

Bit

R/W

Default/Hex

Description

31:7

/

/

/

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6

5

R/W

R/W

0

SIRE
SIR Mode Enable
0:IrDA SIR Mode disable
1:IrDA SIR Mode enable0

AFCE
Auto Flow Control Enable
When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit isset, Auto Flow Control features are enabled.
0: Auto Flow Control Mode disabled
1: Auto Flow Control Mode enabled

4

R/W

0

LOOP
Loop Back Mode
0: Normal Mode
1: Loop Back Mode
This is used to put the UART into a diagnostic mode for test purposes. If
operating in UART mode (SIR_MODE != Enabled or not active,
UART_MCR[6] set to zero), data on the sout line is held high, while serial
data output is looped back to the sin line, internally. In this mode all theinterrupts are fully functional. Also, in Loop Back Mode, the modem
control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and themodem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to
the inputs, internally. If operating in infrared mode (SIR_MODE ==Enabled AND active, UART_MCR[6] set to one), data on the sir_out_n line
is held low, while serial data output is inverted and looped back to thesir_in line.

3:2

/

/

/

1

R/W

0

RTS
Request to Send
This is used to directly control the Request to Send (rts_n) output. The
Request To Send (rts_n) output is used to inform the modem or data set
that the UART is ready to exchange data. When Auto RTS Flow Control is
not enabled (UART_MCR[5] set to zero), the rts_n signal is set low by
programming UART_MCR[1] (RTS) to a high.In Auto Flow Control,
AFCE_MODE == Enabled and active (UART_MCR[5] set to one) and FIFOs
enable (FCR[0] set to one), the rts_n output is controlled in the same way,
but is also gated with the receiver FIFO threshold trigger (rts_n is inactive
high when above the threshold). The rts_n signal is de-asserted when
UART_MCR[1] is set low.
0: rts_n de-asserted (logic 1)
1: rts_n asserted (logic 0)
Note that in Loop Back Mode (UART_MCR[4] set to one), the rts_n
output is held inactive high while the value of this location is internallylooped back to an input.

0

R/W

0

DTR

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Data Terminal Ready
This is used to directly control the Data Terminal Ready (dtr_n) output.
The value written to this location is inverted and driven out on dtr_n.
0：dtr_n de-asserted (logic 1)
1：dtr_n asserted (logic 0)
The Data Terminal Ready output is used to inform the modem or data set
that the UART is ready to establish communications.
Note that in Loop Back Mode(UART_MCR[4] set to one), the dtr_n
output is held inactive high while the value of this location is internallylooped back to an input.

7.3.5.10. UART Line Status Register(Default Value: 0x00000060)
Offset: 0x0014

Register Name: UART_LSR

Bit

R/W

Default/Hex

Description

31:8

/

/

/

0

FIFOERR
RX Data Error in FIFO
When FIFOs are disabled, this bit is always 0. When FIFOs are enabled,
this bit is set to 1 when there is at least one PE, FE, or BI in the RX FIFO. It
is cleared by a read from the LSR register provided there are no
subsequent errors in the FIFO.

1

TEMTTransmitter Empty
If the FIFOs are disabled, this bit is set to "1" whenever the TX Holding
Register and the TX Shift Register are empty. If the FIFOs are enabled, this
bit is set whenever the TX FIFO and the TX Shift Register are empty. In
both cases, this bit is cleared when a byte is written to the TX datachannel.

1

THRE
TX Holding Register Empty
If the FIFOs are disabled, this bit is set to "1" whenever the TX Holding
Register is empty and ready to accept new data and it is cleared when the
CPU writes to the TX Holding Register.
If the FIFOs are enabled, this bit is set to "1" whenever the TX FIFO isempty and it is cleared when at least one byte is written
to the TX FIFO.

7

6

5

R

R

R

BI
Break Interrupt
This is used to indicate the detection of a break sequence on the serial
input data.
4R

0

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sin, is held in a logic '0' state for longer than the sum of start time + databits + parity + stop bits.
If in infrared mode(SIR_MODE=Enable),it is set whenever the serial input,
sir_in,is continuously pulsed to logic ‘0’ for longer than the sum of start
time + data bits + parity + stop bits.Abreak condition on serial input
causes one and only one character,consisting of all zeros,to be received
by the UART.
In the FIFO mode, the character associated with the break condition iscarried through the FIFO and is revealed when the character is at the topof the FIFO. Reading the LSR clears the BI bit. In the non-FIFO mode, theBI indication occurs immediately and persists until the LSR is read.
FE
Framing Error
This is used to indicate the occurrence of a framing error in the receiver.
A framing error occurs when the receiver does not detect a valid STOP bit
in the received data.

3

2
1

R

R
R

0

In the FIFO mode, since the framing error is associated with a character
received, it is revealed when the character with the framing error is at the
top of the FIFO. When a framing error occurs, the UART tries toresynchronize. It does this by assuming that the error was due to the start
bit of the next character and then continues receiving the other bit i.e.
data, and/or parity and stop. It should be noted that the Framing Error(FE) bit (UART_LSR[3]) is set if a break interrupt has
occurred, as indicated by Break Interrupt (BI) bit (UART_LSR[4]).
0: no framing error
1:framing error
Reading the LSR clears the FE bit.

0

PE
Parity Error
This is used to indicate the occurrence of a parity error in the receiver if
the Parity Enable (PEN) bit (UART_LCR[3]) is set. In the FIFO mode, since
the parity error is associated with a character received, it is revealed
when the character with the parity error arrives at the top of the FIFO. It
should be noted that the Parity Error (PE) bit (UART_LSR[2]) is set if abreak interrupt has occurred, as indicated by Break Interrupt(BI) bit(UART_LSR[4]).
0: no parity error
1: parity error
Reading the LSR clears the PE bit.

0

OE
Overrun Error

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This occurs if a new data character was received before the previous data
was read. In the non-FIFO mode, the OE bit is set when a new character
arrives in the receiver before the previous character was read from the
RBR. When this happens, the data in the RBR is overwritten. In the FIFO
mode, an overrun error occurs when the FIFO is full and a new character
arrives at the receiver. The data in the FIFO is retained and the data in thereceive shift register is lost.
0: no overrun error
1: overrun error
Reading the LSR clears the OE bit.

0

R

0

DR
Data Ready
This is used to indicate that the receiver contains at least one character inthe RBR or the receiver FIFO.
0: no data ready
1: data readyThis bit is cleared when the RBR is read in non-FIFO mode, or when thereceiver FIFO is empty, in FIFO mode.

7.3.5.11. UART Modem Status Register(Default Value: 0x00000000)
Offset: 0x0018

Register Name: UART_MSR

Bit

R/W

Default/Hex

Description

31:8

/

/

/

0

DCD
Line State of Data Carrier Detect
This is used to indicate the current state of the modem control line
dcd_n. This bit is the complement of dcd_n. When the Data Carrier
Detect input (dcd_n) is asserted it is an indication that the carrier has
been detected by the modem or data set.
0: dcd_n input is de-asserted (logic 1)
1: dcd_n input is asserted (logic 0)0

RILine State of Ring Indicator
This is used to indicate the current state of the modem control line ri_n.
This bit is the complement of ri_n. When the Ring Indicator input (ri_n) is
asserted it is an indication that a telephone ringing signal has been
received by the modem or data set.
0: ri_n input is de-asserted (logic 1)
1: ri_n input is asserted (logic 0)0

DSRLine State of Data Set Ready
This is used to indicate the current state of the modem control line dsr_n.

7

6

5

R

R

R

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This bit is the complement of dsr_n. When the Data Set Ready input(dsr_n) is asserted it is an indication that the modem or data set is readyto establish communications with UART.
0: dsr_n input is de-asserted (logic 1)
1: dsr_n input is asserted (logic 0)
In Loop Back Mode (UART_MCR[4] set to one), DSR is the same as
UART_MCR[0] (DTR).

4

3

2

1

R

R

R

R

0

CTS
Line State of Clear To Send
This is used to indicate the current state of the modem control line cts_n.
This bit is the complement of cts_n. When the Clear to Send input (cts_n)
is asserted it is an indication that the modem or data set is ready to
exchange data with UART.
0: cts_n input is de-asserted (logic 1)
1: cts_n input is asserted (logic 0)
In Loop Back Mode (UART_MCR[4] = 1), CTS is the same as UART_MCR[1] (RTS).

0

DDCD
Delta Data Carrier Detect
This is used to indicate that the modem control line dcd_n has changed
since the last time the MSR was read.
0: no change on dcd_n since last read of MSR
1: change on dcd_n since last read of MSR
Reading the MSR clears the DDCD bit.
Note: Ff the DDCD bit is not set and the dcd_n signal is asserted (low) anda reset occurs (software or otherwise), then the DDCD bit is set when thereset is removed if the dcd_n signal remains asserted.

0

TERI
Trailing Edge Ring Indicator
This is used to indicate that a change on the input ri_n (from anactive-low to an inactive-high state) has occurred since the last time theMSR was read.
0: no change on ri_n since last read of MSR
1: change on ri_n since last read of MSR
Reading the MSR clears the TERI bit.

0

DDSR
Delta Data Set Ready
This is used to indicate that the modem control line dsr_n has changed
since the last time the MSR was read.
0: no change on dsr_n since last read of MSR
1: change on dsr_n since last read of MSR
Reading the MSR clears the DDSR bit. In Loop Back Mode (UART_MCR[4]= 1), DDSR reflects changes on UART_MCR[0] (DTR).
Note: If the DDSR bit is not set and the dsr_n signal is asserted (low) andA64 User Manual(Revision 1.0)

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a reset occurs (software or otherwise), then the DDSR bit is set when thereset is removed if the dsr_n signal remains asserted.

0

R

0

DCTS
Delta Clear to Send
This is used to indicate that the modem control line cts_n has changed
since the last time the MSR was read.
0: no change on ctsdsr_n since last read of MSR
1: change on ctsdsr_n since last read of MSR
Reading the MSR clears the DCTS bit. In Loop Back Mode (UART_MCR[4]= 1), DCTS reflects changes on UART_MCR[1] (RTS).
Note: If the DCTS bit is not set and the cts_n signal is asserted (low) and a
reset occurs (software or otherwise), then the DCTS bit is set when thereset isremoved if the cts_n signal remains asserted.

7.3.5.12. UART Scratch Register(Default Value: 0x00000000)
Offset: 0x001C

Register Name: UART_SCH

Bit

R/W

Default/Hex

Description

31:8

/

/

/

0

SCRATCH_REG
Scratch Register
This register is for programmers to use as a temporary storage space. It
has no defined purpose in the UART.

7:0

R/W

7.3.5.13. UART Status Register(Default Value: 0x00000006)
Offset: 0x007C

Register Name: UART_USR

Bit

R/W

Default/Hex

Description

31:5

/

/

/

0

RFF
Receive FIFO FullThis is used to indicate that the receive FIFO is completely full.
0: Receive FIFO not full
1: Receive FIFO FullThis bit is cleared when the RX FIFO is no longer full.

0

RFNE
Receive FIFO Not Empty
This is used to indicate that the receive FIFO contains one or more
entries.
0: Receive FIFO is empty
1: Receive FIFO is not empty

4

3

R

R

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This bit is cleared when the RX FIFO is empty.

2

1

0

R

R

R

1

TFE
Transmit FIFO Empty
This is used to indicate that the transmit FIFO is completely empty.
0: Transmit FIFO is not empty
1: Transmit FIFO is empty
This bit is cleared when the TX FIFO is no longer empty.

1

TFNF
Transmit FIFO Not FullThis is used to indicate that the transmit FIFO in not full.
0: Transmit FIFO is full
1: Transmit FIFO is not fullThis bit is cleared when the TX FIFO is full.

0

BUSY
UART Busy Bit
0: Idle or inactive
1: Busy

7.3.5.14. UART Transmit FIFO Level Register(Default Value: 0x00000000)
Offset: 0x0080

Register Name: UART_TFL

Bit

R/W

Default/Hex

Description

31:7

/

/

/

0

TFL
Transmit FIFO Level
This is indicates the number of data entries in the transmit FIFO.

6:0

R

7.3.5.15. UART Receive FIFO Level Register(Default Value: 0x00000000)
Offset: 0x0084

Register Name: UART_RFL

Bit

R/W

Default/Hex

Description

31:7

/

/

/

0

RFL
Receive FIFO Level
This is indicates the number of data entries in the receive FIFO.

6:0

R

7.3.5.16. UART Halt TX Register(Default Value: 0x00000000)
Offset: 0x00A4
Bit

R/W

Register Name: UART_HALT
Default/Hex

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Description
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31:4

5

/

R/W

/

/

0

SIR_RX_INVERTSIR Receiver Pulse Polarity Invert
0: Not invert receiver signal
1: Invert receiver signal

4

R/W

0

SIR_TX_INVERTSIR Transmit Pulse Polarity Invert
0: Not invert transmit pulse
1: Invert transmit pulse

3

/

/

/

0

CHANGE_UPDATE
After the user using HALT[1] to change the baudrate or LCR configuration,
write 1 to update the configuration and waiting this bit self clear to 0 to
finish update process. Write 0 to this bit has no effect.
1: Update trigger, Self clear to 0 when finish update.

0

CHCFG_AT_BUSY
This is an enable bit for the user to change LCR register configuration(except for the DLAB bit) and baudrate register (DLH and DLL) when the
UART is busy (UART_USR[0] is 1).
1: Enable change when busy0

HALT_TX
Halt TX
This register is use to halt transmissions for testing, so that the transmit
FIFO can be filled by the master when FIFOs are implemented andenabled.
0 : Halt TX disabled
1 : Halt TX enabled
Note: If FIFOs are not enabled, the setting of the halt TX register has noeffect on operation.

2

1

0

R/W

R/W

R/W

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7.4. CIR Receiver
7.4.1. Overview
The CIR includes the following features:Full physical layer implementation
Support CIR for remote control
64x8 bits FIFO for data buffer
Programmable FIFO thresholds

For saving CPU resource, CIR receiver is implemented in hardware. The CIR receiver samples the input signal on
the programmable frequency and records these samples into RX FIFO when one CIR signal is found on the air.
The CIR receiver uses Run-Length Code (RLC) to encode pulse width. The encoded data is buffered in a 64
levels and 8-bit width RX FIFO; the MSB bit is used to record the polarity of the receiving CIR signal. The highlevel is represented as ‘1’ and the low level is represented as ‘0’. The rest 7 bits are used for the length of RLC.
The maximum length is 128. If the duration of one level (high or low level) is more than 128, another byte isused.
In the air, there is always some noise. One threshold can be set to filter the noise to reduce system loading andimprove the system stability.

7.4.2. CIR Receiver Register List
Module Name

Base Address

CIR

0x01F02000

Register Name

OffsetDescription

CIR_CTL

0x00

CIR Control Register

CIR_RXCTL

0x10

CIR Receiver Configure Register

CIR_RXFIFO

0x20

CIR Receiver FIFO Register

CIR_RXINT

0x2C

CIR Receiver Interrupt Control Register

CIR_RXSTA

0x30

CIR Receiver Status Register

CIR_CONFIG

0x34

CIR Configure Register

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7.4.3. CIR Receiver Register Description
7.4.3.1. CIR Receiver Control Register(Default Value: 0x00000000)
Offset: 0x0000

Register Name: CIR_CTL

Bit

R/W

Default/Hex

Description

31:9

/

/

/

8

/

/

/

7:6

/

/

/

5:4

R/W

0

CIR ENABLE
00~10: Reserved
11: CIR mode enable

3:2

/

/

/.

0

RXEN
Receiver Block Enable
0: Disable
1: Enable

0GEN
Global Enable
A disable on this bit overrides any other block or channel enables andflushes all FIFOs.
0: Disable
1: Enable

1

0

R/W

R/W

7.4.3.2. CIR Receiver Configure Register(Default Value: 0x00000004)
Offset: 0x0010

Register Name: CIR_RXCTL

Bit

R/W

Default/Hex

Description

31:3

/

/

/

2

R/W

1

RPPI
Receiver Pulse Polarity Invert
0: Not invert receiver signal
1: Invert receiver signal

1:0

/

/

/

7.4.3.3. CIR Receiver FIFO Register(Default Value: 0x00000000)
Offset: 0x0020

Register Name: CIR_RXFIFO

Bit

R/W

Default/Hex

Description

31:8

/

/

/

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7:0

R

0

Receiver Byte FIFO

7.4.3.4. CIR Receiver Interrupt Control Register(Default Value: 0x00000000)
Offset: 0x002C

Register Name: CIR_RXINT

Bit

R/W

Default/Hex

Description

31:14

/

/

/

0

RAL
RX FIFO Available Received Byte Level for interrupt and DMA request
TRIGGER_LEVEL = RAL + 1

0

DRQ_ENRX FIFO DMA Enable
0: Disable
1: Enable
When set to ‘1’, the Receiver FIFO DRQ is asserted if reaching RAL. The
DRQ is de-asserted when condition fails.

13:8

5

R/W

R/W

4

R/W

0

RAI_ENRX FIFO Available Interrupt Enable
0: Disable
1: Enable
When set to ‘1’, the Receiver FIFO IRQ is asserted if reaching RAL. The IRQ
is de-asserted when condition fails.

3:2

/

/

/

0

RPEI_EN
Receiver Packet End Interrupt Enable
0: Disable
1: Enable

0

ROI_EN
Receiver FIFO Overrun Interrupt Enable
0: Disable
1: Enable

1

0

R/W

R/W

7.4.3.5. CIR Receiver Status Register(Default Value: 0x00000000)
Offset: 0x0030

Register Name: CIR_RXSTA

Bit

R/W

Default/Hex

Description

31:15

/

/

/

0

RAC
RX FIFO Available Counter0: No available data in RX FIFO
1: 1 byte available data in RX FIFO

14:8

R

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2: 2 byte available data in RX FIFO…
64: 64 byte available data in RX FIFO

7

R

0x0

STAT
Status of CIR
0x0 – Idle
0x1 – busy

6:5

/

/

/

4

R/W

0

RA
RX FIFO Available
0: RX FIFO not available according its level
1: RX FIFO available according its level
This bit is cleared by writing a ‘1’.

3:2

/

/

/

0

RPE
Receiver Packet End Flag
0: STO was not detected. In CIR mode, one CIR symbol is receiving or notdetected.
1: STO field or packet abort symbol (7’b0000,000 and 8’b0000,0000 for
MIR and FIR) is detected. In CIR mode, one CIR symbol is received.
This bit is cleared by writing a ‘1’.

0

ROI
Receiver FIFO Overrun
0: Receiver FIFO not overrun
1: Receiver FIFO overrun
This bit is cleared by writing a ‘1’.

1

0

R/W

R/W

7.4.3.6. CIR Receiver Configure Register(Default Value: 0x00001828)
Offset: 0x0034

Register Name: CIR_RCR

Bit

R/W

Default/Hex

Description

31

/

/

/

30:25

/

/

/

0x0

SCS2
Bit2 of Sample Clock Select for CIR
This bit is defined by SCS bits below.

0x0

ATHC
Active Threshold Control for CIR
0x0 –ATHR in Unit of (Sample Clock)
0x1 –ATHR in Unit of (128*Sample Clocks)

0x0

ATHR
Active Threshold for CIR
These bits control the duration of CIR from Idle to Active State. The

24

23

22:16

R/W

R/W

R/W

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duration can be calculated by ((ATHR + 1)*(ATHC? Sample Clock:
128*Sample Clock)).

15:8

7:2

R/W

R/W

0x18

ITHR
Idle Threshold for CIR
The Receiver uses it to decide whether the CIR command has been
received. If there is no CIR signal on the air, the receiver is staying in IDLE
status. One active pulse will bring the receiver from IDLE status to
Receiving status. After the CIR is end, the inputting signal will keep the
specified level (high or low level) for a long time. The receiver can use thisidle signal duration to decide that it has received the CIR command. The
corresponding flag is asserted. If the corresponding interrupt is enable,
the interrupt line is asserted to CPU.
When the duration of signal keeps one status (high or low level) for the
specified duration ( (ITHR + 1)*128 sample_clk ), this means that theprevious CIR command has been finished.

0xa

NTHR
Noise Threshold for CIR
When the duration of signal pulse (high or low level) is less than NTHR,
the pulse is taken as noise and should be discarded by hardware.
0: all samples are recorded into RX FIFO
1: If the signal is only one sample duration, it is taken as noise anddiscarded.
2: If the signal is less than (<=) two sample duration, it is taken as noiseand discarded.
…
61: if the signal is less than (<=) sixty-one sample duration, it is taken as
noise and discarded.
SCS
Sample Clock Select for CIR

1:0

R/W

0

A64 User Manual(Revision 1.0)

SCS2

SCS[1]

SCS[0]

Sample Clock

0

0

0

ir_clk/64

001

ir_clk/128

0

1

0

ir_clk/256

0

1

1

ir_clk/512

1

0

0

ir_clk1

0

1

Reserved1

10

Reserved

1

1

1

Reserved

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7.5. USB
7.5.1. USB Controller Block Diagram

USB-OTG
USB0 Controller

Port Control

EHCI

OHCI

USB2.0
PHY

UTMI+

HCI0

OHCI

UTMI+

HSIC

PHY Switch

EHCI

DP

Data
Port Control

System AHB Bus

USB-OTG-HCISIE Switch

DM

StrobeDM
USB2.0PHY

DP

Figure 7-7. USB Controller Block DIagram

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7.5.2. USB OTG
7.5.2.1. Overview
The USB OTG is a Dual-Role Device controller, which supports both device and host functions which can also be
configured as a Host-only or Device-only controller, fully compliant with the USB 2.0 Specification. It can
support high-speed (HS, 480-Mbps), full-speed (FS, 12-Mbps), and low-speed (LS, 1.5-Mbps) transfers in Hostmode. It can support high-speed (HS, 480-Mbps), and full-speed (FS, 12-Mbps) in Device mode. Standard USB
transceiver can be used through its UTMI+PHY Level3 interface. The UTMI+PHY interface is bidirectional with
8-bit data bus. For saving CPU bandwidth, USB-OTG DMA interface can support external DMA controller totake care of the data transfer between the memory and USB-OTG FIFO. The USB-OTG core also supports USB
power saving functions.
The USB2.0 OTG controller has following features:
 Complies with USB 2.0 Specification
 Support High-Speed (HS, 480-Mbps), Full-Speed (FS, 12-Mbps),and Low-Speed(LS,1.5-Mbps) in Host modeand support High-Speed(HS,480-Mbps),Full-Speed(FS,12-Mbps) in device mode Supports bi-directional endpoint0 for Control transfer
 Supports up to 10 User-Configurable Endpoints for Bulk , Isochronous and Interrupt bi-directional transfers(Endpoint1, Endpoint2, Endpoint3, Endpoint4, Endpoint5)
 Supports up to 8KB FIFO for EPs
 Support High-bandwidth Isochronous & Interrupt transfers
 Automated splitting/combining of packets for Bulk transfers
 Supports point-to-point and point-to-multipoint transfer in both Host and Peripheral mode
 Include automatic ping capabilities
 Soft connect/disconnect function
 Performs all transaction scheduling in hardware Supports the UTMI+ Level 3 interface . The 8-bit bidirectional data buses are used
 Supports point-to-point and point-to-multipoint transfer in both Host and Peripheral mode
 Power Optimization and Power Management capabilities
 Include interface to an external Normal DMA controller for every EPs

7.5.3. USB Host
7.5.3.1. Overview
USB Host Controller is fully compliant with the USB 2.0 specification, Enhanced Host Controller Interface (EHCI)
Specification, Revision 1.0, and the Open Host Controller Interface (OHCI) Specification Release 1.0a. The
controller supports high-speed, 480-Mbps transfers (40 times faster than USB 1.1 full-speed mode) using an
EHCI Host Controller, as well as full and low speeds through one or more integrated OHCI Host Controllers.

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The USB host controller includes the following features: Supports industry-standard AMBA High-Performance Bus (AHB) and it is fully compliant with the AMBA
Specification, Revision 2.0.
 Supports 32-bit Little Endian AMBA AHB Slave Bus for Register Access.
 Supports 32-bit Little Endian AMBA AHB Master Bus for Memory Access.
 Including an internal DMA Controller for data transfer with memory.
 Complies with Enhanced Host Controller Interface (EHCI) Specification, Version 1.0, and the Open Host
Controller Interface (OHCI) Specification, Version 1.0a.
 Supports High-Speed (HS, 480-Mbps), Full-Speed (FS, 12-Mbps), and Low-Speed (LS, 1.5-Mbps) Device.
 Supports the UTMI+ Level 3 interface . The 8-bit bidirectional data buses are used.
 Supports only 1 USB Root Port shared between EHCI and OHCI.

7.5.3.2. USB Host Timing Diagram
Please refer USB2.0 Specification, Enhanced Host Controller Interface (EHCI) Specification, Version 1.0, and theOpen Host Controller Interface (OHCI) Specification, Version 1.0a.

7.5.3.3. USB Host Register List
Module Name

Base Address

USB_HCI1

0x01C1B000

Register Name

OffsetDescription
EHCI Capability Register

E_CAPLENGTH

0x000

EHCI Capability register Length Register

E_HCIVERSION

0x002

EHCI Host Interface Version Number Register

E_HCSPARAMS

0x004

EHCI Host Control Structural Parameter Register

E_HCCPARAMS

0x008

EHCI Host Control Capability Parameter Register

E_HCSPPORTROUTE

0x00c

EHCI Companion Port Route Description
EHCI Operational Register

E_USBCMD

0x010

EHCI USB Command Register

E_USBSTS

0x014

EHCI USB Status Register

E_USBINTR

0x018

EHCI USB Interrupt Enable Register

E_FRINDEX

0x01c

EHCI USB Frame Index Register

E_CTRLDSSEGMENT

0x020

EHCI 4G Segment Selector Register

E_PERIODICLISTBASE

0x024

EHCI Frame List Base Address Register

E_ASYNCLISTADDR

0x028

EHCI Next Asynchronous List Address Register

E_CONFIGFLAG

0x050

EHCI Configured Flag Register

E_PORTSC

0x054

EHCI Port Status/Control Register
OHCI Control and Status Partition Register

O_HcRevision

A64 User Manual(Revision 1.0)

0x400

OHCI Revision Register

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O_HcControl

0x404

OHCI Control Register

O_HcCommandStatus

0x408

OHCI Command Status Register

O_HcInterruptStatus

0x40c

OHCI Interrupt Status Register

O_HcInterruptEnable

0x410

OHCI Interrupt Enable Register

O_HcInterruptDisable

0x414

OHCI Interrupt Disable Register
OHCI Memory Pointer Partition Register

O_HcHCCA

0x418

OHCI HCCA Base

O_HcPeriodCurrentED

0x41c

OHCI Period Current ED Base

O_HcControlHeadED

0x420

OHCI Control Head ED Base

O_HcControlCurrentED

0x424

OHCI Control Current ED BaseO_HcBulkHeadED

0x428

OHCI Bulk Head ED BaseO_HcBulkCurrentED

0x42c

OHCI Bulk Current ED Base

O_HcDoneHead

0x430

OHCI Done Head BaseOHCI Frame Counter Partition Register

O_HcFmInterval

0x434

OHCI Frame Interval Register

O_HcFmRemaining

0x438

OHCI Frame Remaining Register

O_HcFmNumber

0x43c

OHCI Frame Number Register

O_HcPerioddicStart

0x440

OHCI Periodic Start Register

O_HcLSThreshold

0x444

OHCI LS Threshold Register
OHCI Root Hub Partition Register

O_HcRhDescriptorA

0x448

OHCI Root Hub Descriptor Register A

O_HcRhDesriptorB

0x44c

OHCI Root Hub Descriptor Register B

O_HcRhStatus

0x450

OHCI Root Hub Status Register

O_HcRhPortStatus

0x454

OHCI Root Hub Port Status Register

7.5.3.4. EHCI Register Description

7.5.3.4.1. EHCI Identification Register(Default Value: Implementation Dependent)
Offset: 0x0000
Bit

7:0

R/W

R

Register Name: CAPLENGTH
Default/Hex

Description

0x10

CAPLENGTH
The value in these bits indicates an offset to add to register base to findthe beginning of the Operational Register Space.

7.5.3.4.2. EHCI Host Interface Version Number Register(Default Value: 0x0100)
Offset: 0x0002

Register Name: HCIVERSION

Bit

R/W

Default/Hex

Description

15:0

R

0x0100

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This is a 16-bits register containing a BCD encoding of the EHCI revision
number supported by this host controller. The most significant byte ofthis register represents a major revision and the least significant byte is
the minor revision.

7.5.3.4.3. EHCI Host Control Structural Parameter Register(Default Value: Implementation Dependent)
Offset: 0x0004
Bit
31:24

23:20
19:16

15:12

11:8

R/W
/

R
/

R

R

Register Name: HCSPARAMS
Default/Hex

Description

0

Reserved.
These bits are reserved and should be set to zero.

0

Debug Port NumberThis register identifies which of the host controller ports is the debug
port. The value is the port number (one based) of the debug port.
This field will always be ‘0’.

0

Reserved.
These bits are reserved and should be set to zero.

0

Number of Companion Controller (N_CC)
This field indicates the number of companion controllers associated withthis USB2.0 host controller. A zero in this field indicates there are nocompanion host controllers. And a value larger than zero in this fieldindicates there are companion USB1.1 host controller(s).
This field will always be ‘0’.

0

Number of Port per Companion Controller(N_PCC)
This field indicates the number of ports supported per companion hostcontroller host controller. It is used to indicate the port routing
configuration to system software.
This field will always fix with ‘0’.
Port Routing Rules
This field indicates the method used by this implementation for how all
ports are mapped to companion controllers. The value of this field has
the following interpretation:
Value

Meaning

0

The first N_PCC ports are routed to the lowest numberedfunction companion host controller, the next N_PCC port
are routed to the next lowest function companion
controller, and so on.

1
7
6:4

R
/

The port routing is explicitly enumerated by the first
N_PORTS elements of the HCSP-PORTTOUTE array.

0This field will always be ‘0’.

0

Reserved.
These bits are reserved and should be set to zero.

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3:0

R

1

N_PORTSThis field specifies the number of physical downstream ports
implemented on this host controller. The value of this field determines
how many port registers are addressable in the Operational Register
Space. Valid values are in the range of 0x1 to 0x0f.
This field is always 1.

7.5.3.4.4. EHCI Host Control Capability Parameter Register(Default Value: Implementation Dependent)
Offset: 0x0008
Bit
31:16

15:18

7:4
3

2

1

R/W
/

R

Register Name: HCCPARAMS
Default/Hex

Description

0

Reserved
These bits are reserved and should be set to zero.

0

EHCI Extended Capabilities Pointer (EECP)This optional field indicates the existence of a capabilities list. A value of
00b indicates no extended capabilities are implemented. A non-zerovalue in this register indicates the offset in PCI configuration space of thefirst EHCI extended capabiliby. The pointer value must be 40h or greater if
implemented to maintain to consistency of the PCI header defined forthis calss of device.
The value of this field is always ‘00b’.

R

Isochronous Scheduling Threshold
This field indicates, relative to the current position of the executing hostcontroller, where software can reliably update the isochronous schedule.
When bit[7] is zero, the value of the least significant 3 bits indicates thenumber of micro-frames a host controller can hold a set of isochronous
data structures(one or more) before flushing the state. When bit[7] is aone, then host software assumes the host controller may cache anisochronous data structure for an entire frame.

R

Reserved
These bits are reserved and should be set to zero.

0R

Asynchronous Schedule Park Capability
If this bit is set to a one, then the host controller supports the parkfeature for high-speed queue heads in the Asynchronous Schedule. The
feature can be disabled or enabled and set to a specific level by using the
Asynchronous Schedule Park Mode Enable and Asynchronous SchedulePark Mode Count fields in the USBCMD register.

R

Programmable Frame List Flag
If this bit is set to a zero, then system software must use a frame list
length of 1024 elements with this host controller.The USBCMD register
Frame List Size field is a read-only register and should be set to zero.
If set to 1,then system software can specify and use the frame list in the
USBCMD register Frame List Size field to cofigure the host controller.

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The frame list must always aligned on a 4K page boundary.This
requirement ensures that the frame list is always physically contiguous.

0

R

Reserved
These bits are reserved for future use and should return a value of zero
when read.

0

7.5.3.4.5. EHCI Companion Port Route Description (Default Value: UNDEFINED)
Offset: 0x000C
Bit

31:0

R/W

Register Name: HCSP-PORTROUTE
Default/Hex

Description
HCSP-PORTROUTE
This optional field is valid only if Port Routing Rules field in HCSPARAMS
register is set to a one.
This field is used to allow a host controller implementation to explicitly
describe to which companion host controller each implemented port ismapped. This field is a 15-element nibble array (each 4 bit is one arrayelement). Each array location corresponds one-to-one with a physicalport provided by the host controller (e.g. PORTROUTE [0] corresponds tothe first PORTSC port, PORTROUTE [1] to the second PORTSC port, etc.).
The value of each element indicates to which of the companion hostcontrollers this port is routed. Only the first N_PORTS elements have valid
information. A value of zero indicates that the port is routed to the lowest
numbered function companion host controller. A value of one indicatesthat the port is routed to the next lowest numbered function companion
host controller, and so on.

R

7.5.3.4.6. EHCI USB Command Register (Default Value: 0x00080000,0x00080B00 if Asynchronous SchedulePark Capability is a one)
Offset: 0x0010
Bit
31:24

R/W
/

Register Name: USBCMD
Default/Hex

Description

0

Reserved
These bits are reserved and should be set to zero.
Interrupt Threshold Control
The value in this field is used by system software to select the maximum
rate at which the host controller will issue interrupts. The only valid
values are defined below:

23:16

R/W

0x08

A64 User Manual(Revision 1.0)

Value

Minimum Interrupt Interval

0x00

Reserved

0x01

1 micro-frame

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0x02

2 micro-frame

0x04

4 micro-frame

0x08

8 micro-frame(default, equates to 1 ms)

0x10

16 micro-frame(2ms)

0x20

32 micro-frame(4ms)

0x40

64 micro-frame(8ms)

Any other value in this register yields undefined results.
The default value in this field is 0x08 .
Software modifications to this bit while HC Halted bit is equal to zero
results in undefined behavior.
15:12

11
10

9:8

7

6

/

R/W orR/

R/W or
R

R/W

R/W

0

Reserved
These bits are reserved and should be set to zero.

0

Asynchronous Schedule Park Mode Enable(OPTIONAL)
If the Asynchronous Park Capability bit in the HCCPARAMS register is aone, then this bit defaults to a 1 and is R/W. Otherwise the bit must be azero and is Read Only. Software uses this bit to enable or disable Park
mode. When this bit is one, Park mode is enabled. When this bit is zero,
Park mode is disabled.

0

Reserved
These bits are reserved and should be set to zero.

0

Asynchronous Schedule Park Mode Count(OPTIONAL)
Asynchronous Park Capability bit in the HCCPARAMS register is a one,
Then this field defaults to 0x3 and is W/R. Otherwise it defaults to zeroand is R. It contains a count of the number of successive transactions thehost controller is allowed to execute from a high-speed queue head on
the Asynchronous schedule before continuing traversal of the
Asynchronous schedule.
Valid value are 0x1 to 0x3.Software must not write a zero to this bit when
Park Mode Enable is a one as it will result in undefined behavior.

0Light Host Controller Reset(OPTIONAL)
This control bit is not required.
If implemented, it allows the driver to reset the EHCI controller without
affecting the state of the ports or relationship to the companion hostcontrollers. For example, the PORSTC registers should not be reset totheir default values and the CF bit setting should not go to zero (retaining
port ownership relationships).
A host software read of this bit as zero indicates the Light Host Controller
Reset has completed and it si safe for software to re-initialize the hostcontroller. A host software read of this bit as a one indicates the Light
Host

0

Interrupt on Async Advance Doorbell
This bit is used as a doorbell by software to tell the host controller toissue an interrupt the next time it advances asynchronous schedule. SoftWare must write a 1 to this bit to ring the doorbell.

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When the host controller has evicted all appropriate cached schedule
state, it sets the Interrupt on Async Advance status bit in the USBSTS. if
the Interrupt on Async Advance Enable bit in the USBINTR register is a
one then the host controller will assert an interrupt at the next interrupt
threshold.
The host controller sets this bit to a zero after it has set the Interrupt on
Async Advance status bit in the USBSTS register to a one.
Software should not write a one to this bit when the asynchronousschedule is disabled. Doing so will yield undefined results.
Asynchronous Schedule Enable
This bit controls whether the host controller skips processing the
Asynchronous Schedule. Values mean:
Bit Value

5

R/W

0

Meaning0

Do not process the Asynchronous Schedule.

1

Use the ASYNLISTADDR register to access the
Asynchronous Schedule.

The default value of this field is ‘0b’.
Periodic Schedule Enable
This bit controls whether the host controller skips processing the Periodic
Schedule. Values mean:
Bit Value

4

R/W

0

Meaning0

Do not process the Periodic Schedule.

1

Use the PERIODICLISTBASE register to access the
Periodic Schedule.

The default value of this field is ‘0b’.
Frame List Size
This field is R/W only if Programmable Frame List Flag in the HCCPARAMS
registers is set to a one. This field specifies the size of the
Frame list. The size the frame list controls which bits in the Frame Index
Register should be used for the Frame List Current index. Values mean:

3:2

1

R/W or
R

R/W

Bits

Meaning00b1024 elements(4096bytes)Default

01b

512 elements(2048byts)

10b

256 elements(1024bytes)For resource-constrained condition

11b

reserved

0

The default value is ‘00b’.

0

Host Controller ResetThis control bit is used by software to reset the host controller. The
effects of this on Root Hub registers are similar to a Chip Hardware Reset.
When software writes a one to this bit, the Host Controller resets its
internal pipelines, timers, counters, state machines, etc. to their initialvalue. Any transaction currently in progress on USB is immediately
terminated. A USB reset is not driven on downstream ports.

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All operational registers, including port registers and port state machines
are set to their initial values. Port ownership reverts to the companion
host controller(s). Software must reinitialize the host controller as
described in Section 4.1 of the CHEI Specification in order to return thehost controller to an operational state.
This bit is set to zero by the Host Controller when the reset process iscomplete. Software cannot terminate the reset process early by writing azero to this register.
Software should not set this bit to a one when the HC Halted bit in the
USBSTS register is a zero. Attempting to reset an actively running hostcontroller will result in undefined behavior.

0

R/W

0

Run/Stop
When set to a 1, the Host Controller proceeds with execution of theschedule. When set to 0, the Host Controller completes the current andany actively pipelined transactions on the USB and then halts. The Host
Controller must halt within 16 micro-frames after software clears this bit.
The HC Halted bit indicates when the Host Controller has finished its
pending pipelined transactions and has entered the stopped state.
Software must not write a one to this field unless the Host Controller is in
the Halt State.
The default value is 0x0.

7.5.3.4.7. EHCI USB Status Register (Default Value: 0x00001000)
Offset: 0x0014

Register Name: USBSTS

Bit

R/W

Default/Hex

Description

31:16

/

0

Reserved
These bits are reserved and should be set to zero.

0

Asynchronous Schedule Status
The bit reports the current real status of Asynchronous Schedule. If this
bit is a zero then the status of the Asynchronous Schedule is disabled. If
this bit is a one then the status of the Asynchronous Schedule is enabled.
The Host Controller is not required to immediately disable or enable the
Asynchronous Schedule when software transitions the Asynchronous
Schedule Enable bit in the USBCMD register. When this bit and the
Asynchronous Schedule Enable bit are the same value, the Asynchronous
Schedule is either enabled (1) or disabled (0).

0Periodic Schedule Status
The bit reports the current real status of the Periodic Schedule. If this bit
is a zero then the status of the Periodic Schedule is disabled. If this bit is a
one then the status of the Periodic Schedule is enabled. The Host
Controller is not required to immediately disable or enable the Periodic
Schedule when software transitions the Periodic Schedule Enable bit in

15

14

R

R

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the USBCMD register. When this bit and the Periodic Schedule Enable bit
are the same value, the Periodic Schedule is either enabled (1) or
disabled (0).

13

12
11:6

5

4

3

2

1

R

R
/

R/WC

R/WC

R/WC

R/WC

R/WC

0

Reclamation
This is a read-only status bit, which is used to detect an empty
asynchronous schedule.

1

HC Halted
This bit is a zero whenever the Run/Stop bit is a one. The Host Controller
Sets this bit to one after it has stopped executing as a result of the
Run/Stop bit being set to 0, either by software or by the Host Controller
Hardware (e.g. internal error).
The default value is ‘1’.

0

Reserved
These bits are reserved and should be set to zero.

0Interrupt on Async Advance
System software can force the host controller to issue an interrupt thenext time the host controller advances the asynchronous schedule bywriting a one to the Interrupt on Async Advance Doorbell bit in the
USBCMD register. This status bit indicates the assertion of that interrupt
source.

0

Host System Error
The Host Controller set this bit to 1 when a serious error occurs during ahost system access involving the Host Controller module. When this error
occurs, the Host Controller clears the Run/Stop bit in the Command
register to prevent further execution of the scheduled TDs.

0

Frame List Rollover
The Host Controller sets this bit to a one when the Frame List Index rolls
over from its maximum value to zero. The exact value at which therollover occurs depends on the frame list size. For example, if the frame
list size is 1024, the Frame Index Register rolls over every time FRINDEX[13] toggles. Similarly, if the size is 512, the Host Controller sets this bit toa one every time FRINDEX [12] toggles.

0Port Change Detect
The Host Controller sets this bit to a one when any port for which thePort Owner bit is set to zero has a change bit transition from a zero to a
one or a Force Port Resume bit transition from a zero to a one as a resultof a J-K transition detected on a suspended port. This bit will also be set
as a result of the Connect Status Chang being set to a one after system
software has relinquished ownership of a connected port by writing a one
to a port’s Port Owner bit.

0

USB Error Interrupt(USBERRINT)
The Host Controller sets this bit to 1 when completion of USB transaction
results in an error condition(e.g. error counter underflow).If the TD on
which the error interrupt occurred also had its IOC bit set, both.

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This bit and USBINT bit are set.

0

R/WC

0

USB Interrupt(USBINT)The Host Controller sets this bit to a one on the completion of a USB
transaction, which results in the retirement of a Transfer Descriptor that
had its IOC bit set.
The Host Controller also sets this bit to 1 when a short packet is detected(actual number of bytes received was less than the expected number ofbytes)

7.5.3.4.8. EHCI USB Interrupt Enable Register (Default Value: 0x00000000)
Offset: 0x0018
Bit
31:6

5

4

3

2

1

0

R/W
/

R/W

R/W

R/W

R/W

R/W

R/W

Register Name: USBINTR
Default/Hex

Description

0

Reserved
These bits are reserved and should be zero.

0Interrupt on Async Advance Enable
When this bit is 1, and the Interrupt on Async Advance bit in the USBSTS
register is 1, the host controller will issue an interrupt at the next
interrupt threshold. The interrupt is acknowledged by software clearing
the Interrupt on Async Advance bit.

0

Host System Error Enable
When this bit is 1, and the Host System Error Status bit in the USBSTS
register is 1, the host controller will issue an interrupt. The interrupt is
acknowledged by software clearing the Host System Error bit.

0

Frame List Rollover Enable
When this bit is 1, and the Frame List Rollover bit in the USBSTS register is
1, the host controller will issue an interrupt. The interrupt is
acknowledged by software clearing the Frame List Rollover bit.

0

Port Change Interrupt Enable
When this bit is 1, and the Port Chang Detect bit in the USBSTS register is
1, the host controller will issue an interrupt. The interrupt is
acknowledged by software clearing the Port Chang Detect bit.

0

USB Error Interrupt Enable
When this bit is 1, and the USBERRINT bit in the USBSTS register is 1,thehost controller will issue an interrupt at the next interrupt threshold.
The interrupt is acknowledged by software clearing the USBERRINT bit.

0

USB Interrupt Enable
When this bit is 1, and the USBINT bit in the USBSTS register is 1,the hostcontroller will issue an interrupt at the next interrupt threshold.
The interrupt is acknowledged by software clearing the USBINT bit

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7.5.3.4.9. EHCI Frame Index Register (Default Value: 0x00000000)
Offset: 0x001C
Bit
31:14

Register Name: FRINDEXR/W/

Default/Hex

Description

0

Reserved
These bits are reserved and should be zero.
Frame Index
The value in this register increment at the end of each time frame(e.g. micro-frame).Bits[N:3] are used for the Frame List current index. It
Means that each location of the frame list is accessed 8 times(frames orMicro-frames) before moving to the next index. The following illustrates
Values of N based on the value of the Frame List Size field in the USBCMD
register.

13:0

R/W

0

USBCMD[Frame List Size]

Number Elements

N

00b

1024

12

01b

512

11

10b

256

10

11b

Reserved

Note: This register must be written as a DWord. Byte writes produce undefined results.

7.5.3.4.10.

EHCI Periodic Frame List Base Address Register (Default Value: Undefined)

Offset: 0x0024
Bit

31:12

11:0

R/W

Register Name: PERIODICLISTBASEDefault/Hex

Description

R/W

Base Address
These bits correspond to memory address signals [31:12], respectively.
This register contains the beginning address of the Periodic Frame List in
the system memory.
System software loads this register prior to starting the schedule
execution by the Host Controller. The memory structure referenced bythis physical memory pointer is assumed to be 4-K byte aligned. The
contents of this register are combined with the Frame Index Register(FRINDEX) to enable the Host Controller to step through the Periodic
Frame List in sequence.

/

Reserved
Must be written as 0x0 during runtime, the values of these bits are
undefined.

Note: Writes must be Dword Writes.

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7.5.3.4.11.

EHCI Current Asynchronous List Address Register (Default Value: Undefined)

Offset: 0x0028
Bit

31:5

4:0

Register Name: ASYNCLISTADDR

R/W

R/W

/

Default/Hex

Description/

Link Pointer (LP)This field contains the address of the next asynchronous queue head to
be executed.
These bits correspond to memory address signals [31:5], respectively.

/

Reserved
These bits are reserved and their value has no effect on operation.
Bits in this field cannot be modified by system software and will always
return a zero when read.

Note: Write must be DWord Writes.

7.5.3.4.12.

EHCI Configure Flag Register (Default Value: 0x00000000)

Offset: 0x0050
Bit
31:1

Register Name: CONFIGFLAG

R/W/

Default/Hex

Description

0

Reserved
These bits are reserved and should be set to zero.
Configure Flag(CF)Host software sets this bit as the last action in its process of configuring
the Host Controller. This bit controls the default port-routing control logic
as follow:

0

R/W

0

Value

Meaning0Port routing control logic default-routs each port to an
implementation dependent classic host controller.

1

Port routing control logic default-routs all ports to this hostcontroller.

The default value of this field is ‘0’.

Note: This register is not use in the normal implementation.

7.5.3.4.13.

EHCI Port Status and Control Register (Default Value: 0x00002000(w/PPC set toone);0x00003000(w/PPC set to a zero))

Offset: 0x0054

Register Name: PORTSC

Bit

R/W

Default/Hex

Description

31:22

/

0

Reserved

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These bits are reserved for future use and should return a value of zero
when read.

21

20

R/W

R/W

0

Wake on Disconnect Enable(WKDSCNNT_E)
Writing this bit to a one enables the port to be sensitive to device
disconnects as wake-up events.
This field is zero if Port Power is zero.
The default value in this field is ‘0’.

0

Wake on Connect Enable(WKCNNT_E)
Writing this bit to a one enable the port to be sensitive to device
connects as wake-up events.
This field is zero if Port Power is zero.
The default value in this field is ‘0’.
Port Test Control
The value in this field specifies the test mode of the port. The encoding of
the test mode bits are as follow:

19:16

15:14

13

12
11:10

R/W

R/W

R/W

/
R

Bits

Test Mode

0000b

The port is NOT operating in a test mode.

0001b

Test J_STATE

0010b

Test K_STATE

0011b

Test SE0_NAK

0100b

Test Packet

0101b

Test FORCE_ENABLE

0110b1111b

Reserved

0

The default value in this field is ‘0000b’.

0

Reserved
These bits are reserved for future use and should return a value of zero
when read.

1

Port Owner
This bit unconditionally goes to a 0b when the Configured bit in the
CONFIGFLAG register makes a 0b to 1b transition. This bit unconditionallygoes to 1b whenever the Configured bit is zero.
System software uses this field to release ownership of the port toselected host controller (in the event that the attached device is not ahigh-speed device).Software writes a one to this bit when the attacheddevice is not a high-speed device. A one in this bit means that acompanion host controller owns and controls the port.
Default Value = 1b.

0

Reserved
These bits are reserved for future use and should return a value of zero
when read.

0Line Status
These bits reflect the current logical levels of the D+ (bit11) and D-(bit10)

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signal lines. These bits are used for detection of low-speed USB devices
prior to port reset and enable sequence. This read only field is valid only
when the port enable bit is zero and the current connect status bit is set
to a one.
The encoding of the bits are:Bit[11:10]

USB State

Interpretation

00b

SE0

Not Low-speed device, perform EHCI
reset.

10b

J-stateNot Low-speed device, perform EHCI
reset.

01b

K-stateLow-speed device, release ownership of
port.

11b

Undefined

Not Low-speed device, perform EHCI
reset.

This value of this field is undefined if Port Power is zero.

9

8

7

/

R/W

R/W

0

Reserved
This bit is reserved for future use, and should return a value of zero when
read.

0

Port Reset
1=Port is in Reset. 0=Port is not in Reset. Default = 0.
When software writes a one to this bit (from a zero), the bus reset
sequence as defined in the USB Specification Revision 2.0 is started.
Software writes a zero to this bit to terminate the bus reset sequence.
Software must keep this bit at a one long enough to ensure the reset
sequence, as specified in the USB Specification Revision 2.0, completes.
Notes: when software writes this bit to a one , it must also write a zero to
the Port Enable bit.
Note that when software writes a zero to this bit there may be a delay
before the bit status changes to a zero. The bit status will not read as azero until after the reset has completed. If the port is in high-speed mode
after reset is complete, the host controller will automatically enable thisport (e.g. set the Port Enable bit to a one). A host controller mustterminate the reset and stabilize the state of the port within 2
milliseconds of software transitioning this bit from a one to a zero. For
example: if the port detects that the attached device is high-speed duringreset, then the host controller must have the port in the enabled statewith 2ms of software writing this bit to a zero.
The HC Halted bit in the USBSTS register should be a zero before software
attempts to use this bit. The host controller may hold Port Reset asserted
to a one when the HC Halted bit is a one.
This field is zero if Port Power is zero.

0

Suspend
Port Enabled Bit and Suspend bit of this register define the port states asfollows:

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Bits[Port Enables, Suspend]

Port State0x

Disable10

Enable11

Suspend

When in suspend state, downstream propagation of data is blocked on
this port, except for port reset. The blocking occurs at the end of thecurrent transaction, if a transaction was in progress when this bit was
written to 1. In the suspend state, the port is sensitive to resume
detection. Not that the bit status does not change until the port issuspend and that there may be a delay in suspending a port if there is atransaction currently in progress on the USB.
A write of zero to this bit is ignored by the host controller. The hostcontroller will unconditionally set this bit to a zero when:① Software sets the Force Port Resume bit to a zero(from a one).
② Software sets the Port Reset bit to a one(from a zero).
If host software sets this bit to a one when the port is not enabled(i.e.
Port enabled bit is a zero), the results are undefined.
This field is zero if Port Power is zero.
The default value in this field is ‘0’.

6
5

R/W
R/WC

0

Force Port Resume
1 = Resume detected/driven on port. 0 = No resume (K-state) detected/
driven on port. Default = 0.
This functionality defined for manipulating this bit depends on the valueof the Suspend bit. For example, if the port is not suspend and softwaretransitions this bit to a one, then the effects on the bus are undefined.
Software sets this bit to a 1 drive resume signaling. The Host Controller
sets this bit to a 1 if a J-to-K transition is detected while the port is in the
Suspend state. When this bit transitions to a one because a J-to-Ktransition is detected, the Port Change Detect bit in the USBSTS register isalso set to a one. If software sets this bit to a one, the host controller
must not set the Port Change Detect bit.
Note that when the EHCI controller owns the port, the resume sequence
follows the defined sequence documented in the USB Specification
Revision 2.0. The resume signaling (Full-speed ‘K’) is driven on the port aslong as this remains a one. Software must appropriately time the Resume
and set this bit to a zero when the appropriate amount of time has
elapsed. Writing a zero (from one) causes the port to return high-speed
mode (forcing the bus below the port into a high-speed idle). This bit willremain a one until the port has switched to high-speed idle. The hostcontroller must complete this transition within 2 milliseconds of softwaresetting this bit to a zero.
This field is zero if Port Power is zero.

0Over-current Change
Default = 0. This bit gets set to a one when there is a change to

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Over-current Active. Software clears this bit by writing a one to this bit
position.

4

3

2

1

0

R

R/WC

R/W

R/WC

R

0

Over-current Active
0 = This port does not have an over-current condition. 1 = This port
currently has an over-current condition. This bit will automaticallytransition from a one to a zero when the over current condition isremoved.
The default value of this bit is ‘0’.

0Port Enable/Disable Change
Default = 0. 1 = Port enabled/disabled status has changed. 0 = No change.
For the root hub, this bit gets set to a one only when a port is disabled
due to the appropriate conditions existing at the EOF2 point (See Chapter
11 of the USB Specification for the definition of a Port Error). Software
clears this bit by writing a 1 to it.
This field is zero if Port Power is zero.

0

Port Enabled/Disabled
1=Enable, 0=Disable. Ports can only be enabled by the host controller as apart of the reset and enable. Software cannot enable a port by writing a
one to this field. The host controller will only set this bit to a one when
the reset sequence determines that the attached device is a high-speed
device.
Ports can be disabled by either a fault condition(disconnect event orother fault condition) or by host software. Note that the bit status does
not change until the port state actually changes. There may be a delay indisabling or enabling a port due to other host controller and bus events.
When the port is disabled, downstream propagation of data is blocked on
this port except for reset.
The default value of this field is ‘0’.
This field is zero if Port Power is zero.

0

Connect Status Change
1=Change in Current Connect Status, 0=No change, Default=0.
Indicates a change has occurred in the port’s Current Connect Status. The
host controller sets this bit for all changes to the port device connect
status, even if system software has not cleared an existing connect statuschange. For example, the insertion status changes twice before system
software has cleared the changed condition, hub hardware will be“setting” an already-set bit. Software sets this bit to 0 by writing a 1 to it.
This field is zero if Port Power is zero.

0

Current Connect Status
Device is present on port when the value of this field is a one, and nodevice is present on port when the value of this field is a zero. This value
reflects the current state of the port, and may not correspond directly tothe event that caused the Connect Status Change(Bit 1) to be set.
This field is zero if Port Power zero.

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Note: This register is only reset by hardware or in response to a host controller reset.

7.5.3.5. OHCI Register Description

7.5.3.5.1. HcRevision Register(Default Value: 0x00000010)
Offset: 0x400

Register Name: HcRevision

Read/Write
Bit

HCD

HC

Default/Hex

Description

31:8

/

/

0x00

Reserved

0x10

Revision
This read-only field contains the BCD representation of the version of
the HCI specification that is implemented by this HC. For example, avalue of 0x11 corresponds to version 1.1. All of the HC implementations
that are compliant with this specification will have a value of 0x10.

7:0

R

R

7.5.3.5.2. HcControl Register(Default Value: 0x00000000)
Register Name: HcRevision

Offset: 0x404
Read/Write
Bit

HCD

HC

Default/Hex

Description

31:11

/

/

0x00

Reserved

0x0

RemoteWakeupEnable
This bit is used by HCD to enable or disable the remote wakeup feature
upon the detection of upstream resume signaling. When this bit is set
and the ResumeDetected bit in HcInterruptStatus is set, a remote
wakeup is signaled to the host system. Setting this bit has no impact on
the generation of hardware interrupt.

0x0

RemoteWakeupConnected
This bit indicates whether HC supports remote wakeup signaling. If
remote wakeup is supported and used by the system, it is the
responsibility of system firmware to set this bit during POST. HC clear
the bit upon a hardware reset but does not alter it upon a software
reset. Remote wakeup signaling of the host system is host-bus-specificand is not described in this specification.

0x0

InterruptRoutingThis bit determines the routing of interrupts generated by events

10

9
8

R/W

R/W
R/W

R

R/W
R

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registered in HcInterruptStatus. If clear, all interrupt are routed to thenormal host bus interrupt mechanism. If set interrupts are routed to the
System Management Interrupt. HCD clears this bit upon a hardware
reset, but it does not alter this bit upon a software reset. HCD uses thisbit as a tag to indicate the ownership of HC.
HostControllerFunctionalState for USB

7:6

5

4

3

R/W

R/W

R/W

R/W

R/W

R

R

R

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00b

USBReset

01b

USBResume

10b

USBOperational

11b

USBSuspend

0x0

A transition to USBOperational from another state causes SOF
generation to begin 1 ms later. HCD may determine whether HC has
begun sending SOFs by reading the StartoFrame field of
HcInterruptStatus.
This field may be changed by HC only when in the USBSUSPEND state.
HC may move from the USBSUSPEND state to the USBRESUME state
after detecting the resume signaling from a downstream port.
HC enters USBSUSPEND after a software reset, whereas it enters
USBRESET after a hardware reset. The latter also resets the Root
Hub and asserts subsequent reset signaling to downstream ports.

0x0

BulkListEnable
This bit is set to enable the processing of the Bulk list in the next
Frame. If cleared by HCD, processing of the Bulk list does not occur after
the next SOF. HC checks this bit whenever it determines to process thelist. When disabled, HCD may modify the list. If HcBulkCurrentED ispointing to an ED to be removed, HCD must advance the pointer by
updating HcBulkCurrentED before re-enabling processing of the list.

0x0

ControlListEnable
This bit is set to enable the processing of the Control list in the next
Frame. If cleared by HCD, processing of the Control list does not occur
after the next SOF. HC must check this bit whenever it determines toprocess the list. When disabled, HCD may modify the list. If
HcControlCurrentED is pointing to an ED to be removed, HCD must
advance the pointer by updating HcControlCurrentED before
re-enabling processing of the list.

0x0

IsochronousEnable
This bit is used by HCD to enable/disable processing of isochronous EDs.
While processing the periodic list in a Frame, HC checks the status of
this bit when it finds an Isochronous ED (F=1). If set (enabled), HC
continues processing the EDs. If cleared (disabled), HC halts processingof the periodic list (which now contains only isochronous EDs) andbegins processing the Bulk/Control lists.
Setting this bit is guaranteed to take effect in the next Frame (not thecurrent Frame).

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2

R/W

R

PeriodicListEnable
This bit is set to enable the processing of periodic list in the next Frame.
If cleared by HCD, processing of the periodic list does not occur after the
next SOF. HC must check this bit before it starts processing the list.

0x0

ControlBulkServiceRatio
This specifies the service ratio between Control and Bulk EDs. Before
processing any of the nonperiodic lists, HC must compare the ratio
specified with its internal count on how many nonempty Control EDs
have been processed, in determining whether to continue serving
another Control ED or switching to Bulk EDs. The internal count will be
retained when crossing the frame boundary. In case of reset, HCD is
responsible for restoring this value.
CBSR

1:0

R/W

R

0x0

No. of Control EDs Over Bulk EDs Served

0

1:1

1

2:1

2

3:1

3

4:1

The default value is 0x0.

7.5.3.5.3. HcCommandStatus Register(Default Value: 0x00000000)
Offset: 0x408

Register Name: HcCommandStatus

Read/Write
Bit

HCD

HC

Default/Hex

Description

31:18

/

/

0x0

Reserved

17:16

R

R/W

0x0

SchedulingOverrunCount
These bits are incremented on each scheduling overrun error. It is
initialized to 00b and wraps around at 11b. This will be incremented
when a scheduling overrun is detected even if SchedulingOverrun in
HcInterruptStatus has already been set. This is used by HCD to monitor
any persistent scheduling problem.

15:4

/

/

0x0

Reserved

0x0

OwershipChangeRequest
This bit is set by an OS HCD to request a change of control of the HC.
When set HC will set the OwnershipChange field in HcInterruptStatus.
After the changeover, this bit is cleared and remains so until the next
request from OS HCD.

0x0

BulklListFilled
This bit is used to indicate whether there are any TDs on the Bulk list. It
is set by HCD whenever it adds a TD to an ED in the Bulk list.
When HC begins to process the head of the Bulk list, it checks BLF. As
long as BulkListFilled is 0, HC will not start processing the Bulk list. If

3

2

R/W

R/W

R/W

R/W

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BulkListFilled is 1, HC will start processing the Bulk list and will set BF to
0. If HC finds a TD on the list, then HC will set BulkListFilled to 1 causing
the Bulk list processing to continue. If no TD is found on the Bulk list,
and if HCD does not set BulkListFilled, then BulkListFilled will still be 0
when HC completes processing the Bulk list and Bulk list processing will
stop.

1

0

R/W

R/W

R/W

R/E

0x0

ControlListFilled
This bit is used to indicate whether there are any TDs on the Control list.
It is set by HCD whenever it adds a TD to an ED in the Control list.
When HC begins to process the head of the Control list, it checks CLF. As
long as ControlListFilled is 0, HC will not start processing the Control list.
If CF is 1, HC will start processing the Control list and will set
ControlListFilled to 0. If HC finds a TD on the list, then HC will set
ControlListFilled to 1 causing the Control list processing to continue. If
no TD is found on the Control list, and if the HCD does not set
ControlListFilled, then ControlListFilled will still be 0 when HC
completes processing the Control list and Control list processing will
stop.

0x0

HostControllerResetThis bit is by HCD to initiate a software reset of HC. Regardless of thefunctional state of HC, it moves to the USBSuspend state in which mostof the operational registers are reset except those stated otherwise; e.g,
the InteruptRouting field of HcControl, and no Host bus accesses areallowed. This bit is cleared by HC upon the completion of the reset
operation. The reset operation must be completed within 10 ms. Thisbit,when set, should not cause a reset to the Root Hub and no subsequent
reset signaling should be asserted to its downstream ports.

7.5.3.5.4. HcInterruptStatus Register(Default Value: 0x00000000)
Offset: 0x40c

Register Name: HcInterruptStatus

Read/Write
Bit

HCD

HC

Default/Hex

Description

31:7

/

/

0x0

Reserved

0x0

RootHubStatusChangeThis bit is set when the content of HcRhStatus or the content of any of
HcRhPortStatus[NumberofDownstreamPort] has changed.

0x0

FrameNumberOverflow
This bit is set when the MSb of HcFmNumber (bit 15) changes value,
from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been
updated.

6

5

R/W

R/W

R/W

R/W

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4

3

2

1

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0x0

UnrecoverableError
This bit is set when HC detects a system error not related to USB. HC
should not proceed with any processing nor signaling before the systemerror has been corrected. HCD clears this bit after HC has been reset.

0x0ResumeDetected
This bit is set when HC detects that a device on the USB is asserting
resume signaling. It is the transition from no resume signaling toresume signaling causing this bit to be set. This bit is not set when HCD
sets the USBRseume state.

0x0

StartofFrame
This bit is set by HC at each start of frame and after the update of
HccaFrameNumber. HC also generates a SOF token at the same time.

0x0

WritebackDoneHead
This bit is set immediately after HC has written HcDoneHead to
HccaDoneHead. Further updates of the HccaDoneHead will not occur
until this bit has been cleared. HCD should only clear this bit after it has
saved the content of HccaDoneHead.

0x0

SchedulingOverrun
This bit is set when the USB schedule for the current Frame overruns
and after the update of HccaFrameNumber. A scheduling overrun will
also cause the SchedulingOverrunCount of HcCommandStatus to be
Incremented.

7.5.3.5.5. HcInterruptEnable Register(Default Value: 0x00000000)
Offset: 0x410

Register Name: HcInterruptEnable Register

Read/Write
Bit

HCD

HC

Default/Hex

Description

31

R/W

R

0x0

MasterInterruptEnableA ‘0’ writtern to this field is ignored by HC. A ‘1’ written to this fieldenables interrupt generation due to events specified in the other bits ofthis register. This is used by HCD as Master Interrupt Enable.

30:7

/

/

0x0

Reserved
RootHubStatusChange Interrupt Enable

6

R/W

R

0x0

0

Ignore;1

Enable interrupt generation due to Root Hub Status Change;

FrameNumberOverflow Interrupt Enable

5

R/W

R

0

Ignore;1

Enable interrupt generation due to Frame Number Over Flow;

0x0
UnrecoverableError Interrupt Enable

4

R/W

R

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0x0

0

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1

Enable interrupt generation due to Unrecoverable Error;

ResumeDetected Interrupt Enable
3

R/W

R

0x0

0

Ignore;1

Enable interrupt generation due to Resume Detected;

StartofFrame Interrupt Enable
2

R/W

R

0x0

0

Ignore;1

Enable interrupt generation due to Start of

Flame;

WritebackDoneHead Interrupt Enable
1

R/W

R

0x0

0

Ignore;1

Enable interrupt generation due to Write back Done Head;

SchedulingOverrun Interrupt Enable
0

R/W

R

0x0

0

Ignore;1

Enable interrupt generation due to Scheduling Overrun;

7.5.3.5.6. HcInterruptDisable Register(Default Value: 0x00000000)
Offset: 0x414

Register Name: HcInterruptDisable Register

Read/Write
Bit

HCD

HC

Default/Hex

Description

31

R/W

R

0x0

MasterInterruptEnable
A written ‘0’ to this field is ignored by HC. A ‘1’ written to this fielddisables interrupt generation due events specified in the other bits ofthis register. This field is set after a hardware or software reset.

30:7

/

/

0x00

Reserved
RootHubStatusChange Interrupt Disable

6

R/W

R

0x0

0

Ignore;1Disable interrupt generation due to Root Hub Status Change;

FrameNumberOverflow Interrupt Disable
5

R/W

R

0x0

0

Ignore;1Disable interrupt generation due to Frame Number Over Flow;

UnrecoverableError Interrupt Disable
4

R/W

R

0x0

0

Ignore;1Disable interrupt generation due to Unrecoverable Error;

ResumeDetected Interrupt Disable
3

R/W

R

0x0

0

Ignore;1Disable interrupt generation due to Resume Detected;

StartofFrame Interrupt Disable
2

R/W

R

0x0

0

Ignore;1Disable interrupt generation due to Start of

Flame;

WritebackDoneHead Interrupt Disable
1

R/W

R

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0x0

0

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1

Disable interrupt generation due to Write back Done Head;

SchedulingOverrun Interrupt Disable
0

R/w

R

0x0

0

Ignore;1Disable interrupt generation due to Scheduling Overrun;

7.5.3.5.7. HcHCCA Register(Default Value: 0x00000000)
Offset: 0x418

Register Name: HcHCCA

Read/Write
Bit

31:8

7:0

HCD

R/W

R

HC

R

R

Default/Hex

Description

0x0

HCCA[31:8]
This is the base address of the Host Controller Communication Area.
This area is used to hold the control structures and the Interrupt tablethat are accessed by both the Host Controller and the Host Controller
Driver.

0x0

HCCA[7:0]
The alignment restriction in HcHCCA register is evaluated by examining
the number of zeros in the lower order bits. The minimum alignment is
256 bytes, therefore, bits 0 through 7 must always return 0 when read.

7.5.3.5.8. HcPeriodCurrentED Register(Default Value: 0x00000000)
Offset: 0x41c

Register Name: HcPeriodCurrentED(PCED)

Read/Write
Bit

31:4

3:0

HCD

R

R

HC

R/W

R

Default/Hex

Description

0x0

PCED[31:4]
This is used by HC to point to the head of one of the Periodec list
which will be processed in the current Frame. The content of thisregister is updated by HC after a periodic ED has been processed. HCD
may read the content in determining which ED is currently being
processed at the time of reading.

0x0

PCED[3:0]
Because the general TD length is 16 bytes, the memory structure for
the TD must be aligned to a 16-byte boundary. So the lower bits in the
PCED, through bit 0 to bit 3 must be zero in this field.

7.5.3.5.9. HcControlHeadED Register(Default Value: 0x00000000)
Offset: 0x420

A64 User Manual(Revision 1.0)

Register Name: HcControlHeadED[CHED]

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Read/Write
Bit

31:4

3:0

HCD

R/W

R

7.5.3.5.10.

HC

R

R

Default/Hex

Description

0x0

EHCD[31:4]
The HcControlHeadED register contains the physical address of the
first
Endpoint Descriptor of the Control list. HC traverse the Control list
starting with the HcControlHeadED pointer. The content is loaded
from HCCA during the initialization of HC.

0x0

EHCD[3:0]
Because the general TD length is 16 bytes, the memory structure for
the TD must be aligned to a 16-byte boundary. So the lower bits in the
PCED, through bit 0 to bit 3 must be zero in this field.

HcControlCurrentED Register(Default Value: 0x00000000)

Offset: 0x424

Register Name: HcControlCurrentED[CCED]

Read/Write
Bit

31:4

3:0

HCD

R/W

R

7.5.3.5.11.

HC

R/W

R

Default/Hex

Description

0x0

CCED[31:4]
The pointer is advanced to the next ED after serving the present one.
HC will continue processing the list from where it left off in the last
Frame. When it reaches the end of the Control list, HC checks theControlListFilled of in HcCommandStatus. If set, it copies the contentof HcControlHeadED to HcControlCurrentED and clears the bit. If notset, it does nothing.
HCD is allowed to modify this register only when the ControlListEnableof HcControl is cleared. When set, HCD only reads the instantaneous
value of this register. Initially, this is set to zero to indicate the end of
the Control list.

0x0

CCED[3:0]
Because the general TD length is 16 bytes, the memory structure for
the TD must be aligned to a 16-byte boundary. So the lower bits in the
PCED, through bit 0 to bit 3 must be zero in this field.

HcBulkHeadED Register(Default Value: 0x00000000)

Offset: 0x428

Register Name: HcBulkHeadED[BHED]

Read/Write
Bit
31:4

HCD
R/W

HC
R

A64 User Manual(Revision 1.0)

Default/Hex

Description

0x0

BHED[31:4]
The HcBulkHeadED register contains the physical address of the first

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Endpoint Descriptor of the Bulk list. HC traverses the Bulk list startingwith the HcBulkHeadED pointer. The content is loaded from HCCA
during the initialization of HC.

3:0

R

7.5.3.5.12.

R

BHED[3:0]
Because the general TD length is 16 bytes, the memory structure for
the TD must be aligned to a 16-byte boundary. So the lower bits in the
PCED, through bit 0 to bit 3 must be zero in this field.

0x0

HcBulkCurrentED Register(Default Value: 0x00000000)

Offset: 0x42c

Register Name: HcBulkCurrentED [BCED]

Read/Write
Bit

31:4

3:0

HCD

R/W

R

7.5.3.5.13.

HC

R/W

R

Default/Hex

Description

0x0

BulkCurrentED[31:4]
This is advanced to the next ED after the HC has served the present
one. HC continues processing the list from where it left off in the last
Frame. When it reaches the end of the Bulk list, HC checks theControlListFilled of HcControl. If set, it copies the content of
HcBulkHeadED to HcBulkCurrentED and clears the bit. If it is not set, it
does nothing. HCD is only allowed to modify this register when the
BulkListEnable of HcControl is cleared. When set, the HCD only reads
the instantaneous value of this register. This is initially set to zero toindicate the end of the Bulk list.

0x0

BulkCurrentED [3:0]
Because the general TD length is 16 bytes, the memory structure for
the TD must be aligned to a 16-byte boundary. So the lower bits in the
PCED, through bit 0 to bit 3 must be zero in this field.

HcDoneHead Register(Default Value: 0x00000000)

Offset: 0x430

Register Name: HcDoneHead

Read/Write
Bit

31:4
3:0

HCD

R
R

HC

R/W
R

A64 User Manual(Revision 1.0)

Default/Hex

Description

0x0

HcDoneHead[31:4]
When a TD is completed, HC writes the content of HcDoneHead to the
NextTD field of the TD. HC then overwrites the content of
HcDoneHead with the address of this TD. This is set to zero wheneverHC writes the content of this register to HCCA. It also sets theWritebackDoneHead of HcInterruptStatus.

0x0

HcDoneHead[3:0]
Because the general TD length is 16 bytes, the memory structure for

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the TD must be aligned to a 16-byte boundary. So the lower bits in the
PCED, through bit 0 to bit 3 must be zero in this field.

7.5.3.5.14.

HcFmInterval Register(Default Value: 0x00002EDF)

Offset: 0x434

Register Name: HcFmInterval Register

Read/Write
Bit
31

HCD
R/W

HC
R

Default/Hex

Description

0x0

FrameIntervalToggler
HCD toggles this bit whenever it loads a new value to FrameInterval.

30:16

R/W

R

0x0

FSLargestDataPacket
This field specifies a value which is loaded into the Largest Data Packet
Counter at the beginning of each frame. The counter value represents
the largest amount of data in bits which can be sent or received by the
HC in a single transaction at any given time without causing schedulingoverrun. The field value is calculated by the HCD.

15:14

/

/

0x0

Reserved

0x2edfFrameIntervalThis specifies the interval between two consecutive SOFs in bit times.
The nominal value is set to be 11,999. HCD should store the current
value of this field before resetting HC. By setting the
HostControllerReset field of HcCommandStatus as this will cause the
HC to reset this field to its nominal value. HCD may choose to restore
the stored value upon the completion of the Reset sequence.

13:0

R/W

7.5.3.5.15.

R

HcFmRemaining Register(Default Value: 0x00000000)

Offset: 0x438

Register Name: HcFmRemaining

Read/Write
Bit

HCD

HC

Default/Hex

Description

31

R

R/W

0x0

FrameRemaining Toggle
This bit is loaded from the FrameIntervalToggle field of HcFmInterval
whenever FrameRemaining reaches 0. This bit is used by HCD for thesynchronization between FrameInterval and FrameRemaining.

30:14

/

/

0x0

Reserved

0x0

FramRemaining
This counter is decremented at each bit time. When it reaches zero, it
is reset by loading the FrameInterval value specified in HcFmInterval at
the next bit time boundary. When entering the USBOPERATIONAL
state, HC re-loads the content with the FrameInterval of HcFmInterval
and uses the updated value from the next SOF.

13:0

R

RW

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7.5.3.5.16.

HcFmNumber Register(Default Value: 0x00000000)

Offset: 0x43c

Register Name: HcFmNumber

Read/Write
Bit

HCD

HC

Default/Hex

Description

31:16

/

/

/

Reserved

0x0

FrameNumberThis is incremented when HcFmRemaining is re-loaded. It will berolled over to 0x0 after 0x0ffff. When entering the USBOPERATIONAL
state, this will be incremented automatically. The content will be
written to HCCA after HC has incremented the FrameNumber at eachframe boundary and sent a SOF but before HC reads the first ED inthat Frame. After writing to HCCA, HC will set the StartofFrame in
HcInterruptStatus.

15:0

R

7.5.3.5.17.

R/W

HcPeriodicStart Register(Default Value: 0x00000000)

Offset: 0x440

Register Name: HcPeriodicStatus

Read/Write
Bit

HCD

HC

Default/Hex

Description

31:14

/

/

/

Reserved

0x0

PeriodicStart
After a hardware reset, this field is cleared. This is then set by HCD
during the HC initialization. The value is calculated roughly as 10% off
from HcFmInterval. A typical value will be 0x2A3F (0x3e67). When
HcFmRemaining reaches the value specified, processing of theperiodic lists will have priority over Control/Bulk processing. HC will
therefore start processing the Interrupt list after completing thecurrent Control or Bulk transaction that is in progress.

13:0

R/W

7.5.3.5.18.

R

HcLSThreshold Register(Default Value: 0x00000628)

Offset: 0x444

Register Name: HcLSThreshold

Read/Write
Bit

HCD

HC

Default/Hex

Description

31:12

Reserved

11:0

LSThreshold
This field contains a value which is compared to the FrameRemaining

R/W

R

A64 User Manual(Revision 1.0)

0x0628

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field prior to initiating a Low Speed transaction. The transaction isstarted only if FrameRemaining ³ this field. The value is calculated by
HCD with the consideration of transmission and setup overhead.

7.5.3.5.19.

HcRhDescriptorA Register(Default Value: 0x02001201)

Offset: 0x448

Register Name: HcRhDescriptorA

Read/Write
Bit

31:24

HCD

R/W

HC

R

Default/Hex

Description

0x2

PowerOnToPowerGoodTime[POTPGT]This byte specifies the duration HCD has to wait before accessing a
powered-on port of the Root Hub. It is implementation-specific. The
unit of time is 2 ms. The duration is calculated as POTPGT * 2ms.

23:13

Reserved
NoOverCurrentProtection
This bit describes how the overcurrent status for the Root Hub ports
are reported. When this bit is cleared, theOverCurrentProtectionMode field specifies global or per-port
reporting.

12

R/W

R

1

0

Over-current status is reported collectively for all downstream
ports.

1

No overcurrent protection supported.

OverCurrentProtectionMode
This bit describes how the overcurrent status for the Root Hub ports
are reported. At reset, these fields should reflect the same mode asPowerSwitchingMode. This field is valid only if the
NoOverCurrentProtection field is cleared.

11

10

R/W

R

R

R

0

Over-current status is reported collectively for all downstream
ports.

01Over-current status is reported on per-port basis.

0x0

Device Type
This bit specifies that the Root Hub is not a compound device. The
Root Hub is not permitted to be a compound device. This field should
always read/write 0.
PowerSwitchingMode
This bit is used to specify how the power switching of the Root Hub
ports is controlled. It is implementation-specific. This field is only valid
if the NoPowerSwitching field is cleared.

9

R/W

R

A64 User Manual(Revision 1.0)

10

All ports are powered at the same time.

1

Each port is powered individually. This mode allows port power
to be controlled by either the global switch or per-port
switching. If the PortPowerControlMask bit is set, the port

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responds only to port power commands (Set/ClearPortPower).
If the port mask is cleared, then the port is controlled only by
the global power switch (Set/ClearGlobalPower).
NoPowerSwithcing
These bits are used to specify whether power switching is supported
or ports are always powered. It is implementation-specific. When this
bit is cleared, the PowerSwitchingMode specifies global or per-port
switching.

8

7:0

R/W

R

7.5.3.5.20.

R

R

0

Ports are power switched.

1

Ports are always powered on when the HC is powered on.

0
NumberDownstreamPorts
These bits specify the number of downstream ports supported by the
Root Hub. It is implementation-specific. The minimum number ofports is 1. The maximum number of ports supported.

0x01

HcRhDescriptorB Register(Default Value: 0x00000000)

Offset: 0x44c

Register Name: HcRhDescriptorB Register

Read/Write
Bit

HCD

HC

Default/Hex

Description
PortPowerControlMask
Each bit indicates if a port is affected by a global power control
command when PowerSwitchingMode is set. When set, the port's
power state is only affected by per-port power control(Set/ClearPortPower). When cleared, the port is controlled by the
global power switch (Set/ClearGlobalPower). If the device isconfigured to global switching mode (PowerSwitchingMode = 0 ), thisfield is not valid.
Bit0

Reserved

Bit1

Ganged-power mask on Port #1.

Bit2

Ganged-power mask on Port #2.

…
31:16

R/W

R

0x0

Bit15

Ganged-power mask on Port #15.

DeviceRemovable
Each bit is dedicated to a port of the Root Hub. When cleared, theattached device is removable. When set, the attached device is notremovable.

15:0

R/W

R

A64 User Manual(Revision 1.0)

0x0

Bit0

Reserved

Bit1

Device attached to Port #1.

Bit2

Device attached to Port #2.

…

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Bit15

7.5.3.5.21.

Device attached to Port #15.

HcRhStatus Register(Default Value: 0x00000000)

Offset: 0x450

Register Name: HcRhStatus Register

Read/Write
Bit

HCD

HC

Default/Hex

Description

31

W

R

0

(write)ClearRemoteWakeupEnable
Write a ‘1’ clears DeviceRemoteWakeupEnable. Write a ‘0’ has noeffect.

30:18

/

/

0x0

Reserved

0

OverCurrentIndicatorChang
This bit is set by hardware when a change has occurred to the
OverCurrentIndicator field of this register. The HCD clears this bit bywriting a ‘1’.Writing a ‘0’ has no effect.

0x0(read)LocalPowerStartusChange
The Root Hub does not support the local power status features, thus,
this bit is always read as ‘0’.
(write)SetGlobalPowerIn global power mode (PowerSwitchingMode=0), This bit is written to‘1’ to turn on power to all ports (clear PortPowerStatus). In per-port
power mode, it sets PortPowerStatus only on ports whose
PortPowerControlMask bit is not set. Writing a ‘0’ has no effect.

17

16

R/W

R/W

R

R

(read)DeviceRemoteWakeupEnable
This bit enables a ConnectStatusChange bit as a resume event, causinga USBSUSPEND to USBRESUME state transition and setting theResumeDetected interrupt.

15

R/W

R

0x0

0

ConnectStatusChange is not a remote wakeup event.

1

ConnectStatusChange is a remote wakeup event.

(write)SetRemoteWakeupEnable
Writing a ‘1’ sets DeviceRemoveWakeupEnable. Writing a ‘0’ has noeffect.

14:2

Reserved

10x0

OverCurrentIndicator
This bit reports overcurrent conditions when the global reporting is
implemented. When set, an overcurrent condition exists. When
cleared, all power operations are normal.
If per-port overcurrent protection is implemented this bit is always ‘0’

0x0(Read)LocalPowerStatus
When read, this bit returns the LocalPowerStatus of the Root Hub. The

0

R
R/W

R/W
R

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Root Hub does not support the local power status feature; thus, this
bit is always read as ‘0’.
(Write)ClearGlobalPower
When write, this bit is operated as the ClearGlobalPower. In global
power mode (PowerSwitchingMode=0), This bit is written to ‘1’ toturn off power to all ports (clear PortPowerStatus). In per-port powermode, it clears PortPowerStatus only on ports whose
PortPowerControlMask bit is not set. Writing a ‘0’ has no effect.

7.5.3.5.22.

HcRhPortStatus Register(Default Value: 0x00000100)

Offset: 0x454

Register Name: HcRhPortStatus

Read/Write
Bit

HCD

HC

Default/Hex

Description

31:21

/

/

0x0

Reserved
PortResetStatusChangeThis bit is set at the end of the 10-ms port reset signal. The HCD writesa ‘1’ to clear this bit. Writing a ‘0’ has no effect.

20

R/W

R/W

0x0

0

port reset is not complete

1

port reset is complete

PortOverCurrentIndicatorChangeThis bit is valid only if overcurrent conditions are reported on a
per-port basis. This bit is set when Root Hub changes the
PortOverCurrentIndicator bit. The HCD writes a ‘1’ to clear this bit.
Writing a ‘0’ has no effect.
19

R/W

R/W

0x0

0

no change in PortOverCurrentIndicator

1

PortOverCurrentIndicator has changed

PortSuspendStatusChangeThis bit is set when the full resume sequence has been completed.
This sequence includes the 20-s resume pulse, LS EOP, and 3-ms
resychronization delay. The HCD writes a ‘1’ to clear this bit. Writing a‘0’ has no effect. This bit is also cleared when ResetStatusChange is
set.
18

R/W

R/W

0x0

0

resume is not completed

1

resume completed

PortEnableStatusChangeThis bit is set when hardware events cause the PortEnableStatus bit to
be cleared. Changes from HCD writes do not set this bit. The HCD
writes a ‘1’ to clear this bit. Writing a ‘0’ has no effect.
0

no change in PortEnableStatuschange in PortEnableStatus

17

R/W

R/W

0x0

1

16

R/W

R/W

0x0

ConnectStatusChange

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This bit is set whenever a connect or disconnect event occurs. The
HCD writes a ‘1’ to clear this bit. Writing a ‘0’ has no effect. If
CurrentConnectStatus is cleared when a SetPortReset,SetPortEnable,or SetPortSuspend write occurs, this bit is set to force the driver tore-evaluate the connection status since these writes should not occur
if the port is disconnected.
0

no change in PortEnableStatus1

change in PortEnableStatus

Note: If the DeviceRemovable[NDP] bit is set, this bit is set only
after a Root Hub reset to inform the system that the device is
attached.
15:10

/

/

0x0

Reserved(read)LowSpeedDeviceAttachedThis bit indicates the speed of the device attached to this port. Whenset, a Low Speed device is attached to this port. When clear, a Full
Speed device is attached to this port. This field is valid only when the
CurrentConnectStatus is set.

9

R/W

R/W

-

0

full speed device attached1

low speed device attached(write)ClearPortPowerThe HCD clears the PortPowerStatus bit by writing a ‘1’ to this bit.
Writing a ‘0’ has no effect.
(read)PortPowerStatus
This bit reflects the port’s power status, regardless of the type of
power switching implemented. This bit is cleared if an overcurrent
condition is detected. HCD sets this bit by writing SetPortPower or
SetGlobalPower. HCD clears this bit by writing ClearPortPower or
ClearGlobalPower. Which power control switches are enabled isdetermined by PowerSwitchingMode and
PortPortControlMask[NumberDownstreamPort]. In global switchingmode(PowerSwitchingMode=0), only Set/ClearGlobalPower controls
this bit. In per-port power switching (PowerSwitchingMode=1), if the
PortPowerControlMask[NDP] bit for the port is set, only
Set/ClearPortPower commands are enabled. If the mask is not set,
only Set/ClearGlobalPower commands are enabled. When port power
is disabled, CurrentConnectStatus, PortEnableStatus,
PortSuspendStatus, and PortResetStatus should be reset.

8

R/W

R/W

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0x10

port power is off

1

port power is on(write)SetPortPower

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The HCD writes a ‘1’ to set the PortPowerStatus bit. Writing a ‘0’ has
no effect.
Note: This bit is always reads ‘1b’ if power switching is not supported.
7:5

/

/

0x0

Reserved(read)PortResetStatus
When this bit is set by a write to SetPortReset, port reset signaling isasserted. When reset is completed, this bit is cleared when
PortResetStatusChange is set. This bit cannot be set if
CurrentConnectStatus is cleared.

4

R/W

R/W

0x0

0

port reset signal is not active

1

port reset signal is active(write)SetPortReset
The HCD sets the port reset signaling by writing a ‘1’ to this bit.
Writing a ‘0’ has no effect. If CurrentConnectStatus is cleared, thiswrite does not set PortResetStatus, but instead sets
ConnectStatusChange. This informs the driver that it attempted toreset a disconnected port.
(read)PortOverCurrentIndicator
This bit is only valid when the Root Hub is configured in such a waythat overcurrent conditions are reported on a per-port basis. If
per-port overcurrent reporting is not supported, this bit is set to 0. Ifcleared, all power operations are normal for this port. If set, an
overcurrent condition exists on this port. This bit always reflects theovercurrent input signal.

3

R/W

R/W

0x0

0

no overcurrent condition.

1

overcurrent condition detected.

(write)ClearSuspendStatus
The HCD writes a ‘1’ to initiate a resume. Writing a ‘0’ has no effect. A
resume is initiated only if PortSuspendStatus is set.
(read)PortSuspendStatus
This bit indicates the port is suspended or in the resume sequence. It
is set by a SetSuspendState write and cleared when
PortSuspendStatusChange is set at the end of the resume interval.
This bit cannot be set if CurrentConnectStatus is cleared. This bit isalso cleared when PortResetStatusChange is set at the end of the port
reset or when the HC is placed in the USBRESUME state. If an
upstream resume is in progress, it should propagate to the HC.

2

R/W

R/W

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0x00

port is not suspended

1

port is suspended(write)SetPortSuspend
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The HCD sets the PortSuspendStatus bit by writing a ‘1’ to this bit.
Writing a ‘0’ has no effect. If CurrentConnectStatus is cleared, thiswrite does not set PortSuspendStatus; instead it sets
ConnectStatusChange. This informs the driver that it attempted tosuspend a disconnected port.
(read)PortEnableStatus
This bit indicates whether the port is enabled or disabled. The Root
Hub may clear this bit when an overcurrent condition, disconnect
event, switched-off power, or operational bus error such as babble isdetected. This change also causes PortEnabledStatusChange to be set.
HCD sets this bit by writing SetPortEnable and clears it by writing
ClearPortEnable. This bit cannot be set when CurrentConnectStatus iscleared. This bit is also set, if not already, at the completion of a port
reset when ResetStatusChange is set or port suspend when
SuspendStatusChange is set.

1

R/W

R/W

0x0

0

port is disabled1

port is enabled(write)SetPortEnable
The HCD sets PortEnableStatus by writing a ‘1’. Writing a ‘0’ has noeffect. If CurrentConnectStatus is cleared, this write does not set
PortEnableStatus, but instead sets ConnectStatusChange. This informs
the driver that it attempted to enable a disconnected Port.
(read)CurrentConnectStatus
This bit reflects the current state of the downstream port.

0

R/W

R/W

0x0

0

No device connected1

Device connected(write)ClearPortEnable
The HCD writes a ‘1’ to clear the PortEnableStatus bit. Writing ‘0’ has
no effect. The CurrentConnectStatus is not affected by any write.
Note: This bit is always read ‘1’ when the attached device isnonremovalble(DviceRemoveable[NumberDownstreamPort]).

7.5.3.6. HCI Interface Control and Status Register Description

7.5.3.6.1. HCI Interface Control Register(Default Value: 0x00000000)
Offset: 0x800

Register Name: HCI_ICR

Bit

R/W

Default/Hex

Description

31:21

/

/

Reserved.

20

R/W

0

EHCI HS force
Set 1 to this field force the ehci enter the high speed mode during bus

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reset.
This field only valid when the bit 1 is set.
19:18

/

/

/

17

R/W

0

HSIC Connect detect
1 in this field enable the hsic phy to detect device connect pulse on thebus.
This field only valid when the bit 1 is set.

16

R/W

0

HSIC Connect Interrupt Enable
Enable the HSIC connect interrupt.
This field only valid when the bit 1 is set.

15:13

/

/

/

12

/

/

/

11

R/W

0

AHB Master interface INCR16 enable
1: Use INCR16 when appropriate
0: do not use INCR16,use other enabled INCRX or unspecified length burst
INCR

10

R/W

0

AHB Master interface INCR8 enable
1: Use INCR8 when appropriate
0: do not use INCR8,use other enabled INCRX or unspecified length burst
INCR

9

R/W

0

AHB Master interface burst type INCR4 enable
1: Use INCR4 when appropriate
0: do not use INCR4,use other enabled INCRX or unspecified length burst
INCR

8

R/W

0

AHB Master interface INCRX align enable
1: start INCRx burst only on burst x-align address
0: Start burst on any double word boundary
Note: This bit must enable if any bit of 11:9 is enabled

7:2

/

/

Reserved

1

R/W

0

HSIC
0:/
1:HSICThis meaning is only valid when the controller is HCI1.

0

R/W

0

ULPI bypass enable。
1: Enable UTMI interface, disable ULPI interface(SP used utmi
interface)
0: Enable ULPI interface, disable UTMI interface

7.5.3.6.2. HSIC status Register(Default Value: 0x00000000)
Offset: 0x804
Bit

R/W

Register Name: HSIC_STATUS
Default/Hex

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31:17

/

/

/

16

R/W

0

HSIC Connect Status
1 in this field indicates a device connect pulse being detected on the bus.
This field only valid when the EHCI HS force bit and the HSIC Phy Select bit
is set.
When the HSIC Connect Interrupt Enable is set, 1 in this bit will generate aninterrupt to the system.
This register is valid on HCI1.

15:0

/

/

/

7.5.3.7. USB Host Clock Requirement
Name

Description

HCLK

System clock (provided by AHB bus clock). This clock needs to be >30MHz.

CLK60M

Clock from PHY for HS SIE, is constant to be 60MHz.

CLK48M

Clock from PLL for FS/LS SIE, is constant to be 48MHz.

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7.6. I2S/PCM
7.6.1. Overview
The I2S/PCM Controller has been designed to transfer streaming audio-data between the system memory andthe codec chip. The controller supports standard I2S format, Left-justified Mode format, Right-justified Mode
format, PCM Mode format and TDM Mode format.
The I2S/PCM controller includes the following features:Compliant with standard Philips Inter-IC sound (I2S) bus specificationCompliant with Left-justified, Right-justified, PCM mode, and TDM (Time Division Multiplexing) format
Support different sample period width in each interface when using LRCK and LRCKR at the same timeSupport full-duplex synchronous work modeSupport Master / Slave modeSupport adjustable interface voltage
Support clock up to 100MHz
Support adjustable audio sample rate from 8-bit to 32-bit.
Support up to 8 slots which has adjustable width from 8-bit to 32-bit.
Support sample rate from 8KHz to 192KHz
Support 8-bits u-law and 8-bits A-law companded sample
One 128 x 32-bit width FIFO for data transmit, one 64 x 32-bit width FIFO for data receiveSupport programmable PCM frame width: 1 BCLK width (short frame) and 2 BCLKs width (long frame)Programmable FIFO thresholds
Interrupt and DMA Support
Support loopback mode for testSupport Audio HUB

7.6.2. Signal Description
7.6.2.1. I2S/PCM Pin List
Signal Name(x=0,1)

Direction(M)Description

PCMx_BCLKI/O

I2S/PCM x BCLK Output

PCMx_SYNC

I/O

I2S/PCM x Sample Rate Clock/Sync

PCMx_DINI

I2S/PCM x Serial Data Input

PCMx_DOUTO

I2S/PCM x Serial Data Output

I2S_MCLKO

I2S CLK Output

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7.6.2.2. Digital Audio Interface Clock Source and FrequencyeDescription
Audio_PLL

24.576Mhz or 22.5792Mhz generated by AUDIO-PLL to produce 48KHz or 44.1KHz serial
frequency

7.6.3. Functionalities Description
7.6.3.1. Typical Applications
The I2S/PCM provides a serial bus interface for stereo and multichannel audio data. This interface is mostcommonly used by consumer audio market, including compact disc, digital audio tape, digital sound processors,and digital TV-sound.

7.6.3.2. Functional Block Diagram
The I2S/PCM Interface block diagram is shown below:
DA_INT

RX_DRQ

TX_DRQ

SystemBus(APB)

AUDIO_PLL

Clock
DivideRegister

BCLK

MCLK
64x32bits
RX FIFO
128x32bits
TX FIFO

S
Y
N
C

I2S
Engine

BCLK
M
U
X

PCM
Codec

PCM
Engine

LRCK
SDO
SDI

Figure 7-8. I2S/PCM Interface System Block Diagram

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7.6.4. Timing Diagram

1 / fsLRCK

Left Channel

Right Channel

BCLK
DOUT/DIN 8 slot
[TDM-I2S mode]02

DOUT/DIN 4 slot
[TDM-I2S mode]02

DOUT/DIN 2 slot
[I2S mode]

0

m

slot
…

n-1n-2

4

6

1

3

1

3

5

7

1

m=0~7

1 0 sample

MSB

LSB

Figure 7-9. Timing Diagram for I2S/TDM-I2S mode

1 / fsLRCK

Left Channel

Right Channel

BCLK
8 slot[TDM-Left mode]02

4 slot[TDM-Left mode]02

2 slot[Left-Justified mode]

0

m

slot

n-1n-2

…

MSB

4

6

1

3

1

3

5

7

1

m=0~7

1 0 sample
LSB

Figure 7-10. Timing Diagram for Left-justified/TDM-Left mode

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1 / fsLRCK

Left Channel

Right Channel

BCLK
0

8 slot[TDM-Right mode]2

4 slot[TDM-Right mode]

4

6

0

2

2 slot[Right-Justified mode]

3

5

7

1

3

0

m

1

m=0~7

slot
…

n-1n-21

1 0 sample

MSB

LSB

Figure 7-11. Timing Diagram for Right-justified/TDM-Right mode
1 / fsLRCK
BCLK
8 slot[TDM-DSP_A mode]

0

1

2

3

4 slot[TDM-DSP_A mode]

0

1

2

3

2 slot[DSP_A stereo]

0

1

1 slot[DSP_A mono]0

8 slot[TDM-DSP_B mode]

0

1

2

3

4 slot[TDM-DSP_B mode]

0

1

2

3

2 slot[DSP_B stereo]

0

1

1 slot[DSP_B mono]0mn-1n-2

slot
…

4

4

6

5

5

6

7

7

m=0~7

1 0 sample

MSB

LSB

Figure 7-12. Timing Diagram for PCM/TDM-PCM mode

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7.6.5. Operation Modes
The software operation of the I2S/PCM is divided into five steps: system setup, I2S/PCM initialization, thechannel setup, DMA setup and Enable/Disable module. These five steps are described in detail in the following
sections.
7.6.5.1. System setup and I2S/PCM initialization
The first step in the system setup is properly programming the GPIO. Because the I2S/PCM port is a multiplex
pin. You can find the function in the pin multiplex specification. The clock source for the I2S/PCM should be
followed. At first you must reset the audio PLL through the PLL_ENABLE bit of PLL_AUDIO_CTRL_REG in the
CCU. The second step, you must setup the frequence of the audio pll in the PLL_AUDIO_CTRL_REG. After that,you must open the I2S/PCM gating through the I2S/PCM 0_CLK_REG / I2S/PCM 1_CLK_REG when you
checkout that the LOCK bit of PLL_AUDIO_CTRL_REG become 1. At last, you must reset the I2S/PCM in
BUS_SOFT_RST_REG3's bit[13:12] and open the I2S/PCM bus gating in the BUS_CLK_GATING_REG2's
bit[13:12].
After the system setup, the register of I2S/PCM can be setup. At first, you should initialization the I2S/PCM. You
should closed the Globe Enable bit(I2S/PCM_CTL[0]) , Transmitter Block Enable bit(I2S/PCM_CTL[2]) andReceiver Block Enable bit(I2S/PCM_CTL[1]) by write 0 to it. After that, you must clear the TX/RX FIFO by write
0 to register I2S/PCM_FCTL[25:24]. At last, you can clear the TX/RX FIFO counter by write 0 to
I2S/PCM_TXCNT/I2S/PCM_RXCNT.

7.6.5.2. The channel setup and DMA setup
Before the usage and control of I2S/PCM, you must configure the I2C. The configuration of I2C will not describe
in this chapter. But you can only configure I2S/PCM of master and slave through the I2C. In the following, you
can setup the I2S/PCM of mater and slave. The configuration can be referred to the the protocol of I2S/PCM.
Then, you can set the translation mode, the sample precision, the wide of slot, the frame mode and the trigger
level. The register set can be found in the spec.
The I2S/PCM supports three methods to transfer the data. The most common way is DMA, the set of DMA canbe found in the DMA. In this module, you just to enable the DRQ.

7.6.5.3. Enable and disable the I2S/PCM
To enable the function, you can enable TX/RX by write the I2S/PCM_CTL[2:1]. After that, you must enable
I2S/PCM by write the Globe Enable bit to 1 in the I2S/PCM_CTL. The disable process is writed the Globe
Enable to 0.

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7.6.6. I2S/PCM Register List
Module Name

Base Address

I2S/PCM 0

0x01C22000

I2S/PCM 1

0x01C22400

I2S/PCM 2

0x01C22800 (for HDMI)

Register Name

OffsetDescription

I2S/PCM_CTL

0x00

I2S/PCM Control Register

I2S/PCM_FMT0

0x04

I2S/PCM Format Register 0

I2S/PCM_FMT1

0x08

I2S/PCM Format Register 1

I2S/PCM_ISTA

0x0C

I2S/PCM Interrupt Status Register

I2S/PCM_RXFIFO

0x10

I2S/PCM RX FIFO Register

I2S/PCM_FCTL

0x14

I2S/PCM FIFO Control Register

I2S/PCM_FSTA

0x18

I2S/PCM FIFO Status Register

I2S/PCM_INT

0x1C

I2S/PCM DMA & Interrupt Control Register

I2S/PCM_TXFIFO

0x20

I2S/PCM TX FIFO Register

I2S/PCM_CLKD

0x24

I2S/PCM Clock Divide Register

I2S/PCM_TXCNT

0x28

I2S/PCM TX Sample Counter Register

I2S/PCM_RXCNT

0x2C

I2S/PCM RX Sample Counter Register

I2S/PCM_CHCFG

0x30

I2S/PCM Channel Configuration Register

I2S/PCM_TX0CHSEL

0x34

I2S/PCM TX0 Channel Select Register

I2S/PCM_TX1CHSEL

0x38

I2S/PCM TX1 Channel Select Register

I2S/PCM_TX2CHSEL

0x3C

I2S/PCM TX2 Channel Select Register

I2S/PCM_TX3CHSEL

0x40

I2S/PCM TX3 Channel Select Register

I2S/PCM_TX0CHMAP

0x44

I2S/PCM TX0 Channel Mapping Register

I2S/PCM_TX0CHMAP

0x48

I2S/PCM TX1 Channel Mapping Register

I2S/PCM_TX0CHMAP

0x4C

I2S/PCM TX2 Channel Mapping Register

I2S/PCM_TX0CHMAP

0x50

I2S/PCM TX3 Channel Mapping Register

I2S/PCM_RXCHSEL

0x54

I2S/PCM RX Channel Select register

I2S/PCM_RXCHMAP

0x58

I2S/PCM RX Channel Mapping Register

7.6.7. I2S/PCM Register Description
7.6.7.1. I2S/PCM Control Register(Default Value: 0x00060000)
Offset: 0x00
Bit

Register Name: I2S/PCM_CTL
R/W

Default/Hex

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31:19

18

/

R/W

/

/

1

BCLK_OUT
0: input
1: output

17

R/W

1

LRCK_OUT
0: input
1: output

16

R/W

0

/

15:12

/

/

/

11

R/W

0

/

10

R/W

0

/

9

R/W

0

/

8

R/W

0

SDO0_EN
0: Disable, Hi-Z state
1: Enable

7

/

/

/

0

OUT Mute
0: normal transfer
1: force DOUT to output 00MODE_SEL
Mode Selection
0: PCM mode (offset 0: DSP_B; offset 1: DSP_A)
1: Left mode (offset 0: LJ mode; offset 1: I2S mode)
2: Right-Justified mode
3: Reserved

0

LOOP
Loop back test
0: Normal mode
1: Loop back test
When set ‘1’, connecting the SDO0 with the SDI0

TXEN
Transmitter Block Enable
0: Disable
1: Enable

0

RXEN
Receiver Block Enable
0: Disable
1: Enable

0

GEN
Globe Enable
A disable on this bit overrides any other block or channel enables.
0: Disable
1: Enable

6

5:4

3

2

1

0

R/W

R/W

R/W

R/W

R/W

R/W

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7.6.7.2. I2S/PCM Format Register0 (Default Value: 0x00000033)
Offset: 0x04

Register Name: I2S/PCM_FMT0

Bit

R/W

Default/Hex

Description

31

R/W

0

/

30

R/W

0

LRCK_WIDTH(only apply in PCM mode ) LRCK width
0: LRCK = 1 BCLK width (short frame)
1: LRCK = 2 BCLK width (long frame)

29:20

R/W

0

/

19

R/W

0

LRCK_POLARITY/LRCKR_POLARITY
When apply in I2S / Left-Justified / Right-Justified mode:
0: Left channel when LRCK is low
1: Left channel when LRCK is highWhen apply in PCM mode:
0: PCM LRCK/LRCKR asserted at the negative edge
1: PCM LRCK/LRCKR asserted at the positive edge

18

/

/

/

0

LRCK_PERIOD
It is used to program the number of BCLKs per channel of sample frame.
This value is interpreted as follow:
PCM mode: Number of BCLKs within (Left + Right) channel width
I2S / Left-Justified / Right-Justified mode: Number of BCLKs within eachindividual channel width (Left or Right)
N+1
For example:
n = 7: 8 BCLK width…
n = 1023: 1024 BCLKs width0

BCLK_POLARITY
0: normal mode, negative edge drive and positive edge sample
1: invert mode, positive edge drive and negative edge sample

17:8

7

R/W

R/W

6:4

R/W

3

SR
Sample Resolution
0: Reserved
1: 8-bit
2: 12-bit
3: 16-bit
4: 20-bit
5: 24-bit
6: 28-bit
7: 32-bit

3

R/W

0

EDGE_TRANSFER

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0: SDO drive data and SDI sample data at the different BCLK edge
1: SDO drive data and SDI sample data at the same BCLK edge
BCLK_POLARITY = 0, use negative edge
BCLK_POLARITY = 1, use positive edge

2:0

R/W

0x3

SW
Slot Width Select0: Reserved
1: 8-bit
2: 12-bit
3: 16-bit
4: 20-bit
5: 24-bit
6: 28-bit
7: 32-bit

7.6.7.3. I2S/PCM Format Register1 (Default Value: 0x00000030)
Offset: 0x08

Register Name: I2S/PCM_FMT1

Bit

R/W

Default/Hex

31:8

/

/

7

6

5:4

3:2

1:0

R/W

R/W

R/W

R/W

R/W

Description0

RX MLSMSB / LSB First Select0: MSB First
1: LSB First0

TX MLSMSB / LSB First Select0: MSB First
1: LSB First

3

SEXT
Sign Extend in slot [sample resolution < slot width]
0: Zeros or audio gain padding at LSB position
1: Sign extension at MSB position
2: Reserved
3: Transfer 0 after each sample in each slot

0

RX_PDMPCM Data Mode
0: Linear PCM
1: reserved
2: 8-bits u-law
3: 8-bits A-law

0

TX_PDMPCM Data Mode
0: Linear PCM

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1: reserved
2: 8-bits u-law
3: 8-bits A-law

7.6.7.4. I2S/PCM Interrupt Status Register(Default Value: 0x00000010)
Offset: 0x0C

Register Name: I2S/PCM_ISTA

Bit

R/W

Default/Hex

Description

31:7

/

/

/

0

TXU_INTTX FIFO Under run Pending Interrupt
0: No Pending Interrupt
1: FIFO Under run Pending Interrupt
Write 1 to clear this interrupt

0

TXO_INTTX FIFO Overrun Pending Interrupt
0: No Pending Interrupt
1: FIFO Overrun Pending Interrupt
Write ‘1’ to clear this interrupt

6

5

R/W

R/W

4

R/W

1

TXE_INTTX FIFO Empty Pending Interrupt
0: No Pending IRQ
1: FIFO Empty Pending Interrupt when data in TX FIFO are less than TX
trigger level
Write ‘1’ to clear this interrupt or automatic clear if interrupt condition
fails.

3

/

/

/

0

RXU_INTRX FIFO Under run Pending Interrupt
0: No Pending Interrupt
1:FIFO Under run Pending Interrupt
Write 1 to clear this interrupt

0

RXO_INTRX FIFO Overrun Pending Interrupt
0: No Pending IRQ
1: FIFO Overrun Pending IRQ
Write ‘1’ to clear this interrupt

0

RXA_INTRX FIFO Data Available Pending Interrupt
0: No Pending IRQ
1: Data Available Pending IRQ when data in RX FIFO are more than RX
trigger level
Write ‘1’ to clear this interrupt or automatic clear if interrupt condition

2

1

0

R/W

R/W

R/W

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fails.

7.6.7.5. I2S/PCM RX FIFO Register(Default Value: 0x00000000)
Offset: 0x10
Bit

31:0

R/W

R

Register Name: I2S/PCM_RXFIFODefault/Hex

Description0

RX_DATARX Sample
Host can get one sample by reading this register. The left channel sample
data is first and then the right channel sample.

7.6.7.6. I2S/PCM FIFO Control Register (Default Value: 0x000400F0)
Offset: 0x14
Bit

R/W

Register Name: I2S/PCM_FCTLDefault/Hex

Description

31

R/W

0

HUB_EN
Audio hub enable
0:disable
1:enable

30:26

/

/

/

0

FTX
Write ‘1’ to flush TX FIFO, self clear to ‘0’.

25

R/W

24

R/W

0

FRX
Write ‘1’ to flush RX FIFO, self clear to ‘0’.

23:19

/

/

/

18:12

R/W

0x40

TXTL
TX FIFO Empty Trigger Level
Interrupt and DMA request trigger level for TXFIFO normal condition
Trigger Level = TXTL

11:10

/

/

/

9:4

R/W

0xF

RXTL
RX FIFO Trigger Level
Interrupt and DMA request trigger level for RXFIFO normal condition
Trigger Level = RXTL + 1

3

/

/

/

0

TXIM
TX FIFO Input Mode (Mode 0, 1)
0: Valid data at the MSB of TXFIFO register
1: Valid data at the LSB of TXFIFO register
Example for 20-bits transmitted audio sample:
Mode 0: FIFO_I[31:0] = {APB_WDATA[31:12], 12’h0}

2R/W

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Mode 1: FIFO_I[31:0] = {APB_WDATA[19:0], 12’h0}

1:0

R/W

RXOM
RX FIFO Output Mode (Mode 0, 1, 2, 3)
00: Expanding ‘0’ at LSB of DA_RXFIFO register.
01: Expanding received sample sign bit at MSB of DA_RXFIFO register.
10: Truncating received samples at high half-word of DA_RXFIFO registerand low half-word of DA_RXFIFO register is filled by ‘0’.
11: Truncating received samples at low half-word of DA_RXFIFO registerand high half-word of DA_RXFIFO register is expanded by its sign bit.
Example for 20-bits received audio sample:
Mode 0: APB_RDATA[31:0] = {FIFO_O[31:12], 12’h0}Mode 1: APB_RDATA [31:0] = {12{FIFO_O[31]}, FIFO_O[31:12]}
Mode 2: APB_RDATA [31:0] = {FIFO_O[31:16], 16’h0}Mode 3: APB_RDATA [31:0] = {16{FIFO_O[31], FIFO_O[31:16]}

0

7.6.7.7. I2S/PCM FIFO Status Register (Default Value: 0x10800000)
Offset: 0x18

Register Name: I2S/PCM_FSTA

Bit

R/W

Default/Hex

Description

31:29

/

/

/

28

R

1

TXE
TX FIFO Empty
0: No room for new sample in TX FIFO
1: More than one room for new sample in TX FIFO (>= 1 word)

27:24

/

/

/

23:16

R

0x80

TXE_CNTTX FIFO Empty Space Word Counter

15:9

/

/

/

8

R

0

RXA
RX FIFO Available
0: No available data in RX FIFO
1: More than one sample in RX FIFO (>= 1 word)

7

/

/

/

0

RXA_CNTRX FIFO Available Sample Word Counter

6:0

R

7.6.7.8. I2S/PCM DMA & Interrupt Control Register(Default Value: 0x00000000)
Offset: 0x1C

Register Name: I2S/PCM_INT

Bit

R/W

Default/Hex

Description

31:8

/

/

/

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7

6

5

4

3

2

1

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0

TX_DRQ
TX FIFO Empty DRQ Enable
0: Disable
1: Enable

0

TXUI_EN
TX FIFO Under run Interrupt Enable
0: Disable
1: Enable

0

TXOI_EN
TX FIFO Overrun Interrupt Enable
0: Disable
1: Enable
When set to ‘1’, an interrupt happens when writing new audio data if TX
FIFO is full.

0

TXEI_EN
TX FIFO Empty Interrupt Enable
0: Disable
1: Enable

0

RX_DRQ
RX FIFO Data Available DRQ Enable
0: Disable
1: Enable
When set to ‘1’, RXFIFO DMA Request line is asserted if Data is available in
RX FIFO.

0

RXUI_EN
RX FIFO Under run Interrupt Enable
0: Disable
1: Enable

0

RXOI_EN
RX FIFO Overrun Interrupt Enable
0: Disable
1: Enable

0

RXAI_EN
RX FIFO Data Available Interrupt Enable
0: Disable
1: Enable

7.6.7.9. I2S/PCM TX FIFO Register(Default Value: 0x00000000)
Offset: 0x20
Bit
31:0

R/W
W

Register Name: I2S/PCM_TXFIFODefault/Hex

Description0

TX_DATATX Sample

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Transmitting left, right channel sample data should be written this register
one by one. The left channel sample data is first and then the right channel
sample.

7.6.7.10. I2S/PCM Clock Divide Register(Default Value: 0x00000000)
Offset: 0x24

Register Name: I2S/PCM_CLKD

Bit

R/W

Default/Hex

Description

31:9

/

/

/

0

MCLKO_EN
0: Disable MCLK Output
1: Enable MCLK Output
Notes: Whether in Slave or Master mode, when this bit is set to 1, MCLK
should be output.

0

BCLKDIVBCLK Divide Ratio from PLL2
0: reserved
1: Divide by 1
2: Divide by 2
3: Divide by 4
4: Divide by 6
5: Divide by 8
6: Divide by 12
7: Divide by 16
8: Divide by 24
9: Divide by 32
10: Divide by 48
11: Divide by 64
12: Divide by 96
13: Divide by 128
14: Divide by 176
15: Divide by 192

0

MCLKDIVMCLK Divide Ratio from PLL2 Output
0: reserved
1: Divide by 1
2: Divide by 2
3: Divide by 4
4: Divide by 6
5: Divide by 8
6: Divide by 12
7: Divide by 16
8: Divide by 24

8

7:4

3:0

R/W

R/W

R/W

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9: Divide by 32
10: Divide by 48
11: Divide by 64
12: Divide by 96
13: Divide by 128
14: Divide by 176
15: Divide by 192

7.6.7.11. I2S/PCM TX Counter Register(Default Value: 0x00000000)
Offset: 0x28
Bit

31:0

R/W

R/W

Register Name: I2S/PCM_TXCNTDefault/Hex

Description0

TX_CNT
TX Sample Counter
The audio sample number of sending into TXFIFO. When one sample is put
into TXFIFO by DMA or by host IO, the TX sample counter register
increases by one. The TX sample counter register can be set to any initial
valve at any time. After been updated by the initial value, the counterregister should count on base of this initial value.

7.6.7.12. I2S/PCM RX Counter Register(Default Value: 0x00000000)
Offset: 0x2C
Bit

31:0

R/W

R/W

Register Name: I2S/PCM_RXCNT
Default/Hex

Description

0

RX_CNT
RX Sample Counter
The audio sample number of writing into RXFIFO. When one sample iswritten by Digital Audio Engine, the RX sample counter register increases
by one. The RX sample counter register can be set to any initial valve at any
time. After been updated by the initial value, the counter register shouldcount on base of this initial value.

7.6.7.13. I2S/PCM Channel Configuration Register(Default Value: 0x00000000)
Offset: 0x30

Register Name: I2S/PCM_CHCFG

Bit

R/W

Default/Hex

Description

31:10

/

/

/

0

TX_SLOT_HIZ
0: normal mode for the last half cycle of BCLK in the slot
1: turn to hi-z state for the last half cycle of BCLK in the slot

9R/W

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8

R/W

0

TXn_STATE
0: transfer level 0 when not transferring slot
1: turn to hi-z state when not transferring slot

7

/

/

/

6:4

R/W

0

RX_SLOT_NUM
RX Channel/Slot Number which between CPU/DMA and FIFO
0: 1 channel or slot...
7: 8 channels or slots

3

/

/

/

0

TX_SLOT_NUM
TX Channel/Slot Number which between CPU/DMA and FIFO
0: 1 channel or slot...
7: 8 channels or slots

2:0

R/W

7.6.7.14. I2S/PCM TXn Channel Select Register(Default Value: 0x00000000)
Offset: 0x34 + n*4 (n = 0, 1, 2, 3)

Register Name: I2S/PCM_TXnCHSEL

Bit

R/W

Default/Hex

Description

31:13

/

/

/

12

R/W

0

TXn_OFFSET
TXn offset tune, TXn data offset to LRCK
0: no offset
1: data is offset by 1 BCLK to LRCK

11:4

R/W

0

TXn_CHEN
TXn Channel (slot) enable, bit[11:4] refer to slot [7:0]. When one ormore slot(s) is(are) disabled, the affected slot(s) is(are) set to disable
state
0: disable
1: enable

3

/

/

/

0

TXn_CHSEL
TXn Channel (slot) number Select for each output
0: 1 channel / slot…
7: 8 channels / slots

2:0

R/W

7.6.7.15. I2S/PCM TXn Channel Mapping Register(Default Value: 0x00000000)
Offset: 0x44 + n*4 (n = 0, 1, 2, 3)

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Bit

R/W

Default/Hex

Description

31

/

/

/

30:28

R/W

0

TXn_CH7_MAP
TXn Channel7 Mapping
0: 1st sample…
7: 8th sample

27

/

/

/

26:24

R/W

0

TXn_CH6_MAP
TXn Channel6 Mapping
0: 1st sample…
7: 8th sample

23

/

/

/

22:20

R/W

0

TXn_CH5_MAP
TXn Channel5 Mapping
0: 1st sample…
7: 8th sample

19

/

/

/

18:16

R/W

0

TXn_CH4_MAP
TXn Channel4 Mapping
0: 1st sample…
7: 8th sample

15

/

/

/

14:12

R/W

0

TXn_CH3_MAP
TXn Channel3 Mapping
0: 1st sample…
7: 8th sample

11

/

/

/

10:8

R/W

0

TXn_CH2_MAP
TXn Channel2 Mapping
0: 1st sample…
7: 8th sample

7

/

/

/

6:4

R/W

0

TXn_CH1_MAP
TXn Channel1 Mapping
0: 1st sample…
7: 8th sample

3

/

/

/

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Interfaces
2:0

R/W

0

TXn_CH0_MAP
TXn Channel0 Mapping
0: 1st sample…
7: 8th sample

7.6.7.16. I2S/PCM RX Channel Select Register(Default Value: 0x00000000)
Offset: 0x54

Register Name: I2S/PCM_RXCHSEL

Bit

R/W

Default/Hex

Description

31:13

/

/

/

12

R/W

0

RX_OFFSET
RX offset tune, RX data offset to LRCK
0: no offset
1: data is offset by 1 BCLK to LRCK

11:3

/

/

2:0

R/W

0

RX_CHSEL
RX Channel (slot) number Select for input
0: 1 channel / slot…
7: 8 channels / slots

7.6.7.17. I2S/PCM RX Channel Mapping Register(Default Value: 0x00000000)
Offset: 0x58

Register Name: I2S/PCM_RXCHMAP

Bit

R/W

Default/Hex

Description

31

/

/

/

30:28

R/W

0

RX_CH7_MAP
RX Channel7 Mapping
0: 1st sample…
7: 8th sample

27

/

/

/

26:24

R/W

0

RX_CH6_MAP
RX Channel6 Mapping
0: 1st sample…
7: 8th sample

23

/

/

/

22:20

R/W

0

RX_CH5_MAP
RX Channel5 Mapping

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0: 1st sample…
7: 8th sample
19

/

/

/

18:16

R/W

0

RX_CH4_MAP
RX Channel4 Mapping
0: 1st sample…
7: 8th sample

15

/

/

/

14:12

R/W

0

RX_CH3_MAP
RX Channel3 Mapping
0: 1st sample…
7: 8th sample

11

/

/

/

10:8

R/W

0

RX_CH2_MAP
RX Channel2 Mapping
0: 1st sample…
7: 8th sample

7

/

/

/

6:4

R/W

0

RX_CH1_MAP
TX Channel1 Mapping
0: 1st sample…
7: 8th sample

3

/

/

/

2:0

R/W

0

RX_CH0_MAP
RX Channel0 Mapping
0: 1st sample…
7: 8th sample

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7.7. OWA
7.7.1. Overview
The OWA(One Wire Audio) provides a serial bus interface for audio data between system. This interface iswidely used for consumer audio connect.
The OWA includes the following features:IEC-60958 transmitter functionalityComplies with SPDIF Interface
Support channel status insertion for the transmitterHardware Parity generation on the transmitter
One 32×24bits FIFO (TX) for audio data transfer
Programmable FIFO thresholds
Interrupt and DMA support
Support Audio HUB

7.7.2. Functional Description
7.7.2.1. OWA Interface Pin List
Signal Name

Direction(M)Description

Pin

OWA_DOUTOOWA output

PH8

7.7.2.2. OWA Clock Requirement
Clock Name

Description

Requirement

apb_clk

APB bus clock>13 MHzs_clk

OWA serial access clock

4x24.576 MHz or 4x22.5792 MHz from CCU

7.7.2.3. OWA Block Diagram
Figure 7-13 shows the OWA block diagram.

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Figure 7-13. OWA Block Diagram

7.7.2.4. OWA Frame Format

Figure 7-14. Sub-Frame Format

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Interfaces

Figure 7-15. Frame/block format

Figure 7-16. Biphase-Mark Encoding

7.7.2.5. Operation Modes
The software operation of the OWA is divided into five steps: system setup, OWA initialization, the channel
setup, DMA setup and Enable/Disable module. These five steps are described in detail in the following
sections.
7.7.2.5.1. System setup and OWA initialization
The first step in the OWA initialization is properly programming the GPIO. Because the OWA port is a multiplex
pin. You can find the function in the Port Controller(CPUx-PORT). The clock source for the OWA should be
followed. At first you must reset the audio PLL in the CCU. The second step, you must setup the frequence of
the audio pll. After that, you must open the OWA gating. At last, you must open the OWA bus gating.
After the system setup, the register of OWA can be setup. At first, you should reset the OWA by write 1 to
OWA_CTL[0] and clear the TX/RX FIFO by write 1 to register OWA_FCTL[17:16]. After that you should enable
the globe enable bit by write 1 to OWA_CTL[1] and clear the interrupt and TX/RX counter throught the
OWA_ISTA and OWA_TX_CNT/OWA_RX_CNT.

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7.7.2.5.2. The channel setup and DMA setup
The OWA support three methods to transfer the data. The most common way is DMA, the set of DMA can befound in the DMA. In this module, you just to enable the DRQ.

7.7.2.5.3. Enable and disable the OWA
To enable the function, you can enable TX/RX by writting the OWA_TX_CFIG[31] and OWA_RX_CFIG[0]. After
that, you must enable OWA by write the Globe Enable bit to 1 in the OWA_CTL. Writting the Globe Enable to 0
disable process.

7.7.3. OWA Register List
Module Name

Base Address

OWA

0x01C21000

Register Name

OffsetDescription

OWA_GEN_CTL

0x00

OWA General Control

OWA_TX_CFIG

0x04

OWA TX Configuration Register

OWA_RX_CFIG

0x08

OWA RX Configuration Register

OWA_ISTA

0x0C

OWA Interrupt Status Register

OWA_RX_FIFO

0x10

OWA RX FIFO Register

OWA_FCTL

0x14

OWA FIFO Control Register

OWA_FSTA

0x18

OWA FIFO Status Register

OWA_INT

0x1C

OWA Interrupt Control Register

OWA_TX_FIFO

0x20

OWA TX FIFO Register

OWA_TX_CNT

0x24

OWA TX Counter Register

OWA_RX_CNT

0x28

OWA RX Counter Register

OWA_TX_CHSTA00x2C

OWA TX Channel Status Register0

OWA_TX_CHSTA1

0x30

OWA TX Channel Status Register1

OWA_RX_CHSTA00x34

OWA RX Channel Status Register0

OWA_RX_CHSTA1

0x38

OWA RX Channel Status Register1

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7.7.4. OWA Register Description
7.7.4.1. OWA General Control Register(Default Value : 0x00000080)
Offset: 0x00

Register Name: OWA_CTL

Bit

R/W

Default/Hex

Description

31:10

/

/

/

9:4

R/W

0x08

MCLK_DIV_RATIO
Mclk divide Ratio
Note: only support 2n divide ratio(n=1~31)

3:2

/

/

/

1

R/W

0

GEN
Globe Enable
A disable on this bit overrides any other block or channel enables andflushes all FIFOs.
0: Disable
1: Enable

0

R/W

0

RST
Reset
0: Normal
1: Reset
Self clear to 0

7.7.4.2. OWA TX Configure Register(Default Value: 0x000000F0)
Offset: 0x04

Register Name: OWA_TX_CFIG

Bit

R/W

Default/Hex

Description

31

R/W

0

TX_SINGLE_MODE
Tx single channel mode
0: Disable
1: Eanble

30:18

/

/

/

17

R/W

0

ASS
Audio sample select with TX FIFO under run
when
0: sending 0
1: sending the last audio
Note: This bit is only valid in PCM mode

16

R/W

0

TX_AUDIO
TX data type
0: Linear PCM (Valid bit of both sub-frame set to 0 )A64 User Manual(Revision 1.0)

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Interfaces
1: Non-audio(Valid bit of both sub-frame set to 1)
15:9

/

/

/

8:4

R/W

0xF

TX_RATIO
TX clock divide Ratio
Note: clock divide ratio = TX TATIO +1

3:2

R/W

0

TX_SF
TX Sample format:
00: 16bit
01: 20bit
10: 24bit
11: Reserved

1

R/W

0

TX_CHMCHSTMODE
0: Channel status A&B set to 0
1: Channel status A&B generated form TX_CHSTA

0

R/W

0

TXEN
0: disabled
1: enabled

7.7.4.3. OWA RX Configure Register(Default Value: 0x00000000)
Offset: 0x08

Register Name: OWA_RX_CFIG

Bit

R/W

Default/Hex

Description

31:5

/

/

/

4

R

0

RX_LOCK_FLAG
0: unlock
1: lock

3

R/W

0

RX_CHST_SRC
0: RX_CH_STA Register holds status from Channel A
1: RX_CH_STA Register holds status from Channel B

2

/

/

/

1

R/W

0

CHST_CP
Channel status Capture
0: Idle or capture end
1: Capture Channel status start
Notes: When set to ‘1’, the channel status information is capturing,
the bit will clear to ‘0’ after captured.

0

R/W

0

RXEN
0: disabled
1: enabled

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Interfaces
7.7.4.4. OWA Interrupt Status Register(Default Value: 0x00000010)
Offset: 0x0C

Register Name: OWA_ISTA

Bit

R/W

Default/Hex

Description

31:19

/

/

/

18

R/W

0

RX_LOCK_INT
0: No pending IRQ
1: RX lock Pending Interrupt (RX_LOCK_FLAG 0→1)
Write “1” to clear this interrupt

17

R/W

0

RX_UNLOCK_INTRX Unlock Pending Interrupt
0: No pending IRQ
1: RX Unlock Pending Interrupt (RX_LOCK_FLAG 1→0)
Write “1” to clear this interrupt

16

R/W

0

RX_PARERRI_INTRX Parity Error Pending Interrupt
0: No pending IRQ
1: RX Parity Error Pending Interrupt
Write “1” to clear this interrupt

15:7

/

/

/

6

R/W

0

TXU_INTTX FIFO Under run Pending Interrupt
0: No pending IRQ
1: FIFO Under run Pending Interrupt
Write “1” to clear this interrupt

5

R/W

0

TXO_INTTX FIFO Overrun Pending Interrupt
0: No Pending IRQ
1: FIFO Overrun Pending Interrupt
Write “1” to clear this interrupt

4

R/W

1

TXE_INTTX FIFO Empty Pending Interrupt
0: No Pending IRQ
1: FIFO Empty Pending Interrupt
Write “1” to clear this interrupt or automatically clear if interrupt
condition fails.

3:2

/

/

/

1

R/W

0

RXO_INTRX FIFO Overrun Pending Interrupt
0: FIFO Overrun Pending
Write “1” to clear this interrupt

0

R/W

0

RXA_INTRX FIFO Available Pending Interrupt

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0: No Pending IRQ
1: Data Available Pending IRQ
Write “1” to clear this interrupt or automatically clear if interrupt
condition fails

7.7.4.5. OWA RX FIFO Register(Default Value: 0x00000000)
Offset: 0x10

Register Name: OWA_RXFIFO

Bit

R/W

Default/Hex

Description

31:0

R

0

RX_DATA
Host can get one sample by reading this register, the A channel data is
first and then the B channel data

7.7.4.6. OWA FIFO Control Register(Default Value: 0x00001078)
Offset: 0x14

Register Name: OWA_FCTL

Bit

R/W

Default/Hex

Description

31

R/W

0

HUB_EN
Audio hub enable
0 : Disable
1: Enable

30:18

/

/

/

17

R/W

0

FTX
Write “1” to flush TX FIFO, self clear to “0”

16

R/W

0

FRX
Write “1” to flush RX FIFO, self clear to “0”

15:13

/

/

/

12:8

R/W

0x10

TXTL
TX FIFO empty Trigger Level
Interrupt and DMA request trigger level for TX FIFO normal condition
Trigger Level = TXTL

7:3

R/W

0x0F

RXTL
RX FIFO Trigger Level
Interrupt and DMA request trigger level for RX FIFO normal condition
Trigger Level = RXTL + 1

2

R/W

0

TXIM
TX FIFO Input Mode(Mode0, 1)
0: Valid data at the MSB of OWA_TXFIFO register
1: Valid data at the LSB of OWA_TXFIFO register
Example for 20-bits transmitted audio sample:
Mode 0: FIFO_I[23:0] = {TXFIFO[31:12], 4’h0}

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Mode 1: FIFO_I[23:0] = {TXFIFO[19:0], 4’h0}
1:0

R/W

0

RXOM
RX FIFO Output Mode(Mode 0,1,2,3)
00: Expanding “0” at LSB of SPDIP_RXFIFO register
01: Expanding received sample sign bit at MSB of OWA_RXFIFO
register
10: Truncating received samples at high half-word of OWA_RXFIFO
register and low half-word of AC_FIFO register is filled by “0”
11: Truncating received samples at low half-word of OWA_RXFIFO
register and high half-word of AC_FIFO register is expanded by its sighbit
Mode0: RXFIFO[31:0] = {FIFO_O[23:0], 8’h0}Mode 1: RXFIFO[31:0] = {8’FIFO_O[23], FIFO_O[23:0]}
Mode 2: RXFIFO[31:0] = {FIFO_O[23:8], 16’h0}Mode 3: RXFIFO[31:0] = {16’FIFO_O[23], FIFO_O[23:8]}

7.7.4.7. OWA FIFO Status Register(Default Value: 0x00006000)
Offset: 0x18

Register Name: OWA_FSTA

Bit

R/W

Default/Hex

Description

31:15

/

/

/

14

R

1

TXE
TX FIFO Empty (indicate FIFO is not full)
0: No room for new sample in TX FIFO
1: More than one room for new sample in TX FIFO ( >=1 word )

13:8

R

0x20

TXE_CNTTX FIFO Empty Space Word counter

7

/

/

/

6

R

0

RXA
RX FIFO Available
0: No available data in RX FIFO
1: More than one sample in RX FIFO ( >=1 word )

5:0

R

0

RXA_CNTRX FIFO Available Sample Word counter

7.7.4.8. OWA Interrupt Control Register(Default Value: 0x00000000)
Offset: 0x1C

Register Name: OWA_INT

Bit

R/W

Default/Hex

Description

31:19

/

/

/

18

R/W

0

RX_LOCKI_EN

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RX LOCK Interrupt enable
0: Disable
1: Enable
17

R/W

0

RX_UNLOCKI_EN
RX UNLOCK Interrupt enable
0: Disable
1: Enable

16

R/W

0

RX_PARERRI_EN
RX PARITY ERORR Interrupt enable
0: Disable
1: Enable

15:8

/

/

/

7

R/W

0

TX_DRQ
TX FIFO Empty DRQ Enable
0: Disable
1: Enable

6

R/W

0

TXUI_EN
TX FIFO Under run Interrupt Enable
0: Disable
1: Enable

5

R/W

0

TXOI_EN
TX FIFO Overrun Interrupt Enable
0: Disable
1: Enable

4

R/W

0

TXEI_EN
TX FIFO Empty Interrupt Enable
0: Disable
1: Enable

3

/

/

/

2

R/W

0

RX_DRQ
RX FIFO Data Available DRQ Enable
When set to “1”, RX FIFO DMA Request is asserted if Data is available
in RX FIFO
0: Disable
1: Enable

1

R/W

0

RXOI_EN
RX FIFO Overrun Interrupt Enable
0: Disable
1: Enable

0

R/W

0

RXAI_EN
RX FIFO Data Available Interrupt Enable
0: Disable
1: Enable

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7.7.4.9. OWA TX FIFO Register(Default Value: 0x00000000)
Offset: 0x20

Register Name: OWA_TXFIFO

Bit

R/W

Default/Hex

Description

31:0

W

0

TX_DATA
Transmitting A, B channel data should be written this register one byone. The A channel data is first and then the B channel data.

7.7.4.10. OWA TX Counter Register(Default Value: 0x00000000)
Offset: 0x24

Register Name: OWA_TX_CNT

Bit

R/W

Default/Hex

Description

31:0

R/W

0

TX_CNT
TX Sample counter
The audio sample number of writing into TX FIFO. When one sample iswritten by DMA or by host IO, the TX sample counter register
increases by one. The TX Counter register can be set to any initialvalue at any time. After been updated by the initial value, the counterregister should count on base of this value.

7.7.4.11. OWA RX Counter Register(Default Value: 0x00000000)
Offset: 0x28

Register Name: OWA_RX_CNT

Bit

R/W

Default/Hex

Description

31:0

R/W

0

RX_CNT
RX Sample counter
The audio sample number of writing into RX FIFO. When one sample
is written by Codec, the RX sample counter register increases by one.
The RX Counter register can be set to any initial value at any time.
After been updated by the initial value, the counter register shouldcount on base of this value.

7.7.4.12. OWA TX Channel Status Register0(Default Value: 0x00000000)
Offset: 0x2C

Register Name: OWA_TX_CHSTA0

Bit

R/W

Default/Hex

Description

31: 30

/

/

/

29:28

R/W

0

CA
Clock Accuracy

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00: Level 2
01: Level 1
10: Level 3
11: not matched
27:24

R/W

FREQ
Sampling frequency
0000: 44.1kHz
0001: not indicated0010: 48kHz
0011: 32kHz
0100: 22.05kHz
0101: Reserved0110: 24kHz
0111: Reserved

1000: Reserved
1001: 768kHz
1010: 96kHz
1011: Reserved
1100:176.4kHz
1101: Reserved
1110: 192kHz
1111: Reserved

23:20

R/W

0

CN
Channel Number

19:16

R/W

0

SN
Source Number

15:8

R/W

0

CC
Category code
Indicates the kind of equipment that generates the digital audio
interface signal.

7:6

R/W

0

MODE
Mode
00: Default Mode
01~11: Reserved

5:3

R/W

0

EMP
Emphasis
Additional format information
For bit 1 = “0”, Linear PCM audio mode:
000: 2 audio channels without pre-emphasis
001: 2 audio channels with 50 μs / 15 μs pre-emphasis
010: Reserved (for 2 audio channels with pre-emphasis)011: Reserved (for 2 audio channels with pre-emphasis)100~111: Reserved
For bit 1 = “1”, other than Linear PCM applications:
000: Default state001~111: Reserved

2

R/W

0

CP
Copyright
0: copyright is asserted
1: no copyright is asserted

1

R/W

0

TYPE
Audio Data Type

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0: Linear PCM Samples
1: For none-linear PCM audio such as AC3, DTS, MPEG audio
0

R/W

0

PRO
Application type
0: Consumer Application
1: Professional Application
Note: This bit must be fixed to “0”7.7.4.13. OWA TX Channel Status Register1(Default Value: 0x00000000)
Offset: 0x30

Register Name: OWA_TX_CHSTA1

Bit

R/W

Default/Hex

Description

31:10

/

/

/

9:8

R/W

0

CGMS_A
00: Copying is permitted without restriction
01: One generation of copies may be made10: Condition not be used
11: No copying is permitted

7:4

R/W

0

ORIG_FREQ
Original sampling frequency
0000: not indicated0001: 192kHz
0010: 12kHz
0011: 176.4kHz
0100: Reserved
0101: 96kHz
0110: 8kHz
0111: 88.2kHz
1000: 16kHz
1001: 24kHz
1010: 11.025kHz
1011: 22.05kHz
1100: 32kHz
1101: 48kHz
1110: Reserved
1111: 44.1kHz

3:1

R/W

0

WL
Sample word length
For bit 0 = “0”:000: not indicated001: 16 bits
010: 18 bits
100: 19 bits

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101: 20 bits
110: 17 bits
111: Reserved
For bit 0 = “1”:000: not indicated001: 20 bits
010: 22 bits
100: 23 bits
101: 24 bits
110: 21 bits
111: Reserved
0

R/W

0

MWL
Max Word length
0: Maximum audio sample word length is 20 bits
1: Maximum audio sample word length is 24 bits

7.7.4.14. OWA RX Channel Status Register0(Default Value: 0x00000000)
Offset: 0x34

Register Name: OWA_RX_CHSTA0

Bit

R/W

Default/Hex

Description

31: 30

/

/

/

29:28

R/W

0

CA
Clock Accuracy
00: Level 2
01: Level 1
10: Level 3
11: not matched

27:24

R/W

0

FREQ
Sampling frequency
0000: 44.1kHz
0001: not indicated0010: 48kHz
0011: 32kHz
0100: 22.05kHz
0101: Reserved0110: 24kHz
0111: Reserved

23:20

R/W

0

CN
Channel Number

19:16

R/W

0

SN
Source Number

15:8

R/W

0

CC

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1000: Reserved
1001: 768kHz
1010: 96kHz
1011: Reserved
1100:176.4kHz
1101: Reserved
1110: 192kHz
1111: Reserved

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Category code
Indicates the kind of equipment that generates the digital audio
interface signal.
7:6

R/W

0

MODE
Mode
00: Default Mode
01~11: Reserved

5:3

R/W

0

EMP
Emphasis
Additional format information
For bit 1 = “0”, Linear PCM audio mode:
000: 2 audio channels without pre-emphasis
001: 2 audio channels with 50 μs / 15 μs pre-emphasis
010: Reserved (for 2 audio channels with pre-emphasis)011: Reserved (for 2 audio channels with pre-emphasis)100~111: Reserved
For bit 1 = “1”, other than Linear PCM applications:
000: Default state001~111: Reserved

2

R/W

0

CP
Copyright
0: copyright is asserted
1: no copyright is asserted

1

R/W

0

TYPE
Audio Data Type
0: Linear PCM Samples
1: For none-linear PCM audio such as AC3, DTS, MPEG audio

0

R/W

0

PRO
Application type
0: Consumer Application
1: Professional Application

7.7.4.15. OWA RX Channel Status Register1(Default Value: 0x00000000)
Offset: 0x38

Register Name: OWA_CH_STA0

Bit

R/W

Default/Hex

Description

31:10

/

/

/

9:8

R/W

0

CGMS_A
00: Copying is permitted without restriction
01: One generation of copies may be made10: Condition not be used
11: No copying is permitted

7:4

R/W

0

ORIG_FREQ

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Original sampling frequency
0000: not indicated0001: 192kHz
0010: 12kHz
0011: 176.4kHz
0100: Reserved
0101: 96kHz
0110: 8kHz
0111: 88.2kHz
1000: 16kHz
1001: 24kHz
1010: 11.025kHz
1011: 22.05kHz
1100: 32kHz
1101: 48kHz
1110: Reserved
1111: 44.1kHz
3:1

R/W

0

WL
Sample word length
For bit 0 = “0”:000: not indicated001: 16 bits
010: 18 bits
100: 19 bits
101: 20 bits
110: 17 bits
111: Reserved
For bit 0 = “1”:000: not indicated001: 20 bits
010: 22 bits
100: 23 bits
101: 24 bits
110: 21 bits
111: Reserved

0

R/W

0

MWL
Max Word length
0: Maximum audio sample word length is 20 bits
1: Maximum audio sample word length is 24 bits

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7.8. SCR
7.8.1. Overview
The Smart Card Reader (SCR) is a communication controller that transmits data between the system and Smart
Card. The controller can perform a complete smart card session, including card activation, card deactivation.
Cold/warm reset, Answer to Reset (ATR) response reception, data transfers, etc.
The SCR includes the following features:Supports APB slave interface for easy integration with AMBA-based host systems

Supports the ISO/IEC 7816-3:1997(E) and EMV2000 (4.0) Specifications

Performs functions needed for complete smart card sessions, including:- Card activation and deactivation- Cold/warm reset- Answer to Reset (ATR) response reception- Data transfers to and from the cardSupports adjustable clock rate and bit rateConfigurable automatic byte repetitionSupport commonly used communication protocols:- T=0 for asynchronous half-duplex character transmission- T=1 for asynchronous half-duplex block transmission
Support FIFOs for receive and transmit buffers (up to 128 characters) with thresholdSupport configurable timing functions:- Smart card activation time
- Smart card reset time
- Guard time
- Timeout timersSupports synchronous and any other non-ISO 7816 and non-EMV cards

7.8.2. Block Diagram
The Top Diagram of Smart Card Reader is below:

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Smart Card Reader
SCR_Vcc

SCR
Registers

SCR_Clk

SCR
Clock
Generator

SCR
Interface

SCR_RstSCR_IOSCR
Controller

APB

SCR_Vppen

TX FIFO

SCR_Vpppp

SCR_DetRX FIFO

Figure 7-17. SCR Block Diagram

7.8.3. SCR Timing Diagram
Please refer ISO/IEC 7816 and EMV2000 Specification.

7.8.4. SCR Special Requirement
7.8.4.1. Clock Generator
The Clock Generator generates the Smart Card Clock signal and the Baud Clock Impulse signal, used in timing
the Smart Card Reader.
The Smart Card Clock signal is used as the main clock for the smart card. Its frequency can be adjusted using
the Smart Card Clock Divisor (SCCDIV). This value is used to divide the system clock. The SCCLK frequency isgiven by the following equation:f scclk f sysclk
2*( SCCDIV  1)

f scclk -- Smart Card Clock Frequency

f sysclk -- System Clock (PCLK) Frequency

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The Baud Clock Impulse signal is used to transmit and receive serial between the Smart Card Reader and the
Smart Card. The baud rate can be modified using the Baud Clock Divisor (BAUDDIV). The value is used to divide
the system clock. The BUAD rate is given by the following equation:

BAUD 

f sysclk
2*( BAUDDIV  1)

BAUD -- Baud rate of the data stream between Smart Card and Reader.
The duration of one bit, Elementary Time Unit (ETU), is defined in the ISO/IEC 7816-3 specification. During thefirst answer to reset response after the cold reset, the initial ETU must be equal to 372 Smart Card Clock Cycles.

1372
 ETU BAUD
f scclk
In this case, the BAUDDIV should be

BAUDDIV 

372* f sysclk
2* f scclk

 1  372*( SCCDIV  1)  1 .

After the ATR is completed, the ETU can be changed according to Smart Card abilities.

1
F
1
 ETU  *BAUD
D f scclk
Parameters F and D are defined in the ISO/IEC 7816-3 Specification.

7.8.4.2. SCIO Pad Configuration

Figure 7-18. SCIO Pad Configuration Diagram

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7.8.5. SCR Register List
Module Name

Base Address

SCR

0x01C2C400

Register Name

OffsetDescription

SCR_CSR

0x000

Smart Card Reader Control and Status Register

SCR_INTEN

0x004

Smart Card Reader Interrupt Enable Register 1

SCR_INTST

0x008

Smart Card Reader Interrupt Status Register 1

SCR_FCSR

0x00c

Smart Card Reader FIFO Control and Status Register

SCR_FCNT

0x010

Smart Card Reader RX and TX FIFO Counter Register

SCR_RPT

0x014

Smart Card Reader RX and TX Repeat Register

SCR_DIV

0x018

Smart Card Reader Clock and Baud Divisor Register

SCR_LTIM

0x01c

Smart Card Reader Line Time Register

SCR_CTIM

0x020

Smart Card Reader Character Time Register

SCR_LCTLR

0x030

Smart Card Reader Line Control Register

SCR_FSM

0x03c

Smart Card Reader FSM Register

SCR_FIFO

0x100

Smart Card Reader RX and TX FIFO Access Point

7.8.6. SCR Register Description
7.8.6.1. Smart Card Reader Control and Status Register(Default Value: 0x00000000)
Offset: 0x00
Bit

Register Name: SCR_CSR
R/W

Default/Hex

Description

31

R

0

SCDET
Smart Card Detected
This bit is set to ‘1’ when the scdetect input is active at least for adebounce time.

30

/

/

/

0

SCDETPOL
Smart Card Detect Polarity
This bit set polarity of scdetect signal.
0: Low Active
1: High Active0

Protocol Selection (PTLSEL)
0x0 : T=0.
0x1 : T=1, no character repeating and no guard time is used when T=1
protocol is selected.
0x2 : Reserved
0x3 : Reserved

24

23:22

R/W

R/W

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21

20

19

18

17

R/W

R/W

R/W

R/W

R/W

0

ATRSTFLUSHATR Start Flush FIFO
When enabled, both FIFOs are flushed before the ATR is started.

0

TSRXE
TS Receive Enable
When set to ‘1’, the TS character (the first ATR character) will be store in
RXFIFO during card session.

0

CLKSTPPOLClock Stop Polarity
The value of the scclk output during the clock stop state.

0

PECRXE
Parity Error Character Receive Enable
Enables storage of the characters received with wrong parity in RX FIFO.

0MSBF
MSB First
When high, inverse bit ordering convention (msb to lsb) is used.

16

R/W

0

DATAPOL
Data Plorarity
When high, inverse level convention is used (A=’1’, Z=’0’).

15:12

/

/

/

0

DEACTDeactivation. Setting of this bit initializes the deactivation
sequence. When the deactivation is finished, the DEACT bit isautomatically cleared.

0

ACT
Activation. Setting of this bit initializes the activation sequence. Whenthe activation is finished, the ACT bit is automatically cleared.

0

WARMRST
Warm Reset Command. Writing ‘1’ to this bit initializes Warm Reset of
the Smart Card. This bit is always read as ‘0’.

11

10

9

R/W

R/W

R/W

8

R/W

0

CLKSTOP
Clock Stop. When this bit is asserted and the smart card I/O line is in ‘Z’state, the SCR core stops driving of the smart card clock signal after the
CLKSTOPDELAY time expires. The smart card clock is restarted
immediately after the CLKSTOP signal is deasserted. New charactertransmission can be started after CLKSTARTDELAY time. The expirationof both times is signaled by the CLKSTOPRUN bit in the interrupt
registers.

7:3

/

/

Reserved

0

GINTEN
Global Interrupt Enable. When high, IRQ output assertion is enabled.

0

RXEN
Receiving Enable. When enabled the characters sent by the Smart Cardare received by the UART and stored in RX FIFO. Receiving is internallydisabled while a transmission is in progress.

2

1

R/W

R/W

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0

R/W

0

TXEN
Transmission Enable. When enabled the characters are read from TX
FIFO and transmitted through UART to the Smart Card.

7.8.6.2. Smart Card Reader Interrupt Enable Register(Default Value: 0x00000000)
Offset: 0x04

Register Name: SCR_INTEN

Bit

R/W

Default/Hex

Description

31:24

/

/

/

0

SCDEA
Smart Card Deactivation Interrupt Enable.

0

SCACT
Smart Card Activation Interrupt Enable.

0

SCINS
Smart Card Inserted Interrupt Enable.

0

SCREM
Smart Card Removed Interrupt Enable.

0

ATRDONEATR Done Interrupt Enable.

0

ATRFAILATR Fail Interrupt Enable.

0

C2CFULL
Two Consecutive Characters Limit Interrupt Enable.

23
22
21
20
19
18
17

R/W
R/W
R/W
R/W
R/W
R/W
R/W

16

R/W

0

CLKSTOPRUN
Smart Card Clock Stop/Run Interrupt Enable.

15:13

/

/

/

0

RXPERRRX Parity Error Interrupt Enable.

12

R/W

11

R/W

0

RXDONERX Done Interrupt Enable.

10

R/W

0

RXFIFOTHD
RX FIFO Threshold Interrupt Enable.

9

R/W

0

RXFIFOFULLRX FIFO Full Interrupt Enable.

8

/

/

/

7:5

/

/

/

4

R/W

0

TXPERRTX Parity Error Interrupt Enable.

0

TXDONETX Done Interrupt Enable.

0

TXFIFOTHD
TX FIFO Threshold Interrupt Enable.

3
2

R/W
R/W

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1
0

R/W
R/W

0

TXFIFOEMPTY
TX FIFO Empty Interrupt Enable.

0

TXFIFODONETX FIFO Done Interrupt Enable.

7.8.6.3. Smart Card Reader Interrupt Status Register(Default Value: 0x00000000)
Offset: 0x08

Register Name: SCR_INTST

Bit

R/W

Default/Hex

Description

31:24

/

/

/

0

SCDEA
Smart Card Deactivation Interrupt. When enabled, this interrupt isasserted after the Smart Card deactivation sequence is complete.

0

SCACT
Smart Card Activation Interrupt. When enabled, this interrupt isasserted after the Smart Card activation sequence is complete.

0

SCINS
Smart Card Inserted Interrupt. When enabled, this interrupt is asserted
after the smart card insertion.

0

SCREM
Smart Card Removed Interrupt. When enabled, this interrupt is asserted
after the smart card removal.

0

ATRDONEATR Done Interrupt. When enabled, this interrupt is asserted after the
ATR sequence is successfully completed.

0

ATRFAILATR Fail Interrupt. When enabled, this interrupt is asserted if the ATR
sequence fails.

0

C2CFULL
Two Consecutive Characters Limit Interrupt. When enabled, thisinterrupt is asserted if the time between two consecutive characters,
transmitted between the Smart Card and the Reader in both directions,is equal the Two Characters Delay Limit described below. The C2CFULL
interrupt is internally enabled from the ATR start to the deactivation or
ATR restart initialization. It is recommended to use this counter todetect unresponsive Smart Cards.

0

CLKSTOPRUN
Smart Card Clock Stop/Run Interrupt. When enabled, this interrupt isasserted in two cases: When the smart card clock is stopped.
 When the new character can be started after the clock restart.
To distinguish between the two interrupt cases, we recommend reading
the CLKSTOP bit in SCR_CTRL1 register.

23

22

21

20

19

18

17

16

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

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15:13

12

11

10

/

R/W

R/W

R/W

/

/

0

RXPERRRX Parity Error Interrupt. When enabled, this interrupt is asserted after
the character with wrong parity was received when the number of
repeated receptions exceeds RXREPEAT value or T=1 protocol is used.

0

RXDONERX Done Interrupt. When enabled, this interrupt is asserted after acharacter was received from the Smart Card.

0

RXFIFOTHD
RX FIFO Threshold Interrupt. When enabled, this interrupt is asserted if
the number of bytes in RX FIFO is equal or exceeds the RX FIFO
threshold.

9

R/W

0

RXFIFOFULLRX FIFO Full Interrupt. When enabled, this interrupt is asserted if the RX
FIFO is filled up.

8

/

/

/

7:5

/

/

/

0

TXPERRTX Parity Error Interrupt. When enabled, this interrupt is asserted if theSmart Card signals wrong character parity during the guard time after
the character transmission was repeated TXREPEAT times or T=1
protocol is used.

0

TXDONETX Done Interrupt. When enabled, this interrupt is asserted after one
character was transmitted to the smart card.

0

TXFIFOTHD
TX FIFO Threshold Interrupt. When enabled, this interrupt is asserted if
the number of bytes in TX FIFO is equal or less than the TX FIFO
threshold.

0

TXFIFOEMPTY
TX FIFO Empty Interrupt. When enabled, this interrupt is asserted if the
TX FIFO is emptied out.

0

TXFIFODONETX FIFO Done Interrupt. When enabled, this interrupt is asserted after all
bytes from TX FIFO ware transferred to the Smart Card.

4

3

2

1

0

R/W

R/W

R/W

R/W

R/W

Note: This register provides information about the state of each interrupt bit. You can clear the register bits
individually by writing ‘1’ to a bit you intend to clear.

7.8.6.4. Smart Card Reader FIFO Control and Status Register(Default Value: 0x00000101)
Offset: 0x0C
Bit

Register Name: SCR_FCSR
R/W

Default/Hex

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31:11
10
9

/
R/W
R

/

/

0

RXFIFOFLUSH
Flush RX FIFO. RX FIFO is flushed, when ‘1’ is written to this bit.

0

RXFIFOFULLRX FIFO Full.

8

R

1

RXFIFOEMPTYRX FIFO Empty.

7:3

/

/

/

0

TXFIFOFLUSH
Flush TX FIFO. TX FIFO is flushed, when ‘1’ is written to this bit.

0

TXFIFOFULL
TX FIFO Full.

1

TXFIFOEMPTY
TX FIFO Empty.

2
1
0

R/W
R
R

7.8.6.5. Smart Card Reader FIFO Counter Register(Default Value: 0x00000000)
Offset: 0x10
Bit

31:24

23:16

15:8

7:0

Register Name: SCR_FIFOCNT
R/W

R/W

R/W

R

R

Default/Hex

Description

0

RXFTH
RX FIFO Threshold
These bits set the interrupt threshold of RX FIFO. The interrupt isasserted when the number of bytes it receives is equal to, or exceeds
the threshold.

0

TXFTH
TX FIFO Threshold
These bits set the interrupt threshold of TX FIFO. The interrupt isasserted when the number of bytes in TX FIFO is equal to or less than
the threshold.

0

RXFCNT
RX FIFO Counter
These bits provide the number of bytes stored in the RXFIFO.

0

TXFCNT
TX FIFO Counter
These bits provide the number of bytes stored in the TXFIFO.

7.8.6.6. Smart Card Reader Repeat Control Register(Default Value: 0x00000000)
Offset: 0x14

Register Name: SCR_REPEAT

Bit

R/W

Default/Hex

Description

31:8

/

/

/

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7:4

3:0

R/W

R/W

0

RXRPT
RX Repeat
This is a 4-bit register that specifies the number of attempts to request
character re-transmission after wrong parity was detected. The
re-transmission of the character is requested using the error signal
during the guard time.

0

TXRPT
TX Repeat
This is a 4-bit register that specifies the number of attempts to
re-transmit the character after the Smart Card signals the wrong parity
during the guard time.

7.8.6.7. Smart Card Reader Clock Divisor Register(Default Value: 0x00000000)
Offset: 0x18
Bit

Register Name: SCR_CLKDIVR/WDefault/Hex

Description
BAUDDIV
Baud Clock Divisor. This 16-bit register defines the divisor value used togenerate the Baud Clock impulses from the system clock.

BAUD 
31:16

R/W

0

f sysclk
2*( BAUDDIV  1)

SCCDIV
Smart Card Clock Divisor. This 16-bit register defines the divisor value
used to generate the Smart Card Clock from the system clock.

f scclk 

f scclk
15:0

R/W

0

f sysclk

f sysclk
2*( SCCDIV  1)

is the frequency of Smart Card Clock Signal.
is the frequency of APB Clock.

7.8.6.8. Smart Card Reader Line Time Register(Default Value: 0x00000000)
Offset: 0x1C

Register Name: SCR_LTIM

Bit

R/W

Default/Hex

Description

31:24

/

/

/

0

ATR
ATR Start Limit. This 16-bit register defines the maximum time between
the rising edge of the scrstn signal and the start of ATR response.

23:16

R/W

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T

ATR Start Limit = 128* ATR* scclk .
RSTReset Duration. This 16-bit register sets the duration of the Smart Card
reset sequence. This value is same for the cold and warm reset.
15:8

R/W

0

T

Cold/Warm Reset Duration = 128* RST* scclk .
ACT
Activation/Deactivation Time. This 16-bit register sets the duration ofeach part of the activation and deactivation sequence.

T

Activation/Deactivation Duration = 128* ACT * scclk .

Tscclk 
7:0

R/W

0

1
f scclk is the Smart Card Clock Cycle.

7.8.6.9. Smart Card Reader Character Time Register(Default Value: 0x00000000)
Offset: 0x20
Bit

Register Name: SCR_CTIM
R/W

Default/Hex

Description

31:16

R/W

0

CHARLIMIT
Character Limit. This 16-bit register sets the maximum time between theleading edges of two consecutive characters. The value is ETUs.

15:8

/

/

/

0

GUARDTIME
Character Guard time. This 8-bit register sets a delay at the end of eachcharacter transmitted from the Smart Card Reader to the Smart Card.
The value is in ETUs. The parity error is besides signaled during theguard time.

7:0

R/W

7.8.6.10. Smart Card Reader Line Control Register(Default Value: 0x00000000)
Offset: 0x30

Register Name: SCR_PAD

Bit

R/W

Default/Hex

Description

31:8

/

/

/

0

DSCVPPPP
Direct Smart Card Vpp Pause/Prog. It provides direct access to SCVPPPP
output.

0

DSCVPPEN
Direct Smart Card Vpp Enable. It provides direct access to SCVPPEN
output.

7

6

R/W

R/W

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5

4

3

2

1

0

R/W

R/W

R/W

R/W

R/W

R/W

0

AUTOADEAVPP
Automatic Vpp Handling. When high, it enables automatic handling of
DSVPPEN and DSVPPPP signals during activation and deactivation
sequence.

0

DSCVCC
Direct Smart Card VCC. When DIRACCPADS=’1’, the DSCVCC bit provides
direct access to SCVCC pad.

0

DSCRST
Direct Smart Card Clock. When DIRACCPADS=’1’, the DSCRST bit
provides direct access to SCRST pad.

0

DSCCLK
Direct Smart Card Clock. When DIRACCPADS=’1’, the DSCCLK bit
provides direct access to SCCLK pad.

0

DSCIO
Direct Smart Card Input/Output. When DIRACCPADS=’1’, the DSCIO bit
provides direct access to SCIO pad.

0

DIRACCPADS
Direct Access to Smart Card Pads. When high, it disables a serialinterface functionality and enables direct control of the smart card pads
using following 4 bits.

Note: This register provides direct access to smart card pads without serial interface assistance. You can use
this register feature with synchronous and any other non-ISO 7816 and non-EMV cards.

7.8.6.11. Smart Card Reader FIFO Data Register(Default Value: 0x00000000)
Offset: 0x0100

Register Name: SCR_FIFO

Bit

R/W

Default/Hex

Description

31:8

/

/

/

0

FIFO_DATAThis 8-bit register provides access to the RX and TX FIFO buffers. The TX
FIFO is accessed during the APB write transfer. The RX FIFO is accessed
during the APB read transfer.

7:0

R/W

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7.9. EMAC
7.9.1. Overview
The Ethernet MAC(EMAC) controller enables a host to transmit and receive data over Ethernet in compliancewith the IEEE 802.3-2002 standard. It supports 10M/100M/1000M external PHY with RMII/ RGMII interface inboth full and half duplex mode. The Ethernet MAC-DMA is designed for packet-oriented data transfers basedon a linked list of descriptors. 4K Byte TXFIFO and 16K Byte RXFIFO are provided to keep continuoustransmission and reception. Flow Control, CRC Pad & Stripping, and address filtering are also supported in thismodule.
The Ethernet MAC Controller includes the following features:Supports 10/100/1000Mbps data transfer rates

Supports RMII/RGMII PHY interface
Supports both full-duplex and half-duplex operationProgrammable frame length to support Standard or Jumbo Ethernet frames with sizes up to 16 KB
Supports a variety of flexible address filtering modes
Separate 32-bit status returned for transmission and reception packets
Optimization for packet-oriented DMA transfers with frame delimiters
Support linked-list (chained) descriptor chainingDescriptor architecture, allowing large blocks of data transfer with minimum CPU intervention; each
descriptor can transfer up to 4 KB of dataComprehensive status reporting for normal operation and transfers with errors

4KB TXFIFO for transmission packets and 16KB RXFIFO for reception packets
Programmable interrupt options for different operational conditions

7.9.2. Block Diagram
The EMAC Controller block diagram is shown below:

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DMA

TXFIFORXFIFO

TXFC

RXFC
EMAC
RMII
PHY
Interface

AHB
Master
MAC CSRDMA CSRRGMII

OMR Register

AHB Slave

Figure 7-19. EMAC Block Diagram

7.9.3. EMAC Core Register List
Module Name

Base Address

EMAC

0x01C30000

Register Name

OffsetDescription

BASIC_CTL_0

0x00

Basic Control 0 Register

BASIC_CTL_1

0x04

Basic Control 1 Register

INT_STA

0x08

Interrupt Status Register

INT_EN

0x0C

Interrupt Enable Register

TX_CTL_0

0x10

Transmit Control 0 Register

TX_CTL_1

0x14

Transmit Control 1 Register

TX_FLOW_CTL

0x1C

Transmit Flow Control Register

TX_DMA_DESC_LIST

0x20

Transmit Descriptor List Address Register

RX_CTL_0

0x24

Receive Control 0 Register

RX_CTL_1

0x28

Receive Control 1 Register

RX_DMA_DESC_LIST

0x34

Receive Descriptor List Address Register

RX_FRM_FLT

0x38

Receive Frame Filter Register

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RX_HASH_0

0x40

Hash Table 0 Register

RX_HASH_1

0x44

Hash Table 1 Register

MII_CMD

0x48

Management Interface Command Register

MII_DATA

0x4C

Management Interface Data Register

ADDR_HIGH_0

0x50

MAC Address High Register 0

ADDR_LOW_0

0x54

MAC Address High Register 0

ADDR_HIGH_x

0x50+8*x

MAC Address High Register x(x:1~7)

ADDR_LOW_x

0x54+8*x

MAC Address Low Register x(x:1~7)

TX_DMA_STA

0xB0

Transmit DMA Status Register

TX_CUR_DESC

0xB4

Current Transmit Descriptor Register

TX_CUR_BUF

0xB8

Current Transmit Buffer Address Register

RX_DMA_STA

0xC0

Receive DMA Status Register

RX_CUR_DESC

0xC4

Current Receive Descriptor Register

RX_CUR_BUF

0xC8

Current Receive Buffer Address Register

RGMII_STA

0xD0

RGMII Status Register

7.9.4. EMAC Core Register Description
7.9.4.1. Basic Control 0 Register(Default Value: 0x00000000)
Offset: 0x00

Register Name: BASIC_CTL_0

Bit

R/W

Default/Hex

Description

31:4

/

/

/

0

SPEED
00: 1000Mbps
11: 100Mbps
10: 10Mbps
01: Reserved

0

LOOPBACK
0: Disable;
1: Enable;

0

DUPLEX
0: Half-duplex
1: Full-duplex

3:2

1

0

R/W

R/W

R/W

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7.9.4.2. Basic Control 1 Register(Default Value: 0x08000000)
Offset: 0x04

Register Name: BASIC_CTL_1

Bit

R/W

Default/Hex

Description

31:30

/

/

/

29:24

R/W

8

BURST_LEN
The burst length of RX and TX DMA transfer.

23:2

/

/

/

0

RX_TX_PRI
0: RX DMA and TX DMA have same priority
1: RX DMA has priority over TX DMA

0

SOFT_RSTWhen this bit is set, soft reset all registers and logic. All clock inputs
must be valid before soft rest. This bit is cleared internally when thereset operation is completed fully. Before write any register, this bit
should read a 0.

1

0

R/W

R/W

7.9.4.3. Interrupt Status Register(Default Value: 0x00000000)
Offset: 0x08

Register Name: INT_STA

Bit

R/W

Default/Hex

Description

31:17

/

/

/

16

R

0

RGMII_LINK_STA_INTWhen this bit is asserted, the link status of RGMII interface is changed.

15:14

/

/

/

13

R

0

RX_EARLY_INTWhen this bit asserted, the RX DMA had filled the first data buffer of thereceive frame.

12

R

0

RX_OVERFLOW_INT
When this bit is asserted, the RX FIFO had an overflow error.

0

RX_TIMEOUT_INT
When this bit asserted, the length of receive frame is greater than 2048
bytes(10240 when JUMBO_FRM_EN is set)0

RX_DMA_STOPPED_INT
When this bit asserted, the RX DMA FSM is stopped.

0

RX_BUF_UA _INTWhen this asserted, the RX DMA can’t acquire next RX descriptor and RXDMA FSM is suspended. The ownership of next RX descriptor should bechanged to RX DMA. The RX DMA FSM will resume when write to
DMA_RX_START bit or next receive frame is coming.

0

RX_INT
When this bit is asserted, a frame reception is completed. The RX DMA

11
10

9
8

R
R

R
R

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FSM remains in the running state.
7:6
5
4
3

2

/
R
R
R

R

/

/

0

TX_EARLY_INTWhen this bit is asserted , the frame is transmitted to FIFO totally.

0

TX_UNDERFLOW_INT
When this bit is asserted, the TX FIFO had an underflow error.

0

TX_TIMEOUT_INT
When this bit is asserted, the transmitter had been excessively active.

0

TX_BUF_UA_INTWhen this asserted, the TX DMA can not acquire next TX descriptor and
TX DMA FSM is suspended. The ownership of next TX descriptor should
be changed to TX DMA. The TX DMA FSM will resume when write to
DMA_TX_START bit.

1

R

0

TX_DMA_STOPPED_INT
When this bit is asserted, the TX DMA FSM is stopped.

0

R

0

TX_INT
When this bit is asserted, a frame transmission is completed.

7.9.4.4. Interrupt Enable Register(Default Value: 0x00000000)
Offset: 0x0C

Register Name: INT_EN

Bit

R/W

Default/Hex

Description

31:14

/

/

/

0

RX_EARLY_INT_EN
0: Disable early receive interrupt enable
1: Enable early receive interrupt enable

0

RX_OVERFLOW_INT_EN
0: Disable overflow interrupt
1: Enable overflow interrupt

0

RX_TIMEOUT_INT_EN
0: Disable receive timeout interrupt
1: Enable receive timeout interrupt

0

RX_DMA_STOPPED_INT_EN
0: Disable receive DMA FSM stopped interrupt
1: Enable receive DMA FSM stopped interrupt

0

RX_BUF_UA_INT_EN
0: Disable receive buffer unavailable interrupt
1: Enable receive buffer unavailable interrupt

0

RX_INT_EN
0: Disable receive interrupt
1: Enable receive interrupt

13

12

11

10

9

8

R/W

R/W

R/W

R/W

R/W

R/W

7:6

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5

4

3

2

1

0

R/W

R/W

R/W

R/W

R/W

R/W

0

TX_EARLY_INT_EN
0: Disable early transmit interrupt
1: Enable early transmit interrupt

0

TX_UNDERFLOW_INT_EN
0: Disable underflow interrupt
1: Enable underflow interrupt

0

TX_TIMEOUT_INT_EN
0: Disable transmit timeout interrupt
1: Enable transmit timeout interrupt

0

TX_BUF_UA_INT_EN
0: Disable transmit buffer available interrupt
1: Enable transmit buffer available interrupt

0

TX_DMA_STOPPED_INT_EN
0: Disable transmit DMA FSM stopped interrupt
1: Enable transmit DMA FSM stopped interrupt

0

TX_INT_EN
0: Disable transmit interrupt
1: Enable transmit interrupt

7.9.4.5. Transmit Control 0 Register(Default Value: 0x00000000)
Offset: 0x10
Bit

31

Register Name: TX_CTL_0
R/W

R/W

Default/Hex

Description

0

TX_EN
Enable transmitter.
0: Disable transmitter after current transmission
1: Enable

30

R/W

0

TX_FRM_LEN_CTL
0: Allow to transmit frames no more than 2,048 bytes (10,240 if
JUMBO_FRM_EN is set) and cut off any bytes after that
1:Allow to transmit frames of up to 16,384 bytes

29:0

/

/

/

7.9.4.6. Transmit Control 1 Register(Default Value: 0x00000000)
Offset: 0x14
Bit

Register Name: TX_CTL_1
R/W

Default/Hex

Description

31

R/W

0

TX_DMA_START
When set this bit, the TX DMA FSM will go no to work. It is clearedinternally and always read a 0.

30

R/W

0

TX_DMA_EN

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0: Stop TX DMA after the completion of current frame transmission.
1: Start and run TX DMA.
29:11

/

/

/

10:8

R/W

0

TX_TH
The threshold value of TX DMA FIFO. When TX_MD is 0, transmission
starts when the size of frame in TX DMA FIFO is greater than thethreshold. In addition, full frames with a length less than the threshold
are transferred automatically.
000: 64001: 128010: 192
011: 256
Others: Reserved

7:2

/

/

/

0

TX_MD
0: Transmission starts after the number of data in TX DAM FIFO isgreater than TX_TH
1: Transmission starts after a full frame located in TX DMA FIFO

0

FLUSH_TX_FIFO
The functionality that flush the data in the TX FIFO.
0: Enable
1: Disable

1

0

R/W

R/W

7.9.4.7. Transmit Flow Control Register(Default Value: 0x00000000)
Offset: 0x1C
Bit

R/W

Register Name: TX_FLOW_CTL
Default/Hex

Description

31

R/W

0

TX_FLOW_CTL_STA
This bit indicates a pause frame transmission is in progress. When theconfiguration of flow control is ready, set this bit to transmit a pause
frame in full-duplex mode or activate the backpressure function. Aftercompletion of transmission, this bit will be cleared automatically. Before
write register TX_FLOW_CTRL, this bit must be read as 0.

30:22

/

/

/

0

TX_PAUSE_FRM_SLOT
The threshold of the pause timer at which the input flow control signal
is checked for automatic retransmission of pause frame. The thresholdvalues should be always less than the PAUSE_TIME

21:20

R/W

19:4

R/W

0

PAUSE_TIME
The pause time field in the transmitted control frame.

3:2

/

/

/

1

R/W

0

ZQP_FRM_EN

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When set, enable the functionality to generate Zero-Quanta Pause
control frame.

0

R/W

TX_FLOW_CTL_EN
When set, enable flow control operation to transmit pause frames infull-duplex mode, or enable the back-pressure operation in half-duplex
mode.
0: Disable
1: Enable

0

7.9.4.8. Transmit DMA Descriptor List Address Register(Default Value: 0x00000000)
Offset: 0x20
Bit
31:0

Register Name: TX_DMA_LIST
R/W
R/W

Default/Hex

Description

0

TX_DESC_LIST
The base address of transmit descriptor list. It must be 32-bit aligned.

7.9.4.9. Receive Control 0 Register(Default Value: 0x00000000)
Offset: 0x24
Bit

31

30

29

28

Register Name: RX_CTL_0
R/W

R/W

R/W

R/W

R/W

Default/Hex

Description

0

RX_EN
Enable receiver
0: Disable receiver after current reception
1: Enable

0

RX_FRM_LEN_CTL
0: Allow to receive frames less than or equal to 2,048 bytes (10,240 if
JUMBO_FRM_EN is set) and cuts off any bytes received after that
1: Allow to receive frames of up to 16,384 bytes

0

JUMBO_FRM_EN
When set, allows Jumbo frames of 9,018 bytes without reporting a giant
frame error in the receive frame status.

0

STRIP_FCSWhen set, strip the Pad/FCS field on received frames only when thelength’s field value is less than or equal to 1,500 bytes.

27

R/W

0

CHECK_CRC
When set, calculate CRC and check the IPv4 Header Checksum.

26:18

/

/

/

0

RX_PAUSE_FRM_MD
0: Only detect multicast pause frame specified in the 802.3x standard.
1: In addition to detect multicast pause frame specified in the 802.3x
standard, also detect unicast pause frame with address specified in MAC

17

R/W

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Address 0 High Register and MAC address 0 Low Register.

16

R/W

0

RX_FLOW_CTL_EN
When set, enable the functionality that decode the received pause
frame and disable its transmitter for a specified time by pause frame.

15:0

/

/

/

7.9.4.10. Receive Control 1 Register(Default Value: 0x00000000)
Offset: 0x28
Bit

31

Register Name: RX_CTL_1
R/W

R/W

Default/Hex

Description0

RX_DMA_START
When set, the RX DMA will go no to work. It is cleared internally andalways read a 0.

30

R/W

0

RX_DMA_EN
0: Stop RX DMA after finish receiving current frame
1: Start and run RX DMA

29:25

/

/

/

0

RX_FIFO_FLOW_CTL
0: Disable RX flow control
1: Enable RX flow control based on RX_FLOW_CTL_TH_DEACT and
RX_FLOW_CTL_TH_ACT0

RX_FLOW_CTL_TH_DEACT
The threshold for deactivating flow control in both half-duplex modeand full-duplex mode
00: Full minus 1 KB
01: Full minus 2 KB
10: Full minus 3 KB
11: Full minus 4 KB

24

23:22

R/W

R/W

21:20

R/W

0

RX_FLOW_CTL_TH_ACT
The threshold for activating flow control in both half-duplex mode andfull-duplex mode.
00: Full minus 1 KB
01: Full minus 2 KB
10: Full minus 3 KB
11: Full minus 4 KB

19:6

/

/

/

0

RX_TH
The threshold value of RX DMA FIFO. When RX_MD is 0, RX DMA starts
to transfer data when the size of received frame in RX DMA FIFO isgreater than the threshold. In addition, full frames with a length lessthan the threshold are transferred automatically.
00: 6401: 32

5:4

R/W

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10: 96
11: 128

3

2

1

0

R/W

R/W

R/W

R/W

0

RX_ERR_FRM
0: RX DMA drops frames with error
1: RX DMA forwards frames with error

0

RX_RUNT_FRM
When set, forward undersized frames with no error and length less than64bytes0

RX_MD
0: RX DMA reads data from RX DMA FIFO to host memory after thenumber of data in RX DAM FIFO is greater than RX_TH
1: RX DMA reads data from RX DMA FIFO to host memory after acomplete frame has been written to RX DMA FIFO

0

FLUSH_RX_FRM
The functionality that flush the frames when receive descriptors/buffers
is unavailable
0: Enable
1: Disable

7.9.4.11. Receive DMA Descriptor List Address Register(Default Value: 0x00000000)
Offset: 0x34
Bit
31:0

Register Name: RX_DMA_LIST
R/W
R/W

Default/Hex

Description0

RX_DESC_LIST
The base address of receive descriptor list. It must be 32-bit aligned.

7.9.4.12. Receive Frame Filter Register(Default Value: 0x00000000)
Offset: 0x38
Bit

Register Name: RX_FRM_FLT
R/W

Default/Hex

Description

31

R/W

0

DIS_ADDR_FILTER
0: Enable address filter
1: Disable address filter

30:18

/

/

/

0

DIS_BROADCAST
0: Receive all broadcast frames
1: Drop all broadcast frames
RX_ALL_MULTICAST
0: Filter multicast frame according to HASH_MULTICAST
1: Receive all multicast frames

17

R/W

16

R/W

0

15:14

/

/

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13:12

R/W

0

CTL_FRM_FILTER
00, 01: Drop all control frames
10: Receive all control frames
11: Receive all control frames when pass the address filter

11:10

/

/

/

0

HASH_MULTICAST
0: Filter multicast frames by comparing the DA field with the values in
DA MAC address registers
1: Filter multicast frames according to the hash table

9

R/W

8

R/W

0

HASH_UNICAST
0: Filter unicast frames by comparing the DA field with the values in DA
MAC address registers
1: Filter unicast frames according to the hash table

7

/

/

/

0

SA_FILTER_EN
0: Receive frames and update the result of SA filter
1: Update the result of SA filter. In addition, if the SA field of received
frame does not match the values in SA MAC address registers, drop thisframe.

0

SA_INV_FILTER
0: When the SA field of current frame matches the values in SA MAC
address registers, it passes the SA filter
1: When the SA filed of current frame does not match the values in SA
MAC address registers,, it passes the SA filter

6

5

R/W

R/W

4

R/W

0

DA_INV_FILTER
0: Normal filtering of frames is performed
1: Filter both unicast and multicast frames by comparing DA field ininverse filtering mode

3:2

/

/

/

0

FLT_MD
0: If the HASH_MULTICAST or HASH_UNICAST is set, the frame is passed
only when it matches the Hash filter
1: Receive the frame when it pass the address register filter or the hashfilter(set by HASH_MULTICAST or HASH_UNICAST)

0

RX_ALL
0: Receive the frames that pass the SA/DA address filter
1: Receive all frames and update the result of address filter(pass or fail)in the receive status word

1

0

R/W

R/W

7.9.4.13. Receive Hash Table 0 Register(Default Value: 0x00000000)
Offset: 0x40
Bit

Register Name: RX_HASH_0
R/W

Default/Hex

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HASH_TAB_0

31:0

R/W

0

The upper 32 bits of Hash table for receive frame filter.

7.9.4.14. Receive Hash Table 1 Register(Default Value: 0x00000000)
Offset: 0x44
Bit

Register Name: RX_HASH_1
R/W

Default/Hex

Description
HASH_TAB_1

31:0

R/W

0

The lower 32 bits of Hash table for receive frame filter.

7.9.4.15. MII Command Register(Default Value: 0x00000000)
Offset: 0x48

Register Name: MII_CMD

Bit

R/W

Default/Hex

Description

31:23

/

/

/

22:20

R/W

0

MDC_DIV_RATIO_M
MDC clock divide ration(m). The source of MDC clock is AHB clock.
000: 16001: 32010: 64011: 128
Others: Reserved

19:17

/

/

/

16:12

R/W

0

PHY_ADDR
Select a PHY device from 32 possible candidates.

11:9

/

/

/

8:4

R/W

0

PHY_REG_ADDR
Select register in the selected PHY device

3:2

/

/

/

0

MII_WR
0: Read register in selected PHY and return data in EMAC_GMII_DATA
1: Write register in selected PHY using data in EMAC_GMII_DATA

0MII_BUSYThis bit indicates that a read or write operation is in progress. When
prepared the data and register address for a write operation or theregister address for a read operation, set this bit and start to accessregister in PHY.
When this bit is cleared automatically, the read or write operation isover and the data in EMAC_GMII_DATA is valid for a read operation.

1

0

R/W

R/W

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7.9.4.16. MII Data Register(Default Value: 0x00000000)
Offset: 0x4C

Register Name: MII_DATA

Bit

R/W

Default/Hex

Description

31:16

/

/

/

0

MII_DATAThe 16-bit data to be written to or read from the register in the selected
PHY.

15:0

R/W

7.9.4.17. MAC Address 0 High Register(Default Value: 0x0000FFFF)
Offset: 0x50

Register Name: ADDR0_HIGH

Bit

R/W

Default/Hex

Description

31:16

/

/

/

0xFFFF

MAC_ADDR_0_HIGH
The upper 16bits of the 1st MAC address.

15:0

R/W

7.9.4.18. MAC Address 0 Low Register(Default Value: 0xFFFFFFFF)
Offset: 0x54
Bit
31:0

Register Name: ADDR0_LOW
R/W
R/W

Default/Hex

Description

0xFFFFFFFF

MAC_ADDR_0_LOW
The lower 32bits of 1st MAC address.

7.9.4.19. MAC Address x High Register(Default Value: 0x0000FFFF)
Offset: 0x50+8*x (x=1~7)

Register Name: ADDRx_HIGH

Bit

Default/Hex

Description

0

MAC_ADDR_CTL
0: MAC address x(x: 1~7) is not valid, and it will be ignored by theaddress filter
1: MAC address x(x：1~7) is valid

0.

MAC_ADDR_TYPE
1: MAC address x(x:1~7) used to compare with the source address of thereceived frame
0: MAC address x(x:1~7) used to compare with the destination addressof the received frame0

MAC_ADDR_BYTE_CTL
MAC address byte control mask. The lower bit of mask controls the

31

30
29:24

R/W

R/W

R/W
R/W

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lower byte of in MAC address x(x:1~7). When the bit of mask is 1, do notcompare the corresponding byte.
23:16
15:0

/
R/W

/

/

0xFFFF

MAC_ADDR_x_HIGH
The upper 16bits of the MAC address x(x:1~7).

7.9.4.20. MAC Address x Low Register(Default Value: 0xFFFFFFFF)
Offset: 0x54+8*x (x=1~7)

Register Name: ADDRx_LOW

Bit

Default/Hex

Description

0xFFFFFFFF

MAC_ADDR_x_LOW
The lower 32bits of MAC address x(x:1~7).

31:0

R/W
R/W

7.9.4.21. Transmit DMA Status Register(Default Value: 0x00000000)
Offset: 0xB0

Register Name: TX_DMA_STA

Bit

R/W

Default/Hex

Description

31:3

/

/

/

0

TX_DMA_STA
The state of Transmit DMA FSM.
000: STOP: When reset or disable TX DMA;
001: RUN_FETCH_DESC: Fetching TX DMA descriptor;
010: RUN_WAIT_STA: Waiting for the status of TX frame;
011: RUN_TRANS_DATA: Passing frame from host memory to TX DMA
FIFO;
111: RUN_CLOSE_DESC: Closing TX descriptor.
110: SUSPEND: TX descriptor unavailable or TX DMA FIFO underflow;
100, 101: Reserved;

2:0

R

7.9.4.22. Transmit DMA Current Descriptor Register(Default Value: 0x00000000)
Offset: 0xB4

Register Name: TX_DMA_CUR_DESC

Bit

R/W

Default/Hex

Description

31:0

R

0

The address of current transmit descriptor.

7.9.4.23. Transmit DMA Current Buffer Address Register(Default Value: 0x00000000)
Offset: 0xB8

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Bit

R/W

Default/Hex

Description

31:0

R

0

The address of current transmit DMA buffer.

7.9.4.24. Receive DMA Status Register(Default Value: 0x00000000)
Offset: 0xC0

Register Name: RX_DMA_STA

Bit

R/W

Default/Hex

Description

31:3

/

/

/

0

RX_DMA_STA
The state of RX DMA FSM.
000: STOP: When reset or disable RX DMA;.
001: RUN_FETCH_DESC: Fetching RX DMA descriptor;
011: RUN_WAIT_FRM: Waiting for frame.
100: SUSPEND: RX descriptor unavailable;
101: RUN_CLOSE_DESC: Closing RX descriptor.
111: RUN_TRANS_DATA: Passing frame from host memory to RX DMA
FIFO;
010, 110: Reserved.

2:0

R

7.9.4.25. Receive DMA Current Descriptor Register(Default Value: 0x00000000)
Offset: 0xC4

Register Name: RX_DMA_CUR_DESC

Bit

R/W

Default/Hex

Description

31:0

R

0

The address of current receive descriptor

7.9.4.26. Receive DMA Current Buffer Address Register(Default Value: 0x00000000)
Offset: 0xC8

Register Name: RX_DMA_CUR_BUF

Bit

R/W

Default/Hex

Description

31:0

R

0

The address of current receive DMA buffer

7.9.4.27. RGMII Status Register(Default Value: 0x00000000)
Offset: 0xD0

Register Name: RGMII_STA

Bit

R/W

Default/Hex

Description

31:4

/

/

/

0

RGMII_LINK
The link status of RGMII interface

3

R

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0: down
1: up

2:1

0

R

R

0

RGMII_LINK_SPD
The link speed of RGMII interface
00: 2.5 MHz
01: 25 MHz
10: 125 MHz

0

RGMII_LINK_MD
The link Mode of RGMII interface
0: Half-Duplex
1: Full-Duplex

7.9.5. EMAC RX/TX Descriptor
The EMAC’ internal DMA transfers data between host memory and internal RX/TX FIFO with a linked list ofdescriptors. Each descriptor is consisted of four words, and contains some necessary information totransfer TX and RX frames. The descriptor list structure is shown in Figure 7-20. The address of each
descriptor must be 32-bit aligned.
1st Desc

2nd Desc

3rd Desc

Desc List Base Addr

N-th Desc…

1st: Status

1st: Status

1st: Status

1st: Status

2nd: Buffer Size

2nd: Buffer Size

2nd: Buffer Size

2nd: Buffer Size

2rd: Buffer Addr

2rd: Buffer Addr

2rd: Buffer Addr

2rd: Buffer Addr

4th: Next Desc

4th: Next Desc

4th: Next Desc

4th: Next Desc

Figure 7-20. EMAC RX/TX Descriptor List

7.9.5.1. Transmit Descriptor
1st Word of Transmit Descriptor
Bits

Description

31

TX_DESC_CTL
When set, current descriptor can be used by DMA. This bit is cleared by DMA when the whole frame istransmitted or all data in current descriptor’s buffer are transmitted.

30:17

Reserved

16

TX_HEADER_ERR

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When set, the checksum of transmitted frame’s header is wrong.
15

Reserved

14

TX_LENGHT_ERR
When set, the length of transmitted frame is wrong.

13

Reserved

12

TX_PAYLOAD_ERR
When set, the checksum of transmitted frame’s payload is wrong.

11

Reserved

10

TX_CRS_ERR
When set, carrier is lost during transmission.

9

TX_COL_ERR_0
When set, the frame is aborted because of collision after contention period.

8

TX_COL_ERR_1
When set, the frame is aborted because of too many collisions.

7

Reserved.

6:3

TX_COL_CNT
The number of collisions before transmission.

2

TX_DEFER_ERR
When set, the frame is aborted because of too much deferral.

1

TX_UNDERFLOW_ERR
When set, the frame is aborted because of TX FIFO underflow error.

0

TX_DEFER
When set in Half-Duplex mode, the EMAC defers the frame transmission.

2nd Word of Transmit Descriptor
Bits

Description

31

TX_INT_CTL
When set and the current frame have been transmitted, the TX_INT in Interrupt Status Register will be
set.

30

LAST_DESC
When set, current descriptor is the last one for current frame.

29

FIR_DESC
When set, current descriptor is the first one for current frame.

28:27

CHECKSUM_CTL
These bits control to insert checksums in transmit frame.

26

CRC_CTL
When set, CRC field is not transmitted.

25:11

Reserved

10:0

BUF_SIZEThe size of buffer specified by current descriptor.

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3rd Word of Transmit Descriptor
Bits

Description

31:0

BUF_ADDR
The address of buffer specified by current descriptor.

4th Word of Transmit Descriptor
Bits

Description

31:0

NEXT_DESC_ADDR
The address of next descriptor. It must be 32-bit aligned.

7.9.5.2. Receive Descriptor
1st Word of Receive Descriptor
Bits

Description

31

RX_DESC_CTL
When set, current descriptor can be used by DMA. This bit is cleared by DMA when complete frame isreceived or current descriptor’s buffer is full.

30

RX_DAF_FAIL
When set, current frame don’t pass DA filter.

29:16

RX_FRM_LEN
When LAST_DESC is not set and no error bit is set, this field is the length of received data for current
frame.
When LAST_DESC is set, RX_OVERFLOW_ERR and RX_NO_ENOUGH_BUF_ERR are not set, this field isthe length of receive frame.

15

Reserved

14

RX_NO_ENOUGH_BUF_ERR
When set, current frame is clipped because of no enough buffer.

13

RX_SAF_FAIL
When set, current fame don’t pass SA filter.

12

Reserved.

11

RX_OVERFLOW_ERR
When set, a buffer overflow error occurred and current frame is wrong.

10

Reserved

9

FIR_DESC
When set, current descriptor is the first descriptor for current frame.

8

LAST_DESC
When set, current descriptor is the last descriptor for current frame.

7

RX_HEADER_ERR
When set, the checksum of frame’s header is wrong.

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6

RX_COL_ERR
When set, there is a late collision during reception in half-duplex mode.

5

Reserved.

4

RX_LENGTH_ERR
When set, the length of current frame is wrong.

3

RX_PHY_ERR
When set, the receive error signal from PHY is asserted during reception.

2

Reserved.

1

RX_CRC_ERR
When set, the CRC filed of received frame is wrong.

0

RX_PAYLOAD_ERR
When set, the checksum or length of received frame’s payload is wrong.

2nd Word of Receive Descriptor
Bits

Description

31

RX_INT_CTL
When set and a frame have been received, the RX_INT will not be set.

30:11

Reserved

10:0

BUF_SIZEThe size of buffer specified by current descriptor.

3rd Word of Receive Descriptor
Bits

Description

31:0

BUF_ADDR
The address of buffer specified by current descriptor.

4th Word of Receive Descriptor
Bits

Description

31:0

NEXT_DESC_ADDR
The address of next descriptor. This field must be 32-bit aligned.

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7.10. TSC
7.10.1. Overview
The transport stream controller(TSC) is responsible for de-multiplexing and pre-processing the inputting
multimedia data defined in ISO/IEC 13818-1.
The transport stream controller receives multimedia data stream from SSI (Synchronous Serial Port)/SPI(Synchronous Parallel Port) inputs and de-multiplexing the data into Packets by PID (Packet Identify). Before
the Packet to be store to memory by DMA, it can be pre-processing by the Transport Stream Descrambler.
The transport stream controller can be used for almost all multi-media application cases, example: DVB Set top
Box, IPTV, Streaming-media Box, multi-media players and so on.
The Transport Stream Controller (TSC) includes the following features:Supports industry-standard AMBA Host Bus (AHB) and it is fully compliant with the AMBA Specification,
Revision 2.0. Supports 32-bit Little Endian bus.
Supports AHB 32-bit bus widthOne external Synchronous Parallel Interface (SPI) or one external Synchronous Serial Interface (SSI)
32 channels PID filterMultiple transport stream packet (188, 192, 204) format support

SPI and SSI timing parameters are configurable
Hardware packet synchronous byte error detectingHardware PCR packet detectingConfigurable SPI transport stream generator for streams in DRAM memory
DMA is supported for transferring dataInterrupt is supported
Support DVB-CSA V1.1 Descrambler
The Top Diagram of TSC is shown below:

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Figure 7-21. TSC Block Diagram
Note:
TSC – TS Controller
TSF – TS Filter
TSD – TS Descrambler
TSG – TS Generator

7.10.2. Transport Stream Input Timing Diagram
Table 7-1. Input Signals Description
Name

Description

Clock

Clock of SPI/SSI data input

Psync

Packet sync (or Start flag) for TS packet

DvalidData valid flag for TS data input

Error

Error flag for TS data, but do not used by TSC

Data[7:0]

TS data input.
Data[7:0] are used in SPI mode;
Only Data[0] is used in SSI mode.

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Figure 7-22. Input Timing for SPI mode
(CLOCK = Rising Edge, PSYNC = High Active, DVALID = High Active, Packet Size = 188 Bytes)

Figure 7-23. Alternative Input Timing for SPI mode
(CLOCK = Rising Edge, PSYNC = High Active, DVALID = High Active, Packet Size = 188 Bytes)

Figure 7-24. Alternative Input Timing for SSI mode
(CLOCK = Rising Edge, PSYNC = High Active, DVALID = High Active, Packet Size = 188 Bytes)

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7.10.3. Transport Stream Controller Register List
Module Name

Base Address

TSC

0x01C06000

TSG OFFSET

0x00000040

TSF0 OFFSET

0x00000080

TSD OFFSET

0x00000180

Register Name

OffsetDescription

TSC_CTLR

TSC + 0x00

TSC Control Register

TSC_STAR

TSC + 0x04

TSC Status Register

TSC_PCTLR

TSC + 0x10

TSC Port Control Register

TSC_PPARR

TSC + 0x14

TSC Port Parameter Register

TSC_TSFMUXR

TSC + 0x20

TSC TSF Input Multiplex Control Register

TSC_OUTMUXR

TSC + 0x28

TSC Port Output Multiplex Control Register

TSG_CTLR

TSG + 0x00

TSG Control Register

TSG_PPR

TSG + 0x04

TSG Packet Parameter Register

TSG_STAR

TSG + 0x08

TSG Status Register

TSG_CCR

TSG + 0x0c

TSG Clock Control Register

TSG_BBAR

TSG + 0x10

TSG Buffer Base Address Register

TSG_BSZRTSG + 0x14

TSG Buffer Size Register

TSG_BPR

TSG + 0x18

TSG Buffer Pointer Register

TSF_CTLR

TSF + 0x00

TSF Control Register

TSF_PPR

TSF + 0x04

TSF Packet Parameter Register

TSF_STAR

TSF + 0x08

TSF Status Register

TSF_DIER

TSF + 0x10

TSF DMA Interrupt Enable Register

TSF_OIER

TSF + 0x14

TSF Overlap Interrupt Enable Register

TSF_DISRTSF + 0x18

TSF DMA Interrupt Status Register

TSF_OISRTSF + 0x1c

TSF Overlap Interrupt Status Register

TSF_PCRCR

TSF + 0x20

TSF PCR Control Register

TSF_PCRDR

TSF + 0x24

TSF PCR Data Register

TSF_CENR

TSF + 0x30

TSF Channel Enable Register

TSF_CPER

TSF + 0x34

TSF Channel PES Enable Register

TSF_CDER

TSF + 0x38

TSF Channel Descramble Enable Register

TSF_CINDR

TSF + 0x3c

TSF Channel Index Register

TSF_CCTLR

TSF + 0x40

TSF Channel Control Register

TSF_CSTAR

TSF + 0x44

TSF Channel Status Register

TSF_CCWIRTSF + 0x48

TSF Channel CW Index Register

TSF_CPIDRTSF + 0x4c

TSF Channel PID Register

TSF_CBBAR

TSF + 0x50

TSF Channel Buffer Base Address Register

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TSF_CBSZR

TSF + 0x54

TSF Channel Buffer Size Register

TSF_CBWPR

TSF + 0x58

TSF Channel Buffer Write Pointer Register

TSF_CBRPR

TSF + 0x5c

TSF Channel Buffer Read Pointer Register

TSD_CTLR

TSD + 0x00

TSD Control Register

TSD_STARTSD + 0x04

TSD Status Register

TSD_CWIR

TSD + 0x1c

TSD Control Word Index Register

TSD_CWR

TSD + 0x20

TSD Control Word Register

7.10.4. Transport Stream Controller Register Description
7.10.4.1. TSC Control Register(Default Value: 0x00000000)
Offset: 0x00

Register Name: TSC_CTLR

Bit

R/W

Default/Hex

Description

31:0

/

/

/

7.10.4.2. TSC Status Register(Default Value: 0x00000000)
Offset: 0x04

Register Name: TSC_STAR

Bit

R/W

Default/Hex

Description

31:0

/

/

/

7.10.4.3.

TSC Port Control Register(Default Value: 0x00000000)

Offset: 0x10

Register Name: TSC_PCTLR

Bit

R/W

Default/Hex

Description

31:1

/

/

/

0

TSInPort0Ctrl
TS Input Port0 Control
0 – SPI
1 – SSI

07.10.4.4.

R/W

TSC Port Parameter Register(Default Value: 0x00000000)

Offset: 0x14
Bit

Register Name: TSC_PPARR
R/W

Default/Hex

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/

31:8

/

/
TSInPort0Par
TS Input Port0 Parameters

7:0

7.10.4.5.

R/W

Bit

Definition

7:5

Reserved

4

SSI data order
0: MSB first for one byte data
1: LSB first for one byte data

3

CLOCK signal polarity
0 : Rise edge capturing
1: Fall edge capturing

2

ERROR signal polarity
0: High level active
1: Low level active

1

DVALID signal polarity
0: High level active
1: Low level active

0

PSYNC signal polarity
0: High level active
1: Low level active

0x00

TSC TSF Input Multiplex Control Register(Default Value: 0x00000000)

Offset: 0x20

Register Name: TSC_TSFMUXR

Bit

R/W

Default/Hex

Description

31:4

/

/

/

0x0

TSF0InputMuxCtrl
TSF0 Input Multiplex Control
0x0 –Data from TSG
0x1 –Data from TS IN Port0
Others – Reserved

3:0

7.10.4.6.

R/W

TSC Port Output Multiplex Control Register(Default Value: 0x00000000)

Offset: 0x28

Register Name: TSC_TSFMUXR

Bit

R/W

Default/Hex

Description

31:0

/

/

/

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7.10.4.7.

TSC Port Output Multiplex Control Register(Default Value: 0x00000000)

Offset: TSG+0x00

Register Name: TSC_TSFMUXR

Bit

R/W

Default/Hex

Description

31:26

/

/

/

25:24

R

0

TSGStsStatus for TS Generator
0: IDLE state
1: Running state
2: PAUSE state
Others: Reserved

23:10

/

/

/

0

TSGLBufMode
Loop Buffer Mode
When set to ‘1’, the TSG external buffer is in loop mode.

9

R/W

8

R/W

0

TSGSyncByteChkEn
Sync Byte Check Enable
Enable/ Disable check SYNC byte fro receiving new packet
0: Disable
1: Enable
If enable check SYNC byte and an error SYNC byte is receiver, TS
Generator would come into PAUSE state. If the correspond interrupt isenable, the interrupt would happen.

7:3

/

/

/

0

TSGPauseBit
Pause Bit for TS Generator
Write ‘1’ to pause TS Generator. TS Generator would stop fetch newdata from DRAM. After finishing this operation, this bit will clear to zeroby hardware. In PAUSE state, write ‘1’ to resume this state.

0

TSGStopBit
Stop Bit for TS Generator
Write ‘1’ to stop TS Generator. TS Generator would stop fetch new datafrom DRAM. The data already in its FIFO should be sent to TS filter. After
finishing this operation, this bit will clear to zero by hardware.

0

TSGStartBit
Start Bit for TS Generator
Write ‘1’ to start TS Generator. TS Generator would fetch data from
DRAM and generate SPI stream to TS filter. This bit will clear to zero by
hardware after TS Generator is running.

2

1

0

R/W

R/W

R/W

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7.10.4.8. TSG Packet Parameter Register(Default Value: 0x00470000)
Offset: TSG+0x04

Register Name: TSG_PPR

Bit

R/W

Default/Hex

Description

31:24

/

/

/

23:16

R/W

0x47

SyncByteVal
Sync Byte Value
This is the value of sync byte used in the TS Packet.

15:8

/

/

/

7

R/W

0

SyncBytePos
Sync Byte Position
0: the 1st byte position
1: the 5th byte position
Notes: This bit is only used for 192 bytes packet size.

6:2

/

/

/

0

PktSize
Packet Size
Byte Size for one TS packet
0: 188 bytes
Others: Reserved

1:0

7.10.4.9.

R/W

TSG Interrupt Enable and Status Register(Default Value: 0x00000000)

Offset: TSG+0x08

Register Name: TSG_IESR

Bit

R/W

Default/Hex

Description

31:20

/

/

/

0

TSGEndIE
TS Generator (TSG) End Interrupt Enable
0: Disable
1: Enable
If set this bit, the interrupt would assert to CPU when all data in external
DRAM are sent to TS PID filter.

0

TSGFFIE
TS Generator (TSG) Full Finish Interrupt Enable
0: Disable
1: Enable

19

18

R/W

R/W

17

R/W

0

TSGHFIE
TS Generator (TSG) Half Finish Interrupt Enable
0: Disable
1: Enable

16

R/W

0

TSGErrSyncByteIETS Generator (TSG) Error Sync Byte Interrupt Enable

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Interfaces
0: Disable
1: Enable
15:4

3

2

1

0

/

R/W

R/W

R/W

R/W

/

/

0

TSGEndSts
TS Generator (TSG) End Status
Write ‘1’ to clear.

0

TSGFFSts
TS Generator (TSG) Full Finish Status
Write ‘1’ to clear.

0

TSGHFSts
TS Generator (TSG) Half Finish Status
Write ‘1’ to clear.

0

TSGErrSyncByteSts
TS Generator (TSG) Error Sync Byte Status
Write ‘1’ to clear.

7.10.4.10. TSG Clock Control Register(Default Value: 0x00000000)
Offset: TSG+0x0C
Bit

31:16

15:0

R/W

R/W

R/W

Register Name: TSG_CCR
Default/Hex

Description

0x0

TSGCDF_N
TSG Clock Divide Factor (N)The Numerator part of TSG Clock Divisor Factor.

0x0

TSGCDF_D
TSG Clock Divide Factor (D)The Denominator part of TSG Clock Divisor Factor.
Frequency of output clock:Fo = (Fi*(N+1))/(8*(D+1)).
Fi is the input special clock of TSC, and D must not less than N.

7.10.4.11. TSG Buffer Base Address Register(Default Value: 0x00000000)
Offset: TSG+0x10

Register Name: TSG_BBAR

Bit

R/W

Default/Hex

Description

31:28

/

/

/

0x0

TSGBufBase
Buffer Base AddressThis value is a start address of TSG buffer.
Note: This value should be 4-word (16Bytes) align, and the lowest 4-bitof this value should be zero.

27:0

RW

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Interfaces
7.10.4.12. TSG Buffer Size Register(Default Value: 0x00000000)
Offset: TSG+0x14

Register Name: TSG_BSZR

Bit

R/W

Default/Hex

Description

31:24

/

/

/

0

TSGBufSize
Data Buffer Size for TS Generator
It is in byte unit.
The size should be 4-word (16Bytes) align, and the lowest 4 bits shouldbe zero.

23:0

R/W

7.10.4.13. TSG Buffer Point Register(Default Value: 0x00000000)
Offset: TSG+0x18

Register Name: TSG_BPR

Bit

R/W

Default/Hex

Description

31:24

/

/

/

0

TSGBufPtr
Data Buffer Pointer for TS Generator
Current TS generator data buffer read pointer (in byte unit)

23:0

R

7.10.4.14. TSF Control and Status Register(Default Value: 0x00000000)
Offset: TSF+0x00

Register Name: TSF_CSR

Bit

R/W

Default/Hex

Description

31:3

/

/

/

2

R/W

0

TSF Enable
0: Disable TSF Input
1: Enable TSF Input

1

/

/

/
TSFGSRTSF Global Soft Reset
A software writing ‘1’ will reset all status and state machine of TSF. And
it’s cleared by hardware after finish reset.
A software writing ‘0’ has no effect.

07.10.4.15. TSF Packet Parameter Register(Default Value: 0x00470000)
Offset: TSF+0x04
Bit

R/W

Register Name: TSF_PPR
Default/Hex

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Description

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Interfaces

31:28

27:24

R/W

R/W

0

LostSyncThd
Lost Sync Packet Threshold
It is used for packet sync lost by checking the value of sync byte.

0

SyncThd
Sync Packet Threshold
It is used for packet sync by checking the value of sync byte.

23:16

R/W

0x47

SyncByteVal
Sync Byte Value
This is the value of sync byte used in the TS Packet.

15:10

/

/

/

0

SyncMthd
Packet Sync Method
0: By PSYNC signal
1: By sync byte
2: By both PSYNC and Sync Byte
3: Reserved

9:8

R/W

7

R/W

0

SyncBytePos
Sync Byte Position
0: the 1st byte position
1: the 5th byte position
Notes: This bit is only used for 192 bytes packet size.

6:2

/

/

/

0

PktSize
Packet Size
Byte Size for one TS packet
0: 188 bytes
1: 192 bytes
2: 204 bytes
3: Reserved

1:0

R/W

7.10.4.16. TSF Interrupt Enable and Status Register(Default Value: 0x00000000)
Offset: TSF+0x08

Register Name: TSF_IESR

Bit

R/W

Default/Hex

Description

31:20

/

/

/

0

TSFFOIE
TS PID Filter (TSF) Internal FIFO Overrun Interrupt Enable
0: Disable
1: Enable

0

TSFPPDIE
TS PCR Packet Detect Interrupt Enable
0: Disable
1: Enable

19

18

R/W

R/W

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Interfaces

17

R/W

0

TSFCOIE
TS PID Filter (TSF) Channel Overlap Interrupt Global Enable
0: Disable
1: Enable

16

R/W

0

TSFCDIE
TS PID Filter (TSF) Channel DMA Interrupt Global Enable
0: Disable
1: Enable

15:4

/

/

/

0

TSFFOISTS PID Filter (TSF) Internal FIFO Overrun Status
Write ‘1’ to clear.

0

TSFPPDISTS PCR Packet Found Status
When it is ‘1’, one TS PCR Packet is found. Write ‘1’ to clear.

0

TSFCOISTS PID Filter (TSF) Channel Overlap Status
It is global status for 16 channel. It would clear to zero after all channels
status bits are clear.

0

TSFCDISTS PID Filter (TSF) Channel DMA status
It is global status for 16 channel. It would clear to zero after all channels
status bits are clear.

3

2

1

0

R/W

R/W

R

R

7.10.4.17. TSF DMA Interrupt Enable Register(Default Value: 0x00000000)
Offset: TSF+0x10
Bit

31:0

R/W

R/W

Register Name: TSF_DIER
Default/Hex

Description

0x0

DMAIE
DMA Interrupt Enable
DMA interrupt enable bits for channel 0~31.

7.10.4.18. TSF Overlap Interrupt Enable Register(Default Value: 0x00000000)
Offset: TSF+0x14
Bit

31:0

R/W

R/W

Register Name: TSF_OIER
Default/Hex

Description

0x0

OLPIE
Overlap Interrupt Enable
Overlap interrupt enable bits for channel 0~31.

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Interfaces
7.10.4.19. TSF DMA Interrupt Status Register(Default Value: 0x00000000)
Offset: TSF+0x18
Bit

31:0

R/W

R/W

Register Name: TSF_DISR
Default/Hex

Description

0x0

DMAIS
DMA Interrupt Status
DMA interrupt Status bits for channel 0~31.
Set by hardware, and can be cleared by software writing ‘1’.
When both these bits and the corresponding DMA Interrupt Enable bits
set, the TSF interrupt will generate.

7.10.4.20. TSF Overlap Interrupt Status Register(Default Value: 0x00000000)
Offset: TSF+0x1C
Bit

31:0

R/W

R/W

Register Name: TSF_OISR
Default/Hex

Description

0x0

OLPIS
Overlap Interrupt Status
Overlap interrupt Status bits for channel 0~31.
Set by hardware, and can be cleared by software writing ‘1’.
When both these bits and the corresponding Overlap Interrupt Enable
bits set, the TSF interrupt will generate.

7.10.4.21. TSF PCR Control Register(Default Value: 0x00000000)
Offset: TSF+0x20

Register Name: TSF_PCRCR

Bit

R/W

Default/Hex

Description

31:17

/

/

/

16

R/W

0

PCRDE
PCR Detecting Enable
0: Disable
1: Enable

15:13

/

/

/

12:8

R/W

0

PCRCIND
Channel Index m for Detecting PCR packet (m from 0 to 31)

7:1

/

/

/

0

PCRLSBPCR Contest LSB 1 bit
PCR[0]0R

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Interfaces
7.10.4.22. TSF PCR Data Register(Default Value: 0x00000000)
Offset: TSF+0x24
Bit

31:0

R/W

R

Register Name: TSF_PCRDR
Default/Hex

Description

0

PCRMSBPCR Data High 32 bits
PCR[33:1]

7.10.4.23. TSF Channel Enable Register(Default Value: 0x00000000)
Offset: TSF+0x30
Bit

31:0

R/W

R/W

Register Name: TSF_CENR
Default/Hex

Description0FilterEn
Filter Enable for Channel 0~31
0: Disable
1: Enable
From Disable to Enable, internal status of the corresponding filter
channel will be reset.

7.10.4.24. TSF PES Enable Register(Default Value: 0x00000000)
Offset: TSF+0x34
Bit

31:0

R/W

R/W

Register Name: TSF_CPER
Default/Hex

Description

0x0

PESEn
PES Packet Enable for Channel 0~31
0: Disable
1: Enable
These bits should not be changed during the corresponding channel
enable.

7.10.4.25. TSF Channel Descramble Enable Register(Default Value: 0x00000000)
Offset: TSF+0x38
Bit

31:0

R/W

R/W

Register Name: TSF_CDER
Default/Hex

Description

0x0

DescEnDescramble Enable for Channel 0~31
0: Disable
1: Enable
These bits should not be changed during the corresponding channel

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Interfaces
enable.

7.10.4.26. TSF Channel Index Register(Default Value: 0x00000000)
Offset: TSF+0x3C

Register Name: TSF_CINDR

Bit

R/W

Default/Hex

Description

31:5

/

/

/

0x0

CHIND
Channel Index
This value is the channel index for channel private registers access.
Range is from 0x00 to 0x1f.
Address range of channel private registers is 0x40~0x7f.

4:0

R/W

7.10.4.27. TSF Channel Control Register(Default Value: 0x00000000)
Offset: TSF+0x40

Register Name: TSF_CCTLR

Bit

R/W

Default/Hex

Description

31:0

/

/

/

7.10.4.28. TSF Channel Status Register(Default Value: 0x00000000)
Offset: TSF+0x44

Register Name: TSF_CSTAR

Bit

R/W

Default/Hex

Description

31:0

/

/

/

7.10.4.29. TSF Channel CW Index Register(Default Value: 0x00000000)
Offset: TSF+0x48

Register Name: TSF_CCWIR

Bit

R/W

Default/Hex

Description

31:3

/

/

/

0x0

CWIND
Related Control Word Index
Index to the control word used by this channel when Descramble Enableof this channel enable.
This value is useless when the corresponding Descramble Enable is ‘0’.

2:0

R/W

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Interfaces
7.10.4.30. TSF Channel PID Register(Default Value: 0x1FFF0000)
Offset: TSF+0x4C
Bit
31:16
15:0

R/W
R/W
R/W

Register Name: TSF_CPIDR
Default/Hex

Description

0x1fffPIDMSK
Filter PID Mask for Channel

0x0

PIDVAL
Filter PID value for Channel

7.10.4.31. TSF Channel Buffer Base Address Register(Default Value: 0x00000000)
Offset: TSF+0x50

Register Name: TSF_CBBAR

Bit

R/W

Default/Hex

Description

31:28

/

/

/

0

TSFBufBAddr
Data Buffer Base Address for Channel
It is 4-word (16Bytes) align address. The LSB four bits should be zero.

27:0

R/W

7.10.4.32. TSF Channel Buffer Size Register(Default Value: 0x00000000)
Offset: TSF+0x54

Register Name: TSF_CBSZR

Bit

R/W

Default/Hex

Description

31:26

/

/

/

25:24

R/W

0

CHDMAIntThd
DMA Interrupt Threshold for Channel
The unit is TS packet size. When received packet (has also stored inDRAM) size is beyond (>=) threshold value, the corresponding channelinterrupt is generated to CPU. TSC should count the new received
packet again, when exceed the specified threshold value, one newinterrupt is generated again.
0: 1/2 data buffer packet size
1: 1/4 data buffer packet size
2: 1/8 data buffer packet size
3: 1/16 data buffer packet size

23:21

/

/

/

0

CHBufPktSz
Data Buffer Packet Size for Channel
The exact buffer size of buffer is N+1 bytes.
The maximum buffer size is 2MB.
This size should be 4-word (16Bytes) aligned. The LSB four bits should be
zero.

20:0

R/W

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Interfaces

7.10.4.33. TSF Channel Write Pointer Register(Default Value: 0x00000000)
Offset: TSF+0x58

Register Name: TSF_CBWPR

Bit

R/W

Default/Hex

Description

31:21

/

/

/

0

BufWrPtr
Data Buffer Write Pointer (in Bytes)
This value is changed by hardware, when data is filled into buffer, thispointer is increased.
And this pointer can be set by software, but it should not be changed bysoftware during the corresponding channel is enable.

20:0

R/W

7.10.4.34. TSF Channel Read Pointer Register(Default Value: 0x00000000)
Offset: TSF+0x5C

Register Name: TSF_CBRPR

Bit

R/W

Default/Hex

Description

31:21

/

/

/

0

BufRdPtr
Data Buffer Read Pointer (in Bytes)
This pointer should be changed by software after the data of buffer is
read.

20:0

R/W

7.10.4.35. TSD Control Register(Default Value: 0x00000000)
Offset: TSD+0x00

Register Name: TSD_CTLR

Bit

R/W

Default/Hex

Description

31:2

/

/

/

0x0

DescArith
Descramble Arithmetic
00: DVB CSA V1.1
Others: Reserved

1:0

R/W

7.10.4.36.

TSD Status Register(Default Value: 0x00000000)

Offset: TSD+0x04

Register Name: TSD_STAR

Bit

R/W

Default/Hex

Description

31:0

/

/

/

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Interfaces

7.10.4.37. TSD Control Word Index Register(Default Value: 0x00000000)
Offset: TSD+0x1C

Register Name: TSD_CWIR

Bit

R/W

Default/Hex

Description

31:3

/

/

/

6:4

R/W

0x0

CWI
Control Word Index
This value is the Control index for Control word access.
Range is from 0x00 to 0x7.

3:2

/

/

/

0x0

CWII
Control Word Internal Index
0 – Odd Control Word Low 32-bit, OCW[31:0];
1 – Odd Control Word High 32-bit, OCW[63:32];
2 – Even Control Word Low 32-bit, ECW[31:0];
3 – Even Control Word High 32-bit, ECW[63:0];

1:0

R/W

7.10.4.38. TSD Control Word Register(Default Value: 0x00000000)
Offset: TSD+0x20
Bit
31:0

R/W
R/W

Register Name: TSD_CWR
Default/Hex

Description

0x0

CWD
Content of Control Word corresponding to the TSD_CWIR value

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Appendix

Appendix
Control signal and data port mapping for TCON:SYNC RGB
Para

I/O

CPU

CPU

CPU

CPU

CPU

cmd

18bit

16bit

8bit

9bit

CCIR

Serial RGB

RGB

1st

2nd

256K

256K

656

3rd

1st

2nd

3rd

1st

256K

65K
2nd

1st

2nd

1st

2nd

65K
3rd

1st

2nd

256K
1st

2nd

LVDS
Single
Link

IO0

VSYNC

CS

D3N

IO1

HSYNC

RD

D3P

IO2

DCLK

WR

CKP

IO3

DE

RS

CKN

D23

R7

D23

R5

R5

B5

G5

R5

R5

B5

R4

D2N

D22

R6

D22

R4

R4

B4

G4

R4

R4

B4

R3

D2P

D21

R5

D21

R3

R3

B3

G3

R3

R3

B3

R2

D1N

D20

R4

D20

R2

R2

B2

G2

R2

R2

B2

R1

D1P

D19

R3

D19

R1

R1

B1

G1

R1

R1

B1

R0

D0N

D18

R2

D18

R0

R0

B0

G0

R0

R0

B0

G5

D0P

D17

R1

D17

D16

R0

D16

D15

G7

D15

G5

G4

D14

G6

D14

G4

G3

D13

G5

D13

G3

D12

G4

D17

D27 D37 D7

D12

G2

G5

R5

B5

G5

B5

G5

G2

R5

G5

B5

R4

G2

R5

G2

D11

G3

D16

D26 D36 D6

D11

G1

G4

R4

B4

G4

B4

G4

G1

R4

G4

B4

R3

G1

R4

G1

D10

G2

D15

D25 D35 D5

D10

G0

G3

R3

B3

G3

B3

G3

G0

R3

G3

B3

R2

G0

R3

G0

D9

G1

D9

D8

G0

D8

D7

B7

D14

D24 D34 D4

D7

B5

G2

R2

B2

G2

B2

G2

B4

R2

G2

B2

R1

B4

R2

B5

D6

B6

D13

D23 D33 D3

D6

B4

G1

R1

B1

G1

B1

G1

B3

R1

G1

B1

R0

B3

R1

B4

D5

B5

D12

D22 D32 D2

D5

B3

G0

R0

B0

G0

B0

G0

B2

R0

G0

B0

G5

B2

R0

B3

D4

B4

D11

D21 D31 D1

D4

B2

B1

G4

B1

G5

B2

D3

B3

D10

D20 D30 D0

D3

B1

B0

G3

B0

G4

B1

D2

B2

D2

B0

G3

B0

D1

B1

D1

D0

B0

D0

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