SHF Communication Technologies AGWilhelm-von-Siemens-Str. 23D • 12277 Berlin • Germany
Phone ++49 30 / 772 05 10 • Fax ++49 30 / 753 10 78
E-Mail: sales@shf.de • Web: http://www.shf.deDatasheet
SHF 431B55 Gbps
D-type Flip Flop (DFF)Description
The SHF 431B is a D-type flip-flop (DFF) module capable of broadband operation up to 55 Gbps.
AC-coupled and 50 Ω terminated data and clock inputs ensure proper line termination anduncomplicated application. Optimum bias point for the data input can be set using the data bias
connector.

Features••••

Broadband operation up to 55 Gbps
Differential output, 250 mVpp single ended output swing
Low power consumption
single ended operation (data and clock input)

Applications••

OC-768/STM-256 applications
Broadband test and measurement equipment

Option•Option bias adjust (BA): Module comes along with a wall power supply. One potentiometers toallow data bias to be adjusted without the need for additional power supplies.

SHF reserves the right to change specifications and design without notice - SHF 431B DFF Revision 001 - 16/May/2008 Page 2/6Specifications
Parameter

SymbolUnit

Min

TypMaxMinimum input data rate

1Rin,min

Gbps

Maximum input data rate

Rin,max

Gbps

50

Data input voltage

DinmVpp3001000

GHz

5501000

Conditions

Performance

Clock input frequency
Clock input voltage

CLKin

mVpp

500

Input return loss

S11dB

5mV

250

Single ended output
swing
Rise/Fall time

tr/tf

RMS jitter
Output return loss

S22

Data/Clock bias adjust

5500mVpp clock signal

55500mVpp clock signal
Eye Height

Eye Amplitude, into 50 Ωload

ps920%/80%fs400600

dB5V-5-2.50-4.5-5-5.5

Operating conditions
Power supply

VEEV

Supply current

IEEmA

100

Power consumption

TdmW

500

Operating temperature

Top°CDimensions

10@ VEE = -5V
5059x40x18mm1) The theoretical limit is DC, practical limit depends on slew rate of clock signal.

Block Diagram

V (1.85mm) female

Data

V (1.85mm) female

ClockY

V (1.85mm) femaleY

V (1.85mm) female

DFF

Voltage
Regulator

VEE = -5V

SHF reserves the right to change specifications and design without notice - SHF 431B DFF Revision 001 - 16/May/2008 Page 3/6Sensitivity and Clock Phase Margin Measurements
31

The measurements below have been performed using a SHF 12100A BPG (PRBS 2 -1,Vamplitude = 400 mV), a SHF 11100A Error Analyzer and an Agilent 86100B DCA with Precision
Time Base Module (86107A) and 70 GHz Sampling Head (86118A) to determine the eye heightand jitter contribution of the input signal. In case of the sensitivity measurement the input signal
has been reduced until a BER limit of 10-9 was achieved. For the CPM measurement the phase ofthe clock signal was varied until the BER reached the 10-9 limit.

Typical Sensitivity Measurement
140Eye Height [mV]

12010080604020040435055

Bitrate [Gbps]

Typical Clock Phase Margin Measurement

Clock Phase Margin [deg]30025020015010050040435055

Bitrate [Gbps]

SHF reserves the right to change specifications and design without notice - SHF 431B DFF Revision 001 - 16/May/2008 Page 4/6

Output waveforms
31The measurements below have been performed using a SHF 12100A BPG (PRBS 2 -1,
Vamplitude = 400 mV) and an Agilent 86100B DCA with Precision Time Base Module (86107A) and70 GHz Sampling Head (86118A). The output of the DFF module has been connected to the DCA
input with a 0.5 m microwave cable assembly.

Y @ 40 Gbps

Y! @ 40 Gbps

Y @ 43 Gbps

Y! @ 43 Gbps

Y @ 50 Gbps

Y! @ 50 Gbps

SHF reserves the right to change specifications and design without notice - SHF 431B DFF Revision 001 - 16/May/2008 Page 5/6

Y @ 55 Gbps

Y! @ 55 Gbps

Outline Drawing
Data Bias

11.2

2

7.2

15.2

-5V

GND4xØ
2.

7

11.3

Clock7.2

28

9.05

34

11.2

40

9.05

11.3

538

Y

32

10YDFF10

SHF 431 B

Data

9.05
18

11.3
PortConnector

Data

V-Connector

Clock

V-Connector

Y

V-Connector

Y

V-Connector

SHF reserves the right to change specifications and design without notice - SHF 431B DFF Revision 001 - 16/May/2008 Page 6/6