Journal of Robotics, Networking and Artificial Life, Vol. 2, No. 4 (March 2016), 209-212

Compensating Temperature-Dependent Characteristics of a Subthreshold-MOSFET Analog
Silicon Neuron
Ethan Green

Department of Electrical Engineering and Information Systems, The University of Tokyo, 4-6-1 Komaba,
Meguro-ku, Tokyo, 153-8505, Japan
Takashi Kohno

Institute of Industrial Science, The University of Tokyo, 4-6-1 Komaba,
Meguro-ku, Tokyo, 153-8505, Japan
E-mail: green@sat.t.u-tokyo.ac.jp, kohno@sat.t.u-tokyo.ac.jp
www.u-tokyo.ac.jp

AbstractAnalog silicon neurons are neuro-mimetic VLSI (very-large-scale-integrated) circuits that replicate theelectrophysiological behavior of animal nerve tissue. This research focuses on the temperature sensitivity of asubthreshold-MOSFET analog silicon neuron. Subthreshold operation of CMOS transistors allows for low power
consumption, but is also drastically sensitive to temperature changes. This critical issue must be addressed before
these circuits can be implemented into massive networks to develop future neuromorphic technologies.
Keywords: neuromorphic engineering, analog VLSI, silicon neurons

1. Introduction
The field of neuromorphic engineering seeks to design
circuits that mimic the electrophysiological behavior
and network structure of neurons to create biologicallyinspired or neuromimetic technology that can perform
calculations in ways fundamentally different fromtraditional digital computers. Motivations for researchin this field include developing brain-like computersand bio-silico hybrid systems for medical devices.
Analog silicon neurons are electronic circuits that
exploit the characteristics of transistors to mimic how
nerve cells control membrane potential. These circuits
operate in continuous time, can replicate a variety of
spike shapes and spiking behavior, and require low
power1,2,3,4. They are expected to be a promising tool toconstruct neuromorphic systems. However, manytechnical challenges must be addressed before thesecircuits can be implemented in large-scale networks. A
possible method to solve a key issue, temperaturesensitivity, is to actively tune the circuit parameters
depending on temperature. We report our approach inwhich appropriate parameter sets for several

temperatures are found and parameter sets forintermediary temperatures are obtained by interpolation.
2. Circuit Description
The circuit used in this research (Fig. 1) is an ultra-low
power VLSI silicon neuron based on qualitative
neuronal modeling1, which seeks to use judicious
approximation and mathematical understanding5 toconvert the model of membrane potential to equations
with fewer variables that are more suitable for circuit
implementation. In the model for this circuit, variable v
represents membrane potential and variable n represents
abstracted ionic activity. The value of each variable iscalculated by subtracting the voltage over eachcapacitor from Vdd (1.0V). These two variables control
the output currents of transconductance circuitcomponents fx(v), gx(v) (x=v,n), and r(n) that charge anddischarge capacitors attached to the v-block and n-blockwithin the circuit. This circuit was shown to support thedynamical behaviors of Class I and II neurons in the
Hodgkin’s classification6. The system equations of thismodel are as follows:

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Ethan Green, Takashi Kohno

Fig. 1. Circuit block diagram of the silicon neuron circuit.

dv= f v ( v ) − g v ( v ) + I av − r ( n ) + I stimdt
dv
Cn= f n ( v ) − g n ( v ) + I an − r ( n )dtFig. 2. Circuit components. (a) fv(v) and fn(v), (b) gv(v), gn(v),and r(n).

(1)

Cv

(2)

Istim is an external stimulus current, and Iav and Ian areconstant currents. The current-voltage characteristics ofthe fx(v), gx(v) (x=v,n), and r(n) components are
expressed by the following sigmoidal relationships:
fx (v) = Mx (1 + exp(−g x (v) = I 0 exp(r ( n) = I 0 exp(κUTκUTκUT(3)(v − δ x )))θ x ) (1 + exp(−θ r ) (1 + exp(−κUTκUT(v − θ x )))(4)(v − θ r )))(5)

I0 is the PMOS transistor off-current, UT is the thermal
voltage (~26 mV at room temperature), and κ is thecapacitive coupling ratio. Parameters Mx, θx, δx (x=v,n),and θr can be tuned by bias voltages applied to thecircuit. All transistors are operated in the subthreshold
regime. Figure 2 (a) shows a differential pair attached toa current mirror used for fv(v) and fn(v). Figure 2 (b)shows the circuit used for gv(v), gn(v), and r(n). This
circuit is a cascoded transistor with source degeneration
and a detached bulk voltage.
This silicon neuron circuit includes a nullclinedrawing function which assists in the diagramming of aphase plane to evaluate the circuit’s dynamicalstructure. For example, a sigmoidally shaped n-nullcline
and cubic-shaped v-nullcline that cross at 3 distinct
points yields Class I behavior in the Hodgkin’sFig. 3. Nullclines in Class I mode.

classification (Fig. 3). The points are characterized
mathematically through analysis with nonlinear
dynamics5.
The temperature sensitivity of this circuit originatesin the intrinsic temperature sensitivity of MOSFETs inthe subthreshold regime. Figure 4 illustrates periodic
spiking behavior in the Class I mode in response to a 4pA sustained stimulus over a narrow range oftemperatures from 25 to 26.5°C. The stimulus begins at
0.2 seconds. As can be seen from the figure, the spiking
frequency varies by temperature, and ceases at 26.5°C.
3.

Parameter Compensation by Interpolation

In this work, we suppose a temperature sensitivity
management algorithm in which the parameter voltages
applied to the circuit are adjusted depending on thetemperature. Such an algorithm will be used by simple
on-chip components to control circuit parameters, thus
complementing the low-power characteristics of thecircuit. We examined an approach to finding appropriate
parameter sets for each temperature which maintain thePublished by Atlantis Press
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Compensating Temperature-Dependent Characteristics

Fig. 4. Periodic spiking at different temperatures.

important characteristics of a neuron: spike frequency inresponse to sustained stimuli and the threshold pulse
stimulus for spike generation.
First, circuit behavior was analyzed at 27°C andthese results were considered the benchmark for
operation at other temperatures. The data recorded
included frequency response to 5 pA and 10 pA
sustained stimuli, and the threshold current Ith of a pulse
stimulus (500µs pulse width) required to generate anaction potential. The v and n-nullclines were alsoplotted. Next, the circuit was simulated at 17, 22, 32,
and 37°C. Selected circuit parameters were tuned togenerate behavior that most closely matched the 27°C
benchmark. The nullcline-drawing function was used
extensively, with the conjecture that similarly shaped
nullclines lead to similar circuit behavior. Finally, thetuned parameter sets were input into a script whichinterpolates functions from these data points and returns
circuit parameter sets for any intermediary temperature.
This procedure was performed with the Class I setting
simulated by the Spectre circuit simulator.
4. Simulation Results
4.1. Simple approach
We selected 5 significant circuit parameters because
exploring high-dimensional parameter space isinefficient. The tail current of the fn(v) component, thebias voltages of the gv(v) and r(n) components, and theconstant current sources Iav and Ian were tuned with allother circuit parameters held constant. The gn(v)component was turned off. Table 1 shows the bestparameter sets which most closely replicated thebenchmark behavior at each temperature. The bottom 3
rows of the table show the circuit behavior at eachtemperature. The script was then used to generateparameter sets for all intermediary temperatures in
0.5°C steps from 17 to 37°C. Parameters were rounded
to the nearest 0.5 mV. These 42 parameter sets werethen simulated with Spectre in their corresponding
temperatures. The "simple" column in Table 2
summarizes the results. "Average % change" refers to
the average percent difference from the benchmark
behavior. Firing frequencies were relatively close to thebenchmark behavior, with the exception of the 5 pA
stimulus at 29°C which failed to fire. The thresholdcurrent showed a downward trend with higher values
above 200 pA at lower temperatures and lower values
around 140 pA at higher temperatures.
Table 1. Parameter sets with corresponding circuit
behavior using the simple approach
Temperature (°C)
17222732
37
gv_Vm (mV)

388

417

432

443 449.5

fn_Vb (mV)

257

248

237

231

Iav_Vin (mV)

434

450

461 468.5 473.5

Ian_Vin (mV)rn_Vm (mV)

420 449.5 464.5
480.5 462.5

219

475 481.5

445

430

185 178.5

415

Ith (pA)

201

164147

5 pA response (Hz)16.3 15.8 15.1 15.7

18.5

10 pA response (Hz)39 38.8 36.2 38.7

39.4

Table 2. Analysis of interpolation results
5 pA stim average freq. (Hz)simple15.8full
11.9

5 pA stim average % change
5 pA stim frequency range (Hz)

5.2
3.7–27.1-9.3
2.4–26.1

10 pA stim average freq. (Hz)10 pA stim average % change

38.7
6.8

35.5
-0.6

10 pA stim freq. range (Hz)Average threshold current Ith (pA)

34.6–43.2
172

26.8–40.4
185.4

Average Ith % change
Ith range (pA)

–3.6
115.5–216-0.1
131–303.5

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Ethan Green, Takashi Kohno

Table 3. Parameter sets with corresponding circuit
behavior using the full-parameter approach
Temperature (°C)
1722 27
32 37
fv_Vb (mV)

256.5 248.5 238

matched the benchmark were obtained, suggesting that
future modifications may yield better results.

230 219

5. Discussion
The above results can be improved by setting theinterpolation script to return parameters rounded to thenearest 0.1 mV, but this accuracy would be difficult toreplicate with real-world circuits because of thermal
noise and other restrictions including the limited
precision of bias voltage generator circuits.
The relative success of the simple approach suggeststhat limiting the available parameters leads to asmoother progression of values over a range oftemperatures, allowing more success in intermediary
steps. The full-parameter approach in contrast offered
too much fine tuning capability. At a given temperature,some parameters were tuned more aggressively thanothers, depending on which yielded the most desirable
behavior. This is a potential cause of the problems in theintermediary steps. Using a meta-heuristic algorithm toobtain the pillar parameter sets may solve this problem.

fv_Vdlt (mV)567

571 580

588 596

gv_Vm (mV)464

451 432

420 398

fn_Vb (mV)

255

246 237 228.5 219

fn_Vdlt (mV)517

520 520521 524

Iav_Vin (mV)437

452 461469 472

gn_Vm (mV)

220 178.5 156 132.5 113

Ian_Vin (mV)

395 445.5 461

473 479

rn_Vm (mV)

480.5 463.5 445

427 413Ith (pA)

250

191 186

169 145

5 pA response (Hz)

13.3

17.1 13.2

13.2 13.2

10 pA response (Hz)32.7

36.5 35.7

36.0 38.6

4.2. Full-parameter approach
A second approach augments the strategy used above by
incorporating all the influential circuit parameters
including the tail current and offset voltage of fv(v), theoffset voltage of fn(v), and the bias voltage of gn(v).
First, each of the circuit components were simulated
individually and circuit parameters were sought thatmaintained I-V characteristics over a range oftemperatures. These parameters were then used as astarting point for tuning the entire circuit at differenttemperatures. Focus was placed on matching thenullclines as closely as possible. Through analysis of theindividual components, it was discovered that the gv(v),and gn(v) components experience a temperature induced
offset, which can be compensated for by tuning theoffset voltages of the fv(v) and fn(v) components.
The parameters for the pillar temperatures are listed
in Table 3. Those for the intermediary temperatures in
the range 17–37°C in 0.5°C steps were determined in
the same way as in the previous approach. The "full"column in Table 2 shows the results of the Spectre
simulations. Ith showed a downward trend and the firing
frequencies were relatively close to the benchmark, but
the 5 pA sustained stimulus failed to induce periodic
spiking at 17.5–21°, 29.5°, 34.5°, 35.5°, and 36.5°C.
While the temperature compensation with this approach
was less effective, nullclines that more accurately

Acknowledgements
This study was supported by JST PRESTO and VLSI
Design and Education Centre (VDEC) at the Universityof Tokyo with collaboration from Cadence Corporation.
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