June 11, 2012
Press Release
NEC Corporation
Tohoku University

Groundbreaking New Technology for Improving theReliability of Spintronics Logic Integrated Circuits
Progress towards the commercialization of circuits that enable
electronic devices to consume zero standby power

NEC Corporation (NEC; TSE: 6701) and Tohoku University have developed
the world’s first technology for improving the reliability of spintronics logic
integrated circuits with the intention of reducing the standby power ofelectronic devices to zero. The behavior of this technology has been verified
using a prototype chip.

Spintronics logic integrated circuits use two of the properties of electrons,
namely negative charge and spin *1 (the fact that electrons are similar to tinymagnets), to remember the results of calculations by flipping the polarity ofthese tiny magnets between “north” and “south” according to the direction ofan electric current. This technology has become the focus of interest as asemiconductor technology because it has non-volatility *2 , meaning that it canretain data even if the power supply is cut off because data is rememberedusing magnetic polarity. It is this non-volatility that has the potential toeliminate the power consumed by electronic devices while they are in standby
mode.

These technologies use vertical domain wall elements *3 , which have verticalmagnetization with respect to a magnetic body. Multiple vertical domain wall
elements are loaded for each individual component of a logic integrated circuit,so that there is redundancy in the way that data is remembered. This enables-1-a high level of reliability to be achieved because the data errors *4 thatoccasionally occur with logic integrated circuits can be detected andcorrected.

With this technology, spin elements are connected in a series, whichprevents power consumption from increasing and prevents the area of thecircuit from becoming larger. These highly reliable circuit components also
support automatic placement and wiring, which means that highly reliable
non-volatile logic integrated circuits can be designed even without expertisein spintronics technology.

Key features of this technology are as follows.

1. Delivers non-volatile logic integrated circuits with high reliability

Data redundancy is achieved by loading multiple “spin elements” (theelements that remember calculation results until the power is turned backon) for the components of logic integrated circuits. Although the probabilityof errors occurring with non-volatile logic integrated circuits is very low,errors where calculation result data is remembered incorrectly do occur,and having redundant spin elements enables these errors to be detected
and corrected, so that the data can be read correctly. *5 Normally, adding
redundant elements would make the physical size of the circuit larger, butvertical domain wall elements can be placed on top of transistor elements
and the elements are connected in a series so there is no need for a newtransistor to branch the wires. This means high reliability can be achieved
without increasing the circuit area.

-2-Vertical domain wall elements also feature low electrical resistance on acurrent pathway, and so by connecting the elements in a series very little
extra time or current is required to write data.

2. Non-volatile circuits can be designed even without knowledge of spintronics
technology
The circuit components that incorporate spin elements support automatic
placement and wiring, whereby the placement and wiring of transistors isdesigned programmatically. This enables non-volatile logic integrated circuits
to be designed easily, even without expertise in spintronics.

Recently the increasing power consumed by electrical devices has become
an important issue, with the expansion of cloud computing, the rapid increasein the volume of communications data associated with the uptake of smart
phones, and the tight balance between supply and demand following the Great
East Japan Earthquake.

Spintronics logic integrated circuits can hold data even when the power isturned off, and then recover rapidly when the power is turned back on. There
are great expectations for these spintronics logic integrated circuits as atechnology capable of significantly reducing power consumption byeliminating the power consumed by electronic devices in standby mode.

These technologies enable circuits to become highly reliable, which isimportant for the commercialization of spintronics logic integrated circuits.
Both NEC and Tohoku University will continue research and development withthe goal of commercializing these circuits in the near future.

NEC and Tohoku University plan to present these results at the VLSI Circuit
Symposium 2012, an international academic meeting held between Tuesday,-3-

June 12 and Saturday, June 16 in Honolulu, Hawaii.

A portion of these results were obtained through “Research andDevelopment into Energy Efficient Spintronics Logic Integrated Circuits” *6 ,directed by Professor Hideo Ohno of Tohoku University and supported by theCabinet Office’s Funding Program for World-Leading Innovative R&D on
Science and Technology (the FIRST Program).

*1: “Spin” is one of the properties of electrons (an elem entary particle with negative electriccharge) that makes them behave like tiny magnets.
*2: “Non-volatility” means that even if the power is turned off, the properties of the elem ents
(data) will still be retained when the power is turned back on.
*3: A “vertical domain wall elem ent” is an elem ent where the structure and materials of thecircuit have been optimized so that the magnetism from tiny magnets is perpendicular
to the electrical current.
*4: Possible causes of errors include such things as cosmic rays, high and low temperatures,and fluctuations in the write voltage or the write current.
*5: It was not possible to avoid higher design costs and chip costs in order to completely
eliminate the possibility of data errors occurring in non-volatile logic integratedcircuits.
*6: The Funding Program for W orld-Leading Innovative R&D on Science and Technology is anational project with the goal of improving Japan’s international competitiveness byselecting core researchers in cutting-edge technologies and then pursuing researchand developm ent centered on these core researchers.

＜ NEC Press Contacts (Japan)＞
Takehiko Kato
NEC Corporation+81-3-3798-6511
E-Mail:t-kato@cj.jp.nec.com-4-