Printed with permission of The Institute of Pure and Applied Physics (IPAP)

JAPANESE JOURNAL OF APPLIED PHYSICS
Vol.43, No.7A (2004) pp.4055-4067 [Part1]

Invited Review Paper

Present Status and Prospect of Si Wafers
for Ultra Large Scale Integration
Hideki TSUYA

Si wafers have contributed to the rapid
growth of the semiconductor industry as abasic material for ultra large scale integration (ULSI) through the research and development of new technologies and mass production in response to the various demands ofdevice manufacturers. In this paper, first, thekey issues of wafer quality improvement withrespect to wafer fabrication technology, gettering and grown-in defects are reviewed.
Various wafers currently in use such as annealed wafers, epitaxial wafers and 300 mm
diameter wafer are discussed with respect totechnology and cost effectiveness. Advanced
Si-based wafers represented by silicon on insulator (SOI) and strained SiGe wafers arealso described. After discussing the challenge
to develop innovative Si wafer technologies
which will lead to the future development of
ULSI, the other important issues associatedwith Si wafers such as the re-examination ofover-stringent specifications, cost reduction,
economically reasonable pricing and the promotion of mutual understanding and cooperation between device makers and wafer makers for the continued development of bothindustries are emphasized.
Keywords: Si wafer, ULSI, SFQR, particle,
gettering, grown-in defect,
COP, annealed wafer, epitaxial
wafer, 300 mm wafer, SOI, SIMOX, Bonding SOI, strained
SiGe

1. Introduction
The International Technology Roadmap
for Semiconductors (ITRS), which was released in 2001, states that miniaturization
will proceed by a factor of 0.7 every three
years until 2016.1) However, the technologicalprospect is not necessarily clear. Beyond the
45nm node, it may be difficult to use opticallithography. Furthermore, in order to realize
Moore’s law, the introduction of new materials, for example, high-dielectric gate materials is inevitable. So to speak, we are now
proceeding toward a new age governed bymaterials.
At the same time, the semiconductor industry is expanding onto the global stage andrequires major investments, and thus collaboration and cooperation among companies
on the worldwide scale as well as domestically are being accelerated. In addition, thefoundry industry is growing and the worldwide share is drastically changing every year.
It is clear that the semiconductor industry at
the beginning of the 21st century is facing amajor turning point in terms of business andtechnology.
Against this background, the silicon wafer industry, of which about 70% is occupied
by Japanese-capital companies, has contributed to the growth of the semiconductor industry by providing the basic material for ULSI
through the research and development of
new technologies and mass-production techniques of Si wafers in response to the various
demands of device manufactures.
Today, the quality requirements for Si
wafers are divided into two categories. One
includes universal qualities such as flatness
and particle which are demanded by the ITRS
roadmap. The other includes nonuniversal
qualities such as gettering ability and shape/

2-44-44 Fujigaoka, Aoba-ku, Yokohama 227-0043, Japan(Received March 15, 2004; accepted April 27, 2004; published July 7, 2004)© 2004 The Japan Society of Applied Physics

4

JSAP International No.11 (January 2005)

brightness of the back surface of a wafer,
which strongly depend on the device processes employed. These qualities are closely correlated to the device fabrication tools used andthe requirements differ among device manufactures.
On the other hand, the cost reduction ofsemiconductor devices is an absolute necessity, which requires both higher quality andcheaper wafers. In order to meet these requirements, cost reduction technologies in
the mass production of wafers have been developed.
SOI wafers for low-voltage and lowpower consumption devices are highly anticipated. According to the SOI roadmap, thethickness of the Si top layer will continue tobecome thinner, and 10 – 15 nm thickness
and a uniformity of ±5% are requested. The
strained SiGe/SOI heterostructure is a promising candidate for channel engineering toobtain a higher carrier mobility. The practicaluse of new Si-based materials is in the near
future expected. In this paper, the present
status of Si wafers for ULSI is reviewed andtheir future prospects are addressed.

2. Effect of Crystal Quality on
Device Performance
After the establishment of dislocationfree Czochralski (CZ) Si crystal growth technology by Dash,2) the greatest concerns in theearly 1980s were oxygen impurities and thecontrol of oxygen-induced bulk microdefects(BMDs). Intrinsic gettering (IG) using oxygen
precipitates, of which the concept had already been proposed by Tan et al .3) in 1977,
was in practical use in the late 1980s.
A new type of grown-in defect, which
was named the crystal originated particle(COP) by Ryuta et al .4) in 1990, was found tocause the breakdown of SiO2 film.6,7)
Gettering technologies are extremely effective for device yield enhancement, andtheir usefulness has been widely demonstrated in various devices. An example of theyield increase of DRAM using denuded zone
IG (DZIG) wafers compared to natural IG (NIG)
wafers is shown in Fig. 1.5)
There have been many investigations concerning COP-induced device failures such as
the degradation of isolation characteristics,8,9)
gate oxide integrity (GOI) failure, 10,11) the
short fail of deep trench cell-based DRAM12)and so on. If COPs exist in the isolation region, local oxidation of silicon (LOCOS) areawith a residue of Si3N4 film is formed during
the etching process, resulting in the isolation
failure.8) The thinning area of the field oxide
film caused by COP increases the subthreshold leakage current markedly between the

degrade device performance and yield due tothe nearly same size as the design rule, andit has attracted much attention. Thereafter,
the formation mechanism and the control/
suppression of COP were extensively investigated.
Near-surface crystalline defects and metal contamination which cause device failure
have been troublesome issues to the volume
production engineers of device manufacturers. For example, defects-related oxygen precipitates inject minority carriers, resulting in
the holding time failure of dynamic random
access memory (DRAM).5) Dislocation halfloops generated by film-edge-induced stressare one of the main causes of white spot
defects of charge coupled device (CCD). 5)
Furthermore, Fe and Cu impurities which
nucleate at the interface of SiO2-Si as metallic α-FeSi2 and Cu-rich silicide, respectively,

adjacent memory cells, resulting in the degradation of the isolation characteristics.9)
In order to investigate the effect of COP
on GOI failure, the I – V characteristics were
measured for each metal oxide semiconductor (MOS) capacitor diode containing one
COP and no COP of which the position were
determined using a laser particle counter.11)
As shown in Fig. 2, the GOI yield more than
11 MV/cm for MOS diodes with one COP
was 5 to 15%, and that for MOS withouta COP was more than 95% for three kindsof crystals. The cross-sectional transmission
electron microscopy (XTEM) observation of
the V-grooved oxide layer showed the thinning of oxide on {111} which is related to the
GOI failure due to the focusing of the electricfield.11)

HOLDING TIME FAILURE RATE
3

2

1

0

(Arb.)

100
With COP
Without COPNIG

DZIG-ADZIG-BGOI Yield (%)

80
60
40
20
0
SampleA(p-type)B(p-type)C(n-type)

DZIG-C

Fig.1.

Holding time failure rate of DRAM for DZIG and NIG wafers.5)

Fig.2. GOI yield for MOS capacitors of 25nm oxide thickness and 1mm2 electrode areawith COP (n=100) or without COP (n=50) on three kinds of crystal wafers.11)

JSAP International No.11 (January 2005)

5

3. Key Issues for Wafer
Quality Improvement

nanotopography.
The microroughness and reflectivity ofthe back surface of a wafer are important
issues for device processes. For the lithography process, the microroughness of theback surface which meets the shape of stepper chuck is required. In the case of the dry
etching process in which a wafer is chucked
electrostatically, the microroughness of theback surface affects on thermal conductivity,
resulting in incorrect temperature measurements. To date, acid etching has mainly beenused. Recently, alkaline etching has become
more favorable because it improves SFQR and
nanotopography, but the microroughness isenhanced by the presence of facets.15) Minor
process tuning may therefore be necessary.

3.1 Wafer fabrication technologies
The requirement for wafer flatness andparticle is becoming still more stringent withdecreasing design rule. The ITRS requires thatsite flatness (SFQR) is comparable to or lessthan the design rule.
Silicon wafer fabrication technologies
have not changed substantially over the past
forty years. However, in order to improve flatness and reduce cost, new fabrication technologies have been introduced step by step.
A low-damage surface grinding process was
adopted to overcome the problem of freeabrasive lapping damage. This process isan etchingless one and has the potential tobe applied without the degradation of flatness induced by etching processes. Doubleside polishing (DSP), where a wafer is unconstrained and is freely moving, realizes thehighest polish quality and is inevitable to the
manufacture of all 300 mm wafers.13)
Newly adopted shallow trench isolation(STI) using SiO 2 deposited by chemical vapor deposition (CVD) instead of LOCOS isachieved by using chemical mechanical planarization (CMP). Silicon front surface topography variation, called nanotopography,
which involves nanometer level waviness on alateral range of a few millimeters up to centimeters, deteriorates the remaining oxide layer
thickness uniformity after CMP, resulting indegraded isolation performance.14) DSP wafer
is a solution for the problems associated with

3.2 Gettering
3.2.1 Gettering technologies and the current
understanding of mechanisms
The gettering technologies, which eliminate unwanted heavy metal impurities fromthe device active region and capture themat gettering sites, have been widely used asa necessary key technology for the improvement of device yield and reliability. In particular, IG and polysilicon back sealing (PBS)
gettering utilizing the grain boundary and defects of polysilicon deposited on the back surface of a wafer16) as well as gettering using
a p/p+ epitaxial wafer are currently employedon device mass-production lines.
Physical gettering mechanisms are classified into three types; relaxation-induced
gettering, segregation-induced gettering

Diffusion Length after 30-min Anneal ( m)

1

10

100

1000

Solubility of Metals (cm-3)

1016

Fig.3. Dependences of the solubility of Ti, Fe and Cu on their diffusivity. The dashed horizontal line
corresponds to the target bulk contamination level of metals of 1010
atoms/cm3.28)

6

1014
1012
785ºC

640ºC

275ºC

1010
108

Ti

Fe

Cu

10-6

10-5

106
10-12 10-11 10-10 10-9

JSAP International No.11 (January 2005)

10-8

10-7

Diffusivity of Metals (cm /s)2

10-4

and injection-induced gettering.17) IG occurs
through the diffusion of supersaturated impurities from the device active region to theheterogenous nucleation gettering site due tothe concentration gradient between the twosides. When the impurity concentrations forthe two sides reach the solubility limit, gettering is achieved. The supersaturated condition
is relaxed, and therefore this is called relaxation-induced gettering. The mechanism wasconfirmed on the basis of the low-temperature Fe-precipitation kinetics at silicon oxide
precipitates.18)
PBS gettering, which was found to occur
even under the unsaturated conditions of Cu
and Fe, is understood as segregation-induced
gettering19) due to the enhanced metal-solid
solubility.20) The segregation of metal impurities proceeds at lower temperatures and at
more gettering sites.
In the case of heavily boron doped epitaxial wafer, Fe impurities are strongly gettered by the Fe + – B – pair formation. The
concentration of Fe+ increases at lower temperatures and with the larger difference inFermi energy between the epitaxial layer andthe bulk induced by the difference in boron concentration between them. Therefore,
this is called Fermi-level-induced gettering,21)
and the physical mechanism is classified experimentally as segregation-induced gettering.22,23)
The p/p+ epitaxial wafer is effective forCu gettering,24) but the gettering efficiency
is weaker than for Fe, because the dissociation energies for the Cu – B pair and for the
Fe – B pair were reported to be 0.61 eV25) and1.40 eV,26) respectively. Ni is not gettered by
the p/p+ wafer because of uncharged Ni0 species, 24) which requires BMD formation beforehand. A heavily boron doped wafer easily
generates many BMDs.27)
Practically, various kinds of metal impurities are targeted. The key parameters such assolubility, diffusion coefficient and temperature must be considered. Figure 3 shows thedependences of the solubility of Ti, Fe andCu on their diffusivity. From this figure, theprocess window of relaxation gettering is deduced for the target bulk contamination levelof metals of 1010 atoms/cm3.28)

Invited Review Paper

3.2.2 Advanced gettering technologies
no contamination
with Ni contamination

100

Generation Lifetime (msec)

10

1

0.1
1

2

1

2

A

B
1150º C 4hr

A. High temperatureprocess Simulation

1000º C 2hr

B. Low temperatureprocess Simulation

800º C 2hr

Ni

1000º C 16hr

1

1050º C 1hr

700º C 20hr

Ni

1

2
2

Fig.4. Gettering behaviors for initial Ni contamination (1×1012 atoms/cm2) in thehigh-temperature process and in the low-temperature process.29)

1000
Calculated platelet length L (nm)The favorable gettering technologies
have been selected from the point of view ofdevice miniaturization and device processes.
DSP wafers and rapid thermal processing (RTP)
using low temperatures are necessary for advanced devices, and epitaxial wafers are extensively adopted. Therefore, IG and p/p+ Fermi-level-induced gettering will survive.
It is difficult to expect that many oxygen
precipitates are generated during low-temperature device processes due to the suppression of BMD growth. Figure 4 shows the gettering behaviors for initial Ni contaminationin the high- and low-temperature processes.29) Ni silicides are dissolved and gettering
proceeds during the drive-in process throughBMDs formed in the high-temperature process. The generation lifetime measured by
MOS-Ct recovers to the same level of no Ni
contamination, but in the low-temperatureprocess, lifetime is degraded, and thus it iscritically important that the gettering sites
should be optimized in the early stages of thedevice process.
Recently, progress has been made withthe simulation of gettering. It is possible topredict the oxygen precipitation behavior by
introducing parameters such as process conditions, thermal history of a crystal and initialoxygen concentration into the Fokker – Plank
equation.30) Using the critical size and density of oxygen precipitates for IG occurrence,
which are obtained from computer simulation and experimental data, IG effect is able
to be predicted in the actual device processes.
Figure 5 shows an example of the IG prediction for Ni in p/p– wafers with IG and without
IG.31) This prediction is also confirmed by generation lifetime measurement.
Many vacancy agglomerates are formedby quenching a silicon crystal from a hightemperature in an Ar atmosphere.32) Recently,
by controlling the vacancy concentration profile at 1250ºC for 30s in Ar using a RTP tool,
a new type of silicon wafer with DZ and oxygen precipitates for IG, which is named themagic denuded zone (MDZ) wafer, was developed.33) The soaking temperature, quenching conditions and ambient gas are importantparameters.

L criwith IG
final

step2 final
step3

100

step1
step3
without IG
10
106

107

108

109

1010

Calculated precipitate density Np (/cm3)
Fig.5. Example of IG prediction in p/p– wafer without IG (앬) and p/p– wafer with IG
at 900ºC for 1h before epitaxial process (앪). Process sequence is 800ºC/4h (step 1) +1000ºC/2h (step 2) + 750ºC/4h (step 3) + 1000ºC/2h (final).31)

3.3 Grown-in defects
3.3.1 Structures and features
The origin of COP is the singularities observed by a laser particle counter as small
particles which are not dust on the wafer but
pits delineated by repeated SC1 cleaning. It
was suggested that such pits originate fromdefects in the melt-grown crystals.4) Vacancyrelated complexes were presumed from theexistence of pits. Park et al .34) observed voidsof 0.25 to 0.50 µm in diameter at the Si/SiO2

interface of the B-mode type oxide breakdown classified by Yamabe et al .35) The oxide
defects were characterized to be octahedron
structures full of vacancies by Itsumi et al .36)
using XTEM and energy-dispersive X-ray spectroscopy (EDX). Voids on a wafer surface arerecognized as pits.
A number of investigations were performed on the wafers after the cleaning processes and heat treatment processes. Katoet al . observed for the first time the grown-

JSAP International No.11 (January 2005)

7[110](a)(b)

Height (nm)

[110]

50
0
–50
–100

2
0
–2
–4
0

200
400
600
Distance (nm)800

01000 2000 3000
Distance (nm)4000

Fig.6. AFM images and cross-sectional profiles of COPs on the Si (001) surface after H2 annealing. (a)as-received and (b) at 1100ºC for 10min.38)

in defects of as-grown crystals by TEM. The
basic structure was to be found a composite
of two or three incomplete octahedral voids,of which the walls are surrounded by several
nanometer thick SiOX .37)
The shape of COP changes with heat
treatment, and it finally disappears. Figure 6
shows typical atomic force microscopy (AFM)
images and cross-sectional profiles of the(001) wafers, (a) as-received and (b) after
heat treatment at 1100ºC for 10 min in H2.38)
The COPs had disappeared completely after
the annealing at 1100ºC for 20 min. Silicon
atomic step etching caused by silicon atom
evaporation in H2 and surface reconstruction
as well as silicon atom migration from thestep edge to the bottom of the COP at hightemperatures are the main causes for thechange of COP shape.

3.3.2 Formation mechanism
With respect to the behavior of grownin defects, it is important to understand theincorporation and diffusion of intrinsic point
defects such as vacancies and self-interstitials.
Voronkov proposed an excellent theory inwhich the type and concentration of dominant point defects after crystal growth depend on the ratio V/G , where V is the growthrate and G is the longitudinal temperature
gradient near the crystallization temperaturefor floating zone (FZ) crystal.39) His theory,
based on the recombination and diffusionof point defects, predicts that vacancies are
dominant if V/G >ξ and self-interstitials are
dominant if V/G <ξ , where ξ is a certain constant, and it also explains many experimental
results for CZ crystals well.
In order to clarify the formation mecha-

nism of grown-in defects in CZ crystals, twocrystals were grown under extremely different growth conditions.40) One was quenchedduring growth and the other was halted after growth. It was found that the size of thegrown-in defects formed in the narrow temperature range of the halted crystal was muchlarger that of the quenched ones as shown in
Fig. 7. This means that grown-in defects nucleate and grow in the narrow temperature
range of about 30ºC below 1100ºC due to a
rapid agglomeration of vacancies. It was also
found that the growth of the oxide film inthe voids is a rate-limited process limited by
the diffusion of oxygen atoms. The formation
process of the grown-in defects consists of
two main steps, being the rapid void growth
and the growth of oxide film on the innerwall as shown in Fig. 8.

OPP Signal Size (V)3.3.3 Control and suppression
10
9
8
7
6
5
4
3
2
1
0
800

1070ºC–1100ºC

900 1000 1100 1200 1300
Temperature (ºC)

Fig.7. Distribution of optical precipitate profiler (OPP) signal size as afunction of the crystal temperature just before quenching converted fromthe crystal axial position. 앪 quenched, 왖 halted crystal.40)

8JSAP International No.11 (January 2005)

Stacking faults with a ringlike distribution
after thermal oxidation (R-OSF) are observedin some commercial wafers. The appearanceof R-OSF depends on the crystal diameterand growth rate. For example, R-OSFs are notobserved for growth rates less than 0.5 mm/
min or more than 1.0 mm/min for 125 mmcrystals.41) A distinct difference between thegrown-in defect distributions inside and outside the R-OSF region with changing the
growth rate was found using Secco-etching
and light scattering tomography (LST). 42)

higher

Invited Review Paper

Vacancy[001]

Oxygen50nm

Void

Temperature

1100ºCvacancy gatheringvoid formation

Growth rate

[110]

Void
R–OSF

formation of oxide film
on inner surface of void

lower

1070ºC

Dislocation loop

[011]

900ºC

[011]

oxide film

10 m
Fig.8.

Schematic illustration of the grown-in defect formation.40)

Considering Voronkov’s theory and the previous findings for FZ silicon crystals,43) it is
widely accepted that the vacancy-related defects distribute inside the R-OSFs and the selfinterstitial-related defects distribute outside
the R-OSFs. Figure 9 shows schematicallythe longitudinal cross-sectional distribution ofgrown-in defects versus the growth rate, including TEM images of the voids37) and large
dislocation loops.42)
In a conventional CZ furnace, G increases
along the crystal radial direction due to thelarge heat radiation, and thus V/G decreases
towards the crystal surface even for a constant V , resulting in dominant self-interstitials
towards the outer region of a crystal.
For the suppression of grown-in defects,
it is important to design the hot zone with amore radially uniform V/G and to control thegrowth parameters. By controlling the axial
and radial V/G within certain critical values
during crystal growth, “pure silicon wafer”,
which are none of agglomerate defects suchas COPs and large dislocation loops due tothe intrinsic point defects much less thanFig.9. Schematic longitudinal cross-section distribution of grown-in defects versus growth rate including TEM image of void37) and large dislocation loops.42)

the critical concentrations, have been developed.44) Pure silicon wafers of 200 mm diameter which are COP-free and large dislocation-free from top to bottom are now being
in mass produced.45)
Several critical values of V/G obtained experimentally and theoretically have been reported.46–48) The reason for the scattered values may be the uncertainty of the observed
values and of the constant values of point
defects used in the calculation. In addition,
the V/G value is shifted by the presence of
impurities such as oxygen, carbon and nitrogen.49,50)
Nitrogen doping enhances oxygen precipitate-induced defects,51) which were foundto be stable even after heat treatment at
1100ºC.52) It was also found that nitrogen
doping affects the formation of grown-in defects, and the tolerance of the V/G value forthe grown-in defects-free region was expanded particularly for the doping of more than
1×1014 atoms/cm3.50) This is explained by thereaction of nitrogen with point defects which
serves to reduce the point defect concentra-tion. Nitrogen doped wafers are favorable forthe epitaxial wafer substrate.

4. Various Wafers Currently in
Use
Here, current Si wafers, aside from thepure silicon and MDZ wafers are discussed.

4.1 Annealed wafers
The DZIG wafer and the H2 annealed wafer53) (called the Hi or HAI wafer) which werein practical use in the 1980s are kinds of annealed wafers for the enhancement of gettering ability and the defect-free near subsurface. In the late 1990s and the early 2000s,
high-temperature annealed wafers for the
suppression of COP were investigated and nitrogen doped wafers annealed in Ar were developed.
It is important in practice to expand thepossible range of initial oxygen content andto homogenize the oxygen precipitation independent of thermal history.54) A multistep
heat treatment for IG (MIG, hereafter) after
the high-temperature annealing for DZ for-

JSAP International No.11 (January 2005)9mation enhances the IG ability and homogenizes the oxygen precipitation.55) Figure 10
shows the oxygen content of wafers from top
to bottom of a crystal after each annealing
process: (a) for two-step annealing and (b)for MIG (520ºC+620ºC+720ºC, for each 16h)
annealing.5) The homogenization of oxygen
precipitation is achieved after MIG annealing.
In the case of a two-step annealing, the interstitial oxygens which precipitate incompletely
after the first heat treatment proceed to precipitate during the second heat treatment,
whereas almost all of the interstitial oxygens
precipitate completely after the MIG annealing. After the final annealing at 1140ºC, oxygen precipitates are partially redissolved andthe interstitial oxygen content is close to thesolubility limit.56) A multistep heat treatment
MIG is a prototype of DZIG wafer fabrication.
To achieve cost reduction, MIG was replaced
by a ramping annealing from a low temperature.
Furthermore, the Hi wafer was reported
to eliminate COP perfectly even in the region
deeper than 500nm by hydrogen annealing
at 1200ºC.57) Argon annealing is also effective in the elimination of COP. The high-temperature annealings at 1200ºC and 1300ºC

with a ramping rate of 1ºC/min achieved the
COP-free zones of 20 µm and 100 µm depth,
respectively.58) A shrinkage model of grownin defects consisting of the dissolution of theoxide on the inner walls of defects and thesubsequent injection of self-interstitials at athermal equilibrium concentration was proposed.58)
It was also found that the annealingsin H2 and Ar at 1200ºC for 1h easily annihilate the COP of nitrogen doped wafers anda high density of BMDs still exist.59) In thiscase the heating and cooling rates were 6
and 3ºC/min, respectively. The annihilation
was more effective to the initial smaller sizeof COP and at a lower oxygen content. The
combination of rapid growth (1.8 mm/min)and nitrogen doping was the optimum forachieving smaller voids and deeper void-freezone of 10 µm. 59) The mechanism of BMD
formation and void annihilation is explainedby the model in which the morphology ofvoids changes from octahedral to plate shape
triclinic, which nucleates oxygen precipitation
for nitrogen concentrations above 4.6×1014
atoms/cm3.60) Under argon annealing, voids
are annihilated and a high density of oxygen
precipitates is generated stably.

1017(cm-3)
20
820ºC, 64h
1140ºC, 2h

1230ºC, 2h

MIG, 16h

1140ºC, 2h

OXYGEN CONTENT

15

10

5

Fig.10. Oxygen content of wafers obtained from top to bottom of a crystal
after each annealing process; (a)asgrown; 앬 820ºC/64h; 앪 820ºC/64h +1140ºC/2h, (b) as-grown; 앬 1230ºC/2h +MIG; 앪 1230ºC + MIG + 1140ºC/2h.5)

10JSAP International No.11 (January 2005)

TOP

BOTTOM TOP

BOTTOMPOSITIONPOSITION(a)(b)

4.2 Epitaxial Wafers
Si epitaxy has a long history. Epitaxial
growth technology has advanced with theprogress of bipolar devices. Epitaxitial wafers
with a thin epitaxial layer grown under low
pressure have contributed to the realizationof high-performance and high-speed bipolar
devices. On the other hand, p/p+ epitaxial wafers have been widely used in complementary
MOS (CMOS) logic devices because of the effectiveness of the latch-up suppression61) andof the noise reduction of analog and digital circuits62) and also of the gettering of Fe.
Epitaxial wafers have been used in memory
devices such as 64MDRAM and flash memory and the production output has increased
since 1997.

4.2.1 Features of epitaxial wafers
Epitaxial wafers have certain features
which are different from that of bulk wafers.
High-quality DZ is essentially formed because
there is no fabrication surface damage andno oxygen precipitate-induced microdefects
due to the extremely low oxygen content andthe small number of precipitate nuclei. Furthermore, in many cases the COP disappears
during epitaxial growth processes on the substrate with COP.
However, it is undeniable that someunique defects such as mounds and epitaxial
stacking faults are generated during epitaxial
growth.63) These defects are usually evaluatedusing a light scattering system, and thus arecalled light point defects (LPD). Mounds are
generated due to the foreign materials detached from the quartz chamber of the epitaxial reactor, and increase in number withdecreasing growth temperature. Defects larger than 20 µm diameter are called large area
defects (LADs). Stacking faults are generated
from the particles at the interface between
the epitaxial layer and substrate. The relation
between the substrate particles and the epitaxial defect morphology was investigated indetail.64) The epitaxial defect morphology was
found to change depending on the epitaxial
layer thickness and particle size. The suppression of size and density of epitaxial defects isurgently demanded with the continuing de-Invited Review Paper

4.2.2 p/p+ wafer+

The back side of the p/p wafer is covered
with CVD-SiO2 film in order to prevent boron
autodoping from the substrate. The deposition of film is the cause of increase in costand contamination. In the case of 300 mm
wafers fabricated using the DSP process, theCVD process is not adopted. The epitaxial
layer is usually grown using a horizontal single reactor at around 1100ºC. The epitaxial
growth at lower temperatures is promising
for the prevention of boron autodoping.
Recently, a single epitaxial reactor ofwhich the susceptor is rotated at the very
high speed of 500 – 2000 rpm was developed.65) It was reported that epitaxial layersgrown at low temperatures of 900 – 1000ºC
and under 2 – 100Torr, with a growth rate of3 – 4 µm/min, were mound-free and uniform
in thickness. This may be because the reaction efficiency of gas is increased and particles are blown off by the high-speed rotationof the susceptor.
The improvement of the susceptor andthe epitaxial process is effective in the prevention of boron autodoping. The plurality ofholes on the susceptor allows the boron atoms out-diffused from the back surface during epitaxial growth to be carried away in an
inert gas stream from the front surface andinto the exhaust such that the autodopingof the front surface is minimized.66) The resistivity of the epitaxial layer without a CVDSiO2 film was uniform and comparable to one
with a CVD-SiO2 film.

4.2.3 Epitaxial wafer grown on nitrogen
doped substrate
A COP-free epitaxial layer is grown in H2
at above 1100ºC, but under this condition
the BMD density of the substrate decreases,
resulting in the degradation of the gettering
ability. Both freedom from COP and an effictive BMD density are necessary.
A nitrogen doped substrate is useful for
epitaxial wafer because of the stability of the

WAFER DIAMETER (" )crease of the design rule, and continuous effort toward the improvement of production
technology is required.
12"

256M
64M

12
16M
4M
1M

8

256K
64K

6
4K

4

6"

5"

16K

5

8"

4"

3"

3
‘70

‘75

‘80

‘85

‘90

‘95

‘00

‘05

‘10

‘15

YEARS
Fig.11. Trends in Si wafer diameter and packing density of DRAM.69)

BMD density obtained after epitaxial growth.
However, some defects happen to be generated in the epitaxial layer. Nakai et al . positedthat epitaxial layer defects such as stacking
faults and dislocations are generated due tovoid morphology changes and grown-in oxygen precipitates in nitrogen doped substrates
with higher nitrogen concentration and lower
V/G .67) They have proposed that the optimization of nitrogen concentration and V/G value, and also carbon co-doping are effective
for the prevention of epitaxial layer defects
growth.67)

4 2.4 Cost reduction of epitaxial wafer
The cost reduction of epitaxial wafer isvery important and four points are considered.63) The cost of substrates has to be reduced. Substrates grown with high growthrate should be widely used and the severe
limitation of the oxygen and boron concentration ranges should be relaxed. In the wafer
fabrication process, is it necessary to use thesame recipe as polished wafers? For example,
Yamamoto reported that GOI failure causedby the wafer fabrication process is improvedby using epitaxial wafer.68) A simpler fabrication process may be adopted. A epitaxial
reactor with high performance such as highproductivity and low running cost is urgently
demanded. As for the epitaxial growth process, the reduction of the epitaxial growth cycle time, wafer etch reduction and the savingof monitor wafers are key issues.

4.3 300mm (12 inch) wafer
As shown in Fig. 11, the diameter ofsilicon wafers increases by 1 inch every four
years.69) By extrapolating this trend, the massproduction age of 12 inch wafers is expected
to be after 2005. (The mass-production age
is tentatively defined as the year when thepercentage of the production sheets of thetarget wafer occupies the 10% of all wafers
from 4 inch to 12 inch). At present, the production of 12 inch wafers is increasing steadily. At the end of 2003, the production of 12
inch wafers in worldwide was estimated tobe 3.4% of all wafers produced.
The wafer fabrication process technology for the 300mm wafer is basically similar tothat of the 200mm wafer, but with the adoption of the DSP process, a superior flatness isachieved. The specification of SFQR and particle of polished 300 mm wafer for the 130nm
rule is already fulfilled.70) The concept for theepitaxial reactor for 300 mm wafers is thesame as that for 200 mm wafers, so there isno technical difficulties.
The issue causing the most concern is the
crystal growth technology for heavy 300 mm
crystals. In order to obtain the same yield asthat for 200mm crystals, the establishment ofa growth technology for over 300 Kg weight
crystals is necessary.71) Here, the yield means
the ratio of product weight to charge weight.

JSAP International No.11 (January 2005)

11

In addition, a quartz crucible with a large diameter of around 40 inches has to be developed for the pulling of long and heavy crystals.
It is impossible to support stably theheavy crystals of 300 – 400 Kg weight by
the Dash necking method2) using a necking
part of 3 – 4 mm in diameter. The supporting
method using the larger knob formed afternecking 72) is currently in practical use. Recently, dislocation-free 150 mm crystals weregrown using a seed of 7×7 mm2 in size without Dash necking.73) The seed doped with aboron concentration of 1×10 18 atoms/cm 3
was used to prevent thermal shock. Furthermore, by co-doping Ge of 8×1019 atoms/cm3
and B of 2×1019 atoms/cm3, the misfit dislocation was suppressed and dislocation-freecrystals were grown using a seed 15×15 mm2in size.74) The application to a 300 mm crystal
is expected.
The melt flow becomes more complex
with increasing diameter due to various factors such as the large heat radiation from themelt surface and the increase of temperature
at the crucible wall. Turbulent convection ofa large silicon melt up to 300 mm diameteris discussed experimentally from the fluid dynamics.75) The development of a numericalmodel combined with global heat transfer is
expected,76) and more precise values of thermophysical properties are urgently demanded.
Considering the crystal growth technology, the growth rate must be slower due tothe concave shape of the solid-melt interface.
The consumption of the quartz crucible increases, resulting in the increasing incorporation of oxygen. In addition, due to the another factor of thermal history different from
200 mm crystal, the oxygen precipitation/
retardation/recovery phenomenon is different
from 200mm.77) The stabilization of the heatflow is critically important, for example, using
the magnetic Czochralski (MCZ) method developed by Hoshi et al .78) A uniform oxygen
concentration with a radial gradient of 5%or less has been reported using a cusp-type
MCZ, which is also beneficial to the minimization of the emission of SiO2 particles from

12

JSAP International No.11 (January 2005)

the crucible wall.79)
Another issue is the slip generation in a
vertical furnace at high temperatures due tothe large gravitation-induced bending stressand thermal stress. These issues have to beresolved while maintaining the level of productivity. The use of three point support80)
and a ring-like jig81) in a vertical batch furnace
can lead to the slip reduction. Recently, it wasreported that nitrogen doped wafers pulled
at high speed are resistive to slip generation
at 1200ºC when supported using ring-like SiC
holders covered by CVD coating.82) The suppression of the slip propagation is explained
as being due to a high density of nanometersized nitrogen-induced precipitates.

5. Advanced Si-Based Wafers
5.1 SOI
5.1.1 Various SOI wafers
Various kinds of SOI structures have beendeveloped. However, two SOI wafers; separation by implanted oxygen (SIMOX) and bonding SOI wafer are in use at present. Althoughmany new materials and processes have beendeveloped over a long period, a genuine
technology which overcomes the competitive
ones can survive. These SOI wafers as leading
substrates are promising for the coming highspeed, low-voltage and low-power consumption devices.
In 1978, Izumi et al . developed a newisolation structure using a high-dose oxygenion implantation of 2×10 18/cm 2 and hightemperature annealing at 1150ºC, and realized a high-performance 19-stage CMOS ringoscillator fabricated in the SOI on the buriedoxide (BOX) layer.83) This is called SIMOX and
it is one of the fundamental structures of SOI.
In order to reduce a high density of dislocations and fabrication cost of SIMOX wafer,various investigations have been carried out.
A BOX layer formed with a dose 1/5 lower
than that used previously was actively oxidized at 1350ºC, resulting in internal thermaloxide (ITOX) formation on the BOX layer.84)
Using this method, the thickness of the BOX
layer was increased and the morphology of
the interface between the top Si and the

BOX layer was greatly improved. Anotherapproach which uses lower energy oxygen
implantation at 65 keV with the dose reduction of 2×1017/cm2 achieved SIMOX wafers ofhigher quality.85) SIMOX technology is suitablefor ULSI, because the top Si layer with great
thinness and high uniformity in thickness canbe achieved simply by controlling the acceleration energy of the ion implantation.
A bonding SOI is fabricated by sticking
two wafers of which one is thermally oxidized
and by annealing at around 1100ºC for 2h
in O2, followed by grinding and polishing theactive SOI. The prototype of the bonding SOI
was invented by Nakamura in 1961.86) Bonding SOI with thick top Si layer is widely usedin high-power devices.
Since the new fabrication methods using
epitaxial growth and ion implantation processes have been introduced, bonding SOI
wafers have received much attention for ULSI.
The technological features of the epitaxial
layer transfer (ELTRAN) wafer87) are epitaxial
growth on porous silicon, splitting by water
jet, etching with extremely high selectivity
and hydrogen annealing to achieve smoothness of the epitaxial layer. The controllability
and uniformity of the top Si layer are excellent because of the use of epitaxial growth.
The achievement of an ultrathin top Si layerof 55±2.1 nm by controlling the epitaxial
growth has been reported for the 200 mm
wafer.88)
Another type of bonding SOI wafer fabricated using a smart-cut process89) featureshydrogen ion implantation for the delaminating layer formation underneath the SiO2 layer
and annealing at 600ºC for splitting. A highquality top Si layer is obtained by touch polishing. Cost reduction is expected becauseof the re-use of wafers, but the uniformity ofthe delaminating layer may be uncertain.
The issue of SOI wafers is the development of fabrication technology for the cost
reduction of 300 mm. It is reported that theuniform thickness of 147±1.6 nm, which corresponds to ±1.1%, of the top Si layer isachieved for the ELTRAN 300 mm wafer.90) As
for bonding SOI using the smart-cut process,the uniformity of 200±20Å of the top Si layer

Invited Review Papera)with high aspect ratios formed by reactive
ion etching were heat-treated in H2, which

b)

400nm

resulted in the empty space in Si (ESS) due
to silicon surface migration.100) The desired
shape and area of the ESS can be obtained
depending on the size and layout of the initial trenches. A SON-MOS field effect transistor (MOSFET) was successfully fabricated using the ESS technique.

300nm

5.2 SiGe Wafers
Fig.12. XTEM images of (a) Cu:Si precipitate colonies and (b) NiSi2 precipitate formed beneath the
BOX layer of SIMOX wafers. Surface metal contaminations of Cu and Ni are 2×1015 atoms/cm2 and5×1012 atoms/cm2, respectively. Diffusion temperature and time are 950ºC and 30min, respectively.92)

in terms of wafer-to-wafer and on-wafer for
300 mm is reported.91) The uniformity of the
SIMOX wafer is superior in principle.

5.1.2 Gettering in SOI wafers
The gettering phenomenon in SOI wafers is a critically important issue. The SiO2
layer underneath the top Si layer prevents the
diffusion of almost all metal impurities into
the bulk substrate, resulting in a condensation of metals within the top Si layer. In thecase of Cu and Ni, it was found that a BOX
layer does not prevent diffusion from the top
Si layer into the bulk substrate in the temperature range from 600ºC to 900ºC. These
metals are gettered due to the heterogenous
impurity precipitation at stacking fault tetrahedral formed during SIMOX implantation
processes as metal silicides as shown in Fig.
12.92) On the other hand, the BOX layer itself isan effective barrier against Fe diffusion, andthus the extended defects associated withoxygen implantation are less effective for Fe
compared to Cu and Ni.93) It has been notedthat PBS gettering is efficient for Fe at temperatures higher than 1150ºC during wafer
processing,94) due to the poor quality of the
BOX layer. However, during device processing, PBS gettering may be surely inefficientbecause perfect BOX layer is already formed.
Lateral gettering by introducing crystalline defects in the vicinity of the device region is effective for achieving the metal capture. Many investigations have been carriedout.95–97) For example, significant improvement of the GOI was achieved by employing the Si implanted gettering sinks at thesource and drain regions prior to gate oxide
growth.95) Both implantation-induced dislocation loops and P diffusion for lateral gettering
sinks were reported to be effective for GOI
improvement for all SOI types.96)

5.1.3 SOI/bulk patterned structures and SON
The patterned structure of the hybrid SOI
and bulk for achieving good performancesof both DRAM and logic devices is interesting. Patterned SOI wafers were fabricated bymasking out the oxygen implantation fromthe bulk regions during SIMOX processing.98)
DRAM and logic devices were fabricatedon the bulk and SOI areas, respectively. The
high-performance SOI-based logic-embedded
DRAM was successfully demonstrated. Another approach is the combination of selective etching with a nitride mask and selective
epitaxial growth on a bonding SOI wafer.99)
DRAM embedded in SOI devices attained
equal data retention characteristics to thosefor the bulk, while maintaining the superior
SOI performance.
Traditional SOI is fabricated on a BOX
layer having the dielectric constant of 3.9.
However, the ideal structure is a buried air
gap with a dielectric constant of unity. Structures employing silicon on nothing (SON),
having empty space beneath the top Si layer,
have been also investigated. Trench structures

It is well known that a biaxial tensile
strain in Si reduces the intervalley scatteringand lightens the effective mass by splitting
the band degeneracy, which results in theenhancement of carrier mobilities. A biaxial
strain is induced in a thin Si layer grown on arelaxed SiGe layer which is grown on Si substrate. For a high-quality Si/SiGe/Si structure,a SiGe buffer layer with a linearly graded Ge
concentration profile101) is greatly used, and athin Si buffer layer grown at a low temperature reduces the dislocation density to as low
as 10 4/cm 2 in mismatched SiGe/Si heterostructures.102)
A commercially available strained Si wafer is fabricated by three steps; (1) growthof graded SiGe layer (3 – 4µm), (2) planarization and polishing, (3) growth of strained Si
thin layer, of which the layers are grown by
CVD.103) It is reported that the thickness anduniformity of such strained Si layers is 17.5nm±5% and their rms roughness after CMP isless than 2Å.
Recently, with respect to SiGe/SOI structures, much concern has arisen regarding
the suppression of short channel effect andthe reduction of junction capacitance withdecreasing design rule. Various fabrication
methods have been investigated. By means of
the SIMOX technique using oxygen implantation at 25 keV and annealing at 1280ºC,
Si0.82Ge0.18 / SOI was successfully created.104)
In order to obtain an ultrathin SiGe / SOI witha higher Ge content, a condensation method
was developed.105) Graded SiGe and uniform
Si0.9Ge0.1 layers grown on Si were implantedby oxygen followed by annealing for SIMOX
structure. Finally, by oxidation at 1050ºC below the melting point of the SiGe layer, an

JSAP International No.11 (January 2005)

13

ultrathin Si0.43Ge0.57 / SOI with a Ge content

the design rule, respectively, were required.
However, the actual specifications are morerelaxed; The SFQR and particle size required
are comparable to or less than and comparable to the design rule, respectively. It wasreported that there is actually no difference inthe final yield of 0.17 µm DRAM between the“good” flatness wafers recommended by the
ITRS and the “bad” ones.108) Furthermore, it
is pointed out that the continuing tighteningof material quality needs to be re-examined
and re-looked at wafer requirements due tousing innovative technologies and new process materials.109) The silicon wafer industry
must make major investments at long periods in advance to achieve the developmentof technologies which can satisfy the severe
technology roadmap requirements. Additionally, the severe specifications place muchpressure on the manufacturing cost and also
bring the waste of valuable resources.
It is of great importance for wafer manufacturers to establish a reproducible manufacturing technology which does not have fluctuation against the actual targets, although
it must be important to achieve the stringent
specifications with desperate effort. For thisreason, active exchanges and a significant
degree of reliance between device and wafer
manufacturers are indispensable. It is recalledthat in the early 1980s mutual informationexchange and collaboration between thesewas fabricated because the Ge atoms werecondensed into the SiGe / SOI layer due to therejection of Ge atoms from the oxide layer.
Using the condensation method, in the SiGe /SOI with a Ge content of 25%, the electron
mobility and hole mobility were enhanced by
1.85 times and 1.5 times compared with theuniversal mobilities, respectively.106)

6. Future Prospect and Issues
It is certain that silicon crystal is indispensable to ULSI as a basic material, and willcontinue to be used indefinitely. However,for the continuing and healthy growth of thesilicon wafer industry, many issues have tobe resolved. On the other hand, the fundamental research and development of innovative silicon wafer technologies are expectedto satisfy the demands for a wide variety ofleading-edge devices.

6.1 Silicon wafer industry
It seems that the requirement of the technology roadmap which covers the long-termyears is over-stringent. For example, the technical roadmap of the Semiconductor Industry
Association (SIA) in 1994 indicated that SFQR
would be 0.08 µm and particle size 0.04 µm
for the 0.13 µm design rule to be developedin 2004.107) In other words, SFQR and particle size which were 1/1.6 and 1/3 times ofConcentration (atoms/cm3)

1 1018Ar anneal

1 1017

H2 anneal
1 1016

1 1015
0

1

2

3

4

5

Depth ( m)Fig.13. Depth profiles of boron concentration after annealing in Ar and H2 at 1200ºC
for 1h.

14

JSAP International No.11 (January 2005)

parties were promoted for the successful development and mass-production of DRAM,
and fruitful results such as device yield improvement were obtained.

6.2 Choice and issues of current
silicon wafers
A variety of silicon wafers have been developed and manufactured. Based on theunderstanding of grown-in defects and theprecise control of crystal growth technology,“pure silicon wafer” has come into practicaluse. A MDZ wafer fabricated by RTP alone
was developed. The issues of these polishedwafers will be the cost reduction for 300mm.
In order to be widely accepted by device
makers, more than two suppliers will be necessary.
Regarding annealed wafers, the establishment of productivity for hydrogen annealed 300 mm wafers and the migration ofboron atoms to the surface due to hydrogenannealing as shown in Fig. 13 are the key
issues. The most important problem associated with nitrogen doped wafers by annealing in Ar is the quantitative measurement of
nitrogen concentration, particularly at values
less than 1×10 14 atoms/cm 3. The nitrogenconcentration in Si wafer is calculated using the initial quantity of doping nitride andthe conversion efficiency of nitrogen in Si. It
is reported that the measurement down to
2×1014 atoms/cm3 is possible by IR absorption, through using the sum of absorption
by the interstitial N pair, N2O and N2O2, anddown to 4×1013 atoms/cm3 by secondary ion
mass spectroscopy (SIMS).110)
Recently, the small amount of nitrogenwith a concentration of 3×1013 atoms/cm3
was successfully measured in a nitrogen doped
Si crystal by using a Fourier-transform infrared
spectrometer (FTIR) at liquid He temperatureusing O – N – O complexes, which were foundto be solely dominant for the nitrogen concentrations less than 1×1014 atoms/cm3.111) The
further improvement and the practical use ofthis method are expected. For mass production, it is convenient that a nondestructive
measurement technique using FTIR at room
temperature similar to oxygen is used.

Invited Review Paper

The choice of epitaxial wafers, p/p– or

ogy.

+

Besides DRAM and the microprocessors(MPU) indicated by the technology roadmap,
new silicon devices with various functions
and unique performances are expected tocontribute to the future development of thesemiconductor industry. The innovative Si wafers to support those new devices are attractive. A one-chip CMOS with both an analog
RF circuit and a large-scale digital circuit is required for wireless communication networks.
For the system, high Q inductors and low-loss
transmission lines are indispensable, and thus
high-resistivity Si wafers above 2500Ω·cm are
required.118) Although high-resistivity wafers

p/p , compared to mirror-polished or annealed wafers, strongly depends on the device structures and the over-all total cost,
including device process and wafer costs.
Anyway, the cost reduction has to be proceeded. Recently, concepts for a low-pricep/p – epitaxial wafer 112) and a high-quality
epitaxial layer as thin as 0.5 µm, using a very
cost effective deposition scheme and substrates,113) have been presented.
Whichever wafers are chosen to satisfy
the stringent demands of various devices,
economically reasonable prices have to beconsidered based on the cost effectiveness. It
is sometimes experienced that those wafers
which contribute to device yield improvement
needs manufacturing extra cost. Reasonable
price is necessary to maintain the coexistenceof both device and wafer makers.

6.3 Challenge to innovative Si
wafersThe development of SOI technology issteadily continuing and the mass-production
line is being gradually strengthened. The
next target is the establishment of a massproduction technology which achieves cost
reduction. Recently, an interesting method
for fabricating SOI structures which uses theimplantation damage of light ions such as H+
and He+ has been proposed.114) A slow ramping rate and a high oxygen concentration in
the atmosphere for the annealing enabled
the creation of a continuous BOX structure byforming oxygen precipitates. This technique ispromising for the improvement of the qualityof patterned SOI and SON structures due to
low implantation damage.115)
Bonding SOI offers the possibility ofbonding with other materials. It is pointed
out that XOI structures of which the active
layers are SiGe, GaAs and SiC, and SOX structures of which the base materials are glass,sapphire, diamond, plastic and so on are
possible.116) A wide range of device applications is expected. The SOI structure with basemetal material is promising for 10 GHz operation and giga-scale integrated system LSIs,117)
which is fabricated using bonding technol-

are easily available from FZ and MCZ wafers
with low oxygen contents, CZ wafers are usable. It was demonstrated that by applying a
multistep annealing from low to high temperatures, CZ wafers with initial oxygen contents
of at least 15×1017 atoms/cm3 with a conversion factor of 4.81×1017/cm2 are converted
to have high resistivities of 1000Ω·cm and up
without donor formation during device processing.119)
Nitrogen doped Si wafers are expected
for practical use. However, the physical phenomena of nitrogen in Si are not thoroughly
understood. On the other hand, many spectroscopic data of hydrogen in Si have been
well identified. For example, it is confirmedthat the optical absorption peaks at 1987
and 1990cm –1 , 2122 and 2145cm –1 , and2223cm–1 are due to IH2, VH2 and VH4, respectively.120) On the basis of the observationthat in FZ crystal grown in H2 followed by theslow cooling vacancy-hydrogen complexes,
VH4, do not grow into large clusters such as
voids and swirls, Suezawa has proposed thathigh-quality COP-free Si crystals are hopefully grown in an atmosphere of H2 and Ar
with optimum percentage.120) VH4 complexes
are observed to dissolve at around 600ºC
and come out of the wafer. Hydrogen in Si isworth investigating.
MOS devices have been fabricated using(100) substrates for a long time because of
the many advantages. Recently, much attention has been paid to (113) and (110) substrates. High-quality SiO2/Si (113) films can beproduced by standard oxidation techniques,because Si (113) exhibits a significantly lower oxidation-induced roughening than Si(001).121) The 110GHz cutoff frequency of theultrathin gate oxide p-MOSFETs on the (110)substrate was demonstrated, because Gm of
p-MOSFET on the (110) substrate is 1.9 times
greater than that on the (100) substrate.122) It
is hoped that crystal growth technology along
the desired axes is developed for the efficient
wafer fabrication and material loss reduction.
With regard to wafer fabrication technologies, a number of advanced nanotechnologies, including newly designed machines
which were developed for 400 mm wafers123)
are expected to be used for the mass-production line of 300 mm and smaller wafers in thenear future. For future innovations, various
basic works are under investigation.

7. Conclusion
As mentioned above, Si wafers have contributed to the development and mass production of silicon ULSI devices. If innovativeand high-quality Si wafers were not being
supplied timely, further progress in the silicon
device industry would not be anticipated. It isnoted that silicon technology is expected tocontinue to be the most powerful driver ofthe information age for at least the next 100
years.124) Si wafers will continue to play a significant role as a key material indefinitely.
However, tremendous developments insilicon technology are leading to large increases in manufacturing cost. Thus, achieving cost reductions is now the most important
issue and its resolution will enable the nextstage of growth in the semiconductor industry. The reduction in cost of manufacturing isimportant, but breakthroughs in technology
leading to cost reductions are also expected.
From this point of view, mutual exchanges
between science and technology with respect
to silicon materials is earnestly desired.

Acknowledgements
The author would like to acknowledge
his former colleagues at Sumitomo Mitsubishi
Silicon Corp. for preparation of the manuscript.

JSAP International No.11 (January 2005)151 ) ITRS, 2001 Edition, Semiconductor Industry Association, San Jose (2001).
2 ) W. C. Dash: J. Appl. Phys. 29 (1958) 736.
3 ) T. Y. Tan, E. E. Gardner and W. K. Tice: Appl. Phys. Lett. 30 (1977) 175.
4 ) J. Ryuta, E. Morita, T. Tanaka and Y. Shimanuki: Jpn. J. Appl. Phys. 29 (1990)
L1947.
5 ) H. Tsuya: Oxygen in Silicon , ed. F. Shimura (Academic Press, San Diego, 1994)
Chap.14, p.619.
6 ) K. Honda, T. Nakanishi, A. Ohsawa and N. Toyokura: J. Appl. Phys. 62 (1987)
1960.
7 ) H. Wendt, H. Cerva, V. Lehmann and W. Pamler: J. Appl. Phys. 65 (1989) 2402.
8 ) Y. Furumura: Proc. 2nd Int. Conf. Symp. Advanced Sci. and Tech. Silicon
Materials , Kona, 1996 (The Japan Soc. for the Promotion of Science, Tokyo,
1996) p.418.
9 ) M. Muranaka, K. Makabe, M. Miura, H. Kato, S. Ide, H. Iwai, M. Kawamura,Y. Tadaki, M. Ishihara and T. Kaeriyama: Jpn. J. Appl. Phys. 37 (1998) 1240.
10 ) H. Ishii, S. Shiratake, K. Oka, K. Motonami, T. Koyama and J. Izumitani: Jpn. J. Appl. Phys. 35 (1996) L1385.
11 ) M. Miyazaki, S. Miyazaki, T. Kitamura, Y. Yanase, T. Ochiai and H. Tsuya: Jpn. J.
Appl. Phys. 36 (1997) 6187.
12 ) E. Dornberger, D. Temmler and W. von Ammon: J. Electrochem. Soc. 149 (2002)
G226.
13 ) K. V. Ravi: Future Fab. International, July (1999) 207.
14 ) C. S. Xu, E. Zhao, R. Jairath and W. Krusell: Electrochem. Solid-State Lett. 1 (1998)
181.
15 ) E. Morita: Proc. 98th Meet. of 145 Committee , Tokyo, 2003 (The Japan Soc.
for the Promotion of Science, Tokyo, 2003) p.23 [in Japanese].
16 ) S. M. Hu: U. S. Patent 4053335 (1977).
17 ) W. Schröter, M. Seibt and D. Gilles: Electronic Structure and Properties of
Semiconductors , ed. W. Schröter (VCH, Weiheim, 1991) p.539.
18 ) D. Gilles, E. R. Weber and S. Hahn: Phys. Rev. Lett. 64 (1990) 196.
19 ) Y. Hayamizu, S. Tobe, H. Takeno and Y. Kitagawara: Semiconductor Silicon
1998 , eds. H. R. Huff, U. Gösele and H. Tsuya (The Electrochem. Soc., Pennington, 1998) p.1080.
20 ) J. S. Kang and D. K. Schroder: J. Appl. Phys. 65 (1989) 2974.
21 ) J. L. Benton, P. A. Stolk, D. J. Eaglesham, D. C. Jacobson, J.-Y. Cheng, J. M. Poate,
N. T. Ha, T. E. Haynes and S. M. Myers: J. Appl. Phys. 80 (1996) 3275.
22 ) M. Sano, S. Sumita, T. Shigematsu and N. Fujino: Semiconductor Silicon/1994 ,eds. H. R. Huff, W. Bergholz and K. Sumino (The Electrochem. Soc., Pennington,1994) p.784.
23 ) S. Tobe, Y. Hayamizu and Y. Kitagawara: J. Appl. Phys. 84 (1998) 1279.
24 ) R. Hoelzl, D. Huber, K.-J. Range, L. Fabry, J. Hage and R. Wahlich: J. Electrochem.
Soc. 147 (2000) 2704.
25 ) P. Wagner, H. Hage, H. Prigge, Th. Prescha and J. Weber: Semiconductor Silicon/1990 , eds. H. R. Huff, K. G. Barraclough and J. Chikawa (The Electrochem.
Soc., Pennington, 1990) p.675.
26 ) H. Hieslmair, A. A. Istratov, C. Flink, S. A. McHugo and E. R. Weber: Physica B
273–274 (1999) 441.
27 ) H. Tsuya, Y. Kondo and M. Kanamori: Jpn. J. Appl. Phys. 22 (1983) L16.
28 ) A. A. Istratov, H. Hieslmair and E. R. Weber: MRS Bulletin/June (2000) 33.
29 ) S. Sadamitsu, S. Ogushi, Y. Koike, N. Reilly, T. Nagashima, M. Sano and H. Tsuya:
Solid State Phenomena , eds. C. Claeys, J. Vanhellemont, H. Richter and
M. Kittler (Scitec Publications Ltd., Switzerland, 1997) Vols.57 – 58, p.53.
30 ) H. Takeno, T. Otogawa and Y. Kitagawara: J. Electrochem. Soc. 144 (1997) 4340.

16

JSAP International No.11 (January 2005)31 ) K. Sueoka, M. Akatsuka, M. Yonemura, S. Sadamitsu, E. Asayama, T. Ono,
Y. Koike and H. Katahama: Solid State Phenomena , eds. H. G. Grimmeiss,
L. Ask, M. Kleverman, M. Kittler and H. Richter (Scitec Publications Ltd., Switzerland, 1999) Vols.69 – 70, p.63.
32 ) K. Tempelhoff and N. van Sung: Phys. Status Solidi A 72 (1982) 617.
33 ) R. Falster, D. Gambaro, M. Olmo, M. Cornara and H. Korb: Mater. Res. Soc.
Symp. Proc. 510 (1998) p.27.
34 ) J.-G. Park, H. Kirk, K.-C. Cho, H.-K. Lee, C.-S. Lee and G. A. Rozgonyi: Semiconductor Silicon/1994 , eds. H. R. Huff, W. Bergholz and K. Sumino (The Electrochem. Soc., Pennington, 1994) p.370.
35 ) K. Yamabe, K. Taniguchi and Y. Matsushita: 21st annual Proc. Reliability Physics,
1983, p.184.
36 ) M. Itsumi, H. Akiya, T. Ueki, M. Tomita and M. Yamawaki: J. Appl. Phys. 78 (1995)
5984.
37 ) M. Kato, T. Yoshida, Y. Ikeda and Y. Kitagawara: Jpn. J. Appl. Phys. 35 (1996)
5597.
38 ) Y. Yanase, H. Nishihata, T. Ochiai and H. Tsuya: Jpn. J. Appl. Phys. 37 (1998) 1.
39 ) V. V. Voronkov: J. Cryst. Growth 59 (1982) 625.
40) H. Nishikawa, T. Tanaka, Y. Yanase, M. Hourai, M. Sano and H. Tsuya: Jpn. J. Appl. Phys. 36 (1997) 6595.
41 ) M. Hasebe, Y. Takeoka, S. Shinoyama and S. Naito: Defect Control in Semiconductors , ed. K. Sumino (North-Holland, Amsterdam, 1990) p.157.
42) S. Sadamitsu, S. Umeno, Y. Koike, M. Hourai, S. Sumita and T. Shigematsu: Jpn. J.
Appl. Phys. 32 (1993) 3675.
43) P. J. Roksnoer and M. M. B. van den Boom: J. Cryst. Growth 53 (1981) 563.
44) J. G. Park, G. S. Lee, J. M. Park, S. M. Chon and H. K. Chung: Silicon Wafer
Symp., Portland, 1998 (SEMI, Mountain View, 1998) p.E-1.
45) H. Furuya, K. Harada, Y. Muroi, K. Kurita, H. Koya, K. Ikezawa and J. G. Park:
Proc. 3rd Int. Symp. Advanced Sci. and Tech. Silicon Materials , Kona,
2000 (The Japan Soc. for the Promotion of Science, Tokyo, 2000) p.96.
46) T. Sinno, R. A. Brown, W. von. Ammon and E. Dornberger: J. Electrochem. Soc.
145 (1998) 302.
47) T. Saishoji, K. Nakamura, H. Nakajima, T. Yokoyama, F. Ishikawa and J. Tomioka:
High Purity Silicon V , eds. V. C. L. Claeys, P. Rai-Choudhury, M. Watanabe,
P. Stalhofer and H. J. Dawson (The Electrochem. Soc., Pennington, 1998) p.28.
48) M. Hourai, H. Nishikawa, T. Tanaka, S. Umeno, E. Asayama, T. Nomachi and
G. Kelly: Semiconductor Silicon 1998 , eds. H. R. Huff, U. Gösele and H. Tsuya(The Electrochem. Soc., Pennington, 1998) p.453.
49) V. V. Voronkov and R. Falster: J. Electrochem. Soc. 149 (2002) G167.
50 ) M. Iida, W. Kusaki, M. Tamatsuka, E. Iino, M. Kimura and S. Muraoka: Defects
in Silicon III , eds. T. Abe, W. M. Bullis, S. Kobayashi, W. Lin and P. Wagner (TheElectrochem. Soc., Pennington, 1999) p.499.
51 ) F. Shimura and R. S. Hockett: Appl. Phys. Lett. 48 (1986) 224.
52 ) K. Nakai, H. Yokota, J. Takahashi, A. Tachikawa, K. Kitahara, A. Ikari, Y. Ohta,
M. Hasebe and W. Ohashi: Proc. Kazusa Akademia Park Forum Sci. andTech. Silicon Materials ‘99 , ed. K. Sumino (Japan Tech. Information Service,
Tokyo, 1999) p.192.
53 ) Y. Matsushita, M. Wakatsuki and Y. Saito: Ext. Abstr. 18th Int. Conf. Solid State
Devices and Materials, 1986, p.529.
54 ) H. Tsuya, F. Shimura, K. Ogawa and T. Kawamura: J. Electrochem. Soc. 129 (1982)
374.
55 ) H. Tsuya, K. Ogawa and F. Shimura: Jpn. J. Appl. Phys. 20 (1981) L31.
56 ) Y. Takano and M. Maki: Semiconductor Silicon/1973 , eds. H. R. Huff and
R. R. Burgess (The Electrochem. Soc., Pennington, 1973) p.469.

Invited Review Paper57 ) Y. Matsushita, M. Sanada, A. Tanabe, R. Takeda, N. Shimoi and N. Kobayashi:
Semiconductor Silicon 1998 , eds. H. R. Huff, U. Gösele and H. Tsuya (TheElectrochem. Soc., Pennington, 1998) p.683.
58 ) N. Adachi, T. Hisatomi, M. Sano and H. Tsuya: Semiconductor Silicon 1998 ,eds. H. R. Huff, U. Gösele and H. Tsuya (The Electrochem. Soc., Pennington,1998) p.698.
59 ) M. Tamatsuka, N. Kobayashi, S. Tobe and T. Masui: Defects in Silicon III , eds.
T. Abe, W. M. Bullis, S. Kobayashi, W. Lin and P. Wagner (The Electrochem. Soc.,
Pennington, 1998) p.456.
60 ) W. Ohashi, A. Ikari, Y. Ohta, H. Yokota, A. Tachikawa, K. Ishizaka, H. Deai,
T. Futagi, J. Takahashi, Y. Inoue and K. Nakai: Proc. Kazusa Akademia Park
Forum Sci. and Tech. Silicon Materials ‘99 , ed. K. Sumino (Japan Tech. Information Service, Tokyo, 1999) p.80.
61 ) Y. Taur, W. H. Chang and R. H. Dennard: IEDM Tech. Dig., 1984, p.398.
62 ) D. K. Su, M. J. Loinaz, S. Masui and B. A. Wooley: IEEE J. Solid-State Circuits 28(1993) 420.
63 ) H. Tsuya: 10th SEMI Silicon Wafer Workshop on Silicon Material Beyond Quarter
Micron, Tokyo, 1999.
64) M. Iwabuchi, K. Mizushima, M. Mizuno and Y. Kitagawara: J. Electrochem. Soc.
147 (2000) 1199.
65 ) S. Tobashi, T. Ohashi and H. Goto: Ext. Abstr. (61st Autumn Meet. 2000); Japan
Society of Applied Physics, 6p-ZD-3.
66 ) R. F. Stanley and C. C. Yang: U. S. Patent WO01/86034 A2 (2001).
67 ) K. Nakai, K. Kitahara, Y. Ohta, A. Ikari and M. Tanaka: Solid State Phenomena, eds. H. Richter and M. Kittler (Scitec Publications Ltd., Switzerland, 2004)
Vols.95 – 96, p.11.
68 ) H. Yamamoto: Proc. 50th Symp. Semicond. and Integrated Circuits Tech.,Tokyo, 1966, p.70 [in Japanese].
69) H. Tsuya: 39th VLSI Forum, Tokyo, 1995, p.13 [in Japanese].
70 ) Selete Manufacturing Tech. Res. Dep. Final Report, Tokyo, 2002, p.39.
71 ) Y. Shimizu: Semicon Europe 2002 SMG Meet., Munich.
72 ) M. Maruyama: Japan Patent 1851653 (1994).
73 ) X. Huang, T. Taishi, I. Yonenaga and K. Hoshikawa: Jpn. J. Appl. Phys. 40 (2001)
12.
74 ) X. Huang, T. Taishi, I. Yonenaga and K. Hoshikawa: Jpn. J. Appl. Phys. 39 (2000)
L1115.
75 ) A. Seidl, G. Müller, E. Dornberger, E. Tomzig, B. Rexer and W. von Ammon: Semiconductor Silicon 1998 , eds. H. R. Huff, U. Gösele and H. Tsuya (The Electrochem. Soc., Pennington, 1998) p.417.
76 ) F. Dupret, N. Van den Bogaert, R. Assaker and V. Regnier: Semiconductor Silicon 1998 , eds. H. R. Huff, U. Gösele and H. Tsuya (The Electrochem. Soc., Pennington, 1998) p.396.
77 ) T. Ono, G. A. Rozgonyi, C. Au, T. Messina, R. K. Goodall and H. R. Huff: J. Electrochem. Soc. 146 (1999) 3807.
78 ) K. Hoshi, T. Suzuki, Y. Okubo and N. Isawa: Meet. Abstr. Vol.80-1, No.324, 157th
ECS Meet. (1980).
79 ) K.-M. Kim: Solid State Tech. Jan. (2000) 69.
80 ) K. Hikazutani, K. Irino and T. Fukuda: Meet. Abstr. Vol.98-1, No.518, 193rd ECS
Meet. (1998).
81 ) T. Möller, W. Siebert, K. Messmann, R. Wahlich, P. Krottenthaler, R. Hölzl, A. Ikari
and W. von Ammon: Semiconductor Silicon 2002 , eds. H. R. Huff, L. Fabry
and S. Kishino (The Electrochem. Soc., Pennington, 2002) p.194.
82 ) T. Müller, E. Daub, H. Yokota, R. Wahlich, P. Krottenthaler and W. von Ammon:
Solid State Phenomena , eds. H. Richter and M. Kittler (Scitec Publications Ltd.,
Switzerland, 2004) Vols.95 – 96, p.105.

83) K. Izumi, M. Doken and H. Ariyoshi: Electron. Lett. 14 (1978) 593.
84) S. Nakashima, T. Katayama, Y. Miyamura, A. Matsuzaki, M. Imai, K. Izumi and
N. Ohwada: Proc. 1994 IEEE Int. SOI Conf., 1994, p.71.
85 ) M. J. Anc, J. G. Blake and T. Nakai: Silicon-on-Insulator Technology and Devices IX , eds. P. L. F. Hemment, S. Cristoloveanu, T. W. Houston, K. Izumi andH. Hovel (The Electrochem. Soc., Pennington, 1999) p.51.
86 ) T. Nakamura: Japan Patent 17869 (1961).
87 ) T. Yonehara, K. Sakaguchi and N. Sato: Appl. Phys. Lett. 64 (1994) 2108.
88 ) N. Sato, Y. Kakizaki, T. Atoji, K. Notsu, H. Miyabayashi, M. Ito and T. Yonehara:
Proc. 2002 IEEE Int. SOI Conf., 2002, p.209.
89 ) M. Bruel: Electron. Lett. 31 (1995) 1201.
90 ) T. Yonehara, K. Ohmi, J. Nakayama, K. Sakaguchi, N. Sato, K. Yamagata,
K. Yanagita and Y. Kakizaki: Oyo Buturi 71 (2002) 1102 [in Japanese].
91 ) C. Maleville and A.-J. Auberton-Herve: Ext. Abstr. 2002 Int. Conf. Solid State Devices and Materials, 2002, p.788.
92 ) J. Jablonski, Y. Miyamura, M. Imai and H. Tsuya: J. Electrochem. Soc. 142 (1995)
2059.
93 ) K. L. Beaman, A. Agarwal, O. Kononchuk, S. Koveshnikov, I. Bondarenko and G. A.
Rozgonyi: App. Phys. Lett. 71 (1997) 1107.
94) A. A. Istratov, W. Huber and E. R. Weber: Solid State Phenomena , eds.
H. Richter and M. Kittler (Scitec Publications Ltd., Switzerland, 2004) Vols.95 – 96,
p.547.
95 ) S. Q. Hong, T. Wetteroth, H. Shin, S. R. Wilson, D. Werho, T.-C. Lee and
D. K. Schroder: Appl. Phys. Lett. 71 (1997) 3397.
96 ) K. L. Beaman, O. Kononchuk, S. Koveshnikov, C. M. Osburn and G. A. Rozgonyi:
J. Electrochem. Soc. 146 (1999) 1925.
97 ) H. Naruoka, T. Iwamatsu, T. Ipposhi, N. Hattori, Y. Inoue and Y. Mashiko: Ext. Abstr. 2002 Int. Conf. Solid State Devices and Materials, 2002, p.792.
98 ) R. Hannon, S. Sundar, K. Iyer, D. Sadana, J. P. Rice, H. L. Ho, B. A. Khan and
S. S. Iyer: 2000 Symp. VLSI Tech. Dig. Tech. Pap., 2000, p.66.
99 ) T. Yamada et al .: 2002 Symp. VLSI Tech. Dig. Tech. Pap., 2002, p.112.
100) T. Sato, H. Nii, M. Hatano, K. Takenaka, H. Hayashi, K. Ishigo, T. Hirano, K. Ida,
N. Aoki, T. Ohguro, K. Ino, I. Mizushima and Y. Tsunashima: IEDM Tech. Dig.,1999, p.517.
101) Y. J. Mii, Y. H. Xie, E. A. Fitzgerald, D. Monroe, F. A. Thiel, B. E. Weir and
L. C. Feldman: Appl. Phys. Lett. 59 (1991) 1611.
102) K. K. Linder, F. C. Zhang, J.-S. Rieh, P. Bhattacharya and D. Houghton: Appl. Phys.
Lett. 70 (1997) 3224.
103) M. T. Bulsara: Semicon Europa: Workshop Silicon Wafers with Functional Layers(2003).
104) S. Fukatsu, Y. Ishikawa, T. Saito and N. Shibata: Appl. Phys. Lett. 72 (1998) 3485.
105) T. Tezuka, N. Sugiyama, T. Mizuno, M. Suzuki and S. Takagi: Ext. Abstr. 2000 Int.
Conf. Solid State Devices and Materials, 2000, p.472.
106) T. Mizuno, N. Sugiyama, T. Tezuka, T. Numata and S. Takagi: 2002 Symp. VLSI
Tech. Dig. Tech. Pap., 2002, p.106.
107) The National Technology Roadmap for Semiconductors, Semiconductor Industry
Association, San Jose, 1994.
108) H. Dietrich, C. Kupfer, J. Martin and F. Katzwinkel: Semiconductor Silicon
2002 , eds. H. R. Huff, L. Fabry and S. Kishino (The Electrochem. Soc., Pennington, 2002) p.176.
109) K. V. Ravi: Solid State Phenomena , eds. H. G. Grimmeiss, L. Ask,
M. Kleverman, M. Kittler and H. Richter (Scitec Publications Ltd., Switzerland,1999) Vols.69 – 70, p.103.
110) N. Inoue, K. Shingu and K. Masumoto: Semiconductor Silicon 2002 , eds.
H. R. Huff, L. Fabry and S. Kishino (The Electrochem. Soc., Pennington, 2002)
p.875.

JSAP International No.11 (January 2005)

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Invited Review Paper111) H. Ono and M. Horikawa: Jpn. J. Appl. Phys. 42 (2003) L261.
112) H. Shimizu, T. Satoh, M. Muranaka, K. Makabe and M. Miura: J. Electrochem.
Soc. 147 (2000) 1930.
113) R. Schmolke, M. Blietz, R. Schauer, D. Zemke, H. Oelkrug, W. von Ammon,
U. Lambert and D. Gräf: High Purity Silicon VI , eds. C. L. Claeys,
P. Rai-Choudhury, M. Watanabe, P. Stallhofer and H. J. Dawson (The Electrochem.
Soc., Pennington, 2000) p.3.
114) A. Ogura: Jpn. J. Appl. Phys. 40 (2001) L1075.
115) A. Ogura: Appl. Phys. Lett. 82 (2003) 4480.
116) S. Cristoloveanu: Semiconductor Silicon 2002 , eds. H. R. Huff, L. Fabry and
S. Kishino (The Electrochem. Soc., Pennington, 2002) p.328.
117) T. Ohmi and S. Sugawa: Proc. 3rd Int. Symp. Advanced Sci. and Tech. Silicon Materials , Kona, 2000 (The Japan Soc. for the Promotion of Science,
Tokyo, 2000) p.1.
118) M. Muraguchi: Ext. Abstr. 1998 Int. Conf. Solid State Devices and Materials,
1998, p.76.

119) T. Abe, S. Saito, K. Aihara, W. Qu, Y. Hayamizu, M. Kimura and K. Mitani: Ext.
Abstr. 1999 Int. Conf. Solid State Devices and Materials, 1999, p.356.
120) M. Suezawa: Proc. Kazusa Akademia Park Forum Sci. and Tech. Silicon
Materials ‘99 , ed. K. Sumino (Japan Tech. Information Service, Tokyo, 1999) p.15.
121) H.-J. Müssig, J. Dabrowski, K.-E. Ehwald, P. Gaworzewski, A. Huber andU. Lambert: Proc. 3rd Int. Symp. Advanced Sci. and Tech. Silicon Materials , Kona, 2000 (The Japan Soc. for the Promotion of Science, Tokyo, 2000)
p.374.
122) H. S. Momose, T. Ohguro, K. Kojima, S. Nakamura and Y. Toyoshima: 2002 Symp.
VLSI Tech. Dig. Tech. Pap., 2002, p.156.
123) S. Hagino, H. Oisi, K. Abe and K. Hayashi: Proc. 3rd Int. Symp. Advanced Sci.
and Tech. Silicon Materials , Kona, 2000 (The Japan Soc. for the Promotion of
Science, Tokyo, 2002) p.108.
124) H. R. Huff: Semiconductor Silicon 2002 , eds. H. R. Huff, L. Fabry and
S. Kishino (The Electrochem. Soc., Pennington, 2002) p.1005.

Hideki Tsuya was born in Hokkaido, Japan in 1938. He received his B.S. degree in Physics from the University of Tokyo in 1962. He joined NEC Co. Ltd., Central Research Laboratories in 1962. He earned his Ph. D. in Engineering fromthe University of Tokyo in 1976. He was promoted to General Manager of the VLSI Development Division in 1989
and was Research Fellow of the R&D Group in 1991. He joined Sumitomo Sitix Co. as Managing Director and General Manager of Silicon Technology R&D Center in 1995. He was appointed as Technology Director of Sumitomo Metal
Industries Ltd. in 1998 and Corporate Auditor of Sumitomo Mitsubishi Silicon Co. in 2002 before retiring in 2003. He
is an author and coauthor of more than 70 original papers and 34 patents. He was awarded the 39th Okochi Memorial Grand Prize in 1993. He served concurrently as Visiting Professor of North Carolina State University in 1993
and Kyushu University in 2000. He is a member of the Japan Society of Applied Physics.

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