QN9080-001-M17
Ultra Low-Power Bluetooth Smart 5.0 SIP
Rev. 1.0 — 5 December 2018

Objective data sheet

1. General description
The QN9080-001-M17 is a fully certified device supporting BLE and NFC. It has ultra-low
power consumption, highly integrated with rich feature sets, fully FCC/CE/IC/MIC certified.
The QN9080-001-M17 supports Bluetooth 5, and it is intended for ultra-small, portableconnected wireless applications.
This ultra-small device is based on QN9080 die and NT3H2211 die. QN9080 is poweredby an Arm Cortex-M4F, and has a dedicated fusion sensor co-processor (FSP) tofurther reduce power consumption by off-loading complex math computations to thehardware. 512 KB of on-board flash and 128 KB SRAM provide enough room andflexibility for complex applications. NT3H2211 is NFC Forum Type 2 Tag compliant IC with
I2C interface, which supplies the fastest, least expensive way to add tap-and-goconnectivity to just about any electronic applications.
The QN9080-001-M17 also integrates 32 MHz and 32.768 kHz crystals, a 2.4 GHz
optimized antenna, and necessary components for QN9080 system to run. It offers acomplete solution for applications requiring BLE wireless connectivity and fast pairing withNTAG as an option. Its low external component count reduces overall system size,
complexity and shortens development time.

2. Features and benefitsKey features: Bluetooth 5.0 certified
 Integrated antenna
 Integrated 32 MHz and 32.768 kHz crystals
 32-bit Arm Cortex-M4F core at 32 MHz
 512 KB flash
 128 KB RAM
 TX power: up to +2 dBm
 RX sensitivity: -92.7 dBm in 1 Mbps mode and -89 dBm in 2 Mbps mode
True single-chip Bluetooth Low Energy (v5.0) SoC solution:
 Integrated Bluetooth LE radio, protocol stack and application profiles
 Support central and peripherals roles
 Support master/slave concurrency
 Support 16 simultaneous links
 Support secure connections
 Support data packet length extension
 48-bit unique BD address
 -92.7 dBm in 1 Mbps mode and -89 dBm in 2 Mbps mode

NXP Semiconductors

Ultra Low-Power Bluetooth Smart
QN9080-001-M17









 TX output power from -20 dBm to +2 dBm
Very low power consumption:
 Single 1.67 V ~3.6 V power supply 1 A power-down mode, to wake up by GPIO
 2 A power-down mode, to wake up by 32 kHz sleep timer, RTC and GPIO
 4 mA RX current at 3 V supply in 1 Mbps
 Ultra Low power Bluetooth Low Energy 5.0 module 3.5 mA TX current at 0 dBm TX power at 3 V supply in 1 Mbps mode
Interface: 32 General-Purpose Input/Output (GPIO) pins, with configurable pull-up/pull-downresistors
 8 external ADC inputs (shared with GPIO pins) 2 Analog Comparator input pins (share with GPIO pins)
Single power supply 1.67 V to 3.6 V
Operating temperature range -40 °C to +85 °C
6 x9.7x1.17 mm LFLGA package

2.1 Feature of QN9080
 True single-chip Bluetooth Low Energy (v5.0) SoC solution
 Integrated Bluetooth LE radio, protocol stack and application profiles
 Supports central and peripherals roles
 Supports master/slave concurrency
 Supports 16 simultaneous links
 Supports secure connections
 Supports data packet length extension
 Wifi/Bluetooth LE coexistence interface
 48-bit unique bluetooth device address
 RF
 Fast and reliable RSSI in 1 dB step
 TX output power from 20 dBm to 2 dBm
 Single-ended RF port with integrated balun
 Generic FSK modulation with programmed data rate from 250 Kbps to 2 Mbps
 Compatible with worldwide radio frequency regulations
 Very low power consumption
 Single 1.67 V to 3.6 V power supply
 Integrated DC-to-DC buck converter and LDO
 1.0 A power-down 1 mode, to wake up by GPIO
 2.5 A power-down 0 mode, to wake up by 32 kHz sleep timer, RTC and GPIO
 3.5 mA RX current with DC-to-DC convertor enabled at 3 V supply in 1Mbps mode 4 mA TX current at 0 dBm TX power with DC-to-DC converter enabled at 3 V
supply in 1 Mbps mode Arm Cortex-M4 core (version r0p1)
 Arm Cortex-M4 processor, running at a frequency of up to 32 MHz
 Floating Point Unit (FPU) and Memory Protection Unit (MPU)
QN9080-001-M17

Objective data sheet

All information provided in this document is subject to legal disclaimers.

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Ultra Low-Power Bluetooth Smart
QN9080-001-M17

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QN9080-001-M17

Objective data sheet

 Arm Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC)
 Serial Wire Debug (SWD) with six instruction breakpoints, two literal comparators,
and four watch points, including serial wire output for enhanced debug capabilities
 System tick timer
On-chip memory
 512 KB on-chip flash program memory and 2 KB page erase and write 128 KB SRAM
 256 KB ROM
ROM API support
 Flash In-System Programming (ISP)
Serial interfaces Four Flexcomm serial peripherals
 USART protocol supported by Flexcomm0, USART and I2C by Flexcomm1, SPI
and I2C by Flexcomm2, and SPI by Flexcomm3
 Each Flexcomm includes a FIFO I2C-bus interfaces support fast mode and with multiple address recognition andmonitor mode USB 2.0 (full speed) device interface
 Two quadrature decoders
 SPI Flash Interface (SPIFI) uses a SPI bus superset with four data lines to accessoff-chip quad SPI flash memory at a much higher rate than is possible using
standard SPI or SSP interfaces
 Supports SPI memories with 1 or 4 data lines
Digital peripherals
 DMA controller with 20 channels, able to access memories and DMA capable
peripherals
 Up to 35 General Purpose Input Output (GPIO) pins, with configurable pull-up or
pull-down resistors
 GPIO registers are located on the AHB for fast access 32 GPIOs can be selected as Pin INTerrupts (PINT), triggered by rising, or falling
input edges
 AES-128 security coprocessor Random Number Generator (RNG)
 CRC engine
 Fusion Signal Processor (FSP) for data fusion and machine learning algorithms
resulting in low power consumption compared to software processing

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Ultra Low-Power Bluetooth Smart
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 Analog peripherals
 16-bit ADC with 8 external input channels, with sample rates of up to 32k sample
per second, and with multiple internal and external trigger inputs
 Integrated temperature sensor, connected to one internal dedicated ADC channel
 Integrated battery monitor connected to one internal dedicated ADC channel
 General-purpose 8-bit 1M sample per second DAC
 Integrated capacitive sense up to 8 channels, able to wake up the MCU from low
power states.
 Two ultra low-power analog comparators, able to wake up the MCU from low powerstates.
 Timers Four 32-bit general-purpose timers or counters, support capture inputs andcompare outputs, PWM mode, and external count input
 Sleep timer, which can work in power-down mode and wake up MCU
 32-bit Real Time Clock (RTC) with 1 second resolution running in the always-on
power domain; can be used for wake-up from all low power modes including
power-down Watchdog Timer.
 SC Timer or PWM.
 Clock generation
 32 MHz internal RC oscillator, which can be used as a system clock 16 MHz or 32 MHz crystal oscillator, which can be used as a system and RF
reference 32 kHz on-chip RC oscillator 32.768 kHz crystal oscillator
 Power control
 Programmable Power Management Unit (PMU) to minimize power consumption
 Reduced power modes: sleep, and power-down
 Power-On Reset (POR)
 Brown-Out Detection (BOD) with separate thresholds for interrupt and forced reset Single power supply 1.67 V to 3.6 V
 Operating temperature range 40 °C to +85 °C
See QN908x data sheet for more details.

2.2 Features of NTAG
 Interoperability ISO/IEC 14443 Part 2 and 3 compliant
 NTAG I2C plus development board is certified as NFC Forum Type 2 Tag(Certification ID: 58514)
 Unique 7-byte UID
 GET_VERSION command for easy identification of chip type and supported
features Input capacitance of 50 pF
 Host interface
 I2C slave
QN9080-001-M17

Objective data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1.0 — 5 December 2018

© NXP Semiconductors B.V. 2018. All rights reserved.

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 Configurable event detection pin to signal NFC or pass-through data events
Memory 1912 bytes of EEPROM-based user memory
 64 bytes SRAM buffer for transfer of data between NFC and I2C interfaces withmemory mirror or pass-through mode Clear arbitration between NFC and I2C memory access
Data transfer
 Pass-through mode with 64-byte SRAM buffer
 FAST_WRITE and FAST_READ NFC commands for higher data throughput
Security and memory-access management
 Full, read-only, or no memory access from NFC interface, based on 32-bit
password
 Full, read-only, or no memory access from I2C interface
 NFC silence feature to disable the NFC interface
 Originality signature based on Elliptic Curve Cryptography (ECC) for simple,
genuine authentication
Power Management
 Configurable field-detection output signal for data-transfer synchronization anddevice wake-up Energy harvesting from NFC field, so as to power external devices (e.g. connected
microcontroller)

See NT3H2111_2211 Product Data Sheet for more details.

2.3 Features of integrated 2.4 GHz antenna
 Monolithic SMD with small, low-profile and light-weight type.
 Wide bandwidth RoHS compliant
Note: When NFC function is required, the NFC tag antenna need to be connected
externally.

3. Applications


Health and medical devices
Sports and fitness trackers
Building and home automation
Retail and advertising beacons

4. Ordering information
Table 1.

Ordering information

Type number

Package
Name

QN9080-001-M17

QN9080-001-M17

Objective data sheet

LFLGA54

Description

VersionSIP module in LGA package; body 6  9.7  1.17 mm SOT1910 AA1

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Table 2.

Ordering options

Type number

PackagenumberFlash (KB)

QN9080-001-M17 3322 960 18570 512

Total SRAM Cortex-M4(KB)
with FPUFSP

USB FS

GPIO

128

1

1

32

1

5. Marking

QN9080-1-M17
XXXXX
XXXXXXXXXXXXEtDYYWWXX

Fig 1.

QN9080-001-M17 package marking

Table 3.

Marking codesLine
numberContent

Descriptions

NXP

1

Logo

2

QN9080-1-M17

Product identifier

3

XXXXX

STR number request. It will be removed on production

4

XXXXXXXXXXXX

QN batch number

5

E

TSMC

t

ASE-K

D

RoHS indicator (Dark green)

YYyear; last two digits of year code of assemblyWWweek code of assemblyX

mask version

X

for SIP before CQS; it will be removed after

QN9080-001-M17 has the following top-side marking:Table 4.

Device revision table

Revision identifier (R)001

Revision description
Initial SIP module revision

QN9080-001-M17 device has received FCC "Modular Approval", in compliance with CFR
47 FCC part 15 regulations and in accordance to FCC public notice DA00-1407. The
modular approvals notice and test reports are available on request.
Remark: FCC, IC & Japan ID are not mentioned on the package due to the small device
size.

QN9080-001-M17

Objective data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1.0 — 5 December 2018

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QN9080-001-M17

6. Block diagram

QN9080M

Antenna

Harmonic filter
L2 3.3 nH

C3
0.1 ¾ FC4
0.1 ¾ F

ANT INC5
0.1 ¾ FC2
1.8 pFC1
1.8 pF

DCDC

L3
10nH

L1
10 ¾ H

DVDD

RVDD

AVDD

IDC

C6
1¾F

XTAL_IN
XTAL_OUT

Y1
32 MHzVCC

VCC
XTAL32_IN
Y2
32.768 kHz

RF
XTAL32_OUT

RF OUT

QN9080 die

PA31-PA00

CHIP_MODE
CHRG_SCL
CHRG_SDA

RSTN

SCL
SDA
FD

NTAG_LANTAG
NT3H2211

NTAG_LB
NTAG_VOUT

VSS
GND

GND

GND

DAP

NTAG_FDFig 2.

NTAG_VCC

QN9080-001-M17 – high level HW block diagram

QN9080-001-M17

Objective data sheet

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QN9080-001-M17

QN9080M

Antenna

Harmonic filter
L2 3.3 nH

C3
0.1 ¾ FC4
0.1 ¾ F

ANT INC5
0.1 ¾ FC2
1.8 pFC1
1.8 pF

DCDC

L3
10nH

L1
10 ¾ H

DVDD

RVDD

AVDD

IDC

C6
1¾F

XTAL_IN
XTAL_OUT

Y1
32 MHzDesigned and provided by customer
External
Antenna

VCC

VCC

Harmonic filter

XTAL32_IN
Y2
32.768 kHz
XTAL32_OUT

L2 3.3 nH

RF OUT

RF

QN9080 die

C1
1.8 pFC2
1.8 pF

PA31-PA00

CHIP_MODE
CHRG_SCL
CHRG_SDA

RSTN

SCL
SDA
FD

NTAG_LANTAG
NT3H2211

NTAG_LB
NTAG_VOUT

VSS
GND

GND

GND

DAP

NTAG_FDFig 3.

NTAG_VCC

QN9080-001-M17 block diagram using external antenna

Remark: (1) QN9080-001-M17 is not certified with external antenna but only with its
internal antenna. Customer using external antenna has to do new certification. (2)Harmonic filter is in adequacy with board.

QN9080-001-M17

Objective data sheet

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QN9080-001-M17

7. Pinning information
7.1 Pinning

1

44

43

41

40

39

38

37

36

35

2

34

3

33

4

32

5

51

31

54

6

30

7

29

8

52

28

53

9

27

10

26

11

25

12

24

13

Fig 4.

42

14

15

16

17

18

19

20

21

22

23

45

50

46

49

47

48

QN9080-001-M17 pinout diagram

7.2 Pin description
Table 5.

Pin description

Symbol LFLGA54

Reset
state[1]Alternate function Type

Description

PA30

PU

GPIOA30

I/O

general-purpose digital input output pin

ACMP1PAI

analog comparator 1 positive input

1

QN9080-001-M17

Objective data sheet

ETM_TRACEDAT3 O

ETM trace data output bit 3

CTIMER3_MAT1

O

timer 3 match output 1

FC2_SCK

I/O

flexcomm 2: SPI clock

FC3_MOSI

I/O

flexcomm 3: SPI MOSISPIFI_IO3

I/O

data bit 3 for the SPI flash interface

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QN9080-001-M17

Table 5.

Pin description …continued

Symbol LFLGA54

Reset
state[1]Alternate function Type

Description

PA29

PU

GPIOA29

I/O

general-purpose digital input output pin

ACMP1NAI

analog comparator 1 negative input

PA28

PA27

PA26

2

3

4

5

PU

PU

PU

ETM_TRACEDAT2 O

ETM trace data output bit 2

CTIMER3_MAT0

O

timer 3 match output 0

FC2_SCK

I/O

flexcomm 2: SPI clock

FC3_MISO

I/O

flexcomm 3: SPI MISOSPIFI_IO2

I/O

data bit 2 for the SPI flash interface

GPIOA28

I/O

general-purpose digital input output pin

CLK_AHBOAHB clock output

ETM_TRACECLKOETM trace clock output

RTC_CAPI

RTC capture input

FC1_SCK

I/O

flexcomm 1: USART clock

SD_DACO

sigma-delta modulator DAC output

SPIFI_CSN

O

active low chip select output for the SPI flash interface

GPIOA27

I/O

general-purpose digital input output pin

USB_DM

I/O

USB0 bidirectional D- line

SCT0_IN1I

SCTimer input 1

CTIMER1_MAT2

O32-bit CTimer 1 match output 2

FC2_SCL_MISO

I/O

flexcomm 2: I2C SCL, SPI MISOQDEC0_BI

quadrature decoder 0 input channel B

BLE_IN_PROCO

BLE event in process indicator for coexistence

GPIOA26

I/O

general-purpose digital input output pin

USB_DP

I/O

USB0 bidirectional D+ line

SCT0_IN0I

SCTimer input 0

CTIMER1_MAT0O32-bit CTimer 1 match output 0

FC2_SDA_MOSI

I/O

flexcomm 2: I2C SDA, SPI MOSIQDEC0_AI

quadrature decoder 0 input channel A

BLE_SYNCO

BLE sync pulse

LB

6





RF

NTAG antenna/coil terminal B

LA

7





RF

NTAG antenna/coil terminal A

PA25

8

PU

GPIOA25

I/O

general-purpose digital input output pin

ACMP0P/CS7

AI

analog comparator 0 positive input, or capacitive touch sense
button input 7

QN9080-001-M17

Objective data sheet

ETM_TRACEDAT1 O

ETM trace data output bit 1

CTIMER3_CAP1

I

timer 3 input capture 1

RFE_TX_ENO

TX enable for external RF front-end

FC3_SSEL0

I/O

flexcomm 3: SPI SSEL0SPIFI_IO1

I/O

data bit 1 for the SPI flash interface

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QN9080-001-M17

Table 5.

Pin description …continued

Symbol LFLGA54

Reset
state[1]Alternate function Type

Description

PA24

PU

GPIOA24

I/O

general-purpose digital input output pin

ACMP0N/CS6

AI

analog comparator 0 negative input, or capacitive touch
sense button input 6

SWDIO/
PA23

SWCLK
/PA22

PA21

PA20

9

10

11

12

13

QN9080-001-M17

Objective data sheet

PU

PU

PU

PU

ETM_TRACEDAT0 O

ETM trace data output bit 0

CTIMER3_CAP0

I

timer 3 input capture 0

RFE_RX_ENO

RX enable for external RF front-end

FC3_SSEL1

I/O

flexcomm 3: SPI SSEL1SPIFI_IO0

I/O

data bit 0 for the SPI flash interface

SWDIO

I/O

serial wire debug I/O; it is the default function after booting

GPIOA23

I/O

general-purpose digital input output pin

SCT0_IN3I

SCTimer input 3

CTIMER3_MAT1

O32-bit CTimer 3 match output 1

FC2_SCL_SSEL1

I/O

flexcomm 2: I2C SCL, SPI SSEL1

FC3_SSEL2

I/O

flexcomm 3: SPI SSEL2

QDEC1_BI

quadrature decoder 1 input channel B

SWCLK

I/O

serial wire clock; it is the default function after reset

GPIOA22

I/O

general-purpose digital input output pin

SCT0_IN2I

SCTimer input 2

CTIMER3_MAT0O32-bit CTimer 3 match output 0

FC2_SDA_SSEL0

I/O

flexcomm 2: I2C SDA, SPI SSEL0

FC3_SSEL3

I/O

flexcomm 3: SPI SSEL3

QDEC1_AI

quadrature decoder 1 input channel A

GPIOA21

I/O

general-purpose digital input output pin

QDEC1_BI

quadrature decoder 1 input channel B

SCT0_OUT0O

SCTimer output 0, PWM output 0

CTIMER2_MAT1

O32-bit CTimer 2 match output 1

FC2_SSEL3

I/O

flexcomm 2: SPI SSEL3

FC1_CTS_SDA

I/O

flexcomm 1: USART CTS, I2C SDASPIFI_CSN

O

active low chip select output for the SPI flash interface

GPIOA20

I/O

general-purpose digital input output pin

QDEC1_AI

quadrature decoder 1 input channel A

SCT0_OUT1OSCTimer output 1, PWM output 1

CTIMER2_MAT0O32-bit CTimer 2 match output 0

SWO

I/O

serial wire trace output

FC1_RTS_SCL

I/O

flexcomm 1: USART RTS, I2C SCLSPIFI_CLKO

clock output for the SPI flash interface

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Table 5.

Pin description …continued

Symbol LFLGA54

Reset
state[1]Alternate function Type

Description

PA19

PU

GPIOA19

I/O

general-purpose digital input output pin

CS5

AI

capacitive touch sense button input 5

SCT0_OUT2O

SCTimer output 2, PWM output 2

RFE_EN

O

enable for external RF front-end

FC0_SCK

I/O

flexcomm 0: USART clock

FC3_SSEL3

I/O

flexcomm 3: SPI SSEL3

PA18

PA17

PA16

PA15

14

15

16

17

18

QN9080-001-M17

Objective data sheet

PU

PU

PU

PU

BLE_IN_PROCO

BLE event in process indicator for coexistence

GPIOA18

I/O

general-purpose digital input output pin

CS4

AI

capacitive touch sense button input 4

SCT0_OUT3O

SCTimer output 3, PWM output 3

CTIMER2_MAT2

O32-bit CTimer 2 match output 2

FC0_SCK

I/O

flexcomm 0: USART clock

FC3_SSEL2

I/O

flexcomm 3: SPI SSEL2

BLE_SYNCO

BLE sync pulse

GPIOA17

I/O

general-purpose digital input output pin

CS3

AI

capacitive touch sense button input 3

SD_DACO

sigma-delta modulator DAC output

CTIMER2_MAT1

O32-bit CTimer 2 match output 1

FC0_RXD

I/O

flexcomm 0: USART RXD

FC3_MISO

I/O

flexcomm 3: SPI MISOQDEC0_BI

quadrature decoder 0 input channel B

GPIOA16

I/O

general-purpose digital input output pin

CS2

AI

capacitive touch sense button input 2

SCT0_OUT1OSCTimer output 1, PWM output 1

CTIMER2_MAT0O32-bit CTimer 2 match output 0

FC0_TXD

I/O

flexcomm 0: USART TXD

FC3_MOSI

I/O

flexcomm 3: SPI MOSIQDEC0_AI

quadrature decoder 0 input channel A

GPIOA15

I/O

general-purpose digital input output pin

CS1

AI

capacitive touch sense button input 1

SCT0_OUT0O

SCTimer output 0, PWM output 0

CTIMER2_CAP1

I

timer 2 input capture 1

FC0_CTS

I/O

flexcomm 0: USART CTS

FC3_SCK

I/O

flexcomm 3: SPI clock

QDEC1_BI

quadrature decoder 1 input channel B

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Table 5.

Pin description …continued

Symbol LFLGA54

Reset
state[1]Alternate function Type

Description

PA14

PU

GPIOA14

I/O

general-purpose digital input output pin

CS0

AI

capacitive touch sense button input 0

PA13

CHIP_M
ODE/PB
02

19

20

21

PU

PU

ANT_SWO

external antenna switch for diversity

CTIMER2_CAP0

I

timer 2 input capture 0

FC0_RTS

I/O

flexcomm 0: USART RTS

FC3_SSEL0

I/O

flexcomm 3: SPI SSEL0

QDEC1_AI

quadrature decoder 1 input channel A

GPIOA13

I/O

general-purpose digital input output pin

R

I/O

reserved

SCT0_OUT4O

SCTimer output 4

ACMP1_OUT

O

analog comparator 1 output

FC1_RXD_SDA

I/O

flexcomm 1: USART RXD, I2C SDA

FC3_SSEL1

I/O

flexcomm 3: SPI SSEL1

RFE_EN

O

enable for external RF front-end

CHIP_MODEI

boot selection with pull-up by default; it should be pulled low
to go through the normal ISP process for firmware
programming, otherwise the ISP process is escaped to jump
to flash

GPIOB02

I/O

general-purpose digital input output pin

ANT_SWO

external antenna switch for diversity

RSTN

22

PU



I

active low reset input

ANT_IN

23





RF

Internal antenna

RF_OU
T

24





RF

RF input output port with Tx or Rx switch integrated on chip

GND

25





PA12

26

PU

GPIOA12

PA1127

QN9080-001-M17

Objective data sheet

PU

groundI/Ogeneral-purpose digital input output pin

RO

reserved

SCT0_OUT5O

SCTimer output 5

ACMP0_OUT

O

analog comparator 0 output

FC1_TXD_SCL

I/O

flexcomm 1: USART TXD, I2C SCL

SD_DACO

sigma-delta modulator DAC output

ANT_SWO

external antenna switch for diversity

GPIOA11

I/O

general-purpose digital input output pin

ADC7

AI

ADC external input 7

SCT0_IN3I

SCTimer input 3

CTIMER1_MAT2

O32-bit CTimer 1 match output 2

FC2_SSEL2

I/O

flexcomm 2: SPI SSEL2

ACMP1_OUT

O

analog comparator 1 output

BLE_RXO

BLE reception indicator for coexistence

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Table 5.

Pin description …continued

Symbol LFLGA54

Reset
state[1]Alternate function Type

Description

PA10

PU

GPIOA10

I/O

general-purpose digital input output pin

ADC6

AI

ADC external input 6

SCT0_IN2I

SCTimer input 2

CTIMER1_MAT1

O32-bit CTimer 1 match output 1

FC1_SCK

I/O

flexcomm 1: USART clock

ACMP0_OUT

O

analog comparator 0 output

PA09

PA08

PA07

PA06

28

29

30

31

32

QN9080-001-M17

Objective data sheet

PU

PU

PU

PU

BLE_TXO

BLE transmit indicator for coexistence

GPIOA9I/O

general-purpose digital input output pin

ADC5

AI

ADC external input 5

SCT0_IN1I

SCTimer input 1

CTIMER1_MAT0O32-bit CTimer 1 match output 0

FC1_RXD_SDA

I/O

flexcomm 1: USART RXD, I2C SDA

BLE_PTI3

O

BLE packet traffic information bit 3

SPIFI_IO3

I/O

data bit 3 for the SPI flash interface

GPIOA8

I/O

general-purpose digital input output pin

ADC4

AI

ADC external input 4

SCT0_IN0I

SCTimer input 0

CTIMER1_CAP1

I

timer 1 input capture 1

FC1_TXD_SCL

I/O

flexcomm 1: USART TXD, I2C SCL

BLE_PTI2

O

BLE packet traffic information 2

SPIFI_IO2

I/O

data bit 2 for the SPI flash interface

GPIOA7

I/O

general-purpose digital input output pin

ADC_VREFIAI

ADC external reference voltage input

SCT0_OUT2O

SCTimer output 2

CTIMER1_CAP0

I

timer 1 input capture 0

FC1_CTS_SDA

I/O

flexcomm 1: USART CTS, I2C SDA

BLE_PTI1

O

BLE packet traffic information 1

SPIFI_CSN

O

active low chip select output for the SPI flash interface

GPIOA6

I/O

general-purpose digital input output pin

ADC_EX_CAP

Aconnected with ADC external capacitor

SCT0_OUT3O

SCTimer output 3

CTIMER0_MAT2

O32-bit CTimer 0 match output 2

FC1_RTS_SCL

I/O

flexcomm 1: USART RTS, I2C SCL

BLE_PTI0

O

BLE packet traffic information bit 0

SPIFI_CLKO

clock output for the SPI flash interface

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Table 5.

Pin description …continued

Symbol LFLGA54

Reset
state[1]Alternate function Type

Description

PA05

PU

GPIOA5

I/O

general-purpose digital input output pin

ADC3

AI

ADC external input 3

SCT0_OUT5O

SCTimer output 5

CTIMER0_MAT1

O32-bit CTimer 0 match output 1

FC0_RXD

I/O

flexcomm 0: USART RXD

FC2_SCL_MISO

I/O

flexcomm 2: SCL, SPI MISO

PA04

PA03

PA02

33

34

35

36

PU

PU

PU

SPIF_IO1

I/O

data bit 1 for the SPI flash interface

GPIOA4

I/O

general-purpose digital input output pin

ADC2

AI

ADC external input 2

SCT0_OUT4O

SCTimer output 4

CTIMER0_MAT0O32-bit CTimer 0 match output 0

FC0_TXD

I/O

flexcomm 0: USART TXD

FC2_SDA_MOSI

I/O

flexcomm 2: I2C SDA, SPI MOSISPIF_IO0

I/O

data bit 0 for the SPI flash interface

GPIOA3

I/O

general-purpose digital input output pin

QDEC0_BI

quadrature decoder 0 input channel B

SCT0_OUT3O

SCTimer output 3

CTIMER0_MAT1

O32-bit CTimer 0 match output 1

RO

reserved

FC2_SDA_SSEL0

I/O

flexcomm 2: I2C SDA, SPI SSEL0

RFE_TX_ENO

TX enable for external RF front-end

GPIOA2

I/O

general-purpose digital input output pin

QDEC0_AI

quadrature decoder 0 input channel A

SCT0_OUT2O

SCTimer output 2

CTIMER0_MAT0O32-bit CTimer 0 match output 0R

I/O

reserved

FC2_SCL_SSEL1

I/O

flexcomm 2: I2C SCL, SPI SSEL1

RFE_RX_ENO

RX enable for external RF front-end

NTAG_
FD

37





O

field detection

VCC

38







power supply

NTAG_
VCC

39







NTAG power supply

VOUT

40







output supply voltage(energy harvesting)

VSS1

41







ground

QN9080-001-M17

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Table 5.

Pin description …continued

Symbol LFLGA54

Reset
state[1]Alternate function Type

Description

PA01

PU

GPIOA1

I/O

general-purpose digital input output pin

ADC1

AI

ADC external input 1

PA00

PA31

42

43

44

PU

PU

SCT0_OUT1OSCTimer output 1

CTIMER0_CAP1

I32-bit CTimer 0 capture input 1

FC0_CTS

I/O

flexcomm 0: USART CTS

FC2_SSEL2

I/O

flexcomm 2: SPI SSEL2

WLAN_RXI

WLAN active high RX active indicator for coexistence

GPIOA0I/O

general-purpose digital input output pin

ADC0

AI

ADC external input 0

SCT0_OUT0O

SCTimer output 0

CTIMER0_CAP0

I32-bit CTimer 0 capture input 0

FC0_RTS

I/O

flexcomm 0: USART RTS

FC2_SSEL3

I/O

flexcomm 2: SPI SSEL3

WLAN_TXI

WLAN active high TX active indicator for coexistence

GPIOA31

I/O

general-purpose digital input output pin

DAC

AO

DAC analog output

RTC_CAPI

RTC capture input

CTIMER3_MAT2

O

Timer 3 match output 2

SWO

I/O

serial wire trace output

FC3_SCK

I/O

flexcomm 3: SPI clock

SPIFI_CLKO

clock output for the SPI flash interface

GND

45







ground

GND

46







ground

GND

47







groundANT_Pi
n3

48







Internal antenna ground

ANT_Pi
n2

49







Internal antenna ground

ANT_Pi
n1

50







Internal antenna ground

GND

51







ground

GND

52







ground

GND

53







ground

GND

54







ground[1]

PU = input mode, pull-up enabled (pull-up resistor pulls up pin to VCC). Z = high impedance; pull-up or pull-down disabled, AI = analog
input, AO = analog output, I = input, O = output, F = floating. Reset state reflects the pin state at reset without boot code operation.

7.2.1 Termination of unused pins
Table 6 shows how to terminate pins that are not used in the application. In many cases,
unused pins should be connected externally or configured correctly by software tominimize the overall power consumption of the part.
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Unused pins with GPIO function should be configured as outputs LOW with their internal
pull-up disabled. To configure a GPIO pin as output and drive it LOW, select the GPIO
function in the IOCON register, select output in the GPIO DIR register, and write a 0 to the
GPIO PORT register for that pin. Disable the pull-up in the pin's IOCON register.
In addition, it is recommended to configure all GPIO pins that are not bonded out on
smaller packages as outputs driven LOW with their internal pull-up disabled.
Table 6.

Termination of unused pins

Pin

Default
state[1]Recommended termination of unused pins

RSTN

I; PU

the RSTN pin can be left unconnected if the application does
not use it.

all PAnm

I; PU

can be left unconnected if driven LOW and configured as
GPIO output with pull-up disabled by software

CHIP_MODE

I; PU

can be left unconnected if driven LOW and configured as
GPIO output with pull-up disabled by software[1]

I = Input, IA = Inactive (no pull-up/pull-down enabled), PU = Pull-Up enabled.

7.2.2 Pin states in different power modes
Table 7.
Pin

Pin states in different power modes
Active - Sleep - Power Down modes

all PAnm

As configured in the SYSCON[1]. Default: internal pull-up enabled.

RSTN

Reset function enabled. Default: input, internal pull-up enabled[1]

Default and programmed pin states are retained in sleep, and power-down mode.

8. Compliance statements and documentation• The FCC ID number of the QN9080-001-M17 is XXMQN9080M17• The IC ID number of the QN9080-001-M17 is 8764A-QN9080M17• The Japan ID number of the QN9080-001-M17 is207-990010

8.1 FCC Statements and documentation
This section contains the Federal Communication Commission (FCC) statements anddocuments.

8.1.1 FCC interference Statements• This equipment has been tested and found to comply with the limits for a Class B
digital device, pursuant to Part 15 of the FCC Rules. These limits are designed toprovide reasonable protection against harmful interference in a residential installation.
This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instructions, may cause harmfulinterference to radio communications. However, there is no guarantee thatinterference will not occur in a particular installation. If this equipment does cause
harmful interference to radio or television reception, which can be determined byturning the equipment off and on, the user is encouraged to try to correct theinterference by one of the following measures:
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QN9080-001-M17– Reorient or relocate the receiving antenna– Increase the separation between the equipment and receiver– Connect the equipment into an outlet on a circuit different from that to which thereceiver is connected– Consult the dealer or an experienced radio/TV technician for help

• OEM integrators instructions– The OEM integrators are responsible for ensuring that the end-user has no manual
instructions to remove or install SIP– The SIP is limited to installation in mobile or fixed applications, according to CFR
47 Part 2.1091(b)– Separate approval is required for all other operating configurations, including
portable configurations with respect to CFR 47 Part 2.1093 and different antennaconfigurations• User guide mandatory statements
User's instructions of the host device must contain the following statements in addition
to operation instructions:* "This device complies with part 15 of the FCC Rules. Operation is subject to thefollowing two conditions:(1) This device may not cause harmful interference, and(2) This device must accept any interference received, including interference that may
cause undesired operation"* "Changes or modifications not expressly approved by the party responsible forcompliance could void the user's authority to operate the equipment"• FCC RF Exposure requirements
User's instructions of the host device must contain the following instructions inaddition to operation instructions:
Avoid direct contact to the antenna, or keep it to a 20cm minimum distance while
using this equipment. This device must not be collocated or operating in conjunction
with another antenna or transmitter.
This SIP has been designed to operate etheir with internal antenna or with externalantennas having a maximum gain of 2 dBi. Antennas having a gain greater than 2 dBi arestrictly prohibited for use with this device. The required antenna impedance is 50 ohms

8.1.2 FCC end product labelling
The final 'end product' should be labelled in a visible area with the following:"Contains TX FCC ID: XXMQN9080M17 to reflect the SIP being used inside the product.

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8.2 Industry Canada Statement
This device complies with Industry Canada licence-exempt
RSS standard(s). Operation is subject to the following two
conditions: (1) this device may not cause interference, and(2) this device must accept any interference, includinginterference that may cause undesired operation of thedevice.

Le présent appareil est conforme aux CNR d'Industrie Canada
applicables aux appareils radio exempts de licence.
L'exploitation est autorisée aux deux conditions suivantes : (1)il ne doit pas produire de brouillage, et (2) l'utilisateur dudispositif doit être prêt à accepter tout brouillage
radioélectrique re?u, même si ce brouillage est susceptible decompromettre le fonctionnement du dispositif.

This device complies with Industry Canada RF radiation
exposure limits set forth for general population (uncontrolled Le présent appareil est conforme aux niveaux limites
d'exigences d'exposition RF aux personnes définies par
exposure). This device must be installed to provide aseparation distance of at least 20 cm from all persons and Industrie Canada. Cet appareil doit être installé afin d'offrir une
must not be collocated or operating in conjunction with any distance de séparation d'au moins 20 cm avec l'utilisateur, et
ne doit pas être installé à proximité ou être utilisé enother antenna or transmitter.
conjonction avec une autre antenne ou un autre émetteur.

To reduce potential radio interference to other users, the antenna type and its gain should
be so chosen that the equivalent isotropic radiated power (e.i.r.p.) is not more than that
permitted for successful communication.
The Gain of SIP with internal antenna is -3dBi.
If customer wants, he can also use the SIP with external antenna with maximum gain of
2dbi. This feature is not certified by NXP and need to be done by the customer. Antennas
having a gain greater than 2 dBi are strictly prohibited for use with this device. The
required antenna impedance is 50 ohms.
As long as the above condition is met, further transmitter testing will not be required.
However, the OEM integrator is still responsible for testing their end-product for any
additional compliance requirements required with this SIP installed (for example, digital
device emissions, PC peripheral requirements, etc.).

8.2.1 Industry of Canada end product labelling
For Industry Canada purposes the following should be used:"Contains Industry Canada ID IC: 8764A-QN9080M17

8.3 Japanese Radio Certification Statement
This equipment has been tested and found to comply with the Japanese Radio
Certification Rules

8.3.1 Radio Certification end product labelling
For Japanese Radio Certification purposes, the following should be used:"Contains Japanese Radio certificate product: Japan ID number is

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9. Static characteristics
9.1 General operating conditions
Table 8.
General operating conditions
Tamb = −40 °C to +85 °C, unless otherwise specified.
Typ[1]

SymbolParameter

Conditions

Min

fclk

Clock frequency







32

MHz

VCC

Supply voltage



1.67

3

3.6

V

VESD

Electrostatic discharge
voltage

Human body model[2]; all pins





2

kV

Charged device model; all pins





300

V







85

C

TJ(max)Maximum junction
temperature

Max

[1]

Typical ratings are not guaranteed. The values listed are for room temperature (25 °C), nominal supply voltages.

[2]

Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.

Unit

9.2 Power consumption
Power measurements in active, sleep, power down modes were performed under thefollowing conditions:• All peripherals disabled• Analog peripherals (ADC/DAC/ACMP/Capacitive Sense) powered down
• RF off• Internal 32 MHz HFRCO powered down
Table 9.
Static characteristics: Power consumption in active modes
Tamb = −40 °C to +85 °C, unless otherwise specified.
SymbolParameter

Conditions

Min

Typ[1]

Max

Unit



920



A

Typ[1][2]Max[3]

Unit



mA



mA

32 MHz HFXO; DC-DC converter enabled, VCC = 3.0 V
Supply current

ICC

CoreMark code executed from flash
CLK_AHB = 16 MHz

[2]

[1]

Typical ratings are not guaranteed. Typical values listed are at room temperature (25 °C).

[2]

Characterized through bench measurements using typical samples.

Table 10. Static characteristics: Bluetooth LE power consumption in active modes
Tamb = −40 °C to +85 °C, unless otherwise specified.
SymbolParameter

Conditions

Min

32 MHz crystal oscillator, CLK_AHB = 16 MHz, transmitter mode: fc = 2440 MHz, 1 Mbps mode
supply current

ICC

DC-to-DC converter enabled, Vcc = 3 V
Tx power = 0 dBm



3.5

32 MHz crystal oscillator, CLK_AHB = 16 MHz, transmitter mode: fc = 2440 MHz, 1 Mbps mode
supply current

ICC

DC-to-DC converter enabled, Vcc = 3 V-92.7 dBm RX sensitivity

[1]



4

Typical ratings are not guaranteed. Typical values listed are at room temperature (25 °C).

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Characterized through bench measurements using typical samples, with 50 loading on RF port.

[3]

Guaranteed by characterization, not tested in production.

Table 11. Static characteristics: Power consumption in sleep, and power-down modes
Tamb = −40 °C to +85 °C; unless otherwise specified.
Min

Typ[1][2]Max[3]

SymbolParameter

Conditions

Unit

ICC

Supply current

Sleep mode:
all SRAM on. Flash in standby mode. DC-to-DC converter enabled, Vcc = 3 V.
32 MHz crystal oscillator

CLK_AHB = 16 MHz



470

A

Power down mode; all clocks off.
Flash is powered down. DC-DC disabled, Vcc = 3 V. Tamb = 25 C.


8 KB SRAM powered



1.0

A

Power down mode; 32.768 kHz LFXO on.
Flash is powered down. DC-DC disabled, Vcc = 3 V. Tamb = 25 C.


8 KB SRAM powered[1]

Typical ratings are not guaranteed. Typical values listed are at room temperature (25 °C).

[2]

Characterized through bench measurements using typical samples.

[3]

Guaranteed by characterization, not tested in production.



2.5

A

9.3 Clock source
Table 12.

32 MHz clock source characteristics

SymbolParameter

Conditions

Min

Typ

Max

Unit

fnom

Nominal frequency





32



MHz

Frequency tolerance

at +25°C

-10



+10

ppm

CL

Load capacitance





10



pF

Rr

Equivalent resistance







60



Conditions

Min

Typ

Max

Unit

Table 13.

32.768 kHz clock source characteristics

SymbolParameter

fnom

Nominal frequency



32.768kHz

Frequency tolerance

at +253°C, Not
include aging

-20



+20

ppm

CL

Load capacitance





12.5



pF

Rr

Equivalent resistance







120

k

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10. RF characteristics
10.1 Receiver
Table 14. Receiver characteristics
Tamb = 25 °C; based on characterization; not tested in production. VCC = 3 V; fc = 2440 MHz; BER <0.1 %, 1 Mbps mod
SymbolSRXParameter

Conditions

Min

Typ

Max

Unit

RX sensitivity

low power mode with
DC-to-DC converter



92.7



dBm

Pi(max)maximum input
power



0



dBm

C/I[1]

co-channel
carrier-to-interfere
adjacent channel at 1 MHz 
nce ratio
alternate channel at2 MHz 

6



dB

4



dB

41



dB

image[1]out-of-band
suppression

[1]



41



dB

30 MHz to 2000 MHz

1





dBm

2003 MHz to 2399 MHz

10





dBm

2484 MHz to 2997 MHz

10





dBm

3 GHz to 12.75 GHz

10





dBm

image rejectionsup(oob)[1]

The values of these parameters are from QN9080 data sheet

10.2 Transmitter
Table 15. Transmitter characteristics
Tamb = 25 °C; based on QN9080 characterization; not tested in production.VCC = 3 V; fc = 2440 MHz
SymbolParameter

Conditions

Min

Typ

Max

fo(RF)

RF output
frequency



2400



2483.5 MHz

CSchannelseparation





2



MHz

Po

output power

TX power

20



+2

dBm





1



dB



2



+2

dB

Po(RF)step RF output powerstep
Po(acc)TX power
accuracy

Unit

Remark: The QN9080-001-M17 is a fully certified device supporting Bluetooth 5.0. Thereis a marginality (5% drift compare to the Min value of 185 kHz) on frequency deviation df2
99.9% at -40°C.

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11. Internal antenna characteristic
Table 16. BOD static characteristics
Tamb = 25 °C; based on characterization; not tested in production.

QN9080-001-M17

Objective data sheet

Parameter

Min

Typ

Max

Unit

Frequency range

2400



2480

MHz

Impedance



50





Peak gain



0.5



dBi

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12. Layout guideline
12.1 Footprint information for reflow solderingFig 5.

Footprint information for reflow soldering of SIPs

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QN9080-001-M17

12.2 Layout recommendation for ground plane implementation andclearance area for QN9080-001-M17 with integrated 2.4 GHz antenna

Physical View

Antenna Clearance
On EVB(mm)Module + Antenna
Clearance(mm)4.65
4Scenario#A(Center
Edge)

13.7
0.55
6.55
6.55

4 x 4.65 mm

13.7x 6.55 mm

7.5
3.75
13.45

Scenario#B(Corner)

7.5

7.5 x 3.75 mm
Fig 6.

13.45 x 7.5 mm

QN9080-001-M17 chip with integrated 2.4 GHz antenna / SIP clearance size (top view)

QN9080-001-M17

Objective data sheet

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12.2.1 Center edge PCB ground plane design

Integrated 2.4 GHz antenna function pin

9.7mm

Fig 7.

QN9080-001-M17 module on 36 mm x 31 mm PCB layout guide- center edge

• Do not route signal trace across antenna clearance area
• Connect pin 49 to Upper GND, pin 50 to lower GND

QN9080-001-M17

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Upper GND

ʊ10.5mm

Pin49

3.5mm

Trace
route

≥ 36mm

Pin50

Trace
route
0.55mm

Trace
route

Lower GND

≥ 31mm
QN9080-001-M17 module on 36 mm x 31 mm GND PCB layout guide - center edge - clearance area

A

G

B

C

Units : mm

A

1.25

B

2.9

C

5.5

D

0.38

E

0.55

G

0.5

F

0.25

H

0.5

I

3.5

H
I

Antenna Clearance Area
Parameter

Units : mm

Lower GND

D

Parameter

Upper GND

Fig 8.

E

F
Layer 1

Layer 1

Fig 9.

QN9080-001-M17 module on 36 mm x 31 mm GND PCB layout guide - center edge - clearance area layer 1
dimensions

QN9080-001-M17

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J
Antenna Clearance Area

L
K

Parameter

Units : mm

J

4.15

K

2

L

5.5

Layer 2,3,4
Fig 10.

QN9080-001-M17 module on 36 mm x 31 mm GND PCB layout guide - center edge - clearance area layers
2, 3, 4 dimensions

QN9080-001-M17

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12.2.2 Corner EVB ground plane design

Antenna Function Pin

9.7mm

6 mm
Fig 11. QN9080-001-M17 module on 36 mm x 31 mm PCB layout guide - corner• Do not route signal trace across antenna clearance area
• Connect pin 48 to antenna trace

QN9080-001-M17

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Ant. Trace

3.5mm

Trace
route
Trace
route

Pin48

≥ 31mm0.25mm

Trace
route

≥ 36mmLayer 1
Fig 12. QN9080-001-M17 module on 36 mm x 31 mm GND PCB layout guide - corner - clearance area

A

L
B

C D
Antenna Clearance Area
E

I
H

F
G

J
K

Parameter

Units : mm

A

0.5

B

4.34

C

0.5

D

M
O

Parameter

Units : mm

L

6.75

M

3.5

1

N

2

E

1.5

O

2.9

F

1.5

G

2

H

2.9

I

3.5

J

0.25

K

0.25

Layer 1N

Layer 1

Fig 13. QN9080-001-M17 module on 36 mm x 31 mm GND PCB layout guide - corner - clearance area layer 1
dimensions

QN9080-001-M17

Objective data sheet

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P
Antenna Clearance Area
RS

Q

Parameter

Units : mm

P

6.75

Q

2

R

2.9

S

5.5

Layer 2,3,4
Fig 14.

QN9080-001-M17 module on 36 mm x 31 mm GND PCB layout guide - corner - clearance area layers 2, 3,
4 dimensions

12.3 Reflow profile
QN9080-001-M17 is an MSL3 and PSL R5G product. PSL has been defined based on thestandard J-STD-075. For reflow soldering, it is requested to follow the reflow profile andthe paste manufacturer's guidelines on peak flow temperature, soak times, time above
liquid and ramp rates.
Table 17.

Recommended solder reflow profile
Temperature range

Time

Peak temperature: 255 C

10 s Max.

Heating: 230 C or higher

30 s Max.

Preheating: 150 C to 180 C

60-120 s

12.4 Soldering paste and cleaning
NXP does not recommend to use a solder paste that requires the module and PCB
assembly to be cleaned (rinsed in water) for the following reasons:• Solder flux residues and water can be trapped by the PCB, can or components andresult in short circuits
NXP recommends to use a 'no clean' solder paste for all its module products.

QN9080-001-M17

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13. Package outline

Fig 15. Package outline LFLGA54 (SOT1910-1)

QN9080-001-M17

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14. Abbreviations
Table 18.

Abbreviations

AcronymDescription

ADC

Analog to Digital Converter

AES

Advanced Encryption Standard

API

Application Program Interface

CLK

CLocK

CRC

Cyclic redundancy Check

CTS

Clear-To-Send

DC

Direct current

DIO

Digital Input Output

DMA

Direct memory Access

EEPROM

Electrically-Erasable Programmable Read Only Memory

FIFO

First In First Out

GPIO

General Purpose Input Output

ID

IDentification

IF

Intermediate frequency

IO

Input Output

MSL

Moisture sensitivity level

NVIC

Nested Vector Interrupt Controller

PCB

Printed-Circuit Board

PHY

PHYsical

POR

Power-On Reset

PWM

Pulse Width Modulation

RAM

Random Access Memory

RC

Remote Control

RFRadio Frequency

RoHS

Restriction of Hazardous Substances

RSSI

Receive Signal Strength Indication

RTS

Request-To-Send

RX

Received

SCL

Serial CLock

SDA

Serial DatA

SMDs

Surface Mount Devices

SPI-busSerial Peripheral Interface -bus

SysTick

System Tick timer

TX

Transmit

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15. References

QN9080-001-M17

Objective data sheet[1]

IEEE Std 802.15.4-2011 IEEE Standard for Information Technology Part 15.4 —Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications
for Low-Rate Wireless Personal Area Networks (LR-WPANs).

[2]

Wireless Connectivity —http://www.nxp.com/products/wireless-connectivity:WIRELESS-CONNECTIVITY

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16. Revision history
Table 19.

Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

QN9080-001-M17 v1.0

20181205

Objective data sheet

Public release-

QN9080-001-M17

Objective data sheet

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17. Legal information
17.1 Data sheet status
Document status[1][2]Product status[3]Definition

Objective [short] data sheet

Development

This document contains data from the objective specification for product development.

Preliminary [short] data sheet

Qualification

This document contains data from the preliminary specification.

Product [short] data sheet

Production

This document contains the product specification.

[1]

Please consult the most recently issued document before initiating or completing a design.

[2]

The term ‘short data sheet’ is explained in section “Definitions”.

[3]

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.

17.2 Definitions
Draft — The document is a draft version only. The content is still underinternal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences ofuse of such information.
Short data sheet — A short data sheet is an extract from a full data sheetwith the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed andfull information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, thefull data sheet shall prevail.
Product specification — The information and data provided in a Productdata sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors andcustomer have explicitly agreed otherwise in writing. In no event however,shall an agreement be valid in which the NXP Semiconductors product isdeemed to offer functions and qualities beyond those described in the
Product data sheet.

17.3 Disclaimers
Limited warranty and liability — Information in this document is believed tobe accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy orcompleteness of such information and shall have no liability for theconsequences of use of such information. NXP Semiconductors takes noresponsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not suchdamages are based on tort (including negligence), warranty, breach ofcontract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordancewith the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to makechanges to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.

QN9080-001-M17

Objective data sheet

Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical orsafety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability forinclusion and/or use of NXP Semiconductors products in such equipment orapplications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. NXP Semiconductors makes norepresentation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer productdesign. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications andproducts planned, as well as for the planned application and use ofcustomer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with theirapplications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in thecustomer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications andthe products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or theCharacteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects toapplying the customer’s general terms and conditions with regard to thepurchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted orconstrued as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents orother industrial or intellectual property rights.

All information provided in this document is subject to legal disclaimers.

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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a priorauthorization from competent authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of thisdocument, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use inautomotive applications to automotive specifications and standards, customer(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design anduse of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is forreference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.

17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP Semiconductors N.V.

18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com

QN9080-001-M17

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19. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.

Ordering information . . . . . . . . . . . . . . . . . . . . .5
Ordering options . . . . . . . . . . . . . . . . . . . . . . . .6
Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .6
Device revision table. . . . . . . . . . . . . . . . . . . . . .6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .9
Termination of unused pins. . . . . . . . . . . . . . . .17
Pin states in different power modes . . . . . . . . .17
General operating conditions . . . . . . . . . . . . . .20
Static characteristics: Power consumption in
active modes. . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 10. Static characteristics: Bluetooth LE power

consumption in active modes. . . . . . . . . . . . . . 20
Table 11. Static characteristics: Power consumption insleep, and power-down modes . . . . . . . . . . . . 21
Table 12. 32 MHz clock source characteristics . . . . . . . . 21
Table 13. 32.768 kHz clock source characteristics . . . . . 21
Table 14. Receiver characteristics . . . . . . . . . . . . . . . . . . 22
Table 15. Transmitter characteristics . . . . . . . . . . . . . . . . 22
Table 16. BOD static characteristics . . . . . . . . . . . . . . . . 23
Table 17. Recommended solder reflow profile. . . . . . . . . 31
Table 18. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 19. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 35

20. Figures
Fig 1.
Fig 2.
Fig 3.

QN9080-001-M17 package marking . . . . . . . . . . .6
QN9080-001-M17 – high level HW block diagram7
QN9080-001-M17 block diagram using externalantenna . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Fig 4. QN9080-001-M17 pinout diagram . . . . . . . . . . . . .9
Fig 5. Footprint information for reflow soldering of SIPs 24
Fig 6. QN9080-001-M17 chip with integrated 2.4 GHz
antenna / SIP clearance size (top view). . . . . . . .25
Fig 7. QN9080-001-M17 module on 36 mm x 31 mm PCB
layout guide- center edge . . . . . . . . . . . . . . . . . .26
Fig 8. QN9080-001-M17 module on 36 mm x 31 mm GND
PCB layout guide - center edge - clearance area 27
Fig 9. QN9080-001-M17 module on 36 mm x 31 mm GND
PCB layout guide - center edge - clearance area
layer 1 dimensions . . . . . . . . . . . . . . . . . . . . . . .27
Fig 10. QN9080-001-M17 module on 36 mm x 31 mm GND

QN9080-001-M17

Objective data sheet

Fig 11.
Fig 12.
Fig 13.

Fig 14.

Fig 15.

PCB layout guide - center edge - clearance area
layers 2, 3, 4 dimensions. . . . . . . . . . . . . . . . . . . 28
QN9080-001-M17 module on 36 mm x 31 mm PCB
layout guide - corner . . . . . . . . . . . . . . . . . . . . . . 29
QN9080-001-M17 module on 36 mm x 31 mm GND
PCB layout guide - corner - clearance area . . . . 30
QN9080-001-M17 module on 36 mm x 31 mm GND
PCB layout guide - corner - clearance area layer 1
dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
QN9080-001-M17 module on 36 mm x 31 mm GND
PCB layout guide - corner - clearance area layers 2,
3, 4 dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Package outline LFLGA54 (SOT1910-1) . . . . . . 32

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21. Contents
1
2
2.1
2.2
2.3
3
4
5
6
7
7.1
7.2
7.2.1
7.2.2
8
8.1
8.1.1
8.1.2
8.2
8.2.1
8.3
8.3.1
9
9.1
9.2
9.3
10

General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Feature of QN9080 . . . . . . . . . . . . . . . . . . . . . . 2
Features of NTAG. . . . . . . . . . . . . . . . . . . . . . . 4
Features of integrated 2.4 GHz antenna . . . . . 5
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Ordering information . . . . . . . . . . . . . . . . . . . . . 5
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pinning information . . . . . . . . . . . . . . . . . . . . . . 9
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9
Termination of unused pins. . . . . . . . . . . . . . . 16
Pin states in different power modes . . . . . . . . 17
Compliance statements and documentation 17
FCC Statements and documentation . . . . . . . 17
FCC interference Statements . . . . . . . . . . . . . 17
FCC end product labelling . . . . . . . . . . . . . . . 18
Industry Canada Statement . . . . . . . . . . . . . . 19
. . . . Industry of Canada end product labelling 19
Japanese Radio Certification Statement . . . . 19
Radio Certification end product labelling . . . . 19
Static characteristics. . . . . . . . . . . . . . . . . . . . 20
General operating conditions . . . . . . . . . . . . . 20
Power consumption . . . . . . . . . . . . . . . . . . . . 20
Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . 21
RF characteristics . . . . . . . . . . . . . . . . . . . . . . 22

10.1
10.2
11
12
12.1
12.2

Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal antenna characteristic . . . . . . . . . . .
Layout guideline . . . . . . . . . . . . . . . . . . . . . . .
Footprint information for reflow soldering. . . .
Layout recommendation for ground plane
implementation and clearance area for
QN9080-001-M17 with integrated 2.4 GHz
antenna . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.1
Center edge PCB ground plane design . . . . .
12.2.2
Corner EVB ground plane design . . . . . . . . .
12.3
Reflow profile . . . . . . . . . . . . . . . . . . . . . . . . .
12.4
Soldering paste and cleaning. . . . . . . . . . . . .
13Package outline . . . . . . . . . . . . . . . . . . . . . . . .
14Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
15
References . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
Revision history . . . . . . . . . . . . . . . . . . . . . . .
17
Legal information . . . . . . . . . . . . . . . . . . . . . .
17.1
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
17.2
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.3
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
18
Contact information . . . . . . . . . . . . . . . . . . . .
19
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

22
22
23
24
24

25
26
29
31
31
32
33
34
35
36
36
36
36
37
37
38
38
39

Please be aware that important notices concerning this document and the product(s)described herein, have been included in section ‘Legal information’.

© NXP Semiconductors B.V. 2018.

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Date of release: 5 December 2018
Document identifier: QN9080-001-M17