参考資料
SN6501-Q1
JAJSK49C – JUNE 2013 – REVISED MARCH 2021

SN6501-Q1 絶縁電源用のトランス・ドライバ
1 特長

3 説明

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SN6501-Q1 は、絶縁型インターフェイス・アプリケーショ
ンで使用される小型の絶縁型電源向けに設計された、モノリシックな発振器 / 電源ドライバです。3.3V または 5V のDC 電源から、低背のセンター・タップ付きトランスの 1 次側を駆動します。2 次側は、トランスの巻数比に基づいて任意の絶縁電圧に設定できます。

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車載アプリケーション向けに認定済み
下記内容で AEC-Q100 認定済み
– デバイス温度グレード 1：-40℃～125℃の周囲動
作温度範囲– デバイス HBM ESD 分類レベル H2– デバイス CDM ESD 分類レベル C4B
機能安全対応– 機能安全システムの設計に役立つ資料を利用可
能小型トランス用のプッシュプル・ドライバ
3.3V または 5V のシングル電源
1 次側大電流駆動：– 5V 電源：350mA (最大値)– 3.3V 電源：150mA (最大値)
整流出力のリップルが小さいため、小型の出力コンデンサを使用可能小型の 5 ピン SOT-23 パッケージ

SN6501-Q1 は、発振回路に続いて、グランド基準の N
チャネル電源スイッチを駆動するための相補型出力信号を供給するゲート駆動回路を搭載しています。内部ロジッ
クにより、2 つのスイッチ間で Break-Before-Make 動作が保証されます。
SN6501-Q1 は小型の SOT-23 (5) パッケージで供給され、-40℃～125℃の温度範囲で動作が規定されています。
デバイス情報部品番号(1)2 アプリケーション

SN6501-Q1

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(1)

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CAN、RS-485、RS-422、RS-232、SPI、I2C、低消費
電力 LAN 用の絶縁インターフェイス電源
産業用オートメーション
プロセス制御
医療用機器

パッケージ

本体サイズ (公称)SOT-23 (5)2.90mm × 1.60mm

利用可能なすべてのパッケージについては、このデータシートの末尾にある注文情報を参照してください。

簡略回路図

出力電圧および効率と出力電流との関係

英語版の TI 製品についての情報を翻訳したこの資料は、製品の概要を確認する目的で便宜的に提供しているものです。該当する正式な英語版の最新情報は、
www.ti.com で閲覧でき、その内容が常に優先されます。TI では翻訳の正確性および妥当性につきましては一切保証いたしません。実際の設計などの前には、必ず最新版の英語版をご参照くださいますようお願いいたします。

English Data Sheet: SLLSEF3

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Table of Contents
1 特長................................................................................... 1
2 アプリケーション...................................................................1
3 説明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 Handling Ratings.........................................................4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................5
6.7 Typical Characteristics................................................ 6
7 Parameter Measurement Information.......................... 11
8 Detailed Description......................................................12
8.1 Overview................................................................... 12
8.2 Functional Block Diagram......................................... 12

8.3 Feature Description...................................................12
8.4 Device Functional Modes..........................................13
9 Application and Implementation.................................. 14
9.1 Application Information............................................. 14
9.2 Typical Application.................................................... 15
10 Power Supply Recommendations..............................27
11 Layout........................................................................... 28
11.1 Layout Guidelines................................................... 28
11.2 Layout Example...................................................... 28
12 Device and Documentation Support..........................29
12.1 Device Support....................................................... 29
12.2 Trademarks............................................................. 29
12.3 静電気放電に関する注意事項.................................. 29
12.4 用語集..................................................................... 29
13 Mechanical, Packaging, and Orderable
Information.................................................................... 29

4 Revision History
資料番号末尾の英字は改訂を表しています。その改訂履歴は英語版に準じています。
Changes from Revision B (October 2020 ) to Revision C (March 2021)
Page• Added a short-circuit protection note to SN6501 Drive Capability ...................................................................15• Changed 式 4 ...................................................................................................................................................18• Removed duplicate equation labeled as (5) in Revision B............................................................................... 18• Added 17 line items to Recommended Isolation Transformers Optimized for SN6501 ...................................20

Changes from Revision A (September 2014) to Revision B (October 2020)•

Changes from Revision * (June 2013) to Revision A (September 2014)
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2

Page

機能安全の箇条書き項目を追加...........................................................................................................................1
Page「ピン構成および機能」セクション、「取り扱いに関する定格」の表、「機能説明」セクション、「デバイスの機能モード」セ
クション、「アプリケーションと実装」セクション、「電源に関する推奨事項」セクション、「レイアウト」セクション、「デバイスおよびドキュメントのサポート」セクション、「メカニカル、パッケージ、および注文情報」セクションを追加 .................... 1
Changed 式 10 .................................................................................................................................................18
Changed 式 11 .................................................................................................................................................18
Changed 表 9-4, From: Wuerth-Elektronik / Midcom To: Wurth Electronics Midcom Inc..................................22
Changed 図 9-16 ............................................................................................................................................. 22

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5 Pin Configuration and Functions
D1

1

VCC

2

D2

3

5

GND

4

GND

図 5-1. 5-Pin SOT-23 DBV Package Top View
表 5-1. Pin FunctionsPIN

DESCRIPTIONNAMENUMBER

TYPE

D1

1

OD

Open Drain output 1. Connect this pin to one end of the transformer primary side.

VCC

2

P

Supply voltage input. Connect this pin to the center-tap of the transformer primary side. Buffer thisvoltage with a 1 μF to 10 μF ceramic capacitor.

D2

3

OD

Open Drain output 2. Connect this pin to the other end of the transformer primary side.

GND

4,5

P

Device ground. Connect this pin to board ground.

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VCC

Supply voltage

VD1, VD2

Output switch voltage

MIN

MAX

UNIT

–0.3

6

V

14

V

ID1P, ID2P Peak output switch current

500

mA

PTOT

Continuous power dissipation

250

mW

TJ

Junction temperature

170

°C

(1)

Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions beyond those indicated under セクション 6.3 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods affects device reliability.

6.2 Handling Ratings
Tstg

Storage temperature range

V(ESD)

4

Electrostatic
discharge

MIN

MAX

UNIT

–65

150

°C

Human body model (HBM) AEC-Q100 Classification Level H2, all pins

–2

2

kV

Charged device model (CDM) AEC-Q100 Classification Level C4B, all pins

–750

750

V

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6.3 Recommended Operating Conditions
MIN
VCC

Supply voltage

VD1, VD2

Output switch voltage

ID1, ID2

D1 and D2 output switch
current – Primary-side

TA

VCC = 5 V ± 10%,VCC = 3.3 V ± 10%

When connected to Transformer withprimary winding Center-tapped

TYP

MAX

UNIT

3

5.5

V

0

11

0

7.2

VCC = 5 V ± 10%

VD1, VD2 Swing ≥ 3.8 V,
see 図 6-32 for typical characteristics

350

VCC = 3.3 V ± 10%

VD1, VD2 Swing ≥ 2.5 V,
see 図 6-31 for typical characteristics

150

Ambient temperature

V

mA

–40

125

°C

6.4 Thermal Information
THERMAL METRIC(1)SN6501θJA

Junction-to-ambient thermal resistance

208.3

θJCtopJunction-to-case (top) thermal resistance

87.1

θJB

Junction-to-board thermal resistance

40.4

ψJT

Junction-to-top characterization parameter

5.2

ψJB

Junction-to-board characterization parameter

39.7

θJCbotJunction-to-case (bottom) thermal resistance

N/A

(1)

UNIT

DBV 5-PINS°C/W

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).

6.5 Electrical Characteristics
over full-range of recommended operating conditions, unless otherwise noted
PARAMETER
RON

Switch-on resistance

ICC

Average supply current(1)fST

Startup frequency

fSW
(1)

D1, D2 Switching frequency

TYP

MAX

VCC = 3.3 V ± 10%, See 図 7-4

TEST CONDITIONS

MIN

1

3

VCC = 5 V ± 10%, See 図 7-4

0.62

VCC = 3.3 V ± 10%, no load

150

400

VCC = 5 V ± 10%, no load

300

700

300

VCC = 2.4 V, See 図 7-4

UNIT
Ω
µA
kHz

VCC = 3.3 V ± 10%, See 図 7-4

250

360

495

VCC = 5 V ± 10%, See 図 7-4

300

410

620

MIN

TYP

MAX

kHz

Average supply current is the current used by SN6501 only. It does not include load current.

6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
tr-D
tf-D
tBBM

D1, D2 output rise time

D1, D2 output fall time

Break-before-make time

TEST CONDITIONSVCC = 3.3 V ± 10%, See 図 7-4

70

VCC = 5 V ± 10%, See 図 7-4

80

VCC = 3.3 V ± 10%, See 図 7-4

110

VCC = 5 V ± 10%, See 図 7-4

60

VCC = 3.3 V ± 10%, See 図 7-4

150

VCC = 5 V ± 10%, See 図 7-4

50

UNIT

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6.7 Typical Characteristics
TP1 Curves are measured with the Circuit in 図 7-1; whereas, TP1 and TP2 Curves are measured with Circuit in
図 7-3 (TA = 25°C unless otherwise noted). See 表 9-3 for Transformer Specifications.
90
80

5

TP1

70

Efficiency - %VOUT - V

4
TP1

3
2

0

0

50
40
30
20

T1 = 760390011 (2.5kV)
VIN = 3.3V, VOUT = 3.3V

160

T1 = 760390011 (2.5kV)
VIN = 3.3V, VOUT = 3.3V

100

10 20 30 40 50 60 70 80 90 100

0ILOAD - mA

図 6-1. Output Voltage vs Load Current

ILOAD - mA

図 6-2. Efficiency vs Load Current
90

6
TP1

80

5

Efficiency - %70

VOUT - V

4
3
2

0

TP1

60
50
40
30
20

T1 = 760390012 (2.5kV)
VIN = 5V, VOUT = 5V

10

T1 = 760390012 (2.5kV)
VIN = 5V, VOUT = 5V

100

10 20 30 40 50 60 70 80 90 100

0ILOAD - mA

図 6-3. Output Voltage vs. Load Current

図 6-4. Efficiency vs Load Current
90

TP1

80

5
Efficiency - %VOUT - V

TP1

70

4
3
2

60
50
40
30
20

T1 = 760390013 (2.5kV)
VIN = 3.3V, VOUT = 5V

1

T1 = 760390013 (2.5kV)
VIN = 3.3V, VOUT = 5V

10
0

0

10 20 30 40 50 60 70 80 90 100
ILOAD - mA

図 6-5. Output Voltage vs Load Current

6

10 20 30 40 50 60 70 80 90 100
ILOAD - mA

6

0

10 20 30 40 50 60 70 80 90 100

010 20 30 40 50 60 70 80 90 100
ILOAD - mA

図 6-6. Efficiency vs Load Current

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90

5
TP1

3

Efficiency - %VOUT - V

4
TP2

2

0

0

TP1

70

TP2

60
50
40
30
20

T1 = 760390014 (2.5kV)
VIN = 3.3V, VOUT = 3.3V

180

T1 = 760390014 (2.5kV)
VIN = 3.3V, VOUT = 3.3V

100

10 20 30 40 50 60 70 80 90 100

0ILOAD - mA

図 6-7. Output Voltage vs Load Current

10 20 30 40 50 60 70 80 90 100
ILOAD - mA

図 6-8. Efficiency vs Load Current

8

90

7

80

TP1

TP1

70

5

Efficiency - %VOUT - V

6
TP2

4
3
2

50
40
30
20

T1 = 760390014 (2.5kV)
VIN = 5V, VOUT = 5V

1
0

TP2

60

0

T1 = 760390014 (2.5kV)
VIN = 5V, VOUT = 5V

100

10 20 30 40 50 60 70 80 90 100
ILOAD - mA

図 6-9. Output Voltage vs Load Current

0

10 20 30 40 50 60 70 80 90 100
ILOAD - mA

図 6-10. Efficiency vs Load Current

7
TP1

VOUT - V

6
5

TP2

4
3
2
T1 = 760390015 (2.5kV)
VIN = 3.3V, VOUT = 5V

1
00

10 20 30 40 50 60 70 80 90 100
ILOAD - mA

図 6-11. Output Voltage vs Load Current

図 6-12. Efficiency vs Load Current
90
80

5

TP1

TP1

3

TP2

Efficiency - %VOUT - V

70
4

2

0

0

50
40
30
20

T1 = 750313710 (2.5kV)
VIN = 5V, VOUT = 3.3V

1

TP2

60

T1 = 750313710 (2.5kV)
VIN = 5V, VOUT = 3.3V

10

10 20 30 40 50 60 70 80 90 100

0ILOAD - mA

図 6-13. Output Voltage vs Load Current

0

10 20 30 40 50 60 70 80 90 100
ILOAD - mA

図 6-14. Efficiency vs Load Current

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6

90
80

5

TP1

70
Efficiency - %VOUT - V

4
TP1

3
2
T1 = 750313734 (5kV)
VIN = 3.3V, VOUT = 3.3V

1
0

10 20 30 40 50 60 70 80 90 10030

0T1 = 750313734 (5kV)
VIN = 3.3V, VOUT = 3.3V

0

10 20 30 40 50 60 70 80 90 100

図 6-16. Efficiency vs Load Current

6

90
TP1

80

5
Efficiency - %704VOUT - V40100

図 6-15. Output Voltage vs Load Current

3
2

50
40
30
T1 = 750313734 (5kV)
VIN = 5V, VOUT = 5V

10
0

0

TP1

60

20

T1 = 750313734 (5kV)
VIN = 5V, VOUT = 5V

1

10 20 30 40 50 60 70 80 90 100
ILOAD - mA0

10 20 30 40 50 60 70 80 90 100
ILOAD - mA

図 6-17. Output Voltage vs Load Current

図 6-18. Efficiency vs Load Current

図 6-19. Output Voltage vs Load Current

図 6-20. Efficiency vs Load Current
90

6Efficiency - %4VOUT - V

TP2

70
TP1

3

TP2

2

60
50
40
30
20

1
0

TP1

80

5

T1 = 750313638 (5kV)
VIN = 3.3V, VOUT = 3.3V

0

T1 = 750313638 (5kV)
VIN = 3.3V, VOUT = 3.3V

10

10 20 30 40 50 60 70 80 90 100
ILOAD - mA

図 6-21. Output Voltage vs Load Current
8

50

20

ILOAD - mA

0

60

0

0

10 20 30 40 50 60 70 80 90 100
ILOAD - mA

図 6-22. Efficiency vs Load Current

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90

8

80

7
TP1

VOUT - V

Efficiency - %

6
5

TP2

4
3
2

50
40
30

0

0

10 20 30 40 50 60 70 80 90 100

010 20 30 40 50 60 70 80 90 100
ILOAD - mA

図 6-23. Output Voltage vs Load Current

図 6-24. Efficiency vs Load Current
90

8

80

7

TP1

70

TP1

6

TP2

60

5

TP2

50

4

40

3

30

2

20
T1 = 750313626 (5kV)
VIN = 3.3V, VOUT = 5V

10

T1 = 750313638 (5kV)
VIN = 5V, VOUT = 5V

10

ILOAD - mA

VOUT - V

TP2

60

20
T1 = 750313638 (5kV)
VIN = 5V, VOUT = 5V

1
0

TP1

70

0

T1 = 750313626 (5kV)
VIN = 3.3V, VOUT = 5V

100

10 20 30 40 50 60 70 80 90 100

010 20 30 40 50 60 70 80 90 100
ILOAD - mA

ILOAD - mA

図 6-26. Efficiency vs Load Current

図 6-25. Output Voltage vs Load Current

90

6

80

5

TP1

TP1

3

TP2

Efficiency - %VOUT - V

70
4

2
1
0

50
40
30
20

T1 = 750313638 (5kV)
VIN = 5V, VOUT = 3.3V

0

T1 = 750313638 (5kV)
VIN = 5V, VOUT = 3.3V

10

10 20 30 40 50 60 70 80 90 100
ILOAD - mA

図 6-27. Output Voltage vs Load Current

00

10 20 30 40 50 60 70 80 90 100

図 6-28. Efficiency vs Load Current
460

350
300

440

VCC = 5V

f - Frequency - kHz

ICC – Supply Current - µA

TP2

60

250
200
150

VCC = 3.3V

100
50

VCC = 5V

420
400
380

VCC = 3.3V

360
340

0
-55 -35 -15

5

25

45

65

85 105 125320-55 -35 -15oTA - Free Air Temperature - C

図 6-29. Average Supply Current vs Free-Air
Temperature

5

25

45

65

85 105 125

TA - Free Air Temperature - oC

図 6-30. D1, D2 Switching Frequency vs Free-Air
Temperature
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5.00

VD1, VD2 - Voltage Swing - V

VD1, VD2 - Voltage Swing - V

3.30
3.25
VCC = 3.3V

3.20
3.15
3.10
3.05
3.00
0

50

100

150

200

4.95

VCC = 5V

4.90
4.85
4.80
4.75
4.70
4.65
4.60
4.55

ID1, ID2 - Switching Current - mA

0

100

200

300

400

ID1, ID2 - Switching Current - mA

図 6-31. D1, D2 Primary-Side Output Switch Voltage 図 6-32. D1, D2 Primary-Side Output Switch Voltage
Swing vs Current
Swing vs Current

10

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7 Parameter Measurement Information
7.1

図 7-2. Timing Diagram
図 7-1. Measurement Circuit for Unregulated
Output (TP1)

図 7-3. Measurement Circuit for regulated Output (TP1 and TP2)

図 7-4. Test Circuit For RON, FSW, FSt, Tr-D, Tf-D, TBBM

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8 Detailed Description
8.1 Overview
The SN6501-Q1 is a transformer driver designed for low-cost, small form-factor, isolated DC-DC converters
utilizing the push-pull topology. The device includes an oscillator that feeds a gate-drive circuit. The gate-drive,
comprising a frequency divider and a break-before-make (BBM) logic, provides two complementary output
signals which alternately turn the two output transistors on and off.
The output frequency of the oscillator is divided down by an asynchronous divider that provides twocomplementary output signals with a 50% duty cycle. A subsequent break-before-make logic inserts a dead-time
between the high-pulses of the two signals. The resulting output signals, present the gate-drive signals for the
output transistors. As shown in the functional block diagram, before either one of the gates can assume logic
high, there must be a short time period during which both signals are low and both transistors are highimpedance. This short period, known as break-before-make time, is required to avoid shorting out both ends ofthe primary.

8.2 Functional Block Diagram

8.3 Feature Description
8.3.1 Push-Pull Converter
Push-pull converters require transformers with center-taps to transfer power from the primary to the secondary(see 図 8-1).
CR1

C
VIN

CR1

VOUT

C

RL

RL

VIN

CR2
Q2

VOUT

Q1

CR2
Q2

Q1

図 8-1. Switching Cycles of a Push-Pull Converter
When Q1 conducts, VIN drives a current through the lower half of the primary to ground, thus creating a negative
voltage potential at the lower primary end with regards to the VIN potential at the center-tap.
At the same time the voltage across the upper half of the primary is such that the upper primary end is positive
with regards to the center-tap in order to maintain the previously established current flow through Q2, which now
has turned high-impedance. The two voltage sources, each of which equaling VIN, appear in series and cause a
voltage potential at the open end of the primary of 2×VIN with regards to ground.

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Per dot convention the same voltage polarities that occur at the primary also occur at the secondary. The
positive potential of the upper secondary end therefore forward biases diode CR1. The secondary current
starting from the upper secondary end flows through CR1, charges capacitor C, and returns through the load
impedance RL back to the center-tap.
When Q2 conducts, Q1 goes high-impedance and the voltage polarities at the primary and secondary reverse.
Now the lower end of the primary presents the open end with a 2×VIN potential against ground. In this case CR2
is forward biased while CR1 is reverse biased and current flows from the lower secondary end through CR2,
charging the capacitor and returning through the load to the center-tap.
8.3.2 Core Magnetization
図 8-2 shows the ideal magnetizing curve for a push-pull converter with B as the magnetic flux density and H as
the magnetic field strength. When Q1 conducts the magnetic flux is pushed from A to A’, and when Q2 conducts
the flux is pulled back from A’ to A. The difference in flux and thus in flux density is proportional to the product ofthe primary voltage, VP, and the time, tON, it is applied to the primary: B ≈ VP × tON.
B
VIN

A’

VP

H
RDS

VDS

A
VIN = VP + VDS

図 8-2. Core Magnetization and Self-Regulation Through Positive Temperature Coefficient of RDS(on)This volt-seconds (V-t) product is important as it determines the core magnetization during each switching cycle.
If the V-t products of both phases are not identical, an imbalance in flux density swing results with an offset fromthe origin of the B-H curve. If balance is not restored, the offset increases with each following cycle and thetransformer slowly creeps toward the saturation region.
Fortunately, due to the positive temperature coefficient of a MOSFET’s on-resistance, the output FETs of theSN6501 have a self-correcting effect on V-t imbalance. In the case of a slightly longer on-time, the prolonged
current flow through a FET gradually heats the transistor which leads to an increase in RDS-on. The higher
resistance then causes the drain-source voltage, VDS, to rise. Because the voltage at the primary is thedifference between the constant input voltage, VIN, and the voltage drop across the MOSFET, VP = VIN – VDS, VP
is gradually reduced and V-t balance restored.

8.4 Device Functional Modes
The functional modes of the SN6501 are divided into start-up, operating, and off-mode.
8.4.1 Start-Up Mode
When the supply voltage at Vcc ramps up to 2.4V typical, the internal oscillator starts operating at a startfrequency of 300 kHz. The output stage begins switching but the amplitude of the drain signals at D1 and D2 has
not reached its full maximum yet.
8.4.2 Operating Mode
When the device supply has reached its nominal value ±10% the oscillator is fully operating. However variations
over supply voltage and operating temperature can vary the switching frequencies at D1 and D2 between 250
kHz and 495 kHz for VCC = 3.3 V ±10%, and between 300 kHz and 620 kHz for VCC = 5 V ±10%.
8.4.3 Off-Mode
The SN6501 is deactivated by reducing VCC to 0 V. In this state both drain outputs, D1 and D2, are highimpedance.
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9 Application and Implementation
注Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI ’ s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.

9.1 Application Information
The SN6501-Q1 is a transformer driver designed for low-cost, small form-factor, isolated DC-DC converters
utilizing the push-pull topology. The device includes an oscillator that feeds a gate-drive circuit. The gate-drive,
comprising a frequency divider and a break-before-make (BBM) logic, provides two complementary output
signals which alternately turn the two output transistors on and off.

図 9-1. SN6501-Q1 Block Diagram
The output frequency of the oscillator is divided down by an asynchronous divider that provides twocomplementary output signals, S and S, with a 50% duty cycle. A subsequent break-before-make logic inserts adead-time between the high-pulses of the two signals. The resulting output signals, G1 and G2, present the gatedrive signals for the output transistors Q 1 and Q2. As shown in 図 9-2, before either one of the gates can assume
logic high, there must be a short time period during which both signals are low and both transistors are highimpedance. This short period, known as break-before-make time, is required to avoid shorting out both ends ofthe primary.
fOSC
S

S
G1
G2
Q1
Q2

図 9-2. Detailed Output Signal Waveforms

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9.2 Typical Application

図 9-3. Typical Application Schematic (SN6501-Q1)
9.2.1 Design Requirements
For this design example, use the parameters listed in 表 9-1 as design parameters.
表 9-1. Design Parameters
DESIGN PARAMETER

EXAMPLE VALUE

Input voltage range

3.3 V ± 3%

Output voltage

5V

Maximum load current

100 mA

9.2.2 Detailed Design Procedure
The following recommendations on components selection focus on the design of an efficient push-pull converterwith high current drive capability. Contrary to popular belief, the output voltage of the unregulated converter
output drops significantly over a wide range in load current. The characteristic curve in 図 6-11 for example
shows that the difference between VOUT at minimum load and VOUT at maximum load exceeds a transceiver’s
supply range. Therefore, in order to provide a stable, load independent supply while maintaining maximum
possible efficiency the implementation of a low dropout regulator (LDO) is strongly advised.
The final converter circuit is shown in 図 9-7. The measured VOUT and efficiency characteristics for the regulated
and unregulated outputs are shown in 図 6-1 to 図 6-28.
9.2.2.1 SN6501 Drive Capability
The SN6501 transformer driver is designed for low-power push-pull converters with input and output voltages in
the range of 3 V to 5.5 V. While converter designs with higher output voltages are possible, care must be takenthat higher turns ratios don’t lead to primary currents that exceed the SN6501 specified current limits.
Unlike SN6505 devices, SN6501 does not have soft-start, internal current limit, or thermal shutdown (TSD)features. Therefore, unregulated large currents exceeding device absolute maximum current ratings may
damage the device or affect its long-term reliability. In addition, high capacitive loads at the isolated power
supply output may appear as short circuits to SN6501 during power-up and may exceed the device's maximum
current ratings. When using SN6501, it is recommended to incorporate LDOs with low short-circuit current limits
or soft-start features to ensure excessive current is not drawn from SN6501.
9.2.2.2 LDO Selection
The minimum requirements for a suitable low dropout regulator are:Submit Document Feedback

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•

•

•

Its current drive capability should slightly exceed the specified load current of the application to prevent the
LDO from dropping out of regulation. Therefore for a load current of 100 mA, choose a 100 mA to 150 mA
LDO. While regulators with higher drive capabilities are acceptable, they also usually possess higher dropout
voltages that will reduce overall converter efficiency.
The internal dropout voltage, VDO, at the specified load current should be as low as possible to maintainefficiency. For a low-cost 150 mA LDO, a VDO of 150 mV at 100 mA is common. Be aware however, that thislower value is usually specified at room temperature and can increase by a factor of 2 over temperature,
which in turn will raise the required minimum input voltage.
The required minimum input voltage preventing the regulator from dropping out of line regulation is given
with:VI-min = VDO-max + VO-max•(1)

This means in order to determine VI for worst-case condition, the user must take the maximum values for VDO
and VO specified in the LDO data sheet for rated output current (i.e., 100 mA) and add them together. Also
specify that the output voltage of the push-pull rectifier at the specified load current is equal or higher than
VI-min. If it is not, the LDO will lose line-regulation and any variations at the input will pass straight through tothe output. Hence below VI-min the output voltage will follow the input and the regulator behaves like a simple
conductor.
The maximum regulator input voltage must be higher than the rectifier output under no-load. Under thiscondition there is no secondary current reflected back to the primary, thus making the voltage drop across
RDS-on negligible and allowing the entire converter input voltage to drop across the primary. At this point thesecondary reaches its maximum voltage ofVS-max = VIN-max × n(2)

with VIN-max as the maximum converter input voltage and n as the transformer turns ratio. Thus to prevent the
LDO from damage the maximum regulator input voltage must be higher than VS-max. 表 9-2 lists the maximum
secondary voltages for various turns ratios commonly applied in push-pull converters with 100 mA output drive.
表 9-2. Required Maximum LDO Input Voltages for Various Push-Pull Configurations
PUSH-PULL CONVERTERLDOCONFIGURATION

VIN-max [V]

TURNS-RATIO

VS-max [V]VI-max [V]

3.3 VIN to 3.3 VOUT

3.6

1.5 ± 3%

5.6

6 to 10

3.3 VIN to 5 VOUT

3.6

2.2 ± 3%8.2

10

5 VIN to 5 VOUT

5.5

1.5 ± 3%8.5

109.2.2.3 Diode Selection
A rectifier diode should always possess low-forward voltage to provide as much voltage to the converter output
as possible. When used in high-frequency switching applications, such as the SN6501 however, the diode mustalso possess a short recovery time. Schottky diodes meet both requirements and are therefore strongly
recommended in push-pull converter designs. A good choice for low-volt applications and ambient temperaturesof up to 85°C is the low-cost Schottky rectifier MBR0520L with a typical forward voltage of 275 mV at 100-mA
forward current. For higher output voltages such as ±10 V and above use the MBR0530 which provides a higher
DC blocking voltage of 30 V.
Lab measurements have shown that at temperatures higher than 100°C the leakage currents of the above
Schottky diodes increase significantly. This can cause thermal runaway leading to the collapse of the rectifier
output voltage. Therefore, for ambient temperatures higher than 85°C use low-leakage Schottky diodes, such as
RB168M-40.

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1

Forward Current, IF - A

Forward Current, IF - A

1

0°C
TJ = 100°C

75°C

25°C

-25°C

0.1

0.01

TJ = 125°C

75°C

25°C

-40°C

0.1

0.01
0.1

0.2
0.3
0.4
Forward Voltage, VF - V

0.5

0.2

0.3
0.4
Forward Voltage, VF - V

0.5

図 9-4. Diode Forward Characteristics for MBR0520L (Left) and MBR0530 (Right)

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9.2.2.4 Capacitor Selection
The capacitors in the converter circuit in 図 9-7 are multi-layer ceramic chip (MLCC) capacitors.
As with all high speed CMOS ICs, the SN6501 requires a bypass capacitor in the range of 10 nF to 100 nF.
The input bulk capacitor at the center-tap of the primary supports large currents into the primary during the fastswitching transients. For minimum ripple make this capacitor 1 μF to 10 μF. In a 2-layer PCB design with adedicated ground plane, place this capacitor close to the primary center-tap to minimize trace inductance. In a 4layer board design with low-inductance reference planes for ground and VIN, the capacitor can be placed at the
supply entrance of the board. To ensure low-inductance paths use two vias in parallel for each connection to areference plane or to the primary center-tap.
The bulk capacitor at the rectifier output smoothes the output voltage. Make this capacitor 1 μF to 10 μF.
The small capacitor at the regulator input is not necessarily required. However, good analog design practicesuggests, using a small value of 47 nF to 100 nF improves the regulator ’s transient response and noise
rejection.
The LDO output capacitor buffers the regulated output for the subsequent isolator and transceiver circuitry. The
choice of output capacitor depends on the LDO stability requirements specified in the data sheet. However, inmost cases, a low-ESR ceramic capacitor in the range of 4.7 μF to 10 μF will satisfy these requirements.
9.2.2.5 Transformer Selection
9.2.2.5.1 V-t Product Calculation

To prevent a transformer from saturation its V-t product must be greater than the maximum V-t product appliedby the SN6501. The maximum voltage delivered by the SN6501 is the nominal converter input plus 10%. The
maximum time this voltage is applied to the primary is half the period of the lowest frequency at the specified
input voltage. Therefore, the transformer’s minimum V-t product is determined through:Vtmin ³ VIN-max ´

Tmax
2

=

VIN-max
2 ´ fmin(3)

Inserting the numeric values from the data sheet into the equation above yields the minimum V-t products of
Vtmin ³

3.6 V
= 7.2 Vμs
2 ´ 250 kHz

Vtmin ³

5.5 V
= 9.1 Vμs for 5 V applications.
2 ´ 300 kHz

for 3.3 V, and(4)

Common V-t values for low-power center-tapped transformers range from 22 Vμs to 150 Vμs with typicalfootprints of 10 mm x 12 mm. However, transformers specifically designed for PCMCIA applications provide as
little as 11 Vμs and come with a significantly reduced footprint of 6 mm x 6 mm only.
While Vt-wise all of these transformers can be driven by the SN6501, other important factors such as isolation
voltage, transformer wattage, and turns ratio must be considered before making the final decision.
9.2.2.5.2 Turns Ratio Estimate

Assume the rectifier diodes and linear regulator has been selected. Also, it has been determined that thetransformer choosen must have a V-t product of at least 11 Vμs. However, before searching the manufacturer
websites for a suitable transformer, the user still needs to know its minimum turns ratio that allows the push-pullconverter to operate flawlessly over the specified current and temperature range. This minimum transformation
ratio is expressed through the ratio of minimum secondary to minimum primary voltage multiplied by a correction
factor that takes the transformer’s typical efficiency of 97% into account.

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nmin1.031uJAJSK49C – JUNE 2013 – REVISED MARCH 2021v s minv p min(5)

VS-min must be large enough to allow for a maximum voltage drop, VF-max, across the rectifier diode and still
provide sufficient input voltage for the regulator to remain in regulation. From the LDO SELECTION section, thisminimum input voltage is known and by adding VF-max gives the minimum secondary voltage with:
VS-min = VF-max + VDO-max + VO-max

(6)
VF
VI

VDO

VS

VIN

VO
RL

VP

VDS

RDS

Q

図 9-5. Establishing the Required Minimum Turns Ratio Through Nmin = 1.031 × VS-min / VP-min
Then calculating the available minimum primary voltage, VP-min, involves subtracting the maximum possible
drain-source voltage of the SN6501, VDS-max, from the minimum converter input voltage VIN-min:
VP-min = VIN-min – VDS-max(7)

VDS-max however, is the product of the maximum RDS(on) and ID values for a given supply specified in theSN6501 data sheet:
VDS-max = RDS-max × IDmax(8)

Then inserting 式 8 into 式 7 yields:
VP-min = VIN-min - RDS-max x IDmax(9)and inserting 式 9 and 式 6 into 式 5 provides the minimum turns ration with:nmin = 1.031 ´VF-max + VDO-max + VO-max
VIN-min - RDS-max ´ ID-max(10)

Example:For a 3.3 VIN to 5 VOUT converter using the rectifier diode MBR0520L and the 5 V LDO TPS76350, the data
sheet values taken for a load current of 100 mA and a maximum temperature of 85°C are VF-max = 0.2 V,
VDO-max = 0.2 V, and VO-max = 5.175 V.
Then assuming that the converter input voltage is taken from a 3.3 V controller supply with a maximum ±2%
accuracy makes VIN-min = 3.234 V. Finally the maximum values for drain-source resistance and drain current at
3.3 V are taken from the SN6501 data sheet with RDS-max = 3 Ω and ID-max = 150 mA.
Inserting the values above into 式 10 yields a minimum turns ratio of:

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nmin = 1.031 ´

0.2V + 0.2V + 5.175 V=2
3.234 V - 3 Ω ´ 150 mA(11)

Most commercially available transformers for 3-to-5 V push-pull converters offer turns ratios between 2.0 and 2.3
with a common tolerance of ±3%.
9.2.2.5.3 Recommended Transformers

Depending on the application, use the minimum configuration in 図 9-6 or standard configuration in 図 9-7.

図 9-6. Unregulated Output for Low-Current Loads
With Wide Supply Range

図 9-7. Regulated Output for Stable Supplies andHigh Current Loads

The Wurth Electronics Midcom isolation transformers in 表 9-3 are optimized designs for the SN6501, providing
high efficiency and small form factor at low-cost.
The 1:1.1 and 1:1.7 turns-ratios are designed for logic applications with wide supply rails and low load currents.
These applications operate without LDO, thus achieving further cost-reduction.
表 9-3. Recommended Isolation Transformers Optimized for SN6501
Turns
Ratio

VxT
(Vμs)

1:1.1 ±2%

Isolation(VRMS)

Dimensions(mm)

Application

7

LDO

Figures

3.3 V → 3.3 V

Order No.

図 6-1
図 6-2

760390011

図 6-3
図 6-4

760390012

1:1.1 ±2%

5V→5V

1:1.7 ±2%

3.3 V → 5 V

図 6-5
図 6-6

760390013

3.3 V → 3.3 V
5V→5V

図 6-7
図 6-8
図 6-9
図 6-10760390014

2500
1:1.3 ±2%6.73 x 10.05 x 4.19

11

No

Yes
1:2.1 ±2%

3.3 V → 5 V

図 6-11
図 6-12760390015

1.23:1 ±2%

5 V → 3.3 V

図 6-13
図 6-14750313710

1:1.1 ±2%

3.3 V → 3.3 V

図 6-15
図 6-16750313734

1:1.1 ±2%

5V→5V

図 6-17
図 6-18750313734

1:1.7 ±2%

3.3 V → 5 V

図 6-19
図 6-20750313769

1:1.3 ±2%

3.3 V → 3.3 V
5V→5V

図 6-21
図 6-22
図 6-23
図 6-24750313638

1:2.1 ±2%

3.3 V → 5 V

図 6-25
図 6-26750313626

1.3:1 ±2%

5 V → 3.3 V

図 6-27
図 6-28750313638

11

5000

9.14 x 12.7 x 7.37

No

Yes

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表 9-3. Recommended Isolation Transformers Optimized for SN6501 (continued)
Turns
Ratio

VxT
(Vμs)

Isolation(VRMS)

1:1.1 ±2%71:1.1 ±2%11

1:1.7 ±2%

Dimensions(mm)

Application

1500

11
7.1 x 11 x 4.19

LDO

Figures

Order No.

3.3 V → 3.3V

No

N/A

EPC3804G-L

5V → 5V

No

N/A

EPC3805G-L

3.3V → 5V

No / Yes

N/A

EPC3806G-L

N/A

EPC3807G-L

3.3V → 3.3V

Manufacturer

PCA Electronics
1:1.3 ±2%11

1:2 ±2%11

1:1.1 ±2%

4.3

2500

3.3V → 3.3V

Yes

5V → 5V

8.6 x 12.5 x 5.97

3.3V → 5V

Yes

N/A

EPC3808G-L

5V → 5V

No

N/A

EPC3809G-L

No

N/A

HCTSM80101AAL

3.3V → 3.3V

1:1

5V → 5V

1:2

3.3V → 5V

Yes

N/A

HCTSM80102AAL

2:1

5V → 1.8V

Yes

N/A

HCTSM80201AAL

3.3V → 3.3V

Yes

N/A

HCTSM80304BAL

3:4

5V → 5V
3.3V → 5V

No

N/A

HCTSM80305BAL

3:8

5V → 12V

Yes

N/A

HCTSM80308BAL

4:3

5V → 3.3V

No

N/A

HCTSM80403AAL

8:3

5V → 1.8V

No

N/A

HCTSM80803AAL

8:9

3.3V → 3.3V

N/A

HCTSM80809AAL

N/A

HCTSM80910BAL

N/A

HCTSM81017CAL

3:5

11

4200

10.8 x 15.2 x 6.6

9:10

5V → 5V

10:17

3.3V → 5V

No
Yes

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9.2.3 Application Curve
See 表 9-3 for application curves.
9.2.4 Higher Output Voltage Designs
The SN6501 can drive push-pull converters that provide high output voltages of up to 30 V, or bipolar outputs of
up to ±15 V. Using commercially available center-tapped transformers, with their rather low turns ratios of 0.8 to5, requires different rectifier topologies to achieve high output voltages. 図 9-8 to 図 9-11 show some of these
topologies together with their respective open-circuit output voltages.
nnVOUT+ = n·VIN

VIN

VOUT- = n·VIN

図 9-8. Bridge Rectifier With Center-Tapped
Secondary Enables Bipolar Outputsn

図 9-9. Bridge Rectifier Without Center-Tapped
Secondary Performs Voltage Doubling

VOUT+ = 2n·V IN

VIN

VOUT = 2n·VIN

VIN

n

VOUT = 4n·VIN

VIN

VOUT- = 2n·V IN

図 9-10. Half-Wave Rectifier Without Center-Tapped
Secondary Performs Voltage Doubling, Centered
Ground Provides Bipolar Outputs

図 9-11. Half-Wave Rectifier Without Centered
Ground and Center-Tapped Secondary Performs
Voltage Doubling Twice, Hence Quadrupling VIN

9.2.5 Application Circuits
The following application circuits are shown for a 3.3 V input supply commonly taken from the local, regulated
micro-controller supply. For 5 V input voltages requiring different turn ratios refer to the transformer
manufacturers and their websites listed in 表 9-4.
表 9-4. Transformer Manufacturers
Coilcraft Inc.

http://www.coilcraft.com

Halo-Electronics Inc.

http://www.haloelectronics.com

Murata Power Solutions

http://www.murata-ps.com

Wurth Electronics Midcom Inc

http://www.midcom-inc.com

Certain components might not possess AEC-Q100 Q1 qualification. For more detailed information on qualified
components for automotive applications please refer to the automotive web page: http://www.ti.com/lsds/ti/apps/
automotive/applications.page.

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図 9-12. Isolated RS-485 Interface

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図 9-13. Isolated Can Interface

図 9-14. Isolated RS-232 Interface

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図 9-15. Isolated Digital Input Module

図 9-16. Isolated SPI Interface for an Analog Input Module With 16 Inputs

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図 9-17. Isolated I2C Interface for an Analog Data Acquisition System With 4 Inputs and 4 Outputs
VS
3.3 V

0.1 F

2

1:1.33

VCC D2 3

MBR0520L
1

SN6501

4.7 F 0.1 F

GND D1IN

OUT

3.3VISO

5

10 F

TPS76333
3

1

EN

GND

2

10 F
MBR0520L

4, 5

0.1 F

ISO-BARRIER

0.1 F

20

LOOP+

0.1 F

0.1 F

15

0.1 F
10
1

8

2
5
6

DVCC
XOUT
XIN

MSP430
G2132

8

P3.0 11
12
P3.1

VCC1

VCC2

2 OUTA

INA
ISO7421

3 INB

OUTB

DVSS

GND1

GND2

4

4

5

7

5

6

4

3
VA

VD

LOW

BASE

ERRLVL16
0.1 F

DAC161P997
22

DBACK
DIN

C1

14
3 × 22 nF

1 F

C2C3 COMA

13

12

1

OUT
COMD

9
LOOP±

2

図 9-18. Isolated 4-20 mA Current Loop

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Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: SN6501-Q1
English Data Sheet: SLLSEF3

SN6501-Q1

www.ti.com/ja-jp

JAJSK49C – JUNE 2013 – REVISED MARCH 2021

10 Power Supply Recommendations
10.1
The device is designed to operate from an input voltage supply range between 3.3 V and 5 V nominal. This input
supply must be regulated within ±10%. If the input supply is located more than a few inches from the SN6501 a
0.1μF by-pass capacitor should be connected as possible to the device VCC pin, and a 10 μF capacitor should
be connected close to the transformer center-tap pin.

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Product Folder Links: SN6501-Q1
English Data Sheet: SLLSEF3

SN6501-Q1

www.ti.com/ja-jp

JAJSK49C – JUNE 2013 – REVISED MARCH 2021

11 Layout11.1 Layout Guidelines
•
•

•
•
•
•
•
•

The VIN pin must be buffered to ground with a low-ESR ceramic bypass-capacitor. The recommended
capacitor value can range from 1 μF to 10 μF. The capacitor must have a voltage rating of 10 V minimum anda X5R or X7R dielectric.
The optimum placement is closest to the VIN and GND pins at the board entrance to minimize the loop area
formed by the bypass-capacitor connection, the VIN terminal, and the GND pin. See 図 11-1 for a PCB layout
example.
The connections between the device D1 and D2 pins and the transformer primary endings, and theconnection of the device VCC pin and the transformer center-tap must be as close as possible for minimum
trace inductance.
• The connection of the device VCC pin and the transformer center-tap must be buffered to ground with a lowESR ceramic bypass-capacitor. The recommended capacitor value can range from 1μF to 10 μF. The
capacitor must have a voltage rating of 16 V minimum and a X5R or X7R dielectric.
The device GND pins must be tied to the PCB ground plane using two vias for minimum inductance.
The ground connections of the capacitors and the ground plane should use two vias for minimum inductance.
The rectifier diodes should be Schottky diodes with low forward voltage in the 10 mA to 100 mA current range
to maximize efficiency.
The VOUT pin must be buffered to ISO-Ground with a low-ESR ceramic bypass-capacitor. The recommended
capacitor value can range from 1μF to 10 μF. The capacitor must have a voltage rating of 16 V minimum anda X5R or X7R dielectric.

11.2 Layout Example

図 11-1. Layout Example of a 2-Layer Board (SN6501)

28

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Product Folder Links: SN6501-Q1
English Data Sheet: SLLSEF3

SN6501-Q1

www.ti.com/ja-jp

JAJSK49C – JUNE 2013 – REVISED MARCH 2021

12 Device and Documentation Support
12.1 Device Support
12.1.1 サード・パーティ製品に関する免責事項
サード・パーティ製品またはサービスに関するテキサス・インスツルメンツの出版物は、単独またはテキサス・インスツルメン
ツの製品、サービスと一緒に提供される場合に関係なく、サード・パーティ製品またはサービスの適合性に関する是認、サード・パーティ製品またはサービスの是認の表明を意味するものではありません。

12.2 Trademarks
すべての商標は、それぞれの所有者に帰属します。

12.3 静電気放電に関する注意事項

この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい ESD 対策をとらないと、デバイスを破損するおそれがあります。
ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。

12.4 用語集
TI 用語集

この用語集には、用語や略語の一覧および定義が記載されています。

13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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29

Product Folder Links: SN6501-Q1
English Data Sheet: SLLSEF3

PACKAGE OPTION ADDENDUM

www.ti.com

27-Feb-2021

PACKAGING INFORMATION
Orderable Device

Status(1)

Package Type Package Pins Package
Drawing
Qty

Eco Plan(2)

Lead finish/
Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

(3)

(4/5)

(6)

SN6501QDBVRQ1

ACTIVE

SOT-23

DBV

5

3000

RoHS & Green

NIPDAU

Level-1-260C-UNLIM-40 to 125

SBRQ

(1)

The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)

RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

SamplesPACKAGE MATERIALS INFORMATION
www.ti.com

25-Sep-2024

TAPE AND REEL INFORMATIONREEL DIMENSIONSTAPE DIMENSIONS
K0

P1

B0 W
Reel
DiameterCavity
A0
B0
K0
W
P1

A0

Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers

Reel Width (W1)QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes

Q1

Q2

Q1

Q2

Q3

Q4

Q3

Q4

User Direction of Feed

Pocket Quadrants*All dimensions are nominal

DeviceSN6501QDBVRQ1

Package Package Pins
Type Drawing

SPQ

SOT-23

3000

DBV

5

Reel
Reel
A0
Diameter Width (mm)(mm) W1 (mm)
178.0

9.0

Pack Materials-Page 1

3.23

B0
(mm)

K0
(mm)

P1
(mm)

W
Pin1
(mm) Quadrant

3.17

1.37

4.0

8.0

Q3

PACKAGE MATERIALS INFORMATION
www.ti.com

25-Sep-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)

W

L

H

*All dimensions are nominal

DevicePackage Type

Package Drawing

Pins

SPQ

Length (mm)Width (mm)Height (mm)

SN6501QDBVRQ1

SOT-23

DBV

5

3000

180.0

180.0

18.0

Pack Materials-Page 2

PACKAGE OUTLINE

DBV0005A

SOT-23 - 1.45 mm max height
SCALE 4.000

SMALL OUTLINE TRANSISTOR

C

3.0
2.6
1.75
1.45

PIN 1
INDEX AREA
1

A

5

(0.1)

2X 0.95
1.9

0.1 C
B

3.05
2.75
1.9

2
(0.15)

4
0.5
5X
0.3
0.2

3
C A B

NOTE 5

4X 0 -15

(1.1)

0.15
TYP
0.00

1.45
0.90
4X 4 -15

0.25
GAGE PLANE

8
TYP
0

0.22
TYP
0.08

0.6
TYP
0.3

SEATING PLANE

4214839/K 08/2024

NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.

www.ti.com

EXAMPLE BOARD LAYOUT

DBV0005A

SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5

5X (0.6)

SYMM
(1.9)

2
2X (0.95)
3

4(R0.05) TYP(2.6)

LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE:15X

SOLDER MASKOPENINGMETALSOLDER MASKOPENINGMETAL UNDERSOLDER MASKEXPOSED METALEXPOSED METAL

0.07 MIN
ARROUND

0.07 MAX
ARROUNDNON SOLDER MASKDEFINED(PREFERRED)SOLDER MASKDEFINEDSOLDER MASK DETAILS

4214839/K 08/2024

NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DBV0005A

SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5

5X (0.6)

SYMM
(1.9)

2
2X(0.95)
4

3(R0.05) TYP(2.6)

SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCILSCALE:15X

4214839/K 08/2024

NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com

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