# Side-Channel Exploitation of DRAM Access Patterns for Fingerprinting FPGA-CPU Environments

Eliott Quéré, Maria Mendez Real, Alessandro Palumbo, Lilian Bossuet, Ruben Salvador

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Eliott Quéré, Maria Mendez Real, Alessandro Palumbo, Lilian Bossuet, Ruben Salvador. Side-Channel Exploitation of DRAM Access Patterns for Fingerprinting FPGA-CPU Environments. RESSI 2025 - Rendez-Vous de la Recherche et de l'Enseignement de la Sécurité des Systèmes d'Information, May 2025, Lannion, France. hal-05266486

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# Side-Channel Exploitation of DRAM Access Patterns for Fingerprinting FPGA-CPU Environments

Eliott Quéré

Univ Rennes, Inria, CNRS, IRISA

eliott.quere@irisa.fr

Maria Méndez Real

Univ Bretagne-Sud

Lab-STICC - UMR 6285

maria.mendez-real@univ-ubs.fr

Alessandro Palumbo

CentraleSupélec, Inria, CNRS, IRISA

alessandro.palumbo@inria.fr

Lilian Bossuet

Univ Lyon, UJM-Saint-Etienne, CNRS

Laboratoire Hubert Curien UMR 5516 F-42023

lilian.bossuet@univ-st-etienne.fr

Rubén Salvador

CentraleSupélec, Inria, CNRS, IRISA

ruben.salvador@inria.fr

**Abstract**—The widespread adoption of FPGA-accelerated computing in embedded and cloud environments introduces new side-channel threats due to shared hardware resources. This work investigates DRAM access patterns as a leakage source to fingerprint CPU activity, examining both SoC-FPGA and cloud-based co-processor models. In SoC environments, cache-miss-induced DRAM activity generates measurable power fluctuations that can be remotely observed. While previous research has detected these fluctuations using external electromagnetic probes for side-channel-based disassembly, we assess whether embedded FPGA sensors can achieve similar results, enabling attackers to infer CPU operations without physical access. However, in cloud-based co-processor models, where FPGA-CPU interactions occur over PCIe and RDMA, large-scale power management appears to significantly lower the Signal-to-Noise Ratio (SNR), potentially making power side channels more challenging to exploit compared to SoC-FPGAs. Given this uncertainty, we investigate the feasibility of power-based leakage while also exploring timing-based side channels leveraging PCIe contention and RDMA latency variations, which have been shown to reveal workload characteristics. By evaluating both power and timing leakage across these architectures, we comprehensively assess side-channel risks in FPGA-accelerated platforms and emphasize the need for stronger isolation mechanisms.

**Index Terms**—FPGA security, side-channel attacks, DRAM access patterns, cache-miss leakage, power analysis, PCIe contention, RDMA timing attacks, CPU fingerprinting, embedded sensors, cloud computing security.

## I. INTRODUCTION

Field-Programmable Gate Arrays (FPGAs) have become essential components in modern high-performance computing, offering flexible acceleration capabilities across various domains, from machine learning to cryptographic processing. As their adoption expands to cloud environments, new security concerns arise due to the shared infrastructure in which multiple users operate on the same hardware[1]. Unlike traditional embedded FPGA deployments, cloud-based architectures expose shared resources, such as Peripheral Component Inter-

connect Express (PCIe), DRAM, and power delivery networks (PDNs), to potential adversaries, creating new avenues for remote side-channel attacks.

A key concern in FPGA security is the potential for information leakage through shared memory and communication interfaces. In a SoC-FPGA, where the CPU and FPGA fabric are tightly integrated on the same die, cache misses from the CPU trigger DRAM accesses and generate distinct power fluctuation patterns visible from the FPGA. Prior work [2] has demonstrated that these patterns, visible through electromagnetic (EM) emanations, can be exploited for side-channel disassembly. However, whether these cache-miss patterns can be observed through embedded power sensors[3] such as Time-to-Digital Converters (TDCs)[4] or Routing Delay Sensors (RDS)[5] remains an open question. If confirmed, this approach would introduce a novel method for cache attacks, leveraging embedded sensors to monitor specific DRAM access patterns and fingerprint CPU activity.

Beyond vulnerabilities in SoC-FPGAs, cloud deployments introduce additional complexities. In a co-processor model, where FPGAs communicate with CPUs via PCIe and Remote Direct Memory Access (RDMA), DRAM access is mediated through memory controllers and the I/O Memory Management Unit (IOMMU). Unlike tightly integrated SoC-FPGAs, cloud infrastructures rely on large-scale Power Supply Units (PSUs) feeding both CPUs and FPGAs[6]. This increased scale significantly lowers the SNR of power side channels, as the aggregation of multiple power domains introduces noise that attenuates fine-grained fluctuations. The resulting low-SNR conditions challenge the feasibility of power-based attacks [7], making signal extraction more complex and potentially less exploitable. However, a systematic evaluation is needed to determine whether advanced filtering or statistical techniques could improve leak observability. Alternatively, timing-based side channels that use PCIe contention and RDMA latency
variations offer a more resilient attack vector under these conditions, as previous research has shown their effectiveness in workload inference [8]. We aim to study the exploitability and security implications of these leakages in cloud FPGA environments by evaluating power and timing-based side channels.

Building on these insights, we examine the feasibility of leveraging DRAM access patterns for CPU fingerprinting in various FPGA deployment models. Our contributions are as follows.

* We evaluate how cache-miss-induced DRAM activity generates power fluctuations in the PDN of SoC-FPGAs, assessing its impact as a side-channel leakage source.

* We assess the feasibility of power-based leakage in cloud FPGA co-processor models and, if limited by low SNR, investigate timing-based exploitation via PCIe and RDMA contention.

* We have initiated preliminary experimentation using a TDC sensor on an SoC-FPGA (Zybo Z7-20) to validate our approach against previously identified EM-based cache-miss patterns [2].

By demonstrating that DRAM access patterns leak across both embedded and cloud FPGA deployments, our work underscores the need for stronger isolation mechanisms and security-aware FPGA designs. The insights presented in this paper highlight the urgency of addressing side-channel risks in FPGA-accelerated computing, particularly as these architectures become increasingly central to modern high-performance and cloud-based workloads.

## II. BACKGROUND

The emergence of FPGA-accelerated cloud computing has introduced new security challenges due to the remote threat model, where adversaries lack physical access but can exploit shared infrastructure to mount side-channel attacks. Unlike traditional FPGA security concerns, which primarily focus on bitstream confidentiality [9], hardware Trojans [10], and fault injection attacks [11], cloud-based deployments expose FPGAs to multitenant environments where isolation mechanisms are imperfect. In this context, attackers can leverage shared resources—such as PCIe, DRAM, and PDNs to infer sensitive computations from co-located workloads.

FPGAs in the cloud are typically deployed under an Acceleration-as-a-Service (AaaS) or FPGA-as-a-Service (FaaS) model [12]. These services integrate FPGA boards into cloud environments using different deployment configurations, each with distinct security and resource-sharing implications. This work focuses on two of the three primary deployment setups [13]: the co-processor and the SoC models. Each model employs a distinct resource-sharing arrangement, leading to unique avenues for side-channel exploitation (see Fig. 1). While the co-processor model allows power-based leakage exploitation via shared PSU [6], its effectiveness may be constrained by low SNR. In such cases, timing-based attacks through PCIe contention could offer a more viable alternative for side-channel exploitation. In contrast, with its tighter

integration between the FPGA and CPU, the SoC model may exhibit even more pronounced power-based leakage due to localized PDN effects, making power side channels the primary focus of investigation.

### A. Co-processor and PCIe Contention-Based Threats

In the co-processor deployment model, an FPGA and CPU share a node and communicate through a dedicated PCIe interface. While this setup ensures high-throughput data transfers, it also introduces shared-resource contention. PCIe is a point-to-point full-duplex communication standard designed for high-speed data transfers among multiple devices. It interconnects devices such as GPUs, FPGAs, NICs, and SSDs through switches and Platform Controller Hubs (PCHs). In high-density configurations, scheduling inefficiencies in these switches can lead to performance degradation and open side-channel vulnerabilities.

Early research demonstrated [14] that variations in PCIe bandwidth, for instance, those influenced by different driver implementations, can disclose the co-location of virtual machines by revealing distinct resource usage patterns. In subsequent work [15], PCIe congestion-induced delays were used as a side channel. In particular, attackers probing an RDMA Network Interface Controller (NIC) that shared a PCIe switch with a GPU managed to infer the GPU's workload on a remote server.

More recent research [8] examines PCIe contention in FPGA-accelerated cloud environments and demonstrates cross-VM attacks leveraging PCIe traffic for covert channels. By analyzing bandwidth signatures, attackers inferred operational details such as cross-NUMA node co-locations and identified interference arising from network and SSD activities. Additionally, the study highlighted how PCIe contention can degrade host-FPGA communication. Another work [16] extends these insights by designing an attack circuit to measure PCIe bandwidth and collect side-channel traces, then training machine learning models to classify victim accelerators based on their unique communication signatures.

Additionally, RDMA presents another attack vector within PCIe-based infrastructures. DMA enables efficient data transfers between peripherals and memory without processor intervention, a key mechanism in high-throughput cloud environments. In FPGA-based systems, frameworks like Intel's Open Programmable Acceleration Engine (OPAE)[17] request contiguous physical memory blocks accessible by the FPGA. At the same time, Intel Virtualization Technology for Directed I/O (VT-d) assigns Input/Output Virtual Addresses (IOVA) to PCIe devices, ensuring the FPGA has a contiguous view of allocated memory. However, PCIe as the underlying interface for DMA also introduces vulnerabilities in RDMA-enabled environments [18].

Specifically, the IOMMU walker mechanism translates memory accesses for PCIe I/O devices, such as Remote Network Interface Cards (RNICs) and GPUs [19]. During intensive GPU workloads, these walkers can become saturated, delaying RDMA operations and increasing response times.
<figure><img src="image_2.png" /><figcaption>Fig. 1. Different FPGA deployment models in cloud computing. a) The co-processor model utilizes PCIe connections to link FPGA boards with CPUs in data centres. b) The SoC model integrates the FPGA and CPU on the same chip die. Adapted from [13].</figcaption></figure>

Such timing variations create a measurable side channel, allowing attackers to infer GPU activity and extract sensitive workload information. On platforms like AWS EC2 F1, DMA operations map DRAM channels to FPGA memory via PCIe using designs such as CL_DRAMDMA [20]. As previously noted [8], contention-based side channels arising from PCIe traffic and DMA timing can be exploited to profile and fingerprint co-tenant activity in cloud environments.

## B. Power Analysis in SoC-FPGA Environments

SoC-FPGA devices integrate microprocessors with FPGA fabric on a single chip. This tight coupling reduces latency and power consumption between the CPU and FPGA but also exposes a shared PDN that can be exploited for power-based side-channel attacks [21]. By monitoring subtle voltage fluctuations in the PDN, adversaries can extract sensitive information, even in the presence of logical isolation or when the SoC architecture suggests physical separation between processing elements.

While traditional power analysis attacks required physical probes, recent advancements have demonstrated the feasibility of remote power monitoring through embedded on-chip sensors [3]. Among the most studied techniques, Time-to-Digital Converters (TDCs) [22] and Ring Oscillators (ROs) [23, 24] provide a means to capture power variations without external access. TDCs measure propagation delays within uniform buffer chains, correlating voltage fluctuations with power consumption, while ROs rely on frequency modulation induced by supply voltage changes. Although ROs are easier to implement, TDCs generally offer higher sensitivity and resolution, enabling key recovery and other advanced attacks.

Recent sensor designs prioritize integration and stealthiness to blend seamlessly into the FPGA fabric. For instance, VITI [25] uses look-up tables (LUTs) in place of dedicated delay elements, while MULT-8 [26] repurposes DSP primitives to reduce detectability. Routing Delay Sensors (RDS) [5] exploit the inherent sensitivity of FPGA routing resources to PDN voltage changes, achieving higher precision with minimal resource overhead.

SideLine [27] demonstrates how existing modules in a SoC, like delay-locked loops (DLLs), typically used to mitigate jitter [28] and synchronize high-speed memory buses, can be repurposed as remote power sensors in high-end SoC memory controllers. While DLL-based sensing is easy to implement via memory-mapped registers, its limited resolution requires many traces for successful side-channel analysis. However, given the widespread integration of DLLs and programmable delay blocks in modern SoCs, their evolving role in high-speed memory interfaces is likely to enhance their power-sensing capabilities, improving sampling rates with next-generation RAM technologies and thereby increasing the risk of remote power side-channel attacks in SoC-FPGA environments.

## C. Memory and Cache Attacks

In cloud environments, the increasing demand for peripheral performance places significant strain on the memory subsystem of modern processors. In some cases, DRAM throughput is insufficient to handle data traffic from high-performance peripherals such as network cards. To address this shortfall, modern Intel processors implement Direct Cache Access (DCA) instead of traditional DMA [29], performing I/O operations directly on the Last Level Cache (LLC) to minimize latency and optimize performance. However, this shared LLC, accessible by both the CPU and accelerators like FPGAs, creates opportunities for cache-based side-channel attacks [30].

Previous research has shown that cache attacks exploit timing differences to infer sensitive information [31]. By measuring memory access latencies, adversaries can deduce whether specific addresses are cached or identify the cache level used. Modern hierarchical cache architectures, composed of faster, smaller caches (L1 and L2) and larger, slower caches (LLC), further facilitate these attacks. Such vulnerabilities have been extensively studied in cloud computing [32]. A prominent example is NetCAT [33], which introduced the first network-based PRIME+PROBE attack targeting the LLC of a remote machine, demonstrating vulnerabilities in both cooperative and adversarial network scenarios.
Subsequent studies revealed hardware vulnerabilities in hy-
brid FPGA- CPU systems, particularly in cloud deployments
where FPGAs and CPUs belong to distinct security domains
[34]. The memory interfaces, including hardware-level drivers
and logical interfaces, can be exploited to infer CPU cache ac-
tivity, allowing adversaries to deduce memory access patterns
and extract sensitive information. For instance, FPGA-based
accelerators have been shown able to spy on neighbouring
peripherals through the I/O Translation Lookaside Buffer
(IOTLB), a cache specialized in DMA address translations
[35]. Using Flush+Reload and PRIME+PROBE techniques,
malicious FPGAs can snoop on PCIe peripherals such as smart
NICs or GPUs, all sharing the same DMA remapping engine.

Parallel work leveraged EM emanations from DRAM ac-
cesses as a cache side-channel [2], highlighting that DRAM
leakage can reveal cache access patterns. Although physical
EM measurements are impractical in typical cloud FPGA
settings, power measurements offer a viable alternative for
remote leakage exploitation through embedded sensors. This
approach adapts the principles of EM-based cache attacks by
analyzing voltage fluctuations, aligning with the two deploy-
ment scenarios discussed in this article.

In co-processor models, attackers may indirectly exploit
PCIe and RDMA to infer cache misses and memory access
patterns. In contrast, the shared DRAM and PDN enable more
direct monitoring of cache-related power fluctuations in SoC
environments, facilitating CPU fingerprinting and cache-based
attacks.

### III. THREAT MODEL

The growing adoption of FPGA-accelerated computing in
embedded and cloud environments introduces new attack
surfaces for remote side-channel analysis. We consider an
adversary capable of deploying custom FPGA logic and
software probes to extract sensitive information from CPU
operations by monitoring power fluctuations, timing variations,
or memory access patterns. The adversary lacks physical
access but can leverage shared hardware resources to mount
these attacks.

In SoC-FPGA environments, where the CPU and FPGA fab-
ric are tightly integrated, shared components such as DRAM
controllers and the PDN become leakage vectors. Cache-miss-
induced DRAM activity can generate observable power varia-
tions, which adversaries may exploit despite logical isolation
mechanisms. In cloud-based co-processor deployments, where
FPGA-CPU interactions occur over PCIe and RDMA, power-
based attacks may be limited by low SNR. However, adver-
saries can exploit timing-based side channels by analyzing
PCIe contention and RDMA latency fluctuations to infer CPU
workloads.

The primary risk across both models is that logically
separated security domains, such as an FPGA user partition
and an isolated CPU workload, may still physically share key
hardware components. DRAMs, PDNs, and PCIe interfaces
create unintended leakage channels, enabling attackers to infer

memory access patterns and extract sensitive CPU computa-
tions

#### IV. ONGOING EXPERIMENTATIONS AND FUTURE WORK

Our research investigates side-channel leakage from DRAM access patterns in SoC-FPGA and cloud co-processor FPGA environments. To assess the feasibility of such attacks, we conduct controlled experiments leveraging embedded TDC sensors within the FPGA fabric. Using the SCABox framework [21], we integrate well-calibrated TDC sensors, stream the collected measurements into internal BRAM-based FIFOs, and post-process the extracted traces. On the CPU side, we execute bare-metal workloads, starting with TinyAES [36] to evaluate the sensor's sensitivity to fine-grained power variations. We validate leakage exploitability through Correlation Power Analysis (CPA) and extend our study to general DRAM activity inference, comparing traces from idle execution with those collected during structured memory-intensive workloads. We aim to identify DRAM access signatures that reveal CPU workload characteristics by analyzing these traces in the time and frequency domains. Since SCABox was initially designed for the Zybo Z7-20, used in previous EM-based cache-miss studies [2], we perform our initial experiments on this platform before transitioning to a Xilinx UltraScale+ FPGA, where we will assess the scalability of our approach in high-performance environments and explore potential countermeasures.

Beyond SoC environments, we aim to extend our study
to cloud FPGA deployments, where FPGA-CPU interactions
occur via PCIe and RDMA. Power-based side channels are
more challenging in these settings due to large-scale power
management and lower SNR. To address this, we will in-
vestigate whether cache-miss-related DRAM access patterns
remain observable when memory transactions are mediated
through PCIe and RDMA mechanisms. We will also explore
timing-based side channels by monitoring latency variations
in the IOMMU and memory controllers, as such anomalies
could indicate concurrent memory accesses or CPU-driven
contention, revealing workload characteristics even in cloud
environments. By systematically analyzing both power-based
leakage (in SoCs) and timing-based leakage (in co-processor
models), we aim to extend cache-miss detection methodologies
to the cloud. Ultimately, these findings contribute to a uni-
fied framework for side-channel analysis in FPGA-accelerated
computing, exposing new security risks and emphasizing the
need for stronger isolation mechanisms at both the hardware
and system levels to safeguard next-generation heterogeneous
computing platforms.

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