# A topological field-effect memristor

Manuel Meyer, Selena Barragan, Sergey Krishtopenko, Adriana Wolf, Monika Emmerling, Sebastian Schmid, Jean-Baptiste Rodriguez, Eric Tournie, Benoit Jouault, Gerald Bastard, et al.

<figure><img src="image_1.png" /></figure>

## To cite this version:

Manuel Meyer, Selena Barragan, Sergey Krishtopenko, Adriana Wolf, Monika Emmerling, et al. A topological field-effect memristor. 2025. hal-05408357

HAL Id: hal-05408357

https://cnrs.hal.science/hal-05408357v1

Preprint submitted on 10 Dec 2025

HAL is a multi-disciplinary open access
archive for the deposit and dissemination of sci-
entific research documents, whether they are pub-
lished or not. The documents may come from
teaching and research institutions in France or
abroad, or from public or private research centers.

L'archive ouverte pluridisciplinaire HAL, est
destinée au dépôt et à la diffusion de documents
scientifiques de niveau recherche, publiés ou non,
émanant des établissements d'enseignement et de
recherche français ou étrangers, des laboratoires
publics ou privés.

<figure><img src="image_2.png" /></figure>

Distributed under a Creative Commons Attribution 4.0 International License
A topological field-effect memristor

Manuel Meyer¹,ᵃ), Selena Barragan¹, Sergey Krishtopenko¹,², Adriana Wolf¹, Monika
Emmerling¹, Sebastian Schmid¹, Jean-Baptiste Rodriguez³, Eric Tournie³,⁴ Benoit
Jouault², Gerald Bastard¹,⁵, Frederic Teppe², Victor Lopez-Richard⁶, Ovidiu Lipan⁷,
Lukas Worschech¹, Sven Höfling¹, and Fabian Hartmann¹,ᵇ)

¹Julius-Maximilians-Universität Würzburg, Physikalisches Institut and Würzburg-Dresden Cluster of
Excellence ct.qmat, Lehrstuhl für Technische Physik, Am Hubland, 97074 Würzburg, Germany

²Laboratoire Charles Coulomb (L2C), UMR 5221 CNRS-Université de Montpellier, Montpellier, France

³IES, Université de Montpellier, CNRS, F-34000 Montpellier, France

⁴Institut Universitaire de France, F-75005 Paris, France

⁵Physics Department, École Normale Supérieure, PSL 24 rue Lhomond, 75005 Paris, France

⁶Departamento de Física, Universidade Federal de Sao Carlos, 13565-905 Sao Carlos, SP, Brazil

⁷Department of Physics, University of Richmond, 28 Westhampton Way, Richmond, Virginia 23173, USA

Overcoming the limitations of the von Neumann architecture requires new computational
paradigms capable of solving complex problems efficiently. Quantum and neuromorphic computing
rely on unconventional materials and device functionalities, yet achieving resilience to imperfections
and reliable operation remains a major challenge. This has motivated growing interest in topological
materials that provide robust and low-power operation while preserving coherence. However,
integrating coherent topological transport with non-volatile memory functionality in a single
reconfigurable device has remained challenging. In this work, we demonstrate a topological field-
effect memristor based on inverted InAs/GaInSb/InAs trilayer quantum wells operating in the
quantum spin Hall regime. The intrinsic floating-gate behavior allows one to reconfigure the
transistor functionality into memristive functionality with broad electric-field tunability. Unlike
other memristor implementations, one resistance state is governed entirely by dissipationless,
coherent transport through helical edge channels, while the other arises from incoherent bulk
conduction. By combining electrically tunable coherent and incoherent transport with memory
functionality, our device realizes a prototypical topological electronic element that integrates
coherent transport and adaptive memristive behavior, paving the way for hybrid quantum-
neuromorphic architectures.

a) Email: manuel.meyer@uni-wuerzburg.de

b) Email: fabian.hartmann@uni-wuerzburg.de
Conventional computing architectures encode information in binary bits high (1 or H) or low (0 or L) and perform operations using Boolean logic. The robustness and fault tolerance of binary computation lies in the large separation between bit values that suppresses the effect of small perturbations[1]. However, this separation also renders binary computation intrinsically energy inefficient. A second limitation - more by choice than fundamentally - is the separation of the central processing unit and memory in the von Neumann architecture. This separation requires a constant data transfer between memory and processing units, leading to sequential computation and performance limitations known as the von Neumann bottleneck, as well as high-power consumption[2,3]. To overcome these limitations,, alternative computational architectures are actively explored[4]. Among them, quantum computing introduces parallelism through superposition and entanglement, leveraging coherence for computation[5]. While quantum computation can be realized on various material platforms with different quantum bit realizations, it demands sufficiently long coherence times for solving complex problems. Thus, fault-tolerance remains the central challenge as coherence is destroyed by environmental factors and disorder².

In contrast, neuromorphic computation does not rely on quantum coherence, but its parallel computing ability emerges from the complex interconnection within the network itself[6-8]. While neuromorphic computing can be realized in standard CMOS architectures[9,10], such implementations are energy-inefficient and hence new materials with emergent functionalities are required to solve this issue[11,12].

At first glance, quantum and neuromorphic computing appear mutually exclusive as quantum computing relies on isolation and coherence and neuromorphic computing thrives on interaction with a complex environment. This apparent incompatibility motivates the search for material platforms that can simultaneously preserve coherence and support adaptive electronic behavior. However, a key challenge for both architectures is resilience to perturbations such as disorder, structural imperfections and dissipation, which can disrupt computational outcomes. Therefore, devices that exhibit intrinsic robustness while preserving their functional properties are essential for advancing these technologies.
In recent decades, quantum systems with intrinsic protection have gained significant interest. In particular, topological insulators (TIs), characterized by a non-trivial band topology, offer a compelling route towards low-dissipation and robust information processing even in the presence of perturbations[13]. Time-reversal-invariant two-dimensional (2D) TIs, also known as quantum spin Hall insulators (QSHIs), support protected coherent edge states that are dissipationless and spin-polarized even in the presence of disorder[14–17]. This raises the intriguing possibility of combining (quantum) coherence and neuromorphic adaptability within a single material platform[18–20], potentially reconciling these two seemingly incompatible computational schemes. To explore this possibility, a material system must support coherence-preserving transport while also enabling volatile or non-volatile adaptive behavior characteristic of neuromorphic devices.

Inverted InAs/(Ga,In)Sb-based quantum wells (QWs) are a tunable and scalable III-V semiconductor platform[21,22] that support the QSHI state through band inversion and strong spin-orbit coupling[23,24]. Moreover, these QWs in its symmetrical three-layer configuration possess large topological gaps up to ~50 meV[25,26] with the perspectives of the observation of coherent transport via the topological edge states at elevated temperatures[27–29]. A recent observation of the QSHI state in inverted InAs/GaInSb/InAs trilayer quantum wells (TQWs) at 60 K[30] makes them a promising platform for implementing functional devices that harness topologically protected edge states for electronic applications even at higher temperatures.

Here, we report on the experimental realization of a topological field-effect memristor based on inverted InAs/GaInSb/InAs TQWs, combining coherent helical edge transport with memristive functionality. Our device exploits the broken-gap band alignment between InAs and (Ga,In)Sb, in which appropriate quantum well thicknesses and mole fractions give rise to a band-inverted regime with a topological QSHI state. By harnessing the intrinsic floating-gate behavior of the gate dielectric, we fabricate a topological memristor broadly tunable by electric fields, which demonstrates memristive switching between a bulk-dominated (incoherent) state and a helical edge-dominated (coherent) state leveraging the topological
protection. This realization uniquely combines coherent helical edge transport with memristive switching behavior, establishing a new platform for neuromorphic networks based on topological materials.

## Device architecture

The topological field-effect memristor is based on an InAs/Ga<sub>0.68</sub>In<sub>0.32</sub>Sb/InAs TQW heterostructure, grown on (001) AlSb buffer and engineered to realize the QSHI state. Figure 1 summarizes the device architecture and illustrates its possible dual operation as a field-effect transistor and memristor. As shown in Fig. 1(a), the TQW exhibits an inverted band-gap energy of about 27 meV opened between the two electron subbands (E1 and E2). The first hole subband (H1) lies approximately 20 meV above the E2 band. The relatively large band-gap energy enables the high-temperature observation of the QSHI state[30]. Figs. 1(b) and (c) illustrate a standard transistor configuration, showing a schematic layer structure and an exemplary optical image of a large Hall bar device. In the transistor configuration, a constant bias voltage is applied to the drain contact and the relative position of the Fermi energy (E<sub>F</sub>) is controlled electrically via the top-gate voltage. The source is on the common ground. By shorting the drain and top-gate electrodes (Figs. 1(d) and (e)), the same device can operate as a memristor, where the floating gate functionality emerges intrinsically[31] due to charge trapping at the semiconductor/oxide interface[28,32]. The oxide used for this device is a superlattice of SiO<sub>2</sub>/SiN (5x 10 nm/ 10 nm and ending with an additional 10 nm SiO<sub>2</sub> layer). Both configurations share a six-terminal Hall bar geometry with a channel width of W = 20 µm and contact separation length between the voltage probes of L = 10 µm (see optical images in panels (c) and (e) for an exemplary device). An additional back-gate voltage is applied to independently manipulate the Fermi energy and the perpendicular electric field utilizing this dual-gating approach[21], providing full electrostatic control of the device. This dual-mode architecture allows direct comparison of transistor and memristor transport within the same topological device. All transport measurements were performed at T = 4.2 K in the dark.
<figure><img src="image_3.png" /><figcaption>**Fig. 1.** Device architecture and dual-mode operation as field-effect transistor and memristor. (a) Calculated band dispersion of the sample with a topological non-trivial band gap of approximately 27 meV. The gap is formed between the two electron-like (E1 and E2) bands. (b),(c) Transistor configuration: Bias and top-gate voltages are applied independently and via the back-gate voltage, the electric field can additionally be adjusted. (d),(e) Memristor configuration: bias and top-gate voltages are shorted to form a memristor device. Via the back-gate voltage, the electric field can be controlled leading to a three-terminal memristor.</figcaption></figure>

We now examine how topological protection manifests in the field-effect transistor configuration before turning to the memristive operation.

## Quantum spin Hall insulator in field-effect transistor configuration

To demonstrate how topological protection can enable adaptive electronic behavior, we first examine the device in a field-effect transistor configuration as was shown in Figs. 1(b) and 1(c). The device exhibits tunability via electric fields applied through both the top and back gates. Figures 2(a) and (b) show the resistance as a function of top-gate voltage for two exemplary back-gate voltages $V_{BG} = -6$ V and $-9$ V, respectively. The top-gate voltage is swept from $V_{TG} = +10$ V to $-10$V (in black, down-sweep) and back to $+10$ V (in red, up-sweep). In both sweep directions, a prominent resistance peak appears when the Fermi energy lies within the topological-insulating gap. On the right- and left-hand sides of each peak, the Fermi
energy lies in the conduction and valence bands, respectively. The insets schematically illustrate the
position of the Fermi energy for both sweep directions. A pronounced hysteresis (ΔV) appears between
the up and down sweeps. It originates from charge accumulation (ΔQ) at the oxide-semiconductor
interface, which acts as an intrinsic floating gate. The relative shift of the peak is governed by the
difference in localized charges and the effective capacitive coupling C<sub>eff</sub>: ΔV = ΔQ/C<sub>eff</sub>. As seen in Fig.
2(a) for a back-gate voltage of -6 V, both peaks are on the negative top-gate voltage side while for a back-
gate voltage - 9 V (see Fig. 2(b)), the peak for the down-sweep direction can be shifted to the positive top-
gate voltage region. Hence, for a specific back-gate voltage and thus electric field, the topological gap can
be tuned to zero top-gate voltage. Figs. 2(c) and 2(d) show the extracted peak resistance values and their
corresponding positions as a function of back-gate voltage. As V<sub>BG</sub> decreases, the peak resistance
increases systematically. Since transport in the band-gap region is mediated entirely by helical edge
channels[30], this trend reflects a reduction in the phase coherence length[33]. Concurrently, the peak
position shifts towards more positive top-gate voltages, eventually crossing zero at V<sub>BG</sub> ≈ -7 V (as seen
in Fig. 2(d)).
<figure><img src="image_4.png" /><figcaption>**Fig. 2.** Electric field dependence of resistance in transistor configuration. (a) Resistance as a function of top-gate voltage between +10 V and -10 V (down-sweep, black; up-sweep, red) for a back-gate voltage of -6 V. For positive top-gate voltages, the Fermi energy is in the conduction band, and the dominant charge carrier type is n-type. After the gap region, the Fermi energy is in the valence band, and the transport is mainly p-type. Due to charge accumulation, the up- and down-sweep directions show pronounced hysteresis (ΔV). (b) For a back-gate voltage of -9 V, the position of the gap can be set to positive top-gate voltages. Extracted peak resistance values Rmax are shown in (c) and their positions in (d) for the up- and down-sweep directions, respectively. At a back-gate voltage of -7 V, the peak position in the down-sweep direction coincides with zero top-gate voltage.</figcaption></figure>

Having established the topological-insulator behavior in the transistor mode, we now turn to the memristive configuration to explore how these edge states contribute to adaptive transport.
Quantum spin Hall insulator in field-effect memristor configuration

The realization of the topological memristor follows the operation scheme indicated in Fig. 1(d) and (e).
In this configuration, the drain and top-gate voltages are shorted and sweeps of the bias voltage
simultaneously control both the in-plane and perpendicular electric fields[34,35]. As was mentioned
above, the back-gate offers additional control over the perpendicular electric field. We first consider the
case where the band-gap region appears on the positive side for the down-sweep but at the negative side
for the up-sweep, i.e. for back-gate voltages below ~ -8V.

Figure 3(a) shows the voltage-current characteristic of the memristor device when the bias current is swept
between ±10 µA and the back-gate voltage is set constant to -10 V. The voltage is recorded as the voltage
drop between the leads 5 and 4. A clear pinched hysteresis loop is observed between the down- and up-
sweeps (black and red, respectively). For large positive currents, the in-plane and perpendicular electric
fields are large, placing the Fermi energy in the conduction band, and resulting in n-type bulk conduction.
Consequently, the voltage drops across the device and resistances are low. As the bias voltage is reduced
towards zero, both in-plane and perpendicular electric fields decrease, pushing the Fermi energy into the
topological band gap. This transition corresponds to the resistance peak observed near zero bias in the I-
V curve. Further reduction of the bias voltage to -10 V increases the in-plane electric field and shifts the
Fermi energy into the valence band, where transport is dominated by p-type bulk holes. Due to the
charging of the floating gate for the up-sweep direction, the voltage-current characteristic shifts leading
to the observed pinched hysteresis loop. Two key features characterize the transport behavior of our
topological memristor. First, the transport mechanism depends on the sweep direction, as indicated by the
color-coded boxes. At large in-plane electric fields, both sweep directions involve a single carrier type
(the regions labeled with n/n and p/p). At lower fields however, the carrier type differs between sweeps
(e.g. p-type for the up-sweep and n-type for the down-sweep). Finally, the regions labeled gap/n and gap/p
are characterized by joint transport via the helical edge states and conductive bulk (n-type or p-type).
The second notable feature is the appearance of negative differential resistance (NDR) regions. Such NDR regions, also recently reported, in e.g., MOTT-Memristors, are of great interest for emulating neural functions using memristors [36,37]. Figs. 3(b) and 3(c) illustrate the two distinct transport regimes that define the functionality of the topological memristor. When the Fermi energy lies in the conduction or valence band, transport occurs through bulk states (n-type or p-type), leading to low-resistance values (Fig. 3(b)). This bulk resistance can be tuned by modulating the charge carrier density and mobility via the bias voltage, effectively enabling a variable conductance analogous to a tunable synaptic weight in a neural computation scenario. In contrast, when the Fermi energy is placed in the topological band gap, the conductivity through the bulk states is suppressed, and the transport is dominated by helical edge channels (Fig. 3(c)). This regime exhibits a stable resistance value representing a robust state, comparable to a fixed synaptic weight. Together, these two regimes offer the possibility to combine the flexibility of tunable bulk transport with the robustness of topologically protected edge conduction. However, it is important to note that the helical edge transport is not fully coherent over the entire device length, as the contact separation exceeds the phase coherence length [33,38]. To observe fully coherent and quantized edge transport, the contact separation must be reduced below the phase coherence length - a regime that will be explored in the next section (see Fig. 5).
<figure><img src="image_5.png" /><figcaption>**Fig. 3.** Transport features of the topological memristor. (a) Voltage-current pinched hysteresis loop by sweeping the current between ±10 µA for a back-gate voltage of -10 V in black (down-sweep) and red (up-sweep), respectively. The device shows a clear pinched hysteresis loop with two resistance values emerging at zero bias current (High - helical edge and low - bulk, see inset). The color-coded boxes provide the regions with different combinations of carrier types responsible for transport dependent on the sweeping direction: p/p, n/n, p/n, gap/n and gap/p regions can be realized. (b),(c) Schematic of the two types of transport: low resistance via bulk transport in the n- and p-type regions and high resistance via helical edge transport in the topological gap regions.</figcaption></figure>

To evaluate the performance of the topological memristor, we examine the change in resistance states under external electric fields applied, focusing on the tunability between high- and low-resistance states and their relative ratio. Figure 4 presents the detailed memristor response as a function of both the perpendicular (via back-gate voltage) and in-plane electric fields (via applied bias). Figure 4(a) shows a zoom-in of the voltage-current characteristics around zero bias voltage for two exemplary back-gate
values: V<sub>BG</sub> = -2 V in black and V<sub>BG</sub> = -8V in blue. At V<sub>BG</sub> = -2 V, the slope of the voltage-current
characteristics is almost flat and similar for both sweep directions, indicating a low resistance due to the
bulk conductivity. The small difference in resistances mainly reflects variations in the charge carrier
densities and mobilities resulting from different Fermi energy positions. In contrast, for V<sub>BG</sub> = -8 V, the
down-sweep exhibits a much steeper voltage-current slope near zero bias than the up-sweep. This sharp
increase in differential resistance indicates that the Fermi energy lies in the topological band gap during
the down-sweep. Figure 4(b) depicts how the position of this maximum differential resistance evolves
with back-gate voltage. Around V<sub>BG</sub> = -8 V, the resistance peak shifts towards zero bias, similar to the
transistor behavior discussed previously (see Fig. 2(d)). This demonstrates that the perpendicular electric
field can be used to align the topological band gap with the operating point of the memristor. Fig. 4(c)
depicts the differential resistance value at zero bias for both the high-resistance (down-sweep) and low-
resistance (up-sweep) states as a function of the back-gate voltage, for two different maximal bias voltages
(±7 V and ±10 V). For a bias of ±10 V, the low-resistance state stays in the range below ~10 kΩ. In
contrast, the high-resistance state exceeds 100 kΩ. The high-resistance state peaks near V<sub>BG</sub> = -8 V, where
the topological band gap aligns with zero bias. In comparison, for a bias voltage of ±7 V, the difference
between the high and low resistance states is less pronounced. The complete extracted High/Low ratios
are summarized in Fig. 4(d). As shown above, the resistance ratio can be tuned by both the back-gate
voltage and the bias amplitude. A maximum ratio of 22.5 is achieved for V<sub>BG</sub> ≈ -8 V and ± 10 V bias,
where the topological band-gap region fully overlaps with the high-resistance state at zero bias. This
maximizes the contrast between the bulk and edge contributions to the conductivity.
<figure><img src="image_6.png" /></figure>

<figure><img src="image_7.png" /></figure>

<figure><img src="image_8.png" /></figure>

<figure><img src="image_9.png" /><figcaption>**Fig. 4.** Electric field dependence of the topological memristor. (a) Zoom-in of the voltage-current characteristics for back-gate voltages of -2 V (red) and -8 V (black) vertically offset by 0.1 V for clarity. The arrows indicate the sweeping direction. (b) Bias voltage position at the peak resistance in dependence of the back-gate voltage. At $V_{BG}$ = -8 V, the topological gap aligns with zero bias voltage. (c) Differential resistance at zero bias for the high- and low-resistance state as a function of back-gate voltage for two bias voltage amplitudes (±7 V in purple and ±10 V in black). (d) High/Low resistance ratios as a function of back-gate voltage for various bias voltage amplitudes between ±3 V and ±10 V. Below ±7 V, both resistance values almost coincide. At larger bias, the resistance ratio increases significantly and reaches a maximal value of 22.5 for a bias voltage of ±10 V and $V_{BG} \approx$ -8 V. This maximum is achieved when the topological gap coincides with zero bias voltage.</figcaption></figure>
Coherent helical edge transport in a topological memristor

To directly probe coherent helical edge transport in the topological memristor, we fabricated a microscopic device with a contact separation length of 3 µm, which is shorter than the experimentally determined phase coherence length[30]. This microscopic design enables observation of memristive switching between a low-resistance incoherent bulk state and a high-resistance coherent helical edge state, highlighting the interplay between coherence and adaptive functionality in a single device. Figure 5(a) presents the voltage versus current (swept between ±10 µA) at zero back-gate voltage. The corresponding differential resistance (in units of h/2e²) is shown in Fig. 5(b) for both current sweep directions (down-sweep in black, up-sweep in red). Strikingly, a robust resistance value emerges at h/2e² at around zero current, providing direct evidence of dissipationless quantized transport via topological helical edge states. This represents a clear manifestation of the QSHI state in the memristor configuration. While these measurements were performed at T = 4.2 K, the same material platform has exhibited quantized edge transport up to 60 K[30], indicating that the coherence underlying the memristive functionality can persist at elevated temperatures.

During the up-sweep at zero current, the transport is dominated by incoherent bulk conductivity, resulting in a significantly lower differential resistance. This operating point of the memristor is indicated by the vertical dashed grey line. The differential resistance in the band-gap region during the up-sweep reaches approximately 1.3 h/2e², exceeding a quantized value because of the reduction in phase coherence length[33,39]. These results establish that memristive switching between a low-resistance of incoherent bulk states and a high-resistance of the coherent helical edge states can be realized in a single device. This demonstrates the successful integration of quantum-coherent and memory functionalities within a single topological field-effect memristor, highlighting its potential as a building block for hybrid quantum-neuromorphic architectures.
<figure><img src="image_10.png" /><figcaption>**Fig. 5.** Microscopic topological memristor with coherent edge transport. (a) Voltage as a function of current (down, black; up, red) in the memristor configuration for the microscopic device (see inset) with a contact separation length of L = 3 µm. (b) Differential resistance in units of h/2e², for the down- (black) and up-sweep direction (red). The pronounced quantized resistance value at h/2e² emerges due to dissipationless and coherent transport via helical edge states. For the up-sweep direction, the low resistance originates from incoherent bulk conduction.</figcaption></figure>

**Conclusion**

In summary, we realized a topological field-effect memristor that combines quantized helical edge transport with memristive switching between distinct history-dependent transport regimes. Built on a scalable III-V semiconductor platform, the device exploits the helical edge states of InAs/GaInSb/InAs TQWs to switch between coherent topological and incoherent bulk conducting states. Crucially, the
quantized resistance value of $h/2e^2$ in the microscopic device confirms the robustness and dissipationless character of the underlying topological edge states, even under device-level operation.

These results establish a direct link between topological protection and non-volatile memory functionality, introducing a new class of quantum-coherent memory elements. The dual transistor–memristor operation unifies topologically protected transport and adaptive charge-storage functionality within a single material system, enabling information to be stored and processed locally in the same coherent medium. This intrinsic coexistence of logic and memory offers a route to overcoming the von Neumann bottleneck. Beyond its conceptual implications, our work demonstrates a prototypical topological electronic device that combines coherence, adaptability, and scalability, opening the prospect of integrated quantum-neuromorphic hardware architectures.

## Acknowledgments

The work was supported by the Elite Network of Bavaria within the graduate program “Topological Insulators” and by the Occitanie region through the TOP platform and the “Quantum Technologies Key Challenge” program (TARFEP project). We acknowledge financial support from the DFG within the project HO 5194/19-1 and through the Würzburg-Dresden Cluster of Excellence on Complexity and Topology in Quantum Matter – ct.qmat (EXC 2147, project-id 390858490). We also acknowledge the French Agence Nationale pour la Recherche (Cantor project - ANR-23-CE24-0022), and Equipex+ Hybat project - ANR-21-ESRE-0026), and the Physics Institutes of CNRS for Emergence 2024 - STEP - project. V. L.-R. acknowledges the support of CNPq Proj. 311536/2022-0 and FAPESP Projs. 2025/00677-8, and 2025/04805-0
## References

[1] C. S. Raghavendra, A. Avizienis, and M. D. Ercegovac, Fault Tolerance in Binary Tree Architectures, IEEE Trans. on Comp., 568 (1984).

[2] J. Backus, Can Programming Be Liberated from the von Neumann Style? A Functional Style and Its Algebra of Programs, Commun. ACM 21, 613 (1978).

[3] M. Di Ventra and Y. V. Pershin, The parallel approach, Nat. Phys. 9, 200 (2013).

[4] G. Finocchio et al., Roadmap for Unconventional Computing with Nanotechnology, Nano Futures 8, 012001 (2024).

[5] M. M. Waldrop, More Than Moore, Nature 530, 144 (2016).

[6] G. Indiveri and S. C. Liu, Memory and Information Processing in Neuromorphic Systems, Proc. IEEE 103, 1379 (2015).

[7] M. Ziegler, R. Soni, T. Patelczyk, M. Ignatov, T. Bartsch, P. Meuffels, and H. Kohlstedt, An Electronic Version of Pavlov's Dog, Adv. Funct. Mater. 22, 2744 (2012).

[8] Marina Ignatov, Martin Ziegler, Mirko Hansen, and Hermann Kohlstedt, Memristive stochastic plasticity enables mimicking of neural synchrony: Memristive circuit emulates an optical illusion, Sci. Adv. 3, e1700849 (2017).

[9] S. Pazos, K. Zhu, M. A. Villena, O. Alharbi, W. Zheng, Y. Shen, Y. Yuan, Y. Ping, and M. Lanza, Synaptic and neural behaviours in a standard silicon transistor, Nature 640, 69 (2025).

[10] M. Prezioso, F. Merrikh-Bayat, B. D. Hoskins, G. C. Adam, K. K. Likharev, and D. B. Strukov, Training and operation of an integrated neuromorphic network based on metal-oxide memristors, Nature 521, 61 (2015).

[11] V. Milo, G. Malavena, C. M. Compagnoni, and D. Ielmini, Memristive and CMOS devices for neuromorphic computing, Materials 13, 166 (2020).

[12] P. D. Hodgson, D. Lane, P. J. Carrington, E. Delli, R. Beanland, and M. Hayne, ULTRARAM: A Low-Energy, High-Endurance, Compound-Semiconductor Memory on Silicon, Adv. Electron. Mater. 8, 2101103 (2022).

[13] M. Z. Hasan and C. L. Kane, Colloquium: Topological insulators, Rev. Mod. Phys. 82, 3045 (2010).

[14] M. König, S. Wiedmann, C. Brüne, A. Roth, H. Buhmann, L. W. Molenkamp, X. Qi, and S. Zhang, Quantum Spin Hall Insulator State in HgTe Quantum Wells, Science 318, 766 (2007).

[15] C. L. Kane and E. J. Mele, Z2 topological order and the quantum spin Hall effect, Phys. Rev. Lett. 95, 146802 (2005).

[16] S. Wu, V. Fatemi, Q. D. Gibson, K. Watanabe, T. Taniguchi, R. J. Cava, and P. Jarillo-Herrero, Observation of the quantum spin Hall effect up to 100 kelvin in a monolayer crystal, Science 359, 76 (2018).
[17] A. Roth, C. Brüne, H. Buhmann, L. W. Molenkamp, J. MacIejko, X. L. Qi, and S. -C. Zhang, *Nonlocal Transport in the Quantum Spin Hall State*, Science **325**, 294 (2009).

[18] H. Wu *et al.*, Magnetic memory driven by topological insulators, Nat. Commun. **12**, 6251 (2021).

[19] Y. Liu *et al.*, Cryogenic in-memory computing using magnetic topological insulators, Nat. Mater. **24**, 559 (2025).

[20] M. Chen *et al.*, Selective and quasi-continuous switching of ferroelectric Chern insulator devices for neuromorphic computing, Nat. Nanotechnol. **19**, 962 (2024).

[21] F. Qu *et al.*, Electric and Magnetic Tuning between the Trivial and Topological Phases in InAs/GaSb Double Quantum Wells, Phys. Rev. Lett. **115**, 036803 (2015).

[22] M. Meyer, T. Fähndrich, S. Schmid, A. Wolf, S. S. Krishtopenko, B. Jouault, G. Bastard, F. Teppe, F. Hartmann, and S. Höfling, Coexistence of topological and normal insulating phases in electro-optically tuned InAs / GaSb bilayer quantum wells, Phys. Rev. B **109**, L121303 (2024).

[23] C. Liu, T. L. Hughes, X. L. Qi, K. Wang, and S. C. Zhang, Quantum spin hall effect in inverted type-II semiconductors, Phys. Rev. Lett. **100**, 236601 (2008).

[24] L. Du, I. Knez, G. Sullivan, and R.-R. Du, Robust Helical Edge Transport in Gated InAs/GaSb Bilayers, Phys. Rev. Lett. **114**, 096802 (2015).

[25] S. S. Krishtopenko and F. Teppe, Quantum spin Hall insulator with a large bandgap, Dirac fermions, and bilayer graphene analog, Sci. Adv. **4**, eaap7529 (2018).

[26] C. Avogadri *et al.*, Large inverted band-gap in strained three-layer InAs/GaInSb quantum wells, Phys. Rev. Res. **4**, L042042 (2022).

[27] S. S. Krishtopenko *et al.*, Temperature-dependent terahertz spectroscopy of inverted-band three-layer InAs/GaSb/InAs quantum well, Phys. Rev. B **97**, 245419 (2018).

[28] M. Meyer, S. Schmid, F. Jabeen, G. Bastard, F. Hartmann, and S. Höfling, Topological band structure in InAs / GaSb / InAs triple quantum wells, Phys. Rev. B **104**, 085301 (2021).

[29] S. Benlenqwanssa *et al.*, Multi-probe analysis to separate edge currents from bulk currents in quantum spin Hall insulators and to analyze their temperature dependence, Phys. Rev. Appl. **22**, 064059 (2024).

[30] M. Meyer *et al.*, Quantum spin Hall effect in III-V semiconductors at elevated temperatures: Advancing topological electronics, Sci. Adv. **11**, eadz2408 (2025).

[31] G. Labes Rodrigues, A. B. Yoshida, G. S. Selmi, Tomi Kamijo Barbosa de Jesus, Nickolas Filgueira e Silva, Igor Ricardo, K. Watanabe, T. Taniguchi, R. F. de Oliveira, V. Lopez-Richard, and A. R. Cadore, Graphene Heterostructure-Based Non-Volatile Memory Devices with Top Floating Gate Programming, ACS Appl. Elec. Mater. (2025).

[32] S. Mueller, A. N. Pal, M. Karalic, T. Tschirky, C. Charpentier, W. Wegscheider, K. Ensslin, and T. Ihn, Nonlocal transport via edge states in InAs/GaSb coupled quantum wells, Phys. Rev. B **92**, 081303(R) (2015).
[33] L. Lunczer, P. Leubner, M. Endres, V. L. Müller, C. Brüne, H. Buhmann, and L. W. Molenkamp, Approaching Quantization in Macroscopic Quantum Spin Hall Devices through Gate Training, Phys. Rev. Lett. **123**, 047701 (2019).

[34] M. Ziegler, M. Oberländer, D. Schroeder, W. H. Krautschneider, and H. Kohlstedt, Memristive operation mode of floating gate transistors: A two-terminal MemFlash-cell, Appl. Phys. Lett. **101**, 263504 (2012).

[35] P. Maier, F. Hartmann, T. Mauder, M. Emmerling, C. Schneider, M. Kamp, S. Höfling, and L. Worschech, Memristive operation mode of a site-controlled quantum dot floating gate transistor, Appl. Phys. Lett. **106**, 203501 (2015).

[36] S. Kumar, R. S. Williams, and Z. Wang, Third-order nanocircuit elements for neuromorphic engineering, Nature **585**, 518 (2020).

[37] F. Peronaci, S. Ameli, S. Takayoshi, A. S. Landsman, and T. Oka, Mott memristors based on field-induced carrier avalanche multiplication, Phys. Rev. B **107**, 075154 (2023).

[38] E. M. Spanton, K. C. Nowack, Du Lingjie, G. Sullivan, R. Du Rui, and K. A. Moler, Images of edge current in InAs/GaSb quantum wells, Phys. Rev. Lett. **113**, 026804 (2014).

[39] M. Meyer, S. Schmid, F. Jabeen, G. Bastard, F. Hartmann, and S. Höfling, Voltage control of the quantum scattering time in InAs/GaSb/InAs trilayer quantum wells, New J. Phys. **25**, 023035 (2023).