# Development of Ni P contact technology and its integration on III-V materials for 300 mm Si photonics platform

Flore Boyer, Romain Famulok, Stephane Minoret, Nicolas Coudurier,
Christophe Jany, Patrice Gergaud, Philippe Rodriguez

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## To cite this version:

Flore Boyer, Romain Famulok, Stephane Minoret, Nicolas Coudurier, Christophe Jany, et al. Development of Ni P contact technology and its integration on III-V materials for 300 mm Si photonics platform. IEEE Journal of the Electron Devices Society, 2022, 10, pp.728-736. 10.1109/JEDS.2021.3135971. cea-04904244

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Distributed under a Creative Commons Attribution 4.0 International License
Received 19 October 2021; revised 22 November 2021 and 29 November 2021; accepted 10 December 2021. Date of publication 16 December 2021; date of current version 9 September 2022. The review of this article was arranged by Editor T. Narita.

Digital Object Identifier 10.1109/JEDS.2021.3135971

# Development of Ni₂P Contact Technology and Its Integration on III-V Materials for 300 mm Si Photonics Platform

FLORE BOYER<sup>D 1</sup>, ROMAIN FAMULOK<sup>2</sup>, STÉPHANE MINORET<sup>2</sup>, NICOLAS COUDURIER<sup>2</sup>, CHRISTOPHE JANY<sup>2</sup>, PATRICE GERGAUD<sup>2</sup>, AND PHILIPPE RODRIGUEZ<sup>D 2</sup>

1 STMicroelectronics, 38926 Crolles, France

2 CEA, Leti, Université Grenoble Alpes, 38000 Grenoble, France

CORRESPONDING AUTHOR: P. RODRIGUEZ (e-mail: philippe.rodriguez@cea.fr)

This work was supported by the French National Research Agency (ANR) through the "Investissements d'avenir" Program under Grant ANR 10-AIRT-0005 (IRT NANOELEC) and Grant ANR 10-EQPX-0030 (EQUIPEX FDSOI 11).

**ABSTRACT** In order to assess their potential use as contact layers for Si photonics devices, Ni₂P thin films were developed on a 300 mm platform. The Ni₂P layers, obtained by magnetron sputtering of a Ni₂P target, were stable and reproducible. The films were mainly composed of the hexagonal Ni₂P phase with small amount of Ni₁₂P₅ impurities. The film density was 6.9 g/cm³ with a ratio of 62 at.% of Ni and 38 at.% of P. We implemented and integrated these Ni₂P films on III-V structures to study their electrical properties on n-InP and p-InGaAs (i.e., n-doped and p-doped III-V/Si hybrid laser contact layers). The results obtained on p-InGaAs did not meet the requirements in terms of contact resistivity. On the other hand, due to its high thermal stability and low contact resistivities, Ni₂P metallization exhibited the best results among the Ni-based metallizations studied for contacting n-InP layers, namely Ni, NiPt and Ni₂P.

**INDEX TERMS** Contact technology, InP, Ni₂P, Si photonics.

## I. INTRODUCTION

The interest for Si photonics [1]–[3] grew with the thirst for information and digital data over the past years. People not only need more and more data storage capacities, but they also need to exchange data as fast as possible. In this way, the Si photonics application range has been extended from data centers, high-performance computing and telecom to medical, automotive, aeronautics and defense use. Decades ago, optical links were only used for long-distance communications such as cross-country and trans-oceanic transmissions. Nowadays optical interconnects are envisioned at the scale of the chip. Si photonics represents the combination of optical communication networks and Si CMOS (complementary metal oxide semi-conductor) industry. The key driving force behind Si photonics is the ability to use CMOS-like fabrication resulting in high-volume production at low cost [4].

Among all the various potential technologies covered by the term "Si photonics", the hybrid integration of

III-V on Si was widely studied. III-V / Si photonics was envisioned for spectroscopic sensing and optical communications including lasers, amplifiers, photodetectors and optical interconnects [5]. To enable the integration of III-V devices directly onto 200 and 300 mm platforms, various integration schemes were investigated such as flip-chip bonding [6] or unprocessed III-V die bonding [7]. For the direct bonding of III-V wafers or dies [8], the development of CMOS-compatible processes is mandatory. Among all these technological steps, the capability to integrate CMOS-compatible contact technology is of significant importance.

Classical or historical metallizations developed to contact n-InP and p-InGaAs layers were based on the use of noble metals such as gold (Au), platinum (Pt) or palladium (Pd). In this way, the stacks Ni / AuGe, AuGe(Ni) or Au/Pt/Ti were widely investigated [9]–[11]. These metallizations were usually integrated in III-V dedicated clean rooms using non-planar integration schemes, namely lift-off processes. These
contacts are thus not Si CMOS-compatible, i.e., they cannot be integrated in a Si-Fab line. More recently, a few studies were published by various groups in which the metallization and processes implemented to integrate the contacts on III-V materials were compatible with standard CMOS fabrication lines [12]–[15].

In our group, at the CEA-Leti, we developed a contact technology that is fully compatible with a Si-Fab line. This implies studies ranging from surface preparation [16], [17] and solid-state reaction [18]–[21] to electrical results [22], [23] and integration schemes [24]–[26]. A strong experience was obtained in 200 mm with the development of a CMOS-compatible contact technology [26]. These developments played a part in the realization of hybrid III-V/Silicon lasers integrated on a 200 mm fully CMOS-compatible silicon photonics platform [27], [28]. Technological modules, contact technology in particular, are now being developed to obtain a 300 mm Si photonics platform.

The study of the Ni / InP system [29]–[33] showed that several phases formed during the solid-state reaction of a Ni thin film with an InP layer. We recently demonstrated the following phase formation sequence [32], [33]. At low temperature, the Ni thin film was present along with an intermixing layer of NiₓInP in an amorphous state. Beyond a threshold temperature, the system evolved towards a crystalline state where the coexistence of 3 phases was reported, namely Ni₂P, Ni₃P and Ni₂InP. At higher temperatures, the agglomeration of Ni₂P and In was evidenced and the contacts became non-ohmic [22], [33]. To overcome this issue, a technological solution was proposed. As Ni₂P was reported to lower the contact resistivity [34], a target, only made of this material, was designed and used to directly sputter the most favorable phase – and only this one – on III-V layers. The results obtained in 200 mm were strongly encouraging [22], [25], [26].

Based on the promising results obtained in 200 mm, we decided to develop a Ni₂P process on a 300 mm platform. We believe that the results obtained in 200 mm are not directly transposable in 300 mm. From a materials point of view, it is reasonable to imagine that similar results should be obtained in 300 mm. Nevertheless, III-V materials are very sensitive surfaces and the impact of process conditions should not been underestimated. For instance, the power density involved are higher in 300 mm and the subsequent impact on III-V surfaces could be deleterious for the contact properties. In addition, the deposition pressure is different. This parameter might have an impact on the Ni₂P film properties. It is hence mandatory in the framework of developing a 300 mm technology to assess these potential impacts on contact's properties and technology.

In this study, we thus propose the development of Ni₂P thin films on a 300 mm platform by magnetron sputtering, their physico-chemical characterization and their integration on III-V layers, n-InP and p-InGaAs in particular, to evaluate their potential in terms of contact layer for Si photonics

<figure><img src="image_3.png" /><figcaption>**FIGURE 1.** Monitoring of the wafer-to-wafer resistivity and thickness uniformity over several batches of 25 wafers.</figcaption></figure>

devices. These results were partially reported in the 20th International Workshop on Junction Technology (IWJT) [35].

## II. EXPERIMENTAL SECTION

A specific target of Ni₂P was designed by JX Nippon Mining & Metals Corp. and mounted into a magnetron sputtering chamber (RF-PVD) of an Endura 300 mm platform. A standard protocol was then applied to qualify this process and define optimal process parameters. First, we performed a burn-in of the target to condition it. Then, we made metal and particle contamination tests to ensure that no cross contamination would happen between the deposition platform and characterization tools. After a tuning of the capacitance and a target-to-wafer spacing adjustment, we carried out a fine tuning of the deposition pressure – controlled by the Ar flow – and of RF and DC powers. The deposition process was realized at room temperature. Applying these optimal process parameters, we performed a marathon test consisting in the monitoring of the thickness, within wafer and wafer-to-wafer thickness uniformity over several batches of 25 wafers. Results highlighted that the process was quite stable and reproducible as shown in Fig. 1. Finally, we calibrated the process to obtain a correlation between the deposition duration and the thickness of Ni₂P films – their thickness was ranging from 5 nm up to 60 nm.

We performed several physicochemical characterizations on Ni₂P blanket thin films such as X-ray Reflectivity (XRR), X-ray Diffraction (XRD) in Bragg-Brentano geometry and in-plane configuration, Wavelength Dispersive X-ray Fluorescence (WD-XRF) and 4-point probe sheet resistance. All the above-mentioned characterizations were performed on 300 mm Si wafers with a 100 nm thick thermal silicon oxide grown at their surface.

Finally, we integrated the Ni₂P films on III-V materials, namely InP and InGaAs layers. We performed some of the developments on III-V blanket layers but most of the tests were done on samples dedicated to electrical
<figure><img src="image_4.png" /><figcaption>FIGURE 2. In-plane diffraction pattern of a 55 nm thick Ni₂P film.</figcaption></figure>

characterizations. The latter were fabricated using 300 nm doped epilayers (Si-doped n-InP, N<sub>d</sub> = 5 × 10<sup>18</sup> at.cm<sup>-3</sup> or Zn-doped p-In<sub>0.53</sub>Ga<sub>0.47</sub> As with N<sub>a</sub> = 2 × 10<sup>19</sup> at.cm<sup>-3</sup>) on semi-insulating InP substrates. Transfer length measurement (TLM) structures were fabricated according to the procedure already described in previous works [23], [33] to extract the contact resistivity.

Each extracted contact resistivity is the average value of 9 TLM measurements performed on 9 different unit dies. The error bars shown in the various charts contain two contributions: (i) the variability over 9 unit dies, specific to each sample, and (ii) the measurement repeatability, specific to the measurement tool. The measurement repeatability was calculated by performing TLM measurements 9 times on the same die. Each of the 9 extracted contact resistivity values was normalized by the average value of the 9 contact resistivity values. The standard deviation of the series of values was calculated and normalized as well: it is equal to ± 1.4%, which means that the measurements are highly repeatable.

### III. RESULTS AND DISCUSSION

#### A. DEVELOPMENT OF Ni₂P FILMS ON A 300 MM PLATFORM

Fig. 2 shows the in-plane diffraction pattern of a 55 nm thick Ni₂P film.

The main diffraction peaks located at 40.9°, 44.9°, 47.5° and 54.5° were linked to 111, 021, 210 and 002 diffraction lines of the hexagonal Ni₂P phase (PDF File #03-065-9706), respectively. Additional small peaks highlighted by black arrows in Fig. 2 could be related to the presence of small amounts of the Ni₁₂P₅ phase (PDF File #00-022-1190). The presence of such impurities is inherent to the target fabrication process and its presence was confirmed by XRD analyses of the raw powder, the sintering plate and the Ni₂P final target (not shown here).

<figure><img src="image_5.png" /><figcaption>FIGURE 3. XRR pattern and modeling obtained for a Ni₂P (9 nm) / SiO₂ (100 nm) / Si sample.</figcaption></figure>

We measured the sheet resistance of 10 nm-thick Ni₂P thin films deposited on 300 mm Si wafers with a 100 nm thick thermal silicon oxide grown at their surface. An average resistivity of 218 ± 1 μΩ.cm and an average non-uniformity of 2.7 ± 0.1% were obtained (see Fig. 1). As far as resistivity is concerned, Appelbaum *et al.* reported a value of 270 μΩ.cm for as-sputtered Ni₂P films [34]. They observed a decrease of the resistivity of the film with the increase of annealing temperature; this tendency was linked to the grain growth. In our previous studies, for the developments we made in 200 mm and depending on the pressure conditions, the Ni₂P film resistivity was ranging between 160 and 240 μΩ.cm. In the current study, the value of 220 μΩ.cm is thus in line with the previous data.

We performed X-ray reflectivity (XRR) analyses to obtain the thickness and the electronic density of Ni₂P thin films. Fig. 3 exhibits the XRR pattern and the corresponding modeling obtained for a 9 nm thick Ni₂P film. The inset table reproduces the thickness and the density of the layers composing the sample.

Without any capping layer, the XRR analyses showed that the Ni₂P films tended to oxidize and a thin oxide layer – typically 0.2 up to 0.5 nm thick – was systematically observed on the sample surface. We measured a density of about 6.9 g/cm³ for the Ni₂P films. This value is in line with the value calculated for the bulk material [36].

After calibration based on pure Ni and InP substrate, we performed Wavelength Dispersive X-ray Fluorescence (WD-XRF) analyses of Ni₂P thin films. We obtained a strong XRF signal of Ni K<sub>α</sub> and P K<sub>α</sub> lines without any noise as shown in Fig. 4.

We performed WD-XRF analyses for Ni₂P films with thicknesses ranging between 10 and up to 30 nm. We demonstrated that a good correlation between the film thickness and the signal intensity was obtained and that the analyses
<figure><img src="image_6.png" /><figcaption>**FIGURE 4.** XRF signals of (a) Ni Kα and (b) P Kα lines obtained for various Ni₂P / SiO₂ (100 nm) / Si samples.</figcaption></figure>

were quite reproducible for a given thickness. The quantification of the obtained XRF signal led to the following ratio: 62 at.% of Ni and 38 at.% of P, in line with the expected stoichiometry of the films.

We then implement and integrate Ni₂P thin films on n-InP and p-InGaAs-based structures to evaluate their potential as metallization layer for Si photonics devices.

## B. INTEGRATION OF Ni₂P FILMS ON III-V MATERIALS

### B.1. EVOLUTION OF THE Ni₂P / INP SYSTEM WITH TEMPERATURE

In Section III-A, we highlighted that Ni₂P films were sensitive to air and that a thin oxide layer grew at their surface without any protection. We thus deposited 20 nm thick Ni₂P thin films on InP layers and capped them by a TiN layer to protect them from atmosphere contamination. The samples were then annealed in a N₂ environment in a rapid

<figure><img src="image_7.png" /><figcaption>**FIGURE 5.** θ/2θ XRD patterns obtained in Bragg-Brentano geometry for TiN (7 nm) / Ni₂P (20 nm) / InP samples annealed in a N₂ environment in a rapid thermal annealing (RTA) furnace for 60 s at temperatures ranging from 250 °C up to 500 °C.</figcaption></figure>

thermal annealing (RTA) furnace for 60 s at temperatures ranging from 250 °C up to 500 °C. θ/2θ XRD patterns (shown in Fig. 5) were recorded to follow a potential evolution of phases in presence when increasing the annealing temperature.

The XRD patterns in Fig. 5 exhibit diffraction peaks in common with the one shown in Fig. 2 at 40.8°, 44.7°, 47.4° and 54.5°. These peaks are due to 111, 021, 210 and 002 diffraction lines of the hexagonal Ni₂P phase, respectively. An additional diffraction peak due to the Ni₂P phase is visible at 2θ = 31.9°. It is due to the 011 diffraction line. In addition, diffraction peaks due to the InP layer are located at 2θ = 30.4° and 63.3°. They are linked to 200 and 400 diffraction lines of InP, respectively.

We did not observe any phase evolution over the whole investigated temperature range, i.e., apart from diffraction peaks due to the InP layer, no diffraction peak could be related to another phase than Ni₂P. On the other hand, the intensity of some of the diffraction peaks related to this phase increased with temperature. For instance, it was the case for the 111 diffraction line. As the Ni₂P deposition was performed at room temperature, the crystallinity of the Ni₂P layer can evolve with increasing temperature.

Ni₂P thin films remain thus stable over the whole investigated temperature range. This behavior was expected since Ni₂P was reported to be thermodynamically stable on InP at 470 and 600 °C [37].

### B.2. STUDY OF THE CONTACT RESISTIVITY ON N-INP

We integrated Ni₂P thin films on TLM structures to extract the contact resistivity of the Ni₂P / n-InP system in the as-deposited state and after various rapid thermal annealing (RTA) performed in a N₂ environment, for 60 s and at
<figure><img src="image_8.png" /><figcaption>**FIGURE 6.** Electrical properties of Ni/n-InP (square symbols), Ni₀.₉Pt₀.₁/n-InP (triangle symbols) and Ni₂P/n-InP (circle symbols) systems extracted from Transfer Length Method (TLM) measurements in the as-deposited state and after various RTA.</figcaption></figure>

temperatures ranging from 250 °C up to 500 °C. The results are shown in Fig. 6 (circle symbols).

The Ni₂P-based contact was ohmic at each investigated temperature, and the contact resistivity values ranged from 1.9 up to 3.2 × 10⁻⁵ Ω·cm², which constitutes a particularly narrow dispersion of values, within the calculated error bar range. These values were below the target imposed by the integration requirements and fixed at 7.2 × 10⁻⁵ Ω·cm² for n-InP layers [23]. This target is symbolized by an horizontal red line in Fig. 6.

The overall absence of variation of the electrical properties is consistent with the absence of phase evolution previously highlighted by XRD characterization. The Ni₂P phase remains stable over the entire investigated temperature range without any phase evolution, therefore granting the electrical stability of the Ni₂P/n-InP system. The small evolution observed for the contact resistivity values on the [250–350 °C] temperature range can be related to the evolution of the layer’s crystallinity and the grain growth with increasing temperature. Beyond 350 °C, the contact resistivity was stable.

Fig. 6 also shows a comparison between the electrical properties of the Ni₂P/n-InP system and two other Ni-based contact metallizations previously investigated, namely Ni (square symbols) and Ni₀.₉Pt₀.₁ (triangle symbols) [21], [33]. For all the systems, an initial metal thickness of 20 nm capped by a TiN layer was deposited on the n-InP layers. Out of the three Ni-based investigated contacts, it should be reminded that both Ni and Ni₀.₉Pt₀.₁ led to an evolution of the phase formation sequence over the investigated temperature range [21], [33], while Ni₂P remained the sole crystallized phase up to 500 °C included. From an electrical standpoint, Ni₀.₉Pt₀.₁ led to the highest contact resistivity,

even though it remained compatible with the requirements of the integration [23]. The formation of Pt-based compounds such as Pt₃In₇ [21] was probably not favorable for the contact resistivity. The contact resistivity reached in the case of Ni and Ni₂P were overall the same on the [250–350 °C] temperature range (2 – 3 × 10⁻⁵ Ω·cm²).

These results highlighted that contact resistivity values were independent of initial thin film resistivities. Indeed, resistivity values were about 13.5, 27 and 200 µΩ·cm for 20 nm-thick Ni, Ni₀.₉Pt₀.₁ and Ni₂P films, respectively. The highest resistive thin film (namely Ni₂P) led to the lowest contact resistivity values. The predominant criteria to obtain low contact resistivity values, even for relative large contact area (contact pads were 200 µm × 200 µm), are thus the quality of the contact interface, phases in presence and the overall stability of the system.

While with Ni and Ni₀.₉Pt₀.₁, the contacts were ohmic up to 350 and 400 °C respectively, with Ni₂P the contacts were however ohmic up to 500 °C included yielding a contact resistivity of 3.2 × 10⁻⁵ Ω·cm². In conclusion, due to (i) the thermodynamic stability, (ii) the broaden ohmicity range, and (iii) the lowered contact resistivity, out of the three Ni-based metallizations, Ni₂P exhibited the most promising properties in the scope of n-InP contact integration.

### B.3. IMPACT OF INTEGRATION AND LONG-TERM THERMAL STRESS

We also studied the impact of subsequent integration steps – namely W-plug filling and back end of line (BEOL) – and long-term thermal stress on the contact properties of the Ni₂P / n-InP system. To do this, TLM structures were submitted to 2 kinds of annealing. Annealing 1 consisted in two consecutive annealing processes: the first one emulating the thermal budget involved during the W-plug filling, with a temperature of 450 °C for 180 s, and the second one expected to reproduce the thermal budget involved during the BEOL, with a temperature of 400 °C for 30 min. Annealing 2 aimed at estimating the impact of long-term thermal stress in order to estimate the contact reliability. To do so, an annealing of 100 °C during 1 week was performed on the samples.

Fig. 7 presents the contact resistivity at different stages, namely (i) after various RTA (left bar chart), (ii) after various RTA followed by Annealing 1 (middle bar chart) and (iii) after various RTA + Annealing 1 followed by Annealing 2 (right bar chart).

In the previously as-deposited sample and up to a 350 °C RTA included, it appeared that after Annealing 1 (middle bar chart) the extracted contact resistivity slightly increased. On the contrary, in the case of samples which underwent RTA from 400 °C and up to 500 °C, the contact resistivity extracted after Annealing 1 remained within the error bar range, with contact resistivity between 2.9 and 3.6 × 10⁻⁵ Ω·cm². Each extracted contact resistivity value however remained below integration requirements – horizontal red line in Fig. 7 at 7.2 × 10⁻⁵ Ω·cm². This suggests that for samples which underwent RTA below or equal to
<figure><img src="image_9.png" /><figcaption>**FIGURE 7.** Contact resistivity of the Ni₂P/n-InP contact extracted from Transfer Length Method measurements after various RTA (left bar chart), after RTA + Annealing 1 (middle bar chart) and after RTA + Annealing 1 + Annealing 2 (right bar chart).</figcaption></figure>

350 °C, the W-plug filling and BEOL would most likely induce a light degradation of the electrical properties of the contact, while a higher temperature of RTA submitted to the system prior to integration is expected to prevent the latter from further degradation. The Ni₂P films being deposited at room-temperature, a temperature of 400 °C seems necessary to stabilize the layer and ensure the subsequent contact stability. So far, the best configuration of this system is reached by submitting the contact to a 400 °C RTA prior to integration.

After the emulation of long-term thermal stress (Annealing 2, right bar chart), each sample exhibited either a light increase of contact resistivity compared to right after Annealing 1, or a constant contact resistivity (within the error bar range). Each value nonetheless still remained below integration requirements. This suggests that long-term thermal stress which aimed at reproducing several use of the laser device would induce a slight degradation of the system regardless of the pre-thermal budget submitted to the latter.

We observed the layer morphology of samples submitted to RTA, followed by subsequent Annealing 1 and Annealing 2 by scanning electronic microscopy (SEM). Fig. 8 shows a representative example of a sample in the as-deposited state and after a 450 °C RTA, with subsequent Annealing 1 and Annealing 2.

Even after a series of various annealings (RTA, Annealing 1, Annealing 2), Ni₂P films were continuous, homogeneous and flat, and the stack thicknesses appeared to be identical to an as-deposited sample. Such layer morphology highlights the strong stability of the system, and suggests that the W-plug filling and BEOL followed by long-term thermal stress would not lead to degraded morphological properties.

<figure><img src="image_10.png" /><figcaption>**FIGURE 8.** Scanning Electron Microscopy of a top electrode / TiN / Ni₂P / n-InP contact (a) in the as-deposited state and (b) after a 450 °C RTA, with subsequent Annealing 1 and Annealing 2.</figcaption></figure>

If we compare the results obtained in the current study for Ni₂P metallization with the ones obtained for Ni [33] or Ni₀.₉Pt₀.₁ [21], [38], we can conclude that, due to their high thermal stability in terms of electrical and morphological properties, their high robustness toward integration steps and long-thermal stress impact, Ni₂P thin films exhibited the best performances among all the Ni-based metallizations we investigated to contact n-InP layers.

## B.4. INTEGRATION ON P-INGAAS

The elaboration of III-V/Si hybrid lasers implies the development of ohmic contacts not only on n-InP but also on p-InGaAs layers [27], [28], [39]. In this way, we implemented Ni₂P thin films developed on 300 mm platform on p-InGaAs layers as well to study the possibility of using this film for simultaneous p- and n-contact integration.

Fig. 9 presents the contact resistivity at different stages, namely (i) after various RTA (left bar chart), (ii) after various RTA followed by Annealing 1 (middle bar chart) and (iii) after various RTA + Annealing 1 followed by Annealing 2 (right bar chart).

After RTA (left bar chart) and up to 400 °C included, p- contacts were non-ohmic. After a 450 °C and 500 °C RTA, contacts became ohmic, reaching 1.3 and 1.1 × 10⁻⁴ Ω·cm², respectively. It should be highlighted that these values were above the expected integration requirements fixed at 1.4 × 10⁻⁵ Ω·cm² for the envisioned devices [23] (horizontal red line in Fig. 9). The use of Ni₂P thin films as contact layer on p-In₀.₅₃Ga₀.₄₇As thus led to contact resistivity
<figure><img src="image_11.png" /><figcaption>FIGURE 9. Contact resistivity of the Ni₂P/p-InGaAs contact extracted from Transfer Length Method measurements after various RTA (left bar chart), after RTA + Annealing 1 (middle bar chart) and after RTA + Annealing 1 + Annealing 2 (right bar chart).</figcaption></figure>

values above integration requirements at each investigated temperatures.

After Annealing 1 (middle bar chart), the samples that had previously exhibited a non-ohmic behavior showed an ohmic behavior with contact resistivity values ranging between 8.9 × 10⁻⁵ Ω.cm² up to 1.1 × 10⁻⁴ Ω.cm². The samples previously annealed with a RTA at 450 °C or 500 °C maintained their ohmicity with similar contact resistivity values. As a result, regardless of the electrical properties of the contacts prior to Annealing 1, the contact resistivity values extracted after Annealing 1 are ranging in a narrow dispersion of values but still above the expected target. W-plug filling and BEOL are likely not to induce any degradation of the electrical properties of the contacts, and tend to contribute to the stabilization of the electrical properties of the system. A temperature of 400-450 °C appears as a threshold temperature to obtain a layer with stabilized electrical properties (but above the expected target).

Annealing 2 (right bar chart) induced either slight increases of contact resistivity, or no significant change of values (within the error bar range). Consequently, it is safe to deduce that the long-term thermal stress which aims at reproducing several use of the laser device would not induce a significant damage of the electrical properties of the contact. The overall extracted contact resistivity values are however significantly above the target, and therefore do not meet the contact requirements.

We studied the layer morphology of Ni₂P / p-InGaAs samples submitted to RTA, followed by subsequent Annealing 1 and Annealing 2 by scanning electronic microscopy (not shown here). The morphology was highly stable, and it can be projected that the W-plug filling, Back End Of Line

and long-term thermal stress would not lead to a degraded morphological state.

On p-In₀.₅₃Ga₀.₄₇ As the Ni₂P metallization presents contact resistivity values above the expected target at each investigated stage of the reaction. This is the case both before and after the emulation of contact integration and long-term thermal stress. Consequently, the contact requirements are not met for the p-contact, which disqualifies the Ni₂P metallization for simultaneous p- and n-contact integration.

## IV. CONCLUSION

In this study, we tuned optimal process parameters to obtain Ni₂P thin films on a 300 mm platform by magnetron sputtering of a Ni₂P target. We obtained stable and reproducible thin films of hexagonal Ni₂P phase films with small impurities of Ni₁₂P₅. The film density was 6.9 g/cm³ with a ratio of 62 at.% of Ni and 38 at.% of P, in line with expected or reported values.

We implemented and integrated the Ni₂P films on III-V structures to study their potential use as contact layer for Si photonics devices. The results obtained on n-InP were quite promising. Nevertheless, on p-InGaAs, Ni₂P did not meet the contact requirements. Consequently, in the scope of simultaneous n- and p-contact integration for III-V/Si hybrid laser integration, one should consider other alternatives, such as Ti-based metallization [23].

On the other hand, due to its remarkable thermal stability and low contact resistivities, Ni₂P metallization exhibited the best results among all the Ni-based metallization studied for contacting n-InP layers. In this way, for sequential integration (in cases where n- and p-metallization are not performed with the same metal and at the same step), Ni₂P thin films are the best choice for contacting n-InP layers. For contacting p-InGaAs layers, one should consider the use of Ni metallization [38], [40].

## ACKNOWLEDGMENT

The authors would like to thank JX Nippon Mining & Metals Corp. for the fruitful collaboration around Ni₂P target design and fabrication.

The authors are thankful to E. Nolot (CEA-Leti) for the WD-XRF characterizations, to K. Dabertrand (STMicroelectronics) for the SEM observations, to P. Grosse (CEA-Leti) for his assistance during the electrical characterizations, to G. Zucchi (CEA-Leti) for his assistance on target qualification and to V. Amalbert (CEA-Leti) for his contribution on the TLM structure processing.

This work was inspired by the fruitful discussions the author had with our colleagues E. Ghegin and F. Nemouchi. The authors are very grateful to them.

## REFERENCES

[1] R. Soref, "The past, present, and future of silicon photonics," *IEEE J. Sel. Topics Quantum Electron.*, vol. 12, no. 6, pp. 1678-1687, Nov./Dec. 2006.

[2] G. T. Reed, Ed., *Silicon Photonics: The State of the Art*. Chichester, U.K.: Wiley, 2008.
[3] X. Chen et al., "The emergence of silicon photonics as a flexible technology platform," *Proc. IEEE*, vol. 106, no. 12, pp. 2101–2116, Dec. 2018.

[4] D. Thomson et al., "Roadmap on silicon photonics," *J. Opt.*, vol. 18, no. 7, 2016, Art. no. 073003.

[5] G. Roelkens et al., "III-V-on-silicon photonic devices for optical communication and sensing," *Photonics*, vol. 2, no. 3, pp. 969–1004, 2015.

[6] T. Matsumoto et al., "Hybrid-integration of SOA on silicon photonics platform based on flip-chip bonding," *J. Lightw. Technol.*, vol. 37, no. 2, pp. 307–313, Jan. 2019.

[7] G. Roelkens et al., "III-V/Si photonics by die-to-wafer bonding," *Mater. Today*, vol. 10, nos. 7–8, pp. 36–43, 2007.

[8] L. Sanchez, F. Fournel, B. Montmayeul, L. Bally, B. Szelag, and L. Adelmini, "Collective die direct bonding for photonic on silicon," *ECS Trans.*, vol. 86, no. 5, pp. 223–231, 2018.

[9] J. Dunn and G. B. Stringfellow, "Annealed AuGe based ohmic contacts on InP with ion milling prior to metallization," *J. Electron. Mater.*, vol. 19, no. 2, pp. L1–L3, 1990.

[10] M. Cooke, "Making III-V contact with silicon substrates," *Semicond. Today*, vol. 6, no. 3, pp. 106–110, 2011.

[11] A. Katz, B. E. Weir, and W. C. Dautremont-Smith, "Au/Pt/Ti contacts to p-In₀.₅₃Ga₀.₄₇As and n-InP layers formed by a single metallization common step and rapid thermal processing," *J. Appl. Phys.*, vol. 68, no. 3, pp. 1123–1128, 1990.

[12] L. Grenouillet et al., "CMOS compatible contacts and etching for InP-on-silicon active devices," in *Proc. 6th IEEE Int. Conf. Group IV Photon. (GFP)*, Sep. 2009, pp. 196–198.

[13] S. Jain, M. Sysak, M. Swaidan, and J. Bowers, "Silicon fab-compatible contacts to n-InP and p-InGaAs for photonic applications," *Appl. Phys. Lett.*, vol. 100, no. 20, 2012, Art. no. 201103.

[14] N. Y. Pacella, K. Mukherjee, M. T. Bulsara, and E. A. Fitzgerald, "Silicon CMOS ohmic contact technology for contacting III-V compound materials," *ECS J. Solid State Sci. Technol.*, vol. 2, no. 7, pp. P324–P331, 2013.

[15] H. Hahn, M. Sousa, and L. Czornomaz, "Low-resistive, CMOS-compatible ohmic contact schemes to moderately doped n-InP," *J. Phys. D Appl. Phys.*, vol. 50, no. 23, 2017, Art. no. 235102.

[16] P. Rodriguez et al., "Cleaning of InGaAs and InP layers for nanoelectronics and photonics contact technology applications," *ECS Trans.*, vol. 69, no. 8, pp. 251–259, 2015.

[17] N. Coudurier et al., "Plasma surface preparation of III-V materials: Quasi in-situ XPS measurements and integration guidelines," *ECS Trans.*, vol. 92, no. 2, pp. 73–83, 2019.

[18] S. Zhoui et al., "Reaction of Ni film with In₀.₅₃Ga₀.₄₇As: Phase formation and texture," *J. Appl. Phys.*, vol. 120, no. 13, 2016, Art. no. 135304.

[19] E. Ghegin et al., "Phase formation sequence in the Ti/InP system during thin film solid-state reactions," *J. Appl. Phys.*, vol. 121, no. 24, 2017, Art. no. 245311.

[20] S. Bensalem et al., "Study of the Ti/InGaAs solid-state reactions: Phase formation sequence and diffusion schemes," *Mater. Sci. Semicond. Process.*, vol. 113, Jul. 2020, Art. no. 105038.

[21] F. Boyer, K. Dabertrand, P. Gergaud, M. Grégoire, Q. Rafhay, and Ph. Rodriguez, "Platinum redistribution in the Ni₀.₉Pt₀.₁/InP system: Impact on solid-state reaction and layer morphology," *Mater. Sci. Semicond. Process.*, vol. 128, no. 6, 2021, Art. no. 105731.

[22] E. Ghegin et al., "CMOS-compatible contacts to n-InP," *IEEE Trans. Electron Devices*, vol. 64, no. 11, pp. 4408–4414, Nov. 2017.

[23] F. Boyer et al., "Integration, BEOL, and thermal stress impact on CMOS-compatible titanium-based contacts for III-V devices on a 300-mm platform," *IEEE Trans. Electron Devices*, vol. 67, no. 6, pp. 2495–2502, Jun. 2020.

[24] E. Ghegin et al., "Metallurgical studies of integrable Ni-based contacts for their use in III-V/Si heterogeneous photonics devices," in *Proc. IEEE Silicon Nanoelectron. Workshop (SNW)*, Jun. 2016, pp. 214–215.

[25] P. Rodriguez, E. Ghegin, and F. Nemouchi, "CMOS-compatible contact technology for Si photonics," in *Proc. 18th Int. Workshop Junction Technol. (IWJT)*, Mar. 2018, pp. 1–6.

[26] P. Rodriguez et al., "Development of a CMOS-compatible contact technology for III-V materials and Si photonics," *Jpn. J. Appl. Phys.*, vol. 59, Mar. 2020, Art. no. SL0801.

[27] B. Szelag et al., "Hybrid III-V/silicon technology for laser integration on a 200 mm fully CMOS-compatible silicon photonics platform," *IEEE J. Sel. Topics Quantum Electron.*, vol. 25, no. 5, Sep./Oct. 2019, Art. no. 8201210.

[28] K. Hassan et al., "Hybrid III-V/silicon CMOS-compatible technology for laser integration on 200mm and 300mm platforms (conference presentation)," in *Proc. Integr. Photon. Platforms Fundamental Res. Manuf. Appl.*, vol. 11364, 2020, Art. no. 113640Y.

[29] D. G. Ivey, R. Bruce, and G. R. Piercy, "Electron microscopy characterization of Au/Ni contacts to p-type InP," *J. Electron. Mater.*, vol. 17, no. 5, pp. 373–380, Sep. 1988.

[30] N. S. Fatemi and V. G. Weizer, "The structural and electrical properties of low-resistance Ni contacts to InP," *J. Appl. Phys.*, vol. 73, no. 1, pp. 289–295, 1993.

[31] S. E. Mohney and Y. A. Chang, "Phase formation in Ni/InP contacts," *J. Appl. Phys.*, vol. 78, no. 2, pp. 1342–1347, 1995.

[32] E. Ghegin et al., "Phase formation in the Ni/n-InP contacts for heterogeneous III/V-silicon photonic integration," *Microelectron. Eng.*, vol. 156, pp. 86–90, Apr. 2016.

[33] P. Boyer et al., "Integration of the Ni/InP system on a 300 mm platform for III-V/Si hybrid lasers," *J. Vac. Sci. Technol. B*, vol. 38, no. 1, 2020, Art. no. 012209.

[34] A. Appelbaum, M. Robbins, and F. Schrey, "Sputtered Ni-P as an ohmic contact to n-InP, p-InGaAs and as a diffusion barrier," *IEEE Trans. Electron Devices*, vol. 34, no. 5, pp. 1026–1032, May 1987.

[35] F. Boyer et al., "Ni 2P contact technology for 300 mm Si photonics platform," in *Proc. 20th Int. Workshop Junction Technol. (IWJT)*, 2021, pp. 1–4.

[36] K. Persson, "Materials data on Ni 2P (SG:189) by materials project," Nov. 2014, doi: 10.17188/1183670.

[37] S. E. Mohney and Y. A. Chang, "Phase equilibria and ternary phase formation in the In-Ni-P system," *J. Mater. Res.*, vol. 7, no. 4, pp. 955–960, 1992.

[38] F. Boyer, "Integration of CMOS-compatible contacts on III-V materials for Si photonics applications in 300 mm," Ph.D. dissertation, Dept. Nanoelectron. Nanotech., Université Grenoble Alpes, Saint-Martin-d'Hères, France, 2020.

[39] K. Hassan et al., "Technological advances on CMOS compatible hybrid III-V/Si lasers in 200 mm platform," in *Proc. Int. Conf. Solid State Devices Mater. (SSDM)*, Sep. 2018, doi: 10.7567/SSDM.2018.H-3-01.

[40] F. Boyer et al., "Nickel-based CMOS-compatible contacts on p-In₀.₅₃Ga₀.₄₇As for III-V/silicon hybrid lasers," in *Proc. IEEE Int. Interconnect Technol. Conf. (IITC)*, 2020, pp. 121–123.

<figure><img src="image_12.png" /></figure>

**FLORE BOYER** received the M.S. degree from the National Institute of Applied Sciences, Lyon, France, in 2017, and the Ph.D. degree from Grenoble Alpes University, France, in 2020. She is currently a Characterization and Modeling Engineer with STMicroelectronics, Crolles, France.

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**ROMAIN FAMULOK** has been a Senior Technician with CEA-Leti, since 2013. His work is mainly focused on PVD and CVD deposition processes for contact technology and other application. Before this position, he worked seven years with the Cleaning and Bonding Team, SOITEC.
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**STÉPHANE MINORET** has been a Research Engineer with Advanced Materials Deposition Department, CEA-Leti, since 2003. He is an Expert of contact plug and damascene process integration. His area of expertise is mainly focused on metal deposition by PVD and CVD.

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**NICOLAS COUDURIER** received the Ph.D. degree from Université Grenoble Alpes, in 2014. He is a Research Engineer with the Advanced Materials Deposition Laboratory, CEA-Leti. His research interests are surface preparation and CMOS-compatible metallization for optoelectronics devices.

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**CHRISTOPHE JANY** received the Ph.D. degree in materials science from the University of Paris XIII, France, in 1998. He studied thin film technology of CVD Diamond on Silicon. He joined the Alcatel Research & Innovation Center, Marcoussis, in 1999 to develop optical III-V technology (InP-like), including high speed (>40 Gb/s) integrated Lasers and electro-absorption Modulators, and PhotoDetectors (InP/InGaAs-like). Within Bell Labs France, he contributed to the development of new InP-based platforms integration using SAG and SIBH Technologies. Then, with III-V Lab, he became expert in the field of photonic integration with over 20 years of experience for manufacturing components: InP-based Photonic Integrated Circuits (PICs). For ten years, he develops the hybrid technology III-V on SOI, leading to the Silicon Photonics chips. He main focuses to make compatible manufacturing III-V wafers bonded on CMOS material. In 2013, he joined CEA-Leti to further develop fabrication technology of III-V materials on SOI Wafers, mainly for silicon photonics (Edge-emitting lasers /EELs and vertical cavity surface emitting lasers/Vcsel) and Solar applications. Since 2016, he investigated optical devices in the field of direct GaAs/InP-on-Si epitaxy. Recently, he participated in the development of technologies on SiC. Christophe Jany (CEA-Leti Expert Senior) has authored or coauthored more than 170 scientific publications in peer reviewed journals, and 8 patents. He is currently the Head of the Front-End Processes Laboratory (100-150 mm line), CEA-Leti.

<figure><img src="image_17.png" /></figure>

**PATRICE GERGAUD** is a CEA International Expert in X-ray characterization in micro and nanotechnologies, with more than 25 years of experience in this field. After ten years as a Senior Researcher with the French National Center for Scientific Research, in 2006, he joined the nano-characterization platform of the CEA-Minatec Campus, Grenoble and is the Group Leader of the X-Ray Lab. His work is aimed at a better understanding of stresses in microelectronic devices. He has considerable experience in X-ray diffraction and synchrotron radiation. He has authored or coauthored more than 170 articles. His main field of interest is the structure and the mechanical properties of thin films and multilayers.

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**PHILIPPE RODRIGUEZ** received the Ph.D. degree from Lyon 1 University in materials chemistry in 2007 for his work on metalorganic vapour phase epitaxy growth of B(In)GaAs epilayers. He is a Research Engineer and the Head of the Advanced Materials Deposition Laboratory, Semiconductor Platform Division, CEA-Leti. From 2007 to 2009, he worked for the CNRS (French National Center for Scientific Research) and developed coating methods on structured supports for process intensification applications. In 2009, he started his career with CEA (French Alternative Energies and Atomic Energy Commission). First, he worked on the coating and fluidization of dense powder by fluidized bed metalorganic chemical vapor deposition for the development of new nuclear fuels (2009–2011). Then, he developed silica permeation barriers by magnetron sputtering for Laser Megajoule gaseous targets (2011–2013). Finally, he joined the CEA-Leti Institute. Since 2013, his research activity is mainly focused on advanced contact technologies for electronics and photonics applications. He develops contact metallization for advanced CMOS and photonics devices [Si, Ge(Sn), III-V, and GaN materials] and also deals with the surface preparation and interface modulation prior to metallization. He led the CEA-Leti's Contact Team from 2017 to 2020 and became the Head of the Advanced Materials Deposition Laboratory in 2020. He has authored and coauthored of about 80 articles in peer reviewed journals, 100 international conference papers, two book chapters, and ten patents.