# System-Level Optimization of a DAC for Hearing-Aid Audio Class D Output Stage

Peter Pracný, Ivan H. Jørgensen, Erik Bruun

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Peter Pracný, Ivan H. Jørgensen, Erik Bruun. System-Level Optimization of a DAC for Hearing-Aid Audio Class D Output Stage. 4th Doctoral Conference on Computing, Electrical and Industrial Systems (DoCEIS), Apr 2013, Costa de Caparica, Portugal. pp.647-654, 10.1007/978-3-642-37291-9_70. hal-01348812

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# System-level Optimization of a DAC for Hearing-aid Audio Class D Output Stage

Peter Pracný, Ivan H. H. Jørgensen, Erik Bruun,

Department of Electrical Engineering, Technical University of Denmark,
2800 Kgs. Lyngby, Denmark, pp@elektro.dtu.dk

**Abstract.** This paper deals with system-level optimization of a digital-to-analog converter (DAC) for hearing-aid audio Class D output stage. We discuss the ΣΔ modulator system-level design parameters – the order, the oversampling ratio (OSR) and the number of bits in the quantizer. We show that combining a reduction of the OSR with an increase of the order results in considerable power savings while the audio quality is kept. For further savings in the ΣΔ modulator, overdesign and subsequent coarse coefficient quantization are used. A figure of merit (FOM) is introduced to confirm this optimization approach by comparing two ΣΔ modulator designs. The proposed optimization has impact on the whole hearing-aid audio back-end system including less hardware in the interpolation filter and half the switching rate in the digital-pulse-width-modulation (DPWM) block and Class D output stage.

**Keywords:** Sigma-Delta Modulator; Digital-to-Analog Converter; Interpolation Filter; Class D; Hearing Aid; Low Voltage, Low Power

## 1 Introduction

The hearing-aids of today are devices where strict specifications are applied. High audio quality and the need for longer operation time combined with the desire to shrink the size of the hearing-aid devices to make it virtually invisible leaves less space for the battery and integrated circuits. These demands contradict each other, making the current consumption of the electronics inside the hearing-aid one of the crucial parameters for the design. To find the optimum balance between the design parameters in every part of a hearing-aid device is therefore of vital importance. This includes the back-end of the audio signal processing path (see Fig.1). As part of the digital-to-analog conversion a digital ΣΔ modulator is usually used in audio applications. Due to the oversampling nature of the ΣΔ modulator an interpolation filter is needed prior to the modulator. In the case of a multi-bit ΣΔ modulator, to be able to connect the output of the ΣΔ modulator to the input of the Class D output-stage a DPWM block that turns the ΣΔ signal into pulse width modulation, is needed. The Class D output stage is usually implemented as an H-bridge (schematic in Fig.1 is simplified). This paper deals with optimization of such a back-end system resulting in considerable power savings compared to the design of [1]. In Section 2, design specifications for the ΣΔ modulator intended for hearing-aid application are
discussed. A figure of merit (FOM) that allows relative comparison of ΣΔ modulators and estimation of power savings is introduced here too. In Section 3, optimization approach is proposed. In Section 4 two ΣΔ modulator designs are compared as an example of the optimization approach. Finally, the conclusions can be found in Section 5.

## 2 Contribution to Internet of Things

In the future the Internet will become even more important part of our daily life. Multimedia information will be delivered to our portable electronic devices. This will require audio readout “on the fly” of the internet content, low power digital signal processing and amplification inside an ear-plug. In this work we propose how such signal processing can be done in a more power efficient way.

## 3 Design Specifications and Figure of Merit

A thorough discussion on hearing-aid audio back-end system specification and the ΣΔ modulator is provided in [1]. The band-width (BW) of high-end hearing aids is a trade-off between ensuring sufficient sound quality and the limited power available and is normally around 10 kHz. In order to fulfill the Nyquist criterion the sampling frequency at the input of the back-end system is $f_{s_in} > (2 * BW) = 20$ kHz. In the case of this work we use 44.1 kHz / 2 = 22.05 kHz [1]. Also in this work we assume ideal 16 bit quantization of the back-end system input signal [2]. This results in signal-to-quantization-noise ratio (SQNR) = 98 dB. The input signal of the back-end is then up-sampled using an interpolation filter [2] and passed to the ΣΔ modulator. The interpolation filter in [2] consists of 4 stages (FIR filter, half-band filter, 1st order Sinc filter, 3rd order Sinc filter) and is used to up-sample the input signal 64 times. Another requirement in this work is the signal-to-noise-and-distortion ratio (SNDR) at the total output of the back-end of 90 dB. The interpolation filter and the ΣΔ modulator are designed to keep the quality of the audio signal at SNDR = 98 dB so that a margin of 8 dB is left for the performance reduction introduced by the output stage. Note that we are dealing with a digital ΣΔ modulator in this work and we treat it as a digital filter. This allows us to adopt the idea for a FOM from [3, 4] by counting the number of adders in the design. Unlike in the case of the interpolation filter the number of bits does not have to be the same for all the adders in a ΣΔ modulator. We have to take this fact into account and propose FOM so that the number of bits of individual adders is included. This leads us to

$$FOM = \sum_i b_i \cdot OSR_i. \qquad (1)$$

Where i is the number of adders in the ΣΔ modulator block, b_i is the number of bits used in individual adders and OSR_i is the oversampling used for the individual adders. In the case of the ΣΔ modulator block OSR_i is the same for all the adders. Since this FOM accounts for the majority of the cells needed to implement the ΣΔ modulator it is roughly proportional to the power of the ΣΔ modulator and is a valuable tool when
choosing between designs in early design phase. The lower the FOM the better the
design is. The above mentioned specifications and FOM will be used in the next
sections when optimizing the back-end system including the ΣΔ modulator and
comparing it to previous design of [1].

4 Design Optimization Approach

The idea behind the optimization of the ΣΔ modulator and the entire back-end design compared to [1] is to decrease the OSR of the modulator from 64 to 32 and increase its order from 3 to 6. By performing these changes in the ΣΔ modulator we aim to reduce the switching frequency of the Class D output stage and the DPWM block by 50% as this frequency is the same as the operating frequency of the ΣΔ modulator. With the Class D output stage being the main power consumer in the back-end system due to the large output transistors and low output impedance, this will result in considerable power savings. Moreover these changes will have positive impact on the interpolation filter too as oversampling by 32 only is needed compared to oversampling by 64 in [1]. This saves one stage performing oversampling by a factor of 2 in the interpolation filter of [2]. Using the same idea as in Eq.(1) for the FOM of the interpolation filter we calculate FOM = 113 for the whole interpolation filter out of which FOM = 24 goes for the stage that will be saved by our optimization. This is improvement of hardware/power saving by 21% in the interpolation filter.

With a signal with SQNR = 98 dB at the ΣΔ modulator input any oversampling
(OSR) and noise-shaping order in the ΣΔ modulator providing better SQNR than 98
dB is denoted in this work as overdesign. However, just like in the case of FIR filters
in [5], overdesign can allow very coarse quantization of the ΣΔ modulator coefficients
leading to lower amount of adders used and thus reducing the power consumption.
Keeping this in mind we compare two cascade-of-resonator-with-feedback (CRFB)
ΣΔ modulator designs with the same performance. We chose the designs so that the
same peak-SQNR is achieved in both cases. To ensure a simple interpolation filter,
only factors of integer power of two are considered in this work. In Fig.2 peak-SQNR
is plotted as a function of OSR for orders N = 1 to 8 when 3 bit quantizer is used. This
figure shows that the following parameter combinations achieve peak-SQNR of
approx. 106 dB: OSR = 64, order = 3, 3 bit quantizer (see [1]), OSR = 32, order = 6,
3 bit quantizer (optimized). With SQNR = 98 dB needed at the ΣΔ modulator output
we leave margin for coarse coefficient quantization (as proposed in [5] for digital FIR
filters) and we overdesign the ΣΔ modulator to reach 106 dB peak-SQNR. Again, for
the sake of comparison both of these designs use 3 bit quantizer. As explained in [1],
the number of bits used in the quantizer is one of the factors that decide the clock
frequency of the DPWM block. Increasing the number of bits in the quantizer can
result in clock frequency that is not available in hearing aids. For this reason we keep
the number of bits in the quantizer the same as in [1] and limit the design freedom in
this case to OSR and the order of the ΣΔ modulator. Moreover the maximum stable
amplitude at the modulator input is the same in both cases, -1 dBFS. The noise-
transfer-functions (NTF) of both ΣΔ modulators can be seen in Fig. 3. Having the
same performance in both designs allows us to compare these designs using the FOM of Eq. (1). The only block of the back-end system that remains to be investigated to see whether or not this optimization approach is reasonable is the ΣΔ modulator. We discuss this in the next section.

## 5 ΣΔ Modulator Optimization

The two ΣΔ modulator structures we used in this work can be seen in Fig. 4. A 3 bit quantizer is used in both cases, the order of the modulator was increased from 3 (Fig. 4a) to 6 (Fig. 4b) and the OSR was decreased from 64 to 32. The ΣΔ modulator performance is the same in both cases. For both designs a model using floating-point arithmetic and a model using fixed-point arithmetic was built and simulated in Matlab. The fixed-point arithmetic model performs digital operations exactly as a VHLD design does. Thus the fixed-point arithmetic model can be directly used to judge the complexity of the filter. The FOM used in this work depends on the number of the adders and the number of bits used in the individual adders. This means that one way to improve the FOM in the 6th order modulator is to keep the number of adders as low as possible. For this reason in this work, we adopt the FIR filter over-design approach from [5] and use it for the ΣΔ modulator designs. Peak-SQNR of 98 dB needed at the modulator output allows us to use the 8 dB margin achieved by the modulator being overdesigned to reach approx. peak-SQNR of 106 dB to coarsely quantize the coefficients. Using coarse quantization of the coefficients reduces the peak-SQNR from approx. 106 dB to 98 dB – still within specification with lower number of adders used than in direct design. To confirm our optimization approach, we design both ΣΔ modulators in two versions: Version 1: with high-precision coefficients and adders to achieve peak-SQNR = approx. 106 dB (see Fig. 4). Version 2: with coarsely quantized coefficients and adders to allow peak-SQNR = 98 dB (see Fig. 4). The list of coefficients used for the 3rd order modulator can be seen in Tab. 1 and the list of coefficients for the 6th order modulator in Tab. 2. The number of bits used for the internal integrators can be seen in Fig. 4 for both Version 1 and Version 2. Taking the Matlab fixed-point models and calculating the FOM according to Eq. 1 gives data and FOM in Tab. 3, clearly showing that the FOM of the 6th order modulator with OSR = 32 compared to 3rd order modulator with OSR = 64 of [1] remains approximately the same after the back-end system optimization in both high-precision and coarsely quantized case. This can be predicted by looking at Fig. 4. The OSR of the 6th order modulator in Fig. 4a is half compared to the 3rd order modulator in Fig. 4b but the area is doubled. To have lower power consumption in the Class-D output stage and have larger area of the ΣΔ modulator is reasonable tradeoff since the ΣΔ modulator is completely digital and thus easily scales with technology. The same cannot be said about the Class-D output stage. Expressing the current consumption of the back-end as sum of the currents needed in individual blocks we write

$$I_{total} = I_{int} + I_{SDM} + I_{DPWM} + I_{dr} \quad (2)$$
Where $I_{int}$ is the current needed in the interpolation filter (see Fig. 1), $I_{SDM}$ is the current of the $\Sigma\Delta$ modulator, $I_{DPWM}$ is the current of the DPWM block and $I_{dr}$ is the current of the Class-D driver (output-stage). In Section 3 We explained that $I_{dr}$ and $I_{DPWM}$ will be lowered by 50% and $I_{int}$ by 21% by the optimization. Table 3 shows that $I_{SDM}$ will remain approximately the same. Thus in total there are considerable power savings achieved by the proposed optimization approach. In future work, the OSR in the 6th order modulator being halved compared to [1] will allow us to increase the number of bits in the quantizer from 3 to 4 while keeping the maximum sampling frequency in the system. This will help to increase the maximum stable amplitude of the $\Sigma\Delta$ modulator – a crucial parameter in hearing-aid application.

## 6 Conclusion

In this paper we optimized the back-end of the audio signal processing path in hearing-aid application on system-level compared to the design of [1]. A figure of merit was introduced to decide early in the design process whether or not the optimization approach is reasonable. The optimization approach uses combination of the increase of the $\Sigma\Delta$ modulator order and the decrease of its OSR. Further savings are achieved by peak-SQNR overdesign and subsequent coarse quantization of the $\Sigma\Delta$ modulator coefficients. This approach leads to simplified interpolation filter, reduces the frequency of the DPWM block and the switching-rate of the Class-D output stage by 50%. The power consumption of the $\Sigma\Delta$ modulator is kept as in [1]. Overall the power of the entire back-end system is optimized showing that trading higher order for lower OSR in the $\Sigma\Delta$ modulator DAC is an approach to be considered in low-voltage, low-power, portable audio applications.

<table><caption>**Table 1.** 3rd order $\Sigma\Delta$ modulator coefficient list.</caption><thead><tr><th colspan="2">Quantization</th><th colspan="2">Version 1</th><th colspan="2">Version 2</th></tr><tr><th>Coeff.</th><th>Value</th><th>Shift/Add</th><th>Adders</th><th>Shift/Add</th><th>Adders</th></tr></thead><tbody><tr><td>a<sub>1</sub></td><td>1/8</td><td>2<sup>-3</sup></td><td>0</td><td>2<sup>-3</sup></td><td>0</td></tr><tr><td>a<sub>2</sub></td><td>0.3446</td><td>2<sup>-2</sup>+2<sup>-4</sup>+2<sup>-5</sup></td><td>2</td><td>2<sup>-2</sup></td><td>0</td></tr><tr><td>a<sub>3</sub></td><td>0.3941</td><td>2<sup>-2</sup>+2<sup>-3</sup>+2<sup>-6</sup></td><td>2</td><td>2<sup>-2</sup>+2<sup>-3</sup></td><td>1</td></tr><tr><td>b<sub>1</sub></td><td>1/8</td><td>2<sup>-3</sup></td><td>0</td><td>2<sup>-3</sup></td><td>0</td></tr><tr><td>c<sub>1</sub></td><td>1/2</td><td>2<sup>-1</sup></td><td>0</td><td>2<sup>-1</sup></td><td>0</td></tr><tr><td>c<sub>2</sub></td><td>1/2</td><td>2<sup>-1</sup></td><td>0</td><td>2<sup>-1</sup></td><td>0</td></tr><tr><td>c<sub>3</sub></td><td>1.4063</td><td>2<sup>0</sup>+2<sup>-2</sup>+2<sup>-3</sup>+2<sup>-5</sup></td><td>3</td><td>2<sup>0</sup>+2<sup>-2</sup></td><td>1</td></tr><tr><td>g<sub>1</sub></td><td>0.0029</td><td>2<sup>-9</sup>+2<sup>-10</sup></td><td>1</td><td>2<sup>-9</sup></td><td>0</td></tr></tbody></table>
<table><caption>**Table 2.** 6th order ΣΔ modulator coefficient list.</caption><thead><tr><th colspan="2">Quantization</th><th colspan="2">Version 1</th><th colspan="2">Version 2</th></tr><tr><th>Coeff.</th><th>Value</th><th>Shift/Add</th><th>Adders</th><th>Shift/Add</th><th>Adders</th></tr></thead><tbody><tr><td>a<sub>1</sub></td><td>1/16</td><td>2<sup>-4</sup></td><td>0</td><td>2<sup>-4</sup></td><td>0</td></tr><tr><td>a<sub>2</sub></td><td>0.1542</td><td>2<sup>-3</sup>+2<sup>-6</sup>+2<sup>-7</sup></td><td>2</td><td>2<sup>-3</sup></td><td>0</td></tr><tr><td>a<sub>3</sub></td><td>0.1705</td><td>2<sup>-3</sup>+2<sup>-5</sup>+2<sup>-7</sup></td><td>2</td><td>2<sup>-3</sup>+2<sup>-5</sup></td><td>1</td></tr><tr><td>a<sub>4</sub></td><td>0.2532</td><td>2<sup>-2</sup></td><td>0</td><td>2<sup>-2</sup></td><td>0</td></tr><tr><td>a<sub>5</sub></td><td>0.5544</td><td>2<sup>-1</sup>+2<sup>-5</sup>+2<sup>-7</sup></td><td>2</td><td>2<sup>-1</sup>+2<sup>-5</sup></td><td>1</td></tr><tr><td>a<sub>6</sub></td><td>0.6353</td><td>2<sup>-1</sup>+2<sup>-3</sup></td><td>1</td><td>2<sup>-1</sup>+2<sup>-3</sup></td><td>1</td></tr><tr><td>b<sub>1</sub></td><td>1/16</td><td>2<sup>-4</sup></td><td>0</td><td>2<sup>-4</sup></td><td>0</td></tr><tr><td>c<sub>1</sub></td><td>1/8</td><td>2<sup>-3</sup></td><td>0</td><td>2<sup>-3</sup></td><td>0</td></tr><tr><td>c<sub>2</sub></td><td>1/8</td><td>2<sup>-3</sup></td><td>0</td><td>2<sup>-3</sup></td><td>0</td></tr><tr><td>c<sub>3</sub></td><td>1/4</td><td>2<sup>-2</sup></td><td>0</td><td>2<sup>-2</sup></td><td>0</td></tr><tr><td>c<sub>4</sub></td><td>1/2</td><td>2<sup>-1</sup></td><td>0</td><td>2<sup>-1</sup></td><td>0</td></tr><tr><td>c<sub>5</sub></td><td>1/2</td><td>2<sup>-1</sup></td><td>0</td><td>2<sup>-1</sup></td><td>0</td></tr><tr><td>c<sub>6</sub></td><td>0.8791</td><td>2<sup>-0</sup>-2<sup>-3</sup></td><td>1</td><td>2<sup>-0</sup>-2<sup>-3</sup></td><td>1</td></tr><tr><td>g<sub>1</sub></td><td>0.0044</td><td>2<sup>-8</sup>+2<sup>-12</sup></td><td>1</td><td>2<sup>-8</sup></td><td>0</td></tr><tr><td>g<sub>2</sub></td><td>0.0168</td><td>2<sup>-6</sup>+2<sup>-10</sup></td><td>1</td><td>2<sup>-6</sup></td><td>0</td></tr><tr><td>g<sub>3</sub></td><td>0.0167</td><td>2<sup>-6</sup>+2<sup>-10</sup></td><td>1</td><td>2<sup>-6</sup></td><td>0</td></tr></tbody></table>

<table><caption>**Table 3.** Modulator comparison.</caption><thead><tr><th rowspan="2">Modulator Order</th><th rowspan="2">Quant. bits</th><th rowspan="2">OSR</th><th rowspan="2">Adders</th><th colspan="2">Peak-SQNR [dB]</th><th rowspan="2">FOM</th></tr><tr><th>ideal</th><th>quantized</th></tr></thead><tbody><tr><td>3</td><td>3</td><td>64</td><td>18</td><td>106</td><td>106<br>(Version 1)</td><td>296</td></tr><tr><td>6</td><td>3</td><td>32</td><td>29</td><td>105</td><td>105<br>(Version 1)</td><td>303</td></tr><tr><td>3</td><td>3</td><td>64</td><td>12</td><td>106</td><td>98<br>(Version 2)</td><td>193</td></tr><tr><td>6</td><td>3</td><td>32</td><td>22</td><td>105</td><td>98<br>(Version 2)</td><td>192</td></tr></tbody></table>
<figure><img src="image_2.png" /><figcaption>Fig. 1. Simplified schematic of the back-end of audio signal processing chain: interpolation filter, ΣΔ modulator, Class-D output-stage and output filter.</figcaption></figure>

<figure><img src="image_3.png" /><figcaption>Fig. 2. Peak SQNR versus OSR for ΣΔ modulator orders N = 1 to 8 with 3 bit quantizer.</figcaption></figure>

<figure><img src="image_4.png" /><figcaption>Fig. 3. ΣΔ modulator NTF in the case of (red) 3rd order modulator (frequency is normalized to 64xfsin) and (blue) 6th order modulator (frequency is normalized to 32xfsin)</figcaption></figure>
<figure><img src="image_5.png" /></figure>

<figure><img src="image_6.png" /><figcaption>Fig. 4. Simplified ΣΔ modulator CRFB schematic (a) 3rd order modulator, OSR = 64 and (b) 6th order modulator, OSR = 32.</figcaption></figure>

References

1. P. Pracný, E. Bruun, "ΣΔ Modulator System-Level Considerations for Hearing-Aid Audio Class-D Output Stage Application," Proc. 2012 8th Conf. on Ph.D. Research in Microelectronics and Electronics (PRIME), pp. 103-106, Aachen, June 2012.

2. Pracný P., Llimós M. P., Bruun E. : 'Interpolation filter design for hearing-aid audio class-D output stage application', Proc. 19th IEEE Int. Conf. on Electronics, Circuits, and Systems, Seville, Spain, Dec. 2012.

3. Anzova V. I., Yli-Kaakinen J., and Saramäki, T. : 'An algorithm for the design of multiplierless IIR filters as a parallel connection of two all-pass filters', Proc. IEEE Asia Pacific Conf. on Circuits and Systems, Singapore, Dec. 2006, pp. 744-747.

4. Stoyanov G., Nikolova Z., Ivanova K., Anzova V. : 'Design and realization of efficient IIR digital filter structures based on sensitivity minimizations', Proc. 8th Int. Conf. on Telecommunications in Modern Satellite, Cable and Broadcasting Services, Niš, Serbia, Sep. 2007, pp. 299-308.

5. Mehboob R., Khan S. A., Qamar R. : 'FIR filter design methodology for hardware optimized implementation', IEEE Trans. Consumer Electronics, 2009, 55, (3), pp. 1669-1673.