# Air Gaps Fabrication for Sub-100 nm GaN HEMTs by Novel SF6 Plasma Etching

Simon St-Jacques, Mariyam Salmi, Oleh Fesiienko, Erwine Pargon, Ali Soltani, Bassem Salem, Hassan Maher

► To cite this version:

Simon St-Jacques, Mariyam Salmi, Oleh Fesiienko, Erwine Pargon, Ali Soltani, et al. Air Gaps Fabrication for Sub-100 nm GaN HEMTs by Novel SF6 Plasma Etching. Microelectronics, 2026, 2 (1), pp.1. 10.3390/microelectronics2010001. hal-05487116

HAL Id: hal-05487116

https://hal.science/hal-05487116v1

Submitted on 3 Feb 2026

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# Air Gaps Fabrication for Sub-100 nm GaN HEMTs by Novel SF₆ Plasma Etching

Simon St-Jacques ¹,²,³, Mariyam Salmi ¹,², Oleh Fesiienko ¹, Erwine Pargon ³, Ali Soltani ¹,², Bassem Salem ³,* and Hassan Maher ¹,²,*

¹ Institut Interdisciplinaire d'Innovation Technologique (3IT), Université de Sherbrooke, 3000 Boulevard de l'Université, Sherbrooke, QC J1K 0A5, Canada; simon.st-jacques2@usherbrooke.ca (S.S.-J.); mariyam.salmi@usherbrooke.ca (M.S.); oleh.fesiienko@usherbrooke.ca (O.F.); ali.soltani@usherbrooke.ca (A.S.)

² Laboratoire Nanotechnologies Nanosystèmes (LN2)-IRL3463, CNRS, Université de Sherbrooke, 3000 Boulevard de l'Université, Sherbrooke, QC J1K 0A5, Canada

³ Univ. Grenoble Alpes, CNRS, CEA/LETI-Minatec, Grenoble INP, LTM, Grenoble F-38054, France, ; er-wine.pargon@cea.fr (E.P)

* Correspondence : bassem.salem@cea.fr (B.S.); hassan.maher@usherbrooke.ca (H.M.)

## Abstract

We demonstrate the fabrication of air gaps in a PECVD SiN interlayer through lateral recess by employing two consecutive plasma etch steps on an AlN/SiN/Al₂O₃ stack. This approach enables the preservation of sub-100 nm openings in Al₂O₃, offering a potential optimization for the GaN-HEMT gate stack in RF applications while retaining low gate foot dimensions. A low-power, SF₆-based plasma etch is introduced, and time-dependent etch profiles reveal the formation of a skirt-like profile. The process exhibits excellent selectivity between SiN and Al₂O₃ etch rates. Furthermore, low-power SF₆ plasma produces a small self-bias voltage, and surface fluorine contamination which can subsequently be eliminated by annealing.

**Keywords:** air gaps; capacitance; plasma etching; undercut; GaN-HEMT; sub-100 nm

## 1. Introduction

For high-power, high-frequency applications based on GaN-HEMT technology, transistor scaling has been a primary strategy to improve frequency performance. The figures of merit $f_T$ and $f_{MAX}$ increase as the gate length is reduced, but only up to a certain limit [1]. At very small dimensions, short-channel effects (SCEs) emerge as a major constraint on device performance.

Another critical limitation in ultra-scaled devices is the increasing role of parasitic capacitances. Two dominant sources are fringing capacitance and geometry-dependent capacitance of the gate structure. Common gate geometries for high-frequency transistors include T-gates [2,3], Γ-gates [4], and Π-gates [5], each composed of a wide “gate head” or cap above a narrower “gate foot” or stem. As the gate foot is shortened, its height is also typically reduced, which in turn increases the effective capacitance between the gate head and the channel. At very small gate-foot lengths and heights, the parasitic capacitance of the gate head becomes an important contributor [6].

The impact of different capacitance components can be analyzed through their contribution to parasitic delay. Parasitic delay may be expressed as⁶:

$$ \tau_{par} = (C_{gs,ext} + C_{gd,ext})/g_m + C_{gd}(R_s + R_d) + (C_{gs} + C_{gd})(R_s + R_d) g_{ds}/g_m $$
where $(C_{gs,ext} + C_{gd,ext})/g_m$, the dominant extrinsic gate capacitances contribution, include fringing capacitance of the gate foot and the parallel-plate component with the access regions. Extrinsic delay alone can account for more than 50% of the total parasitic delay time⁶. In T-gate geometries featuring a 40 nm gate foot length and an 80 nm foot height, the elimination of the SiON dielectric layer ($\epsilon_r = 5$) between the gate head and the barrier layer significantly lowers the total gate parasitic capacitance, achieving reductions of up to 30% [6]. This reduction highlights the important influence of the dielectric environment on the extrinsic capacitance, especially for reduced gate foot heights.

To reduce parasitic capacitance, low-permittivity passivation layers have been investigated [7,8], since capacitance scales with dielectric permittivity. Air, with the lowest possible permittivity ($\epsilon \approx 1$), offers favorable electrostatic performance when used to surround standing T-gates. However, such structures introduce challenges, including enhanced leakage through surface defects in unpassivated regions.

The fabrication of T-gates with very narrow feet and wide heads can lead to issues of mechanical stability, robustness, and poor yield [9]. An alternative approach is to form air cavities (also referred to as air gaps or air pockets) around the gate foot, retaining some dielectric for structural stability while still incorporating low-permittivity regions to reduce capacitance [10,11].

Previously, air-gap structures have been achieved [12] by wet etching dielectric bilayers to create an undercut in the bottom dielectric. Resulting structures have been shown to improve $f_T/f_{MAX}$ performance of the device compared to non-air-gapped structures. However, this approach has not been demonstrated for gate-foot lengths below 100 nm.

In this work, we present a fabrication process for sub-100 nm gate foot with air gaps using a selective SF₆ plasma etch to produce controlled undercuts in a dielectric bilayer. This method represents a crucial step toward realizing air-gapped T-gates at deeply scaled dimensions. To the best of our knowledge, this is the first demonstration of SF₆ plasma etching being used to fabricate air gaps surrounding the gate foot.

## 2. Experimental Section

The material selection reflects typical layers used in GaN-HEMT architectures. From bottom to top, the first layer is the etch-stop (bottom) layer, the second layer is the interlayer (or undercut layer), and the third (top) layer serves as a hard mask (mask layer). The top two dielectric layers together will be referred to as the dielectric bilayer, while the complete three-layer stack is termed the trilayer.

Aluminium nitride (AlN) was chosen as the etch-stop layer, consistent with its widespread use for barrier recesses and as a barrier material in scaled GaN devices [13,14]. The interlayer consists of PECVD-deposited silicon nitride SiN, selected for its common application as a passivation layer [15,16] and for its relatively high etch rate compared to LPCVD SiN or SiO₂. For the top layer, ALD-deposited aluminum oxide Al₂O₃ was used, since only a thin hard mask is required and Al₂O₃ is also a common gate dielectric in GaN technology.

The process flow illustrated in Figure 1 was used to fabricate the SiN undercut structures. The vertical stack begins with a 165 nm AlN layer grown by MOCVD on a Si(111) substrate, followed by deposition of PECVD SiN and Al₂O₃ by thermal ALD at 300 °C. The SiN thickness was varied between 20 and 80 nm, while the Al₂O₃ thickness was fixed at 20 nm. Electron-beam lithography (EBL) was performed on ZEP520A resist spin-coated at a dilution ratio of 2.0 and developed in a 1:1 MIBK:IPA solution. Pattern transfer into the Al₂O₃ hard mask was achieved using a BCl₃-based plasma etch. The resist was subsequently stripped by deep ultraviolet (DUV) irradiation, 1-methyl-2-pyrrolidone (NMP) immersion, and standard acetone/isopropanol (IPA) cleaning followed by N₂ drying. The
critical step of SiN interlayer etch was then performed using an SF₆-based plasma etch. After processing, the samples were cleaved for cross-sectional SEM imaging.

<figure><img src="image_2.png" /><figcaption>**Figure 1.** Process flow for fabrication of air cavities for GaN-HEMT using AlN/GaN heterostructure with steps (a) deposition of dielectric bilayer on AlN/Si(111), (b) spincoat and patterning of EBL resist for sub 100 nm openings, (c) etch through Al₂O₃ hard mask by plasma etch, (d) Stripping of EBL resist, (e) Selective SiN etch (with hard mask and etch stop layer), (f) deposition of conformal dielectric by ALD, (g) metal gate deposition. Only steps (a) → (e) are discussed here.</figcaption></figure>

Plasma etching was conducted in a 200 mm PlasmaPro 100 Cobra inductively coupled plasma (ICP) reactor (Oxford Instruments, Oxford, UK). The plasma was sustained by a 13.56 MHz radio-frequency (RF) induction coil; a separate 13.56 MHz RF supply, capacitively coupled to the chuck, provided an optional substrate bias. The chamber walls and chuck were temperature-controlled at 60 °C and 20 °C, respectively. All samples presented in this work were centrally mounted on a 200 mm carrier wafer using Crystal-bond™ 555-HMP (silicone-free thermoplastic adhesive; SPI Supplies, West Chester, PA, USA) to ensure good thermal contact. Plasma etch parameters are summarized in Table 1. Samples sizes ranges from 10 × 10 mm to 15 × 15 mm, with total coverage of carrier wafer less than 5% at all times. Until said otherwise, default carrier wafer is silicon. SiO₂ and sapphire (Al₂O₃) are used for comparison of loading effects in pertinent sections.

<table><caption>**Table 1.** Table of plasma parameters for Al₂O₃ and SiN etch used for structure fabrication.</caption><thead><tr><th>Etch Step and Name</th><th>Gas Species</th><th>Recipe #</th><th>Chamber Pressure (mTorr)</th><th>Coil Power (W)</th><th>Platen Power (W)</th><th>Gas Flux (sccm)</th><th>Substrate Temperature (°C)</th></tr></thead><tbody><tr><td>Al<sub>2</sub>O<sub>3</sub> etch</td><td>BCl<sub>3</sub></td><td>1</td><td>2.0</td><td>200</td><td>100</td><td>15</td><td>20</td></tr><tr><td>SiN etch ("low-power")</td><td>SF<sub>6</sub></td><td>2</td><td>10.0</td><td>200</td><td>10</td><td>20</td><td>20</td></tr></tbody></table>

Thin film's thicknesses were measured with a Woolam Alpha-SE ellipsometer (J.A. Woollam, Lincoln, USA), allowing samples from 5 × 5 mm up to 200 mm wafers to be measured. Scans using 180 datapoints in the spectral range from 370 to 900 nm were performed. For most unpatterned dielectric layers on silicon, a simple Cauchy model was used. This model was applied for Al₂O₃, AlN, ZEP520, PMMA and SiO₂ layers and the fitting gave satisfactory results. For PECVD and LPCVD SiN layers, a Tauc-Lorentz model was used to model layer thickness to further improve fitting. In all cases, repeatability of the measurement yielded the same thickness ± 1 nm. Offset angle compensation was turned on in the models and roughness compensation was turned off.

The first plasma step defined the Al₂O₃ top layer openings to expose the SiN interlayer. Chlorine-based RIE (BCl₃, Cl₂), known to etch Al₂O₃ effectively [17,18], was used. A target depth of 20 nm, with an additional 5 nm over-etch, ensured full opening of the Al₂O₃ layer. A slow etch rate was selected for depth control. Under conditions of 200 W on the ICP coil, 100 W on the platen, 2.0 mTorr chamber pressure, and 15 sccm BCl₃ flow, i.e., recipe #1 of Table 1, the etch rate was ~16 nm/min. High platen power was required, as lower settings (20–50 W) produced non-uniform etching of the Al₂O₃ hard mask [17].
The second plasma step etches the PECVD-SiN interlayer. Fluorine-based plasmas (SF₆, CF₄) are known to etch SiN selectively relative to Al-based materials, as aluminum compounds forms non-volatile AlFₓ(s) species. A low SiN etch rate is desired the target dimensions are below 100 nm vertically and ideally up to 200 nm or more laterally for air gaps. An optimized recipe (#2) was 200 W ICP coil power, 10 W platen power, 10 mTorr pressure, and 20 sccm SF₆ as the gas source. The recipe gives a PECVD etch rate of about 10.5 nm/min on unpatterned thin films. Reducing platen power minimized fluorine implantation into the AlN layer and prevented AlN roughening from ion sputtering, which could otherwise degrade GaN HEMT device performance. SF₆ was chosen as the fluorine source due to its etching ability of SiN thin films but negligible or very low etch rates of AlN and Al₂O₃ layers at low platen bias voltage, as well as its availability in our plasma reactor. O₂ and/or Ar was not added to the mixture because tests showed an increase in the etch rate.

AFM measurements were performed using a Park Tool NX20 system equipped with PPP-NCHR-10 AFM tips. Scan areas of 1 × 1 µm² were imaged with resolution 256 × 256, at a scan rate varying between 0.5 and 0.8 Hz. Imaging was performed in non-contact mode; 5 × 5 µm² areas were initially performed to find suitable 1 × 1 µm² areas but not shown here. In some cases, some parasitic signal from the cleanroom environment was removed by FFT filtering. Background polynomial baseline was removed and scale bar adjusted to -1 to +1 nm. Area roughness was measured using Root Mean Square (RMS) and denoted S_q.

SEM cross-section imaging was performed using Thermofisher Apreo 2 system. Samples were tilted at 5° from cross-section unless stated otherwise. EDS measurements were performed in the SEM chamber at the same time as SEM imaging. Images were taken at acceleration voltage of 10 kV, with working distance varying between 8 and 10 mm. Images were taken from ETD, T1 or T2 depending on best less noise, best brightness and/or contrast.

Contactless sheet resistance (R_s) measurements of epitaxial samples were performed using a Semilab LEI88, allowing probing of the 2DEG sheet resistance under the SiN and AlN cap layers. The tool allows measurements of R_s values ranging from 16 to 3000 Ω/□ and can measure sheet resistance for samples of sizes above 10 × 10mm. A minimum of three measurements points per sample were taken to see variance of the measurement.

Hall effect measurements for μ_e, N_s were taken using a Lake Shore M91 FastHall controller (Lake Shore Cryotronics, Westerville, USA). Measurement sequence included contact-to-contact check for I-V ohmicity, sheet resistance measurement, and was followed by hall effect measurements performed in FastHall mode, using a permanent magnet of 500 mT. The samples analyzed were either 15 × 15 mm² or 10 × 10 mm², with ohmic contacts in Van Der Pauw geometry.

Epitaxial GaN-HEMT structures discussed later in this study are commercial wafers consisting of MOCVD 2 nm in situ SiN cap, 4 nm AlN barrier layer, 150 nm GaN channel layer, 1.2 µm buffer layer on HR-Si, with 2DEG properties of Rs of 270 Ω/□ or better and electron mobility µ_n of 1000–1100 cm²/(V.s) or better.

### 3. Results and Analysis

The fabrication process flow created a lateral under-etch in the dielectric bilayer which relied heavily on the ability to have a selective SiN/Al₂O₃ and selective SiN/AlN in terms of etch rates. The selectivity parameter S, as defined in $S_{A/B} = \frac{\text{Etch Rate (A)}}{\text{Etch Rate (B)}}$, does not, however, account for plasma-induced surface modifications of these layers, which will be discussed later. The limited etch of the Al-containing films primarily arises from the formation of non-volatile Al–F species, which result from the conversion of surface Al–O or Al–N bonds during plasma exposure. In the case of the AlN barrier layer, this Al–N to Al–
F conversion can significantly influence the subsequent electrical behavior of the device [19].

Let us start by observing the etch rate of dielectric layers by both of the plasma etch steps used in this process flow to quantify the selectivity.

The selectivity of the BCl₃-based plasma etch used to create openings in the Al₂O₃ hard mask was characterized. Etch rates were measured on unpatterned thin films of the deposited dielectrics as well as on common EBL resists. Figure 2 presents the calculated etch rates. While BCl₃ effectively etches Al₂O₃, it is non-selective in relation to both PECVD and LPCVD SiN, indicating that this etch step will not stop precisely at the Al₂O₃/SiN interface (mask/interlayer interface). Therefore, the etch time must be carefully defined and controlled to prevent deep over-etching into the SiN layer. As anticipated, the etch rate of the EBL resists is significant. For this reason, ZEP520A (dilution ratio 2.0) was selected rather than PMMA to maintain a thin resist layer relative to the feature size and to provide better etch resistance.

<figure><img src="image_3.png" /><figcaption>**Figure 2.** Etch rate of dielectrics and resists used in structures by (a) BCl₃ plasma recipe 1—200 W coil 100 W platen 2 mTorr 15 sccm BCl₃ (b) “Low-Power” SF₆ plasma recipe 2—200 W coil 10 W platen 10 mT 20 sccm SF₆. AlN and Al₂O₃ are values labeled as zero because the thickness did not change by more than the ellipsometry thickness measurement uncertainty. Etch rates shown here are calculated using unpatterned thin films.</figcaption></figure>

The selectivity of the SF₆-based plasma etch for the SiN relative to the hard mask and etch-stop layers was also calculated using unpatterned thin films. Results, shown in Figure 2b, demonstrate excellent selectivity of SiN over both ALD Al₂O₃ and MOCVD AlN, along with a moderate rate for the e-beam resists. The resist is not required during this step, as the pattern has already been transferred into the Al₂O₃ hard mask and the resist can be and is stripped between the BCl₃ and SF₆ plasma etches. To evaluate the hypothesis of negligible etching for Al₂O₃ and AlN, samples subjected to prolonged SF₆ plasma etching to form etch profiles were immersed in diluted hydrofluoric acid (1:100 in H₂O) to remove the SiN and Al₂O₃ layers to expose the AlN surface. AFM measurements (not shown here) in the etched profiles region revealed etching depths in the range of 0.3–0.4 nm after etching time of 15 min, centered on the Al₂O₃ openings. Therefore, we calculate an approximate etch rate of 0.03 nm/min, giving us a selectivity above 300:1 with PECVD SiN.
Before presenting etch profiles, we would like to address the choice of carrier wafer material and its effect on the SF₆-based etch. Common carrier wafers used in SF₆ plasma etching processes include silicon, silicon oxide coated (SiO₂), and sapphire (Al₂O₃). It is known that fluorine species etches silicon rapidly relative to the silicon oxide sapphire. Since sample coverage is low here, most of the available fluorine reacts with the carrier wafer. If a silicon carrier wafer is used, less fluorine species should be available for the SiN etch of the samples. Inversely, good etch resistance of silicon oxide and sapphire should increase the concentration of fluorine species available for the SiN etch, and the etch rate of the layer should be higher. This effect is also combined with the high etch resistance of the Al₂O₃ hard mask.

In preliminary tests, unpatterned PECVD SiN thin films measuring 10 × 10 mm were etched on three types of carrier wafer. Measured etch rates were 10 nm/min for the silicon carrier, 20 nm/min for the silicon oxide carrier, and 24 nm/min for the sapphire. Ultimately, the silicon carrier was chosen because the lower etch rate allows for better control of the etch profiles. Etch profiles of patterned samples, after 5 min of SiN etch, are shown in Figure 3, illustrating much deeper lateral etch for silicon oxide and sapphire carriers, consistent with higher availability of fluorine species for the SiN etch.

<figure><img src="image_4.png" /><figcaption>**Figure 3.** Comparison of etch profiles in Al₂O₃/SiN/AlN samples following SiN etch step. Plasma etch parameters were kept constant, with only the carrier wafer type varied. The increase in lateral etch depth is very pronounced when transitioning from Si to SiO₂, and less pronounced when transitioning from SiO₂ to Al₂O₃. This is consistent with the trend observed for unpatterned thin films.</figcaption></figure>

We then examined the etch profiles generated for different opening widths as a function of etch time during the SiN etch step. Two distinct etching regimes were observed. In the first regime, the SiN layer undergoes semi-vertical etching until the AlN etch-stop layer is reached. Once the AlN layer is exposed, a second regime begins, characterized by pronounced lateral etching beneath the Al₂O₃ hard mask, leading to the formation of air-gap regions. Corresponding etch profiles for these two regimes are presented in Figures 4 and 5.

During the first regime of the SiN etch step, the etch is predominantly vertical but exhibits a small lateral component, as illustrated in Figure 4. The horizontal etch rate, calculated directly underneath the hard mask, is seen to be lower than horizontal etch rate. Using a linewidth of 100 nm and etch times of 4, 4.75 and 6.5 min, calculated vertical and horizontal components are, respectively, 16 nm/min and 4.2 nm/min. The calculated
degree of anisotropy $A_f = 1 - \frac{v_l}{v_h}$ with $v_l$ the lateral etch rate and $v_h$ the vertical etch rate gives $A_f$ a value of 0.74.

Vertical etch rates were determined for openings with widths ranging from 10 to 100 nm, as shown in Figure 6a. The etch rate was defined as the total etched SiN thickness divided by the etch time. A small initial over-etch of the SiN layer (less than 5 nm), originating from the previous $Al_2O_3$ etch step to ensure complete interface removal, has been accounted for in the calculations.

The linearity of the vertical etch rate can be assessed by examining whether the rate remains constant across different etch durations, i.e., whether the data points for different times overlap. Nominal linewidth values are reported, as the actual widths vary slightly across samples (±5 nm). For openings wider than approximately 30–40 nm, etch depths in SiN at fixed etch times are comparable, indicating a uniform vertical etch rate that is independent of opening width. In contrast, for openings narrower than 30–40 nm, the etch rate decreases sharply as the linewidth decreases. This reduction is likely due to a limited collection angle for neutral and ionic fluorine species, causing the etch mechanism to become transport- or diffusion-limited, typical of aspect-ratio dependent etching (ARDE).

Interestingly, in all trenches except 10 nm we also observe higher vertical etch rates compared to unpatterned thin films (10 nm/min), suggesting enhanced etching within confined geometries. We attribute this enhancement, at least in part, to the presence of the hard mask: since the hard mask itself does not undergo significant reaction with fluorine species (apart from the initial formation of $AlF_x$ on its surface), a greater concentration of fluorine remains available to etch the SiN.

<figure><img src="image_5.png" /><figcaption>**Figure 4.** Part 1 of the SiN etch step following $Al_2O_3$ plasma etch, where etch is mostly vertical. Etch profiles formed in 80 nm thick SiN PECVD layer for different etch times and various opening widths. We observe that the AlN is reached after an etch time of between 4 and 4.75 min.</figcaption></figure>
<figure><img src="image_6.png" /><figcaption>**Figure 5.** Part 2 of SiN etch step, where lateral etch is observed after reaching the AlN etch stop layer. PECVD SiN thickness is 80 nm thick here. Etch profile formed for different linewidths and appearance of a skirt profile due to different lateral etch rates at bottom and top of the SiN layer. Some profiles for small linewidths are discarded here because electrolithography issues prevented the correct etch in the SiN interlayer.</figcaption></figure>

The SEM images in Figure 5 depict etch profiles during the second phase of etching (i.e., for times after 4 min and 53 s). The sidewall does not etch laterally in a uniform manner in the SiN interlayer from top to bottom. In all cases, the lateral etch rate at bottom of the SiN layer exceeded that of the top, leading to the formation of a characteristic skirt-like profile. Furthermore, the bottom lateral etch rate increases with the width of the opening in the hard mask layer, unlike top etch rate which remains constant. The top and bottom lateral etch rates are reported in Figure 6b. The same calculation was performed for SiN thicknesses of 20, 40 and 80 nm. SEM images of profiles for 20 and 40 nm thick SiN are not shown here. For 80 nm samples compared to 40 nm SiN thickness, the top lateral etch rate is similar, while bottom lateral etch rate is higher for 80 nm thick SiN.

Figure 5 illustrates that the location of a "kink" in the skirt profile is approximately 20–30 nm above the bottom of the SiN layer, indicating different etch conditions for the top and bottom of the SiN layer. For the 20 nm PECVD SiN, the lateral etch rates at the top and bottom are considered equal, as SEM resolution was insufficient to distinguish a top and bottom section. This suggests that the difference in lateral etch widths between the top and bottom is minimal, since the entire layer thickness falls below the kink height position in the skirt profile. Under this assumption, the global lateral etch rate is enhanced relative to the top etch rate observed in 40 nm and 80 nm SiN layers.

The etching observed at the top of the SiN interlayer beneath the Al₂O₃ mask is primarily attributed to neutral species, resulting in an isotropic profile. If neutral species exclusively governed the etching of the entire SiN layer, one would not anticipate the
formation of a lateral skirt but rather a vertical profile at the termination of the lateral recess within the SiN. The more pronounced lateral etching near the bottom of the layer indicates a combined effect influenced by both ionic and neutral species. Nonetheless, direct line-of-sight ion bombardment alone cannot fully explain the presence of deeper lateral recesses at the SiN layer's bottom.

We propose that plasma sheath electric fields and sidewall charging influence etching. Electrons, being lighter and more mobile than ions, first accumulate negative charge on the Al₂O₃ surface by bombardment, creating a sheath field that accelerates positive ions (e.g., SFx⁺, F⁺) toward the sample. Positive ion impact on insulating sidewalls results in net positive charging, attracting negatively charged fluorine ions (e.g., F⁻) vertically toward the SiN layer. As etching exposes the underlying AlN layer, its insulating nature leads to negative charge buildup, further deflecting incoming ions laterally and deepening the recesses in the SiN layer.

Another hypothesis is the surface diffusion of the fluorine along AlN surface. It is known that the fluorine preferentially binds to aluminum compounds, forming non-volatile AlFₓ species more readily than SiFₓ species. The bond dissociation energies of thin-film AlN and amorphous SiN:H are 2.88 eV [19] and 3.5 eV [20], respectively, supporting the premise that Al–N bonds cleave more easily to form Al–F bonds than Si–F bonds. As AlF₃ saturates the AlN surface and forms a passivating layer, only the adjacent SiN compounds remain available for etching. Consequently, volatile SiF₄ is formed and removed, exposing more AlN surface to fluorination, which precedes SiN etching.

<figure><img src="image_7.png" /><figcaption>**Figure 6.** (a) Vertical etch rate versus opening widths for multiple etch times, only for 80 nm thick SiN. Etch rates for etch time of 1 min were excluded to account for plasma stabilization and difficult measurement of SiN thickness etched in trenches. (b) Calculated etch rates at top and bottom of SiN interlayer resulting in skirt-shaped profile. Note here that lateral etch rate value is for one side (either left or right undercut).</figcaption></figure>

Since the top of the SiN layer is shielded by the Al₂O₃ hard mask, it is expected that only neutral fluorine species contributes to lateral etch directly under the hard mask. The quasi-constant top etch rates between 40 nm and 80 nm seem to reflect that fact. Here samples of 20 nm, 40 nm, and 80 nm were etched at the same time for a total of 10 minutes in the reactor and thus submitted to the same plasma conditions, and the resulting etch profiles are shown in Figure 7. The conclusion is that lateral top etch rate etch mechanism
is independent of SiN interlayer thickness, as long as thickness is greater than 20 nm. It
seems that there is a small increase in lateral etch rates for 40 nm and 80 nm SiN for wider
opening (towards 100 nm). It is possible that bigger openings allow greater neutral species
circulation under etch mask.

<figure><img src="image_8.png" /><figcaption>**Figure 7.** Etch profiles for different PECVD SiN thicknesses at constant etch time. SiN etch using plasma recipe #2 and etch duration of 10 min for all samples.</figcaption></figure>

Next, three specific linewidth-SiN thickness pairs were etched to evaluate whether
100 nm air gaps could be formed on both sides of the central opening. These cases follow
the general rule of maintaining a 1:1 aspect ratio for gate metal deposition in device fabri-
cation. The corresponding bottom widths are 280 nm, 240 nm, and 220 nm for openings
of 80 nm, 40 nm, and 20 nm, with SiN thicknesses of 80 nm, 40 nm, and 20 nm, respectively.
Figure 8 shows the fabricated air gaps along with the corresponding etch times.

For the (80 nm, 80 nm) case, the total etch time was 10 min. Of this, approximately
4.75 min were required to reach the AlN layer, after which the bottom region etched with
a high lateral etch rate. In the intermediate (40 nm, 40 nm) case, the smaller opening re-
duced the effective etch rate, resulting in a longer etch time. Additionally, because the etch
rate difference between the top and bottom regions was smaller, the skirt profile was less
pronounced. In the final (20 nm, 20 nm) case, the AlN is reached rapidly because of the
thin SiN layer, and most of the etch time is in the lateral etch regime, where the lateral
etch rate is enhanced relative to the 40 nm SiN and narrow openings. Although a skirt
profile was not observed in SEM due to the small dimensions, it was also not expected,
since the SiN thickness was below the kink-height threshold observed for thicker SiN lay-
ers. Overall, these etching results demonstrate the capability to achieve meaningful lateral
recess depths suitable for device integration, and remain effective when scaled to reduced
dimensions, including the 20 nm regime.
<figure><img src="image_9.png" /></figure>

**Figure 8.** Structures etched in order to generate 100 nm of lateral depth on each side of the central opening. Width is measured at bottom for the 80 nm SiN layer, since there is a discrepancy between the top and bottom. Different magnification and scales are used here for the SEM images. For 20 nm structure, the Al₂O₃ warping and line roughness is caused by incomplete resist removal affected under the SEM beam.

Now we would like to focus on the effect of the plasma etch on the surface of AlN etch stop layer. The quality of this barrier layer is of critical importance in HEMT devices. Roughening of the barrier layer, introduction of defects such as fluorine contamination, strongly affect the 2DEG quality in the regions etched. Plasma etch even at low ion energies (under 15 eV) is expected to introduce fluorine contamination up to the first nanometer of depth of AlₓGa₁-xN layers by diffusion of species from the surface [21].

To qualitatively assess surface fluorination after plasma etching, energy-dispersive X-ray spectroscopy (EDS) measurements were performed on the epitaxial samples described in the experimental section. The spectra are depicted in Figure 9. Epitaxial samples were chosen instead of simple Al₂O₃/PECVD SiN/MOCVD AlN samples to verify etch resistance of in situ MOCVD SiN layer. Using a beam tilt angle of 5° and an acceleration voltage of 5 keV and considering the thinness of the first two layers (2 nm and 4 nm, respectively, for SiN cap and AlN barrier layers), the electron beam likely probes beyond these top layers but not deeply enough to reach the HR-Si substrate.

<figure><img src="image_10.png" /></figure>
**Figure 9.** Fluorination of sample observed by SEM-EDS, using 5 keV beam current and tilt angle of 5 deg from cross-section plane. Signal is normalized to main Ga peak at 1150 eV. Epitaxial samples followed (a) SiN cap removal by wet etching compared or (b) SF₆ plasma dry etch with low-power recipe, and post-etch anneal treatment at 400 °C for 5 min.

After HF wet etching, the observed decrease in the silicon peak at 1750 eV confirms the removal of the SiN cap layer. Concurrently, the slight increase in F peak at 855 eV is attributed to fluorine presence on the exposed AlN surface, remaining even after sample drying. After plasma etching, a similar decrease in the Si peak indicates removal of the SiN cap layer, demonstrating that the plasma etch effectively removes not only PECVD SiN but also the more resistant MOCVD SiN layer. However, the stronger fluorine signal increase after plasma etching suggests greater fluorine quantities present after plasma etch. This fluorine adsorption or shallow implantation is in the AlN layer. The disappearance of the F peak after RTA annealing at 400 °C for 5 min suggests effective removal of most fluorine contamination.

The variation of aluminum peak signal at around 1500 eV is of interest. In all etch methods, the Al signal increases following the removal of the SiN cap. This is coherent with the removal of screening by SiN cap layer, attenuating the signal emanating from AlN layer to the detector. When comparing all Al peaks, it is maximal after HF etch. In comparison, for the plasma etch, Al peak also increases after SiN cap removal and decreases following annealing. While initial SiN cap removal and reduced attenuation explain the increase in signal, the maximum difference in Al signal between wet etch and dry etch could be due to a thicker fluorinated layer of plasma etch screening the EDS signal. This hypothesis is supported by the bigger F peak observed in dry etch versus wet etch. The decrease in Al signal following annealing could be the result of partial barrier removal; a thinner AlN barrier would produce less Al signal. However, thickness of the remaining AlN layer after both treatments has not yet been performed and, thus, could not be verified.

AFM measurements were also performed in parallel to EDS measurements to evaluate the surface roughness post-etch of the previous epitaxial samples and are depicted in Figure 10. Our reference is the wet etching of the cap layer in HF which introduces the least damage to the barrier surface. This technique decreases roughness slightly from 0.162 nm to 0.141 nm. In comparison, the roughness increases after dry etch step, initially from 0.162 nm to 0.195 nm. This is expected as plasma etching bombards the surface with energetic ions, and even at extremely low etch rate rates like here for a barrier layer, some of the AlN is expected to be sputtered [22] over long-time scales. In addition, the conversion of AlN into AlF₃, which is often non-uniform at the nanoscale due to surface chemistry variations, means the surface etches at different rates, leading to more roughening. After annealing, the roughness further increases to 0.230 nm. If there is partial or total AlF₃ removal after annealing (EDS signal decreases), the roughness would increase again, since AlF₃ would also be non-uniform at the nanoscale. AFM also seems to suggest thinning of the AlN barrier.

Contactless Rs measurements performed in parallel to AFM scans to assess the 2DEG quality of the epitaxy after the SiN plasma etch relative to wet etching. Alongside scans of Figure 10, we measured a sheet resistance of (a) 260 Ω/□, (b) 350 Ω/□, (c) 915 Ω/□, and (d) 775 Ω/□. Is it known that SiN cap removal acts both as suppression of strain relief and defects the suppression layer. Using wet etch technique as reference for minimal 2DEG degradation by cap removal, the sheet resistance increases from 260 Ω/□ to 360 Ω/□. In contrast, plasma etching causes a significant increase in sheet resistance up to 915 Ω/□, which must be reduced to ensure acceptable device performance (e.g., RON).
<figure><img src="image_11.png" /><figcaption>**Figure 10.** Roughness measurements on 1 × 1 µm AFM scans of SiN/AlN/GaN MOCVD epitaxy samples. (a) Initial sample with SiN cap. (b) After wet etch in HF 1:1 to remove SiN cap layer. (c) After plasma etch with recipe 2 ("Low-Power") for 5 min. (d) Low-power plasma etched sample after RTA annealing at 400 °C for 5 min.</figcaption></figure>

Discrimination between $N_s$ or $\mu_n$ degradation as the source of $R_s$ degradation during SF$_6$ plasma etching is important. To this end, Hall effect measurements were performed, which allows separate measurements of both electron mobility and sheet density. Another epitaxial sample was exposed to SF$_6$ plasma etch multiple times and Hall effect measurements were performed at each step. The results are presented in Figure 11. We observed that both mobility and sheet charge density degrade during the etch. The mobility degrades towards a value in the range of GaN bulk mobility, which was measured at approximately 300 cm$^2$/Vs. The bulk mobility was also measured by Hall effect on a sample with top AlN barrier completely etched by BCl$_3$ plasma. In the case of negatively charged surface states or traps, the electrons are repelled from the 2DEG deeper into the bulk, and transition as 2D → 3D conduction mode is observed. Such negative surface charges also seem coherent with the skirt formation hypothesis that incident F- from the plasma negatively charges the AlN surface.
<figure><img src="image_12.png" /><figcaption>**Figure 11.** Degradation of electron properties in SF<sub>6</sub> plasma etch, as observed by Hall effect measurements of μ<sub>e</sub>, N<sub>s</sub> after different plasma etch time, on epitaxial sample of 15 × 15 mm. Measured sheet resistance R<sub>s</sub> is, respectively, 160, 620, 980, 6920 Ω/□ at etch times of 0, 2, 7 and 12 min.</figcaption></figure>

**4. Conclusions**

This work demonstrates a plasma-based approach for the selective etching of SiN interlayers with sub-100 nm linewidths, enabling the fabrication of air-gap structures. A low-power SF<sub>6</sub> plasma process was developed, achieving low SiN etch rates with excellent selectivity against AlN and Al<sub>2</sub>O<sub>3</sub>, allowing etch times beyond 30 min without noticeable wear of the Al<sub>2</sub>O<sub>3</sub> hard mask. Lateral etch profiles analysis revealed different etch behaviors at the top and bottom of the SiN layer, resulting in a skirt-shaped geometry and suggesting different underlying etch mechanisms. Lateral etch depths of 100 nm from central opening in hard mask layer were reached for wider openings, while ARDE starts to severely limit lateral etch rates for linewidths under 30 nm. Etch depths of >100 nm were possible on 20, 40, 80 nm thick PECVD SiN stacks with a 20 nm thick Al<sub>2</sub>O<sub>3</sub> hard mask. The observed etch profile strongly depends on fluorine concentration at the surface, indicating that surface coverage and loading effects critically influence the etching outcome.

SF<sub>6</sub> plasma-induced contamination of AlN etch stop layer remains an issue despite low plasma energy. EDS measurements confirmed the presence of shallow AlF<sub>x</sub> fluorination on AlN surfaces, which was partially mitigated by subsequent thermal treatment. Further optimization of the 2DEG recovery is necessary for good device performance.

**Author Contributions:** Conceptualization, S.S.-J.; Methodology, S.S.-J., A.S., B.S., and H.M.; Software, S.S.-J.; Formal Analysis, O.F., E.P., and A.S.; Investigation, S.S.-J., M.S., and A.S.; Resources, M.S. and O.F.; Data Curation, S.S.-J.; Writing—Original Draft Preparation, S.S.-J.; Writing—Review & Editing, S.S.-J. E.P., B.S., and H.M.; Visualization, S.S.-J.; Supervision, B.S. and H.M. All authors have read and agreed to the published version of the manuscript.

**Funding:** This study was partially supported by the French RENATECH network through the LTM technological platforms, as well as from the Fonds de recherche du Québec – Nature et technologies
(FRQNT), the Natural Sciences and Engineering Research Council of Canada (NSERC), the Agence Nationale de la Recherche (ANR), and the Laboratoire Nanotechnologies Nanosystèmes (LN2).

**Acknowledgments:** LN2 is a French-Canadian joint International Research Laboratory (IRL 3463) funded and co-operated by CNRS, Université de Sherbrooke, INSA Lyon, École Centrale Lyon (ECL) as well as Université Grenoble Alpes (UGA). It is also supported by the Fonds de Recherche du Québec Nature et Technologie (FRQNT). LN2 is principally operated at the Institut Interdisciplinaire d'Innovations Technologiques (3IT) at Sherbrooke. The authors further acknowledge funding from the Natural Sciences and Engineering Research Council (NSERC) of Canada through the Discovery Grants program. This work was partly supported by the French Renatech network.

**Data Availability Statement:** The data supporting the conclusions of this article will be made available by the authors upon request.

**Conflicts of Interest:** The authors declare no conflicts of interest.

## References

1. Jessen, G.H.; Fitch, R.C.; Gillespie, J.K.; Via, G.; Crespo, A.; Langley, D.; Denninghoff, D.J.; Trejo, M.; Heller, E.R. Short-Channel Effect Limitations on High-Frequency Operation of AlGaN/GaN HEMTs for T-Gate Devices. *IEEE Trans. Electron Devices* **2007**, *54*, 2589-2597. https://doi.org/10.1109/ted.2007.904476.

2. Karami, K.; Dhongde, A.; Cheng, H.; Reynolds, P.M.; Reddy, B.A.; Ritter, D.; Li, C.; Wasige, E.; Thoms, S. Robust sub-100 nm T-Gate fabrication process using multi-step development. *Micro Nano Eng.* **2023**, *19*, 100211. https://doi.org/10.1016/j.mne.2023.100211.

3. Lei, S.; Cheng, W.-C.; Wu, J.; Wang, L.; Wang, Q.; Xia, G.; Zhao, F.; Yu, H. Low leakage GaN HEMTs with sub-100 nm T-shape gates fabricated by a low-damage etching process. *J. Mater. Sci. Mater. Electron.* **2019**, *31*, 5886-5891. https://doi.org/10.1007/s10854-019-02758-z.

4. Toprak, A.; Haliloglu, M.T.; Durmus, Y.; Sen, O.A.; Ozbay, E. Effect of gate field plate and Γ(gamma)-gate structures on RF power performance of AlGaN/GaN HEMTs. In Proceedings of the 2015 10th European Microwave Integrated Circuits Conference (EuMIC), Paris, France, 7-8 September 2015; pp. 215-218. https://doi.org/10.1109/eumic.2015.7345107.

5. Sehra, K.; Kumari, V.; Gupta, M.; Mishra, M.; Rawal, D.S.; Saxena, M. A Π-shaped p-GaN HEMT for reliable enhancement mode operation. *Microelectron. Reliab.* **2022**, *133*, 114544. https://doi.org/10.1016/j.microrel.2022.114544.

6. Song, B.; Sensale-Rodriguez, B.; Wang, R.; Guo, J.; Hu, Z.; Yue, Y.; Faria, F.; Schuette, M.; Ketterson, A.; Beam, E.; et al. Effect of Fringing Capacitances on the RF Performance of GaN HEMTs With T-Gates. *IEEE Trans. Electron Devices* **2014**, *61*, 747-754. https://doi.org/10.1109/ted.2014.2299810.

7. Wang, W.-K.; Lin, C.-H.; Lin, P.-C.; Lin, C.-K.; Huang, F.-H.; Chan, Y.-J.; Chen, G.-T.; Chyi, J.-I. Low-κ Passivation on AlGaN-GaN HEMT Fabrication. *IEEE Electron Device Lett.* **2004**, *25*, 763-765. https://doi.org/10.1109/led.2004.838322.

8. Wang, R.; Li, G.; Laboutin, O.; Cao, Y.; Johnson, W.; Snider, G.; Fay, P.; Jena, D.; Xing, H. 210-GHz InAlN/GaN HEMTs with Dielectric-Free Passivation. *IEEE Electron Device Lett.* **2011**, *32*, 892-894. https://doi.org/10.1109/led.2011.2147753.

9. Denis, P.; Sahin, H.; Madel, M.; Böhm, T.; Ehrbrecht, R.; Trinh-Xuan, L.; Hugger, A.; Grünenpütt, J.; Grunwald, M.; Amann, M.; et al. Optical and Electrical Methods for Yield Improvement of T-Shaped Gates for AlGaN/GaN HEMT. In Proceedings of the 2023 International Conference on Compound Semiconductor Manufacturing Technology (CS Mantech 2023), Orlando, USA, 15-18 May 2023;

10. Huang, Z.; Sun, H.; Ding, X.; Wang, P.; Li, Y.; Xia, F.; Xia, X.; Tan, X.; Zhang, M.; Ma, J.; et al. Novel gate air cavity GaN HEMTs design for improved RF and DC performance. *Results Phys.* **2021**, *29*, 104718. https://doi.org/10.1016/j.rinp.2021.104718.

11. Chen, Y.; Edgar, D.; Li, X.; Macintyre, D.; Thoms, S. Fabrication of 30 nm T gates using SiNx as a supporting and definition layer. *J. Vac. Sci. Technol. B Microelectron. Nanometer Struct. Process. Meas. Phenom.* **2000**, *18*, 3521-3524. https://doi.org/10.1116/1.1321279.

12. Liu, X.; Chen, J.; Jiang, Y.; Bian, K.; Wang, H. Novel T-Shaped Gate with Air Gap for AlGaN/GaN HEMTs on Silicon with High Johnson's Figures of Merit. *IEEE Trans. Electron Devices* **2024**, *71*, 2943-2949. https://doi.org/10.1109/ted.2024.3381101.

13. Harrouche, K.; Kabouche, R.; Okada, E.; Medjdoub, F. High Performance and Highly Robust AlN/GaN HEMTs for Millimeter-Wave Operation. *IEEE J. Electron Devices Soc.* **2019**, *7*, 1145-1150. https://doi.org/10.1109/jeds.2019.2952314.

14. Medjdoub, F.; Zegaoui, M.; Ducatteau, D.; Rolland, N.; Rolland, P.A. High-Performance Low-Leakage-Current AlN/GaN HEMTs Grown on Silicon Substrate. *IEEE Electron Device Lett.* **2011**, *32*, 874-876. https://doi.org/10.1109/led.2011.2138674.
15. Kim, H.-S.; Kang, M.-J.; Jang, W.-H.; Seo, K.-S.; Kim, H.; Cha, H.-Y. PECVD SiNx passivation for AlGaN/GaN HFETs with ultra-thin AlGaN barrier. *Solid-State Electron.* **2020**, *173*, 107876. https://doi.org/10.1016/j.sse.2020.107876.

16. Singh, S.P.; Liu, Y.; Ngoo, Y.J.; Kyaw, L.M.; Bera, M.K.; Dolmanan, S.B.; Tripathy, S.; Chor, E.F. Influence of PECVD deposited SiNxpassivation layer thickness on In0.18Al0.82N/GaN/Si HEMT. *J. Phys. D Appl. Phys.* **2015**, *48*, 365104. https://doi.org/10.1088/0022-3727/48/36/365104.

17. Yun, S.J.; Efremov, A.; Kim, M.; Kim, D.-W.; Lim, J.W.; Kim, Y.-H.; Chung, C.-H.; Park, D.J.; Kwon, K.-H. Etching characteristics of Al2O3 thin films in inductively coupled BCl3/Ar plasma. *Vacuum* **2008**, *82*, 1198-1202. https://doi.org/10.1016/j.vacuum.2007.12.018.

18. Koo, S.-M.; Kim, D.-P.; Kim, K.-T.; Kim, C.-I. The etching properties of Al2O3 thin films in N2/Cl2/BCl3 and Ar/Cl2/BCl3 gas chemistry. *Mater. Sci. Eng. B* **2005**, *118*, 201-204. https://doi.org/10.1016/j.mseb.2004.12.029.

19. Harrison, W.A. *Electronic Structure and the Properties of Solids: The Physics of the Chemical Bond*; Dover Publications: New York, NY, USA, 1989.

20. Chowdhury, T.; Hidayat, R.; Kim, H.-L.; Mayangsari, T.R.; Cho, S.; Park, S.; Jung, J.; Lee, W.-J. Density functional theory study on the modification of silicon nitride surface by fluorine-containing molecules. *Appl. Surf. Sci.* **2021**, *554*, 149481. https://doi.org/10.1016/j.apsusc.2021.149481.

21. Fesiienko, O.; Petit-Etienne, C.; Darnon, M.; Soltani, A.; Maher, H.; Pargon, E. Plasma induced damage on AlGaN/GaN hetero-structure during gate opening for power devices. *J. Vac. Sci. Technol. A* **2023**, *41*, 033004. https://doi.org/10.1116/6.0002339.

22. Chen, D.; Xu, D.; Wang, J.; Zhao, B.; Zhang, Y. Dry etching of AlN films using the plasma generated by fluoride. *Vacuum* **2008**, *83*, 282-285. https://doi.org/10.1016/j.vacuum.2008.07.007.

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