# RSFQ comparator behaviour modelling for sigma-delta bandpass ADC application with VHDL-AMS

Rachid Guelaz, Patricia Desgreys, Patrick Loumeau, Pascal Febvre

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Rachid Guelaz, Patricia Desgreys, Patrick Loumeau, Pascal Febvre. RSFQ comparator behaviour modelling for sigma-delta bandpass ADC application with VHDL-AMS. Conference on Design of Circuits and Integrated Systems (DCIS), Nov 2008, Grenoble, France. hal-04930556

HAL Id: hal-04930556

https://cnrs.hal.science/hal-04930556v1

Submitted on 5 Feb 2025

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# RSFQ comparator behaviour modelling for sigma-delta bandpass ADC application with VHDL-AMS

Rachid Guelaz<sup>(1)</sup>, Patricia Desgreys<sup>(1)</sup>, Patrick Loumeau<sup>(1)</sup> and Pascal Febvre<sup>(2)</sup>

<sup>(1)</sup> L.T.C.I.-CNRS-UMR 5141- Institut Telecom - Telecom Paristech, 75013 France

<sup>(2)</sup> LAHC - Campus scientifique CNRS-UMR 5130 University of Savoie 73376 Le Bourget du Lac Cedex, France

Contact: rachid.guelaz@telecom-paristech.fr

## Abstract:

This paper presents the behavioural modelling with VHDL-AMS of the superconducting comparator which is part of a sigma-delta bandpass ADC based on RSFQ (Rapid Single Flux Quantum) technology. We studied an architecture based on Josephson junctions described with VHDL-AMS models. We developed our Josephson junction model by implementing RCSJ electrical model with the specificities of VHDL-AMS language. Then, once proving the feasibility and good operation of the comparator, we assimilated SFQ pulses to ideal rectangular pulses to simplify comparator behaviour and simulations. In this manner, we studied the performance of sigma delta bandpass ADC. Pulses duration is directly a physical parameter obtained from superconducting technology. Finally, we show simulated relations between ADC performances (SNR) and the duration of comparator pulses in the case of rectangular form.

## 1. Introduction:

Recent advances in RSFQ (Rapid Single Flux Quantum) technology promise opportunity to get better performance compared to CMOS technology [1] for specific applications such as spatial telecommunications. Sigma-delta bandpass ADC [2] is an element that could be implemented in software radio communication systems [3] in replacement of classic time-interleaved architecture. Sigma-delta is well known to be an efficient converter because of its simple architecture, easy to implement and composed with basic elements. RSFQ technology exploits sigma-delta advantages because of the capability to operate at several hundred GHz [4, 5, 6]. To perform actual converter, we propose to identify sigma delta ADC classic structure to a converter using Josephson junctions which compose principally the ADC comparator and the clock

generation. To reproduce sigma-delta principle, a feedback must be operated between output and input. SFQ pulses generated by the Josephson junctions of the balanced comparator are studied and quantized to reproduce this feedback effect. Pulse form and duration determine directly the ADC performance, the dependence is shown on the particular parameter SNR. To simplify the ADC conception with performance rapid estimation, we assimilated SFQ pulses to rectangular forms with area and duration in agreement to the real case. We study pulses effect in the current across the resonator. VHDL-AMS language [7] permits us in this particular case to reproduce pulses effect in the system modelling with the use of “break” statement. Precedent work [8] has considered SFQ (Single Flux Quantum) pulses as Dirac forms, but model could be improved with incorporation of the pulse duration.

## 2. Josephson junction model:

Basis of RSFQ technology lies on the use of the Josephson junction properties which is a three layers material composed by two superconducting materials separated by a thin metallic layer (SNS). Principal property of the junction is to have perfect voltage oscillator behaviour when it was polarised with a constant current above its critical current $I_c$. Oscillating frequency could be in the order of several hundred GHz. Junction model is based on the writing of each branch of the RCSJ (Resistively and Capacitively Shunted Junction) circuit composed by an ideal current source with $I_c$ the critical current, in parallel with a resistance R and a capacitance C as illustrated by figure (1).
<figure><img src="image_2.png" /><figcaption>Figure 1: RCSJ Josephson junction electric model.</figcaption></figure>

The relation between junction phase $\Phi$ and RCSJ model can be written as the equation (1).

$$I_{sj} = I_c \cdot \sin(\phi) + \frac{\phi_0}{2 \cdot \pi \cdot R} \cdot \frac{d\phi}{dt} + \frac{\phi_0 \cdot C}{2 \cdot \pi} \cdot \frac{d^2\phi}{dt^2} \quad (1)$$

Where $I_{sj}$ is the current across the junction and $\Phi_0$ is the flux quantum constant equal to $2.07\mu V/\text{GHz}$. Implementation with VHDL-AMS language is given by this code:

**Entity JosephsonJunction is**

generic (Ic : real;

Rn : real;

Cs : real);

port ( terminal ta, tb : electrical );

**End entity JosephsonJunction;**

**Architecture behaviour of JosephsonJunction is**

Quantity Vq across i1, i2, i3 through ta to tb;

**Begin**

i1 == Ic*sin(2.0*MATH_PI/2.075e-15*Vq'integ);

i2 == Vq/Rn;

i3 == Cs*Vq'dot;

**End Architecture behaviour;**

## Code 1: VHDL-AMS Josephson junction code

First part of the code specifies the junction parameters $I_c$, $R_n$, $C_s$ as real constants. Then, RCSJ model is described with separation of each branch equation. Currents sum $i_1$, $i_2$ and $i_3$ is the interpretation of equation (1).

### 3. Comparator composed by Josephson Junctions synchronised with clock:

As presented in the figure (2), comparator in RSFQ is based on the use of two junctions, one of which (JJ3 in figure (2)) has higher critical current. Comparison is made on the input current, if it is positive, an SFQ pulse is generated at the output. If it is negative, output is unchanged. SFQ pulse is interpreted as “1” logic level, otherwise it’s a “0” logic level.

<figure><img src="image_3.png" /><figcaption>Figure 2: SFQ comparator with clock stimulation</figcaption></figure>

The clock is generated by polarisation of junction JJ1 at a constant current. JJ1’s critical current is fixed at approximately a value corresponding to sum of JJ2 and JJ3 critical currents. $L_4$ inductance is set to a value ensuring that the comparison results appear between two SFQ clock pulses. $I_p$ is the comparator polarisation current.

In accordance to technology Nb/AlOx/Nb with parameter $R_nI_c = 300\mu V$ [5], we obtain a clock at 60GHz ($T=16.6\text{ps}$) with:

$V_c = 1.15 \text{ mV},$

$R_c=1 \text{ Ohm},$

$L_3=1 \text{ pH},$

JJ1: $I_c=542 \mu A$, $R_n=300 \mu/542 \mu = 0.55 \text{ Ohm},$

$C=\Phi_0 \cdot I_c/(2 \cdot \pi \cdot R_n I_c)^2=0.32 \text{ pf}$

We implemented this clock separately and we obtained the simulation results shown in figures 3, 4 and 5. Simulations are executed with Simplorer V7 software.

<figure><img src="image_4.png" /><figcaption>Figure 3: Clock generated at JJ1 junction for a fixed frequency 60GHz</figcaption></figure>

When the sum of the input current $I_x$ and the current across junction JJ2 is above junction JJ3 critical current, a SFQ pulse is generated at the comparator output. With an ideal input current $I_x$, we analyse the output comparator result obtained at JJ3, and JJ2 such as circuit values correspond to:

JJ1: $I_c=900\mu A$

JJ2: $I_c = 300 \mu A$; JJ3: $I_c=310\mu A$

$V_c = 1.2 \text{ mV}$; $R_c = 1 \text{ Ohm}$; $L_3=1 \text{ pH}$; $L_4=4 \text{ pH}$
Coupling the comparator to the clock implies to adjust $I_c$ and $V_c$ values to obtain the same form for the clock.

<figure><img src="image_5.png" /><figcaption>Figure 4: JJ3- Comparator output with input $I_x$ [-300µA; +300µA]</figcaption></figure>

These results show that the comparator is operated as wanted. When the current $I_x$ is near 0, we observe a small variation of the frequency. A theoretical analysis of the junction behaviour should be completed to explain precisely this aspect. Symmetrical signal resulted from JJ2 junction is presented in figure 5.

<figure><img src="image_6.png" /><figcaption>Figure 5: JJ2 junction voltage</figcaption></figure>

For the last part of our study, the SFQ pulses generated by junction JJ3 are assimilated to rectangular pulses with the same area and duration, parameters controlled by fabrication technologic parameters.

## 4. Second Order Sigma-Delta Bandpass ADC:

Sigma delta classic architecture is based on a resonator $H(z)$ with a loop formed by a single comparator as shown in figure 6. For a second order ADC with 1-bit quantization, a simple comparator at the output generates the feedback with 1/-1 (normalised) values.

Theoretical interpretation of the resonator is:

$$H(z) = \frac{-z^{-2}}{1 + z^2} \qquad (2)$$

<figure><img src="image_7.png" /><figcaption>Figure 6: 2nd order Sigma-Delta classic architecture with the corresponding schematic of RSFQ design</figcaption></figure>

To identify sigma delta principle in the RSFQ design, we consider that each SFQ pulse delivered by the comparator, results in the addition or the subtraction of a value $\Delta_{IL}$ to the resonator current $I_L$.

$$\Delta_{IL} = \Phi_0/(2.L) \qquad (3)$$

The resonator current $I_L$ is determined by the circuit equation (with $p$ the Laplace symbol):

$$V_{in}(p) - V_{JJ2}(p) = I_{L}(p) \cdot \left( \frac{1}{C \cdot p} + L \cdot p \right) = I_{L}(p) \cdot \frac{1 + LC \cdot p^2}{C \cdot p} \quad (4)$$

We consider that pulses are bipolar as mentioned in Bulzacchelli work [8]. The figure 7 shows a simplified representation with an idealised comparator.

<figure><img src="image_8.png" /><figcaption>Figure 7: ADC modelling with a comparator generating rectangular bipolar pulses</figcaption></figure>

The comparator effect on the current across the resonator LC is implemented with the statement “break”. This VHDL-AMS instruction makes possible to stop the analogical simulator and to initialize it again with a new value of the current $I_L$. This new value is determined at each clock pulse and is a function of the present value. The code 2 shows the behaviour of the resonator with the
comparator effect included in the "break" statements.

**Entity ResonatorLC is**

generic (L : real; C : real);
port ( terminal ta,tb : electrical);

**End entity ResonatorLC;**

**Architecture behaviour of ResonatorLC is**

Terminal tc : electrical;
Quantity VC across IC through ta to tc;
quantity VL across IL through tc to tb;

**Begin**

break IL => IL - 2.075e-15/(2.0*L)
when clk'event and clk = '1' and IL >= 0.0;
break IL => IL + 2.075e-15/(2.0*L)
when clk'event and clk = '1' and IL < 0.0;

Ic == C*VC'dot;

VL == L*IL'dot;

**End architecture behaviour;**

## Code 2: VHDL-AMS Resonator code with comparator effect on the current

To implement pulse duration, we introduce this parameter into the comparator VHDL-AMS model as shown in the Code 3:

**Entity Compaldeal is**

generic (Dt : Time);
port (terminal ta,tb : electrical');

**End Entity Compaldeal;**

**Architecture behaviour of Compaldeal is**

Quantity vq2 across iq2 through ta to tb;
signal output : real := 0.0;

**Begin**

Process(clk) is
begin
  if (clk'event and clk='1') then
    if (iq2 >= 0.0) then
      output <= -1.0,0.0 after Dt; else
      output <= 1.0,0.0 after Dt;
    end if;
  end if;
  end Process;
vq2 == -2.075e-15/2.0/(real(Dt/fs)*1.0e-15)*output;

**End architecture behaviour;**

## Code 3: VHDL-AMS Resonator code with comparator effect on the current

## 5. Simulation results:

To illustrate sigma-delta bandpass ADC operation, we implement the structure of the figure 6 written in VHDL-AMS into the Smash-Dolphin® software. The converter is specified for a clock system fixed at 120GHz. Simulations are done for an over sampling ratio of 120 and a bandwidth of 500MHz. We study specifically the SNR as a function of the pulse duration generated by the comparator. The pulse duration is included in the range 1fs to 2,5ps. Figure 8 shows the pulses effect and the ADC output, obtained with the Code 4,

compared to results obtained with SFQ pulses in figure 9 when ADC simulated results with the real comparator including Josephson junctions.

<figure><img src="image_9.png" /><figcaption>Figure 8: Simulation results with ideal pulses effect on the current.</figcaption></figure>

<figure><img src="image_10.png" /><figcaption>Figure 9: Comparison with SFQ pulses</figcaption></figure>

**Architecture behaviour of tb_ADC_Supra is**

Terminal ta,tb : electrical;
Quantity vin across iin through ta to ground;
Signal clk_compa : bit := '0';
Constant Dt : Time := 0.0834ps;
Constant Phio : real := 2.075e-15;

**Begin**

-- Clock system
Process (clk_compa) begin
  if clk_compa = '1' then
    clk_compa <= '0' AFTER 4.17ps;
  else
    clk_compa <= '1' AFTER 4.17ps;
-- Input Signal with amplitude = $\Phi_0/(2.T_e)$

vin == Phio/(2.0*8.34e-12)*sin(2.0*MATH_PI*30.1e9*now);

-- Resonator

Resonator1: entity work.ResonatorLC (behaviour)

generic map (28.15e-12,1.0e-12) - L - C => 30Ghz

port map ( ta => ta, tb => tb);

-- Comparator and ADC output (+/-1)

Comunalde1: entity work. Comunalde(behaviour)

generic map (Dt)

port map ( ta => tb, tb => ground);

End;

## Code 4: VHDL-AMS Sigma Delta Band Pass ADC code in the ideal case

Current variations are in the two cases equal to the quantified value $\Delta IL = \Phi_0/(2.L)$. The SNR of the idealized structure is obtained with the spectral analysis of the output voltage. For a Blackman windowing with 16384 points, we obtain the result illustrated by figure 10.

<figure><img src="image_11.png" /><figcaption>Figure 10: Output spectral analysis</figcaption></figure>

Noise Transfer Function is highlighted in this result with its particular form of rejected noise out of the interest bandwidth (29,5GHz – 30,5GHz). Signal is identified at the particular frequency of 30,1GHz. Figure 11 shows the evolution of the SNR (dB) as a function of the pulse duration that is a varying parameter in the simulations.

SNR (dB)

$$y = -5E-07x^2 - 0,0011x +$$

$$54,892$$

$$R^2 = 0,6393$$

$$\delta t (10^{-12} s)$$

<caption>Figure 11: SNR in function of the pulse duration for an over sampling ratio of 120</caption>

This result shows that the SNR is a quasi-linear function of the comparator pulse duration. In particular, if the duration is under 2.2 ps, the SNR obtained is in the range [55 – 50] dB which corresponds to 8 bits resolution. Best results are around 55db and obtained when $\delta t << T/100$ where T is the clock period.

## 6. Conclusion:

In this work, we propose an approach to estimate performance of a superconducting sigma-delta bandpass ADC in RSFQ technology. We assimilate comparator behaviour to a pulses generator parameterized by the duration of its pulses. We show that the increase of comparator pulse duration implies quasi-linear decrease of the SNR. In the next step, simulations should give rapidly the ADC performance when using the complete circuit with Josephson junctions.

## Acknowledgments:

This work is supported by ANR-Project: HyperScan - ANR/06 TCOM 023.

## Bibliography:

[1] O.A. Mukhanov, V.K. Semenov, and al.: "High-resolution ADC operating at 19,6 GHz clock frequency", Superconductor Science and Technology, pp.1065-1070. 2001.

[2] R. Schreier, G. C. Temes: "Understanding Delta-Sigma Data Converters", Wiler Interscience, 2005.

[3] P. Loumeau, L. Naviner and J.F. Naviner: "Analog-to-digital conversion for software radio", in Reconfigurable Mobile Radio Systems: A Snapshot of Key Aspects Related to Reconfigurability in Wireless Systems, GB, Iste Publishing Company. 2007.

[4] E. Baggetta, R. Setzu, J-C. Villégier, M. Maignan: "Implementation of basic NBN RSFQ Logic Gates of a wide-Band Sigma-Delta Modulator", Applied Superconductivity Conference, Seattle. 2006.

[5] E. Baggetta, R. Setzu, J-C. Villégier: "Study of SNS and SIS NbN Josephson junctions coupled to a microwave band-pass filter", Conference Series, Vol. 43, 1167-1170. 2006.
[6] K.K. Likharev, V.K. Semenov, “RSFQ Logic/Memory Family: A new Josephson-Junction Technology for Sub-Terahertz-Clock-Frequency Digital systems”, IEEE Trans. on Applied Superconductivity, pp. 3-28. 1991.

[7] IEEE STD 1076.1-1999: IEEE Standard VHDL Analog and Mixed Signal extensions.SH94731, IEEE Press. 1999.

[8] J. Bulzachelli: “A superconducting Bandpass Delta-Sigma Modulator for direct Analog-to-Digital Conversion of microwave Radio”, Ph.d. thesis, Massachusetts Institute of Technology. 2003.