# Three-Phase PFC Rectifier with only two AC-side Transistors P2S6

Simon Peter, Karl Stephan Stille, Jan Boris Loesenbeck

► To cite this version:

Simon Peter, Karl Stephan Stille, Jan Boris Loesenbeck. Three-Phase PFC Rectifier with only two AC-side Transistors P2S6. The 26th European Conference on Power Electronics and Applications, GDR SEEDS France & EPE Association, Mar 2025, Paris, France. 10.34746/epe2025-0087. hal-05088909

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Submitted on 28 May 2025

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<figure><img src="image_1.png" /></figure>

Distributed under a Creative Commons Attribution 4.0 International License
Three-Phase PFC Rectifier with only two AC-side Transistors
P2S6

Simon Peter, Karl Stephan Stille, Jan Boris Loesenbeck

Power Electronics Group

Hochschule Bielefeld – University of Applied Sciences and Arts

Bielefeld, Germany

E-Mail: {simon.peter,ks.stille,jan_boris.loesenbeck}@hsbi.de

URL: https://www.hsbi.de/

*Index Terms*—AC-DC converter, Power factor correction, DC power supply, Voltage Source Converter (VSC), Switched-mode power supply.

**Abstract**—A novel three-phase AC/DC converter topology consisting of an input side pulse inverter and an output side rectifier is presented. The pulse inverter produces an electrically isolated three-phase voltage using only two active switches. This voltage is rectified by a three-phase boost converter. A control scheme with internal hysteresis control is designed for the rectifier, which allows fast current adjustment and ensures PFC operation. The topology is simulated and verified in practice.

# I. INTRODUCTION

Rectifiers are commonly used to power various DC loads, such as IT components, batteries and electrolysers for hydrogen production [1]. Converters that supply loads exceeding 3 kW are typically designed with a three-phase supply without neutral. This design allows for a continuous power flow throughout the grid period. Additionally, separate loads, independent circuits and any protective measures may require an electrically isolated output voltage [2]. To reduce weight and construction volume, high-frequency transformers are used for galvanic isolation [3]. The DC voltage is typically generated in two stages: potential isolation and rectification. These circuits require a high number of switchable semiconductors, many of which must be designed for high peak voltages [2]–[4].

Therefore, a new inverter topology is presented in this paper. The topology is shown in figure 1 and consists of a pulse inverter with galvanic isolation and a rectifier. This topology utilizes only two active semiconductor switches for high voltages, resulting in lower cost and efficiency advantages. The objective of this work is to

rectify the output voltage of the pulse inverter. A suitable rectifier circuit is selected for the output voltage of the pulse inverter and a control concept is designed. The control of the pulse inverter proves to be simple. The rectifier is driven by a hysteresis controller, which ensures fast current adjustment and also generates a sinusoidal input current for the entire inverter topology. The topology and its control are verified by simulation and finally validated in practice.

# II. COMPARISON WITH A CONVENTIONAL CONVERTER

<figure><img src="image_2.png" /><figcaption>Fig. 1: The three-phase inverter topology consisting of the P2 pulse inverter followed by a S6 rectifier.</figcaption></figure>

Conventional three-phase AC/DC converters with galvanic isolation are based on a multi-stage principle, whereby each stage requires several switchable semiconductor elements [5]. The widely used topology
<figure><img src="image_3.png" /><figcaption>Fig. 2: Conventional three-phase AC/DC converters consisting of 14 transistors.</figcaption></figure>

shown in figure 2 consists of a fully controlled rectifier with six switchable semiconductors. A high-frequency transformer, controlled by two full bridges with a total of 8 switches, generates the galvanically isolated output voltage from the DC link voltage. A total of 14 semiconductor switches are required, ten of which must be designed for high voltages. Special hardware is required for the operation of such converters to ensure precise control of the individual semiconductor switches. The two stages are usually operated with cascaded controls.

## A. Proposed Topology

In the following, a new two-stage inverter from the topology set in [6] is presented, which is shown in figure 1. The corresponding block diagram is displayed in figure 3. The primary side consists of three push-pull flow converters with center tapping, to which the three-phase mains are connected. The upper and lower winding ends are each connected to a B6 diode bridge with a parallel semiconductor switch. There are two primary switches in total, resulting in four possible switching states. However, simultaneous switching of both switches is not permitted, as this is equivalent to a short circuit due to the opposite winding direction.

The push-pull operation of the primary circuit is illustrated in figure 4 with an assumed grid polarity of $u_{AC1}$, $u_{AC2}$ > 0 and $u_{AC3}$ < 0. When the switch $S_{P1}$

is closed, the cores of the push-pull transformer are magnetised by the marked current flow across the upper diode bridge. If the switch $S_{P1}$ is open and $S_{P2}$ is closed, the current flows through the lower diode bridge. Due to the opposing winding, the transformer is magnetised in the opposite direction. The alternating activation of the switches causes an alternating flow in the transformer. The pulse inverter thus generates an isolated three-phase voltage with only two semiconductor switches, which is why this part of the circuit is labelled P2.

If the maximum blocking voltage of the semiconductor switches $u_{DS,max}$ mentioned in [7] is adapted to the present three-phase case, the switches are exposed to twice the peak mains voltage given by the equation 1.

$$u_{DS,max} = 2 \cdot \sqrt{2} \cdot U_{AC12} = 2 \cdot \sqrt{2} \cdot \sqrt{3} \cdot U_{AC1} \quad (1)$$

The output voltage $u_{Sk}$ of the pulse inverter alternates with the switch control on the primary side and is enveloped by a sinusoidal envelope as shown in figure 5. $D_P$ is the duty cycle, which is in the range $0 < D_P < 0.5$. $T_{PP}$ is the duration of the primary-side pulse phase in which one of the two primary switches is closed. $T_P$ measures the duration of a primary-side cycle consisting of the two pulses of the primary switches. The pulse frequency of the transistors $f_P$ is much higher than the grid frequency. A mains filter is connected upstream

<figure><img src="image_4.png" /><figcaption>Fig. 3: Block diagram of the inverter, consisting of mains filter, pulse inverter and rectifier.</figcaption></figure>
<figure><img src="image_5.png" /><figcaption>(a) Switch $S_{P1}$ is closed</figcaption></figure>

<figure><img src="image_6.png" /><figcaption>(b) Switch $S_{P2}$ is closed</figcaption></figure>

Fig. 4: Illustration of the current path and the output voltage $u_{Sk}$ of the pulse inverter. A grid polarity of $u_{AC1}$, $u_{AC2} > 0$ and $u_{AC3} < 0$ is assumed.

of the primary side in order to smooth out the high-frequency pulsating input current.

The task of the secondary side is to rectify the alternating pulse pattern of the primary side. The secondary side is designed as a fully controlled rectifier and operates in boost converter mode. It enables the setting of

<figure><img src="image_7.png" /><figcaption>(a)</figcaption></figure>

<figure><img src="image_8.png" /><figcaption>(b)</figcaption></figure>

Fig. 5: The three-phase output voltage $u_{Sk}$ with $k \in \{1, 2, 3\}$ of the pulse inverter is enclosed by the grid-side sine envelope (a). Few primary-side pulses are shown in (b). The polarity alternates due to the alternating control of the primary switches.

any input current, which is important for PFC operation. Due to the winding ratio of the primary side, the six switches on the secondary side only need to be designed for low voltage. The secondary side is labelled S6.

The main advantage of the P2S6 topology is that only two semiconductor switches have to be designed for high voltages, compared to 10 high voltage semiconductor switches in the conventional topology (figure 2). PFC operation is also possible with appropriate regulation and an upstream mains filter. However, bidirectional power flow is not possible due to the pulse inverter.
### III. CONTROL OF THREE-PHASE VSR

<figure><img src="image_9.png" /><figcaption>Fig. 6: The fully controlled three-phase VSR.</figcaption></figure>

<figure><img src="image_10.png" /><figcaption>Fig. 7: Switching behaviour with the voltage ratios: $u_{S1}$, $u_{S2}$ > 0 and $u_{S3}$ < 0.</figcaption></figure>

The S6 will be analyzed in more detail. It is connected to the pulse inverter as shown in figure 1. With a fully controlled rectifier, the losses can be reduced because commutation of the current to the diodes can be largely avoided. The circuit depicted in figure 6 is also known as a voltage source rectifier (VSR) because the DC output voltage can be regulated by suitable control of the switches [8]. Due to the fully controlled circuit and Kirchhoff's first law, two of the three input currents can be set independently [4].

To maintain the circuit in boost converter mode and ensure that the diodes always block, the DC output voltage

$u_{DC}$ must exceed the peak phase-to-phase secondary voltage $U_{S12}$ [2].

$$u_{DC} > \sqrt{2} \cdot U_{S12} = \sqrt{2} \cdot \sqrt{3} \cdot U_{S1} \quad (2)$$

Power can only be drawn from the grid during a primary-side pulse due to the upstream pulse inverter. The rectifier's control must ensure a current consumption $i_{Sk}$ that corresponds to the polarity of the voltage $u_{Sk}$, as shown in figure 8. The voltage $u_{Sk}$ is enclosed by a sinusoidal envelope, with its polarity alternating with each primary-side pulse. Since the magnitude of the input current of the pulse inverter $i_{Pk}$ is proportional to the magnitude of the output current $i_{Sk}$, it is important that the current curve follows a sinusoidal envelope for maintaining PFC operation. To achieve this, the pulsing sinusoidal input current $i_{Pk}$ must be filtered to convert it into a pure sinusoidal input current ($i_{ACk}$ in figure 3). This will minimize grid perturbations caused by harmonics and reactive power [4]. The fully controlled rectifier circuit enables current control on all phases, but power cannot be fed back into the grid due to the pulse inverter.

Figure 9 shows the control of the fully controlled three-phase rectifier using a cascaded control structure. The outer control loop (a) controls the output DC voltage $u_{DC}$, while the inner hysteresis controllers (b) are responsible for setting the current for the respective phase. The control structure's functionality is explained below.

#### A. Voltage and Current control

The voltage controller $G_u$ in the outer control loop utilizes the deviation between the DC output voltage $u_{DC}$ and its reference value $u_{DC,ref}$ to generate the required peak value of the input current $\hat{i}_{S,ref}$. For the inner control loop there are several control techniques that aim to produce a control signal for the switches based on the current set point value [9]. In this case, hysteresis control is used for the current setting. Hysteresis controls are stable and simple controls that enable rapid current adjustment [9]. Due to the three input currents $i_{Sk}$, a hysteresis control acts on each half-bridge branch (illustrated in figure 9 in gray). The hysteresis control directly influences the input current of the rectifier by changing the switching state as soon as the hysteresis

<figure><img src="image_11.png" /><figcaption>Fig. 8: Principle of secondary side voltage and current (longer pulses than real).</figcaption></figure>
<figure><img src="image_12.png" /><figcaption>Fig. 9: Control structure consisting of voltage controller (a) and (hysteresis) current controller (b).</figcaption></figure>

band is exceeded or undershot. $i_{Sk,ref}$ serves as the set point for the hysteresis control, the calculation of which is explained below.

1) *Sine multiplication:* To ensure PFC operation, the current set point $i_{Sk,ref}$ and the voltage, $\hat{i}_{S,ref}$ is multiplied by the magnitude of the sine function which is in phase with the input voltage $u_{ACk}$.

2) *Alternating polarity:* The polarity of the current set point $i_{Sk,ref}$ must match that of the voltage $u_{Sk}$. Therefore, the sign is adjusted by multiplying it with the sign function.

3) *Active hysteresis controller:* Due to Kirchhoff's first law only two current controllers can be active at the same time. The third current is a result of the two regulated currents, but may exceed the hysteresis band [9] (cf. blue line in figure 11).

The polarity of the input voltage $u_{Sk}$ during a primary-side pulse determines which bridge branch is affected by its hysteresis control and which is positively driven. In figure 7, for example, a state is selected where $u_{S1}$ and $u_{S2}$ have a positive and $u_{S3}$ a negative voltage. In this state, switch $S_{3L}$ remains permanently closed, while $S_{1\{L,H\}}$ and $S_{2\{L,H\}}$ are controlled by their hysteresis controls. When $S_{\{1,2\}L}$ is closed, the current through this phase increases and the inductance magnetizes. Changing the switching state ($S_{\{1,2\}H}$ close) causes demagnetization, whereby energy is transferred to the DC voltage side. The first and second half-bridge branches can be switched independently of each other. Table I lists the bridge branches that are controlled by their hysteresis controllers depending on the voltage states. This corresponds to the block $f(u, en)$ in figure 9.

<table><caption>TABLE I: Switching states as a function of the input voltages and the enable signal</caption><thead><tr><th rowspan="2">Enable</th><th rowspan="2">Input voltages</th><th colspan="3">Half bridge states</th></tr><tr><th>S<sub>1</sub>{L,H}</th><th>S<sub>2</sub>{L,H}</th><th>S<sub>3</sub>{L,H}</th></tr></thead><tbody><tr><td>α<sub>en</sub></td><td>u<sub>S1</sub> u<sub>S2</sub> u<sub>S3</sub></td><td colspan="3">Not possible</td></tr><tr><td>X</td><td>+</td><td>+</td><td>+</td><td></td></tr><tr><td>1</td><td>+</td><td>+</td><td>-</td><td></td></tr><tr><td>1</td><td>+</td><td>-</td><td>+</td><td></td></tr><tr><td>1</td><td>+</td><td>-</td><td>-</td><td></td></tr><tr><td>1</td><td>-</td><td>+</td><td>+</td><td></td></tr><tr><td>1</td><td>-</td><td>+</td><td>-</td><td></td></tr><tr><td>1</td><td>-</td><td>-</td><td>+</td><td></td></tr><tr><td>X</td><td>-</td><td>-</td><td>-</td><td>Not possible</td></tr><tr><td>0</td><td>X</td><td>X</td><td>X</td><td></td></tr></tbody></table>

X: don't care.

+: $u_{Sk} > 0$.

-: $u_{Sk} < 0$.

Half-bridge state indicates whether the switches are hysteresis controlled or forced.
4) Primary-side Zero Switching: During the primary-side pulse, one of the primary switches is closed. This causes a current to flow through the windings, leading to magnetization of the push-pull flow converter. To prevent voltage peaks at the primary switches caused by remaining magnetization, it is important to only open the primary switches when they are not carrying current. As shown in figure 8, the current drops to zero before the end of the pulse period. This is accomplished through the enable signal ($\alpha_{en}$), as indicated in table I and illustrated in figure 11. The enable signal has twice the frequency and the positive edge is synchronised with one of the positive edges of the primary switch signals (figure 5). The pulse width is also reduced compared to the primary switch signals.

## IV. SIMULATION

The functionality of the previously developed inverter concept is tested as part of a simulation. The pulse inverter and the fully controlled rectifier are simulated as a complete system using PLECS. The simulation parameters are listed in table II.

<table><caption>TABLE II: Operation Parameters</caption><thead><tr><td>Parameter</td><td>Simulation Value</td><td>Experimental Value</td></tr></thead><tbody><tr><td>Grid Voltage U<sub>AC</sub></td><td>230 V</td><td>40 V</td></tr><tr><td>Grid Frequency f<sub>AC</sub></td><td>50 Hz</td><td>50 Hz</td></tr><tr><td>Transformer turns ratio a</td><td>15</td><td>3.67</td></tr><tr><td>Primary pulse frequency f<sub>P</sub></td><td>15 kHz</td><td>17.5 kHz</td></tr><tr><td>Primary Duty cycle D<sub>P</sub></td><td>0.45</td><td>0.45</td></tr><tr><td>Inductances L<sub>k</sub></td><td>1.5 μH</td><td>3.3 μH</td></tr><tr><td>Hysteresis band i<sub>Sk, err</sub></td><td>±5 A</td><td>±3 A</td></tr><tr><td>DC output voltage u<sub>DC, ref</sub></td><td>48 V</td><td>40 V</td></tr><tr><td>DC capacitor C</td><td>1 mF</td><td>154 μF</td></tr><tr><td>DC load resistance R</td><td>3 Ω</td><td>10 Ω</td></tr></tbody></table>

Figure 10 shows the voltages $u_{P_k}$ and the currents $i_{P_k}$ over a half grid-side period. It can be seen that both the voltage and the current are enclosed by a sinusoidal envelope.

Figure 11 displays the voltage and current progression over a shorter time interval. The first bridge branch (switch $S_{1\{L,H\}}$) is positively driven during the periods, while the second and third bridge branches are influenced by their hysteresis control (see table I). At the start of each pulse on the primary side, the current approaches its set point value and is maintained around this value by the hysteresis current controller. The hysteresis interval of $\Delta I = 10$ A is not exceeded for $i_{S2}$ and $i_{S3}$, while $i_{S1}$ may be exceeded briefly. The effect of the enable

<figure><img src="image_13.png" /><figcaption>Fig. 10: Grid side voltage and current (dark colors) and primary current after filter (light colors).</figcaption></figure>

signal is also recognizable. The transistors are switched off before the end of the pulse on the primary side, which causes the current to drop to zero before the primary side is switched off.

## V. PRACTICAL REALISATION

To verify the functionality of the P2S6 converter in practice, the S6 rectifier was designed as shown in figure 12 and connected to the existing P2 pulse inverter.

### A. System design

The rectifier bridges were built with three EPC90154 half-bridge development boards, which contain EPC2088 GaN power mosfets and are suitable for switching frequencies up to the MHz range. The hardware design is aimed at flexible control of the half bridges, whereby the behaviour at different operating points, such as with different hysteresis bands, can be evaluated. The control of the primary and secondary circuits is thereby realised by a microcontroller on which the control structure shown in figure 9 is implemented. The block diagram for pulse generation, which is explained next, is shown in figure 13.

The core elements for the pulse pattern calculation are the model of the control structure, as explained above, as well as models of the subcircuits, i.e. the P2 pulse inverter and the S6 rectifier. The two circuit models only require measurement of the DC output voltage and synchronisation to the mains frequency, all other state variables can be calculated internally. The P2 model utilises the present mains phase position and knowledge of the P2 switch control to calculate the secondary-side input voltage. This voltage is then used as an input as well as the setpoint current for the S6 model
<figure><img src="image_14.png" /><figcaption>Fig. 11: Voltage and current curves of primary-side periods. The course of the switch states, determined by the hysteresis control, ensures the current setting. The enable signal terminates the current control early.</figcaption></figure>

to perform hysteresis control predictively. Through this process, the predicted pulse pattern is calculated. High-frequency detection of the input current is therefore not necessary. The pulse pattern is then available as an array and is loaded into the timers using DMA (Direct Memory Access), from where it is finally output at the pins of the microcontroller.

## B. Experimental Results

The operating point for the following figures is listed in the table II on the right. The two primary switches are controlled with a fixed duty cycle of $D_p = 0.45$. Figure 14 shows that the S6 rectifier works as a boost converter in each primary-side pulse period and thus generates a constant DC output voltage. Due to the pre-calculated pulse pattern, the hysteresis band is not exactly maintained. However, it can be clearly seen that the current strives its setpoint value at the beginning of each period, is maintained around this value and is

<figure><img src="image_15.png" /><figcaption>Fig. 12: Hardware structure of the S6 rectifier. The half-bridge branches are realised with EPC GaN evaluation boards, which are controlled by a STM32.</figcaption></figure>

<figure><img src="image_16.png" /><figcaption>Fig. 13: Predicted pulse pattern calculation using models of the control strucute, the P2 and the S6. DMA and timer are used to output the pulse.</figcaption></figure>

brought back to 0 A before the end of the primary-side pulse. The switching frequency on the secondary side is around $f_S = 500$ kHz.

The circuit is powered by a Chroma AC source. At the mains side before the P2 pulse inverter, just 1.5 µF capacitors are connected in star. Figure 15 shows that due to the high pulse frequency, these capacitors are already sufficient to draw a sinusoidal input current. The power factor here is $PF \ge 0.99$.

The efficiency of the S6 rectifier is strongly influenced by whether the current is commutated to the mosfet body diodes. It is therefore important to minimise the dead time between the upper and lower mosfets. The
<figure><img src="image_17.png" /><figcaption>Fig. 14: Measured DC output voltage and secondary input current on the S6 rectifier over 4 primary-side pulse periods.</figcaption></figure>

control in combination with the S6 model must also ensure that, unlike in table I, at $\alpha_{en} = 0$ the current to 0 A is conducted via a mosfet and not via the body diode.

As the secondary circuit does not draw any current at the end of a primary-side pulse, the current through the primary switches is reduced to a minimum. However, due to the finite main inductance and the leakage inductance on the primary side of the P2 pulse inverter, a small magnetising current remains. At present, a freewheeling circuit is provided for this by means of snubber networks. A regenerative snubber design is the subject of current investigations.

## VI. CONCLUSION

The presented inverter topology generates an electrically isolated DC voltage using only two switchable semiconductors which must be designed for high voltages. A total of six switches are required for rectification. However, at lower DC voltages, the semiconductors may have a lower voltage capability.

The designed hysteresis current control is capable of reacting to the pulses on the primary side and adjusting

<figure><img src="image_18.png" /><figcaption>Fig. 15: Grid voltage and current measured internally by the Chroma AC source.</figcaption></figure>

the current in a rectangular manner during this time. The PFC operation is maintained by controlling the input current to follow the sinusoidal envelope curve of the input voltage. The practical implementation verified that the new inverter topology, including the control concept, works.

In order to optimise the behaviour of the converter in all load ranges, it can be useful to vary the enable signal. In the partial load range, it can be more efficient to inject shorter secondary-side pulse phases. In the full load range, on the other hand, it is advantageous to utilise the full primary-side pulse phase. The models must therefore be extended to calculate the enable signal depending on the load.

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