# Power Capping Control Across Varying Workloads in HPC

Mohamed Abdeldjalil Maziz

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Mohamed Abdeldjalil Maziz. Power Capping Control Across Varying Workloads in HPC. Automatic. 2025. hal-05226190

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Submitted on 27 Aug 2025

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Université Grenoble Alpes

Master in Systems, Control & Information Technologies
(MiSCIT)

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gipsa-lab

# Power Capping Control Across Varying Workloads in HPC

Prepared by:
Mohamed Abdeldjalil MAZIZ

Academic Supervisor:
Dr. Taha Zoulagh

Internship Supervisors:
Dr. Bogdan Robu
Dr. Sophie Cerf
Abstract

Balancing energy consumption and performance remains a key challenge in high
performance computing (HPC). While static power capping mechanisms such as
RAPL provide basic control, they are not well suited to adapt to dynamically chang-
ing workloads. These workloads often vary in computational intensity, alternating
between compute-bound and memory-bound phases.

As part of this internship, a first step is taken toward developing a dynamic control
framework capable of responding to mixed workload scenarios. Two strategies are
explored: a gain-scheduled PI controller and a *H*<sub>∞</sub> polytopic LPV controller, both
modulated by a scheduling parameter *β*, which represents the ratio of compute to
memory activity. These approaches aim to improve power regulation by adapting
the control action based on workload evolution.

**Keywords:** HPC, Power Capping, Gain-Scheduled Control, LPV Control, Dynamic Systems, Mixed Workloads
List of Figures

<table>
  <tbody>
    <tr>
      <td>1.1</td>
      <td>Architecture of Energy Management System (EMS).</td>
      <td>6</td>
    </tr>
    <tr>
      <td>1.2</td>
      <td>Typical HPC architecture</td>
      <td>7</td>
    </tr>
    <tr>
      <td>1.3</td>
      <td>Workload phases in HPC</td>
      <td>7</td>
    </tr>
    <tr>
      <td>1.4</td>
      <td>Control structure and NRM interaction [6]</td>
      <td>10</td>
    </tr>
    <tr>
      <td>2.1</td>
      <td>LPV system identification methodology</td>
      <td>12</td>
    </tr>
    <tr>
      <td>2.2</td>
      <td>Nonlinear vs Linear model for memory</td>
      <td>13</td>
    </tr>
    <tr>
      <td>3.1</td>
      <td>β-based interpolation of controller and system.</td>
      <td>15</td>
    </tr>
    <tr>
      <td>3.2</td>
      <td>Gain scheduling PI controller performance analysis.</td>
      <td>16</td>
    </tr>
    <tr>
      <td>3.3</td>
      <td>Tracking error analysis for the gain scheduling PI controller.</td>
      <td>16</td>
    </tr>
    <tr>
      <td>3.4</td>
      <td>controller performance under aggressive workload variations.</td>
      <td>17</td>
    </tr>
    <tr>
      <td>3.5</td>
      <td>Generalized H∞ control structure</td>
      <td>19</td>
    </tr>
    <tr>
      <td>3.6</td>
      <td>LPV Controller Performance</td>
      <td>20</td>
    </tr>
    <tr>
      <td>3.7</td>
      <td>Tracking Error Analysis.</td>
      <td>20</td>
    </tr>
    <tr>
      <td>3.8</td>
      <td>LPV Controller Performance under aggressive dynamics.</td>
      <td>21</td>
    </tr>
    <tr>
      <td>3.9</td>
      <td>Tracking Error Analysis under aggressive conditions.</td>
      <td>21</td>
    </tr>
    <tr>
      <td>3.10</td>
      <td>Sensitivity function for the LPV H∞ controller.</td>
      <td>22</td>
    </tr>
  </tbody>
</table>
# List of Tables

<table><tr><td>2.1</td><td>Model Parameters and Variables</td><td>12</td></tr><tr><td>3.1</td><td>PI Controller Performance Specifications</td><td>14</td></tr><tr><td>3.2</td><td>PI Controller Parameters</td><td>15</td></tr><tr><td>3.3</td><td>Performance comparison of PI and LPV H<sub>&infin;</sub> controllers</td><td>22</td></tr></table>
# Chapter 1

# Motivation and Background

## 1.1 Introduction

High performance computing (HPC) refers to the practice of combining multiple computing resources to achieve performance levels that far exceed those of standard workstations. This aggregation of power is essential for solving large-scale problems. Numerous fields rely on high performance computing to tackle computationally intensive problems. For example, applications such as chemical process simulation, numerical weather prediction, finite element analysis, molecular dynamics, quantum chromodynamics, air pollution control, and seismic migration all depend on HPC systems to achieve results that would be unattainable with standard computing resources [17].

Recent advancements in high performance computing continue to push the boundaries of speed and scale. For instance, El Capitan, currently ranked first on the TOP500 list, delivers over 1.7 exaflops using more than 11 million CPU and GPU cores [18]. However, with this increased computational performance comes a significant rise in energy consumption. According to recent estimates, 196 of the TOP500 supercomputers collectively consume around **3 billion kilowatt-hours** of electricity annually, an amount comparable to the yearly usage of several hundred thousand households [14]. This highlights the urgent need for energy-efficient control and management strategies within high performance computing environments.

Several energy-saving mechanisms have been proposed to reduce the power consumption of HPC systems, including techniques such as **Dynamic Voltage and Frequency Scaling (DVFS)** and **Dynamic Power Management (DPM)** that have been widely adopted [4, 6]. These approaches adjust the power usage of system components based on workload activity. Although these mechanisms offer valuable tools for reducing energy use, they often lack direct enforceability or require tight integration with the application and system scheduler [16]. In contrast, **power capping** has emerged as a hardware-supported and enforceable approach to limit power consumption in a predictable manner. Through interfaces like **Intel's Running Average Power Limit (RAPL)**, power caps can be set and enforced directly at the hardware level, ensuring that components such as CPUs stay within specified power limits during runtime [6, 12].
Traditional power capping is typically **static or rule-based**, which means that it does not account for the highly dynamic nature of HPC workloads. Fixed power limits may under-utilize available performance or miss opportunities for energy savings [15]. This issue is further amplified by the dynamic behavior of HPC applications, which often alternate between phases, each one exhibiting different power and performance characteristics, making it difficult for static strategies to maintain efficiency and responsiveness. To overcome these limitations, **control theory** offers a promising alternative [9], such as feedback-based control strategies to continuously monitor performance and power metrics and adapt the power caps in real time.

## 1.2 Energy Management Systems

As HPC systems continue to scale in complexity and performance, energy consumption has become a major design and operational concern. Efficient energy management is critical to maintaining thermal stability, system longevity, and operational costs without sacrificing performance. Modern data centers rely on **Energy Management Systems (EMS)**. These systems operate across multiple layers, from high-level workload management to low-level hardware enforcement.

<figure><img src="image_6.png" /><figcaption>Figure 1.1: Architecture of Energy Management System (EMS).</figcaption></figure>

## 1.3 HPC Architecture and Workload Behavior

High-Performance Computing (HPC) systems are composed of multiple interconnected layers that work together to execute complex, large-scale computations. As illustrated in Figure 1.2, users access the system remotely via login nodes on the frontend, which serves as the entry point for job submission and resource requests. The job scheduler running on management nodes allocates tasks to the compute nodes, which may include
general CPUs, GPUs, and specialized units. These compute resources are connected via a high-speed network, in parallel with storage resources [13].

<figure><img src="image_7.png" /><figcaption>**Figure 1.2:** Typical HPC architecture</figcaption></figure>

HPC workloads typically consist of multiple execution phases. **Compute-intensive** phases rely heavily on CPU or GPU resources to perform floating-point operations. **Memory-intensive** phases demand high bandwidth and low latency access to memory. **I/O-intensive** phases involve frequent data transfer to and from storage. Many applications exhibit hybrid behavior, transitioning between different resource-intensive phases during execution. For instance, molecular dynamics simulations often begin with I/O-intensive phases to load initial configurations, proceed to compute-intensive phases for force calculations, and then enter memory-intensive phases during state updates [2]. These transitions significantly impact both power consumption and performance efficiency. Identifying and adapting to such variations in real time is essential for dynamic power control strategies, as each phase has distinct energy and responsiveness characteristics.

<figure><img src="image_8.png" /><figcaption>**Figure 1.3:** Workload phases in HPC</figcaption></figure>
## 1.4 Power Capping and RAPL

Among the mechanisms available, **power capping** stands out as a practical and enforceable method. It works by imposing upper bounds on the power usage of key components such as CPUs and memory, thereby maintaining operational stability, reducing thermal stress, and minimizing energy costs. One of the most prominent hardware-level solutions for power capping is Intel's **Running Average Power Limit (RAPL)** interface, introduced in the Sandy Bridge microarchitecture [6]. RAPL enables runtime power control by allowing users to configure both a power limit and a time window over which the average power must remain below the threshold. It covers domains such as the CPU package and DRAM and operates through low-level Model Specific Registers (MSRs). Additionally, RAPL includes sensors for energy measurement, enabling accurate monitoring since system startup.

Although RAPL offers a reliable and low-overhead mechanism, it is a *black-box* system: the internal logic and enforcement strategy remain undocumented. Studies have shown that RAPL exhibits nonlinear and platform-dependent behavior [6, 15]. For example, the actual power consumption may overshoot or saturate. Furthermore, static RAPL settings do not adapt to the application's execution phase, leading to either underutilized performance potential or wasted energy. While RAPL is specific to Intel processors, AMD platforms also expose power and energy data through mechanisms such as Application Power Management (APM) and system energy counters, though these are often less standardized [1, 8].

## 1.5 Control-Based Approaches

The limitations of static or rule-based power capping mechanisms, such as Intel's RAPL, have motivated the integration of control-theoretic methods into HPC power management [9]. Control theory offers a principled framework for designing feedback mechanisms that can dynamically regulate power based on the observed behavior of the system. Unlike fixed policies, feedback control systems continuously monitor performance indicators such as progress and adjust control inputs. These approaches are particularly well-suited to the dynamic and phase-varying nature of HPC workloads.

Recent work has shown the viability of using classical controllers such as proportional-integral (PI) control to dynamically modulate RAPL power limits while preserving performance. For example, [6] propose a PI control loop that regulates processor power in real time. Their experiments on multiple clusters show substantial energy savings with bounded performance degradation. Also building on this work, [12] proposed adap-
tive control strategies that adjust controller parameters online, enhancing responsiveness. Other work [10] further extended this to Model Predictive Control (MPC) schemes. Recent work on compute-intensive benchmarks [11] introduced robust cascade-based control strategies to handle model uncertainties and external disturbances. The approach achieved up to 25% energy savings with minimal performance degradation, highlighting the practical potential of control-based power regulation in real-world HPC systems.

However, these studies typically evaluate control strategies on fixed workload types either compute-bound or memory-bound. In contrast, this work introduces a **control architecture** that dynamically handles mixed workloads.

## 1.6 Feedback Control Architecture

The control architecture consists of a closed-loop feedback mechanism that dynamically regulates processor power through runtime performance monitoring. At the heart of this architecture lies the concept of the **heartbeat signal**, a lightweight, periodic event generated by the HPC application. Each heartbeat represents the completion of a meaningful computational unit, such as a loop iteration or simulation step. These heartbeats are collected by the **Node Resource Manager (NRM)**, which functions as a middleware layer interfacing between the operating system, application, and control infrastructure (illustrated in Figure 1.4). The purpose of the heartbeat is to allow the system to monitor how quickly the application is making progress during execution. To extract a reliable performance indicator from this raw data, the NRM includes a **progress sensor**. This sensor computes the application's execution rate by measuring the intervals between consecutive heartbeats. However, to avoid reacting to transient fluctuations caused by I/O delays or system noise, the progress signal is smoothed using a median-based estimator. The smoothed progress $y(t_i)$ at time $t_i$ is defined as:

$$y(t_i) = \text{median} \left( \left\{ \frac{1}{t_k - t_{k-1}} \mid t_k \in [t_{i-1}, t_i] \right\} \right) \quad (1.1)$$

To balance performance and energy, a **performance degradation tolerance** is defined by the user. This value reflects the maximum allowable slowdown relative to the uncapped execution. A **transducer** module converts this degradation tolerance into a reference progress signal. For example, a 10% degradation limit would correspond to a progress reference set at 90% of the nominal execution rate. The **controller** receives both the measured progress and the reference and computes the error between them. Based on this error, it generates a control signal representing a new power cap, which is applied
to the processor using the **RAPL (Running Average Power Limit)** interface. RAPL enforces the specified power cap by limiting the average power consumed over a fixed time window, effectively throttling the processor's energy use. Once the new cap is applied, the HPC application adapts to the available power, and its performance evolves accordingly. The resulting heartbeat rate is fed back into the control loop, allowing the system to continuously monitor and adjust power in response to changes in workload behavior. This feedback structure enables real-time control of energy consumption, ensuring that performance remains within defined bounds while optimizing power usage across diverse execution phases.

<figure><img src="image_9.png" /><figcaption>**Figure 1.4:** Control structure and NRM interaction [6]</figcaption></figure>
# Chapter 2

## System Design and Modeling

### 2.1 Phase Detection Indicators

Dynamic power control in HPC systems relies on knowing which type of workload is currently running. This requires classifying the application's execution phase in real time. Previous research [7] has demonstrated that combinations of hardware counters can reliably indicate execution phases. For example, high cache miss rates are commonly associated with memory-bound workloads. Elevated instruction and branch activity may suggest mixed or hybrid phases. Meanwhile, low I/O sensor activity often corresponds to CPU-focused execution or compute-bound, whereas sudden bursts in I/O indicate disk or communication-heavy behavior.

These indicators are often preprocessed using dimensionality reduction techniques such as Principal Component Analysis (PCA), and categorized via thresholds or decision tree logic. When the values stabilize over time, it is assumed that a new phase has started, allowing the control strategy to switch modes accordingly. In this work, we do not implement a full phase detection. Instead, we assume access to a scheduling parameter $\beta \in [0, 1]$ that represents the current workload phase (where $\beta = 0$ corresponds to memory-intensive phases, $\beta = 1$ to compute-intensive). This parameter can be derived from hardware counters or inferred externally. It serves as an input to both the modeling and control stages.

### 2.2 System Modeling

The scheduling parameter enables the formulation of a *Linear Parameter-Varying (LPV)* model, where system dynamics evolve with $\beta$. The goal is to identify a model $S(\beta)$ that describes how the progress rate of the system output responds to both the characteristics of the workload and the control actions under varying power caps.

Ideally, this modeling process would involve running benchmarks with controlled arithmetic intensity profiles and injecting a range of power cap values. Arithmetic intensity refers to the ratio of computational operations (typically floating-point operations) to
<figure><img src="image_10.png" /><figcaption>**Figure 2.1:** LPV system identification methodology</figcaption></figure>

memory accesses during a program’s execution [3]. By varying this ratio, one can simulate different workload phases and observe how the system responds under power constraints.

The resulting progress and power data could then be used to identify models that vary smoothly with the scheduling parameter, forming the basis for a unified LPV (Linear Parameter-Varying) control strategy. However, due to practical limitations such as the lack of programmable mixed-phase benchmarks and restricted access to hardware, we adopt a simplified modeling strategy. In this approach, compute and memory phases are treated as two separate systems, control strategies are then interpolated based on the estimated workload phase. In future work, as more experimental data becomes available, we plan to revisit full LPV system identification and construct a globally valid model.

### 2.2.1 Memory System

For memory-bound workloads, experiments were conducted using the STREAM benchmark. By applying different levels of power caps (Pcap [W]) and recording the resulting progress ([Hz]), a nonlinear relationship between power and performance was identified, as detailed in [6, 12]. The resulting model is:

$$ \text{Progress} = K_L \left(1 - e^{-\alpha(a \cdot \text{pcap} + b - \beta)}\right) \qquad (2.1) $$

<table><caption>**Table 2.1:** Model Parameters and Variables</caption><thead><tr><th>Symbol</th><th>Description</th><th>Dahu Value</th></tr></thead><tbody><tr><td>K<sub>L</sub></td><td>Max. achievable progress (saturation)</td><td>42.4 Hz</td></tr><tr><td>α</td><td>Exponential decay rate parameter</td><td>0.032 W<sup>-1</sup></td></tr><tr><td>a</td><td>RAPL actuator slope coefficient</td><td>0.94</td></tr><tr><td>b</td><td>RAPL actuator offset</td><td>0.17 W</td></tr><tr><td>β</td><td>Workload-specific offset parameter</td><td>34.8 W</td></tr></tbody></table>
To enable control design, the nonlinear memory model was linearized in a high power operating range (pcap > 70 W), where system performance is most critical. Two power sensors (pkg-0 and pkg-1) were used to capture input/output models as shown in Figure 2.2 (all the data used are for Dahu cluster). The resulting linearized memory system is modeled by the following first-order transfer function:

$$G_m(s) = \frac{0.6269s + 0.01798}{s + 0.05317} \qquad (2.2)$$

<figure><img src="image_11.png" /><figcaption>Figure 2.2: Nonlinear vs Linear model for memory</figcaption></figure>

### 2.2.2 Compute System

In the case of compute-intensive applications, the Embarrassingly Parallel (EP) benchmark is used. The relationship between power and progress exhibits a more linear behavior as described in [11]. The outer loop models the impact of measured power on progress as a discrete-time transfer function of the form:

$$G_c(s) = \frac{0.2361s + 0.4722}{s + 1.783} \qquad (2.3)$$
# Chapter 3

## Control Strategy

### 3.1 Gain Scheduling PI

The control objective is to track a target application progress while minimizing power consumption across varying workload characteristics. The proposed controller design employs a gain scheduling approach based on linearized plant models for each workload type. The foundation of this approach rests on the classical Proportional-Integral (PI) control law:

$$U(t) = K_P \cdot e(t) + K_I \int_{0}^{t} e(\tau) d\tau \qquad (3.1)$$

where:

* $e(t) = r(t) - y(t)$ represents the tracking error

* $r(t)$ is the target application progress setpoint

* $y(t)$ is the measured application progress

* $u(t)$ is the control input (power cap) applied to the system

* $K_P$ and $K_I$ are the proportional and integral gains, respectively

Each PI controller is individually designed to meet performance requirements that ensure both responsiveness and stability. These specifications ensure rapid response to setpoint changes while maintaining system stability and avoiding excessive power fluctuations that could destabilize the computing platform.

<table><caption>**Table 3.1:** PI Controller Performance Specifications</caption><thead><tr><td>Performance Metric</td><td>Specification</td></tr></thead><tbody><tr><td>Rise time</td><td>≤ 1.5 seconds</td></tr><tr><td>Settling time</td><td>≤ 3.0 seconds</td></tr><tr><td>Maximum overshoot</td><td>≤ 10%</td></tr></tbody></table>

The tuned PI controller gains for each workload type are presented in Table 3.2:
<table><caption>**Table 3.2: PI Controller Parameters**</caption><thead><tr><td>Workload Type</td><td>K<sub>p</sub></td><td>K<sub>i</sub></td></tr></thead><tbody><tr><td>Memory-Bound</td><td>0.0213</td><td>0.0397</td></tr><tr><td>Compute-Bound</td><td>4.3161</td><td>8.1339</td></tr></tbody></table>

The gain scheduling mechanism employs linear interpolation based on a workload characterization parameter $\beta \in [0, 1]$, where $\beta = 0$ corresponds to purely memory-bound workloads and $\beta = 1$ represents purely compute-bound workloads.

<figure><img src="image_12.png" /><figcaption>**Figure 3.1: $\beta$-based interpolation of controller and system.**</figcaption></figure>

The scheduled controller gains and the measured output is interpolated to account for the mixed workload characteristics:

$$K_P(\beta) = (1 - \beta)K_{P,mem} + \beta K_{P,comp} \qquad (3.2)$$

$$K_I(\beta) = (1 - \beta)K_{I,mem} + \beta K_{I,comp} \qquad (3.3)$$

$$Y(\beta) = (1 - \beta)Y_{mem} + \beta Y_{comp} \qquad (3.4)$$
3.1.1 Gain Scheduling PI Controller Results

The gain scheduling PI controller was implemented and evaluated under experimental conditions with different reference levels, as described in previous work [6, 11], in correspondence with the Dahu cluster environment. Figure 3.2 presents the overall system performance, demonstrating the controller's ability to track the reference progress signal while adapting to varying workloads and progress levels. The tracking performance exhibits acceptable accuracy as shown in Figure 3.3. Despite these positive characteristics, the main fundamental limitation is the occurrence of abrupt gain changes when the workload parameter $\beta$ experiences rapid transitions, as clearly visible in the experimental data where sudden jumps between memory-bound and compute-bound operating modes trigger corresponding discontinuities in controller behavior, creating periods where stability guarantees are compromised and system performance becomes unpredictable.

<figure><img src="image_13.png" /><figcaption>Figure 3.2: Gain scheduling PI controller performance analysis.</figcaption></figure>

<figure><img src="image_14.png" /><figcaption>Figure 3.3: Tracking error analysis for the gain scheduling PI controller</figcaption></figure>
Under more aggressive system behavior with frequent $\beta$ changes and less smooth transitions, the tracking accuracy decreases significantly and the error spikes become substantially higher, as shown in Figure 3.4.

<figure><img src="image_15.png" /><figcaption>Figure 3.4: controller performance under aggressive workload variations.</figcaption></figure>

These findings motivate the investigation of more advanced control methodologies that could potentially address the identified limitations while maintaining the beneficial characteristics.

## 3.2 Linear Parameter Varying (LPV) Control Design

Linear Parameter Varying (LPV) control offers a framework to control systems whose dynamics change with time-varying, measurable parameters. The polytopic LPV approach models the system as a convex combination of Linear Time-Invariant (LTI) systems (vertex systems), enabling robust control design using linear tools.

Let the system depend on a scheduling parameter $\beta(t) \in [\underline{\beta}, \bar{\beta}]$. The state-space matrices are written as:

$$S(\beta) = \sum_{i=1}^{N} \alpha_i(\beta)V_i \qquad (3.5)$$

where $\alpha_i(\beta) \ge 0$ and $\sum \alpha_i(\beta) = 1$. These are convex weights expressing the influence of each vertex model ($V_i$). The LPV system is described by:
$$ \dot{x}(t) = A(\beta(t)) x(t) + B(\beta(t)) u(t) \qquad (3.6) $$

$$ y(t) = C(\beta(t)) x(t) + D(\beta(t)) u(t) \qquad (3.7) $$

$$ \begin{pmatrix} A(\beta) & B(\beta) \\ C(\beta) & D(\beta) \end{pmatrix} = \sum_{i=1}^{N} \alpha_i(\beta) \begin{pmatrix} A_i & B_i \\ C_i & D_i \end{pmatrix}, \quad \alpha_i(\beta) \ge 0, \quad \sum_{i=1}^{N} \alpha_i(\beta) = 1 \qquad (3.8) $$

The goal is to design a parameter-dependent controller that ensures robust stability and prescribed $H_\infty$ performance. We consider the generalized plant at each vertex:

$$ \dot{x} = A_i x + B_{1,i} w + B_{2,i} u \qquad (3.9) $$

$$ z = C_{1,i}x + D_{11,i}w + D_{12,i}u \qquad (3.10) $$

$$ y = C_{2,i}x + D_{21,i}w + D_{22,i}u \qquad (3.11) $$

We then seek symmetric matrices $X > 0, Y > 0$, and controller matrices ($A_c^i, B_c^i, C_c^i, D_c^i$) such that the following LMI condition holds for each $i = 1, \dots, N$ as in [5]

## LMI Condition

$$ \begin{bmatrix} A_i X + X A_i^\top + B_{2,i} C_c^i + C_c^{i\top} B_{2,i}^\top & A_c^i + A_i^\top + C_{2,i}^\top D_c^{i\top} B_{2,i}^\top & B_{1,i} + B_{2,i} D_c^i D_{21,i} & C_{1,i} X + D_{12,i} C_c^i \\ * & Y A_i + A_i^\top Y + B_c^i C_{2,i} + C_{2,i}^\top B_c^{i\top} & Y B_{1,i} + B_c^i D_{21,i} & C_{1,i} + D_{12,i} D_c^i C_{2,i} \\ * & * & -\gamma I & D_{11,i} + D_{12,i} D_c^i D_{21,i} \\ * & * & * & -\gamma I \end{bmatrix} < 0 \qquad (3.12) $$

These LMIs are convex and can be solved using semidefinite programming solvers (SeDuMi, SDPT3). Once the vertex controllers $K_i = \begin{bmatrix} A_c^i & B_c^i \\ C_c^i & D_c^i \end{bmatrix}$ are computed, the global controller is recovered by interpolation:

$$ K(\beta) = \sum_{i=1}^{N} \alpha_i(\beta) K_i \qquad (3.13) $$

This ensures continuity and robustness across the full operating range $\beta \in [\underline{\beta}, \bar{\beta}]$.
## 3.3 LPV $H_\infty$ for HPC Workload Regulation

In the context of power management in high-performance computing (HPC), the system exhibits different dynamics depending on the workload characteristics. here we consider two dominant regimes : memory-bound and compute-bound phases, these are represented by two vertex models derived from system identification. To unify the input-output structure and enable LPV controller synthesis, both models are augmented with fast pre and post compensator filters. Additionally, performance specifications are introduced via weighting functions: $W_e(s)$ emphasizes accurate progress tracking by penalizing low-frequency errors, while $W_u(s)$ limits excessive variations in power cap commands. These components are integrated into a generalized plant used for $H_\infty$ synthesis.

At each vertex, an $H_\infty$ controller is designed ensuring that the closed-loop system remains robust to disturbances and model variations. The design objective is to minimize the worst-case gain from exogenous disturbances to a set of weighted outputs, as illustrated in Figure 3.5. The synthesis condition is given as follow:

$$ \sup_{\|w\|_2 \neq 0} \frac{\|z\|_2}{\|w\|_2} < \gamma, \quad \forall \beta \in [0, 1] \qquad (3.14) $$

where $z$ denotes the weighted performance outputs and $w$ the external inputs.

Once controllers are synthesized for each vertex system, the final LPV controller is constructed through convex interpolation based on the current value of the scheduling parameter, this interpolation guarantees continuous adaptation of control actions in response to the varying workload while maintaining robust performance over the entire parameter range.

<figure><img src="image_16.png" /><figcaption>Figure 3.5: Generalized $H_\infty$ control structure</figcaption></figure>
The effectiveness of the proposed LPV controller is validated through simulation results. As shown in Figure 3.6, the controller successfully tracks the desired progress reference while adapting to workload shifts represented by variations in $\beta$. The smooth transition between memory- and compute-bound regimes confirms the effectiveness of the polytopic LPV formulation.

<figure><img src="image_17.png" /><figcaption>Figure 3.6: LPV Controller Performance</figcaption></figure>

<figure><img src="image_18.png" /><figcaption>Figure 3.7: Tracking Error Analysis.</figcaption></figure>

To quantify tracking performance, Figure 3.7 provides a detailed error analysis. the left plot illustrates the evolution of tracking error over time which indicate that the error remains well controlled even under aggressive transitions in reference progress and highly dynamic changes in workload type as in Figures 3.8 and 3.9
<figure><img src="image_19.png" /><figcaption>**Figure 3.8:** LPV Controller Performance under aggressive dynamics</figcaption></figure>

<figure><img src="image_20.png" /><figcaption>**Figure 3.9:** Tracking Error Analysis under aggressive conditions.</figcaption></figure>

In terms of tracking results, the LPV $H_\infty$ controller performs reliably under both smooth and aggressive workload variations, to further validate the quality of the controller, we also analyzed its frequency-domain behavior using sensitivity functions. The plots of the sensitivity $S$ and complementary sensitivity $KS$ functions (Figure 3.10) show that the controller responses stay well within the designed template. Specifically, $S$ remains below the inverse of the weighting function $1/W_e$, indicating good disturbance rejection in the low-frequency range. Similarly, $KS$ remains below $1/W_u$, showing that the control effort is bounded and does not overreact at high frequencies. These results confirm that the $H_\infty$ performance level
<figure><img src="image_21.png" /><figcaption>Figure 3.10: Sensitivity function for the LPV $H_\infty$ controller.</figcaption></figure>

## 3.4 Comparison Between PI and LPV $H_\infty$ Controllers

To evaluate the relative performance of the proposed LPV $H_\infty$ controller against the baseline gain-scheduled PI controller, we analyze tracking accuracy using Fit percentage and Root Mean Square Error (RMSE) metrics under both simple and aggressive workload scenarios. Table 3.3 summarizes the quantitative performance comparison.

<table><caption>Table 3.3: Performance comparison of PI and LPV $H_\infty$ controllers</caption><thead><tr><th>Metric</th><th>PI</th><th>LPV H<sub>∞</sub></th><th>Improv.</th></tr></thead><tbody><tr><td colspan="4">Simple Workload</td></tr><tr><td>Fit (%)</td><td>93.84</td><td>95.71</td><td>+1.87%</td></tr><tr><td>RMSE</td><td>0.0475</td><td>0.0368</td><td>-22.5%</td></tr><tr><td colspan="4">Aggressive Workload</td></tr><tr><td>Fit (%)</td><td>89.98</td><td>94.02</td><td>+4.04%</td></tr><tr><td>RMSE</td><td>0.0532</td><td>0.0387</td><td>-27.2%</td></tr><tr><td colspan="4">Degradation Analysis</td></tr><tr><td>Fit Deg.</td><td>3.86%</td><td>1.69%</td><td>-56%</td></tr><tr><td>RMSE Inc.</td><td>12.0%</td><td>5.2%</td><td>-57%</td></tr></tbody></table>

The results demonstrate that while both controllers perform adequately under simple conditions, the LPV controller maintains significantly better performance consistency during aggressive workload variations, with substantially lower tracking error and superior robustness to dynamic operating conditions.
# Chapter 4

## Conclusion

This internship focused on the design and evaluation of power capping control strategies for High Performance Computing (HPC) systems operating under dynamic workload conditions. Given the growing energy demands and workload variability in modern data centers, the objective was to ensure effective power regulation while maintaining system progress and performance.

To address this challenge, two main control approaches were developed and tested. First, a gain-scheduled PI controller was implemented to switch between control gains for memory-intensive and compute-intensive modes based on a workload scheduling signal. This strategy offered a simple yet effective solution under moderate workload changes. However, its limitations became apparent under aggressive or rapidly shifting workloads, where performance degradation, overshoot, and instability were observed. To overcome these issues, a robust LPV $H_\infty$ controller was designed using a polytopic approach, this formulation enabled smooth interpolation between operating modes and explicitly accounted for disturbances and model uncertainty, the controller synthesis was based on Linear Matrix Inequalities (LMIs) and incorporated performance weighting functions to balance disturbance rejection and control effort.

Simulation results demonstrated that the LPV controller consistently outperformed the gain-scheduled PI controller. Under aggressive workloads, it achieved higher tracking accuracy, better robustness to disturbances, and smoother control actions.

In conclusion, the LPV $H_\infty$ framework proved to be a powerful method for managing power consumption in HPC systems with variable workloads. It enables predictive, scalable, and reliable control across different system behaviors.
Future Work

Future work will focus on several key extensions to this study. First, experimental validation on a real HPC cluster is essential to confirm the simulation results and assess the controller's performance under real-world disturbances, measurement noise, and actuator constraints. A second direction involves improving the system identification process by designing and utilizing dedicated benchmarks, this would enable more accurate LPV model extraction and reduce reliance on simplified assumptions. Another promising direction is the integration of learning-based components into the LPV control architecture, for instance, data driven adaptation or reinforcement learning could be combined with the current LPV structure to enhance performance under previously unseen workload patterns to help address nonlinearities leading to more accurate predictions and better control allocation. These enhancements would contribute to building a more intelligent, adaptable, and robust power capping solution for HPC systems.
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