# DC-DC converter with low components voltage stress and reduced conduction losses by branches parallel connection

Robert Stala, Filip Orlowski

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Robert Stala, Filip Orlowski. DC-DC converter with low components voltage stress and reduced conduction losses by branches parallel connection. The 26th European Conference on Power Electronics and Applications, GDR SEEDS France & EPE Association, Mar 2025, Paris, France. 10.34746/epe2025-0148 . hal-05105984

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# DC-DC converter with low components voltage stress and reduced conduction losses by branches parallel connection

Robert Stala, Filip Orłowski

AGH UNIVERSITY OF KRAKOW

al. A. Mickiewicza 30

Krakow, Poland

Tel.: +48 / (12) – 617 5712.

E-mail: stala@agh.edu.pl, filiporlo@agh.edu.pl

URL: https://www.agh.edu.pl

## Acknowledgements

Research project supported by program „Excellence initiative – research university” for the AGH University of Krakow.

## Keywords

«Bi-directional converters», «DC-DC converter», «Buck converter», «Boost», «Photovoltaics».

## Abstract

This paper presents modular DC-DC bi-directional converter, which is characterized by reduced voltage and current stress of components as well as increased frequency of current ripple. The converter is dedicated to work with a high voltage step-down ratio, because the output current is divided among many switches, reducing their resistive losses. In addition, the synchronous branches of the system conduct the in parallel connection. The converter can be implemented from discrete components or half-bridge modules, which can simplify its design. Concept of the converter, its modular design, basic waveforms and efficiency results are demonstrated. Basic experimental results are presented as well. The advantages resulting from the multi-division input voltage and the parallel operation of transistors branches are discussed.

## Introduction

DC-DC converters are widely used in DC power supply systems such as data centers [1], battery-powered vehicles [2], fuel-cell vehicles [3], electric vehicle power supply systems or photovoltaic systems.

The DC-DC converter presented in this article is demonstrated as the 48 V to 5 V step-down circuit for application as an intermediate bus converter. It is a synchronous switched-mode converter, so

it can also work as a boost circuit and can be designed for different voltage ranges. The proposed DC-DC converter has ability for continuous output voltage regulation. It operates at reduced voltage stress of transistors and choke compared to a classic buck or boost converter. Furthermore, at high step-down operation the converter requires a higher duty cycle than a classic buck converter, so it assures more even load of transistors.

DC-DC converters with a high degree of step-down are often used in power supply systems for telecommunications equipment. An example is the case of supplying microprocessor systems with a voltage of e.g. 1 V from 48 V distribution network. Power supply systems with 48 V to point-of-load can be implemented using a single-stage converter [4]. Another concept is to combine an Intermediate Bus Converter (IBC) and a Point-of-Load (PoL) system. Converters of this type with a high degree of voltage step-down are presented in [5]–[8]. The converters presented in [6] and [7] use the technique of resonant circuits with switched capacitors and the converter in [8] is a switch-mode circuit with the DC-link composed of three capacitors and bidirectional switches in a topology.

The converter proposed in this article can be configured with discrete components or four basic power electronic half-bridge modules.

On the higher voltage side, the circuit uses a triple capacitor divider, which initially reduces the voltage conversion level. This proposed converter can also be configured to operate with multiple voltage division on the DC-link on the higher voltage side. Lower voltage stress across the components is then obtained, but also less total resistance of the synchronous transistors, which operates in paralleled branches.

A novelty in the concept presented in this article is the converter topology with low voltage stress and parallel operation of synchronous branches.
From the technical viewpoint it is important that the proposed converter can be designed for basic power electronic half-bridge modules use. Owing to the rapidly growing number of power electronic converters, the aspects of reducing this type of e-waste through a design approach assuming the possibility of reuse of power electronics are becoming important [9]. The modular design of the proposed converter based on half-bridge units allows to achieve optimization of the system to reduce the amount of e-waste and facilitate its repair.

## Principle of operation of the proposed converter

The proposed DC-DC converter is presented in Fig. 1. The converter operates based on the following basic assumptions:

- voltage stress across transistors is less than the input voltage because the voltages from the input divider are used for modulation (e.g. of (1/3)Uin as in Fig. 1). This reduces Eoss switching losses of transistors and allow to reduce their Rds(on),

- the choke voltage is significantly reduced in relation to the value of the total input voltage,

- current stress of transistors is reduced by current sharing between multiple transistors. This reduces the conduction losses of I²Rds(on),

- bi-directional conversion is possible as in the case of typical DC-DC synchronous circuits.

<figure><img src="image_2.png" /><figcaption>Fig. 1: The proposed DC-DC high voltage step-down converter</figcaption></figure>

## Redundant states for the output voltage modulation and parallel operation of branches

The proposed modular half-bridge converter can generate a positive output voltage in three redundant states (Fig. 2). In each of the three

states, when, a different input divider capacitor is used.

In the case, when the modulated output voltage is zero uout=0V, two branches of synchronous transistors can conduct inductor current in parallel (Fig. 3). It allows to reduce conduction losses. This is an important advantage of the high step-down system (e.g. 48 V to 5 V), where synchronous transistors (S2, S4, S5 and S7) conduct for a longer time interval during the switching period.

<figure><img src="image_3.png" /><figcaption>State_2: uout = uC2 = uin/3:</figcaption></figure>

<figure><img src="image_4.png" /><figcaption>State 3: uout = uC3 = uin/3:</figcaption></figure>

<figure><img src="image_5.png" /><figcaption>Fig. 2: Redundant states of the step-down converter with positive choke voltage</figcaption></figure>
<figure><img src="image_6.png" /><figcaption>Fig. 3: Parallel operation of branches in the proposed converter during State_0: $u_{out}=0$</figcaption></figure>

## Modulation and control

The modulation in the converter is performed using the appropriate sequence of states presented in Fig. 2:

$$PWM\_states\_sequence = \{State\_1, State\_0, State\_2, State\_0, State\_3, State\_0, ...\} \quad (1).$$

Practical implementation of the modulation can be based on the carrier-based strategy or the state machine algorithm, where transitions between individual states take place in the order (1) with the modulation frequency.

The regulation of the load voltage value is a function of the duty cycle:

$$U_{load}=U_{in}D \quad (2).$$

The implementation time of individual states in (1) is proportional to the duty cycle. The control system can use one of the typical structures for a buck or boost converter integrated with a module that implements the algorithm for controlling the voltage balance on the divider capacitors. The balancing circuit algorithm corrects the duty cycle in one of the active states (Fig. 2) to change the load of a capacitor with the incorrect voltage. The concept of the control system is presented in Fig. 4.

<figure><img src="image_7.png" /><figcaption>Fig. 4: Closed loop regulation with a state machine-based PWM module and circuit for equalizing voltages of divider capacitors.</figcaption></figure>

<figure><img src="image_8.png" /><figcaption>Fig. 5: Logic control signals for the system presented in Fig. 1</figcaption></figure>

<figure><img src="image_9.png" /><figcaption>Fig. 6: Steady-state waveforms: choke current ($i_L$), output voltages of the switch-mode part ($u_{out}$) and voltage of load ($u_{Load}$) at $U_{in}=48V$</figcaption></figure>

## Results demonstrating the operation of the converter and its efficiency

The tests of the proposed converter include its operation and efficiency in the case of operation as a 48 V to 5 V buck converter in the power range up to 350W. The basic parameters of the system are given in Table 1. Fig. 5 shows logic control signals of transistors and Fig. 6 the waveforms that confirm the correct operation of the system. The voltage at the output of the system (in front of the output filter) consists of pulses with a value of $U_{in}/3$ and a duty factor providing $U_{loadavg}=5V$.
## Voltage stress across components

Theoretical voltage stress of transistors can be obtained from Fig. 2:

* State_1: $u_{S4}=u_{in}/3$, $u_{S5}=u_{S7}=u_{in}/6$, $u_{S6}=2u_{in}/3-u_{in}/6=u_{in}/2$, $u_{S8}=2u_{in}/3$;

* State_2: $u_{S2}=u_{S3}=u_{S5}=u_{S8}=u_{in}/3$;

* State_3: $u_{S1}=2u_{in}/3-u_{in}/6=u_{in}/2$, $u_{S2}=u_{S4}=u_{in}/6$, $u_{S3}=2u_{in}/3$, $u_{S7}=u_{in}/3$;

* State_0: $u_{S3}=u_{S8}=u_{in}/2$; $u_{S1}=u_{S6}=u_{in}/2-u_{in}/3=u_{in}/6$;

All transistors have a voltage stress $U_{ds\_max}$ much lower than the value of the input voltage. In case of four transistors, it is $u_{in}/3$, two transistors have voltage stress about $u_{in}/2$ and two $2u_{in}/3$. The maximum values of voltage stress on the elements are listed in Table II.

<table><caption>**Table I: Parameters of the simulation models**</caption><thead><tr><td>Parameter</td><td>Value</td></tr></thead><tbody><tr><td>Maximum output power P<sub>out</sub></td><td>350 W</td></tr><tr><td>Input voltage U<sub>in</sub></td><td>48 V</td></tr><tr><td>Output voltage U<sub>out</sub></td><td>5 V</td></tr><tr><td>Switching frequency</td><td>200 kHz of current ripple in simulations, 600 kHz in experiment</td></tr><tr><td>Simulation method</td><td>Matlab/Simulink with Simscape library (waveforms results) PLECS (efficiency and power losses results)</td></tr><tr><td>Transistor models</td><td>GaN EPC 2302 - manufacturer model for efficiency analysis in PLECS, MOSFET model for waveforms analysis in MATLAB</td></tr></tbody></table>

<table><caption>**Table II: Maximum voltage stress of converter transistors**</caption><tr><td>Switch</td><td>S<sub>3</sub>, S<sub>8</sub></td><td>S<sub>1</sub>, S<sub>6</sub></td><td>S<sub>2</sub>, S<sub>4</sub>, S<sub>5</sub>, S<sub>7</sub></td></tr><tr><td>U<sub>ds\_max</sub> per U<sub>in</sub></td><td>2/3</td><td>1/2</td><td>1/3</td></tr></table>

Figs. 7-9 shows the voltages across the transistors in the form of waveforms. The value of the $U_{ds}$ voltage changes over time, but their maximum values are consistent with the data in Table II. The current load of the transistors in the converter is shown in Figs. 10-11. From these waveforms, it is seen some differences in transistor load. Through the switches S3 and S8 flows current with impulses at the level of the choke current with the frequency $f_s/4$. This is also the case with the S1 and S6 transistors use, but with twice the frequency.

<figure><img src="image_10.png" /><figcaption>**Fig. 7: The drain-source voltage of transistors S2, S4, S5 and S7. Matlab/Simulink results**</figcaption></figure>

<figure><img src="image_11.png" /><figcaption>**Fig. 8: The drain-source voltage of transistors S1 and S6. Matlab/Simulink results**</figcaption></figure>
<figure><img src="image_12.png" /><figcaption>Fig. 9: The drain-source voltage of transistors S3 and S8. Matlab/Simulink results</figcaption></figure>

The waveforms presented in Fig. 11 show that the current of the synchronous transistors S2, S4, S5 and S7 in the State_0 state (Fig. 3) is equal to $i_L/2$, which is advantageous due to the possibility of reducing conduction losses.

<figure><img src="image_13.png" /><figcaption>Fig. 10: Current of the main transistors (S1, S3, S6 and S8. Matlab/Simulink results</figcaption></figure>

Table 2 lists the rms values of the transistor current in the converter. They show an even load on the transistors (six switches conduct current at a level of about $0.5I_{Lrms}$, and two $0.33I_{Lrms}$).

<table><caption>Table II: Rms value of converter transistors</caption><thead><tr><th>Component</th><th>S<sub>3</sub>, S<sub>8</sub></th><th>S<sub>1</sub>, S<sub>6</sub></th><th>S<sub>2</sub>, S<sub>4</sub>, S<sub>5</sub>, S<sub>7</sub></th><th>L</th></tr></thead><tbody><tr><td>I<sub>rms</sub> per I<sub>Lrms</sub></td><td>0.35</td><td>0.5</td><td>0.53</td><td>1</td></tr></tbody></table>

<figure><img src="image_14.png" /><figcaption>Fig. 11: Current of the synchronous transistors (S2, S4, S5 and S7). Matlab/Simulink results</figcaption></figure>

## Zero voltage switching of synchronous transistors in the step-down converter

In the proposed converters, it is advantageous that the synchronous transistors are switched on in ZVS mode at the beginning of the State_0 state. During the dead-time, when all transistors in the converter are turned off, the choke current flows through transistors S2, S4, S5 and S7 in reverse direction. They are switched on after the drain-source voltage drops to the level of the reverse voltage. Fig. 12 shows the waveforms for the S5 switch modelled as a MOSFET with body diode. In the initial phase of commutation, the current of the reverse diode ($i_d$) rises, and at the same time the $v_{ds}$ voltage of the switch drops to -1.5V. Approximately, a constant diode current causes a pulse of power loss in the diode (MOSFET5\_diode\_d\_power dissipated signal). When the MOSFET is switched on, the current commutates from the diode to the transistor ($i_{ds}$) and a small pulse of power loss in the transistor (MOSFET5\_MOS\_power\_dissipated) is seen. The energy dissipated during switching in synchronous transistors is much lower than in transistors that operate in the hard switching mode (S1, S3, S6, S8), which can be seen from the example waveforms for the S3 transistor presented in Fig. 13.
<figure><img src="image_15.png" /><figcaption>Fig. 12: ZVS turn on of the synchronous transistor S5. Matlab/Simulink results based on MOSFET model with body diode</figcaption></figure>

<figure><img src="image_16.png" /><figcaption>Fig. 13: Turn on process of the S3 main transistor in the converter. Matlab/Simulink results based on MOSFET model</figcaption></figure>

## Switching losses

A single main transistor operates at a lower frequency and voltage than a transistor in the classic buck converter. However switching between a high state (State_(1-3) as in Fig. 1) and State_0 requires switching two main transistors (S1, S3, S6, S8) and two or three synchronous transistors (S3, S4, S5, S7). Therefore, it would be beneficial to mitigate reverse recovery losses by implementing such a system based on GaN transistors.

The characteristics of switches in terms of switching losses are presented in Table III.

<table><caption>Table III: Operating states change and switched transistors</caption><thead><tr><th>State change</th><th>Main transistors<br>switched and its U<sub>ds</sub><br>voltage</th><th>Synchronous<br>transistors<br>switched</th></tr></thead><tbody><tr><td>State1 –<br>State0</td><td>S<sub>3</sub><br>(2/3)U<sub>in</sub></td><td>S<sub>1</sub><br>(1/2)U<sub>in</sub></td><td>S<sub>4</sub>, S<sub>5</sub>, S<sub>7</sub></td></tr><tr><td>State2 –<br>State0</td><td>S<sub>1</sub><br>(1/2)U<sub>in</sub></td><td>S<sub>6</sub><br>(1/2)U<sub>in</sub></td><td>S<sub>2</sub>, S<sub>5</sub></td></tr><tr><td>State3 –<br>State0</td><td>S<sub>6</sub><br>(1/2)U<sub>in</sub></td><td>S<sub>8</sub><br>(2/3)U<sub>in</sub></td><td>S<sub>2</sub>, S<sub>4</sub>, S<sub>7</sub></td></tr></tbody></table>

Main transistors switching frequency is the following in the converter:

$$f_{sw\_S1} = f_{sw\_S8} = \frac{1}{3}f_s \quad (3).$$

$$f_{sw\_S3} = f_{sw\_S6} = \frac{2}{3}f_s \quad (4).$$

For GaN-based converter no reverse recovery losses is considered and switching losses are dominated by overlap switching losses of main transistors (S1, S3, S6, S8) approximated by:

$$E_{sw\_S1} = E_{sw\_S6} = \frac{1}{2} \cdot \left( \frac{1}{2} U_{in} \right) I_L \left[ \left( t_{ir} + t_{vf} \right) + \left( t_{if} + t_{vr} \right) \right] \quad (5).$$

$$E_{sw\_S3} = E_{sw\_S8} = \frac{1}{2} \cdot \left( \frac{2}{3} U_{in} \right) I_L \left[ \left( t_{ir} + t_{vf} \right) + \left( t_{if} + t_{vr} \right) \right] \quad (6).$$

Considering the switching frequency of transistors (2), the overlap switching losses are the sum of the losses of 8 transistors:

$$P_{sw} = \sum_{n=1,3,6,8} \{ f_s(n) U_{in}(n) I_L \left[ \left( t_{ir} + t_{vf} \right) + \left( t_{if} + t_{vr} \right) \right] \} = \frac{7}{12} f_s U_{in} I_L \left[ \left( t_{ir} + t_{vf} \right) + \left( t_{if} + t_{vr} \right) \right] \quad (7).$$

Assuming the same values of transistors current and voltage change time, the switching losses with respect to the a classic synchronous buck converter are on similar level.
Taking into account the reduced voltage in relation to $U_{in}$ (Tab. 3) and the reduced switching frequency in relation to $f_s$, the switching losses due to the discharge of the output capacitance (energy related effective output capacitance $C_{oss(er)}$ losses) are lower than in the case of a buck converter: $P_{oss\_tot} = 0.347f_s C_{oss(er)} U_{in}^2$.

## Power efficiency

ZVS and hard switching commutation, as well as possible switching losses, have been demonstrated on MOSFET models with reverse diode (Figs. 12-13). Due to the differences in the mechanism of reverse conduction and internal capacitance variation of the GaN transistor and MOSFET, the efficiency of the converter designed for the GaN technique was demonstrated using simulations based on a dedicated model of the GaN transistor. The efficiency tests were performed using PLECS software and results are shown in Fig. 14.

<figure><img src="image_17.png" /><figcaption>Fig. 14: Efficiency of the DC-DC 48 V to 5 V converter versus output power. Results obtained in PLECS software for GaN-based model</figcaption></figure>

In simulation tests the converter achieved an efficiency of over 98% with an output power of less than 100 Watt, and for the maximum power it is about 97%. The efficiency tests were performed in the model with the parasitic resistances of the circuits included.

A large number of synchronous transistors in the analysed converter does not cause a significant increase in losses, because their current is divided between the parallel branches, and switching on occurs in the ZVS mode.

## Experimental results

In order to confirm the feasibility of the system in the proposed technique, Figs. 15 and 16 present its experimental results of operation. The circuit

is made on the basis of EPC2302 GaN transistors. The frequency of choke's current ripple is $f_{ripple}=600$ kHz. The control signals were generated based on MAX10 FPGA hardware.

<figure><img src="image_18.png" /><figcaption>Fig. 15: Logic signals for the control of the experimental converter system (S1 to S8 from the top).</figcaption></figure>

<figure><img src="image_19.png" /><figcaption>Fig. 16: Experimental results. Steady-state choke current, input and load voltage waveforms. Voltage ratio is 48 to 5 V, input power $P_{in}=100$ W, choke's inductance $L_{out}=2.2$ uH, current's ripple frequency $f_{ripple}=600$ kHz.</figcaption></figure>

## Topology extension towards for high step-down operation

Extension of the topology by increasing the input voltage division is possible and can be beneficial due to the reduction of voltage stress of some components and current load of transistors. An increase in the number of components will be a factor that increases the cost, but it allows for increased system frequency.
<figure><img src="image_20.png" /><figcaption>Fig. 17: The proposed DC-DC topology with increased number of divider capacitors for high step-down operation</figcaption></figure>

<figure><img src="image_21.png" /><figcaption>Fig. 18: Example current flow paths in the extended topology of the proposed DC-DC converter in states when $u_{out}=u_{in}/4$ (a) and $u_{out}=0$ V (b).</figcaption></figure>

Fig. 17 shows a generalized topology with $n > 3$ number of divider capacitors on the high voltage side. An example of the current flow path in the topology with number of divider capacitors

$n = 4$ is shown in Fig. 18. When extending the topology with one voltage divider capacitor, one additional switch attached to the DC-link voltage and two synchronous transistors are required. The additional switches should have the ability to block bidirectionally. Only dividing the input voltage into three, as shown in Fig. 1, the converter requires the use of conventional transistors, such as MOSFET or GaN.

An advantageous feature of expanding the topology by a larger number of input voltage divisions is the decrease in the total resistance of the synchronous parallel conducting branches. In an extended topology, the synchronous branches contain two transistors each, but the number of conductive parallel branches increases when $u_{out}=0$ (Fig. 18b).

## Converter design solutions

The converter can be designed for discrete transistors implementation using the circuit as shown in Fig. 1 or with the use of typical modules in the half-bridges configuration (Fig. 19). The use of half-bridges modules can be beneficial for optimizing the cost of the system, as well as technical parameters.

<figure><img src="image_22.png" /><figcaption>Fig. 19: The modular implementation based on half-bridge modules of the proposed converter</figcaption></figure>

## Conclusion

The novel DC-DC converter topology is presented in the paper. The demonstrated results for the system operating as a 48 V to 5 V step-down converter confirm its following positive features:

* The voltage across the choke is three times lower than in a classic DC-DC
buck converter and reaches the value $U_{in}/3-U_{out}$

* The voltage stress across the transistors is significantly below the input voltage level. This allows the use of transistors with lower voltage and resistance.

* In the analysed case of voltage gain an even load of transistors was obtained (load of six transistors is equal).

* Synchronous branches in the buck converter can be operated in parallel, which reduces conduction losses.

* The main transistors of the converter are turned on at a voltage value lower than the input voltage, which allows to reduce $C_{oss}$ losses.

* Synchronous transistors are turned on in ZVS mode.

* The modelled maximum efficiency of the converter above 98%.

* The converter topology allows for increased input voltage division, which reduces the voltage and current stress of the components and can be beneficial for operation with a high degree of voltage step-down.

* The converter can be designed for the use of four half-bridge modules. Such a modular design allows for fast repair in the event of a failure and easy re-use of half-bridge modules.

## References

[1]. Chen Y., Shi K., Chen M. and Xu D.: Data Center Power Supply Systems: From Grid Edge to Point-of-Load, IEEE Journal of Emerging and Selected Topics in Power Electronics Vol. 11 no 3 pp 2441-2456, 2023

[2]. Chen J., Nguyen M.-K., Yao Z., Wang C., Gao L., Hu G.: DC-DC Converters for transportation electrification: topologies, control, and future challenges, IEEE Electrification Magazine Vol. 9 no 2 pp 10-22, 2021

[3]. Sagar Bhaskar M., Ramachandaramurthy V. K., Padmanaban S., Blaabjerg F., Ionel D. M., Mitolo M., Almakhles D.: Survey of DC-DC Non-Isolated Topologies for Unidirectional Power Flow in Fuel Cell Vehicles, IEEE Access Vol 8 pp 178130-178166, 2020

[4]. Sandri P., Increasing Hyperscale Data Center Efficiency: A Better Way to Manage 54-V/48-V-to-Point-of-Load Direct Conversion, IEEE Power Electron. Mag. Vol 4 no 4 pp. 58-64, 2017

[5]. Reusch D., Biswas S., Zhang Y.: System Optimization of a High Power Density Non-Isolated Intermediate Bus Converter for 48 V Server Applications, IEEE Trans. Ind. Appl. Vol 55 no 2 pp 1619-1627, 2019

[6]. Abramson R. A., Ye Z., Pilawa-Podgurski R. C. N.: A High Performance 48-to-8 V Multi-Resonant Switched-Capacitor Converter for Data Center Applications, EPE'20 ECCE Europe, 2020

[7]. Folmer S., Kosakowski M., Stala R.: 48-V Input DC-DC High Step-Down Converter in GaN-Based Design, IEEE Access Vol 10 pp 115958-115973, 2022

[8]. Stala R., Folmer S.: High step-down DC-DC converter and results for 48-to-5 V and 400-to-48 V implementation, EPE'23 ECCE Europe, 2023

[9]. Huber J., Imperiali L., Menzi D., Musil F., Kolar J. W.: Energy Efficiency is Not Enough!, IEEE Power Electronics Magazine Vol 11 no 1 pp 18-31, 2024