# Enhancing Accuracy of a 2MW Power Converter for High-Current Electromagnets

Jérôme Savary, Xavier Bonnin, Gilles Le Godec

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Jérôme Savary, Xavier Bonnin, Gilles Le Godec. Enhancing Accuracy of a 2MW Power Converter for High-Current Electromagnets. The 26th European Conference on Power Electronics and Applications, GDR SEEDS France & EPE Association, Mar 2025, Paris, France. 10.34746/epe2025-0230. hal-05095754

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# Enhancing Accuracy of a 2MW Power Converter for High-Current Electromagnets

Jérôme Savary, Xavier Bonnin, Gilles Le Godec

CERN,

Esplanade des Particules 1,

1217 Meyrin, Suisse.

+41.22.766.99.08

jerome.savary@cern.ch, xavier.bonnin@cern.ch, gilles.le.godec@cern.ch

https://section-mpc.web.cern.ch/content/general-neptune

*Index Terms*—AC-DC converter, Current-source DC-DC, Interleaved inverters, Multiphase converter, Physics research.

*Abstract*—This paper focuses on designing the so-called NEPTUNE: a high-power (2 MW), high-current (24 kA) multiphase power converter for particle accelerators, with the goal of minimizing load current harmonics using cost-effective components while considering market constraints. In particular, the effects of parasitic resistance and inductance asymmetries, DC-Link perturbations, and associated mitigation strategies are explored. The paper employs analytical studies, simulations, and measurements on a small-scale prototype to validate the proposed solutions.

## I. INTRODUCTION

Septa electromagnets are either used to transfer particle beams between accelerators or to inject and extract them from a ring accelerator to an experimental zone. These warm electromagnets are low inductive and must be fed with a large and accurate current to reach a magnetic field sufficiently strong and stable to deflect the beam adequately. In this context, such an electromagnet requires a flat-top power of about 2 MW, a current that can be higher than 20 kA, with an accuracy of 50 ppm and a high repeatability. Injection and extraction can be fast or slow. In the latter case, it means that the beam makes a large number of revolutions before being completely injected or extracted, which gives rise to several technical challenges regarding the design of the power converter that supplies the septum electromagnet. It must provide high current in cycling mode during long flat-tops – typically 10 seconds – with off times of about 15 seconds, while guaranteeing a flat-top accuracy of 50 ppm and a high repeatability (see Fig. 1).

Design, calibration and implementation techniques of

<figure><img src="image_2.png" /><figcaption>Fig. 1: Illustration of a current cycle.</figcaption></figure>

such accurate high current sensors (DCCT) is out of the scope of this paper and can be found in [1], [2]. The reliability is another key point, since the power converter shall perform tens of millions of power cycles during its lifetime.

Studying the ways to mitigate the harmonics generated by a high-power multiphase buck power converter in the low inductive electromagnet, whether due to grid, to switching, or to structural imbalances, appears as a necessary step to fulfill the accuracy requirements formulated by the physicists. This topology is well established for microprocessors circuits (low voltage, high current) [3], and is more generally well adapted for generating high current since it allows an easy parallelization of several unmatched power legs despite a more complex control and the need of additional components. It has also been used in accelerator applications in TRIUMF for high inductive magnets [4]. Furthermore, this modular topology reduces passive component sizes, distributes the thermal stresses among every parts, and significantly reduces the output current ripple thanks to the interleaving. Balancing the switching legs' DC-currents is either solved through the control, and the literature is abundant about this [5]–[8], or by working
in discontinuous conduction mode (DCM): in [9] a 16-phases interleaved bidirectional dc/dc converter for hybrid vehicle application uses the DCM as a way to get rid of the legs current sensors. Nevertheless, in the multi mega-watts power range, having one current sensor per leg is common practice. Thus very standard regulation techniques, like PI cascade control, state-space feedback controller, or more sophisticated architectures can be efficiently used for this application. In [10], five control strategies including the usual PI controller are compared in the particular case of the current regulation of an interleaved buck converter. But, in spite of well balanced DC currents, geometrical asymmetries (module connections lengths, position of the connection plates, ...) and mismatches in the components values lead to the emergence of subharmonics of $N \cdot f_{sw}$, $N$ and $f_{sw}$ being the number of interleaved legs and the switching frequency. In this particular setup, these asymmetries increase the grid harmonics transferred to the electromagnet. The impacts of mismatches of the phase impedances are studied analytically for the general case of a N-legs multiphase buck converter in [11]. A solution based on controlling accurately the switching moment is studied in [12] to eliminate the ripple in virtually any load in steady-state, and not only for $d = k/N$, $k \in \{1, \dots, N\}$. However, this approach cannot help to solve the issue related to the DC-link grid harmonics, and the control dynamic is no help at all since at this power level, the legs switching frequency is too close from the first multiples of 300 Hz (6 times the grid frequency).

This article highlights the duality between getting a reliable high-power cost effective solution using standard components of the market, and reaching a very high precision load current (50 ppm). Moreover, it provides methods to estimate how the asymmetries are reflected into the load current harmonic content.

For this purpose, Section II studies the design of the NEPTUNE power converter, a 2 MW / 24 kA 16-legs multiphase buck converter, by conducting an analytical study and running simulations to estimate the load current harmonics. In Section III, measurements carried-out on a prototype are presented and compared to the design outcomes.

## II. DESIGN

### A. Description of the NEPTUNE power converter

The NEPTUNE is a 2MW / 24kA / 110V power converter intended for cycling applications. Its architecture consists in 8 identical bricks in parallel (see Fig. 2). Each brick consists in a 50Hz 400V-120V extended-delta coupled transformer (Dy11.5). The merits of this

<figure><img src="image_3.png" /><figcaption>Fig. 2: The NEPTUNE Power Converter Topology.</figcaption></figure>

coupling in rectifier applications are described in [13]. It is followed by a diode rectifier and a DC-link filter. The latest supplies two bucks connected in parallel. Each of the 16 bucks is followed by a high frequency choke. The 16 chokes are all connected to a common output capacitor and to the low inductive load. The component values are given in TABLE I.

<table><caption>TABLE I: NEPTUNE component values.</caption><thead><tr><th>Section</th><th>Component</th><th>Value</th></tr></thead><tbody><tr><td>Input</td><td>Transfo Ext Dy11.5</td><td>400V/120V, 150kVA</td></tr><tr><td rowspan="4">DC-Link</td><td><i>L</i><sub>dc</sub></td><td>60μH</td></tr><tr><td><i>C</i><sub>dc</sub></td><td>250mF</td></tr><tr><td><i>n</i></td><td>2</td></tr><tr><td><i>R</i><sub>dc</sub></td><td>11mΩ</td></tr><tr><td rowspan="2">Powerstack</td><td>Diode rectifier</td><td></td></tr><tr><td>H bridge</td><td></td></tr><tr><td>High frequency chokes</td><td><i>L</i><sub>i</sub></td><td>25μH</td></tr><tr><td rowspan="2">Output filter</td><td><i>C</i><sub>f</sub></td><td>10mF</td></tr><tr><td><i>R</i><sub>f</sub></td><td>50mΩ</td></tr><tr><td rowspan="2">Load</td><td><i>L</i><sub>m</sub></td><td>82μH</td></tr><tr><td><i>R</i><sub>m</sub></td><td>2.6mΩ</td></tr></tbody></table>

### B. Interleaving

The merit of interleaving multiple legs lies in its ability to drastically reduce current ripple as shown in TABLE II. Analytical calculations and circuit simulations revealed that limitation arises from the converter asymmetries. In particular, value dispersion in the high-frequency chokes and parasitic resistance are of concern.

<table><caption>TABLE II: Effects of interleaving.</caption><thead><tr><th>item</th><th>N</th><th>N = 4</th><th>N = 8</th><th>N = 16</th></tr></thead><tbody><tr><td>Δ<i>I</i></td><td><i>D</i> · (1 − <i>D</i>) · <i>V</i><sub>dc</sub> / <i>N</i> · <i>f</i><sub>sw</sub> · <i>L</i></td><td>300 A</td><td>300 A</td><td>300 A</td></tr><tr><td>Δ<i>V</i></td><td>Δ<i>I</i> / (8 · <i>N</i> · <i>f</i><sub>sw</sub> · <i>C</i>)</td><td>469 mV</td><td>117 mV</td><td>29 mV</td></tr><tr><td>Δ<i>I</i><sub>m</sub></td><td>Δ<i>V</i> / (2 · <i>N</i> · <i>f</i><sub>sw</sub> · <i>L</i><sub>m</sub>)</td><td>144 mA</td><td>18 mA</td><td>2.25 mA</td></tr></tbody></table>
1) Maximum tolerable resistance asymmetry: Resistance value deviations unbalances the switching legs duty cycles which in turn creates subharmonics of the apparent output ripple frequency. It appears that limiting the resistance asymmetries to ±5%, which is common, allows to reach the accuracy performances.

2) Maximum tolerable inductance asymmetry: Unlike resistance deviation, inductance asymmetries have significantly more impact on the accuracy. To reach this conclusion, Monte Carlo simulations were conducted on the inductance value. The resulting output voltage harmonics amplitudes are plotted in Fig. 3. The harmonics amplitude are normalized by the expected amplitude at $N \cdot f_{sw}$. These simulations show that no more than a ±2% relative error on the inductance value can be accepted. Indeed, by interleaving 8 legs and designing the output filter for $8 \cdot f_{sw}$, the subharmonic amplitudes can already reach levels equivalent to the amplitude at the apparent frequency.

<figure><img src="image_4.png" /><figcaption>Fig. 3: Subharmonic impacts due to inductance asymmetries on output voltage for N = 8.</figcaption></figure>

For the remainder of the study, the output capacitor is therefore designed for an apparent switching frequency of $8 \cdot f_{sw}$, while considering the interleaving of 16 legs.

3) Impact of choke arrangement: For a given set of chokes, additional simulations using PSIM have shown that permuting the choke order significantly impacts the unwanted subharmonic amplitudes of the output current. Every apparent period $1/(N f_{sw})$ one leg switches from the ON to the OFF state while another transitions from the OFF to the ON state. Although the number of legs involved in the ramping up (or down) phase remains consistent from one apparent period to the next, the equivalent inductance value varies due to their asymmetries leading to different current slopes. This variation results in the generation of subharmonics of $N \cdot f_{sw}$ with

amplitudes increasing as the mismatch among choke values grows. Nevertheless, for a given duty cycle, the sequence of involved chokes in each apparent period can be predicted allowing for an arrangement that equalizes the equivalent inductance value involved during any of the ramp-up and ramp-down phases.

The inductance asymmetries were extracted from a homogeneous distribution $\epsilon_i \sim U(-0.02, 0.02)$, where $L_i = (1+\epsilon_i)L_0$ and $L_0 = 25\mu H$. Several choke arrangements were selected, among which four are represented in Fig. 4. For each choke configuration, the magnet current peak-to-peak ripples were measured at both the switching and apparent frequency.

By placing the chokes in a way to minimize their consecutive inductance differences, the unwanted subharmonic amplitude can be significantly reduced by a factor of 10 (see Fig. 5). The simulations confirmed that for a given set of chokes, there exists an optimum choke arrangement that minimizes the unwanted subharmonic. To conclude, all the converter asymmetries limit its maximum accuracy and inhibit the benefits of interleaving more than 8 legs.

<figure><img src="image_5.png" /><figcaption>Fig. 4: Four choke arrangements.</figcaption></figure>

### C. Rejection of the DC-link noise

A DC-link is formed from the AC grid using an extended delta Dy11.5 or Dy0.5 transformer and a 6-pulse diode rectifier. The anticipated voltage at the rectifier output is given by:

$$v_{rect}(t) = \frac{3\sqrt{2}u_{rms}}{\pi} \left( 1 + \sum_{k=1}^{\infty} \frac{2(-1)^{k+1}}{36k^2 - 1} \cos(12\pi k f_g t) \right), \quad (1)$$

where $f_g$ and $u_{rms}$ stand for the grid frequency and the rectifier input phase-to-phase voltage. Nevertheless, at the buck outputs, the 300 Hz ripple is canceled out:
<figure><img src="image_6.png" /><figcaption>Fig. 5: Magnet current ripple fundamental and apparent harmonics depending on chokes distribution for N = 16.</figcaption></figure>

Indeed, by offsetting two transformer secondary by 30°, their respective DC-Link 300 Hz perturbation are phase-shifted by 180° (6×30°).

However, this 300 Hz elimination is not flawless due to component imperfections, and measurements indicate that while the 300 Hz component is reduced with this technique, it can noticeably impair the output precision performance. This section outlines the connections between component imperfections and their impact on the output current, presenting design guidelines.

1) DC-link filters asymmetries: The DC-link filter consists in a DC-link inductance $L_{dc}$, a DC-link capacitance $C_{dc}$ and a damping branch $R-nC_{dc}$. The normalized transmittance of such a DC-link filter is given by:

$$T_{dcl}(s) = \frac{1 + nS}{(1 + nS)(S^2 + S + \frac{n-1}{n}) + \frac{1}{n}} \quad (2) \\ \approx \frac{1}{S^2 + S + \frac{n-1}{n}} \quad (\text{if } \Omega \gg 1),$$

where $S = j\Omega = j\sqrt{L_{dc}C_{dc}}\omega$ is the normalized Laplace variable. The last expression is more convenient since the DC-link filter cut-off frequency is chosen well below 300 Hz. The transmittance module $|T_{dcl}(S)|$ is depicted in Fig.6 with the cut-off frequency varying within a ±5% range of the design value. This substantial deviation from the design value is not unrealistic, considering that typical inductance and capacitance tolerances in this power range are approximately 2% and 10%, respectively. Consequently, for a DC-link filter designed to cut

<figure><img src="image_7.png" /><figcaption>Fig. 6: Normalized transmittance of the DC-link filter for $n = 4$ and for various cut-off frequencies.</figcaption></figure>

off at 41 Hz, the 300 Hz attenuation falls between 180.5 and 220.5 (Ω = 10 in Fig.6), and the anticipated residual 300 Hz amplitude at the switching leg output is approximated by $\Delta V_{o,300Hz} \approx 0.001 \times 3\sqrt{2}u_{rms}d/(35\pi)$. Hence, complete elimination of the 300 Hz content is challenging, but the expected attenuation is enhanced by 14 dB compared to a non phase-shifted configuration.

2) DC-link noise rejection by the control: It is assumed that the converter bandwidth is insufficient to compensate properly the DC-link noise. However, the DC-link noise can be introduced as a feed-forward signal based on the measurement of the DC-link voltage. Achieving tens of ppm at the output current necessitates a certain level of measurement accuracy, primarily reliant on precise control over the measurement chain delays. The approach involves determining the duty cycle by dividing the voltage reference by the measured DC-link voltage rather than an estimated constant. This method theoretically eliminates the DC-link noise. Given that the noise is significantly smaller than the DC component, a first-order approximation is employed to better understand the factors affecting performance. Thus, dividing the voltage reference by $V_{dc}^{meas} = V_{dc0}(1 + a \sin 2\pi ft)$ is represented as multiplying by $(1 - a \sin 2\pi ft)/V_{dc0}$. The DC-link compensation mechanism in its first order approximation is illustrated in Fig.7. The measurements are synchronized with the PWM signals therefore a pure delay ($T_d$) is inserted in the model. Because of this measurement delay, the resulting output voltage (only the low frequency content) at one switching leg is given by:

$$V_o = dV_{dc0} (1 + 2a \sin(2\pi f T_d / 2) \cos 2\pi ft), \quad (3)$$

indicating that this DC-link compensation mechanism enables a reduction of the DC-link noise by a factor of $1/(2 \sin(2\pi f T_d / 2))$. As intuitively suggested, the higher
<figure><img src="image_8.png" /><figcaption>Fig. 7: Principle of the 300 Hz rejection: 1st order approximation.</figcaption></figure>

the noise frequency, the lower the noise attenuation. Considering $f_{sw}$ = 5 kHz and $T_d$ = 1/f$_{sw}$, the 300 Hz and 600 Hz harmonics can be attenuated by factors of 2.65 and 1.34, respectively.

### III. EXPERIMENTAL RESULTS

#### A. Setup description

In order to validate both the mathematical equations and simulations, a *prototype* converter has been mounted and assembled. Its topology is very similar to the converter under design (see Fig. 8), except that H-bridges are used instead of single legs to ease the exploration around small output voltages. This topology difference has no impact on the conclusions as DC-Link perturbations are identically transferred to the output. The input stages are

<figure><img src="image_9.png" /><figcaption>Fig. 8: Prototype converter topology.</figcaption></figure>

the same: an extended delta transformer, a diode rectifier, a DC-link filter and a damping branch. The two power bricks are then linked in parallel via the high-frequency chokes $L_{hf}$ and connected to the common output stage made of high-frequency filtering capacitors, a damping branch, and a dummy load $R_m + L_m$. The component values are presented in TABLE III and photos of the *prototype* converter are given in Fig. 9 and 10.

<figure><img src="image_10.png" /><figcaption>Fig. 9: Prototype converter front side.</figcaption></figure>

<table><caption>TABLE III: Prototype converter component values.</caption><thead><tr><th>Section</th><th>Component</th><th>Value</th></tr></thead><tbody><tr><td>Input</td><td>Transfo Ext Dy11.5</td><td>400V/450V, 70kVA</td></tr><tr><td rowspan="4">DC-Link</td><td>$L_{dc}$</td><td>2 × 0.5mH</td></tr><tr><td>$C_{dc}$</td><td>9.36mF</td></tr><tr><td>$C_{dc2}$</td><td>48.33mF</td></tr><tr><td>$R_{dc}$</td><td>330mΩ</td></tr><tr><td rowspan="2">Powerstack</td><td>Diode rectifier</td><td></td></tr><tr><td>H bridge</td><td></td></tr><tr><td>High frequency chokes</td><td>$L_{hf}$</td><td>0.22mH</td></tr><tr><td rowspan="3">Output filter</td><td>$C_f$</td><td>47μF</td></tr><tr><td>$C_{f2}$</td><td>140μF</td></tr><tr><td>$R_f$</td><td>42mΩ</td></tr><tr><td rowspan="2">Load</td><td>$L_m$</td><td>100mH</td></tr><tr><td>$R_m$</td><td>150mΩ</td></tr></tbody></table>

#### B. Measurements

This experiment analyses the rejection of the DC-Link 300Hz perturbation of both the extended delta transformer 30° phase shift and the control compensation. The control compensation is implemented as described in II-C.

The findings outlined in II-C are validated using the prototype consisting of two power bricks powered by extended delta wye coupled transformers. Four scenarios are examined: a) No phase swapping and no DC-link compensation via control; b) Phase swapping without DC-link compensation via control; c) No phase swapping with DC-link compensation via control; d)
<figure><img src="image_11.png" /><figcaption>Fig. 10: Photos of the *prototype* converter used for experimental validation. (a) Power rack (front view). (b) Power rack (rear view). (c) Main rack (rear view).</figcaption></figure>

Phase swapping with DC-link compensation via control. Measurements of the load voltages are conducted, and an FFT analysis is carried out. The results are presented in Fig. 11 and in TABLE IV. Subsequently,

<table><caption>TABLE IV: Measurements of the DC-link noise transferred to the load voltage - 300 Hz content.</caption><thead><tr><td></td><td>No compensation</td><td>With compensation</td></tr></thead><tbody><tr><td>No phase shift</td><td>-21.35 dBv</td><td>-29.38 dBv</td></tr><tr><td>Phase shift</td><td>-38.16 dBv</td><td>-45.95 dBv</td></tr></tbody></table>

as described in II-C, the 300 Hz component does not vanish entirely: it undergoes attenuation by 16.81 dB compared to scenarios without any phase swap. The DC-link compensation by control further diminishes the 300 Hz harmonic by 8 dB (a factor of 2.5), aligning with the expected attenuation of $1/(2 \sin(2\pi f T_{sw}/2)) \approx 3.2$ for $f = 300$ Hz and $T_{sw} = 167$ µs.

IV. CONCLUSION

This article presented the challenges associated with achieving output current precision in the context of a multi-megawatt power supply operating in cycling mode on a low inductive electromagnet. Achieving an accuracy of 50 ppm remains quite ambitious for both

<figure><img src="image_12.png" /><figcaption>Fig. 11: Experimental measurement of the output voltage 300 Hz content in four cases.</figcaption></figure>

the measurement device, the power electronics structure and its control. Not only are the constraints on component parameter deviations in the DC-Link and high frequency filters demanding, but also the high sensitivity to mechanical construction asymmetries. In particular, the busbars connecting the high-frequency inductance and the output filter must be considered at a design early stage.

This study also showed by analytical calculations and simulations that it is futile to attempt to interleave too many switching legs to reduce noise in the output
current, as there is a point after which component asymmetries start to dominate the effects of current ripple due to IGBT switching frequency. Considering the specified components with realistic tolerances, this study showed that eight phase-shifted PWM carriers is a sound technological compromise at this power level.

Moreover, this study showed by analytical calculations, simulation and experimental measurements how the DC-link noise is transmitted to the load, how the use of phase 30° phase-shifted extended delta Dy11.5 transformers can help to reduce this noise and how the command structure can help to reduce it further. This study also showed the limitations of these methods. Although the 30° shifting of pairs of transformers can theoretically eliminate the 300 Hz content at the output, it is limited by the DC-link filter components tolerances and also by imperfections of the transformers themselves: the theory predicts an attenuation of at least 14 dB and experimental measurements showed that an attenuation of 17 dB can be reached by using common electrolytic capacitors with 10% of tolerance. This study also highlighted the limitation of the noise canceling technique by control: the attenuation scales as $1/(2 \sin(2\pi f T_{sw}/2))$ ($f$ being the frequency to attenuate), which is validated experimentally.

## REFERENCES

[1] G. Fernqvist, H.-E. Jorgensen, and A. Saab, "Design and verification of a 24 kA calibration head for a DCCT test facility [LHC current control]," *IEEE Transactions on Instrumentation and Measurement*, vol. 48, no. 2, pp. 346-350, Apr. 1999. [Online]. Available: https://ieeexplore.ieee.org/document/769598

[2] G. Hudson and K. Bouwknegt, "4-13 kA DC current transducers enabling accurate in-situ calibration for a new particle accelerator project, LHC," in *2005 European Conference on Power Electronics and Applications*, Sep. 2005, pp. 8 pp.-P.8. [Online]. Available: https://ieeexplore.ieee.org/document/1665385/

[3] X. Zhou, P.-L. Wong, P. Xu, F. Lee, and A. Huang, "Investigation of candidate vrm topologies for future microprocessors," *IEEE Transactions on Power Electronics*, vol. 15, pp. 1172-1182, 2000.

[4] Carrozza. S, Burini. F, Ferrari. E, Pretelli M, Taddia G, King. Q, Le Godec. G, Hudson. G, Bastos. M, Louie. D, "A New Concept of High Current Power Supply for the Main Cyclotron Magnet at TRIUMF" in 2016 *Proc. of International Conference on Cyclotrons and Their Applications (Cyclotrons' 16)*, Zurich, Switzerland, no. 21, pp. 186-189, 2016.

[5] S. Luo, Z. Ye, R.-L. Lin, and F. Lee, "A classification and evaluation of paralleling methods for power supply modules," in *30th Annual IEEE Power Electronics Specialists Conference. Record. (Cat. No.99CH36321)*, vol. 2, Jul. 1999, pp. 901-908 vol.2, iSSN: 0275-9306. [Online]. Available: https://ieeexplore.ieee.org/document/785618

[6] K.-D. Wu, M.-H. Chiu, C.-S. Jheng, J.-J. Chen, Y.-S. Hwang, Y.-T. Ku, and C.-C. Yu, "A new multiphase buck converter with optimum-damping-control and current-balanced techniques," in *2017 International Conference on Applied System Innovation (ICASI)*, May 2017, pp. 1320-1323. [Online]. Available: https://ieeexplore.ieee.org/document/7988146

[7] H.-W. Choi, S.-M. Kim, J. Kim, Y. Cho, and K.-B. Lee, "Current-balancing strategy for multileg interleaved DC/DC converters of electric-vehicle chargers," *Journal of Power Electronics*, vol. 21, no. 1, pp. 94-102, Jan. 2021. [Online]. Available: https://doi.org/10.1007/s43236-020-00172-x

[8] M. N. Rahman, D. Farrakhov, and V. Vavilov, "Designing of Variable Input Multiphase Buck Converter with Efficient Phase Current Balancing Technique," in *2023 International Conference on Electromechanical and Energy Systems (SIEL-MEN)*, Oct. 2023, pp. 1-6. [Online]. Available: https://ieeexplore.ieee.org/document/10290792

[9] L. Ni, D. J. Patterson, and J. L. Hudgins, "High Power Current Sensorless Bidirectional 16-Phase Interleaved DC-DC Converter for Hybrid Vehicle Application," *IEEE Transactions on Power Electronics*, vol. 27, no. 3, pp. 1141-1151, Mar. 2012. [Online]. Available: https://ieeexplore.ieee.org/document/5986729

[10] G. Tsolaridis, M. Jeong, and J. Biela, "Evaluation of Current Control Structures for Multi-Phase Interleaved DC-DC Converters," *IEEE Access*, vol. 9, pp. 142616-142631, 2021. [Online]. Available: https://ieeexplore.ieee.org/document/9583927/

[11] P. D. Antoszczuk, R. G. Retegui, N. Wassinger, S. Maestri, M. Funes, and M. Benedetti, "Characterization of Steady-State Current Ripple in Interleaved Power Converters Under Inductance Mismatches," *IEEE Transactions on Power Electronics*, vol. 29, no. 4, pp. 1840-1849, Apr. 2014. [Online]. Available: https://ieeexplore.ieee.org/document/6544315/

[12] M. A. Alharbi, M. S. A. Dahidah, S. A. Ali, S. A. E. Ethni, and V. Pickert, "Ripple-Free Multiphase Interleaved Stacked Converter for High-Power Applications," *IEEE Transactions on Power Electronics*, vol. 37, no. 12, pp. 14770-14780, Dec. 2022. [Online]. Available: https://ieeexplore.ieee.org/document/9844867/

[13] Choi. S, Lee. B, Enjeti. P, "New 24-pulse diode rectifier systems for utility interface of high-power AC motor drives", *IEEE Transactions on Industry Applications*, volume 33, pp. 531 - 541, Apr 1997. [Online]. Available: https://ieeexplore.ieee.org/document/568020