# Enhanced Optimization of Power Modules Considering Static and Dynamic Losses Using Fully Coupled RLCG Matrices for Superior Thermal and Electrical Performance

Wilfried Wessel, Gergő Juhász, Florian Bauer, Andreas Schwarzbacher, Christian Jakob

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## To cite this version:

Wilfried Wessel, Gergő Juhász, Florian Bauer, Andreas Schwarzbacher, Christian Jakob. Enhanced Optimization of Power Modules Considering Static and Dynamic Losses Using Fully Coupled RLCG Matrices for Superior Thermal and Electrical Performance. The 26th European Conference on Power Electronics and Applications, GDR SEEDS France & EPE Association, Mar 2025, Paris, France. 10.34746/epe2025-0016. hal-05073951

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https://utc.hal.science/hal-05073951v1

Submitted on 19 May 2025

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# Enhanced Optimization of Power Modules Considering Static and Dynamic Losses Using Fully Coupled RLCG Matrices for Superior Thermal and Electrical Performance

Wilfried Wessel ¹,³, Gergő Juhász ², Florian Bauer ³, Dr. Andreas Schwarzbacher ¹,
Prof. Dr. Christian Jakob ⁴

¹ TU Dublin / Faculty of Electrical and Electronic Engineering, Dublin, Irland

² Vincotech Hungária Kft, Bicske, Hungary

³ Siemens EDA GmbH, Munich, Germany

⁴ University of Applied Sciences Darmstadt / Faculty of Electrical and Electronic Engineering, Darmstadt, Germany

Tel.: +49 / (0) 172 831 46 91

E-Mail: wilfried.wessel@siemens.com

URL: https://www.tudublin.ie/, https://eda.sw.siemens.com/

## Keywords

Design Optimization, Design Space Optimization, Co-Simulation, Computational Cost, Static and Dynamic Losses

## Abstract

This paper presents an advanced, fully automatic placement optimisation method to find an optimised physical design that showed improved thermal performance. The primary optimisation objective is to reduce temperature differences in parallel SiC MOSFET devices. This is done using fully coupled resistance, inductance, conductance, and capacitance matrices to simulate accurate time domain waveforms in an automated, novel optimisation approach. The proposed method replaces modelling power modules using simple parasitic models and enables the integration of switching losses into optimisation. The paper demonstrates that temperature differences can be significantly reduced from 7.72 *K* to 2.52 *K* between parallel SiC MOSFETs. The study emphasises that simple parasitic models, commonly found in datasheets, are no longer adequate for describing power module behaviour, and more enhanced models are necessary.

## 1. Introduction

Even if power modules, hereafter called PM, have an efficiency of up to 98%, investing in enhanced methods for automatically optimising these central units in power electronics is essential. For

example, the Vincotech LC59 [1] is used in solar inverters with a direct current (DC) input voltage of 1350 V and a root mean square (RMS) load current of 120 A. Under these conditions, the module efficiency is 98%. Increasing the PM's efficiency from 98% to 99% is significant. Reaching this state means a reduction in losses of 50%. The existing optimisation methods must be significantly enhanced to achieve this and even more sophisticated goals. This evolution must be done in two main areas. The first area addresses the automation of optimisation, which reduces manual engineering effort and resources. More automation is required since the interdependency between electrical and thermal parameters makes manual optimisation using traditional design and verification methods impossible. Secondly, using more accurate models and modelling methods to create a digital twin of a PM capable of predicting real-world behaviour at its best. The paper [2] focused on improving the optimisation process to reduce manual labour. The study in [2] was based on a power module with five parallel Silicon Carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs). That study significantly reduced the device temperature difference from 7.72 *K* to 4.89 *K* by automatically changing copper structures and placement. Using the same design, this paper focuses on the second area and enhances the process using more accurate interconnect models. The main goal of using these more accurate models is to find the root causes of the remaining temperature difference and a new substrate design template that can be optimised fully automatically.
Additionally, this paper describes how differences in device temperature are reduced from 7.72 K to 2.52 K, improving the performance of the initial optimisation by over 25%. How this was done is described in sections 2 to 4. The paper's second section describes the main reason for the remaining temperature difference and how the new substrate template overcomes the challenges of restrictions in placement and routing. Section three discusses adding static and dynamic switching losses to enhanced automatic optimisation. These losses were automatically simulated using the fully coupled resistance, inductance, conductance, and capacitance (RLGC) matrices. The section also includes the optimisation configuration and the cost function definition. In section four, all measurement results are discussed and compared with the simulated results. Finally, the conclusion gives an outlook on the following steps to enhance the process further.

## 2. Effects of Designs on Electrical and Thermal Performances

Figure 1 shows the original power module design used in an inverter application. All figures 1 to 3 include five parallel placed SiC MOSFETs called T13_a to T13_e. Besides the SiC MOSFETs application connectors, which are consecutively numbered, copper shapes and bond wires are represented. To illustrate the current path in the figures, current injection and outlet points are marked with $i_{in}$ and $i_{out}$. Even though five SiC MOSFETs are placed in parallel, the physical implementation in Figure 1 creates a serial structure. In this structure, all consecutively placed transistors share the complete current path of the predecessor. This caused the thermal measurements of the manufactured design to result in a temperature difference of 7.72 K, which is distributed linearly from left T13_a to right T13_e. Figure 6 shows the result of the measurement that illustrates the temperature distribution.

<figure><img src="image_3.png" /><figcaption>Fig. 1: Design I - Original Power Module Using Five SiC MOSFETs in Parallel[2]</figcaption></figure>

The high-temperature difference affects the module's lifetime [11] and must be significantly reduced using optimisation methods. The result of the first optimisation is shown in Figure 2 [2]. Forcing the electrical current into two separate paths, named $i_1$ and $i_2$, and adjusting the placement significantly reduced the temperature difference to 4.89 K. It was necessary to identify and reduce the remaining temperature difference to address the impact of temperature on lifetime. The changes in Figure 2 through automatic optimisation were further examined for this. The optimisation in [2] used a simple parasitic interconnect model where the entire power loop, including the drain and source path, was shorted. The changes focused on equalising the resistance and inductance of the power loop. Analysis of Figure 2 revealed that most of the changes were made in the drain part of the power loop. The automated adjustment of the copper cutout and placement resulted in a significantly reduced difference in device temperature of 4.89 K. Still, the study demonstrated that significant differences in the source path could not be fully compensated for by making changes in the drain path.

<figure><img src="image_4.png" /><figcaption>Fig. 2: Design II - The Result of the First Automatic Optimization [2]</figcaption></figure>

There are two main reasons for this. The first reason lies in the basic functionality of the MOSFET transistor [19]. The drain current in saturation mode is described in Equation 1 [4, pp. 19-4]. If the channel length modulation factor $\lambda$ is small and the conduction factor $k$ and threshold voltage $V_{th}$ are constant, the drain current $I_D$ only depends on the gate-source voltage $V_{GS}$. Referring to a small $\lambda$, the drain current $I_D$ is independent of the drain-source voltage $V_{DS}$.

$$I_D = \frac{1}{2} \cdot k(V_{GS} - V_{th})^2 \cdot (1 + \lambda \cdot V_{DS}) \quad (\text{Eq. 1})$$

The design in this study has one gate driver for all five parallel SiC MOSFETs. This is a common practice for cost reduction [20]. This causes
different gate-source voltages for each device due to the difference in impedance in the source path. This difference is mainly caused by the difference in copper length, as shown in Figure 1. For this reason, each transistor operates at a different operating point when switched on [19]. The second reason is described in [5], where Li showed the significant influence of the series stray inductance $L_s$ on switching losses. Also, in this case, the length difference in the source path causes a remarkable difference in the $L_s$ of each transistor source path. These findings led to a significantly enhanced template design for the automated optimisation process. Like the first design, this design is restricted in design options because of the compatibility with the inverter application board. Figure 3 shows the new template design.

<figure><img src="image_5.png" /><figcaption>Fig. 3: Design III - Enhanced Design Template to Start the Full Automatic Optimization Process</figcaption></figure>

Compared to the original design in Figure 1 and the result of the first optimisation in Figure 2, the design changes introduced in Figure 3 were focused on the source path. The significant changes were:

* The series source connection was transformed into a star point connection.

* Die-to-die bonds were used to tune the source path length.

* Devices were rotated by 45°.

* Enhanced drain path by bridging connections at pin 43.

All three design variants were compared against dynamic switching energies and the static current distribution during the on-state. To better understand how substrate parasitics as a fully coupled RLCG matrix affect the switching energies and losses, the following diagrams in Figures 4 and 5 demonstrate the differences in turn-on energy of *T13_a* and *T13_e* and how they are calculated in the original design. A single switch-on event was simulated using the power module schematic and HyperLynx Analog Mixed-Signal Simulation [12]. This schematic

was used to generate the simulation program with an integrated circuit emphasis (SPICE) netlist to simulate the waveforms, which are the foundation for the loss calculation.

<figure><img src="image_6.png" /><figcaption>Fig. 4: Design I – Turn-On Energy Simulation for *T13_a*</figcaption></figure>

Figure 4 shows such a single event for *T13_a*, including the drain current $I_{DS}$ and the drain-source voltage $V_{DS}$ in the top diagram. The second diagram represents the gate voltage $V_{GS}$. According to [6], the region of interest is where the gate voltage $V_{GS}$ exceeds 10% of the final voltage, marked with a cursor at 2.0328 *us*, and when $V_{DS}$ is less than 3% of the voltage in the switched-off state, marked at 2.1174 *us*. The third diagram from the top in Figure 4 limits the waveforms of $I_{DS}$ and $V_{DS}$ to this region. Multiplying both quantities in the fourth diagram from the top results in the turn-on power for *T13_a*. The bottom diagram in Figure 4 shows the result of integrating the turn-on power in the boundaries of 2.0328 *us* and 2.1174 *us* with 95 *uJ*. This standard method was used to calculate device-specific losses. The simulation was performed using a technology-specific SPICE model. The difference in impedance for each transistor causes differences in the switching behaviour, as demonstrated in Figure 5. Embedding the fully coupled RLCG matrix caused *T13_e* in Figure 5 to have a different operation point than *T13_a*, leading to a significant difference in turn-on energy of 554 *uJ*. Applying this method to all design templates results in Table I, which shows the simulated
switch-on energy $E_{on}$, switch-off energy $E_{off}$, and the drain current $I_D$ through the SiC MOSFETs. Design I corresponds to Figure 1, Design II to Figure 2, and Design III to Figure 3.

<figure><img src="image_7.png" /><figcaption>Fig. 5: Design I – Turn-On Energy Simulation for T13_e</figcaption></figure>

<table><caption>Table I: Comparison of Simulated Dynamic Switching Energies and the On-Current</caption><thead><tr><th></th><th>Design I<br>(E<sub>on</sub>/E<sub>off</sub><br>I<sub>D</sub>)</th><th>Design II<br>(E<sub>on</sub>/E<sub>off</sub><br>I<sub>D</sub>)</th><th>Design III<br>(E<sub>on</sub>/E<sub>off</sub><br>I<sub>D</sub>)</th></tr></thead><tbody><tr><td>T13_a</td><td>95 μJ/199 μJ<br>17.19 A</td><td>77 μJ/192 μJ<br>26.75 A</td><td>174 μJ/221 μJ<br>20.08 A</td></tr><tr><td>T13_c</td><td>198 μJ/176 μJ<br>18.32 A</td><td>198 μJ/176 μJ<br>10.44 A</td><td>393 μJ/185 μJ<br>21.05 A</td></tr><tr><td>T13_e</td><td>657 μJ/215 μJ<br>26.12 A</td><td>622 μJ/221 μJ<br>20.13 A</td><td>226 μJ/221 μJ<br>16.27 A</td></tr></tbody></table>

The table shows that the optimisation of Design II in [2] significantly affected the drain current $I_D$. The table also shows that the effect on the losses caused by $E_{on}$ and $E_{off}$ is negligible. The reason for those findings is that the optimisation of Design II in [2] was based on simple single electrical parasitics and thermal resistance. This resulted in [2] only affecting the static losses and not the dynamic losses. To include dynamic losses, a fully coupled RLCG matrix in the time domain simulation is required [10]. Table II shows a

simplified, fully coupled resistance matrix of Design I. The table represents the resistance between the source nodes of T13a, T13c, T13e and the current outlet connector CN. For a full representation, an inductance, capacitance and conductance matrix is required as well. Embedding those matrices into a SPICE simulation allows the modelling of current and voltage coupling between the parallel SiC MOSFET devices, which is impossible using simple parasitics as used in [21]. The last column of Table II represents simple parasitics. Embedding them into a SPICE netlist causes three separate current paths, which are insufficient to model common source effects.

<table><caption>Table II: Example of a Fully Coupled Resistance Matrix of Design I</caption><thead><tr><th></th><th>T13a</th><th>T13c</th><th>T13e</th><th>CN</th></tr></thead><tbody><tr><td>T13a</td><td>0 mΩ</td><td>14.15 mΩ</td><td>20.14 mΩ</td><td>20.67 mΩ</td></tr><tr><td>T13c</td><td>14.15 mΩ</td><td>0 mΩ</td><td>15.26 mΩ</td><td>15.67 mΩ</td></tr><tr><td>T13e</td><td>20.14 mΩ</td><td>15.26 mΩ</td><td>0 mΩ</td><td>9.42 mΩ</td></tr><tr><td>CN</td><td>20.67 mΩ</td><td>15.67 mΩ</td><td>9.42 mΩ</td><td>0 mΩ</td></tr></tbody></table>

Compared to that, the fully coupled matrix side elements are used to calculate resistive, capacitive and inductive coupling between the devices. The design template created in Design III was created under those considerations. Comparing the extreme cases, T13_a and T13_e demonstrate significantly better loss distribution between both devices. The new template also caused a change in the order of highest dynamic and static losses of all five parallel SiC MOSFETs. The device with the highest dynamic and static losses changed to T13_c, which is the SiC MOSFET in the centre of the parallel circuit in Figure 3. T13_c shows a maximum difference in static drain current $I_D$ of 4.78 A compared to T13_e and a maximum difference in $E_{on}$ of 219 μJ compared to T13_a. This proves that the initial state of Design III is a significantly better baseline for a fully automatic optimisation run, as described in the next section. Compared to [2], all transistor devices are simultaneously considered. The results of this optimisation run are analysed to determine if this method leads to better-performing PM with more equalised temperatures and lower losses.
### 3. Fully Automatic Optimization to Equalise the Device Temperatures.

The differences in static and dynamic losses of Section 2 are still too high to reach the goal of equal device temperatures. The pre-analysis focused only on the electrical domain. Because of the interdependencies between the electrical and thermal parameters, both domains must be considered simultaneously during optimisation. Compared to the first paper [2], this study's primary goal is to equalise simulated temperatures, not electrical and thermal impedance. Achieving equal temperatures can happen in various ways. This paper uses automatic placement adjustment using an enhanced optimisation workflow revolving around Siemens EDA tools. In this study, electrical and thermal impedance can differ if the temperature matches. The two extreme cases can be used as examples. The first case has a low electrical and thermal impedance, and the second and opposite case has a high impedance in both domains, but both cases can result in the same temperature. To achieve this, the tuning mechanism changed from equalising parameters to changing parameters, for example, increasing the electrical impedance in the source path to reduce losses and achieve equal temperatures. An increase in source path length leads to an increase in source path resistance. The higher resistance has two effects. The first effect is a redistribution of the current due to the change in resistance, and the second effect is a change in the MOSFETs operation point due to the changed gate-source voltage. Both effects reduce the drain current, which reduces the static losses. A similar effect can be observed for increased inductance. These findings were verified based on Design I using the simulation method described before and thermal measurements.

<figure><img src="image_8.png" /><figcaption>Fig. 5: Design I – Drain Current Distribution of T13_a to T13_e</figcaption></figure>

Figure 5 shows all simulated drain current waveforms. This figure highlights that T13_e, with the least source resistance and inductance, has the highest static and dynamic drain current. T13_a has the highest source path resistance and inductance, leading to the lowest static and dynamic currents. The difference in source impedance results in the described 7.72 K temperature difference, as shown in the measurements of Figure 6. The measurements show a linear temperature distribution from left at T13_a to right at T13_e.

<figure><img src="image_9.png" /><figcaption>Fig. 6: Thermal Measurements of Design I [2]</figcaption></figure>

When changing the design parameters, such as component placements, the electrical and thermal dependencies necessitate a multi-domain optimisation environment and can no longer be done by manual labour. The following section describes all significant enhancements in the optimisation environment compared to the one used in [2]. The first enhancement was that the placement of all five SiC MOSFETs was optimised at once. This significantly reduced the run time by increasing the flexibility of the experiment. The second enhancement was instead of using simple parasitics, a fully coupled RLGC matrix was extracted using Siemens HyperLynx Advanced Solvers Fast 3D [13] called HLAS, a quasi-static electrical solver utilising the method of moments [7]. Third, the fully coupled RLGC matrix was automatically back annotated in the electrical SPICE netlist [10]. This enabled the simulation of static and dynamic losses in HyperLynx AMS, hereafter called AMS, a multi-language functional solver [12]. Simulating a transient double pulse and extracting losses was fully automated, according to [6, pp. 48]. This enabled automatic back-annotation of those losses into the thermal simulation, which was the fourth improvement. Using the mentioned losses in the thermal simulation allowed the actual device temperatures to be obtained. Siemens Simcenter FLOEFD [14], later referred to as FLOEFD, was used as the thermal simulation
environment. The entire process flow and all improvements are detailed in Figure 7. The rectangles with rounded corners indicate the Siemens EDA tool utilised for the design and verification task. The design exploration software, HEEDS [15], controls all other tools through the application programming interface (API). Portals, which consist of the code to call each product's API, were created to carry out these tasks. The arrows from left to right in Figure 7 represent the API calls, while the right-to-left arrows illustrate the response. For instance, HEEDS utilises the Siemens Xpedition [16] API to simultaneously adjust the placement of the five SiC MOSFETs in the PM design system.

<figure><img src="image_10.png" /><figcaption>Fig. 7: Process Flow Including all Enhancements</figcaption></figure>

The response is an adjusted PM design utilised for electrical and thermal simulation as well as manufacturing. Using HEEDS [8] for design space exploration, the best placement was explored in a range of ±1 mm in the x and y direction of the component origin defined in Design III. The objective for this placement optimisation was to achieve equalised device temperatures. Combining the optimisation with state-of-the-art design and verification software has significant advantages, as shown in Figure 7. The combination ensures manufacturability due to online design rule checks (DRCs). Other design adjustments, such as adapting the bond wire placement, are made automatically when the component placement changes. Having this functionality in place to equalise all device temperatures simultaneously requires a suitable cost function to find the minimum difference. The cost function in Equation 2 was designed so that the best possible solution has zero value.

$$f_{cost} = (\sum |T_{Tn} - T_{avg}|) \cdot 1000 \quad (\text{Eq. 2})$$

The function sums up all device temperature differences to the average temperature of all five SiC MOSFETs. The result of the sum is weighted with the factor 1000. Especially when initial differences are not as high, the weighting helps to find better results faster. Equation 2 also shows how a design exploration has advantages over pure optimisation since the cost function does not include the minimisation of the absolute temperature. As a result of design space exploration, multiple solutions with equal device temperatures but different maximum temperatures can be found. Exploring the design space was done using an algorithm for multi-objective Pareto optimisation. The algorithm used in this paper was the hybrid adaptive method MO-SHERPA. This method is proprietary to Siemens HEEDS and outperforms other algorithms, such as NSGA-II [17]. Using the results of the simulated temperatures, the search performed with MO-SHERPA is guided to an optimal design. For those optimisation algorithms, the search path differs from run to run. This makes the initial design, which is the starting condition, crucial to reducing the number of evaluations [17]. Processing 76 iterations took 9 hours and 37 minutes on an Intel® Xeon® Gold 5220R. A result summary of 25 designs of those 76 is represented in Figure 8.

<figure><img src="image_11.png" /><figcaption>Fig. 8: Summary of Optimisation Results as Cost Function against Design ID</figcaption></figure>
The diagram shows how the cost function evolved between those 25 design iterations. The baseline and the best design are marked. The best design with a cost function value of 417.9 was found. This translates to a temperature difference of 0.42 K between all devices and their average temperature. This result demonstrates significant improvement compared to the first optimisation, leading to the final design represented in Figure 9.

<figure><img src="image_12.png" /><figcaption>Fig. 9: Design IV - Best Design after 76 Iterations Achieving a Device Temperature Difference of 0.42 K</figcaption></figure>

<table><caption>Table III: Comparison of the Initial Design (Design III) and the Optimised Design (Design IV)</caption><thead><tr><th></th><th>Design III<br>(E<sub>on</sub>/E<sub>off</sub><br>P<sub>N</sub>/T<sub>N</sub>)</th><th>Design IV<br>(E<sub>on</sub>/E<sub>off</sub><br>P<sub>N</sub>/T<sub>N</sub>)</th></tr></thead><tbody><tr><td>T13_a</td><td>174 µJ / 221 µJ<br>27.37 W / 327.03 K</td><td>174 µJ / 221 µJ<br>27.69 W / 328.65 K</td></tr><tr><td>T13_b</td><td>331 µJ / 190 µJ<br>30.89 W / 330.77 K</td><td>331 µJ / 192 µJ<br>31.13 W / 328.76 K</td></tr><tr><td>T13_c</td><td>393 µJ / 185 µJ<br>32.78 W / 327.97 K</td><td>395 µJ / 184 µJ<br>32.84 W / 328.87 K</td></tr><tr><td>T13_d</td><td>385 µJ / 186 µJ<br>30.56 W / 326.54 K</td><td>379 µJ / 187 µJ<br>29.99 W / 328.77 K</td></tr><tr><td>T13_e</td><td>226 µJ / 221 µJ<br>25.26 W / 326.74 K</td><td>230 µJ / 223 µJ<br>25.40 W / 328.94 K</td></tr></tbody></table>

Table III compares the designs before and after optimisation regarding $E_{on}$, $E_{off}$, the device total loss $P_N$, and temperature $T_N$. The results demonstrate that small changes in placement of ±1 mm significantly impact device temperature. This further proves that computer-aided optimisation is needed and that such tasks can no longer be done manually. Considering the high design sensitivity to placement changes, the manufacturing tolerance for the die placement

must be low enough to produce representative prototypes for measurements. For this reason, the chosen manufacturing process had a tolerance of ±50 µm.

## 4. Design IV Measurements

The manufactured PM was characterised using electrical and thermal measurements. Except for the modified thermal measurements in the application, all other measurements can only be performed globally at the module level. The disadvantage of using these standard measurements is that no direct correlation can be made to the behaviour of the single SiC MOSFET device. The first measurement was the double pulse test. The test was performed for the electrical characterisation of Design I, Design II, and Design IV. Figure 10 shows the measurements for Design IV on a Tektronix MSO58 [18] and includes the drain current $I_D$ on measuring channel Ch 3. The current was measured using an SDN-414-01 coaxial shunt [22]. The voltage drop of the shunt was measured using a TPP1000 passive probe [23]. All other voltages were measured using the PMK BumbleBee differential probe [24]. These were the gate-source voltage $V_{GS}$ on channel Ch 1, the drain-source voltage $V_{DS}$ on channel Ch 2, and the output voltage $V_{out}$ on channel 4. These measurements were performed globally on the PM level and used to analyse the PM's functionality, voltage overshoot, ringing, and switch on/off energies. The accuracy of the measurement setup was evaluated using 60 measurements on three different component technologies. As test current 20% and 100% of the nominal device current was used.

<figure><img src="image_13.png" /><figcaption>Fig. 10: Measured Waveforms on Tektronix Series 5 Oscilloscope to Characterise the Electrical Behaviour Using a Double Pulse Test</figcaption></figure>

Those measurements were repeated five times to calculate the tolerances between measurements.
The result of this evaluation was a tolerance of measured E<sub>on</sub> and E<sub>off</sub> of +2.75% and -1.93%. Table IV compares the measured performance using the described measurement setup. The table shows the performance of the original design in Figure 1, the first optimisation result in Figure 2 [2], and the final design in Figure 9 of this paper. E<sub>on</sub> and E<sub>off</sub> and the rise and fall time t<sub>r</sub> and t<sub>f</sub> were used as benchmarks. The measurements were performed using a 2 Ω gate resistor, 600 V V<sub>DS</sub>, and a load of 125 μH. The load current was set in discrete steps to 25 A, 75 A, 125 A, 175 A, and 225 A to measure the load-dependent performance. A similar test bench was used for the simulation. In contrast to the measurements, the inductor was replaced by an ideal current source to speed up the simulation process.

<table><caption>**Table IV: Comparison of E<sub>on</sub>, E<sub>off</sub>, t<sub>r</sub>, and t<sub>f</sub> Measurements of the Original Design, Design I, Design II [2], and the Optimised Design, Design IV at 75 A and 225 A**</caption><thead><tr><th></th><th>Design I<br>(75 A)<br>(225 A)</th><th>Design II<br>(75 A)<br>(225 A)</th><th>Design IV<br>(75 A)<br>(225 A)</th></tr></thead><tbody><tr><th>E<sub>on</sub></th><td>661 μJ<br>1.18 mJ</td><td>696 μJ<br>1.38 mJ</td><td>686 μJ<br>1.58 mJ</td></tr><tr><th>E<sub>off</sub></th><td>1.08 mJ<br>5.16 mJ</td><td>1.10 mJ<br>5.18 mJ</td><td>1.18 mJ<br>5.54 mJ</td></tr><tr><th>t<sub>r</sub></th><td>17.79 ns<br>31.24 ns</td><td>17.77 ns<br>31.84 ns</td><td>17.50 ns<br>34.15 ns</td></tr><tr><th>t<sub>f</sub></th><td>16.53 ns<br>21.67 ns</td><td>16.54 ns<br>21.64 ns</td><td>15.20 ns<br>21.34 ns</td></tr></tbody></table>

The table above shows an increase in the sum of E<sub>on</sub> and E<sub>off</sub> of about 7.2% at a load case of 75 A from Design I to Design IV. The rise time at this load case decreased by 0.29 ns, and the fall time decreased by 1.33 ns. Increasing the load further up to 225 A shows an additional increase in module losses for all three designs. Comparing the 225 A load case results in a difference in switch-on and-off energy of 12.3 %. Under this condition, the rise time increased by 2.91 ns, and the fall time decreased by 0.34 ns from Design I to Design IV. Especially at the 225 A load cases, the measured difference exceeds the measurement tolerance, resulting in higher PM temperatures in the application. Since these

measurements were global on the PM level, application testing is required to measure temperature differences on the single device level. Figure 11 shows the PM of Design IV in the inverter application. To perform the thermal measurements on the device level, the application board and the PM enclosure required modifications similar to [2]. Modifications such as physical board cutouts are time-consuming, and using press-fit pins is insufficient to perform measurements on a large scale. To avoid future application measurements, novel optimisation methods are required.

<figure><img src="image_14.png" /><figcaption>**Fig. 11: Manufactured PM of Design IV in the Inverter Application**</figcaption></figure>

The conditions in [2] were guaranteed using the PM in circulator mode [9], with a system voltage of 500 V and a load of 57 A. The device temperatures were measured using the same measurement equipment as before in [2]. Figures 12, 13, and 14 represent the results of the thermal measurements using an InfraTec ImageIR® 8300 Thermal Camera [25]. “The camera has a thermal resolution of 20 mK and an accuracy of +/- 1%” [25]. Five circular measurement areas, C1 to C5, as shown in Figure 14, with 621 pixels, were used for the temperature measurement. Compared to the first paper [2], the measurement area position dependency on the relative temperature difference was analysed. For this analysis, the temperature was measured at three different positions on the SiC MOSFETs. As a result, only the maximum temperature, but not the temperature difference, was affected. For this reason, the same relative measurement position as used in [2] was used. Figure 14 shows the measurement results of Design IV. The hottest device in the measurement was T13_d at C4, which had a temperature of 70.04 °C, and the coolest device was T13_a, which had a temperature of 67.52 °C at C1. Table IV summarises the minimum and maximum measurements of Design I in Figure 12, Design II in Figure 13, and Design IV in Figure 14.
<table><caption>**Table V: Comparison of minimum and maximum Measurement Temperatures**</caption><thead><tr><th></th><th>Design I<br>Si<sub>3</sub>N<sub>4</sub></th><th>Design II<br>Al<sub>2</sub>O<sub>3</sub></th><th>Design IV<br>Al<sub>2</sub>O<sub>3</sub></th></tr></thead><tbody><tr><th>T<sub>min</sub></th><td>58.89 °C</td><td>62.58 °C</td><td>67.52 °C</td></tr><tr><th>T<sub>max</sub></th><td>66.61 °C</td><td>67.86 °C</td><td>70.04 °C</td></tr><tr><th>ΔT</th><td>7.72 K</td><td>5.28 K</td><td>2.52 K</td></tr><tr><th>TN<sub>min</sub></th><td>58.89 °C</td><td>58.00 °C</td><td>62.58 °C</td></tr><tr><th>TN<sub>max</sub></th><td>66.61 °C</td><td>62.89 °C</td><td>64.92 °C</td></tr><tr><th>ΔTN</th><td>7.72 K</td><td>4.89 K</td><td>2.32 K</td></tr></tbody></table>

<figure><img src="image_15.png" /><figcaption>Fig. 12: Thermal Measurements of Design I [2]</figcaption></figure>

<figure><img src="image_16.png" /><figcaption>Fig. 13: Thermal Measurements of Design II [2]</figcaption></figure>

<figure><img src="image_17.png" /><figcaption>Fig. 14: Thermal Measurements of Design IV</figcaption></figure>

Additionally, the table represents the normalisation of absolute temperature differences caused by using different substrate materials. To take the better heat transfer of silicon nitride Si₃N₄ compared to aluminium oxide Al₂O₃ into account, the temperatures were multiplied by a correction factor of 0.9268. The factor was calculated using

the higher thermal conductivity of 80 W/mK for Si₃N₄, compared to the 20 W/mK for Al₂O₃, in the whole substrate thermal resistance calculation. The remaining temperature difference is 2.52 K or normalised 2.32 K, which is an excellent result. Figure 15 represents another finding of this paper. The figure shows the dynamic process of the thermal measurements. Each line represents the temperature over time of one out of five SiC MOSFETs. The measured areas are C1 to C5, so the devices are described as measurement channels. It can be observed that the order in which the device's temperature changes, from the highest to the lowest, depends on whether the PM is heating up or cooling down. Under certain circumstances, this difference must be considered in the optimisation. For the use case in this paper, it did not affect the maximum device temperature difference.

<figure><img src="image_18.png" /><figcaption>Fig. 15: Dynamic Thermal Measurement Cycle Showing the Cooling and Heating Phase.</figcaption></figure>

## 5. Conclusion

In summary, this paper emphasises the crucial role of the initial design, accurate models, and modelling methods for effective optimisation. The fully automatic placement optimisation in a range of ±1 mm in the x and y direction provided a new design showing significantly less temperature difference in the five parallel SiC MOSFET devices compared to the work presented in [2]. Measurements of the manufactured prototype showed an additional reduction in device temperature difference of 2.5 K. This result was achieved by simulating transient voltages and currents, back-annotating a fully coupled RLGC matrix, and simulating static and dynamic losses using an enriched SPICE netlist. The thermal measurement results of Design IV suggest that to achieve further accuracy improvements, the model must be further enhanced. Potential areas for
improvement include modelling bond wires' Joule heating and considering variations in device parameters, such as the drain-source resistance $R_{DS}$ of the SiC MOSFETs. Even with a well-understood placement process with a tolerance of ±50 µm, it is important to analyse design robustness in order to predict manufacturing yield. Therefore, the remaining temperature difference could be attributed to the factors mentioned earlier. As a final improvement, the simulation time of 76 iterations totalling 9 hours and 37 minutes, including electrical and thermal simulations, could be reduced by using simpler reduced-order models. This paper contributes to best practices in modern power module design and is vital for achieving the goal of power module synthesis.

## References

[1] ‘10-PG12NAB008MR04-LC59F46T’. Vincotech, May 18, 2018. Accessed: Jan. 17, 2025. [Online]. Available: https://shorturl.at/5rwjs

[2] W. Wessel, R. Bátai, G. Juhász, F. Bauer. Dr. A. Schwarzbacher, Prof. Dr. C. Jakob, Optimising a Power Module for Electrical and Thermal Performance and Symmetry Using EDA Tools, PCIM 2024

[3] W. Wondrak, ‘Physical limits and lifetime limitations of semiconductor devices at high temperatures’, Microelectronics Reliability, vol. 39, no. 6–7, pp. 1113–1120, Jun. 1999, doi: 10.1016/S0026-2714(99)00158-4.

[4] M. E. Van Valkenburg and W. Middleton, Reference data for engineers: radio, electronics, computer, and communications, 9th ed. Boston Oxford: Newnes, 2002.

[5] X. Li, L. Zhang, S. Guo, Y. Lei, A. Q. Huang, and B. Zhang, ‘Understanding switching losses in SiC MOSFET: Toward lossless switching,’ in 2015 IEEE 3rd Workshop on Wide Bandgap Power Devices and Applications (WiPDA), Blacksburg, VA, USA: IEEE, Nov. 2015, pp. 257–262. doi: 10.1109/WiPDA.2015.7369295.

[6] ‘Power module datasheet explanation.’ Vincotech, Jul. 28, 2020. [Online]. Available: https://shorturl.at/IQIKo

[7] W. C. Gibson, The method of moments in electromagnetics. Boca Raton: Chapman & Hall/CRC, 2008.

[8] L. Hertel, J. Collado, P. Sadowski, J. Ott, and P. Baldi, ‘Sherpa: Robust hyperparameter optimization for machine learning,’ SoftwareX, vol. 12, p. 100591, Jul. 2020, doi: 10.1016/j.softx.2020.100591.

[9] E. Temesi, ‘Applying Power Circulation Theory to More Accurately Measure Power Loss and Efficiency.’ Vincotech, 2015.

[10] W. Wessel and B. Hoppe, ‘Board parasitic integration in the PCB verification process’, in 2017 28th Irish Signals and Systems Conference (ISSC), Killarney, Ireland: IEEE, Jun. 2017, pp. 1–4. doi: 10.1109/ISSC.2017

[11] R. ten Have, B. Vermulst, and J. van Duivenbode, ‘An approach to lifetime estimation of SiC MOSFETs subjected to thermal stress’, in Proceedings of PCIM Europe 2015; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, May 2015, pp. 1–9. Accessed: May 01, 2024. [Online]. Available: https://shorturl.at/sWeiZ

[12] ‘HyperLynx Analog Mixed Signal Simulation’. Siemens DI SW, Oct. 01, 2025. Accessed: Jan. 10, 2025. [Online]. Available: https://shorturl.at/sWeiZ

[13] ‘HyperLynx Advanced Solvers (HLAS)’. Accessed: Apr. 13, 2024. [Online]. Available: https://shorturl.at/rBXau

[14] ‘Simcenter FLOEFD’. Siemens Software. Accessed: Sep. 27, 2024. [Online]. Available: https://shorturl.at/4VUFN

[15] ‘Simcenter HEEDS’. Siemens Software. Accessed: Sep. 27, 2024. [Online]. Available: https://shorturl.at/iB8Vl

[16] ‘Xpedition Enterprise’. Siemens Software. Accessed: Sep. 27, 2024. [Online]. Available: https://shorturl.at/INEeG

[17] N. Chase, M. Rademacher, E. Goodman, R. Averill, and R. Sidhu, ‘A Benchmark Study of Multi-Objective Optimization Methods’. red cedar Technology. Accessed: Jan. 14, 2025.

[18] ‘8-Kanal-MSO (Mixed-Signal-Oszilloskop) der Serie 5 B’. TEKTRONIX, INC., Jan. 14, 2025.
Accessed: Jan. 14, 2025. [Online].
Available: https://shorturl.at/X0UvL

[19] A. Gaito, R. Scollo, G. Panebianco, and A. Raciti, 'Impact of the source-path parasitic inductance on the MOSFET commutations', in 2012 IEEE Energy Conversion Congress and Exposition (ECCE), Raleigh, NC, USA: IEEE, Sep. 2012, pp. 1367-1373. doi: 10.1109/ECCE.2012.6342656.

[20] A. Paul, 'A Simple Low-Cost Gate Drive for Multiple SiC MOSFETs for Single-Switch Induction Heater', Oct. 05, 2023. doi: 10.36227/techrxiv.24230230.v1.

[21] W. Li, S. Mao, H. Liu, J. Fan, and K. Zeng, 'Current Uniformity Optimization of Multi-Chip SiC Module for High-Power Applications', presented at the 2022 IEEE International Power Electronics and Application Conference and Exposition (PEAC), Guangzhou, China: IEEE, Nov. 2022, pp. 545-550. doi: 10.1109/PEAC56338.2022.9959680.

[22] M. Billmann, 'Coaxial Shunts T&M RESEARCH PRODUCTS'. Ing. Büro M.Billmann, Apr. 2013. Accessed: Jan. 18, 2025. [Online]. Available: https://shorturl.at/6cPiD

[23] 'Passive Voltage Probes'. TEKTRONIX, INC. Accessed: Jan. 18, 2025. [Online]. Available: https://shorturl.at/URZ1K

[24] [1] 'PMK - BumbleBee® Serie, bis 500MHz, bis ±2000V'. PMK Mess- und Kommunikationstechnik GmbH. Accessed: Jan. 18, 2025. [Online]. Available: https://shorturl.at/Sw47Z

[25] 'ImageIR®5300 - High-speed Thermography Camera with Large Pitch'. InfraTec GmbH, 2021. [Online]. Available: https://shorturl.at/3xbO6