# Systematic Design Methodology for Optimization of Voltage Comparators in CMOS Technology

João Xavier, Pedro Barquinha, João Goes

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João Xavier, Pedro Barquinha, João Goes. Systematic Design Methodology for Optimization of Voltage Comparators in CMOS Technology. 14th Doctoral Conference on Computing, Electrical and Industrial Systems (DoCEIS), Jul 2023, Monte Da Caparica, Portugal. pp.279-289, 10.1007/978-3-031-36007-7_21. hal-05473095

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# Systematic Design Methodology for Optimization of Voltage Comparators in CMOS Technology

João Xavier<fnref n="1" />,<fnref n="2" />(✉), Pedro Barquinha<fnref n="2" />, and João Goes<fnref n="1" />

**Abstract.** The increasing rate of digitalization and the growing use of the Internet-of-Things translate into a rise in demand for sensor-to-digital interface circuits and electronics for processing information. This demand increases the need for a standard workflow, which allows a straightforward comparison between active building-blocks (both amplifiers and comparators) with different architectures. Although comparators are essential building-blocks in many circuit architectures, there is no standard workflow to simulate and compare different circuit topologies. This paper proposes a systematic design workflow to simulate dynamic voltage comparators. The workflow consists of the “testbenches” and a simulation setup for extracting key parameters of comparator performance, such as static-offset, random-offset, worst-case comparison-time for both hard and soft decisions, power dissipation, and input-referred noise. As an example, this paper implements the methodology in Virtuoso environment and presents results for different dynamic comparators in a 28-nm standard bulk-CMOS technology.

**Keywords:** Dynamic Comparators · Comparator Testbench · Simulation
Workflow

## 1 Introduction

The increasing rate of digitalization and the growing use of the Internet-of-Things (IoT) have led to a significant increase in the demand for sensors and sensor-to-digital interfaces. IoT relies on a vast network of sensors that are capable of collecting data from various sources, communicating with each other and other systems. These sensors are used in a wide range of applications, such as environmental monitoring, smart homes, industrial automation, and healthcare. To process and make sense of the data collected by these sensors, sensor-to-digital interfaces are required. These interfaces convert the analog signals generated by the sensors into digital signals, that can be processed by

<footnote n="1">¹ Nova University of Lisbon, School of Science and Technology, UNINOVA – CTS and LASI, Lisbon, Caparica, Portugal
jpg.xavier@campus.fct.unl.pt, goes@fct.unl.pt</footnote>

<footnote n="2">² I3N/CENIMAT, Department of Materials Science, NOVA School of Science and Technology, Lisbon, Caparica, Portugal
pmcb@fct.unl.pt</footnote>
digital circuits and systems. This conversion process is crucial to ensure accurate and reliable data analysis. Voltage comparators, as a key building block of these interfaces, play a critical role in meeting these requirements. By accurately comparing two input voltages, voltage comparators enable the detection and conversion of analog signals to digital signals with high precision and speed [1, 2].

The performance of a voltage comparator, which is critical for the overall performance of the integrated circuit, is determined by the following design parameters: input offset, speed, power consumption, metastability, and input-referred electronic noise [3, 4]. These parameters are affected by various factors, including transistor size, process variations, and temperature changes. Therefore, designing and optimizing a voltage comparator requires a thorough understanding of its operation and performance characteristics [5].

This paper describes a characterization under simulation environment of dynamic comparators, focusing mainly on key parameters such as the offset and comparation time. The comparator's operation will be briefly explained in Sect. 3, as well as the influence of its key parameters. In Sect. 4, it will be described the simulation methodology used to evaluate the performance of the comparator and extracted its key parameters. In Sect. 5, it will be presented the simulation results and discussed the impact of key design parameters on the comparator's performance. Finally, in Sect. 6, it will be summarized the findings and provided conclusions.

## 2 Connected Cyber Physical Spaces

Connected cyber physical spaces are the result of combining the digital and physical worlds. They can be found in a variety of applications, including smart homes, smart cities, and smart factories. In a smart home, for example, sensors and devices can be used to monitor and control temperature, lighting, security, and other systems. Similarly, in a smart city, data from sensors and other sources can be used to optimize traffic flow, manage energy usage, and enhance public safety. In a smart factory, cyber-physical systems can be used to optimize production processes, reduce downtime, and increase efficiency. Overall, cyber-physical spaces have the potential to transform how we live, work, and interact with the world around us.

Integrated electronics play a crucial role in the development and operation of cyber-physical spaces, making it possible to collect, process, and exchange data in real-time. As the interface between the physical and digital worlds, analog-to-digital converters (ADCs) are an essential component of these integrated electronics. To meet the increasing requirements of ADCs, it is crucial to improve and optimize the performance of building blocks, such as comparators. This work describes a characterization of dynamic comparators under simulation environment, making it possible to create a standard workflow to design these essential components.

## 3 Operation and Key Parameters

A comparator senses a differential input and generates a logical output according to the polarity of the input difference [3, 4]. Most of today's applications use dynamic, or clocked, comparators, since it allows for low power dissipation, as they do not have
static consumption [6]. Most dynamic voltage comparators consist of a pre-amplifier and a latch. For example, strongarm latch combines both in a single stage [7]. In [8] is presented a dynamic comparator, however, in this case, a sense amplifier is used as a pre-amplifier. More complex topologies are also implemented, as in [9], where it is presented a triple tail comparator, using cascaded latches and feed-forward paths. Despite these differences in architecture, dynamic comparators present the same working principle. In short, when the clock signal goes high, the comparator makes a decision. Some operation parameters can be defined, such as the time that the comparator needs to make a decision, the minimum input voltage that the comparator is able to distinguish, and power consumption. These key parameters will be analyzed in this chapter.

## 3.1 Comparison Time

The time required for the comparator to make a decision is labeled comparison time. It consists of the time delay between the clock signal going high and the comparator making the decision. It is one of the most important parameters in a comparator, since it can limit its application.

It can be measured in different ways. One of the ways is to measure the time duration from the beginning of the comparison phase (reset is released when the appropriate clock edge reaches typically 50% of $V_{DD}$) until a valid logical voltage level is available at the output. A more faithful way to measure it is to wait until the appropriate clock edge and the logical level output both reach 90% of $V_{DD}$. It will present a higher value, however, it guarantees that the following circuit reads it as a high value [4, 6].

The comparator must compare the signal during one clock cycle and provide a stable output before the next cycle. The speed of the comparator depends on its input voltage difference, as the difference between input voltages gets smaller, the slower the comparison will be, ultimately requiring a metastability analysis [6].

## 3.2 Offset Voltage

The offset voltage can be seen as the sensitivity of the comparator, it defines the minimum voltage for which the comparator makes a reliable decision. This is the input voltage difference required to make the output change from low to high or vice versa [4]. If the input voltages have a voltage difference smaller than that of the offset voltage, it will not be able to make a trustworthy decision. This offset voltage is caused due to mismatch in the manufacturing process of the transistors. Due to this non-ideality, the input pairs are not entirely identical and will therefore have slightly different threshold voltages. This will mean that their behavior is not exactly the same, which will result in an offset in the input pairs. When the voltage is exactly the same on the gates of the input transistors, one will draw a somewhat larger current and the corresponding drain node will move faster and give an output that might not be correct. Other transistors than the input pairs will also contribute to the offset, but in general, the input pairs are the most dominant source to offset due to a large gain from the input pairs before other transistors activate [6].
The offset voltage can be divided into two values: the systematic offset and the random offset. The systematic offset is the offset that is always present in the comparator. The random offset is caused by mismatch in transistor sizes, deviation from ideal symmetrical circuit structure, and other non-idealities.

### 3.3 Power Dissipation

A further important parameter to characterize a clocked regenerative comparator is its power dissipation. It is the amount of power consumed by the comparator during operation. It is an important parameter in low-power applications and can be minimized by optimizing the circuit design. Typically, it consists of a static and a dynamic part, which depends on the clock frequency and the capacitances, which have to be charged and discharged [4]. As in almost every electronic design, low power consumption is desired. One significant advantage of the dynamic latched comparator compared to the pre-amplified based comparator is that it does not consume any static power, if leakage currents are neglected [6].

### 3.4 Trade-Offs Between Performance Parameters

Before starting an optimization, it is important to set the specifications for the comparator, especially the critical ones that absolutely need to be reached. In general, there are trade-offs between the key parameters of a voltage comparator. For example, a high gain comparator may have a longer comparison time due to the need for multiple amplification stages. Similarly, increasing the gain of the comparator may lead to an increase in power consumption. Another trade-off is between speed and accuracy, where increasing the speed of the comparator may result in a decrease in the accuracy of the output. There are also trade-offs between power consumption and noise performance, where increasing the power may result in lower noise levels but higher power dissipation. In addition, there can be trade-offs between noise and speed, where increasing the speed of the comparator may result in higher noise levels. So, it is important to carefully consider these trade-offs and select the parameters that are most important for the specific application to optimize the overall performance of the comparator.

## 4 Testbench Setup

The testbench can be represented by the following figure, Fig. 1. It consists of a dynamic comparator which requires a clock signal, Clk. In the comparator's input there is a reference voltage, $V_{ref}$, and a stimulus voltage, $V_{in}$. Depending on the analysis, the waveform of the stimulus voltage can be different. Regarding the reference voltage, in this case, a DC value was applied. However, instead of using a DC reference voltage, a differential input signal can be used, which will not affect the comparator's operation, since it only relies on the voltage difference between both inputs.

The comparator separates the analog signals, at the input, from the digital signals, at the output. Depending on the logic structure, it might be necessary for the output to be connected to several logic gates. This action might overload the comparator's output
stage, making it slower and power hungry. In order to avoid this, it is recommended to employ a digital buffer. This digital buffer consists of a cascade of two inverters. The first inverter must be a minimum size inverter, as it will relieve the load of the comparator's output stage. The smaller the size, the faster the output stage will be and less current will be consumed. If a high fanout is necessary, the size of the second inverter can be increased. In Fig. 1, the load consists of a minimum size inverter followed by a two-time minimum size inverter.

Values such as the clock frequency and the reference voltage depend on the compara-
tor's characteristics, application, and technology used, among others. In this case, the
reference voltage was defined as 450 mV, and the clock frequency is 1 GHz. In order to
start the study, from this point on, it is necessary to set the above-mentioned comparator's
desired specifications, such as the offset, comparison time, power consumption.

<figure><img src="image_3.png" /><figcaption>**Fig. 1.** Comparator Testbench. On the left of the comparator is presented the input signal. On the right is presented the digital buffer as the comparator's load.</figcaption></figure>

**4.1 Comparison Time**

In order to measure the comparison time, Fig. 2 shows a sequence of the different
decisions that the comparator will make. The input voltage, or stimulus voltage, will
alternate between four levels, which will present “easy” and “difficult” decisions. These
levels were defined as easy high, easy low, difficult high, difficult low. They are so
called due to the voltage difference that they will force onto the comparator’s input. For
example, the easy high level is defined as a bigger voltage difference, when compared
to the reference voltage, while the difficult high level is defined as a smaller voltage
difference, when compared to the reference voltage. These values will depend on the
comparator’s application [3, 4].

The sequence presented in Fig. 2 was created in such a way to force the comparator
to make decisions between all these levels. Alternating between these different levels
has several advantages when it comes to the comparator’s behavior analysis. All these
different combinations of transaction between levels will allow us to infer if the com-
parator suffers from memory effects, that is, if the previous decision has influence on
the next decision.
In order to properly evaluate the comparison time, it is necessary to simulate PVT corners and extract the longest time, in other words, the worst-case scenario comparison time.

<figure><img src="image_4.png" /><figcaption>**Fig. 2.** Input wave for comparison time simulation, representing the difficult and easy decisions.</figcaption></figure>

In Fig. 3 is represented a close-up of a clock signal when the comparator is making a decision. As explained before, this time will be better measured by subtracting the time when the clock signal reaches 90% of V<sub>DD</sub> to the time when the comparator's output reaches 90% of V<sub>DD</sub>.

<figure><img src="image_5.png" /><figcaption>**Fig. 3.** Comparison time measured at 90% V<sub>DD</sub>.</figcaption></figure>
## 4.2 Offset

To analyze the comparator's offset it is necessary to have a static wave at the input, with a frequency much lower than the frequency of the clock. It is recommended to use a wave amplitude as small as possible, since it will reduce the measurement error. As presented in Fig. 4, a half-period triangular wave can be applied in one input, in such a way that it is possible to observe both transition moments, rise and fall, and the reference voltage in the other one.

In the start of the analysis is normal to have a high offset value or to don't know the offset value, so it is recommended to start with a higher amplitude value and reduce as you go along testing.

<figure><img src="image_6.png" /><figcaption>Fig. 4. Input wave for offset voltage simulation.</figcaption></figure>

The offset can be separated into static offset and random offset. In simulation environment the static offset must be very close to zero, a value in the order of μV is acceptable. To measure the random offset, it is necessary to run Monte Carlo simulations, because it is this simulation that takes into consideration the mismatch of the devices.

Figure 5 shows how to extract the offset value. The first value to extract is the exact moment the output value is higher than VDD/2. This is the moment the comparator makes its decision; it is the time of the first clock cycle where the stimulus voltage is higher than the reference voltage. The offset value can then be obtained by subtracting the reference voltage value to the stimulus voltage value at that exact moment obtained. The described process should be performed using the simulator tools, such as the calculator.

In order to get a complete evaluation of the offset voltage, it is necessary to simulate Monte Carlo analysis across PVT corners. To have statistical importance a minimum of 200 samples is required.
<figure><img src="image_7.png" /><figcaption>**Fig. 5.** Representation of a close-up of the moment Vin is higher than V<sub>REF</sub> and the comparator makes its decision, and how to measure the offset.</figcaption></figure>

## 4.3 Power Dissipation

Power dissipation is measured by multiplying the supply voltage by the Root Mean Square, RMS, of the current drain from the supply. These values can be obtained by either the comparison time or the offset voltage simulation. However, taking a closer look into the comparison time simulation presented in this paper, as explained before, different levels of decision are considered, easy or difficult decisions. These different decisions consume different amounts of current, which, as a consequence, will lead to different values of power dissipation: if a decision takes a longer time to be made, more power dissipation will occur, and vice versa. So, it is recommended to extract the power dissipation from these values presented in the comparison time simulation, as it will give a better idea of the range of power dissipation presented by the comparator.

To perform a complete power analysis may be important to separate the analog power consumption, associated to the pre-amplifier, and the digital power consumption, related to the latch. This gives an idea of which domain is more power hungry and can be important when designing the supply buffers.

# 5 Simulation Results

This section is going to put into practice the above-described simulation approach. To illustrate the analysis, two different topologies of dynamic comparators are going to be analyzed. Both double tail topologies, however, the difference is the latch used in each one of them: one is implemented with the latch presented in [8] and [10], we'll call it NMOS Latch, Fig. 6-(a); and the other is the latch presented in [11], we'll call it PMOS Latch, Fig. 6-(b). The way they work is essentially the same, however, the main
difference is that one of the topologies has an NMOS transistor as the input device, and
the other one has a PMOS transistor as the input device.

<figure><img src="image_8.png" /><figcaption>**Fig. 6.** Double-tail comparator schematic: (a) using NMOS Latch, adapted from [8]. (b) using PMOS Latch, adapted from [11].</figcaption></figure>

Regarding NMOS Latch, two different analyses will be presented. One will focus on optimizing the comparator's speed (NMOS-1), while the other will focus on decreasing the offset voltage (NMOS-2). For PMOS Latch, only one analysis will be performed, identical to the second approach of NMOS Latch, where it will focus on decreasing the offset voltage (PMOS). These analyses will work as an example of the utility if this optimization approach, since it will be applied to two different topologies, and two different parameter optimizations, within the same topology.

All the simulations have been carried out in a 28 nm standard bulk CMOS process, a V<sub>DD</sub> value of 0.9 V. and a clock frequency of 1 GHz, using Cadence Virtuoso environment. Regarding the comparison time simulation, as presented in Fig. 2, there should
be between 3 and 4 clock signal periods in each level. For the difficult decisions the difference between $V_{REF}$ and $V_{in}$ is 5 mV, and for the easy decisions this difference is 50 mV. Regarding the offset voltage simulations, the input signal frequency is 1 MHz, the amplitude is 5 mV, and for the Monte Carlo simulation, 200 runs were considered.

For PVT simulations, five process corners were considered, SS, FF, TT, SF, FS; voltage variation was considered ± 5% $V_{DD}$; and two corners of temperature, 0 and 85 °C.

It is important to note that the simulations are not independent from one another. They should be carried out at the same time because, for example, an alteration in the comparator's transistor sizing that might improve the offset might just increase the comparison time.

The results of the three analyses are summarized in the following table, Table 1.

<table><caption>**Table 1.** Simulation results for the three analyses: NMOS-1 focuses on optimizing the comparator's speed for a double-tail topology with an NMOS Latch; NMOS-2 focuses on decreasing the offset voltage, with the same topology as NMOS-1; and PMOS focuses on decreasing the offset voltage for a double-tail topology with an PMOS Latch.</caption><thead><tr><th></th><th></th><th></th><th>NMOS-1</th><th>NMOS-2</th><th>PMOS</th></tr></thead><tbody><tr><td rowspan="4">Offset</td><td rowspan="2">Systematic</td><td>Rise</td><td>1.78 μV</td><td>99.15 μV</td><td>97.41 μV</td></tr><tr><td>Fall</td><td>1.48 μV</td><td>64.87 μV</td><td>69.29 μV</td></tr><tr><td rowspan="2">Random</td><td>Rise</td><td>3.1 mV</td><td>2.8 mV</td><td>8.8 mV</td></tr><tr><td>Fall</td><td>3.2 mV</td><td>2.8 mV</td><td>8.8 mV</td></tr><tr><td rowspan="2">Comparison Time</td><td>Easy</td><td>19.08 ps</td><td>59.9 ps</td><td>83.4 ps</td></tr><tr><td>Hard</td><td>27.1 ps</td><td>67.2 ps</td><td>88.2 ps</td></tr><tr><td>Power</td><td></td><td></td><td>164.7 μW</td><td>32.62 μW</td><td>56.13 μW</td></tr></tbody></table>

By analyzing the results presented in Table 1, it is possible to note the difference between the values of these parameters for both the NMOS-1 and NMOS-2 simulations. For the first one, where speed was prioritized, it is presented an improvement of 60% when compared to NMOS-2. However, for the second simulation, where the offset was prioritized, a value of 2.8 mV was obtained. It doesn't show a great improvement when compared to NMOS-1, however, the power dissipation is five times lower, obtaining a value of 32.62 μW. Regarding PMOS, it shows worst results overall when compared to NMOS-2, since it presents a higher offset of 8.8 mV, a higher comparison time of 88.2 ps, and a power dissipation of 56.13 μW.

## 6 Conclusions

In this paper it was presented a testbench for standard comparison of dynamic voltage comparators, as well as an overview of dynamic comparators operation and key parameters, and a simulation setup for extracting key parameters of comparator performance,
such as static-offset, random-offset, worst-case comparison-time for both hard and soft decisions, and power dissipation.

As an example, this paper implemented the methodology in Virtuoso environment and presents results for different dynamic comparators in a 28-nm standard bulk-CMOS technology.

**Acknowledgments.** The authors acknowledge the Portuguese FCT program UIDB/00066/2020 and UIDP/00066/2020 for providing partial financial support for this work.

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