# Efficient Multi-rate Hybrid Continuous-Time/Discrete-Time Cascade 2-2 Sigma-Delta Modulators for Wideband Telecom

J. Gerardo García-Sánchez, José Rosa

► To cite this version:

J. Gerardo García-Sánchez, José Rosa. Efficient Multi-rate Hybrid Continuous-Time/Discrete-Time Cascade 2-2 Sigma-Delta Modulators for Wideband Telecom. 19th International Conference on Very Large Scale Integration (VLSISOC), Oct 2011, Hong Kong, China. pp.124-143, 10.1007/978-3-642-32770-4_8 . hal-01519763

HAL Id: hal-01519763

https://inria.hal.science/hal-01519763

Submitted on 9 May 2017

**HAL** is a multi-disciplinary open access archive for the deposit and dissemination of scientific research documents, whether they are published or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers.

L'archive ouverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d'enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

<figure><img src="image_1.png" /></figure>

Distributed under a Creative Commons Attribution 4.0 International License
Efficient Multi-rate Hybrid
Continuous-Time/Discrete-Time Cascade 2-2
Sigma-Delta Modulators for Wideband Telecom

J. Gerardo García-Sánchez and José M. de la Rosa*

Instituto de Microelectrónica de Sevilla, IMSE-CNM (CSIC/Universidad de Sevilla)
C/Américo Vespucio, 41092 Sevilla, Spain
{jggarcia,jrosa}@imse-cnm.csic.es
http://www.imse-cnm.csic.es/~jrosa

**Abstract.** This chapter discusses the use of hybrid continuous-time /discrete-time fourth-order cascade two-stage 2-2 ΣΔ modulators for wideband low-power wireless applications. The modulator architecture under study is based on a new concept of multi-rate operation, in which the front-end stage – implemented using continuous-time (Gm-C) integrators – operates at a higher rate than the back-end (switched-capacitor) stage. This strategy benefits from the faster operation of continuous-time circuits while keeping power efficiency and high robustness against circuit element tolerances. A comparison with conventional multi-rate and single-rate (continuous-time) ΣΔ modulators is carried out based on the impact of main circuit-level error mechanisms, namely: mismatch, finite OTA dc gain and finite gain-bandwidth product. Closed-form analytical expressions are derived for the nonideal in-band noise power of the different architectures under study, demonstrating a good agreement with simulations and showing the benefits of the presented approach. Simulation results show that the proposed modulator is able to operate with a maximum sampling rate of up to 1GHz, digitizing signals with a 44-to-92dB peak signal-to-(noise+distortion) ratio within a programmable 5-to-60MHz bandwidth.

**Key words:** Analog-to-digital conversion, multi-rate sigma-delta modulators, continuous-time and discrete-time circuits.

# 1 Introduction

In the last decade the number of wireless applications and operation modes have increased significantly, demanding higher and higher data rates in hand-held mobile devices. The efficient implementation of these multi-standard devices requires using power-efficient wideband Analog-to-Digital Converters (ADCs).

* This work has been supported by the Spanish Ministry of Science and Innovation (with support from the European Regional Development Fund) under contract TEC2010-14825/MIC, and the Consejería de Innovación, Ciencia y Empresa, Junta de Andalucía, under contract TIC-2532.
Among other ADC techniques, Sigma-Delta Modulators (ΣΔMs) implemented with Continuous-Time (CT) circuits have demonstrated to be a suited solution in these applications. Compared with Discrete-Time (DT) ΣΔMs – mostly implemented with Switched-Capacitor (SC) circuits – CT-ΣΔMs achieve faster rates with less power consumption. However, CT-ΣΔMs are more sensitive than DT-ΣΔMs to some circuit nonideal effects, mainly: clock jitter error and circuit element tolerances [1].

The mentioned limitations of CT-ΣΔMs has motivated exploring other alternative ΣΔM strategies like the so-called Hybrid CT/DT ΣΔMs (H-ΣΔMs). In these hybrid topologies some parts of the modulator – usually the front-end blocks – are implemented with CT circuits, thus benefiting from their faster operation, embedded anti-aliasing filtering and reduced power dissipation, while keeping a higher robustness against circuit errors than in pure CT-ΣΔMs [2–6].

The main drawback of H-ΣΔMs is that their sampling rate is indeed limited by the DT part of the system. For that reason, reported H-ΣΔM Integrated Circuits (ICs) did not really exploit the speed advantages of using CT circuits. A possible solution to palliate this limitation might be using a different sampling frequency for each part (either CT or DT) of the H-ΣΔM, i.e. using a *multi-rate* system [7]. This approach has been applied to both DT- [8] and CT-ΣΔMs [9]. However, in both cases, the strategy was based on using a lower OverSampling Ratio (OSR) in the front-end parts of the modulator – where most of the power is consumed – and a higher OSR in the subsequent stages or blocks – where the dynamic requirements can be relaxed. The same idea has been also applied to cascade H-ΣΔMs, by using double-sampling technique in order to implement the DT back-end stage of the modulator more efficiently [10].

In spite of their potential benefits, *conventional* Multi-Rate (MR) H-ΣΔMs are not feasible in practice when digitizing wideband signals, for instance in the order of 10-100 MHz. In these applications, the back-end SC stages of the modulator need to operate at unfeasible sampling rates (in the order of GHz) in order to achieve low-medium effective resolutions (8-10 bits). These specifications demand for prohibitive values of the Gain BandWidth (GBW) product required for the operational amplifiers [11]. These problems can be alleviated if the signal is *downsampled* across the cascade modulator, so that the CT front-end stage operates at a higher clock rate than the DT back-end stage. This way, the dynamic requirements of the corresponding SC integrators can be relaxed and the resulting effective resolution can be improved by properly combining the different OSRs in a multi-rate operation [12].

This chapter contributes to this topic and presents the high-level design of a multi-rate fourth-order cascade 2-2 H-ΣΔM, in which the CT (Gm-C) front-end stage uses a higher OSR than the SC back-end stage. The aliasing error derived from the downsampling operation can be attenuated in the digital domain so that no extra analog circuits are required as compared to conventional cascade ΣΔMs. Simulation results including all circuit-level error mechanisms show a correct operation of the circuit, demonstrating the feasibility of the presented
architectures for the implementation of wideband ADCs in wireless telecom systems.

The chapter is organized as follows. Section 2 overviews the basic principles underlying the operation of multi-rate cascade H-ΣΔMs, considering both the conventional upsampling approach and the proposed downsampling approach. The effect of circuit nonideality is analyzed in detail in Section 3, where closed-form expressions for the IBN degraded by several error mechanisms is obtained for all the architectures under study. As an application and case study, the presented analysis is applied to the systematic high-level synthesis of a fourth-order cascade GmC/SC H-ΣΔM, described in Section 4. Finally, simulation results are presented in Section 5 to demonstrate the potentiality of the presented approach.

## 2 ΣΔ Modulator Architectures Under Study

Fig. 1 shows the block diagram of the ΣΔMs under study, where $H(s) = 1/s$ and $H(z) = z^{-1}/(1 - z^{-1})$, denote the transfer functions of the CT and DT integrators, respectively. The same loop filter topology is used in all cases, consisting on a fourth-order cascade 2-stage (2-2) architecture, where the front-end stage includes feed-forward paths to implement a Unity Signal Transfer Function (USTF). Embedded multi-bit quantization is considered in both stages of the modulators. The circuit technique used to implement each stage, either CT or DT, as well as their corresponding sampling frequencies, $f_{si}$, are highlighted in the figure.

Three different topologies are considered attending to the sampling rate of each stage and its circuit nature, either CT or DT. Thus, Fig. 1(a) is a Single-Rate (SR) CT-ΣΔM, where both stages operate at the same sampling frequency, $f_s$. Fig. 1(b) is a conventional UpSampling (US) MR H-ΣΔM, where the back-end stage operates at a higher sampling frequency than the front-end stage, i.e. $f_{s2} = r \cdot f_{s1}$, where $r > 1$ denotes the upsampling ratio. The opposite operation is carried out in Fig. 1(c), which corresponds to a DownSampling (DS) MR H-ΣΔM, in which the front-end stage operates at the highest sampling rate, i.e. $f_{s1} = p \cdot f_{s2}$, with $p > 1$ being the downsampling ratio.

### 2.1 Quantization Noise Transfer Function

The analysis of the modulators in Fig. 1 can be carried out in the Z-domain by applying a CT-to-DT transformation to the CT stages. The resulting DT-ΣΔMs are equivalent to the original architectures. This CT-to-DT equivalence can be guaranteed because of the DT nature of the (open) loop transfer function from the quantizer output to the sampled quantizer input [1, 13]. Thus, assuming a linear model for the quantizers in Fig. 1(a)-(b), it can be shown that the quantization Noise Transfer Function (NTF) at the output of both modulators are respectively given by:

$$ \text{NTF}_{\text{SR}}(z) = (1 - z^{-1})^{(L_1+L_2)} \quad (1) $$
<figure><img src="image_2.png" /><figcaption>Fig. 1. Block diagram of the cascade 2-2 ΣΔMs under study: (a) SR CT-ΣΔM, (b) US MR H-ΣΔM, (c) DS MR-ΣΔM.</figcaption></figure>
$$NTF_{US}(z) = (1 - z^{-r})^{L_1} (1 - z^{-1})^{L_2} \quad (2)$$

where $L_1 = 2$ and $L_2 = 2$ stand for the order of the front-end and the back-end stages of the modulators, respectively.

In contrast to the conventional US MR H-ΣΔM of Fig. 1(b), the back-end (DT) stage of the DS MR H-ΣΔM shown in Fig. 1(c) operates at a lower rate than the front-end (CT) stage, i.e $f_{s2} < f_{s1}$. Therefore, the quantization error signal, $E_1(z)$, that is fed to the back-end stage, is downsampled, thus containing aliased components at multiples of $f_{s2}$. This can be expressed in the Z-domain as [12]:

$$E_{1,AL}(z) = \frac{1}{p} \sum_{k=0}^{p-1} E_1(z^{1/p} e^{j(2\pi k/p)}) \quad (3)$$

Note that $E_{1,AL}(z)$ is indeed an error signal, that contains the quantization error, $E_1(z)$, and its aliased components. Therefore, $E_{1,AL}(z)$ can be also cancelled out by the Digital Cancellation Logic (DCL) transfer functions. To this purpose, the digital functions $H_1(z)$ and $H_2(z)$ in Fig. 1(c) are used. These functions must be reconfigurable and programmable according to the value of $p$.

Assuming a linear model for the quantizers in Fig. 1(c), it can be shown that both $E_1(z)$ and its aliased error components can be completely cancelled out if $H_1(z)$ and $H_2(z)$ are given by the following expression:

$$H_1(z) = H_2(z) = \left( \sum_{k=0}^{p-1} z^{-k} \right)^{L_1} \quad (4)$$

Taking into account the above expression, it can be shown that the NTF of Fig. 1(c) can be written as:

$$NTF_{DS}(z) = (1 - z^{-1})^{L_1} (1 - z^{-p})^{L_2} \quad (5)$$

As an illustration, Fig. 2 shows the output spectra of the modulators in Fig. 1 for different cases of $r$ and $p$, showing the variation of the notch frequency caused by the multi-rate operation.

## 2.2 In-band Quantization Noise Power

Integrating the expressions (1), (2) and (5) within the signal bandwidth, $B_w$, it can be shown that the In-Band Noise (IBN) power at the output of the modulators in Fig. 1(a)-(c) are respectively given by [1, 12]:

$$IBN_{SR}^{ideal} \approx \frac{\Delta^2 \pi^{2L}}{12(2L + 1)OSR^{2L+1}} \quad (6)$$

$$IBN_{US}^{ideal} \approx \frac{\Delta^2 \pi^{2L} r^{2L_1}}{12(2L + 1)OSR_{2US}^{2L+1}} \quad (7)$$
$$ \mathrm{IBN}_{\mathrm{DS}}^{\mathrm{ideal}} \approx \frac{\Delta^2 \pi^{2L} p^{2L_2}}{12(2L+1)\mathrm{OSR}_{1\mathrm{DS}}^{2L+1}} \qquad (8) $$

where $\Delta$ stands for the quantization step of the last quantizer; $L = L_1 + L_2 = 4$ is the loop-filter order of the $\Sigma\Delta$Ms in Fig. 1; $\mathrm{OSR}_{\mathrm{SR}} \equiv f_s/(2B_w)$ is the OSR of the SR CT-$\Sigma\Delta$M [Fig. 1(a)], and $\mathrm{OSR}_{2\mathrm{US}} \equiv f_{s2}/(2B_w)$ and $\mathrm{OSR}_{1\mathrm{DS}} \equiv f_{s1}/(2B_w)$ denote the value of the largest OSR in the US MR H-$\Sigma\Delta$M [Fig. 1(b)] and DS MR H-$\Sigma\Delta$M [Fig. 1(c)], respectively. It can be noted that the expressions in (7) and (8) reduce to the one obtained by conventional single-rate (SR) $\Sigma\Delta$Ms, shown in (6), provided that $r = p = 1$ and $\mathrm{OSR}_{2\mathrm{US}} = \mathrm{OSR}_{1\mathrm{DS}} = \mathrm{OSR}_{\mathrm{SR}}$, where $\mathrm{OSR}_{\mathrm{SR}}$ denotes the OSR of the SR modulator. Note also that the same ideal IBN can be achieved by all $\Sigma\Delta$Ms in Fig. 1, by properly choosing the values of $r, p, \mathrm{OSR}_{\mathrm{SR}}, \mathrm{OSR}_{2\mathrm{US}}$ and $\mathrm{OSR}_{1\mathrm{DS}}$.

<figure><img src="image_3.png" /></figure>

<figure><img src="image_4.png" /><figcaption>Fig. 2. Output spectra of the $\Sigma\Delta$Ms under study for: (a) $r = p = 2$, (b) $r = p = 4$.</figcaption></figure>
As an illustration, Fig. 3 depicts the Signal-to-Noise Ratio (SNR) versus OSR<sub>1DS</sub> for different values of *r* and *p*, showing a good agreement between theory and simulations within a wide resolution range.

<figure><img src="image_5.png" /><figcaption>Fig. 3. SNR vs. OSR<sub>1DS</sub> for different values of *r* and *p*.</figcaption></figure>

3 Performance degradation due to circuit errors

The analysis described in previous section assumed that the ΣΔMs in Fig. 1 were
implemented with ideal building blocks. However, in practice, the noise shaping
(and consequently the effective resolution) of these modulators is degraded by the
action of circuit-level errors. This section analyses the IBN degradation caused
by three of the most critical nonideal effects, namely: mismatch error, finite
dc gain of the finite Operational Transconductance Amplifier (OTA) and Gain-
BandWidth (GBW) product. To this end, it will be assumed that the DT and
CT integrators in ΣΔMs in Fig. 1 are implemented by Forward-Euler (FE)
Switched-Capacitor (SC) integrators and Gm-C integrators, respectively.

**3.1 Integrators’ Weight Error**

Let us assume that the integrators in Fig. 1 have a weight error caused by
technology process variations. In the case of SC FE integrators, this gain error,
denoted as ϵ<sub>DT</sub>, is caused by the capacitor mismatch and it is modeled as a
random deviation of the integrator’s weight, i.e. the ratio between the sampling
capacitor and the integrator capacitor [14]. In the case of Gm-C integrators,
the weight error, ϵ<sub>CT</sub>, is due to random variations of the time constant, i.e. the
transconductance-capacitor product [1].

Considering the effect of ϵ<sub>DT</sub> and ϵ<sub>CT</sub> the integrator transfer functions in
Fig. 1, H(z) and H(s), become degraded by the action of errors ϵ<sub>DT</sub> and ϵ<sub>CT</sub>,
respectively [14, 1]. The effect of this error can be propagated through the modulator in order to obtain the nonideal NTF and IBN. Following this systematic procedure, it can be shown that the IBN power at the output of the ΣΔMs in Fig. 1(a)-(c) can be respectively approximated by:

$$ \mathrm{IBN}_{\mathrm{SR}}^{\mathrm{mis}} \approx (1 + \epsilon_{\mathrm{CT}})^2 \cdot \mathrm{IBN}_{\mathrm{SR}}^{\mathrm{ideal}} + \frac{\Delta_1^2 \pi^{2L_1} \epsilon_{\mathrm{CT1}}^2}{12(2L_1 + 1)\mathrm{OSR}_{\mathrm{SR}}^{2L_1+1}} \quad (9) $$

$$ \mathrm{IBN}_{\mathrm{US}}^{\mathrm{mis}} \approx (1 + \epsilon_{\mathrm{DT}})^2 \cdot \mathrm{IBN}_{\mathrm{US}}^{\mathrm{ideal}} + \frac{\Delta_1^2 \pi^{2L_1} \epsilon_{\mathrm{CT1}}^2 r^{2L_1+1}}{12(2L_1 + 1)\mathrm{OSR}_{\mathrm{2US}}^{2L_1+1}} \quad (10) $$

$$ \mathrm{IBN}_{\mathrm{DS}}^{\mathrm{mis}} \approx (1 + \epsilon_{\mathrm{DT}})^2 \cdot \mathrm{IBN}_{\mathrm{DS}}^{\mathrm{ideal}} + \frac{\Delta_1^2 \pi^{2L_1}}{12(2L_1 + 1)\mathrm{OSR}_{\mathrm{1DS}}^{2L_1+1}} \cdot \sum_{k=0}^{p-1} \left| \alpha(k) \epsilon_{\mathrm{CT11}} + \frac{\beta(k)}{2} \epsilon_{\mathrm{CT12}} \right|^2 \quad (11) $$

where $\Delta_1$ stands for the quantization step of the front-end quantizer in Fig. 1; $\epsilon_{\mathrm{CTij}}$ denote the weight error of the j-th Gm-C integrator in the i-th stage $(i, j = 1, 2)$; and $\alpha(k)$ and $\beta(k)$ are respectively given by:

$$ \alpha(k) = (2e^{-j2\pi k/p} - e^{-j4\pi k/p}) \quad (12) $$
$$ \beta(k) = (e^{-j2\pi k/p} + e^{-j4\pi k/p}) $$

In order to verify the theoretical expressions given in (9)-(11), the ΣΔMs under study were simulated using SIMSIDES – a time-domain behavioral simulator for ΣΔMs [15]. To make a fair comparison, the same ideal conditions, i.e. $r = p$ were assumed, and the values of the OSR for each modulator were computed from (6), (7) and (8), so that the same ideal IBN is achieved in all cases. The same embedded quantizers were used in all ΣΔMs, considering 4-bit quantization in both stages. Two values of signal bandwidths were simulated, $B_w = 20, 40$ and a 1-MHz input tone with amplitude –7dB below quantization full-scale range was applied in all cases. For the sake of simplicity, only the effect of errors associated to the front-end (CT) integrators – which are common in both ΣΔM architectures in Fig. 1 – have been taken into account in the simulations.

Fig. 4 shows the effect of circuit element tolerances in the time constant of the front-end Gm-C integrator. It can be noted how both theoretical calculations and simulations demonstrate that the DS MR H-ΣΔM achieves the largest robustness against mismatches, getting better as both $p$ and $B_w$ increase.

## 3.2 Finite OTA dc Gain Error

Let us consider now that the integrators in Fig. 1 have a finite OTA dc gain. This effect can be modeled as a finite dc gain of the opamp in SC integrators [14] and as a finite output resistance of the transconductor circuit in Gm-C [1].
<figure><img src="image_6.png" /><figcaption>Fig. 4. IBN vs. integrator’s weight error for: (a) $B_w=20$MHz and (b) $B_w=40$MHz.</figcaption></figure>

Thus, taking into account this effect on the integrators’ transfer functions, it can be demonstrated that the IBN at the output of the modulators in Fig. 1(a)-(c) are respectively given by:

$$ \text{IBN}_{\text{SR}}^{\text{gain}} \approx \left[ 1 + \frac{2L+1}{2L-1} \cdot \left( \frac{\mu_2 \cdot \text{OSR}_{\text{SR}}}{\pi} \right)^2 \right] \cdot \text{IBN}_{\text{SR}}^{\text{ideal}} + \frac{\Delta_1^2 \pi^{2L_1-2} \mu_1^2}{12 \cdot (2L_1-1) \cdot \text{OSR}_{\text{SR}}^{2L_1-1}} \quad (13) $$

$$ \text{IBN}_{\text{US}}^{\text{gain}} \approx \left[ 1 + \frac{2L+1}{2L-1} \cdot \left( \frac{\mu_2 \cdot \text{OSR}_{2\text{US}}}{\pi} \right)^2 \right] \cdot \text{IBN}_{\text{US}}^{\text{ideal}} + \frac{\Delta_1^2 \pi^{2L_1-2} \mu_1^2 r^{2L_1-1}}{12 \cdot (2L_1-1) \cdot \text{OSR}_{2\text{US}}^{2L_1-1}} \quad (14) $$
$$ \mathrm{IBN}_{\mathrm{DS}}^{\mathrm{gain}} \approx \left[ 1 + \frac{2L+1}{2L-1} \cdot \left( \frac{\mu_2 \cdot \mathrm{OSR}_{1_{\mathrm{DS}}}}{\pi p} \right)^2 \right] \cdot \mathrm{IBN}_{\mathrm{DS}}^{\mathrm{ideal}} + \frac{\Delta_1^2 \pi^{2L_1-2} \mu_1^2 p^{2L_1-1}}{12 \cdot (2L_1-1) \cdot \mathrm{OSR}_{1_{\mathrm{DS}}}^{2L_1-1}} \quad (15) $$

where $\mu_i \equiv 1/A_{dc1} + 1/A_{dc2}$ and $A_{dcij}$ stand for the finite OTA dc gain of the j-th integrator in the i-th stage of Fig. 1.

As an illustration, Fig. 5 shows the impact of finite dc gain error of the first Gm-C integrator for the $\Sigma\Delta$Ms under study. Note that both theoretical predictions and simulation results are in good agreement, showing that the DS MR H-$\Sigma\Delta$M is less sensitive to the impact of this error, regardless the value of $r$, $p$ and $B_w$.

<figure><img src="image_7.png" /></figure>

<figure><img src="image_8.png" /><figcaption>Fig. 5. IBN vs. finite OTA dc gain for: (a) $B_w$=20MHz and (b) $B_w$=40MHz.</figcaption></figure>
### 3.3 Finite GBW Error

Following the same procedure as in previous sections, it can be found that the IBN degradation caused by the effect of the integrators GBW can be modeled by replacing the expressions of $\epsilon_{CTij}$ and $\epsilon_{DTij}$ in (9)-(11) by the following expressions:

$$ \epsilon_{CTij} \equiv \frac{f_s}{\text{GBW}_{ij}}; \epsilon_{DTij} \equiv e^{\frac{-\pi \text{GBW}_{ij}}{f_s}} \quad (16) $$

where GBW$_{ij}$ is the value of GBW for the j-th integrator in the i-th stage.

The impact of GBW is illustrated in Fig. 6, highlighting a good matching between theory and simulations. A worse performance of the US MR H-ΣΔM is obtained, while a similar degradation is roughly obtained for the DS MR H-ΣΔM and the SR CT-ΣΔM. Indeed, the latter achieves a higher robustness against the impact of GBW in the first integrator.

<figure><img src="image_9.png" /></figure>

<figure><img src="image_10.png" /><figcaption>Fig. 6. IBN vs. GBW for: (a) $B_w=20$MHz and (b) $B_w=40$MHz.</figcaption></figure>
## 4 Case study: A Gm-C/SC Cascade 2-2 DS MR H-ΣΔM

As a case study, Fig. 7 shows a conceptual schematic of the modulator in Fig. 1(c). The front-end (CT) stage is realized using Gm-C integrators. All transconductors can be tuned in order to keep the time constants, $C/g_m$, unchanged over $C$ variations. Table 1 shows the values of nominal loop filter transconductances, $g_{mi}$ (expressed in terms of the unitary transconductance, $g_{mu}$) as well as the capacitances, $C_i$, used to realize both Gm-C and SC integrators.

<figure><img src="image_11.png" /><figcaption>Fig. 7. Conceptual Gm-C/SC schematic of the modulator in Fig. 1(c).</figcaption></figure>
Note that an extra feedback branch between the output and the input of the front-end quantizer and two additional D-latches are included in order to compensate for the excess loop delay [1]. This extra branch forces modifying the loop filter coefficients in order to obtain the ideal NTF given in (5). The back-end (DT) stage – realized with SC circuits – is a conventional second-order topology based on two feedback paths. Both stages include multi-level quantizers – 3-level in the front-end stage and 5-level in the back-end stage – in order to benefit from the extra level provided by fully differential implementation of the embedded flash ADCs.

The Full-Scale (FS) reference voltage, $V_{FS}$, is 1V. Feedback DACs in the CT front-end stage are implemented as current steering Non-Return-to-Zero (NRZ) 3-level DACs (named IDACs in Fig. 7) because of their potential high-speed operation and the convenience to interface with the Gm-C loop filter. The output currents provided by both IDACs are also shown in Table 1. An additional voltage-mode 3-level DAC, named VDAC in Fig. 7, is required in the inter-stage path. The digital cancellation logic is implemented as described in Section 2.

Fig. 8 shows the output spectra of the modulator in Fig. 7 for different values of $p$, considering a sampling frequency of the front-end stage of $f_{s1} = 1$GHz and including thermal noise corresponding to $g_{mu} = 75\mu A/V$. Ideally, the modulator is able to digitize signals with $B_w$ from 5MHz to 60MHz and an effective resolution ranging from 9 to 16 bits. According to (8), these specifications can be satisfied for $OSR_1 \in [8, 128]$ and $p = [2, 3, 4, 5, 6]$. This is illustrated in Fig. 9 that represents IBN vs. $B_w$ (Fig. 9(a)) and IBN vs. $OSR_1$ (Fig. 9(b)) for different values of $p$. In this case, three values of $f_{s1}$ are considered, $f_{s1} = 1$GHz, 500MHz and 333MHz. The values of the Gm-C integration capacitors, $C_{1,2}$ are changed according to the expressions shown in Table 1, by using a switchable bank of three unit capacitances of value $C_u=1.2pF$. The sampling frequency of the SC back-end stage can be reconfigured through a programmable clock-phase generator$^1$, such that $f_{s2} = f_{s1}/p$. Both clock-phase generators are synthesized and controlled by a single master clock – generated by a digital PLL-based synthesizer whose reference frequency is $f_{s1}$. This is conceptually depicted in Fig. 10, where clock phases of both CT and SC stages are shown for different values of $p$.

# 5 Simulation Results

The modulator has been simulated using SIMSIDES [15], considering main circuit error mechanisms. Fig. 11 shows the effect of finite OTA dc gain of front-end integrators, given by $A_{vi} \equiv g_{mi}R_{oi}$, where $R_{oi}$ is the finite output resistance of the $i$-th Gm-C integrator. Note that $A_{v11,12} > 30$dB is enough to satisfy the required specifications. The effect of finite GBW of the front-end Gm-C integrator is illustrated in Fig. 12, considering $f_{s1} = 1$GHz and different values of $B_w$ and

<footnote n="1">¹ Note that in this modulator, $f_{s1} = p \cdot f_{s2}$.</footnote>
<figure><img src="image_12.png" /></figure>

<figure><img src="image_13.png" /></figure>

<figure><img src="image_14.png" /></figure>

<figure><img src="image_15.png" /><figcaption>Fig. 8. Output spectra for: (a) $p = 3$, (b) $p = 4$, (c) $p = 5$, (d) $p = 6$.</figcaption></figure>
<table><caption>Table 1. Loop filter coefficient implementation of Fig.7</caption><tr><td colspan="2">Transconductances</td></tr><tr><td>$g_{m1} = 4g_{mu}$, $g_{m2} = g_{mu}$, $g_{m3} = 10g_{mu}$, $g_{m4} = 4g_{mu}$, $g_{m5} = 16g_{mu}$</td><td></td></tr><tr><td colspan="2">Capacitances</td></tr><tr><td>Gm-C Integ.</td><td>$C_1 = g_{m1}/f_{s1}$, $C_2 = g_{m4}/f_{s1}$</td></tr><tr><td>SC Integ.</td><td>$C_{s1} = C_{s4} = 0.4\text{pF}$, $C_{s2} = C_{s3} = 0.1\text{pF}$, $C_{s5} = 0.2\text{pF}$, $C_{i1} = C_{i2} = 0.4\text{pF}$</td></tr><tr><td colspan="2">Voltage-to-Current Converters and Feedback DACs</td></tr><tr><td colspan="2">$R = 1/g_{m1} = 3.3\text{k}\Omega$, $I_{\text{DAC1}} = 4g_{mu}V_{\text{FS}}=300\mu\text{A}$, $I_{\text{DAC2}} = 2g_{mu}V_{\text{FS}}=150\mu\text{A}$</td></tr></table>

<figure><img src="image_16.png" /><figcaption>Fig. 9. IBN for different values of *p*: (a) IBN vs. $B_w$. (b) IBN vs. OSR₁.</figcaption></figure>
<figure><img src="image_17.png" /><figcaption>**Fig. 10.** Clock phase generator. (a) Conceptual block diagram. (b) Clock phases for different values of the multi-rate ratio.</figcaption></figure>

$p$. It is noted that – depending on the value of $p$ and $B_w$ – the required GBW may vary from 700MHz to 1.5GHz.

Fig. 13 illustrates the effect of circuit element tolerances in the CT part and capacitor mismatch in the DT part of the modulator, by showing an histogram of IBN for $B_w = 20$MHz and different values of $p$. In order to evaluate the impact of random circuit errors, a 250-sample Monte Carlo simulation was carried out, considering a standard deviation of 1% in the transconductances and 5% for the capacitors in the CT part of the circuit, while a 0.1% mismatch variation was considered for the SC stage. Note that the effective resolution degradation is similar to the one obtained in conventional cascade $\Sigma\Delta$Ms.

Table 2 sums up the modulator performance in terms of the maximum signal bandwidth, $B_{wmax}$, that can be handled for a given value of $p$, $f_{s1}$ and the Signal-to-(Noise+Distortion) Ratio (SNDR). The table includes also the circuit-level performance metrics required to achieve this modulator performance, including both nonideal and nonlinear effects, such as the input-referred third-order intercept point (IIP3). In the case of SC integrators, folded cascode operational amplifiers were considered and their electrical performance – extracted from transistor-level simulations carried out in Cadence Spectre – are also shown, considering a 1.2-V 90-nm CMOS technology.

The diverse range of specifications covered by the proposed modulator is illustrated in Fig. 14, that represents the SNDR vs. input amplitude for $f_{s1}$ =1GHz and considering different values of $B_w$ and $p$, taking into account all circuit non-ideal and nonlinear effects listed in Table 2. It can be noted that the modulator is able to cover a wide region in the resolution-vs-bandwidth plane.
<figure><img src="image_18.png" /><figcaption>Fig. 11. IBN degradation caused by finite OTA dc gain in (a) 1st and (b) 2nd Gm-C integrators.</figcaption></figure>

<figure><img src="image_19.png" /><figcaption>Fig. 12. IBN degradation due to GBW of the front-end Gm-C integrator.</figcaption></figure>
<figure><img src="image_20.png" /><figcaption>Fig. 13. Monte Carlo simulation for $f_{s1} = 1$GHz and $B_w = 20$MHz.</figcaption></figure>

<figure><img src="image_21.png" /><figcaption>Fig. 14. SNDR vs. amplitude for different values of $B_w$ and $p$.</figcaption></figure>
<table><caption>**Table 2.** Modulator Performance Summary</caption><thead><tr><th colspan="10">Modulator</th></tr><tr><th>p</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>(2,6)</th><th>2</th><th></th><th></th></tr></thead><tbody><tr><td>f<sub>s1</sub></td><td colspan="8">1GHz</td><td>500MHz</td><td>333MHz</td></tr><tr><td>B<sub>wmax</sub> (MHz)</td><td>60</td><td>50</td><td>40</td><td>30</td><td>25</td><td>20</td><td>5</td><td>10</td><td>5</td></tr><tr><td>SNDR (bits)</td><td>7</td><td>8.3</td><td>8.9</td><td>10</td><td>10.5</td><td>11.5</td><td>15</td><td>12.5</td><td>14.6</td></tr><tr><td>Clock Jitter (ps)</td><td>8.9</td><td>4</td><td>3</td><td>1.6</td><td>1.2</td><td>0.7</td><td>0.2</td><td>0.9</td><td>0.3</td></tr><tr><td colspan="10">Front-End Gm-C Integrator</td></tr><tr><td>DC Gain (dB)</td><td>20</td><td>20</td><td>20</td><td>25</td><td>25</td><td>30</td><td>40</td><td>35</td><td>40</td></tr><tr><td>GBW (GHz)</td><td>0.7</td><td>0.8</td><td>0.8</td><td>1</td><td>1.2</td><td>1.5</td><td>1.5</td><td>1.5</td><td>1.5</td></tr><tr><td>IIP3 (dBV)</td><td>10</td><td>13</td><td>15</td><td>18</td><td>20</td><td>25</td><td>35</td><td>30</td><td>35</td></tr><tr><td>Input Swing</td><td colspan="8">500mV</td><td></td><td></td></tr><tr><td>Output Swing</td><td colspan="8">500mV</td><td></td><td></td></tr><tr><td colspan="10">Second Gm-C Integrator and Loop-filter Transconductances</td></tr><tr><td>DC Gain (dB)</td><td>20</td><td>20</td><td>20</td><td>25</td><td>25</td><td>30</td><td>40</td><td>35</td><td>40</td></tr><tr><td>GBW (MHz)</td><td>200</td><td>250</td><td>250</td><td>300</td><td>350</td><td>400</td><td>500</td><td>450</td><td>500</td></tr><tr><td>IIP3 (dBV)</td><td>5</td><td>7</td><td>7</td><td>10</td><td>12</td><td>15</td><td>15</td><td>15</td><td>15</td></tr><tr><td>Input Swing</td><td colspan="8">500mV</td><td></td><td></td></tr><tr><td>Output Swing</td><td colspan="8">500mV</td><td></td><td></td></tr><tr><td colspan="10">SC Integrators (Transistor-Level Performance)</td></tr><tr><td>DC Gain (dB)</td><td colspan="8">47</td><td></td><td></td></tr><tr><td>g<sub>m</sub> (mA/V)</td><td colspan="8">4.4</td><td></td><td></td></tr><tr><td>Phase Margin</td><td colspan="8">73.4°</td><td></td><td></td></tr><tr><td>Output Current (μA)</td><td colspan="8">404</td><td></td><td></td></tr><tr><td>Input Parasitic Cap. (pF)</td><td colspan="8">0.2</td><td></td><td></td></tr><tr><td>Out. Parasitic Cap. (pF)</td><td colspan="8">0.1</td><td></td><td></td></tr><tr><td>Output Swing (mV)</td><td colspan="8">700</td><td></td><td></td></tr></tbody></table>

Conclusion

Different approaches for the implementation of multi-rate cascade hybrid CT/DT ΣΔ modulators have been discussed in this chapter. One of them increases the clock rate across the cascade while the other uses a lower oversampling ratio in the back-end stage. Both multi-rate cascade topologies have been compared to conventional single-rate cascade continuous-time ΣΔ modulators. The effect of main circuit errors has been theoretically analyzed and verified by time-domain simulations, demonstrating that the downsampling multi-rate architecture exploits the capability of continuous-time circuits to operate at higher frequencies with less power consumption, while keeping a higher robustness against circuit errors. These characteristics make these kinds of ΣΔMs very suited candidates for the implementation of analog-to-digital converters in the next generation software-defined-radio based mobile terminals. As a case study, the high-level design of a multi-rate hybrid Gm-C/SC fourth-order cascade 2-2 ΣΔM has been presented. The simulated performance demonstrates that the circuit can digitize 5-to-60MHz signals with programable effective resolutions ranging from 7 to 15 bits, thus covering a wide region of the resolution-vs-bandwidth plane.
References

1. M. Ortmanns and F. Gerfers, *Continuous-Time Sigma-Delta A/D Conversion: Fundamentals, Performance Limits and Robust Implementations*. Springer, 2006.

2. P. Morrow et al., "A 0.18µm 102dB-SNR Mixed CT SC Audio-band ΣΔ ADC," *IEEE ISSCC Digest of Technical Papers*, pp. 177-178, February 2005.

3. K. Nguyen et al., "A 106dB SNR Hybrid Oversampling ADC for Digital Audio," *IEEE ISSCC Digest of Technical Papers*, pp. 176-177, February 2005.

4. B. Putter, "A 5th-Order CT/DT Multi-Mode ΣΔ Modulator," *IEEE ISSCC Digest of Technical Papers*, pp. 244-245, February 2007.

5. S. Kulchycki et al., "A 77-dB Dynamic Range, 7.5-MHz Hybrid Continuous-Time/Discrete-Time Cascade ΣΔ Modulator.," *IEEE J. of Solid-State Circuits*, vol. 43, pp. 796-804, April 2008.

6. M. Choi et al., "A 101-dB SNR Hybrid Delta-Sigma Audio ADC Using Post Integration Time Control," *Proc. of the 2008 IEEE Custom Integrated Circuits Conference (CICC)*, pp. 89-92, 2008.

7. F. Colodro and A. Torralba., "Multirate ΣΔ Modulators ," *IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing*, vol. 49, pp. 170-176, March 2002.

8. L. Bos et al., "Multirate Cascaded Discrete-Time Low-Pass ΔΣ Modulator for GSM/Bluetooth/UMTS," *IEEE J. of Solid-State Circuits*, vol. 45, pp. 1198-1208, June 2010.

9. M. Ortmanns et al., "Multirate Cascaded Continuous-Time ΣΔ Modulators.," *Proc. of the 2002 IEEE Int. Symp. on Circuits and Systems (ISCAS'02)*, pp. 4225-4228, May 2002.

10. M. Maghami and M. Yavari, "Multirate Double-Sampling Hybrid CT/DT Sigma-Delta Modulators for Wideband Applications.," *Proc. of the 2009 IEEE Int. Symp. on Circuits and Systems (ISCAS'09)*, pp. 2253-2256, May 2009.

11. J. M. de la Rosa, A. Morgado, and R. del Rio, "Hybrid Continuous-Time/Discrete-Time Cascade ΣΔ Modulators with Programmable Resonation.," *Proc. of the 2009 IEEE Int. Symp. on Circuits and Systems (ISCAS'09)*, pp. 2249-2252, May 2009.

12. J. G. García-Sánchez and J. M. de la Rosa, "Multirate Hybrid CT/DT Cascade ΣΔ Modulators with Decreasing OSR of Back-end DT stages.," *Proc. of the 2010 IEEE Int. Symp. on Circuits and Systems (ISCAS'10)*, pp. 33-36, May 2010.

13. S. Pavan, "Systematic Design Centering of Continuous Time Oversampling Converters," *IEEE Transactions on Circuits and Systems II: Express Briefs*, vol. 57, pp. 158-162, March 2010.

14. R. del Rio et al., *CMOS Cascade ΣΔ Modulators for Sensors and Telecom: Error Analysis and Practical Design*. Springer, 2006.

15. J. Ruiz-Amaya et al., "High-Level Synthesis of Switched-Capacitor, Switched-Current and Continuous-Time ΣΔ Modulators Using SIMULINK-based Time-Domain Behavioral Models.," *IEEE Trans. on Circuits and Systems - I: Regular Papers*, vol. 51, pp. 1795-1810, September 2005.