The first idea stems from utilizing the cycle-to-cycle read or programming variability to create random number generators (RNGs) that consume less power than traditional pseudo-random or truly random number generators. By harnessing the inherent variability in these devices, we can develop RNGs that are not only more energy-efficient but also offer improved security and robustness for various applications. Experimental realizations using filamentary memristors,⁹⁰ phase change memories,³⁶⁵ and spintronic devices³⁶⁶,³⁶⁷ have validated this concept. An interesting application is stochastic computing, an alternative approximate low area/low energy computing scheme that has been held back by the lack of compact RNGs: It requires large amounts of RNGs, which in conventional implementations dominate the area of circuits.³⁶⁸,³⁶⁹ Stochastic computing can, therefore, strongly benefit from such stochastic nanodevices.³⁷⁰,³⁷¹

The second idea involves making these RNGs adjustable, i.e., the probability for an output to be one can be controlled by an input signal, effectively creating probabilistic bits or “p-bits.”³⁷² Such structures are analogous to stochastic binary neurons,³⁷³,³⁷⁴ and they have been used in adaptive inference models designed for optimization problems, wherein a set of variables evolves through local and more-or-less random transformations toward configurations that are increasingly probable as they minimize energy.²⁷⁷,³⁷² A particularly exciting opportunity is their use within Ising machines, which have shown potential for solving highly complex tasks using reduced resources.³⁷⁵ Some of the most promising p-bit implementations use spintronics, as low-energy barrier magnetic tunnel junctions provide a p-bit functionality almost intrinsically.²⁷⁷,³⁷²,³⁷³ Some recent studies³⁷⁶,³⁷⁷ have used a limited number of stochastic devices as fast high-quality randomness sources for larger FPGA-based circuits, while stressing that the projected benefits of utilizing nanodevices at a larger scale intrinsically harnessing randomness from the thermal bath remain significant and appealing. Memristors with high random telegraph noise³⁷⁸ could also be used in that direction.

The third idea underscores the striking parallels between the behavior of nanodevices and the principles of Markov Chain Monte Carlo (MCMC) algorithms, a class of stochastic optimization techniques. This correspondence is particularly evident in the case of the Metropolis-Hastings MCMC algorithm. In this context, it is required to generate and store multiple random values for a single parameter, a process that can be naturally implemented using the inherent variability of nanodevices. For instance, the programming current can be employed to determine the mean value, while the imperfections of the devices provide the necessary randomness. This family of algorithms has been extensively used for sampling synaptic weight distributions in training Bayesian models, which excel at modeling uncertainty in complex situations. The most important experimental demonstration, using filamentary memristors, is presented in Ref. 197.

While MCMC algorithms serve as a compelling illustration, they are by no means the only example of stochastic computing methods that can benefit from the unique properties of nanodevices. Indeed, a diverse and rapidly evolving field of research is currently exploring the potential of other stochastic computing techniques for a wide range of applications, from neural networks to combinatorial optimization problems. As our understanding of nanodevice

behavior continues to deepen, the opportunities to leverage their inherent variability in novel and transformative ways promise to fuel further innovation in stochastic computing and beyond.

## 2. Challenges

The primary challenge in exploiting the imperfection of nanodevices lies in the imperfect nature of the imperfections themselves. To harness the inherent variability of these devices for practical applications, it is necessary to achieve a certain level of “controlled” imperfection, which refers to maintaining the desired degree of variability without compromising the reliability and stability of the devices.

The details of memristor or superparamagnetic tunnel junction imperfections are subject to variability. This variability stems from various factors, such as manufacturing variations, environmental conditions, and the complex interplay of atomic-level features and underlying physics. In the case of superparamagnetic tunnel junctions, additional variability in time can occur due to their sensitivity to magnetic field, which is higher than in stable magnetic tunnel junctions. Magnetic shielding can be required to suppress this sensitivity.³⁶⁷ Overall, modeling the imperfections of these nanodevices accurately becomes a challenging task, as capturing these variations in a consistent manner is difficult.

This challenge is further exacerbated by the fact that different types of imperfections have different impacts on the performance and usability of the devices. Therefore, identifying and understanding the specific imperfections that can be harnessed for the development of efficient RNGs and stochastic computing models is of utmost importance.

## 3. Potential solutions

To address the challenges associated with exploiting the imperfections in nanodevices, it is essential to acknowledge that not all imperfections are equally exploitable. For instance, cycle-to-cycle (C2C) variability and device-to-device (D2D) variability differ in terms of their usability and intrinsic nature. C2C variability arises from the inherent variability in the behavior of a single device across different operational cycles, making it more directly applicable and intrinsic to the device. On the other hand, D2D variability occurs due to variations in the performance of different devices, which may be influenced by manufacturing inconsistencies or other external factors.

C2C variability in nanodevices can manifest in two distinct forms: the variability resulting from two consecutive read operations on a device and the variability arising from two programming operations on the device. Distinguishing between these two effects can be challenging, particularly because both types of variability are highly dependent on the read and programming conditions of the devices. These two forms of C2C variability offer unique advantages from an algorithmic perspective, but they are utilized differently in various applications. For instance, read variability is especially well-suited for RNGs or probabilistic bits,²⁷⁷,³⁶⁷ while programming variability is specifically tailored for MCMC algorithms.¹⁹⁷

Even if C2C variability is, in general, more appealing than D2D variability from an algorithmic perspective, D2D variability also has applications: It enables generation of distinct and irreproducible
signatures for each device. Physically unclonable functions (PUFs) are cryptographic primitives that derive their security from the unique and unpredictable physical characteristics of individual devices and are therefore an excellent example of harnessing D2D variability for practical applications.³⁷⁹

Understanding the specific physics underlying different nanodevices can greatly impact their suitability for exploiting imperfections. For example, in hafnium-oxide memristors, only the low-resistance state (LRS) can be readily exploited for our proposed applications, as this state exhibits a much-more controlled degree of variability compared to the high-resistance state (HRS).¹⁹⁷ Spintronic devices also show promising potential in this regard, as they rely on physical phenomena that inherently exhibit a degree of randomness, which can be understood and modeled.²⁷⁷,³⁶⁷,³⁷³,³⁷⁴,³⁸⁰ For example, the switching time of a magnetic tunnel junction is directly connected to the initial angle of the free layers' magnetization, a random quantity, which can be well-modeled³⁸¹ and, to some extent, controlled. When using low-barrier MTJs as artificial spins in Ising machines, D2D variability may cause an unwanted spread in threshold values or even effective pseudotemperature across the network. It was shown that these non-ideal and non-uniform activations could be compensated to some degree by relearning the synaptic weights following the initial mapping.³⁸²

Another core idea for dealing with nanodevice imperfections can be to utilize multiple devices instead of relying on a single one. By employing an ensemble of devices, we can achieve better statistical properties, resulting in improved performance and robustness of the RNGs and stochastic computing models. This approach also helps mitigate the impact of individual device variations and reduces the reliance on any single device, thereby enhancing the overall reliability and stability of the systems (examples of this strategy are seen in Refs. 383–385).

## 4. Concluding remarks

Embracing the inherent variability of emerging nanoelectronic components, such as memristors and spintronic devices, presents a unique opportunity to advance stochastic computing, machine learning, and security applications. By understanding and exploiting the intricate relationship between the variability of these devices and the requirements of various algorithms, we can develop efficient random number generators, p-bits, and Markov chain Monte Carlo implementations, among other stochastic computing techniques.

However, not every nanodevice imperfection can be exploited. To fully harness the potential of these nanodevices, it is essential to address the challenges associated with their imperfect nature. Achieving a “controlled” level of imperfection, understanding the impact of different types of variability, and leveraging the specific physics underlying each device are crucial steps in this endeavor. By employing multiple devices in an ensemble, we can further enhance the reliability, stability, and performance of the resulting systems. As our understanding of the nanodevice behavior and the opportunities to exploit their inherent variability continues to deepen, we can anticipate a surge in innovation in stochastic computing and beyond.

# B. Spiking-based computing

## Sayeed Shafayet Chowdhury and Kaushik Roy

### 1. Status

Spiking neural networks (SNNs) are a promising energy efficient alternative to traditional artificial neural networks (ANNs). While ANN based deep learning has achieved tremendous progress in fields such as computer vision and natural language processing, it comes at a cost of huge compute requirements. Spike-based neuromorphic computing³⁸⁶ provides a potential solution to this issue using brain-inspired event-driven processing. SNNs use binary spikes for computation contrary to analog values used in ANNs. A schematic of spiking neurons with their temporal dynamics is shown in Fig. 17. The spiking neuron receives spike inputs over time, which are accumulated in the membrane potential ($V_{mem}$), which upon crossing a threshold ($V_{th}$), emits an output spike.

A key characteristic of SNNs is the notion of time. While conventional feedforward ANNs are able to map static inputs to outputs with very impressive performance, learning long-term temporal correlations using them is challenging. On the other hand, recurrent neural networks (RNNs) are more suited to process temporal information efficiently,³⁸⁷ although recent developments, such as transformers, have shown that ANNs can perform well in temporal processing too,³⁸⁸ albeit with a higher training and memory cost. Different variants of RNNs, such as vanilla RNNs,³⁸⁹ long-short term memory networks (LSTMs),³⁹⁰,³⁹¹ and gated recurrent units (GRUs),³⁹²,³⁹³ have been proposed, which differ in their degree of complexity and capability to capture temporal information. However, they all contain explicit feedback connections and memory elements to handle temporal dependencies. On the contrary, SNNs can be regarded as a simpler form of RNNs, where the recurrent dynamics of $V_{mem}$ acts as an internalized memory.³⁹⁴ Interestingly, the leak in SNNs can play the role of a lightweight gating mechanism, thereby temporally filtering out some irrelevant information.³⁹⁵ In addition, SNNs may lead to a lower parameter count and an easier training overhead compared to LSTMs.³⁹⁶

The sequential nature of processing in SNNs leads to unique opportunities in terms of input representation. Traditional feedforward ANNs, such as CNNs, and the more recent vision transformers³⁹⁷ process several temporal inputs by merging them into a single large representation. On the other hand, SNNs can process the sequential inputs in a streaming fashion, using the inherent

<figure><img src="image_28.png" /><figcaption>FIG. 17. A leaky-integrate-and-fire (LIF) neuron. (a) Schematic connection between three pre-neurons and a post-neuron; (b) temporal dynamics of the post-neuron. Adapted from Ref. 387.</figcaption></figure>
recurrence of neuronal membrane potential. As a result, SNNs are inherently suitable to process temporal event camera<sup>40</sup> data. However, for analog inputs, it becomes a key challenge to efficiently encode the data into a spike train. Initial studies<sup>398,399</sup> use Poisson rate-coding, where the input is compared to a random number at each time step and a spike is generated if the input is higher than the random number. However, this process suffers from high inference latency. Temporal coding schemes, such as phase coding,<sup>400</sup> burst<sup>401</sup> coding, DCT-encoding,<sup>402</sup> time-to-first-spike (TTFS) coding,<sup>403</sup> and temporal coding,<sup>404</sup> attempt to capture the temporal correlation in the data. However, their accuracy is often lower than ANNs. More recently, direct encoding approach<sup>405,406</sup> has become popular, where analog values are given directly to the SNN and the first layer of the neural network layer acts as a spike generator. Such a method has provided impressive performance on complex tasks with very few time steps. Besides the analog input modalities, DVS cameras (such as DAVIS240<sup>407</sup>) provide discrete spikes directly as inputs, which are inherently more amenable to SNNs. Conventional ANN-based approaches tackle the event streams by accumulating them over time and subsequently processing the lumped input altogether.<sup>408,409</sup> However, the rich temporal cues present in the event data may not be optimally leveraged in this process. Therefore, recent studies proposed to process the event streams using SNNs,<sup>410</sup> which leads to a synergistic alliance between the inputs and spike-based processing. We believe that this is a promising direction to pursue as it enables harnessing the inherent temporal processing capabilities of SNNs with event data.

## 2. Challenges and potential solutions

A crucial bottleneck in the advancement of SNNs is the lack of suitable training methods. Sparsity of activations and the discontinuous derivative of spike functions lead to training complexity in SNNs. To counter that, initial approaches mostly used ANN-SNN conversion.<sup>398,411</sup> Although the conversion method provides high accuracy, it suffers from significant inference latency. Following this, surrogate gradient-based backpropagation (BP) methods have been proposed<sup>399,412,413</sup> to train SNNs from scratch. Note that, due to the sequential nature of inputs, SNNs are trained with backpropagation-through-time (BPTT), similar to RNNs. However, simpler neuron models and lower parameter complexity makes the optimization of SNNs simpler compared to RNNs. Although these surrogate gradient-based BPTT methods have advanced the field of SNNs by obtaining high accuracy, the training workloads are still quite intensive in addition to considerable inference latency (100 time steps). To overcome these, the authors in Ref. 414 propose to merge the conversion and BP-based training methods (termed "hybrid" training), where first, an ANN is trained to use it as initialization for subsequent surrogate gradient-based BP. More recently, advanced training approaches, such as temporal pruning,<sup>415</sup> custom regularizers,<sup>416</sup> and modified neuron models,<sup>417</sup> have been proposed, which enable reducing the latency of SNNs to unit time step. A complementary research direction proposes to utilize equilibrium propagation to train SNNs.<sup>418,419</sup> These approaches provide a promising more bio-plausible alternative to backpropagation. However, challenges remain in their large scale implementation.

Parallel to algorithmic developments, advancements in neuro-morphic hardware fabrics are equally critical to unearth the true potential of SNNs. Due to the sequential nature of data processing,

SNNs present unique challenges on the hardware front as current graphics processing units (GPUs) and tensor processing units (TPUs) are sub-optimal to exploit the high temporal as well as spatial sparsity.<sup>420</sup> Furthermore, information processing using membrane potential over multiple time steps leads to memory-intensive operations, an overhead that is non-trivial to mitigate using off-the-shelf digital accelerators. Taking such issues into account, several research directions have been pursued in recent years across the stack from devices and circuits to architectures. Event-driven neuromorphic chips, such as Neurogrid<sup>421</sup> and TrueNorth,<sup>50</sup> are notable, which are based on mixed signal analog and digital circuits, respectively. Two standout features of these neuromorphic chips are asynchronous address event representation and networks-on-chip (NOCs). Another promising direction is investigating various beyond von Neumann computing models to counter the "memory wall bottleneck." To this end, near-memory and in-memory<sup>50,422,423</sup> computing paradigms are being explored to improve throughput and energy efficiency. To realize these emerging computing platforms, exciting progress is being achieved in the device domain utilizing non-volatile technologies.<sup>424</sup> Some noteworthy approaches based on memristive technologies include resistive random-access memory (RRAM),<sup>343</sup> phase-change memory (PCM),<sup>356</sup> and spin-transfer torque magnetic random-access memory (STT-MRAM).<sup>425</sup> RRAMs provide analog programmable resistance but are prone to process and cycle variations and read/write endurance. Devices based on PCM can achieve comparable programming voltages and write speed to RRAMs; however, high write-current and resistance drift over time cause issues. On the other hand, compared to RRAMs and PCMs, advantages of spin devices<sup>426</sup> are almost unlimited endurance, lower write energy, and faster reversal. However, their ON/OFF ratio is much smaller than in PCMs and RRAMs, requiring proper algorithm/hardware co-design.<sup>427</sup> Note that each of these technologies has its pros and cons and there is no single winner at the moment. Floating-gate transistors<sup>428</sup> are another class of non-volatile devices that are being explored for synaptic storage. While their compatibility with MOS fabrication process is attractive, challenges persist regarding reduced endurance and high programming voltage.

## 3. Conclusion

To conclude, SNNs are a promising bio-plausible alternative to conventional deep neural networks. However, it is imperative to understand the "why" and "where" of their proper usage. While SNN algorithms have largely focused on static vision tasks<sup>428</sup> until now, their true potential lies in processing sequential information. To that effect, several works are exploring event-based vision for optical flow, depth estimation, egomotion, etc. We believe that immense opportunities lie ahead in further exploration of SNNs in varied avenues requiring temporal processing, such as video processing, reinforcement learning, speech, and control. In order to achieve that, there is a need of concerted synergistic efforts on algorithms as well as hardware. On the algorithmic aspect, we need to focus on investigating learning approaches that can leverage the unique data representation provided by spiking neurons. In addition, developing hardware geared toward SNN-specific algorithms is critical for the whole field to move forward. Overall, while domain-specific challenges are prevalent in spike-based computing, we believe that the next few years will be exciting as we discover the niche of
SNNs, most likely comprising temporal applications with low power requirements.

## C. Analog computing for linear algebra

Zhong Sun, Piergiulio Mannocci, and Yimao Cai

### 1. Status

Linear algebra problems are being solved in every corner of the information world. Solving these problems by running algorithms in digital computers, however, is generally hard and resource-demanding, featuring a high computational complexity, such as $O(n^3)$, where *n* is the number of variables. To overcome the inadequacy of digital computers whose performance is fundamentally limited by the ultimate scaling of Moore's law and the intrinsic bottleneck of von Neumann architecture, analog computing arises as a promising solution, thanks to its efficient information encoding, massive parallelism, fast response, and the emerging resistive memory technology.¹²⁹ Analog matrix computing (AMC) is conveniently realized with a crosspoint resistive memory array, which forms a physical matrix by storing entries as crosspoint device conductances and thus can be used for linear algebra computations. There are several resistive memory device concepts that rely on distinct underlying physics, including two-terminal devices, such as

resistive random-access memory (RRAM), phase change memory (PCM), magnetoresistive RAM (MRAM), and ferroelectric tunnel junction (FTJ),⁴³⁰ and three-terminal devices, such as ferroelectric field-effect transistor (FeFET) and electrochemical RAM (ECRAM). They are all simply used as programmable resistive devices to implement AMC.⁷⁵,¹⁹⁹,⁴³¹⁻⁴³⁴ In this context, one of their differences lies in the conductance range that may limit the capacity of mapping matrix elements, say one bit or multiple bits. It is possible to replace one type of resistive memory device that has been demonstrated for AMC application by another one. For simplicity, we limit our discussion to RRAM that we have used frequently.

The most straightforward AMC implementation is to perform the matrix-vector multiplication (MVM) in one step. By simply applying simultaneously a set of voltages (representing an input vector) to the crosspoint columns, the currents through the crosspoint array are collected at the grounded rows, constituting the output vector, which in turn is converted and read out with transimpedance amplifiers (TIAs) [Fig. 18(a)]. By adopting the conductance compensation strategy,⁴³⁵ MVM of a mixed matrix that contains negative entries can be implemented with the same number of TIAs as shown in Fig. 18(a). MVM is the backbone of many important algorithms, such as neural networks and discrete transformations. Consequently, RRAM-based AMC has widely been considered as an accelerator approach, showing more than two orders of magnitude improvements of throughput and energy efficiency.¹⁷⁸

<figure><img src="image_29.png" /><figcaption>FIG. 18. AMC circuits for (a) matrix-vector multiplication, (b) matrix inversion, (c) generalized left inverse, (d) generalized right inverse, and (e) eigenvector computations.</figcaption></figure>

<figure><img src="image_30.png" /><figcaption>FIG. 19. AMC circuits for (a) matrix-matrix-vector multiplication and (b) solving sparse approximation problems, e.g., compressed sensing recovery.</figcaption></figure>
In addition to the naive MVM application, more complicated
linear algebra computations have been realized through configur-
ing AMC circuits with feedback loops. Figure 18 shows closed-loop
AMC circuits for other basic matrix operations, including matrix
inversion (INV), generalized inverse, and eigenvector. The INV
circuit in Fig. 18(b) is constructed based on the global feedback
connections between crosspoint rows and columns through opera-
tional amplifiers (OPAs). It solves a system of linear equations when
an input current vector is provided, with the output voltages of
OPAs representing the solution.436 INV is exactly the inverse prob-
lem of MVM. Both circuits utilize the same electronic components,
whereas the different connection topologies define the opposite
functions. The INV concept can be generalized to non-square matri-
ces, by configuring AMC circuits with two sets of crosspoint arrays
and amplifiers. Depending on the matrix shape (tall or broad), the
generalized left [Fig. 18(c)] and right [Fig. 18(d)] inverse circuits
have been designed, both based on the same feedback loops while
showing differences in terms of input terminals and matrix storage
(transpose or not).190 INV and generalized inverse find application
in many scenarios, such as machine learning, wireless communi-
cations, and scientific computing.437–439 Unlike MVM, INV suffers
from the condition number issue, where the input error would be
amplified for an ill-conditioned matrix (with a large condition num-
ber), resulting in a low computing precision. Consequently, it is
appropriate to use the INV circuit as an analog preconditioner,
and the performance of scientific computing may be improved by
more than three orders of magnitude.437 The eigenvector circuit
in Fig. 18(e) uses global feedback as well, but it is a fully self-
sustained system with no external inputs, while working by positive
feedback mechanism.436 It finds application in typical scenarios,
including quantum simulations, PageRank for Google search, or
recommender systems.

Recently, more AMC circuits have been developed for solving
more complicated matrix problems. Figure 19(a) shows a design
for matrix–matrix–vector multiplication (MMVM), by mapping
two matrices (or two copies of one matrix) in a RRAM array,
assisted by the use of conductance compensation.⁴⁴⁰ By connecting
this MMVM circuit with other analog components, and particu-
larly a nonlinear function module based on operational amplifiers,
to form a feedback loop, the resulting circuit solves the sparse
approximation problem in Fig. 19(b) in one step without discrete
iterations. Notably, the nonlinear function may also be implemented
by a volatile resistive switching device, thus substantially improv-
ing the compactness of the AMC circuit.⁴⁴¹ It has been used for
compressed sensing recovery of sparse signal, natural images, and
medical images, representing a highly promising solution for the
backend processor to deliver real-time processing capability in the
microsecond regime.

## 2. Challenges

Thanks to the manufacturability and compatibility of RRAM
devices in modern CMOS technology processes, large-scale RRAM
arrays have been fabricated for AMC implementations. In particular,
RRAM macros including peripheral circuitries are usually designed
to deliver MVM accelerations. By contrast, closed-loop AMC has
been limited to small-scale concept demonstration, e.g., for 3 × 3
matrices. The reason behind the developmental stagnation might
be ascribed to the unconventional analog circuitry. Different from

MVM that consists of only local feedback, closed-loop AMC cir-
cuits contain complicated, hard-wired global feedback connections
across the entire RRAM array. Since all elements are involved to
provide a collective circuit response, the operation may become sen-
sitive, risking the damage of RRAM devices under excessive electric
stimulus. In addition, for large-scale circuits, the non-ideal factors
of devices and circuits will jointly lead to an exaggerated deviation
from the correct result. In addition, the time response of the circuit
might be influenced by non-idealities, such as parasitic resistances
and capacitances, which may even cause an instability issue.

Despite the lack of large-scale demonstration at this moment,
it is quite promising to build closed-loop AMC circuits based on
the relatively mature RRAM technology in the near term, given that
lots of theoretical and simulation works have intensively examined
the potential issues. In the long term, the following aspects shall be
addressed to support the development of AMC circuits for linear
algebra:

(1) Device/array level: At present, the largest available array size is 512 × 512.¹⁷³ In practice, only a fraction of the array is turned on for computation, due to the current/power overload and the accuracy limitation. We believe that such an array size is already sufficient to well support the advantages of AMC over other paradigms. Otherwise, we should put the stress on the analog conductance tunability of RRAM devices, which are expected to show as many distinguishable conductance levels as possible. In turn, fast and accurate programming of the RRAM conductance is essential to maximizing the AMC efficiency. The linearity and symmetry of device conductance update have been continuously emphasized for the online training of neural network weighs;¹⁴² such a characteristic should also be favored for real-time update of matrix elements in general AMC applications. On the other hand, there should be a trade-off consideration on the RRAM conductance range, which is associated with the power consumption, alleviation, or exacerbation of the impacts of resistive and capacitive parasitics. The device variations should matter most to affect the computing precision. In particular, for solving inverse problems with the closed-loop circuits, the matrix structure related to the condition number should also be a deterministic factor.

(2) Circuit/architecture level: The scalability of AMC circuits comes at the cost of the reduced precision, where the accumulated error may eventually decline the nominal result. As a result, there is a trade-off between the desired computing accuracy and the possible array size. For solving extremely large-scale problems, especially for the inverse matrix problems, it is imperative to have algorithmic solutions to recover the result correctly. Therefore, a clever design of efficient algorithms for matrix processing would be very helpful. In particular, as RRAM-based AMC uses two physical attributes, namely conductance and voltage, the cascading of an algorithm may require transition between the two attributes, which will inevitably make the operation complicated. To this end, algorithms featuring as less such transitions as possible are precious. In addition, since AMC circuits are all based on the core RRAM array, it is valuable to have a reconfigurable architecture for performing different
matrix operations. As amplifiers play another critical role in AMC, it is highly beneficial to design efficient amplifiers that are well suited to the circuits.

(3) Software and application: During the AMC operation, multiple rows/columns of the array are simultaneously activated to carry out computation, indicating a primary requirement of such instructions in an AMC program. In addition, instructions for circuit reconfigurations should be included to enable a general AMC architecture. Therefore, the efforts on compiling and programming for AMC will be of significant importance.443 To support the AMC concept, finding a killer application that well matches the advantages of AMC will be most convincing. The application of MVM to neural network acceleration has attracted enormous attention in past years, with a few successful silicon demonstrations toward real-world applications. For closed-loop AMC circuits, we believe that nonlinear matrix problems and related applications would be most promising, since they are more tolerant to errors as in the neural network.

### 3. Potential solutions

RRAM-based AMC is extremely fast in that the computation is basically a parallel reading process. To prevent the memory writing process being a bottleneck, parallel writing schemes have been developed. For instance, the weight matrix in the array can be updated by using the outer product operations, sometimes assisted by gradient decomposition methods.444 However, these methods usually overlooked the memory nature of RRAM, that is, the analog information needs to be reliably read out. To this end, a verification circuit should be included to confine the conductance distributions. In particular, fast writing with less/no iterations will be very beneficial to saving the latency. One example is the closed-loop write scheme that uses current feedback to control the resistive switching process.445 Because of the underlying ionic migration mechanism of RRAM devices, the endurance capability has constantly been a critical issue for both memory and AMC applications.62 It is unlikely that this issue can be overcome solely by test method innovations; new physical mechanisms may be needed to solve it from the source. In addition, investigations on device materials and structures to fundamentally optimize analog RRAM performance and to empower the array extension are always highly desired.

The scale-accuracy trade-off of RRAM-based AMC should be elaborated to balance the efficiency and reliability. Efficient algorithms for matrix tiling and result recovery are vital for solving large-scale problems. Recently, a scalable AMC method, termed BlockAMC, has been proposed for solving large-scale linear systems. It partitions a large original matrix into smaller ones on different memory arrays and performs MVM and INV operations with the block matrices to recover the original solution.446 To reduce the impact of non-idealities, AMC systems with both algorithmic and architectural innovations should be designed. For MVM, it is convenient to implement the bit slicing method to extend the computing precision, by using only low-precision memory devices.447 However, as the INV circuits contain global feedback loops, it is difficult to apply this method to improve the precision of INV operations. Eventually, an analog-digital hybrid system may be required to deliver

this capability. With the RRAM array as the core, the peripheral circuits and the connections can be reconfigured to perform different AMC operations. In this regard, the basic models shall include RRAM arrays, amplifiers, and reconfigurable routing. Different circuit configurations are actually hardware-embedded instructions of matrix operations.

It is of great practical convenience to have a set of fixed AMC primitives that can be adopted to realize general matrix computations, together with vector processing, parameter scaling, and variable attribute conversion. There is a trend that takes MVM and INV as two primitives to enable a reconfigurable, general-purpose AMC system, which may be used for linear regression, generalized regression, and eigen-decomposition.448-450 Given the intrinsic noises in analog computing, we believe that nonlinear closed-loop AMC that is inherent in error tolerance is more promising toward real-world applications. Typical examples include solving some optimization problems, such as sparse coding, compressed sensing recovery, and linear/quadratic programming. These problems appear in many common scenarios, such as wireless channel estimation, magnetic resonance imaging, and signal processing.451 In addition, front-end integration with sensors for signal processing would be encouraging, which helps save data conversions and thus reduces the accumulation of noise effects.452 These problems typically favor relatively small RRAM arrays, thus alleviating the rigorous requirements on the device/array performance. Eventually, as the RRAM technology matures, the application to large-scale and high-precision problems will be advanced, with the help of innovative algorithms and architectures.

### 4. Conclusion

In the modern era, due to the strong demand for linear algebra acceleration and the rapid development of emerging resistive memory devices/architectures, analog computing has gained a renewed interest across academia and the industry. Various AMC circuits have been successfully demonstrated for fast solutions of matrix problems that constitute the basic operations for linear algebra computations. However, most of the AMC concepts still remain in the laboratory prototype stage, calling for a roadmap covering different aspects to guide system integration, optimization, and application. Next steps toward effective AMC shall include developing (1) reliable analog conductance programming methods, (2) architecture and algorithm designs for large-scale problems, (3) circuit designs for non-ideality mitigation, (4) reconfigurable systems, (5) more AMC circuits, e.g., for nonlinear matrix operations, and (6) application to near-term and long-term typical scenarios.

## D. Analog content addressable memories (CAMs) for in-memory computing

### Giacomo Pedretti

#### 1. Status

Content addressable memories (CAMs) are a class of memory structures that, given an input query, return their stored location or
<figure><img src="image_31.png" /><figcaption>FIG. 20. Illustration of a TCAM (a) and an analog CAM (b). (c) Circuit schematic of a 6T2M analog CAM, capable of returning a match if the input on the DL is within a function of the memristor conductance (inset). (d) Example of decision tree and (e) its mapping to an in-memory computing circuit for single/few cycle inference.</figcaption></figure>

address. A wildcard, “X,” can be added allowing for “fuzzy” searches, resulting in a ternary CAM (TCAM).⁴⁵³

Figure 20(a) shows a TCAM schematic. An input query is applied along the columns, or search lines (SLs), and outputs are returned along the rows, or match lines (MLs). A given row is matched (returning a “1”) if each value $q_j$ of q is equal to the corresponding key-value $K_{ij}$ stored in the row i (column j), which corresponds to performing the operation

$$ML_i = \prod_j (q_j \oplus K_{ij}).$$

CMOS/SRAM-based TCAMs are ubiquitous in networking, but they are usually bulky and power-hungry. Memristor-based TCAMs have been shown to outperform CMOS circuits, but given the relatively low speed and inefficient writing of memristors, they are currently being proposed for in-memory computing applications. In this framework, we have recently proposed an analog CAM⁴⁵⁴ that stores ranges and returns a match on the MLs if the analog input is within the stored ranges or

$$ML_i = \prod_j (T_{l,ij} \le q_j < T_{h,ij}),$$

where $T_l$ and $T_h$ are the stored upper and lower bounds thresholds, respectively. Figure 20(c) shows a conceptual representation of an analog CAM, and Fig. 20(c) shows the schematic of a 6-transistor-2-memristor (6T2M) analog CAM. Two 1T1R voltage dividers compare the analog input on their gate with the stored value in the memristor conductance, and their drain node controls

either a pulldown transistor (left side) or a series of an inverter and a pull-down transistor (right side) to discharge the pre-charged ML if the input is lower than the lower bound or higher than the upper bound, respectively. For example, if the input voltage is high enough to turn on the input transistor, resulting in a voltage on the leftmost 1T1R drain lower than the pulldown threshold, the latter will not be activated. Similarly, if the same input voltage is low enough such that the input voltage of the inverter is above its threshold of the rightmost 1T1R, its pulldown transistor would not be activated. This results in a match, given that the ML would not discharge.

Other implementations of analog CAMs have been proposed based on compact ferroelectric structures, although given the absence of the inverter, a proper conditioning of the input should be performed.⁴⁵⁵

While the in-memory computing community in the past decade have been focused on the acceleration of deep neural networks (DNNs), tree based machine learning (ML) still outperforms DNN when processing tabular data due mainly to the presence of missing and categorical features.⁴⁵⁶ Figure 20(d) shows a schematic representation of a decision tree (DT), which is essentially a collection of conditional branches (nodes) in a tree structure. Given the irregular structure, ensembles of DTs are not well suited for being accelerated in CPU and GPU, due to thread synchronization issues, load imbalance, and uncoalesced memory accesses.⁴⁵⁷ Recently, we have shown that DT ensembles can be mapped to analog CAMs, providing a one-cycle and conversion-less inference, given that the output is already digital and ready to be post-processed.⁴⁵⁸ Figure 20(e) shows the DT of Fig. 20(d) mapped into an analog CAM array, where each root-to-leaf path is encoded in a row. The digital
ML outputs are connected to a conventional RAM storing the leaf values or prediction. All branches are executed in parallel, providing size-independent inference latency.

## 2. Challenges

Most of the challenges in building reliable analog CAMs are shared with crossbar arrays of memristors, although some circuit and device requirements are different. Similarly, a wide range of programmable levels in the memristor conductance is desirable, but different from crossbar arrays, slicing techniques for increasing precision<sup>459</sup> cannot be performed. Range-based analog CAMs have a unary encoding; thus, connecting multiple adjacent analog CAMs on a given row doubles the number of levels as opposed to bit-slicing in crossbar arrays, which doubles the number of bits, leading to an exponential overhead. Linear approaches for an improved analog CAM precision have recently been shown,<sup>460</sup> although with a significant circuit complexity overhead. Moreover, given the voltage divider operation performed directly on the memristor, its conductance needs to be stable at higher read voltages, e.g., 1 V, to be able to efficiently control the pulldown transistor.

While a small 2 × 2 array was realized in the 180 nm technology node and large array simulations at the 16 nm technology node were performed,<sup>454</sup> experiments on large arrays, i.e., 128 × 16, have yet to be realized. There are several concerns to be solved at the array level, for example, the impact of memristor variation and noise on the search accuracy and the impact of parasitic capacitances and resistances on a reliable operation. Moreover, due to the nonlinear input/output relationship, even defining the appropriate patterns for the program is challenging and ad hoc circuit-aware programming routines should be performed.

Finally, a full and general architecture design has yet to be performed, to feed and pull data with enough bandwidth to take advantage of the single-cycle memory lookup operation, eventually including multiple independent cores and performing operations on a large amount of data in parallel. The architecture should be programmable, not limited to tree-based ML inference, allowing multiple tasks such as associative searches,<sup>455</sup> and resilient to errors due to memristor variations, for example, including error correction codes routines.

## 3. Potential solutions

First, large arrays of CMOS-integrated analog CAMs with memristor devices should be designed and fabricated. Techniques for increasing the memristor conductance stability at relatively high reading voltages have been presented and should be used to develop an analog CAM-specific memristor stack. For example, a larger oxidation layer and/or a controlled deposition to limit the oxygen defect in it can be used to increase the set voltage of memristor devices, which could result in better stability.

Analog CAM circuits to support a higher number of bits can be designed by studying the appropriate logic functionalities in the case of a separate comparison of the least significant and most significant bits, for example by mapping different logic functions between adjacent cells.<sup>461</sup> In principle, it is possible to implement any kind of logic operation between adjacent CAM cells by opportunistely connecting the pulldown transistors. Custom program and verify algorithms,

efficiently including process variation and noise, are being developed,<sup>462</sup> in order to design appropriate target patterns to program in the memristor conductance while performing nonlinear operations.

Finally, a similar architecture to the crossbar array accelerators with a custom instruction set architecture (ISA) compiled from popular tools, such as sk-learn, can be implemented.<sup>463</sup> The analog CAM operation should be abstracted enough in order to efficiently map different workloads in a hierarchical way to the programmable accelerator, with multiple cores handling a different part of the problems, and a global network on chip accumulating the results to finalize the computation. In order to make each core operation reliable, an error detection scheme already designed for TCAMs can be adapted to the new analog CAM to efficiently re-program a given device once the state has been drifted out of the desired one.<sup>464</sup>

## 4. Conclusion

While a lot of efforts have been spent in the past years by academia and industry research for developing in memory computing structures based on linear operators, such as crosspoint arrays, recently, a renewed interest in memristor-based CAMs has arisen. Different circuits for memristive TCAMs and analog CAMs have been proposed, targeting multiple applications, but a circuit-level integration of CMOS circuitry with a BEOL-integrated memristor device along with a system-level analysis of performance at scale has yet to be shown. While engineering such required milestones, researchers should also focus on exploring new applications exploiting open-sourced circuit models, given the novelty of the idea; it is, in fact, likely that we are just scratching the surface of the potentiality of such computing primitives, given the inherited nonlinear operation performed with unprecedented speed and energy efficiency.

## E. Optimization solvers

### John Paul Strachan and Dmitri Strukov

#### 1. Status

One of the best examples of a high-risk-high-reward area for novel computing is the area of optimization solvers. Here, the ambition is to offer some form of speedup or reduced resource requirements (memory, energy, etc.) in solving computationally expensive combinatorial optimization problems. In such problems, the task is to minimize a given cost (or energy) function by choosing the best configuration within a large dimensional space. Well-known examples include the traveling salesmen problem (finding a minimal route uniquely visiting various cities), graph coloring (coloring nodes such that connected nodes have different colors, while using the fewest colors), or training the weights in an artificial neural network (ANN). While some problem classes and instances can be solved approximately and quickly using greedy algorithms, many remain intractable and no known algorithm exists that can solve them all with polynomial resources and in polynomial time. Even a modest speedup could offer immediate benefits in practical applications across planning, wireless communication, bioinformatics, routing, finance, and many more.
The above challenge has inspired many research communities to develop both new algorithms and new physical hardware approaches, often in conjunction. A prominent example of this was the recognition that many optimization problems can be mapped to problems in physics,⁴⁶⁵ such as finding the ground state of an Ising system of coupled up-or-down spins. This has driven interest in the so-called Ising solvers, which can have many physical realizations, including optical parametric oscillators, coupled electrical oscillators, magnetic tunnel junctions, and analog memristors.³⁷⁵ From the early neural-inspired communities, John Hopfield's nonlinear networks of analog neurons turned out to also solve planted optimization problems.⁴⁶⁶ Quantum or quantum-inspired approaches have also been pursued, leveraging the quantum adiabatic theorem, where a ground state (optimal) solution is found by evolving slowly from an initial, simple Hamiltonian toward a final Hamiltonian that encodes the desired problem.⁴⁶⁷ Dynamical solvers are also being pursued,¹⁶⁸,⁴⁶⁹ where the large configuration space is explored rapidly via coupled nonlinear dynamical equations, with optimal configurations acting as attractor states.

It is important to realize that the variety of physics and quantum-inspired approaches discussed above offer primarily an algorithmic paradigm for solving optimization problems. The underlying materials, physics, and computational elements remain quite flexible. For example, traditional CPUs, GPUs, and FPGAs can be used to simulate nonlinear dynamical equations. Or electronic CMOS-based ring oscillators can be built and resistively or capacitively coupled in order to simulate the magnetically interacting spins in an Ising model. Thus, there are many possible combinations of algorithmic or computational models and the physical substrate where computations are performed. It is easy to mistake one for the other. Yet, despite such variety in possible physical realizations, some common underlying challenges emerge, which must be handled in order to successfully engineer an efficient and broadly useful optimization solver. The remaining portion of this document lists these challenges and opportunities.

<figure><img src="image_32.png" /><figcaption>FIG. 21. Typical steps for solving combinatorial optimization problems with Ising machine. The original problem is formulated as a quadratic unconstrained optimization (QUBO) problem. The QUBO problem may need to be modified, e.g., sparsified or decomposed to smaller subproblems, before it can be mapped on the targeted Ising machine. Note that the figure shows a fully connected Ising machine and the simplest baseline QUBO formulation. Efficient implementation of different annealing techniques and approaches for solving constrained optimization problems relies on the ability to adjust coupling weights during runtime.</figcaption></figure>

## 2. Challenges

a. Challenges of mapping to hardware. Mapping optimization problems to physical systems, such as a hardware Ising model (illustrated in Fig. 21), is an attractive approach, but it also highlights many key challenges. An Ising model is based on pairwise couplings of binary spins, and therefore, up to quadratic terms appear in an energy function with binary variables, and there is no explicit mechanism to enforce additional constraints (such as summing to certain integer values). This is also known as a Quadratic Unconstrained Binary Optimization (QUBO) type, having an energy function in the case of an Ising model,

$$E_{\text{QUBO}} = \frac{1}{2} \sum_{i,j \neq i} W_{ij} s_i s_j + \sum_i h_i s_i.$$

Yet, many optimization problems involve higher than quadratic interactions. For example, a k-Satisfiability problem (k-SAT) involves terms of order $k$. Such higher-order interactions must be mapped down to quadratic terms, through the introduction of additional auxiliary variables. The result is a new total number of variables that is polynomially larger than the original number of variables, leading to, in the worst case, an exponential penalty in terms of the configuration space that needs to be searched. This has motivated explorations of algorithms with higher-order interactions¹⁷⁰ and their physical realizations.

In addition, QUBO formulations are sometimes inefficient, even for natively quadratic problems. For example, the typical QUBO approach for a K-city traveling salesman problem is to encode each route with K one-hot-encoded K-bit vectors representing the visitation order of each city.⁴⁶⁵ The result is a quadratic scaling for QUBO variables, i.e., $N = K^2$, with the number of cities. This can lead to a worst-case exponential penalty in the configuration space to search as a function of the number of variables.

b. Scaling challenges. Efficient mapping (“embedding”) of an optimization problem to the underlying Ising hardware may require further modification of the QUBO formulation. Indeed, the naive implementation of N-variable QUBO problems requires $N^2$ coupling weights to allow programmable coupling with unique weights between any pair of neurons. N can be more than a million for many practical sparsely coupled optimization problems [such as the already mentioned TSP and SAT problems], which is clearly unacceptable for most Ising model implementations. To address this challenge, a general approach is to decompose the original QUBO problem into smaller subproblems that can be implemented in the hardware. For example, one can partition a large neuron connectivity graph into smaller subgraphs, with minimized number of edges between subgraphs. The corresponding subgraph subproblems are then solved independently, e.g., by fixing values of variables not participating in the currently solved subgraph. The downside of such an approach can be lower solution quality or longer time, even if all subproblems are individually solved optimally. The scaling problem is further exacerbated for hardware approaches with limited coupling capabilities. For example, if only limited neighbor connectivity is possible—such as in the so-called chimera graph topology implemented in the DWave interconnected superconducting bits—then the embedding comes with an even higher overhead. In this case,
the original QUBO problem is first sparsified to meet the connectiv-
ity limitations by adding redundant variables and then partitioned
into subproblems. The result can be an exponential slowdown⁴⁷¹ in
solution convergence.

c. Precision challenges. Many emerging device technologies do not allow for realizing accurate weight couplings and performing precise computation of node updates. On the other hand, the weight precision should be sufficient to encode the weight dynamic range. More generally, the non-idealities in the physical couplings need to be low enough not to distort the global energy minima. Detailed studies of non-idealities in, for example, Ising machine operations are so far very limited; however, an initial insight is provided by similar studies for training artificial neural networks, a type of optimization task. Training to the highest accuracy requires at least 4-bit weight and dot-product computation precision for many deep learning models.⁴⁷² The precision requirements are higher for very compact models, such as MobileNet, and lower for larger, redundant models, such as VGG. This is likely inversely correlated with the number of global minima and their basin volumes. Therefore, higher precision requirements are expected for solving harder combinatorial optimization problems and/or when better solution quality is sought.

**3. Potential solutions**

Advances are needed across algorithmic, device, and architec-
tural levels. On the algorithmic front, it was already stressed above
that improved mappings are needed to ensure efficient conversion
from the original optimization problem to QUBO, as well as efficient
embedding.

On the device front, we need to identify the best device and
material implementations to overcome challenges in connectivity
and interactions. Are there any material and device concepts that
would allow implementation of the higher order in the hardware?
The scaling issues highlight the importance of efficiently imple-
menting coupling weights. In this respect, emerging analog memory
devices and in-memory computing with dot-product circuits are
especially attractive. Optical computing approaches are attractive
because of the high fan-in interconnects that can be attained. Quan-
tum computing is attractive because of quantum annealing, which
offers a tunneling mechanism through energy barriers. Many tricks
on the device and circuit levels can be borrowed from the work on
neuromorphic inference to improve tolerance to non-idealities and
increase precision.

On the architectural side, we need more flexible designs to han-
dle broadly varying levels of difficulty and size. Many problems are
locally dense but globally sparse. For example, hard k-SAT problems
are sparse, with sparseness increasing with model size, and the archi-
tecture should take advantage of such sparseness by mapping highly
interconnected neuron subgraphs onto fully connected smaller size
Ising machines and interconnecting Ising machines with routing
networks.

A key feature for further advances on every front will be proper
benchmarking. The design space is very broad and is further compli-
cated by the wide range of applications with different characteristics
(hardness, coupling density, and problem size). Figure 22 shows the
key metrics—solution quality found as a function of hardware time
to solution at a fixed power consumption and hardware resource

budgets, highlighting the important trade-offs to identify promising
solutions and guide further design. Such a figure can be drawn for
a collection of benchmarks or an individual benchmark and, in the
general case, would change with the scale of the problems. Note that
the fixed resource budget in Fig. 22 is essential for a fair compar-
ison of different designs because time to solution can be improved
with parallelism, i.e., spending more energy and/or relying on higher
complexity hardware. (Alternatively, Fig. 22 can be extended to
show time, energy, and hardware complexity to the solution qual-
ity. Such characterization would be more complete, although less
insightful when sparse data are available.)

For example, we anticipate that low precision and/or restricted
connectivity systems will be much faster and energy-efficient when
worse precision is required. Such systems may never reach the
highest quality solutions, e.g., because inherent error modifies the
energy landscape or the subspace. On the other hand, a brute
force algorithm, e.g., performed on a conventional computer, would
guarantee finding optimal solutions. The first emerging optimiza-
tion solvers (such as Ising machines) can occupy intermediate
locations in these trade-off curves, tuned to the desired priority
metrics.

**4. Conclusions**

There is great potential to harness physics- and brain-inspired
approaches to improve today's computing systems for solving opti-
mization problems. Yet, we see challenges that must be over-
come at many material, circuit, system, and algorithmic levels
in order to realize this potential. A variety of approaches are
under exploration that use optical, quantum, magnetic, or elec-
tronic components, sometimes in combinations. However, the core
requirements and issues are similar across all of them, as out-
lined here. In the end, it will be critical to engage other non-
hardware communities to become enthusiastic users and to help
in tool development for these emerging hardware systems. It will

<figure><img src="image_33.png" /><figcaption>**FIG. 22.** Benchmarking and design space for optimization hardware (shown schematically). We expect solver implementations of type (A) that are suitable for quickly finding lower-quality solutions but incapable of reaching higher solution qualities, such as fast but approximate hardware heavily relying on parallel decomposition algorithms and/or imprecise circuits. At the other end of the spectrum are brute-force (complete) approaches (C), e.g., running an algorithm of checking all possible solutions on the conventional high-precision computer, that are slow but guaranteed to find the global optimum. Other approaches (B) may perform better for medium solution quality and time cost. We expect a Pareto front formed by different hardware approaches highlighting that linear improvements in solution comes at exponentially longer hardware times. The figure is motivated by similar dependencies at the algorithmic level (the so-called run-length distribution figures) and similar hardware trade-offs in neuromorphic inference and training.473</figcaption></figure>
only be through continuous feedback between the users, developers, materials scientists, and engineers that a reliable and flexible optimization solver can be developed for large-scale practical problems.

# VIII. TECHNOLOGICAL MATURITY

## A. Current status and next steps

Manuel Le Gallo and Stefano Ambrogio

### 1. Status

The various neuromorphic computing technologies and concepts covered in this roadmap have shown promising results through various prototype chip demonstrations realized by academic and industrial institutions. SRAM-based in-memory computing accelerator chips could demonstrate energy efficiencies >100 TOPS/W for 4-bit matrix-vector multiplications and provide support for all the additional CNN and LSTM inference operations with on-chip digital arithmetic and logic units (ALUs).<sup>474</sup> The recent analog accelerator based on NOR flash memory from Mythic, supporting 80M on-chip analog weights, demonstrated 3.3 TOPS/W system-level energy efficiency for 8-bit calculation precision and could run a pose-detection application while consuming only 3.73 W.<sup>475</sup> While several alternative technologies have recently been explored, such as ferroelectric and magnetic devices, 2D transistors, and memtransistors, the investigations are still at the level of single devices or small arrays, preventing a proper computation performance exploration. For this reason, in non-CMOS based implementations, only the more mature PCM and RRAM emerging technologies have been integrated into multi-core in-memory computing chips and could demonstrate various neural network inference tasks, albeit not fully end-to-end. Near software-equivalent accuracies and energy efficiencies of 10 TOPS/W or higher for matrix-vector multiplications have been reported.<sup>56,173,476,477</sup> Less mature technologies, such as ferroelectric and magnetic memories, have been successfully integrated into small arrays with on-chip data converters.<sup>75</sup> Memories based on spintronic, 2D, and atomistic materials as well as photonic processors based on resistive memories have been mainly investigated at the individual device level or integrated into small arrays without peripheral circuits performing data conversions.<sup>297,312</sup>

Besides chips that aim at accelerating matrix-vector multiplications for deep neural network inference tasks, platforms that can execute more novel neuromorphic computing concepts via in-memory computing have been demonstrated as well. A 64k-cell PCM chip from IBM with in situ learning capability using Spike-Timing-Dependent Plasticity (STPD) and leaky integrate-and-fire neurons performing a simple associative learning task was demonstrated.<sup>478</sup> Another 1.4M-cell PCM chip implementing a restricted Boltzmann machine with STDP learning rule could demonstrate low-power on-chip training and inference on the MNIST dataset.<sup>170</sup> Spiking implementations are also used to efficiently implement Residual Network (ResNET) networks on CIFAR-10.<sup>479</sup> Although those platforms are small prototypes and do not support end-to-end deployment of a variety of models, the key computational blocks

involved in the execution of the algorithms have been successfully integrated on-chip together with the in-memory computing crossbar arrays. Nonetheless, such prototype demonstrations are still far behind the maturity of digital CMOS computing platforms, which support full deployment of a wide variety of models, often with an end-to-end software stack. CMOS neuromorphic computing chips, such as IBM TrueNorth<sup>50</sup> and Intel Loihi,<sup>51</sup> have been made available as research platforms to implement inference and training of spiking neural networks with some software support being provided. Moreover, several digital application-specific deep learning accelerators with an end-to-end software stack, such as Google Tensor Processing Unit, Amazon Inferentia, Facebook's M.2 accelerator, and IBM Artificial Intelligence Unit, have reached a mature state in terms of production and system-level integration.<sup>480</sup>

### 2. Challenges

Several challenges at the device- and system-level could hinder the development of fully end-to-end in-memory computing accelerators. The growing interest in inference tasks, where the neural network is first trained in software and then deployed on-chip to get high throughput (number of inferences per second) and low latency (time to process one input), requires chips with multiple crossbar arrays, to account for multiple layers in neural networks, and reasonably large size, to map extended network layers (e.g., first layers in convolutional networks).<sup>476,481</sup> This leads to several device-level requirements, such as high HRS/LRS resistance ratio, moderate endurance, high retention, and low intrinsic variability. It is also beneficial to have a LRS resistance high enough to limit the impact of the voltage drop in the lines of the crossbar array during writing and readout. Although a single device can be designed to easily meet one of those requirements, the challenge is to build multiple chips each containing multiple arrays of devices that should meet all of them. Because it is rather challenging to simultaneously achieve such specifications with emerging technologies, often trade-offs have to be made depending on the envisaged application. As an example, a lower endurance can be acceptable to achieve trade-offs for a higher HRS/LRS ratio for inference purposes. In addition, several aspects regarding the operating voltages and currents of these devices need to be considered when integrating them into crossbar arrays. Programming voltages in excess of 2 V and large programming currents (>100 µA) necessitate the use of large access transistors that can block this voltage and drive this current. Therefore, minimizing the programming voltages and currents is critical to achieve high device density in the crossbar.

On training chips, where the weights of the neural network are actively changed on-chip to get high-accuracy processing on several tasks (classification and language processing), specifications are higher. In addition to the inference requirements, data need to back-propagate through the network. Such a behavior is critical in analog cores, requiring fully symmetric peripheral circuitry during forward and backpropagation and absence of any polarity dependence of the resistive devices (since each memory element is generally biased in a different way between forward propagation and backpropagation). Clearly, device challenges are different: while inference requires high retention, low drift, and low temperature dependence, training requires high endurance and symmetric conductance update behavior, leading to different material choices.
Moreover, to achieve highly competitive system-level perfor-
mance against existing CMOS-based accelerators, further improve-
ments in device-level precision and compute density are required.⁴⁸²
While this poses material challenges on resistive memories, it
also influences the peripheral circuitry by limiting its available
area while ensuring that it does not restrain precision. In addi-
tion, real workloads involve a variety of different operations other
than matrix-vector multiplications that need to be implemented in
separate digital computing units. Therefore, power-hungry analog-
to-digital conversion is needed at the crossbar outputs, which
limits energy efficiency. Moreover, a fast and flexible communica-
tion scheme together with highly efficient pipelining of the digital
compute units and intermediate SRAM storage is primordial to
ensure that they do not dominate the latency and power con-
sumption. Finally, a user-friendly software-stack that tightly inte-
grates such hardware with common machine learning frameworks
(PyTorch/TensorFlow) is key for its widespread adoption within the
community.

### 3. Potential solutions

The advancement in the field requires a joint development of both material aspects of the memory, algorithms used to train the neural networks, efficient network mapping techniques over multi-ple crossbar arrays, and careful design of the peripheral circuitry. In general, inference/training chips are required to have high-accuracy computation and high energy (operations per energy) and high area (operations per square millimeter) efficiency.

To improve the compute precision up to four or five-bit fixed-
point arithmetic, it is essential to minimize the temporal conduc-
tance fluctuations (such as noise, conductance drift, and temper-
ature dependence). To achieve this, additional materials research,
such as proper incorporation of dopants, memories composed of
multi-layer materials stacks,⁴⁸³ and exploiting material confinement
to change device properties,³⁵⁷ is essential. To improve the com-
pute density, besides scaling both the devices and the associated
access transistors, high-density arrays need to be integrated at the
backend of a CMOS wafer. To decrease the computational time
required to convert the integrated charge/voltage after a Multiply-
and-Accumulate (MAC) operation, column multiplexing should be
avoided, using a per-column circuitry, shrinking the area to accom-
modate Analog-to-Digital Converters (ADCs). Exploration of ADC
designs with a low-number of bits enables efficient integration,
while still keeping a reasonably high MAC accuracy.⁴⁸¹ Another
approach uses fully analog peripheral circuitry, which is more power
efficient,⁴⁷⁶ posing, however, more stringent limitations on compu-
tation precision and available activation functions. As an example,
Rectify Linear Unit (ReLU) has been demonstrated in the analog
domain, while nonlinear sigmoid or tanh generally require digital
processing.

Even in the case of highly efficient crossbar arrays, the gen-
eral performance could still be poor due to Amdahl's law, since
fast analog cores would generate large amounts of data that the
neighboring digital cores need to process.⁴⁸² In other words, highly
efficient analog circuitry would require highly efficient digital blocks
closely located. Therefore, to improve the hybrid analog/digital chip,
spatial network mapping, analog/digital cores, spatial location, and
data communication need to be co-designed, leading to a general
trade-off between chip reconfigurability (ability to map any type

of network) and performance (ability to efficiently process specific
networks).⁴⁸²

### 4. Conclusion

Computing in memory has greatly improved in recent years,
thanks to several on-chip demonstrations. However, challenges need
to be overcome to get to product level, such as 4-to-5 bit comput-
ing precision together with performances in the range of 100/200
TOPS/W. Achieving such specifications is critical to provide a com-
petitive advantage over existing purely digital processing cores. This
will be obtained by optimizing the full computing stack: devices
will require large uniformity, reasonably high resistance levels, and
an overall low noise behavior. Compact peripheral circuitry will be
essential to reduce the chip area, and careful spatial mapping of ana-
log and digital dedicated cores will need to improve the performance
on a variety of neural networks.

## IX. EPILOGUE AND CONCLUDING REMARKS FOR THE ROADMAP

Ilia Valov, Rainer Waser, and Adnan Mehonic

After decades of reliance on transistor-based electronics, we are
now delving into an era where the exploration of innovative nano-
electronic technologies based on functional materials is more crucial
than ever. For instance, nanoscale memristive devices have emerged
as key components for future nanoelectronics. Their straightforward
stack structure, diverse functionalities, and specific benefits, such
as scalability, broad temperature stability and operation range, and
resilience to high-energy particles and electromagnetic interference
make them indispensable for numerous applications. Furthermore,
memristors and similar novel technologies now serve as founda-
tional units for the next generation of brain-inspired computing
architectures. From their introduction in the 1960s as resistive
switching memories, through the relation to Chua's memristor and
their use as artificial neurons and synapses at present, memristive
devices have passed decades of intensive research with respect to
both fundamentals and applications by academia and industry.

Examining the foundational aspects of materials science is piv-
otal for developing new nanoelectronic technologies. Using mem-
ristive technology as an example, the appeal of memristive devices
stems from the multitude of benefits they provide, which are influ-
enced and modulated by the materials and processes that dic-
tate their behavior and functionalities. Here, the relation between
materials, material properties, physicochemical processes, and func-
tionalities should be particularly highlighted. A huge spectrum of
materials has been used for switching films—1D (single molecules
or molecular clusters), 2D (graphene, hBN, MoS₂, MoSe₂, etc.), and
3D, including inorganic, organic, and biomaterials. Several physical
phenomena were reported to lead to memristive behavior—phase
change, redox reactions and ionic transport, electronic effects, van
der Waals forces, and magnetic and magneto-resistance changes, all
covered in this roadmap.

All different phenomena, of course, depend strongly on the
used materials. The main challenge appears to properly select a
combination of appropriate materials and their dimensions (i.e.,
thickness and lateral scale). Apparently, a simple two-electrode cell
is composed of a switching layer or in many cases more switching layers, two electrodes, and capping film(s). The devices are exposed to extreme operating conditions, such as current densities of up to 1 × 10⁶ A per square centimeter and electric fields of 10⁸ V/m. Due to these extreme conditions and the nano-dimensions of the films, their thermodynamic and kinetic behaviors typically deviate strongly from their macroscopic counterparts going much beyond the frame of the classical knowledge in terms of chemical and mechanical stability, point defect chemistry, and transport properties. The nano-size effects are especially prominent considering the switching films. These are typically materials that, in a macroscopic sense, are insulators, which are sometimes used as high-k dielectrics, but turn into mixed solid electrolytes at thicknesses below ~50 nm. Furthermore, due to enhanced surface energy excess, the layers react chemically within the stack even if the change in the Gibbs energy for the reaction is positive. As a result, intermediate films can be formed, with similar thicknesses as the switching layers, which can either inhibit or enhance charge and mass transport through interfaces, strongly influencing all related processes. Other effects caused by impurities, absorption of moisture and/or oxygen, local changes of concentrations, and nanocavities are known to additionally complicate the control over the device's behavior and characteristics. This poses a challenge, yet also presents an opportunity to uncover unique device physics and explore alternative device functionalities (e.g., neuromorphic functionalities).

The way to keep control over the devices and to further expand the horizon of functionalities is by using a materials science-based approach where materials properties and processes are studied in very detail, and this knowledge should be applied in the design of the devices.

The “Roadmap to Neuromorphic Computing with Emerging Technologies” roadmap seeks to tackle these issues and present a contemporary perspective on the intersections between current materials science, electronic engineering, and system design. Its ultimate goal is to delve into alternative computing models, particularly brain-inspired (neuromorphic) computing. Eminent groups and experts span a wide spectrum of relevant subjects and technologies, fostering a platform for idea exchange. In addition, they highlight next-generation neuromorphic hardware, emphasizing the foundational role of functional materials and innovative device technologies. Although materials have been the main focus of the roadmap, our aim was to provide a more holistic overview and highlight a range of emerging and highly active research areas. As such, there are many details and specific material considerations not covered here that we strongly recommend the authors explore in the extensive background literature, much of which is published in special issues¹³,⁴⁸⁴⁻⁴⁸⁶ or excellent reviews.⁸,¹² Likewise, in order to keep the format of the roadmap relatively compact, we have not elaborated on a number of equally valid and highly promising approaches in the context of neuromorphic technology development. Some notable examples include adaptive matters and computation based on disorder,³¹,⁵,⁴⁸⁷ systems based on organic perovskites,⁴⁸⁸,⁴⁸⁹ ionic-liquid based devices,⁴³²,⁴⁹⁰ and molecular devices.⁵³,⁴⁹¹,⁴⁹² Of course, the list is not exhaustive, and other approaches, physical systems, and technologies are emerging.

Likewise, in order to keep the format of the roadmap in a relatively compact form, we have not elaborated on a number of

equally valid and highly promising approaches in the context of neuromorphic technology development.

It is natural to ask what needs to happen next for neuromorphic technologies to find their way into real-world applications. Unsurprisingly, this is a complex question and heavily depends on the definition of neuromorphic and the specific application in question. In a broader sense, the integration of memory within (in-memory compute) or closer to the compute units will likely be the first step. A prime example of this is within the context of embedded systems, which are in dire need of better, more scalable non-volatile memory technology. Many memristive technologies are well-positioned to meet this demand. Among these, the most successful will likely be the technology that is the most practical (e.g., easy to embed on the same CMOS die), cost-effective, and, of course, higher performing (e.g., scalable beyond the 28 nm limit of current NOR flash, faster, more energy-efficient, and reliable with a low bit error rate). While replacing NOR flash may not be strictly neuromorphic, it will be an important step in providing better platforms to test energy-efficient neuromorphic approaches. The next step could be the development of true in-memory compute, specifically analog, with the primary goal of providing more efficient linear algebra accelerators (specifically matrix-vector multipliers). This would accelerate neural network inference engines, both in speed and in energy efficiency, and benefit other applications, such as combinatorial optimization and security. In the context of new nanoelectronic devices and analog in-memory computing, the main challenge is to achieve not only two well-separated digital states but also fully gradual analog state programmability. Variability and retention thus become significant challenges that need to be addressed. Beyond, for any analog approach to make sense, honest system-level benchmarking must be conducted, alongside an analysis of which specific target applications this approach would best serve. One of the main open questions is the translation of analog to digital signals and vice versa. This conversion process could be more costly than compute alone and might lead to overall inefficiencies compared to fully digital implementations.

Perhaps, the first two examples are not truly neuromorphic, so the next exploration, which genuinely seeks inspiration from the working principles of the human brain, involves technologies and systems aiming to implement key neurobiological features directly in hardware, whether synaptic or neuronal functionality. Other functionalities, such as dendritic operations, have also been explored. In this context, device functionalities that might typically be seen as less useful in conventional digital or analog in-memory computing may prove very helpful. For example, the volatility of states is an important feature for implementing many neuromorphic functionalities (e.g., short-term plasticity, spiking, eligibility traces, and reservoir computing).

A useful way to consider the next steps in developing neuromorphic hardware technologies is to categorize them into short-term goals (2–3 years: merging novel non-volatile memory and compute for digital systems/fabricating them on the same die at advanced processing nodes), mid-term goals (3–5 years and beyond: analog compute), and long-term goals (truly neuromorphic functionalities). While it is difficult to predict when these milestones might be reached, the first steps are already evident with MRAM, RRAM, and PCM finding their way into product offerings (e.g.,
microcontrollers with novel non-volatile memories). Recent impressive results suggest that some analog systems may be more widely utilized in the next 3-5 years, while truly neuromorphic technologies might initially be implemented in specific scenarios before achieving broader adoption (e.g., spiking systems to implement smart vision cameras). The latter two predictions still remain highly speculative.

Recommending the most promising material systems is a complex task. In general, RRAM technology might have an advantage due to its simplicity and CMOS-friendliness. However, recent developments in HfO₂-based FeRAMs represent a highly active area of research. MRAM is likely the most mature technology, with already available products, while PCM has seen significant interest recently. 2D materials are expected to integrate with all these technologies, providing further device improvements. It is important to keep in mind that the requirements might be dramatically different depending on targeted applications. For embedded systems, ease of integration and full CMOS compatibility are likely the most important factors. Conventional NVM devices need to outperform flash, while in the context of computing, higher endurance will likely be needed. In addition, the requirements for less conventional analog or neuromorphic functionalities are somewhat less defined but equally relevant and in development. One should also bear in mind the gap that exists between academic research on proof-of-concept demonstrators and industrial R&D. Industrial R&D must consider not only technical factors but also economic feasibility.⁴⁹³

Neuromorphic technologies are undoubtedly poised to be strong contenders for the future of computing, whether based on conventional digital, analog, or conceptually different computing and signal processing paradigms.

## ACKNOWLEDGMENTS

We would like to express our sincere gratitude to Prof. Judith Driscoll, former Editor-in-Chief of APL Materials, for her invaluable efforts in the early stages of shaping and organizing this roadmap.

## AUTHOR DECLARATIONS

### Conflict of Interest

Anthony Kenyon is Founder, Director, and CSO of Intrinsic Semiconductor Technologies Ltd. Adnan Mehonic is Founder and CTO of Intrinsic Semiconductor Technologies Ltd.

### Author Contributions

**Adnan Mehonic:** Conceptualization (lead); Project administration (lead); Supervision (lead); Writing – original draft (lead); Writing – review & editing (lead). **Daniele Ielmini:** Conceptualization (lead); Supervision (equal); Writing – original draft (equal); Writing – review & editing (equal). **Kaushik Roy:** Conceptualization (lead); Supervision (equal); Writing – original draft (equal); Writing – review & editing (equal). **Onur Mutlu:** Writing – original draft (equal); Writing – review & editing (equal). **Shahar Kvatinsky:** Writing – original draft (equal); Writing – review & editing (equal). **Teresa Serrano-Gotarredona:** Writing – original draft (equal); Writing – review & editing (equal). **Bernabe Linares-Barranco:** Writing – original draft (equal); Writing – review & editing (equal). **Sabina Spiga:** Writing – original draft (equal); Writing – review & editing (equal). **Sergey Savel'ev:** Writing – original draft (equal); Writing – review & editing (equal). **Alexander G. Balanov:** Writing – original draft (equal); Writing – review & editing (equal). **Nitin Chawla:** Writing – original draft (equal); Writing – review & editing (equal). **Giuseppe Desoli:** Writing – original draft (equal); Writing – review & editing (equal). **Gerardo Malavena:** Writing – original draft (equal); Writing – review & editing (equal). **Christian Monzio Compagnoni:** Writing – original draft (equal); Writing – review & editing (equal). **Zhongrui Wang:** Writing – original draft (equal); Writing – review & editing (equal). **J. Joshua Yang:** Writing – original draft (equal); Writing – review & editing (equal). **Ghazi Sarwat:** Writing – original draft (equal); Writing – review & editing (equal). **Syed Abu Sebastian:** Writing – original draft (equal); Writing – review & editing (equal). **Thomas Mikolajick:** Writing – original draft (equal); Writing – review & editing (equal). **Stefan Sleseazeck:** Writing – original draft (equal); Writing – review & editing (equal). **Beatriz Noheda:** Writing – original draft (equal); Writing – review & editing (equal). **Bernard Dieny:** Writing – original draft (equal); Writing – review & editing (equal). **Tuo-Hung (Alex) Hou:** Writing – original draft (equal); Writing – review & editing (equal). **Akhil Varri:** Writing – original draft (equal); Writing – review & editing (equal). **Frank Brückerhoff-Plückermann:** Writing – original draft (equal); Writing – review & editing (equal). **Wolfram Pernice:** Writing – original draft (equal); Writing – review & editing (equal). **Xixiang Zhang:** Writing – original draft (equal); Writing – review & editing (equal). **Sebastian Pazos:** Writing – original draft (equal); Writing – review & editing (equal). **Mario Lanza:** Writing – original draft (equal); Writing – review & editing (equal). **Stefan Wiefels:** Writing – original draft (equal); Writing – review & editing (equal). **Regina Dittmann:** Writing – original draft (equal); Writing – review & editing (equal). **Wing H. Ng:** Writing – original draft (equal); Writing – review & editing (equal). **Mark Buckwell:** Writing – original draft (equal); Writing – review & editing (equal). **Horatio R. J. Cox:** Writing – original draft (equal); Writing – review & editing (equal). **Daniel J. Mannion:** Writing – original draft (equal); Writing – review & editing (equal). **Anthony J. Kenyon:** Writing – original draft (equal); Writing – review & editing (equal). **Yingming Lu:** Writing – original draft (equal); Writing – review & editing (equal). **Yuchao Yang:** Writing – original draft (equal); Writing – review & editing (equal). **Damien Querlioz:** Writing – original draft (equal); Writing – review & editing (equal). **Louis Hutin:** Writing – original draft (equal); Writing – review & editing (equal). **Elisa Vianello:** Writing – original draft (equal); Writing – review & editing (equal). **Sayeed Shafayet Chowdhury:** Writing – original draft (equal); Writing – review & editing (equal). **Piergiulio Mannocci:** Writing – original draft (equal); Writing – review & editing (equal). **Yimao Cai:** Writing – original draft (equal); Writing – review & editing (equal). **Zhong Sun:** Writing – original draft (equal); Writing – review & editing (equal). **Giacomo Pedretti:** Writing – original draft (equal); Writing – review & editing (equal). **John Paul Strachan:** Writing – original draft (equal); Writing – review & editing (equal). **Dmitri Strukov:** Writing – original draft (equal); Writing – review & editing (equal). **Manuel Le Gallo:** Writing – original draft (equal); Writing – review & editing (equal). **Stefano Ambrogio:** Writing – original draft (equal); Writing – review & editing (equal). **Ilia Valov:** Writing – original draft (equal); Writing – review & editing (equal).
Writing – review & editing (equal). **Rainer Waser**: Writing – original draft (equal); Writing – review & editing (equal).

DATA AVAILABILITY

Data sharing is not applicable to this article as no new data were created or analyzed in this study.

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## AFFILIATIONS

¹Department of Electronic and Electrical Engineering, UCL, Torrington Place, London WC1E 7JE, United Kingdom

²Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Piazza L. da Vinci 32, 20133 Milano, Italy

³School of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana 47907, USA

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<footnote n="494">⁴⁹⁴E. J. Fuller, S. T. Keene, A. Melianas, Z. Wang, S. Agarwal, Y. Li, Y. Tuchman, C. D. James, M. J. Marinella, J. J. Yang, A. Salleo, and A. A. Talin, *Science* **364**, 570 (2019).</footnote>
⁴Department of Information Technology and Electrical Engineering, ETH Zurich, Gloriastrasse 35, 8092 Zurich, Switzerland

⁵Andrew and Erna Viterbi Faculty of Electrical and Computer Engineering, Technion–Israel Institute of Technology, Haifa 3200003, Israel

⁶Instituto de Microelectrónica de Sevilla (IMSE-CNM), CSIC and University of Seville, Avda. Américo Vespucio 28, 41092 Seville, Spain

⁷CNR-IMM Unit of Agrate Brianza, Via C. Olivetti 2, 20864 Agrate Brianza (MB), Italy

⁸Department of Physics, Loughborough University, Epinal Way, Loughborough LE11 3TU, United Kingdom

⁹STMicroelectronics, Knowledge Park III, Greater Noida 201304, India

¹⁰STMicroelectronics S.p.A., System Research and Application, Via Tolomeo 1, 20010 Cornaredo (MI), Italy

¹¹Ming Hsieh Department of Electrical and Computer Engineering, University of Southern California, Los Angeles, California 90089, USA

¹²IBM Research Europe, Säumerstrasse 4, 8803 Rüschlikon, Switzerland

¹³NaMLab gGmbH, Nöthnitzer Stasse. 64a, 01187 Dresden, Germany

¹⁴Institute of Semiconductors and Microsystems, TU Dresden, 01062 Dresden, Germany

¹⁵Zernike Institute for Advanced Materials and CogniGron Center, University of Groningen, Nijenborgh 4, 9747 AG Groningen, The Netherlands

¹⁶CEA, CNRS, SPINTEC, Univ. Grenoble Alpes, rue des Martyrs, 38000 Grenoble, France

¹⁷Institute of Electronics, National Yang Ming Chiao Tung University, 1001 University Road, Hsinchu 30010, Taiwan

¹⁸Institute of Physics, University of Münster, Heisenbergstraße 11, 48149 Münster, Germany

¹⁹Physical Science and Engineering Division, King Abdullah University of Science and Technology (KAUST), Thuwal 23955-6900, Saudi Arabia

²⁰Department of Materials Science and Engineering, National University of Singapore, Singapore 117575, Singapore

²¹Peter Grünberg Institute 7, Forschungszentrum Jülich GmbH, 52428 Jülich, Germany

²²The Alan Turing Institute, British Library, 96 Euston Road, London NW1 2DB, United Kingdom

²³School of Integrated Circuits, Peking University, Beijing 100871, China

²⁴CNRS, Centre de Nanosciences et de Nanotechnologies, Université Paris-Saclay, 91120 Palaiseau, France

²⁵CEA LETI, MINATEC Campus, 17 rue des Martyrs, Grenoble 38054, France

²⁶Institute for Artificial Intelligence and School of Integrated Circuits, Peking University, No. 5 Yiheyuan Road, Haidian District, Beijing 100871, China

²⁷Hewlett Packard Labs, 820 N McCartney Rd., Milpitas, California 95035, USA

²⁸Peter Grünberg Institute (PGI-14) for Neuromorphic Compute Nodes, Forschungszentrum Jülich GmbH, 52428 Jülich, Germany

²⁹Faculty of Electrical Engineering, RWTH Aachen University, 52062 Aachen, Germany

³⁰Department of Electrical and Computer Engineering, University of California, Santa Barbara, California 93106, USA

³¹IBM Research-Almaden, 650 Harry Road San Jose, California 95120, USA

³²Peter Gruenberg Institute 7 (PGI7) and JARA-FIT Research Centre, Juelich, Wilhelm-Johnen-Straße, 52425 Juelich, Germany

³³Institute of Electrochemistry and Energy Systems, Bulgarian Academy of Sciences, “Acad. G. Bonchev” Str. No. 10, 1113 Sofia, Bulgaria

³⁴Institute of Materials in Electrical Engineering and Information Technology 2 (IWE2), RWTH Aachen University, D-52056 Aachen, Germany

<footnote>a) Author to whom correspondence should be addressed: adnan.mehonic.09@ucl.ac.uk</footnote>