# Real-time energy-efficient software and hardware implementations of a QCSP communication system

Camille Monière, Bertrand Le Gal, Emmanuel Boutillon

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Camille Monière, Bertrand Le Gal, Emmanuel Boutillon. Real-time energy-efficient software and hardware implementations of a QCSP communication system. Journal of Systems Architecture, 2023, 141, pp.102933. 10.1016/j.sysarc.2023.102933. hal-04406481

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# Real-Time Energy-Efficient Software and Hardware Implementations of a QCSP Communication System

Camille Monière · Bertrand Le Gal · Emmanuel Boutillon

the date of receipt and acceptance should be inserted later

**Abstract** In the Internet of Things, the energy efficiency of communications is crucial. Thus, using data-less preambles to detect frames is suboptimal. A preamble-less physical layer named “Quasi-Cyclic Short Packet (QCSP)” proposed a solution. However, the high computational complexity of the receiver makes the implementation challenging. This paper studies the feasibility and efficiency of real-time software and hardware QCSP systems. Several highly efficient transmitter implementations are presented, demonstrating the relevance of the approach. The parallelization and optimization strategies are elaborated for both software and hardware receiver implementations. They allowed software implementations with throughputs above 50 kb/s (maximum for the LoRa standard), consuming as low as 27 µJ/b. Thanks to detailed algorithm refinements, the throughput even exceeded 250 kb/s on FPGA using High-Level Synthesis methodology, for an estimated consumption of 3.9 µJ/b. The results support the viability of the QCSP approach for cloud-RAN and edge computing in Low-Power Wide-Area Networks.

**Keywords** Real-Time Implementation · CCSK · Small Packets · Hardware · Software · Low Power Wide Area Network.

This work is funded by the French National Research Agency, grant ANR-19-CE25-0013-01, part of the project entitled Quasi-Cyclic Short Packet (QCSP). Website: https://qcsp.univ-ubs.fr/

## 1 Introduction

The transmission of a small amount of data in an unsupervised communication network is a real challenge, especially in the context of the Internet of Things (IoT).

In an unsupervised IoT network, the payload, i.e., the information to be transmitted, cannot be sent as-is. It would be lost during the transmission. In such a network, the payload is typically embedded in a frame, with additional redundancy to improve error tolerance. The redundancy is generated using Error-Correcting Codes (ECCs) [2, 6, 11]. The payload and its redundancy are preceded by a predefined pilot sequence, also called a preamble. This preamble often takes the form of a known pattern, in the time domain or even in the frequency domain. This known pattern is then searched for and is used to detect and synchronize a potential incoming frame in reception. In traditional contexts, the payload size far exceeds that of the preamble. For instance, in Wi-Fi, the preamble never represents more than 4.3% of the data frame transmission time [35]. Unfortunately, for short packets, the preamble bandwidth consumption is no longer negligible, sometimes being bigger than the payload itself. Indeed, preamble-based methods allow for simplifying the receiver system design, leveraging prior knowledge of the received waveform. The drawback is that energy and resources allocated to preamble transmission are reserved. From the communication perspective, they are lost [32]. As an example, in the IoT-oriented 5G standard entitled massive Ultra-Reliable Low-Latency Communications (mURLLC), preambles already consume a significant amount of bandwidth and energy [14]. Preamble-less strategies for transmission of short packets exist in the

<footnote>C. Monière, E. Boutillon: Lab-STICC, CNRS UMR 6255, University of South Brittany, 56100 Lorient, France, Email: firstname.lastname@univ-ubs.fr · C. Monière, B. Le Gal: IMS, CNRS UMR 5218, Bordeaux-INP, 33400 Talence, France, Email: firstname.lastname@ims-bordeaux.fr</footnote>
literature [4, 7, 46], and have been already explored. However, their efficiency has only been demonstrated for a signal energy per symbol above the noise level, resulting in a positive Signal-to-Noise Ratio (SNR) in dB.

A recently introduced preamble-less physical layer called Quasi-Cyclic Short Packet (QCSP) [37] is proven to work at very low SNR. The performance reported in [37] shows that communications are reliable at an SNR of -10 dB, and can be successful even down to -20 dB. These SNRs are similar to those reached by established solutions in the IoT context [17]. A QCSP frame is based on the association of a Cyclic Code Shift Keying (CCSK) modulation and a non-binary ECC. Moreover, the proposed algorithm is robust to frequency inaccuracies. These characteristics are appreciable since they ease the use of low-cost Software-Defined Radio (SDR) platforms, decreasing the design time required. Indeed, SDR devices allow exploring different setups with the same hardware. Some even allow rapid prototyping on embedded FPGAs, like Universal Software-defined Radio Peripheral (USRP) from Ettus Research [8, 23, 33].

From an implementation standpoint, the QCSP waveform requires low computational power and has a small memory footprint on the transmitting side. These are key features for IoT devices, that are constrained by their power usage. Indeed, they often operate on battery. The drawback is an increase in complexity of the detection and synchronization tasks in reception. Although expected, due to the lack of a preamble, the implementation of a real-time receiver becomes challenging.

In [27], the authors describe a QCSP frame detection method using the principle of time sliding windows. They compare this time sliding method with the legacy method, based on the usage of Fast Fourier Transforms (FFTs) [38]. They also give

early results of software implementation to show the relevance of the method. This work is enhanced in [26], where the authors explore the implementation opportunities offered by the algorithm. The authors propose improvements to the receiver architecture, and present the associated performance results, for both software and hardware implementations. This paper aims to both extend and refine the work presented in [26]. This paper provides the following additional content:

- An extensive presentation of the algorithms and the proposed improvements, giving better insights than in [26].

- A new implementation approach for the necessary correlations in software is also presented. This approach is demonstrated to outperform the previous one on multicore devices, with throughputs about 1.5× higher.

- The source codes have been reworked, allowing us to report the results for both the same benchmarking platform as in [26], and another low-power platform. This offers a broader overview of the context.

- In addition, the energy consumption of each method is studied for each platform, demonstrating the efficiency of the approach.

The article is structured as follows. Section 2 first presents the system model and then exposes the detection methods presented in [27]. Section 3 details all the algorithmic variations available for the detector, estimating and comparing their respective computational complexities, as well as their specificities. In section 4, the parallelization schemes applicable to each evaluated detection approach are analyzed and put in relation with parallelization features available on the different targets. The results coming from the transmitter and the detector implementations on CPUs and FPGAs are reported and explained in section 5. Finally, conclusions and perspectives are discussed in section 6.

<figure><img src="image_3.png" /><figcaption>Fig. 1: Modelling of the QCSP communication chain.</figcaption></figure>
## 2 System Model

This section reviews the complete communication system and the associated detection method presented in [27]. First, the QCSP frame is introduced. Then, transmitter and receiver functioning is explained. From now on and to lighten notations, a bold letter denotes a vector while a scalar from this vector is derived as the normal letter, potentially indexed, e.g., $\forall n \in \mathbb{N}$, $a(n) \in \mathbf{a}$.

### 2.1 QCSP Communication Chain

The complete communication system is depicted in Fig. 1. The message $\mathbf{M}$ sent is composed of $K$ symbols of $p$ information bits, each symbol being in $\llbracket 0, q-1 \rrbracket$, with $q = 2^p$ and $p \in \mathbb{N}$. The message is first encoded using a Non-Binary Low-Density Parity-Check (NB-LDPC) encoder over the Galois Field GF($q$) into a codeword $\mathbf{C}$. The resulting codeword $\mathbf{C}$ contains $N$ symbols of $p$ bits, resulting in a code rate $R_c = K/N$. The QCSP chain uses NB-LDPC codes because they ensure better performance when used with short packets than their binary counterparts [11]. The non-binary symbols are then CCSK modulated, using the circular shifts of a binary Pseudo-random Noise (PN) sequence $\mathbf{P}_0$ [12]. Let us define $\mathbf{P}_k$ as $\mathbf{P}_0$ shifted circularly $k$ times, such that

$$ \mathbf{P}_k(i) = \mathbf{P}_0(k + i \bmod q). \quad (1) $$

This modulation scheme has thus a modulation rate $R_m = p/q$. The conjunction of the code rate and the modulation rate gives an effective rate $R_{eff} = K \times p / N \times q$. The CCSK frame $\mathbf{F}_{CCSK}$ of $N \times q$ chips obtained is modulated using Binary Phase-Shift Keying (BPSK) and over-modulated [38]. Overmodulation adds a frame-level phase information, allowing blind symbol synchronization on the receiving side. This creates a QCSP frame $\mathbf{F}$ of $N \times q$ chips, which is finally filtered by a half-raised cosine filter. The QCSP frame is then sent to an RF front-end for transmission. On the receiver side, chips are oversampled by a factor $O \ge 2$ to satisfy the Nyquist-Shannon theorem [40], resulting in $O$ samples per chip. The sample stream is filtered by a complementary half-raised cosine filter, and is split into $O$ parallel decimated streams. Each decimated stream feeds an independent detector, i.e., $O$ detectors work parallelly, one per sampling hypothesis. Each detector uses CCSK-based detection, described in [38] and summarized in the next subsection. If detection occurs, data associated with the highest-scoring oversampling hypothesis are gathered into a detected frame $\mathbf{F}_D$. The detected frame $\mathbf{F}_D$ is passed

to the synchronization stage of the receiver. The synchronization stage computes an estimation of any frequency, time, or phase inaccuracies, to mitigate them. The now synchronized frame $\mathbf{F}_S$ of $N$ symbols of $q$ chips is CCSK demodulated, which mainly consists of the correlation symbol-by-symbol with $\mathbf{P}_0$ [9], denoted with the operator $\star$. This produces $N \times q$ Log-Likelihood Ratios (LLRs) that are fed to an NB-LDPC decoder. The decoder corrects potential communication errors and outputs the estimated message $\mathbf{M}'$ of $K \times p$ bits.

### 2.2 CCSK-Based Detection

CCSK-based detection mainly consists in computing and comparing the output of a score function to a threshold value $U_0$. For one sampling hypothesis, the score is computed using the last $N \times q$ received samples (i.e., the length of a frame) at the time $n$. If the score value exceeds the threshold $U_0$, a new frame arrival is assumed.

The score function $S_n^\omega$ can be seen as a filter, the output of which is maximized for a frame that arrived at the time $n$ with a frequency offset $f = \omega / (2\pi q)$. The received “frame” of $N \times q$ samples is equally divided into $N$ sub-vectors $\mathbf{y}_n$. $\mathbf{y}_n$ is the vector of $y(n - i)$ for $i \in \llbracket 0, q-1 \rrbracket$ of $q$ samples. The first step in score calculation consists of the mitigation of the frequency offset. To achieve this, $\mathbf{y}_n$ is multiplied term by term (operator $\odot$) with a rotation vector $\mathbf{\Gamma}_n^\omega$, defined such that for all $k \in \llbracket 0, q-1 \rrbracket$,

$$ \mathbf{\Gamma}_n^\omega(k) = e^{-j \frac{(n-k)\omega}{q}}, \quad (2) $$

i.e., a pure complex sinusoidal of frequency $-\omega / (2\pi q) = -f$. This operation gives $\mathbf{y}_n^\omega = \mathbf{y}_n \odot \mathbf{\Gamma}_n^\omega$. A correlation vector $\mathbf{L}_n^\omega$ is then computed, as

$$ \mathbf{L}_n^\omega = (\mathbf{y}_n \odot \mathbf{\Gamma}_n^\omega) \star \mathbf{P}_0. \quad (3) $$

This vector is similar to an attempt of CCSK demodulation. The maximum absolute value of $\mathbf{L}_n^\omega$ is normalized by the 2-norm $\mathcal{L}_2$ of $\mathbf{y}_n$ [27], to be immune to input scaling factors. The result, denoted $M_n^\omega$, is taken as an indicator of the demodulation success. In summary, $M_n^\omega$ results from

$$ M_n^\omega = \frac{\max\{|\mathbf{L}_n^\omega(i)|, i \in \llbracket 0, q-1 \rrbracket\}}{\sqrt{\sum_{i=0}^{q-1} |y(n-i)|^2}}. \quad (4) $$

The score $S_n^\omega$ results from the accumulation of $M_n^\omega$ through an averaging filter of size $N$, the size of a frame, i.e.

$$ S_n^\omega = S_{n-q}^\omega + M_n^\omega - M_{n-Nq}^\omega, \quad (5) $$
<figure><img src="image_4.png" /><figcaption>Fig. 2: Score functions, with $N = 8$ symbols, $p_{\Delta} = q = 64$, a frame arriving at $\Delta = -N \times q = -512$ chips, an SNR of $-7$ dB, for four different values of $\omega$, and depending on $\Delta$. For readability purposes, the number of points has been halved.</figcaption></figure>

In [27], the resulting score $S_n^\omega$ is compared to a threshold $U_0$. So, the square roots involved in the modulus of $|L_n^\omega(i)|$ and in the denominator in (4) can be removed, thus simplifying the score function, provided that a new threshold $\bar{U}_0$ is used. This is performed by using $\bar{M}_n^\omega$ defined as

$$ \bar{M}_n^\omega = \frac{\max\{|L_n^\omega(i)|^2, i \in [0, q-1]\}}{\sum_{i=0}^{q-1} |y(n-i)|^2} = (M_n^\omega)^2. \quad (6) $$

The new score function remains mainly the same but using $\bar{M}_n^\omega$ instead of $M_n^\omega$, i.e.,

$$ \bar{S}_n^\omega = \bar{S}_{n-q}^\omega + \bar{M}_n^\omega - \bar{M}_{n-Nq}^\omega. \quad (7) $$

The detection performance of the two approaches has been measured using Monte-Carlo simulations, and they are the same, i.e., they result in the same $P_{FA}$ and $P_{MD}$. Indeed, the square function is continuous, strictly positive, and strictly increasing over $\mathbb{R}^+$, and $\forall n \in \mathbb{N}$, $M_n^\omega \in \mathbb{R}^+$. Thus, the score values with and without a frame are similarly impacted, as are their statistical expectations. Considering that the detection performance can be simplified as the difference between the score expectation without a frame, and the score expectation with a frame<fnref n="1" />, the results from the Monte-Carlo simulations were expected. A new threshold can be calculated from $U_0$ as $\frac{U_0^2}{N}$. To lighten notations, and

considering the interchangeability of the square and not square method, only $S_n^\omega$ and $M_n^\omega$ are used in the following.

## 2.3 Score Grid

An example of the score function output through time is represented in Fig. 2, for an SNR of $-7$ dB, for several frequency offsets represented as resulting symbol rotations $\omega$. The figure presents how the score evolves depending on $\Delta$, the distance to the perfect time synchronization. When $\Delta = 0$ chip, it means that the last chip of the frame has arrived. Thus, the beginning of the frame can be estimated from $\Delta$ using $\Delta - N \times q + 1$ chips. Note that 8 local maximums are observable from $\Delta = -512$ to 0 chips, which results from the size $N = 8$ of the frame in symbols. The detection probability depends on whether the score exceeds $U_0$ or not. This representation stresses out that the score $S_n^\omega$ must be computed for each new received “symbol” of $q$ samples. Indeed, such “symbol” reception results in a local maximum on the figure, i.e., for $\Delta = -256, -198$, and so on every 64 chips. In the context of the figure, to achieve a bit rate of 100 kb/s assuming an effective rate $R_{eff} = \frac{1}{32}$, one must compute $\frac{100 \times 10^3}{R_{eff}} \times q = \frac{100 \times 10^3}{32} \times 64 = 50 \times 10^3$ scores per second. A lower resolution would result in overlooking parts of the input signals. It ensures the lost of some maxima in Fig. 2. Computing it less often does reduce computational complexity, but it results in performance losses unaffordable at lower SNRs, like $-10$ dB. In contrast, the score can be computed up to $q$ times more, i.e., for each new sample, to increase detection performance. It leads to the introduction of the parameter $p_{\Delta}$, power of 2 indicating the number of score values computed every $q$ samples for one rotation $\omega$, i.e., $p_{\Delta} = 2^l$ for $l \in [0, p]$. It should be noted that it may also impact the memory usage, since only $N \times p_{\Delta}$ values of $M_n^\omega$ are needed. It has not been thoroughly studied in the paper, but the impact on complexity is given in section 3.2.

As seen in Fig. 2, frequency inaccuracies that result in signal rotation can annihilate detection performance. In Fig. 2, nothing is detected when $\omega = \pi$ and $\omega = 2\pi$. As a mitigation, multiple scores $S_n^\omega$ for different values of $\omega$ are computed in parallel. The number of rotation hypotheses tested in parallel in the interval $[-\pi, \pi]$ is denoted $p_\omega$. It can range from 1 to theoretically any natural integer, but is limited to 8 in practice. Indeed, the gain in detection performance is minimal regarding the resulting cost in complexity for higher values. This is supported by the overview of the effect of the couple $(p_\Delta, p_\omega)$ on the detection

<footnote n="1">¹ In [37], the author provides an extensive mathematical analysis of the QCSP detection theory.</footnote>
<figure><img src="image_5.png" /><figcaption>Fig. 4: ROC curves for different values of the couple $(p_\omega, p_\Delta)$ with $N = 60$, $q = 64$ and an SNR of -10 dB.</figcaption></figure>

performance presented in [27] and summarized using the Receiver Operating Characteristics (ROC) curves in Fig. 4. Such curves are obtained by plotting the $P_{MD}$ as a function of the $P_{FA}$. The more a curve is in the bottom-left corner, the better. In a nutshell, these results demonstrate that increasing $p_\omega$ and $p_\Delta$ allows improving detection performance indeed, but not linearly. For instance, starting from $(p_\omega, p_\Delta) = (2, 8)$, it is more efficient to first increase $p_\omega$ from 2 to 8, then to increase $p_\Delta$ from 8 to 16, rather than only increasing $p_\Delta$ to 64. Both modifications have a similar impact on computational complexity. The product $p_\omega p_\Delta$, a good complexity estimator as the overall number of hypotheses computed, is increased from 16 to 128 in both cases. However, the performance gain is around two decades greater in the first case. This figure also demonstrates that a $P_{md} < 10^{-4}$ is achievable for a $P_{fa} = 10^{-6}$.

The structure that allows computing a score $S_n^\omega$ is given in Fig. 3, and is called a Score Processing

Unit (SPU). The two existing SPU architectures are summarized in the next section.

## 3 Score Processing Unit (SPU)

The generic representation of an SPU is given in Fig. 3. The “buffer” in the figure is a block that consumes each $y(n)$ in input and output a vector $y_n$ of $q$ chips every $\frac{q}{p_\Delta}$ chip. The most compute-intensive part of an SPU is the correlation, represented by the $\star P_0$ in Fig. 3, and in (3). This is the function fulfilled by the Correlation Unit (CU). Two CU variations exist, and are described in the following.

### 3.1 Score Processing Unit Variations

The legacy method [38] to compute this correlation is depicted in Fig. 5, and can be expressed as

$$L_n^\omega = \mathcal{F}^{-1}(\mathcal{F}(y_n \odot \Gamma^\omega) \odot \mathcal{F}(P_0)^*), \quad (8)$$

with $\mathcal{F}(x)$ denoting the FFT of $x$ and $\mathcal{F}^{-1}(X)$ denoting the IFFT of $X$. Such CU is called an FFT Correlation Unit (FCU). This method, although proven and well documented, is not well suited for continuous processing of incoming samples due to its computational complexity. Indeed, to achieve the best performance, i.e., for $p_\Delta = q$, the $q$ long FFT and IFFT must be reprocessed for each arriving chip. The exception is the FFT of $P_0$ which is constant, and can be precomputed and stored in memory. One has to lower $p_\Delta$ to lessen the computation complexity, at the expense of detection performance.

In [27], the authors introduce an optimized method to compute the correlations. This approach leverages the fact that a new correlation in the time domain is, in fact, the last correlation plus the value associated with the newest chip and minus the oldest one, resulting in a Time Sliding (TS) window. The correlation is thus computed using

$$L_n^\omega(k) = L_{n-1}^\omega(k-1) + p_k d_n^\omega, \quad (9)$$

<figure><img src="image_6.png" /><figcaption>Fig. 3: Generic complete elementary score processing unit tuned for a given rotation $\omega$.</figcaption></figure>
<figure><img src="image_7.png" /><figcaption>Fig. 5: FFT Correlation Units (FCUs) and their associated Δ-parallelism and ω-parallelism.</figcaption></figure>

<figure><img src="image_8.png" /><figcaption>Fig. 6: TS Correlation Units (TCUs) and their associated Δ-parallelism and ω-parallelism, with $\Theta_i = \frac{n\omega_i}{q}$, $\forall i \in [0, p_\omega - 1]$.</figcaption></figure>

with $p_k = P_k(q-1)$, for $k \in [0, q-1]$, and $d_n^\omega$ the input difference, that can be computed using a distributed method as

$$d_n^\omega = y(n)e^{-j\frac{\omega n}{q}} - y(n-q)e^{-j\frac{\omega(n-q)}{q}}, \quad (10)$$

or a factorized one as

$$d_n^\omega = (y(n) - y(n-q))e^{j\omega}e^{-jn\frac{\omega}{q}}. \quad (11)$$

In [26], to reduce the memory usage, the authors prefer the use of (11). However, it turned out to be too sensitive to quantization errors, even with double- or single-precision floating-point representations. A double-precision floating-point representation allows reaching better frequency resolutions indeed, but it is

not in line with the reduction of memory usage. Even more so, considering that it still results in resolutions below those reachable by using the distributed method shown in (10) with a single-precision representation. Finally, while fixed-point representations are out of the scope of the current paper, the distributed method has demonstrated good performance when using fixed-point representations on less than 32 bits. Consequently, this is the method used in the current work.

This new method, depicted in Fig. 6, is purely iterative and uses the former correlation result to compute the new one. The $q$ values of each correlation result from those of the previous one, so each correlation must be fully computed. Otherwise, it would be equivalent to ignoring some symbol values, which would
<figure><img src="image_9.png" /><figcaption>Fig. 7: Output of two FCUs (left) and two TCUs (right) for $q = 8$ and $p_{\Delta} = 2$. A column represents a complete correlation vector. Each color represents the output of a unique FCU on the left figure, and a unique TCU on the right figure.</figcaption></figure>

have a dramatic impact on detection performance. Correlations are thus computed at each new chip, resulting in a fixed $p_{\Delta}$ value of $q$ when using TS Correlation Units (TCUs). This is best represented in Fig. 7, which depicts the functional difference of FCUs and TCUs. This figure represents the output of $p_{\Delta} = 2$ FCUs on the left side, and the output of $p_{\Delta} = 2$ TCUs on the right side, depending on the time, for $q = 8$. The value $k$ from 0 to $q-1$ represents the value of the correlation. A column is thus equivalent to a full $q$-chip-long correlation vector. It illustrates that FCUs produce complete $q$-chip-long correlation vectors, every $\frac{q}{p_{\Delta}}$ chips, while TCUs produce $p_{\Delta}$ new values for every new chip. Thus, if $p_{\Delta} < q$, TCUs don't correlate with all possible sequence rotations $P_k$, resulting in an unaffordable performance loss.

Finally, the last multiplication in a TCU can be replaced by a conditional negation since $P_0$ is a binary sequence in the time domain. Thus, $\forall (k, i) \in [0, q-1]^2, P(k+i) \in \{1, -1\}$, so the multiplication becomes

$$d_n^w \times P(k+i) = \begin{cases} d_n^w & \text{if } P(k+i) = 1, \\ -d_n^w & \text{if } P(k+i) = -1. \end{cases} \quad (12)$$

This algorithmic optimization reduces the number of complex multiplications by a factor $q$. This is useful for hardware implementations, where floating-point (and even fixed-point for the matter<fnref n="2" />) complex multiplications consume more resources than conditional negation, since a conditional negation can be reduced to the

use of multiplexers. This is less relevant for a software implementation, since CPUs often integrate specialized floating-point multiplication in their Arithmetic-Logic Unit (ALU) and where conditionals result in general in branching and thus loss in throughput, due to pipeline interruptions. Modern CPU architectures even integrate Single Instruction Multiple Data (SIMD) extensions allowing computing several multiply and accumulate operations in parallel on one core, like Fused-Multiply-Add instructions on Intel x86 [20] and ARM [3].

## 3.2 Complexity Comparisons

Table 1 provides a summary of the complexity of each correlation method. These complexities are currently reported in terms of floating-point operations and storage units.

Different setups are considered for the correlation methods. First, it should be noted that parallelly running FCUs can either distribute or share the memory needed by delay buffers. Since the first FCU already requires the $q$ last samples, the second FCU just needs $\frac{q}{2}$ samples more, the third and the fourth ones need $\frac{q}{4}$ in addition, and so on and so forth. It would allow using shared cache memory more efficiently. Second, concerning TCUs, the computational complexities are reported for both the original version, and the conditional version of the algorithm. The conditional version is based on (12), and discussed at the end of section 3.1.

According to the values reported in Table 1, TCUs have the lowest complexities when $p_{\Delta}$ is set to $q$, and this setting ensures the best detection performance.

<footnote n="2">² It is worth noting that for fixed-point, the multiplication can be replaced by a binary operation since for any integer $x$ and noting $b = P(k+i) > 0$, $x \times P(k+i) = x \oplus bb...b + \bar{b}$, with $bb...b$ being $b$ broadcasted to the length of $x$.</footnote>
<table><caption>Table 1: Complexity estimations of the four CU versions presented, depending on $p_Δ$ and for $p_ω \in [1, 8]$.</caption><thead><tr><th>Method</th><th>p<sub>Δ</sub></th><th>Add</th><th>Multiply</th><th>Memory</th></tr></thead><tbody><tr><td>FCU</td><td>[[1, q - 1]]</td><td>2p<sub>ω</sub>p<sub>Δ</sub>q log<sub>2</sub>(q)</td><td>p<sub>ω</sub>p<sub>Δ</sub>q(log<sub>2</sub>(q) + 2)</td><td>(p<sub>Δ</sub>-1/p<sub>Δ</sub>) + p<sub>Δ</sub>q</td></tr><tr><td>(distributed memory)</td><td>q</td><td>2p<sub>ω</sub>q<sup>2</sup> log<sub>2</sub>(q)</td><td>p<sub>ω</sub>q<sup>2</sup>(log<sub>2</sub>(q) + 2)</td><td>q<sup>2</sup> + q + 1</td></tr><tr><td>FCU</td><td>[[1, q - 1]]</td><td>unchanged</td><td>unchanged</td><td>&sum;<sub>i=0</sub><sup>log<sub>2</sub>(p<sub>Δ</sub>)</sup> 2<sup>-i</sup>q</td></tr><tr><td>(shared memory)</td><td>q</td><td>unchanged</td><td>unchanged</td><td>2q - 1</td></tr><tr><td>TCU (original)</td><td>q</td><td>p<sub>ω</sub>q(1 + q)</td><td>p<sub>ω</sub>q<sup>2</sup></td><td>p<sub>ω</sub>2q</td></tr><tr><td>TCU (conditional)</td><td>unchanged</td><td>unchanged</td><td>p<sub>ω</sub>q</td><td>unchanged</td></tr></tbody></table>

However, as said previously, $p_Δ$ in FCUs can be lowered, thus allowing different trade-offs. As an example, in Fig. 4 when $p_ω = 4$, detection performance for $p_Δ = 16$ and $p_Δ = 64$ both reach a $P_{md} < 10^{-4}$ for $P_{fa} = 10^{-6}$.

Let us define the complexity ratio $\frac{C_{FCU}}{C_{TCU}}$ as the ratio between the complexity of FCUs $C_{FCU}$ and the complexity of TCUs $C_{TCU}$. For $q = p_Δ = 64$, it gives complexity ratios of around 3 for additions, 2 for multiplications (128 with TS (conditional)) and of 8 for memory footprint (0.9 for FCU with shared memory).

At this point, no solution seems clearly better than the other for real-time implementation. Indeed, even if complexities are lower for TCUs, they offer a lower-level parallelism, and are more constrained than FCUs. TCUs may not fully benefit from parallelism provided by multicore platforms. This aspect is discussed in the following section.

## 4 Parallelization Strategies Applied to the Detection Task

The detection task is the most demanding task of the receiver. It processes all received samples with complex detection algorithms. To achieve LPWAN compatible throughput (around 100 kb/s of information throughput [1]), the two detection methods must be parallelized and pipelined to benefit from multicore or FPGA features.

The increasing processing performance of multicore and manycore devices, associated with easy-to-use programming models [10, 25], made the implementation of prototypes or real communication systems possible. A software-based implementation may not achieve the same throughput and energy efficiency as ASIC/FPGA implementations. However, it offers a higher flexibility, a higher scalability, and a lower prototyping time than its hardware counterparts, strongly counterbalancing the initial statement. Nevertheless, the behavioral description of an algorithm does not usually consist in algorithmic structures adapted to the CPU architecture.

Even if modern compilers can extract structures from the source code, and can optimize the resulting machine code, compile-time vectorization/parallelization is still a hot topic in the literature [41, 43, 45]. Achieving high efficiency on multicore devices, by taking the best advantage of the features they offer, requires algorithm parallelization efforts.

Several parallelism levels have been identified and reported. However, the parallelization levels and strategies are influenced by several factors, e.g., whether FCUs or TCUs are used, the value of the parameters $p_ω$ and $p_Δ$, and the chosen implementation target. The current section first focuses on identifying the inherent parallelism levels of the system, and then details the strategies used for software and hardware targets.

### 4.1 Inherent Parallelism of the System

The study of the system described in section 3.1 leads to the identification of two coarse-grain parallelism levels: the Δ-parallelism (//Δ), related to $p_Δ$, and the ω-parallelism (//ω), related to $p_ω$. They have been represented in Fig. 5 for FCUs, and in Fig. 6 for TCUs, using dashed double arrows. The one corresponding to //Δ is red, and the one corresponding to //ω is blue.

The pair ($p_Δ$, $p_ω$), with $p_Δ = 2^i$, for $i \in [0, p]$ and $p_ω = 2^m$, for $m \in [0, 3]$, impacts on detection performance and on system complexities [27]. Ideally, computations performed in $p_Δ \times p_ω$ branches should be independent, allowing fully concurrent evaluation.

In fact, an FCU-based correlator is embarrassingly parallel. The computations required to produce vectors $L_n^ω$ are mutually independent, as long as input data can be replicated. This is not the case for TCUs, as discussed in section 3 and shown in Fig. 7. Indeed, the TS correlation at the time $n$ requires the correlation at the time $n-1$, which in turn requires the correlation
at the time $n-2$, and so on. This dependency is verified down to the time $n-q+1$, since the sample $y(n-q)$ is subtracted, as depicted in Fig. 6. Thus, TCU computations are directly dependent from the $q$ last computations. In theory, it would be possible to duplicate accelerators of $q$ layers to break this dependency. However, since the $q-1$ first layers would result in incomplete correlation values (see section 2.2), it is similar to a direct computation of the $q$-chip-long correlation in the time domain for all $q$ values (resulting in a complexity of $q^3$). Correlating complete correlations of evenly-sized sequences in the time domain is known to be less efficient than computing them in the frequency domain [13, 34].

These last two observations imply that in a Cloud Radio Access Network (RAN) context [10], where compute resources can be considered limitless, an FCU-based implementation may have the edge in terms of throughput. Indeed, using manycore devices and leveraging their shared memory feature, it may be possible to run efficiently thousands of FCUs parallelly. Depending on how edge servers are provisioned, the same may be true for the Fog RAN context [39]. However, to reduce latency, it is more efficient to process the data as soon as they are available, rather than buffering them. Furthermore, as previously stated, the current work is focusing on on-site computations and does not consider cloud or fog computing.

A third coarse grain parallelism level results from the signal oversampling. It is related to the oversampling factor $O$ (thus noted $O$-parallelism). Whether it is parallelized or serialized, it requires $O$ independent computations, and as such, increases memory usage linearly. Currently, no method has been found nor implemented to leverage this parallelism level besides allocating one full detector per oversampling hypothesis. It is worth noting that the use of high-throughput dedicated accelerators may allow mutualization of resources, as suggested in [31].

The three coarse grain parallelism levels enable a large set of setups. Indeed, the overall detection task can be seen as a single task or can be split into up to $O \times p_{\Delta} \times p_{\omega}$ parallel sub-tasks.

## 4.2 Software and Hardware Parallelization

Nowadays, a software platform offers at least two parallelization features, being multithreading (MT) and SIMD. First, to take advantage of MT, the sub-tasks that can be executed in parallel have been encapsulated into threads. This allows leveraging Multiple Instructions Multiple Data (MIMD) parallelisms. Threads are especially efficient for coarse grain-level parallelism, involving small interdependent tasks or repetitive processing of different data. This is typically the case for $O$. It is also the case of $\Delta$ in FCUs but not for TCUs, as they are not fully independent, as stated in the previous section. It seems to be the case for $\omega$, regardless of the CU variations. However, as highlighted in the experimentation section, it is not straightforward when subtask complexity is quite low, due to thread start and join time penalties. It is even worse when such subtask can be efficiently pipelined. At the opposite, SIMD vectorization is involved at the lowest level and requires identical computations that can be applied to multiple data simultaneously. This is precisely the case for $\Delta$ in TCUs. Each correlation kernel can be seen as a parallel computation for each chip of $P_0$. FCUs can also benefit from SIMD vectorization. For instance, the FFTW3 library [16] implements FFT efficiently by taking advantage of SIMD features.

An FPGA device can offer more parallelization opportunities than a multicore device. Indeed, processing elements are designed according to the task specification. It enables to manage easily and efficiently low-level parallelism using sequential, semi-parallel, or fully parallel architectures internally. Then, at a higher level, a heterogeneous set of custom processing elements can be allocated to manage sub-tasks concurrently. However, a massively parallel strategy, consisting of blindly duplicating processing elements, is severely limited by the amount of available FPGA resources. Besides, controllers, memories, and logical glue have to be added to the system to manage the spatial or temporal reuse of processing elements.

Different SPU implementations have been designed, achieving different trade-offs. In all cases, $O \times p_{\omega}$ parallel subsystems are allocated to maximize the throughput, using leveraging all the features available, as discussed in the experimental section.

# 5 Implementation Results

The research project aims to implement a complete QCSP communication system. Thanks to the development of Software-Defined Radio (SDR) platforms, like Ettus Universal Software-defined Radio Peripherals (USRPs), it is possible to implement a heterogeneous system more easily than before. This section is focused on the transmitter on one hand, and on the first stage of reception, the detection task, on the other hand. Currently, multiple targets are investigated for prototyping and deployment purposes. Furthermore, both pure software and hardware-accelerated implementations are proposed. Indeed, SDR devices either depend on a CPU-equipped host or embed a dedicated CPU,
that can be used for signal processing. However, they also rely on FPGAs, and USRPs also provide an API to directly access the FPGAs [8]. For instance, in the current system, the Radio-Frequency (RF) related tasks, as well as half-raised cosine filter application are offloaded to the FPGA, to reduce the burden on the host CPU.

The current section is divided in three parts:

- Firstly, the measurement methodologies are explained in section 5.1. Performance metrics and related measurement methodologies are presented in section 5.1.1. Then, the ones used to assess efficiency are detailed in section 5.1.2.

- Secondly, implementations of the QCSP transmitter are presented in section 5.2. ARM-based software implementations of the QCSP transmitter are presented in section 5.2.1, and FPGA-based hardware implementations of the QCSP transmitter are presented in section 5.2.2.

- Thirdly, implementations of the QCSP receiver's detector are presented in section 5.3. Software implementations of the QCSP receiver's detector on Intel- and ARM-based targets are presented in section 5.3.1, and FPGA-based hardware implementations of the QCSP receiver's detector are presented in section 5.3.2.

It should be noted that the resulting system was intended to be used to validate the QCSP waveform in full-scale experiments, and to produce implementation complexity metrics. The pursuit of design flexibility may have resulted in compromises in efficiency in certain instances.

## 5.1 Methodology

This subsection describes the methods used to gather the performance and consumption metrics presented in the paper. The definition of the metrics, as well the associated methods, depend on both the system implemented (the transmitter or the receiver's detector) and the targeted platform<fnref n="3" />.

### 5.1.1 Performance Metrics Estimations

The performance of the implementations is estimated in terms of chip rate, bit rate, and Worst-Case Latency (WCL).

Chip rates are reported in chips per second. In the context of the transmitter, the chip rate is the output throughput, i.e., the rate at which the transmitter produces each chip of the frame. In the context of

the detector, the chip rate is the input throughput, i.e., the rate at which the detector consumes incoming chips. For software implementations, it is estimated by measuring the time needed to process a known number of chips. The number is chosen to ensure a sufficient duration, allowing to neglect transient effects like the setup time. For FPGA implementations, it is estimated using the clock frequency divided by the initiation interval of the system, as reported by the synthesis tool. The initiation interval is the minimum number of clock cycles separating the consumption of two consecutive inputs. This estimation method was selected to avoid bottlenecks resulting from host-to-device transfers involved in actual benchmarking. Let us denote the chip rate as "$\rho$" for the current section.

The bit rate is the information throughput resulting from the chip rate. Reported in bits per second, it is the actual information throughput in the context of the transmitter, and the maximum achievable information throughput in the context of the detector. It is obtained by multiplying the chip rate by the effective rate $R_{eff}$ (see section 2), i.e.,

$$ \text{bit rate} = R_{eff} \times \rho. \qquad (13) $$

Finally, the WCL is reported in seconds. It represents the maximum amount of time needed to process one frame. For the transmitter, it is the processing latency, since the algorithm is deterministic. For the detector, it represents the latency achieved for a frame detected when the very last chip has arrived. In both cases, it is obtained by dividing the size of a frame ($N \times q$ chips) by the chip rate, i.e.,

$$ \text{WCL} = \frac{N \times q}{\rho}. \qquad (14) $$

### 5.1.2 Efficiency Estimations

The reported efficiency of the implementations is estimated in terms of power consumption and energy consumed per information bit processed.

The method to estimate power consumption varies depending on the targeted platform. For Intel-based and NVIDIA's ARM-based platforms, power consumption is estimated using software tooling. On Intel-based systems, data are provided by the Running Average Power Limit (RAPL) library [18, 24] through turbostat. On NVIDIA Jetson systems, The information provided by the Tegra API have been used, via the Jetson Power GUI. Such software support is lacking on Raspberry Pi devices. The maximum rating of the default power supply is used instead. For hardware implementations, power consumption is provided using the "report power" feature of the HDL synthesis tool

<footnote n="3">³ Platforms are detailed later, in section 5.2 for the transmitter, and 5.3 for the detector.</footnote>
<table><caption>Table 2: Performance and efficiency of QCSP software transmitter stack on ARM cores for $q = 64$, $R_{eff} = \frac{1}{32}$ and a payload of 120 bits. The power consumption reported is the maximum rating of the default power supply.</caption><thead><tr><th>Target<br>CPU</th><th>Clock<br>GHz</th><th>Chip Rate<br>Mc/s</th><th>Bit Rate<br>Mb/s</th><th>WCL<br>µs</th><th>Power (max.)<br>W</th><th>Energy / bit<br>µJ/b</th></tr></thead><tbody><tr><td>Cortex-A53</td><td>1.4</td><td>89</td><td>2.8</td><td>43</td><td>15</td><td>4.5</td></tr><tr><td>Cortex-A72</td><td>1.8</td><td>200</td><td>6.3</td><td>19</td><td>12.5</td><td>2.4</td></tr></tbody></table>

Xilinx Vivado, when the design can complete the place-and-route stage. Default settings are used, i.e., typical static consumption, 12.5% of I/O toggle rates and a static probability of 0.5.

The energy consumed per bit is the power consumption divided by the bit rate, and is thus calculated directly from the chip rate, such as

$$ \text{Energy/bit} = \frac{P}{\varrho \times R_{eff}}, \qquad (15) $$

with *P* as the power consumption, *ρ* as the chip rate and *R*<sub>eff</sub> as the effective rate. A summary of this section is provided in Table 3.

## 5.2 QCSP Transmitter Implementations

The QCSP waveform aims to improve the communication efficiency by removing any preamble, any data used solely in detection or synchronization. By merging the payload with detection and synchronization metadata, it has been proven that the sent packets can be 20% shorter, saving the same number of resources in transmission [37]. It is a crucial feature for IoT devices, since those should be low-end systems, operated off-grid and thus, power constrained. A performance evaluation of the transmitter stack has been carried out. The stack includes an NB-LDPC encoder, a CCSK mapper, a BPSK modulator and an over-modulator as shown in Fig. 1. From now on, the data sent consist of a word of 120 bits, or $K = 20$ symbols of $p = 6$ bits, leading to the use of a $P_0$ sequence of $q = 2^6 = 64$ chips. The NB-LDPC code rate is $R_c = \frac{1}{3}$, which results in an emitted frame of $N = 60$ symbols. These values give an effective code rate $R_{eff} = \frac{1}{32}$ for the communication link, and result in a QCSP frame of 3840 chips.

<table><caption>Table 3: Summary of the five different metrics, whether they are estimated or calculated, and how they are calculated, when applicable.</caption><thead><tr><th>Chip Rate</th><th>Bit Rate</th><th>WCL</th><th>Power</th><th>Energy/bit</th></tr></thead><tbody><tr><td>estim.</td><td>calc.</td><td>calc.</td><td>estim.</td><td>calc.</td></tr><tr><td>ρ</td><td>R<sub>eff</sub> × ρ</td><td>ρ / N × q</td><td>P</td><td>P / ρ × R<sub>eff</sub></td></tr></tbody></table>

### 5.2.1 ARM-based Software Implementations of the QCSP Transmitter

The software stack was described in C/C++ language, without special tuning to leverage MT or SIMD efficiently. The optimizations are left to the g++9 compiler, natively provided by the Ubuntu 20.04 operating system. It is informed of the specific model of CPU it must compile to, using the options "-O3 -mcpu=native". For evaluation purpose, a set of low-end ARM CPUs present on Raspberry Pi boards have been selected. Their properties and measured performance levels are provided in Table 2. Only the overall performance of the complete transmitter are reported. Indeed, the results for each individual component were not reproducible, due to their respective lightness. The information throughput, i.e., the emission of a frame, on the ARM Cortex-A72 reaches up to 6.25 Mb/s. The latency needed to process a frame is equal to 19 µs. These results exceed by two orders of magnitude the targeted throughput. Such high throughput on an embedded CPU is due to the low complexity of the encoding and modulation stages. Indeed, the cost of CCSK mapping is low since it is only a rotation, efficiently done by memory remapping and memory copy operations, as shown on the left side of Fig. 8. The over-modulation can be reduced to a "xor", as depicted on the right side of Fig. 8. In fact, the most compute-intensive task is the NB-LDPC encoding, however this topic is widely covered and addressed in the literature [29, 36].

The throughput and latency parameters measured on the ARM Cortex A53 are lower, a factor 2 seems discernible. This may come from the lower clock frequency. Besides, the Raspberry Pi embedding the Cortex A53 uses 32-bit data, while the other manipulates 64-bit data. This can explain the doubling of the time needed to load and map memory, explaining the results. However, achieved performance remains above all expectancies, thus stressing the lightness of the QCSP transmission stack.
<figure><img src="image_10.png" /><figcaption>Fig. 8: Conceptual representations of the CCSK mapping (left) and the over-modulation (right) for $q = 4$, for the $n$-th symbol.</figcaption></figure>

### 5.2.2 FPGA-based Hardware Implementation of the QCSP Transmitter

A solution to increase transmitter power efficiency is to design a dedicated circuit to implement the transmitter stack. Consequently, a hardware implementation has been designed using a High-Level Synthesis (HLS) C description. While HLS is not as tried and tested than plain RTL design, it has become mature in the last decade. Several high-performance digital processing systems have been implemented using this workflow [36]. Used with the APIs of the USRP, it can allow lower design time than direct RTL design for comparable performance [23]. Thanks to fast design exploration features provided by the Vivado HLS tool, different hardware implementations have been designed for several low-end FPGAs. The hardware complexity and the latency values are reported in Table 4. Two types of architectures are presented. They were obtained by inserting pragma directives, and offer different throughput and complexity trade-offs.

Architecture 1 has been optimized to maximize the throughput, to explore how high it can be. In this configuration, the previously presented tasks follow a “dataflow” scheduling, and are internally pipelined. As expected, it performed wonderfully, reaching up to

9.7 Mb/s of information throughput. This transmitter architecture requires less than a thousand LUTs and FFs, and requires 11 BRAMs.

At the extreme opposite, architecture 2 has been designed with resource saving in mind. Thus, as many features as possible have been disabled, relaxing all constraints. For example, the tool has been instructed to avoid any pipeline, and to reuse operators as much as possible. In this configuration, the implementation reached 2.7 Mb/s of information throughput. It is similar to the throughput achieved on the Cortex A53 for twice the latency, but consuming only 390 LUTs, 370 FFs and 12 BRAMs. These results are achieved for a clock frequency of 100 MHz. It means that the clock frequency could be reduced, and the results would still exceed the requirements. This may help in reducing energy consumption. Besides, the low utilization percentage — at most 8% on the Spartan 7 — leaves space to implement other systems on the FPGA. It also indicates that smaller chips can be used, thus reducing the static power consumption.

These hardware results highlight the low complexity feature of the transmission process for software and hardware-based implementations. Moreover, both achieved information throughput above 1 Mb/s, largely fulfilling, for instance, the LPWAN requirements [1].

<table><caption>Table 4: Performance of the QCSP transmitter hardware stack on two different 7-series Xilinx FPGAs clocked at 100 MHz. BRAMs are reported in terms of “RAMB18” (18 kB) elements.</caption><thead><tr><th>Target</th><th>Arch.</th><th>Chip Rate</th><th>Bit Rate</th><th>WCL</th><th>Resources</th><th>Power</th><th>Energy / bit</th></tr><tr><th>Name / Serial</th><th>ID</th><th>Mc/s</th><th>Mb/s</th><th>μs</th><th>FFs (%)</th><th>LUTs (%)</th><th>BRAMs (%)</th><th>W</th><th>μJ/b</th></tr></thead><tbody><tr><td>Artix 7</td><td>1</td><td>310</td><td>9.7</td><td>12</td><td>849 (0.7%)</td><td>839 (1.3%)</td><td>11 (4.1%)</td><td>0.126</td><td>0.013</td></tr><tr><td>xc7a100tcsg324-1</td><td>2</td><td>86</td><td>2.7</td><td>88</td><td>370 (0.3%)</td><td>390 (0.6%)</td><td>12 (4.4%)</td><td>0.105</td><td>0.039</td></tr><tr><td>Spartan 7</td><td>1</td><td>310</td><td>9.7</td><td>12</td><td>849 (1.3%)</td><td>836 (2.6%)</td><td>11 (7.3%)</td><td>0.109</td><td>0.011</td></tr><tr><td>xc7s50ftgb196-1</td><td>2</td><td>96</td><td>3.0</td><td>80</td><td>369 (0.6%)</td><td>390 (1.2%)</td><td>12 (8.0%)</td><td>0.088</td><td>0.029</td></tr></tbody></table>
This throughput is never reached in real functioning, but it allows lowering the latency, which in turn, would lower energy consumption [28]. Indeed, the energy consumption results from power consumed during a period of time. A lower latency given a set clock frequency reduces the impact of the dynamic consumption of the FPGA. In the IoT context where the transmitter does not transmit frames continuously, a lower latency means that the transmitter stack can be unpowered, reducing the static power consumption. Moreover, it is worth noting that, at the speed of light (≈ $3 \times 10^8$ m/s), an electromagnetic wave travels 10 km in approximately 33 µs. Thus, the WCLs are already in the order of magnitude of the frame travel time for a long range communication.

## 5.3 QCSP Receiver's Detector Implementations

The receiving system is implemented on both CPU and FPGA targets as well. However, the selected targets are more powerful and expensive. This choice is in line with the much higher computational complexity of the receiving system. Three distinct high-end devices are targeted for the evaluation of the throughput and latency performance of the receiver:

P1. a high-end server equipped with two Intel Xeon Gold 6148 CPUs of 20 cores each,

P2. an NVIDIA Jetson Orin equipped with a mid-end Cortex-A78AE ARM CPU of 12 cores,

P3. an FPGA Xilinx Kintex 7 (xc7k410tffg900-1).

P1 is a high-end multicore x86 system. It is composed of two Intel Xeon Gold 6148 CPU, with 256 GB of RAM. Each Xeon processor is composed of 20 physical processor cores, which are Simultaneous Multi-Threading (SMT) capable. It means that each core can run two threads in parallel simultaneously, thus, 80 threads in total are executable in parallel on P1. All cores share a 28160 kB L3 cache memory. The working frequency of the CPUs is 2.60 GHz, but the turbob boost feature enables cores to run up to 3.70 GHz when the heat-dissipation constraint is met. The operating system's CPU governor has been set up to allow maximum performance.

P2 is an automotive-grade multicore ARM system. It is composed of an ARM Cortex-A78AE CPU, with 32 GB of RAM, and 12 physical cores which are not SMT capable (thus, 12 threads in total). The cores share a 6 MB L3 cache memory. The working frequency of the CPUs is between 0.120 GHz to 2.20 GHz. This system has a specific power governor, that, like for P1, has been set up to allow maximum performance.

P3 is a bit different, as it is a hardware target. P3 is the FPGA bundled in the Ettus X310 USRP, the

SDR device used as RF frontend. This target is in line of P1 and P2 in terms of cost, but is supposed to run at a much lower working frequency, typically hundreds of MHz. However, an FPGA offers much higher parallelization opportunities, allowing to often surpass the performance achieved by software implementations on CPUs. The Xilinx Kintex 7 xc7k410tffg900-1 is of a higher grade than those targeted for the transmitter implementations. This is motivated by the receiver's detector's computational complexity, that is much higher than the computational complexity of the transmitter. Since it is embedded in the X310 USRP, it can benefit from the tight integration with the RF chain, from software drivers for host-to-device communications, and from a convenient hardware-design framework named RFNoC [8,23]. Those features ease the conducting of full-scale experiments. With a standalone circuit, or a development board, external RF modules have to be used and integrated, and all the components of the system (e.g., host-to-device communications, monitoring, and so on) have to be developed.

In any case, the //o is dealt by using o detectors in parallel, so only the results for one detector are reported in this section. It must be noted that the values are reported as-is. To the best of our knowledge, the QCSP communication protocol is the first real-time preamble-less approach reaching SNRs as low as -10 dB. Besides, combining a direct-sequence spread spectrum technique like CCSK with an ECC is also disruptive in the IoT context. Finally, the prototypes developed demonstrate its viability and highlight its low-complexity and low-power characteristics. Comparing the QCSP waveform to a preamble-based approach would require an intensive study on its own, since the use of ECC provides great communication performance, even for short transmissions, as explained in [37]. Indeed, comparing unrelated communication protocols requires the definition of strict parameters. For instance, LoRa performance depends on the spreading factor and the bandwidth targeted, which also interact with the detection performance [5]. Besides, an equivalent implementation on similar technological targets does not exist in the literature [42,47]. A fair comparison of achieved results would require extensive characterizations.

### 5.3.1 Software Implementations of the QCSP Receiver's Detector on Intel- and ARM-based Targets

The software detector is implemented on P1 and P2. The QCSP detection system depicted in Fig. 3 is described in C/C++ language. On both platforms,
<caption>Table 5: Chip rates, bit rates and latencies for different sets of parameters, with $N = 60$, $q = 64$ and an effective rate $R_{eff} = \frac{1}{32}$, for two different platforms.</caption>

(a) On P1 platform — an Intel x86_64 server using two Xeon Gold 6148 CPUs.

<table><thead><tr><th>Method</th><th>p<sub>Δ</sub></th><th>p<sub>ω</sub></th><th>Chip Rate<br>kc/s</th><th>Bit Rate<br>kb/s</th><th>WCL<br>ms</th><th>Power<br>W</th><th>Energy / bit<br>μJ/b</th></tr></thead><tbody><tr><td rowspan="2">FCU</td><td rowspan="2">8</td><td>4</td><td>2200</td><td>69</td><td>1.7</td><td>106</td><td>1500</td></tr><tr><td>8</td><td>1300</td><td>41</td><td>3.0</td><td>106</td><td>2600</td></tr><tr><td rowspan="4">MT FCU</td><td rowspan="2">16</td><td>4</td><td>1200</td><td>38</td><td>3.2</td><td>106</td><td>2800</td></tr><tr><td>8</td><td>660</td><td>21</td><td>5.8</td><td>106</td><td>5100</td></tr><tr><td rowspan="2">8</td><td>4</td><td>4500</td><td>140</td><td>0.9</td><td>150</td><td>1100</td></tr><tr><td>8</td><td>2200</td><td>69</td><td>1.7</td><td>150</td><td>2200</td></tr><tr><td rowspan="4">TCU<br>(behavioral)</td><td rowspan="2">16</td><td>4</td><td>3600</td><td>110</td><td>1.1</td><td>180</td><td>1600</td></tr><tr><td>8</td><td>1600</td><td>50</td><td>2.4</td><td>180</td><td>3600</td></tr><tr><td rowspan="2">64</td><td>4</td><td>2300</td><td>72</td><td>1.7</td><td>106</td><td>1500</td></tr><tr><td>8</td><td>1300</td><td>41</td><td>3.0</td><td>107</td><td>2600</td></tr><tr><td rowspan="2">TCU<br>(SIMD, data-shifting)</td><td rowspan="2">64</td><td>4</td><td>2900</td><td>91</td><td>1.3</td><td>106</td><td>1200</td></tr><tr><td>8</td><td>1800</td><td>56</td><td>2.1</td><td>106</td><td>1900</td></tr><tr><td rowspan="2">TCU<br>(SIMD, index-shifting)</td><td rowspan="2">64</td><td>4</td><td>5000</td><td>160</td><td>0.8</td><td>105</td><td>670</td></tr><tr><td>8</td><td>2800</td><td>88</td><td>1.4</td><td>105</td><td>1200</td></tr></tbody></table>

(b) On P2 platform — a mid-end NVIDIA Jetson Orin using a 12-core ARM Cortex-A78AE CPU.

<table><thead><tr><th>Method</th><th>p<sub>Δ</sub></th><th>p<sub>ω</sub></th><th>Chip Rate<br>kc/s</th><th>Bit Rate<br>kb/s</th><th>WCL<br>ms</th><th>Power<br>W</th><th>Energy / bit<br>μJ/b</th></tr></thead><tbody><tr><td rowspan="2">FCU</td><td rowspan="2">8</td><td>4</td><td>630</td><td>20</td><td>6.1</td><td>1.8</td><td>91</td></tr><tr><td>8</td><td>360</td><td>11</td><td>10.7</td><td>1.8</td><td>160</td></tr><tr><td rowspan="4">MT FCU</td><td rowspan="2">16</td><td>4</td><td>320</td><td>10</td><td>12.0</td><td>1.8</td><td>180</td></tr><tr><td>8</td><td>190</td><td>6</td><td>20.2</td><td>1.8</td><td>300</td></tr><tr><td rowspan="2">8</td><td>4</td><td>1400</td><td>44</td><td>2.7</td><td>3.6</td><td>82</td></tr><tr><td>8</td><td>1100</td><td>34</td><td>3.5</td><td>3.6</td><td>104</td></tr><tr><td rowspan="4">TCU<br>(behavioral)</td><td rowspan="2">16</td><td>4</td><td>450</td><td>14</td><td>8.5</td><td>3.1</td><td>230</td></tr><tr><td>8</td><td>400</td><td>12</td><td>9.6</td><td>3.1</td><td>260</td></tr><tr><td rowspan="2">64</td><td>4</td><td>670</td><td>21</td><td>5.7</td><td>1.8</td><td>86</td></tr><tr><td>8</td><td>390</td><td>12</td><td>9.8</td><td>1.8</td><td>150</td></tr><tr><td rowspan="2">TCU<br>(SIMD, data-shifting)</td><td rowspan="2">64</td><td>4</td><td>1300</td><td>41</td><td>3.0</td><td>1.8</td><td>44</td></tr><tr><td>8</td><td>780</td><td>24</td><td>4.9</td><td>1.8</td><td>74</td></tr><tr><td rowspan="2">TCU<br>(SIMD, index-shifting)</td><td rowspan="2">64</td><td>4</td><td>2100</td><td>66</td><td>1.8</td><td>1.8</td><td>27</td></tr><tr><td>8</td><td>1200</td><td>38</td><td>3.2</td><td>1.8</td><td>48</td></tr></tbody></table>

the code is compiled with `g++9`, version natively provided by the Ubuntu 20.04 operating systems, with the same optimizations than the transmitter (i.e., "-march=native -mtune=native -O3" on P1, and "-mcpu=native -O3" on P2). The software detector has been implemented for the two detailed CU variations, FFT as presented in Fig. 5 and TS as represented in Fig. 6. We have tested several values of $p_{Δ}$ and $p_{ω}$,

and used three configurations for TCUs, described in the following. Besides, all the data manipulated in the software implementations use single-precision floating-point representations.

The strategies of parallelization described in the previous section have been applied to the C++ source codes. For FCUs, the optimized library FFTW3 [16] is leveraged. This library has CPU detection capabilities,
<figure><img src="image_11.png" /><figcaption>Fig. 9: The two different ways of implementing TCUs, either using the data-shifting method (to the left) or the index-shifting method (to the right).</figcaption></figure>

which allows it to execute efficiently the FFTs. It can internally use all applicable CPU features, like MT or SIMD. However, we restrain it to SIMD to prevent it from interfering with our threads. $//_{\Delta}$ is implemented using the OpenMP API, using shared-memory FCUs as described in section 3. The use of OpenMP has been tested for $//_{\omega}$ as well. However, despite our best efforts, it always resulted in a slower implementation. Our best explanation so far is that the computations necessitated by one frequency hypothesis are not that heavy, compared to thread synchronization overhead. To put that assumption to test, the MT FCU-based SPU on $\mathcal{P}1$ for $(p_{\omega}, p_{\Delta}) = (1, 1)$ is benchmarked with OpenMP toggled at compile-time using preprocessor primitives (i.e., `#ifdef/#endif`). Without OpenMP, a chip rate of 14 Mc/s can be reliably achieved, whereas it cannot exceed 9.4 Mc/s with OpenMP enabled. To better leverage MT, it may be possible to redesign the algorithm to dedicate one thread to each possible time and frequency hypothesis. Moreover, threads can run freely, if they operate on batch of buffered data instead of processing data as soon as possible. Distributed-memory FCUs may be more suitable for the task, and it requires the reorganization of memory allocations, and a rework of the structure of the source code. However, given the performance achieved by the TCU-based SPU, we have not further explored possible improvements to FCU-based approaches.

Concerning TCUs, we implemented them only thanks to handmade C/C++ codes. The sources are written using floating-point values as well, but in a first time as close to the algorithm behavior as possible,

using complex number abstraction for instance. For the second and the third versions, the software description has been finely written, in a way that takes advantage of g++ auto-vectorization feature, with even some specific software parts finely tuned with intrinsic SIMD instructions [3, 20]. The second and third versions correspond to two ways of performing (9). The second version uses the rotation of $L_{n}^{\omega}(k)$, while $p_k$ remains locally constant and is called “data-shifting”. The second one makes the PN sequence rotate instead, thus shifting the $p_k$. It is equivalent to shifting $k$, the index of $p_k$. Thus, we chose to name this the “index-shifting” method. Illustrations of both methods are provided in Fig. 9, in (a) for the data-shifting one, and in (b) for the index-shifting one.<fnref n="4" />

Measured input throughputs in kilochips per second (kc/s) and equivalent information throughputs in kilobits per second (kb/s) for different setups are reported in Table 5. Throughput and latency are measured using the C++ Chrono API. In Table 5 the MT FCU uses $p_{\Delta}$ threads. As it can be seen, the throughput performance depends on the correlation method applied, the selected parameters, and the platform.

As expected, throughputs are lower than transmitter ones, even on high-end CPUs. Indeed, the receiver process is way more complex than the transmitter one [38]. On one hand, executed on a single thread, the FCU-based detector is the slowest, achieving at most

<footnote n="4">⁴ It should be noted that in the Fig. 6 in section 3.1, it is the “index-shifting” method that is represented.</footnote>
2200 kc/s on $\mathcal{P}1$ for $p_\Delta = 8$ and $p_\omega = 4$, while going as low as 190 kc/s on $\mathcal{P}2$ when $p_\Delta = 16$ and $p_\omega = 8$. On another hand, the throughput is improved up to 4500 kc/s by dedicating one physical processor core for each filter, thus using 8 cores. Up to 140 kb/s of information can be processed as shown in Table 5, for the MT FCU method, $p_\Delta = 8$, and $p_\omega = 4$. Multi-thread execution provides, in this configuration, a 2x speed-up that does not scale with $p_\Delta$ value. This performance gap is caused by the overhead incurred by the thread startup and synchronization, due to the OpenMP API. The heavier the load is, the higher the speed-up. This can be seen on $\mathcal{P}1$ for $p_\Delta = 16$, and $p_\omega = 8$, where the speed-up is up to 2.4x. It is even more obvious on $\mathcal{P}2$ for $p_\Delta = 8$, and $p_\omega = 8$, where the speed-up is of 3x. Since $\mathcal{P}2$ have only 12 cores, thus for $p_\Delta = 16$, the speed-up is not as good.

The TCU-based approach, that provides the best detection performance thanks to $p_\Delta = q$ (see section 2), achieves decoding throughput from 390 kc/s for the behavioral description on $\mathcal{P}2$, to 5000 kc/s on $\mathcal{P}3$ when leveraging vectorization using “index-shifting”. The “data-shifting” method is always slower. For instance, on $\mathcal{P}1$ for $p_\omega = 4$, the data-shifting TCU method achieves an input throughput of 2900 kc/s while for the same settings, the index-shifting TCU one achieves 5000 kc/s. This results from the nature of $L_n^\omega(k)$ compared to the one of $p_k$. The vector $L_n^\omega$ is composed of $q$ complex values, while $P_0$ is composed of $q$ real values. Thus, rotating $L_n^\omega$ requires twice as much CPU cycles than for the rotation of $P_0$. The “index-shifting” method is thus superior.

A key comparison point is that the “index-shifting” TCU method uses at most one processor core. So, it does not only outperform the MT FCU method in terms of throughput, achieving 5000 kc/s for $p_\Delta = 8$, and $p_\omega = 4$, while the MT FCU one reaches 4500 kc/s. The “index-shifting” TCU method also consumes 105 W of power while the MT FCU one requires as high as 180 W. Thus, the “index-shifting” TCU method uses on average 670 $\mu J$/b while the MT FCU method requires 1100 $\mu J$/b, thus saving 1.6x of energy per information bit. It is worth noting that a throughput of 2200 kc/s is achievable on $\mathcal{P}2$ using the “index-shifting” TCU method, for an energy consumption as low as 27 $\mu J$/b.

Finally, with “index-shifting” TCUs, the WCLs remain below 2 ms on $\mathcal{P}1$. While being around 20 to 200 times higher than values reported for the transmitter in Table 2 and Table 4, they remain acceptable for IoT devices. Indeed, it means that each monothreaded detector on $\mathcal{P}1$ can process up to 500 frames per second. Assuming that the 20 physical cores of the server can all be dedicated to detection, and that 20

$P_0$ sequences can be used in parallel without loss of detection performances, $\mathcal{P}1$ could process $10^4$ frames per second.

FCU-based detection methods are proved non-relevant. They are always outperformed by TCU-based methods. Indeed, the use of TCUs ensures the best detection performance, and simultaneously offers the highest throughput. These reception chip rates, which reach a few Mc/s (thus around a hundred kb/s of information throughput), are already similar to those required in, for instance, the Low-Rate Wireless Networks (LRWN) domain [1], or those implemented in LoRa transceivers [17]. It makes the software receiver a viable solution for the QCSP modulation evaluation. One can also imagine a mesh network, with $\mathcal{P}2$ systems used as relay transceivers, communicating to aggregator servers, based on the $\mathcal{P}1$ platform. In summary, in the context of this work, for software implementations, the SIMD index-shifting TCU-based detector is the most efficient. However, as mentioned in section 4.1, in another context, like in the Cloud RAN one, FCU-based approaches may still be relevant.

Nonetheless, software implementations are bound to available CPU features. This is not the case for hardware implementations, detailed in the next sections.

### 5.3.2 FPGA-based Hardware Implementations of the QCSP Receiver's Detector

The detector's C++ source codes were reworked to use the authorized C++ synthesis subset [15] supported by Xilinx Vitis HLS 2021 [49]. C++ descriptions, for both detection approaches, are configurable using `#define` and `#pragma` keywords, controlling the HLS design tool. This highly configurable setup allows testing various architectural variations for different values of $p_\omega$ or $p_\Delta$, even if this high configurability may have come at the expanse of performance. These C++ models are synthesized using Vivado HLS for the $\mathcal{P}3$ platform, a Xilinx Kintex 7 FPGA, available in the X310 USRP.

Floating-point and fixed-point approaches of the FCU-based architecture have been developed. They were designed with high throughput at all costs as an objective, instantiating $p_\omega$ processing sub-chains in parallel. Internally, task pipelining and parallel processing were inferred. They differentiate by how data are internally represented. The first variant was using single-precision floating-point representations. However, it requires too many resources to be even synthesized by the HLS tool for the chosen target. The second variant has thus been designed with fixed-point
<table><caption>Table 6: Hardware performance of the detector on a Xilinx Kintex 7 (xc7k410tfg900-1) clocked at 100 MHz. Resources reported for “FCU fixed” designs are theoretical estimations, since the implementation of complete FCU-based SPUs failed, due to the required amount of BRAMs.</caption><thead><tr><th rowspan="2">Method</th><th rowspan="2">p<sub>Δ</sub></th><th rowspan="2">p<sub>ω</sub></th><th rowspan="2">Chip</th><th>Rate</th><th>Bit</th><th>WCL</th><th rowspan="2">FF (%)</th><th colspan="3">Resources</th></tr><tr><th>kc/s</th><th>kb/s</th><th>ms</th><th>LUT (%)</th><th>BRAM (%)</th><th>DSP (%)</th></tr></thead><tbody><tr><td>FCU float</td><td>8</td><td>4</td><td></td><td>2100</td><td>65</td><td>1.8</td><td colspan="3">Complete exhaustion of resources</td></tr><tr><td rowspan="2">FCU fixed</td><td rowspan="2">8</td><td>4</td><td></td><td>2600</td><td>81</td><td>1.5</td><td>25726 (5.1%)</td><td>43206 (17.0%)</td><td>950 (120%)</td><td>380 (25%)</td></tr><tr><td>8</td><td></td><td>2600</td><td>81</td><td>1.5</td><td>51452 (10.1%)</td><td>94468 (34.0%)</td><td>1900 (240%)</td><td>760 (49%)</td></tr><tr><td rowspan="2">TCU float</td><td rowspan="2">64</td><td>4</td><td></td><td>2600</td><td>81</td><td>1.5</td><td>51452 (10.1%)</td><td>94468 (34.0%)</td><td>1900 (240%)</td><td>760 (49%)</td></tr><tr><td>8</td><td></td><td>2600</td><td>81</td><td>1.5</td><td>102904 (20.2%)</td><td>188936 (68.0%)</td><td>3800 (480%)</td><td>1520 (98%)</td></tr><tr><td></td><td></td><td></td><td></td><td>9100</td><td>284</td><td>0.4</td><td>144064 (28.3%)</td><td>80836 (31.8%)</td><td>79 (5%)</td><td>383 (25%)</td></tr><tr><td></td><td></td><td></td><td></td><td>9100</td><td>284</td><td>0.4</td><td colspan="3">Timing constraints are not met</td></tr></tbody></table>

representation of data, with conservative quantification, to eliminate any risk of performance loss. The input of the FFT kernels, as well as the twiddle-factors, were quantized on 16-bits<fnref n="5" />. The FFT models used are derived from work presented in [21]. The floating-point FCU-based detector reaches 2100 kc/s, as estimated by the HLS tool for $p_ω = 1$ and $p_Δ = 1$, the same throughput as its software single-core counterparts. The failure to meet the resource constraints was expected, since floating-point arithmetic is known to require more resources on FPGAs [19]. The fixed-point variant performed slightly better, reaching a throughput of 2900 kc/s, but still exceeding the available amount of BRAMs for $p_ω > 4$ and $p_Δ > 4$. To allow comparing with TCU hardware implementations, we estimated the theoretical resource requirement by multiplying the resource required by an FCU implemented for $p_ω = 1$ and $p_Δ = 1$. This assumes that the amount of resources required by pipelining and logical glue is negligible, and that their is no impact on the throughput. While those assumptions are false, they are overly favorable to the FCU method, since implementing efficient FFTs is not usually straightforward [22, 44].

The TCU-based architecture has also been described using pipeline and parallel task execution approaches, as the FCU-based one. However, using the simplifications mentioned in sections 3.1 (in (12)) and 5.3.2 (“index-shifting”), the computational complexity at $//Δ$ is significantly lower. This resulted in a throughput 3× faster than the most (theoretically) performant FCU-based implementation, despite the use of single-precision floating-point representations. More importantly, its throughput is 1.8× higher than the best software alternative, the “index-shifting” TCU method. Unfortunately, for $p_ω = 8$, it failed to meet the timing constraints. To solve this issue and to im-

prove further the architecture efficiency, a fixed-point implementation of the TCU-based detector is planned. However, the design of a quantized fixed-point model requires identification efforts, and to properly evaluate the noise introduced by the quantization. The main challenge resides in the control of the error accumulated in the memories holding the iterative values of $L_ω^n$. A small uncontrolled error would result in an inexorable drift of the resulting score, which can be hard to see without extensive testing.

Yet again, the FCU-based detector is not up to the task, as it cannot perform better than its software counterpart in terms of throughput. This observation must be tempered, as the FPGA is expected to consume around 10 W [30, 48], which would result in an energy per information bit of 110 µJ/b. For $p_ω = 8$ and $p_Δ = 16$, it is 2.4× less energy consuming than the most energy-efficient FCU-based implementation on P2. Nevertheless, the TCU method asserted its superiority, as it reaches 9100 kc/s of input throughput for $p_ω = 4$. After the place-and-route implementation stage, the power consumption is estimated at 1.113 W, resulting in an energy per bit as low as 3.9 µJ/b. A fixed-point implementation should improve these results even more, since it would not require using dedicated floating-point elements [19]. A dedicated HDL description of the TCU-based detector can also provide higher performance than the one presented in the current work, obtained through HLS.

## 6 Conclusion

The paper demonstrates that the preamble-less QCSP communication system can be implemented in real time, on software and hardware targets, despite the high computational complexity. The resulting software implementations reached information throughput of 160 kb/s on an Intel-based multicore platform while

<footnote n="5">⁵ This quantization was not thoroughly tested, since it cannot be implemented for the targeted parameters.</footnote>
consuming 670 µJ/b. On an ARM-based multicore
plateform, they achieve throngtputs of 66 kb/s with
an estimated consumption of 27 µJ/b, compatible with
the LPWAN context. Moreover, on a Xilinx FPGA, the
throughput can reach up to 284 kb/s, for as low as 3.9
µJ/b, despite being obtained using HLS methodology.
These implementations support the relevance of the
QCSP waveform for wireless sensor networks, working
at low SNRs. They may even challenge already
established solutions like the LoRa physical layer. High
performances and energy efficiencies results from the
algorithm refinements and the parallelization strategies
deployed. Both aspects are detailed in the paper.
Work performed on the score function refinement
demonstrates that the approach based on "index-
shifting" TCUs is the most efficient one. In future
works, a fixed-point version of this method will be
implemented in hardware to reduce costs and improve
the throughput. Moreover, the remaining stages of the
QCSP receiver will also be refined and implemented
to have a complete communication system. Finally, in
parallel, a characterization work is conducted, and an
experimental protocol is elaborated. They should offer
fair comparisons with other established approaches.

Glossary

$P_{FA}$ False Alarm Probability. 4, 5

$P_{MD}$ Miss Detection Probability. 4, 5

ALU Arithmetic-Logic Unit. 7

BPSK Binary Phase-Shift Keying. 3, 11

BRAM Block RAM. 12, 17

CCSK Cyclic Code Shift Keying. 2, 3, 11–13

CU Correlation Unit. 5, 8, 9, 14

DSP Digital Signal Processing slice. 17

ECC Error-Correcting Code. 1, 2, 13

FCU FFT Correlation Unit. 5–9, 14–17

FF Flip-Flop. 12, 17

FFT Fast Fourier Transform. 2, 5, 6, 9, 14, 15, 17, 18

FPGA Field-Programmable Gate Array. 2, 8–10, 12, 13, 16, 17

HLS High-Level Synthesis. 1, 12, 16–18

IFFT Inverse Fast Fourier Transform. 5

IoT Internet of Things. 1, 2, 11, 13, 16

LLR Log-Likelihood Ratio. 3

LPWAN Low-Power Wide-Area Network. 1, 8, 12, 18

LUT Look-Up Table. 12, 17

MIMD Multiple Instructions Multiple Data. 9

MT multithreading. 9, 11, 14–16

mURLLC massive Ultra-Reliable Low-Latency Com-
munications. 1

NB-LDPC Non-Binary Low-Density Parity-Check. 3, 11

PN Pseudo-random Noise. 3, 15

QCSP Quasi-Cyclic Short Packet. 1–5, 7, 9–13, 15–19

RAN Radio Access Network. 1, 9, 16

RF Radio-Frequency. 10, 13

ROC Receiver Operating Characteristics. 5

SDR Software-Defined Radio. 2, 9, 13

SIMD Single Instruction Multiple Data. 7, 9, 11, 14, 15

SMT Simultaneous Multi-Threading. 13

SNR Signal-to-Noise Ratio. 2, 4, 5, 13, 18

SPU Score Processing Unit. 5, 9, 15, 17

TCU TS Correlation Unit. 6–9, 14–18

TS Time Sliding. 5–8, 14, 18

USRP Universal Software-defined Radio Peripheral. 2,
9, 10, 12, 13

WCL Worst-Case Latency. 10–14, 16, 17

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### Camille MONIÈRE

Camille Monière received the M.S. degree in electronics and embedded systems from the ENSEIRB-MATMECA in France, in 2019.

He then received the Ph.D degree in electronics from the University of South Brittany, Lorient, France, in 2023.

He is currently a teaching and research associate in the University of South Brittany and the Lab-STICC Laboratory.

His work currently focuses on the implementation of energy and resource efficient communication systems, on software (CPU) and hardware (FPGA) targets.

### Bertrand LE GAL

Bertrand Le Gal received the M.S. and Ph.D. degrees from the University of South Brittany, Lorient, France, in 2002 and 2005, respectively.

He joined in 2005 the IRISA/INRIA laboratory of the University of Rennes 1 and the ENSSAT graduate engineering school at Lannion, France as a teaching assistant.

Since 2006, he is an Associate Professor in the IMS Laboratory, ENSEIRB-MATMECA engineering school, France.

He received in 2023 the accreditation to supervise doctoral research from University of Bordeaux, France.

His research focused on Algorithm-Architecture-Matching of ECC decoders on both hardware (ASIC/FPGA) and software targets (CPU/DSP/GPU).

Its research topics currently includes complete digital communication system implementations and also RISC-V processor design under performance and security constraints.

He is the author or co-author of 31 peer-reviewed publications in international journals and more than one hundred peer-reviewed articles in international conferences.

### Emmanuel BOUTILLON

Emmanuel Boutillon received the Engineering Diploma and Ph.D. degrees from Telecom Paris Tech, Paris, in 1990 and 1995, respectively.

From 1995 to 2000, he was an Assistant Professor with Telecom Paris Tech.

In 1998, he spent a sabbatical year at the University of Toronto, ON, Canada.

In 2000, he moved to the Université de Bretagne Sud, Lorient, France, as a Professor.

He headed the LESTER Laboratory from 2005 up to the end of 2007.

He was then the Head of the CACS Department (Lab-STICC) until 2016.

In 2011, he had a sabbatical year at INICTEL-UNI, Lima, Peru.

His research interests are on the interactions between algorithm and architecture in the field of wireless communications and high-speed signal processing.

In particular, he works on binary and non-binary decoders.
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**Declaration of interests**

☐ The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

☒ The authors declare the following financial interests/personal relationships which may be considered as potential competing interests:

Camille Moniere reports financial support was provided by French National Research Agency.