# Embodied Carbon Footprint of 3D NAND Memories

Olivier Weppe, Thibaut Marty, Sébastien Toussaint, Nicolas Brusselmans, Jean-Christophe Prévotet, Jean-Pierre Raskin, Maxime Pelcat

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Olivier Weppe, Thibaut Marty, Sébastien Toussaint, Nicolas Brusselmans, Jean-Christophe Prévotet, et al.. Embodied Carbon Footprint of 3D NAND Memories. Inter-national Conference on Computing Frontiers (CF'25), May 2025, Cagliari (Sardinia), France. 10.1145/3706594.3727962. hal-05015578v2

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Embodied Carbon Footprint of 3D NAND Memories

Olivier Weppe

olivier.weppe@insa-rennes.fr
Univ. Rennes, INSA Rennes, CNRS,
IETR - UMR 6164
Rennes, France

Thibaut Marty

thibaut.marty@insa-rennes.fr
Univ. Rennes, INSA Rennes, CNRS,
IETR - UMR 6164
Rennes, France

Sébastien Toussaint

sebastien.toussaint@uclouvain.be
ICTEAM, UCLouvain
Louvain-la-Neuve, Belgium

Nicolas Brusselmans

nicolas.brusselmans@uclouvain.be
ICTEAM, UCLouvain
Louvain-la-Neuve, Belgium

Jean-Christophe Prévotet

jean-christophe.prevotet@insa-rennes.fr
Univ. Rennes, INSA Rennes, CNRS,
IETR - UMR 6164
Rennes, France

Jean-Pierre Raskin

jean-pierre.raskin@uclouvain.be
ICTEAM, UCLouvain
Louvain-la-Neuve, Belgium

Maxime Pelcat

maxime.pelcat@insa-rennes.fr
Univ. Rennes, INSA Rennes, CNRS,
IETR - UMR 6164
Rennes, France

Abstract

This study presents a novel model for estimating the embodied
carbon footprint of Solid-State Drives (SSDs), focusing on the re-
lationship between manufacturing complexity and environmental
impact. By analyzing the number of process steps required to fab-
ricate SSDs, particularly those using 3D NAND technology, the
model predicts carbon emissions without the need for a detailed
physical analysis.

The model is applied to over 1,000 SSD devices, revealing that higher-density SSDs, which utilize more advanced multi-layer technologies, demonstrate an improved carbon efficiency. Devices with more layers show a lower carbon footprint per gigabyte, despite the increased manufacturing complexity.

Our results are compared to product carbon footprints reported
by manufacturers, revealing significant discrepancies both between
our estimates and the manufacturers' reports, as well as among
the manufacturers' own reported values. However, the proposed
model offers a streamlined and accessible method for estimating
the carbon footprint of SSDs, providing insights for sustainable
data storage solutions. On studied NAND Flash chips, the model
estimates an average embodied carbon of 22 kg CO2e per TB.

3D NAND technologies enable an unforeseen density of infor-
mation, which is not without an environmental cost. Due to its
sustained increase in capacity in computing devices, SSDs are be-
coming the dominating factor of the carbon footprint in computers.
This work aims at proposing a new model that may be used to
obtain a more accurate idea of the impact of SSD devices.

CCS Concepts

* Hardware → 3D integrated circuits; Semiconductor memory; Impact on the environment.

Keywords

Flash, Environmental Impact, Greenhouse Gas (GHG) Emissions, Global Warming Potential (GWP), Manufacturing, Silicon Devices, Integrated Circuits (ICs), Life Cycle Assessment (LCA), Solid State Drives (SSDs)

ACM Reference Format:

Olivier Weppe, Thibaut Marty, Sébastien Toussaint, Nicolas Brusselmans, Jean-Christophe Prévotet, Jean-Pierre Raskin, and Maxime Pelcat. 2025. Embodied Carbon Footprint of 3D NAND Memories. In *22nd ACM International Conference on Computing Frontiers (CF Companion '25)*, May 28–30, 2025, *Cagliari, Italy*. ACM, New York, NY, USA, 9 pages. https://doi.org/10.1145/3706594.3727962

# 1 Introduction

The global demand for data storage has been growing exponen-
tially [9], driven by the proliferation of mobile devices, cloud ser-
vices [3] and high volume content like videos. Flash storage, particu-
larly solid-state drives (SSDs), has become increasingly prevalent in
consumer electronics, enterprise data centers, as well as in personal
computing. The recent explosion of memory usage required by
Artificial Intelligence (AI) applications, especially Large Language
Models, will further accelerate the need for larger flash storage
space [22]. With this growing demand for content storage, SSD ca-
pacities have increased significantly over the past decade. Figure 1
illustrates the growth in SSD capacity as recorded in the database
used for this study [2]. Although there appears to be a stagnation
in growth since 2020, most drives introduced in recent years offer
capacities exceeding 1 terabyte (TB).

However, this surge in storage capacity comes with environmen-
tal consequences. The manufacture of silicon-based components,

<footnote>Publication rights licensed to ACM. ACM acknowledges that this contribution was
authored or co-authored by an employee, contractor or affiliate of a national govern-
ment. As such, the Government retains a nonexclusive, royalty-free right to publish
or reproduce this article, or to allow others to do so, for Government purposes only.
Request permissions from owner/author(s).
*CF Companion '25, Cagliari, Italy*
© 2025 Copyright held by the owner/author(s). Publication rights licensed to ACM.
ACM ISBN 979-8-4007-1393-4/2025/05
https://doi.org/10.1145/3706594.3727962</footnote>
<figure><img src="image_2.png" /><figcaption>Figure 1: Evolution of SSD capacity in Gigabytes across time, for models identified in the database [2].</figcaption></figure>

such as SSDs, is responsible for a major part of the greenhouse gas (GHG) emissions associated with electronic devices [13, 17]. Part of these GHG emissions is related to the embodied carbon, which refers to the Global Warming Potential (GWP) due to the manufacturing phase of the device. To address the environmental concern, the carbon footprint of storage devices has been estimated so far by analyzing the physical dimensions of the employed silicon chips. This evaluation often involves techniques such as X-ray imaging or component decapping to measure the silicon area and estimate the induced environmental impacts [12].

Using a linear factor of 110 g/GB as proposed by Li et al. [11], a typical post-2020 SSD with a capacity of 1 TB results in a carbon footprint of 110 kg CO₂e. In comparison, applying a factor of 2.6 kg CO₂e/cm² as suggested by Malmodin et al. [15], a typical Central Processing Unit (CPU) with an area of a few square centimeters has a carbon footprint below 10 kg CO₂e. This highlights that the carbon footprint of modern computers is increasingly dominated by SSDs, necessitating accurate measurement methods to estimate their embodied carbon.

To illustrate this, a break-even equation can be derived from the life cycle assessment (LCA) of a Dell R740 server [5]. This equation determines the point at which, using the linear approximation, flash storage becomes the most significant contributor to a server's embodied carbon footprint. By extracting the carbon impact associated with the fabrication of components such as the chassis, power supply, cooling system, and mainboard from the Dell study, a baseline value of 251.4 kg CO₂e is established for a computing server, excluding SSD storage. Incorporating the SSD impact yields Equation (1), which estimates the total embodied GWP G of a server based on its storage capacity C<sub>GB</sub>, in Gigabytes:

$$G = 251.4 + 0.11 \cdot C_{GB} \quad (1)$$

From this equation, we can conclude that for SSDs above 4 terabytes, the carbon footprint associated with the manufacture of an entire server is predominantly concentrated in the flash storage.

As the semiconductor industry seeks to overcome physical limits in order to meet the SSD size demand, new technologies such as transistor stacking and 3D process integration have emerged [14]. Consequently, linear models based solely on storage capacity are becoming insufficient, and new methodologies must be defined to avoid misleading GWP estimates for computing devices with large storage capacities. Yet, current carbon emission analyses do not account for the additional carbon impact associated with 3D stacking processes and updated assessment techniques are needed to compute a reliable estimation and drive system architectures towards carbon efficiency. One illustration of this evolution towards more comprehensive carbon footprint estimation of 3D stacking in silicon devices, through the example of CMOS image sensors, is shown in [20].

In this study, we propose a novel model based on the number of 3D NAND memory manufacturing steps to estimate the carbon footprint of SSDs, focusing on key production factors without the need for complex physical analyses. Our model is designed to be applied using publicly available information, providing a more accessible and transparent means of assessing the environmental impact of flash storage.

## 2 Related Work

Several studies have looked at estimating the carbon footprint of silicon. In 2012, Boyd et al. [4] have conducted a Life Cycle Analysis (LCA) of silicon chips across various technologies, including flash storage devices. However, at the time, 3D technologies were not widespread and thus were not included in the analysis. Additionally, the study focused on technology nodes down to 32 nm, while more recent flash devices are based on technologies below 32 nm. Pirson et al. [18] offer an extensive review of the literature, emphasizing notable inconsistencies among existing studies, models, and LCA databases. While this report serves as a valuable resource for understanding the environmental footprint of integrated circuits (ICs), it remains too broad for the subject at hand. The fabrication process of Flash memories, being highly specialized, requires its own dedicated analysis. Among the most detailed models is IMEC Netzero [6], which estimates the carbon footprint of a device based on its silicon area and technology node. While widely regarded, this model does not disclose its internal methodology.

Flash storage manufacturing and its environmental effects is a complex topic. Xiao et al. [21] describe the step-by-step breakdown of 3D NAND fabrication processes. This detailed process description forms the basis of our model. Novel LCA methodologies have been recently proposed to determine the carbon footprint of computing devices such as computers or servers [11, 15]. However, in order to propose a streamlined framework that produces estimations without the need for extensive prior knowledge, those methodologies rely on a single parameter, either the storage capacity or the silicon area, to determine the carbon impact of SSDs. Although a linear impact estimation can reveal the order of magnitude of the impact, it fails to grasp the complexity of SSD technology, especially the 3D storage and the multiple bits-per-cell implementations.
By using information about the life cycle impacts provided by manufacturers, Tannu et al. [19] show that SSDs may have a higher carbon footprint than expected. This is one of early works putting the focus on the environmental impact of SSD as a major contributor of the total GWP of a computing system. Our work goes beyond this study, showing that SSDs may become a major contributor in the carbon impact of future computing.

# 3 Methodology

## 3.1 Processing steps as a key determinant of carbon footprint

<figure><img src="image_3.png" /><figcaption>Figure 2: Carbon footprint per square centimeter die (red bars) for technology nodes ranging from 28nm to 3nm, based on IMEC NetZero. The number of processing steps is represented by the blue line, illustrating the strong correlation. The approximation using the proposed affine model is shown in grey bars.</figcaption></figure>

Our analysis of the results provided by Bardon [6]<fnref n="1" /> reveals a notable correlation between the number of steps involved in producing a wafer and the estimated manufacturing carbon footprint for corresponding technology nodes, as illustrated in Figure 2. As expected, more advanced technology nodes, requiring more processing steps, result in a higher carbon footprint. However, the transition from traditional Ultra-Violet (UV) to Extreme Ultra-Violet (EUV) lithography at the 7 nm node significantly reduces the number of processing steps by eliminating the need for multiple-patterning, which in turn decreases the carbon impact [10]. This reduction is reflected in the carbon footprint estimates at this technology transition, which is visible in Figure 2. This phenomenon indicates that raising the number of processing steps also raises the carbon footprint of a wafer, primarily due to the energy consumption required for each step [4].

This analysis reveals that the number of processing steps serves as a robust predictor of wafer-level carbon footprint, with a near-unity correlation coefficient ((ρ = 0.9952) and high statistical significance (2.75 · 10⁻⁷), indicating that the number of steps is sufficient to estimate the carbon footprint of the device. Building on this relationship, we develop an affine regression model (Equation (2)) to estimate the carbon footprint based on the number of steps required to produce a silicon die. This relationship does not mean that all steps are assumed identical, but rather that the cumulative effect of hundreds of steps statistically averages process-specific variations, including those tied to technology nodes. The rationale behind the selection of an affine model is that there is a base carbon cost related to wafer size, and a proportional factor that scales with the number of steps, reflecting the energy consumption of equipment, factory operations, and the use of chemicals. While individual steps such as lithography or etching do indeed have different environmental impacts across different technologies, these variations are absorbed into the empirical coefficients of the model through the regression process, which does not ignore heterogeneity but distils it into an effective per-step impact derived from manufacturer data across multiple nodes. Ultimately, this abstraction enables practical carbon estimation without the need for granular process details, while maintaining predictive accuracy as evidenced by the correlation strength.

$$G = \alpha + \beta \cdot N_{\text{Steps}} \quad (2)$$

Where G is the global warming potential (GWP) of an integrated circuit of 1 cm² expressed in kg CO₂e depending on the number of steps of fabrication NSteps, and α and β are coefficients determined empirically. The affine regression, based on data by the number of steps per process reported by Bardon [6] and silicon die carbon footprint estimated by IMEC NetZero model, provides α and β, which yield the following equation:

$$G = 0.3123 + 0.0009 \cdot N_{\text{Steps}} \quad (3)$$

The estimation error is [-3.4%, +3.8%] compared to reference IMEC NetZero values [6], which translates into a maximum error of ±49 g CO₂e/cm².

## 3.2 Carbon footprint of 3D-NAND components

<figure><img src="image_4.png" /><figcaption>Figure 3: Internal structure of a 3D-NAND die</figcaption></figure>

### 3.2.1 Vertical NAND flash
With this first model in hand, it is possible to compute an approximation of the carbon footprint of the manufacturing of an integrated circuit. This model is based on data available for logic circuits, like processors (CPU, GPU, DSP) or specialized dedicated digital integrated circuits. Applying this model to other types of circuits should be feasible as the notion

<footnote n="1">¹Values reported by https://netzero.imec-int.com (2024-09) in its public version, assuming a worldwide carbon footprint of electricity.</footnote>
of process or technology node is embedded in the model: counting the number of processing steps is sufficient to retrieve a proper embodied carbon estimate. One difficulty in the enumeration of process steps involved in the fabrication of a silicon wafer is to rely on a consistent definition of a processing step. Equation 3 applies to processing steps according to the definition of IMEC. However, depending on the field of work a processing step may be comprised of several sub-steps. For instance, lithography may be considered as a single step in the field of circuit engineering, but can count as several unitary steps (photoresist, trimming, cleaning) in the field of LCA [16].

In order to increase the storage of NAND memory, manufacturers succeeded, using a succession of Oxyde and Nitride layers, in stacking charge trap flash transistors in the vertical direction, opening a new dimension to increase density of information per area unit of silicon. With such stacked transistors, traditional 2D metal connections have been replaced by a stair-case etching at the boundaries of the flash matrix, where each layer can be accessed via a metal connection (word lines). To employ the carbon footprint model on 3D-NAND flash memory embodied carbon assessment, we need to estimate the number of fabrication steps involved in producing a flash circuit in order to capture the complexity involved in fabricating nitride/oxide layers, the staircase structure of the die, and its associated word lines, as shown in Figure 3. A streamlined model assumes that the number of steps depends on the number of stacked transistor layers. We propose a second affine model, this time to determine the number of production steps: a constant term represents the early and final stages of chip production, while a proportional factor accounts for the additional operations needed to build the intermediate layers, as modelled in expression (4).

$$N_{\text{steps}} = K + M \cdot N_{\text{layers}} \quad (4)$$

This definition allows the expression of a general solution based on model (3) which yields the GWP from the 3D NAND silicon die, defined by its number of layers:

$$G_{\text{Chip}} = S_{\text{Die}} \cdot (\alpha + \beta \cdot (K + M \cdot N_{\text{Layers}})) \quad (5)$$

Which can be simplified by introducing constants specific to 3D NAND silicon $\gamma = \alpha + \beta \cdot K$ and $\delta = \beta \cdot M$

$$G_{\text{Chip}} = S_{\text{Die}} \cdot (\gamma + \delta \cdot N_{\text{Layers}}) \quad (6)$$

According to Xiao et al. [21], which detail the steps involved in the 3D Flash fabrication process, the fabrication of a 3D NAND component follows a typical outline:

* Peripheral CMOS process steps. The common transistors are built at the periphery of the Flash matrix. Those transistors are needed to feed the flash strip and read the output values.

* Multi-layer-deposition and staircase-formation process step. (20 + 4*N). This sequence involves the repetition of deposition of Oxyde/nitride layers to form the stacked transistors. With each Oxyde-nitride pair, is a step in the staircase to have direct access to the flash transistors.

* 3D NAND channel formation process steps. The insulation of the channel is then performed.

* Process steps for the isolation module of 3D-NAND. Sections of flash transistors are isolated into individual strips.

* Process steps of the contact and interconnect module of 3D-NAND. At last the final metal interconnections are set to have access to word lines.

This fabrication sequence is summarized in Table 1, with an estimation of the number of steps required. Those values will serve as a reference for the estimations of our model, but more refined number of steps could be used in order to get a more precise estimation.

<table><caption>**Table 1: Steps involved in 3D-NAND fabrication, N stands for the number of layers**</caption><thead><tr><th>NAND structure</th><th>High-level steps</th></tr></thead><tbody><tr><td>Peripheral CMOS</td><td>58</td></tr><tr><td>Multi-layer-deposition and staircase formation</td><td>20 + 4N</td></tr><tr><td>Channel formation</td><td>16</td></tr><tr><td>Isolation module</td><td>19</td></tr><tr><td>Contact and interconnect module</td><td>66 + 0.3N</td></tr><tr><td><strong>Total</strong></td><td><strong>179 + 4.3N</strong></td></tr></tbody></table>

$$N_{\text{Steps}} = 179 + \frac{43}{10} \cdot N_{\text{Layers}} \quad (7)$$

Although the number of steps per layer may appear to be relatively low in comparison to the total fabrication process, recent Flash devices can have over 200 layers<fnref n="2" />, which increases the total number of steps up to 1176. As a comparison, a micro-processor produced in 3nm technology node accounts for 1,300 steps [6].

### 3.2.2 In-package wafer stacking.
Figure 4 illustrates that the complexity of a 3D-NAND Flash component extends beyond the number of layers in a die; it also involves the stacking of multiple dies within a package. Some components can include up to 16 dies in a stacked configuration<fnref n="3" />. Hence, to estimate the total carbon footprint of a Flash chip, the number of dies ($N_{Dies}$) must also be considered. By composing Equations (3) and (7), and factoring in the number of dies and their area, we obtain the following equation:

$$G_{\text{Chip}} = N_{\text{Dies}} \cdot S_{\text{Die}} \cdot (\gamma + \delta \cdot N_{\text{Layers}}) \quad (8)$$

where $S_{Die}$ is the silicon area of one die in square centimeters.

### 3.2.3 Multiple-chip devices.
Most SSD devices contain multiple flash memory chips, from 2 to 16, as shown in Figure 5. The total carbon emissions associated with the production of an SSD must account for the number of chips in the device:

$$G_{\text{SSD}} = N_{\text{chips}} \cdot N_{\text{Dies}} \cdot S_{\text{Die}} \cdot (\gamma + \delta \cdot N_{\text{Layers}}) \quad (9)$$

As a first estimation, based on the number of steps deduced in Table 1, we obtain $\gamma = 4.73 \times 10^{-3}$ and $\delta = 3.87 \times 10^{-5}$ for $S_{Die}$ expressed in mm<fnref n="2" />.

<footnote n="2">²For example, the YMTC Xtacking 3.0 technology</footnote>

<footnote n="3">³For example, Micro B47R FortisFlash technology</footnote>
<figure><img src="image_5.png" /><figcaption>Figure 4: Hierarchy of a SSD drive chip</figcaption></figure>

<figure><img src="image_6.png" /><figcaption>Figure 5: Hierarchy of a SSD drive at the PCB level</figcaption></figure>

### 3.2.4 Silicon area estimation.
Having access to the size of the silicon die within a package is not a simple task. Approaching the die size using a systematic package to die ratio can be used, but is far from being reliable. The same silicon die can be employed in different packages to suit different applications, which means that the relative size of the die compared to the size of the package is not a sufficient proxy, especially if the SSD is the first contributor to the GWP of a device, a proper estimation must be employed. Even X-ray imaging can leave some uncertainty in the measurements: silicon, having a low atomic mass, is quite transparent to X-rays compared to other materials, especially the metallic parts. Distinguing the borders of the silicon die can be tricky and lead to errors. Figure 6 shows a sample of X-ray imaging of a flash device used in a M.2 SSD. The wire-bounding is clearly visible at the top and bottom of the image. One can imagine those mark the limits of the silicon die, but there is no certainty here. Moreover the left and right boundaries are completely invisible. Destructive techniques are by far the most reliable ones, but are often not suitable for expensive equipment. Additionally, it is best to avoid destroying perfectly functional components.

An alternative is to find a proxy that is reliable enough to get a proper estimation of the silicon area, based on easily accessible information. The dependency between the storage capacity and the silicon area can be a solution. A naive model would assure a proportional relationship between silicon area and storage capacity, however as shown in figure 7, this linearity is only true for a given

<figure><img src="image_7.png" /><figcaption>Figure 6: X-Ray imaging of a flash chip on a M.2 SSD</figcaption></figure>

number of bits per cell. For example, the linear relationship is clearly visible in red for flash storage using QLC (4 bits per cell) technology. In a more general expression, the number of cells can be considered as proportional to the silicon area. Indeed, when considering bits per cell, number of layers, the following expression can yield the silicon area:

$$C = S \cdot \eta \cdot d \cdot N_{Layers} \quad (10)$$

Where:

<figure><img src="image_8.png" /><figcaption>Figure 7: Storage density in GB per mm², plotted against the number of Flash technology layers. The disc size indicates the capacity of each device, while the color represents the bits per cell.</figcaption></figure>

* C is the die capacity in GB

* S is the silicon area in mm²
* η is a scaling constant, which can be defined as the cell density of flash technology. The value η =2.61 × 10⁻³ has been determined using statistical regression on all the data used for Figure 7

* d is the number of bits stored per Flash cell. Typical SSDs use TLC (3 bits per cell) or QLC (4 bits per cell).

* N is the number of layers of the 3D NAND technology.

As shown in Figure 7, once the number of bit *D* per cell is fixed, the cell density per mm² can be considered as proportional to the number of layers. As visible on the figure, the SSD capacity does not affect this linearity.

When merging Equations 9 and 10, we can obtain the equation that gives the carbon footprint for a flash device:

$$G_{\text{SSD}} = \frac{C_{\text{GB}}}{\eta \cdot d} \cdot \left( \delta + \frac{\gamma}{N_{\text{Layers}}} \right) \quad (11)$$

<table><caption>Table 2: Model parameters summary</caption><thead><tr><td>Parameter</td><td>Value</td><td>Description</td></tr></thead><tbody><tr><td>δ</td><td>3.87 × 10<sup>-5</sup></td><td>Common carbon impact of NAND production</td></tr><tr><td>γ</td><td>4.73 × 10<sup>-3</sup></td><td>Carbon impact per layer</td></tr><tr><td>η</td><td>2.61 × 10<sup>-3</sup></td><td>Cell density of NAND silicon</td></tr></tbody></table>

The parameters derived from statistical regressions using available characteristics in the database are summarized in Table 2.

Note that the number of chips *N*<sub>Chips</sub> and dies *N*<sub>Dies</sub> have been omitted from Equation (11) because the capacity *C*<sub>GB</sub>, which stands for the total capacity of the flash drive, encompasses the total silicon area. The silicon area of the controller and any DRAM cache should ideally be considered in the IC-related carbon footprint. However, the modeling of these components is kept for future work. The proposed model can be employed to model Flash components in order to determine their carbon footprint. One major issue regarding the estimation of the environmental impacts of silicon devices is the lack of publicly accessible information. The integrated circuit production being a highly competitive market, fabrication process is kept secret by manufacturers. For this reason, it is a hard task to retrieve data on the process node. However, our model relies exclusively on the number of chips, dies and number of layers, as this information is publicly shared by major manufacturers to highlight their technological progress to customers.

# 4 Results

## 4.1 SSD dataset results

Using the same comprehensive database [2] containing detailed specifications for over 2,000 SSD devices, we identify 1,256 devices with sufficient information to apply our model. This allows us to estimate the carbon footprint for a significant number of devices. Figure 8 shows the embodied carbon emission of the SSDs for various capacities in GB. For reference, 335 values extracted from Microsoft<fnref n="4" /> and HP<fnref n="5" /> are included in green and red. One first notable

<figure><img src="image_9.png" /><figcaption>Figure 8: Estimated carbon impact (log-log scale) of fabrication by applying our model (blue violins) to a large number of 3D NAND chips and the comparison to published results from HP (green stars) and Microsoft (red stars) in their Product Carbon Footprints. Associated linear regression of GWP in kg CO₂e per capacity (in GB) is shown in solid lines</figcaption></figure>

trend from this figure is the apparent proportionality of the results from each provider. For instance, a linear regression on our model estimations yields a slope of 22 g CO₂/GB (R² = 0.72). The same linear trend can be observed for estimations from Microsoft with 56 g CO₂/GB (R² = 0.43) and from HP with 128 g CO₂/GB (R² = 0.88). However, there is a large variation in the results, especially for capacities below 1 TB. This variation can be related to the different used hierarchies (number of dies and chips, die area). In particular, at the lowest capacities, older SSDs using 2D silicon (which implies a high number of chips and stacked silicon dies to achieve the required capacity) coexist with some more recent SSDs based on 3D NAND. Another dimension that can explain the observed variability is the number of bits encoded per transistor: increasing the number of bits per cell has the effect of increasing the carbon efficiency of SSDs. Instead of storing one bit per transistor or Single Level Cell (SLC), the number of bits per transistors has been increased to 2 (Multi Level Cell or MLC), 3 (Triple Level Cell or TLC), or 4 (Quad Level Cell or QLC). QLC is currently commonly used. This technology makes it possible to raise the capacity without significantly impacting the carbon footprint as the silicon area remains the same. However multiplying the number of bits per cell does not seem a long term solution to mitigate the carbon impact of SSDs, as it may lower the durability of the drives and increase their power consumption [7].

## 4.2 Comparison of model inference with reported impact from manufacturers

In Figure 8, the red and green stars in the graph represent the reported carbon footprints of SSDs from HP and Microsoft's "Product Carbon Footprint" (PCF) documentation. A clear gap exists between

<footnote n="4">⁴https://aka.ms/EcoProfiles</footnote>

<footnote n="5">⁵http://www.hp.com/go/carbonfootprint</footnote>
our model’s projections and these manufacturer reports, with our estimates showing an 5.8× difference compared to HP and a 2.5× difference compared to Microsoft. Our model accounts only for the silicon-related carbon emissions, whereas the PCF reports likely include packaging, PCBs, cases, connectors, and additional ICs. While these elements contribute to the total environmental impact, silicon, especially large Flash devices, remains the largest contributor to the global warming potential (GWP) of SSDs [5]. The disparity between our model and the manufacturer reports could also stem from differences in the used carbon impact models. Whereas our research is based on the IMEC Netzero model, the PCF data relies on other models, like the MIT PAIA tool [1], which uses the Ecoinvent database [8]. As noted by Pirson [18], the ratio between these models can vary significantly (by a factor of 2 to 7 depending on the technology node), which aligns with the discrepancies observed in this study.

For higher capacities (above 1 TB), the limited number of sustainability reports from manufacturers on devices equipped with large storage devices restricts the scope of our comparison. This may also explain the discrepancies between various source of estimations. With the introduction of 3D technologies, and the use of multiple bits stored by cell, the flash technology has evolved since its introduction, and legacy models based on 2D SLC NAND may not be relevant for more recent fabrication processes. Future sustainability reports will provide more data, allowing further studies to confirm whether these trends continue to hold.

# 5 Discussion

## 5.1 Carbon efficiency per GB

When applying our model to the characteristics of SSD devices found in the database [2], it can be noticed in Figure 8 that the devices with a higher density have a carbon footprint that is below a linear projection with respect to their capacity in Gigabytes. In Figure 9, we plot the carbon intensity of SSDs—defined as the ratio of carbon impact to drive capacity in kg CO₂e per GB—against the number of layers in the component’s technology. The results show a clear decrease in carbon intensity as the number of layers increases.

What can be observed is that higher capacity SSDs (red patches) usually rely on more advanced technologies (more layers). This is consistent with expectation, as multi-layer technologies are developed to provide a higher density of information while limiting the total silicon area. Higher density leads to a better carbon efficiency when using the more advanced technologies, which is illustrated by the blue curve showing a decrease with a trend in $N_{Layers}^{-1}$ as predicted by our model. A similar trend can be observed with logic devices, where the carbon footprint per transistor lowers for the more advanced technologies. This phenomenon may seem counter-intuitive as the literature has rather shown an increase in the environmental impacts when using smaller technology nodes. The important aspect to keep in mind is the metric used to estimate carbon impact. For logic devices, the functional unit is often a silicon area, but this metric fails to embrace the shrinking factor of the successive technologies. Compared to 28 nm technology node,

<figure><img src="image_10.png" /><figcaption>**Figure 9:** Carbon intensity as estimated by our model in the dataset (log scale), plotted against the number of Flash technology layers. The disc size indicates the total silicon area of each device, while the color represents the SSD capacity.</figcaption></figure>

5 nm devices pack more than 10 times the number of transistors per surface unit<fnref n="6" />, while having only twice the carbon footprint [6].

The main driver for the growing impact of silicon devices is not the technology itself, but rather the exponential usage growth that technology triggers [9]. This rebound effect arises because the commoditization of Flash, driven by its affordability and scalability, enables pervasive over-provisioning in data centers, consumer electronics, and disposable IoT devices. As 3D stacking made flash production more efficient, the plummeting cost per gigabyte (a 1000× reduction in the last 20 years<fnref n="7" />) has normalized practices like storing vast quantities of rarely accessed data, deploying short-lived gadgets with non-upgradable storage. The carbon footprint of flash memory must now be considered not only in terms of the efficiency of its manufacturing process per GB, but also in terms of the systemic consequences of its abundance.

Although our study focuses solely on the carbon impact of the flash chips, this initial assessment can still guide architecture choices. To achieve a more comprehensive evaluation of the full device’s environmental impact, additional data on components (PCB, DRAM, connectors) will be needed. Future studies and more detailed manufacturer reports are essential to validate and expand upon the trends observed here. The exponential trend in NAND memory carbon footprint has a significant impact in the apprehension of the LCA of computers. In the last decade, the carbon impact attributed to the fabrication of computers was shared among various components: silicon devices (RAM, CPU, and other ICs) taking a major part of the impact, but also mechanical enclosure, cooling and power supply. With escalating storage capacity, the SSD only can be responsible for up to 80% of the carbon impact [5]. This impact will continue to grow with increasing demand. As the main component to drive the environmental impacts of the computing devices, additional studies should be provided to get precise assessment. Due to the multiplicative effect of 3D NAND and stacking

<footnote n="6">⁶According to reported data in https://en.wikipedia.org/wiki/Transistor_count</footnote>

<footnote n="7">⁷According to reported data in https://jcmit.net/flash2015.htm</footnote>
technologies, a special care must be given to the estimation of the
die area.

## 5.2 Sensitivity analysis

The model expressed in Equation 11 depends on technical parame-
ters, such as the capacity $C_{GB}$, the number of layers $N_{Layers}$ and
the type of flash cell $d$ (SLC, MLC, TLC, QLC). Those parameters
are publicly advertised by manufacturers or can be deduced from
the chip reference, and therefore can be considered as a solid basis
for the estimation of the carbon footprint of the SSD. The constants
in the model however are extracted from statistical analysis. De-
spite being from a quite large database, there is some uncertainty
associated with the constants $\eta$, $\gamma$, and $\delta$ used in our model.

To evaluate the impact of this uncertainty on the results of the
model, we performed a sensitivity analysis on a set of 7 imaginary
SSDs, one for each range of capacity. For each capacity, the pa-
rameters $d$ and $N_{Layers}$ were chosen by taking the median value
of the drives with the same capacity range in the database. The
parameters selected for the 7 drives are shown in Table 3.

<table><caption>Table 3: Typical SSD technologies, according to database [2], used for sensitivity analysis</caption><tr><td>C<sub>GB</sub></td><td>256</td><td>512</td><td>1024</td><td>2048</td><td>4096</td><td>8192</td><td>16384</td></tr><tr><td>N<sub>Layers</sub></td><td>64</td><td>96</td><td>162</td><td>176</td><td>176</td><td>96</td><td>164</td></tr><tr><td>d</td><td>3</td><td>3</td><td>3</td><td>3</td><td>3</td><td>3</td><td>3</td></tr></table>

The sensitivity analysis was performed with a normal variation of the constants $\eta$, $\gamma$, and $\delta$ with a standard deviation of 20% relative to the values proposed in this paper. The results are shown in Figure 10.

The result shows a large variation, around one order of magni-
tude for extreme values when the constant shift contribute towards
the same variation (for example when $\eta$ gets smaller while $\gamma$ and
$\delta$ get larger). This can be an issue if the number of steps is not
properly estimated, as $\gamma$ and $\delta$ could be affected in the same direc-
tion. However, when this cumulative phenomenon is not present,
the variation remains within a more reasonable range with a stan-
dard deviation close to a 2x factor. This can seem a large error, but
as shown by [18], LCA of semiconductor is prone to wide differ-
ences from one methodology to another. Reducing the uncertainty
on the constants of the model would give more soundness of the
estimations.

## 6 Conclusion

In this study, we have proposed a novel model for estimating the
carbon footprint of 3D NAND devices, utilizing the number of steps
as a proxy for the employed technology. The model estimates a
device embodied carbon impact, based solely on publicly accessible
characteristics like the technology used (number of layers, number
of bits per cell) and the storage capacity of the component. Our
results are based on more than 1,200 SSD devices of the market
and show a steady increase of the carbon impact with increasing
capacity, either on data obtained by our model or with estimations
provided by manufacturers. A deeper analysis shows that the more

<figure><img src="image_11.png" /><figcaption>Figure 10: Sensitivity analysis with normal variations of $\eta$, $\gamma$ and $\delta$ of 20%.</figcaption></figure>

advanced technologies using numerous layers of stacked transistors
are more carbon efficient and can reduce the impact of those devices
on the environment. We come to the conclusion that lowering
silicon area by using smaller chips, with low die stacking, maximizes
the carbon efficiency of storage systems. However, the continuous
increase in the demand of storage capacity fosters die stacking and
larger chips.

## Acknowledgments

This study is funded by the France2030 ESOS Project - Electronics: Sustainable, Open and Sovereign, operated by French ANR (Agence Nationale de la Recherche).

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