# Multi-objective Optimization based Design of 3-L Inverters Considering an Extensive WBG Semiconductors Library

Meriem Ouzouigh, Timothé Delaforge, Alain Lacarnoy, Vinicius Kremer, Jean-Luc Schanen

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## ► To cite this version:

Meriem Ouzouigh, Timothé Delaforge, Alain Lacarnoy, Vinicius Kremer, Jean-Luc Schanen. Multi-objective Optimization based Design of 3-L Inverters Considering an Extensive WBG Semiconductors Library. The 26th European Conference on Power Electronics and Applications, GDR SEEDS France & EPE Association, Mar 2025, Paris, France. 10.34746/epe2025-0157. hal-05108293

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Submitted on 11 Jun 2025

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# Multi-objective Optimization based Design of 3-L Inverters
Considering an Extensive WBG Semiconductors Library

Meriem Ouzouigh¹,³, Timothé Delaforge², Alain Lacarnoy¹, Vinicius Kremer¹, Jean-Luc Schanen³

¹ Schneider Electric, Industrial Automation, 38000, Grenoble, France.

² Bern University of Applied Science, E-mobility lab, 2502, Biel, Switzerland.

³ Univ. Grenoble Alpes, CNRS, Grenoble INP, G2ELAB, 38000, Grenoble, France.

E-Mail: meriem.ouzouigh@se.com

***Index Terms***—Inverter design, Design optimization, SiC MOSFET, Multi-level inverters, Multi-objective optimization.

***Abstract***—This paper presents a comparative analysis of the performance of 3-Level DC/AC inverter topologies in terms of price, loss, and volume. An extensive library of commercially available SiC and GaN semiconductors was implemented to create performance maps for the 3-L topologies across various power levels, aiding power electronics engineers in making informed design decisions. The analysis employs a highly precise design-by-optimization methodology to derive the optimal Pareto front for each topology. To ensure a fair comparison and minimize expert bias, all degrees of freedom were retained, and no design rules were imposed during the design flow. The optimization results provide quantitative insights into the enhanced capabilities of 3-L inverters utilizing WBG technology.

## I. INTRODUCTION

The continuous advancement of Wide Band Gap (WBG) semiconductors, particularly Silicon Carbide (SiC) and Gallium Nitride (GaN), is driving the development of next-generation high-performance, efficient, and compact power inverters [1], [2]. WBG semiconductors exhibit superior material properties compared to conventional Silicon devices (Si), enabling enhanced performance and efficient operation at high switching frequencies. In power conversion applications, researchers have been extensively reassessing the new capabilities of power converter topologies since the early emergence of these technologies. Multilevel inverter topologies are popular for their reduced $dv/dt$ stress, favorable harmonic profiles, and lower semiconductor voltage stress compared to the conventional 2-Level voltage source inverter (VSI) [3], [4]. As a result, 3-Level inverters are

gaining popularity in low voltage applications. [5], [6]. The superior performance of the various power inverter topologies based on WBG semiconductors compared to conventional Si IGBTs is well-established. [7]–[11]. Consequently, the focus has shifted to assessing whether WBG semiconductors provide greater advantages to specific topologies over others.

Performance comparison of the various 3-Level inverter topologies have been conducted in [5], [6], [12]–[15]. However, to the best of the author’s knowledge, a performance map of the optimal achievable performances in terms of price, loss, and volume of 3-level inverters based on an extensive library of commercially available WBG semiconductors at various power levels has yet to be conducted.

This paper presents a comprehensive analysis of the performance of 3-Level inverter topologies in terms of price, loss, and volume for different power levels ranging from 15kW to 75kW. The Pareto of optimal design is based on a list of commercially available components, highlighting the feasible limits rather than the theoretical ones. A WBG semiconductor library with more than 30 references from 3 different manufacturers, featuring an $Rds_{on}$ ranging from 7mΩ to 120mΩ, was implemented to represent a meaningful sample of market availability.

Section II presents the considered 3-Level topologies and their modeling methodology based on semi-analytical time-based current and voltage waveforms. Section III discusses the performance models of semiconductors and passive components, including losses, temperature, and volume estimation. Section IV provides an overview of the formulated design optimization problem that yields the Pareto of optimal solutions. Section V presents the optimal performance maps of the different topologies at 15kW, 37kW and 75kW. Finally, a summary of our main findings is provided in Section
## VI.

## II. 3-LEVEL INVERTER MODELING TECHNIQUE

### A. Considered topologies and their control

The conducted analysis is limited to the common 3-phase, 3-level topologies depicted in Figure 1, namely 3-L ANPC inverter, 3-L T-type inverter, 3-L FlyCAP inverter, and 3-L SNPC inverter known also as Multiplexed inverter. The topologies are assessed for variable speed drive (VSD) applications; hence, a solution with an output sine wave filter is adopted to limit the high $dv/dt$ at the load.

The adopted control strategy is space vector modulation. For the 3-L T-type inverter, the carriers are in phase disposition, while for the 3-L FlyCap inverter, the carriers are phase-shifted. The 3-L ANPC inverter offers greater flexibility with multiple control strategies for its six switches per phase. These include the well-known PWM-1, PWM-2, and PWM-3 techniques, as introduced in [16], along with the promising PWM-4 technique discussed in [17]. The optimal PWM technique depends on the specifications of the load; therefore, all four cited strategies will be employed to ensure a comprehensive assessment of this topology. Similarly, the various control sequences developed in [18] for the 3-L SNPC inverter will also be included here.

### B. Modeling methodology

Numerous modeling techniques for power inverters have been introduced in the literature [19]. Selecting the appropriate approach involves balancing model development difficulty, desired accuracy, and simulation time inside an optimization loop. This paper examines various control strategies for 3-L ANPC and 3-L SNPC inverters. As a result, deriving the analytical expressions is fastidious and time-consuming. Consequently, a semi-analytical time-based model was developed and implemented in the MATLAB environment. This methodology

involves reconstructing the inverter's current and voltage waveforms from their low-frequency (LF) and high-frequency (HF) components, using control laws and topology equations. This process will be illustrated for the 3-L T-type inverter, as shown in Figure 2.

<figure><img src="image_3.png" /><figcaption>Fig. 2: 3L T-type inverter with LF and HF decomposition</figcaption></figure>

The targeted LF components of the current and voltage waveforms are determined based on the operating point specifications. Using the LF voltage reference and the control laws, the PWM states of the switches are derived, which modulates the DC link bus accordingly. This results in rectangular voltage stair waveforms, as shown in Figure 3 (a). These waveforms are characterized by their common mode (CM) component shown in Figure 3 (b) and differential mode (DM) component shown in Figure 3 (c). From these waveforms, the HF voltage across the inductor is obtained, as depicted in Figure 3 (d), and consequently used to derive the inductor's HF current. The inductor's LF current is determined from the load current reference and the LF current in the filter capacitor.

<figure><img src="image_4.png" /><figcaption>Fig. 1: 3-L inverter topologies (a) 3-L ANPC, (b) 3-L T-type, (c) 3-L FlyCap, (d) 3-L SNPC</figcaption></figure>
<figure><img src="image_5.png" /><figcaption>(a)</figcaption></figure>

<figure><img src="image_6.png" /><figcaption>(b)</figcaption></figure>

<figure><img src="image_7.png" /><figcaption>(c)</figcaption></figure>

<figure><img src="image_8.png" /><figcaption>(d)</figcaption></figure>

Fig. 3: 3L TType inverter Phase 1 voltage waveforms. (a) Line voltage, (b) Common mode voltage, (c) Differential mode voltage, (d) inductor voltage

From the derived total inductor current (HF + LF) shown in Figure 4 (a), along with the topology equation and switch states, the current and voltage waveforms in the capacitor and semiconductors are determined, as illustrated in Figure 5.

The described approach yields results identical to those of circuit simulator software, assuming a feasible design with balanced sinusoidal output waveforms that meet the reference, and a stable DC-link capacitor voltage with no current in the neutral wire. Figure 4 and 5 shows the waveforms obtained by the model and Plecs.

<figure><img src="image_9.png" /><figcaption>(a) Global overview</figcaption></figure>

<figure><img src="image_10.png" /><figcaption>(b) Zoom</figcaption></figure>

Fig. 4: Inductor current Matlab Vs Plecs

<figure><img src="image_11.png" /></figure>

<figure><img src="image_12.png" /></figure>

Fig. 5: Semiconductor current Matlab Vs Plecs

### III. SEMICONDUCTORS AND PASSIVE COMPONENTS
PERFORMANCES

#### A. Semiconductors electro-thermal model

A Rigorous estimation of semiconductor losses is of great importance to ensure a fair comparison of the multiple SiC and GaN references across the different manufacturers. various numerical and nonlinear models were introduced in literature [20]–[22]. Authors in [23] introduced a virtual prototyping technique of double pulse circuit that use a behavioral mathematical model of WBG semiconductors to estimate the switching losses by solving the circuit ordinary differential equation. This approach, based on datasheet information aligns with our analysis and is used to characterize the switching losses of the semiconductors references over their operating current, voltage and temperature range, to generate loss map lookup tables as shown in Figure 6.

<figure><img src="image_13.png" /></figure>

Fig. 6: LUT - Semiconductors switching energy

The time-based current waveforms of the switches obtained from the inverter model shown in Figure 5 are used to derive the semiconductors performances, for a great accuracy the full waveforms will be used instead of an averaged values. The conduction losses
are straightforwardly obtained using the $R_{ds}on$ equation, while the switching losses should be assessed at each turn on/off sequences with the corresponding current and voltage. To account for the temperature sensitivity, it's evolution will be estimated at the rate of each high frequency period. The adopted thermal model is based on Cauer thermal network of 4th order, the RC elements are fitted from the transient thermal impedance curve Zth given in the datasheet. Accordingly, a dynamic electro-thermal model was developed.

Figure 7 illustrate the loss and temperature estimated for 3-L T-type inverter. Figure 7 (a) show the conduction and switching losses of semiconductor $T_1$ over one LF period Figure 7 (b) shows the temperature evolution over multiple LF period until steady state for a 1200V SiC reference. Similarly, Figure 7 (a)-(b) shows the same parameters for semiconductor $T_2$ for a 650v GaN reference.

<figure><img src="image_14.png" /><figcaption>Fig. 7: 3L T-type waveforms, (a) $T-1$ loss, (b) $T_1$ Temperature evolution, (a) $T-2$ loss, (b) $T_2$ Temperature evolution,</figcaption></figure>

## B. Inductor model

Inductor model is defined using the selected magnetic material, core dimensions, winding type, section and material. For simplicity, this work only considers toroidal cores. The time-based flux density waveform is first derived from the inductor current, design variables and $B(H)$ curves model. These waveforms are then used to estimate the core losses based on the improved general Steinmetz equation (iGSE). Winding losses are

modeled using the harmonics components of the inductor current waveforms based on Dowell equivalent sheets. The detailed inductor model can be found in [24]. The inductor design feasibility is guaranteed through a set of constraints on magnetic material saturation, core loss density and current density.

## C. Capacitor model

Capacitor model is based on the datasheet information. The losses are estimated using the equivalent series resistance, and thermal constraints are accounted for by ensuring that the capacitor current harmonics are below the maximal allowable current curve vs frequency given by the manufacturer.

## D. Inverter overall performances

topologies designs are evaluated based on their price, loss, and volume. The overall loss and price are calculated as the sum of the individual contributions of each component. The volume is estimated based on the total footprint of the components multiplied by the maximum height.

# IV. INVERTER TOPOLOGY'S OPTIMAL DESIGN

## A. Methodology

Design by optimization methodology is performed to obtain the Pareto of the optimal achievable performances. An optimization routine based on the Grid Elitist Multi-objective genetic algorithm described in [25] is utilized. The algorithm search in the design space for the inputs that minimize the price, loss, and volume. In this Analysis, expert rules are not introduced in the design process; only the constraints defined in table I are employed to eliminate unfeasible configurations. The temperature of semiconductors is limited to 120°C to allow a margin for overload operations, as the design process is carried out at the nominal point.

<table><caption>TABLE I: Optimization Constraints</caption><thead><tr><td>Entity</td><td>Symbol</td><td>Unit</td><td>Value</td></tr></thead><tbody><tr><td>Load voltage ripple</td><td>V<sub>load</sub></td><td>V<sub>rms</sub></td><td>4</td></tr><tr><td>DC-link voltage ripple</td><td>V&#773;<sub>dc</sub></td><td>%</td><td>4</td></tr><tr><td>Max Temperature</td><td>T<sub>j,max</sub></td><td>°C</td><td>120</td></tr><tr><td>Inductor core loss density</td><td></td><td>mW/cc</td><td>5</td></tr><tr><td>Inductor current density</td><td></td><td>A/mm<sup>2</sup></td><td>6 "Cu" &amp; 3 "Al"</td></tr></tbody></table>
## B. Design variable

Design variables are based on a library of discrete numbers pointing towards device references and their configuration. Only the switching frequency is continuously mapped from 10kHz to 100kHz. Three-level topologies have different constraints on their constituent semiconductors. in the 3-L T-type inverter, the middle leg semiconductors $T_3$ and $T_2$ block half of the DC bus, while the semiconductors in the horizontal leg, $T_1$ and $T_2$ block the entire DC bus. Similarly, in the 3-L SNPC inverter, the chopper stage semiconductors $T_{p1}$ and $T_{p2}$ block half of the DC bus, while the inverter stage semiconductors $T_1$ and $T_2$ block the entire DC bus. In the 3-L ANPC inverter, all semiconductors have the same voltage rating of half the DC bus; however they have different current stress depending on the chosen control strategy. In PWM-1 $T_5$ and $T_6$ switch at a low frequency of $f_{load}$, while the other semiconductors switch at a high frequency $f_{switch}$. To account for the varying current and voltage stress requirements, independent input variables for semiconductor references are established for each commutation cell. As a result, for the 3-L T-type and SNPC inverters, two semiconductor reference design variables are defined. For the 3-L ANPC inverter, three semiconductor reference design variables are defined. The same applies to the number of possible associations in parallel.

Other design variables include, magnetic material reference, core size, winding, number of turns, number of wire in parallel, capacitor reference, number in series and parallel etc.

## C. Component library

The component libraries contain lists of commercially available devices along with their corresponding data, including price, footprint, characteristics, and behavioral models.

* Semiconductor library: 32 references of SiC and GaN devices, including information related to switching losses LUT, RC network, $Rds_{on}$ model etc.

* Magnetic material library: 21 reference of alloys composite, including information related to $B(H)$ model, steinmetz coefficients etc.

* Magnetic core library: list of standard toroidal core sizes.

* Winding library: +200 reference of litz and solid wires

* Film capacitor library: 20 references.

* DC-link capacitor library: 20 references of Electrolytic and dc-link film capacitors.

## V. 3-L INVERTER PERFORMANCES MAP

This section presents the Pareto comparison results of the considered 3-L inverter topologies at power levels of 15kW, 37kW and 75kW, the fixed specification are given in table II.

<table><caption>TABLE II: Optimization specification</caption><thead><tr><td>Entity</td><td>Symbol</td><td>Unit</td><td>Value</td></tr></thead><tbody><tr><td>Active power</td><td>P<sub>a</sub></td><td>kW</td><td>15 , 55 , 75</td></tr><tr><td>Power factor</td><td>cos φ</td><td></td><td>0.85</td></tr><tr><td>Voltage ref</td><td>v<sub>ref</sub></td><td>V<sub>rms</sub></td><td>230</td></tr><tr><td>DC Bus</td><td>V<sub>DC</sub></td><td>V<sub>rms</sub></td><td>750</td></tr><tr><td>Grid frequency</td><td>f<sub>g</sub></td><td>Hz</td><td>50</td></tr><tr><td>Heatsink Temp</td><td>T<sub>hs</sub></td><td>C</td><td>80</td></tr></tbody></table>

Figures 8 to 10 depict the results of the 3D multi-objective optimization. Sub-figures 8 to 10 (a) show the 2D projection along the Price-loss axis, while sub-figures 8 to 10 (b) show the 2D projection along the Volume-loss axis. Each data point in the Pareto front represents a feasible design along with its bill of materials.

For instance, Figures 8 to 10 show that no particular topology outperforms the others with respect to the three objectives simultaneously. To effectively analyze the results, we decompose the Pareto fronts into three regions. The first region focuses on minimal volume regardless of price and losses, which is particularly relevant in applications where weight is a primary concern, such as in the aerospace field. The second region aims to minimize losses regardless of cost and volume, suitable for applications where high efficiency is paramount, even at the expense of higher costs. Finally, the Trade-off region represents a balance between minimal price, loss, and volume, addressing the common industrial applications that require a compromise among these factors. In our application, we target the optimal cost design that meets an efficiency target ranging between 99% and 98.5%

Accordingly, In the power range from 15kW to 75kW, the 3-L T-type inverter stands out in the region of minimal loss, closely followed by the 3-L SNPC inverter. Within this Pareto region, the performance gap between these two topologies and the 3-L ANPC and 3-L Flycap widens with increasing power. At 15kW as shown in Figure 8(a), the curves of the topologies are closely grouped, however at 75kW as shown in Figure 10(a), the 3-L T-type and SNPC exhibit significantly better performance.

On the other hand, in the Trade-off region of the Pareto, the 3-L SNPC inverter demonstrates optimal
cost at efficiencies around 98.5% and remains relevant across the efficiency range 98.5% to 99%. It is closely followed by the 3-L T-type inverter. The 3-L FlyCAP curve also follows closely, as this topology experiences higher switching losses and additional costs associated with the flying capacitor. Finally, the 3-L ANPC exhibits the least favorable price-loss ratio performance due to its higher number of semiconductors.

In the loss-volume Pareto shown in Figures 8 to 10 (b), the 3-L SNPC topology demonstrates optimal volumes, which can be attributed to the DC-link capacitor sizing requirements. In the optimization constraints displayed in table II, the DC capacitor was sized to respect a maximum voltage ripple of 4%$V_{DC}$. Other

<figure><img src="image_15.png" /><figcaption>(a) Price-Loss 2D projection</figcaption></figure>

<figure><img src="image_16.png" /><figcaption>(b) Volume-Loss 2D projection</figcaption></figure>

<figure><img src="image_17.png" /><figcaption>(a) Price-Loss 2D projection</figcaption></figure>

<figure><img src="image_18.png" /><figcaption>(b) Volume-Loss 2D projection</figcaption></figure>

<caption>Fig. 9: Pareto at 37kW</caption>

sizing factors such as reactive power storage requirements and maximum allowable voltage surge in motor applications, were not taken into account. Therefore, the required capacitor value $C_{DC}$ was chosen to maintain $v_{dc} = \frac{1}{C_{DC}} \int i_{DC} dt < 4\%V_{DC}$. Since the 3-L SNPC control strategies displayed a DC-link current with the smallest harmonics at 150Hz this resulted in minimal volumes. On the other hand, the 3-L FlyCAP inverter exhibits the largest volume due to the presence of flying capacitors. It is important to note that only film capacitors were implemented in the database; ceramic capacitors might offer enhanced volume but come with other electrical constraints.

To summarize the comparative analysis, the 3-L
<figure><img src="image_19.png" /><figcaption>(a) Price-Loss 2D projection</figcaption></figure>

<figure><img src="image_20.png" /><figcaption>(b) Volume-Loss 2D projection</figcaption></figure>

<caption>Fig. 10: Pareto at 75kW</caption>

SNPC (Multiplexed) and the 3-L T-Type inverter are very promising topologies for industrial applications that aim for an optimal price-to-efficiency ratio. The Pareto analysis of the 3-L SNPC converged towards control strategy '8' [18], as it optimized the sizing requirements for passive elements, making this topology appealing for volume minimization

To analyze the WBG semiconductor references selected in the different Pareto fronts, we display in Figure 11 (a) - (b) the maximum junction temperature and its corresponding temperature ripple of the 3-L T-type inverter switch $T_1$ obtained at 37kW for the specification given in table II. In the minimal loss region, we find semiconductors with smaller $Rds_{on}$ and a trend for

paralleling them, which results in a slight increase of junction temperature 5°C and negligible temperature ripple. Conversely, in the region with minimal cost, the design variables converge towards the least expensive references that satisfy the defined constraints, which are naturally characterized by higher $Rds_{on}$, resulting in a junction temperature close to 120°C and high temperature ripples. The trade-off region is based on semiconductor references that have the optimal price-to-performance ratio.

<figure><img src="image_21.png" /><figcaption>(a) maximum junction temperature
3-L T-type switch $T_1$ Temperature ripple evolution</figcaption></figure>

<figure><img src="image_22.png" /><figcaption>Fig. 11: 3-L T-type semiconductor $T_1$ thermal perfoamances</figcaption></figure>

This analysis is valid for all assessed inverter topologies at different power levels. Finally, it's important to note that the semiconductor references dominating the Pareto datasets differ from one topology to another, highlighting the necessity of employing a large database to ensure a fair comparative analysis.
# VI. CONCLUSION

In this paper, the performance of 3-Level inverters is mapped in terms of price, loss, and volume based on a large library of commercially available Wide Band Gap semiconductors. The aim is to provide guidance for designers in choosing the most suitable inverter topology for their specific applications. Design by optimization methodology was used to derive the Pareto of the considered 3-L topologies, with a novelty in defining different semiconductor design variables for each switch, considering the varying current and voltage stress requirements, moreover, the time-based model approach allowed to easily take into consideration the different control strategies for 3-L ANPC and 3-L SNPC inverter to ensure a fair basis of comparison. 3-L T-type inverter achieves the least possible losses at power levels 15kW, 37kW and 75kW, positioning it as a viable topology for applications prioritizing highest efficiency, regardless of cost. On the other hand, the 3-L SNPC (Multiplexed) inverter offers optimized price-to-loss ratio in the efficiency range between 98% and 99% making it particularly interesting for industrial applications where cost competitiveness is a key consideration.

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