# ALICE upgrades during the LHC Long Shutdown 2

S. Acharya, R. Acosta Hernandez, D. Adamová, A. Adler, J. Adolfsson, D. Agguiaro, G. Aglieri Rinella, M. Agnello, F. Agnese, N. Agrawal, et al.

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## ► To cite this version:

S. Acharya, R. Acosta Hernandez, D. Adamová, A. Adler, J. Adolfsson, et al.. ALICE upgrades during the LHC Long Shutdown 2. Journal of Instrumentation, 2024, 19 (05), pp.P05062. 10.1088/1748-0221/19/05/P05062. [hal-04645565](https://hal.science/hal-04645565v1)

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# ALICE upgrades during the LHC Long Shutdown 2

To cite this article: S. Acharya et al 2024 JINST 19 P05062

View the article online for updates and enhancements.

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THE LARGE HADRON COLLIDER AND THE EXPERIMENTS FOR RUN 3 —
ACCELERATOR AND EXPERIMENTS FOR LHC RUN3

ALICE upgrades during the LHC Long Shutdown 2

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ALICE

ALICE Collaboration

E-mail: alice-publications@cern.ch

**ABSTRACT:** A Large Ion Collider Experiment (ALICE) has been conceived and constructed as a heavy-ion experiment at the LHC. During LHC Runs 1 and 2, it has produced a wide range of physics results using all collision systems available at the LHC. In order to best exploit new physics opportunities opening up with the upgraded LHC and new detector technologies, the experiment has undergone a major upgrade during the LHC Long Shutdown 2 (2019–2022). This comprises the move to continuous readout, the complete overhaul of core detectors, as well as a new online event processing farm with a redesigned online-offline software framework. These improvements will allow to record Pb-Pb collisions at rates up to 50 kHz, while ensuring sensitivity for signals without a triggerable signature.

**KEYWORDS:** Heavy-ion detectors; Large detector systems for particle and astroparticle physics

ARXIV ePRINT: 2302.01238

2024 JINST 19 P05062
# Contents

## 1 Introduction 2

1.1 Motivation 2

1.2 Experimental setup 2

1.3 Data samples 4

1.4 Outline 5

## 2 System design and common developments 5

2.1 System design 6

2.2 Common readout unit 7

2.3 The ALPIDE chip 9

2.3.1 Technology, sensing, pixels 9

2.3.2 Analog front-end and discriminator 11

2.3.3 Matrix and readout 13

2.3.4 Features for integration of ITS2 modules 14

2.3.5 Power consumption 15

2.3.6 Results from the experimental characterization in laboratory and beam tests 16

2.4 SAMPA 18

2.4.1 CSA and shaper 19

2.4.2 ADC 19

2.4.3 DSP and readout 20

2.4.4 Physical implementation and packaging 21

2.4.5 SAMPA performance and tests 22

## 3 Detector systems 23

3.1 Coordinate system 23

3.2 Inner Tracking System 23

3.2.1 Stave modules 25

3.2.2 Global support mechanics and services 30

3.2.3 Readout and powering systems 32

3.2.4 The readout system 32

3.2.5 The powering system 34

3.2.6 Component production, detector assembly, and commissioning on surface 34

3.2.7 Detector calibration 36

3.2.8 Installation and global commissioning 37

3.2.9 First results from global commissioning 37

3.3 Muon forward tracker 40

3.3.1 Detector layout 40

3.3.2 Ladder assembly and testing 41

3.3.3 Half-Disks 43

3.3.4 Cone and barrel 44
3.3.5 Services 46

3.3.6 Readout 47

3.3.7 Detector commissioning 47

3.4 Time projection chamber 48

3.4.1 Introduction 48

3.4.2 Readout chamber design 50

3.4.3 Foil production, chamber production and quality assurance 54

3.4.4 Field cage 54

3.4.5 HV system 55

3.4.6 Front-end electronics and readout 55

3.4.7 Installation 58

3.4.8 Performance 59

3.4.9 Calibration 59

3.5 Fast Interaction Trigger 62

3.5.1 FT0 62

3.5.2 FV0 63

3.5.3 FDD 64

3.5.4 Electronics and readout scheme 64

3.6 Muon system 65

3.6.1 Muon tracking 66

3.6.2 Muon identifier 70

3.7 Transition radiation detector 74

3.7.1 High-voltage distribution and common mode 74

3.7.2 Readout 76

3.7.3 Detector control 78

3.7.4 Standalone tracking 78

3.7.5 Calibration 79

3.7.6 Quality Control 79

3.8 Time-of-Flight detector 80

3.8.1 Implementation of continuous readout 80

3.8.2 The new Data Readout Module (DRM2) 81

3.8.3 Additional upgrades in low voltage and quality control systems 84

3.9 High-momentum particle identification 85

3.9.1 Introduction 85

3.9.2 Upgrading of readout firmware and trigger 85

3.9.3 New readout firmware and readout rate 86

3.9.4 Detector calibration formalism 87

3.9.5 Other subsystems 87

3.10 Electromagnetic Calorimeter 89

3.10.1 The readout system 90

3.10.2 Trigger 91

3.10.3 Spare production 91

3.10.4 Front-end electronics firmware upgrade 91
<table><tbody><tr><td>3.10.5</td><td>Data compression</td><td>92</td></tr><tr><td>3.10.6</td><td>Calibration</td><td>93</td></tr><tr><td>3.10.7</td><td>Quality Control</td><td>93</td></tr><tr><td>3.11</td><td>Photon Spectrometer</td><td>93</td></tr><tr><td>3.11.1</td><td>Detector layout</td><td>94</td></tr><tr><td>3.11.2</td><td>Readout</td><td>94</td></tr><tr><td>3.11.3</td><td>Performance</td><td>96</td></tr><tr><td>3.12</td><td>Zero-Degree Calorimeter</td><td>97</td></tr><tr><td>4</td><td>Mechanics and integration</td><td>100</td></tr><tr><td>5</td><td>Readout and data processing</td><td>102</td></tr><tr><td>5.1</td><td>Readout data flow</td><td>102</td></tr><tr><td>5.1.1</td><td>Synchronous reconstruction</td><td>104</td></tr><tr><td>5.2</td><td>First-Level Processors</td><td>106</td></tr><tr><td>5.2.1</td><td>The FLP detector readout farm</td><td>107</td></tr><tr><td>5.2.2</td><td>Data quality control</td><td>108</td></tr><tr><td>5.2.3</td><td>Services</td><td>109</td></tr><tr><td>5.2.4</td><td>Installation and commissioning</td><td>111</td></tr><tr><td>5.3</td><td>Event Processing Nodes</td><td>111</td></tr><tr><td>5.3.1</td><td>EPN farm</td><td>112</td></tr><tr><td>5.3.2</td><td>EPN installation</td><td>113</td></tr><tr><td>5.3.3</td><td>O<sup>2</sup> data distribution</td><td>113</td></tr><tr><td>5.4</td><td>Physics data processing</td><td>115</td></tr><tr><td>5.4.1</td><td>Asynchronous reconstruction</td><td>115</td></tr><tr><td>5.4.2</td><td>Simulation</td><td>116</td></tr><tr><td>5.4.3</td><td>Analysis</td><td>118</td></tr><tr><td>5.5</td><td>Central Trigger System</td><td>119</td></tr><tr><td>5.5.1</td><td>Requirements of the Central Trigger System</td><td>119</td></tr><tr><td>5.5.2</td><td>Trigger hardware and interfaces</td><td>119</td></tr><tr><td>5.5.3</td><td>Trigger protocol and data format</td><td>120</td></tr><tr><td>5.6</td><td>Detector Control System</td><td>121</td></tr><tr><td>5.6.1</td><td>DCS computing hardware upgrades</td><td>122</td></tr><tr><td>5.6.2</td><td>DCS software upgrades</td><td>123</td></tr><tr><td>5.6.3</td><td>DCS conditions data</td><td>126</td></tr><tr><td>5.6.4</td><td>DCS operator environment</td><td>128</td></tr><tr><td>6</td><td>Physics performance</td><td>129</td></tr><tr><td>7</td><td>Conclusions and outlook</td><td>133</td></tr><tr><td colspan="2">The ALICE collaboration</td><td>145</td></tr></tbody></table>
# 1 Introduction

A Large Ion Collider Experiment (ALICE) was proposed, conceived, and built to study the properties of the quark-gluon plasma (QGP) in heavy-ion collisions at the Large Hadron Collider (LHC) at CERN [1]. The design was driven by the requirement to reconstruct tracks at high multiplicity in central Pb-Pb collisions and to provide particle identification over a wide range in transverse momentum ($p_T$). In LHC Runs 1 and 2, the ALICE 1 apparatus was used to record and analyse hadronic collisions ranging from pp to Pb-Pb [2]. The measurements have provided new insights in the properties of the quark-gluon plasma as well as several other aspects of the strong interaction. A comprehensive review of this scientific output was reported in ref. [3]. During the Long Shutdown 2 (2019–2021), major upgrades have led to the new experimental setup, ALICE 2, extending the physics capabilities of the experiment for Runs 3 and 4.

## 1.1 Motivation

The main objectives of the upgrades in Long Shutdown 2 (LS2) are to significantly improve the capabilities of ALICE to probe the QGP with heavy-flavour quarks, and to enable completely new measurements of the thermal emission of dielectron pairs. In addition, the upgrades significantly improve the precision of measurements in several other areas, such as jet quenching phenomena probing the interactions of high-energy partons, the production of light nuclei, momentum correlations of hadrons to determine the interaction potentials of unstable particles, and the study of collective effects in collisions of protons with high multiplicity. To gain access to these areas of physics a two-fold approach was taken by improving the pointing resolution and increasing the readout rate capabilities of the entire system to collect larger data samples. A thinner and lighter inner tracker with the first layer closer to the interaction point improves the pointing resolution by a factor of 3 in the transverse direction and a factor 6 in the longitudinal direction. This provides more effective suppression of backgrounds in the reconstruction of decays of heavy-flavour mesons and baryons as well as in the dielectron emission measurements. The increase of the readout rate from below 1 kHz to 50 kHz for Pb-Pb collisions leads to improved statistical precision for all measurements, even in the presence of large backgrounds. The improvements in pointing resolution and readout rate will also enable the measurement of thermal dilepton production in Pb-Pb collisions, as well as a number of new measurements of heavy-flavour production, which were out of reach of the ALICE detector in Runs 1 and 2.

## 1.2 Experimental setup

The experimental setup consists of a central barrel contained in a solenoidal magnet ($B = 0.5$ T) and a forward muon system with a dipole magnet providing a total bending power of 3 T m, see figure 1. The central barrel detector system is designed for efficient tracking in the high track-density environment of heavy-ion collisions, covering transverse momenta from ~100 MeV/c to ~100 GeV/c with excellent hadron and electron identification capabilities.

Until the end of Run 2, the Inner Tracking System (ITS) which is crucial for the extrapolation of tracks to the primary vertex, consisted of two layers of Silicon Pixel Detectors (SPD), two layers of Silicon Drift Detectors (SDD), and two layers of Silicon Strip Detectors (SSD) [1]. The readout rate of the full ITS was limited to 1 kHz. The ITS was replaced with a new detector (ITS2), based on seven layers of ALPIDE monolithic active pixel sensors (MAPS), which provides better pointing
<figure><img src="image_7.png" /><figcaption>**Figure 1.** ALICE 2 detector systems (see legend and text for details).</figcaption></figure>

resolution thanks to its reduced distance to the interaction point and better position resolution. It is also able to handle the hit densities resulting from Pb-Pb collisions at 50 kHz interaction rate.

In the radial direction, the ITS is followed by the Time Projection Chamber (TPC) extending from 0.85 m to 2.5 m in radius over a length of 5 m. With the multiwire proportional chambers used in ALICE 1, the ion backflow into the drift region had to be suppressed by active gating, which in turn limited the readout rate to about 700 Hz for Pb-Pb collisions. This limitation is removed in the upgraded TPC by employing readout chambers based on Gas Electron Multiplier (GEM) foils that reduce the ion backflow and resulting space charge in the TPC to a level that can be corrected for while operating the detector with Pb-Pb interaction rates up to 50 kHz.

The Transition Radiation Detector (TRD) (extending from 2.8 m to 3.5 m in radius) provides additional space points for tracking, which are also used to determine the size of the distortions due to space charge effects in the TPC, as well as $dE/dx$ measurements for particle identification, and the detection of transition radiation for electron identification. The readout electronics were upgraded to minimise the data volume and to reduce the dead time to allow data taking at high interaction rates.

The subsequent Time-of-Flight detector (TOF) allows the identification of hadrons over a wide momentum range and electrons at low momentum. Besides consolidation work on the front-end electronics, the readout was upgraded to handle the increased interaction rates.

A large part of the acceptance in the central barrel is covered by electromagnetic calorimeters. The ElectroMagnetic Calorimeter (EMCal) is realised as Pb-scintillator sampling calorimeters with avalanche photon detector (APD) readout, whereas the PHOton Spectrometer (PHOS) uses $PbWO_4$ crystals with APD readout. All calorimeters have undergone maintenance and improvements of the readout electronics.

The High Momentum Particle Identification Detector (HMPID) is a ring-imaging Cherenkov detector that adds hadron identification capabilities at large transverse momenta over a limited acceptance. A part of the system was equipped with additional absorbers to facilitate a measurement
of the interaction cross section of light antinuclei. Also here, the readout electronics were upgraded
to improve the rate capability.

The muon detectors cover the forward pseudorapidity range $-4.0 < \eta < -2.5$ and use a system of absorbers to remove hadrons and identify muons. The background of secondary muons from pion and kaon decays in the muon system is small at high $p_T$, thanks to the so-called ‘muon plug’ absorber, which is placed at $z = 90$ cm from the interaction point. The main muon detector stations use multiwire proportional chambers (muon tracking chambers, MCH), and resistive plate chambers (muon identifier, MID), both of which were equipped with new front-end electronics. Following Run 2, and as a new addition to the muon detectors in ALICE 2, the Muon Forward Tracker (MFT) consists of tracking stations with the ALPIDE silicon pixel sensors that are installed in front of the muon plug to improve mass resolution and pointing resolution for the detection of secondary charmonia and muons from B-meson decays.

A set of forward detectors form a Fast Interaction Trigger (FIT), which is used for triggering, event selection and determination of the collision time. The FIT system consists of two arrays of fast Cherenkov radiators placed on both sides of the interaction point (FT0), complemented with 3 sets of scintillator detectors. The interaction trigger is provided by the FT0 together with a large azimuthally segmented scintillator detector placed on the opposite side of the muon detectors, which is also used to determine the reaction-plane orientation in Pb-Pb collisions. Two additional scintillator detectors, FDD, are placed on opposite sides of the interaction point at large distances to cover $4.7 < \eta < 6.3$ and $-6.9 < \eta < -4.9$ to select diffractive and ultra-peripheral collisions with rapidity gaps. The FIT detector replaces the T0, V0 and AD detectors, which had similar functionalities in ALICE 1 [1].

The Zero-Degree Calorimeters (ZDC) are installed at ≈ 100 m on either side of the interaction point to help determine the centrality and event plane orientation. The readout electronics of the ZDC were upgraded to increase the readout rate to match the rest of the system.

In addition to the interventions outlined here, significant consolidation work has been performed on several subsystems which are described in the sections on individual detector systems below.

Furthermore, the readout infrastructure was completely renewed to support the continuous readout of the core detectors. The raw data from the detectors are mostly transmitted through optical links and received by First Level Processors (FLPs), where the data are assembled to time frames for further processing. A dedicated farm of Event Processing Nodes (EPN) was installed at the experiment site for the online reconstruction of all collisions. The output of this synchronous reconstruction is stored on mass storage systems and is used for an asynchronous reconstruction stage with improved calibration. The output of the latter is then used for physics analysis. A new common software framework, O², was developed for online and offline reconstruction as well as the physics analysis.

## 1.3 Data samples

During LHC Runs 1 and 2, data were recorded with pp, p-Pb, Xe-Xe, and Pb-Pb collisions at a variety of collision energies. The collision and readout rates were tuned to limit pile-up in pp collisions and to keep the total space charge generated in the gas amplification in the TPC readout chambers to manageable levels. Typical collision rates were up to 8 kHz for Pb-Pb collisions and around 200 kHz for pp collisions. To make optimal use of the different readout rate capabilities across the detector systems, clusters of detectors were read out at different rates. The central barrel
<figure><img src="image_8.png" /><figcaption>**Figure 2.** Accumulation of integrated luminosity over time for different trigger types in pp (left) and Pb-Pb (right) collisions during LHC Run 2.</figcaption></figure>

detectors were read out at a rate of 500 Hz to 600 Hz, while the cluster with the forward muon detectors together with V0, T0 and the silicon pixel layers for event characterisation were read out at a slightly higher rate. For specific triggers, such as coincidence triggers between the forward muon detectors and the calorimeters in the central barrel, the full detector was read out. During pp and p-Pb data taking a 'fast cluster' containing all barrel detectors except the SDD was used in order to double the effective TPC readout rate. Figure 2 shows the luminosities accumulated during Run 2 with different trigger conditions.

For Runs 3 and 4, it is planned to record pp and Pb-Pb data at interaction rates of 0.5 MHz to 1 MHz and 50 kHz, respectively. This will allow us to inspect integrated luminosities of 200 pb⁻¹ and 13 nb⁻¹, respectively.

## 1.4 Outline

In this article, the upgrades made to ALICE during the LHC Long Shutdown 2 are discussed. The next section 2 presents the readout system design, the common readout unit and the integrated circuits (ASICs), that were conceived, designed and produced for the upgrades of multiple detector systems. Section 3 presents the upgrades of the individual detector systems in detail. Section 4 details the mechanical integration of the detector components within ALICE and the interfaces with the LHC. In section 5 the trigger system, the readout chain, as well as the synchronous and asynchronous processing stages are discussed. The expected performance of the upgraded detector and reconstruction is reported in section 6. Section 7 composes of a conclusion with prospects for the LHC Run 3 and a brief outlook on the future ALICE upgrade plans.

# 2 System design and common developments

A series of developments have been pursued commonly for multiple systems. Foremost, the readout chain was redesigned for all detectors (section 2.1). A common readout unit was developed for the readout of the detectors (section 2.2). The ALICE Pixel Detector (ALPIDE) chip is designed and
used for both the inner tracking system and the muon forward tracker (section 2.3). The SAMPA is
used as front-end chip for the time projection chamber and the muon systems (section 2.4).

## 2.1 System design

In nominal operating conditions (50 kHz interaction rate for Pb-Pb) each TPC drift time period of ~100 µs will contain on average 5 Pb-Pb events. It was therefore decided to use a continuous, untriggered readout strategy, combined with online data compression for the upgraded readout and data acquisition system.

In order to synchronise the continuous data stream across all readout and processing branches, the data stream is divided in so-called time frames (TF) of a nominal length of 128 LHC orbits (~11 ms). Each TF is subdivided in heartbeat frames (HBF) with a length corresponding to an orbit of ~89.4 µs. Figure 3 illustrates this structure. For commissioning and calibration runs, for which the data throughput exceeds nominal conditions, all detectors also support triggered mode, in which only data from selected interactions are retained by the readout electronics. In addition, a subset of legacy detectors has not been upgraded to continuous readout and will operate in triggered mode only. For these detectors, as well as for dedicated runs, minimum bias triggers based on the fast interaction trigger detector (FIT) and the PHOS, EMCAL and TOF are distributed. In both the continuous and triggered readout mode, the detector data are time stamped with a precision of an LHC bunch crossing of 25 ns; data belonging to a HBF are grouped together into HBF packets.

The upgraded ALICE system architecture is shown in figure 4. The Common Readout Units (CRU) are standardised PCIe FPGA-based optical I/O processor modules used by all upgraded detectors for data readout and configuration, see section 2.2. Data taking is governed by the Central Trigger System (CTS) which distributes timing and trigger signals. The CTS features a two-staged distribution system consisting of one central trigger processor (CTP) and up to 18 active distribution units, the local trigger units (LTU), one for each subdetector. The CTP-LTU and LTU-CRU connections are implemented using bidirectional TTC-PON links [4, 5]. The standard timing and trigger signal distribution path goes from the CTS via the detector-specific CRUs to the detector front-ends via bidirectional radiation tolerant GBT links [34]. Trigger signals are distributed with three different latencies referred to as LM (level -1 at 425 ns), L0 (level 0 at 1200 ns), and L1 (level 1 at 6100 ns). Detectors that require latency-critical trigger signals receive them additionally on a direct path from the CTS, which is located in the cavern, to the detector front-ends on GBT links. A second group of detectors do not support continuous readout and require a trigger signal indicating the presence of an interaction with a latency of 1.6 µs. Some detectors continue to be read out via legacy readout cards (C-RORC [6]) following a hardware trigger signal to initiate the readout. They receive the clock and trigger signals via the legacy TTC system [4, 5]. For more details on the CTS, see section 5.5.

The Online & Offline processing farm (O²) contains the first level processors (FLP) and event processing nodes (EPN). The detector front-ends send the data via GBT-based links to the CRUs and C-RORCs located in the FLPs. Depending on the detector implementation, the readout data are reformatted or compressed either in the front-ends, the CRUs, or in the FLPs. The FLPs prepare Sub-Time Frames (STF) by merging all HBFs of one TF of the connected detector. Note that for most detectors the data is distributed over several FLPs. The FLPs ship the STFs of all subdetectors via a network to the EPN farm where they are merged into TFs. In order to compress the data to
<figure><img src="image_9.png" /><figcaption>**Figure 3.** Time frame and heartbeat frame structure in continuous and triggered mode. HeartBeat (HB) triggers are issued in continuous and triggered modes to all upgraded detectors. Physics triggers can be sent to upgraded detectors in triggered mode and are sent to non-upgraded detectors in all modes. HBF and TF rates are programmable with the following nominal values; HBF: 1 every orbit, ~ 89.4 µs/ ~ 10 kHz, TF: 1 TF every 128 HBFs/ ~ 11 ms/ ~ 100 Hz.</figcaption></figure>

be stored, the O² system performs a first synchronous online reconstruction pass, converts the data into compressed time frames (CTF) and sends them to the storage system from where it is accessed asynchronously for further processing. In total, a raw data throughput of 3.4 TB/s is processed in a continuous manner by the readout system. After zero suppression and data compression in the front-ends, the CRUs, and the FLPs, a data throughput of 635 GB/s is processed by the data network and the EPN farm.

The detectors are configured via the detector control system (DCS) which is connected to the detector front-ends via the CRU. The experiment control system (ECS) governs the entire data taking process via direct network connections to the central systems (DCS, CTS, FLP, EPN).

## 2.2 Common readout unit

For all upgraded detectors the Common Readout Unit (CRU) serves as interface between detector front-end links, the O² FLP processors, the CTS and DCS. The CRUs are custom developed FPGA-based Gen 3 PCI Express plug-in cards installed in the FLPs. The card (named PCI40) was originally developed for LHCb [7] and has requirements fully compatible with ALICE. ALICE adopted the PCI40 for its CRU and joined the qualification and test effort and has developed firmware for use in the experiment.

The CRU hardware features up to 48 high-speed, bidirectional, 10 Gb/s optical links using 12-lane Minipod parallel optical transmitters (AFBR-812 and AFBR-822) and receivers from Avago/Broadcom. They are accessible from the CRU front-panel through MTP (Multi-Fiber Termination Push-on) optical ribbon cable connectors and establish the interface to the detector front-end electronics using the GBT protocol [34] implemented in the FPGA. GBT links are the result of a common development for all LHC experiments to provide a radiation tolerant transmission
<figure><img src="image_10.png" /><figcaption>Figure 4. ALICE readout and control system architecture.</figcaption></figure>

chip (GBTx, SCA) and optical transceiver set (VTTx, VTRx) to be used on the detector front-end cards communicating with the data acquisition and detector control systems via optical links. The GBTx provides a data bandwidth of 4.48 Gb/s in wide-bus mode, or 3.2 Gb/s in GBT mode depending on whether forward error correction with superior correction capability for radiation induced transmission errors is activated. The slow control adapter ASIC (SCA) is an auxiliary chip compatible with the GBTx. Connected to a GBTx it allows the control of ADCs and digital IOs. VTTx and VTRx are radiation tolerant dual optical transmitter and transceiver components compatible with the GBTx ASIC.
The number of data links used for each CRU and the use of the forward error correction are adapted to the subdetector needs. In most detector implementations, 24 data links are connected to one CRU. Table 10 in section 5.2 shows the number of CRUs, the number of readout links and the data throughput into and out of one CRU for each subdetector.

For the GBT downlink to the detector-front ends carrying the timing and trigger signals as well as the configuration data up to 320 Mb/s are available from the GBTx ASIC on a configurable number of pins. The single word transmission protocol (SWT) has been developed to provide the front-end designers with a common configuration data framework.

One of the two CRU SFP+ optical transceivers is used to connect the CRUs to the CTS system via bidirectional TTC-PON [5] links. The TTC-PON link allows the distribution of timing and trigger signals with constant latency from the CTS to the CRU over passive optical splitters with a bandwidth of up to 9.6 Gb/s. The links carry the LHC clock with a jitter below 20 ps (rms) and synchronise all 474 CRUs and the connected detectors to each other. The upstream link from all CRUs to the CTS carry detector buffer status information, see section 5.5.2.

The 16-lane (x16) PCI Express card edge connector provides the interface between the CRU and the ALICE $O^2$ FLPs, in which up to 3 CRUs are installed. The interface achieves ~90 Gb/s sustainable data throughput from the CRU to the memory of the FLP computers [8]. Depending on subdetector implementation, the CRU FPGA forwards data that has already been formatted and compressed in the detector front-end, or performs detector-specific formatting, compression and base line reconstruction. In both cases, the data stream to the FLP consists of data packets compatible with the HBF structure (see section 2.1). A central FPGA firmware framework provides the interfaces to CTS, FLP, CRU and the subdetectors. Subdetector-dependent functionality, such as link decoding, adding HBF structure, compression or data processing is added via a dedicated user logic (UL) firmware plug-in to the central FPGA firmware. A detailed description of the CRU firmware design can be found in [8].

Figure 5 shows the block diagram of the module functionality and figure 6 shows a photograph of the CRU card.

## 2.3 The ALPIDE chip

### 2.3.1 Technology, sensing, pixels

The ALPIDE chip [9] is a Monolithic Active Pixel Sensor (MAPS) [10] implemented in a 180 nm CMOS technology for imaging sensors provided by TowerJazz (Tower Semiconductor since March 2022) [11]. It was designed for the upgrade of the Inner Tracking System (ITS2) to meet the requirements summarized in table 1.

The ALPIDE chip (figure 7) measures 15 mm by 30 mm and includes a matrix of 152 × 1024 sensing pixels, each one measuring 29.24 µm × 26.88 µm ($z \times r\varphi$). Analog biasing, control, readout and interfacing functionalities are implemented in a peripheral region of 1.2 × 30 mm² (figure 9).

The ALPIDE chips are fabricated on substrates with a high-resistivity (> 1 kΩ·cm) epitaxial layer on p-type substrate. Typical values for the thickness of the epitaxial layer are in the range between 18 and 30 µm. Figure 8 illustrates that a charged particle crossing the sensor liberates charge carriers in the material. The electrons released in the epitaxial layer can diffuse laterally while they remain vertically confined by potential barriers at the interfaces with the overlying p-wells and the
<figure><img src="image_11.png" /><figcaption>**Figure 5.** Block diagram of the common readout unit (CRU): the CRU forms the interface between the first-level processors (via PCIe), the central trigger system (via TTS), and the detectors (via TTS and FE).</figcaption></figure>

<figure><img src="image_12.png" /><figcaption>**Figure 6.** Picture of a CRU; bottom left, FPGA cooling radiator, bottom right, power mezzanine; top row; 3 out of 8 Minipods installed; top left, fiber optics cable to MPO connector on front panel; bottom left, SFP transceivers.</figcaption></figure>
<figure><img src="image_13.png" /><figcaption>**Figure 7.** Photograph of the ALPIDE chip on a test carrier.</figcaption></figure>

<figure><img src="image_14.png" /><figcaption>**Figure 8.** Schematic cross-section of a pixel cell.</figcaption></figure>

underlying p-type substrate. The signal sensing elements are n-well diodes (~2 µm diameter). Their area is typically 100 times smaller than the pixel cell area. The electrons that reach the depletion volume of a diode (or carriers that are released directly inside it) induce a current signal at the input of the pixel front-end.

The manufacturing process also provides a deep p-well layer that can be used to shield the epitaxial layer from the n-wells of the pmos transistors. These would otherwise compete with the sensing diodes in collecting the electrons, strongly impairing the charge collection. This feature permits the use of full CMOS circuits, including pmos transistors, in the active area.

A reverse bias voltage can be applied to the substrate. This increases the depletion volume around the n-well collection diodes and reduces the capacitance of the input junction. All these aspects contribute to increasing the S/N ratio.

### 2.3.2 Analog front-end and discriminator

Each pixel cell contains a sensing diode, a front-end amplifier and a shaping stage, a discriminator and a digital section (see the insert in figure 9). The digital section includes a multi-event buffer with three hit storage registers and a pixel mask register.
<table><caption>**Table 1.** General requirements for the pixel sensor chip for the upgrade of the ALICE inner tracking system. In cases where the actual ALPIDE performance is significantly better than the requirements, the actual performance is indicated in parenthesis and italics. (*) Radiation load integrated over 6 years of operation.</caption><thead><tr><th>Parameter</th><th>Inner Barrel</th><th>Outer Barrel</th></tr></thead><tbody><tr><td>Chip dimensions [mm × mm]</td><td colspan="2">15 × 30</td></tr><tr><td>Silicon thickness [µm]</td><td>50</td><td>100</td></tr><tr><td>Spatial resolution [µm]</td><td>5</td><td>10 (5)</td></tr><tr><td>Detection efficiency</td><td colspan="2">&gt; 99%</td></tr><tr><td>Fake-hit probability [event<sup>-1</sup>pixel<sup>-1</sup>]</td><td colspan="2">&lt; 10<sup>-6</sup> (≈ 10<sup>-6</sup>)</td></tr><tr><td>Integration time [µs]</td><td colspan="2">&lt; 30 (10)</td></tr><tr><td>Power density [mW/cm<sup>2</sup>]</td><td>&lt; 300 (~ 35)</td><td>&lt; 100 (~ 20)</td></tr><tr><td>TID radiation hardness* [krad]</td><td>270</td><td>10</td></tr><tr><td>NIEL radiation hardness* [1 MeV n<sub>eq</sub>/cm<sup>2</sup>]</td><td>1.7 × 10<sup>12</sup></td><td>1 × 10<sup>11</sup></td></tr><tr><td>Readout rate, Pb-Pb interactions [kHz]</td><td colspan="2">100</td></tr></tbody></table>

<figure><img src="image_15.png" /><figcaption>**Figure 9.** Architecture of the ALPIDE chip.</figcaption></figure>

In every pixel, there is a pulse injection capacitor for injection of test charge into the input of the front-end. A digital-only pulsing mode is also available, directly forcing the setting of the in-pixel memory cells, substituting the latching of a discriminated pulse. The analog and digital pulsing patterns are fully programmable. These features are used routinely for testing and calibration.

The front-end and the discriminator are continuously active. They feature a non-linear response and their transistors are biased in weak inversion. The total power consumption of the pixel cell is 40 nW. The small signal gain of the front-end is 4 mV/e, the equivalent noise charge is 3.9 e, while the minimum threshold is below 100 e. The typical value of the capacitance of the sensing diode is 2.5 fF. The input capacitance of the front-end is below 2 fF. The output of the front-end has a peaking time of the order of 2 µs, while the discriminated pulse has a typical duration of 5 µs to 6 µs.
The front-end and the discriminator act as an analogue delay line. This allows operating the chip in triggered mode when, as it happens in ALICE, the latency of the incoming trigger is comparable with the peaking time of the front-end. A common threshold level is applied to all the pixels.

The latching of the discriminated hits in the storage registers is controlled by global STROBE signals. A pixel hit is stored into one of three in-pixel latch cells if a STROBE pulse is applied to the pixel while the output of the front-end is above threshold. The generation of the internal STROBE signals can be either triggered by an external command or optionally initiated by an internal sequencer. The duration of the STROBE pulses is programmable. Two major operating modes are supported. In triggered mode the STROBE and the frame readout are triggered externally from an event synchronous command. In continuous mode the strobe is asserted periodically and for a duration almost equal to the period. The event frames are continuously integrated and read out.

### 2.3.3 Matrix and readout

The readout of the frame data from the matrix is zero-suppressed and is executed by an array of circuits named *priority encoders* (figure 9). The priority encoder provides to the periphery the address of the first pixel with a hit in its double column, selecting it according to a hardwired topological priority.

During one hit transfer cycle a pixel with a hit is selected, its address is encoded and transferred to the periphery and finally the in-pixel memory element is reset. The address of the next pixel with a hit in the double column is then calculated. This cycle is repeated until the addresses of all pixels initially presenting a valid hit at the inputs of a priority encoder have been transferred to the periphery and all the hit storage registers in the double column have been reset.

Each priority encoder is a fully combinatorial circuit and it is steered by sequential logic in the periphery during the readout of a matrix frame. It is implemented in a very narrow region between the pixels, extending vertically over the full height of the columns. There is no free running clock distributed in the matrix and there is no signaling activity if there are no hits to read out. The average energy needed to encode the address of a hit pixel is of the order of 100 pJ. Power is consumed proportionally to the readout rate and to the average hit occupancy of the frames. The readout of the matrix consumes around 3 mW under normal conditions. The priority encoders also implement the buffering and distribution of readout and configuration signals to the pixels.

The 512 double columns and the corresponding priority encoders are functionally grouped in 32 regions (512 × 32 pixels), each of them with 16 double columns being read out by 16 priority encoder circuits (figure 10). There are 32 corresponding region readout units in the chip periphery, each one executing the readout of a region. They steer the priority encoders, latch the encoded pixel hit address, perform additional data reduction and formatting and buffer the hit data into memories. The 16 double columns inside each region are read out sequentially, while the 32 regions are read out in parallel. The data from the 32 region readout units are assembled and formatted by a top readout unit module.

Data can be transmitted on two different readout ports. The largest capacity data readout interface is a 1.2 Gb/s serial data port with differential signaling. The serial transmission is 8b/10b encoded, therefore the maximum data throughput is 960 Mb/s. The serial port can optionally operate at reduced line rates (600 Mb/s or 400 Mb/s). A bidirectional parallel data port with single-ended signaling is also available, with a capacity of 320 Mb/s. This port enables the implementation of
<figure><img src="image_16.png" /><figcaption>Figure 10. Block diagram of the ALPIDE chip.</figcaption></figure>

an inter-chip data transfer and relaying protocol designed to integrate multi-chip modules without additional external devices. This is used in the modules of the ITS2 outer barrel.

The ALPIDE chip has custom control interfaces. There are a differential control port supporting bidirectional (half duplex) serial signaling at 40 Mb/s on differential links and a second single ended control port. The two control interfaces and the dedicated internal logic allow interconnecting multiple chips on a module and control them via the differential interface of only one of the chips acting as hub of the control bus. The control bus is also used to distribute broadcast commands and synchronization messages to the chips, most notably the trigger commands.

The periphery of the chip contains fourteen 8-bit analog DACs for the biasing of the pixel front-ends. The analog section of the periphery also contains a band-gap reference and a temperature sensing circuit. An ADC with 11 bit resolution is available for monitoring and testing purposes, and can probe the outputs of the DACs, the analog as well as digital supply voltages, the band-gap voltage and the temperature sensor.

### 2.3.4 Features for integration of ITS2 modules

The ALPIDE chip has specific design features to enable the integration of multi-chip detector modules, to minimise the electrical wiring between modules and off-detector electronics and to provide common interfaces across the ITS2 staves. Two different hybrid modules built with ALPIDE sensors are used in the upgraded ALICE ITS2 (figure 11): one in the three innermost layers constituting the inner barrel and the other in the staves of the remaining layers of the outer barrel (see also section 3.2.1).

The ITS2 inner barrel module includes nine ALPIDE chips. They share a common differential control and clock distribution buses. Each chip transmits its own data off-detector at maximum line rate (1.2 Gb/s) on point-to-point high speed serial links.
<figure><img src="image_17.png" /></figure>

<figure><img src="image_18.png" /><figcaption>**Figure 11.** Diagrams of the ITS2 inner barrel and outer barrel modules.</figcaption></figure>

The ITS2 outer barrel module contains fourteen chips, arranged in two subgroups of seven. One chip in each group, called *master*, acts as control hub and data relaying chip. Only the master chips communicate with the external electronics through differential clock and control buses shared between multiple modules and through point-to-point differential wire-line links for the transmission of data.

Each of the master chips connects to six neighbouring chips, forwards them to the main clock and bridges the control transactions on electrical interconnects that are local to the modules.

The chips neighbouring the master use a shared parallel local bus to transfer their data to the master. The master chip relays the data from the slave chips on the serial output port driving the point-to-point links. In this configuration the master chips transmit data on the serial data port using a lower bit rate (400 Mb/s).

Grouping of data from neighbouring chips and transmitting at lower rate are possible in the ITS2 outer barrel layers given the lower occupancy. In addition to reducing the total number of copper links, this scheme achieves a significant reduction of the power consumption given that only one out of seven line drivers is maintained active.

Differential copper wire lines directly connect the ALPIDE chips to the off-detector electronics. These links reach a length of 8 m. The electrical receivers and transmitters on the ALPIDE chips were designed and tailored to the electrical and protocol levels to operate with these long interconnects.

### 2.3.5 Power consumption

The ALPIDE sensor chip has three power supplies: one analog domain, one digital domain and a power supply dedicated to the Phase-Locked Loop (PLL) of the high speed serial data transmitter. The power consumption of the analog section, dominated by the analog front-ends, is typically 24 mW. The digital power consumption includes the pixel digital sections, readout modules, peripheral circuits, and I/Os. It depends strongly on the configuration and operating conditions. In the nominal conditions of the ALICE ITS2, it is about 130 mW.
The output serial links are driven by a data transmission unit including a PLL, a fast serialize and a line driver stage with a typical power consumption of about 52 mW. The data transmission unit is enabled in all the chips of the ITS2 inner barrel. In the outer barrel modules it is active only in the master chips and disabled in the remaining chips, that is only 1 out of 7 sensors consumes this extra power.

The power dissipation density is about 47 mW/cm² in the ITS2 inner barrel modules and around 35 mW/cm² in the outer barrel modules.

The readout of the matrix and the digital periphery consume power in proportion to the clocking frequency, the readout rate and the pixel occupancy. In less demanding applications not requiring the high speed links and the full rate capabilities, the power consumption can be reduced considerably with various techniques including slowing down or suspending the primary clock and using the single ended I/Os to read out data at low rates.

### 2.3.6 Results from the experimental characterization in laboratory and beam tests

The ALPIDE chip and its prototype predecessors have been characterised with an extensive test program including laboratory tests and a series of beam tests. A summary of key results is given in this section. The full set of results and details on the methodologies will be presented in a separate paper.

The laboratory measurements were based on the sensible usage of the built-in test pulse charge injection circuitry and on the systematic analysis of threshold scans and noise measurements. These allowed thorough characterisation of the distributions of pixel thresholds, the fractions of pixels requiring masking, and the residual fake-hit rate after masking. Their dependencies on operating conditions were accurately established.

A set of ALPIDE prototype sensors were characterised in beam tests to quantify detection performance and hit-position resolution. The samples under test were located at the center of beam telescopes acting as precision trackers. The telescopes were themselves constructed with ALPIDE sensors and had six detection planes: three upstream and three downstream of the Device Under Test (DUT). The measurements were based on reconstructing particle tracks in the telescope and projecting them onto the DUT plane. The presence of a matching cluster, its size in pixels and its centroid were the basis for measuring the detection efficiency and the hit-position resolution.

Figure 12 provides a summary of the beam test results on the detection efficiency and the fake-hit rate as a function of the global threshold setting. Data of eight different samples are shown, including two non-irradiated DUTs and pairs of devices exposed to increasing doses of ionising radiation before the tests. The samples exposed to the TID level of 200 krad (75% of the lifetime dose) received also a combined Non-Ionising Energy Loss (NIEL) fluence at a level corresponding to 1.3 times the fluence expected over the total lifetime. The Total Ionising Dose (TID) level of 500 krad (190% of the lifetime dose) includes a combined fluence that is 3.2 times the lifetime fluence. Two devices were also irradiated with neutrons for a cumulated non-ionizing energy loss of $1.7 \times 10^{13}$ [1 MeV $n_{eq}/cm^2$], corresponding to ten times the fluence expected over the full detector lifetime.

The results show a large operating margin for the threshold setting between 50 and 250 electrons, providing a detection efficiency above 99% and a fake-hit rate that is several orders of magnitude smaller than the required value of $10^{-6}$ fake-hit probability per pixel per frame. The ALPIDE sensor proved to be extremely well performing in terms of noise. Masking the ten most noisy pixels out of the 524288 in the matrix (less than 0.002%) resulted in a residual fake-hit noise level below the sensitivity of these experiments ($2 \times 10^{-11}$).
<figure><img src="image_19.png" /><figcaption>**Figure 12.** ALPIDE sensor chip detection efficiency and fake-hit rate vs global threshold setting. Beam test results (6 GeV/c pions, orthogonal incidence). ALPIDE substrate reverse bias: -3 V.</figcaption></figure>

<figure><img src="image_20.png" /><figcaption>**Figure 13.** ALPIDE chip hit-position resolution and average cluster size as a function of global threshold setting. Beam test results with 6 GeV/c pions with perpendicular incidence. ALPIDE substrate reverse bias: -3 V.</figcaption></figure>

Figure 13 shows the beam test results on the hit-position resolution (black markers and lines, upper band) and the average cluster size (red markers and lines, lower band) as a function of the global threshold. The data sets refer to the same samples of figure 12. The hit-position resolution is better than 6 µm for thresholds below 300 electrons and better than 5 µm for a threshold below 140 electrons. As expected the average cluster size depends on the threshold setting, due to the cutting on shared charge diffusing into pixels adjacent to the seed pixel. It ranged between 1.5 and 2.5 pixel hits in the range of interest.

The tests also showed that the chip-to-chip performance variations were negligible, that the chips with combined TID and NIEL irradiation performed similarly to the non-irradiated chips and that sufficient operational margin was present also in the samples with a NIEL dose ten times larger than the one expected over the lifetime.
<table><caption>**Table 2.** SAMPA key parameters.</caption><thead><tr><td>Parameter</td><td>MCH</td><td>TPC</td></tr></thead><tbody><tr><td>Input polarity</td><td>pos</td><td>neg</td></tr><tr><td>Input charge linear range</td><td>500 fC</td><td>100 fC and 67 fC</td></tr><tr><td>Sensor capacitance</td><td>40-80 pF</td><td>12-25 pF</td></tr><tr><td>Gain</td><td>4 mV/fC</td><td>20 mV/fC and 30 mV/fC</td></tr><tr><td>Gain channel-to-channel variation</td><td>1.5 %</td><td>1.5 %</td></tr><tr><td>Gain linearity</td><td>0.5 % up to 85 % of range</td><td>0.5 % up to 85 % of range</td></tr><tr><td>Channel-to-channel cross talk</td><td>&lt; 0.3 %</td><td>&lt; 0.2 %</td></tr><tr><td>Noise</td><td>2000 e<sup>-</sup> @ 60 pF</td><td>600 e<sup>-</sup> @ 12 pF</td></tr><tr><td>Peaking time</td><td>330 ns</td><td>170 ns</td></tr><tr><td>Baseline return</td><td>&lt; 550 ns</td><td>&lt; 500 ns</td></tr><tr><td>ADC sampling rate max. 20 MSa/s</td><td>10 MSa/s</td><td>5 MSa/s</td></tr><tr><td>ADC ENOB</td><td>&gt; 9.2</td><td>&gt; 9.2</td></tr><tr><td>ADC INL</td><td>&lt; 1 LSB (abs.)</td><td>&lt; 1 LSB (abs.)</td></tr></tbody></table>

## 2.4 SAMPA

The SAMPA [12] is a 32-channel custom front-end ASIC for the readout of gaseous detectors and specifically for the ALICE Muon Chambers (MCH, section 3.6.1) and Time Projection Chamber (TPC, section 3.4). Each of the 32 channels contains a Charge Sensitive Amplifier (CSA) and a 10-bit 20 MSample/s ADC. The digitised data of all 32 channels is made available on serial links as either a raw data stream or preprocessed by an internal Digital Signal Processor (DSP), supporting both the continuous and triggered readout of the upgraded ALICE system. The SLVS serial output links support 320 Mb/s and are compatible with the input links (e-links) on the serial transceiver ASIC (GBTx) of the GBT-links used in ALICE for data transmission between the detectors and the CRUs. Depending on the data transfer rate needed in the application, the SAMPA data can be routed via a programmable number of up to 11 serial links.

The block diagram of the SAMPA ASIC is shown in figure 14. The front-end is composed of a cascade connection of a CSA (Charge Sensitive Amplifier), a differential semi-Gaussian pulse shaper and an Analog-to-Digital Converter (ADC). The CSA and the pulse shaper convert signals into a semi-Gaussian pulse with an amplitude proportional to the total charge injected on the input. SAMPA was designed and fabricated in 130 nm CMOS technology and it operates at a nominal supply voltage of 1.25 V. In order to adapt the SAMPA to its two applications in the MCH and TPC, the sensitivity, polarity and peaking time of the front-end can be adjusted via external pins. SAMPA supports positive and negative polarity of the input charge and has three different gain modes with different sensitivity and peaking time: 20 mV/fC@160 ns, 30 mV/fC@160 ns for the TPC and 4 mV/fC@300 ns for the MCH. Table 2 summarizes the main characteristics and performance of the SAMPA.

Analog front-end reference voltages (nominal values 450 mV, 600 mV, and 750 mV) are generated internally with temperature compensation and can be adjusted via configuration registers. The ADC requires an external voltage reference of 1.1 V. The DSP eliminates signal perturbations, distortion of the pulse shape, offsets, and signal variations due to changes in the environment. An I2C interface allows setting control registers.
<figure><img src="image_21.png" /><figcaption>Figure 14. Block diagram of the SAMPA ASIC.</figcaption></figure>

### 2.4.1 CSA and shaper

The SAMPA front-end is composed of a positive/negative polarity CSA with a capacitive feedback $C_f$ and a resistive feedback $R_f$ connected in parallel, converting the input charge signal ($Q$) into a voltage step signal proportional to $Q/C_f$. The discharge resistor ($R_f$) provides baseline restoration and reduces pile-up effects in the CSA (figure 15). A pole-zero cancellation resistor ($R_{pz}$) eliminates the undershoot generated by the long time constant of the output step signal of the CSA. The step signal is fed to a band-pass filter constituted by a first order high-pass filter $C_{dif}R_{dif}$ (differentiator) and a two bridged-T second order low-pass filters (integrator). After that, a non-inverting stage (NIS) generates a semi-Gaussian output pulse with an amplitude proportional to the input charge. The amplifier of the first shaper is a scaled-down version of the CSA amplifier. In order to provide the second shaper with a differential mode input, a copy of the first shaper is included. This copy is connected in unity gain configuration to minimize its noise contribution. The second shaper consists of a fully differential amplifier with a Miller configuration and a common-mode feedback network. It has the same functionality as the first shaper and implements two other poles and a zero creating a CR-(RC)⁴ semi-Gaussian shaper together with the differentiator and the first shaper stage.

The gain of the front-end is controlled by $R_G$, which is an array of parallel resistances that are switched by configuration registers. The peaking time of the semi-Gaussian shaper is adjusted for each operation mode (160 ns and 300 ns) by external configuration control of an array of parallel capacitors. These front-end configurations are performed with transmission gates used as low resistance switches.

### 2.4.2 ADC

The 32-channel 10-bit SAMPA ADC features a sampling frequency of up to 20 MSa/s defined by an external clock. The MCH and the TPC use the SAMPA with 10 MHz and 5 MHz sampling clock, respectively.

The SAMPA ADC is based on the successive-approximation register (SAR) architecture [13]. It is shown in figure 16. A differential capacitive DAC is implemented with the split capacitor topology.
<figure><img src="image_22.png" /><figcaption>**Figure 15.** Block diagram of the front-end implemented in the SAMPA ASIC.</figcaption></figure>

<figure><img src="image_23.png" /><figcaption>**Figure 16.** Block diagram of the SAMPA SAR ADC.</figcaption></figure>

Top-plate sampling with MSB (Most Significant Bit) preset to achieve full-range sampling is used. A switching strategy with low energy dissipation per cycle is used.

### 2.4.3 DSP and readout

**Direct ADC Serialization.** In the Direct ADC Serialization (DAS) mode, the SAMPA sends out the unmodified raw data stream from all 32 ADC channels via 11 serial links, bypassing the readout processor and DSP. In this mode, most of the digital circuitry is powered down via clock gating, keeping active only the communication links. 10 SLVS links are used to send the 10-bit data samples of each ADC channel. The 11th link is used to provide a synchronisation clock. Optionally, a split mode can be activated, such that data from ADC channels zero to 15 (16 to 31) are transmitted on serial links zero to four (five to nine). This allows connection of an odd number of SAMPAs to an even number of serial transmitters, as in the case of the TPC readout, where five SAMPAs are connected to two GBTx transmitter chips.

**DSP.** The SAMPA DSP (figure 17) implements fully parallel data processing on the 32 channels and supports both continuous and triggered readout operation. When in DSP mode, the data coming
from the ADC are received via the pre-trigger buffer with programmable depth of up to 192 10-bit words per channel. In triggered operation, the pre-trigger buffer delays the data and allows the collection of the detector signal samples before the arrival of the trigger signal.

<figure><img src="image_24.png" /><figcaption>**Figure 17.** Diagram of digital signal processing chain in the SAMPA.</figcaption></figure>

The pre-trigger buffer is followed by a section of several configurable pipelined digital filters for signal conditioning. The filter blocks are:

* The **baseline correction 1** subtracts a given pedestal value for a fixed time after a trigger and applies a configurable Infinite Impulse Response (IIR) filter to correct slow fluctuations of the baseline.

* The **tail cancellation** corrects long tails via a Digital Shaper, using a cascade of four fully configurable first order IIR filters which also can be used as general low-pass or band-pass filter.

* The **baseline correction 2 and 3** offer a moving average Finite Impulse Response (FIR) filter and a non-linear slope-based filter.

The SAMPA is equipped with 3.2 Gb/s output data bandwidth to extract the full raw data stream for up to 10 MSa/s. This feature is used in the TPC application. For the MCH application, data preprocessing in the SAMPA is used by applying a zero-suppression algorithm, removing all data below a threshold configurable for each channel. In addition, a cluster sum algorithm is available, where instead of delivering time and amplitude of each sample above threshold, consecutive active samples are added up to clusters in time and only the sum of the values and the time of arrival are delivered. The data are formatted for transmission in either continuous or triggered mode. A hamming code protected output buffer handles data size fluctuations and distributes the data to the activated serial links.

### 2.4.4 Physical implementation and packaging

The SAMPA ASIC die is 8.9 mm wide and 9.5 mm long with 350 flip chip bond pads. As visible in the left panel of figure 18, only a minor part of the die is devoted to the analog circuits (left
on the picture), while the largest fraction contains the digital blocks, with part of the area being
occupied by the buffer memories. During the implementation, special care was taken to isolate
the power domains of the different circuits. There are five different power domains: CSA, Shaper
and Output Buffer, ADC, core digital logic and SLVS IO drivers. The SAMPA features a 372 ball
15 mm × 15 mm, 1.2 mm thick, Thin Fine-pitch Ball Grid Array (TFBGA) package with 0.65 mm
ball pitch in order to be compatible with the MCH integration requirements. The high number of
available balls allowed multiple connections to VDD and GND pads, reducing the inductive and
resistive loss. The package includes filtering capacitors for ADC power connections and for on-chip
ADC reference voltages. A QR-code on the SAMPA package (right panel in figure 18) encodes the
wafer lot-ID and a unique chip serial number, allowing the identification and tracking of each ASIC.

<figure><img src="image_25.png" /><figcaption>Figure 18. SAMPA bare die (left) and TFBGA packaged chip (right).</figcaption></figure>

**2.4.5 SAMPA performance and tests**

The main specifications and performance of the SAMPA are listed in table 2 above. Figure 19 shows
the response curve for the 4 mV/fC gain setting.

Robustness measurements of the CSA against saturation in case of multiple consecutive signals
were performed, showing that an average current of at least 30 nA can be sustained for 60 µs without
significant baseline shift, indicating that the SAMPA can stand this charge rate indefinitely.

The SAMPA functionality was verified successfully against the highest expected radiation load of 2.1 krad. Robustness of the SAMPA against single event upsets and single event latchups for an expected maximum flux of high-energy hadrons of 3.4 kHz/cm² has been verified. An upper limit for the SEL cross section of 10⁻⁷ cm² for ions with a linear energy transfer of 16 MeV cm² mg⁻¹ has been measured.

80000 SAMPAs have been tested using a robotic test system to verify the functionality of the
digital blocks and that the output baseline, noise, gain and peaking time are in a narrow intervals
around the nominal values. The SAMPA mass production yield was 79.6 %. A breakdown of the
rate of different kinds of failures can be found in table 14 of [14].
<figure><img src="image_26.png" /><figcaption>Figure 19. Example response curve for 4 mV/fC configuration.</figcaption></figure>

# 3 Detector systems

In the following subsections, each of the ALICE detector systems is presented, with emphasis on the upgrades that were installed during LHC Long Shutdown 2. Each system is presented in a separate subsection, starting from the inner tracking system, the muon forward tracker and the time projection chambers, which have undergone the most significant changes.

## 3.1 Coordinate system

The gloabel reference coordinate system used in ALICE is a right handed system with the z axis point along the beam line, in the direction away from the muon arm, the y-axis pointing vertically up, and the x axis pointing horizontally towards the center of the LHC. The nominal interaction point is the origin of the coordinate system. The two sides of the detector along the beam axis are referred to as the C side, where the muon arm is positioned, and the A side, where FV0 is positioned.

## 3.2 Inner Tracking System

The new Inner Tracking System (ITS2) [15] uses the ALPIDE sensor (described in section 2.3) and represents the largest-scale application of Monolithic Active Pixel Sensors (MAPS) in a high-energy physics experiment. The main goal of the ITS upgrade is to improve the precision of the reconstruction of the primary vertex as well as of decay vertices originating from heavy-flavour hadrons, and the performance in the detection of low-$p_T$ particles. Additionally, readout rates of 50 kHz in Pb-Pb and 400 kHz in pp collisions are required. In order to achieve this performance, the following key improvements were made in comparison with the previous ITS:
* Granularity increased for all layers with pixel sensors with a cell size of 29.24 µm × 26.88 µm. The number of layers for the inner barrel was increased from two to three, raising the total number of layers from six to seven.

* New beam pipe with a central beryllium section with an outer radius reduced from 28 mm to 18 mm (see section 4).

* Innermost detector layer moved closer to the interaction point, from 39 mm to 22.4 mm.

* Material budget reduced to 0.36% $X_0$ per layer for the innermost layers and limited to 1.10% $X_0$ per layer for the outer layers.

Table 3 reports a list of main parameters of the old ITS1, used in Runs 1 and 2, and of the new ITS2. The new design improves the tracking efficiency and momentum resolution at low $p_T$ as well as the impact-parameter resolution by a factor of three and five in the $r\phi$- and z-coordinate, respectively, at a $p_T$ of 500 MeV/c [1].

<table><caption>**Table 3.** Comparison of main detector parameters of the previous ITS1 and the new ITS2.</caption><thead><tr><th></th><th>ITS1</th><th>ITS2</th></tr></thead><tbody><tr><td>Technology</td><td>Hybrid pixel, strip, drift</td><td>MAPS</td></tr><tr><td>No. of layers</td><td>6</td><td>7</td></tr><tr><td>Radius</td><td>39–430 mm</td><td>22–395 mm</td></tr><tr><td>Rapidity coverage</td><td>| η | ≤ 0.9</td><td>| η | ≤ 1.3</td></tr><tr><td>Material budget / layer</td><td>1.14% X<sub>0</sub></td><td>inner barrel: 0.36% X<sub>0</sub><br>outer barrel: 1.10% X<sub>0</sub></td></tr><tr><td>Pixel size</td><td>425 µm × 50 µm</td><td>27 µm × 29 µm</td></tr><tr><td>Spatial resolution (rφ × z)</td><td>12 µm × 100 µm</td><td>5 µm × 5 µm</td></tr><tr><td>Readout</td><td>Analogue (drift, strip), Digital (Pixel)</td><td>Digital</td></tr><tr><td>Max rate (Pb-Pb)</td><td>1 kHz</td><td>50 kHz</td></tr></tbody></table>

An overview of the ITS2 structure is shown in figure 20. The detector is grouped into the inner barrel (IB) consisting of the three innermost layers, and the outer barrel (OB) arranged in two double layers. The radial position of each layer (listed in table 4) was optimized to achieve the best performance in terms of pointing resolution, $p_T$ resolution, and tracking efficiency in the high track-density environment of Pb–Pb collisions. The pseudorapidity coverage of the detector is $|η| < 1.22$ for the most luminous 90% of the interaction region, i.e. for interaction vertices located in the range of approximately ±10 cm around the nominal interaction point along the beam axis, see also figure 34. The total surface area of the sensors is ~10 m² instrumented with about 12.5 billion pixels with binary readout. The detector is operated at room temperature (20°C to 25°C), which is stabilized by water cooling. The radiation load at the innermost layer is expected to be 270 krad of Total Ionising Dose (TID) and 1.7 10¹² 1 MeV $n_{eq}$/cm² of Non-Ionising Energy Loss (NIEL), for 10 years of ALICE running, met by the ALPIDE sensors (see section 2.3). In order to meet the material budget requirements, the silicon sensors are thinned down to 50 µm and 100 µm in the inner and outer barrel, respectively.
<figure><img src="image_27.png" /><figcaption>**Figure 20.** Schematic layout of the ITS2. The three innermost layers form the inner barrel, the middle and outer layers form the outer barrel.</figcaption></figure>

<table><caption>**Table 4.** Main layout parameters of the new ITS2.</caption><thead><tr><th>Layer no.</th><th>Average radius (mm)</th><th>Stave length (mm)</th><th>No. of staves</th><th>No. of HICs/ stave</th><th>Total no. of chips</th></tr></thead><tbody><tr><td>0</td><td>23</td><td>271</td><td>12</td><td>1</td><td>108</td></tr><tr><td>1</td><td>31</td><td>271</td><td>16</td><td>1</td><td>144</td></tr><tr><td>2</td><td>39</td><td>271</td><td>20</td><td>1</td><td>180</td></tr><tr><td>3</td><td>196</td><td>844</td><td>24</td><td>8</td><td>2688</td></tr><tr><td>4</td><td>245</td><td>844</td><td>30</td><td>8</td><td>3360</td></tr><tr><td>5</td><td>344</td><td>1478</td><td>42</td><td>14</td><td>8232</td></tr><tr><td>6</td><td>393</td><td>1478</td><td>48</td><td>14</td><td>9408</td></tr></tbody></table>

### 3.2.1 Stave modules

The basic detector unit, called stave, consists of the following elements (figure 21):

* **Hybrid Integrated Circuit (HIC):** an assembly of a polyimide Flexible Printed Circuit (FPC) on which a number of pixel chips, namely 9 and 14 for the inner and outer barrel staves, respectively, and some passive components, are bonded. Figures 22 and 23 show photos of an inner and outer barrel HIC.

* **Coldplate:** a carbon fibre sheet with high thermal conductivity with embedded polyimide cooling pipes, which is either integrated within the space frame (for the inner barrel staves) or attached to the space frame (for the outer barrel staves).

* **Space Frame:** a carbon fiber truss-like support structure providing the mechanical support and the necessary stiffness to the assembly of HICs on cold plates.
<figure><img src="image_28.png" /><figcaption>**Figure 21.** Layout of the staves of the inner and outer barrels.</figcaption></figure>

The HICs are glued to the cold plate: 1 HIC for the inner barrel and 8 and 14 HICs, for the middle and outer layers, respectively. The cold plate is in thermal contact with the pixel chips to remove the generated heat. For the inner barrel, each stave consists of a single HIC+cold plate assembly. In the outer barrel, staves are further segmented in azimuth in two half-staves. Each half-stave extends over the full length of the stave and consists of a cold plate on which four or seven modules (HICs) are glued depending on the length of the stave.

**Hybrid Integrated Circuit.** As shown in figure 21, the inner barrel HIC includes one row of 9 sensors, whereas the outer barrel HIC comprises two rows of 7 sensors each, as visible in figure 23, bottom. The HICs consist of an assembly of ALPIDE chips glued to an FPC, which provides the connection to analogue and digital power rails as well as p-well and substrate bias voltages. Differential pairs of traces of 100 µm width and spacing are used to distribute control and clock signals in a local bus and to read out individual pixel sensors. In the inner-barrel staves, all 9 sensors share the same aluminium power bus on the FPC, while in the outer-barrel staves, a dedicated aluminium power bus extends over all FPCs of the half-stave and provides analogue and digital power as well as ground connections. The baseline powering scheme is based on a conservative parallel connection: all chips in a HIC are directly connected to the analogue and digital power planes of the FPC, which are in turn fed by the power bus serving the half-stave. The electrical connection to the HICs is made by means of thin aluminium cables soldered onto the HIC, as visible in figure 23. To minimise the material budget, aluminium was chosen as conductor (having a radiation length of 8.9 cm compared to 1.44 cm for copper) for the FPCs of the inner barrel. Since the resistivity of aluminium is 1.5 times larger than that of copper, the thickness of the power lines must be correspondingly increased. A thickness of 25 µm ensures a voltage drop below 50 mV over the full length, as well as an attenuation suitable for signal transmission up to 1.2 Gbps. Polyimide
<figure><img src="image_29.png" /><figcaption>**Figure 22.** Inner HIC seen from the sensor side. The green tabs are used for fixing and handling, and are removed before mounting the HIC.</figcaption></figure>

Upilex-S75 was selected as substrate because it has a small thermal expansion coefficient (0.01% at 200°C) and therefore provides good dimensional stability during the aluminium coating by sputtering in vacuum. The material budget requirements for the outer barrel FPC are less severe and allow for a more standard production procedure, using copper-clad Pyralux, with a substrate of 75 µm and 18 µm metal layer. With the external power bus, the thinner copper traces are compatible with voltage drop requirements and the readout rate of 400 Mbps, sufficient for the lower occupancy of the outer layers. The power bus in the outer barrel is connected to the HICs via short

The main requirements for the chip to FPC interconnection are: (i) compact module layout with minimal dead area; (ii) highly reliable and stable mechanical connection; (iii) high quality, low inductance electrical connection. A custom made automatic Module Assembly Machine (MAM), named ALICIA, supplied by IBS-Precision Engineering, see top left panel of figure 24, implements electrical testing, dimension measurement, integrity inspection and alignment for assembly, was used to achieve a reproducible accuracy and the required production speed at the various HIC assembly sites.

Using a stencil manufactured in an adhesive film (90 µm thick), very precise spots of Araldite 2011 (0.6 mm diameter, 160 per chip) were applied on the FPC clamped on a gripper jig. After the chips were aligned by the MAM onto the vacuum chuck with a position accuracy of better than 5 µm and a spacing of 150 µm, the FPC was positioned precisely on top. Shims of 50 µm were used to ensure a sufficient gap for the glue and variations related to tolerances of tooling (planarity: ±10 µm) and components (FPC thickness: ±10 µm; chip thickness: ±5 µm). The assembly procedure was validated by mechanical tests where on average a pull strength of 44 N/chip and a peel strength of 3 N were measured. The electrical interconnection used a novel approach of wire bonding through the FPC vias (figure 24 bottom left panel). In order to account for the clearance necessary for the
<figure><img src="image_30.png" /><figcaption>**Figure 23.** Top view and bottom view of an outer barrel HIC. The yellow cables connect the HIC to the power bus.</figcaption></figure>

wedge bonding tool, the FPC vias have an oblong shape (1.2 mm × 0.4 mm); in addition 300 µm interconnection pads were implemented on the top surface. Wire bonding was performed using 25 µm aluminium wire (three wires per connection); a typical pull force of 11 cN with a standard deviation of 0.8 cN was measured per wire.

**Space frame and cold plate.** The layout of the ITS2 stave mechanics and cooling consists of a space frame and one or two cold plates. A large effort was devoted to the design of the lightest possible mechanical supports to maintain the silicon sensors in an accurate position while providing the cooling to remove the heat dissipated by the sensors. A novel technology was developed to directly embed polyimide pipes inside the cold plate, an assembly of highly thermally conductive carbon fibre laminate (see figure 25).

For mechanical stability, the cold plate is stiffened by the space frame, a light filament-wound carbon structure with a triangular cross section. The implementations of the cold plate and space frame differ in the inner and outer barrel to satisfy different geometrical and thermal constraints (figure 25). In order to guarantee electrical insulation, a Parylene coating was applied on the cold plates (Parylene volume resistivity is $1.4 \times 10^{17} \Omega$ cm, measured on a 25 µm thick layer). Such a
<figure><img src="image_31.png" /></figure>

<figure><img src="image_32.png" /><figcaption>**Figure 24.** Pictures of the ITS2 assembly. Top left: a view of the MAM used for chip inspection and HIC assembly. Top right: photo of an outer barrel stave, with power bus cables opened on the two sides. Bottom: photo of an inner barrel stave, with detailed views shown in the insert.</figcaption></figure>
<figure><img src="image_33.png" /><figcaption>**Figure 25.** Space frame and cold plate cooling scheme. (Left) Inner Barrel; (Right) Outer Barrel.</figcaption></figure>

structure provides a highly efficient heat dissipation with single-phase liquid flow up to a power density of 0.5 W/cm² produced by the silicon chips glued on top of it. As can be seen in figure 26, this solution meets the quite stringent requirement of a very low material budget, in particular for the inner barrel stave (0.36% X₀/layer). The same solution for the integration of the cooling pipes was adopted for the outer barrel staves. The material budget requirements for the much larger outer barrel layers are less stringent and the different layout corresponds to an average budget of 1.10% X₀/layer (figure 26).

<figure><img src="image_34.png" /><figcaption>**Figure 26.** Azimuthal distribution of single contributions to the material budget of an inner (left) and outer (right) barrel stave layer. The relative contribution of each component to the total material budget is quoted.</figcaption></figure>

### 3.2.2 Global support mechanics and services

In addition to the requirements of minimising the material in the sensitive region and ensuring high accuracy of the relative position of the detector sensors, discussed in the previous section, the ITS2 mechanical structure fulfils the following design criteria:

* provide an accurate position of the detector with respect to the TPC and the beam pipe;

* locate the first detector layer at a minimum distance to the beam pipe wall;

* ensure thermo-mechanical stability over time;

* ensure accessibility for maintenance and inspection.
<figure><img src="image_35.png" /><figcaption>**Figure 27.** Overview of the mechanical structure of the ITS2. The upper panel shows the Inner Barrel, the Outer Barrel staves and the MFT in the back. The lower panel shows the IB and OB conical structural shells supporting the respective services.</figcaption></figure>

Also, the design of the support of the detector and services has to take into account the requirements set by the integration of the new Muon Forward Tracker (MFT) and the Fast Interaction Trigger system (FIT), which are installed very close to the ITS2. The main mechanical support structures of the ITS2 are shaped in two barrels made from carbon fiber composite. The inner shell supports the three innermost layers, while the outer shell supports the outer four layers. Each barrel is divided into top and bottom halves, which are installed sequentially around the beam pipe. Each barrel is composed of a detector section and a service section, as shown in figure 27. The staves are housed in the detector barrel and are connected to the readout and power systems via signal and power cables which are routed through the service barrel to the ALICE miniframe. The pipes that connect the on-detector cooling system to the cooling plant in the cavern are also routed through the service barrels.

**Detector support structure.** The main structural components of the detector barrels are the end-wheels and the cylindrical and conical structural shells. Two light composite end-rings provide the reference plane for the fixation of the two extremities of each stave. The position of the staves in the reference plane is given by a ruby sphere, matching an insert in the mechanical connectors at both extremities. This system ensures accurate positioning, within a few µm, during the assembly and provides the possibility to dismount and re-position the stave with the same accuracy in case of maintenance. Finally, the staves are clamped by a bolt. The end-wheels on the A-side also provide the feed-through for the services.
An outer cylindrical structural shell connects the opposite end-wheels of the barrel and avoids that external loads are transferred directly to the staves. As shown in figure 27, in order to minimise the material budget in the detection area, the following design choices were adopted:

* The inner barrel is conceived as a cantilever structure supported at one end outside the outer barrel acceptance;

* The outer barrel has no intermediate mechanical structures between the four detection layers within the detector acceptance.

The design of the outer barrel allows the separate assembly inside the TPC of all half-layers, which then are combined sequentially, starting from the outermost layer. The mechanical connection between the two double layers is provided by two conical structural shells located at the extremities of the detection area (figure 27). All the barrel support structures are attached to the cage (figure 87), acting as the main supporting element inside the TPC bore.

### 3.2.3 Readout and powering systems

The readout and powering systems are composed of 192 identical readout units and 142 power boards, and have complete control over all sensor operations, including power management, triggering, data readout and slow control. One of the major goals for the ITS upgrade was to minimize the detector material budget, which for the inner layers is on average 0.36% $X_0$ per layer [15]. Reducing the sensor power consumption implies softer cooling requirements, and hence decreasing the passive mass in the system. Transferring data from the sensors to the front-end electronics represents a significant part of the total power budget. To reduce the power consumption, intermediate conversions between electrical and optical layers were avoided. Therefore, the high-speed transceiver on the sensor [16] directly drives the differential line connecting it to the front-end electronics, using the shortest possible path in order to achieve the target bit-rate of 1.2 Gb/s within the power budget [17]. Consequently, both readout units and power boards are located within the ALICE L3 magnet, in a magnetic field of ~0.5 T and exposed to the radiation environment. All system components were validated for these conditions [18].

The matrix of 1024 × 512 pixels of the ALPIDE sensor is digitally read out through serial links at 1.2 Gb/s or 400 Mb/s in the inner and outer barrel, respectively. Because of the higher occupancy, the sensors in the inner barrel are read out individually whereas those in the outer barrel are read out in groups of seven using the master-slave mode described in section 2.3. As mentioned in section 3.2.1, the middle and outer layers share the HIC as a common building block and are identical from the readout point of view. Such a HIC is composed of two rows of seven sensors, where each row implements the aforementioned master-slave topology.

### 3.2.4 The readout system

To maximize the modularity of the system, the readout electronics are organized in 192 autonomous readout units, one for each stave. As schematically shown in figure 28, the readout units provide control and trigger and read the high-speed data lines from the ALPIDE chips. The readout units are identical, and only the I/O connections layer in the firmware adapts to the connected stave. Each readout unit connects to a common readout unit (CRU), see section 2.2, through the optical Versatile
<figure><img src="image_36.png" /><figcaption>Figure 28. Schematic design and interconnections of the ITS2 readout unit.</figcaption></figure>

Link [19], which is custom made by CERN and provides a 3.2 GB/s radiation-tolerant physical transport layer including forward data correction. One downlink is used to transmit the slow-control commands from the counting room to the readout units, while up to three upstream links from each readout unit can transmit in parallel to achieve the needed readout bandwidth. A separate link is used to receive the trigger from the Central Trigger Processor (CTP).

The maximum necessary data bandwidth is determined by the collision system, the interaction rate, and the characteristics (pixel size, noise, etc.), and positioning of the sensors. The maximum bandwidth of 1.2 Gbit/s suffices for the readout of Pb-Pb collisions at interaction rates up to 100 kHz. For the middle and outer layers, the required bandwidth is lower, even though the sensors are read out in groups of seven sensors in master-slave mode. For those layers, the data link is configured for a maximum bandwidth of 400 Mbit/s between the master chips and the readout unit. Table 5 gives an overview of the data flow and bandwidth in the different parts for each layer. Each link represents a direct connection between a master sensor and a readout unit, while the payload is the actual available bandwidth for the data once the 8b/10b transmission encoding overhead is accounted for.

<table><caption>Table 5. Summary of the ITS2 readout connections and payload capacity.</caption><thead><tr><th>Layer</th><th>Staves</th><th>Links per stave</th><th>Links bandwidth [Gb/s]</th><th>Link payload [Gb/s]</th><th>Bandwidth per stave [Gb/s]</th><th>Payload per stave [Gb/s]</th><th>Bandwidth per layer [Gb/s]</th><th>Payload per layer [Gb/s]</th></tr></thead><tbody><tr><td>0</td><td>12</td><td>9</td><td>1.2</td><td>0.96</td><td>10.8</td><td>8.6</td><td>129.6</td><td>104</td></tr><tr><td>1</td><td>16</td><td>9</td><td>1.2</td><td>0.96</td><td>10.8</td><td>8.6</td><td>172.8</td><td>138</td></tr><tr><td>2</td><td>20</td><td>9</td><td>1.2</td><td>0.96</td><td>10.8</td><td>8.6</td><td>216.0</td><td>173</td></tr><tr><td>3</td><td>24</td><td>16</td><td>0.4</td><td>0.32</td><td>6.4</td><td>5.1</td><td>153.6</td><td>123</td></tr><tr><td>4</td><td>30</td><td>16</td><td>0.4</td><td>0.32</td><td>6.4</td><td>5.1</td><td>192.0</td><td>154</td></tr><tr><td>5</td><td>42</td><td>28</td><td>0.4</td><td>0.32</td><td>11.2</td><td>9.0</td><td>470.4</td><td>376</td></tr><tr><td>6</td><td>48</td><td>28</td><td>0.4</td><td>0.32</td><td>11.2</td><td>9.0</td><td>537.6</td><td>430</td></tr><tr><td>Total</td><td>192</td><td></td><td></td><td></td><td></td><td></td><td>1872</td><td>1498</td></tr></tbody></table>
The ITS2 can operate in two modes, triggered and continuous. In triggered mode, pixel hits on the sensors are latched into the sensor memory and then transmitted to the readout boards only if a trigger command arrives within a few microseconds after the event that generated them. In continuous mode, data are always recorded and transmitted, segmented in time frames of programmable duration, where all the events within the same time frame share the same timestamp.

The total bandwidth per stave was adapted to match the capacity of 3 CERN Versatile Link upstream connections per readout unit, with aggregate payload bandwidth of 9.6 Gb/s (3 × 3.2 Gb/s). The system would saturate only at 200 kHz of Pb-Pb collisions. A detailed description of the components and operating modes of the readout units can be found in ref. [18].

### 3.2.5 The powering system

The ITS ALPIDE sensors require 1.8 V analogue and digital power rails; a reverse bias can be applied to the sensor substrate. Power regulation happens through linear regulators mounted on custom power boards, which are housed in the same rack as the corresponding readout unit. The power boards have built-in I2C [20] interconnection to monitor their functional parameters in real time, including the sourced currents and voltages. The readout unit has full control over the power board through the I2C bus: power sequence, monitoring and tuning is therefore managed from the counting room through the same Versatile Link used to manage the data acquisition and read the sensors, as shown in figure 28.

As described in section 3.2.1, staves are connected to the powering system via aluminium power buses. The inner barrel staves have the main power conductors integrated in the FPC that also carries the signal and control lines, while a separate power bus and bias bus are required for each half stave of the middle and outer layers. In the inner staves all nine sensors share the same power bus, while in the middle and outer layers the power delivery path is (half-)separate for each HIC (see figure 24). The power boards can drive up to 16 analogue and digital power rails, providing supply for a full outer barrel stave, which is composed of 14 HICs. The main power supplies are CAEN mainframes (EasyCrates) populated with 61 A3009B radiation tolerant CAEN power modules complemented by 4 CAEN A2518 LV modules for the reverse substrate bias located in the racks in the cavern and in the counting rooms, respectively.

The power board consists of two power units, which contain 16 low voltage and 8 reverse-substrate bias channels. The two power units feature independent I2C control interfaces and output connectors. They are based on radiation tolerant LDO regulators, shunt resistors, overcurrent protection circuitry, current and voltage measuring circuitry, and remote voltage-setting circuitry.

A power unit can power an inner-barrel stave, a middle-layer stave or an outer-layer half-stave. In order to allow every readout unit to control the power units of the attached detector segment, channels have to stay unused. A total of 142 power boards are used to supply the entire ITS2.

### 3.2.6 Component production, detector assembly, and commissioning on surface

The assembly of HICs and staves, and their characterization was distributed over 13 sites spread across North America, Europe and Asia. The workflow is schematically represented in figure 29.

The produced staves were transported to CERN where a large clean room was built to allow assembly of the full detector as well as on-surface commissioning activities before the installation in the ALICE cavern. Staves were assembled into layers by mounting them on the support structures.
<figure><img src="image_37.png" /><figcaption>**Figure 29.** Schematic description of the stave production workflow.</figcaption></figure>

The layers were assembled into four separate half-barrels, two for the inner and outer barrels each. Each half-barrel was then connected to the readout units, power boards, and the cooling system. Throughout the year 2020, the full detector was under commissioning on the surface, with the half-barrels located next to each other to facilitate stepwise integration (figure 30).

<figure><img src="image_38.png" /><figcaption>**Figure 30.** ITS2 in the clean room during on-surface commissioning. The lower left shows a zoomed-in view of the half barrels of the outer barrel (OB) and inner barrel (IB) type.</figcaption></figure>

During commissioning, the detection efficiency, readout performance, and noise levels were characterised. As an example of the results obtained during the commissioning, the fake-hit rate
<figure><img src="image_39.png" /><figcaption>**Figure 31.** Fake-hit rate of an inner half-barrel as a function of the number of masked pixels.</figcaption></figure>

measured for one inner-barrel half barrel is reported here. Randomly distributed triggers were sent to all the chips in the layer and the generated hits were registered. These hits are due to noise as well as to cosmic rays crossing the detector in coincidence with the trigger. In the inner barrel, the fake-hit rate was found to be dominated by roughly hundred pixels per half-barrel as shown in figure 31 [21], where colors indicate how often a pixel fired in $15 \times 10^6$ events acquired at a trigger rate of 50 kHz using a charge threshold of $100 e^-$, e.g. there were 24782 pixels which fired once in the sample. Masking these pixels leads to a fake-hit rate of $1 \times 10^{-10}$ pixel/event. This is significantly better than the target value of $1 \times 10^{-6}$ pixel/event [15]. The majority of pixels which remain after this masking show one or two hits, which is consistent with the expected rate from cosmic muons.

### 3.2.7 Detector calibration

The calibration procedure for the ITS2 consists of two main steps, namely the identification and masking of noisy pixels and the optimization of the in-pixel discriminator thresholds. The calibration has to be performed on a regular basis both to determine the best operating point of the detector and to measure its performance for the chosen operating point at regular intervals. The majority of the calibration scans is based on the injection of analogue or digital pulses into the single pixels, most notably the measurements of the pixel thresholds and their tuning to optimal values. The scan is executed completely by the DCS software, which controls sequencers on the readout units that trigger pulses to the chip. The main challenge in the threshold calibration is related to the high data rate generated by 12.5 billion channels. A threshold scan of the full detector with 50 charge injection points and 50 hits per point results in about $3 \times 10^{13}$ hits or approximately 100 TB of raw hit data. If the scan is performed as fast as the on-detector bandwidth allows, this data will be collected in slightly less than 1 hour, resulting in a data rate of 20–30 GB/s. However, a full scan is generally used as a reference and it is not needed on a daily basis. In fact, to ensure a good threshold calibration of the detector it is sufficient to pulse about 1% of the pixels; such a scan can be completed in under 5 minutes.
In order to process the larger amount of data in a timely way, the analysis is performed in a distributed manner on the EPNs (see section 5.3), making use of the ALICE DPL (see section 5). Once the pixel thresholds are properly tuned, the next calibration step is performed, namely the detection and masking of the noisiest pixels. In general, the fraction of noisy pixels masked is below 0.1 ‰ which leads to an overall fake-hit rate of about $10^{-8}$ hits/event/pixel on average, well below the required $10^{-6}$ hits/event/pixel by design.

After a successful calibration, the addresses of the pixels to be masked and the ALPIDE register settings for threshold tuning are sent off to be stored in the configuration database using a dedicated WinCC panel in the DCS.

### 3.2.8 Installation and global commissioning

The installation of the ITS2 in ALICE started in January 2021, when the services were transferred from the on-surface commissioning hall to the experimental cavern. The detector was installed on rails in the so-called “cage” (see section 4), hosting the beam pipe, ITS2 and MFT inside the ALICE TPC. Several insertion tests were performed on the surface to optimise the procedures and to identify potential interferences. For the final installation inside the experimental apparatus, up to six cameras where used to continuously monitor key contact points during insertion, since the clearance between staves of top and bottom barrels is of the order of a millimeter. Furthermore, surveys were carried out to determine the exact position of the detector elements and the beam pipe and visualize them with the help of three-dimensional scans carried out earlier on the surface. At each step of the insertion process, CAD models of the insertion process were compared with the camera images to verify the positioning of the detector elements. The process started in March 2021, with the outer barrel installation. Figure 32 (top) shows layer 3 in position in ALICE, around the beam pipe. The visible surface is covered by the power distribution bus. After the installation, the outer barrel was thoroughly tested before the inner barrel was inserted into its final position in close vicinity to the beam pipe, in May 2021. Figure 32 (bottom) shows the bottom half of the inner barrel in its final position at around 1 mm distance from the beam pipe. The full detector was installed without damaging any component.

### 3.2.9 First results from global commissioning

After connection and verification of the detector and its services, the focus was set on the central system integration and on gaining experience with the final framework for the operation of the detector. First cosmic muon tracks traversing the full detector, like the one shown in figure 33, could be acquired using continuous integration without a dedicated trigger signal. These tracks were found by matching three hit points in the layers 4 to 6 of the outer barrel and requiring another hit point in the inner barrel, at a rate of about 0.02 Hz, while those traversing only the outer barrel were more frequent (0.5 Hz). The commissioning campaign continued throughout the year and allowed to optimise the detector control system (DCS), the calibration procedures, and readout parameters. During the pilot beams with pp collisions at injection energy (450 GeV) in October 2021, reconstructed tracks from the ITS2 were used to determine the position of the primary vertex, as shown in figure 34, and continuously monitor it online in the QC plots. The primary vertex position is one example of the quantities that are continuously monitored by the online quality control system of the $O^2$ analysis framework to assess the quality of the data acquired with the ITS2.
<figure><img src="image_40.png" /><figcaption>**Figure 32.** Top: outer barrel surrounding the beam pipe with the Muon Forward Tracker (MFT) in the background. Bottom: ITS2 inner barrel bottom half-barrel next to the beam pipe, outer barrel and MFT in the background.</figcaption></figure>
<figure><img src="image_41.png" /><figcaption>**Figure 33.** Event display of a cosmic muon traversing all layers of ITS2 twice, no magnetic field.</figcaption></figure>

<figure><img src="image_42.png" /><figcaption>**Figure 34.** Longitudinal distribution of the primary vertex positions from ITS2 tracks reconstructed online during the LHC pilot beam in October 2021.</figcaption></figure>
<figure><img src="image_43.png" /><figcaption>**Figure 35.** Schematic view of the Muon Forward Tracker (left) and its integration with the central barrel (right).</figcaption></figure>

## 3.3 Muon forward tracker

The Muon Forward Tracker detector (MFT), see figure 35, is a high position resolution silicon detector, which has been designed to extend the physics program of the muon spectrometer (see section 3.6). Its primary goal is to improve the pointing resolution of muons by matching the tracks reconstructed downstream of the hadron absorber to those reconstructed inside the MFT upstream of the absorber [22]. This approach allows the removal of multiple scattering effects in the hadron absorber and improves the pointing resolution of muon tracks down to about 100 µm. The MFT is located between the interaction point and the front absorber and surrounds the beam pipe at the closest possible distance. It provides charged particle tracking in the pseudorapidity interval $-3.6 < η < -2.45$, which covers most of the muon spectrometer acceptance. The acceptance boundaries are defined on one side by the size of the beam pipe, and on the other side by the volume and position of the ITS2, the FIT-C and the beam pipe support, as shown in figure 35.

### 3.3.1 Detector layout

The MFT has a projective geometry (see figure 35) based on five disks, coaxial with the beam pipe and labelled D00 (innermost) to D04 (outermost), the first two (D00 and D01) being identical and the others (D02, D03 and D04) having their diameters increasing with the distance from the interaction point. To ease assembly and insertion, the detector is divided into two identical halves, labelled H0 for the bottom part and H1 for the top part. The MFT is composed of a total of 936 ALPIDE silicon sensors (see section 2.3) distributed on both sides of the ten half-disks, and arranged in detection modules called ladders. Each ladder is a hybrid integrated circuit with two to five sensors (depending on the position within the disk), which are glued and interconnected on a flexible printed
circuit (FPC) board to provide the power and readout connections. In order to minimize the material budget, the silicon-pixel sensors constituting the MFT are thinned down to the same thickness of 50 µm as the ITS2 inner barrel sensors (see section 3.2), and the FPC to which they are connected are made of polyamide with two layers of aluminum on either side. Each ladder is connected to a PCB that is located outside the acceptance, external to each half face. The MFT contains 240 ladders whose positions were defined to ensure an 85% overlap of the sensors between the two faces of each disk. The face of the half-disks is subdivided into four zones (each containing between three and five ladders) which yields a total of 80 zones for the full MFT.

The ten half-disks are then assembled into half-cones. The first three half-disks are connected to a set of motherboards that provide the connection of the readout lines with 6.5 m long copper cables, which run alongside the whole absorber towards the front-end electronics boards. For the two larger half-disks, the same type of copper cables is used, connected directly to the PCBs. Each half-cone also houses a Power Supply Unit (PSU), which controls and monitors the powering of the zones to guarantee the ladder safety and is located outside the acceptance between the last two half-disks. The disks and the PSU are water-cooled and air ventilation is used to ensure temperature homogeneity inside the confined space where the MFT is mounted. Figure 36 shows an exploded view of the different elements composing the detector. The two half-cones are fixed to two end-cap patch-panels which in turn are fixed to large carbon fibre composite structures, called half-barrels, that are used to insert and position the MFT within the ALICE internal cage, see section 3.5. The services are routed along the half-barrels and through the patch-panels to reach the detector. The patch-panels are mechanical pieces used also to support the FIT-C detector and to interconnect the readout cables from the half-cones to the readout units, which are located 6 m away beside the front absorber. Figure 37 shows a fully assembled half-cone and the MFT in its final position.

<figure><img src="image_44.png" /><figcaption>**Figure 36.** Detailed view of the elements composing the MFT detector.</figcaption></figure>

### 3.3.2 Ladder assembly and testing

The basic element of the MFT detector, called ladder, is composed of an aluminum FPC on which silicon-pixels sensors are glued and interconnected. The length of the ladders varies from 2 to 5 chips each to match the size of the half-layers. Each FPC is equipped on one side with footprints for
<figure><img src="image_45.png" /></figure>

<figure><img src="image_46.png" /><figcaption>**Figure 37.** Left-hand panel: fully assembled half-cone of the MFT with patch-panel and the FIT-C detector. Right-hand panel: the MFT in its final position; the cooling and power services can be seen along the half-barrels.</figcaption></figure>

placing the sensors and a 70-pin connector for powering the chips and transmitting the high-speed readout signals, and on the other side with microelectronic components (resistors and capacitors) that decouple the power supply (analog and digital) of the sensors and adapt the impedance of the data lines. Given their variable length, the FPC design was optimized in order to reduce the maximum voltage drop to 100 mV and to ensure the best transmission of the high-speed data lines.

The ladder assembly took place in the clean room of the CERN EP/DT Departmental Silicon Facility using a three-axis digitally controlled placement machine, called ALICIA (ALICE Integrated Circuit Inspection and Assembly machine), which places the chips with a precision of 5 µm on a specially machined stainless steel support with a lattice of very small holes to hold the chips in position by suction. At the same time, the FPC is positioned on a suction support which also keeps it perfectly flat and positioned with a precision better than 300 µm. Small dots of Araldite-type two-component glue are applied to the FPC using a stainless-steel stencil with conical holes. The FPC is flipped and positioned opposite to the chips with the help of precision centering pins. The weight of the FPC carrier provides sufficient pressure to spread out the glue and a spacer between the FPC and the chips ensures that the final thickness of the glue layer is around 50 µm. After curing of the glue, the assembly is removed from ALICIA, visually inspected and brought to the CERN bond-lab, where the connection between the FPC and the chips is realized by ultrasonic micro-wire bonding on the metallized pads of the FPC. Each micro-interconnection consists of 3 wires with 25 µm diameter that pass through the vias of the FPC to be connected to the 74 pads on the surface of the sensors. The assembly of the ladder is then completed and a final visual inspection verifies the quality of the interconnections. Figure 38 shows a picture of an assembled ladder.

Once the ladder is assembled, it is transferred to the MFT laboratory where it undergoes a battery of tests to qualify its performance. In the laboratory, two test benches allow each ladder to be qualified from an electrical and functional point of view. First of all, the ladder is gradually powered with analog and digital voltage and its power consumption is checked. Then, the ladder is connected to an acquisition system developed specifically for the ITS2 and the MFT projects, which allows its functionality to be tested in terms of electronic noise, number of dead or defective pixels, and transmission speed of the digitized data. Each test is associated with a qualification grade which
<figure><img src="image_47.png" /><figcaption>**Figure 38.** Example of an assembled MFT ladder. Upper picture: back side of the FPC with the glue spots on which the sensor are glued. Bottom picture: front view of assembled ladder.</figcaption></figure>

is a function of the performance measured against the expected specifications and automatically determined by the qualification software. At the end of these tests, the ladder is qualified according to four grades:

* "Gold" for a ladder that works perfectly and whose pixels and circuitry respond exactly as expected.

* "Silver" when the number of pixels which do not respond correctly is between 0.1 and 4‰ and the ladder can be used without any problem.

* "Bronze" when the number of defective pixels is between 0.4 and 1% and the ladder, although functional, is used as spare rather than for equipping the MFT detector.

* "non-compliant" when a ladder does not pass the tests because of, for example, damaged chips, a defect of the FPC or improper handling. This ladder is discarded.

To fully equip the MFT (including one additional half detector and 20% spares modules), 500 ladders were manufactured, tested, qualified and mounted on the disks in one year with a rate of gold and silver qualified ladders of around 91%.

### 3.3.3 Half-Disks

As shown in figure 39, each half-disk is composed of a support to which a heat exchanger is glued and two PCBs are screwed. The ladders are glued onto each face of the heat exchanger, screwed to the support, and connected to the PCBs. Four different types of half-disks were designed since the first two disks (D00 and D01) are identical.

The half-disk supports, which form the mechanical interface between the elements of the half-disk and the cone structure, were also designed to ease integration of services (cooling pipes and power cables). To minimise the material budget, the support structures are made of PEEK (PolyEtherEtherKetone plastic).

The ladders are connected to a PCB to route the readout, slow control, and clock signals from the ladders to connectors located at the periphery of the half-disk. The PCBs of half-disks D00, D01 and D02 are connected to motherboards that relocate the connection to readout cables for integration reasons. For half-disks D03 and D04, the readout cables are directly connected to the PCBs. The
<figure><img src="image_48.png" /><figcaption>**Figure 39.** Exploded view of a half-disk (D00-01).</figcaption></figure>

PCB also distributes the different voltages (analog, digital, and reverse bias) to the ladders. Two connectors are located on the left and right sides, one for zones 0 and 1, and the other for zones 2 and 3. The PCB is equipped with decoupling capacitors located close to the ladder and power connectors. In addition, a temperature sensor (PT100) allows the measurement of the local temperature and the acquisition of a reference for the temperature information given by the ALPIDE chips. The temperature signal is sent to the PSU on a dedicated line of the power cables.

The heat exchanger was designed to keep the ALPIDE sensors at a temperature below 30°C using water cooling and to have a total material budget per half-disk below 0.7% of a radiation length. It is composed of two K13D2U carbon fiber cold plates glued to each side of a 14 mm thick core made of Rohacell foam. To circulate cooling water under each sensor, 3 or 4 kapton tubes of 1 mm diameter are glued and covered by a carbon fleece. Two manifolds made of PEEK are glued on each side of each heat exchanger to distribute water through the kapton pipes.

The heat exchangers are qualified in several steps. First, the internal structure is inspected using X-ray tomography in order to check the quality of the gluing and the integrity of the cooling pipes. Before closing the second manifold, the water flow exiting each pipe is measured in order to verify that none of the pipes are pinched. Finally, cooling tests are performed by using resistive patches to simulate the heat generated by the sensors. The temperature is monitored with PT100 sensors located on the heat exchanger and a thermal camera. The goal is to check the homogeneity of the cooling.

The ladders are glued to half-disks using the Dow Corning SE4445-CV silicon glue. The pattern of glue deposition was studied to avoid any flow outside the area of each sensor (see figure 40). The planarity of the heat exchanger is around 50 µm and the final thickness of the glue is around 50 µm. The ladders are positioned using a gantry and plugged into the disk PCB. Electrical and communication tests of the sensors are performed to check their proper functioning. In case of failure in the electrical and functional tests, the ladder can be replaced before the glue is fully cured. The remaining glue is removed and a new ladder can be glued.

### 3.3.4 Cone and barrel

Each MFT half-cone is supported by a mechanical structure on which three motherboards for the readout are mounted (see section 3.3.6). The different half-disks and the PSUs (see section 3.3.5) with their support are mounted on this structure and the different services (readout cables, power
<figure><img src="image_49.png" /><figcaption>**Figure 40.** Left: half-disk during ladder gluing. Right: glue deposition pattern.</figcaption></figure>

<figure><img src="image_50.png" /><figcaption>**Figure 41.** Half-cone structure with air ducts in light blue.</figcaption></figure>

cables, and cooling pipes) are routed inside this structure. The environment of the MFT, in particular the presence of the very fragile beam pipe, imposed several constraints on the design of the cone. As the MFT cone is supported from the side close to disk D04, the displacement due to gravity is the largest at disk D00. This displacement has to be kept below 100 µm to avoid interference with the beam pipe support flanges which are positioned very close to the detector. The cone support structure was produced from aluminum. In order to homogenise the temperature inside the cone, air guides produced by a 3D-printer were added, see figure 41. Reference targets can be fixed to the support structure for the purpose of geometry surveys.

Each half-cone is fixed onto a half-barrel which is built from composite material along which the services (power cables, water pipes, and air ducts) are run as shown in the right-hand panel of figure 37. On the A-side, a patch-panel (PP2) is mounted to guide these services. On the C-side, the patch-panel has the following functions:

* position and support a half-cone
* connect and guide the services from/to the half-cone (this is where the filter boards are fixed, see section 3.3.5)

* position and support the FIT-C detector.

Finally, the half-barrels are equipped with wheels that run on guide rails for the insertion of the half-cones into their final position.

### 3.3.5 Services

The ALPIDE sensors require three different voltage supplies (analog, digital and reverse bias) which are locally generated via DC-DC converters in a PSU in order to minimize the material budget in the barrel by reducing the number of copper power lines and moving the fine power distribution as close as possible to the active detector area. The MFT is equipped with four PSUs, each powering one face of the five half-disks of the same half-MFT. Each PSU is composed of two boards (see figure 42): a main board ensures power distribution from the DC-DC converters and a mezzanine board controls the main board and is equipped with one GBT-SCA to send measurements to the DCS (voltages, currents, temperatures, humidity, and status of zones). The different functionalities of the PSU are:

* Conversion of the eternal power supply for the analog and digital circuitry of the sensors by FEASTMP-CLP DC-DC converters.<fnref n="1" /> One DC-DC converter is used to power two zones of the same half-disk face (0-1 or 2-3) with analog voltage. For digital voltage, one DC-DC converter is also used to power two zones for half-disks 00-01-02 and one zone for half-disks 03 and 04 since they have more sensors per zone and the output current is limited to 4 A. The voltage drop from the PSU to the sensors is taken into account and the output voltages of the DC-DC converters are adjusted accordingly.

* Detection of latch-up events through the measurement of currents per zone (analog, digital, and reverse bias). In case of latch-up, all voltages of the zone are switched off and the information of the line that has generated this event is encoded and transmitted.

* Communication with DCS is realised by the use of GBT-SCAs to control DC-DC converters, reset zones, adjust reverse bias voltage and thresholds on analog, digital and reverse bias currents. It is also used to send the measurements of voltages, currents, and temperatures of the half-disks, of the inlet and outlet of cooling of the PSU, of the ambient temperature (two sensors on the mezzanine board), and finally of the humidity (sensor located on the mezzanine board). The status of zones and the latch-up information are also sent to DCS.

* Fail-safe procedure: in case of a loss of communication with the DCS for more than 6 s, all voltages are automatically switched off and the DC-DC converters are disabled.

All the PSUs are controlled through a dedicated CRU via four intermediate boards, called PSU-Interfaces (one per PSU), equipped with GBTx ASICs.

<footnote n="1">¹A DC-DC converter is an electronics circuit that converts a continuous current from one voltage level to another.</footnote>
<figure><img src="image_51.png" /><figcaption>Figure 42. MFT PSU boards with mezzanine assembled on their support.</figcaption></figure>

### 3.3.6 Readout

The MFT readout is based on the same general architecture used for the ITS2 detector (based on the Readout Unit front-end board, see section 3.2.4) arranged with an implementation specifically designed for the MFT geometry. In particular, the 50 Ω differential pairs connecting the sensors to the external readout are routed from the disk to the cone section, then to the patch panel, and finally along the sides of the ALICE front absorber to the readout crates. This requires a specific design of the routing elements and cables in order to provide a reliable connection quality, in particular for the high speed data link at 1.2 Gb/s used for data transmission over a distance of several meters. The design and development of the MFT readout architecture contains a larger number of connections and passive elements than the ITS2, due to constraints on the number of cables that can be routed through the barrel detectors. All signals are instead routed through the limited space between the absorber and the TPC, requiring a sequence of passive dispatching elements, each one inducing specific constraints in terms of impedance adaption, which is a crucial parameter for the high-speed signal transmission quality.

### 3.3.7 Detector commissioning

The two halves of the MFT detector, together with a third spare half, were assembled by the end of 2019. Over almost one year, the detector was fully qualified and commissioned in the laboratory in order to assess and optimize its operation in terms of powering, cooling, and readout. A detailed study of the noise rates was performed and summarised in figure 43, which shows the fake-hit rate as a function of the number of masked pixels. A noise occupancy below $10^{-7}$ hits per pixel and per event is obtained by masking only 138 pixels out of a total of 490 millions pixels. This result is well within the specifications for the detector.

The installation of the MFT into the ALICE experiment took place in December 2020 and required several months of activity to route all the services and integrate this new detector within the ALICE central systems. A detailed commissioning phase confirmed that the noise levels measured in the laboratory were unchanged after the complex installation inside the ALICE cavern. Moreover, the MFT was ready to take data in October 2021 during the commissioning of the LHC injection lines, using proton beams injected into the transfer line, which are dumped on the Target Extraction Dump (TED). Interactions of the proton beam with the TED, which is located around 30 m upstream
<figure><img src="image_52.png" /><figcaption>**Figure 43.** Noise occupancy, measured in hit/pixel/event as a function of the number of masked pixels over the whole MFT detector.</figcaption></figure>

<figure><img src="image_53.png" /><figcaption>**Figure 44.** Display of the reconstructed muon tracks in the MFT from a TED shot event.</figcaption></figure>

from the ALICE cavern, produce a shower of muons traversing the ALICE detector. As shown in the event display in figure 44, the MFT detector was able to detect and reconstruct these muon showers, proving its readiness for data taking in Run 3.

## 3.4 Time projection chamber

This section summarizes the upgrade of the ALICE Time Projection Chamber (TPC). A more detailed description of the upgrade can be found in [14, 23].

### 3.4.1 Introduction

The TPC was successfully operated in pp, p-Pb, Pb-Pb, and Xe-Xe collisions at a variety of collision energies [2, 24] during LHC Runs 1 and 2 (2009 to 2018). Its active volume has a cylindrical shape with a length and outer diameter of about 5 m, resulting in a total active volume of 88 m³ (see figure 45). It covers a symmetric pseudorapidity interval around midrapidity ($|η| < 0.9$) at full azimuth. The field cage has a high-voltage electrode in its center, which divides the active volume into halves. The inner diameter of the central field cage drum is 114 cm, which provides the necessary space for the installation of the ITS. Each of the two endplates is subdivided into 18 azimuthal sectors. Each sector houses one inner (IROC) and one outer readout chamber (OROC).
<figure><img src="image_54.png" /><figcaption>**Figure 45.** Schematic view of the ALICE TPC.</figcaption></figure>

During Runs 1 and 2, the readout chambers were based on multiwire proportional chamber (MWPC) technology. MWPCs have to be operated with an active ion gating grid in order to collect ions from the amplification region. Otherwise, these ions would drift back into the drift volume, where they would lead to substantial space-charge distortions. However, triggered readout is not compatible with the goals of the ALICE upgrade described in section 5. Instead, the upgraded TPC must be read out continuously. This implies that the previous readout system, including the readout wire chambers and the front-end electronics needed to be replaced. At the same time, the excellent performance achieved in Runs 1 and 2 needed to be maintained in order to achieve the ambitious ALICE physics program for Runs 3 and 4. A $dE/dx$ resolution of 5% (for isolated tracks) translates into a requirement for the local energy resolution of better than 14% at the $^{55}$Fe-peak.

On average, at a collision rate of 50 kHz, tracks from five collisions pile up within the TPC drift time window of about 100 µs. Without continuous readout, not all of these interactions can be read out. With continuous readout, however, novel gas amplification techniques are required in order to provide sufficient ion blocking without an active ion gate. The requirement to keep the ion-induced space-charge distortions at a tolerable level leads to an upper limit of 2% for the fractional ion backflow (defined as the ion escape probability per effective electron-ion pair produced in the gas amplification stage) at the operational gas gain of 2000.

Gas Electron Multipliers (GEMs) [25] provide a viable solution to this challenge. They can be arranged in stacks, creating layers of amplification stages, which can be tuned accordingly. With a careful optimization of the gain share among the GEMs, and by efficiently blocking the path of back-drifting ions that emerge from subsequent layers, the required low ion backflow can be achieved.

The gas mixture for the operation of the upgraded TPC is Ne-CO₂-N₂ (90-10-5), i.e. 90 parts of Ne, 10 parts of CO₂, and 5 parts of N₂. No changes to the existing gas hardware were necessary, since the TPC had already been operated with this gas mixture in Runs 1 and 2. A mixture based on
<table><caption>**Table 6.** Parameters of the upgraded TPC. Table taken from [14].</caption><tr><td>Detector gas</td><td>Ne-CO<sub>2</sub>-N<sub>2</sub> (90-10-5)</td></tr><tr><td>Gas volume</td><td>88 m<sup>3</sup></td></tr><tr><td>Drift voltage</td><td>-100 kV</td></tr><tr><td>Drift field</td><td>400 V/cm</td></tr><tr><td>Maximal drift length</td><td>250 cm</td></tr><tr><td>Electron drift velocity</td><td>2.58 cm/µs</td></tr><tr><td>Maximum electron drift time</td><td>97 µs</td></tr><tr><td>ωτ (B = 0.5 T)</td><td>0.32</td></tr><tr><td>Electron diffusion coefficients</td><td>D<sub>T</sub> = 209 µm/√cm<br>D<sub>L</sub> = 221 µm/√cm</td></tr><tr><td>Ion drift velocity</td><td>1.168 cm/ms</td></tr><tr><td>Maximum ion drift time</td><td>214 ms</td></tr></table>

Ne has the advantage of a higher ion mobility compared to similar Ar-based mixtures, which directly reduces the magnitude of the space-charge distortions by nearly a factor of two [26].

Table 6 summarizes the most important TPC parameters. The drift time for ions from the readout plane to the central electrode is 214 ms at a drift field of 400 V/cm. Therefore, at 50 kHz, around $10^4$ collisions partially contribute to the space-charge distribution.

### 3.4.2 Readout chamber design

The new readout chambers of the upgraded TPC are based on stacks of four GEM foils. Foils with standard (S, 140 µm) and large (LP, 280 µm) hole pitch are combined to an S-LP-LP-S configuration, which is shown in figure 46. Most of the ions are produced in the last amplification step, i.e. GEM 4. Their drift path is efficiently blocked by the upper GEM layers by carefully optimizing the GEM voltages and transfer fields, and by choosing GEM hole patterns avoiding the accidental alignment of holes in subsequent layers. As figure 47 shows, an extended operational region satisfying the requirements (ion backflow below 2% and $\sigma(^{55}\text{Fe})$ below 14%) can be found with an S-LP-LP-S setup. The data exhibit a characteristic anticorrelation between ion backflow and the relative energy resolution $\sigma(^{55}\text{Fe})$. This effect is largely due to the operational conditions at GEM 1 since ions

<figure><img src="image_55.png" /><figcaption>**Figure 46.** Schematic view of a stack with four GEM foils. The baseline settings for the voltages across the four GEMs, the transfer fields between the GEMs, and the induction field between GEM 4 and the pad plane are indicated as well.</figcaption></figure>
<figure><img src="image_56.png" /><figcaption>**Figure 47.** Energy resolution $\sigma(^{55}\text{Fe})$ as a function of ion backflow (IBF) in a 4-GEM stack (S-LP-LP-S) in Ne-CO$_2$-N$_2$ (90-10-5). The gas gain is kept at 2000 in all measurements by adjusting the voltages on GEM 3 and GEM 4 at a fixed ratio of 0.8 or 0.95. Figure from [14].</figcaption></figure>

emerging from this layer have a large probability to escape into the drift volume. In order to minimize the number of ions produced at GEM 1, the gas amplification has to be reduced, which however also leads to an effective loss of primary ionization, and therefore to a degradation of the energy resolution.

A readout chamber consists of a trapezoidal aluminium frame (Al-body), a fiberglass plate (strongback) and a pad plane made of a multilayer printed circuit board (PCB). Figure 48 shows an IROC with the individual components. While an IROC is assembled from one Al-body, one strongback, one pad plane and one GEM stack, an OROC is assembled from one Al-body, one strongback, three pad planes and three GEM stacks labeled OROC 1, OROC 2 and OROC 3. The stacks consist of four GEM foils stretched and glued onto fiberglass epoxy frames, each containing a spacer cross. The geometrical parameters of the new readout chambers are summarized in table 7.

Figure 49 shows the most important features of the GEM design. The design of the Al-bodies includes a copper pipe for temperature control by water cooling. The electric potential is provided to the GEM stacks via feedthroughs. The strongback provides electrical insulation between pad plane and Al-body and reduces the pad capacitance to ground. The pad planes are made of a 3.2 mm thick FR4 multilayer board. The top PCB layer consists of copper readout pads, arranged in pad rows. The pad planes do not contain ground electrodes in order to minimize the capacitance to ground at the preamplifier input. The pads are connected to traces routed to vertical 40-pin female connectors on the backside of the pad plane. The routing of the traces is done using three additional PCB layers. The signal routing was designed to minimize the trace length. Four connectors in radial direction group 160 pads to connect to one front-end card (see section 3.4.6).

The GEM foils for the ALICE TPC upgrade were produced using the single mask technique [27]. The top side of each foil is subdivided into high-voltage segments with an area of about 100 cm$^2$.
<figure><img src="image_57.png" /><figcaption>**Figure 48.** Exploded view of an IROC with chamber body components and GEM frames. Figure taken from [14].</figcaption></figure>

<figure><img src="image_58.png" /><figcaption>**Figure 49.** GEM design details. The detail on top shows the 200 µm separation between the copper sectors and an additional clearance of 100 µm for the GEM holes from the copper edge. Figure taken from [14].</figcaption></figure>

The segmentation limits the currents in case of electrical discharges and minimizes the affected area in case a segment develops a short circuit. The gap between the adjacent segments is 200 µm. An additional 100 µm space is added between the segment boundaries and the surface containing GEM holes. Electric potentials are applied to a foil through wires soldered to HV flaps placed on the top
<table><caption>**Table 7.** Geometrical parameters of the new readout chambers.</caption><tbody><tr><td colspan="2"><strong>Readout chambers</strong></td></tr><tr><td>Total number</td><td>2 × 2 × 18 = 72</td></tr><tr><td>Readout technology</td><td>4-GEM stack, single mask, standard (S, 140 µm) and large (LP, 280 µm) hole pitch GEMs in S-LP-LP-S configuration</td></tr><tr><td>Effective gas gain</td><td>2000</td></tr><tr><td colspan="2"><strong>Inner (IROC)</strong></td></tr><tr><td>Total number</td><td>2 × 18 = 36</td></tr><tr><td>Active range</td><td>848.5 < r < 1321 mm</td></tr><tr><td>Number of HV segments per GEM foil</td><td>18</td></tr><tr><td>Pad rows</td><td>63</td></tr><tr><td>Total pads (IROC)</td><td>5280</td></tr><tr><td>S:N (MIP)</td><td>20:1</td></tr><tr><td colspan="2"><strong>Outer (OROC)</strong></td></tr><tr><td>Total number</td><td>2 × 18 = 36</td></tr><tr><td>Active range</td><td>1347 < r < 2464 mm</td></tr><tr><td>Total pads (OROC)</td><td>9280</td></tr><tr><td>S:N(MIP)</td><td>30:1</td></tr><tr><td>Pad rows</td><td>89</td></tr><tr><td colspan="2"><strong>OROC 1</strong></td></tr><tr><td>Active range</td><td>1347 < r < 1687 mm</td></tr><tr><td>Number of HV segments per GEM foil</td><td>20</td></tr><tr><td>Pad rows</td><td>34</td></tr><tr><td>Number of pads</td><td>2880</td></tr><tr><td colspan="2"><strong>OROC 2</strong></td></tr><tr><td>Active range</td><td>1708 < r < 2068 mm</td></tr><tr><td>Number of HV segments per GEM foil</td><td>22</td></tr><tr><td>Pad rows</td><td>30</td></tr><tr><td>Number of pads</td><td>3200</td></tr><tr><td colspan="2"><strong>OROC 3</strong></td></tr><tr><td>Active range</td><td>2089 < r < 2464 mm</td></tr><tr><td>Number of HV segments per GEM foil</td><td>24</td></tr><tr><td>Pad rows</td><td>25</td></tr><tr><td>Number of pads</td><td>3200</td></tr></tbody></table>

and bottom sides of the foil. From here, the potential is distributed via a 1 mm wide copper trace running along three sides of the foil. Each foil segment is connected to the HV trace via a 5 MΩ loading resistor ($R_{load}$).
### 3.4.3 Foil production, chamber production and quality assurance

In total, 45 IROCs and 40 OROCs were assembled over several years at several production sites. More than 300 shipments of material and subcomponents between the different production sites were necessary. Standardized transport and testing procedures and well defined assembly and quality-assurance protocols were followed in order to ensure high quality and reliability of the assembled ROCs. All assembly activities involving GEM foils were performed in clean rooms with class ISO 5 to 7, taking all precautions to avoid contamination of the GEMs.

The GEM foils were extensively tested before and after each transport. These tests consisted of optical inspection and a measurement of the leakage current [28]. An excessive current of a segment points to a shorted GEM segment. An increased current may come from a defect or contamination and was considered a potential danger. Shorted and contaminated GEMs were sent back to the production site for cleaning. An advanced quality assurance procedure, performed once for each GEM, consisted in a long-term (at least 5 hours) leakage current measurement and an optical survey [29–31]. During the optical survey, microscope photographs were taken of the entire GEM. The pictures were stitched together and analyzed for defects and hole-size nonuniformities. In total, 829 GEM foils were produced in the course of the project. The final yield of good foils after all production and quality assurance steps was about 91%.

The framing of a GEM foil consisted of stretching the foil and positioning it above a frame covered with a thin layer of epoxy glue. The framed foils were subsequently mounted on the preassembled readout chamber bodies, and the HV wires were soldered to the top and bottom HV flaps. The stacks are not glued, such that they can be disassembled and rebuilt in case of problems. After HV connection, resistance and capacitance across each foil were measured in order to identify possible issues at the earliest possible stage. The assembled detectors were mounted in gas-tight test and transport vessels and qualified, before being sent to CERN for acceptance tests, storage and installation in the TPC field cage.

At CERN, the accepted ROCs underwent a final stability test under irradiation. For these tests, the nominal gas mixture and the final components of the HV system were used. These tests were performed in the ALICE cavern during LHC operation or at the CERN Gamma Irradiation Facility (GIF++) [32, 33].

Those ROCs that were not accepted or replaced after initial commissioning of the TPC at the surface have been refurbished such that they are available as good spare chambers for an eventual replacement campaign in the future. The TPC could be brought to the surface again during the Long Shutdown 3 of the LHC in the years 2026 to 2028. The refurbishment of the ROCs includes in particular the assembly and installation of new GEM stacks.

### 3.4.4 Field cage

The field cage of the TPC is described in detail in [24]. The central drift electrode is biased to a potential of about –100 kV and generates a uniform electric drift field with the help of potential strips that are suspended close to the walls of the inner and outer field cage vessels. These strips are powered through a resistor chain housed in a water-cooled rod. In addition, aluminium strips are glued to the walls of the field cage vessels at a certain distance. These *guard rings* are powered through separate resistor chains. Their purpose is to prevent local charging-up of the surfaces. The potential of the last
strip of each resistor chain (both resistor rods and guard rings) is set to a value similar to that of the GEM 1 top electrodes facing the drift volume, which is around -3.26 kV for the nominal configuration. With respect to the original MWPC-based TPC, this potential is now higher, and requires to be set at the last strips with additional power supplies. The existing HV connections in flanges in the aluminium endplates of the field cage, and the connections to the last strips had to be adapted for the higher potential ratings. Suitable last resistors to ground were chosen to allow for a small current to ground.

### 3.4.5 HV system

The baseline settings for the voltages across the GEMs, for the transfer fields between the GEMs, and for the induction field between GEM 4 and the pad plane were optimized with respect to operational stability under the radiation load expected in Run 3. The settings are indicated in figure 46. The main feature is a very low transfer field $E_{T3}$ between GEM 3 and GEM 4 of only 100 V/cm. The other two transfer fields and the induction field $E_{ind}$ are kept at typical values around 3500 V/cm. The highest gain is provided in GEM 3 and GEM 4, while the gain in GEM 1 is relatively low. As a consequence, most ions are created around GEM 4. Their drift into the drift region of the TPC is hindered by the large-pitch foils utilized for GEMs 2 and 3, and by the very low transfer field $E_{T3}$.

An equalization of the gain across all 144 GEM stacks on the TPC is achieved by adjusting the voltages in GEM 3 and GEM 4. The induction field is corrected correspondingly in order to ensure that the potential on the GEM 1 top electrode remains uniform over all stacks, such that the uniformity of the drift field in the TPC drift volume is not disturbed.

A new HV system was designed for the operation of the GEM-based ROCs. A detailed description can be found in [14]. In order to maximize operational safety, while at the same time providing the highest possible flexibility, a power supply system with cascaded channels was chosen. In this way, the potentials at the various electrodes can be easily adjusted, and a safe operation of the GEM stacks can be guaranteed. A schematic view of the high-voltage system including all loading and protection resistors is shown in figure 50. A shunt resistor in the voltage distribution for the GEM 4 top electrode allows to periodically read the currents for all GEM stacks. During the operation of the TPC, current variations in the GEM stacks will directly relate to variations of the local track density in the TPC drift volume. In a high-definition current meter the currents are digitized at a rate of typically 1 kHz (8 kHz maximum) by 24-bit ADCs with a resolution of 3 nA. From these data, three-dimensional maps of the space charge from back-drifting ions can be extracted in order to calibrate drift-field distortions (see section 3.4.9). Finally, the powering scheme also includes the possibility to inject a pulser signal to the HV line of each GEM 4 bottom electrode for calibration purposes.

### 3.4.6 Front-end electronics and readout

A schematic view of the front-end electronics and readout system is shown in figure 51. A single Front-End Card (FEC) processes the signals from 160 input channels. The pulses are transformed into differential, semi-Gaussian voltage signals and then digitized in five SAMPA ASICs (see section 2.4). All ADC values are transmitted off-detector through two optical links. In this way, all data are available such that flexible filter algorithms can be applied in the FPGA-based readout cards (CRU, see section 2.2). One down-link is needed for control and configuration of a FEC. In total, 3276 FECs are needed to read out the TPC. This leads to 6552 data links and a total data
<figure><img src="image_59.png" /><figcaption>**Figure 50.** Detailed powering scheme of a GEM stack. Each subsequent high-voltage channel is stacked on top of the lower-lying channel. The ground reference is defined by a separate line connected to the ground of the detector. The line for GEM 4 top is shunted with a resistor ($R_{shunt}$) inside the high-definition current meter. Each line is connected to the detector through a decoupling resistor ($R_{dec}$). The signal from a calibration pulser is coupled via a capacitor ($C_{pulser}$) to the line for GEM 4 bottom. Individual loading resistors ($R_{load}$) are mounted on all segments on the top sides of the GEMs. Figure taken from [14].</figcaption></figure>

throughput of 3.28 TB/s to the 360 CRUs for TPC readout. In the CRU FPGA the data are corrected for the common-mode effect and ion tails are removed from the signals, before data reduction (zero suppression) is applied. Moreover, the signals are integrated for each channel over 1 ms, and these data are sent out separately as input to calculate three-dimensional space-charge maps for distortion correction. An overview over the correction of the TPC signals in the CRU and of the calibration of the TPC data is given in section 3.4.9.

The parameters for the front-end electronics system are summarized in table 8. With respect to the readout system utilized in Runs 1 and 2 [24], the new FEC has to meet two new requirements: continuous readout and negative input signal polarity. For the charge-sensitive amplifier (CSA), a saturation limit of 30 nA was required in order to accomodate the expected average rate of primary ionization clusters (up to about 3 nA per front-end channel) and in addition fluctuations due to the local track multiplicity. The conversion to digital values takes place with a gain of 20 mV/fC, at a sampling rate of 5 MSa/s, and with a precision of 10 bit.

The TPC FEC is shown in figure 52. It has a similar form factor as the one used in Runs 1 and 2. The 8-layer FEC PCB utilizes rigid-flex technology, where rigid and flexible substrates are laminated
<figure><img src="image_60.png" /><figcaption>**Figure 51.** Schematic view of the TPC readout system. Five SAMPA chips amplify, shape, and digitize the current signals picked up on the connected pads. Two GBTx ASICs multiplex the digitized data. GBTx 0 forwards the data from two and a half SAMPA chips to a VTRx. GBTx 1 forwards the data from the other two and a half SAMPAs to one VTTx module (two optical transmit channels). GBTx 0 also receives configuration data and the reference clock through the VTRx. The reference clock is distributed to the other components. A GBT-SCA chip is used for monitoring and configuration. Figure taken from [14].</figcaption></figure>

together into a single structure. The radiation-hard GBT link [34] system is used (see section 2.2) for data transfer and control. The clock for the digital circuitry is received from the CRU. The electrical links between GBTx and SAMPA use the SLVS standard and are operated at 160 Mb/s. The ADC sampling clock of 5 MHz is derived by division from the SLVS link clock speed inside the SAMPA chips. The monitoring of FEC operational parameters is based on the GBT-SCA 12-bit ADC and includes 14 measurements per FEC. FEC control is achieved via the GBT-SCA as well.

The SAMPA chips are operated in DAS mode, where the DSP is bypassed (see section 2.4). In this mode, the power consumption is 9 mW per channel, which adds up to 1.5 W for the whole FEC. Additional power is needed for the GBT components and for the voltage regulators. The total power consumption for the full FEC is about 9 W (56 mW per channel). The power is supplied using the same Low Voltage (LV) system from Runs 1 and 2 [24]. In particular, two low voltage channels

<table><caption>**Table 8.** Parameters of the upgraded front-end electronics. Table taken from [14].</caption><tr><td>Readout mode</td><td>continuous</td></tr><tr><td>Number of channels</td><td>524160</td></tr><tr><td>Number of FECs</td><td>3276</td></tr><tr><td>Signal polarity</td><td>negative</td></tr><tr><td>Average system noise (ENC)</td><td>670 e</td></tr><tr><td>Conversion gain</td><td>20 mV/fC</td></tr><tr><td>Dynamic range</td><td>100 fC (30 × MIP)</td></tr><tr><td>Peaking time</td><td>160 ns</td></tr><tr><td>CSA saturation limit</td><td>30 nA</td></tr><tr><td>ADC number of bits</td><td>10</td></tr><tr><td>ADC sampling rate</td><td>5 MSa/s</td></tr><tr><td>Power consumption (total)</td><td>56 mW per channel</td></tr></table>
<figure><img src="image_61.png" /><figcaption>**Figure 52.** Layout of the final TPC FEC PCB Rev. 1a. The components are mounted on both sides of the board. The figure shows the top side with five SAMPAs, two GBTx, one GBT-SCA, one VTRx, one VTTx and some other components. On the bottom side a few additional small components and the connectors to the detector are placed. Figure taken from [14].</figcaption></figure>

are used for each TPC sector (91 FECs) to supply the analog (2.25 V, 85 A) and digital (3.25 V, 185 A) power. Each FEC is surrounded by water-cooled copper envelopes. The heat transfer from the hottest components (the two GBTx ASICs, the five SAMPA ASICs and the voltage regulators) to the copper plates is optimized by the addition of flexible heat-transfer pads.

### 3.4.7 Installation

The upgrade of the TPC was carried out in a 15-month period during the Long Shutdown 2 of the LHC in a dedicated clean room on the surface at the site of ALICE at LHC Point 2. The procedure included the deinstallation of the old readout chambers and the installation of the new GEM detectors, the modification of the field cage, the installation of the new front-end electronics and services, and a series of basic functionality and performance tests.

After the end of Run 2, the TPC was disconnected in December 2018 and January 2019, and then moved from the experimental cavern to the surface in February and March 2019. It was installed in the clean room after removal of the old services (cables, pipes and hoses), front-end electronics and Service Support Wheels (SSW) [24], and after extensive cleaning. Initially, all MWPC ROCs were uninstalled on one side of the field cage, and the end plate was closed with aluminum panels. In a second step, the new GEM ROCs were installed. When all GEM chambers had been installed on the first side, the TPC was lifted and rotated by 180 degrees for chamber installation on the second side.
After completion of the ROC installation, the modified SSWs were installed on the two sides of the TPC. Each SSW supports the front-end electronics and related services (LV and fibers), the HV infrastructure (protection resistor boxes), the manifolds for the various circuits for cooling water, and the drift gas manifolds.

In a next step, the front-end electronics (3276 FECs) were installed and the corresponding services (power cables, fibers and cooling tubes) were connected. A first commissioning phase was then carried out for pairs of sectors in order to verify all chambers and the electronics. Various modes of data taking allowed for testing and improving the readout and reconstruction workflow. The acquired data were also used for calibration purposes and validation of the detector simulation. The data sample included pedestal, pulser and laser runs, as well as samples containing cosmic tracks and charge clusters from irradiation with an X-ray source. In August 2020, the TPC was transported back to the experimental cavern for installation into the ALICE magnet.

After installation in the central barrel of the ALICE experiment, the TPC was connected to its service infrastructure in the winter of 2020/21. The necessary connections include the hoses for the water cooling of the electronics and of the auxilliary systems, the LV cables, the HV cables, the fiber patch cords and a few additional cables (pulser and laser control).

### 3.4.8 Performance

After connection and verification of the services, the commissioning of the data processing chain, of the readout and reconstruction workflows and of the calibration procedures started. One first highlight were the pilot beams at low luminosity provided by the LHC in October 2021. Figure 53 shows an online plot from data recorded during this period. No track selection criteria and no calibration was applied in these data. The data come from the online quality control system and demonstrate the particle identification performance for tracks reconstructed online in the graphics processing units installed in the $O^2$ EPN servers (see section 5.3).

From summer 2022 the TPC was recording data at higher luminosities routinely. The data are affected by a baseline shift due to the common-mode effect. This effect is well known, and occurs in the ROCs due to capacitive coupling of the GEM 4 bottom electrode to the readout pads. In addition, during the analysis of the data collected during the commissioning phase, a characteristic tail was identified, which appears in particular for signals with large amplitudes. Simulations showed that part of the tail is induced by ions that are created just below the holes of GEM 4. Due to the local electric field configuration, these ions move fast enough to induce a signal on the pad plane. In addition, due to the rather high induction field applied for the TPC GEMs, amplification occurs in the full induction gap. The gain in the induction gap is very small, but nevertheless the produced ions contribute to the ion tail. A high-precision measurement of the ion tail (using overlay of many signals from laser tracks in the TPC) is shown in figure 54. Figure 55 visualizes the common-mode effect together with the effect of the ion tail on data collected by a single readout channel at high occupancy.

### 3.4.9 Calibration

In order to operate the detector, some basic calibration steps are necessary. The baseline (pedestal value) and noise of each electronics channel are extracted from the data collected in special pedestal calibration runs, where all filtering on the CRU is inactive. The mean of the baseline distribution defines the pedestal value, while the sigma corresponds to the noise of a given channel. The baseline
<figure><img src="image_62.png" /><figcaption>**Figure 53.** TPC $dE/dx$ as a function of momentum $p$. Online plot from quality control during pilot run with 900 GeV collisions in October 2021. No track selection criteria were applied. The magnetic field value was of 0.5 T.</figcaption></figure>

<figure><img src="image_63.png" /><figcaption>**Figure 54.** Measured shape of the ion tail in data recorded with laser tracks.</figcaption></figure>
<figure><img src="image_64.png" /><figcaption>**Figure 55.** Visualization of the ion tail and of the common-mode effect for one readout channel zoomed around the baseline region. The data are from a simulation with 30% pad occupancy and without noise from the electronics. The common-mode effect shifts the baseline to below zero. The ion tail is visible for signals with large amplitude. Both effects are corrected in the CRU FPGAs.</figcaption></figure>

values need to be uploaded to the logic in the CRU FPGAs in order to subtract them from the input signals. The thresholds for the zero suppression filter algorithm in the CRU are derived from the noise values (typically $3\sigma$).

The correction algorithm for the common-mode effect requires the upload of configuration parameters (one per channel) into the logic in the CRU FPGAs as well. The parameter is extracted from the data collected in special calibration pulser runs, where a pulser signal is injected into the HV line of each GEM 4 bottom electrode. It describes the local geometry (distance between pad plane surface and GEM 4 bottom electrode), which is influenced by sagging of the GEM foils.

The correction algorithm for the ion tail filter requires two configuration parameters for each channel, describing the shape of the tail and its amplitude relative to the pulse amplitude. These parameters are extracted for each pad from physics data acquired with beam.

On top of the basic calibrations, more complex calibration of the TPC data is needed. The drift velocity can be extracted from laser tracks that can be generated inside the drift volume of the TPC in special laser calibration runs or during physics runs. The gain can be extracted for each pad in special calibration runs where the radioactive decay of the $^{83}$Kr isotope is measured, or from analysing the tracks generated by particles in the physics runs. Different inputs may be used for the correction of the space-charge distortions.

* An interpolation method using external track references in ITS, TRD and TOF may be used. This method was extensively tested during Run 2, where some distortions due to imperfections were already present in certain regions.

* A reference average distortion map may be scaled with the actual luminosity of the interactions at the given moment for each time frame.
* The signals collected continuously in the TPC front-end electronics are integrated (1 ms integration time) for each channel inside the CRU and may be used for building a three-dimensional map of the space-charge distribution.

* Finally, the information from the high-definition current meters that sample the analog currents at all GEM 4 top electrodes for all GEM stacks may be used for building similar space-charge maps with lower granularity.

The latter two methods require as input the ion drift velocity at the given electric field strength.

In addition, static distortions play an important role. They are related to a small misalignment between readout chambers and central electrode, and to misalignment of the magnetic field and the drift field inside the field cage due to imperfections. The static distortions are constant in time for a given detector configuration.

A two-stage process (see section 5) has been implemented for the processing and calibration of physics data. The first stage is performed synchronously with the collection of the data, and focuses on cluster finding and the association of clusters to tracks. For this purpose, the mean space-charge distortions scaled with the current luminosity are used. The reconstructed tracks have sufficient precision to allow matching to the external detectors (ITS, TRD and TOF). The compressed data are written to permanent storage. The second reconstruction stage is performed on the compressed data in asynchronous mode. It aims at a further improvement of the data quality, in particular in terms of the space-charge distortion calibrations. It may employ a combination of the described methods, as well as other more refined calibration input.

## 3.5 Fast Interaction Trigger

The Fast Interaction Trigger (FIT) [35] serves as an interaction trigger, online and offline luminometer, initial indicator of the vertex position, and forward multiplicity counter. Offline analysis of FIT data provides the precise collision time for TOF-based particle identification, yields the collision centrality and the event plane orientation, and provides the main input for the measurement of cross sections of diffractive processes. The FIT consists of five distinct detector stations, positioned at different locations along the beam line. Three different detector technologies, as detailed below, are used. An illustration of FIT is shown in figure 56; the distance from the interaction point (IP) and pseudorapidity coverage of the different arrays are displayed in the inset table. The naming convention relates to the similar ALICE detectors used during Run 2. FT0 is the successor of T0 [36], which owes its name to the fact that it was used to provide a start time. FV0 is the successor of V0 [37], which provided the vertex location. Finally, FDD (Forward Diffractive Detector) is the successor of ALICE diffractive detector, AD, which detects charged particles at large pseudorapidity for the selection of diffractive and ultra-peripheral events. [38].

A new, fast electronics and readout system [39] that can handle the larger interaction rates in Runs 3 and 4 has been designed and implemented for all FIT subdetectors [40].

### 3.5.1 FT0

The FT0 consists of two arrays of quartz Cherenkov radiators, FT0-A and FT0-C, which are optically coupled to MicroChannel Plate-based photomultipliers (MCP). The FT0-A is located at 3.3 m from
<figure><img src="image_65.png" /><figcaption>**Figure 56.** View of the FIT detectors illustrating the relative sizes of each component. From left to right FDD-A, FT0-A, FV0, FT0-C, and FDD-C are shown. Note that FT0-A and FV0 have a common mechanical support. FT0-A is the small quadrangular structure in the centre of the large, circular FV0 support. Note that all detectors are planar with the exception of FT0-C, which has a concave shape centered on the IP. The inset table lists the distance from the interaction point and the pseudorapidity coverage for each component.</figcaption></figure>

the IP and comprises 24 MCPs and 96 quartz radiators. Due to the close proximity to the IP, the FT0-C support has a convex shape (as seen from the IP), positioning all 28 MCPs such that each of the 112 quartz radiators is at a distance of 84 cm from the nominal IP. The Photonis XP85002/FIT-Q MCPs are factory-customized versions of the Planacon XP85012. The customization is a new back-plane design for FT0 which groups the usual 64 anodes into four outputs, one for each of the four optically isolated quartz radiators, each with a thickness of 2 cm and an area of $2.65 \times 2.65 \text{ cm}^2$. This segmentation provides the granularity for measurements of multiplicity in central Pb-Pb collisions, while minimizing the dead areas due to MCP edges and the optical isolation of the radiators. In order to obtain the best possible timing resolution, the signal path from each MCP anode to the front-end electronics has the same length. The intrinsic time resolution of each quadrant is $\sigma_t \approx 13 \text{ ps}$ [41]. Accounting for signal deterioration along the 30 m long signal cables and processing by the front-end electronics, the achieved time resolution of FT0 is about 25 ps for a single minimum-ionising particle. Simulation studies of FT0 with the PYTHIA event generator [42] and the GEANT detector response simulation [43] indicate that the efficiency of the minimum bias trigger for pp collisions is $\ge 98\%$ for the OR of the two sides and $\ge 77\%$ for coincidences between FT0-A and FT0-C.

### 3.5.2 FV0

FV0 is a large, segmented scintillator disk with a novel light collection scheme [44], assuring short pulses, to achieve a single MIP time resolution of about 200 ps, and a very uniform response across the entire detection surface. The active element of FV0 is a 4 cm thick EJ-204 plastic scintillator divided into five concentric rings of equal pseudorapidity coverage. The outer diameter of the largest ring is 144 cm and the inner diameter of the smallest is 8 cm. The four inner rings are subdivided into eight sectors of 45 degrees each, while the outermost ring, due to its large area, has 16 sectors.
<figure><img src="image_66.png" /><figcaption>**Figure 57.** Photograph of one half of the FV0. The optical fibers connect the scintillators to the PMTs on the rim of the support structure, the black structure seen here. The center wall has been removed to show the scintillator, the surface matrix structure, and the optical fibers.</figcaption></figure>

A grid of equal-length, clear Ashai fibers is attached to the back side (as viewed from the IP) of the scintillator as can be seen in figure 57. At the other end, the fibers from each sector are bundled and optically coupled to Hamamatsu R5924-70 PMTs. This way, the 48 sectors of FV0 are mapped to 48 independent readout channels. This segmentation, combined with the information from the other forward detectors, is sufficient to yield the required centrality and event plane resolution. Together with FT0, FV0 provides the needed input to generate minimum bias and multiplicity triggers at the ‘minus one’ trigger level (LM). With a total latency below 425 ns, this is the fastest trigger in ALICE. In addition, the FV0 monitors the LHC background conditions and luminosity.

### 3.5.3 FDD

The FDD [45] comprises two nearly identical arrays, FDD-A and FDD-C, surrounding the beam pipe on opposite sides of the IP. Each array consists of eight rectangular scintillator pads with a size of $21.6 \times 18.1 \times 2.5 \text{ cm}^3$. These eight pads are assembled in two overlapping layers of four sectors each. To make clearance for the beam pipe, a quadrant was removed from the innermost corner of each scintillator plate. The radius of the removed quadrant is 6.2 cm on the FDD-A scintillators and 3.7 cm on the FDD-C, as illustrated in figure 56. Each pad has two wavelength shifting (WLS) bars attached to the opposite sides of the scintillator. Clear optical fibers carry the light from the WLS to H8409-70 PMTs. There are eight independent FDD channels on each side of the IP.

The FDD covers a large pseudorapidity interval (see table in figure 56) and is sensitive to the presence of even a single MIP. As such, it is an ideal system to tag interactions characterised by large rapidity gaps as those from photon-induced ultra-peripheral collisions or diffractive processes. The main physics goals to which the FDD contributes to the pp program are the studies of centrally produced exclusive states, measurements of cross sections for single and double diffraction, and inelastic processes. Regarding the physics objectives in Pb-Pb and p-Pb collisions, the FDD provides an independent measurement of centrality based on the charged-particle multiplicity in an intermediate pseudorapidity range between the ITS and the ZDC and contributes to the selection of ultra-peripheral collisions as well as their classification into exclusive or dissociated channels.

### 3.5.4 Electronics and readout scheme

All three subsystems of FIT use the same front-end and readout electronics based on just two custom-designed modules: a Processing Module (PM) and a Trigger and Clock Module (TCM). One PM provides twelve independent inputs. Each subdetector has only one TCM while the number of
<figure><img src="image_67.png" /><figcaption>**Figure 58.** Schematic diagram of the FIT readout electronics. The MicroChannel Plates (MCP) are described in the FT0 section.</figcaption></figure>

PMs is determined by the number of channels. Each PM is connected to the dedicated TCM via an HDMI cable to transmit “pre-trigger” data, slow-control data, and the LHC clock. The commands, configuration data, and status data are sent from the detector control system to the TCMs via a 1 Gb Ethernet optical link using an IPbus (UDP-based protocol) [39]. A schematic diagram of the FIT electronics using FT0 as an example, is shown in figure 58. The triggers and the measured event rates for the luminosity measurements are transmitted from the TCMs via the same connection. The PMs are configured from TCMs via an HDMI SPI connection. The PMs and TCMs are connected to the ALICE DAQ with GBT links. The FIT delivers the produced trigger signals to the central trigger system. Custom-made laser calibration systems provide pulses used for time and amplitude calibration, as well as monitoring of ageing and radiation damage of the FIT detector components.

The FIT detectors were installed in ALICE in 2021. Initial commissioning of the detectors was performed in October 2021 with low-intensity proton beams in the LHC at a collision energy of 450 GeV. These pp collisions were used to check both the integration of the FIT detectors in the ALICE data processing chain, and to get a first, preliminary look at FIT performance. We note that such low multiplicity collisions give only a lower bound on the performance of the FIT detectors, particularly on the time resolution of FT0. Using this data set, the time resolution of FT0 was found to be 26 ps. Further checks on this first data set are being performed, and full integration with the online systems and software framework is being completed at the time of writing.

## 3.6 Muon system

The forward muon arm was described in [1]. It consists of a composite absorber of about 10 interaction lengths, made from layers of both high- and low-Z materials located at a distance of 90 cm from the nominal interaction point, a large dipole magnet with a 3 Tm integrated field placed outside the L3 barrel magnet, ten planes of very thin, high granularity, cathode pad tracking stations. The muon arm is completed by a second muon filter (seven interaction lengths of iron) located after the last tracking station and upstream from four planes of resistive plate chambers which are used for muon identification. The spectrometer is shielded by a dense conical absorber tube, of about 60 cm outer diameter, which protects the chambers from secondary particles created in the beam pipe.
The increased luminosity of the LHC at the ALICE interaction point after LS2 required an upgrade of the front-end and readout electronics on both the muon tracking and muon identifier subsystems.

### 3.6.1 Muon tracking

The Muon Tracking Chambers (MCH) [1] consist of 156 multiwire proportional chambers with cathode pad readout (cathode pad chambers) with more than one million electronic channels. The system has five tracking stations, each of which is composed of two chambers. Because of the different sizes of the stations, ranging from a few square meters for station 1 to more than 30 m² for station 5, two different designs were adopted. The first two stations are based on a quadrant structure, with the readout electronics distributed on their surface (left panel of figure 59). Four independent quadrants form one chamber. For the larger stations (3 to 5), a slat architecture was chosen (right panel of figure 59). The largest slat size is 40 × 240 cm² and the electronics are mounted on the top and bottom parts of each slat. Slats are mounted on a support to form one half-chamber. One half-chamber consists of 9 slats for station 3, and 13 slats for stations 4 and 5. The tracking system covers a total area of about 100 m².

<figure><img src="image_68.png" /><figcaption>**Figure 59.** Left: station 2 of the tracking system; the readout electronics are distributed on the surface of a quadrant. Right: stations 4 and 5 of the tracking system; the readout electronics are mounted along the top and bottom edges of the slats.</figcaption></figure>

The detector chambers are unchanged from Runs 1 and 2, while the front-end and the readout electronics were upgraded to accommodate the larger interaction rates for Runs 3 and 4.

The electronics can run either in the default dead-time-free continuous mode or in triggered mode. The readout data flow is schematically shown in figure 60. The Front-End Cards (FEC) continuously send data at 80 Mbit/s through an electrical link to the SOLAR (Sampa to Optical Link for Alice Readout) readout boards which connect to the CRU (see section 2.2) through GBT optical links at 3.2 Gbit/s.

**The DualSAMPA front-end electronic cards.** The front-end electronic cards, called DualSAMPA, host two chained SAMPA chips (see section 2.4) of 32 channels each and three low voltage regulators. Since the detectors are the same ones used in Runs 1 and 2, the dimensions and the layout of the connectors for the DualSAMPA cards on the electronic PCBs remain the same as for the previous FEC. Moreover, two types of cards were produced, each with the same functionalities but with different dimensions to suit the quadrant and slat detector layouts. The DualSAMPA board is shown in figure 61).
<figure><img src="image_69.png" /><figcaption>**Figure 60.** The Muon Tracking readout scheme.</figcaption></figure>

<figure><img src="image_70.png" /><figcaption>**Figure 61.** The two geometries of the DualSAMPA boards (DS12 on the left and DS345 on the right), with the white connector plug socket on PCB and on the other side the black connector connecting to SOLAR boards.</figcaption></figure>

Out of the 19300 DualSAMPA produced (11000 DS345 for slats of stations 3, 4, and 5, and 8300 DS12 for quadrants of stations 1 and 2), 16900 are installed in the cavern (9700 DS345, 7200 DS12).

**The readout electronic FLEX links and large electronic PCBs.** The link between the Dual-SAMPA and the readout cards consists of a flexible circuit (FLEX) and a flat ribbon cable for the
<figure><img src="image_71.png" /><figcaption>**Figure 62.** Left: flex mounted on a slat connecting five DualSAMPA cards linking through a green flat ribbon cable to the readout board. Right: large electronic PCBs covering the surface of a quadrant.</figcaption></figure>

<figure><img src="image_72.png" /><figcaption>**Figure 63.** The FLEX scheme.</figcaption></figure>

slats, while a large electronic PCB and a flat ribbon cable are used for the quadrants (see left and right panels of figure 62).

Each DualSAMPA has dedicated data and clock lines while the trigger lines are daisy chained to feed up to 5 DualSAMPA (see figure 63) using an I2C line. An active buffer was added to the I2C line to ensure a good signal integrity.

More than 3000 FLEX PCBs of 24 different types were produced depending on the number of DualSAMPA to address, the geometry, and the pad density; 2760 of these were installed, the remainder serving as spares.

**The SOLAR readout cards.** Each FLEX/ribbon cable is plugged into one of the eight ports of a SOLAR readout board, allowing this latter to read out up to 40 DualSAMPA boards (see figure 64). The GBTx chip of the SOLAR board acts as a serializer to send the signals from the different DualSAMPA to the CRU through GBT optical links. The SOLAR board also hosts a GBT-SCA chip handling the eight I2C command and control lines, one optical transmitter/receiver VTRx and two DC/DC FEAST converters.

A total of 624 SOLAR boards are hosted in 112 custom SOLAR crates, with up to six boards each.

**The data flow from SAMPA to the CRU User Logic.** In the SAMPA chip, the signal of each electronic channel is amplified with a gain of 4 mV/fC, waveformed with a shaping time of 300 ns, then sampled and digitized at 10 MHz in a 10-bit ADC, and is eventually digitally processed with a
<figure><img src="image_73.png" /><figcaption>**Figure 64.** The SOLAR board: functional diagram (left panel) and photo of the board itself (right).</figcaption></figure>

<figure><img src="image_74.png" /></figure>

<figure><img src="image_75.png" /><figcaption>**Figure 65.** Data flow scheme.</figcaption></figure>

baseline correction and a zero-suppression before being formatted. The SAMPA format consists of data samples from a signal waveform with its time stamp and size together with a header containing mainly the bunch crossing number, the SAMPA address and the channel address of the SAMPA chip.

The signals of the 64 channels of the two chained SAMPA chips of a FEC are serialized at 80 Mbit/s (2 bits at 40 MHz). The first port of the SOLAR board handles the first 2 bits of the first DualSAMPA while the second port takes care of the 2 bits of the second DualSAMPA and so on, combining all 40 ports, which results in a 3.2 Gbit/s data optical transmission to one input of a CRU. The electrical and optical links are always transmitting data, independent of the type of information (physics data, synchronisation, etc.).

The MCH CRU user logic receives data from the 24 GBT links (see section 2.2), each one handling 40 DualSAMPA channels. For each GBT link, the user logic deserializes the 80 bits, forms the SAMPA words, removes the SYNCH words and inserts error checks and configuration conditions. These 64-bit SAMPA words contain the payload, the GBT link identifier, the DualSAMPA channel identifier, and error bits. The user logic then embeds the TTC signals into this stream, constructs the RDH (Readout Data Header) and transmits words of 256 bits to the Front Level Processor (FLP, see section 5.2) (see figures 65 and 66).

No specific processing is performed in the FLPs. The cluster finding, the cluster fitting and the track finding are done on the EPNs (see section 5.3).

Quality Control (QC) processes have two steps: the QC error check task is performed on the entire raw data at the FLP level, while the detector occupancy and pseudo-efficiency are monitored
<figure><img src="image_76.png" /><figcaption>Figure 66. CRU scheme.</figcaption></figure>

from decoded data samples in QC tasks on EPNs. While the detector occupancy QC uses digits (signal from each front-end electronic channel), the pseudo-efficiency task uses the pre-clusters (groups of pad hits that are close in time and space). The charge of the pre-clusters is also verified. These tasks will allow the monitoring of the detector performance.

### 3.6.2 Muon identifier

The Muon Identifier (MID) is the present designation of the Muon Trigger system [1], which was operational in ALICE during LHC Runs 1 and 2.

The detector is composed of 72 single gap Resistive Plate Chamber (RPC) detectors, organised in two stations of two planes each, located at a distance of 16 m and 17 m from the interaction point, respectively. In both stations the two planes are 17 cm apart. The total detection area is about $150 \text{ m}^2$. An overview picture of one half-plane of the MID, in open (maintenance) position, taken during the FEERIC card installation (see next section) in 2019, is shown in figure 67.

The RPC signals are collected by means of a total of 20992 readout strips, each of them connected to Front-End Electronics (FEE). The output signals from the FEE, in LVDS standard with a width of 25 ns, are propagated via multiwire copper cables to the local cards, which are part of the readout electronics.

The FEE cards, which are located on the RPC detectors, were replaced during LS2. The main motivation is to reduce the ageing of the RPCs and improve the rate capability during the upcoming
<figure><img src="image_77.png" /><figcaption>**Figure 67.** Overview of one MID half-plane in open position.</figcaption></figure>

data taking periods. The ASIC of the past FEE, called ADULT [46], was upgraded to a new type, called FEERIC [47, 48]. Unlike ADULT, FEERIC performs amplification of the RPC analog signals. Thanks to this upgrade, the ALICE RPCs can be operated at lower gain, with a reduction by a factor 3–5 of the charge produced in the gas gap, hence limiting ageing effects.

The readout electronics, composed of 234 local cards and 16 regional cards, was also completely replaced to sustain the larger data flow associated with the higher collision rate in Runs 3 and 4.

Although all RPC detectors were still operational at the end of Run 2, a few of them were drawing a relatively large current after having accumulated a charge up to 20 mC/cm² in the gas. It was therefore decided to replace those RPCs with completely new ones. For the longer term, a crucial R&D on new environment-friendly gas mixtures [49] for RPCs, based on tetrafluoropropene, which is characterised by a very low Global Warming Potential (GWP), has been launched.

**FEERIC electronics.** The FEERIC 8-channel ASIC is designed in the AMS 0.35 µm CMOS technology. Its main components are (see figure 68, top scheme) a transimpedance amplifier, a zero-crossing discriminator, and a one-shot circuit which inhibits retriggering during 100 ns. The operating threshold is typically 70 mV corresponding to a charge of approximately 130 fC at the readout strip level. Details of the performance of the FEERIC electronics are given in [50]. Figure 68, bottom panel, shows a picture of a FEERIC card. A total of 2720 cards (spare included) were produced in the second half of 2017. The installation of the FEERIC cards on the RPCs in the ALICE cavern was completed in July 2019.
<figure><img src="image_78.png" /><figcaption>**Figure 68.** FEERIC ASIC architecture (top) and FEERIC card picture (bottom).</figcaption></figure>

During Run 2, one of the 72 ALICE RPCs was equipped with FEERIC electronics and showed satisfactory performance and stability [48]. The charge released in the gas gap, around 30 pC per charged particle crossing the RPC at nominal high voltage, was typically four times smaller as compared to the one with ADULT.

A new wireless threshold distribution for the FEERIC cards was developed. A total of two masters (one on each side of the cavern) and 24 nodes close to the RPCs (see figure 69, right panel) were installed in the ALICE cavern in 2019 to remotely control the threshold of each of the 2384 installed FEERIC cards. The masters are controlled via ethernet and communicate via the high level ZIGBEE wireless protocol with the nodes, which are I2C chained to the FEERIC cards on the RPCs (see figure 69, left panel). A further upgrade of this system to a more powerful WiFi Ethernet-based system is planned for the winter shutdown of 2022. Both master and node share the same hardware and firmware. A card acts either as master or node, depending on the configuration stored in its EEPROM which also retains the memory of the last requested threshold values. The latter are restored at power on.

**Readout electronics.** The LVDS digital signals from the FEERIC electronics, so-called strip-patterns of 16 bit length (one bit corresponding to one RPC readout strip), are received by the local cards. Each local card receives the strip patterns corresponding to 16 horizontal and 16 (or 8 in some cases) vertical readout strips, on both sides of the same RPC, from each of the four detection
<figure><img src="image_79.png" /><figcaption>**Figure 69.** Wireless threshold distribution scheme (left) and master or node electronics card (right).</figcaption></figure>

planes. The vertical readout strips (maximum length 73 cm) cover the full RPC width while the horizontal strips (maximum length 55 cm) are segmented all along the RPC length. The details of each local card inputs are given in [51]. The entire setup consists of 234 local cards, housed in 16 VME-9U crates used as mechanical support and for power supply. The signals from up to 16 local cards are collected by a regional card via the e-links on the J2 bus in each crate. Each regional card is interfaced to a Common Readout Unit (CRU) by means of two GBT links at 3.2 Gb/s.

In total this project has two CRUs, housed in one single FLP desktop computer. The MID readout architecture is shown in the left panel of figure 70, while a picture of the three types of readout cards is shown in the right panel. Simulations of the expected bandwidth for Pb-Pb collisions at 50 kHz rate, based on Run 2 data, indicate that this design includes a safety factor of more than one order of magnitude.

Data corresponding to MID self-triggered physics events [52, 53] are transmitted from the local and regional cards to the CRU using the GBT up-links. Colliding beam particles in the LHC are of course the main source of such events. Every 25 ns (40 MHz) a new self-triggered event is potentially stored in the local and regional FIFOs. Only non-empty events are stored in these FIFOs. In the standard configuration a non-empty event corresponds to, at least, a non-zero strip pattern.

It is important to note that it takes five clock cycles at 40 MHz, per self-triggered event, for the transfer of the regional FIFO data and 9-21 clock cycles for the local ones, depending on the number of non-empty detector planes in this last case. This means that the data from different local and regional cards, corresponding to the same bunch crossing, arrive asynchronously in the CRU. This also means that the local and regional FIFOs saturate in case they are filled at the full clock frequency of 40 MHz. For instance, the FIFO saturation could happen in case of a very high level of noise at the FEE level. It should be noted that a busy bit would be set in such a case.

At the first stage of data processing in the CRU, the user logic performs zero-suppression and raw data header construction using the central trigger (CTP) orbit information. The output of the
<figure><img src="image_80.png" /><figcaption>**Figure 70.** MID readout architecture (left) and readout cards (right picture) with local (LOC) (top right), regional (REG) (top left) and J2 bus (bottom) between local and regional.</figcaption></figure>

user logic is transmitted by words of 256 bits to the FLP. At this level, the data coming from the different GBT links are assembled in C++ structures and synchronized to provide the information corresponding to a given bunch crossing. The local and regional cards always operate in continuous readout mode. However, the system can also run in triggered mode, with the CRU transmitting only data corresponding to a time window centred on a bunch crossing which coincides with a trigger from the CTP.

The local and regional cards respond also to all types of triggers delivered by the CTP and received via the GBT down-link [52].

The commissioning of the complete MID detection chain has started in the autumn of 2020. First muon tracks, in coincidence with MFT and MCH, have been registered in October 2021 by dumping proton beams in the TED, as explained in section 3.3.7.

## 3.7 Transition radiation detector

The construction, operation and performance of the TRD is presented in [54]. The TRD contributes to the overall momentum determination of charged particles, as it provides up to six track segments (tracklets, each of a geometric length of about 3.5 cm) for each charged particle in the acceptance ($|η| < 0.9$). In addition, the TRD allows to identify electrons via the detection of transition radiation. Using a likelihood method enhanced with machine learning techniques, it is possible to suppress pions by a factor of more than 100 while retaining an electron (positron) efficiency of 90%.

The TRD has the capability to trigger on events based on the charged particle content, incl. the identification of electrons, within about 8 µs after a collision. This feature was used in LHC Run 2 to select collisions with charmonia, jets or atomic nuclei. Here we focus on modifications implemented for the high rate running in LHC Runs 3 and 4.

### 3.7.1 High-voltage distribution and common mode

During TRD operation in Runs 1 and 2 a number of anode and drift channels of individual chambers developed high currents and were eventually not operational any more. Based on similar experience on the TPC, and on experience from the repair of one TRD supermodule (SM) during LS1, the
<figure><img src="image_81.png" /><figcaption>**Figure 71.** The status of TRD supermodules concerning capacitors in the high-voltage distribution.</figcaption></figure>

built-in decoupling capacitors in the on-detector high-voltage distribution system were suspected to cause the observed behaviour. At that time, the construction of the TRD was still ongoing, and the last four SMs were built without certain capacitors (4.7 nF) in the high-voltage distribution system. In total, until the end of Run 2, 70 anode channels and 20 drift channels were taken out of operation from a total of 522 chambers installed in 18 SMs.

The high-voltage distribution system with the decoupling capacitors on filter boards is mounted directly on each chamber and therefore encased in the hull of the SMs. Via milling cut-outs into the casing and by removing the top cover, it was possible to access the filter boards of all 30 chambers in a SM. Each anode and each drift channel hold a 4.7 nF capacitor; the anode wire plane is segmented in eight or six sectors of two pad rows each, decoupled from each other by a 2.2 nF capacitor. Measurements of capacitors that were removed confirmed the reason for the high-voltage failures, explaining the observed issues. Most of the problems could be traced to failing 4.7 nF capacitors, but it was found that also a small fraction (in the percent range) of the 2.2 nF capacitors had failed. Therefore, all capacitors on the filter boards were removed from a total of 9 TRD SMs. This number was determined by the turnaround time of SM deinstallation from the space frame of ALICE, repair, test and reinstallation during the first year of LS2. Before reinstallation of each SM, long-term high voltage, low voltage, cooling and readout tests were performed to ensure proper detector operation. It turned out that 96% (80 out of 83 not operational chambers) in the nine SMs could be restored. Figure 71 displays the configuration of the individual SMs in terms of installed decoupling capacitors. Based on experience, the expected failures of remaining capacitors until end of Run 4 is estimated to be low enough such that good tracking capability in all sectors is ensured for the entire period of operation.

As the capacitors were meant to buffer high charge deposits in the chambers, their removal results in larger induced common-mode signals on readout pads in the same high-voltage segment. The measured common-mode signal is shown in figure 72 and is about three times larger than with the capacitors in place, consistent with the expectation from the remaining capacitance of the readout chamber. This effect will be corrected at the software level based on the measured local charge deposit.
<figure><img src="image_82.png" /><figcaption>**Figure 72.** Induced common-mode signal with and without capacitors for the anode high-voltage. The baseline of pads in the same high-voltage segment as a cosmic-ray particle with an integrated signal between 10 000 and 12 500 ADC counts is shown before (red) and after (blue) the removal of the capacitors. For comparison, the baseline from pads in a high-voltage segment without hits is shown in green.</figcaption></figure>

### 3.7.2 Readout

The readout chain has been optimised in the past for a high event inspection rate at Level -1 (LM) with a fast calculation of the L1 trigger contribution (LM tracklet data readout time < 8 µs, L1 decision time < 6 µs), while transferring large, high resolution raw data for events accepted beyond the L1 level (L1 raw data readout time ≈ 300 µs) [54]. In Run 3, the L1 trigger functionality is no longer required and the detector must provide readout rates as high as feasible while writing all events to permanent storage. No data shall be discarded in the readout chain and the fraction of recorded events in 1 MHz interaction rate pp collisions or 50 kHz Pb-Pb collisions shall be maximised.

The applied solution is presented in the following sections. Simulations confirm that it enables collecting more than 70% of the events in a 50 kHz interaction rate Pb-Pb running scenario.

**Optimisation of the existing FEE.** In order to achieve a high event-readout rate in Run 3, only tracklets are read out, a mode which has been used to find fast L1 trigger contributions in Run 2. The maximum data volume per LM trigger and per Multi Chip Module (MCM, processing signals from 18 readout pads) is four words of 32 bits each. The usage of the available bits is no longer optimised for triggering, but for physics analysis.

Previously, each MCM processed and transmitted up to four tracklets, where each tracklet was transmitted as a 32-bit word. However, even in the most central Pb-Pb collisions, a track density of four tracklets per MCM has been rarely reached. Therefore, only three tracklets per MCM are allowed in the Run 3 data format. The estimated fraction of tracklets lost by this measure in central Pb-Pb events is below 1%. The freed-up 32 bit word is used as a header to store position information about the MCM and eight bits per tracklet are reserved for PID information. It is followed by one to three 32-bit tracklet words that store the position within the MCM, slope and additional twelve bits of PID information of the tracklet. The details are shown in table 9.
<table><caption>**Table 9.** TRD tracklet data format. Each MCM that has reconstructed at least one tracklet will send a header with shared coordinate information and eight bits of PID information per tracklet. For each reconstructed tracklet, one additional payload word with additional position and PID information, as well as the reconstructed tracklet angle (slope), will be stored.</caption><thead><tr><th></th><th>31</th><th>30</th><th>27</th><th>26</th><th>25</th><th>24</th><th>17</th><th>16</th><th>9</th><th>8</th><th>1</th><th>0</th></tr></thead><tbody><tr><th>Header</th><td>1</td><td>padrow</td><td>col</td><td colspan="2">HPID2</td><td colspan="2">HPID1</td><td colspan="2">HPID0</td><td colspan="2"></td><td>1</td></tr><tr><th>Payload (1-3x)</th><td colspan="4">position</td><td colspan="2">LPID</td><td colspan="2">slope</td><td colspan="2"></td><td>0</td></tr></tbody></table>

The PID information per reconstructed tracklet will increase from eight to 20 bits, which will be used to store charge information from three time slices with six or seven bit dynamic range each. Simulations have shown that the expected performance with this data format is similar to an offline analysis with the same number of time slices. The tracklet position and slope will also be stored with higher precision than in previous runs.

In Run 3, the TRD uses a physics trigger sent by the CTP at LM latency (575 ns, see section 5.5). In addition, the TRD supports a new trigger type, called calibration trigger. The calibration trigger, also sent at LM latency, enables the shipping of tracklet data and, additionally, the full raw data. This allows to trigger a full readout for a small fraction of events, facilitating detector calibration. Apart from that, the calibration trigger is interpreted by the FEE as a command to reload its configuration parameters from hamming protected memory areas. This is a precaution measure and mitigates the impact of Single Event Upsets (SEUs) on data taking, sporadically observed on some isolated half chambers as Link Monitor Errors (LMEs). An LME of a particular half chamber occurs whenever the data sent by the half chamber cannot be correlated with the corresponding triggers.

**Common Readout Unit (CRU).** For Run 3, the Global Tracking Units used previously [54] are replaced by CRUs (see section 2.2). The CRUs receive the data directly from the FEE via 1044 custom optical links based on 8-bit/10-bit encoding. Every CRU provides 30 link inputs, implying that in total 36 CRUs are in use (two per TRD SM). They are housed in twelve First Level Processors (FLPs).

The FPGA firmware on the CRU is composed of a common logic, and a TRD-specific user logic. It controls the readout process of the detector and receives, buffers and formats the data for the $O^2$ system. All CRUs are connected to the LTU to receive trigger information and to signal a detector busy status to the CTP (see section 2.1). Each CRU determines an individual busy status contribution depending on the status of the readout of the connected FEE links. The CTP combines the busy status contributions from all CRUs in order to determine a global busy status of the detector.

Before being written to permanent storage, the data are reformatted and compressed, optionally either on the FLPs or EPNs (see section 5.2 and 5.3). The following points describe sequentially the process of acquiring an event, explaining the role of the CRU and the interactions with other readout components:

1. The Central Trigger Processor (CTP) sends a trigger at LM latency (physics or calibration) via the Local Trigger Unit (LTU) to the FEE and to the CRUs in parallel. The trigger to the FEE is shipped via a legacy Timing, Trigger and Control (TTC) [4] network. The trigger to the CRU is sent via trigger distribution networks, using the new Trigger and Timing Control via
TTC-PON technology. Nine networks are necessary to achieve the minimum latency (see section 5.5). The CRUs store all information from the received trigger message (e.g. orbit and bunch crossing id) in internal buffers.

2. Upon the arrival of the trigger, the FEE begins recording the data, while primary charge drifts towards the anode region. Each CRU receives the trigger at approximately the same time and internally opens a time window to wait for the input links to send all the acquired data. The timeout is programmable. In addition, each CRU generates its busy status contribution and sends it to the CTP. The TTC-PON upstream communication feature is used to transmit the busy status signal. This prevents the CTP from sending any other trigger as long as any CRU contributes an active busy signal in order to avoid confusion of the FEE state machines.

3. When the FEE has acquired and processed the data, it starts shipping them via the optical links. At the end of the transmission, the FEE appends specific end markers. The CRUs record the data received on all input links. In case no data end marker is recognised by the CRU within the programmable timeout or data words are received outside the data expectation window, the CRU marks the concerned link as erroneous (LME) and excludes it from data taking until a manual or automated recovery takes place. The CRU stores all received data in large internal data buffers with size sufficient to hold entire calibration data events at maximum multiplicity. When the CRU has confirmed the reception of end markers on all active links, or the timeouts have been reached, the CRU releases its busy status contribution. The CTP considers the detector as busy until all 36 CRUs have released their busy contribution.

4. Once the detector side of the event acquisition is finalised, and the data are stored in internal buffers, the CRU is ready to acquire the next event. The buffered data are reformatted and shipped to the readout system in parallel. The CRU packs the data into packets of a maximum size of 8 kB and equips these packets with Raw Data Headers (RDHs). In addition, TRD-specific headers are inserted into the data stream. The headers contain various information, in particular the trigger timestamp information needed in order to link the acquired data to other detector data during the reconstruction.

### 3.7.3 Detector control

A special feature of the upgraded TRD DCS system is that the readout chain status of all half chambers is made available to the DCS system by the CRU. The CRU firmware contains a dedicated error state machine for all half chambers. If a connected half chamber shows a misbehavior that can be detected at the CRU level, the corresponding state machine enters an error state. This error state is stored in a dedicated CRU register, which is read by the DCS system via the ALFRED [55] system (section 5.6.2). The obtained status of all half chambers is displayed on a dedicated DCS panel in order to monitor LMEs.

### 3.7.4 Standalone tracking

A standalone tracking algorithm for the TRD was implemented using a Kalman filter approach. The seeding uses the direction and position information of all pairs of TRD tracklets. The track reconstruction efficiency and transverse momentum resolution was determined by matching tracklets
<figure><img src="image_83.png" /><figcaption>**Figure 73.** Left: $\Delta\alpha$ versus impact angle for a typical TRD chamber in Run 2, having a fixed uncalibrated drift velocity. The quoted values refer to the Run 2 calibration procedure (upper row) and to the new calibration scheme (lower row). Right: average $\Delta\alpha$ versus impact angle for all TRD chambers after the calibration was applied. The red band shows the RMS of the distribution.</figcaption></figure>

to tracks reconstructed by the TPC. For the TRD standalone tracking, a momentum resolution of about 9% for 500 MeV/c particles was achieved for the case of six tracklets in the fit. By including the primary vertex information as an additional constraint, a momentum resolution better than 4% was achieved. The TRD standalone tracking algorithm was used to identify and study photon conversions and nuclear interactions in front of and within the TRD. It will also be used for the TRD drift velocity calibration in Run 3.

### 3.7.5 Calibration

The Run 3 TRD calibration procedure is similar to the one employed before, except for the drift velocity calibration, which is based on a new development. The angle between a TRD tracklet and the corresponding TRD track, $\Delta\alpha$, is measured as a function of the track impact angle for each chamber. A model with two free parameters, the effective drift velocity $v_D^{\text{eff}}$ and the Lorentz angle $\alpha_L$ (the angle between the velocity of drifting electrons and the drift field), is used to fit the distributions. A typical example is depicted in figure 73 (left). The effective drift velocity is compensating the ion tail effect which is systematically changing the tracklet angle. The physical true drift velocity $v_D^{\text{true}}$ is about 35% larger than $v_D^{\text{eff}}$. A closure test with $5 \times 10^4$ events using Run 2 data demonstrates that the average angular difference between tracklets and TRD track is zero, as shown in figure 73 (right).

About $4 \times 10^5$ minimum bias pp-equivalent events are needed for an update of the calibration parameters. This is similar to what was used in Run 2 with about 600 to 3000 tracklets per chamber. The seeding and Kalman filter procedures need on average 10 ms per p-Pb event. In total, not more than 20 minutes for one update of the calibration parameters is needed on a single CPU core.

### 3.7.6 Quality Control

The QC system consists of tasks that are running in various parts of the $O^2$ system and produce QC objects, mostly in the form of histograms. The following items are controlled:
* The data arriving from the FEE via the CRU are validated, allowing to detect disabled or malfunctioning parts in the readout tree or SEUs in the FEE.

* Zero-suppressed ADC data from all calibration events are analyzed to reconstruct the average, time-dependent signal shape for each of the 522 readout chambers. These histograms are versatile low-level monitoring tools for many aspects of the operation of the TRD, including trigger timing, drift velocity and gas gain.

* Tracklets from a small fraction of events are used to monitor the local reconstruction of track segments in the FEE of each chamber.

* The tracking QC monitors the efficiency of the synchronous and asynchronous reconstruction algorithms at the tracklet and track level.

* Residuals between reconstructed tracks and tracklets are analyzed in the asynchronous stage to monitor the impact of alignment and calibration on the detector performance.

The data from these QC tasks are further processed by checker algorithms to provide automated notifications and trending.

In Run 3, the upgraded TRD system successfully recorded calibration data (for gain uniformity correction) with a ⁸³Kr source in standalone mode, and collision data with the whole ALICE setup.

## 3.8 Time-of-Flight detector

The ALICE Time-Of-Flight (TOF) detector [56, 57] is a large array of Multi-gap Resistive-Plate Chamber (MRPC) strip detectors, where each strip is read out by 96 pads each with 2.5 × 3.5 cm² area. Groups of 91 strips are organized in supermodules, covering the 18 sectors of the ALICE spaceframe. Each of the supermodules is read out by four custom VME crates, each hosting nine or ten Time-to-digital-converter Readout Module (TRM) boards, one Data Readout Module (DRM) card and one Local Trigger Module (LTM). While the DRM acts as master and has interfaces with the central systems, the LTM elaborates trigger information and sets the threshold on the NINO ASIC chips hosted on the front-end cards.

The TOF upgrade for Run 3 mostly concerns part of its readout electronics, to accomplish continuous readout, aligning with the ITS and the TPC, and with the aim to exploit at maximum its particle identification discriminating power in the intermediate momentum range. The intervention needed to adapt to a continuous readout was relatively limited thanks to the very small intrinsic dead time (~10 ns) of the MRPC detector and its front-end electronics and the fact that the High Performance TDC (HPTDC) has on-board buffering resources for digitized data, as detailed in the next sub-section.

### 3.8.1 Implementation of continuous readout

The TRM cards are equipped with 30 HPTDCs operated in very high resolution mode, with 24.4 ps bin width. The specifications of the HPTDC (and its performance once integrated in the TRM cards) are detailed elsewhere [58], but it is important to recall here its trigger matching function. Based on time tags, the HPTDC allows the trigger latency to be programmable over a large dynamic range and also supports overlapping triggers, where individual hits may be assigned to multiple events. Once a trigger
<figure><img src="image_84.png" /><figcaption>**Figure 74.** (left) HPTDC programming in Run 1 and 2 operations (top arrow) and in Run 3 (bottom arrow). The three trigger levels L0, L1 and L2a are replaced by a periodic trigger with a given frequency, mimicking a continuous readout. All hits (black lines) are read out and can be associated to physical events at a later stage. (right) Possible selection of parameters (fixed trigger frequency $f_T$ and matching window width $m_w$) to realize a continuous readout. The green circle corresponds to the chosen point of operations.</figcaption></figure>

is received, only stored hits starting from a given time and for a limited matching window are moved to the readout FIFO and made ready for further stages of readout. During Runs 1 and 2, with a limited high-rate capacity in the barrel detectors of ALICE, the trigger was limited to a few kHz. In this situation, the internal HPTDC buffers for the TOF were configured with a latency window of 6500 ns (corresponding to the latency of the triggers reaching the TOF crates) and with a matching window of 600 ns, to comfortably collect all hits registered in the TOF detector associated to the triggered collision.

In this configuration, continuous readout may be achieved by applying a strictly periodic trigger with frequency $f_T$ and matching window $m_w = 1/f_T$. Figure 74 (left) illustrates the underlying idea. Delivering a trigger with a constant 50 kHz frequency, and setting latency and matching windows of 20 µs, all hits are readout. Figure 74 (right) shows the curve of allowed values, together with the limitations of the system. On the one hand, the latency window cannot be set at a value larger than half of an LHC orbit. On the other hand, as discussed in the ALICE Readout Upgrade TDR [59], the trigger frequency cannot be too high, given the time spent reading the HPTDC chains in the TRM cards (two HPTDC chains of 15 chips) with a fixed readout deadtime of 3.2 µs for token-passing operations among chips alone. More generally, the readout time on average has to be less than $1/f_T$. Considering also the readout time over the VME backplane (up to 10 TRMs per crate have to be read) an optimal operation point was found with $f_T = 33$ kHz. The procedure was verified in a test system, sending random hits to several TRM cards, programmed with appropriate latency and matching windows (29 800 ns). The periodic triggers, hereafter labelled as TOF special triggers (TT), were delivered at fixed bunch crossing. The orbit is split in three parts with TT occurring at BC numbers 51, 1177, and 2673. Given the flat distribution hits over the LHC orbit, figure 75 shows that no hits were lost.

### 3.8.2 The new Data Readout Module (DRM2)

In order to keep up with the planned increase of luminosity and of the interaction rate (up to 1 MHz in pp collisions and 50 kHz in Pb-Pb collisions), a new Digital Readout Module 2 (DRM2), was designed [60]. With respect to the existing DRM module (hereafter DRM1) it has a more modern