# Low inductance power module optimized for Flying Capacitor Topology

Philippe Lasserre, Cyrille Duchesne, Anusha Gopishetti

► To cite this version:

Philippe Lasserre, Cyrille Duchesne, Anusha Gopishetti. Low inductance power module optimized for Flying Capacitor Topology. The 26th European Conference on Power Electronics and Applications, GDR SEEDS France & EPE Association, Mar 2025, Paris, France. 10.34746/epe2025-0029. hal-05074051

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Submitted on 19 May 2025

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# Low inductance power module optimized for Flying Capacitor Topology

Philippe LASSERRE(a), Cyrille DUCHESNE(a), Anusha GOPISHETTI(a)

(a) DEEP CONCEPT

Hélioparc 2 Avenue Pierre Angot, 64053 PAU, FRANCE

Tel.: +33 / (0) - 6 75 13 10 00

E-Mail: philippe.lasserre@deepconcept.fr

URL: www.deepconcept.fr

## Keywords

«Packaging», «Power module», «Optimization»,
«Silicon Carbide».

## Abstract

In Renewable Energy domain, power converter require adapted solutions to increase electrothermal performances. In this paper, a high-performance packaging architecture is proposed, dedicated to a flying capacitor topology. Based on 750V SiC bare dies, interconnection technologies, materials and optimized design was established to obtain a dedicated power module, with the support of finite element modeling. A specific assembly process was developed with innovative tooling and was tested at the end of process by electrical static tests and Xray analysis. Power electrical performances was measured by double pulse test method. Electrical characterization and module simulation recovered the value of inductance close to 6nH. Next step is to evaluate the robustness of this new power module with campaigns of passive temperature cycling and power cycling to be performed.

## I- Introduction

In Renewable Energy activities, solutions for managing and optimizing energy systems require innovations in all elementary bricks, from the semiconductor to the automaton logic. As part of the development of its offering dedicated to micro-grids, our partner wishes to develop a 50kW inverter meeting certain specifications, particularly in terms of input voltage range and functionalities. This converter should be able to be used to interface several sources and loads within microgrids. As a result, it is capable of exchanging energy between a three-phase AC grid, or a DC grid, and a battery. For this specific converter, the necessity to create a new custom

power module came with the use of 750V SiC MOSFET and an optimization of the design to be compliant with the topology chosen, as nothing commercial exactly exists. Power converters play a crucial role in converting and controlling the energy generated from renewables. However, the performance of these converters is often limited by their electrothermal characteristics, necessitating the development of advanced solutions to enhance their performance and reliability [1], [2]. Recent advancements in semiconductor technology highlight SiC devices for superior electrical properties, enhancing power converters' efficiency, and thermal management. SiC's better thermal conductivity makes it ideal for high-performance power modules, especially in renewable energy applications [3].

This paper presents a high-performance packaging architecture for a flying capacitor topology using 750V SiC bare dies and advanced interconnection technologies. The design was optimized with Finite Element Modeling (FEM) for improved electrothermal performance. A specific assembly process incorporating innovative tooling was developed and validated through extensive testing. These tests include electrical static tests and X-ray analysis, ensuring the modules integrity and performance.

The power modules' electrical performance was assessed using double pulse test method, electrical characterization reveal an inductance value close to 6nH, demonstrating minimal parasitic inductance.

## II- Module design

In this section some details of the design will be developed, with the optimization of shapes and materials. It is assumed to not give the exact intern layout and dimensions to save some knowhow of DEEP Concept team.
## A. Specification - Context

With another partner of the project, SIREPE (www.sirepe.fr) in charge of power electronic architecture, the best topology for the converter was chosen, according to using profile and final user needs. This topology of Flying capacitor (Fig. 1) enable to use lower breakdown voltage than total bus voltage of the application (800V<sub>DC</sub>).

<figure><img src="image_2.png" /><figcaption>Fig. 1: Power module topology</figcaption></figure>

With this topology, each chip must see only $V_{bus}/2 = 400V$ (except switching overvoltage). The perimeter of the power module is marked in blue dotted lines. The $C_{DC}$ and $C_F$ capacities will be assembled to the module via a power PCB, external to the module.

The objective of designing a specific power module dedicated to Flying Capacitor technology allows to optimize power and signal layouts instead of using two typical Half Bridge modules in series, without any integration. At the start of the project, we didn't find any commercial power module dedicated to this topology, in the good range of current and voltage.

Optimum switching frequency and a special attention to obtain a high level of electric yield lead us to use Silicon Carbide (SiC) MOSFET devices.

According to the state of the art in terms of available SiC bare die devices, we decided to use two MOSFETs in parallel per switch, with reference G3R10MT07 from Navitas-GeneSiC,

and one free wheel diode GD30MPS12 from Navitas-GeneSiC also.

## B. Module Architecture Design

The design is performed with Solid Edge ST software, to ensure all 3 dimension shapes, useful for simulations detailed in the next paragraph. The substrate is a typical DBC (Direct Bonded Copper), with a 0.635µm AlN ceramic and 0.300µm for copper. The layout and power terminal shapes are optimized to minimize specific loop inductances. We have here to consider one loop with $C_{DC}-SW1-C_F-SW4$ (Loop1) and another with $C_F-SW2-SW3$ (Loop2). For the top surface interconnection technology, we decided to use soldered copper clips as seen in Fig. 2. For that, we chose a golden top metallization for power chips, to avoid typical aluminum material not compatible with soldering process.

The reliability of this technology will be studied in the next ageing test campaigns.

<figure><img src="image_3.png" /><figcaption>Fig. 2: 3D model of final design of the module</figcaption></figure>

All gate-source signals and temperature sensor are connected to an internal PCB (Fig. 3), with an optimized layout to avoid imbalances during switching modes.

<figure><img src="image_4.png" /><figcaption>Fig. 3: Final design of the module with PCB</figcaption></figure>
Power terminals are specific copper sheet metals with busbar effect for loop inductance minimization.

Finally, the housing will be ensured by a custom plastic part (Fig. 4), made by additive manufacturing, in cDLM printing technology for this first step of the project. For more industrial projection, this plastic part will be manufacture by typical molding technology.

<figure><img src="image_5.png" /><figcaption>Fig. 4: Final design of the module</figcaption></figure>

Final dimensions of the power module are 62mm × 57mm × 11mm, with a bottom cooling surface of 47mm × 42mm, and a total volume of 38.9 cm³.

### C. Module Simulation

During the design phase, simulations have been done to optimize the layout of the DBC and the shape of conductive parts, thanks to ANSYS Multiphysics suite.

As an example, on Fig. 5, you can see the specific shape of power terminals to ensure a good mutual inductance for the current loop concerned.

<figure><img src="image_6.png" /><figcaption>Fig. 5: Mutual inductance effect</figcaption></figure>

At the end of the design, we managed to obtain a value of 7.5nH (Loop1) and 4nH (Loop 2) for DC analysis. At 40 MHz, the inductance values obtained are 6.53nH (Loop1) and 3.45nH (Loop2). On Characterization section, we describe an experimental test to measure these loop inductances with precision.

## III- Module manufacturing

The first steps of manufacturing will be performed in an ISO7 cleanroom. All equipment used are industrial ones, dedicated to micro and mini-series of power modules. All polymer steps (gluing, dielectric gel) take place in a specific silicone area.

### A. Fabrication Flow development

The flowchart process is described in the Table I below. All materials are ROHS compliant. The process is established with the idea to be possible to separate all materials at the end of life of the product. Parallel studies of this project are dedicated to the replacement of certain materials or process technology to optimize this recyclability.

<table><caption>Table I: Flowchart process</caption><thead><tr><td>Steps</td><td>Components materials Consumables</td><td>Equipment</td></tr></thead><tbody><tr><td>Die attach</td><td>MOS & diodes DBC substrate SAC305 preforms</td><td>SST 3130</td></tr><tr><td>Complements</td><td>Clips, pins, terminals, PCB, SAC305 solder paste</td><td>SIKAMA Falcon5</td></tr><tr><td>Cleaning</td><td>Loctite 7053</td><td>US bath</td></tr><tr><td>Gate/source connection</td><td>Ø200µm aluminum wire</td><td>TPT HB30</td></tr><tr><td>Housing assembly</td><td>Plastic housing, Elastosil N9111 Silicone glue</td><td>manual dispensing</td></tr><tr><td>Insulating</td><td>TSE 3062</td><td>Manual filling</td></tr></tbody></table>

### B. Module assembly and evaluation

Bare dies are soldered with a typical Sn3Ag0.5Cu alloy, in preform format, in a static reflow furnace
with H₂/N₂ gases and vacuum [4]. A mask is used for a good positioning of chips.

Then other parts are assembled with solder paste: terminals, pins, PCB, thermal sensor. A specific tooling was created to adjust all positions of individual parts (Fig. 6).

<figure><img src="image_7.png" /><figcaption>Fig. 6: Process tooling</figcaption></figure>

The process of housing assembly needs a specific silicon glue (Elastosil N9111) to ensure the mechanical maintain of the plastic part on the DBC substrate and avoid any eventual leakage for the following step of filling the insulating silicone gel. This gel (Room Temperature Vitrification) is poured into the module by some holes under bolts. And then power terminals are bent to finalize the assembly. Some quantity of these final modules are shown in Fig. 7.

<figure><img src="image_8.png" /><figcaption>Fig. 7: Some quantity of manufactured modules</figcaption></figure>

At this step, the module is ready for the final static electrical test.

We use a component analyzer B1505A from Keysight for a 100% functioning test. $I_d-V_{ds}$ (Fig. 8), $V_{th}$ and $V_{br}$ are registered to evaluate the

main characteristics of the module. Typical value for $R_{DSon}$ (@$V_{GS}$=15V) is 5.8mΩ.

<figure><img src="image_9.png" /><figcaption>Fig. 8: typical output characteristic @25°C</figcaption></figure>

Additionally to these static electrical tests, Xray analysis was performed to check soldered interface quality (Fig. 9).

<figure><img src="image_10.png" /><figcaption>Fig. 9: Xray analysis of one chip after soldering</figcaption></figure>

Reflow process has been reviewed to obtain a void percentage lower than 5%, by the adjustment of vacuum and gazes sequences and a pre-heat phase.

## IV- Characterization

The first characterization developed below is power electrical characterization, with the double pulse test method. The second part presented here is an experimental measurement of stray inductances to correlate simulation models.

### A. Double pulse tests

The objective of these tests is to define the energy losses, to ensure that the overvoltage / overcurrent are consistent during switching (boosting and blocking) of the power converter (MOSFET and diode) within the defined operating range by the
project specifications. Fig. 10, presents the experimental setup of these tests.

<figure><img src="image_11.png" /></figure>

<figure><img src="image_12.png" /><figcaption>Fig. 10: Experimental setup</figcaption></figure>

Fig. 11 below, is an example of switching, on the high side MOSFET of the Loop2 at 300V-200A, first during turn off, then during turn on.

<figure><img src="image_13.png" /><figcaption>Fig. 11: Switching curves</figcaption></figure>

Losses have been evaluated for several configurations. As an example, Fig. 12 shows switching losses for the Loop2. It validated our hypothesis during the Dimensioning and Design phase of the project.

We can see that during conduction and blocking, the Loop1 has more losses than the Loop2. For the opposite diode it is the reverse: the Loop2 has more losses than the Loop1.

Globally, switching losses are low, less than 2mJ. During our tests we were able to note a maximum overvoltage of 295V and an overcurrent of 150A. The max dV/dt is 21kV/µs for the MOSFET and 50kV/µs for the diode. Maximum dI/dt is 9kA/µs.

<figure><img src="image_14.png" /><figcaption>Fig. 12: Switching losses (Loop2), MOSFET</figcaption></figure>

Thanks to all these characterizations, a preliminary datasheet [5] was established, recovering the main dimensioning values in terms of electrical characteristics, mechanical mounting data, and detailed pinout.

<figure><img src="image_15.png" /><figcaption>Fig. 13: preliminary datasheet of the module</figcaption></figure>
## B. Stray inductance measurement

The experimental evaluation of inductance values obtained from simulation is performed in this section. As presented in [6], the characterization method based on Impedance Analyzer is performed. For this characterization method, the power module is fabricated without semiconductor chips and conductive paths of the loop is formed using soldered copper clips.

The test utilizes an E4990A impedance analyzer equipped with a 42941A test fixture, known as the Impedance probe (shown in Fig. 14). This kit enables in-circuit measurements with enhanced accuracy and a broad impedance coverage range up to 120 MHz [7].

<figure><img src="image_16.png" /><figcaption>Fig. 14: Measurement setup – Impedance Analyzer</figcaption></figure>

As mentioned in [6], the device's influence to the measured impedance value are rarely negligible. Therefore, a calibration procedure is conducted to measure and compensate for the device's impedance prior to any actual measurements. Following which, it is recommended to perform short, open, and load calibration [8]. The jaw width of the impedance probe is maintained fixed throughout the test process (i.e., for calibration and measurement steps).

For the measurements, the average factor is set to 8, meaning that 8 measurements are performed with sweeping points of 201 and average value of these measurements is measured. This settings improve the accuracy and stability of the measurement by reducing the impact of noise and fluctuations. The measurements are performed for each loop.

<figure><img src="image_17.png" /><figcaption>Fig. 15: Inductance measurement using impedance analyzer</figcaption></figure>

The inductance values measured using impedance analyzer are presented in Fig. 15. At 40 MHz, the values measured from experimental setup are 6.26 nH and 3.88 nH for Loop1 and Loop2, respectively. These values obtained from experimental setup for Loop1 and Loop2 are in good agreement with the simulation results at 40 MHz, i.e., 6.53 nH and 3.45 nH respectively.

## V- Conclusion

The originality to have a power module dedicated to Flying capacitor topology for Renewable Energy domain was presented.

A 750V/200A SiC power module using the proposed high-performance module packaging architecture and developed fabrication solutions is prototyped and validated, with major static and dynamic characteristics extracted and presented in this work. Low inductance, i.e., 6.53nH (Loop1) and 3.45nH (Loop 2), is achieved in the final module with the dimension of 62 mm × 57 mm × 11 mm and is validated from experimental measurements (i.e., 6.26nH and 3.88nH for Loop1 and Loop2, respectively).

Through the experimental studies, the proposed module structure has been demonstrated to be a promising packaging solution to better exploit the advantages offered by high-speed 750V SiC devices. For this range of voltage, there is a competition between SiC and GaN (Gallium Nitride) technologies. And a comparison will be possible in the next months to extract the main advantages and inconveniences.
VI- References

[1]. J. M. Carrasco et al., "Power-Electronic Systems for the Grid Integration of Renewable Energy Sources: A Survey," in *IEEE Transactions on Industrial Electronics*, vol. 53, no. 4, pp. 1002-1016, June 2006, doi: 10.1109/TIE.2006.878356.

[2]. S. Yang, A. Bryant, P. Mawby, D. Xiang, L. Ran and P. Tavner, "An Industry-Based Survey of Reliability in Power Electronic Converters," in *IEEE Transactions on Industry Applications*, vol. 47, no. 3, pp. 1441-1451, May-June 2011, doi: 10.1109/TIA.2011.2124436.

[3]. Baliga, B. J. (2010). *Fundamentals of power semiconductor devices*. Springer Science & Business Media.

[4]. Chen Y.: 3.3 kV Low-Inductance Full SiC Power Module, APEC 2023

[5]. Datasheet of DC3NFC750-1 Power Module

[6]. O. Sanjakdar, L. G. Alves Rodrigues and Y. Avenas, "Towards a Modular Multilevel Flying Capacitor Module using SiC MOSFETs," PCIM Europe 2023; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, Nuremberg, Germany, 2023, pp. 1-8, doi: 10.30420/566091009.

[7]. E4990A Impedance Analyzer | Keysight

[8]. B. W. Nelson, A. N. Lemmon, B. T. DeBoi and T. J. Freeborn, "Modeling and Validation of Fixture-Induced Error for Impedance Measurements," in *IEEE Transactions on Instrumentation and Measurement*, vol. 68, no. 1, pp. 129-137, Jan. 2019, doi: 10.1109/TIM.2018.2838858.