# Two copper layer Insulated Metal Substrate PCB potential using Wide-Bandgap semiconductors

Macià Capó-Lliteras, Pau Moreno-Rubio, Daniel Heredero-Peris, Daniel Montesinos-Miracle

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Macià Capó-Lliteras, Pau Moreno-Rubio, Daniel Heredero-Peris, Daniel Montesinos-Miracle. Two copper layer Insulated Metal Substrate PCB potential using Wide-Bandgap semiconductors. The 26th European Conference on Power Electronics and Applications, GDR SEEDS France & EPE Association, Mar 2025, Paris, France. 10.34746/epe2025-0001. hal-05069343

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# Two copper layer Insulated Metal Substrate PCB potential using Wide-Bandgap semiconductors

Macià Capó-Lliteras, Pau Moreno-Rubio,

Daniel Heredero-Peris, and Daniel Montesinos-Miracle

CITCEA-UPC, Universitat Politècnica de Catalunya (UPC)

Av. Diagonal 647 08028

Barcelona, Spain

Tel.: (+34) 93 405 43 16.

E-Mail: macia.capo@upc.edu, pau.moreno@upc.edu,

daniel.heredero@upc.edu, daniel.montesinos@upc.edu

URL: https://citcea.upc.edu

*Index Terms*—Parasitic elements, Design optimization, Wide bandgap devices, Cooling, V2G.

*Abstract*—This paper evaluates two copper-layer Insulated Metal Substrate (IMS) PCBs for power converters, highlighting reduced parasitic inductance and strong thermal performance. It compares various layouts, considering parasitic capacitance, inductance, thermal resistance, and power density, demonstrating exceptional performance in a 4 kVA half-bridge with a 400 V dc-link design.

## I. INTRODUCTION

New-generation Wide-Bandgap (WBG) semiconductor components like silicon carbide (SiC) MOSFETs and Gallium Nitride (GaN) transistors offer superior power handling capabilities in smaller semiconductor footprints compared to traditional silicon-based devices thanks to their exceptional material characteristics. As power loss density rises in WBG-based converters and power modules shrink, effective thermal management of these power devices becomes crucial for achieving peak performance [1]. Meanwhile, these WBG devices switch rapidly with high $dv/dt$ and $di/dt$, and therefore parasitic elements of the power converter design have a strong influence [2]. Also, the ease of assembly of the power converter is essential to reduce human resource costs and possible human error during the production chain. In this context, Insulated Metal Substrate (IMS) Printed Circuit Boards (PCB) have great potential to maximize power density and reduce assembly costs [3]. The low cost and significantly improved thermal efficiency of Insulated Metal Substrate (IMS) make it

a potentially attractive solution deserving exploration when contrasted with Printed Circuit Board (PCB). In general terms, IMS can represent a trade-off between PCB and power module solutions [4].

## II. PARASITIC ELEMENTS OF THE COMMUTATION LOOP

The presence of parasitic elements within the commutation loop influences the switching operation. Parasitic inductance in the power loop increases the voltage overshoot across the device, potentially leading to voltage breakdown. However, parasitic inductance within the gate loop tends to decrease the switching speed, thereby increasing switching losses in the converter. Besides, resonance within the gate loop can cause gate voltage overshoot and damage the semiconductor device's gate structure [5]. Meanwhile, parasitic stray capacitance between different commutation loop electric points and the ground is an important path for undesired displacement currents of Common Mode (CM), which generates noise (EMI). Moreover, displacement currents increase the switching losses of the converter, especially much more turn-on switching losses than turn-off losses [6]. This fact is relevant since turn-on losses can be minimized by zero voltage switching (ZVS) soft-switching strategies. The control strategy implemented for the hardware used and presented in Section III is advanced ZVS control strategy [7] in order to minimize as possible the increment in turn-on switching losses, including the switching losses generated because of the stray capacitance of the layout. After describing the effects of parasitic elements, it is clear that the PCB power loop needs to be carefully
<figure><img src="image_2.png" /><figcaption>Fig. 1. Commutation loop with parasitic elements. Nomenclature of Table I.</figcaption></figure>

designed to reduce these parasitic elements to enable high-frequency switching operations. This section analyses these parasitic elements, along with guidelines on ways to mitigate them.

The commutation loop consists of the power loop and the gate driver loop. Fig. 1 depicts both loops with the parasitic elements for the example of a half-bridge with isolated drivers. Table I describes the nomenclature of Fig. 1.

The parasitic elements can be grouped depending on their effect. This paper focuses on the power loop stage and Table II summarizes the impact that parasitic elements generate, the order of the different groups by priority, which needs to be coped with, and how to solve them [5], [8]–[11].

The parasitic inductances involved in the power loop $L_{PPOS}+L_{PT}+L_{MT}+L_{CST}+L_{PTB}+L_{PB}+L_{MB}+L_{CSB}+L_{PB}+L_{PNEG}$ can cause voltage overshoot. The $v_{DS}$ overshoot may surpass the rated voltage of the semiconductor and make the device fail. Also, the ringing generated due to the inductance of the loop and the high $di/dt$ produces EMI. Regarding the component placement of the loop components, capacitors, and top and bottom semiconductors, the three scenarios shown in Fig. 2 are usually considered.

The capacitances to the heatsink which ends up on the earth, such as $C_{MDH}$, $C_{POSH}$, $C_{NEGH}$, $C_{DCLH}$ generated current displacements and EMI current paths. Reducing large polygons with a high voltage difference can minimize these equivalent capacitors.

Table III summarizes the three different layouts'

<figure><img src="image_3.png" /><figcaption>Fig. 2. Different loop layout with current path indicated with a blue arrow. (a) 1 copper layer, lateral layout. (b) Top cooling layout. (c) Bottom cooling layout.</figcaption></figure>

<figure><img src="image_4.png" /><figcaption>Fig. 3. DAB converter designed for 3.7 kW V2G EV charger application.</figcaption></figure>

characteristics. Therefore, hardware engineers must find a trade-off between parasitic inductance, parasitic capacitance, and thermal performance [12].

### III. DEVELOPED DESIGN AS A CASE STUDY

This section presents a 4 kW GaN full-bridge implemented in two 70 µm copper layer IMS PCB. This full bridge is part of the DAB converter developed for a 3.7 kW V2G EV charger application shown in Fig. 3 designed considering the parasitic elements analyzed in this paper.

It is worth highlighting that the non-standard PCB stack developed in collaboration with the Catalan company Aismalibar made it possible to reduce the power loop parasitic inductance with low parasitic capacitance to the heatsink and with good thermal performance.
<table><caption>TABLE I
PARASITIC ELEMENTS OF THE COMMUTATION LOOP DEPICTED IN FIG. 1.</caption><thead><tr><th>Symbol</th><th>Parasitic component</th></tr></thead><tbody><tr><td>L<sub>PPOS</sub>, L<sub>PT</sub>, L<sub>PTB</sub>, L<sub>PB</sub>, L<sub>PNEG</sub></td><td>Power (P) commutation loop inductances (L<sub>Px</sub>). From positive (POS), top (T), top-to-bottom (TB), bottom (B), and negative (NEG) trace inductance.</td></tr><tr><td>L<sub>CST</sub>, L<sub>CSB</sub></td><td>Common source (CS) top (T) and bottom (B) inductances.</td></tr><tr><td>L<sub>GT1</sub>, L<sub>GT2</sub>, L<sub>GB1</sub>, L<sub>GB2</sub></td><td>Top (T) and bottom (B) gate loop inductances.</td></tr><tr><td>L<sub>MT</sub>, L<sub>MB</sub></td><td>Mutual (CS-with-Gx2) top (T) and bottom (B) inductances.</td></tr><tr><td>C<sub>DRTP</sub>, C<sub>DRBP</sub></td><td>Driver (DR) top (T) and bottom (B) to power loop (P) capacitance.</td></tr><tr><td>C<sub>DRTB</sub>, C<sub>DRTCL</sub>, C<sub>DRBCL</sub></td><td>Driver (DR) top (T) to bottom (B) and to digital control (CL) capacitance.</td></tr><tr><td>C<sub>DCLH</sub></td><td>Digital control (DCL) to heatsink (H) capacitance.</td></tr><tr><td>C<sub>POSH</sub>, C<sub>MDH</sub>, C<sub>NEGH</sub></td><td>Positive (POS), Midpoint (MP), and Negative (N) to heatsink (H) capacitance.</td></tr><tr><td>C<sub>GDT</sub>, C<sub>GDB</sub></td><td>Gate-drain (GD) top (T) and bottom (B).</td></tr></tbody></table>

<table><caption>TABLE II
SUMMARY OF PARASITIC CRITICAL ELEMENTS, PRIORITY TO COPE (PR), EFFECT, AND SOLUTION.</caption><thead><tr><th>Pr</th><th>Critic elements and/or loop</th><th>Effect</th><th>Design rules</th></tr></thead><tbody><tr><td>1</td><td>Power loop:<br>L<sub>PPOS</sub>+L<sub>PT</sub>+L<sub>MT</sub>+L<sub>CST</sub><br>+L<sub>PTB</sub>+L<sub>PB</sub>+L<sub>MB</sub>+L<sub>CSB</sub><br>+L<sub>PNEG</sub></td><td>↑ V<sub>DS</sub> overshoot and undershoot during hard switching-off + EMI.</td><td>· Reduce the distance between components in the power loop.<br>· Apply flux cancellation with larger polygons.</td></tr><tr><td>2</td><td>Capacitance between different potential groups:<br>C<sub>DRTP</sub>, C<sub>DRBP</sub>, C<sub>DRTB</sub>,<br>C<sub>DRTCL</sub>, C<sub>DRBCL</sub></td><td>CM EMI paths.</td><td>· Keep distance between different potential group elements.<br>· Reduce the coupling with CM filter.</td></tr><tr><td>3</td><td>Capacitance to heatsink:<br>C<sub>MDH</sub>, C<sub>POSH</sub>, C<sub>NEGH</sub>, C<sub>DCLH</sub></td><td>Displacement currents during switching and EMI paths.</td><td>· Reduce potential to heatsink equivalent capacitors by reducing large polygons.</td></tr></tbody></table>

<table><caption>TABLE III
CHARACTERISTIC POWER STAGE LAYOUT COMPARISON.</caption><thead><tr><th></th><th>Lateral</th><th>Top cooling</th><th>Bottom cooling</th></tr></thead><tbody><tr><td>Flux cancel</td><td>NO</td><td>YES</td><td>YES</td></tr><tr><td>Top view loop area</td><td>↑↑</td><td>↓↓</td><td>↓</td></tr><tr><td>Vertical impedance</td><td>-</td><td>↑↑</td><td>↑</td></tr><tr><td>PCB thick dependence</td><td>YES</td><td>YES</td><td>NO</td></tr><tr><td>IMS PCB capability</td><td>YES</td><td>NO</td><td>NO<sup>1</sup></td></tr><tr><td>Cap. to heatsink</td><td>↑↑</td><td>↑</td><td>↓</td></tr></tbody></table>

<figure><img src="image_5.png" /><figcaption>Fig. 4. IMS PCB stack manufactured by Aismalibar.</figcaption></figure>

Fig. 4 shows the manufactured PCB stack design, consisting of two copper layers of 70 µm and two dielectric layers of 100 µm. Finally, 1.5 mm of an aluminum substrate on the bottom is shown. This two-layer IMS PCB is not standard for common PCB manufacturers. It allows reduced vertical inductance because of vias height regarding the top cooling and standard bottom cooling layout (Fig. 2c and Fig. 2b). It also minimizes the power loop area in the vertical dimension. For instance, the inductance of the via of the stack developed with the

characteristics shown in Fig. 4 and calculated with the Saturn PCB Design™ tool is 0.1126 nH. However, with the same characteristic but for a standard PCB thickness of 1.6 mm, the inductance is 1.358 nH. This means ten times less inductance with the developed stack.

Fig. 5 shows the power loop layout drawing by the analogy of those presented in Fig. 2 corresponding to the developed design.

It can be observed that it is a hybrid design of lateral layout and bottom-cooled layout (Fig. 2), aiming to seek the trade-off between parasitic inductance, parasitic capacitance to the heatsink, and good thermal performance. The return current does not flow under the top layer, creating a small loop from the top view and not total

<footnote n="1">¹ NO with standard IMS.</footnote>
<figure><img src="image_6.png" /><figcaption>Fig. 5. Developed power loop.</figcaption></figure>

<figure><img src="image_7.png" /><figcaption>Fig. 6. GaN full bridge PCB design.</figcaption></figure>

flux cancellation. However, the vias placed on the middle
point from the top to bottom layer improve the thermal
performance since equivalent thermal resistance to the
aluminum substrate is minimized. This is important
since the device's GaN Systems GS66508B thermal pad
is connected to the source terminal. Additionally, even
though "the drain pad is not as thermally conductive
as the thermal pad, adding more copper under this
pad will improve thermal performance by reducing the
package temperature" [13]. Fig. 6 shows the Altium,
PCB design. Apart from the mentioned characteristics, it
can be observed that polygon areas could be larger, but
they were reduced to minimize the capacitance to the
heatsink. This parasitic effect is important in this design
since the distance between layers is low, as presented
in Fig. 4, so parasitic capacitance could be high. Fig. 7
shows a photo of the GaN full-bridge designed where it
can be observed that most of the thickness is 1.54 mm
of the aluminum substrate.

Fig. 8 shows a zoom of the power loop with the
parasitic inductances of the loop depicted according to
the nomenclature presented in Table II.

A. *Parasitic inductance*

Table IV presents the value of the parasitic induc-
tances of the total loop, which is the summation of
devices, capacitors, and loop path. The parasitic induc-
tances of the GaNSystems GS66508B GaN used devices
extracted from the manufacturer spice model are also
shown. ESL of the capacitor should also be considered.

<figure><img src="image_8.png" /><figcaption>Fig. 7. Photo of GaN full bridge PCB designed.</figcaption></figure>

<figure><img src="image_9.png" /><figcaption>Fig. 8. Power loop with the parasitic inductances.</figcaption></figure>

Finally, path loop inductance is estimated analytically considering an equivalent loop of 10 mm height (H), 17 m long (L) loop, and a track width (d) of 3 mm. The equivalent path inductance deduced is 14.5 nH. Table IV also shows the inductance for a single capacitor and the total number of capacitors, which is considered four in parallel for each leg of the full bridge. Additionally, the rate of the total inductance for any component is presented.

It can be observed from Table IV that the total
power loop parasitic inductance is 15.35 nH, which
4.43% correspond to the semiconductors themselves, the
PCB layout 94.46% and capacitors 1.11%. This result
shows the PCB layout's significant influence on the
communication loop's total parasitic inductance.

B. *Parasitic capacitance*

The parasitic capacitance to the heatsink can be
calculated considering the areas of the polygons, the
PCB stack presented in Fig. 4, and the relative dielectric
constant of the isolation material used between copper
layers (HTC 3.2W with is ε<sub>r</sub>=5.5) and also the aluminum
substrate. The calculated values are intended to give an
idea of the order of magnitude of the capacitances and
should be considered minimum values. This is because
the fringing effect, which increases the capacitance, has
not been accounted for in this calculation. The fringing
<table><caption>TABLE IV
PARASITIC INDUCTANCES OF THE POWER LOOP DEVELOPED.</caption><thead><tr><th>Parasitic inductance</th><th>Value [nH]</th><th>Rate [%]</th></tr></thead><tbody><tr><td><strong>Total layout loop</strong></td><td><strong>14.5</strong></td><td><strong>94.46</strong></td></tr><tr><td>GS66508B L<sub>D</sub></td><td>0.17</td><td>8.54</td></tr><tr><td>GS66508B L<sub>CS</sub></td><td>0.02</td><td>1</td></tr><tr><td>GS66508B L<sub>S</sub></td><td>0.15</td><td>7.54</td></tr><tr><td><strong>Total semiconductors</strong></td><td><strong>0.68</strong></td><td><strong>4.43</strong></td></tr><tr><td>C2225C474KBRAC<br>ESL (4x||)</td><td>0.695</td><td>34.92</td></tr><tr><td><strong>Total capacitors</strong></td><td><strong>0.17</strong></td><td><strong>1.11</strong></td></tr><tr><td><strong>TOTAL</strong></td><td><strong>15.35</strong></td><td><strong>100</strong></td></tr></tbody></table>

<table><caption>TABLE V
STRAY CAPACITANCES $C_{POSH}$ (BUS+), $C_{NEGH}$ (BUS-), AND $C_{MDH}$ (MIDPOINT).</caption><thead><tr><th colspan="3">Power loop</th><th colspan="3">Full bridge</th></tr><tr><th>C<sub>POSH</sub><br>[pF]</th><th>C<sub>NEGH</sub><br>[pF]</th><th>C<sub>MDH</sub><br>[pF]</th><th>C<sub>POSH</sub><br>[pF]</th><th>C<sub>NEGH</sub><br>[pF]</th><th>C<sub>MDH</sub><br>[pF]</th></tr></thead><tbody><tr><td>10</td><td>82.1</td><td>35.8</td><td>110</td><td>544.5</td><td>71.6</td></tr><tr><td>12.5</td><td>102.7</td><td>44.7</td><td>138</td><td>680.6</td><td>89.4</td></tr><tr><td>12.5</td><td>102.7</td><td>44.7</td><td>138</td><td>680.6</td><td>89.4</td></tr></tbody></table>

effect is proportional to the perimeter of the geometry. It can be analytically approximated [14], but this effect has been neglected since the geometries are similar, and the point is the comparison between them. Therefore, the capacitance of the bottom layer to heatsink $C_{BOT-H}$ can be calculated as

$$C_{BOT-H} = \frac{\epsilon_r \epsilon_0 A_i}{100 \cdot 10^{-6}}. \quad (1)$$

where $A_i$ is the area of the polygon, $\epsilon_0$ is the free space electric constant and $\epsilon_r$ is the relative electric constant.

On the other hand, the capacitance that is on the copper top layer to heatsink $C_{TOP-H}$ can be approximated as the worst case scenario that there are two 100 µm layers of dielectric in series and there is no air between them. Therefore

$$C_{TOP-H} = \frac{\epsilon_r \epsilon_0 A_i}{200 \cdot 10^{-6}}. \quad (2)$$

Table V shows the analytical approximation of the capacitances $C_{MDH}$, $C_{POSH}$, $C_{NEGH}$ for the power loop presented in Fig. 8 and for the complete full-bridge presented in Fig. 6.

It can be observed that since the dielectric thickness is low, it is important to consider not only the parasitic inductance but also the parasitic capacitance when the layout is designed.

<table><caption>TABLE VI
THERMAL-ELECTRICAL ANALOGY.</caption><thead><tr><th></th><th>q</th><th>V</th><th>I</th><th>R</th><th>ρ</th><th>σ</th></tr></thead><tbody><tr><th>Electrical [C]</th><td></td><td>[V]</td><td>[A]</td><td>[Ω]</td><td>[Ω m]</td><td>[S/m]</td></tr><tr><th>Q</th><td></td><td>T</td><td>Q̇</td><td>R</td><td>1/k</td><td>k</td></tr><tr><th>Thermal [J]</th><td></td><td>[°C]</td><td>[W]</td><td>[°C/W]</td><td>[(m°C)/W]</td><td>[W/(m°C)]</td></tr></tbody></table>

<figure><img src="image_10.png" /><figcaption>Fig. 9. Thermal circuit analogy. (a) Analog circuit. (b) Analytical results.</figcaption></figure>

### C. Thermal resistance to the heatsink

The electrical analogy shown in Table VI is often used to approximate the thermal performance analytically. Fig. 9a depicts the thermal circuit analogy, which models the stationary thermal behavior of the full bridge presented in this section. It can be observed that there is $R_{J-C}$ from junction to case of the semiconductor, in series the resistance of the top copper polygon $R_{C-T}$ which transfers the heat through the vias $R_{T-B-V}$ in parallel to the dielectric $R_{T-B-D}$ and finally to the bottom layer $R_{T-B}$ and dielectric to the heatsink $R_{B-H}$. The polygon areas, the copper thermal conductivity of 401 W/(m°C), and the thermal dielectric specification allow us to calculate and determine the equivalent thermal resistance of the circuit. The worst scenario is considered since it is supposed that all the heat (power losses) need to be transferred from the source terminal through the top copper polygon, then through vias to the bottom layer (only square polygon below the source terminal), and the dielectric to the aluminum.

Finally, the experimental results were obtained by imposing the conditions to generate about 8 W of losses for each semiconductor. These losses were calculated using PLECS simulation software using the manufacturer's thermal model of the device. Fig. 10 shows the experimental thermal results obtained by using the thermal imager Fluke Ti35 IR FlexCam with a sensitivity of ≤0.1 °C and case temperatures are considered to be black plastic with emissivity of 0.95. It can be observed that the setup reaches a case to ambient drop temperature
<figure><img src="image_11.png" /><figcaption>Fig. 10. Thermal experimental results with the different PCB stacks delivered by Aismalibar. (a) Setup photo. (b) Thermal image.</figcaption></figure>

<figure><img src="image_12.png" /><figcaption>Fig. 11. Alternative design with four copper layers with standard FR4 1.6 mm thickness PCB.</figcaption></figure>

<figure><img src="image_13.png" /><figcaption>Fig. 12. Altium design of the alternative design, PCB stack as proposed (Fig. 4) but with the layout shown in Fig. 2c.</figcaption></figure>

<figure><img src="image_14.png" /><figcaption>Fig. 13. Altium design of the alternative design, 1 IMS 70 µm copper layer lateral layout. (a) PCB stack. (b) Layout.</figcaption></figure>

$\approx \Delta T_{C-A}=33$ °C. Setting the ambient temperature of 25 °C and $R_{J-C}$ of 0.5 °C/W as the manufacturer present in the datasheet, the equivalent thermal resistance can be deduced from experimental results. The experimental thermal resistance obtained is 1.04 °C/W, while the analytical approximation is 1.075 °C/W (Fig. 9b).

## IV. DESIGN COMPARISON WITH ALTERNATIVE DESIGNS

A comparison with alternative designs is presented in this section to show the good performance and achieved trade-off between parasitic inductance, capacitance, thermal behavior, and the easiness of assembling the design developed. The developed design is compared with different alternative designs:

1) Layout presented in Fig. 6 but with a different PCB stack. The stack analyzed in this case is presented in Fig. 11. It comprises a standard four 70 µm layer, dielectric FR4, and 1.6 mm thickness. The TIM material used to calculate inductance, thermal resistance, and capacitance is HI FLOW THF 300P with a thermal conductivity of 1.6 W/(m°C) and $\epsilon_r = 4.5$.

2) Same PCB stack as proposed (Fig. 4) and the layout with flux cancellation. Fig. 12 shows the Altium design of the power loop.

3) The most common copper layer IMS stack using 70 µm copper thickness and best thermal performance Aismalibar dielectric, HTC 3.2W. This layout corresponds to the lateral layout concept (Fig. 2a). Fig. 13 shows the Altium design of the power loop.

The parasitic inductance, parasitic capacitance, and thermal resistance of these alternative designs can be deduced similarly to the deductions addressed in sections III-A, III-B and III-C.

Table VII shows the summary table comparison between the different alternative layouts with the parasitic inductance, thermal resistance, and parasitic capacitance calculated. Also, the PCB area is compact and easy to assemble. Finally, Fig. 14 compares the different alternative layouts. It is considered the criterion, the more area, the better performance: Inductance $\propto 1/L$, Capacitance $\propto 1/C$, Thermal resistance $\propto 1/R_{Th}$.

It can be deduced from Fig. 14 that the best solutions are those with larger areas: Aismalibar 2 IMS layers small-loop and Aismalibar 2 IMS layers flux-cancelling. Both allow a PCB area density and easy assembly, which is much better than the alternatives. Besides the layout implemented, the Aismalibar 2 IMS layers small-loop has better performance in terms of stray inductance than 1 IMS layer and Standard 4 layers FR4 stack, better
<table><caption>TABLE VII
SUMMARY TABLE COMPARISON BETWEEN THE DIFFERENT ALTERNATIVE LAYOUTS.</caption><thead><tr><th>Layout</th><th>Thermal resistance [°C/W]</th><th>Inductance [nH]</th><th>C<sub>POSH</sub> [pF]</th><th>C<sub>NEGH</sub> [pF]</th><th>C<sub>MDH</sub> [pF]</th><th>Area [mm²]</th><th>Assembly</th></tr></thead><tbody><tr><td>Proposed 2 IMS layers small loop*</td><td>1.04</td><td>15.35</td><td>12.5</td><td>102.8</td><td>44.7</td><td>290</td><td>Easy</td></tr><tr><td>2 IMS layers flux canceling*</td><td>3.8</td><td>1.2</td><td>12.7</td><td>142.4</td><td>44.5</td><td>220</td><td>Easy</td></tr><tr><td>IMS layer</td><td>0.8</td><td>33.7</td><td>12.5</td><td>123</td><td>20.7</td><td>400</td><td>Easy</td></tr><tr><td>Standard 4 layers FR4 stack</td><td>2.7</td><td>16.8</td><td>1.46</td><td>82.34</td><td>26.5</td><td>290</td><td>Difficult</td></tr></tbody></table>

<figure><img src="image_15.png" /><figcaption>Fig. 14. Radar diagram of comparison between the different alternative layouts. The chosen criterion is the more area, the better performance (perf.): Inductance $\propto 1/L$, Capacitance $\propto 1/C$, Thermal resistance $\propto 1/R_{Th}$.</figcaption></figure>

thermal resistance than Standard 4 layers FR4 stack and Aismalibar 2 IMS layers flux-cancelling. On the contrary, the solution analyzed as Aismalibar 2 IMS layers flux-canceling performs even better regarding stray inductance than the proposed Aismalibar 2 IMS layers small-loop.

## V. CONCLUSIONS

Therefore, this paper demonstrates the potential of the two copper-layer Insulated Metal Substrate (IMS) PCBs for power converter applications. Depending on the importance of the effect on stray capacitance and thermal resistance regarding stray inductance, the best design will be Aismalibar 2 IMS layers flux-cancelling or Aismalibar 2 IMS layers small-loop. It is worth

highlighting that both designs have high-performance specifications for the case study analyzed of a 4 kVA full-bridge with 400 V of dc-link. On the one hand, the 2 IMS layers flux-cancelling design achieves 1.2 nH of parasitic inductance with a thermal resistance of 3.8 °C/W, maximum capacitance to the heatsink of 142.4 pF in an area of 220 mm². On the other hand, the proposed 2 IMS layers small-loop achieves a 1.04 °C/W of thermal resistance, with a parasitic inductance of 15.35 nH and maximum capacitance to the heatsink of 102.8 pF in an area of 290 mm².

## REFERENCES

[1] P. Weiler, B. Vermulst, M. Roes, and K. Wijnands, "Design limitations of heat spreaders for gallium nitride power modules," in *PCIM Europe Conference Proceedings*, vol. 1, no. July, 2020, pp. 936-942.

[2] J. A. Brothers and T. Beechner, "GaN module design recommendations based on the analysis of a commercial 3-phase GaN module," in *2019 IEEE Energy Conversion Congress and Exposition, ECCE 2019*. IEEE, 2019, pp. 4109-4116.

[3] R. Samani, J. Lu, and I. G. Zurbriggen, "Next Generation of GaN Single-Board High Power Stages," in *2022 IEEE 9th Workshop on Wide Bandgap Power Devices and Applications, WiPDA 2022*. IEEE, 2022, pp. 233-237.

[4] J. Lu, D. Chen, and L. Yushyna, "A high power-density and high efficiency insulated metal substrate based GaN HEMT power module," in *2017 IEEE Energy Conversion Congress and Exposition, ECCE 2017*, vol. 2017-Janua, 2017, pp. 3654-3658.

[5] K. Klein, "Driver integration for fast switching WBG power modules," Fraunhofer Institute for Reliability and Microintegration IZM, Tech. Rep.

[6] M.-v. S. Mosfets, "Impact of Power Module Parasitic Capacitances on," vol. 8, no. 1, pp. 298-310, 2020.

[7] M. Capo-Lliteras, G. G. Oggier, E. Bullich-Massague, D. Heredero-Peris, and D. Montesinos-Miracle, "Analytical and Normalized Equations to Implement the Optimized Triple Phase-Shift Modulation Strategy for DAB Converters," *IEEE Journal of Emerging and Selected Topics in Power Electronics*, vol. 11, no. 3, pp. 3535-3546, 2023.

[8] J. Vanderkloot, "Optimum GaN Power Stage Design," *Gan-Systems, Tech. Rep.*, 2022.

<footnote>* Layout possible with the Aismalibar PCB stack, not with standard one copper layer PCB stack.</footnote>
[9] F. Luo, Z. Chen, L. Xue, P. Mattavelli, D. Boroyevich, and B. Hughes, "Design considerations for GaN HEMT multi-chip halfbridge module for high-frequency power converters," *Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC*, pp. 537-544, 2014.

[10] GaN Systems Inc., "GN001 Application Guide Design with GaN Enhancement Mode HEMT," pp. 1-46, 2018. [Online]. Available: https://gansystems.com/design-center/application-notes/

[11] V. Baker, B. Wen, and V. Baker, "3D Commutation-Loop Design Methodology for a Silicon Carbide Based Matrix Converter run in Step-up mode with PCB Aluminum Nitride Cooling Inlay in partial fulfillment of the requirements for the degree of 3D Commutation-Loop Design Methodology for a

Silic," Ph.D. dissertation, 2021.

[12] S. Munk-Niesen, "2-level Inverter with 10kV SiC Devices Modules for Application in the Field of Renewable Technologies.pdf." Denmark: Aalborg EPE 2023, 2023, p. 28.

[13] GaN Systems Inc., "GS66508B Bottom-side cooled 650 V E-mode GaN transistor Datasheet Features GS66508B Bottom-side cooled 650 V E-mode GaN transistor Datasheet Absolute Maximum Ratings (T case = 25 °C except as noted) Parameter Thermal Characteristics (Typical values un," pp. 1-16, 2020.

[14] X. Chen, Z. Zhang, S. Yu, and T. G. Zsurzsan, "Fringing Effect Analysis of Parallel Plate Capacitors for Capacitive Power Transfer Application," *2019 IEEE 4th International Future Energy Electronics Conference, IFEEC 2019*, 2019.