# Three-Phase Active Split-Source Inverter with step-up/step-down DC bus voltage capabilities for traction application

Antoine Sabrié, Alexandre Battiston, Jean-Yves Gauthier, Xuefang Lin-Shi

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Antoine Sabrié, Alexandre Battiston, Jean-Yves Gauthier, Xuefang Lin-Shi. Three-Phase Active Split-Source Inverter with step-up/step-down DC bus voltage capabilities for traction application. Power Electronic Devices and Components, 2025, 12, pp.100133. 10.1016/j.pedc.2025.100133. hal-05398889

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# Three-Phase Active Split-Source Inverter with step-up/step-down DC bus voltage capabilities for traction application☆

Antoine Sabrié<sup>a,*</sup>, Alexandre Battiston<sup>a,†</sup>, Jean-Yves Gauthier<sup>b,‡</sup>, Xuefang Lin-shi<sup>b,§</sup>

## ARTICLE INFO

**Keywords:**

Voltage Source Inverter (VSI)

DC-AC converter

Single-stage

Split-source inverter

Buck-Boost converter

## ABSTRACT

This paper proposes a new single-stage DC-AC inverter with both step-up and step-down DC bus voltage capability. In a two-level inverter, low-speed operating points result in low modulation index values and poor efficiency. The proposed topology introduces a step-down mode, allowing the motor to be driven with a DC bus voltage lower than the source in low-speed regions, while maintaining the unaltered step-up capability of the DC bus. This means that the addition of the step-down function does not induce extra losses during step-up operation. The converter is validated through both simulation and experiments. In step-down mode, reduced phase current ripple and lower DC-link capacitor temperature are achieved.

## 1. Introduction

In Automotive traction application the two-level Voltage Source Inverter (VSI) has been used extensively due to its maturity, simplicity of implementation, its reliability and its cost. However, the DC bus voltage is fixed and fluctuates with the battery state of charge, which limits the attainable operating points. To address this issue, industrial have introduced a second stage of conversion using DC-DC Boost converter interfaced upstream of the VSI as depicted in Fig. 1. This configuration if for instance used in Toyota Prius, where the DC bus can be elevated from 200 to at most 650 V (Burress et al., 2011). Whereas the usual DC bus voltages are often around 350–400 V (Reimers, Dorn-Gomba, Mak, & Emadi, 2019).

While the Boost stage extends the torque-speed range and increases maximum power, it also introduces additional cost, complexity, and potential reliability concerns. Numerous studies compare the two configuration with and without the Boost stage (Ibrahim & Sujod, 2020; Lemmens, Driesen, & Vanassche, 2013; Li, Huang, Luo, Gao, & Fan, 2018; Schoenen, Kunter, Hennen, & de Doncker, 2010; Yu, Tamura, & Lorenz, 2013). These studies generally report efficiency improvements over normalized drive cycles, thanks to lower switching losses and reduced DC-link temperatures when the DC bus voltage is below the nominal battery voltage (Sabrié, Battiston, Gauthier, & Lin-Shi, 2021). Conversely, at higher voltages and during flux-weakening operation,

the additional losses of the Boost converter can outweigh the benefits (Estima & Marques Cardoso, 2012; Prabhakar et al., 2016; Tenner, Gimther, & Hofmann, 2011).

As reported in Najmabadi, Humphries, Boulet, and Rahman (2016) The main efficiency gains occur when the DC bus voltage is initially lower than the nominal 400 V used in a conventional VSI. In other words, the Boost stage allows the system to operate with a reduced input voltage, for instance 200 V, which is then elevated to 400 V to match the performance of a standard VSI. The largest benefits are therefore observed in the operating range where $V_{DC}$ varies between 200 V and 400 V —i.e., below the nominal DC bus of a single-stage inverter—resulting in lower inverter switching losses and improved overall efficiency. Not only the efficiency will be improved but better THD of the voltages will fed to the machine thanks to higher modulation indexes and reduced DC-link capacitors temperature (Sabrié et al., 2021). The Fig. 3 illustrates these observations. The high efficiency operating area can shift according to the DC bus voltage. One might then question the potential usage of a DC bus voltage step-down function. This function would enable us to optimize the drive train in low speed regions, as well as reducing constraints to connect sources with very fluctuating DC voltages. For the latter case, the step-down function as already been proposed for fuel cell application (Haxhiu, Kyyrä, Chan, & Kanerva, 2021). However, the topology suffers from added losses when using the step-up function.

E-mail addresses: antoine.sabrie@ifpen.fr (A. Sabrié), alexandre.battiston@ifpen.fr (A. Battiston), jean-yves.gauthier@insa-lyon.fr (J.-Y. Gauthier), xuefang.shi@insa-lyon.fr (X. Lin-shi).

<footnote><sup>a</sup> IFP Energies nouvelles - Institut Carnot IFPEN Transports Energie, 1 et 4 Avenue de Bois Préau, 92852 Rueil-Malmaison, France</footnote>

<footnote><sup>b</sup> Univ Lyon, INSA Lyon, Université Claude Bernard Lyon 1, Ecole Centrale de Lyon, CNRS, Ampère UMR 5005, 69621 Villeurbanne, France</footnote>

<footnote>☆ This article is part of a Special issue entitled: 'Selected papers EPE'25' published in Power Electronic Devices and Components.</footnote>

<footnote>* Corresponding author.</footnote>
<figure><img src="image_3.png" /><figcaption>Fig. 1. Two-stage DC-DC Boost and two level VSI configuration.</figcaption></figure>

<figure><img src="image_4.png" /><figcaption>Fig. 2. Single-stage only step-up Bidirectional Active-Split source inverter proposed in Sabrié, Battiston, Gauthier, and Lin-Shi (2024).</figcaption></figure>

In this paper, we propose a new DC-AC inverter topology with both step-up and step-down DC bus voltage capabilities. A two-stage solution offering this function, based on a Buck-Boost converter upstream of the VSI, is shown in Fig. 4. While enabling DC bus voltage reduction, the additional semiconductors needed for this function are increasing the losses during step-up operation. In previous work, we proposed a single-stage step-up inverter based on split source topologies (Abdelhakim, Mattavelli, Boscaino, & Lullo, 2017; Abdelhakim, Mattavelli, & Spiazzi, 2016; Hassan, Abdelhakim, Shoyama, Imaoka, & Dousoky, 2020, 2021; Yin, Ding, Ming, & Loh, 2021) called Bidirectional Active split source Inverter (B-ASSI) (Sabrié et al., 2024). This topology is depicted in Fig. 2. Here, we derive a new topology based on the B-ASSI. The proposed topology offers the step-down function without affecting nor increasing losses when stepping-up the DC bus voltage. Enabling optimized drive train operation, with step-down operation, while retaining the benefits of higher maximum power.

The paper is organized as follows, first in section Section 2 the derived topology is analyzed and modeled. Simulation results and experimental results will then be presented in sections Sections 3 and 4 respectively. Finally, in section Section 5 the advantages of the introduced DC bus voltage step-down will be explored.

## 2. Analysis and mathematical model of the proposed Buck-B-ASSI

In this paper, a novel topology derived from the B-ASSI is proposed. Let us, first, derive operation of the B-ASSI with the charge and discharge inductor state depicted in Fig. 5. The averaged model of the converter is thus expressed by (1).

$$ \begin{bmatrix} \dot{i}_L \\ \dot{V}_{DC} \end{bmatrix} = \begin{bmatrix} 0 & -\frac{1-M_{DC}}{L_{SSI}} \\ \frac{1-M_{DC}}{C_{DC}} & 0 \end{bmatrix} \begin{bmatrix} i_L \\ V_{DC} \end{bmatrix} + \begin{bmatrix} \frac{1}{L_{SSI}} & 0 \\ 0 & -\frac{1}{C_{DC}} \end{bmatrix} \begin{bmatrix} V_{in} \\ i_{load} \end{bmatrix} \quad (1) $$

with $1 - M_{DC}$ representing the elevation ratio, and $i_{load}$ the equivalent current absorbed by the machine. The static characteristic is expressed

<figure><img src="image_5.png" /><figcaption>Fig. 3. High efficiency operation area of a traction PMSM under different DC bus voltage (González-Castaño, Restrepo, Flores-Bahamonde, & Rodriguez, 2022; Higuchi & Shimada, 2013).</figcaption></figure>

<figure><img src="image_6.png" /><figcaption>Fig. 4. Two-stage configuration with a DC-DC 4 switch Buck-Boost converter and a VSI.</figcaption></figure>

as (2).

$$ \frac{V_{DC}}{V_{in}} = \frac{1}{1 - M_{DC}} \quad (2) $$

The proposed topology is called the Buck-B-ASSI (BB-ASSI) and is presented in Fig. 6. Compared to the classical B-ASSI, a new coupled inductor is introduced, allowing the topology to operate with a DC bus voltage lower than the input voltage. The B-ASSI is a structure that can alternate between inductor charging and discharging states during any active or zero-sequence state of the inverter. Proper control of the switches connected to the midpoint of the inverter legs provides this degree of freedom. Such control is necessary to achieve complete and fully decoupled regulation of the DC bus voltage independently of the load operating conditions. This degree of freedom, as well as the ability to ensure regenerative capability, is required in automotive traction applications. The model of the B-ASSI is exactly the same as that of a Boost converter, and can therefore only perform boost operation over the DC bus voltage. If the DC bus voltage is lower than the input voltage, the inductor discharging state would not be achievable. However, in the proposed Buck-B-ASSI, with the added transistor on the secondary side, a discharging state can be achieved under this condition. This discharging state is depicted in Fig. 7(a) and is obtained by applying the command signals $C_{a1}$, $C_{b1}$ and $C_{c1}$ to the transistor, as specified in (3).

$$ C_{a1} = C_{b1} = C_{c1} = \overline{C_{\text{buck}}} \quad (3) $$

This state forces open the three switches $C_{a1}$, $C_{b1}$ and $C_{c1}$ and the transistor $C_{buck}$ turns ON. This state is a forbidden state for the B-ASSI, as it would create a discontinuity in the inductor current. For the BB-ASSI, however, it forces the discharge of the energy stored on the secondary side due to the continuity of the flux in the coupled inductor. The duration of the discharging state is determined by the desired
<figure><img src="image_7.png" /><figcaption>Fig. 5. One possible active state of the B-ASSI for both inductor charging and discharging state.</figcaption></figure>

<figure><img src="image_8.png" /><figcaption>Fig. 6. Proposed topology based on the B-ASSI offering both step-up and step-down DC bus voltage capability.</figcaption></figure>

DC bus voltage. On the contrary, the inductor charging state can be achieved from any previous state of the B-ASSI when operating in Buck mode. This means that the modulation and the state of the converter can be maintained as normally intended (Sabrié et al., 2024). When operating in Buck mode, the command signals $C_{a1}$, $C_{b1}$ and $C_{c1}$ must respect (3). In other words, they can be considered as a single switch composed of three parallelized transistors. Thus, similarly to the way the DC-DC functionality of the B-ASSI can be modeled as a Boost converter, the BB-ASSI can be schematically represented as a non-isolated Flyback converter. This Flyback converter representation is depicted in Fig. 8, where the load current represents the current absorbed by the electrical machine averaged over the switching frequency. This simplified representation allows us to derive the state-space model in a manner similar to that of the Flyback converter, as described in Eq. (4).

$$ \begin{bmatrix} i_{Lm} \\ \dot{V}_{DC} \end{bmatrix} = \begin{bmatrix} 0 & -\frac{(1-M_{DC})N_1}{L_m N_2} \\ \frac{(1-M_{DC})N_1}{C_{DC} N_2} & 0 \end{bmatrix} \begin{bmatrix} i_{Lm} \\ V_{DC} \end{bmatrix} + \begin{bmatrix} \frac{M_{DC}}{L_m} & 0 \\ 0 & -\frac{1}{C_{DC}} \end{bmatrix} \begin{bmatrix} V_{in} \\ i_{load} \end{bmatrix} \quad (4) $$

<figure><img src="image_9.png" /><figcaption>Fig. 7. Conduction mode of the BB-ASSI: (a) Discharging inductor state, (b) Charging inductor state for the zero sequence state $V_{000}$.</figcaption></figure>

<figure><img src="image_10.png" /><figcaption>Fig. 8. Virtual schematics of the BB-ASSI in Buck Mode considered for its modeling.</figcaption></figure>

with $N_1$ and $N_2$ refers to the number of turn of the primary and the secondary side of the coupled inductor. The steady-state model of the converter can then be extracted and is given in (5).

$$ \frac{V_{DC}}{V_{in}} = \frac{N_2}{N_1} \frac{M_{DC}}{1 - M_{DC}} \quad (5) $$

Fig. 9 illustrates the working principle in the switching period $t_{sw}$ in Buck mode. The command signals for the inverter leg can be obtained using any modulation. The one used is the same one as the B-ASSI in Sabrié et al. (2024). The same goes for the command signals of $C_{a2}$, $C_{b2}$ and $C_{c2}$ which enable bidirectional power flow at any load operating condition, while also preventing any shoot-through phenomenon. In Boost mode, the command signals $C_{a1}$, $C_{b1}$ and $C_{c1}$ are generated with dedicated duty cycles for each leg. In Buck mode, however, the command signals $C_{abc1}$ and $C_{buck}$ can be directly obtained from the comparison of the value $1 - M_{DC}$ and the same carrier wave.

The BB-ASSI is simulated considering $N_1 = N_2$ and ideal mutual inductor. The obtained waveforms are presented in Fig. 10. As can be seen, those are the same waveforms as the Flyback converter; the only noticeable difference is the voltage that the transistors $S_{abc1}$ withstand during the zero state $V_{111}$. This voltage drops from the sum of the
<figure><img src="image_11.png" /><figcaption>Fig. 9. Illustration of the working principle of the BB-ASSI over two switching periods.</figcaption></figure>

<figure><img src="image_12.png" /><figcaption>Fig. 10. Obtained waveforms in BB-ASSI in simulation.</figcaption></figure>

input voltage and the turn ratio multiplied by $V_{DC}$ down to the input voltage. However, since the maximum voltage does not change and this variation does not increase losses, it has no impact on the converter's operation.

The BB-ASSI can in fact be considered a Buck-Boost inverter, as shown in (5). However, since the B-ASSI is already a boosting topology, only the Buck mode is used. As stated in the introduction, the main advantage of the BB-ASSI lies in the fact that if the Buck mode is no longer needed, the transistor $S_{buck}$ can be turned OFF, disconnecting the secondary side. The B-ASSI can then operate in its original Boost mode without any added losses due to the Buck function.

### 3. Simulation results

A simulation of the proposed converter is carried out with a Permanent Magnet Synchronous Machine (PMSM) in Matlab/Simulink using the Simscape and SimPowerSystems toolboxes. The motor is speed-controlled using classical Field Oriented Control (FOC), and the parameters used for the simulation are reported in Table 1.

For all simulations, the motor operating regime, the DC bus voltage and input voltage, the applied duty cycle, the modulation index, and the phase currents $i_{abc}$ are represented. The first simulation test case

<table><caption>Table 1
Simulated motor and converter parameters.</caption><thead><tr><td>Parameter</td><td>Symbol</td><td>Value</td></tr></thead><tbody><tr><td>Battery voltage</td><td>V<sub>in</sub></td><td>20 V</td></tr><tr><td>Split source inductor</td><td>L<sub>SSI</sub></td><td>16 μH</td></tr><tr><td>DC bus capacitor</td><td>C</td><td>200 μF</td></tr><tr><td>Motor nominal voltage</td><td>V</td><td>60 V</td></tr><tr><td>Switching frequency</td><td>f<sub>sw</sub></td><td>30 kHz</td></tr><tr><td>Number of pole pairs</td><td>p</td><td>4</td></tr><tr><td>Motor inductance</td><td>L<sub>s</sub></td><td>10 μH</td></tr><tr><td>Motor resistance</td><td>R<sub>s</sub></td><td>5 mΩ</td></tr><tr><td>Flux linkage</td><td>φ<sub>f</sub></td><td>9.5·10<sup>-3</sup> Wb</td></tr><tr><td>Motor inertia</td><td>J</td><td>2.8·10<sup>-6</sup> kg m<sup>2</sup></td></tr><tr><td>Friction coefficient</td><td>f</td><td>5.2·10<sup>-6</sup> N m s/rad</td></tr><tr><td>Speed reference</td><td>ω<sup>*</sup></td><td>[0–15 000 rpm]</td></tr><tr><td>Maximal load torque</td><td>Γ<sub>ch</sub></td><td>15 N m</td></tr></tbody></table>

<figure><img src="image_13.png" /><figcaption>Fig. 11. Validation of the load control over its entire operating range with a regulated DC bus voltage $V_{DC} = V_{in}/2$.</figcaption></figure>

is shown in Fig. 11. This allows validation that the Buck mode of the converter is achieved, as the DC bus is regulated at 10 V from an input voltage of 20 V It can be observed that the load can be operated independently of the DC bus voltage. Indeed, the modulation index can reach its maximum value at 10 V, and the DC bus voltage could, for instance, be set to a higher value to achieve higher speed.

Secondly, it is verified by simulation in Fig. 12 that a smooth transition can be achieved between Buck and Boost modes. It is also verified that the Boost mode remains unaltered. Indeed, it can be observed that the current in the secondary side of the coupled inductor is zero during the Boost stage. In this simulation, one advantage of introducing the Buck mode becomes apparent. Normally, at low operating speeds, the modulation is close to zero, and the waveform fed to the machine suffers from very high Total Harmonic Distortion (THD). In fact, these operating points at low speeds typically exhibit the worst efficiency for the inverter. Here, it can be seen that as the DC bus voltage is gradually decreased from 15 to 10 V, the ripple of the phase currents is greatly reduced. This reduces the losses in the machine as well as in the inverter legs, at the cost of added losses on the secondary side and in the coupled inductor.

Lastly, Fig. 13 shows the waveforms obtained for a step load change from $Γ_{ch} = +2.7$ N m to $Γ_{ch} = -2.7$ N m. This validates the performance of the converter in generator mode, demonstrating the bidirectional power flow capability of the proposed converter.
<figure><img src="image_14.png" /><figcaption>Fig. 12. Validation by simulation of a transition to Boost Mode to buck Mode with gradually decreased DC bus voltage reference for the same load operating condition.</figcaption></figure>

<figure><img src="image_15.png" /><figcaption>Fig. 13. Validation of the generator mode of the BB-ASSI.</figcaption></figure>

## 4. Experimental results

A prototype of the B-ASSI has been developed using NTMTS6D0N15MC MOSFETs from ON Semiconductor. Fig. 14 illustrates the prototype as well as the experimental setup on the test bench. The converter is designed as a proof of concept, and the proposed modulation of the B-ASSI is implemented in the MATLAB/Simulink environment. The converter is used to drive a PMSM in a back-to-back configuration, with a 2L-VSI driving the second machine, thereby enabling control of the torque and speed of the common shaft. The parameters of the B-ASSI prototype and the driven PMSM are provided in Table 1. For the BB-ASSI, an extension board has been developed, as shown in Fig. 15. This board replaces the small six inductors of the B-ASSI.

<figure><img src="image_16.png" /><figcaption>Fig. 14. Experimental validation: (a) – Proposed B-ASSI prototype, (b) – experimental setup.</figcaption></figure>

<figure><img src="image_17.png" /><figcaption>Fig. 15. Experimental board for the BB-ASSI with the coupled inductor and additional transistor.</figcaption></figure>

The working principle of the BB-ASSI is experimentally validated and is depicted in Fig. 16. Large voltage spikes can be observed on the $V_{DS}$ voltage of the secondary-side transistor each time it turns OFF. To avoid operating too close to the breakdown voltage, a very low input voltage is applied. Nevertheless, a DC bus voltage of 3 V is achieved, thus validating the correct Buck operation of the converter. As with the Flyback converter, the BB-ASSI is still affected by the classical issues of Flyback converters. Indeed, parasitic elements such as the leakage inductance of the coupled inductor and the coupling factor are responsible for the over-voltages and ringing observed experimentally. To demonstrate this last point, a detailed simulation of the converter is conducted, with particular attention to the modeling of the parasitic elements. It can be seen from the simulation results in Fig. 17 that taking these elements into account explains the waveforms observed in the experimental setup. While these results were expected, this also
<figure><img src="image_18.png" /><figcaption>Fig. 16. Experimental validation of Buck operation mode of the BB-ASSI.</figcaption></figure>

<figure><img src="image_19.png" /><figcaption>Fig. 17. Simulation of the BB-ASSI with considered leakage inductance non-ideal coupling factor to explain the parasitic phenomenon.</figcaption></figure>

<table><caption>**Table 2**

Considered motor parameters for theoretical calculation.</caption><thead><tr><td>Parameter</td><td>Symbol</td><td>Value</td></tr></thead><tbody><tr><td>Nominal voltage</td><td>V</td><td>350 V</td></tr><tr><td>Maximal peak phase current</td><td>I<sub>max</sub></td><td>500 A</td></tr><tr><td>Nominal power</td><td>P<sub>nom</sub></td><td>130 kW</td></tr><tr><td>Number of pole pairs</td><td>p</td><td>2</td></tr><tr><td>Motor inductance</td><td>L<sub>r</sub></td><td>250 μH</td></tr><tr><td>Motor resistance</td><td>R<sub>r</sub></td><td>6.9 mΩ</td></tr><tr><td>Flux linkage</td><td>φ<sub>f</sub></td><td>87.78·10<sup>-3</sup> Wb</td></tr><tr><td>Friction coefficient</td><td>f</td><td>0.0019 N m s/rad</td></tr><tr><td>Speed reference</td><td>ω<sup>*</sup></td><td>0–20 000 rpm</td></tr><tr><td>Maximal load torque</td><td>Γ<sub>ch</sub></td><td>130 N m</td></tr></tbody></table>

implies that classical solutions used for Flyback converters, such as snubbers or active clamps, can likewise be applied to the BB-ASSI.

## 5. Exploration of the advantages of the DC bus step-down function

As mentioned, the added Buck capability of the BB-ASSI can optimize inverter and machine operation, especially at low speeds. For this analysis, a machine representative of traction applications is considered (Table 2), and its full torque-speed operation at $V_{DC} = 350$ V is shown in Fig. 18, the parameters of the converters are given in Table 3. The MOSFETs used for this theoretical loss analysis are AIMBG120R010M1 from INFINEON considering three devices in parallel.

Four operating areas are defined for the Buck-Boost topologies. The maximum Boost ratio is $V_{DC} \le 2V_{in}$, and the maximum Buck ratio is

<table><caption>**Table 3**

Considered converter parameters for theoretical calculation.</caption><thead><tr><td>Parameter</td><td>Symbol</td><td>Value</td></tr></thead><tbody><tr><td>Input voltage</td><td>V<sub>in</sub></td><td>175 V</td></tr><tr><td>Maximal DC bus voltage</td><td>V</td><td>350 V</td></tr><tr><td>Split source inductor</td><td>L<sub>SSI</sub></td><td>16 μH</td></tr><tr><td>Inductor equivalent series resistance</td><td>r<sub>L</sub></td><td>4 mΩ</td></tr><tr><td>DC bus capacitor</td><td>C</td><td>200 μF</td></tr><tr><td>Switching frequency</td><td>f<sub>sw</sub></td><td>30 kHz</td></tr></tbody></table>

<figure><img src="image_20.png" /><figcaption>Fig. 18. (a) Electric motor speed profile and (b) operating points in the torque-speed plane corresponding during the considered WLTC drive cycle. (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.)</figcaption></figure>

$V_{DC} \ge V_{in}/2$, with $V_{in} = 175$ V. Area 1 corresponds to the MTPA trajectory at minimum DC bus voltage (Buck mode). In areas 2 and 3, $V_{DC}$ is increased from $V_{in}/2$ to $2 * V_{in}$, while area 4 corresponds to flux-weakening at maximum DC bus voltage.

Three topologies are compared: the Boost-only two-stage configuration (Fig. 1), with merged first two areas and $V_{DC} = V_{in}$, the two-stage Buck-Boost configuration (Fig. 4), and the proposed single-stage Buck-Boost configuration (Fig. 6). Simulations are performed in Matlab/Simulink for each point of a WLTC driving cycle. The speed profile is shown in Fig. 18(a), and all operating points are indicated by purple dots in Fig. 18(b). For all three topologies, converters of the same size are compared, i.e. the same semiconductors are considered and the same passive elements are chosen. Although this is not suitable for real-case applications, the same switching frequency is also considered to simplify the comparison.

In these simulations, the voltage and current of each semiconductor are used to calculate conduction and switching losses. Switching events are detected from the waveforms, and the equivalent $E_{on}$ and $E_{off}$ are computed using the component datasheets. Joule losses of the inductor and DC bus capacitors, and iron losses, are also included.

DC bus capacitor losses are negligible compared to semiconductor losses; however, significant RMS current variations occur depending on the presence of the Buck function. Only areas 1 and 2 are relevant for
<figure><img src="image_21.png" /><figcaption>Fig. 19. Difference of DC bus capacitor RMS current between the BB-ASSI and the VSI in low speed regions (zone 1 and 2), considering the turn ratio $N_1/N_2 = 1/8$.</figcaption></figure>

<figure><img src="image_22.png" /><figcaption>Fig. 20. Cumulative dissipated energy during the WLTC drive cycle for the three considered topologies.</figcaption></figure>

this comparison. Fig. 19 shows that RMS current is lower in the BB-ASSI than in the Boost+VSI, demonstrating that reducing the DC bus voltage can lower capacitor operating temperature.

The analytical derivation for BB-ASSI is complex and based on previous B-ASSI work (Antoine, Alexandre, Jean-Yves, & Xuefang, 2024). The simulation of the converters offers an easier alternative for loss calculation. The cumulative energy dissipated during the WLTC cycle is plotted in Fig. 20.

The two-stage 4-switch Buck-Boost+VSI configuration exhibits lower efficiency due to additional semiconductors, while the BB-ASSI performs better as its Boost mode remains unaltered, though with slightly higher overall losses. Increasing the number of turns in the secondary inductor can reduce Buck-mode losses; a turn ratio of at least 1:8 is recommended to achieve efficiency close to the Boost+VSI.

The three compared converters are designed with the same power rating for the analysis. However, since they use a different number of transistors, a stress factor analysis is employed (Pittini, Mira, Zhang, Knott, & Andersen, 2014). The stress factor of a given semiconductor is defined by (6).

$$SCSF_i = \frac{\Sigma_j W_j}{W_i} \cdot \frac{V_{max}^2 I_{rms}^2}{P_{rated}} \quad (6)$$

<table><caption>Table 4
Mean, max and cumulative SCSF over the WLTC cycle.</caption><thead><tr><th>SCSF</th><th>Mean</th><th>Max</th><th>Cumulative</th></tr></thead><tbody><tr><td>Boost + VSI</td><td>0.79</td><td>8.1</td><td>1367.1</td></tr><tr><td>Buck-Boost + VSI</td><td>1.29</td><td>15</td><td>2314.7</td></tr><tr><td>BB-ASSI n = 1:8</td><td>0.99</td><td>12</td><td>1783.2</td></tr></tbody></table>

where $\Sigma_j W_j/W_i$ is the weighting factor for the $i_{th}$ component, taken as one for simplicity, $V_{max}$ the maximum voltage the device must withstand, $I_{rms}$ is the rms current through the component, $P_{rated}$ is the rated power of the converter. A stress factor is calculated for each power semiconductor and then summed to obtain the global Semi-Conductor Stress Factor (SCSF), as defined in (7).

$$SCSF = \sum SCSF_i \quad (7)$$

The global SCSF, which varies with $I_{rms}$ and $V_{DC}$ characterizes overall semiconductor stress of given converter. The SCSF over all operating points for the driving cycle is presented in Table 4, leading to conclusions consistent with the efficiency analysis.

The Boost VSI exhibits a lower stress factor, mainly due to its reduced number of components. In contrast, although the BB-ASSI uses more switches than the Buck-Boost+VSI, it achieves a lower SCSF, particularly at low speeds. The stress factor quantifies semiconductor stress and potential aging: a lower SCSF indicates that individual devices experience reduced electrical stress in the BB-ASSI compared to the Buck-Boost four-switch+VSI solution. While both topologies require semiconductors with similar maximum voltage ratings, the BB-ASSI transistors have lower $I_{rms}$, implying reduced heating, slower aging, or the possibility of selecting devices with lower current ratings. Consequently, the semiconductor cost and the total amount of silicon required for the BB-ASSI are expected to be lower than for the Buck-Boost+VSI solution.

At low speeds, lowering the DC bus voltage improves the THD of machine currents and voltages while significantly reducing phase current ripple. These effects could also mitigate torque ripple and iron losses, potentially offering system-level benefits, though these aspects remain to be quantified.

## 6. Conclusion

This paper introduces a new single-stage topology capable of both step-up and step-down DC bus operation. It leverages the B-ASSI's ability to induce inductor current discontinuity. The added coupled inductor enables Buck-mode operation without affecting Boost-mode performance. A smooth transition between the two modes can be achieved, and no additional losses occur during Boost operation despite the extra components. With careful sizing of the passive elements, the BB-ASSI can offer high efficiency while reducing phase current ripple and DC link capacitor temperature at low-speed operating points. Moreover, this functionality makes the converter robust to supply voltage variations, allowing operation over a wide DC voltage range. While the coupled inductor proved to be functional in the small-scale prototype, inductor design on full scale remains a challenge due to leakage inductance and associated loss-processing requirements. A topological improvement might be necessary and is subject of ongoing research.

### CRediT authorship contribution statement

**Antoine Sabrié:** Writing – review & editing, Writing – original draft, Visualization, Validation, Software, Methodology, Investigation, Conceptualization. **Jean-Yves Battiston:** Visualization, Validation, Supervision, Software, Resources, Methodology, Investigation, Conceptualization. **Jean-Yves Gauthier:** Supervision, Methodology, Investigation, Formal analysis, Conceptualization. **Xuefang Lin-shi:** Supervision, Methodology, Investigation, Formal analysis, Conceptualization.
Declaration of competing interest

The authors declare that they have no known competing finan-
cial interests or personal relationships that could have appeared to
influence the work reported in this paper.

Data availability

Data will be made available on request.

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