# VLSI-SoC: Design Trends

Andrea Calimera, Pierre-Emmanuel Gaillardon, Kunal Korgaonkar, Shahar Kvatinsky, Andre Reis

## ► To cite this version:

Andrea Calimera, Pierre-Emmanuel Gaillardon, Kunal Korgaonkar, Shahar Kvatinsky, Andre Reis. VLSI-SoC: Design Trends. Andrea Calimera; Pierre-Emmanuel Gaillardon; Kunal Korgaonkar; Shahar Kvatinsky; Ricardo Reis. Springer International Publishing, AICT-621, pp.i-xviii, 2021, VLSI-SoC: Design Trends, 978-3-030-81641-4. 10.1007/978-3-030-81641-4. hal-03759823

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Submitted on 24 Aug 2022

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Distributed under a Creative Commons CC BY 4.0 - Attribution - International License
Editor-in-Chief

Kai Rannenberg, Goethe University Frankfurt, Germany

Editorial Board Members

TC 1 – Foundations of Computer Science
Luís Soares Barbosa*†, University of Minho, Braga, Portugal

TC 2 – Software: Theory and Practice
Michael Goedicke, University of Duisburg-Essen, Germany

TC 3 – Education
Arthur Tatnall*‡, Victoria University, Melbourne, Australia

TC 5 – Information Technology Applications
Erich J. Neuhold, University of Vienna, Austria

TC 6 – Communication Systems
Burkhard Stiller, University of Zurich, Zürich, Switzerland

TC 7 – System Modeling and Optimization
Fredi Tröltzsch, TU Berlin, Germany

TC 8 – Information Systems
Jan Pries-Heje, Roskilde University, Denmark

TC 9 – ICT and Society
David Kreps*§, National University of Ireland, Galway, Ireland

TC 10 – Computer Systems Technology
Ricardo Reis*¶, Federal University of Rio Grande do Sul, Porto Alegre, Brazil

TC 11 – Security and Privacy Protection in Information Processing Systems
Steven Furnell*§, Plymouth University, UK

TC 12 – Artificial Intelligence
Eunika Mercier-Laurent*§, University of Reims Champagne-Ardenne, Reims, France

TC 13 – Human-Computer Interaction
Marco Winckler*¶, University of Nice Sophia Antipolis, France

TC 14 – Entertainment Computing
Rainer Malaka, University of Bremen, Germany
IFIP – The International Federation for Information Processing

IFIP was founded in 1960 under the auspices of UNESCO, following the first World Computer Congress held in Paris the previous year. A federation for societies working in information processing, IFIP's aim is two-fold: to support information processing in the countries of its members and to encourage technology transfer to developing nations. As its mission statement clearly states:

> IFIP is the global non-profit federation of societies of ICT professionals that aims at achieving a worldwide professional and socially responsible development and application of information and communication technologies.

IFIP is a non-profit-making organization, run almost solely by 2500 volunteers. It operates through a number of technical committees and working groups, which organize events and publications. IFIP's events range from large international open conferences to working conferences and local seminars.

The flagship event is the IFIP World Computer Congress, at which both invited and contributed papers are presented. Contributed papers are rigorously refereed and the rejection rate is high.

As with the Congress, participation in the open conferences is open to all and papers may be invited or submitted. Again, submitted papers are stringently refereed.

The working conferences are structured differently. They are usually run by a working group and attendance is generally smaller and occasionally by invitation only. Their purpose is to create an atmosphere conducive to innovation and development. Refereeing is also rigorous and papers are subjected to extensive group discussion.

Publications arising from IFIP events vary. The papers presented at the IFIP World Computer Congress and at open conferences are published as conference proceedings, while the results of the working conferences are often published as collections of selected and edited papers.

IFIP distinguishes three types of institutional membership: Country Representative Members, Members at Large, and Associate Members. The type of organization that can apply for membership is a wide variety and includes national or international societies of individual computer scientists/ICT professionals, associations or federations of such societies, government institutions/government related organizations, national or international research institutes or consortia, universities, academies of sciences, companies, national or international associations or federations of companies.

More information about this series at http://www.springer.com/series/6102
Andrea Calimera · Pierre-Emmanuel Gaillardon · Kunal Korgaonkar · Shahar Kvatinsky · Ricardo Reis (Eds.)

VLSI-SoC:
Design Trends

28th IFIP WG 10.5/IEEE International Conference
on Very Large Scale Integration, VLSI-SoC 2020
Salt Lake City, UT, USA, October 6–9, 2020
Revised and Extended Selected Papers

<figure><img src="image_2.png" /></figure>

Springer
Editors

Andrea Calimera ID

Politecnico di Torino

Turin, Italy

Kunal Korgaonkar ID

Technion – Israel Institute of Technology

Haifa, Israel

Ricardo Reis ID

Universidade Federal do Rio Grande do Sul

Porto Alegre, Brazil

Pierre-Emmanuel Gaillardon ID

University of Utah

Salt Lake City, UT, USA

Shahar Kvatinsky ID

Technion – Israel Institute of Technology

Haifa, Israel

ISSN 1868-4238

ISSN 1868-422X (electronic)

IFIP Advances in Information and Communication Technology

ISBN 978-3-030-81640-7

ISBN 978-3-030-81641-4 (eBook)

https://doi.org/10.1007/978-3-030-81641-4

© IFIP International Federation for Information Processing 2021

This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed.

The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use.

The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, expressed or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

This Springer imprint is published by the registered company Springer Nature Switzerland AG

The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland
# Preface

This book contains extended and revised versions of the highest quality papers presented during the 28th edition of the IFIP/IEEE WG 10.5 International Conference on Very Large Scale Integration (VLSI-SoC 2020), a global system-on-chip design and CAD conference. The 28th edition of the conference was held during October 6–9, 2020, virtually from Salt Lake City, USA. Previous conferences have taken place in Edinburgh, Scotland (1981); Trondheim, Norway (1983); Tokyo, Japan (1985); Vancouver, Canada (1987); Munich, Germany (1989); Edinburgh, Scotland (1991); Grenoble, France (1993); Chiba, Japan (1995); Gramado, Brazil (1997); Lisbon, Portugal (1999); Montpellier, France (2001); Darmstadt, Germany (2003); Perth, Australia (2005); Nice, France (2006); Atlanta, USA (2007); Rhodes Island, Greece (2008); Florianopolis, Brazil (2009); Madrid, Spain (2010); Kowloon, Hong Kong (2011), Santa Cruz, USA (2012), Istanbul, Turkey (2013), Playa del Carmen, Mexico (2014), Daejeon, South Korea (2015), Tallin, Estonia (2016), Abu Dhabi, United Arab Emirates (2017), Verona, Italy (2018), and Cuzco, Peru (2019).

The purpose of this conference, sponsored by the IFIP TC 10 Working Group 10.5, the IEEE Council on Electronic Design Automation (CEDA), and the IEEE Circuits and Systems Society, with the in-cooperation of ACM SIGDA, is to provide a forum for the presentation and discussion of the latest academic and industrial results and developments as well as the future trends in the field of system-on-chip (SoC) design, considering the challenges of nano-scale along with state-of-the-art and emerging manufacturing technologies. In particular, VLSI-SoC 2020 addressed cutting-edge research fields like low-power design of RF, analog and mixed-signal circuits, EDA tools for the synthesis and verification of heterogenous SoCs, accelerators for cryp-tography and deep learning and on-chip interconnection systems, reliability and testing, and integration of 3D-ICs. The chapters of this new book in the VLSI-SoC series continue its tradition of providing an internationally acknowledged platform for sci-entific contributions and industrial progress in this field.

For VLSI-SoC 2020, 38 papers out of 74 submissions were selected for oral pre-sentation, and out of those 38 full papers presented at the conference, 16 papers were chosen by a special selection committee to have an extended and revised version included in this book. The selection process for these papers considered the evaluation scores during the review process as well as the review forms provided by members of the Technical Program Committee and the session chairs as a result of the presentations.

The chapters of this book have authors from Belgium, Brazil, England, France, Germany, Israel, Italy, Japan, and USA. The Technical Program Committee for the regular tracks comprised 93 members from 23 countries.

VLSI-SoC 2020 was the culmination of the work of many dedicated volunteers: paper authors, reviewers, session chairs, invited speakers, and various committee chairs. We thank them all for their contributions.
This book is intended for the VLSI community at large, and in particular the many colleagues who did not have the chance to attend the conference. We hope that you enjoy reading this book and find it useful in your professional life and for the development of the VLSI community as a whole.

May 2021

Andrea Calimera
Pierre-Emmanuel Gaillardon

Kunal Korgaonkar
Shahar Kvatinsky

Ricardo Reis
# Organization

The IFIP/IEEE International Conference on Very Large Scale Integration System-on-Chip (VLSI-SoC) 2020 took place during October 6–9, 2020, virtually from Salt Lake City, USA. VLSI-SoC 2020 was the 28th in a series of international conferences, sponsored by IFIP TC 10 Working Group 10.5 (VLSI), IEEE CEDA, and ACM SIGDA. The Organization Committee of the conference consisted of the following colleagues:

## General Chair

Pierre-Emmanuel
Gaillardon

University of Utah, USA

## Technical Program Chairs

Shahar Kvatinsky
Andrea Calimera

Technion, Israel
Politecnico di Torino, Italy

## Special Sessions Chairs

Mike Niemier
David Atienza

University of Notre Dame, USA
EPFL, Switzerland

## PhD Forum Chair

Cunxi Yu

University of Utah, USA

## Local Chairs

Ross Walker
Mike Wirthlin

University of Utah, USA
Brigham Young University, USA

## Industrial Chair

Luca Amaru

Synopsys, USA

## Publicity Chairs

Anupam Chattopadhyay
Andre Reis
Ian O'Connor
Joseph Friedman

NTU, Singapore
UFRGS, Brazil
ECL, France
UT Dallas, USA
## Publication Chair

Kunal Korgaonkar

Technion, Israel

## Web Chairs

Ganesh Gore

University of Utah, USA

Edouard Giacomin

University of Utah, USA

## VLSI-SoC Steering Committee

Graziano Pravadelli

University of Verona, Italy

Ibrahim Elfadel

Khalifa University, UAE

Manfred Glesner

TU Darmstadt, Germany

Matthew Guthaus

UC Santa Cruz, USA

Luis Miguel Silveira

INESC ID, Portugal

Fatih Ugurdag

Ozyegin University, Turkey

Salvador Mir

TIMA, France

Ricardo Reis

UFRGS, Brazil

Chi-Ying Tsui

HKUST, Hong Kong, China

Ian O'Connor

INL, France

Masahiro Fujita

The University of Tokyo, Japan

As for the Technical Program Committee, it was composed as follows:

## Technical Program Committee Track Chairs

### AMS, Sensors, and RF Track

Salvador Mir

TIMA, France

Ross Walker

University of Utah, USA

### VLSI Circuits and SoC Design Track

H. Fatih Ugurdag

Ozyegin University, Istanbul

Adam Teman

Bar-Ilan University, Israel

### Embedded Systems Design and Software Track

Ibrahim Elfadel

Khalifa University, UAE

Michele Magno

ETH Zurich, Switzerland

### CAD Tools and Methodologies for Digital IC Design and Optimization Track

Victor Grimblatt

Synopsys, Chile

Aida Todri-Sanial

University of Montpellier and CNRS, France
## Verification, Modeling, and Prototyping Track

<table><tr><td>Graziano Pravadelli</td><td>Università di Verona, Italy</td></tr><tr><td>Yakir Vizel</td><td>Technion, Israel</td></tr></table>

## Design for Testability, Reliability, and Fault Tolerance Track

<table><tr><td>Matteo Sonza Reorda</td><td>Politecnico di Torino, Italy</td></tr><tr><td>Leticia Bolzani Poehls</td><td>PUCRS and RWTH Aachen, Germany</td></tr></table>

## Hardware Security Track

<table><tr><td>Odysseas Koufopavlou</td><td>University of Patras, Greece</td></tr><tr><td>Anupam Chattopadhyay</td><td>Nanyang Technological University of Singapore, Singapore</td></tr></table>

## Emerging Technologies and New Computing Paradigms Track

<table><tr><td>Ian O'Connor</td><td>Lyon Institute of Nanotechnology, France</td></tr><tr><td>Yang (Cindy) Yi</td><td>Virginia Tech, USA</td></tr></table>

## Technical Program Committee

<table><tr><td>Alain Pegatoguet</td><td>University of Nice, France</td></tr><tr><td>Alberto Bosio</td><td>Ecole Centrale de Lyon, France</td></tr><tr><td>Alessandro Cimatti</td><td>Fondazione Bruno Kessler, Italy</td></tr><tr><td>Alexander Ivrii</td><td>IBM, Israel</td></tr><tr><td>Alexander Nadel</td><td>Intel, Israel</td></tr><tr><td>Alexandre Levisse</td><td>EPFL, Switzerland</td></tr><tr><td>Ali Akoglu</td><td>University of Arizona, USA</td></tr><tr><td>Armin Tajalli</td><td>University of Utah, USA</td></tr><tr><td>Arnaud Virazel</td><td>University of Montpellier, France</td></tr><tr><td>Avi Mendelson</td><td>Technion, Israel</td></tr><tr><td>Ayesha Khalid</td><td>Queen's University Belfast, Northern Ireland</td></tr><tr><td>Azemard Nadine</td><td>University of Montpellier, France</td></tr><tr><td>Bah Hwee Gwee</td><td>Nanyang Technological University of Singapore, Singapore</td></tr><tr><td>C. Andras Moritz</td><td>University of Massachusetts, USA</td></tr><tr><td>Carlos Silva-Cardenas</td><td>Pontificia Universidad Catolica del Perú, Perú</td></tr><tr><td>Chester Rebeiro</td><td>IIT Madras, India</td></tr><tr><td>Christos Papachristou</td><td>Case Western Reserve University, USA</td></tr><tr><td>Chun-Jen Tsai</td><td>National Chiao Tung University, Taiwan</td></tr><tr><td>Daniele Pagliari</td><td>Politecnico di Torino, Italy</td></tr><tr><td>David Atienza</td><td>EPFL, Switzerland</td></tr><tr><td>Debdeep Mukhopadhyay</td><td>IIT Kharagpur, India</td></tr><tr><td>Dimitrios Soudris</td><td>National Technical University of Athens, Greece</td></tr><tr><td>Donatella Sciuto</td><td>Politecnico di Milano, Italy</td></tr><tr><td>Elena Ioana Vatajelu</td><td>TIMA, France</td></tr></table>
<table>
  <tr>
    <td>Francesco Regazzoni</td>
    <td>ALARI, Switzerland</td>
  </tr>
  <tr>
    <td>George Gielen</td>
    <td>Catholic University of Leuven, Belgium</td>
  </tr>
  <tr>
    <td>George Yuan</td>
    <td>Hong-Kong University of Science and Technology, Hong Kong</td>
  </tr>
  <tr>
    <td>Gianvito Urgese</td>
    <td>Politecnico di Torino, Italy</td>
  </tr>
  <tr>
    <td>Gilles Sicard</td>
    <td>CEA LETI, France</td>
  </tr>
  <tr>
    <td>Gurgen Harutyunyan</td>
    <td>Synopsys, Armenia</td>
  </tr>
  <tr>
    <td>Jacob Rosenstein</td>
    <td>Brown University, USA</td>
  </tr>
  <tr>
    <td>Joseph Friedman</td>
    <td>University of Texas at Dallas, USA</td>
  </tr>
  <tr>
    <td>Katell Morin-Allory</td>
    <td>Université Grenoble Alpes, France</td>
  </tr>
  <tr>
    <td>Ke-Horng Chen</td>
    <td>National Chiao Tung University, Taiwan</td>
  </tr>
  <tr>
    <td>L. Miguel Silveira</td>
    <td>University of Lisbon, Portugal</td>
  </tr>
  <tr>
    <td>Lars Bauer</td>
    <td>Karlsruhe Institute of Technology, Germany</td>
  </tr>
  <tr>
    <td>Luc Claesen</td>
    <td>Hasselt University, Belgium</td>
  </tr>
  <tr>
    <td>Maciej Ogorzalek</td>
    <td>Jagiellonian University, Poland</td>
  </tr>
  <tr>
    <td>Marco Donato</td>
    <td>Harvard University, USA</td>
  </tr>
  <tr>
    <td>Matthew Guthaus</td>
    <td>University of California, Santa Cruz, USA</td>
  </tr>
  <tr>
    <td>Matthew Johnston</td>
    <td>Oregon State University, USA</td>
  </tr>
  <tr>
    <td>Michail Maniatakos</td>
    <td>NYU Abu Dhabi, UAE</td>
  </tr>
  <tr>
    <td>Michele Lora</td>
    <td>Singapore University of Technology, Singapore</td>
  </tr>
  <tr>
    <td>Michele Portolan</td>
    <td>Grenoble INP, France</td>
  </tr>
  <tr>
    <td>Mottaqiallah Taouil</td>
    <td>Delft University of Technology, the Netherlands</td>
  </tr>
  <tr>
    <td>Nicola Nicolici</td>
    <td>McMaster University, Canada</td>
  </tr>
  <tr>
    <td>Ozgur Tasdizen</td>
    <td>ARM, England</td>
  </tr>
  <tr>
    <td>Paolo Rech</td>
    <td>Federal University of Rio Grande do Sul, Brazil</td>
  </tr>
  <tr>
    <td>Peng Liu</td>
    <td>Zhejiang University, China</td>
  </tr>
  <tr>
    <td>Per Larsson-Edefors</td>
    <td>Chalmers University of Technology, Sweden</td>
  </tr>
  <tr>
    <td>Piero Malcovati</td>
    <td>University of Pavia, Italy</td>
  </tr>
  <tr>
    <td>Piero Malcovati</td>
    <td>University of Pavia, Italy</td>
  </tr>
  <tr>
    <td>Pramod Subramanyan</td>
    <td>Indian Institute of Technology, Italy</td>
  </tr>
  <tr>
    <td>Ricardo Reis</td>
    <td>Universidade Federal do Rio Grande do Sul, Brazil</td>
  </tr>
  <tr>
    <td>Robert Wille</td>
    <td>Linz University, Austria</td>
  </tr>
  <tr>
    <td>Rongmei Chen</td>
    <td>IMEC, Belgium</td>
  </tr>
  <tr>
    <td>Salvatore Pennisi</td>
    <td>University of Catania, Italy</td>
  </tr>
  <tr>
    <td>Sébastien Le Beux</td>
    <td>Concordia University, Canada</td>
  </tr>
  <tr>
    <td>Seiji Kajihara</td>
    <td>Kyushu Institute of Technology, Japan</td>
  </tr>
  <tr>
    <td>Sezer Gören</td>
    <td>Yeditepe University, Turkey</td>
  </tr>
  <tr>
    <td>Shigeru Yamashita</td>
    <td>Ritsumeikan University, Japan</td>
  </tr>
  <tr>
    <td>Shivam Bhasin</td>
    <td>Nanyang Technological University of Singapore, Singapore</td>
  </tr>
  <tr>
    <td>Smail Niar</td>
    <td>Université Polytechnique Hauts-de-France, France</td>
  </tr>
  <tr>
    <td>Srinivas Katkoori</td>
    <td>University of South Florida, USA</td>
  </tr>
  <tr>
    <td>Sujoy Sinha Roy</td>
    <td>University of Birmingham, England</td>
  </tr>
  <tr>
    <td>Swaroop Chosh</td>
    <td>Pennsylvania State University, USA</td>
  </tr>
  <tr>
    <td>Sylvain Bourdel</td>
    <td>Université Grenoble Alpes, France</td>
  </tr>
  <tr>
    <td>Tetsuya Iizuka</td>
    <td>The University of Tokyo, Japan</td>
  </tr>
</table>
<table><tr><td>Tiago Balen</td><td>Federal University of Rio Grande do Sul, Brazil</td></tr><tr><td>Tiziana Margaria</td><td>Lero, Ireland</td></tr><tr><td>Tolga Yalcin</td><td>Northern Arizona University, USA</td></tr><tr><td>Vasilis Pavlidis</td><td>University of Manchester, England</td></tr><tr><td>Walter Weber</td><td>TU Wien, Austria</td></tr><tr><td>Wenjing Rao</td><td>University of Illinois at Chicago, USA</td></tr><tr><td>Xing Huang</td><td>Technical University of Munich, Germany</td></tr><tr><td>Yuanqing Cheng</td><td>Beihang University, China</td></tr><tr><td>Zhaohao Wang</td><td>Beihang University, China</td></tr></table>
# Contents

<table><tbody><tr><td>Low-Power High-Speed ADCs for ADC-Based Wireline Receivers in 22 nm FDSOI.</td><td>1</td></tr><tr><td>David Cordova, Wim Cops, Yann Deval, François Rivet, Herve Lapuyade, Nicolas Nodenot, and Yohan Piccin</td><td></td></tr><tr><td>Mixed-Mode Signal Processing for Implementing MCMC MIMO Detector</td><td>21</td></tr><tr><td>Amin Aghighi, Behrouz Farhang-Boroujeny, and Armin Tajalli</td><td></td></tr><tr><td>Low Power Current-Mode Relaxation Oscillators for Temperature and Supply Voltage Monitoring</td><td>39</td></tr><tr><td>Shanshan Dai, Caleb R. Tulloss, Xiaoyu Lian, Kangping Hu, Sherief Reda, and Jacob K. Rosenberg</td><td></td></tr><tr><td>Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation</td><td>65</td></tr><tr><td>Tutu Ajayi, Sumanth Kamineni, Morteza Fayazi, Yaswanth K. Cherivirala, Kyumin Kwon, Shourya Gupta, Wenbo Duan, Jeongsup Lee, Chien-Hen Chen, Mehdi Saligane, Dennis Sylvester, David Blaauw, Ronald Dreslinski Jr, Benton Calhoun, and David D. Wentzloff</td><td></td></tr><tr><td>Assessing the Configuration Space of the Open Source NVDLA Deep Learning Accelerator on a Mainstream MPSoC Platform</td><td>87</td></tr><tr><td>Alessandro Veronesi, Davide Bertozzi, and Milos Krstic</td><td></td></tr><tr><td>SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays.</td><td>113</td></tr><tr><td>Yukio Miyasaka, Masahiro Fujita, Alan Mishchenko, and John Wawrzynek</td><td></td></tr><tr><td>Learning Based Timing Closure on Relative Timed Design</td><td>133</td></tr><tr><td>Tannu Sharma, Sumanth Kolluru, and Kenneth S. Stevens</td><td></td></tr><tr><td>Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication.</td><td>149</td></tr><tr><td>Rakshith Saligram, Ankit Kaul, Muhannad S. Bakir, and Arijit Raychowdhury</td><td></td></tr><tr><td>From Informal Specifications to an ABV Framework for Industrial Firmware Verification</td><td>179</td></tr><tr><td>Samuele Germiniani, Moreno Bragaglio, and Graziano Pravadelli</td><td></td></tr></tbody></table>
<table><tr><td>Modular Functional Testing: Targeting the Small Embedded Memories in GPUs.</td><td>205</td></tr><tr><td>Josie Esteban Rodriguez Condia and Matteo Sonza Reorda</td><td></td></tr><tr><td>RAT: A Lightweight Architecture Independent System-Level Soft Error Mitigation Technique.</td><td>235</td></tr><tr><td>Jonas Gava, Ricardo Reis, and Luciano Ost</td><td></td></tr><tr><td>SANSCrypt: Sporadic-Authentication-Based Sequential Logic Encryption</td><td>255</td></tr><tr><td>Yinghua Hu, Kaixin Yang, Shahin Nazarian, and Pierluigi Nuzzo</td><td></td></tr><tr><td>3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic Designs</td><td>279</td></tr><tr><td>Edouard Giacomin, Juergen Boemmels, Julien Ryckaert, Francky Catthoor, and Pierre-Emmanuel Gaillardon</td><td></td></tr><tr><td>3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model.</td><td>301</td></tr><tr><td>Arnaud Poittevin, Chhandak Mukherjee, Ian O'Connor, Cristell Maneux, Guilhem Larrieu, Marina Deng, Sebastien Le Beux, François Marc, Aurélie Lecestre, Cedric Marchand, and Abhishek Kumar</td><td></td></tr><tr><td>Statistical Array Allocation and Partitioning for Compute In-Memory Fabrics</td><td>323</td></tr><tr><td>Brian Crafton, Samuel Spetalnick, Gauthaman Murali, Tushar Krishna, Sung-Kyu Lim, and Arijit Raychowdhury</td><td></td></tr><tr><td>abstractPIM: A Technology Backward-Compatible Compilation Flow for Processing-In-Memory</td><td>343</td></tr><tr><td>Adi Eliahu, Rotem Ben-Hur, Ronny Ronen, and Shahar Kvatinsky</td><td></td></tr><tr><td>Author Index</td><td>363</td></tr></table>
List of Contributors

**Amin Aghighi** Electrical and Computer Engineering Department, University of Utah, Salt Lake City, USA

**Tutu Ajayi** University of Michigan, Ann Arbor, MI, USA

**Muhannad S. Bakir** Georgia Institute of Technology, Atlanta, GA, USA

**Rotem Ben-Hur** Technion - Israel Institute of Technology, Haifa, Israel

**Davide Bertozzi** Department of Engineering, Università degli Studi di Ferrara, Ferrara, Italy

**David Blaauw** University of Michigan, Ann Arbor, MI, USA

**Juergen Boemmels** IMEC, Leuven, Belgium

**Moreno Bragaglio** Department of Computer Science, University of Verona, Verona, Italy

**Benton Calhoun** University of Virginia, Charlottesville, VA, USA

**Francky Catthoor** IMEC, Leuven, Belgium; KU Leuven, Leuven, Belgium

**Chien-Hen Chen** University of Virginia, Charlottesville, VA, USA

**Yaswanth K. Cherivirala** University of Michigan, Ann Arbor, MI, USA

**Josie Esteban Rodriguez Condia** Dip. di Automatica e Informatica (DAUIN), Politecnico di Torino, Torino, Italy

**Wim Cops** MACOM Technology Solutions, Sophia Antipolis, France

**David Cordova** MACOM Technology Solutions, Sophia Antipolis, France

**Brian Crafton** Georgia Institute of Technology, Atlanta, GA, USA

**Shanshan Dai** Brown University, Providence, RI, USA

**Marina Deng** University of Bordeaux, CNRS UMR 5218, Bordeaux INP Talence, Bordeaux, France

**Yann Deval** Laboratoire IMS, Université de Bordeaux, Bordeaux INP, CNRS UMR 5218, Talence, France

**Ronald Dreslinski Jr.** University of Michigan, Ann Arbor, MI, USA

**Wenbo Duan** University of Michigan, Ann Arbor, MI, USA

**Adi Eliahu** Technion - Israel Institute of Technology, Haifa, Israel
**Behrouz Farhang-Boroujeny** Electrical and Computer Engineering Department,
University of Utah, Salt Lake City, USA

**Morteza Fayazi** University of Michigan, Ann Arbor, MI, USA

**Masahiro Fujita** The University of Tokyo, Tokyo, Japan

**Pierre-Emmanuel Gaillardon** University of Utah, Salt Lake City, UT, USA

**Jonas Gava** Instituto de Informática, PGMicro, Universidade Federal do Rio Grande
do Sul - UFRGS, 9500, Porto Alegre, Brazil

**Samuele Germiniani** Department of Computer Science, University of Verona,
Verona, Italy

**Edouard Giacomin** University of Utah, Salt Lake City, UT, USA

**Shourya Gupta** University of Virginia, Charlottesville, VA, USA

**Kangping Hu** Brown University, Providence, RI, USA

**Yinghua Hu** University of Southern California, Los Angeles, CA, USA

**Sumanth Kamineni** University of Virginia, Charlottesville, VA, USA

**Ankit Kaul** Georgia Institute of Technology, Atlanta, GA, USA

**Sumanth Kolluru** University of Utah, Salt Lake City, USA

**Tushar Krishna** Georgia Institute of Technology, Atlanta, GA, USA

**Milos Krstic** IHP - Leibniz-Institut für innovative Mikroelektronik, Frankfurt Oder,
Germany

**Abhishek Kumar** Université de Toulouse, LAAS, CNRS, INP Toulouse, Toulouse,
France

**Shahar Kvatinsky** Technion - Israel Institute of Technology, Haifa, Israel

**Kyumin Kwon** University of Michigan, Ann Arbor, MI, USA

**Herve Lapuyade** Laboratoire IMS, Université de Toulouse, Bordeaux INP,
CNRS UMR 5218, Talence, France

**Guilhem Larrieu** Université de Toulouse, LAAS, CNRS, INP Toulouse, Toulouse,
France; Institute of Industrial Science, LIMMS-CNRS/IIS, The University of Tokyo,
Tokyo, Japan

**Sebastien Le Beux** Lyon Institute of Nanotechnology, University of Lyon, CNRS
UMR 5270, Lyon, France; Ecole Centrale de Lyon, Ecully, France

**Aurélie Lecestre** Université de Toulouse, LAAS, CNRS, INP Toulouse, Toulouse,
France

**Jeongsup Lee** University of Michigan, Ann Arbor, MI, USA

**Xiaoyu Lian** Brown University, Providence, RI, USA
**Sung-Kyu Lim** Georgia Institute of Technology, Atlanta, GA, USA

**Cristell Maneux** University of Bordeaux, CNRS UMR 5218, Bordeaux INP Talence, Bordeaux, France

**François Marc** University of Bordeaux, CNRS UMR 5218, Bordeaux INP Talence, Bordeaux, France

**Cedric Marchand** Lyon Institute of Nanotechnology, University of Lyon, CNRS UMR 5270, Ecole Centrale de Lyon, Ecully, France

**Alan Mishchenko** UC Berkeley, Berkeley, CA, USA

**Yukio Miyasaka** UC Berkeley, Berkeley, CA, USA

**Chhandak Mukherjee** University of Bordeaux, CNRS UMR 5218, Bordeaux INP Talence, Bordeaux, France

**Gauthaman Murali** Georgia Institute of Technology, Atlanta, GA, USA

**Shahin Nazarian** University of Southern California, Los Angeles, CA, USA

**Nicolas Nodenot** MACOM Technology Solutions, Sophia Antipolis, France

**Pierluigi Nuzzo** University of Southern California, Los Angeles, CA, USA

**Ian O'Connor** Lyon Institute of Nanotechnology, University of Lyon, CNRS UMR 5270, Ecole Centrale de Lyon, Ecully, France

**Luciano Ost** Wolfson School, Loughborough University, Loughborough, England

**Yohan Piccin** MACOM Technology Solutions, Sophia Antipolis, France

**Arnaud Poittevin** Lyon Institute of Nanotechnology, University of Lyon, CNRS UMR 5270, Ecole Centrale de Lyon, Ecully, France

**Graziano Pravadelli** Department of Computer Science, University of Verona, Verona, Italy

**Arijit Raychowdhury** Georgia Institute of Technology, Atlanta, GA, USA

**Sherief Reda** Brown University, Providence, RI, USA

**Ricardo Reis** Instituto de Informática, PGMicro, Universidade Federal do Rio Grande do Sul - UFRGS, 9500, Porto Alegre, Brazil

**François Rivet** Laboratorie IMS, Université de Bordeaux, Bordeaux INP, CNRS UMR 5218, Talence, France

**Ronny Ronen** Technion - Israel Institute of Technology, Haifa, Israel

**Jacob K. Rosenberg** Brown University, Providence, RI, USA

**Julien Ryckaert** IMEC, Leuven, Belgium

**Mehdi Saligane** University of Michigan, Ann Arbor, MI, USA
**Rakshith Saligram** Georgia Institute of Technology, Atlanta, GA, USA

**Tannu Sharma** University of Utah, Salt Lake City, USA

**Matteo Sonza Reorda** Dip. di Automatica e Informatica (DAUIN), Politecnico di Torino, Torino, Italy

**Samuel Spetalnick** Georgia Institute of Technology, Atlanta, GA, USA

**Kenneth S. Stevens** University of Utah, Salt Lake City, USA

**Dennis Sylvester** University of Michigan, Ann Arbor, MI, USA

**Armin Tajalli** Electrical and Computer Engineering Department, University of Utah, Salt Lake City, USA

**Caleb R. Tulloss** Columbia University, New York, NY, USA

**Alessandro Veronesi** IHP - Leibniz-Institut für innovative Mikroelektronik, Frankfurt Oder, Germany

**John Wawrzynek** UC Berkeley, Berkeley, CA, USA

**David D. Wentzloff** University of Michigan, Ann Arbor, MI, USA

**Kaixin Yang** University of Southern California, Los Angeles, CA, USA