# Large-Scale-Compatible Stabilization of a 2D Semiconductor Platform toward Discrete Components

Pierre Brus, Victor Zatko, Marta Galbiati, Florian Godel, Sophie Collin, Bernard Servet, Stéphane Xavier, Raphaël Aubry, Patrick Garabedian, Marie-Blandine Martin, et al.

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Pierre Brus, Victor Zatko, Marta Galbiati, Florian Godel, Sophie Collin, et al. Large-Scale-Compatible Stabilization of a 2D Semiconductor Platform toward Discrete Components. Advanced Electronic Materials, 2021, 7 (4), pp.2001109. 10.1002/aelm.202001109. hal-03197171

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# Large-Scale-Compatible Stabilization of a 2D Semiconductor Platform toward Discrete Components

Pierre Brus, Victor Zatko, Marta Galbiati, Florian Godel, Sophie Collin, Bernard Servet, Stephane Xavier, Raphael Aubry, Patrick Garabedian, Marie-Blandine Martin, Bruno Dlubak,* Pierre Seneor,* and Odile Bezencenet

Atomically thin 2D materials have drawn considerable attention in the past years with potential ranging from transistors to optoelectronics. As such, they are now foreseen as strong candidates for epitaxy-free technologies and the tetrad of size-weight-power-and-cost (SWAP-C) reduction. Targeting radiofrequency (RF) applications, the 2D semiconducting transition metal dichalcogenides (TMDC) family can offer the opportunity of wide tunability of their electronic properties, providing a large variety of band gaps. However, evaluation and integration of those materials into discrete components requires a stabilization of their properties. This work focuses on the evaluation of a large-scale compatible fabrication/passivation process on large area (>1000 µm²) monolayers of the prototypical 2D semiconductor MoS₂. The process is developed including pre- and post-patterning protection/passivation layers. It is shown to reduce the initial natural p-doping of the sample, leading to lower transistor threshold voltages, a 10⁶ ION/IOFF ratio, and an effective averaged field-effect mobility under ambient conditions of 20 cm² V⁻¹ s⁻¹ (up to 35 cm² V⁻¹ s⁻¹ for some devices), which represents an increase by a 40-fold factor compared to a conventional process carried on the large scale platform. This work represents an important step toward the integration of 2D TMDCs in discrete RF circuits and components.

## 1. Introduction

Since the discovery of graphene in 2004,[1] 2D materials have raised a huge interest in many fields as electronics,[2-6]

P. Brus, Dr. B. Servet, S. Xavier, Dr. R. Aubry, Dr. P. Garabedian, Dr. O. Bezencenet

Thales Research and Technology

1 avenue Augustin Fresnel, Palaiseau 91767, France

V. Zatko, Dr. M. Galbiati, Dr. F. Godel, S. Collin, Dr. M.-B. Martin,

Dr. B. Dlubak, Prof. P. Seneor

Unité Mixte de Physique

CNRS, Thales, Université Paris-Saclay

Palaiseau 91767, France

E-mail: bruno.dlubak@cnrs-thales.fr; pierre.seneor@cnrs-thales.fr

<figure><img src="image_3.png" /></figure>

The ORCID identification number(s) for the author(s) of this article can be found under https://doi.org/10.1002/aelm.202001109.

© 2021 The Authors. Advanced Electronic Materials published by Wiley-VCH GmbH. This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

DOI: 10.1002/aelm.202001109

spintronics,[7,8] optoelectronics,[9-11] radio-frequencies,[12-14] and so on. It was highlighted that integrating those materials into radiofrequencies (RF) applications would allow significant size-weight-power-and-cost (SWAP-C) reduction.[15,16] Such an interest can be closely related to their outstanding 2D material nature. In particular, compared to III-V semiconductors, 2D materials are epitaxy-free (with low thermal budget), CMOS compatible (easily transferable to any compound), and allow low cost fabrication while enabling stacking into heterostructures to develop new functionalities.[17] Among them, a new generation of 2D semiconductors has emerged, widening the perspectives introduced with graphene. TMDCs have a sizable bandgap of 1-2.5 eV and therefore exhibit pronounced drain current saturation, where the main disadvantage of graphene is overcome. Beyond allowing simultaneous GHz operation frequency and power gain, their gap modularity should give a wide range of options for, channel

resistance, length, ON/OFF ratio, and power gain for the best device compromise. Molybdenum disulfide (MoS₂) is probably their most prototypical example with a mobility expected to reach up to ≈500 cm² V⁻¹ s⁻¹.[18] A striking particularity of MoS₂ (and of 2Ds in general) is the tunability of its electronic properties. For example, its bandgap can be tailored from 1.29 eV for the bulk to 1.90 eV for the monolayer.[19] Furthermore, as the needs for multifunctional radar and wireless communications systems continue to grow, complex RF front end modules are required to enable reconfigurable and multiband operations. This leads to increasing demands on each component in the signal chain. Hence, the next technological platform should provide reduced size, increased power efficiency, and reconfigurability among other aspects. 2Ds, such as MoS₂, offer opportunities toward exploring these applications.[20,21] Importantly, while being epitaxy-free among other advantages, the thickness control at atomic precision allows 2D materials to bring new opportunities when compared to III-V materials. Nevertheless, due to their 2D nature, their properties are highly disturbed by their interaction with the environment. Hence, reaching a stabilized large
<figure><img src="image_4.png" /><figcaption>**Figure 1.** a) Schematics of the MoS₂ monolayer modified exfoliation process to obtain large surface flakes. b) Optical image of a monolayer MoS₂ on an RF compatible substrate. The whole surface is covered with MoS₂. A specific zone with a scratch is selected for the Raman map in (d) to show some contrast. c) Corresponding Raman spectrum of MoS₂ monolayer. d) Large Raman mapping of the A'₁ mode intensity (red for high intensity to black for zero intensity) performed on the highlighted part of the image in (b) and showing high homogeneity of the MoS₂ monolayer. e) Photoluminescence spectrum corresponding to MoS₂ monolayer.</figcaption></figure>

scale 2D semiconductor platform remains a key challenge for applications.

In this study, we introduce a large-scale compatible fabrication process-flow leading to properties stabilization of the prototypical MoS₂. In our work we focused on the fabrication process with this early technological implementation in mind. Thus, to properly develop the early technological bricks essential for our device realization, we defined four key requirements: i) work on relatively large surfaces of material (>1000 µm²) to realistically integrate properties over large-scale material and extract a mean value relevant to the considered platform exploitation compatible with discrete component fabrication (Figure 1). ii) Be compatible with targeted applications (CMOS and RF) relying on a low-loss low-cost substrate already used in many RF applications.[10,22-26] For this reason we selected an already known substrate, highly-resistive silicon covered by 780 nm of SiO₂ (HR-Si/SiO₂). iii) Develop processes that are compatible

with large-scale integration (at least 4-inches wafer). All our processes need to be scalable in terms of passivation, lithography processes for contacts deposition or etching. This is why we chose to focus on scalable physical vapor deposition (PVD) and atomic layer deposition (ALD) processes (Figures 2 and 3). iv) Stabilize the 2D material's electronic properties with clear ON/OFF states (Figure 4). In the following, we detail our process step by step considering the necessary requirements stated above.

## 2. Results and Discussion

Following the first requirement (i), we focused on a large MoS₂ surface with a size on par with crystals domains reached by CVD processes,[27,28] but achieved from bulk crystals thanks to an adapted exfoliation process as exfoliated material
<figure><img src="image_5.png" /><figcaption>b. Protection / Passivation process</figcaption></figure>

<figure><img src="image_6.png" /><figcaption>**Figure 2.** a) Standard process compared to b) protection/passivation process used for our device fabrication: the use of Al₂O₃ layers before and after fabrication allows to preserve the transport characteristics of the 2D semiconductor.</figcaption></figure>

quality remains the reference for the field. Crucially, we took care that our process remained fully compatible with any future emerging large-scale 2D material source. Since interlayer force for MoS₂[29] (29 × 10¹⁸ N m⁻³) is stronger than for graphene[30] (12.8 × 10¹⁸ N m⁻³), the yield of thin flakes of MoS₂ resulting from tape method exfoliation[1] is poor.[31] To alleviate this issue we opted for a modified exfoliation process flow following the work of Desai and coworkers.[32] This process is schematized in Figure 1a. First, bulk material is exfoliated from the crystal using a standard scotch tape exfoliation technique. We then evaporate a layer of gold (≈100 nm) on top of the MoS₂ which bonds with the chalcogen (sulfur) atoms of the upper layer. This is the key step of this process as the interaction between chalcogen and gold is known to be stronger than van der Waals forces between the MoS₂ layers.[33] This allows us to selectively exfoliate the topmost monolayer of MoS₂ using a thermal release tape (TRT). Then, we transfer the MoS₂/Au/ TRT stack onto the targeted HR-Si/SiO₂ substrate. The TRT is heated (≈90 °C) to release Au and underlying MoS₂ onto the substrate. We used a KI/I₂ wet etch diluted in water to etch Au without damaging MoS₂. Finally, we end up with large monolayers of MoS₂ on HR-Si/SiO₂ substrate. TRT process is a solution we adopted to derive a reference exfoliated crystal on scales large enough to assess our encapsulation approach. While this whole approach already allows to produce devices on small-scale for discrete components demonstrators—a crucial starting point for industrial developments—we envision it to be applied to any emerging large scale 2D fabrication.

We present in Figure 1b–e characterization of the MoS₂ transferred on the HR-Si/SiO₂ substrate. Figure 1b displays an optical image of the derived MoS₂ layer with a feeble contrast pointing to its monolayer nature. The Raman spectrum of this layer (514 nm laser) under ambient conditions is shown in Figure 1c. The difference between A'₁ and E' modes (Δω ≈ 17.5 cm⁻¹) confirms the presence of a monolayer.[34] Additionally, a map of the Raman A'₁ mode intensity is presented in Figure 1d highlighting the flake homogeneity. In Figure 1e the flake photoluminescence (PL) spectrum is presented where a direct bandgap of ≈1.85 eV, consistent with reported literature value for the monolayer, can be clearly observed.[35] All these characterizations confirm the presence of a

monolayer with a surface of about 10⁴ µm², 3–4 orders of magnitude larger than the standard exfoliation approach.

Since conventional O₂ plasma treatment classically used in microelectronics to remove residual resist after lithographic processes would lead to etch the MoS₂,[36] a classical fabrication process (Figure 2a) resulted in devices with really high contact resistances (>10 GΩ µm) not allowing electrical characterization. To overcome this issue, we developed the protection/passivation process described in Figure 2b starting from the 2D layer on HR-Si substrates to follow requirement (ii). The next steps were developed following requirement (iii) of choosing processes that are compatible with large-scale integration. First, we deposited a thin aluminum layer by PVD and we further oxidized it in air, resulting in a continuous protection layer of ≈1 nm of alumina (Al₂O₃) over the sample. This protection layer was shown not to damage 2D materials[10,37] but also to prevent their degradation under ambient atmosphere.[38] This allows to protect MoS₂ ahead of the technological steps. For example, during a lift-off process, the MoS₂ layer is never directly in contact with the resist. The MoS₂ layer was then etched to define the device channel. The next step was contact metal deposition. Here, the protection layer was removed by using tetramethylammonium hydroxide (TMAH) diluted in water (1:4) before performing the metal evaporation. Finally, we encapsulated the device in a passivation layer consisting in 10 nm of Al₂O₃ grown by atomic layer deposition (ALD). In the following we describe the characterization of this protection/passivation process and show that it leads to a MoS₂ platform stabilized against environment.

We performed Raman and PL spectroscopies after both the protection and passivation steps in order to see how the MoS₂ properties were influenced. We observed that Raman spectra (see Figure 3b) were affected by the protection/passivation process. The process induced a red-shift of the A'₁ mode but no obvious modification for the E' mode which could correspond to a decrease of the environmental p-type dopant.[39] A special representation allows extraction of the MoS₂ doping variation by taking into account strain variations.[40] It consists in representing the A'₁ as a function of the E' mode (see Figure 3a). In our case, we obtain a reduction of the environmental p-type
<figure><img src="image_7.png" /><figcaption>**Figure 3.** Raman and photoluminescence characterizations of MoS₂: as exfoliated (black), with protection layer (dark purple) and with protection + passivation layers (light purple). a) ω(A') versus ω(E') recorded at various positions at each step of the process. Arrow represents the increase of p-type doping for unprotected channels and the dotted lines are just a guide for the eye representing strain and doping variations. b) Raman spectra taken at each step, dotted lines represent the Raman shifts of the as exfoliated sample. c) Photoluminescence intensity versus peak energy at various positions taken at each step. Arrow represents the increase of p-type doping for unprotected channels. d) Photoluminescence spectra taken at each step.</figcaption></figure>

doping. In Figure 3c,d the PL spectroscopy of monolayer MoS₂ is presented at each process step and we can see a PL intensity drop as well as red-shift of the bandgap which can be attributed to the same doping modification observed in Raman spectroscopy.[39] This is in-line with previous studies showing that this protection/passivation process affects graphene doping,[37] reducing the p-doping caused by ambient conditions.

Finally, we present electrical transport characterization. Thanks to this protection/passivation process, we could observe a contact resistance improvement allowing to electrically characterize our device. We chose to realize a Hall bar design where probes are deported as shown in Figure 4a: this results in more robust non-invasive measurements.[41,42] We use a backgate voltage applied directly to the substrate that allows us to extract the threshold voltage (V<sub>T</sub>), I<sub>ON</sub>/I<sub>OFF</sub> ratio and four-probe field-effect carrier mobility (μ<sub>eff</sub>) of the device. Figure 4b shows

the drain-source current versus backgate voltage with a constant drain-source bias of 5 V. We can notice that adding the passivation layer on top of the channel, reduces the absolute value of the electric field corresponding to the threshold voltage V<sub>T</sub> by 50% from 0.26 V nm<sup>-1</sup> to approximately 0.13 V nm<sup>-1</sup> (for a 780 nm SiO<sub>2</sub> layer). More importantly, the passivation layer increases the I<sub>ON</sub>/I<sub>OFF</sub> ratio by two orders of magnitude to a value of ≈10<sup>6</sup>, allowing higher current intensity through the channel. Already an I<sub>ON</sub>/I<sub>OFF</sub> ratio in the range of 10<sup>4</sup> to 5 × 10<sup>7</sup> (depending on requirements, high performances or low-power) is in-line with requirements for FETs to be used in CMOS logic,[43,44] and we note that even further improvements can be foreseen.[45,46] This is well in agreement with the observed reduction of environmental p-doping of the n-type MoS<sub>2</sub> channel by Raman and PL analyses, as explained before (Figure 3) allowing us to reach higher I<sub>ON</sub>. We note that this
<figure><img src="image_8.png" /><figcaption>**Figure 4.** a) Optical image of a device with a long monolayer MoS₂ channel. b) Drain–source current intensity (I<sub>DS</sub>) versus backgate electric field (V<sub>BG</sub>) applied with a constant source–drain bias (V<sub>DS</sub>) of 5 V for the protected sample with and without passivation. The protection/passivation process allows to restore a large ON/OFF ratio. Inset: relative four-probes field-effect mobility (μ<sub>eff</sub>) comparison for the different fabrication processes. The protection/passivation process leads to a 40-fold increase in the mobility.</figcaption></figure>

result has been well reproduced showing the stabilization of
the properties with similar mobility, threshold voltage, and
saturation velocity being extracted: the variability is reduced
when using our protection/passivation scheme (see Figure S1,
Supporting Information). This result has been well confirmed
on >10 devices without noticing a change in extracted charac-
teristics, confirming that fabricated long devices give a reliable
averaged response. Next, we extracted the four-probe field-
effect carrier mobility (μ<sub>eff</sub>) of our devices following Lembke
et al.<sup>[42]</sup> The four-probe conductivity σ of the MoS<sub>2</sub> monolayer
was found from σ = (L<sub>CH</sub> I<sub>DS</sub>) / (W ΔV), where L<sub>CH</sub> is the length of the
channel separating the voltage probes (≈12 µm), W is the width
of this channel (≈3 µm), I<sub>DS</sub> is the drain–source current, and
ΔV is the potential drop between the two central voltage probes
(see Figure 4a). From this conductivity, the extracted four-probe
field-effect carrier mobility was derived using μ<sub>eff</sub> = (1/d) (dσ/dV<sub>BG</sub>)
where C<sub>OX</sub> is the oxide capacitance and V<sub>BG</sub> is the applied back-
gate voltage. In the following discussion, we assume the capaci-
tance to be C<sub>OX</sub> = ε<sub>r</sub>ε<sub>0</sub> = 4.5 × 10<sup>-3</sup> F m<sup>-2</sup> (with SiO<sub>2</sub> dielectric
constant ε<sub>r</sub> = 3.9 and thickness d = 780 nm).

In the inset of Figure 4b, we can see a comparison of the
different four-probe field-effect mobilities that can be extracted
as a function of the different fabrication processes used. The
standard process without any protection is given as reference.
As expected, this process gives rise to a limited four-probe field-
effect mobility ≈0.5 cm² V⁻¹ s⁻¹ in average. As a comparison,
the mobility obtained on small non passivated exfoliated MoS₂
are on the range of 0.1–13 cm² V⁻¹ s⁻¹.[⁴⁵,⁴⁷] For CVD material,
the mobility is approximately in the same range.[⁴⁸,⁴⁹] Using our
protection layer during the process leads to a higher mobility
of ≈6 cm² V⁻¹ s⁻¹ for our long channel 2D device, highlighting
an increase of more than one order of magnitude compared
to standard process. This shows the importance of protecting
the MoS₂ right from the beginning. Remarkably, the final pas-
sivation layer, which is the last step of our process, leads to
an additional three-fold increase of the averaged mobility to
≈20 cm² V⁻¹ s⁻¹ (up to 35 cm² V⁻¹ s⁻¹ for some devices, see Sup-
porting Information). While working with constraints i) large

2D layers, ii) CMOS and RF compatible substrate, iii) large
scale processing, and iv) stabilized ON/OFF conditions, we are
thus able to observe device characteristics on par with those
obtained with much shorter exfoliated 2D channels in similar
ambient atmosphere at room-temperature (see Figure S1, Sup-
porting Information).[⁴⁶,⁵⁰⁻⁵³] Beyond this positive result, fur-
ther improvements are foreseen for such 2D platforms: high
mobility values have been reported for instance using an
additional chemical treatment[⁴⁶,⁵⁴] or vacuum conditions.[⁴²,⁵⁴]
Moreover, while exfoliated material remain the acknowledged
reference, some studies have already shown the striking poten-
tial of CVD grown layers with large mobilities.[⁵⁵⁻⁵⁸]

**3. Conclusion**

In conclusion, we present in this study a process flow toward the implementation of a large-scale compatible 2D semiconductor platform constrained by key technical requirements toward integration in small series of discrete functional devices. The results we present in this study would certainly benefit many different fields such as RF,[¹²,¹³] digital applications,[⁵⁹] analogic devices,[⁶⁰] optoelectronics,[⁶¹] spintronics,[⁸] and beyond. We made use of large 2D layers compatible with the definition of discrete components and basic cascading, CMOS and RF compatible substrates, scalable PVD and ALD processing, and aimed stabilized ON/OFF conditions. Following these requirements, we already measured transport characteristics equivalent to much shorter exfoliated 2D MoS₂ channels previously reported and a 40-fold improvement of the four-probe field-effect mobility. Our successful protection/passivation results, complementary to first large-scale 2D semiconductor growths[²⁷,²⁸] and test-line wafer scale device integrations[⁴,⁶] reported recently, highlight a very positive path for the definition of highly-efficient large-scale 2D semiconductor platforms.

**4. Experimental Section**

Device Fabrication: Devices were fabricated on relevant SiO₂/HR-Si
substrate. As an initial fabrication step, Ti/Pt alignment marks were
defined on the substrate. These were designed to resist the gold layer etching step during 2D deposition process. Further device structures were defined by PVD metal depositions and lift-off processes.

**Dielectric Deposition:** For the PVD deposition, the samples were transferred under inert atmosphere into an ultra-high vacuum evaporator system (base pressure10⁻⁸ mbar). A 1 nm-thick layer of metallic Al was evaporated on the sample (the deposited thickness and the deposition rate of 40 pm s⁻¹ were controlled using a quartz crystal microbalance) and was then exposed to air so that the Al was oxidized instantly to form an Al₂O₃ passivation layer.

**Electrical Characterization:** All electrical measurements were performed under ambient conditions at room temperature using a Keithley 4200 electrical characterization bench.

## Supporting Information

Supporting Information is available from the Wiley Online Library or from the author.

## Acknowledgements

The authors acknowledge financial support from the European Commission through H2020 Future and Emerging Technologies Graphene Flagship (Grants Nos. 881603 and 785219), from the French National Research Agency (ANR) through “EPOS BP” (ANR-17-CE24-0023-03) “STEM2D” (ANR-19-CE24-0015), and as part of the “Investissements d'Avenir” program (Labex NanoSaclay, reference: ANR-10-LABX-0035).

## Conflict of Interest

The authors declare no conflict of interest.

## Data Availability Statement

The data that support the findings of this study are available from the corresponding author upon reasonable request.

## Keywords

2D semiconductors, MoS₂, transition metal dichalcogenides, radiofrequency, passivation

Received: November 12, 2020

Revised: December 21, 2020

Published online: March 12, 2021

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