TOWARDS REAL-TIME AURALIZATION ON
FPGAS

Rémi Jeunehomme, Romain Michon, Tanguy Risset, Pierre Cochard,
Stéphane Letz

► To cite this version:

Rémi Jeunehomme, Romain Michon, Tanguy Risset, Pierre Cochard, Stéphane Letz. TOWARDS REAL-TIME AURALIZATION ON FPGAS. SMC 2025 - 22nd Sound and Music Computing Conference, University of Music and Performing Arts, Graz, Jun 2025, Gratz, Austria. 10.5281/zenodo.15836298. [https://doi.org/10.5281/zenodo.15836298](https://doi.org/10.5281/zenodo.15836298). [hal-05298956](https://HAL Id: hal-05298956)

Submitted on 6 Oct 2025

HAL is a multi-disciplinary open access
archive for the deposit and dissemination of sci-
entific research documents, whether they are pub-
lished or not. The documents may come from
teaching and research institutions in France or
abroad, or from public or private research centers.

L'archive ouverte pluridisciplinaire HAL, est
destinée au dépôt et à la diffusion de documents
scientifiques de niveau recherche, publiés ou non,
émanant des établissements d'enseignement et de
recherche français ou étrangers, des laboratoires
publics ou privés.

<figure><img src="image_1.png" /></figure>

Distributed under a Creative Commons Attribution 4.0 International License
TOWARDS REAL-TIME AURALIZATION ON FPGAS

Rémi JEUNEHOMME¹, Romain MICHON², Tanguy RISSET², Pierre COCHARD², and Stéphane LETZ²

¹INSA Lyon, Lyon, France

²Inria, INSA Lyon, GRAME-CNCM, CITI, UR3720, Villeurbanne, France

ABSTRACT

Auralization seeks to reproduce the acoustical proper-
ties of a space through artificial reverberation (typically
implemented as a room impulse response convolution).
This process is computationally intensive, especially for
long Impulse Responses (IRs). While CPUs and GPUs
(to lesser extents) have been broadly used for auraliza-
tion, the potential of Field-Programmable Gate Arrays
(FPGAs) remains largely unexplored. This paper inves-
tigates FPGA-based real-time convolution for auraliza-
tion purposes, leveraging High-Level Synthesis (HLS) and
the Syfala toolchain to implement two convolution tech-
niques: a time-domain uniformly partitioned overlap-save
(TUPOLS) algorithm and a frequency-domain uniformly
partitioned overlap-save (FUPOLS) algorithm. These find-
ings highlight the potential of FPGA-based auralization
and suggest avenues for further optimization.

1. INTRODUCTION

Auralization aims at artificially recreating the acoustic
characteristics of an environment. It is the process of ren-
dering the sound field of a source in a space, in such a way
as to simulate the listening experience at a given position in
the modeled space [1]. Auralization has many applications
in various fields, including immersive concerts, Virtual Re-
ality (VR), etc. It is generally implemented by convolving
the Impulse Response (IR) of a modeled or measured space
with an input audio signal. The computational cost of a
convolution increases with the length of the IR. In some
cases (e.g., large churches, etc.), the IR can be longer than
10 seconds, which corresponds to an FIR filter with hun-
dreds of thousands of coefficients. Many algorithms have
been developed to overcome this issue and are known as
Fast Convolution methods.

Most convolution implementations are based on CPU ar-
chitectures [2], but some projects also rely on GPUs [3].
In this paper, we study the implementation of these algo-
rithms on Field Programmable Gate Arrays (FPGAs). FP-
GAs are often referred to as *programmable circuits*. They
offer exceptional latency performances for real-time audio
signal processing [4, 5] and they can be used to manage a
large number of audio channels in parallel at a very low
cost [6]. FPGA architectures are particularly well suited

for parallelizing computations and processing streams of
data, making them a good fit for applications around aural-
ization.

Only few attempts have been made to implement aural-
ization algorithms on FPGAs. A reason for this might be
that implementing complex audio DSP algorithms on an
FPGA is a notoriously hard task. The use of Hardware
Description Languages (HDL) such as Verilog and VHDL
requires advanced hardware skills and is out of reach for
many audio programmers.

This article presents auralization algorithms that
are adapted to FPGA architectures, using the Syfala
toolchain [7], which relies on High Level Synthesis (HLS)
to compile C code downto FPGA. Hence, all implemen-
tations developed here are based on Fast Convolution
techniques and are written in C. We study in particular a
time domain algorithm and a frequency domain algorithm
and show that much better performance can be obtained
from the frequency domain algorithm.

Section 2 presents the state-of-the-art. Sections 3 and 4
respectively describe our time and frequency domain im-
plementations. Section 5 introduces hardware optimiza-
tion techniques used in our solution. Section 6 presents the
performance of both implementations. Finally, Sections 7
and 8 provide an overview of the more general context in
which this work was carried out as well as ongoing and
future works around this project.

## 2. STATE OF THE ART AND PROBLEM STATEMENT

First works around auralization date back to the 1960s. At
the time, geometrical approaches such as ray tracing [8]
or image source techniques [9] were developed to cope
with the limited computational resources available. In the
1990s, the first sound field simulations based on physical
wave equations [10] were conducted. The rise of GPUs
in the 2010s allowed for the solving of these wave-based
equations in real-time [11, 12]. Recently, Machine Learn-
ing and data-driven methods started to be explored [13, 14],
but efficient fast convolution techniques are still currently
the main approach for real-time auralization [2, 15].

Partitioned convolution techniques were first introduced
by Kulp [16] in the late 1980s and later improved by
Egelmeers and al. and Gardner [17–19]. These techniques
decompose the IR and the input signal in smaller blocks of
samples. "Sub-convolutions" are then computed between
the IR blocks and the input signal blocks to deliver par-
tials outputs. In these methods, the input signal blocks al-

Copyright: © 2025. This is an open-access article distributed under the terms of the [Creative Commons Attribution 3.0 Unported License](https://creativecommons.org/licenses/by/3.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.
<figure><img src="image_2.png" /><figcaption>Figure 1. Time-domain Uniformly Partitioned Overlap-Save algorithm (TUPOLS) with P blocks of B samples.</figcaption></figure>

ways have the same length, because the input signal cannot be predicted. Partitioned convolution can be implemented using equal or different length for IR blocks, leading to uniformly-partitioned [2, 16] or non-uniformly partitioned convolution [2, 18]. Thanks to the FFT algorithm [20], it is more efficient to compute convolutions in the frequency domain [2, 21, 22] by multiplying FFT results and then performing an inverse FFT.

Partitioned convolution and FFT-based convolutions can be combined, leading to highly efficient convolution techniques. It has been shown that for high order FIR filters, non-uniformly partitioned FFT-based convolutions are more efficient [2, 18]. They are the current state of the art for computing convolutions for real-time audio signal processing applications on CPUs.

While a lot of research has been conducted on FPGA-based 2D convolutions for image processing and Deep Learning [15, 23, 24], fewer works were carried on FPGA-based 1D convolution for audio purposes. The computation of FFTs on FPGAs can be tedious, and the possibility of parallelization might give an advantage to direct convolutions. Thus, direct convolutions and FFT-based convolutions are relevant on FPGAs.

In 2009, [25] implemented direct convolutions on FPGAs, and in 2015, [26] implemented FFT-based overlap-save convolutions on FPGA for digital pulse compression. Both approaches are tested in this article. Other approaches such as modal-based techniques may be relevant for FPGAs [27]. The modal approach focuses on implementing resonance modes of a room. A drawback is that it is a destructive approach as only a limited number of modes can be implemented and efficiently extracting mode parameters from an impulse response remains a complicated and approximate task [28].

As for other platforms, partitioned convolution methods

are significantly more efficient on FPGAs than other techniques. Non-Uniformly partitioned convolutions are difficult to implement because they need appropriate computation scheduling in order to deliver the correct output. Moreover, the choice of IR partition is itself a complicated problem. For those reasons, only uniformly partitioned convolutions have been evaluated in this paper.

Partitioned convolutions rely on *Overlap-Save* (OLS) or *Overlap-Add* (OLA) schemes [2, 29]. Indeed, the segmentation of the input signal leads to sub-convolutions whose outputs are overlapping and therefore need to be properly delayed and summed. OLS allows to directly get the right output block while storing redundant input blocks instead of storing sub-convolutions results and sum them. OLS saves one addition for overlapping samples, so it is usually preferred to OLA. In regard to these prior points, OLA is not considered in this paper and the two algorithms studied here are referred to as TUPOLS (Time-domain Uniformly Partitioned Overlap-Save) and FUPOLS (Frequency-domain Uniformly Partitioned Overlap-Save).

### 3. TIME DOMAIN APPROACH

The TUPOLS algorithm is depicted in Figure 1. It is based on a temporal transcription of the Uniformly Partitioned OLS technique presented in [2]. The *sub-convolutions* are computed in the time domain using direct (or linear) convolution. Staying in the time domain saves the computation of DFTs and the use of complex numbers, which are twice as heavy to process as real numbers. The IR and the input block are decomposed in *P* Blocks of *B* samples. The input block length does not have to match the IR block length for TUPOLS algorithms (even though we do it here for simplicity). Input blocks are stored in a time do-
<figure><img src="image_3.png" /><figcaption>Figure 2. Frequency-domain Uniformly Partitioned Overlap-Save (FUPOLS) algorithm [2].</figcaption></figure>

main delay-line delaying the blocks of *B* samples at each iteration of the algorithm.

The convolution is decomposed in *P* small *B*×*B* linear sub-convolutions, however in order to avoid a side effect of the block decomposition at frontiers of blocks, current input blocks *x*<sub>*n*</sub> and *x*<sub>*n*−1</sub> are concatenated (this is the OLS principle [2,29]) and successively convolved with IR blocks *h*<sub>*i*</sub> with *i* ∈ {0, 1, ..., *P* − 1} of size *B*.

The result of the sub-convolution is of length 3B - 1,
but due to OLS we only need the samples between B and
2B. Thus, we are able to not calculate the entire output of
the sub-convolutions but only the right B samples. Sub-
convolutions are then summed together to obtain the cor-
responding output block.

4. FREQUENCY DOMAIN APPROACH

The FUPOLS algorithm is adapted from [2] and shown in
Figure 2. It is based on the same principles as the TUPOLS
algorithm, but transposed in the frequency domain. It uses
circular convolutions instead of linear convolutions. As for
TUPOLS, the IR is partitioned in *P* subfilters of *B* sam-
ples, and the input blocks are of length *B* samples as well.
Input blocks *x*<sub>*n*</sub> and *x*<sub>*n*−1</sub> are concatenated in a buffer win-
dow. Then, a 2*B*-length DFT is performed on these blocks,
and only the first *B* + 1 coefficients are kept since we only
manipulate real data.

These *B* + 1 coefficients are then put in the delay-line
(sometimes called *frequency-domain delay-line*), which is
performing a shift of *B* + 1 samples at each iteration of
the algorithm. The *P* subfilters are zero-padded with *B*
zeros, and then a 2*B*-length DFT is performed and only
the first *B* + 1 coefficients are kept just like for the in-
put blocks. This process can be done offline, since the

IR does not change between two iterations. Both input
blocks and subfilter spectrum are then multiplied, which
is sometimes called “spectral convolution” [2]. The results
are then summed in the frequency domain. *B* − 1 com-
plex conjugate coefficients are concatenated to the sum of
spectral convolutions and a 2*B*-point inverse DFT is com-
puted. Since the DFT lengths are inferior to the length of
the output result (2*B* < 3*B* − 1), the first B-1 samples are
time-aliased, but this is not a problem since we are only
interested in the last B samples (due to OLS). The first B
samples are therefore discarded and the last B samples are
returned as the output block.

A key parameter of this algorithm is the block length *B*,
which is also defining the DFT length *K* = 2*B*. This trans-
form length is the minimal length that guarantees the last
*B* valid samples. Most FFTs are more efficient on power
of two, so the block length must be a power of two as well.

5. HARDWARE OPTIMIZATIONS

The FPGA architecture offers several possibilities of hard-
ware acceleration for computations. On the other hand,
they are limited in memory and computing resources. The
Syfala toolchain relies on VITIS HLS which is the HLS
tool provided by AMD/Xilinx (see §1). It provides di-
rectives and pragmas to guide hardware design and syn-
thesis [30]. In this section, we discuss the hardware opti-
mization performed during the implementation of the algo-
rithms. Both TUPOLS and FUPOLS algorithms are imple-
mented on a AMD/Xilinx DIGILENT Zybo Z7-20 board.
## 5.1 Memory Constraints

The AMD/Xilinx Zynq-7000 FPGA used inside the Digilent Zybo Z7-20 board has limited memory resources. It is impossible to store more than approximately 35,000 real coefficients on the Programmable Logic (PL) Block RAMs (BRAM) [31]. Since we want the IR to last several seconds, both the IR coefficients and the input delay-line (whose length is the same as that of the IR) are stored in the DDR external memory and implemented as ring buffers.

FPGAs can retrieve several items in a single memory access request, which is called *bursting*. In order to obtain the best possible burst (approximately one data read per cycle), the IR and the input data should be stored contiguously in memory in such a way that they are accessed in the ascending order. This is depicted in Figure 3 for the TUPOLS case.

For each algorithm iteration, a new input signal block is written below the most recent blocks. The IR blocks are written in memory at the initialization of the algorithm. In this way, the data is read in the ascending order (from the newest to the oldest block for the input signal (block n to 0 in Figure 3), and from the first block, to the last block (block 0 to P-1) for the IR). The number of bursted data should always be even. Thanks to bursts and pipelining (explained below), a new data can be obtained at every clock cycle.

<figure><img src="image_4.png" /><figcaption>Figure 3. Data structure in memory for optimizing burst access (TUPOLS case).</figcaption></figure>

## 5.2 Dataflow Pipeline

One advantage of FPGAs is that they can process streams of data. In particular, it is possible to “pipeline” function calls to improve the overall throughput. This is referred to as “dataflow mode” in AMD/Xilinx tools. Dataflow demands particular code architecture but offers significant latency gains. It is typically suited to read-compute-write code structures, which is the case here. Dataflow partly overcomes the bottleneck of reading the data from the external memory, because it allows the computing step to start as soon as the first blocks of data are available.

## 5.3 Numerical Formats

Most audio programs compute data in floating point format. However, for specific hardware like FPGAs, fixed point format is more efficient and consumes less power and hardware resources [32]. The precision is not the same for both formats: the dynamic range of fixed-point numbers is smaller and thus it is required to manually adapt the precision throughout the calculation, which is a difficult task for non-expert programmers. Numerous tests have been conducted on both TUPOLS and FUPOLS algorithms to maximize the computational efficiency while keeping an acceptable noise. The fixed-point arithmetic can be implemented for TUPOLS algorithm without too much complexity, but the computation of fixed-point FFTs can be tedious because of overflows occurring at different stages of computation [33]. Moreover, it was observed that the AMD/Xilinx HLS tools did not always took advantage of the use of fixed-point arithmetic in terms of resources and latency, leading to similar results as floating-point arithmetic with a poorer precision. For those reasons, floating-point arithmetic was preferred in our implementation.

## 5.4 Loop Nest Pipeline

The TUPOLS algorithm is using linear convolution composed in sub-convolutions. The corresponding code is made out of two nested loops. The outer loop is iterating over the samples of the block while the inner loop is multiplying the B coefficients to get one output sample. It was observed that interchanging the loops – i.e. setting the outer loop for the accumulation and the inner loop for processing each samples – could give significant gains in terms of computation throughput, because it removes the memory dependency in the inner loop [4]. The loop responsible for multiplying coefficients being the outer loop, we are able to unroll the new inner loop because the IR coefficients array is now constant in this loop. This enables Xilinx HLS tool to optimize the first loop pipelining and get much better performance. With this optimization, the design latency<fnref n="1" /> is divided by factors going up to 350.

## 5.5 FFT-based Convolution

The FUPOLS algorithm uses circular convolution, that is, using the FFT algorithm. Numerous implementations of FFT exist on several platforms.

It was chosen to use AMD/Xilinx' LOGICORE IP FFT provided in VITIS HLS [33]. This is a C/C++ library adaptation of Xilinx FFT IP based on Cooley-Tuckey FFT algorithm [20]. This library was used for simplicity, because it is one of the only libraries adapted to HLS. However, its use remains complex and several implementation constraints must be considered. In particular, to use floating point arithmetic in LOGICORE IP FFT in VITIS HLS, it is necessary to set bitwidth to 32 bits, choose 24 or 25 bits phase factors, dynamically set the FFT length, and choose

<footnote n="1">¹ Design latency is the time it takes for a design to be executed on the FPGA. It does not impact the overall audio latency of the system. Throughout this paper, we refer to “design latency” as “latency” as we never talk about audio latency.</footnote>
<figure><img src="image_5.png" /><figcaption>Figure 4. TUPOLS and FUPOLS CSIM outputs compared to the MATLAB convolution implementation</figcaption></figure>

the Radix-2 burst I/O architecture [33], which is not the optimal one in terms of latency.

## 6. RESULTS

The previously discussed TUPOLS and FUPOLS algorithms were submitted to a broad range of tests. The correctness of the output signal was verified and then their performance was evaluated. Figure 4 shows the comparison to the MATLAB standard convolution function in floating point data. The Root-mean Squared Error for TUPOLS and FUPOLS was calculated:

$$RMSE_{TUPOLSfloat} = 1.0654 \times 10^{-05} \quad (1)$$

$$RMSE_{FUPOLSfloat} = 4.2312 \times 10^{-07} \quad (2)$$

Errors between MATLAB implementation and TUPOLS and FUPOLS algorithms are acceptable considering floating point format, though FUPOLS shows better performances: for long signals, optimised FFTs can accumulate less errors. In both cases, the difference between signals is not audible. To evaluate performance, we focus on two main indicators: input-output latency and FPGA resource usage, evaluated by the AMD/Xilinx compilation tools during synthesis. Estimated resource and latency during implementation can vary a bit compared to synthesis. Input-output latency is measured in clock cycles (the internal Zybo Z7-20 clock is set to 125 MHz [31]) and resources are presented in percentage relative to the maximum available on the board. Only floating point results are shown here and a sampling rate of $f_s = 48$ kHz is used.

### 6.1 TUPOLS Performances

For the time domain approach TUPOLS, Figure 5 shows the I/O latency per output samples for several IR lengths, going from 1 to 5 seconds, and for several input block lengths. Resources do not evolve with the length of the IR because the sub-convolutions are implemented sequentially, but they do with block length. Figure 6 shows the resources consumption for different input block lengths for a one second IR.

On Figure 5, we observe that the TUPOLS algorithm is only able to deliver the output signal in real-time only for

<figure><img src="image_6.png" /><figcaption>Figure 5. TUPOLS latency in function of IR length. The dashed line represents the maximum possible latency, over this line two successive convolutions will overlap in time.</figcaption></figure>

<figure><img src="image_7.png" /><figcaption>Figure 6. TUPOLS resources on a Zybo-Z7-20 as a function of input block length for a 1s IR. The dashed line represents 100% of resources.</figcaption></figure>

IR inferior to 1 second with long block length. However Figure 6 shows that resource consumption grows with the block length. Hence, a convolution with an IR of 1 second cannot be executed on the Zybo Z7-20 with TUPOLS. This is mostly due to the unrolling of loops during the sub-convolutions computation. The majority of the latency and resources consumption is still due to the computation of linear convolutions despite hardware and software optimizations discussed above. It is clear that the Zybo Z7-20 is not dimensioned to support such calculations with real-time constraints. Better performance could be achieved with a bigger FPGA. However, this would not help with the bottleneck shown in Figure 5 (i.e., latency limitation due to memory accesses) unless it contains enough block RAM to store the whole IR and the delay-line.

### 6.2 FUPOLS Performances

FUPOLS algorithm provides much better performances. Figure 7 shows the I/O latency per output sample for several IR lengths going from 1 to 10 seconds for several input block lengths. As for the TUPOLS algorithm, resources do not increase with the length of the IR because processing is carried out sequentially. Figure 8 shows the resource consumption for different input block lengths for a 1 second IR.

The I/O latency of the FUPOLS algorithm is below the
<figure><img src="image_8.png" /><figcaption>Figure 7. FUPOLS latency in function of the IR length (floating point data). The dashed line represents the maximum possible latency.</figcaption></figure>

<figure><img src="image_9.png" /><figcaption>Figure 8. FUPOLS resources on a Zybo-Z7-20 as a function of the input block length.</figcaption></figure>

real-time maximum for IRs going up to more than 10 seconds, depending on the block length. All resources are acceptable (below 70%). A notable difference with TUPOLS is that resource don't evolve a lot with the block length (only BRAMs change at 1024 samples block length, due to FFT LOGICORE IP configuration). This is because the spectral convolution computations are only pipelined and not unrolled. The resources consumption is mainly due to FFT computations.

## 6.3 Algorithms Comparison

TUPOLS and FUPOLS algorithms have quite distinct performances. TUPOLS algorithm is below real-time requirements. The bottleneck is the direct convolutions in terms of resources and latency. A bigger FPGA with more DSPs or LUTs could solve the problem of resource consumption, but the latency is still beyond real-time for IRs superior to 1 second. Despite the loop inversion and dual-ports BRAM on the Zybo Z7-20, the VITIS HLS compiler was not able to remove all memory dependencies, leading to poor pipeline performance [30].

The FUPOLS algorithm has significantly better performances. The resource consumption is reasonable for the Zybo Z7-20 and does not evolve with block length or IR length. It is thus possible to implement convolution with long IRs (several seconds) in real-time. The limitation only comes from the latency, again related to memory ac-

cesses, but acceptable up to 10 second IR length. The better performance of FUPOLS can be explained by the lower complexity of FFT-based convolution ($O(\log N)$) per output sample for FFT-based, $O(N)$ for direct convolution), but also by a better use of VITIS HLS dataflow mode and bursts in memory accesses. The bottleneck of this algorithm is still the spectral convolutions and the DFT computation, but it is closely followed by memory access limitations. FPGAs with more memory resources having a faster DFT implementation could be relevant here.

## 7. FUTURE WORKS

As mentioned in §1, FPGAs are a good fit for spatial audio applications as they can manage a large number of audio channels in parallel. This has been demonstrated in [6] where various audio interfaces targeting FPGAs and providing hundreds of audio inputs and outputs were introduced. The work presented in this paper can be seen as a first milestone towards running multichannel convolution operations in the context of spatial audio for advanced auralization applications. Much work remains to be done though for deploying spatial audio algorithms such as ambisonics decoder [34] on an FPGA. The use of much larger FPGAs than the ones present on the Zybo Z7-20 will be essential to provide the necessary additional computational power. We are also in the process of investigating the use of other auralization techniques such as modal reverberation as an alternative to the convolution implementations presented here. The parallel nature of FPGAs could be exploited in this context to compute a large number of modal filters in parallel. We recently proposed a paper (under review) comparing the performances of CPUs, FPGAs, and GPUs for this kind of applications [35].

## 8. CONCLUSION

In this paper, we investigated the implementation of various convolution techniques on an FPGA aiming convolution-based artificial reverberation and hence auralization applications. Similar tendencies can be observed between FPGA and CPUs in this context: for long IRs, FFT-based convolution is more efficient, despite the possibility of hardware optimization offered by FPGAs. Fixed-point arithmetic could potentially improve these results but is tedious to implement in HLS with the use of external libraries. This is where we experienced the limitation of the HLS approach: further hardware optimizations would probably require a low-level VHDL or Verilog implementation, which is out of reach for now.

"Real-world" auralization applications imply the processing of a large number of audio channels in parallel using convolutions and will necessitate the use of a large FPGA. Dynamic IRs have not been investigated here, however auralization would benefit from it. Further software implementations have been discarded for this study, but could be of interest:

* Non-uniformly partitioned convolution which is theoretically more efficient than uniformly partitioned
convolution on CPUs could benefit from FPGA
hardware in terms of computational load.

* The use of NTTs (Number Theoretic Transforms) to replace FFTs for circular convolutions. Currently not relevant on CPUs compared to efficient implementation of FFTs [2], NTTs could be particularly well suited to embedded hardware like FPGAs and fixed-point arithmetic. Important resources and latency gains could be observed.

More generally, we believe that FPGAs will help improve
auralization systems targeting general public applications.

Acknowledgments

This work was funded by the French National Agency
for Research as part of the FAST ANR project (ANR-20-
CE38-0001). <fnref n="2" />

9. REFERENCES

[1] M. Kleiner, B.-I. Dalenbäck, and P. Svensson, “Au-
ralization - an overview,” in *Journal of the Audio Engi-
neering Society*, vol. 41, 1993, p. 861–875.

[2] F. Wefers, “Partitioned convolution algorithms for real-time auralization,” Master’s thesis, Aachen University, 2015.

[3] F. Wefers and J. Berg, "High-performance real-time fir-
filtering using fast convolution on graphics hardware," in
*Proceedings of the 13th International Conference on
Digital Audio Effects (DAFx-10)*, 2010.

[4] M. Popoff, R. Michon, T. Risset, P. Cochard, S. Letz, Y. Orlarey, and F. De Dinechin, “Audio DSP to FPGA Compilation,” in *Proceedings of the IEEE 34th International Conference on Application-specific Systems, Architectures and Processors (ASAP)*, Jul. 2023, pp. 31–32.

[5] P. Cochard, M. Popoff, A. Fraboulet, T. Risset, S. Letz, and R. Michon, “A programmable linux-based FPGA platform for audio DSP,” in *Proceedings of the 2023 Sound and Music Computing Conference (SMC-23)*. Bresin, R., Falkenberg, K., 2023, pp. 110–116.

[6] M. Popoff, R. Michon, and T. Risset, “Enabling afford-
able and scalable audio spatialization with multichan-
nel audio expansion boards for FPGA,” in *Proceedings
of the 2024 Sound and Music Computing Conference*,
Porto, Portugal, 2024, pp. 397–402.

[7] M. Popoff, R. Michon, T. Risset, P. Cochard, S. Letz, Y. Orlarey, and F. de Dinechin, “Audio DSP to FPGA Compilation: The Syfala Toolchain Approach,” Univ Lyon, INSA Lyon, Inria, CITI, Grame, Emeraude, Tech. Rep. RR-9507, May 2023.

[8] A. Krokstad, S. Strom, and S. Sørsdal, “Calculating the acoustical room response by the use of a ray tracing technique,” vol. 8, pp. 118–125, 1967.

[9] J. B. Allen and D. A. Berkley, “Image method for effi-
ciently simulating small-room acoustics,” pp. 943–950,
1978.

[10] D. Botteldooren, “Acoustical finite-difference time-
domain simulation in a quasi-cartesian grid,” pp. 2313–
2319, 1994.

[11] N. Tsingos, “Using programmable graphics hardware for acoustics and audio rendering,” in *Proceedings of the Audio Engineering Society Convention 127*, 2009.

[12] L. Savioja, “Real-time 3D finite-difference time-
domain simulation of low- and mid-frequency room
acoustics,” in *Proceedings of the 13th International
Conference on Digital Audio Effects (DAFx-10)*, 2010.

[13] S. Wirler, S. J. Schlecht, and V. Pulkki, “Machine
learning based auralization of rigid sphere scattering,”
in *Proceedings of the Immersive and 3D Audio: from
Architecture to Automotive (I3DA) conference*. IEEE,
2021.

[14] M. Cobos, J. Ahrens, K. Kowalczyk, and A. Poli-
tis, “An overview of machine learning and other data-
based methods for spatial audio capture, processing,
and reproduction,” 2022.

[15] D. Varughese and S. Sridevi, “Optimum resource uti-
lization for the implementation of FPGA-based fast
convolutional algorithms for CNN modelling,” in *Pro-
ceedings of the 2023 IEEE Women in Technology Con-
ference (WINTECHCON)*, 2019.

[16] B. D. Kulp, “Digital equalization using fourier transform techniques,” *Journal of The Audio Engineering Society*, 1988.

[17] G. P. M. Egelmeers and P. C. W. Sommen, “A new method for efficient convolution in frequency domain by nonuniform partitioning for adaptive filtering,” in *Proceedings of the 7th European Signal Processing Conference*, 1994, pp. 1030–1033.

[18] W. G. Gardner, “Efficient convolution without input-output delay.” vol. 43, pp. 127–136, 1995.

[19] D. S. M. Huron, “A digital audio convolution worksta-
tion,” in *Proceedings of the Audio Engineering Society
Regional Convention*, 1995.

[20] J. W. Cooley and J. W. Tukey, “An algorithm for the machine calculation of complex fourier series,” *Mathematics of Computation*, vol. 19, no. 90, pp. 297–301, 1965.

[21] P. Duhamel and M. Vetterli, “Fast fourier transforms: A tutorial review and a state of the art,” in *Signal Processing*, 1990, pp. 259–299.

[22] T. G. Stockham, “High-speed convolution and correla-
tion,” in *Proceedings of the Spring joint computer con-
ference*, 1965, p. 229–233.

<footnote n="2">² https://fast.grame.fr</footnote>
[23] A. S. Kushchenko, N. E. Ternovoy, M. G. Popov, and A. N. Yakunin, "Implementation of convolution function through fast fourier transform in convolution neural networks computation," in *Proceedings of the 2022 Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus)*, 2022, pp. 368–370.

[24] Z. Bai, H. Fan, L. Liu, L. Liu, and D. Wang, "An OpenCL-based FPGA accelerator with the winograd's minimal filtering algorithm for convolution neuron networks," in *Proceedings of the 2019 IEEE 5th International Conference on Computer and Communications (ICCC)*, 2019.

[25] K. Mohammad and S. Agaian, "Efficient FPGA implementation of convolution," in *Proceedings of the IEEE International Conference on Systems, Man, and Cybernetics*, 2009, pp. 3478–83.

[26] V. ThakurAmit, K. Verma, P. Jena, and G. S. Prasad, "Design and implementation of FPGA based digital pulse compression via fast convolution using FFT-OS method," in *Proceedings of the 2015 International Conference on Microwave, Optical and Communication Engineering (ICMOCE)*, 2015, pp. 455–458.

[27] E. Maestre, J. S. Abel, J. O. Smith, and G. P. Scavone, "Constrained pole optimization for modal reverberation," in *Proceedings of the 5th International Conference on Digital Audio Effects (DAFx)*, Edinburgh, UK, 2017.

[28] O. Das and J. S. Abel, "Modal estimation on a warped frequency axis for linear system modeling," *arXiv preprint arXiv:2202.11192*, 2022.

[29] F. D. Harris, *Handbook of Digital Signal Processing*. Academic Press, 1987.

[30] VITIS HLS, "Vitis unified software platform documentation application acceleration development," Xilinx AMD, Tech. Rep., 2020.

[31] DIGILENT, "Zybo™ fpga board reference manual," Xilinx AMD, Tech. Rep., 2016.

[32] A. Finnerty and H. Ratigner, "Reduce power and cost by converting from floating point to fixed point," Xilinx AMD, Tech. Rep., 2017.

[33] VITIS HLS, "Fast fourier transform v9.1 logicore ip product guide," Xilinx AMD, Tech. Rep., 2022.

[34] M. A. Gerzon, "Multi-system ambisonic," *Wireless World*, vol. 83, pp. 43–47, 1977.

[35] R. Michon, M. Ducceschi, P. Cochard, T. Skare, C. J. Webb, and R. Russo, "Evaluating cpu, gpu, and fpga performance in the context of modal reverberation: A comparative analysis," *Frontiers in Signal Processing*, 2025, Paper under review.