# Analysis of Imbalance in Input-Series Output-Parallel Configuration of Series Resonant Converters

Minho Kwon, Yujong Jeon, Jong-Pil Lee

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Minho Kwon, Yujong Jeon, Jong-Pil Lee. Analysis of Imbalance in Input-Series Output-Parallel Configuration of Series Resonant Converters. The 26th European Conference on Power Electronics and Applications, GDR SEEDS France & EPE Association, Mar 2025, Paris, France. 10.34746/epe2025-0104. [hal-05089008](https://wwwHAL.fr/hal-05089008)

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Distributed under a Creative Commons Attribution 4.0 International License
# Analysis of Imbalance in Input-Series Output-Parallel Configuration of Series Resonant Converters

Minho Kwon, Yujong Jeon and Jong-pil Lee
Korea Electrotechnology Research Institute (KERI)
Gwangju-si, Korea (south)
Tel.: +82-62-606-7274
E-Mail: mhkwon@keri.re.kr

## Acknowledgements

This work was supported by Korea Institute of Energy Technology Evaluation and Planning (KETEP) grant funded by the Korea government (MOTIE) (20225500000090, Advanced Control & Protection Platform for Multi-terminal MVDC System and Engineering Design Protocol).

## Keywords

«DC-DC converter», «Medium voltage», «LVDC», «Resonant converter», «Modular converter».

## Abstract

This paper analyses the power imbalance in input series output parallel (ISOP) configurations of series resonant converters (SRC), which are crucial for MVDC to LVDC conversion where electrical isolation and bidirectional operation are required. The dual active bridge (DAB)-based ISOP structure presents a promising solution, but it requires careful management of power distribution among modules to prevent imbalances. This study provides analysis on imbalance among SRC modules for a partial power control method, which contributes to reducing communication costs and complexity by minimizing the number of active control modules. Experimental results with two prototype SRC modules validate the theoretical analysis, demonstrating that power imbalances are negligible in the ISOP configuration.

## Introduction

Recently, significant advancements in power semiconductor and power electronics technology have spurred active research into utilizing transmission and distribution lines as DC systems. Among these, power conversion between MVDC and LVDC requires bidirectional operation and electrical isolation. To meet these requirements,

the input series output parallel (ISOP) structure of DAB-based isolated DC-DC converters, as shown in Fig. 1, is a promising candidate [1]-[5].

The modulation techniques for DAB-based DC-DC converters primarily use phase shift (PS), which transmits power by utilizing the phase difference between the primary and secondary sides with a 50% duty cycle based on PWM. Additionally, various modulation techniques such as dual phase shift (DPS), triple phase shift (TPS), and PWM plus phase shift (PPS) exist to reduce switching losses and expand the voltage range. When operating in an ISOP structure with DAB, tight active current sharing techniques among modules are required. While high-speed communication can cover this when the number of modules is relatively small, as voltage increases and higher capacity is needed, more modules are required. As the number of modules grows, the cost of communication setup increases significantly, and the increased complexity may lead to reduced reliability.

For this reason, a partial power control method has been proposed [1]-[4], which uses a resonant converter with a fixed gain DCX [6]-[10] to handle most of the power, with only a few

<figure><img src="image_2.png" /><figcaption>Fig. 1. DAB based ISOP dc-dc converter for MVDC-to-LVDC conversion.</figcaption></figure>
<figure><img src="image_3.png" /><figcaption>Fig. 2: Topology of SRC</figcaption></figure>

<figure><img src="image_4.png" /><figcaption>Fig. 3: the voltage gain curve of a module of SRC</figcaption></figure>

modules performing the regulation role. This proposed method results in minimal switching losses since the resonant converter is designed and operated at its optimal point, and power imbalance between DCXs can be kept very small without special control. Therefore, the number of active control modules is reduced, significantly lowering communication costs. This paper analyzes power imbalance among DCXs in an ISOP structure. The imbalance factors and causes were examined through theoretical analysis of the input-output parallel structure and the ISOP structure, and the validity of this paper was verified through experimental results with two prototype DCX modules.

## A series resonant converter

A dual active bridge based SRC is shown in Fig. 2. All switches are operate at half duty cycle. The gating of S4 is synchronized with S1. The switches S2 and S3 are from a pair, and their gating is symmetrically complementary with S1. The secondary side switches (S5, S6, S7 and S8) are used for synchronous rectifing. When the power flow changes direction from secondary to primary, the secondary switches operate as active switches, and the primary switches (S1, S2, S3 and S4) are taken over the role of synchronous rectification, and vice versa. In this paper, the active switches are defined as an inverter bridge, and the

<figure><img src="image_5.png" /><figcaption>Fig. 4: Key waveforms in below region.</figcaption></figure>

<figure><img src="image_6.png" /><figcaption>Fig. 5: Key waveforms in above region.</figcaption></figure>

synchronous rectifing switches are defined as a rectifier bridge.

The voltage gain of a module can be obtained by the fundamental harmonic approximation as follows:

$$G = \frac{V_L}{V_m} = N \cdot \frac{1}{1 + j \frac{\pi^2}{8} Q\left(\frac{\omega_s}{\omega_r} - \frac{\omega_r}{\omega_s}\right)} \quad (1)$$

where $V_L$ is LV side voltage, $V_m$ is MV side voltage of the module, N is the transformer turn ratio and $\omega_s$ is switching angular frequency. The resonant angular frequency is determined by resonant inductance ($L_r$) and capacitance ($C_r$) as follows:

$$\omega_r = \frac{1}{\sqrt{L_r C_r}}, \quad (2)$$
<figure><img src="image_7.png" /><figcaption>Fig. 6: IPOP connection (a) MV side parallel. (b) MV side series.</figcaption></figure>

<figure><img src="image_8.png" /><figcaption>Fig. 7: ISOP (a) MV side parallel. (b) MV side series.</figcaption></figure>

and quality factor is defined as follows:

$$Q = \frac{N^2 \omega_r L_r}{R_L} \qquad (3)$$

where $R_L$ is LV side load. The input impedance seen from inverter side is as follows:

$$Z_{in} = R_L \left( \frac{8}{\pi^2} + jQ \left( \frac{\omega_s}{\omega_r} - \frac{\omega_r}{\omega_s} \right) \right). \quad (4)$$

Operating an SRC at fixed frequency PWM can offer various advantages such as a simple controller, optimal transformer design, and less influence from tolerance of resonant components, at the cost of giving up itself regulation function [6]. Fig. 3 shows the voltage gain curve of a module of an SRC. The switching frequency is preferably close to the resonant frequency in order to reduce voltage gain deviation depending on load conditions. The switching frequency can be selected either above or below the resonant frequency. Fig. 4 shows the key waveforms in the below region. In this case, all switches can be achieved ZVS turn-on, furthermore, turn-off current of inverter side switches can be minimized by using magnetizing inductance of the transformer. However, the gating signals for synchronous rectifying are not the same as those of the inverter side. This difference is determined by the load condition, thus, an active control scheme is required to achieve synchronous rectification switching [11]. Fig 5 shows the key waveforms in the above region. In this case, also, all switches can be achieved ZVS turn-on, but

turn-off loss is greater than the below region. However, it is not significantly higher when the switching frequency is closed to the resonant frequency. Besides, when switching in the above region, synchronous rectifying can be achieved by identical gating signals for both the inverter and rectifier side switches (the same dead-time, duty and phase). To ensure seamless transition of the direction of power flow, the switching pattern of the inverter side and rectifier side should be the same. Accordingly, although the turn-off current is a bit higher than when operating in below region, the control system is simplified. Especially in a multi modular system as in this application, a simple controller is a significant advantage.

## Analysis on parallel

The voltage gains for multiple modules inevitably have mismatches due to manufacturing tolerances in the resonant components. Thus, (1) can be rewritten as follows:

$$g_k = \frac{1}{1 + j \frac{\pi^2 \omega_{rk} L_{rk} I_k}{8V_L} \cdot \left( \frac{\omega_s}{\omega_{rk}} - \frac{\omega_{rk}}{\omega_s} \right)} \quad (5)$$

where the subscript k is the index number of modules. The mismatched gains can be reduced by designing smaller resonant inductance[6]. However, it is not zero. An input parallel output parallel (IPOP) connection of two modules is shown in Fig. 6. Its equivalent circuit can be
<figure><img src="image_9.png" /></figure>

<figure><img src="image_10.png" /><figcaption>Fig. 8: Imbalance in case of IPOP (a) LV side current according to $\Delta G$ (b) current difference according to $R_{line}$.</figcaption></figure>

expressed as shown in Fig. 6(b). The output currents of each module can be obtained, respectively, as follows:

$$I_1 = \frac{g_1 V_{m1} (R_L + R_{line}) - g_2 V_{m2} R_L}{2 R_L R_{line} + R_{line}^2} \quad (6)$$

$$I_2 = \frac{g_2 V_{m2} (R_L + R_{line}) - g_1 V_{m1} R_L}{2 R_L R_{line} + R_{line}^2} \quad (7)$$

where $R_{line}$ is line impedance, $R_L$ is a load on the LV side and $V_M$ is the MV side voltage and equals $V_{m1}$ and $V_{m2}$. In this case, the difference between the module currents can be obtained as follows:

$$\Delta I = \Delta G \frac{V_M}{R_{line}} \quad (8)$$

where $\Delta I = I_1 - I_2$ and $\Delta G = g_1 - g_2$. From (8), it is evident that $\Delta I$, which represents imbalance, is directly proportional to $\Delta G$, and the imbalance dramatically rises under conditions of smaller line impedance.

Fig 8 shows the imbalance in the case of IPOP. The voltage on both sides are the same as each other because they share a common node. But the current difference gradually increases as the gain mismatch rises, as shown in Fig. 8(a). The current

<figure><img src="image_11.png" /><figcaption>Fig. 9: MV side voltage difference of ISOP.</figcaption></figure>

<table><caption>Table I: Calculation specification</caption><thead><tr><th>Parameters</th><th>Symbols</th><th>Values</th></tr></thead><tbody><tr><td>LV side voltage</td><td>V<sub>L</sub></td><td>750V</td></tr><tr><td>LV side load resistance</td><td>R<sub>L</sub></td><td>14 Ω</td></tr><tr><td>Line impedance</td><td>R<sub>line</sub></td><td>0.1 Ω</td></tr><tr><td>Voltage gain of stack#1</td><td>g<sub>1</sub></td><td>0.99</td></tr><tr><td>Voltage gain of stack#2</td><td>g<sub>2</sub></td><td>~ 0.98</td></tr></tbody></table>

difference dramatically increases under low line impedance conditions as shown in Fig. 8(b). An equivalent circuit for the LV side parallel and the MV side series connection of two modules is shown in Fig. 4(b) where the input impedance seen from the MV side is as follows:

$$Z_{ink} = \frac{8R_L}{\pi^2 g_k} \quad (9)$$

The MV side voltage for a module is determined by the input impedances as follows:

$$V_{mk} = \frac{Z_{ink}}{Z_{in1} + Z_{in2}} V_M \quad (10)$$

In the case of ISOP, the difference between the module currents can be obtained using (6), (7) and (10) as follows:

$$\Delta I = \frac{g_1 Z_{in1} - g_2 Z_{in2}}{R_{line}} \cdot \frac{V_M}{Z_{in1} + Z_{in2}} \quad (11)$$

From (11), we can see that $\Delta I$ is mathematically zero. Thus, the LV side current between modules is balanced. However, this does not imply balanced power due to the unbalanced voltage on the MV side. The voltage imbalance is determined by the mismatched input impedance which is expressed as follows:

$$\Delta Z_{in} = - \frac{4R_L \Delta G}{\pi^2 g_1 g_2} \quad (12)$$
<figure><img src="image_12.png" /><figcaption>Fig. 10: Self balancing principle for two SRC module in ISOP.</figcaption></figure>

<figure><img src="image_13.png" /><figcaption>Fig. 11: Two laboratory DCX prototypes.</figcaption></figure>

<figure><img src="image_14.png" /><figcaption>Fig. 12: Voltage gain curves of two different prototypes.</figcaption></figure>

where $\Delta Z_{in} = Z_{in1} - Z_{in2}$. Thus, the voltage difference is as follows:

$$ \Delta V_m = - \frac{4R_L I_M \Delta G}{\pi^2 g_1 g_2} \quad (13) $$

The important thing to note is that the line impedance has no effect, unlike in the case of parallel connection on both sides. Additionally, the voltage mismatch on the MV side is rarely observed in Fig. 9. This indicates that the power mismatch can be managed without an active control scheme.

Fig. 10 shows the self-balancing principle for two SRC modules in ISOP. If $I_1$ increases for any

<figure><img src="image_15.png" /><figcaption>(a)</figcaption></figure>

<figure><img src="image_16.png" /><figcaption>(b)</figcaption></figure>

<caption>Fig. 13: Resonant current and switch voltage of (a) Stack #1 (b) Stack #2.</caption>

<table><caption>Table II: Resonant parameters</caption><thead><tr><td>Module</td><td>L<sub>r</sub></td><td>C<sub>r</sub></td></tr></thead><tbody><tr><td>Stack #1</td><td>2.4 µH</td><td>4 µF</td></tr><tr><td>Stack #2</td><td>2.2 µH</td><td>8 µF</td></tr></tbody></table>

<table><caption>Table III: Specification of Experimental</caption><thead><tr><td>Parameters</td><td>Symbols</td><td>Values</td></tr></thead><tbody><tr><td>MV side voltage</td><td>V<sub>m</sub></td><td>100V</td></tr><tr><td>LV side voltage</td><td>V<sub>L</sub></td><td>100V</td></tr><tr><td>LV side load resistance</td><td>R<sub>L</sub></td><td>14 Ω</td></tr><tr><td>Switching frequency</td><td>f<sub>s</sub></td><td>49kHz</td></tr><tr><td>Dead-time</td><td>T<sub>dead</sub></td><td>1.3µs</td></tr></tbody></table>

reason, it means that the load resistance for the that module is decreasing. This leads to a reduction in its input impedance as shown in (4).

## Experimental results

To validate the analysis in this paper, two SRC modules with identical specifications have used as shown in Fig 11, and the specifications of the resonant components for each module are listed in Table II. The resonant inductance $L_r$ has utilized the leakage inductance of the transformer. The difference in $L_r$ is due to manufacturing
<figure><img src="image_17.png" /></figure>

<figure><img src="image_18.png" /><figcaption>Fig. 14: Experimental results of IPOP.</figcaption></figure>

tolerance. The difference of $C_r$ is intentional to clearly demonstrate the imbalance. The switching frequency is 49kHz for both stack, but the effective switching frequency, considering the dead-time, is approximately 51kHz. The different gain curves is plotted in Fig. 12. The effective switching frequency considering dead-time $T_{dead}$ can be expressed as follows:

$$f_e = \frac{f_s}{1 - 2T_{dead}f_s} \qquad (14)$$

Although the first stack operates near the resonant frequency, the resonant frequency of the second stack is about 36kHz, which is significant different from the switching frequency. As a result, the difference in voltage gain between the two stacks is approximately 0.03 at the effective switching frequency. Fig. 13 shows the experimental waveforms for each stack, including the resonant current and drain-source voltage of the switch. The resonant current of the first stack, which operates very close to the resonant frequency, displays an almost sinusoidal waveform. In contrast, the resonant current of the second stack exhibits switching before the completion of a half-cycle sinusoidal waveform.

The experimental results shown in Figs. 14 and 15 depict the resonant currents of the two modules. In both tests, a 90° phase shift was applied between the modules to achieve the interleaving effect. Fig. 14 represents the IPOP condition, where a significant difference between

<figure><img src="image_19.png" /></figure>

<figure><img src="image_20.png" /><figcaption>Fig. 15: Experimental results of ISOP.</figcaption></figure>

the two resonant currents can be observed. In contrast, Fig. 15 shows the ISOP condition, where, despite the noticeable differences in the shape of the resonant currents, the differences in the peak and RMS values of the two resonant currents are minimal.

## Conclusion

In this paper, we provided an analysis and experimental results on the imbalance between modules when using SRC in ISOP configuration. To offer a clearer comparison, we also included analysis and experimental results for the IPOP configuration. As demonstrated by the analysis and experimental results, the ISOP configuration does not lead to power imbalance between modules, even with significant discrepancies in the resonant component tolerances. Therefore, this structure is highly suitable for applications with high step up/down, such as MVDC/LVDC converters. Future research will focus on proposing the optimal structure and control methods for partial power regulation.

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