# Performance Evaluation of Three-Phase, Two-Level Medium Voltage Power Stack Based on 10 kV SiC MOSFETs

Morten Rahr Nielsen, Martin Kjaer, Gao Liu, Zhixing Yan, Asger Bjørn Jørgensen, Hongbo Zhao, Michael Møller Bech, Stig Munk-Nielsen

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## To cite this version:

Morten Rahr Nielsen, Martin Kjaer, Gao Liu, Zhixing Yan, Asger Bjørn Jørgensen, et al., Performance Evaluation of Three-Phase, Two-Level Medium Voltage Power Stack Based on 10 kV SiC MOSFETs. The 26th European Conference on Power Electronics and Applications, GDR SEEDS France & EPE Association, Mar 2025, Paris, France. 10.34746/epe2025-0134. hal-05099127

HAL Id: hal-05099127

https://utc.hal.science/hal-05099127v1

Submitted on 5 Jun 2025

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Distributed under a Creative Commons Attribution 4.0 International License
# Performance Evaluation of Three-Phase, Two-Level Medium Voltage Power Stack Based on 10 kV SiC MOSFETs

Morten Rahr Nielsen, Martin Kjær, Gao Liu, Zhixing Yan, Asger Bjørn Jørgensen, Hongbo Zhao, Michael Møller Bech, and Stig Munk-Nielsen

AAU Energy / Aalborg University
Pontoppidanstræde 111, Aalborg, Denmark
E-Mail: mrni@energy.aau.dk

## ACKNOWLEDGMENT

The authors thank the research project Competitive Electrolyzer Converter (ComElCo), a project within Mission Green Fuels funded by The Innovation Fund Denmark (1150-00001B), for its economic funding.

*Index Terms*—Silicon Carbide (SiC), MOSFET, Wide Bandgap, Medium Voltage Converter, Power Losses.

*Abstract*—The performance of a 50 kVA three-phase, two-level medium voltage power stack based on 10 kV SiC MOSFETs has been evaluated under varying load conditions, i.e. voltage- and current-levels, coolant temperatures, and switching frequencies. A calorimetric measurement method is applied to estimate the power stack losses and its equivalent power stack efficiency. Experimental results from an inductive load test setup show an equivalent power stack efficiency of 98.8% ± 0.56% at 6 kV DC-link voltage, 10 kHz switching frequency, and 40°C coolant temperature with a maximum MOSFET junction temperature of less than 115°C and thermal resistance of 0.38 K/W.

## I. INTRODUCTION

Efficiency of power electronic converters (PEC) is a key performance indicator used to compare and benchmark different converter designs; however, often, efficiencies are reported as single standalone numbers without any consideration given to the method or measurement accuracy. With the utilization of wide bandgap (WBG) semiconductor devices, the efficiency of PECs is elevated due to the improved material properties of WBG materials compared to the conventional silicon (Si) material [1]–[4].

Medium voltage (MV) PECs based on 10 kV silicon-carbide (SiC) MOSFETs are still in their early maturing phase, limiting the existing literature to electrical characterization of power modules [5]–[10] and single point

evaluations on stack-level [11]–[15]. As a result, accurate estimation of power losses on module- and stack-level poses a challenge with efficiencies reported above 99% in the existing literature [12]–[14].

Currently, two traditional power loss methods exist based on either electrical or calorimetric measurements [16]. Power loss estimation based on electrical measurements is either directly measured with a power analyzer or indirectly estimated through electrical power module characterizations. In power loss methods based on calorimetric measurements, the device under test is typically placed in a calorimetric chamber, where the heat transfer from the device to the coolant is used as an estimator of the power loss [16]. A comparison between the calorimetric and electrical measurement methods is outside the scope of this paper as this was previously covered in detail in [17].

This paper evaluates the performance of a 50 kVA three-phase, two-level MV power stack based on 10 kV SiC MOSFET under varying load conditions. The power stack performance is evaluated with DC-link voltages ranging from 1 to 6 kV, while sweeping the RMS currents from zero to 7 A at switching frequencies of 5 and 10 kHz and coolant temperatures of 20 and 40°C. The experimental results are used to quantify the rated operation conditions of the power stack.

## II. CALORIMETRIC POWER LOSS ESTIMATION

Power loss estimation based on calorimetric measurements is a convenient, simple, and cheap method, which only requires a few additional components and little to no calibration beforehand [16].

### A. Water Cooling System

The water cooling system consists of a standalone refrigerated/heating laboratory circulator, a calorimetric measurement unit (CMU), and a liquid-cooled heatsink
<figure><img src="image_3.png" /><figcaption>Fig. 1: Schematic of water cooling system and junction temperature measurement unit.</figcaption></figure>

housing the three-phase power stack. In addition to the water cooling system, an optic temperature unit is used for direct junction temperature measurements. A schematic of the water cooling system together with the temperature measurement unit is shown in Fig. 1.

The standalone refrigerated/heating laboratory circulator is a Julabo Corio CD-1000F with a cooling capacity of 1 kW, heating capacity of 2 kW, internal bath with a volume of 7.5 L, and pump flow capacity of 15 L/min [18]. The laboratory circulator uses Julabo Thermal G as cooling liquid, which is a water-glycol-based bath fluid with a working temperature of -30°C to 80°C, density of 1.07 g/cm³ at 20°C, and specific heat capacity of 3.34 kJ/(kg·K) at 20°C [19].

The CMU is a Kamstrup Multical 403 with integrated flow and Pt500 temperature sensors intended for district heating in residential and commercial buildings [20]. Flow and temperature sensors are located close to the in- and outlets of the heatsink to reduce the heat transfer to the ambient from the hoses. The Pt500 temperature sensors used for liquid temperatures typically have an accuracy of ±1.0 K. The CMU is targeted at a 500 kVA power stack based on multiple 10 kV SiC MOSFET power modules, which inevitably impacts the accuracy of the CMU when utilized for the 50 kVA power stack due to lower flow and temperature operating points.

The temperature unit utilized for die surface measurements is an OpSens CoreSens with OTG-F fiber optic temperature sensors [21] with an accuracy of ±0.8 K. The power module is encapsulated with silicone-gel, which through built-in pipettes in the power module leaves direct access to the surface of the low-side (LS) and high-side (HS) SiC MOSFET dies for one-point measurements as shown in Fig. 2.

Dominating loss contributors are explicitly included in Fig. 1, with the main loss contributors being the three half-bridge, single die power modules, $P_{module,x}$,

of phase A, B, and C, constituting the power stack losses, $P_{stack}$. The power modules are assumed to only have a heat transfer to the cooling liquid; however, with a temperature difference between the heatsink of the water cooling system and the surrounding ambient air, a heat transfer between the two media is unavoidable and denoted $P_{cool2amb}$. The power stack losses can be found from the measured heat transfer of the CMU, $P_{CMU}$, after correcting and calibrating for the heat transfer from/to the ambient air as shown in (1).

$$ 
\begin{aligned}
P_{stack}(Q, \Delta T) &= P_{CMU}(Q, \Delta T) - P_{cool2amb}(Q, \Delta T_0) \\
&= Q \cdot \rho \cdot C \cdot (\Delta T - \Delta T_0)
\end{aligned} 
\qquad (1) $$

where Q is the liquid flow rate in L/s, ρ is the density of the cooling liquid in g/L, C is the specific heat capacity of the cooling liquid in J/(g·K), and ΔT and ΔT₀ being the temperature difference between T₀ and Tᵢₙ during operation and calibration, respectively. Before each measurement series, the heat transfer, $P_{cool2amb}$, can be estimated with the power stack turned off to limit the impact of fluctuating environmental conditions.

<figure><img src="image_4.png" /><figcaption>Fig. 2: Photograph of built-in pipettes in the power module for one-point junction temperature measurements.</figcaption></figure>
<figure><img src="image_5.png" /><figcaption>Fig. 3: Relative uncertainty of calorimetric measurement unit (i.e. Kamstrup MULTICAL 403) at several power loss curves.</figcaption></figure>

## B. Measurement Uncertainty

When reporting numbers on power losses and efficiencies for PECs, the accuracy of measurement equipment needs to be considered. In this case, the manufacturer explicitly states the relative error of the CMU, $\delta E_{CMU}$, as individual errors for each of the measurement components [20] as shown in (2).

$$ \begin{aligned} \delta E_{CMU}(Q, \Delta T) &= \delta E_c(\Delta T) + \delta E_f(Q) + \delta E_t(\Delta T) \\ &= (0.15 + 2/\Delta T) + (1 + 0.01q_p/Q) \\ &\quad + (0.4 + 4/\Delta T) \end{aligned} \qquad (2) $$

where $\delta E_c$, $\delta E_f$, and $\delta E_t$ are the relative measurement errors of the Kamstrup MULTICAL 403 calculator, flow sensor, and temperature sensors, respectively, and $q_p$ is the maximum flow rate of 1500 L/h.

With the use of both (1) and (2), the relative error of the CMU can be mapped out for different power stack losses as shown in Fig. 3. The 500 kVA power stack is expected to have an efficiency of around 99%, which results in power stack losses of 5 kW, from which the trajectory can be seen to traverse through uncertainties ranging from 2.0% to 2.5%. However, for the 50 kVA power stack under investigation in this paper, the 0.5 kW trajectory traverses through uncertainties ranging from 2.9% to 7.6% depending on the flow rate. Therefore, a relatively low flow rate of 150 L/h is targeted for the 50 kVA power stack to obtain an uncertainty of less than 3.5% at 0.5 kW of power stack losses.

As the power stack losses are found from two individual readings from the CMU as shown in (1), the total absolute uncertainty of the power stack losses, $E_{stack}$, are the sum of the absolute errors from both the CMU, $E_{CMU}$, and the calibration, $E_{cool2amb}$, according to the rules of propagation of errors for subtrac-

<figure><img src="image_6.png" /></figure>

<figure><img src="image_7.png" /><figcaption>Fig. 4: Photographs from the experimental test setup. (a) Three-phase inductive load test setup and power stack, (b) calorimetric measurement unit (CMU), and (c) standalone refrigerated/heating laboratory circulator.</figcaption></figure>

<figure><img src="image_8.png" /><figcaption>Fig. 5: Schematic of inductive load test setup.</figcaption></figure>

tion/addition [22] as shown in (3).

$$ \begin{aligned} E_{stack}(Q, \Delta T) &= E_{CMU}(Q, \Delta T) + E_{cool2amb}(Q, \Delta T_0) \\ &= \delta E_{CMU}(Q, \Delta T) \cdot P_{CMU}(Q, \Delta T) \\ &\quad + \delta E_{cool2amb}(Q, \Delta T_0) \cdot P_{cool2amb}(Q, \Delta T_0) \end{aligned} \qquad (3) $$

where $\delta E_{cool2amb}$ is the relative error of the calibration.

## III. EXPERIMENTAL SETUP AND RESULTS

The 50 kVA power stack consists of three half-bridge, single die power modules [23] populated with
<figure><img src="image_9.png" /><figcaption>Fig. 6: Electrical measurements at 6 kV, 7 A RMS, and 10 kHz at a cooling liquid of 40°C. Experimental (a) phase currents, (b) phase voltages, and (c) gate-source voltages of phase A.</figcaption></figure>

3rd generation 10 kV, 20 A, 300 mΩ SiC MOSFET dies from Wolfspeed [24]. The power stack has dimensions of 19 x 30 x 100 cm, which gives a total volume of 57 L and a power density of 0.88 kVA/L. The power stack

<figure><img src="image_10.png" /><figcaption>Fig. 7: Experimentally measured phase A voltage dv/dt throughout a fundamental period. Measurements at a junction temperature of 55°C are captured during continuous operation at a switching frequency of 5 kHz and 20°C cooling liquid, while the 110°C's are captured at 10 kHz and 40°C from the waveforms shown in Fig. 6.</figcaption></figure>

is evaluated in a three-phase inductive load test setup, comprising of the three-phase power stack, a control unit, three 30 mH MV load inductors, and two 2 kW, 10 kV power supplies from Magna-Power Electronics, XR10000-0.2, as shown in Fig. 4 and Fig. 5.

Three-phase voltage vectors, $v_{abc}^*$, are applied to the power stack in open-loop as in (4) to operate it continuously until thermal equilibrium is obtained. Thermal equilibrium is obtained when calorimetric and thermal measurements have been constant for a minute.

$$v_{abc}^* = V_0 \cdot \cos(\omega t) + V_L \cdot \cos(\omega t + \theta) \quad (4)$$

where $V_0$ is a constant, zero sequence voltage vector of 20% of the DC-link voltage, $V_L$ is the magnitude of the positive sequence voltage vectors, and $\theta$ is 0, $-2\pi/3$, and $2\pi/3$ for phase A, B, and C, respectively. After obtaining its thermal equilibrium, the electrical, thermal, and calorimetric quantities have been captured with the oscilloscope, temperature unit, and CMU, respectively.

Measurements performed under varying DC-link voltages, $V_{DC}$, and RMS phase currents, $i_{abc}$, ranging from 1 to 6 kV and zero to 7 A have been carried out for switching frequencies of 5 and 10 kHz with coolant temperatures of 20 and 40°C. As an example, the electrical measurements during load conditions of 6 kV, 7 A RMS, 10 kHz, and 40°C are shown in Fig. 6. The measured three-phase currents are shown in Fig. 6(a), in which the 50 Hz fundamental component is overlaid with a distinct, asymmetrical high-frequency component at the switching frequency due to parasitic capacitances within the system. The asymmetry is due to the change in phase voltage $dv/dt$ throughout a fundamental current period as shown in Fig. 7 in accordance with [25]. To evaluate
<figure><img src="image_11.png" /><figcaption>(a)</figcaption></figure>

<figure><img src="image_12.png" /><figcaption>(b)</figcaption></figure>

<figure><img src="image_13.png" /><figcaption>(a)</figcaption></figure>

<figure><img src="image_14.png" /><figcaption>(b)</figcaption></figure>

<caption>Fig. 9: Experimental results at 40°C cooling liquid and 5 kHz switching frequency - Case 2. (a) Total power stack losses and (b) maximum junction temperatures.</caption>

the quality of the phase currents, the total harmonic distortion (THD) for the first 50 harmonics has been evaluated to 1.50% in average per phase using (5) with the most predominant being the 5th and 7th harmonics.

$$THD_{50} = 100 \cdot \frac{\sqrt{\sum_{n=2}^{50} i_{n,rms}^2}}{i_{1,rms}} \quad (5)$$

where $i_{n,rms}$ is the individual harmonic components.

The measured three-phase voltages are shown in Fig. 6(b) together with the estimated three-phase voltages, $v_{abc}^*$, found from averaging the measured three-phase voltages over one switching period. The voltage vectors have a peak zero sequence component of 1.2 kV (20% of the DC-link voltage) and positive sequence

component of around 100 V in accordance with (4) for an inductance of 30 mH and peak phase current of 10 A.

The measured gate-source voltages for phase A are shown in Fig. 6(c), in which three zoomed views at approx. -10 A, zero, and 10 A of phase currents are shown with indicators of the presence of Miller plateaus for the turn-on switching event of the HS and LS SiC MOSFETs. The absence of a Miller plateau indicates a zero-voltage switching event, which inevitably reduces the turn-on switching losses. From Fig. 6(c), it is apparent that no zero-voltage switching events happen around low magnitudes of phase currents.

The experimentally measured power stack losses and junction temperatures obtained with a switching frequency of 5 kHz at a coolant temperature of 20 and 40°C are shown in Fig. 8 and Fig. 9, respectively. Trendlines
<figure><img src="image_15.png" /><figcaption>(a)</figcaption></figure>

<figure><img src="image_16.png" /><figcaption>(b)</figcaption></figure>

Fig. 10: Experimental results at 20°C cooling liquid and 10 kHz switching frequency - Case 3. (a) Total power stack losses and (b) maximum junction temperatures.

<figure><img src="image_17.png" /><figcaption>(a)</figcaption></figure>

<figure><img src="image_18.png" /><figcaption>(b)</figcaption></figure>

Fig. 11: Experimental results at 40°C cooling liquid and 10 kHz switching frequency - Case 4. (a) Total power stack losses and (b) maximum junction temperatures.

have been included based on the measurements from 1 to 7 A with the equation of the trendlines shown at 6 kV DC-link voltage. Measurements made at zero current show increased power stack losses and junction temperatures in all tests as all switching events are performed under hard-switching as shown in Fig. 6(c). Similar trendlines are seen when cross-comparing the power stack losses and delta junction temperatures at both coolant temperatures; however, interestingly the results reveal a slight decrease in the switching losses at a coolant temperature of 40°C, whereas the conduction losses are elevated due to higher junction temperatures and on-state resistances of the SiC MOSFETs. The maximum delta junction temperature shown in the figures is of the HS SiC MOSFET, knowing that the HS SiC MOSFET will have the highest junction temperature due to its increased turn-on energy [25].

Likewise, the experimentally measured power stack losses and junction temperatures obtained with a switching frequency of 10 kHz at a coolant temperature of 20 and 40°C are shown in Fig. 10 and Fig. 11, respectively. At an elevated switching frequency, a similar pattern is seen in terms of trendlines and observations with slightly lower switching losses and increased conduction losses at higher coolant temperatures.

All the measured power stack losses and MOSFET junction temperatures are used to estimate a steady-state thermal resistance as shown in Fig. 12. The estimation assumes an equal distribution of losses in each of the three power modules and a fixed inlet temperature, $T_{in}$, of 20 or 40°C. A slight difference in thermal resistance is observed among the tests performed at coolant temperatures of 20 and 40°C, which are estimated to 0.38 K/W and 0.35 K/W, respectively.
<figure><img src="image_19.png" /><figcaption>Fig. 12: Estimation of steady-state thermal resistance from measured power module losses and maximum high-side MOSFET junction temperature.</figcaption></figure>

<figure><img src="image_20.png" /><figcaption>Fig. 13: Experimental results at 6 kV DC-link voltage. (a) Total power stack losses and (b) equivalent power stack efficiencies.</figcaption></figure>

In summary, a direct comparison of the power stack losses among all tests at 6 kV DC-link voltage is shown in Fig. 13(a). The total absolute uncertainty of the power stack losses, $E_{stack}$, are found from (3) and shown as error bars in the figure, ranging between 19 to 30 W. The x-axis has been converted into an equivalent apparent power using an AC voltage of 4.16 kV to estimate an equivalent power stack efficiency as shown

in Fig. 13(b) for all tests. Common among all tests, the efficiency seems to peak around an equivalent apparent power of 45 kVA. The summary is tabulated in Table I, highlighting the key metrics from all four tests. In conclusion, case 4 with a switching frequency of 10 kHz at a coolant temperature of 40°C is deemed the rated operation conditions of the 50 kVA power stack with an equivalent efficiency of 98.8% ± 0.56‰ at a maximum junction temperature of 112.2°C ± 1.8°C and thermal resistance of 0.38 K/W.

All of the presented measurements are performed with an external gate resistance of 45 Ω to obtain a maximum $dv/dt$ during turn-on switching events of 30 V/ns and turn-off switching events of 55 V/ns throughout all tests. In addition, all measurements are performed under ambient room temperatures ranging from 22.0 to 24.0°C used to adjust the calibration data, $P_{cool2amb}$, from (1) before performing each measurement series to obtain accurate power stack losses.

## IV. CONCLUSION

The performance of the 50 kVA three-phase, two-level MV power stack based on 10 kV SiC MOS-FETs has been evaluated under varying load conditions throughout the paper. The power stack is evaluated at varying voltage- and current-levels with switching frequencies of 5 and 10 kHz at coolant temperatures of 20 and 40°C. At rated operation conditions of 10 kHz switching frequency and 40°C coolant temperature, the power stack obtains an equivalent power stack efficiency of 98.8% ± 0.56‰ at a maximum MOSFET junction temperature of 112.2 ± 1.8°C and an average phase current $THD_{50}$ of 1.50% at an equivalent power rating of 50 kVA. The power stack losses and equivalent power stack efficiencies are estimated using a calorimetric measurement method, which provides high measurement accuracy and simple integration with liquid-cooled heatsinks.

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<table><caption>TABLE I: Summary of experimental results at 6 kV and 7 A RMS from inductive load test setup.</caption><thead><tr><th></th><th>Switching frequency [kHz]</th><th>Coolant temperature [°C]</th><th>Avg. current THD<sub>50</sub> [%]</th><th>Power stack losses [W]</th><th>Max. junction temperature [°C]</th><th>Equivalent efficiency [% ± %c]</th></tr></thead><tbody><tr><td>Case 1†</td><td>5</td><td>20</td><td>1.23</td><td>309.8 ± 23.4</td><td>57.5 ± 1.8</td><td>99.4 ± 0.46</td></tr><tr><td>Case 2‡</td><td>5</td><td>40</td><td>1.19</td><td>313.4 ± 22.2</td><td>73.8 ± 1.8</td><td>99.4 ± 0.44</td></tr><tr><td>Case 3†</td><td>10</td><td>20</td><td>1.46</td><td>606.5 ± 29.3</td><td>95.9 ± 1.8</td><td>98.8 ± 0.58</td></tr><tr><td>Case 4‡</td><td>10</td><td>40</td><td>1.50</td><td>611.9 ± 28.4</td><td>112.2 ± 1.8</td><td>98.8 ± 0.56</td></tr></tbody></table>

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<footnote>†at a thermal resistance of 0.38 K/W.</footnote>

<footnote>‡at a thermal resistance of 0.35 K/W.</footnote>