# A Cost-Effective Three Level Shared Leg Flying Capacitor Converter for Switched Reluctance Motors

Ali Yousefi Darani, Nasir Ali, Mehdi Narimani

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Ali Yousefi Darani, Nasir Ali, Mehdi Narimani. A Cost-Effective Three Level Shared Leg Flying Capacitor Converter for Switched Reluctance Motors. The 26th European Conference on Power Electronics and Applications, GDR SEEDS France & EPE Association, Mar 2025, Paris, France. 10.34746/epe2025-0114. hal-05095968

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# A Cost-Effective Three Level Shared Leg Flying Capacitor Converter for Switched Reluctance Motors

Ali Yousefi Darani, Nasir Ali, Mehdi Narimani

MCMASTER UNIVERSITY

1280 Main St W, Hamilton, ON L8S 4L8

Tel.: +1 / (905) 525-9140.

E-Mail: yousea11@mcmaster.ca, alin49@mcmaster.ca, narimanm@mcmaster.ca.

URL: https://www.mcmaster.ca/.

## Acknowledgements

This research was undertaken, in part, thanks to funding and support from Enedym Inc, Natural Sciences and Engineering research Council of Canada (NSERC), and MITACS of Canada.

## Keywords

«Switched reluctance drive», «Multi-level inverter», «Three-phase motor drive», «Flying Capacitor Converter».

## Abstract

This paper presents a novel, cost-effective multilevel inverter for switched reluctance motor (SRM) drives. The proposed inverter has a three-level topology with shared-leg flying-capacitor (SLFC) structure. This topology utilizes two shared legs for adjacent phases during the magnetization, freewheeling, and demagnetization of the SRM. This innovative approach reduces the drive's size and cost by reducing the number of power switches, diodes, gate drivers, current and voltage sensors while achieving the same performance as the conventional three-level flying capacitor topology. In comparison to the conventional asymmetric half bridge converter, it improves the performance in terms of current ripple and reduces the voltage stress of some of semiconductors. The feasibility of the proposed three-level SLFC topology is verified through simulation studies based on a three-phase 12/16 SRM drive system.

## Introduction

The switched reluctance motor (SRM) have become an attractive area of interest in modern research due to their straightforward design, lack of permanent magnets, high reliability, and resilience in harsh conditions [1]–[3]. Despite these advantages, the inherent doubly salient

stator and rotor design of an SRM [4], combined with their highly nonlinear electromagnetic properties [5], results in significant torque ripples. Researchers have sought to enhance SRM performance through various methods, including optimizing the motor's physical structure [6], [7], introducing advanced control strategies such as differential flatness-based control [8], current chopping control (CCC) [9], and direct instantaneous torque control (DITC) [10], [11], and improving power converter designs [12]. The power converter plays a crucial role in the performance and cost of the drive system [13]. By enhancing power converter designs, the overall efficiency and applicability of SRM drives can be improved.

Traditionally, SRM drive systems have employed an asymmetric half-bridge (AHB) power converter [14], known for its phase independence, and fault-tolerant features. However, this converter is limited to providing only three voltage levels, which restricts the voltage at the winding terminals during magnetization or demagnetization to the DC power supply voltage. To overcome these issues. In [15], an innovative modular AHB driving topology that can function in both driving and charging modes to maintain the battery pack voltage level is proposed. Moreover, a cascaded multi-port converter has been proposed to improve excitation and demagnetization processes and enhance torque performance and efficiency [16].

Multi-level (ML) converters provide several benefits, such as lower voltage stress and operating frequency on switching devices, lower switching losses, and enhanced system stability. However, the implementation of ML converters necessitates a greater number of diodes and switches, adding complexity to system design and control. In [17], a T-type three-level converter to achieve a higher number of voltage levels is proposed, while a neutral point diode-clamped ML converter is developed in [18] to increase the
<figure><img src="image_2.png" /><figcaption>Fig.1 The proposed three-level SLFC converter.</figcaption></figure>

number of voltage levels However, in the converter in [17] there is a path through the parallel diode of the switches connected to the neutral point that may short circuit the input capacitors. The converter proposed in [18], provides independent control for each phase of SRM ; however, it requires a high number of semiconductors making the converter complex and costly.

To improve the motor performance, and at the same time reduce the cost, this paper introduces an innovative three-level shared-leg flying capacitor (SLFC) converter topology specifically designed for three-phase SRMs applications (Fig.1). Unlike the conventional FC converter shown in Fig.2, where each phase-leg is constituted of two flying capacitors, a voltage sensor, and a current sensor, the new design employs two shared legs for adjacent phases thereby eliminating number of power semiconductors, and sensors. The proposed three-level SRM drive could be a promising solution for low-cost industrial applications.

## Operational Principles of the Proposed Converter

The proposed three-level SLFC converter for three-phase SRM drives is illustrated in Fig. 1. In Fig. 1 C.T₁ and C.T₂ represent the current transducers needed for closed loop control. Six independent modes exist for each phase leg, as depicted in Fig. 3. For simplicity, it is assumed that all power devices in the topology are ideal devices. Table.I provides an illustration of the potential modes for the switches in one phase.

<figure><img src="image_3.png" /><figcaption>Fig.2 The conventional three-level FC converter.</figcaption></figure>

Furthermore, Table.I presents the capacitors voltages ($V_{C1}$, $V_{C2}$) corresponding to various modes.

Switch states are represented as 1 for ON and 0 for OFF, with symbols ↑, ↓, and × indicating increases, decreases, and no change in capacitor voltage, respectively. Initially, independent modes occurring in the single conduction region are discussed. The operation of the converter during phase commutation is then elaborated through common modes. The operation during the conduction of phase A, including its independent modes and common modes with the incoming phase B, is explained. Due to the symmetry of the converter, the operation of phases B and C is considered similar and is not repeated.

### A) Independent modes

**Mode 1 [Fig. 3(a)]:** The switches, $S_{1,2,3}$, are ON. The dc-link voltage, *E*, is applied to the phase winding and the load current flows through $S_1$, $S_2$ and $S_3$. The diodes $D_1$, $D_2$ and $D_3$ are reverse-biased. No current flows into the capacitor. Therefore, the capacitor voltage is unchanged in this mode. The phase voltage is equal to *E*.
<figure><img src="image_4.png" /><figcaption>Fig. 3 Independent operation modes of phase A.</figcaption></figure>

**Mode 2 [Fig. 3(b)]**: $S_2$ and $S_3$ are ON. $S_1$ is OFF. Diode $D_2$ is forward-biased, but $D_1$ and $D_3$ are reverse-biased. The load current flows through $C_1, S_2, S_3$ and $D_2$. Current flows out of the positive terminal of the capacitor $C_1$.

Therefore, the capacitor voltage decreases in this mode. The phase voltage is equal to $V_{C1}$.

**Mode 3 [Fig. 3(c)]**: $S_1, S_3$, and $D_1$ are ON. $S_2$ is OFF. Diode $D_1$ is forward-biased, but $D_2$ and $D_3$ are reverse-biased. The load current flows through $S_1, C_1, D_1$ and $S_3$. Current injects into the positive terminal of capacitor $C_1$. Therefore, the capacitor voltage increases in this mode. The phase voltage is equal to $V_{C1}$.

**Mode 4 [Fig. 3(d)]**: $S_1$, and $S_2$ are OFF and $S_3$ is ON. $D_1$, and $D_2$ are forward-biased but $D_3$ is reverse-biased. Load current free wheels through $S_3, D_1$ and $D_2$. No current is injected into the capacitor. Therefore, the capacitor voltage is unchanged in this mode. The phase voltage is 0.

**Mode 5 [Fig. 3(e)]**: $S_1$, and $S_2$ are ON and $S_3$ is OFF. $D_1$, and $D_2$ are reverse-biased and $D_3$ is forward-biased. Load current free wheels through $S_1, S_2$ and $D_3$. No current is injected into the capacitor. Therefore, the capacitor voltage is unchanged in this mode. The phase voltage is 0.

**Mode 6 [Fig. 3(f)]**: All the switches are turned OFF in this mode. Diodes $D_1, D_2$ and $D_3$ are forward-biased and the load current flows through them. No current is injected into the capacitor. Therefore, the capacitor voltage is unchanged in this mode. The phase voltage is equal to $-E$ which means that the current starts to decrease to zero.

## B) Common Modes

**Mode 7 [Fig. 4(a)]**: In this mode both phase's A and B are magnetized by E. $S_1, S_2, S_3, S_4$ and $S_5$ are ON and $S_6$ is OFF. All the diodes are reverse-biased. No current is injected into the capacitor. Therefore, the capacitor voltage is unchanged in this mode.

**Mode 8 [Fig. 4(b)]**: Both phases A and B are operating in freewheeling mode. Voltage of both phases is 0. $S_3$ is ON and the rest of the switches are OFF. $D_1, D_2, D_3$ and $D_4$ are forward-biased. No current is injected into the capacitor. Therefore, the capacitor voltage is unchanged in this mode.

**Mode 9 [Fig. 4(c)]**: This mode is also a freewheeling mode like mode 8. $S_1, S_2, S_4, S_5$ are ON and $S_3$ and $S_6$ are OFF and among diodes, only $D_3$ is forward biased.

**Mode 10 [Fig. 4(d)]**: In this mode also both phases of A and B are magnetized by the capacitors. $C_1$, and $C_2$ are charging since the current is injected into their positive terminal. $S_1, S_3$ and $S_4$ are ON and $D_1$ and $D_4$ are reverse-biased.

**Mode 11 [Fig. 4(e)]**: In this mode, capacitor voltages are applied to both phases of A and B. $C_1$, and $C_2$ are discharging since the current flows out of their positive terminal. $S_2, S_3$ and $S_5$ are ON and $D_2$ and $D_5$ are reverse-biased.

**Mode 12 [Fig. 4(f)]**: In this mode phase A is in freewheeling mode and phase B is magnetized with E.
<figure><img src="image_5.png" /><figcaption>Fig.4 Common operational modes of phase A.</figcaption></figure>

$S_3, S_4$ and $S_5$ are ON and the rest of the switches are OFF. $D_1$ and $D_2$ are forward-biased. No current is injected into the capacitor. Therefore, the capacitor voltage is unchanged in this mode.

**Mode 13 [Fig. 4(g)]:** In this mode phase A is in freewheeling mode and phase B is magnetized $V_{C2}$. $S_3, S_4$ are ON and the rest of the switches are OFF. $D_1, D_2$ and $D_4$ are forward-biased and $C_2$ is discharging.

**Mode 14 [Fig. 4(h)]:** The voltages applied to the phase A and B are like mode 13, but $C_2$ is charging in this mode. $S_3, S_5$ are ON and the rest of the switches are OFF. $D_1, D_2$ and $D_5$ are forward-biased.

**Mode 15 [Fig. 4(i)]:** In this mode phase A is demagnetizing with $E$ and phase B is in freewheeling mode. $S_4$ and $S_5$ are ON and the rest of the switches are OFF. $D_1, D_2$ and $D_3$ are forward-biased. No current is injected into the capacitor. Therefore, the capacitor voltage is unchanged in this mode.

In Fig. 5, a potential current waveform is presented, with the worst-case scenario assumed where the current waveform of each phase overlaps with those of other phases. The corresponding independent or common modes for each time interval of phase A are also shown to

track the current path. Initially, during the magnetization of phase A, phase C is operating. Since phase C does not share any current path with phase A, both phases operate in independent modes. When phase B begins to magnetize while phase A is still conducting, common modes between phases A and B occur until phase A is fully demagnetized and its current reaches zero. Additionally, specific modes affect the capacitor voltage differently: in modes 3, 10, and 13, the voltage increases as current flows into the capacitor's positive terminal, whereas in modes 2, 11, and 14, the voltage decreases as current flows out of the positive terminal.

<figure><img src="image_6.png" /><figcaption>Fig.5 A potential current waveform for the SRM using the proposed converter.</figcaption></figure>
<table><caption>Table I. Potential modes in one phase.</caption><thead><tr><th></th><th>Mode</th><th>S<sub>1</sub></th><th>S<sub>2</sub></th><th>S<sub>3</sub></th><th>S<sub>4</sub></th><th>S<sub>5</sub></th><th>V<sub>ph,A</sub></th><th>V<sub>ph,B</sub></th><th>V<sub>c1</sub></th><th>V<sub>c2</sub></th></tr></thead><tbody><tr><td rowspan="5">Independent Modes</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>E</td><td>0</td><td>×</td><td>×</td></tr><tr><td>2</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>E/2</td><td>0</td><td>↑</td><td>×</td></tr><tr><td>3</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>E/2</td><td>0</td><td>↓</td><td>×</td></tr><tr><td>4</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>×</td><td>×</td></tr><tr><td>5</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>×</td><td>×</td></tr><tr><td rowspan="7">Common Modes</td><td>6</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>-E</td><td>0</td><td>×</td><td>×</td></tr><tr><td>7</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>E</td><td>E</td><td>×</td><td>×</td></tr><tr><td>8</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>×</td><td>×</td></tr><tr><td>9</td><td>1</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>×</td><td>×</td></tr><tr><td>10</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td><td>E/2</td><td>E/2</td><td>↑</td><td>↑</td></tr><tr><td>11</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td><td>E/2</td><td>E/2</td><td>↓</td><td>↓</td></tr><tr><td>12</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td><td>E/2</td><td>×</td><td>×</td></tr><tr><td></td><td>13</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>E/2</td><td>×</td><td>↑</td></tr><tr><td></td><td>14</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>E/2</td><td>×</td><td>↓</td></tr><tr><td></td><td>15</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>-E</td><td>0</td><td>×</td><td>×</td></tr></tbody></table>

Therefore, to keep the capacitor voltage stable at E/2, it is important to select a suitable mode. Furthermore, certain modes show distinct behaviors with respect to the conduction losses. Modes of 4, 5,7 and 8 yield identical phase voltage of 0 but demonstrate different behaviors regarding the conduction losses of the semiconductors. In mode 4 and 7, the free-wheeling currents flows through upper semiconductors, while in mode 5 and 8, the free-wheeling currents flow through bottom semiconductors. Therefore, a suitable mode should be selected to divide the free-wheeling current's conduction losses between upper ($S_{1,2,4,5}$ and $D_{3,6}$) and bottom ($S_{3,6}$ and $D_{1,2,4,5}$) semiconductors with an equal share.

## Design of Flying Capacitors for the Proposed Converter

The capacitance values of the flying capacitors $C_1$ and $C_2$ in the proposed converter is critical to ensure optimal performance of the motor. Accurate determination of this value involves considering the rated motor current ($I_m^{rated}$), switching frequency ($f_{sw}$), and permissible

voltage ripple ($\Delta V$). The required capacitance for $C_1$ can be calculated using (1)

$$C_1 = \frac{I_m^{rated} T_{sw}}{\Delta V} \qquad (1)$$

The switching period ($\Delta t$) is calculated in (2).

$$T_{sw} = 1/f_{sw} \qquad (2)$$

As the capacitor $C_2$ is shared between phases B and C, current passing through $C_2$ is twice that of $C_1$ when $E/2$ is applied across both phases. Thus, the capacitance value of $C_2$ must be twice that of $C_1$ ($C_2 = 2C_1$). Considering the rated current of the motor is $I_m^{rated}=165A$, the maximum allowable voltage variation across the capacitor is 20 percent of the DC link voltage ($E=80V$) and $f_{sw} = 10kHz$, $C_1$ and $C_2$ are equal to 515 $\mu F$ and 1030 $\mu F$, respectively.

## Simulation Studies

To verify the effectiveness of the proposed shared-leg FC converter, simulations were conducted in MATLAB/SIMULINK. In this simulation model, the reference current is generated by the speed control loop and then fed to the PWM modulator to generate the switches' gate signals. The standard PWM modulation method discussed in [17] is used for this simulation.

<figure><img src="image_7.png" /><figcaption>Fig.6 Simulation results of the proposed converter. Three phase currents and their reference value at different speeds.</figcaption></figure>
Simulation results displayed in Fig. 6 are captured at two different speeds, 500 rpm and 1000 rpm respectively. A 12/16, 4 kW, 80V and 1800 rpm three-phase SRM was selected for modelling and testing in the simulation. The converter was simulated with a switching frequency of 20 kHz. The three-phase currents waveforms of the motor using the proposed converter are shown in Fig. 6. It is evident from the simulation results that the three-phase currents are following their reference values.

In this converter, the voltage applied to phases A and B during demagnetization switches between 0, -E, which prolongs the demagnetization time for these phases. Meanwhile, the voltage applied to phase C is maintained at E and does not switch to other values during its demagnetization, resulting in a shorter demagnetization time for phase C.

The conventional AHB converter and the conventional AHB converter are also simulated to be compared with the proposed converter and their simulation results are presented in Fig.7. It is shown that, compared to the two-level AHB converter, the phase current ripple of the three level converters is reduced by 40% due to applying E/2 for magnetization of the phase in conduction region. Furthermore, by comparing the Fig. 7(b) and Fig. 7(c), it can be inferred that the proposed converter has the same current ripple as the conventional FC converter.

## Comparative Analysis

In this section, the conventional AHB, the conventional FC-AHB ML converter, the asymmetric-FC half bridge (AFCHB) ML converter [19] and [20], and the proposed three-level SLFC converter are evaluated based on various factors (Table.II). The conventional AHB converter and the proposed converter features the fewest number of switches (with a total of six switches), contributing to its straightforward design. In contrast, the FC-AHB converter includes 12 switches, which is double the number found in the conventional AHB.

The proposed converter also has six switches, the least among the ML converters compared, as it shares two switches and two diodes between a pair of phases. In the conventional AHB, each switch must handle the full voltage rating (E), leading to higher stress on the switches and possibly affecting their reliability.

<figure><img src="image_8.png" /><figcaption>(a) Conventional AHB converter</figcaption></figure>

<figure><img src="image_9.png" /><figcaption>(b) Conventional FC converter</figcaption></figure>

<figure><img src="image_10.png" /><figcaption>(c) Proposed three-level SLFC Converter.</figcaption></figure>

Fig. 7. Simulation results of the SRM operating at 1000 RPM with a switching frequency of 20 kHz. Displayed are the phase current (black), voltage (blue), and current reference (red).

The FC-AHB converter reduces voltage stress on each switch by halving the voltage rating to E/2, potentially enhancing the reliability of the switches. The proposed converter keeps the voltage rating at E for two switches and two diodes but halves the voltage rating for the remaining switches and diodes, indicating medium reliability compared to the others. The simplicity of the conventional AHB is due to its lower switch count, though this comes at the cost of higher voltage stress on each switch. The FC-AHB converter, despite improved reliability from lower voltage ratings per switch, is more complex due to its higher switch count.
<table><caption>Table.II Comparative analysis of the proposed converter and other counterparts.</caption><thead><tr><th>Topologies</th><th>AHB</th><th>FC-AHB</th><th>AFCHB<br>[19] and [20]</th><th colspan="2">Proposed SLFC</th></tr></thead><tbody><tr><td>Voltage Levels</td><td>2</td><td>3</td><td>3</td><td colspan="2">3</td></tr><tr><td>(Number of Switches,<br>Number of Diodes)</td><td>(6,6)</td><td>(12,12)</td><td>(9,9)</td><td colspan="2">(6,6)</td></tr><tr><td rowspan="3">Switches Voltage Rating</td><td rowspan="3">E</td><td rowspan="3">E/2</td><td>S<sub>x1,2</sub> E/2</td><td>S<sub>1,2,4,5</sub></td><td>E/2</td></tr><tr><td>S<sub>x3</sub><br>x = a, b, c</td><td>E</td><td>S<sub>3,6</sub></td><td>E</td></tr><tr><td>D<sub>x1,2</sub> E/2</td><td>D<sub>1,2,4,5</sub></td><td>E/2</td></tr><tr><td rowspan="2">Diodes Voltage Rating</td><td rowspan="2">E</td><td rowspan="2">E/2</td><td>D<sub>x3</sub><br>x = a, b, c</td><td>D<sub>3,6</sub></td><td>E</td></tr><tr><td>D<sub>3,6</sub></td><td>E</td></tr><tr><td>Total Voltage Rating</td><td>12E</td><td>12E</td><td>12E</td><td colspan="2">8E</td></tr><tr><td rowspan="2">Switches Current Rating</td><td rowspan="2">I</td><td rowspan="2">I</td><td rowspan="2">I</td><td>S<sub>1,2,4,5</sub></td><td>I</td></tr><tr><td>S<sub>3,6</sub></td><td>2I</td></tr><tr><td rowspan="2">Diodes Current Rating</td><td rowspan="2">I</td><td rowspan="2">I</td><td rowspan="2">I</td><td>D<sub>1,2,4,5</sub></td><td>I</td></tr><tr><td>D<sub>3,6</sub></td><td>2I</td></tr><tr><td>Total Current Rating</td><td>16I</td><td>24I</td><td>18I</td><td colspan="2">16I</td></tr><tr><td>(Number of Current<br>Sensors, Number of<br>Voltage Sensors)</td><td>(3, 1)</td><td>(3, 6)</td><td>(3,3)</td><td colspan="2">(2,2)</td></tr><tr><td>Current ripple</td><td>High</td><td>Low</td><td>Low</td><td colspan="2">Low</td></tr><tr><td>Cost of Gate Drivers</td><td>Low</td><td>Very High</td><td>Medium</td><td colspan="2">Low</td></tr><tr><td>DC Capacitors</td><td>1</td><td>6</td><td>3</td><td colspan="2">2</td></tr></tbody></table>

The proposed converter matches the conventional AHB's switch count and is less complex than the FC-AHB converters. Although the current rating of switches $S_3$, $S_4$ and $S_5$ and diodes $D_3$, $D_4$ and $D_5$ in the proposed converter is double that of other switches, this does not significantly increase the converter cost since the cost of the switches is primarily influenced by voltage rating.

The proposed converter has the lowest total voltage rating and the fewest current sensors among all counterparts, the same number of gate drivers and total current rating as the AHB converter, underscoring its cost-effectiveness. Additionally, it requires only two DC capacitors while maintaining the same performance as the conventional FC-AHB, reducing the number of voltage sensors needed for capacitor voltage control, further enhancing cost-effectiveness.

## Conclusion

In summary, a cost-efficient three-level SLFC converter for three-phase SRM applications has been introduced. Two shared legs are utilized for adjacent phases during the magnetization, freewheeling, and demagnetization processes.

According to simulation results, the proposed three-level SLFC converter operates the SRM with nearly the same performance as the conventional FC converter while reducing the number of gate drives, switches, and diodes without increasing voltage stress. Additionally, it allows for the elimination of one current sensor, one voltage sensor, and one capacitor, thereby achieving significant cost reductions, minimizing current ripple, and simplifying overall system complexity.

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