# Slope Compensation and Bifurcation in a DC-DC, Single-Input, Multiple-Output, CMOS Integrated Converter Under Current-Mode and Comparator-Based Hybrid Control

Mathieu Ginet, Eric Feltrin, Nicolas Jeanniot, Bruno Allard, Xuefang Lin-Shi

<figure><img src="image_1.png" /></figure>

## To cite this version:

Mathieu Ginet, Eric Feltrin, Nicolas Jeanniot, Bruno Allard, Xuefang Lin-Shi. Slope Compensation and Bifurcation in a DC-DC, Single-Input, Multiple-Output, CMOS Integrated Converter Under Current-Mode and Comparator-Based Hybrid Control. Journal of Low Power Electronics and Applications, 2025, 15 (4), pp.69. 10.3390/jlpea15040069. [https://hal.science/hal-05456661v1](https://hal.science/hal-05456661v1)

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Article

# Slope compensation and bifurcation in a DC-DC, Single-Input, Multiple-Outputs, CMOS integrated Converter under current-mode and comparator-based hybrid control

Mathieu Ginet <fnref n="1" />,<fnref n="2" />, Eric Feltrin <fnref n="1" />, Nicolas Jeanniot <fnref n="1" />, Bruno Allard <fnref n="2" /> and Xuefang Lin-Shi <fnref n="2" />

## Abstract

Single-Input, Multi-Output (SIMO) converters present significant challenges when operated under current-mode control, due to their strongly non-linear dynamics and susceptibility to bifurcation phenomena. To mitigate the effects on the converter's steady-state, a double slope compensation solution is proposed. The compensation parameters play a critical role in shaping the system dynamics and rejecting the susceptibility to bifurcation. This paper proposes a detailed analysis methodology to investigate the design parameter space regarding the slope compensations with respect to bifurcation phenomena. The approach is validated on a CMOS integrated converter, where theoretical predictions are compared to the simulation results of a full transistor-level model of the circuit.

**Keywords:** SIMO DC-DC converter; current-mode control; stability; bifurcation; bifurcation map.

## 1. Introduction and State of Art

In the microcontroller (MCU) ecosystem, the innovation is driven by computation speed, power efficiency, and the integration of complex analog functions such as analog-to-digital converters (ADC) or radio frequency (RF) transmitters [1]. A key advancement has been the integration of switch-mode power supplies (SMPS), which reduce the bill of materials by eliminating external companion components, reduce the overall footprint and enhance both computation speed and energy efficiency. The latest MCUs feature at least three distinct power domains: digital glue, memories, and RF peripherals. Each power domain requires a different voltage level and power demand. A potential next step in power management integration is the use of a single-input multiple-output (SIMO) SMPS [2,3], as it can supply multiple domains using a single (off-chip) inductor. However, the implementation and stability analysis of such a topology are more complex compared to a standard one-output SMPS.

as mentioned in [4].

Stability issues and bifurcation analyses in the case of single-input single-output (SISO) DC-DC buck converters are extensively covered in the literature. In [5], multiple stability analysis methods are proposed.

Discrete-time modeling of a SISO DC-DC converter can be performed, as explained in [6,7]. Based on the discrete converter model, iterative simulations in steady-state can

Received:

Revised:

Accepted:

Published:

**Citation:** Ginet, M.; Feltrin, E.; Jeanniot, N.; Allard, B.; Lin-Shi, X. Slope compensation and bifurcation in a DC-DC, Single-Input, Multiple-Outputs, CMOS integrated Converter under current-mode and comparator-based hybrid control. *J. Low Power Electron. Appl.* **2025**, *1*, 0. https://doi.org/

**Copyright:** © 2026 by the authors. Submitted to *J. Low Power Electron. Appl.* for possible open access publication under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).

<footnote n="1">¹ STMicroelectronics, 38000 Grenoble, France</footnote>

<footnote n="2">² INSA Lyon, Universite Claude Bernard Lyon 1, Ecole Centrale de Lyon, CNRS, Ampère, UMR5005, 69621 Villeurbanne, France</footnote>

<footnote>* Correspondence: mathieu.ginet-ext@st.com</footnote>
<figure><img src="image_3.png" /><figcaption>Figure 1. Double slope compensation implementation on a DC-DC SIMO converter</figcaption></figure>

<figure><img src="image_4.png" /></figure>

66

3. The SIMO converter

Figure 2 pictures the core schematic of the considered SIMO converter.

<figure><img src="image_5.png" /></figure>

67

68

69
<figure><img src="image_6.png" /><figcaption>**Figure 2.** 3-output SIMO DC-DC converter power stage</figcaption></figure>

### 3.1. Power stage architecture

The off-chip inductor, L, is charged and then discharged over each operating period, by connecting the node, $V_{LX}$, to the input DC supply voltage or the ground node, respectively. This connection is performed by the two input switches, $Q_P$ and $Q_N$. The inductor current is dynamically split among the three outputs by three switches, $Q_{O1}$, $Q_{O2}$ and $Q_{O3}$ respectively. An off-chip capacitor is added in parallel on each output and acts as a charge tank when the output is not connected to the inductance with the goal to limit the voltage ripple.

A free-wheeling switch, $Q_{FW}$, is implemented between the ground node and the node $V_{LY}$. The latter switch can be considered as a fourth output switch that is used to derive an excess of inductance current that would otherwise overcharge the outputs above their reference voltage. An auxiliary current source is realized with the transistor, $Q_{AUX}$, added in parallel with the inductor regarding the input switches. When a load transient occurs, this source supplies additional current to assist the SMPS until the control feedback loop adjusts the current provided by the inductor to the outputs. The circuit is a simple copy of a fixed bias current, which means the source current amplitude is fixed and constant.

The connections between the outputs of the SIMO converter and the off-chip capacitors suffer from parasitic resistances and inductances due to the bonding of the off-chip power network. Thus, the swap of the inductor current from one output to another causes an important ripple on the output voltages. An RC low-pass filter is used to reject the effect of the ripple due to bonding parasitics on the output voltage for the purpose of voltage sensing with minimal impact on the control loops. Thus, the sensed output voltages $V_{FO1}$, $V_{FO2}$ and $V_{FO3}$ are obtained.

### 3.2. Control scheme

A current-mode control and a comparator-based hybrid control are proposed to operate the converter in Figure 2 as pictured in Figure 3. The first loop matches the average current flowing through the off-chip inductor to the sum of the instantaneous required output load currents. The second loop adjusts the duty cycle of the output switches, $Q_{Oi}$, to split optimally the inductor current into the three outputs. The first control loop is managed by a PWM peak-current mode control. Depending on the difference between
the actual output voltages and their nominal references, error currents are generated and summed into a resistor bridge to create the voltage, V<sub>ERROR</sub>. A Proportional-Integral (PI) corrector is implemented to generate the voltage, V<sub>CONTROL</sub>. The latter voltage signal is compared to a sensed image of the inductor current to control the duty cycle of input switches. The current sensing is performed by a current copy circuit on the high-side switch, Q<sub>P</sub>. The second control loop implements a comparator-based voltage control. When the off-chip inductor charge or discharge phase starts, the first output is supplied until it reaches its reference voltage. Then the second output is supplied, and finally the third one is supplied until the inductor charge or discharge phase ends and the cycle restarts. When the free-wheeling switch is enabled, the charge of the third output stops when its reference is reached and the remaining current is sent to the ground node until the end of the period. Loads transients are detected by a hysteretic comparator on the voltage, V<sub>ERROR</sub>. The auxiliary current source and free-wheeling switch are enabled when V<sub>ERROR</sub> reaches the hysteretic thresholds. Moreover, an assistance signal is added to the error amplifier input to speed up its response during a transient.

<figure><img src="image_7.png" /><figcaption>**Figure 3.** SIMO DC-DC converter proposed control</figcaption></figure>

### 3.3. Issue

The SIMO DC-DC converter presented in the previous subsection is implemented in a ST-18nm-process. Figure 4 shows the main waveforms from the simulation of the transistor-level circuit model in a steady-state scenario under nominal supply voltage and maximum loads: V<sub>IN</sub> is set to 3.0 V, I<sub>LOAD1</sub> equals 500 mA, I<sub>LOAD2</sub> and I<sub>LOAD3</sub> equal 200 mA. The switching frequency is 2.73 MHz, which corresponds to a period T=366 ns.

<caption>Figure 4.</caption>

The inductor current ripple and the respective output voltage ripples are higher than in the case of a SIMO converter operating without sub-harmonic oscillations. The efficiency of power conversion is slightly degraded.
<figure><img src="image_8.png" /><figcaption>Figure 4. Sub-harmonic oscillations occurring during a steady-state scenario</figcaption></figure>

A bifurcation has occurred in the converter operation, shown by a more complex pattern of the transistor control signals than the expected nominal ones. During the converter design flow, it is mandatory to explore the conditions of the bifurcation onset prior to fabrication. It is the main interest of subsequent sections.

## 4. Theoretical analysis of sub-harmonic oscillation damping

Sub-harmonic oscillations, which occur when the duty cycle is higher than 50% in a Single-Input Single-Output (SISO) DC-DC Buck converter, are a well-known phenomenon. The common solution presented in the state-of-the-art consists of adding a compensating ramp to the image voltage of the sensed inductor current. The same effect is achieved by adding a compensating ramp with a negative slope to the output signal of the error amplifier compared to the current image.

<figure><img src="image_9.png" /></figure>

### 4.1. Implementation of a double slope compensation

In the SIMO converter, the first control loop regulates the inductor current similarly to that of a PWM current-mode converter. Thus, it is possible to implement a slope compensation on that control loop as shown in Figure 5.

<figure><img src="image_10.png" /><figcaption>Figure 5. Slope compensation implementation on the input switch control loop</figcaption></figure>
In the case of the proposed SIMO converter, a comparator-based control is applied to operate the output switches, $Q_{Oi}$. This implies that the duty cycle of an output switch can be different from one period to another, as long as the mean duty cycle remains coherent with the supplied load current and the inductor current. This opens the possibility of subharmonic oscillation phenomenon on the output voltages. Moreover, different duty cycle values from one period to another lead to different inductor current slopes from one period to another. Thus, it is another cause of subharmonic oscillation in the inductor current.

To address this issue, a compensation ramp is added to the output reference voltage as shown in Figure 6.

<figure><img src="image_11.png" /><figcaption>Figure 6. Slope compensation implementation on the output switch control loop</figcaption></figure>

The output voltages $V_{Oi}$ are filtered by a low-pass filter, $RC_{FILTER}$, to avoid glitches linked to parasitic resistance of the bonding. These glitches are visible on the output voltage waveforms in Figure 4. An offset occurs on an output voltage when its switch is turned on. The sensed output voltages, $V_{FOi}$, are compared to their respective reference voltages, $V_{REFi}$, plus a compensating ramp, $s_{C,VREF}$. For the sake of simplification during the analysis, the comparators are modeled by an ideal comparator and a delay block, $delay_{OUT}$.

As shown in Figure 6, a phase shift, $\Phi$, is added between the reset of the compensating ramp and the reset of the logic glues and non-overlapping circuit, to avoid both resets at the same time. Without this phase shift, if the sensed output voltage, $V_{FOi}$, becomes lower than its reference minus the slope compensation just before the logic glues and non-overlapping circuit is reset, the comparator's propagation time, $delay_{OUT}$, causes an incoherence between the comparator inputs and the output fed to the logic glues. This phenomenon is highlighted in Figure 7(a). The RESET of the logic glues happens while the SET is still in a high state, even if the sensed output voltage is already lower than its reference minus the compensating ramp. As a result, the output voltage will decrease during the whole next period, then it will increase again, and this phenomenon will be repeated. It causes an unwanted pattern of subharmonic oscillations. This issue is also addressed in [25].

<figure><img src="image_12.png" /><figcaption>Figure 7. (a) Issue without phase shift and (b) benefit of the added phase shift</figcaption></figure>
Figure 7(b) shows the benefit of the phase shift between the compensating ramp reset and the logic glues reset, leading to a stable operation. During a steady-state, the signal is guaranteed to be lower than its reference when the compensating ramp resets. If the phase shift is higher than the propagation time (or delay) of the comparator, the comparator output is guaranteed to be coherent with respect to its input when the logic glues reset signal occurs. In [26], single-edge and dual-edge modulation techniques are applied to generate different PWM phase shifts, and the bifurcation diagram shows that the bifurcation phenomenon is impacted by the phase shift.

For the input switches control loop, the phase shift is not needed if the reset signal of the RS flip-flop is implemented with a width slightly larger than delay<sub>IN</sub>. The priority of the reset over the set makes it possible to ignore the comparator output until it is matched again with its inputs when its propagation time has ended.

The drawback of increasing the reset signal width is that it forces the power stage in a fixed state for the whole reset signal duration. With the control strategy presented in this article, this fixed state corresponds to the charge of the first output, while the inductor current rises as the node, V<sub>LY</sub>, is connected to the supply voltage, V<sub>IN</sub>.

Through transistor-level simulation of the SIMO converter, delay<sub>IN</sub> is estimated at 20 ns, while delay<sub>OUT</sub> is estimated at 65 ns. When the first output load is relatively low compared to the total load supplied by the converter, it is not feasible to replace the phase shift in the output switches control loop with a flip-flop reset signal wider than delay<sub>OUT</sub>. Doing so forces a fixed state for at least 65 ns during each period, causing the first output voltage to gradually rise significantly above its reference.

## 4.2. Damping sub-harmonic oscillations

A theoretical analysis is proposed to demonstrate the suitable slope value needed by the compensating ramps to damp any tendency toward sub-harmonic oscillations.

Figure 8 shows which signals from the SIMO converter power stage are compared to a reference signal plus a compensating ramp, for the input and output switches' control loops, respectively, in Figure 8.(a) and Figure 8.(b). Moreover, the expression of the slopes, s<sub>1</sub> and s<sub>2</sub> of the fed signals, are given as a function of the circuit parameters, voltages and currents.

<figure><img src="image_13.png" /><figcaption>**Figure 8.** (a) Input switches' control and (b) output switches' control signals fed to comparators respectively</figcaption></figure>

The resistance, R<sub>p</sub>, corresponds to the sum of the input and output switches, inductor and bonding parasitic resistances. Its value is estimated at 280 mΩ. The weighted output
voltage, $\overline{V_{OUT}}$, in Figure 8 is evaluated from the nominal conditions of operation of the converter (1), while the inductor current is averaged by the mean value, $\overline{I_L}$, (2):

$$ \overline{V_{OUT}} = \frac{I_{LOAD1} \cdot V_{O1} + I_{LOAD2} \cdot V_{O2} + I_{LOAD3} \cdot V_{O3}}{\overline{I_L}} \quad (1) $$

$$ \overline{I_L} = I_{LOAD1} + I_{LOAD2} + I_{LOAD3} \quad (2) $$

For the bifurcation analysis, generalized figures and equations will be given, with only one signal and one compensating ramp represented at a time, as shown in Figure 9. However,

* The signals' slopes, $s_1$ and $s_2$, are pictured in Figure 8.(a) and Figure 8.(b) respectively.

* The signals' slopes, $s_1$ and $s_2$, are pictured in Figure 8.(a) and Figure 8.(b) respectively.

The slope compensation is useful only if a stable steady-state pattern (without sub-harmonic oscillations) exists for a given operating point. Figure 9 shows a steady-state waveform with no sub-harmonic oscillations: the signal value at the end of the period T is the same as its starting value. The signal rises with a slope, $s_1$, for the duration, $T_{ON}$, and drops with a slope, $s_2$, for the duration, (T-T_{ON}).

Figure 9. Steady-state pattern without sub-harmonic oscillations

<figure><img src="image_14.png" /><figcaption>Figure 9. Steady-state pattern without sub-harmonic oscillations</figcaption></figure>

A stable pattern without sub-harmonic oscillation, where the signal returns to its initial value at the end of the period T, can be described by the following inequality (3):

$$ T_{ON} \cdot s_1 = -(T - T_{ON}) \cdot s_2 \quad (3) $$

$$ \text{delay} < T_{ON} = \frac{-s_2 \cdot T}{s_1 - s_2} \quad (4) $$

$$ \text{delay} < T_{ON} = \frac{-s_2 \cdot T}{s_1 - s_2} \quad (4) $$

(4) can be reviewed as the one in (5) using the expression of $s_1$ and $s_2$ from Figure 8.(a):

$$ \text{delay}_{IN} < \frac{\overline{V_{OUT}} + R_P \cdot \overline{I_L}}{V_{IN}} \cdot T \quad (5) $$

$$ \text{delay}_{IN} < \frac{\overline{V_{OUT}} + R_P \cdot \overline{I_L}}{V_{IN}} \cdot T \quad (5) $$
<table><caption>**Table 1.** Specification range of the circuit parameters</caption><thead><tr><th>Parameter</th><th>min</th><th>max</th></tr></thead><tbody><tr><td>V<sub>OUT</sub></td><td>0.8 V</td><td>1.5 V</td></tr><tr><td>I<sub>L</sub></td><td>0 A</td><td>0.9 A</td></tr><tr><td>V<sub>IN</sub></td><td>1.6 V</td><td>3.6 V</td></tr></tbody></table>

The minimum value for the right-side term in inequality (5) is reached when considering the minimum value of $V_{OUT}$, the maximum value of $V_{IN}$ and the averaged inductor current, $I_L$, equal to zero. Thus, (5) - , which means that the inequality (5) -, as described by the inequality (4), can be reworked as (6) using the slope expressions, $s_1$ and $s_2$, from Figure 8(b):

$$delay_{OUT} < \frac{min(I_{LOADi})}{I_{L}} \cdot T \quad (6)$$

in (6) is satisfied only if the load current at each output is higher than 19.5% of the converter total load current, which is not always the case.

The following analysis will consider the case where in (6) and a stable pattern with no sub-harmonic oscillations exists for the three output switches' control loops, while a solution to manage the cases where (6) is not will be presented later on.

□ in (6)

In Figure 10, the blue waveform corresponds to a signal of interest in steady-state condition, i.e. a stable pattern without sub-harmonic oscillations, while the orange waveform starts with an initial perturbation of $\Delta V_0$. During each switching cycle, the signal is rising with a slope, $s_1$, until it reaches its reference minus the compensating ramp of slope, $s_C$. A delay, which corresponds to the comparator delay in the circuit implementation, is considered between the crossing and the start of the signal fall. The signal decreases with a slope, $s_2$, until the next switching cycle starts. The time during which the signal is rising is denoted $T_{ON}$, while the switching period is denoted T. When no sub-harmonic oscillations occur, the signal in blue returns to its initial value, $V_0$ at the start of the next switching cycle, while the perturbed signal in orange reaches $V_0 + \Delta V_1$ at the end of the cycle.

<figure><img src="image_15.png" /><figcaption>**Figure 10.** Slope compensation effect in nominal conditions</figcaption></figure>
Based on Figure 10, the expression of $T_{ON}$ for the perturbed signal comes as (7):

$$T_{ON} = \frac{REF - V_0 - \Delta V_0}{s_1 - s_C} + delay \quad (7)$$

Moreover, the signal value achieved at the end of a switching cycle ($V_0 + \Delta V_1$) can be expressed as:

$$V_0 + \Delta V_1 = V_0 + \Delta V_0 + s_1 \cdot T_{ON} + s_2(T - T_{ON}) \quad (8)$$

Combining equations (7) and (8) yields:

$$\Delta V_1 = \Delta V_0 + (s_1 - s_2) \left( \frac{REF - V_0 - \Delta V_0}{s_1 - s_C} + delay \right) + T \cdot s_2 \quad (9)$$

In the case where no sub-harmonic oscillations occur, i.e. the signal in blue in Figure 10, the initial voltage value in each switching cycle, $V_0$, can be expressed as follows:

$$V_0 = REF + (s_1 - s_C) \left( \frac{T \cdot s_2}{s_1 - s_2} + delay \right) \quad (10)$$

Combining equations (9) and (10) gives a simple expression of $\Delta V_1$, which depends only on the initial perturbation $\Delta V_0$, the signal slopes and the compensating ramp slope:

$$\Delta V_1 = \Delta V_0 \left( 1 - \frac{s_1 - s_2}{s_1 - s_C} \right) \quad (11)$$

The sub-harmonic oscillation phenomenon is damped if the absolute value of $\Delta V_1$ is lower than the absolute value of $\Delta V_0$. Since the slopes $s_2$ and $s_C$ are negative, the damping condition can be written as:

$$s_C < \frac{s_1 + s_2}{2} \quad (12)$$

The inequality in (12) gives a general expression of the slope compensation value needed as a function of the rising slope and falling slope of the signal to protect from sub-harmonic oscillation phenomena.

In the SIMO converter, two compensation ramps are implemented. Based on the expressions of $s_1$ and $s_2$ from Figure 8.(a) and Figure 8.(b) respectively, the inequality in (12) can be rewritten as (13) and (14), for the input switches' control loop and output switches' control loop respectively.

$$s_{C,I_L} < \frac{V_{IN} - 2\overline{V_{OUT}} - 2R_P \cdot \overline{I_L}}{2L} \times K_{SENSE} \quad (13)$$

$$s_{C,V_{REF}} < \frac{\overline{I_L} - 2\overline{I_{LOAD}}}{2C} \times RC_{FILTER} \quad (14)$$

For a given operating point of the SIMO converter, in (5), (6), (13) and (14), no sub-harmonic oscillations should be forecasted.

□ in (6)

The condition in (6) is not fulfilled when the comparator propagation delay of the output switch control loop is longer than the theoretical supply duration needed by the output, which happens when one output current load is relatively low compared to the total current load supplied by the SIMO converter. In [23], this issue is addressed with a skip mechanism, while a phase interchange strategy is applied in [27]. However, both latter strategies are unsuited in the SIMO converter because they can be sources of bifurcation.
In the present context, it is possible to reach a supply duration lower than the comparator delay if the slope of the compensating ramp, $s_{C,VREF}$, is steeper than the decreasing slope, $s_2$, of the sensed output voltage, as shown in Figure 11.

<figure><img src="image_16.png" /><figcaption>Figure 11. $T_{ON}$ lower than the delay, $delay_{OUT}$</figcaption></figure>

With a compensation slope steeper than the decreasing slope of the sensed output voltage, $V_{FOi}$, the comparator triggers before the RESET pulse, which allows the supply duration, $T_{ON}$, to be shorter than the delay, $delay_{OUT}$.

If a perturbation affects the signal, $V_{FOi}$, the intersection between the compensation slope and the sensed output voltage is shifted by $\Delta V_0$ in value. It is possible to express the shift of the perturbed signal after one period T with respect to the slopes, $s_1$, $s_2$, and $s_{C,VREF}$, and the initial perturbation as expressed in (15):

$$ \Delta V_1 = \Delta V_0 \left( 1 + \frac{s_1 - s_2}{s_{C,VREF} - s_2} \right) \qquad (15) $$

The sub-harmonic oscillation phenomenon is damped if the absolute value of $\Delta V_1$ is lower than the absolute value of $\Delta V_0$. Since $s_{C,VREF}$ is steeper than $s_2$, and since $s_1$ is higher than the absolute value of $s_2$, the damping condition can be written as (16):

$$ s_{C,VREF} < \frac{3 \cdot s_2 - s_1}{2} \qquad (16) $$

Based on the expression of $s_1$ and $s_2$ from Figure 8.(b), (16) can be expressed as (17):

$$ s_{C,VREF} < - \frac{\overline{I_L} + 2 \cdot I_{LOADi}}{2C} \times RC_{FILTER} \qquad (17) $$

For a given operating point of the SIMO converter, in (5), (13) and (17), no sub-harmonic oscillations should be forecasted.

## 5. Impact of circuit parameters on the onset of bifurcation

in (13), (14) and (17), However, many simplifications were considered that might have an impact on the boundaries found between sub-harmonic oscillation onset and stable patterns.

* The inductor current slope values are computed based on the weighted output voltage, $\overline{V_{OUT}}$, evaluated from the nominal conditions of the converter. In reality, the inductor current slopes depend on the output currently supplied: it is not a single value slope.
* Only the static gain of the current sensing filter, $K_{SENSE}$, is considered. The cut-off frequency of the filter is supposed to be well above the switching frequency of the converter so that the high frequency behavior is neglected and the current image is not distorted.

* The inductor current flowing through the output switches is averaged from the sum of the output current loads, and the current ripple is not considered in the output switches' control loops and voltage drop on parasitic resistance, $R_p$, as well.

* The output voltage sensing filters, $RC_{FILTER}$, are considered as ideal low-pass filters with a gain of 1, that reject any voltage perturbations caused by the parasitic inductances and resistances from the bonding and the output capacitors.

Thus, the

## 5.1. Modeling using Matlab/Simulink

The SIMO converter architecture is implemented at system-level in Matlab/Simulink, as shown in Figure 12.

<figure><img src="image_17.png" /><figcaption>Figure 12. Implementation in Matlab/Simulink</figcaption></figure>

The power stage is represented by a state-space model, with adequate matrices depending on the switches' states. The current sensor gain, $K_{SENSE}$, and the time-constants of output voltage sensing filters, $RC_{FILTER}$, are implemented as first-order transfer functions. The comparators are modeled as ideal comparator blocks and delay blocks. The input switches' control loop in Figure 3 is implemented with transfer function blocks and basic mathematical blocks, yielding the signal $V_{CONTROL}$. The compensation ramp slopes, $S_{C,IL}$ and $S_{C,VREF}$, are added to $V_{CONTROL}$ and $V_{REFi}$ respectively. Finally, a logic circuit determines the switches' states depending on the comparators' outputs.

In order to validate the inequalities in (5), (6), (13), (14) and (17), the SIMO converter is simulated in steady-state considering eight different load cases, as listed in Table 2:

<table><caption>Table 2. Load cases considered in the system-level simulations</caption><thead><tr><th>Case</th><th>I<sub>LOAD1</sub></th><th>I<sub>LOAD2</sub></th><th>I<sub>LOAD3</sub></th></tr></thead><tbody><tr><td>#1</td><td>500 mA</td><td>200 mA</td><td>200 mA</td></tr><tr><td>#2</td><td>500 mA</td><td>200 mA</td><td>20 mA</td></tr><tr><td>#3</td><td>500 mA</td><td>20 mA</td><td>200 mA</td></tr><tr><td>#4</td><td>500 mA</td><td>20 mA</td><td>20 mA</td></tr><tr><td>#5</td><td>50 mA</td><td>200 mA</td><td>200 mA</td></tr><tr><td>#6</td><td>50 mA</td><td>200 mA</td><td>20 mA</td></tr><tr><td>#7</td><td>50 mA</td><td>20 mA</td><td>200 mA</td></tr><tr><td>#8</td><td>50 mA</td><td>20 mA</td><td>20 mA</td></tr></tbody></table>
<figure><img src="image_18.png" /></figure>

## 5.2. Slope compensation on the input switches' control loop

The previous section shows the factors that can impact the boundaries between stable operation patterns and sub-harmonic oscillation appearance regarding the input switches' control loop: the supply voltage, the current sensor characteristics, the comparator delay and the relative output load currents compared to the total current load supplied by the SIMO converter.

### ☐ Impact of the supply voltage, $V_{IN}$

Considering the circuit parameters with their respective nominal values and $V_{IN}$ in the range [1.6 V; 3.6 V], in (5) - (13).

<figure><img src="image_19.png" /></figure>

in (13) for all load cases in Table 2, (18).

$$s_{C,IL} = V_{IN} \cdot 5.25 \cdot 10^{5} - 1.48 \cdot 10^{6} [V/s] \quad (18)$$

This boundary equation is verified through simulation. The supply voltage, $V_{IN}$, varies in the range [1.6 V; 3.6 V] with a 100 mV step. The compensation ramp slope, $s_{C,IL}$, varies between 0 V/s and $9 \cdot 10^{5}$ V/s. The maximum value for this slope corresponds to an amplitude of 300 mV with 3 MHz switching frequency of the SIMO converter. Figure (13) shows the obtained results. For a given set of ($V_{IN}$, $s_{C,IL}$), a yellow point means that at least one load case is leading to sub-harmonic oscillations, while a blue point means that a stable operation pattern is achieved by the SIMO converter for all load cases in Table 2.

<figure><img src="image_20.png" /><figcaption>Figure 13. Correlation between $s_{C,IL}$ and $V_{IN}$ regarding sub-harmonic oscillations' damping</figcaption></figure>

Similar behavior is observed between the theoretical boundary equation (18) and the simulation results, with a constant shift. This difference can be explained by the simplifications made to determine the theoretical equation: $K_{SENSE}$ is considered as a static gain without high frequency behavior, inductor current and weighted output voltage are averaged over one period.

### ☐ Impact of the current sensing transfer function, $K_{SENSE}$

As shown by the inequality in (13), the current sensing transfer function, $K_{SENSE}$, has a direct impact on the slope needed by the compensation ramp, $s_{C,IL}$, to damp any tendency toward sub-harmonic oscillations. Considering a first-order transfer function, its cut-off frequency has an impact on the current sensing gain for high-frequency signals. Moreover, an additional delay is introduced in the input switches' control loop depending
on the transfer function phase. Simulations are conducted to analyse this effect: the cut-off frequency varies between 1.6 MHz and 160 MHz, while $s_{C,IL}$ varies between 0 V/s and $9 \cdot 10^5$ V/s.

<figure><img src="image_21.png" /><figcaption>Figure 14. Correlation between $s_{C,IL}$ and $K_{SENSE}$ regarding the sub-harmonic oscillation damping</figcaption></figure>

Figure 14 shows the results obtained, with a logarithmic x-axis scale. For a cut-off frequency higher than 5 MHz, a stable operation pattern is achieved for all load cases, except for few points when no compensation ramp is applied: a steady-state with period doubling is reached by the SIMO converter. In this case, even a very low compensation ramp slope value is enough to make the converter converge to a stable operation pattern. For a cut-off frequency lower than 5 MHz, the value of the compensation ramp slope increases as the current sensing cut-off frequency decreases. The lower the cut-off frequency, the more distorted the sensed current image.

### ☐ Impact of the comparator's delay, $delay_{IN}$

Considering the circuit parameters with their respective nominal values, in (5) for all load cases. This statement is verified through simulation, with the comparator delay $delay_{IN}$ varying between 5 ns and 45 ns, as shown in Figure (15).

<figure><img src="image_22.png" /><figcaption>Figure 15. Correlation between $s_{C,IL}$ and $delay_{IN}$ regarding the sub-harmonic oscillation damping</figcaption></figure>

Over the simulated $delay_{IN}$ range, stable pattern is achieved for all load cases, except for few points when no slope compensation is applied.

### 5.3. *Slope compensation in the output switches' control loops*

Inequalities in (6), (14) and (17) from the previous section show the factors that can impact the boundaries between stable operation pattern and sub-harmonic oscillation
appearance: the output load currents, the comparator delay and the output voltage sensing filter characteristics.

### ☐ Impact of the converter's total current load, $K_{LOAD}$

As described by the inequalities in (14) and (17), [__2__, multiple simulations are conducted. However, a multiplicative coefficient, $K_{LOAD}$, between 0.5 and 2, is considered as the simulation parameter. This coefficient is multiplied with the load cases from Table 2 [__2__].

The load case #3 corresponds to the most critical case regarding the compensating ramp slope needed. [__6__, in (6)] and the boundary between stable operation pattern and sub-harmonic oscillations is given by the inequality in (17). [__19__, __19__].

$$s_{C,VREF} = -3.45 \cdot 10^4 \cdot K_{LOAD} [V/s] \qquad (19)$$

Figure (16) shows the obtained simulation results for a compensation ramp slope, $s_{C,VREF}$, between 0 V/s and 9.10⁴ V/s. A behavior similar to the one given by the theoretical equation (19) is observed: the higher the load current, the steeper the required compensation ramp slope value.

<figure><img src="image_23.png" /><figcaption>Figure 16. Correlation between $s_{C,VREF}$ and $K_{LOAD}$ regarding the sub-harmonic oscillation damping</figcaption></figure>

### ☐ Impact of comparators' delay, $delay_{OUT}$

For the load case #1 in Table 2, the [__6__, in (6)] when the comparator's delay, $delay_{OUT}$, is lower than 74 ns. The compensating ramp slope needed to prevent sub-harmonic oscillation, given by the stability condition in (14), is rewritten as (20), considering the numerical application for the load case #1.

$$s_{C,VREF} = \begin{cases} -4.55 \cdot 10^3 [V/s] & \text{if } delay_{OUT} < 74 \text{ ns} \\ -5.91 \cdot 10^4 [V/s] & \text{if } delay_{OUT} > 74 \text{ ns} \end{cases} \qquad (20)$$

For load case #3 in Table 2, [__6__, in (6)] when the comparator's delay, $delay_{OUT}$, is higher than 9 ns. The compensation ramp slope needed to damp sub-harmonic oscillation phenomenon is given by (17), which can be rewritten as (21), considering the numerical application for the load case #3.

$$s_{C,VREF} = \begin{cases} -1.27 \cdot 10^4 [V/s] & \text{if } delay_{OUT} < 9 \text{ ns} \\ -3.45 \cdot 10^4 [V/s] & \text{if } delay_{OUT} > 9 \text{ ns} \end{cases} \qquad (21)$$

Simulations results are given in Figure (17).
<figure><img src="image_24.png" /><figcaption>Figure 17. Correlation between $s_{C,VREF}$ and $delay_{OUT}$ regarding the sub-harmonic oscillation damping</figcaption></figure>

When $delay_{OUT}$ is higher than 74 ns, the simulation results differ from the ones given by the theoretical equations: the needed compensation ramp slope increases as the comparator's delay increases. For a delay lower than 74 ns, simulation results are coherent with respect to the theoretical inequalities given in the previous section.

### ☐ Impact of the output voltage sensing filter, $RC_{FILTER}$

The output voltage sensing filter, $RC_{FILTER}$, impacts the slope of the compensation ramp, $s_{C,VREF}$, as shown by the inequalities in (14) and (17). Since the filter is a first order one, the high-frequency gain is impacted by its cut-off frequency, $f_{CUT,RCFILTER}$. Moreover, the phase of this filter introduces another form of delay in the output switch control loops.

When the filter phase introduces a non-negligible delay and in (6), the load case #1, high load on the three outputs, becomes the most critical case regarding the needed compensation ramp slope. in (17) is given as (22)

$$s_{C,VREF} = -5.91 \cdot 10^4 \cdot G_{RCFILTER} [V/s] \quad (22)$$

The gain of the filter is limited by its static gain. Thus, the steeper compensation ramp is evaluated considering $G_{RCFILTER} = 1$.

Simulations are conducted with a cut-off frequency varying between 40 kHz and 4 MHz, while $s_{C,VREF}$ varies between 0 V/s and $9 \cdot 10^4$ V/s. Figure 18 shows the obtained results, with a logarithmic x-axis scale.

<figure><img src="image_25.png" /><figcaption>Figure 18. Correlation between $s_{C,VREF}$ and $f_{CUT,RCFILTER}$ regarding the sub-harmonic oscillation damping</figcaption></figure>
For a cut-off frequency lower than 150 kHz, no stable operation patterns are achieved whatever the load cases. It can be explained by the fact that the sensed output voltages are too distorted, and too much delay is introduced in the loop because of the filter's phase. For frequencies of 150 kHz and higher, a stable operation pattern may be achieved for all load cases depending on the compensation ramp slope value. The required slope value varies with the gain and the phase of the filter. The boundary described by (22) is coherent.

**6. Implementation and transistor-level circuit simulation**

The double slope compensation is implemented in the SIMO converter transistor-level circuit, using the ST-18nm-process.

Regarding the bifurcation phenomenon, the worse simulation case is when the supply voltage, $V_{IN}$, is minimum. The previous section highlighted that a lower supply voltage requires a steeper compensating ramp to reach a stable pattern. Moreover, a lower supply voltage creates higher comparator propagation delays, which also require steeper slope compensation to damp any tendency toward sub-harmonic oscillations.

In this Section, we will consider a minimum supply voltage $V_{IN}$ of 1.8 V instead of the 1.6 V value given in the previous section. This is because for $V_{IN}$ between 1.6 V and 1.8 V, the energy conversion is managed by a slightly different architecture than the SIMO DC-DC converter presented in this article: the third output of the SIMO converter is bypassed and is instead supplied by a linear regulator.

Figure 19 shows the waveforms obtained with $s_{C,IL}$ set to $8.3 \cdot 10^5$ V/s and $s_{C,VREF}$ set to $6.0 \cdot 10^4$ V/s. Based on the previous Section, this set of compensating ramp slopes should damp any tendency toward sub-harmonic oscillations. However, a stable pattern is only achieved for the load case #1 as shown in Figure 19(a). For the load cases #7 and #3, respectively shown in Figure 19(b) and Figure 19(c), period doubling occurs.
<figure><img src="image_26.png" /><figcaption>Figure 19. Steady-state waveforms achieved in (a) load case #1, (b) load case #7, (c) load case #3, for $s_{C,IL} = 8.3 \cdot 10^5$ V/s and $s_{C,VREF} = 6.0 \cdot 10^4$ V/s</figcaption></figure>

Figure 20 shows the waveforms obtained with $s_{C,IL}$ set to $9.6 \cdot 10^5$ V/s and $s_{C,VREF}$ set to $6.0 \cdot 10^4$ V/s. A stable pattern is achieved for the three load cases.

<figure><img src="image_27.png" /><figcaption>Figure 20. Steady-state waveforms achieved in (a) load case #1, (b) load case #7, (c) load case #3, for $s_{C,IL} = 9.6 \cdot 10^5$ V/s and $s_{C,VREF} = 6.0 \cdot 10^4$ V/s</figcaption></figure>
A shift is observed on the boundary between stable pattern and bifurcation, with respect to the compensating ramp $s_{C,IL}$, between system-level simulations and transistor-level circuit simulations. In the transistor-level circuit, a non-overlapping strategy is implemented to prevent any short-cut between two outputs when the supplied output changes from one to another. Because of this strategy, the inductor node, $V_{LY}$, rises above 2 V during the non-overlapping phase, which lasts for around 6 ns. It can be seen as an increase in the weighted output voltage. Thus, a steeper compensating ramp is needed to damp any tendency towards sub-harmonic oscillations.

Figure 21 shows the waveforms obtained with $s_{C,IL}$ set to $9.6 \cdot 10^5$ V/s and $s_{C,VREF}$ set to $5.0 \cdot 10^4$ V/s. A stable pattern is achieved for the load cases #1 and #3, respectively, as shown in Figure 21(a) and Figure 21(c), Figure 21(b).

<figure><img src="image_28.png" /><figcaption>**Figure 21.** Steady-state waveforms achieved in (a) load case #1, (b) load case #7, (c) load case #3, for $s_{C,IL} = 9.6 \cdot 10^5$ V/s and $s_{C,VREF} = 5.0 \cdot 10^4$ V/s</figcaption></figure>

The value of $s_{C,VREF}$ decreases from $6.0 \cdot 10^4$ V/s to $5.0 \cdot 10^4$ V/s before the onset of period doubling. It is coherent with the theoretical analysis and system-level simulations from previous sections that predict a bifurcation onset when $s_{C,VREF}$ is lower than $5.91 \cdot 10^4$ V/s.

<figure><img src="image_29.png" /></figure>
<table><caption>**Table 3.** Impact of the compensating ramps on the steady-state and transient performances of the DC-DC SIMO converter</caption><thead><tr><th>Compensating ramps</th><th>load case #1 steady-state</th><th>load case #7 steady-state</th><th>load case #3 steady-state</th><th>#1 → #7 Transient voltage overshoot</th><th>#7 → #3 Transient voltage undershoot</th></tr></thead><tbody><tr><td>no slope compensation</td><td>Bifurcation</td><td>Bifurcation</td><td>Bifurcation</td><td>35 mV</td><td>14 mV</td></tr><tr><td>s<sub>C,IL</sub> = 8.3·10<sup>5</sup> V/s<br>s<sub>C,VREF</sub> = 6.0·10<sup>4</sup> V/s</td><td>Stable pattern (145 mA ripple)</td><td>Period-doubling (125 mA ripple)</td><td>Period-doubling (205 mA ripple)</td><td>46 mV</td><td>24 mV</td></tr><tr><td>s<sub>C,IL</sub> = 9.6·10<sup>5</sup> V/s<br>s<sub>C,VREF</sub> = 6.0·10<sup>4</sup> V/s</td><td>Stable pattern (145 mA ripple)</td><td>Stable pattern (105 mA ripple)</td><td>Stable pattern (155 mA ripple)</td><td>47 mV</td><td>29 mV</td></tr><tr><td>s<sub>C,IL</sub> = 9.6·10<sup>5</sup> V/s<br>s<sub>C,VREF</sub> = 5.0·10<sup>4</sup> V/s</td><td>Stable pattern (145 mA ripple)</td><td>Period-doubling (140 mA ripple)</td><td>Stable pattern (155 mA ripple)</td><td>44 mV</td><td>22 mV</td></tr></tbody></table>

## 7. Conclusion

This paper presents a SIMO DC-DC converter architecture with a current-mode and comparator-based hybrid control. Simulation of the full transistor-level circuit design of this topology highlighted the bifurcation phenomenon occurring during steady-state. Based on the classical slope compensation approach used in SISO current-controlled DC-DC converter, a new solution to damp any tendency toward sub-harmonic oscillations for the SIMO converter is proposed: a double slope compensation, with one implemented on the current-mode control loop and the other on the comparator-based control loop.

From a simplified theoretical analysis of the operating principle of the converter, inequalities are identified that describe the boundaries between stable operation and bifurcation. Moreover, the impactful circuit parameters are identified. An accurate model of the SIMO converter is implemented in Matlab/Simulink, with all possible switches' states defined by a state-space model with varying matrices. Through system-level simulation, the boundaries between stable operation and bifurcation are verified with respect to the impactful parameters.

**Author Contributions:** Conceptualization, M.G., X.L.-S., B.A., E.F. and N.J.; methodology, M.G.; software, M.G., E.F., N.J.; validation, M.G.; formal analysis, M.G.; investigation, M.G.; resources, M.G., X.L.-S., B.A., E.F. and N.J.; data curation, M.G.; writing—original draft preparation, M.G., X.L.-S., B.A., E.F. and N.J.; writing—review and editing, M.G., X.L.-S., B.A., E.F. and N.J.; visualization, M.G.; supervision, X.L.-S., B.A., E.F. and N.J.; project administration, X.L.-S., B.A., E.F. and N.J.; All authors have read and agreed to the published version of the manuscript.

**Funding:** This research received no external funding

**Data Availability Statement:** The original contributions presented in this study are included in the article. Further inquiries can be directed to the corresponding author.

**Conflicts of Interest:** Mathieu Ginet, Eric Feltrin and Nicolas Jeanniot are employees of STMicroelectronics. The remaining authors declare that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.
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