# ZVS Analysis and Design of Four-Port CLLC Converters for Automotive Battery Chargers

Zhen Huang, Mattia Iurich, Thomas Langbauer, Franz Vollmaier, Roberto

Petrella, Michael Hartmann

► To cite this version:

Zhen Huang, Mattia Iurich, Thomas Langbauer, Franz Vollmaier, Roberto Petrella, et al. ZVS Analysis and Design of Four-Port CLLC Converters for Automotive Battery Chargers. The 26th European Conference on Power Electronics and Applications, GDR SEEDS France & EPE Association, Mar 2025, Paris, France. 10.34746/epe2025-0060. hal-05077835

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Submitted on 21 May 2025

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Distributed under a Creative Commons Attribution 4.0 International License
# ZVS Analysis and Design of Four-Port CLLC Converters for Automotive Battery Chargers

Zhen Huang¹, Mattia Iurich¹, Thomas Langbauer¹, Franz Vollmaier¹, Roberto Petrella²,³ and Michael Hartmann⁴

¹ Architectures & Topologies, Division Power Electronics, Silicon Austria Labs GmbH (SAL)

² System Level Integration Technologies, Division Power Electronics, Silicon Austria Labs GmbH (SAL)

³ Polytechnic Department of Engineering and Architecture (DPIA), University of Udine

⁴ Electric Drives and Power Electronic Systems Institute (EALS), Graz University of Technology

¹ Sandgasse 34, 8010 Graz, Austria

² Europastraße 12, 9524 Villach, Austria

³ Via delle Scienze 206, 33100 Udine, Italy

⁴ Inffeldgasse 18, 8010 Graz, Austria

Tel: +43 / (0) - 664.8396156

E-Mail: zhen.huang@silicon-austria.com

URL: https://silicon-austria-labs.com/

## ACKNOWLEDGMENT

This work has been jointly supported by AVL List GmbH, Fronius International GmbH, Infineon Technologies Austria AG, Infineon Technologies AG, META SYSTEM S.P.A., TDK Electronics GmbH, Technische Universität Graz and by Silicon Austria Labs (SAL), owned by the Republic of Austria, the Styrian Business Promotion Agency (SFG), the federal state of Carinthia, the Upper Austrian Research (UAR), and the Austrian Association for the Electric and Electronics Industry (FEEI).

## KEYWORDS

«Multi-port converters», «CLLC resonant converter», «On-board charger», «Zero-voltage switching», «DCX».

**Abstract**—Resonant DC/DC converters in DC transformer (DCX) operating mode emerged to be an optimal solution for isolated DC/DC converters due to its simple circuit structure and soft-switching behavior of the primary and secondary switches. The zero voltage switching (ZVS) condition in a bidirectional CLLC DCX converter is, however, dependent on dead-time, resonant tank parameters and load current. In this work the ZVS behavior of this structure is fully analyzed. Detailed circuitual and closed-form analytical model of the time behavior of the resonant inductor and stray capacitance currents, as well as the drain-source voltage of the power devices, during the dead-time interval is provided, aiming an optimal prediction/selection based on the resonant tank parameters and load current. Validation of the proposed analytical calculations is done under the simplifying assumption of constant output capacitance of the power devices during the switching transient. Even under a limited validity of the proposed analysis under the considered strong assumption, it anyhow allows to gain further insights on the ZVS operation as a function of main design parameters of the converter by a fast analytical approach. A laboratory prototype of a DC/DC converter for on-board charger (OBC) applications with an output power of 11 kW has been constructed and preliminary experimental results are provided.

## I. INTRODUCTION

With the increased penetration of electric vehicles (EVs) and the need for charging their high voltage (HV) batteries, automotive OBCs have become essential. A typical OBC

consists of an ac/dc conversion stage aiming to interface with the distribution grid and ensure unity power factor and low current total harmonic distortion (THD), connected to an isolated dc/dc converter that controls the charging voltage-current profile and provides galvanic isolation between the grid and the HV battery. The main design criteria for OBCs are high efficiency, reasonable cost, single-phase (1-Φ) and three-phase (3-Φ) operability, and high power-to-weight ratio (PWR).

Two different concepts exist for implementation of the 3-Φ OBC, i.e., phase modular systems and pure 3-Φ systems. The phase modular approach normally allows better efficiency in 1-Φ operation than classical pure 3-Φ systems. In such a configuration, each phase module is operated at 1-Φ, with possible parallelization to increase the output power, with the drawback of twice the line frequency power fluctuations in the individual DC-link of each module [1], [2].

To achieve a high power density for phase modular concepts, a multiport dc/dc converter with an high-frequency (HF) transformer with integrated windings can be adopted, as comprehensively studied and investigated for OBCs in [3], [4]. As magnetic components dominate the overall volume of the converter, an increased switching frequency yields an enhanced power density which can be enabled by application of Gallium Nitride (GaN)-high-electron-mobility transistors (HEMTs). In addition, a flat design is preferred to enable high system integration, which is typically achieved with a planar transformer approach. The *CLLC* topology operating at (or below) the resonance frequency in DCX mode is an ideal solution due to the constant voltage ratio in open loop and the ZVS feature for all load conditions [5].

The metal oxide semiconductor field effect transistor (MOSFET)-based DCX achieves natural bidirectional operation when adopting dual-active-synchronous (DAS) modulation strategy, namely applying identical driving signals to the primary and secondary sides [6]. The same principle applies for a GaN-HEMT-based DCX. Considering ideal switching transitions, ZVS can indeed be assured over a wide operat-
ing range, however, this is not always the case in practical implementation [5], [6]. Current ringing between resonant inductors and device output capacitance during deadtime may inhibit ZVS condition as shown in [7]. The non-ideal current ringing is affected by load and resonant parameters, and the modulation strategy [8].

Several methods have been introduced to overcome this limitation. In [7], a modulation and dead-time selection approach has been proposed to ensure ZVS, however, this approach results in a small magnetizing inductance. In [8], a modulation strategy is proposed to reduce the impact of secondary side commutation on the primary side by turning off the secondary side bridge earlier than the primary side one. However, there is a lack of detailed analysis of the mechanism and the effective dead-time becomes too long compared to the switching period.

The time domain transition analysis for a DCX in *LLC* structure is given in [9], however, in this work, the influence of magnetizing current to ZVS of the primary side bridge-legs after commutation of the secondary side bridge-legs is finished has not been considered. The current ringing of DCX under DAS modulation is analyzed in [10], but does not take into account the transformer stray capacitance and/or the influence of circuit resonant parameters, which represent the main issues in the selection of the dead-time interval in a real application scenario.

High-frequency oscillations (HFOs) stimulated by the high $dv/dt$ of modern power semiconductors associated with the stray capacitance of the transformer has been discussed for dual-active-bridge (DAB) converters in [11]. These oscillations result in large voltage spikes and severe electro-magnetic interference (EMI) issues. Converters based on the *CLLC* topology have not been sufficiently analyzed regarding this effect, although similar HFOs may occur during dead-time.

In this work the ZVS behavior of a bidirectional CLLC DCX converter is fully analyzed and detailed circuital and analytical model of the current evolution during the dead-time interval is provided, aiming at its optimal prediction/selection based on the resonant tank parameters and load current. A simplifying hypothesis is introduced to allow calculation of the closed form solution of the differential equations, i.e., the power devices output capacitance $C_{oss}$ is considered constant during the switching event. This represents for sure a strong

assumption, but aims at demonstrating that a proper (and complex) solution to the problem can be provided, and to gain further insights on the ZVS operation as a function of main design parameters of the converter. Extension to the nonlinear case is for sure not straightforward (and is not the main objective of this paper), and will be analyzed in a future work.

The basic structure of the OBC considered in this paper is depicted in Fig. 1, consisting of three single-phase power factor correction (PFC) modular stages and a multi-port DCX adopting a *CLLC* structure, where each phase is feeding one of the three primary windings of the transformer.

As already discussed, in the single-phase PFC stages a power fluctuation with twice the grid line frequency exists which would imply the adoption of quite large DC-link capacitors on each module to smoothen the input voltages $V_{dc,pri}$ of each DCX. An additional active pulsating buffer is connected between PFC and DCX to further shrink down the size of the PFC stage [12].

A DCX design and optimization procedure is proposed based on the analytical calculations, to ensure ZVS for all load conditions and achieve optimal performance for power devices, as illustrated in Fig. 2. Main individual steps will be discussed in detail in the following sections.

This paper is organized as follows. Section II introduces an equivalent 2-port circuit diagram and presentes the adopted modulation approach. Section III shows the transition analysis of the DCX converter under the simplifying assumption of constant switch capacitance, allowing a closed form calculation of the current trajetory during the dead-time interval.

<figure><img src="image_2.png" /><figcaption>Fig. 2. Proposed procedure for optimal multiport DCX design.</figcaption></figure>

<figure><img src="image_3.png" /><figcaption>Fig. 1. Topology of the OBC with a HF multiport DCX. The phase modules a, b and c are connected either to the 1-Φ or 3-Φ grid. The HV port is connected to the HV battery. Input and output voltage ranges are shown with the colored bars.</figcaption></figure>
<figure><img src="image_4.png" /><figcaption>Fig. 3. Topology of the 4-port DCX.</figcaption></figure>

In section IV, the proposed analysis is verified by detailed circuit simulation, and the effects of output power and circuit parameters on the achievable ZVS operating conditions are discussed. The DCX converter prototype is described in section V, together with some preliminary tests. Concluding remarks and an outlook on future work are reported in Section VI.

## II. CONVERTER MODELLING AND MODULATION STRATEGY

In a first step, it is assumed that the 3-to-1 DCX can operate as a 1-to-1 converter when the three primary ports are operated synchronously. Subsequently, the simplified 1-to-1 equivalent circuit is given. Furthermore, the DAS modulation strategy is introduced.

### A. Simplified equivalent model

Fig. 3 shows the basic structure of the considered 4-port HF DCX converter. Table I lists main operating parameters. The considered 11 kW all-GaN converter operates in a 3-to-1 manner where the three primary ports operate synchronously to shift power from/to the secondary port connected to the HV-battery with a voltage range of 250 V to 450 V. The DC-link voltages $V_{dc,pri}$ are all equal and follow the secondary port voltage controlled by the phase-modular active front end (AFE) converters with active buffers. In order not to loose generality, the transformer turns ratio is shown as $n:n:n:1$ in Fig. 3. The turns ratio of the planar transformer of the final prototype has been chosen as $n=1$, due to the considered voltage ranges at the grid- and battery-sides. The transformer equivalent circuit is described with an ideal 4-port transformer (with turn ratio $n$) and the magnetizing inductance $L_{m,sec}$, whereas the leakage inductances are incorporated with the resonant inductors in the reported circuit diagram. The resonant tanks of the three primary ports are designed to be symmetrical with $\omega_{res} = 1/\sqrt{L_{r,pri}C_{r,pri}} = 1/\sqrt{L_{r,sec}C_{r,sec}} = 2\pi f_{res}$. The resonant frequency $f_{res}$ is selected to optimize the transformer performance by balancing the core loss and copper loss, whereas the switching frequency $f_{sw}$ is defined in the following parts of this article.

Assuming synchronization of the three primary ports, this 3-to-1 DCX can be modeled as a standard 2-port CLLC DCX, as shown in Fig. 4a. Due to the similar principle of nonlinear device output capacitance behavior of GaN-HEMTs and standard silicon MOSFETs, the switches are represented by MOSFET symbols in Fig. 4a in order not to lose generality. Under this condition, the equivalent circuit of the transformer

<table><caption>TABLE I
PARAMETERS OF THE CONSIDERED MULTI-PORT DCX</caption><thead><tr><td>Variable</td><td>Value</td></tr></thead><tbody><tr><td>V<sub>dc,pri</sub></td><td>250 ~ 450 V</td></tr><tr><td>V<sub>dc,sec</sub></td><td>250 ~ 450 V</td></tr><tr><td>P</td><td>11 kW</td></tr><tr><td>f<sub>res</sub></td><td>600 kHz</td></tr></tbody></table>

<figure><img src="image_5.png" /><figcaption>Fig. 4. (a) Equivalent 2-port circuit diagram of the CLLC DCX. (b) Equivalent 2-port circuit diagram with secondary circuits referred to the primary side.</figcaption></figure>

is simplified into a 2-port model consisting of an ideal transformer, an equivalent magnetizing inductance, and a lumped equivalent stray capacitance, i.e., main parameters being $n$, $L_{m,eq}$, and $C_{wp,eq}$. The stray capacitance of the PCB winding has been measured in the actual prototype using an impedance analyzer, resulting in a capacitance value of $\approx 160$ pF. The equivalent primary-side circuit parameters in Fig. 4a can be calculated as $L_{r,pri,eq} = L_{r,pri}/3$ and $C_{r,pri,eq} = 3C_{r,pri}$. The two values $R_{s,pri}$ and $R_{s,sec}$ are the equivalent series resistances in the primary- and in the secondary-side circuits, respectively.

The simplified 1-to-1 DCX circuit is simulated in LTspice and compared with the simulation waveforms of the 3-to-1 DCX converter, without considering the transformer winding capacitance. The good correlation between the steady state behaviors of two simulations shown in Fig. 5 justify the simplification process.

To facilitate transition analysis during the dead-time interval, the output capacitance of the nonlinear device is modeled by the charge-equivalent value [13], and for the 1-to-1 DCX configuration is assumed, that is, $C_{oss,pri,eq} = 3C_{oss,pri}$.

The secondary side circuit is referred to the primary side as presented in Fig. 4b. The transformed secondary side
parameters (i.e., subscript Tsec) can be expressed as

$$ egin{cases} V_{dc,Tsec} = n \cdot V_{dc,sec}, & I_{r,Tsec} = I_{r,sec}/n \\ L_{r,Tsec} = n^2 L_{r,sec}, & C_{r,Tsec} = C_{r,sec}/n^2 \\ R_{s,Tsec} = n^2 R_{s,sec}, & C_{oss,Tsec} = C_{oss,sec}/n^2. \end{cases} \quad (1) $$

It is worth mentioning that this assumption will prove to be incorrect, as the differential equations accounting for the time-domain circuit behavior should take the actual time-dependent capacitance during the voltage transition into account, being in turn a function of the time-dependent voltage across the capacitor itself, and cannot be approximated by a single value for the solution purposes. However, the general approach presented hereafter is still valid, but further investigation is needed for a proper modeling of the capacitance variation, as will be demonstrated in the simulation analysis reported later in the paper.

## B. Modulation scheme of the DCX

The modulation of insulated-gate bipolar transistor (IGBT)-based DCXs has been analyzed in detail in [14], [15]. Typically operation slightly below resonance is considered in a discontinuous conduction mode, aiming at achieving zero current switching (ZCS) for IGBTs and load independence feature, whilst the magnetizing current is considered mainly to facilitate the charge-carriers recombination and switching loss reduction [14]. Whereas in MOSFET-based DCXs, it is often assumed that this below-resonance operation is not necessary [5], [6], as magnetizing current is meant to be discharging the device output capacitance and the transformer stray capacitance during the dead-time interval $T_d$ [6]. The magnetizing inductance $L_m$ should satisfy the following requirement to ensure ZVS for all semiconductors

$$ L_m \le \frac{T_d}{8f_{sw} \cdot (C_{oss,pri} + C_{wp,eq} + C_{oss,Tsec})} \quad (2) $$

However, this ZVS criteria is not valid in all operating conditions when the DCX operates exactly at the resonance frequency and uses DAS modulation approach. A significant current distortion on the resonant inductor current is observed, as shown in the simulation results reported in Fig. 6a, which can lead to failure of ZVS of primary side switches.

An active phase shift modulation strategy is adopted in [5] to reduce the current ringing amplitude by manipulating

<figure><img src="image_6.png" /><figcaption>Fig. 5. Comparison of simulated current waveforms of the (a) 3-to-1 and (b) simplified 1-to-1 DCX (no stray capacitance has been considered in this test).</figcaption></figure>

<figure><img src="image_7.png" /><figcaption>Fig. 6. DAS modulation approach. (a) Simulated currents of a DCX when operating directly at the resonance frequency. (b) Simulated currents under DAS modulation.</figcaption></figure>

the reactive current. To avoid this active control of a DCX converter, a MOSFET-based or GaN-HEMT-based DCX can be operated below resonance using DAS modulation approach at the switching frequency described in (3).

$$ egin{aligned} T_{\text{cond}} &= \frac{1}{2f_{\text{res}}} \\ f_{\text{sw}} &= \frac{1/2}{T_{\text{cond}} + T_d}. \end{aligned} \quad (3) $$

The $T_{cond}$ denotes the conduction interval of each half switching period. The corresponding current waveforms are shown in Fig. 6b, where the current ringing is reduced. Nevertheless, the current distortion during the dead-time interval is impacted by the load current and circuit parameters, and affects the ZVS condition and are therefore analyzed in detail in the next section.

## III. SWITCHING TRANSITION ANALYSIS

The switching transition of the DCX under DAS modulation is analyzed in detail in this section and the time-domain expressions of the resonant current and device voltages during the dead-time interval (from $t_1$ to $t_2$ shown in Fig. 6b) are provided.

The simplified equivalent circuit during the dead-time interval is shown in Fig. 7. The primary-side switches $Q_1$, $Q_4$ and the secondary-side switches $S_1$, $S_4$ in Fig. 4b are on during $t_0$ to $t_1$, and it is assumed that $Q_1$ and $Q_4$ as well as $S_1$, $S_4$ are turned off at $t_1$.

The impact of the dead-time interval on the resonant current can be divided into two distinct oscillation processes featuring different fundamental frequencies. The predominant oscillation happens due to the resonance between the device output capacitance and the resonant inductor, as illustrated in Fig. 7, which is normally addressed as current ringing in literature [10]. The other oscillation is the HFO depicted in Fig. 8, namely the resonance between resonant inductors and the transformer stray capacitance $C_{wp,eq}$ induced by the high $dv/dt$ during the dead-time interval. A simple model assuming that the switch node voltage is linearly changing is shown in Fig. 9.

### A. Resonant current ringing analysis

During the dead-time interval from $t_1$ to $t_2$, the system can be described by a set of equations (4) - (10). Equation (4) and (5) describe the Kirchhoff Voltage Law (KVL) at the primary- and at the secondary-side, including $Q_1$ and $Q_4$,
<figure><img src="image_8.png" /><figcaption>Fig. 7. Simplified equivalent circuit for main transition process during the dead-time interval.</figcaption></figure>

<figure><img src="image_9.png" /><figcaption>Fig. 8. Simplified equivalent circuit for analyzing the HFO process between resonant inductors and stray capacitance.</figcaption></figure>

<figure><img src="image_10.png" /><figcaption>Fig. 9. Approximation of $dv/dt$ between primary side and secondary side switch nodes during the dead-time interval.</figcaption></figure>

and S₁ and S₄, respectively. Equations (6) and (7) represent the constitutive equations of the primary- and secondary-side output capacitance of the power devices, highlighting the resonant currents which is used to discharge them during the dead-time interval. The remaining equations (8) to (10) describe the relationship between resonant inductor currents, magnetizing current and the differential mode (DM) current flowing through the stray capacitance.

$$ u_{\text{Cr,pri,eq}}(t) + L_{\text{r,pri,eq}} \frac{di_{\text{r,pri}}(t)}{dt} + R_{\text{s,pri,eq}} i_{\text{r,pri}}(t) + u_{\text{Lm}}(t) = V_{\text{dc,pri}} - u_{\text{Q1}}(t) - u_{\text{Q4}}(t) \quad (4) $$

$$ -u_{\text{Cr,Tsec}}(t) - L_{\text{r,Tsec}} \frac{di_{\text{r,Tsec}}(t)}{dt} - R_{\text{s,Tsec}} i_{\text{r,Tsec}}(t) + u_{\text{Lm}}(t) = V_{\text{dc,Tsec}} - u_{\text{S1}}(t) - u_{\text{S4}}(t) \quad (5) $$

$$ C_{\text{oss,pri,eq}} \frac{du_{\text{Q1}}(t)}{dt} = C_{\text{oss,pri,eq}} \frac{du_{\text{Q4}}(t)}{dt} = \frac{1}{2} i_{\text{r,pri}}(t) \quad (6) $$

$$ C_{\text{oss,Tsec}} \frac{du_{\text{S1}}(t)}{dt} = C_{\text{oss,Tsec}} \frac{du_{\text{S4}}(t)}{dt} = -\frac{1}{2} i_{\text{r,Tsec}}(t) \quad (7) $$

$$ i_{\text{Lm}}(t) = i_{\text{r,pri}}(t) - i_{\text{r,Tsec}}(t) - i_{\text{Cw}}(t) \quad (8) $$

$$ u_{\text{Lm}}(t) = L_{\text{m,eq}} \frac{di_{\text{Lm}}(t)}{dt} \quad (9) $$

$$ i_{\text{Cw}}(t) = C_{\text{wp,eq}} \frac{du_{\text{Lm}}(t)}{dt} \quad (10) $$

Substituting (5) and (8) into (4) and by elimination of $i_{\text{r,Tsec}}(t)$, (11) is derived, showing the relationship between $i_{\text{r,pri}}$ and $i_{\text{Lm}} + i_{\text{Cw}}$. To reduce complexity of symbols, the eq subscript of $L_m$ is omitted in $i_{\text{Lm}}$ and $u_{\text{Lm}}$ symbols.

The current $i_{\text{Cw}}(t)$ flowing through the parasitic winding capacitance is neglected at this stage of analysis since it is mainly induced by the high $dv/dt$ during the dead-time interval and features a different fundamental frequency when resonating with the resonant inductors, as already discussed and shown in Fig. 8. However, its analysis will be recovered in the next subsection III-B.

Deriving (4) to get the second time derivative of $i_{\text{Lm}}(t)$ and substitute it into (11) yields to the expression

$$ \begin{aligned} & L_{\text{r,eq}} \frac{d^2 i_{\text{r,pri}}(t)}{dt^2} + R_{\text{s,eq}} \frac{di_{\text{r,pri}}(t)}{dt} + \frac{i_{\text{r,pri}}(t)}{C_{\text{oss,eq}}} \\ &= R_{\text{s,Tsec}} \frac{di_{\text{Lm}}(t)}{dt} + \frac{i_{\text{Lm}}(t)}{C_{\text{oss,Tsec}}} \end{aligned} \quad (12) $$

in which, the coefficients on the left side are

$$ L_{\text{r,eq}} = \lambda L_{\text{r,pri,eq}} + L_{\text{r,Tsec}} \quad (13) $$

$$ R_{\text{s,eq}} = \lambda R_{\text{s,pri,eq}} + R_{\text{s,Tsec}} \quad (14) $$

$$ C_{\text{oss,eq}} = \frac{1}{\frac{\lambda}{C_{\text{oss,pri,eq}}} + \frac{1}{C_{\text{oss,Tsec}}} + \frac{\lambda}{C_{\text{r,pri,eq}}} + \frac{1}{C_{\text{r,Tsec}}}} \quad (15) $$

with

$$ \lambda = 1 + \frac{1}{L_n}, \quad L_n = \frac{L_{\text{m,eq}}}{L_{\text{r,pri,eq}}}. $$

As $C_{\text{r,pri,eq}} = C_{\text{r,Tsec}} \gg C_{\text{oss,pri,eq}}$ or $C_{\text{oss,Tsec}}$, the equivalent capacitor $C_{\text{oss,eq}}$ can be simplified to

$$ C_{\text{oss,eq}} = \frac{C_{\text{oss,pri,eq}} \cdot C_{\text{oss,Tsec}}}{C_{\text{oss,pri,eq}} + \lambda C_{\text{oss,Tsec}}}. \quad (16) $$

The right-hand side of (12) is a high-order differential polynomial of $i_{\text{Lm}}(t)$. As mentioned at the beginning of this chapter, a segmental linear function can be used to represent the switch node voltages of a DCX as the voltage drop on the resonant tanks are comparatively low at the operation frequency. This is a valid approximation unless the resonant inductor currents change signs during dead-time interval and cause oscillations on the device drain-source voltages, which might lead to loss of ZVS condition. In this case, the magnetizing current can be expressed as

$$ i_{\text{Lm}}(t) = i_{\text{Lm}}(t_1) + \frac{V_{\text{dc,pri}}}{L_m}(t - t_1) - \frac{V_{\text{dc,pri}}}{L_m T_d}(t - t_1)^2 \quad (17) $$

in which $i_{\text{Lm}}(t_1) = \frac{V_{\text{dc,pri}}(1-2f_{\text{sw}}T_d)}{4L_m f_{\text{sw}}}$.

$$ \begin{aligned} & (L_{\text{r,pri}} + L_{\text{r,Tsec}}) \frac{d^2 i_{\text{r,pri}}(t)}{dt^2} + (R_{\text{s,pri,eq}} + R_{\text{s,Tsec}}) \frac{di_{\text{r,pri}}(t)}{dt} + (\frac{1}{C_{\text{oss,pri}}} + \frac{1}{C_{\text{oss,Tsec}}} + \frac{1}{C_{\text{r,pri}}} + \frac{1}{C_{\text{r,Tsec}}}) i_{\text{r,pri}}(t) \\ &= L_{\text{r,Tsec}} \frac{d^2 (i_{\text{Lm}}(t) + i_{\text{Cw}}(t))}{dt^2} + R_{\text{s,Tsec}} \frac{d (i_{\text{Lm}}(t) + i_{\text{Cw}}(t))}{dt} + (\frac{1}{C_{\text{r,Tsec}}} + \frac{1}{C_{\text{oss,Tsec}}}) (i_{\text{Lm}}(t) + i_{\text{Cw}}(t)) \end{aligned} \quad (11) $$
Substituting (17) into the right side of (12) yields the expression in (18). As $\frac{1-2f_{sw}T_d}{4f_{sw}C_{oss,Tsec}} \gg R_{s,Tsec}$, and $\frac{1}{C_{oss,Tsec}} \gg \frac{2R_{s,Tsec}}{T_d}$, (18) can be more simplified to (19). Equations (18) and (19) can be found at the bottom of this page.

Solution of (12) requires the knowledge/definition of the initial conditions (i.e., at $t = t_1$) for $i_{r,pri}$ and its time derivative $\frac{di_{r,pri}}{dt}$.

Under DAS modulation, the initial state of primary-side resonant inductor current $i_{r,pri}|_{t=t_1}$ is expressed by

$$i_{r,pri}(t_1) = \frac{C_{oss,pri,eq}}{C_{oss,pri,eq} + C_{oss,Tsec}} i_{Lm}(t_1) \quad (20)$$

meaning that the magnetizing current is split between the primary side and secondary side circuits according to the ratio of corresponding charge equivalent output capacitance of the switches. Because the active current has decreased to zero at $t_1$, there is only the reactive current, which is magnetizing current in the CLLC DCX, recirculating in the circuit during dead-time interval and output capacitance of the switches. As shown in Fig. 7, the impedance of the equivalent capacitors define how the magnetizing current is shared between the primary- and secondary-sides.

The other initial state $\frac{di_{r,pri}}{dt}|_{t=t_1}$ can be obtained from (4). As the capacitor voltage cannot change instantaneously and the voltage drop on the resonant tank is nearly zero when operating close to the resonance frequency, the value of $\frac{di_{r,pri}}{dt}|_{t=t_1}$ could be derived from the resonant capacitor voltage at $t_1$, which is load-dependent

$$u_{Cr,pri,eq}(t_1) = \frac{P_{in}}{4f_{sw}C_{r,pri,eq}V_{dc,pri}} \quad (21)$$

where $P_{in}$ is the input power of the DCX.

Based on the considered assumptions, a solution for (12) can now be given, i.e., the current $i_{r,pri}$ during dead-time interval can be expressed as

$$i_{r,pri}(t) = e^{-\frac{R_{s,eq}}{2L_{r,eq}}(t-t_1)} \left[ A_1 \cos(\omega_{ring}(t-t_1)) + A_2 \sin(\omega_{ring}(t-t_1)) \right] + A_3 \quad (22)$$

in which the coefficients are

$$\begin{align*} \omega_{ring} &= \sqrt{\frac{1}{L_{r,eq}C_{eq}} - \frac{R_{s,eq}^2}{4L_{r,eq}^2}} \\ A_1 &= i_{r,pri}(t_1) - a_0 \\ A_2 &= \frac{-u_{Cr,pri,eq}(t_1)}{L_{r,pri,eq}\omega_{ring}} + \frac{R_{s,eq}}{2L_{r,eq}\omega_{ring}}(i_{r,pri}(t_1) - a_0) - \frac{a_1}{\omega_{ring}} \\ A_3 &= a_2(t - t_1)^2 + a_1(t - t_1) + a_0. \end{align*}$$

<figure><img src="image_11.png" /><figcaption>Fig. 10. Simplified equivalent circuit for analyzing the HFO process between resonant inductors and stray capacitance (initial state of the stray capacitance is included).</figcaption></figure>

$$a_2 = - \frac{C_{oss,eq}V_{dc,pri}}{C_{oss,Tsec}L_m T_d}$$

$$a_1 = C_{oss,eq} \cdot \left( \frac{V_{dc,pri}}{C_{oss,Tsec}L_m} - 2a_2 R_{s,eq} \right)$$

$$a_0 = C_{oss,eq} \cdot \left( \frac{i_{Lm}(t_1)}{C_{oss,Tsec}} - 2a_2 L_{r,pri,eq} - a_1 R_{s,eq} \right).$$

## B. High-frequency oscillation analysis

The HFO process occurring between the resonant inductors and the transformer stray capacitance and excited by the high $dv/dt$ voltage transition at the switch node is analyzed in this subsection. The simplified equivalent circuit describing this process is reported in Fig. 8. The switch node voltage during the commutation can be approximated by a segmental linear function, as already shown in Fig. 9 and expressed by

$$u_{sw}(t) = V_{dc} + K \left( (t - t_1)\theta(t - t_1) - (t - t_1 - T_d)\theta(t - t_1 - T_d) \right) \quad (23)$$

in which

$$K = -\frac{2V_{dc}}{T_d}, \quad V_{dc} = \frac{1}{2}(V_{dc,pri} + V_{dc,Tsec}).$$

The stray capacitance $C_{wp,eq}$ is normally smaller than the device output capacitance $C_{oss}$, and furthermore the resonant inductors are paralleled in this process. Thus the HFO features a higher fundamental frequency than the current ringing process already described in the last subsection, allowing to be analyzed separately, i.e., the superposition principle is applied (with some limitations that will be addressed later). The resonant inductor currents at the resulting oscillation frequency are written as $i_{r,pri,HF}$ and $i_{r,Tsec,HF}$. The corresponding equivalent series resistances are denoted by $R_{s,pri,HF}$ and $R_{s,Tsec,HF}$, which could be easily obtained from measurements on the actual circuit. Considering the operation frequency the transformer is designed for, it can be assumed that the series resistances are big enough to attenuate the HFO within each half-switching period. Therefore, the initial states of the HFO currents are both considered to be zero. Based on this assumption, the Thevenin's equivalent circuit can be drawn as reported in Fig. 11, where the corresponding

$$\dots = \left( \frac{1}{C_{oss,Tsec}} - \frac{2R_{s,Tsec}}{T_d} \right) \frac{V_{dc,pri}}{L_m} t + \frac{V_{dc,pri}}{C_{oss,Tsec}L_m T_d} t^2 + \left( \frac{1 - 2f_{sw}T_d}{4f_{sw}C_{oss,Tsec}} + R_{s,Tsec} \right) \frac{V_{dc,pri}}{L_m} \quad (18)$$

$$\dots = \frac{V_{dc,pri}}{L_m C_{oss,Tsec}} t + \frac{V_{dc,pri}}{C_{oss,Tsec} L_m T_d} t^2 + \frac{(1 - 2f_{sw}T_d) V_{dc,pri}}{4 f_{sw} L_m C_{oss,Tsec}} \quad (19)$$
<figure><img src="image_12.png" /><figcaption>Fig. 11. Thevenin equivalent circuit governing the HFO process.</figcaption></figure>

parameters are given in the equations (24) - (27).

$$L_{r,HF,eq} = \frac{L_{r,pri,eq} \cdot L_{r,Tsec}}{L_{r,pri,eq} + L_{r,Tsec}} \quad (24)$$

$$R_{s,HF,eq} = \frac{R_{s,HF,pri} \cdot R_{s,HF,Tsec}}{R_{s,HF,pri} + R_{s,HF,Tsec}} \quad (25)$$

$$C_{r,HF,eq} = C_{r,pri,eq} + C_{r,Tsec} \quad (26)$$

$$u_{sw}(t) = u_{sw12}(t) + u_{sw34}(t). \quad (27)$$

The stray capacitance voltage $u_{Cw}(t)$ is then derived by solving the zero-input and zero-state response separately in this case. Again, the output capacitance of the power devices is considered constant to allow a simple solution of the differential equation, as it will discussed in detail in the next section. Also, because $C_{r,HF,eq} \gg C_{wp,eq}$, the capacitance $C_{r,HF,eq}$ can be neglected to simplify the analysis as it will behave like a short circuit in the considered frequency range.

The zero-state response during the dead-time interval is expressed in (28) and the zero-input response is shown in (29), where the oscillation frequency is given by

$$\omega_{HF} = \sqrt{\frac{1}{L_{HF,eq}C_{wp,eq}} - \frac{R_{s,HF,eq}^2}{4L_{HF,eq}^2}}$$

Finally, the overall voltage response can be calculated by summing up these two components

$$u_{Cw}(t) = u_{Cw,ZSR}(t) + u_{Cw,ZIR}(t). \quad (30)$$

The DM current flowing through the stray capacitance $i_{Cw}$ is obtained from (10). The high-frequency part primary-side resonant current is finally

$$i_{r,pri,HF}(t) = \frac{1}{2}i_{Cw}(t). \quad (31)$$

## IV. MODEL VALIDATION

Based on the former analysis, the overall primary-side resonant current can be calculated by applying the superposition principle, i.e., summing up the component derived from current ringing and HFO

$$i_{r,pri,tot}(t) = i_{r,pri}(t) + i_{r,pri,HF}(t). \quad (32)$$

<table><caption>TABLE II
MAIN CIRCUIT PARAMETERS CONSIDERED FOR THE CONVERTER ANALYSIS</caption><thead><tr><th>Variable</th><th>Value</th></tr></thead><tbody><tr><td>V<sub>dc,pri</sub> / V<sub>dc,sec</sub></td><td>250 V / 245 V</td></tr><tr><td>P<sub>in</sub></td><td>2 kW</td></tr><tr><td>f<sub>res</sub> / f<sub>sw</sub></td><td>627 kHz / 580 kHz</td></tr><tr><td>T<sub>d</sub></td><td>60 ns</td></tr><tr><td>L<sub>m</sub></td><td>10 µH</td></tr><tr><td>L<sub>r,pri,eq</sub> / L<sub>r,Tsec</sub></td><td>280 nH / 280 nH</td></tr><tr><td>C<sub>r,pri,eq</sub> / C<sub>r,Tsec</sub></td><td>230 nF / 230 nF</td></tr><tr><td>C<sub>wp,eq</sub></td><td>160 pF</td></tr><tr><td>R<sub>s,pri,eq</sub> / R<sub>s,Tsec</sub></td><td>80 mΩ / 80 mΩ</td></tr><tr><td>R<sub>s,pri,HF</sub> / R<sub>s,Tsec,HF</sub></td><td>8 Ω / 8 Ω</td></tr><tr><td>GaN power devices</td><td>2 × 4 GS66516T</td></tr></tbody></table>

Therefore, the voltage of the primary switches $u_{Q,pri}(t)$ (of $Q_1$ or $Q_4$, being charged in this case, whilst $Q_2$ or $Q_3$ discharged in the meanwhile) can be derived

$$u_{Q1}(t) = \frac{1}{C_{oss,pri,nonlinear}} \int_{t_1}^{t} i_{Q1}(t) dt. \quad (33)$$

It is well-known that the parasitic output capacitance $C_{oss}$ of the power devices exhibits a nonlinear dependency on the drain-source voltage $U_{ds}$. Thus, the current $i_Q$ flowing into the device output capacitance $C_{oss}$ and the drain-source voltage $U_{ds}$ are all time-dependent functions. A linear charge-equivalent capacitance is normally introduced to represent the same amount of stored charge as the nonlinear capacitance a given drain-source voltage $U_{ds}$, thus facilitating charge-based ZVS analysis [13].

In this case, this equivalent capacitance cannot accurately represent the actual time-dependent voltage transition across the drain-source terminals. Nevertheless, a constant capacitance is assumed helping to solve the analytical model presented in the previous sections for the drain-source voltage transition within the dead-time interval, which is useful to validate the analytical approach and results, and that can be assumed as a starting point for ZVS analysis. Under this assumption, the drain-source voltage $U_{ds}$ of switch $Q_1$ is expressed by

$$u_{Q1}(t) = \frac{1}{2C_{oss,pri,eq}} \int_{t_1}^{t} i_{r,pri}(t) dt. \quad (34)$$

The developed analytical model has been verified by comparing the time dependent resonant inductor and stray capacitance currents with the ones coming from a dynamical

$$u_{Cw,ZSR}(t) = (V_{dc} - KC_{wp,eq}R_{s,HF,eq} + K(t - t_1))\theta(t - t_1) - ((V_{dc} - KC_{wp,eq}R_{s,HF,eq})\cos(\omega_{HF}(t - t_1)) + \frac{R_{s,HF,eq}V_{dc} - KC_{wp,eq}R_{s,HF,eq}^2 + 2KL_{r,HF,eq}}{2L_{r,HF,eq}\omega_{HF}}\sin(\omega_{HF}(t - t_1)))e^{-\frac{R_{s,HF,eq}}{2L_{r,HF,eq}}(t - t_1)}\theta(t - t_1) \quad (28)$$

$$u_{Cw,ZIR}(t) = \left( \cos(\omega_{HF}(t - t_1)) + \frac{R_{s,HF,eq}}{2L_{r,HF,eq}\omega_{HF}} \sin(\omega_{HF}(t - t_1)) V_{dc} e^{-\frac{R_{s,HF,eq}}{2L_{r,HF,eq}}(t - t_1)} \theta(t - t_1) \right) \quad (29)$$
<figure><img src="image_13.png" /></figure>

<figure><img src="image_14.png" /></figure>

<figure><img src="image_15.png" /><figcaption>Fig. 12. Comparison of calculated and simulated current and voltage waveforms using ideal switches and constant capacitors during dead-time interval at operation point $U_{dc,pri} = 250$ V, $I_{load} = 10$ A, (a) Resonant inductor currents (primary- and secondary-side). (b) Stray capacitance current. (c) Drain-source voltages of switch $Q_1$ and $S_1$.</figcaption></figure>

<figure><img src="image_16.png" /></figure>

<figure><img src="image_17.png" /></figure>

<figure><img src="image_18.png" /><figcaption>Fig. 13. Comparison of calculated and simulated current and voltage waveforms using device SPICE models (nonlinear $C_{oss}$) at operation point $U_{dc,pri} = 250$ V, $I_{load} = 10$ A, during dead-time interval. (a) Resonant inductor currents (primary- and secondary-side). (b) Stray capacitance current. (c) Drain-source voltages of switch $Q_1$ and $S_1$.</figcaption></figure>

simulation in LTspice. The verification is carried out into two steps: first, the simplified model of the power devices adopting constant charge-equivalent capacitors are used; then, the complete device model is adopted, including its nonlinear behavior with the drain-source voltage. The circuit parameters listed in Table II are used both for the analytical calculation and the simulation model. The equivalent stray capacitance is obtained on the actual prototype of the converter with an impedance analyzer.

A proper reference value for the dead-time interval is adopted to allow capturing the currents behavior within an enough high time range. A first comparison between the analytical and dynamical simulation results is considered, where the simplified model of the power devices adopting a constant value of output capacitance, i.e., the charge-equivalent one. The results are reported in Fig. 12, where the calculated resonant inductor currents (primary and secondary), transformer lumped stray capacitance currents, and the switch drain-source voltages at the primary-side during the transition process within the dead-time interval are reported in three different subplots. One can notice that a perfect agreement is obtained, thus proving that the analytical model is able to capture the actual time behavior of the converter within that operating region. The actual nonlinear model of the output capacitance power devices is then considered in the dynamical simulation model, and corresponding results are shown in Fig. 13. It is evident that the resonant inductor currents and transformer

stray capacitance current from the analytical calculations are not consistent with the dynamical simulation anymore, due to the considered nonlinearity of the output capacitance $C_{oss}$.

Further investigations have been conducted to map the relationship between current ringing behavior and load and circuit parameters, aiming at defining the ZVS regions associated to the different parameters and load conditions.

The output capacitance of switches $C_{oss}$ has the largest value at the lowest operating voltage, when the magnetizing current is the smallest. Therefore, for a DCX converter parameter selection fulfilling the specifications in Table I, the worst case for ZVS achievement at both primary and secondary side switches occur at the operating point $U_{dc,sec} = 250$ V and nominal power $P = 11$ kW. The dead-time interval has initially been selected to 100 ns. The value of the magnetizing inductance being required to ensure ZVS of the power devices was obtained with (2) at the lowest nominal input voltage. Based on these main parameters selection, the analysis of the resonant inductors currents and power devices voltages on both primary- and secondary-side of the converter has been carried out as a function of the resonant inductor value, i.e., the three values 0.1, 0.3 and 0.9 µH, and actual output (i.e., secondary-side) power, i.e., 10, 50 and 100% of the rated value. The results of the analysis are reported in Fig. 14 and Fig. 15 respectively.

According to Fig. 14a, the lowest value of the resonant inductance (i.e., 0.1 µH) guarantees that the resonant current at
<figure><img src="image_19.png" /><figcaption>Fig. 14. Calculated resonant inductors currents (a) and power devices voltages (b) for different values of the resonant inductance.</figcaption></figure>

<figure><img src="image_20.png" /><figcaption>Fig. 15. Calculated Resonant inductors currents (a) and power devices voltages (b) for different values of the output power.</figcaption></figure>

<figure><img src="image_21.png" /><figcaption>Fig. 16. Calculated dead-time interval and resonant parameter relevant ZVS region.</figcaption></figure>

<figure><img src="image_22.png" /><figcaption>Fig. 17. Picture of the laboratory DCX test setup.</figcaption></figure>

the primary-side is high (and positive) enough to completely discharge the low-side capacitance of $Q_2$ for the selected dead-time of 100 ns, thus achieving ZVS operation within the considered simulated time range for the dead-time interval (as proved by the voltage plots in Fig. 14b), and allowing to shrink its volume.

The results of similar simulations are reported in Fig. 15, where a constant value of the resonant inductance of $L_r = 0.3$ µH has been selected, and the output power has been swept as already pointed out. The amplitude of the current ringing increases when the load current is increased, as clearly shown in Fig. 15a. Generally, operating with maximum load is the worst-case scenario for ZVS design. Also in this case, ZVS operation is fully achieved at the secondary side within the considered simulated time range, whereas there is some remaining voltage for the primary side devices, proved by the voltage plots in Fig. 15b).

Finally, the resulting ZVS region based on the calculated current and voltage trajectories is plotted in Fig. 16 as a function of dead-time interval and converter parameter $L_r$. The

red dashed plot shows the value of the magnetizing inductance which is selected according to the dead-time interval value, in order to reduce the conduction losses caused by the circulating current. Input and output voltages, as well as the output power are kept to the same values considered in the results of Fig. 14.

Although a small resonant inductance requires tight manufacturing tolerances, it helps to ensure ZVS on both sides of the converter. A trade-off among synchronous ZVS, resonant inductance, and dead-time interval design is therefore present for the considered *CLLC* DCX topology. The parasitic parameters of printed circuit board (PCB) windings are predictable and controllable, and the leakage inductance of the transformer itself can easily reach several hundreds of nH. An external inductor normally shows a tolerance of some percent and high resonant inductance $L_r$ can lead to loss of ZVS at heavy load conditions. In this case, the usage of the leakage inductance of the planar transformer as resonant inductance gets beneficial.

## V. EXPERIMENTAL SETUP AND PRELIMINARY RESULTS

A test circuit setup has been manufactured to verify the proposed analysis, including only two full bridges with the three primary ports of the transformer connected in parallel. The circuit parameters of the implemented hardware prototype are the same as listed in Table II, except that the newest IGLT65R025D2 GaN-HEMTs in TOLT package are used instead of GS65516T. The planar transformer has been characterized using an impedance analyzer, so to extract the leakage inductance and the equivalent parasitic inductance of the cables between the transformer terminals and switching nodes of the converters, contributing to the resonant inductance value, which is 280 nH. The test setup is shown in Fig. 17.

A preliminary test has been performed operating the DCX at an input voltage of 250 V and a load current of 15 A. The measured primary- and secondary-side resonant inductor currents and the drain-source voltages of $Q_3$ and $S_3$ in this operating condition are plotted in Fig. 18. The effective dead-time interval in the experiment is measured to be 70 ns, instead of 60 ns, being the value set in the control platform (due to the rise and fall time of the power devices and small differences in the gate driving).

Primary- and secondary-side power devices achieve ZVS in this operating condition, as expected from the simulation analysis. Direct comparison with the analytical calculations
<figure><img src="image_23.png" /><figcaption>**Fig. 18.** Device voltage and resonant current waveforms at an input voltage of $U_{dc,pri} = 250$ V, and a load current of $I_{load} = 15$ A. (a) Resonant tank currents and magnetizing current. (b) Drain-source voltages of $Q_3$ and $S_3$.</figcaption></figure>

is not possible, due to the simplifying hypothesis of constant output capacitance of the power devices adopted in the analytical investigation, as already recalled. Further measurements are planned to get an insight on the actual ZVS region as a function of the resonant inductance and dead-time interval, allowing a comparison at least with the dynamical simulation analysis.

## VI. CONCLUSIONS AND FUTURE WORK

A bidirectional CLLC DCX converter adopted in OBC applications has been considered in this paper. The ZVS operating conditions for such a converter has been analyzed, and a detailed circuit and analytical model of the resonant currents evolution during the dead-time interval is proposed, aiming at its optimal prediction/selection based on the resonant tank parameters and load current.

A simplifying hypothesis has been introduced to allow the calculation of the closed form solution of the differential equations, i.e., the power devices output capacitance $C_{oss}$ is considered constant during the switching transition. This represents for sure a strong assumption, but aimed at demonstrating that a proper (and complex) solution to the problem can be provided, so to gain further and fast insights on the ZVS operation as a function of main design parameters of the converter.

Time-domain dynamical LTspice simulations results have been compared to the proposed analytical model calculations within the dead-time interval, demonstrating an excellent agreement under the considered simplifying hypothesis. Significant discrepancies are observed when the actual nonlinear behavior of the output capacitance is considered. Extension of the analytical model to the non-linear case is for sure not straightforward (and was not the main objective of this paper) and will be analyzed in a future work.

Finally, a test circuit setup has been manufactured to get an insight on the actual ZVS region as a function of the resonant inductance and dead-time interval, allowing a comparison with the dynamical simulation analysis.

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