# Good practices to sort 650 V GaN die inside a PCB

Alonso Gutierrez, Emmanuel Marcault, Antoine Izoulet, Marc Orsatelli, Mathieu Gavelle, Pierre-Yves Hamelin, Aymeric Lagadec, Laurent Guillot

► To cite this version:

Alonso Gutierrez, Emmanuel Marcault, Antoine Izoulet, Marc Orsatelli, Mathieu Gavelle, et al.. Good practices to sort 650 V GaN die inside a PCB. The 26th European Conference on Power Electronics and Applications, GDR SEEDS France & EPE Association, Mar 2025, Paris, France. 10.34746/epe2025-0059. hal-05077816

HAL Id: hal-05077816

https://utc.hal.science/hal-05077816v1

Submitted on 21 May 2025

HAL is a multi-disciplinary open access
archive for the deposit and dissemination of sci-
entific research documents, whether they are pub-
lished or not. The documents may come from
teaching and research institutions in France or
abroad, or from public or private research centers.

L'archive ouverte pluridisciplinaire HAL, est
destinée au dépôt et à la diffusion de documents
scientifiques de niveau recherche, publiés ou non,
émanant des établissements d'enseignement et de
recherche français ou étrangers, des laboratoires
publics ou privés.

<figure><img src="image_1.png" /></figure>

Distributed under a Creative Commons Attribution 4.0 International License
# Good practices to sort 650 V GaN die inside a PCB

Alonso Gutierrez¹, Emmanuel Marcault¹, Antoine Izoulet¹, Marc Orsatelli¹,
Mathieu Gavelle¹, Pierre-Yves Hamelin², Aymeric Lagadec², Laurent Guillot³

¹CEA, CEA in Occitanie Region, Labège, France

²ELVIA Electronics, Coutances, France

³STMicroelectronics, Labège, France

E-Mail: (alonso.gutierrez-galeano, emmanuel.marcault, antoine.izoulet
marc.orsatelli, mathieu.gavelle)@cea.fr,
(pierre-yves.hamelin, aymeric.lagadec)@elviaelectronics.com, laurent.guillot@st.com

## Acknowledgements

Work carried out in the framework of the G-Mobility project. This work is part of the IPCEI Microelectronics and Connectivity and was supported by the French Public Authorities within the frame of France 2030.

## Keywords

«GaN-HEMT», «Embedded PCB», «Bias-T»,
«S-parameters», «microvias», «Smith chart»,
«X-ray tomography», «Power die».

## Abstract

This work studies the embedding of 650V d-mode GaN within a PCB using double-side microvias. The study begins with a comparison of electrical parameters before and after packaging in a sample of devices. This comparison aims to evaluate the packaging impact. After, all packaged devices are characterized and statistically classified. This classification allows detecting some parts with atypical values. X-ray tomography on these atypical parts highlight backside die delamination or voids on them. However, this failure detection method could be time-consuming. Therefore, this study proposes a method based on S-parameters for early failure detection. S-parameters analysis and test results on the identified backside delaminated devices reveal their tendency to have higher intrinsic capacitance. Finally, lessons learned through this study have led to propose some guidelines to improve the embedded PCB process for better sort practices.

## Introduction

Wide-band gap (WBG) components, and specifically gallium nitride (GaN) High Electron Mobility Transistor (HEMT), are expected to be highly promising in the field of power electronics [1]. Indeed, these transistors have enviable performances with reduced conduction and switching losses, thus achieving a high switching frequency, up to a few MHz. Nevertheless, proven robustness and reliability are essential for their commercialization on a large scale, such as in the automotive field with traction control systems of electric vehicles or in the aeronautics field.

Within this context, the maximum ratings for current, voltage, and temperature must be respected during the transistor's operation. Due to the new switching range offered by GaN transistors, fast di/dt and dV/dt occur across stray elements, potentially penalizing the device's lifetime [2]. Therefore, device packaging becomes fundamental for GaN-HEMT performance and reliability [3]. For instant, studies have shown the impact of mechanical stress in the GaN-HEMT packaging process that can result in further reliability issues [4].

The study reported here describes the embedding of GaN transistor inside a printed circuit board (PCB). The embedded packaging process inside a PCB, also called ePCB, consists of several steps that potentially increase the risk of device pre-damage or failure [5]. Therefore, our proposed experimental approach aims to characterize some GaN-HEMTs before and after the embedded
packaging to assess the packaging impact on the device parameters. Furthermore, characterization results on several devices are correlated with a non-invasive method such as X-ray tomography that is a powerful technique for packaging failure detection [6]. Indeed, this correlation through statistical analysis of characterization results and X-ray tomography has led to identify a backside die delamination or voids in some devices.

However, the use of this correlation method could be time-consuming for early failure detection at production level. Therefore, this study proposes a radiofrequency approach based on S-parameters for failure detection. This method take advantage of S-parameters and high-frequency wave propagation to explore and to identify abnormal variation in either semiconductor properties [7] or device connections [8]. Given the main findings in this work, the S-parameters approach has shown its potential for early failure identification using a quick test with a single setup. For instance, S-parameters analysis and test results on devices with identified backside delamination have revealed their tendency to higher intrinsic capacitances.

In perspective, current non-invasive methods can detect packaging failures; for instance, die attach delamination or voids. However, they are unsuitable for high-volume production due to its time-consuming nature and specialized equipment requirements [9]. In contrast, the proposed method could be able to detect die delamination or voids by measuring S-parameter with an accessible test setup. It is fully compatible with existing Automated Test Equipment (ATE) in production lines, making it ideal for high-volume manufacturing due to its speed and scalability.

The structure of the paper is as follows: Section I provides an overview of embedded design considerations and the manufacturing details. Section II compares the device parameters before and after packaging. Section III provides details about atypical results for embedded devices and correlates them with X-ray tomography. Section IV describes the S-parameters approach for embedded PCB inspection and the main findings about failure identification. Final section proposes guidelines to improve the embedded PCB manufacturing and yield.

# Embedded PCB overview and prototype manufacturing details

This section describes the embedded PCB features of the developed prototype and the main manufacturing steps.

The embedded PCB packaging has the potential to take advantages of the remarkable switching performance of GaN-HEMT devices [10]. This packaging method aims to embed the GaN-HEMT die into a PCB for achieving low stray inductance and low thermal impedance. Indeed, direct copper connection of power dice and short connection length lead to a significant reduction of stray resistance and inductance improving the switching behavior and reducing losses. Several embedded approaches have been described in the literature [5][11]. Nevertheless, this work focuses on the double-side microvias method given their promising application perspectives in power electronics [12]. Work results aim to contribute in the knowledge about the impact of this packaging process on the device electrical characteristics.

Figure 1 describes the embedded PCB process using double-side microvias. For this process, a laser microvia interconnection is only allowed with top and bottom copper metallization on the die. Indeed, a minimum of 8µm of copper is mandatory to fit with laser drill process (Fig. 1-1). The manufacturing of the embedded PCB prototype begins with a first lamination to embed the die and stack the layers (Fig. 1-2, 1-3). Then, laser drill equipment is used to drill laser vias on top and bottom side of copper die areas (Fig. 1-4). After, the microvias are copper filled (Fig. 1-5). Finally, a second lamination process is done to stack the second level of laser microvias (Fig. 1-6). Figure 2 shows top, bottom, and lateral views of the designed embedded PCB prototype.

The build up of the PCB is critical to optimize the life time of the embedded PCB. A symmetrical stack up is the first important rule to minimize the twist and bow effects. Furthermore, the die is located on the middle of the stack to keep the symmetry. The manufactured prototype has two levels of stacked microvias used to interconnect the die layer pads to the external top and bottom PCB layers (Figure 2a-2b). Figure 2c shows a cross section view of the designed stack up.

Regarding the PCB dielectric material, FR4 with high glass transition temperature (Tg>180°C) is
used to have a good resin flow to facilitate the encapsulation of the die. Moreover, standard FR4 is easier to fit with manufacturing PCB lines. Next section will compare the GaN-HEMT characteristics before and after the described packaging process.

<figure><img src="image_2.png" /><figcaption>Fig. 1: Illustration of the PCB embedding process based on double-side microvias</figcaption></figure>

<figure><img src="image_3.png" /><figcaption>Fig. 2: Embedded PCB prototype</figcaption></figure>

## Embedded device tracking and characterization

The embedded packaging process with double-side microvias involves several stages as described in previous section. As a result, this manufacturing process could lead to increase the risk of device damage or unexpected failure [5]. Therefore, our proposed experimental approach aims to characterize the GaN-HEMTs before and after the embedded packaging to assess the packaging impact on the device parameters. The packaged GaN-HEMT devices are 650V d-mode Normally-ON with nominal 25mΩ R<sub>DSon</sub>.

This study is carried out on forty-five packaged devices distributed in two groups. The first group of five bare dice are randomly chosen to be tracked before and after packaging. The second group of forty packaged devices is used to statistically quantify the tendency values and to identify the atypical values with potential failures. The rest of this section describes the tracking of the first group (sampling of five devices). The next section will deal with the characterization of the

second group reporting the main findings about the atypical statistical values.

Figure 3 depicts the experimental setup based on the MPI TS2000-DP probe station and the Keysight B1505A power device analyzer. The setup employs the same B1505A configuration to keep comparable conditions before and after assembly. Moreover, the needles of the probe station are used in both cases given the similar pad layout distribution of the bare die and the packaged device.

<figure><img src="image_4.png" /><figcaption>Fig. 3: Characterization of bare die and tracking after embedded PCB packaging</figcaption></figure>

For the developed study, a first sample of five GaN-HEMT have been tracked before and after packaging. After packaging, four devices are functional. This reveals a suitable yield of 80%. Furthermore, the identified non-functional device showed a failure in the gate characteristics.

Characterization comparisons of functional devices before and after embedded PCB packaging are shown from Figure 4 to Figure 8. Figure 4 shows the characterization of the V<sub>th</sub> value around -12.5V before and after packaging. In Figure 5, the comparison of I<sub>dss</sub> from 0V to 650V shows a slight increase in two devices, but still under a compliance I<sub>dss</sub> lower than 1µA. Figure 6 depicts a particular improvement of the I<sub>gss</sub> values. Figure 7 illustrates that impact of the embedded packaging in the R<sub>DSon</sub>. The average R<sub>DSon</sub> before packaging is 27.38 mΩ and after packaging is 31.65 mΩ for measurements with I<sub>DS</sub>=1A. Therefore, the average increase of R<sub>DSon</sub> is around 4.27 mΩ. Figure 8 depicts the evolution of the intrinsic capacitances C<sub>iss</sub>, C<sub>oss</sub>, and C<sub>rss</sub> measured at 1MHz from 0V to 600V. Some differences arise in the intrinsic capacitances in voltage lower than around 100V; nevertheless, before and after packaging the capacitance convergence to similar values above 150 V. These comparison of results, from Figure 4 to Figure 8, highlight that functional devices do not show significant parameters evolution after assembly.
<figure><img src="image_5.png" /><figcaption>Fig. 4: Comparison of threshold voltage (Vth) before and after packaging</figcaption></figure>

<figure><img src="image_6.png" /><figcaption>Fig. 5: Comparison of $I_{DSS}$ before and after packaging</figcaption></figure>

<figure><img src="image_7.png" /><figcaption>Fig. 6: Comparison of $I_{GSS}$ before and after packaging</figcaption></figure>

<figure><img src="image_8.png" /><figcaption>Fig. 7: $R_{ON}$ measurement at $I_{DS}=1A$ before and after packaging</figcaption></figure>

<figure><img src="image_9.png" /><figcaption>Fig. 8: Comparison of intrinsic capacitance of bare die (red) and embedded packaged device (blue)</figcaption></figure>

## Atypical results for embedded devices

This section shows the characterization of forty GaN-HEMT packaged in embedded PCB devices and the findings of atypical characterization results.

Forty GaN-HEMT devices were packaged in the same conditions that devices of previous section. Furthermore, a sequence of characterization was carried out as in previous case measuring $V_{th}$, $I_{dss}$, $I_{gss}$, and $R_{DSon}$. In this case, the characterization of functional embedded devices has shown that most of devices have relatively similar values. However, a statistical analysis on measured devices shows some atypical results. The most significant variations were found in $R_{DSon}$ and $I_{dss}$.

From Figure 9, the box plot show that DUT13, DUT23, and DUT25 have atypical high $R_{DSon}$. Furthermore, Figure 10 highlights than DUT13, DUT22, DUT25, and DUT28 have $I_{dss}$ above the maximum value of the box plot. Intersection of results from Figure 9 and 10 leads to conclude that DUT13 and DUT25 have both atypical high $R_{DSon}$ and $I_{dss}$. In contrast, the DUT9 is selected as a reference device given their suitable values at bottom of the first quartile of the box plot for the $R_{DSon}$ and $I_{dss}$ measurements. Therefore, more detail study is carried out in these devices.

X-ray tomography is the non-destructive testing method used to check the assembly of DUT13, DUT25, and DUT9 in greater detail and depth. This method allows inspecting these devices without affecting their functionality. Fundamentally, X-ray absorption tomography is a non-destructive technique based on radiation-matter interaction, enabling the reconstruction of 3D cross-sectional images of a three-dimensional object, with a precision of less than ten microns.

As highlighted in yellow rectangles in Figure 11 and Figure 12, X-ray tomography analysis shows defects in the X-Y and Y-Z planes. These defects, located on the rear face of the bare die. This issue is clearly visible in Figure 11 with delamination or voids in the die backside at the opposed side of the gate and source die contacts. In Figure 12, given the bright appearance of the defective layer, we can confirm the delamination or voids in the copper metallization of the components. In contrast, reference DUT9 shows no evidence of delamination issues.
Potentially, this delamination concern arose whereas the dice cutting and their side effects were enhanced during the packaging process. After an inspection with a Keyence microscope, Figure 13 shows an identified bare die with edge delamination in remain dice of the same lot but not packaged yet. This early fault identification previous packaging was possible because of the current study findings. Next section will introduce an alternative radiofrequency methodology to compare the atypical and reference devices.

<figure><img src="image_10.png" /><figcaption>Fig. 9: R<sub>ON</sub> measurement on embedded PCB and box plot.</figcaption></figure>

<figure><img src="image_11.png" /><figcaption>Fig. 10: I<sub>dss</sub> at 650V characterization and box plot.</figcaption></figure>

<figure><img src="image_12.png" /><figcaption>Fig. 11: Backside die delamination or voids on DUT13 and DUT 25. Y-Z tomography plan.</figcaption></figure>

<figure><img src="image_13.png" /><figcaption>Fig. 12: Backside die delamination or voids on DUT13 and DUT 25. X-Y tomography plan. DUT9 shows no evidence of backside die delamination or voids.</figcaption></figure>

<figure><img src="image_14.png" /><figcaption>Fig. 13: GaN-HEMT die with backside delamination. Early fault detection through visual inspection with Keyence microscope.</figcaption></figure>

## S-parameters for embedded PCB inspection and failure identification

As describe in previous section, electrical characterization methods correlate with X-ray tomography allowed identifying potential packaged device failures. However, this approach could be time consuming for testing many packaged devices. As a complementary approach, this section describes a packaging inspection based on S-parameters. This approach can provide valuable information about the packaging and device healthy in a single test setup with less time consumption.

S-parameters or scattering parameters are defined by considering a set of high-frequency waves traveling on a network. The equipment that provides the high-frequency waves to measure the S-parameters is known as Vector Network Analyzer (VNA). As shown in Figure 14, when a voltage wave from a VNA port is incident on a DUT, a portion of the voltage wave is transmitted through the DUT. Additionally, the other portion
of the wave is reflected back toward the initial VNA port. By definition, S-parameters are the coefficients between these incident and reflected waves [13]. As described by equation (1), the S-parameters nomenclature depends on the ports for the incident and reflected waves.

<figure><img src="image_15.png" /><figcaption>Fig. 14: Vector Network Analyzer (VNA)</figcaption></figure>

$$S_{11} = \frac{b_1}{a_1}; S_{21} = \frac{b_2}{a_1}; S_{22} = \frac{b_2}{a_2}; S_{12} = \frac{b_1}{a_2} \quad (1)$$

The reflected waves are consequence of the interaction between the characteristic impedance $Z_0$ of the measurement system and the impedance of the DUT. Usually, the characteristic impedance of the measurement system is $Z_0=50\Omega$. Furthermore, the reflection coefficient at the input port $\Gamma_{in}$ or at the output port $\Gamma_{out}$ are defined as equivalents to $S_{11}$ and $S_{22}$ respectively (see equation (2)).

$$\Gamma_{in} = S_{11} \quad \text{and} \quad \Gamma_{out} = S_{22} \quad (2)$$

$S_{11}$ and $S_{22}$ are complex quantities; therefore, $\Gamma_{in}$ and $\Gamma_{out}$ are complex quantities and may be graphically represented on polar diagrams or Smith charts [13]. The S-parameters and their graphical representation in the Smith chart are usually employed for the design of radiofrequency systems. Nevertheless, the developed study proposes the use of this radiofrequency approach to identify potential device failures after the manufacturing of embedded PCB packaging.

The proposed packaging and GaN-HEMT healthy inspection measures the S-parameters of packaged devices using a test fixture and a DC polarization Bias-T. The test fixture allows interconnecting the VNA ports and the DUT. The developed test fixture consists of a test board and a socket for packaging inspection without soldering the DUT (see Figure 15).

<figure><img src="image_16.png" /><figcaption>Fig. 15: Test fixture with socket for embedded PCB device inspection</figcaption></figure>

This test board fixture is designed using the radiofrequency software Advanced Design System (Keysight ADS). The design simulates with S-parameters an open and a short circuit test boards to get information about the characteristic impedance $Z_{OTB}$ of the test board fixture (see Figure 16) [14]. The open and short circuit test board allow respectively calculating the characteristic capacitance $C_{OTB}$ and inductance $L_{OTB}$ of the test board fixture. By definition of $Z_0$ in equation (3), $Z_{OTB}$ is calculated from $C_{OTB}$ and $L_{OTB}$. Results in Figure 17 confirms that the designed test board fixture has a suitable characteristic impedance around $Z_{OTB} \approx 52\Omega$ in a frequency range from 1MHz to 1GHz.

<figure><img src="image_17.png" /><figcaption>Fig. 16: ADS circuit simulation of test fixture board in short and open circuit</figcaption></figure>

$$Z_0 = \sqrt{\frac{L_0}{C_0}} \quad (3)$$

<figure><img src="image_18.png" /><figcaption>Fig. 17: Simulation results of characteristic impedance of test fixture board</figcaption></figure>

After the development of the test fixture, the second element of the experimental setup is the Bias-T (see Figure 18). The Bias-T allows providing a DC polarization to the GaN-HEMT device isolating both DC and radiofrequency (RF) ports [15].
<figure><img src="image_19.png" /><figcaption>Fig. 18: Bias-T schematic circuit</figcaption></figure>

The design principle of the Bias-T takes into account the definition of characteristic impedance to calculate its capacitance C<sub>B</sub> and inductance L<sub>B</sub> as shown in equation (4) [15]. The commercial selected values are C<sub>B</sub>=3.3nF and L<sub>B</sub>=8.5µH to get a characteristic impedance Z<sub>0B</sub> around 50Ω with a suitable bandwidth between 700kHz and 5GHz.

$$Z_{0B} = \sqrt{\frac{L_B}{C_B}} = \sqrt{\frac{8.5\mu H}{3.3nF}} \approx 50.8\Omega \quad (4)$$

Figure 19 depicts the experimental setup with two Bias-T and the socket based test fixture. As shown in Figure 19, the V<sub>GS</sub> terminal is associated to the VNA-Port1 and the V<sub>DS</sub> terminal is associated to the VNA-Port2. Therefore, the parameter S<sub>11</sub> mainly provide information about the Gate-Source characteristics and the parameter S<sub>22</sub> mainly provide information about the Drain-Source characteristics.

<figure><img src="image_20.png" /><figcaption>Fig. 19: Test setup and polarization Bias-T</figcaption></figure>

The experimental setup for the packaging and device healthy inspection uses a VNA Rohde & Schwarz ZVH8 option ZVH-K42. Table I lists the VNA configuration parameters. The remainder of this section describes the S-parameters results of DUTs considering the bias voltage.

<table><caption>**Table I:** VNA configuration parameters</caption><thead><tr><td>Parameter</td><td>Value</td></tr></thead><tbody><tr><td>Start frequency</td><td>1MHz</td></tr><tr><td>Stop frequency</td><td>1GHz</td></tr><tr><td>Number of points</td><td>1201</td></tr><tr><td>Tracking generator power</td><td>0 dBm</td></tr><tr><td>Resolution bandwidth</td><td>300Hz</td></tr><tr><td>Characteristic impedance</td><td>50Ω</td></tr></tbody></table>

Previous works have shown the S-parameters dependency of the bias voltage in GaN-HEMT devices [16]. Therefore, the V<sub>DS</sub> value is swept from 0V to 400V keeping V<sub>GS</sub> at -20V to ensure the off-state of the d-mode GaN. As a result, V<sub>DS</sub>=10V is chosen because S-parameters showed more significant variation for V<sub>DS</sub> at low voltage. Furthermore, the frequency range is set from 1MHz to 1GHz given the suitable frequency characteristics of the designed test fixture and Bias-T. As shown in Figure 20 and Figure 21, S<sub>11</sub> and S<sub>22</sub> parameters of devices with identified delamination or voids (DUT13 and DUT25) have significant dissimilarities in comparison with the healthy reference device (DUT9). Indeed, these results agree with previous correlation between device characterization and X-ray tomography. Therefore, these S-parameters results show their potential to identify early packaging or device failures in the production line with a single setup and a quick test.

<figure><img src="image_21.png" /><figcaption>Fig. 20: S<sub>11</sub>-Parameter of delaminated and reference devices. V<sub>GS</sub> =-20V and V<sub>DS</sub>=10V.</figcaption></figure>

<figure><img src="image_22.png" /><figcaption>Fig. 21: S<sub>22</sub>-Parameter of delaminated and reference devices. V<sub>GS</sub> =-20V and V<sub>DS</sub>=10V.</figcaption></figure>
## S-parameter translation in the Smith chart

Figure 20 and Figure 21 around 1MHz disclose in the Smith chart an S-parameter displacement of DUT13 and DUT25 in comparison with DUT9. This section deals with the theoretical description of the S-parameter translation in the Smith for analysis of these results.

The Smith chart is a useful graphical tool for calculating reflection coefficients and unknown impedances. The Smith chart is based on a polar plot of the complex reflection coefficient Γ overlaid with the corresponding load impedance $Z_L$. To better interpretation of Smith chart results, it is necessary to remind that the reflection coefficient Γ of a characteristic impedance $Z_0$ terminated with a load impedance $Z_L$ is given by equation (5) [17].

$$ \Gamma = \frac{Z_L - Z_0}{Z_L + Z_0} = \frac{(Z_L/Z_0) - 1}{(Z_L/Z_0) + 1} = \frac{z-1}{z+1} \quad (5) $$

Where $z=Z_L/Z_0$ is a normalized impedance as shown in equation (6).

$$ z = \frac{Z_L}{Z_0} = \frac{R + jX}{Z_0} = \frac{R}{Z_0} + j \frac{X}{Z_0} = r + jx \quad (6) $$

Given the complex reflection coefficient Γ defined in equation (7),

$$ \Gamma = \Gamma_{re} + j \Gamma_{im} \quad (7) $$

the equation (5) can be rewritten as,

$$ \Gamma_{re} + j \Gamma_{im} = \frac{r + jx - 1}{r + jx + 1} \quad (8) $$

Solving the equation (8) in the complex domain and join the real and imaginary parts, the equation (9) and the equation (10) are obtained to correlate the reflection coefficient and the normalized impedance in the Smith chart [17]. Geometrically, the equations (9) and (10) correspond to the standard equation of a circle.

$$ (\Gamma_{re} - \frac{r}{1+r})^2 + \Gamma_{im}^2 = (\frac{1}{1+r})^2 \quad (9) $$

$$ (\Gamma_{re} - 1)^2 + \left(\Gamma_{re} - \frac{1}{x}\right)^2 = \left(\frac{1}{x}\right)^2 \quad (10) $$

The equation (9) represents a circle centered at $c=[r/(1+r), 0]$ with a radius $r=1/(1+r)$. This is

called constant resistance circle because it is independent of the normalized reactance $x$. Figure 22 depicts the geometric representation of the equation (9) in the Smith chart.

<figure><img src="image_23.png" /><figcaption>Fig. 22: Representation of constant resistance circles in the Smith chart</figcaption></figure>

Similarly, the equation (10) represents a circle centered at $c=[1,1/x]$ with a radius $r_x=1/x$. This is called constant reactance circle because it is independent of the normalized resistance $r$. Figure 23 depicts the geometric representation of the equation (10) in the Smith chart. Indeed, the Smith chart arises from the association of both the constant resistance circles and the constant reactance arcs inside the unitary reflection coefficient circle $|\Gamma| = 1$.

<figure><img src="image_24.png" /><figcaption>Fig. 23: Representation of constant reactance circles in the Smith chart</figcaption></figure>

Comparing these constant resistance and constant reactance circles with results of Figure 20 and 21, the comparison leads to conclude that the main influence on the S-parameter translation is mainly associated to the device reactance. This S-parameter translation takes place in the lower semicircle of capacitive reactance; thus, the radius $r_x$ of the constant reactance circles are given by equation (11),
$$r_x = \frac{1}{x} = \frac{1}{\left(\frac{X}{Z_0}\right)} = \frac{Z_0}{\left(\frac{1}{\omega C}\right)} = Z_0 \omega C = 2\pi Z_0 f C \quad (11)$$

where $Z_0$ is a constant. According to equation (11), radius $r_x$ in a given frequency $f$ will be proportional to the device capacitance $C$ (equation (12)).

$$r_x \propto C \quad (12)$$

Therefore, the S-parameter displacement in the lower semicircle toward the left side implies a capacitance increase of the DUT. Most specifically, this could lead to conclude that the intrinsic capacitances increase in the identified delaminated devices in comparison with the healthy device.

## Intrinsic capacitance of delaminated and reference devices at 1MHz

In order to validate the previous deduction, as a second source of measurement, the Keysight B1505A measures the intrinsic capacitance of the selected devices in a range of voltage from 0V to 120V. Figure 24 to Figure 26 confirm the increase of intrinsic capacitances at 1MHz and $V_{DS}=10V$ in the failure devices. Additionally, capacitance measurements highlight an evolution of the capacitance-voltage dependence potentially because of the backside die delamination or voids. Physical analysis of these results are out of scope of current work. However, some studies have modeled the impact of the substrate voltage on the GaN-HEMT intrinsic capacitances [18].

In contrast, results from Figure 24 to Figure 26 provides information about the constraints of the proposed S-parameters method given that some voltage regions show not significant evolution (e.g. $V_{DS}$ around 30V). Then, the bias voltage should be carefully selected for device inspection.

<figure><img src="image_25.png" /><figcaption>Fig. 24: $C_{iss}$ comparison for delaminated and reference devices at 1MHz</figcaption></figure>

<figure><img src="image_26.png" /><figcaption>Fig. 25: $C_{oss}$ comparison for delaminated and reference devices at 1MHz</figcaption></figure>

<figure><img src="image_27.png" /><figcaption>Fig. 26: $C_{rss}$ comparison for delaminated and reference devices at 1MHz</figcaption></figure>

## Proposed guideline to improve embedded PCB manufacturing

Embedded PCB packaging is a promising option to take advantage of GaN-HEMT. However, this package manufacturing could require some special care to provide suitable performance and high yield in the industrial line. Therefore, lessons learned through this study allow providing some guidelines to improve the manufacturing process and yield leading to good sort practices. Figure 27 illustrates the proposed guideline.

<figure><img src="image_28.png" /><figcaption>Fig. 27: Proposed guideline to improve embedded PCB manufacturing process and yield</figcaption></figure>
## Conclusion

This work reported a study on embedding GaN-HEMT within PCB using double-side microvias. The study compared device electrical parameters before and after packaging on five sampled parts. Comparison showed that this packaging process has low impact on the power device parameters. In a second group of forty packaged devices, correlation of statistical atypical $R_{Dson}$ and $I_{dss}$ with X-ray tomography allowed identifying a failure due to backside die delamination or voids (two identified units). However, this failure detection method could be time-consuming. Therefore, a method based on S-parameters was proposed. The S-parameters measurements confirmed the failure findings with a single and a quick test. Furthermore, S-parameters analysis and test results on the identified backside delaminated devices revealed an increase in the intrinsic capacitances. Conversely, a method limitation was identified because the bias voltage should be carefully selected. Lessons learned through this work have led to proposed guidelines to improve the embedded manufacturing process and yield. Future work aims to extend the analysis of the failures and to others embedded packaging.

## References

[1]. P. Moens, A. Banerjee, P. Coppens, F. Declercq, M. Tack, "AlGaN/GaN power device technology for high current (100+A) and high voltage (1.2 kV)," ISPSD, Prague, Czech Republic, June 2016.

[2]. B. Sun, K.L. Jorgensen, Z. Zhang, M. Andersen, "Research of Power Loop Layout and Parasitic Inductance in GaN Transistor Implementation", IEEE PEDCC 2019.

[3]. S. Lu, "Packaging of Enhancement-Mode Gallium Nitride High-Electron-Mobility Transistors for High Power Density Applications," PhD thesis, Virginia Polytechnic University, Virginia, USA, 2022.

[4]. Z. Dahrouch, G. Malta, M. d'Ambrosio, AA. Messina, M. Musolino, A. Sitta, M. Calabretta, S. Patanè, "Assessing the Stress Induced by Novel Packaging in GaN HEMT Devices via Raman Spectroscopy," Applied Sciences, 2024.

[5]. T. Huesgen, "Printed Circuit Board Embedded Power Semiconductors: A Technology Review," Power Electronic Devices and Components, Volume 3, 2022.

[6]. H. Villarraga-Gómez, K. Crosby, M. Terada, et al. "Assessing Electronics with Advanced 3D X-ray Imaging Techniques, Nanoscale

Tomography, and Deep Learning," Journal of Failure Analysis and Prevention, 2024.

[7]. M. A. Belaïd, A. M. Nahhas and M. Masmoudi, "Failure analysis of S-parameter in N-MOSFET devices after thermal life tests," THERMINIC, Netherlands, 2017.

[8]. Y. Pascal, F. Daschner, M. Liserre, M. Höft, "Condition monitoring of power module using S-parameters, TDR, and TDT," Microelectronics Reliability, Volume 138, 2022.

[9]. MIL-STD-883, "Test method 2030.1 Ultrasonic Inspection of Die Attach," Feb. 2010.

[10]. Z. Qi, Y. Pei, L. Wang, Q. Yang and K. Wang, "A Highly Integrated PCB Embedded GaN Full-Bridge Module With Ultralow Parasitic Inductance," in IEEE Transactions on Power Electronics, vol. 37, no. 4, April 2022.

[11]. L. Böttcher, A. Ostmann, T. Löhler and M. Seckel, "Concepts for realizing High-Voltage Power Modules by Embedding of SiC Semiconductors," 24th EMPC, Cambridge, United Kingdom, 2023.

[12]. R. Caillaud et al., "Thermal Considerations of a Power Converter With Components Embedded in Printed Circuit Boards," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 10, no. 2, Feb. 2020.

[13]. A. J. Baden Fuller, "An Introduction to Microwave Theory and Techniques", Second Edition, Pergammon International Library, 1979.

[14]. T. Dufort, "Conception et Réalisation d'un Banc de Test pour Composants de Puissance GaN/Si et Leur Packaging," 2nd year project, ENSEA, CEA Occitanie, Labège, France, 2023.

[15]. L. Pace, "Caractérisation et Modélisation de Composants GaN pour la Conception des Convertisseurs Statiques Haute Fréquence," PhD thesis, Université de Lille, France, 2019.

[16]. A. Gutierrez, N. Said, E. Marcault and M. Gavelle, "Verification of GaN-HEMT Spice Models Using an S-parameters Approach," 24th European Conference on Power Electronics and Applications, Hanover, Germany, 2022.

[17]. C. Li, D.M.M.-P. Schreurs, "Chapter 1 – Fundamental of Microwave Engineering, Principles and Applications of RF/Microwave in Healthcare and Biosensing," Editor(s): C. Li, M.-R. Tofighi, D. Schreurs, T.-Sheng, Academic Press, 2017.

[18]. S. A. Albahrani et al., "Modeling of the Impact of the Substrate Voltage on the Capacitances of GaN-on-Si HEMTs," in IEEE Transactions on Electron Devices, Dec. 2019.