# Process challenges of the STRASS technique to increase the electron mobility in advanced FD-SOI nMOSFETs

F. Milesi, Ph. Rodriguez, L. Zouknakl, L. Brunet, N.-P. Tran, V. H. Le, E.

Nolot, J. Hartmann, V. Loup, P. Hauchecorne, et al.

► To cite this version:

F. Milesi, Ph. Rodriguez, L. Zouknakl, L. Brunet, N.-P. Tran, et al., Process challenges of the STRASS technique to increase the electron mobility in advanced FD-SOI nMOSFETs. MRS Advances, 2025, 10.1557/s43580-025-01148-4. [hal-04935690](https://hal.science/hal-04935690v1)

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https://hal.science/hal-04935690v1

Submitted on 7 Feb 2025

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# Process challenges of the STRASS technique to increase the electron mobility in advanced FD-SOI nMOSFETs

F. Milesi<fnref n="1" /> Ⓒ · Ph. Rodriguez<fnref n="1" /> · L. D. Mohgouk Zouknak<fnref n="1" /> · L. Brunet<fnref n="1" /> · N.-P. Tran<fnref n="1" /> · V. H. Le<fnref n="1" /> · E. Nolot<fnref n="1" /> ·

J. M. Hartmann<fnref n="1" /> · V. Loup<fnref n="1" /> · P. Hauchecorne<fnref n="1" /> · M. Jourdan<fnref n="1" /> · B. Perrin<fnref n="1" /> · T. Marion<fnref n="1" /> · L. Saidi<fnref n="1" /> · J. Marchand<fnref n="1" /> · M. Coig<fnref n="1" /> ·

L. Lachal<fnref n="1" /> · F. Mazen<fnref n="1" />

Received: 20 September 2024 / Accepted: 16 January 2025

© The Author(s) 2025

## Abstract

To improve the I<sub>on</sub>/I<sub>off</sub> performance of transistors, it is crucial to significantly increase the charge carrier mobility in the channels of field-effect transistors. Tensile stress/strain is known to improve the electron mobility in the channels of nMOS-FETs. This paper focuses on the STRASS (Strained Silicon by Top Recrystallization of Amorphized SiGe on SOI) process for introducing tensile stress into the silicon channel of the next-generation n-type Fully Depleted Silicon-On-Insulator (FD-SOI) devices. This technique is challenging, especially for very thin silicon film channels (e.g., less than 10 nm), where the controlled creation of a buried amorphous layer by ion implantation is difficult. By carefully optimizing the individual process steps of the STRASS technique, we have achieved the transfer of up to 1.6 GPa of tensile stress into the silicon of blanket SOI wafers.

## Introduction

One approach to further improve the I<sub>on</sub>/I<sub>off</sub> performance of advanced FD-SOI transistors is to increase the charge carrier mobility in their channel. Applying mechanical stress is an interesting way to achieve this: compressive stress increases hole mobility in pMOSFETs, while tensile stress enhances electron mobility in nMOSFETs [1, 2]. Various techniques are currently being investigated to achieve the desired stress, depending on the type of MOSFET and its specific performance requirements. These techniques include sSOI [3], SiGe condensation [4], BOX-creep [5], and STRASS [6–8], to name a few.

In this paper, we focus on the STRASS (Strained Silicon by Top Recrystallization of Amorphized SiGe on SOI) technique for introducing tensile stress into the silicon channel of n-type FD-SOI devices. The STRASS technique is based on the process flow shown in Fig. 1.

Starting from a SOI substrate (step 1), SiGe epitaxy (step 2) is performed, resulting in compressive stress within the SiGe layer due to the lattice mismatch between SiGe and

silicon. A buried amorphization layer is created by ion implantation (step 3), resulting in a partial amorphization of the SiGe layer, while a crystalline seed remains at the surface. During this step, the crystalline SiGe layer relaxes its initial compressive stress. An annealing process (step 4) results in a top-down recrystallization of the underlying Si layer. The relaxed SiGe seed layer imposes its lattice constant on the other layers of the stack, particularly to the silicon channel, which becomes tensile-strained as a result. Finally, the SiGe layer is removed (step 5).

The most challenging aspect of the STRASS technique is step 3, where a buried amorphous layer must be created in very thin SiGe and Si layers, while maintaining a crystalline seed at the surface. The process window to form the buried amorphous layer by ion implantation is so narrow that it is difficult to predict the optimal conditions by simulation alone. In this study, we will first determine the ion implantation parameters to obtain a buried amorphous layer in bulk silicon, and then transfer the appropriate ion implantation parameters to a thin Si/SiGe stack for the implementation of the STRASS process.

<footnote>F. Milesi
frederic.milesi@cea.fr</footnote>

<footnote n="1">¹ Univ. Grenoble Alpes, CEA-Leti, 17 avenue des Martyrs,
38054 Grenoble, France</footnote>
<figure><img src="image_2.png" /><figcaption>**Fig. 1** Process flow of the STRASS technique, adapted from [6]</figcaption></figure>

## Experimental

Experiments were performed on blanket wafers. For the STRASS process, we used blanket SOI wafers with thin BOX (20 nm) and 8-nm or 12-nm silicon top layers. The SiGe layers with a germanium content of 30% were grown with thickness between 8 and 24 nm by epitaxy in a 300-mm RP-CVD cluster tool. Ion implantation was performed using silicon implantation in the Applied Materials' VIISta HCP tool, with a physical mask (VMask) enabling four different implantation conditions to be tested on the same wafer. Recrystallization annealing was performed at 850 °C for 5 min in a nitrogen atmosphere, using a VT412 furnace from ASM. Finally, SiGe layers were selectively removed by low-temperature HCl gas etching.

To characterize the depth and thickness of the buried amorphous layers, spectroscopic ellipsometry (SE) measurements were performed using an Onto Innovation tool in conjunction with cross-sectional transmission electron microscopy (TEM). After ion implantation, a "soft" anneal (500 °C for 2 min) was necessary to reorganize the amorphous-crystalline interfaces and ensure accurate SE measurements. Without it, the mean squared error (MSE) of the SE response would be high. Raman spectroscopy (Horiba T64000), with a laser wavelength of 363 nm, 2400 grooves/mm grating, and 1 µm spot size, was used to measure the strain transferred in the silicon channel by the STRASS technique. The stress/strain was estimated from the Raman wavenumber shift (Δω, cm⁻¹) of the silicon peak, assuming a biaxial strain. A shift Δω < 0 indicates tensile strain, while Δω > 0 indicates compressive strain. In addition, the full width at half maximum (FWHM) of the Raman peak provided insight into the crystalline quality. Smaller FWHM values indicate better crystalline quality, with an ideal FWHM for perfectly crystalline silicon being approximately 3.5 cm⁻¹. Several measurements were carried out at different positions to quantify measurement uncertainties.

## Fabrication of a buried amorphous layer by ion implantation

As a preliminary work, we performed tests to determine the optimal parameters (energy, dose, and beam current) by silicon implantation to form a buried amorphous layer and the surface crystalline seed layer in bulk silicon.

Figure 2 shows the impact of different ion implantation parameters on the thickness and depth of the buried amorphous silicon layer (a-Si) and the crystalline surface seed (c-Si). First, we varied the beam current from 0.5 to 8 mA. SE measurements (Fig. 2a) showed that the beam current had no influence on the depth of the amorphous layer (a-Si). However, as expected, it impacted the thickness of the amorphous and crystalline layers. An increase of the beam current (we assume that the wafer temperature is almost constant, close to RT, for both beam currents) indeed led to a damage increase and thus to an amorphous layer thickness increase [9]. As seen in Fig. 2a Low and a High TEM images, which are in line with SE measurements, a small fraction of the damaged layer is fully amorphized at low currents, resulting in a thicker interfacial transition between amorphous and crystalline layers. For both samples, the crystalline seed layer at the surface remained continuous and uniform. To mitigate the effect of the ion implantation beam current on the depth and thickness of the amorphous layer, we fixed the current at 5 mA for the remainder of the study. Next, we modulated the ion implantation dose (in the 10¹⁴ at/cm² range). Figure 2b SE measurement graph shows that the implantation dose also had no impact on the a-Si depth. However, the a-Si thickness increased with the dose. The formation of the buried amorphous layer occured only within a narrow dose window that was sufficient to create the layer, but not so high as to eliminate the crystalline silicon layer on the surface. Finally, we varied the ion implantation energy (<50 keV). The SE measurements graph in Fig. 2c shows that the implantation energy had a limited impact on the a-Si thickness, but a significant impact on the a-Si depth.
<figure><img src="image_3.png" /><figcaption>**Fig. 2** Impact of silicon ion implantation parameters on the formation of buried amorphized layers in bulk silicon from SE measurements (a—impact of beam current/b—impact of dose/c—impact of energy)</figcaption></figure>

and corresponding TEM images (a Low: TEM image at low current/a High: TEM image at high current)

which increased with the energy. Minimal implantation energy is thus required to create the buried amorphous layer.

Based on these results, we confirm that the process window for creating buried amorphous layers by silicon implantation is very narrow.

The STRASS technique was then used to fabricate Fully Depleted Silicon-On-Insulator (FD-SOI) substrates with tensile strain for advanced nodes (silicon thickness of 12 nm and SiGe of 12 nm in our case). First, we note that

the process window for ion implantation is even narrower for Si/SiGe stacks than for single Si layers, with noticeable differences. As shown in Fig. 3, cross-sectional TEM images show an irregular and discontinuous c-SiGe layer after ion implantation compared to a silicon layer (Fig. 2a High). Enlarged images of the c-SiGe layer show crystal pockets. This situation would be due to SiGe properties [8, 10].

<figure><img src="image_4.png" /><figcaption>**Fig. 3** Cross-sectional TEM images at different scales showing the c-SiGe layer after the ion implantation step for the STRASS technique</figcaption></figure>
<figure><img src="image_5.png" /><figcaption>**Fig. 4** Raman spectroscopy measurements of strain transfer (histogram) vs. crystal quality (dotted lines with symbols) as a function of Si and SiGe layer thickness or thickness ratio. The Si layer thickness in **a** plot was 8 nm. **b** Effect of Si/SiGe ratio thickness</figcaption></figure>

## Strain transfer and crystalline quality in the silicon layer after the use of STRASS

Having optimized the ion implantation conditions to achieve a buried amorphous layer in a thin Si/SiGe stack, we then evaluated the strain transfer to the silicon layer using the STRASS technique. According to Stoney's equation [11], with a-Si/SiGe bilayer with 30% of germanium, the theoretical model suggested a stress transfer of more than 2 GPa.

Figure 4a shows that the stress and crystalline quality of the silicon layer are directly influenced by the SiGe layer thickness. Significantly increasing the SiGe thickness (from 8 to 24 nm) results in an almost doubled stress transfer (from 1.0 up to 1.8 GPa), with a slightly lower crystalline quality (the Raman peak's FWHM increases from 4.75 up to 5.25 cm⁻¹). We otherwise observe a stress loss of about 200 MPa after the selective removal of the SiGe layer. This stress reduction was attributed to the mechanical equilibrium that occurs at the Si/SiGe interface after epitaxy. Figure 4b shows the impact of the Si/SiGe thickness ratio on stress transfer and crystalline quality, prior SiGe removal. The ratio between Si and SiGe thicknesses has a strong influence on the stress transfer, even for small modifications. It is possible to multiply the stress transfer by 3 (0.55 GPa for a-Si/SiGe ratio of 1.5, to be compared with 1.8 GPa for a-Si/SiGe thickness ratio of 0.33). Meanwhile, the crystalline quality is slightly degraded as this thickness ratio decreases and thus, the tensile stress increases (the FWHM increases from 4.75 to 5.25 cm⁻¹). For the same Si/SiGe thickness ratio, the overall thickness of the Si/SiGe bilayer also has a definite impact on stress transfer with a crystal quality which is less affected (for instance, 1 GPa for Si = 12 nm and SiGe = 18 nm versus 1.5 GPa for Si = 8 nm and SiGe = 12 nm). These results confirm theoretical simulations based on Stoney's equation that the maximum stress to be expected in the silicon layer would be reached at the lowest possible Si/SiGe thickness ratio. However, 100% of the theoretical stress transfer (2 GPa) was not reached.

We found that by modulating the Si/SiGe stack thickness, it was possible to induce up to 1.6 GPa of tensile stress in the silicon layers on top of the buried oxide in blanket SOI wafers. However, we consistently observed a strong correlation between stress and defect formation in the silicon layer. Compared to previous STRASS studies, these results are equivalent [12] or even better [8] in terms of stress transfer.

## Conclusions and perspectives

In this work, we investigated the impact of ion implantation parameters and Si/SiGe layer or stack thickness on stress transfer using the STRASS technique. We showed that it was possible to transfer tensile stress of up to 1.6 GPa into the silicon layer of blanket SOI substrates. The key step was ion implantation. The ion implantation conditions had to be adapted depending on the individual thickness of the Si and SiGe layers on top. The stress transfer depended on the Si/SiGe thickness ratio; to maximize the stress, the Si/SiGe thickness ratio should be significantly less than 1 with the thinnest possible Si/SiGe stack. However, we also observed that the stress transfer created defects in the resulting tensile-strained silicon layer.

All results were obtained on blanket wafers, but future work will focus on integrating the STRASS technique on patterned wafers to better understand its impact on CMOS device performance within an advanced FD-SOI process flow (<< 28 nm technological node). In addition, it will be important to evaluate how Shallow Trench Isolation (STI) interacts with the STRASS process and find the right trade-off between induced strain and crystalline defects to maximize the electrical performance.

**Funding** Open access funding provided by Commissariat à l'Énergie Atomique et aux Énergies Alternatives. This work was supported by a grant from the French government, managed by the "Agence

<figure><img src="image_6.png" /></figure>
Nationale de la Recherche" under the France 2030 program: ANR-22-NEXG-0001 (NextGen project). Work carried out on the Platform for Nanocharacterisation (PFNC), was supported by the "Recherche Technologique de Base" and "France 2030 - ANR-22-PEEL-0014" programs of the French National Research Agency (ANR).

**Data availability** Datasets generated during the current study are avail-
able from the corresponding author on reasonable request.

Declarations

**Conflict of interest** On behalf of all authors, the corresponding author states that there is no conflict of interest.

**Informed consent** Informed consent was obtained from all individual participants included in the study.

**Open Access** This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons licence, and indicate if changes were made. The images or other third party material in this article are included in the article's Creative Commons licence, unless indicated otherwise in a credit line to the material. If material is not included in the article's Creative Commons licence and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this licence, visit http://creativecommons.org/licenses/by/4.0/.

References

1. O. Weber et al., Proc. VLSI Tech. Symp., 2014, p. 16

2. B. De Salvo et al., Proc. IEEE International Electron Devices Meeting (IEDM), 2014, p. 172

3. Q. Liu et al., Proc. IEEE International Electron Devices Meeting (IEDM), 2014, p. 219

4. S. Nakaharai et al., J. Appl. Phys. **105**, 024515 (2009)

5. R. Berthelon et al., Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2017, pp. 91–94

6. A. Halimaoui, J. M. Hartmann, Pat. EP 2 782 118 A1 (2014)

7. A. Bonnevialle et al., EuroSOI 2015, p. 177

8. S. Maitrejean et al., ECS Trans. **66**, 47 (2015)

9. L. Pelaz et al., J. Appl. Phys. **96**, 5947–5976 (2004)

10. S. Maitrejean et al., ECS J. Solid State Sci. Technol. **4**, P376 (2015)

11. S. Sharan Injeti et al., Thin Solid Films **598**, 252–259 (2016)

12. A. Bonnevialle et al., 2016 IEEE Symposium on VLSI Technology

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