# Development of Integrated Functions in GaN

Yovan Andyka Marcelino, Rene Escoffier, Bruno Allard

► To cite this version:

Yovan Andyka Marcelino, Rene Escoffier, Bruno Allard. Development of Integrated Functions in GaN. The 26th European Conference on Power Electronics and Applications, GDR SEEDS France & EPE Association, Mar 2025, Paris, France. 10.34746/epe2025-0138 . hal-05101402

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Distributed under a Creative Commons Attribution 4.0 International License
# Development of Integrated Functions in GaN

Yovan Andyka Marcelino¹², Rene Escoffier¹, Bruno Allard²

¹Univ. Grenoble Alpes, CEA, Leti, F-38000 Grenoble, France

²AMPERE, INSA-Lyon, F-69621, France

Tel.: +33 4 38 78 01 84

E-Mail: yovan-andyka.marcelino@cea.fr

yovan.marcelino@insa-lyon.fr

URL: https://www.leti-cea.com, http://www.ampere-lab.fr/

## Keywords

«Driver concepts», «Gallium Nitride (GaN)», «Gate driver», «HEMT», «Integrated Circuit (IC)».

## Abstract

This paper takes advantages of Gallium Nitride (GaN) as an ideal material in the development of electronic devices for high power and frequency applications. The paper details the circuit design and implementation of logic and analogue gates using a GaN-on-SI, non isolated proprietary technology to create a gate driver circuit for driving and instrumenting wide-gap power transistors.

## I. Introduction

In recent years, Gallium Nitride (GaN) has proved an excellent material for the design of power semiconductor devices. With its superior properties, such as large energy bandgap, high electrical breakdown field, high electron saturation velocity and high electron mobility, GaN-based transistors offer excellent performance compared with silicon, and the interest in this technology is growing rapidly [1], [2] as shown in figure 1.

<figure><img src="image_2.png" /><figcaption>Fig. 1: Comparison of properties of Si, SiC and GaN [3]</figcaption></figure>

In comparison to other materials, the advantages of GaN can be translated in the following form. GaN

devices may operate at higher junction temperature [4] and under higher voltage than Si counterparts which is crucial for high-power applications [5]. Devices can also operate efficiently at high frequency and switch with larger speed than Si devices, which is important for RF applications and fast switching devices [4].

The paper presents an early design of logic and analogue functions based on a GaN-on-Si proprietary non-isolated technology to create a gate driver circuit for driving and instrumenting wide-gap power components.

Section II introduces the GaN transistor technology at hand. Section III focuses on the circuit design and simulation of the blocks needed for a core gate driver for a GaN power transistor. The following part explains how the overall gate driver circuit operates and compares the driver with one offer available on the market. The layout of the various blocks are illustrated.

## II. Characterization of the GaN HEMT transistor

A technology for power GaN transistors is under development at CEA LETI. The technology is not based on an isolated substrate as with GaN-on-SOI. This is a restricting constraint that constitutes a challenge for the development of a gate driver co-integrated with the GaN power transistor. From a design kit perspective, an accurate SPICE model has been validated for numerous GaN transistors fabricated with the proprietary technology.

In this section, a generic GaN HEMT transistor is simulated using LTSPICE plotting the drain current (Id) as a function of the voltage between drain and source (Vds) with variations in the gate voltage (Vgs). The supply voltage varied from -3 V to 4 V on the drain, while the gate voltage
varied between 0 V and 6 V in 1 V steps. The simulation result is shown in the figure below.

<figure><img src="image_3.png" /><figcaption>Fig. 2: GaN HEMT transistor characteristics in 4 quadrants</figcaption></figure>

In linear mode, the drain current varies linearly with the bias voltage, and the transistor behaves like a resistor controlled by the gate voltage. In saturated mode, under the effect of the increasing electric field on the drain side, the current reaches a limit. Note that in the third quadrant, the Id characteristic is similar to a diode (see green curve).

The switching performances of device is determined by the time required to establish voltage changes across capacitances. Due to the structure of a MOSFET, parasitic capacitances primarily impact the transient.

Therefore, in order to understand the device's behavior, we simulate in LTspice the input capacitances (Ciss = Cgd+Cgs), the output capacitance (Coss = Cds+Cgs) and the reverse transfer capacitance (Crss=Cgd).

<figure><img src="image_4.png" /><figcaption>Fig. 3: Extraction of parasitic capacitances of the GaN HEMT</figcaption></figure>

We can see in figure 3. the different values of parasitic capacitances with respect to the voltage Drain-Source. The Ciss capacitance determines the charging and discharging speed of the gate, a high Ciss requires more current for switching, what also impacts Tr (time rise) and Tf (time fall).

Then, the Coss determines the drain's charging and discharging speed, hence the energy stored in Coss is released as heat when switching.

Lastly, the Crss is the capacitances between gate and drain (Cgd) itself, a large Crss will delay the rise and fall in drain current after the gate is turned on or off. Also it can affect the switching time.

<figure><img src="image_5.png" /><figcaption>Fig. 4: Test circuit for the evaluation of the switching times [6].</figcaption></figure>

Fig. 4 shows a circuit for evaluating the switching time. Here is an explanation of the results with RG = 5 Ω and RL=100 Ω.
<table><caption>**Table I: Extracted Dynamic Characteristics**</caption><tr><td>Td(on): Turn-on delay time</td><td>Time from Vgs rises over 10% until 90% of Vds</td><td>0,5 ns</td></tr><tr><td>Tr: Rise time</td><td>Time for Vds to fall from 90% to 10%</td><td>0,6ns</td></tr><tr><td>Ton: Turn-on time</td><td>Td(on) + Tr</td><td>1,1ns</td></tr><tr><td>Td(off): Turn-off delay time</td><td>Time from Vgs drops below 90% until 10% of Vds</td><td>3ns</td></tr><tr><td>Tf: Fall time</td><td>Time for Vds to rise from 10% to 90%</td><td>5,4ns</td></tr><tr><td>Toff: Turn-off time</td><td>Td(off) + Tf</td><td>8,4ns</td></tr></table>

The time-values vary depending on the condition of Id, Vds, Vgs, RG and RL. The higher the value of RG, the longer it takes for the transistor to turn on. In addition, the higher the value of RL, the longer it takes for the transistor to turn off.

To conclude, in order to achieve a fast switching performance, the value of parasitic capacitances, Rg, and RL must be as lower as possible. So it can lead the operation at higher frequency, higher energy efficiency, and even reduce the heat generation. However, if RL is too small, it will affect the functionality of the circuit.

### III. Design of logic gates

To create a driver that would control the power transistors, we will first explain the various needed logic gates such as NOT, AND, NOR, and SR latch with 2-input NOR. The basic circuits will use resistors and transistors, that allows us to parameterize the transistor's gate width and the number of transistors in parallel (number of fingers), for enabling adjustment in the resistor current level. Ltspice is used to simulate the behavior of the circuit.

#### A. NOT gate

The NOT gate (inverter) is a fundamental component in digital electronics. Fig. 5 shows the NOT circuit with a resistor and a transistor. The input signal A is applied to the transistor gate, and the output signal Out is measured between the resistive load and the transistor source.

<figure><img src="image_6.png" /><figcaption>Fig. 5: Schematic of the resistor-to-transistor logic inverter.</figcaption></figure>

When input voltage V(A) is low, the value of Vgs is lower than Vth (1 V), which turns the transistor U1 in off condition (Fig. 6). The output will take the value VDD (logic high level). With input V(A) at high level, Vgs is larger than Vth (1 V), thus activating transistor U1. The output becomes VSS (logic low level). Based on the current flow, we can estimate the power consumption of this inverter at approximately 360 mW when the input signal is high.

<figure><img src="image_7.png" /><figcaption>Fig. 6: Simulation of the inverter circuit</figcaption></figure>

#### B. AND gate

The AND circuit consists of a resistive load and three GaN transistors in series in the first stage forming a NAND circuit and a NOT circuit in the second stage resulting in a logical AND, which is explained in the following equation $A.B.C = A.B.C$. The input voltages are applied to the gates of the first stage transistors with a third input for future development such as feedback coupled to a current sensor of a low-side power transistor. While the output is located between the drain of the second stage transistor and VDD (Fig. 7).

Note: Resistors R2 and R3 are used to recall the reference voltage VSS at the source of transistors U1 and U2, to facilitate their control.
<figure><img src="image_8.png" /><figcaption>Fig. 7: Schematic of the AND circuit and resulting logic state table.</figcaption></figure>

Fig. 8 shows that if one of the three input signals is at 0 V, the output goes to the low level (~0 V). In situation where all the three input signals are at +6 V, the output is at the logic high level (VDD), which means it corresponds to the truth table.

<figure><img src="image_9.png" /><figcaption>Fig. 8: Simulation result for 3-input AND gate</figcaption></figure>

### C. NOR gate

The 3-input NOR circuit requires the use of a resistive load and three transistors in parallel as shown in Fig. 9.

<figure><img src="image_10.png" /></figure>

<table><caption>Fig. 9: Schematic of the NOR circuit and resulting logic state table.</caption><thead><tr><th>A</th><th>B</th><th>C</th><th>OUT</th></tr></thead><tbody><tr><td>0</td><td>0</td><td>0</td><td>1</td></tr><tr><td>0</td><td>0</td><td>1</td><td>0</td></tr><tr><td>0</td><td>1</td><td>0</td><td>0</td></tr><tr><td>1</td><td>0</td><td>0</td><td>0</td></tr><tr><td>1</td><td>1</td><td>0</td><td>0</td></tr><tr><td>1</td><td>1</td><td>1</td><td>0</td></tr><tr><td>1</td><td>1</td><td>1</td><td>1</td></tr></tbody></table>

When all three input voltages are low, a potential difference below the threshold voltage $V_{th} = 1$ V occurs between the gates and the sources (Vgs), causing the transistors to be in off condition. It allows the NOR output to be at high level.

In the case that one of the three input voltages $V(A), V(B), V(C)$ is high, the potential between gate and source (Vgs) becomes larger than the threshold voltage $V_{th} = 1$ V, enabling the transistor to be activated. This condition allows the NOR output to switch to the low level.

<figure><img src="image_11.png" /><figcaption>Fig. 10: Simulation results for 3-input NOR gate</figcaption></figure>
## D. SR NOR latch

Normally, SR latch is normally used to store a bit information based on inputs and the previous state of outputs. It can be realized with two connected NOR gates and only two complemented inputs (R and S) without any clock input, since each NOR output is looped back to one input of the other, as shown in Fig. 11.

<figure><img src="image_12.png" /><figcaption>Fig. 11: Schematic of the SR-latch circuit and resulting logic state table.</figcaption></figure>

The output values Out and $\overline{Out}$ at time t (denoted Qt and $\overline{Qt}$) are determined depending on the values S, R, as well as the previous output state (denoted Qt-1), enabling to obtain several combinations, as described in Fig. 11.

When R=S=1, the output is $Out = \overline{Out} = 0$ due to the NOR function. This state should not be used, as it is indeterminate.

For S=1, the output of NOR X1($\overline{Out}$) is 0, which is equal to the input of NOR X2. If R is 0, we obtain the combination of functions: $(0 + 0) = Out = 1$ and the output of the SR latch will be Out=1 and $(\overline{Out}) = 0$.

With R set to 1, the output of NOR X2 (Out) is 0, which is equal to the input of NOR X1. If S is 0, we obtain the combination of functions: $(0 + 0) =$

($\overline{Out}$) = 1. The output of the RS flip-flop will then be Out=0 and $(\overline{Out}) = 1$.

In the case where S=R=0, if the previous state is 0 then the output is also 0, if the previous state is 1, the output is also 1. This memory function is shown in Fig. 12.

<figure><img src="image_13.png" /><figcaption>Fig. 12: Simulation results for the SR-latch</figcaption></figure>

In conclusion, we have succeeded in demonstrating that all the logic circuits operate correctly. Each stage of the simulation is essential to validate the expected theoretical studies and understand their application in the driver.

# IV. Design of the driver

Drivers are designed to operate MOSFET or IGBT gates in various applications, particularly in power electronics. In this context, the goal is to design a dual driver circuit to independently drive an upper side power transistor (called “High-side”) and a lower-side power transistor (called “Low-side”), so that it can drive a complete power inverter leg.

## A. Core-driver logic inputs

Both sides of the driver (high-side and low-side) have the same input logic scheme. They are made up of NOT, SR latch, 3-input NOR logic circuits. In the simulation, we use the input signals HIN for the high-side, LIN for the low-side, and SD being the “reset” input as illustrated in Fig. 13.
<figure><img src="image_14.png" /><figcaption>Fig. 13: Input signals used to simulate the driver operation (high-side and low-side)</figcaption></figure>

The SD signal can also be used as a protection circuit. For example, in an overvoltage or overcurrent protection case, it is possible to send an SD signal to stop the driver. Indeed, when SD is high, the system will block the HO and LO output (=0 V), as shown in the truth table (Fig. 14) and the waveforms in Fig. 15.

<table><caption>Fig. 14: Truth table of driver inputs</caption><thead><tr><th>IN</th><th>S_RS</th><th>R_RS</th><th>OUT_RS</th><th>OUT_NOR</th></tr></thead><tbody><tr><td>HIN / LIN</td><td>SD</td><td>IN</td><td>Q</td><td>H_out / L_out</td></tr><tr><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td></tr><tr><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td></tr><tr><td>1</td><td>0</td><td>0</td><td>0<br>1</td><td>1</td></tr><tr><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td></tr></tbody></table>

<figure><img src="image_15.png" /><figcaption>Fig. 15: Simulation result of driver inputs</figcaption></figure>

## B. High-Side output

In the high side, the source of the transistor we wish to control is at a potential Vs varying between 400 V and 0 V, which necessitates the use of a level shifter. This will enable the gate to be driven between Vs+0 V and Vs+6 V, whatever the value of Vs.

The level shifter in Fig. 16 is made up of a transistor and two resistors. The transistor gate is fixed at high level (VDD = 6 V), and the drain is connected to high voltage (VB = 400 V) via a resistor. The source, the level shifter input, is connected to the NOR output (H_out).

<figure><img src="image_16.png" /><figcaption>Fig. 16: level shifter schematic</figcaption></figure>

When the source is at +6 V, there is no potential difference between the gate and the source (Vgs=0 V), the transistor is off and the level shifter output takes the voltage VB = 400 V.

If the source changes to 0 V, Vgs = +6 V, the transistor is turned on and the level shifter output takes the value H_out = 0 V, as shown in Fig. 17.

<figure><img src="image_17.png" /><figcaption>Fig. 17: Chronogram of level shifter</figcaption></figure>

We then connect the output of the level shifter to an inverter (Fig. 18). With this inverter, transistors U2 and U3 behave like complementary transistors (when U2 is off, U3 is on, and vice versa). This scheme generates the HO output signal at the high level (400 V) when the Hin input is at 6V, and 0V when Hin=0V.

<figure><img src="image_18.png" /><figcaption>Fig. 18: High side driver schematic</figcaption></figure>

## C. Low-Side output

The low side requires two inverters, a 3-input AND logic gate and two transistors (Fig. 19). The output
signal is given by the midpoint between the two
transistors U4 and U5 connected in series. With
this circuit, we obtain an output logic level similar
to the input signal.

<figure><img src="image_19.png" /><figcaption>Fig. 19: Low side driver schematic</figcaption></figure>

On the previous figure, we notice the presence of
an input labelled Vml, which will provide
feedback to set LO to the low-level to regulate the
current in the power transistor (low-side) as a
future development.

Fig. 20 shows the entire driver, including the
various logic gates. The high and low-sides are
used to drive the high-side transistor and the low-
side transistor of the power inverter (HO and LO
output).

<figure><img src="image_20.png" /><figcaption>Fig. 20: Schematic of the driver</figcaption></figure>

The LTspice model (symbol) of the driver will be
made up of several pins: input pins, output pins,
power supply pins, and pins for testing the driver's
operation (pin t_XXX).

D. Simulation of the driver connected to
an inverter leg

The driver outputs are connected to the gate and
sources of the high and low-side power transistors.
A voltage of 400 V is applied to the drain of the
high-side power transistor, and a voltage of 7 V
supplies the logic inputs.

D1, C2 connected to the driver form a bootstrap
circuit. When LIN is at logic high, C2 is charged
up to VB (equal to VDD minus the voltage drop
across diode D1). When LIN is at 0 and HIN is at
1, the potential difference across C2 is added to the
voltage VB, which rises above the source level to

drive U1 in high-side configuration. The complete
circuit for simulation is shown in Fig. 21.

<figure><img src="image_21.png" /><figcaption>Fig. 21: Simulation circuit including power transistors [7]</figcaption></figure>

Simulation of the driver operation is shown in Fig. 22. The waveform in red represents HIN (input high side), LIN is in green (input low side) and pink signals denote SD (shutdown) input signal. The output signals show the low-side driver output (noted LO) and the voltage between HO and VS (noted V(HO,VS),), which has a difference of about +6 V.

<figure><img src="image_22.png" /><figcaption>Fig. 22: Gate signal waveform for driver</figcaption></figure>

Simulation results confirm that the driver can
produce the desired control signals. When HIN or
LIN are equal to 1, HO or LO are also equal. The
SD stop signal works correctly, thanks to the SR
latch. SD can therefore interrupt the control signal
and generate a low output state.

The power dissipation due to driver current
consumption simulated at different resistors of
logic gate is shown in figure 23
<figure><img src="image_23.png" /><figcaption>Fig. 23: Power consumption driver for different logic gate resistor values</figcaption></figure>

As expected, when the value of resistor increase, it will limit the current flow, resulting in reduced current consumption by the driver, and consequently, a lower power consumption.

The Fig. 24 shows simulated the switching power losses [8] and the various delay with supply voltage of 7V, switching frequency of 1MHz, and 20A current of load.

<figure><img src="image_24.png" /><figcaption>Fig. 24: Switching power losses and various delay in the rising edge (top) and the falling edge (bottom).</figcaption></figure>

The results show that increasing the resistor leads to longer switching delay, which also result in an increase of power losses.

After evaluating the impact of different resistor values on power consumption, switching power losses, and time delay, a 100 Ω resistor was selected. This resistor minimizes power consumption effectively, while keeping both the delay and switching power losses within acceptable limits.

## E. Comparison with the IR2110 commercial silicon driver

In this section, we compare the simulation results obtained with the driver under design to the SPICE model of the IR2110 driver [9] available on the market. The IR2110 (silicon) driver is manufactured by Infineon to drive MOSFETs and IGBTs for applications such as high frequency switching power supplies, DC and AC motor drives, and battery chargers. We will use the same input voltages and signals for our driver as for the commercial one (Fig. 25).

<figure><img src="image_25.png" /><figcaption>Fig. 25: Comparison of the output signals of the IR2110 driver and our driver.</figcaption></figure>

We can see that both drivers generate the same output signals. However, the outputs of the IR2110 driver are a few microseconds behind those of our driver. Due to the long delay in the IR2110 driver, it can reduce the precision of switching.

<table><caption>Table II: Comparison of Dynamic Characteristics</caption><thead><tr><td>Characteristics (simulation)</td><td>This driver</td><td>Driver IR2110</td></tr></thead><tbody><tr><td>Ton (ns)</td><td>LO = 6,2 ; HO =14</td><td>LO=110 ; HO=108</td></tr><tr><td>Toff (ns)</td><td>LO =8,4 ; HO= 10</td><td>LO=92 ; HO = 95</td></tr><tr><td>Tfall (ns)</td><td>LO=4,3 ; HO =35</td><td>LO= 9,4 ; HO = 8</td></tr><tr><td>Trise (ns)</td><td>LO= 4,8 ; HO = 93</td><td>LO=13 ; HO=12</td></tr><tr><td>Slew rate (V/ns)</td><td>3,4 & -9,1</td><td>26,6 & -40</td></tr></tbody></table>

This result confirms that the proposed GaN driver switches adequately compared to the IR2110 (Silicon) driver. On the high-side output (HO), the GaN driver exhibits larger rise and fall times. This is an issue that requires further investigation.
## V. Layout and PCB of the driver

In this section, the process of creating the layout of the GaN driver will be shown. the connections between transistors or logic gates are made with the layer named METAL1 in the layout. It will be necessary to match with DRC (Design Rule Check) design rules, and then to measure the resistances of the metal tracks providing the interconnections between the logic gates (using the LVS (Layout vs. Schematic) code). At the end we need to manually check the connections of each layout component, as there is no direct link between LTspice and Klayout.

<figure><img src="image_26.png" /><figcaption>Fig. 26: Layout of the complete driver (6.26mm X 2.38mm).</figcaption></figure>

Once the layout is complete (Fig. 26), it's time to prepare the test measurements to be made once the chip will be available. For this, a test board (PCB in Fig. 25) must be created using KiCad software, to accommodate the chip and connect the various pads. In the PCB, the wires required to connect the driver chip to the PCB are positioned. The green wires represent the actual wires used to build the daughterboard, and the yellow wire represents the METAL1 connection at layout level between the small VSS pads and the large VSS pads. So, there's no need to create a small VSS pad on PCB.

<figure><img src="image_27.png" /><figcaption>Fig. 26: PCB with connections for driver chip and power transistors.</figcaption></figure>

<figure><img src="image_28.png" /><figcaption>Fig. 27: 3D CAD of the PCB with location of the cut-out chip.</figcaption></figure>

## VI. Conclusion

In this paper, the concepts of various GaN-based logic gates needed to design a core gate driver have been explained and their functions have been validated through simulation. This step was crucial to ensure the driver's reliability and efficiency.

The operation of the overall driver circuit has been described and a comparison with a Si-based driver available on the market shows that our design is competitive in terms of switching speed and accuracy in responding to the driver's input signal. The results of this comparison are expected considering the advantages of GaN material over Si.

Following this project, the electrical measurement of this driver will be carried out after the chip delivery. This will enable us to validate the GaN driver's performances and adjust a number of issues required to optimize the driver efficiency.

## References

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[2] K. J. Chen et al., "GaN-on-Si Power Technology: Devices and Applications," in IEEE Transactions on Electron Devices, vol. 64, no. 3,
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[3]. Qi, Zhiyuan & Pei, Yunqing & Wang, Laili & Wang, Kangping & Zhu, Mengyu & Zhao, Cheng & Yang, Qingshou & Gan, Yongmei. (2020). An Accurate Datasheet-Based Full-Characteristics Analytical Model of GaN HEMTs for Deadtime Optimization. IEEE Transactions on Power Electronics. PP. 1-1. 10.1109/TPEL.2020.3044083.

[4]. He Li, Chengcheng Yao, Lixing Fu, Xuan Zhang and Jin Wang, "Evaluations and applications of GaN HEMTs for power electronics," 2016 IEEE 8th International Power Electronics and Motion Control Conference (IPEMC-ECCE Asia), Hefei, 2016, pp. 563-569, doi: 10.1109/IPEMC.2016.7512348.

[5]. H. Wu, X. Fu and S. Hu, "A 650V Enhancement Mode GaN HEMT Device with Field Plate for Power Electronic Applications," 2021 International Conference on Electrical, Communication, and Computer Engineering (ICECCE), Kuala Lumpur, Malaysia, 2021, pp. 1-5, doi: 10.1109/ICECCE52056.2021.9514197.

[6]. Power MOSFET Electrical Characteristics, Application Note Thosiba

[7]. Application Note AN-978, HV Floating MOS Gate Driver ICs

[8]. L. Balogh, "Fundamentals of MOSFET and IGBT gate driver circuits: Applications report," Appl. Report. SLUA618A, 2017.

[9]. IR2110 driver datasheet