# Indirect Avalanche Event Detection of Single Photon Avalanche Diode Implemented in CMOS FDSOI Technology

Tulio Chaves de Albuquerque, Dylan Issartel, Raphaël Clerc, Patrick Pittet, Rémy Cellier, Dominique Golanski, Sébastien Jouan, Andreia Cathelin, Francis Calmon

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Tulio Chaves de Albuquerque, Dylan Issartel, Raphaël Clerc, Patrick Pittet, Rémy Cellier, et al. Indirect Avalanche Event Detection of Single Photon Avalanche Diode Implemented in CMOS FDSOI Technology. Solid-State Electronics, 2020, pp.107636. 10.1016/j.sse.2019.107636. hal-02294857

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# Indirect avalanche event detection of Single Photon Avalanche Diode implemented in CMOS FDSOI technology

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## ARTICLE INFO

The review of this paper was arranged by Prof. S. Cristoloveanu

Keywords:

CMOS FDSOI
SPAD - Single Photon Avalanche Diode
Body-biasing
Indirect avalanche detection

## ABSTRACT

In this letter, a novel indirect avalanche event detection is proposed and demonstrated for Single Photon Avalanche Diodes (SPADs) implemented in CMOS 28 nm Fully Depleted Silicon-On-Insulator (FDSOI) technology. This approach is based on the capacitive coupling between the P-well, i.e. SPAD anode, and the transistor channel, separated by the ultra-thin buried oxide. The associated body-biasing effect is used to dynamically modulate the output of a simple voltage divider synchronously with the SPAD activity. A test-chip has been designed, fabricated and characterized to validate the proposed approach. This novel architecture opens the way for innovative SPAD processing circuitry implemented in 3D native CMOS FDSOI.

## 1. Introduction

Single Photon Avalanche Diode (SPAD) is a remarkable sensor for low intensity light detection as its simple structure allows for an easy integration in CMOS technologies of single pixel or pixel matrix, featuring sub-nanosecond response time [1]. SPADs enter a wide range of applications from IoT (e.g. proximity sensor, facial recognition, 3D imaging) to specific medical instrumentation such as fluorescence lifetime imaging [1,2]. SPAD integration in advanced CMOS technology node (e.g. 40 nm) has been industrialized [3], allowing to combine SPAD array and associated electronics for quenching, addressing, processing (and so on) on the same die, but at the expense of limited fill-factor (~40% at die level without microlenses). Consequently, current research and development focus on optimizing the Photon Detection Efficiency (PDE) for Near Infrared (NIR), as well as the fill factor. A popular approach consists in using 3D wafer level integration. In this case, the detector is made of two layers (with the best-optimized process for each of them): one hosting the SPAD array and the other one, the associated electronics [4]. Such 3D detector requires a Back-Side Illumination (BSI) with top die thinning and eventually surface treatment (such as anti-reflective coating) and microlenses to increase the photon collection. In this later case, both PDE and fill-factor (larger than 70%) are enhanced. An alternative concept was proposed in [5,6], in which SPADs are implemented in CMOS Fully Depleted Silicon-On-Insulator (FDSOI) technology. It features a native 3D integration for higher fill-factor achievement. In this letter, an original indirect detection of the avalanche events is proposed and experimentally validated for such innovative approach. This first experimental demonstration of SPAD activity indirect detection is possible thanks to body-biasing effect, which is a specific feature in ultra-thin body and box FDSOI CMOS. This indirect detection could be very useful for original integrated processing electronics in SPAD-based cameras (simpler circuitry, allowing excess bias voltage larger than transistor supply voltage, as no physical connection to the SPAD is required).

## 2. SPAD implemented in CMOS FDSOI technology

A disruptive and innovating approach has been proposed in [5,6], taking advantage of the native 3D integration of SPAD in an advanced CMOS 28 nm FDSOI technology (Fig. 1). The diode is implemented below the ultra-thin buried oxide (BOX, 25 nm) (using doped-areas normally intended for transistor body-biasing) while the CMOS electronics stands at the top thin silicon film, 7 nm (Fig. 1a). The schematic cross section presented in Fig. 1b represents the diode formed by P-well/deep N-well junction with the associated electronics above, separated by the buried oxide. The uniformity of electric field in the multiplication region is verified by TCAD simulations (Fig. 1c). Then, SPAD-FDSOI, after die thinning with BSI, features an intrinsically 3D pixel architecture (allowing an optimized fill-factor) without complex and expensive wafer-to-wafer assembly techniques requirements.

## 3. Avalanche indirect detection

### 3.1. Principle

A typical circuitry of the SPAD and its associated electronics is presented in Fig. 2a with a passive quenching (e.g. resistor $R_q$) and a buffer (shaper) connected to the anode. The SPAD is reversed biased at $V_{bd} + V_{ex}$ with $V_{bd}$ its breakdown voltage and $V_{ex}$ the excess voltage above $V_{bd}$. The anode voltage then varies between 0 V (standby state) to a maximum value around $V_{ex}$ (when an avalanche occurs). As the CMOS buffer cannot withstand an input voltage larger than $V_{dd}$ (e.g. 1.8 V), the excess voltage $V_{ex}$ range is also limited to $V_{dd}$ (limiting the PDE). With CMOS FDSOI technology, the concept of body-biasing allows to modulate the transistor properties, changing its threshold voltage $V_{th}$ to obtain high performance or low leakage device [7,8]. Thanks to this capacitive coupling between the P-well (i.e. SPAD anode, see Fig. 1b) and the transistor channel separated by the ultra-thin buried box, an indirect detection or sensing of the SPAD-FDSOI avalanche events is possible. The transistor threshold voltage $V_{th}$ will change according to the SPAD anode voltage fluctuations (P-well layer). With this feature, it is no longer necessary to physically connect the avalanche detection
<figure><img src="image_3.png" /><figcaption>Fig. 1. Illustration of the integration of SPAD into CMOS FDSOI technology. a) The diode is implemented below the ultra-thin buried oxide, under the thin silicon film hosting the transistors. b) Schematic cross section of the SPAD formed by the P-well – deep N-well junction with backside illumination. c) Electric field map in the multiplication region.</figcaption></figure>

circuitry to the SPAD anode. Furthermore, the excess voltage $V_{ex}$ range is no more limited to $V_{dd}$ without cascade transistor. Thanks to the capacitive coupling through the ultra-thin buried box, the CMOS circuitry can be placed anywhere onto the active area of the SPAD FDSOI, contrary to previous proposal where CMOS circuitry can only be integrated in the guard ring area of SPAD integrated in a triple-well process [9].

## 3.2. Implementation

In order to demonstrate the indirect detection of the avalanche events, a simple sensing circuit was implemented on top of the SPAD with the standard CMOS 28 nm FDSOI process, without any modification or design rule violation. It consists of a voltage divider realized with two MOS transistors, as shown in Fig. 2b. Since both transistors are placed over the same P-well (i.e. the SPAD anode) [6], a regular $V_{th}$ NMOS (due to regular well) and a low $V_{th}$ PMOS (due to the flipped well) were used. Furthermore, to enhance the body-biasing effect, the transistors with the thick front gate oxide (referred as GO2, 28 Å), featuring a larger body-bias factor ($\Delta V_{th}/\Delta V_{bb}$), were chosen. The basic behavior of the sensing circuit is shown in Fig. 2b, demonstrating that the output node of the voltage divider $V_{out}$ varies dynamically with the SPAD state. Each avalanche event gives a positive transient voltage pulse on the anode, i.e., a P-well voltage increase. Then, the $V_{th,n}$ of NMOS will decrease (forward body-biasing) while the absolute value $|V_{th,p}|$ of PMOS will also increase (reverse body-biasing). A transient negative voltage spike is then expected at the output node ($V_{out}$) of the

voltage divider (the spike amplitude is limited to $V_{dd}$/2).

## 3.3. Measurements

A test-chip including the sensing circuitry (voltage divider) was designed, fabricated and tested. It is placed above the active area of the SPAD, both being electrically isolated from each other by the BOX layer (Fig. 2c). The simulated and measured static characteristics of the divider (output voltage versus the P-well biasing voltage $V_{bb}$) are compared in Fig. 3. The experimental curve $V_{out} = f(V_{bb})$ is measured with an external source, allowing to control the P-well layer voltage thanks to a dedicated contact in a specific SPAD cell layout ($V_{bb}$). The simulated curve is obtained with calibrated MOS transistor models available in the physical design kit environment (SPECTRE simulator). The sensing circuit sensitivity evaluated by $\Delta V_{out}/\Delta V_{p-well} = \Delta V_{out}/\Delta V_{bb}$ is around -140 mV/V for both simulated and experimental results. The use of the voltage divider for demonstration of the indirect detection concept, although effective, presents a natural (direct) sensitivity to the variation of the supply voltage. With respect to process variations (SS FF SF FS) and temperature (-40 °C to 125 °C), the simulations give a relatively constant sensitivity factor of 142 ± 8 mV/V and an output voltage of 790 ± 65 mV, at zero back-biasing voltage. Under these conditions, the voltage divider circuit will be robust only for high excess voltage, to compensate for the offset of the operating point. It may be noted that a more complex detection circuit will make possible to obtain better robustness to PVT variations (for example differential circuitry).

<figure><img src="image_4.png" /><figcaption>Fig. 2. Basic principle of SPAD and associated electronics. a) classical implementation of passive quenching and buffer. b) indirect sensing circuitry of SPAD-FDSOI with a voltage divider (the dashed red line represents the body-biasing, i.e. the indirect coupling between the SPAD anode and transistors). c) layout view with the divider on top of the SPAD and also the quenching resistor.</figcaption></figure>
<figure><img src="image_5.png" /><figcaption>Fig. 3. Static behavior of the sensing circuit (voltage divider) with the output voltage as a function of the body-biasing voltage, i.e., P-well voltage (at V<sub>dd</sub> = 1.7 V).</figcaption></figure>

<figure><img src="image_6.png" /><figcaption>Fig. 4. SPAD avalanche event measurements with anode voltage and output of the indirect sensing circuit. The tested circuit is presented in Fig. 2(c) (at 25 °C with integrated passive quenching R<sub>q</sub> ≈ 200 kΩ, V<sub>bd</sub> = 9.6 V, V<sub>ex</sub> = 0.2 V, V<sub>dd</sub> = 1.7 V, P-substrate is grounded). Here the avalanches correspond to dark events.</figcaption></figure>

The test-chip was also characterized in operation, as shown in Fig. 4, by measuring simultaneously the anode voltage and the output of the indirect sensing circuit for several avalanches (they correspond here to dark events). The proposed indirect sensing allows avalanche event detection at excess bias voltages as low as V<sub>ex</sub> ≈ 0.2 V. The average relative magnitude of the spikes ΔV<sub>out</sub>/ΔV<sub>anode</sub> is around 140 mV/V, which is consistent with the static characteristic shown in Fig. 3.

Demonstration with higher excess bias voltage was unfortunately not possible because current SPAD presents a low breakdown voltage associated with band-to-band and field-enhanced trap assisted tunneling effects, limiting the operating range to low excess voltage [6]. The efficiency of the voltage divider circuit would be better at higher excess voltage (few volts). In this case, undesired parasitics of tens of mV will have no impact with respect to avalanche pulses, when using proper sizing for the voltage divider.

The long RC time constant of the event is due to the integrated passive quenching with R<sub>q</sub> ≈ 200 kΩ associated to total capacitance including the SPAD capacitance and the load capacitance: around 3 pF min (IO pad, printed circuit board, oscilloscope active probe). In our test chip, the integrated quenching resistor is realized with P<sup>+</sup> polysilicon layer available in the physical design kit environment. The path through the deep N-well may also contribute to the total quenching resistance and therefore leads to a higher effective quenching resistance (and, thus, the RC time constant).

This voltage divider circuit has a notable static consumption. In our

case, the transistors have large sizes (W = 10 µm with L<sub>min</sub> = 150 nm) to enable the output signal to be measured directly with an oscilloscope probe. The static consumption is then about 0.7 mA (simulated and measured) under V<sub>dd</sub> = 1.7 V. In a realistic configuration, with a voltage divider circuit which controls an integrated buffer – inverter, the transistors may have a width of 1 µm or less. Thus, the consumption will be much lower: of the order of 70 µA (simulated). A much lower static consumption could be obtained with a more suitable indirect detection circuit.

Here, the supply voltage of 1.7 V was chosen arbitrarily (no link with the recommended voltage for the extended gate type transistor with thick oxide). If we associate the voltage divider circuit with a buffer – inverter, the size of the transistors and/or the supply voltage can be chosen so that the spikes can switch the logic gate.

## 4. Conclusion

In this letter, a novel indirect sensing technique for SPADs implemented in CMOS 28 nm FDSOI technology was proposed and validated experimentally. It is based on the body-biasing effect and allows basic sensing circuit, such as a two MOS transistors voltage divider, to detect SPAD avalanche events. Such indirect sensing supports the use of larger excess voltage, as compared to direct approaches and paves the way for simpler and innovative SPAD processing electronics.
Acknowledgments

The authors would like to thank the Auvergne Rhone Alpes region (ARC6 research program 2016 no 16 – 005689 – 01) for the PhD Grant of Tulio Chaves de Albuquerque, the French National Research Agency (ANR-18-CE24-0010) for the PhD Grant of Dylan Issartel, CMP (Grenoble) for IC prototyping service, and also IngéLySE federation, for funding.

References

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Prof. Francis CALMON (Eng. 1992, Ph.D. 1995, HDR 2006) is Professor at INSA Lyon (Université de Lyon, France), attached to the Institut des Nanotechnologies de Lyon (INL UMR CNRS 5270), where he is co-head of the “Electronics Devices” group. In the field of innovative concepts in 3D integrated devices and systems, he led several projects e.g. SEDIMOS (Single Electron Device Integration on CMOS Technology) project funded by ANR (France) and NSERC – CRSNG (Canada) and participated to French and European research programs (e.g. ANR 3IDEAS, EU CATRENE 3DIM3, EU FP7 INFIERI). Since 2014, Francis Calmon is developing CMOS SPAD detectors and their associated electronics with different approaches CMOS bulk, CMOS FDSOI, 3D stacked detectors for charged particle

tracking etc. and has published several original papers in that domain.

Tulio Chaves de Albuquerqueª, Dylan Issartelª, Raphaël Clercᵇ, Patrick Pittetª, Rémy Cellierª, Dominique Golanskiᶜ, Sébastien Jouanᶜ, Andreia Cathelinᶜ, Francis Calmonª,⁺

ª INL – Institut des Nanotechnologies de Lyon, UMR CNRS 5270, Université de Lyon, France

ᵇ LHC – Laboratoire Hubert Curien, UMR CNRS 5516, Université Jean Monnet & Institut d'Optique Graduate School, Saint Etienne, France

ᶜ STMicroelectronics, Crolles, France

E-mail address: francis.calmon@insa-lyon.fr (F. Calmon).

<footnote>* Corresponding author at: Université de Lyon – INSA Lyon – Institut des Nanotechnologies de Lyon – INL UMR CNRS 5270, 7 Avenue Jean Capelle, Bât. Blaise Pascal, F-69621 Villeurbanne Cedex, France.</footnote>