# Piezoresistive Platinum Diselenide Pressure Sensors with Reliable High Sensitivity and Their Integration into Complementary Metal-Oxide-Semiconductor Circuits

Sebastian Lukas, Nico Rademacher, Sofía Cruces, Michael Gross, Eva Desgué, Stefan Heiserer, Nikolas Dominik, Maximilian Prechtl, Oliver Hartwig, Cormac Ó Coileáin, et al.

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Sebastian Lukas, Nico Rademacher, Sofía Cruces, Michael Gross, Eva Desgué, et al. Piezoresistive Platinum Diselenide Pressure Sensors with Reliable High Sensitivity and Their Integration into Complementary Metal-Oxide-Semiconductor Circuits. ACS Nano, 2025, 19 (7), pp.7026 - 7037. 10.1021/acsnano.4c15098. hal-05100759

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# Piezoresistive Platinum Diselenide Pressure Sensors with Reliable High Sensitivity and Their Integration into Complementary Metal-Oxide-Semiconductor Circuits

Sebastian Lukas, Nico Rademacher, Sofia Cruces, Michael Gross, Eva Desgué, Stefan Heiserer, Nikolas Dominik, Maximilian Prechtl, Oliver Hartwig, Cormac Ó Coileáin, Tanja Stimpel-Lindner, Pierre Legagneux, Arto Rantala, Juha-Matti Saari, Miika Soikkeli, Georg S. Duesberg, and Max C. Lemme*

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Cite This: ACS Nano 2025, 19, 7026–7037

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**ABSTRACT:** Membrane-based sensors are an important market for microelectromechanical systems (MEMS). Two-dimensional (2D) materials, with their low mass, are excellent candidates for suspended membranes to provide high sensitivity, small footprint sensors. The present work demonstrates pressure sensors employing large-scale-synthesized 2D platinum diselenide (PtSe₂) films as piezoresistive membranes supported only by a thin polymer layer. We investigate three different synthesis methods with contrasting growth parameters and establish a reliable high yield fabrication process for suspended PtSe₂/PMMA membranes across sealed cavities. The pressure sensors reproducibly display sensitivities above 6 × 10⁻⁴ kPa⁻¹. We show that the sensitivity clearly depends on the membrane diameter and the piezoresistive gauge factor of the PtSe₂ film. Reducing the total device size by decreasing the number of membranes within a device leads to a significant increase in the area-normalized sensitivity. This allows the manufacturing of pressure sensors with high sensitivity but a much smaller device footprint than the current state-of-the-art MEMS technology. We further integrate PtSe₂ pressure sensors with CMOS technology, improving the technological readiness of PtSe₂-based MEMS and NEMS devices.

**KEYWORDS:** platinum diselenide, pressure sensor, 2D materials, MEMS, CMOS

Research in micro- and nanoelectromechanical systems (MEMS and NEMS) has increasingly included two-dimensional (2D) materials. Their crystalline, layered nature promises decisive advantages, especially in the area of sensing.¹⁻³ One outstanding property of several 2D materials is their piezoresistivity, which can be more fully exploited due to the atomic material thinness. Piezoresistive sensors utilizing 2D materials have been demonstrated in the form of graphene-

Received: October 24, 2024

Revised: January 20, 2025

Accepted: January 23, 2025

Published: February 12, 2025

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<figure><img src="image_14.png" /><figcaption>Figure 1. (a) Atomic structure of PtSe₂ (side view of two monolayers and top view of a single monolayer). Crystal data from the Materials Project,⁵¹,⁵² graphical representation created using VESTA.⁵³ (b) Cross-sectional schematics of the process flow for the fabrication of PtSe₂/ PMMA pressure sensors. (c) Photograph of several PtSe₂/PMMA films inside their transfer frames after delamination from the growth substrate. (d-e) Optical microscopy images of PtSe₂/PMMA membrane devices on chip #182.2 with various membrane diameters. Images of 17 different chips are shown in Figure S2.</figcaption></figure>

<table><caption>Table 1. Overview of the Fabricated and Analyzed Pressure Sensor Chips<sup>a</sup></caption><thead><tr><th>source</th><th>synthesis method</th><th>chip name</th><th>approx PtSe<sub>2</sub> thickness</th><th>GF</th><th>contact metal stack</th></tr></thead><tbody><tr><td rowspan="14">University of the Bundeswehr Munich</td><td rowspan="14">thermally assisted conversion (TAC)</td><td>#133.2</td><td>12.2 nm</td><td>-6.2</td><td>Ti/Pd + Au</td></tr><tr><td>#151.2</td><td>23.5 nm</td><td>+4.2</td><td>Ti/Pd + Au</td></tr><tr><td>#180.3</td><td>6.1 nm</td><td>-33.2</td><td>Ti/Pd + Al</td></tr><tr><td>#182.2</td><td>4.2 nm</td><td>-46.8</td><td>Ti/Pd + Au</td></tr><tr><td>#183.4</td><td>3.3 nm</td><td>-55.6</td><td>Ti/Pd + Au</td></tr><tr><td>#184.3</td><td>4.2 nm</td><td>-47.9</td><td>Ti/Pd + Au</td></tr><tr><td>#190.2</td><td>14.9 nm</td><td>-32.4</td><td>Ti/Pd + Au</td></tr><tr><td>#216.3 *</td><td>3.5 nm</td><td>-30.6</td><td>Ti/Pd + Au</td></tr><tr><td>#220.1</td><td></td><td></td><td>Ti/Pd + Al</td></tr><tr><td>#220.3</td><td></td><td></td><td>Ti/Pd + Au</td></tr><tr><td>#220.4</td><td></td><td></td><td>Ti/Pd + Au</td></tr><tr><td>#221.1 **</td><td></td><td></td><td>Ti/Au</td></tr><tr><td>#221.2 **</td><td></td><td></td><td>Ti/Au</td></tr><tr><td>#249.1</td><td>20 nm</td><td>-29.6</td><td>Ti/Pd + Au</td></tr><tr><td rowspan="4">Thales R&T</td><td rowspan="4">molecular beam epitaxy (MBE)</td><td>#192.3</td><td>8.5 nm</td><td>unknown</td><td>Ti/Pd + Al</td></tr><tr><td>#192.4</td><td></td><td></td><td>Ti/Pd + Au</td></tr><tr><td>#195.8</td><td>7 nm</td><td>-38.2</td><td>Ti/Pd + Au</td></tr><tr><td>#195.9</td><td></td><td></td><td>Ti/Pd + Au</td></tr><tr><td rowspan="2">University of the Bundeswehr Munich</td><td rowspan="2">metal-organic chemical vapor deposition (MOCVD)</td><td>#266.4</td><td>5 nm</td><td>-36.0</td><td>Ti/Pd + Au</td></tr><tr><td>#268.6</td><td>3.5-5 nm</td><td>-31.3</td><td>Ti/Pd + Au</td></tr></tbody></table>

<sup>a</sup>Chip #216.3 (marked with *) featured a modified device design with reduced membrane area. Chips #221.1 and #221.2 (marked with **) were CMOS ASIC substrates featuring a different device design from all other chips.

based pressure sensors⁴⁻¹⁴ and accelerometers,¹⁵ as well as pressure¹⁶ and mass sensors¹⁷ made from one of the best-studied 2D materials, molybdenum disulfide (MoS₂). Noble-metal dichalcogenides (NMDCs), a subgroup of transition-metal dichalcogenides (TMDCs) in which the metal is a noble metal such as platinum (Pt) or palladium (Pd), have also recently gained attention. The piezoresistive properties of platinum diselenide (PtSe₂, shown with its atomic structure in Figure 1a) have been studied,¹⁸,¹⁹ and PtSe₂-based piezoresistive pressure sensors have been demonstrated.²⁰,²¹

Although the resonance²²,²³ and capacitance²⁴⁻²⁸ of 2D membranes have also been used as pressure sensor mechanisms, the piezoresistivity of 2D materials is a simple transduction mechanism for sensors with high sensitivity. A piezoresistive pressure sensor based on the NMDC palladium diselenide (PdSe₂) has been shown to reach a sensitivity of 3.9 × 10⁻⁴ kPa⁻¹; however, a silicon nitride (SiNₓ) membrane of very large dimensions was used as a mechanical support.²⁹ Utilizing the 2D material itself as a membrane instead would
<figure><img src="image_15.png" /><figcaption>Figure 2. (a) AFM height map of a device with suspended PtSe₂/PMMA membranes. AFM scan images of 8 additional chips are shown in Figure S3. (b) Height profiles extracted from the AFM height maps of the 9 chips (Figure S3). (c) Raman depth scan along a line on a device with PtSe₂/PMMA membranes. The scan line is shown in red on the microscope image. The intensities of the main PtSe₂ peak (Eg peak at ~178 rel. cm⁻¹) and the Si peak (at 520 rel. cm⁻¹) are shown in the two maps in red and blue.</figcaption></figure>

truly exploit the advantages of 2D materials in membrane-based sensors.

In our study, we aim to approach the ultimate limit of 2D membrane-based sensors. We used nanocrystalline layered PtSe₂ from three different synthesis methods: thermally assisted conversion (TAC) of predeposited Pt layers,³⁰⁻³³ metal-organic chemical vapor deposition (MOCVD),³⁴ and molecular beam epitaxy (MBE).³⁵⁻³⁷ These three synthesis methods each have their own advantages and disadvantages. While MBE and MOCVD are more likely to result in well-aligned PtSe₂ layers with larger crystallites (grains), TAC is very easily scalable to industry-relevant wafer sizes and can simultaneously produce high-quality PtSe₂ films at low temperature (<450 °C), compatible with complementary metal-oxide-semiconductor (CMOS) back-end-of-line thermal budgets. Based on our knowledge of the process of fabricating suspended 2D material membranes on sealed cavity substrates,²¹,³⁸,³⁹ we constructed and characterized pressure sensors from a total of 13 different growth batches with different synthesis parameters. The suspended PtSe₂ membranes were examined by means of atomic force microscopy (AFM) and Raman spectroscopy depth scans. The pressure sensors were measured in an automated pressure chamber, and their sensitivity was extracted. In parallel, the piezoresistive gauge factor (GF) was determined from PtSe₂ samples of the same growth batches, and its influence on the sensor sensitivity is shown. Finally, we also show PtSe₂ pressure sensors fabricated by the same methods on top of CMOS application-specific integrated circuit (ASIC) substrates from a semiconductor foundry. This demonstrates that our technology can be implemented in well-established CMOS fabrication lines.

## RESULTS

PtSe₂/Poly(methyl methacrylate) (PMMA) membrane-based pressure sensors with closed cavities and bottom contacts were fabricated as described in the Methods section. PtSe₂ synthesized by TAC, MOCVD, or MBE was transferred to target substrates and thereby suspended above pre-etched cavities using a frame-based transfer process and a subsequent patterning step. A schematic of the device cross section is shown in Figure 1b together with the process flow. A summary of the fabricated and analyzed chips is shown in Table 1.

Each chip had up to 48 sensor devices depending on the area covered with PtSe₂ during the transfer, with six different membrane diameters ranging from 1.5 to 12 µm. Each of the

devices comprised arrays of these suspended PtSe₂/PMMA membranes. The yield of intact membranes after transfer and patterning (lithography, etching, and resist removal) was generally high. Broken membranes occurred only in places where small bubbles or wrinkles had formed during transfer or where particles prevented good adhesion of PtSe₂ to SiO₂. In those places, liquid chemicals (developer, solvent) were able to penetrate the interface and delaminate the PtSe₂. The fraction of devices with an estimated 90% or more of intact membranes with respect to the number of devices covered with PtSe₂ after transfer ranged between only a few % to 100%, with its mean at approximately 71% (see left side of Figure S1). However, during pressure sensor characterization at a later stage, a large fraction of all wire-bonded devices was measured successfully, no matter if only few membranes were intact (see right side of Figure S1). This shows that only a small number of intact membranes (in theory, one) is sufficient for a highly sensitive PtSe₂-based pressure sensor.

Variations in device performance caused by the manual nature of the transfer process could be minimized in the future when large-scale, nonmanual transfer processes are utilized. Such processes already exist for 2D materials⁴⁰ and are further explored in research such as in the European (Experimental) Pilot Line Project.⁴¹

Optical microscope images of the fabricated devices are shown in Figure 1d-e and Figure S2. The color difference between chips originates from factors such as the difference in PtSe₂ thickness in the channel areas and by overetching during the patterning process in the surrounding areas of the SiO₂ substrate.

Atomic force microscopy (AFM) confirmed the suspended nature of the PtSe₂/PMMA membranes above the void, 2.0–2.5 µm deep cavities, as shown in Figure 2a and Figure S3. The membranes show a rather flat topography, with a maximum deflection of approximately 50 nm across a scanned membrane diameter of 5.2 µm, as depicted in Figure 2b. The difference in the deflection and the surface morphology between the chips can be attributed to small changes in the manual transfer process, differences in the adhesion of PtSe₂ to its growth substrate and therefore different applied tensions during delamination, and differences in the nanocrystalline structure of the various PtSe₂ films.

Additionally, Raman depth scanning⁴² was performed on devices with 12 µm membrane diameters. This method uses several line scans with consecutive laser focus planes in the z-direction to reconstruct two-dimensional images of the device cross sections (see Figure 2c and Figure S5). The intensity
<figure><img src="image_16.png" /><figcaption>Figure 3. Measurements of the PtSe₂/PMMA pressure sensors. (a) A PtSe₂ pressure sensor chip wire bonded into a chip carrier. (b-c) Photographs of the pressure chamber for sensor characterization and the pressure sensor demonstrator, respectively. (d) An example measurement curve of the change in pressure over time as recorded by a commercial reference sensor. Note that the small jumps at high pressure are interpreted as measurement artifacts caused by the switching of the electronic valves, not depicting the actual pressure inside the chamber at the particular moments in time. (e) An example measurement curve of a PtSe₂/PMMA pressure sensor with a large membrane diameter (12 µm). The resistance is maximized when the membranes are flat, as indicated by the purple circles. For both the low- and high-pressure cases, tensile strain dominates along the PtSe₂, and the resistance decreases. The sensitivity between the resistance maxima of the flat membranes and the levels of low and high pressure was extracted as indicated. The device has a high sensitivity of approximately 6 × 10⁻⁴ kPa⁻¹. (f) Exemplary measurement curve of a PtSe₂/PMMA pressure sensor with a small membrane diameter (3.4 µm). Due to the combination of tensile and compressive strains, high pressure leads to an increase in the measured resistance, while low pressure leads to a decrease. The sensitivity is extracted as indicated between the levels of high and low pressure. The device has a low sensitivity of approximately 0.3 × 10⁻⁴ kPa⁻¹. (g) Schematic of the working principle of the piezoresistive pressure sensor. (h-k) Sketched membrane deflection for the cases of low pressure, a flat membrane, ambient pressure, and high pressure, as indicated in the measurement curves in (e) and (f).</figcaption></figure>

maps of the PtSe₂ Raman peak (E_g peak at ~178 rel. cm⁻¹) show that the PtSe₂/PMMA membranes are freely suspended,

while the intensity maps of the silicon (Si) Raman peak display the profile of the 2.0–2.5 µm deep cavities below.
<figure><img src="image_17.png" /><figcaption>Figure 4. (a-b) Sensitivity of the PtSe₂/PMMA pressure sensors vs the membrane diameter of the respective device, plotted for 18 different chips. Parabolic fits (without offset and without linear terms) are shown for each chip. (c) Dependence of the sensitivity on the piezoresistive gauge factor (GF) of PtSe₂. The graph includes the data points from all chips from graphs (a) and (b), categorized by membrane diameter. Linear fits for the three different membrane diameters are plotted. In (a), (b), and (c), the error bars show the range of extracted sensitivity values for the individual devices. (d) Nonlinearity (NL) dependence on the membrane diameter. Depending on the sensor characteristics, the NLs extracted from the full pressure range or the two high- and low-pressure ranges are shown. (e) Boxplot of NLs extracted from all devices with the same membrane diameter of d = 12 µm, grouped by material growth and thickness range for TAC-PtSe₂. (f) Comparison of the mean sensitivity normalized to the membrane area (S<sub>A</sub>) for various piezoresistive pressure sensors (see also Table 2).</figcaption></figure>

Four-probe back-gated transfer measurements were con-
ducted using six-port reference devices without membranes
fabricated on the same substrates as the pressure sensors. The
field-effect charge carrier mobility μ<sub>F</sub> and sheet resistance R<sub>sheet</sub>
of the transferred PtSe<sub>2</sub> films were determined as described in
the Methods section and are displayed in Figure S6. Most
PtSe<sub>2</sub> films show R<sub>sheet</sub> in the range of a few kΩ to a few 100
kΩ and a maximum μ<sub>F</sub> between 1 and 12 cm<sup>2</sup>/(V s). One chip
of MOCVD-PtSe<sub>2</sub> (#266.4) has a higher R<sub>sheet</sub> of approx-
imately 10 MΩ up to 1 GΩ and, at the same time, a very low
μ<sub>F</sub>.

The piezoresistive gauge factor (GF) was determined for all
different batches of PtSe₂ films (except for one MBE film, for
which no additional material from the same batch was
available). The PtSe₂ was exposed to a defined strain, and
the electrical resistance was measured, as described in the
Methods section and shown in Figure S7, Figure S8, and
Figure S9. The extracted GFs are listed in Table 1. The GF
varies between the samples, ranging from -55.6 to +4.2, while
most values are close to approximately -35. The origin of the
spread of the GF is related to the layer thickness as well as the
nanocrystalline structure of the PtSe₂ and is difficult to
predict.<sup>18,19</sup> The GF is an important indicator of the resulting
sensitivity of the membrane-based pressure sensor.

The wire-bonded pressure sensor chips were characterized
in an automated pressure chamber with various gas pressures
between 200 mbar and 1550 mbar (see Figure 3a-b). Pressure,
temperature, and relative humidity were monitored by
commercial reference sensors inside the chamber. For all
measurements, the chamber was purged with nitrogen to
ensure a low relative humidity (<15%) and therefore minimize
the reaction of the sensor to a change in relative humidity. The
temperature was stable between 22 and 25 °C. The chips were
exposed to ambient light during the measurements, which, as
verified in a reference measurement (see Figure S10a), did not
lead to significant additional drifts of the sensor output due to
its low intensity.

The device resistance was recorded while the pressure inside
the chamber was cycled between low and high pressure (see
Figure 3d-f as well as Figure S11 and Figure S12). Due to the
difference in the pressure inside the cavities sealed by the PtSe₂
membranes, p<sub>internal</sub>, and the external pressure p<sub>external</sub>, the
membrane is deflected and thereby strained. A schematic of
this operation principle is shown in Figure 3g. The strain leads
to a change in the electric resistance of PtSe₂, ΔR ∝ GF·ε. The
signal shape of the devices varies depending on several factors,
mainly the membrane diameter of the device and the PMMA
thickness, as previously analyzed and simulated.<sup>21</sup> In this study,
the PMMA thickness was kept the same for all fabricated and measured chips: We used approximately 60 nm of PMMA A2 950k, which was selected as a compromise between sufficient mechanical stability for the transfer and sufficient thinness to ensure the high sensitivity of the sensors.

For a PMMA thickness of approximately 60 nm, the sensors exhibit two clearly distinguishable signal shapes, both of which are shown in Figure 3e-f. The device in Figure 3e has comparably large membranes with diameters of 12 µm. The PtSe₂ in this device dominantly experiences tensile strain in both directions of deflection (outward or inward for low and high pressures, respectively). Therefore, resistance minima can be observed for both high- and low-pressure cases in the *R* curve of this device, where the tensile strain is maximized and, due to the negative GF, the device resistance is minimized. The maxima in *R* are observed at a pressure of approximately 835 mbar, corresponding to the minima in tensile strain, i.e., a nondeflected, flat membrane. The exact pressure of the resistance maximum varies from device to device and depends on the pressure history. At an ambient pressure of approximately 1050 mbar, the membranes are therefore not unstrained but have already deflected inward. The different cases are shown in the schematics in Figure 3h-k. For the devices exhibiting the described signal shape, the sensitivity was extracted between the low pressure level and the flat-membrane resistance maximum, as well as between the mentioned resistance maximum and the high pressure level (as indicated in Figure 3e).

A different signal shape was observed for several devices with a smaller membrane diameter, such as for the device shown in Figure 3f with a membrane diameter of 3.4 µm. Here, the piezoresistively dominating type of strain changes from dominating tensile strain for the low-pressure case to a combination of tensile and compressive strain across each membrane (with a possible slight domination of compressive strain) for the high-pressure case. Compressive strain occurs in the PtSe₂ film due to its position at the bottom of the double-layer stack of PtSe₂ and PMMA, where the PMMA is approximately 3 to 18 times as thick as the PtSe₂. The dominating strain occurs around the edge of the membrane, as shown previously.²¹,⁴³ As a result, the measured devices show a resistance minimum for the low-pressure case and a resistance maximum for the high-pressure case, between which the sensitivity was extracted.

The extracted sensitivity is plotted against the membrane diameter in Figure 4a-b. The error bars show the ranges of the extracted sensitivities for each chip. A total of 264 devices across the 17 different chips with PtSe₂ from 13 different growth batches (i.e., various growth methods and/or growth parameters) were characterized, using the main device layout. Additionally, 14 devices without membranes were measured as reference devices and showed only a minor response with very low sensitivity, approximately 2 orders of magnitude lower than the sensitivity extracted from those devices with membranes, attributed to small changes in relative humidity (see four exemplary curves in Figure S13). These reference devices are plotted with a membrane diameter of zero in Figure 4a-b.

Generally, a trend of increasing sensitivity with increasing membrane diameter can be observed. This is expected due to the increase in strain with increasing membrane diameter.²¹ Parabolic fits are calculated and plotted for all different chips, following the quadratic dependence of the membrane area on

its diameter. However, multiple factors influence the sensitivity of the sensors in addition to the membrane diameter, such as the total active area (i.e., the area of the channel that is covered by intact membranes; see also Table S1), and processing variations, which cause differences in the pretension of the membranes. The parabolic fit nevertheless matches the data well for many chips.

One chip (#151.2) shows an opposite signal shape, and therefore, a sensitivity with the opposite sign is extracted (see Figure S11c and Figure 4a). This can be explained by the GF of this PtSe₂ film which, in contrast to all other samples, has a positive sign. Computational analysis¹⁹ predicts GF of both signs in nanocrystalline PtSe₂, depending on the prevalent stacking phases. The dependence of the sensitivity on the GF is further shown in Figure 4c, where the sensitivity values of all the measured devices with the three largest membrane diameters are plotted against the GF. Despite the significant spread of the data, linear fits visualize the clear trends of higher sensitivities with larger membrane diameters as well as higher sensitivities with larger GF magnitudes.

The membrane thickness *t* is expected to influence the sensitivity as well, as an increasing *t* leads to a less flexible membrane. Here, the influence of the PMMA layer is neglected due to its significantly lower Young's modulus and therefore higher flexibility. According to theoretical calculations,⁷,⁴⁴ the sensitivity *S* should follow *S* ∝ *t*⁻²/³, as plotted in Figure S14. Several data points deviate from the fit line significantly, especially the data point of sample #151.2 with negative *S* and positive GF, in contrast to all other data. This shows that the GF clearly is an influence on *S*. Furthermore, there is a general trend of higher magnitude GF with decreasing PtSe₂ film thickness *t*, complicating the differentiation between the effects of GF and *t* on *S*.

The device design with a large PtSe₂ channel and hundreds to thousands of membranes in each single device (see Table S1) has the disadvantage of low sensitivity normalized to the membrane area $S_A = S/A_{membranes,total}$ but was chosen earlier when the transfer process still resulted in lower yields of intact membranes. To show that a much higher $S_A$ is possible with the demonstrated technology, one chip (#216.3) was fabricated with enlarged Ti/Pd contact pads, covering significant parts of the cavity array and therefore reducing the active membrane area of the devices. Details on this chip can be found in Figure S15. The extracted sensitivity *S* of the two measured devices with reduced active membrane areas was on the same order of magnitude as that of the previously characterized chips (see turquoise-colored stars in Figure 4a), and the extracted sensitivity normalized to the membrane area ($S_A$) was greater by a factor of 5–6 compared to that of the chips with PtSe₂ from the same batch. For future device designs (and as already considered in the later-designed devices on CMOS ASIC substrates, see below), a much smaller footprint with fewer membranes per device should therefore be considered to achieve an even greater $S_A$.

The nonlinearity (NL) of the PtSe₂ pressure sensors was evaluated for all measured devices. The maximum *R*, corresponding to the flat membrane state of minimum strain, leads to a very nonlinear response across the whole pressure range from low to high pressure. Therefore, the NL was calculated for two ranges for each device, from low pressure to 50 mbar below the flat membrane pressure and from 50 mbar above the flat membrane pressure to high pressure, according to $NL(p) = (R_{p,measured} - R_{p,linear})/(R_{p,max} - R_{p,min})$, where $R_{p,measured}$
<figure><img src="image_18.png" /><figcaption>Figure 5. (a-c) Optical microscope images of PtSe₂/PMMA pressure sensors on CMOS ASIC substrates. (d) Reference curve of the chamber pressure during measurement. (e-f) Measurement curves of two PtSe₂/PMMA pressure sensors on CMOS ASIC substrates.</figcaption></figure>

is the measured sensor resistance at pressure $p = (p_{max} - p_{min})/2$, between the resistances $R_{p,max}$ and $R_{p,min}$ at the upper and lower bounds of the respective range, $p_{max}$ and $p_{min}$. $R_{p,linear}$ is the theoretical resistance of the sensor at pressure $p$ assuming a linear relation of $R$ and $p$ between $R_{p,max}$ and $R_{p,min}$.⁴⁵,⁴⁶ $R-p$ plots of several devices are shown in Figure S16a-d, with the ranges for NL extraction indicated. The NL is dependent on the membrane diameter $d$ (see Figure 4d), with an increase in $d$ leading to a better (i.e., lower) NL. Almost all PtSe₂ pressure sensors with $d = 12 \ \mu m$ reach a NL below 4%, while several even show a NL below 1% in both pressure ranges (see Figure 4e and, for example, chip #216.3 with a reduced active membrane area in Figure S16a).

Long-term measurements were performed on two devices on chip #220.1 (see Figure S10b), which had previously demonstrated high sensitivity and rather little drift. Starting from ambient pressure, the pressure was decreased to 200 mbar and kept constant for more than 16 min. After several minutes at 200 mbar, a drift of the device resistance toward higher values was observed, which can be attributed to slow leakage of the gas encapsulated below the membranes and, therefore, a slow reduction in the membrane deflection and strain. It was also seen in subsequent measurements that the pressure at which the device resistance was maximized was shifted to lower pressures, indicating that the flat membrane state was now reached at a lower pressure, corresponding to the pressure inside the cavities. Nevertheless, the drift is not

significant on the order of seconds. In fact, a very slow drift of a pressure sensor back to its most sensitive configuration under a permanent change in ambient conditions might be favorable for certain applications.

In addition to the devices discussed to this point, pressure sensors were also fabricated on top of commercially fabricated dedicated CMOS ASIC substrates with read-out circuitry (including multiplexers for device selection) in the layers below the pressure sensors. Microscope images of two dies on a CMOS ASIC substrate, a matrix with 16 devices, and a single device are shown in Figure 5a, b, and c, respectively. The measured devices had membrane diameters of 11.6 and 13.5 $\mu m$. Measurement curves of two devices are shown in Figure 5d-f, while more data can be found in Figure S17. The average extracted $S$ ranged between $3.1 \times 10^{-4} \ \text{kPa}^{-1}$ and $4.7 \times 10^{-4} \ \text{kPa}^{-1}$, i.e., in the same range as the devices on non-CMOS substrates. The devices on the CMOS ASIC substrates were designed with smaller membrane arrays due to space restrictions, leading to a much higher $S_A$ (see Figure 4f and Table 2).

## CONCLUSIONS

The present work shows that large-scale-synthesized PtSe₂ possesses great potential as a piezoresistive membrane material in pressure sensors. A large data set of devices, with PtSe₂ from three different synthesis methods, each featuring several synthesis batches with differing parameters, was analyzed. A
<table><caption>Table 2. Comparison of the Mean Sensitivity and the Mean Area-Normalized Sensitivity of Si-Based and 2D-Material-Based Pressure Sensors</caption><thead><tr><th>device structure</th><th>mean sensitivity [10<sup>-4</sup> kPa<sup>-1</sup>]</th><th>suspended area [µm<sup>2</sup>]</th><th>mean sensitivity normalized to membrane area [10<sup>-8</sup> kPa<sup>-1</sup> µm<sup>-2</sup>]</th><th>reference</th></tr></thead><tbody><tr><td>Si membrane with boron-implanted piezoresistors</td><td>0.24</td><td>π(80<sup>2</sup> - 20<sup>2</sup>) = 18,850</td><td>0.13</td><td>Godovitsyn et al., 2013<sup>49</sup></td></tr><tr><td>Si membrane with boron-implanted piezoresistors</td><td>0.32</td><td>450 × 1,000 = 450,000</td><td>0.0071</td><td>Infineon MultiMEMS platform pressure sensor for tire-pressure monitoring system (TPMS)<sup>45</sup></td></tr><tr><td>suspended graphene without PMMA, graphene grown by CVD</td><td>0.3</td><td>6 × 64 = 384</td><td>7.7</td><td>Smith et al., 2013<sup>7</sup></td></tr><tr><td>graphene on perforated SiN<sub>x</sub> membrane, graphene grown by CVD</td><td>2.8</td><td>490 × 490 = 240,100</td><td>0.12</td><td>Wang et al., 2016<sup>5</sup></td></tr><tr><td>BN/graphene/BN, graphene grown by CVD</td><td>1.9</td><td>6 × 64 = 384</td><td>49.5</td><td>Li et al., 2018<sup>11</sup></td></tr><tr><td>suspended graphene with 50 nm PMMA, graphene grown by CVD</td><td>0.29</td><td>20 × π·5<sup>2</sup> = 1,571</td><td>1.83</td><td>Lin et al., 2019<sup>12</sup></td></tr><tr><td>suspended graphene with 50 nm PMMA, graphene grown by CVD</td><td>0.74</td><td>3 × π·8<sup>2</sup> = 603</td><td>12.3</td><td>Liu et al., 2020<sup>8</sup></td></tr><tr><td>hBN/graphene/hBN, graphene grown by CVD</td><td>2.9</td><td>210 × 210 = 44,100</td><td>0.66</td><td>Wang et al., 2022<sup>13</sup></td></tr><tr><td>suspended graphene with 100 nm Si<sub>3</sub>N<sub>4</sub>, graphene grown by CVD</td><td>5.3</td><td>9 × 64 = 576</td><td>92.4</td><td>Zeng et al., 2023<sup>14</sup></td></tr><tr><td>graphene/hBN/graphene membrane (simulated only)</td><td>4.5</td><td>6 × 6 = 36</td><td>1,249</td><td>Zeng et al., 2024<sup>50</sup></td></tr><tr><td>PdSe<sub>2</sub> on SiN<sub>x</sub> membrane</td><td>3.9</td><td>700 × 700 = 490,000</td><td>0.08</td><td>Gong et al., 2024<sup>29</sup></td></tr><tr><td>suspended PtSe<sub>2</sub>/PMMA, PtSe<sub>2</sub> grown by TAC</td><td>13.9</td><td>157</td><td>885</td><td>Wagner et al., 2018<sup>20,43</sup></td></tr><tr><td>suspended PtSe<sub>2</sub> without PMMA, PtSe<sub>2</sub> grown by MBE</td><td>3.8</td><td>66,162</td><td>0.57</td><td>Lukas et al., 2023<sup>21</sup></td></tr><tr><td>suspended PtSe<sub>2</sub> with 60 nm PMMA, PtSe<sub>2</sub> grown by TAC</td><td>6.1</td><td>66,162</td><td>0.93</td><td>this work (#180.3, d<sub>mem</sub> = 12 µm)</td></tr><tr><td></td><td>3.7</td><td>8,822 (approx.)</td><td>4.1</td><td>this work (#216.3, d<sub>mem</sub> = 12 µm, device E1-06)</td></tr><tr><td></td><td>2.8</td><td>5,881 (approx.)</td><td>4.8</td><td>this work (#216.3, d<sub>mem</sub> = 12 µm, device E1-12)</td></tr><tr><td></td><td>4.7</td><td>1,268</td><td>36.9</td><td>this work (#221.1, d<sub>mem</sub> = 11.6 µm, device C4R2, CMOS ASIC substrate)</td></tr><tr><td>suspended PtSe<sub>2</sub> with 60 nm PMMA, PtSe<sub>2</sub> grown by MBE</td><td>4.0</td><td>66,162</td><td>0.61</td><td>this work (#192.4, d<sub>mem</sub> = 12 µm)</td></tr><tr><td>suspended PtSe<sub>2</sub> with 60 nm PMMA, PtSe<sub>2</sub> grown by MOCVD</td><td>5.2</td><td>60,536</td><td>0.86</td><td>this work (#266.4, d<sub>mem</sub> = 7.9 µm)</td></tr></tbody></table>

fabrication process to reliably fabricate suspended PtSe₂/PMMA membranes across sealed cavities with a high yield was established. The measured pressure sensors reproducibly showed sensitivities of up to higher than 6 × 10⁻⁴ kPa⁻¹ and low nonlinearities of down to <1% in several devices. The sensitivity has been shown to clearly depend on the membrane diameter and the piezoresistive gauge factor of the PtSe₂ film. We have demonstrated that a reduction in the device size through a decrease in the number of membranes within a device is possible, leading to a significant increase in the area-normalized sensitivity. This will allow the manufacturing of pressure sensors with high sensitivity but a much smaller device footprint than the current state-of-the-art MEMS technology. We have further demonstrated the feasibility of integrating PtSe₂ pressure sensors with CMOS technology, improving the technology readiness of PtSe₂-based MEMS and NEMS technology.

## METHODS

**Substrate Fabrication.** Before the PtSe₂ transfer, target substrates based on 150 mm p-doped Si wafers were prepared. For the marker layer, stepper lithography was done, and the markers were etched by reactive ion etching (RIE) with C₄F₈ and SF₆. After a second step of stepper lithography for the cavity layer, 2.0–2.5 µm

deep cavities were etched into the Si using RIE, again with C₄F₈ and SF₆ chemistry. After a subsequent cleaning step in a mix of H₂O₂ and H₂SO₄ the wafers were thermally oxidized to grow 90 nm of SiO₂ on top of the Si for passivation. Oxide growth after etching allows passivating cavity sidewalls and floors, erasing the possibility of short circuits from collapsed PtSe₂ membranes later on.

Stepper lithography with a resist double layer of lift-off resist (LOR) 3A and the photoactive AZ5214E resist was executed to deposit and pattern bottom contacts consisting of evaporated titanium (Ti, 5 nm) and palladium (Pd, 10 nm). Even though the wafer surface was uneven due to the etched cavities, the metal lift-off was successful thanks to the resist stack. A final stepper lithography and lift-off step was done to evaporate and pattern 300 nm thick aluminum (Al) pads on top of the previously patterned metal contacts in the probing pad areas for later wire bonding. Lastly, the wafers were diced to 2 cm square chips.

Due to adhesion issues with the Al pads on the Pd surface in the final step of resist stripping with TMAH-containing developer after transfer and patterning (see below), several chips were alternatively fabricated with gold (Au) bond pads. In this case, the above-mentioned Ti/Pd deposition and the subsequent gold (Au) bond pad deposition, instead of the Al deposition, were performed by contact lithography on several 2 cm pieces diced from the wafers after thermal oxide growth. The metal stack used for each respective chip is indicated in Table 1. Note that in all chips, the metal contacting the PtSe₂ was Pd.
For one chip (#216.3), lithography for Ti/Pd metallization was performed with the help of a maskless aligner (Microtech LW405C), extending the metal contacts to cover significant parts of the cavity array and therefore decreasing the active membrane area. Au bond pads were subsequently deposited by contact lithography.

**CMOS ASIC Substrate Fabrication.** The CMOS wafers used for integration of the PtSe₂ pressure sensors were manufactured using a standard commercial technology provided by X-FAB Silicon Foundries SE. The 200 mm CMOS wafers utilize a 0.18 µm analog CMOS process node with up to six metallization layers. The CMOS technology includes a wide range of active devices and high-performance analog devices.

Wafer-scale postprocessing was started by etching the vias to the topmost CMOS metal layer by inductively coupled plasma etching (ICP-RIE). Titanium tungsten (TiW)/Au (10 nm/100 nm) via metallization was deposited by sputtering and patterned using a wet etching process. In the next step, Ti/Au (2 nm/30 nm) was deposited by lift-off for the bottom contact metals. The wafers were then diced into single CMOS microsystem chips. All postprocess patterning steps were done by standard UV-lithography.

**PtSe₂ Growth.** PtSe₂ from various synthesis methods was used.

**Thermally Assisted Conversion (TAC).** Thin Pt films were initially sputtered onto Si/SiO₂ substrates using a Cressington magnetron sputter coater. These films were then converted by TAC to PtSe₂ in a custom-built cold wall TAC and CVD system. As a precursor, selenium (Se) powder (>99.5% purity, VWR) was heated to 228 °C and transported to the samples by a carrier gas flow, consisting of varying parts of N₂ and H₂ in the range of 50–500 sccm. The conversion was carried out for 120 min at a substrate temperature of 450 °C and at a low pressure of <10 mbar. Samples #184 and #190 were converted at a higher temperature of 550 °C. After conversion, the PtSe₂ films tended to be approximately 2.5–3 times thicker than the initial Pt layer.

**Molecular Beam Epitaxy (MBE).** MBE-PtSe₂ samples were synthesized in a 2-in. MBE reactor supplied by Dr. Eberl MBE-Komponenten GmbH (Germany). The sapphire (0001) (c-plane) substrates were purchased from Kyocera Corporation (Japan). The sapphire was first chemically cleaned with acetone/propanol and then a 100 nm-thick molybdenum film was deposited on the back to improve radiative heating. It was outgassed under ultrahigh vacuum (10⁻¹⁰ mbar) at 500 °C overnight and then annealed at 900 °C for 15 min. A Se flux was supplied by a valved Se cracker source filled with ultrahigh purity (7N) Se, which was heated to 290 °C, and the cracker temperature was fixed at 600 °C. A Pt flux originated from high purity (4N) Pt heated in an electron beam evaporator. During synthesis, the sapphire (0001) substrate was heated to the desired growth temperature (463 and 520 °C for samples #192 and #195, respectively) and simultaneously exposed to Pt flux (0.003 Å/s) and Se flux (0.2 Å/s and 0.5 Å/s for samples #192 and #195, respectively). Sample #195 was annealed after growth at 690 °C for 30 min under the same Se flux as used during growth. After synthesis, the substrate was cooled down to 200 °C within 20 min, continuously under Se flux.

**Metal–Organic Chemical Vapor Deposition (MOCVD).** MOCVD growth of PtSe₂ was carried out within a custom-built cold-wall reactor.³,⁴,⁷ Cleaned 20 mm × 20 mm Si chips with a 90 nm SiO₂ layer were placed on the substrate plate and heated up to 600 °C under low pressure conditions. Se powder (>99.5% purity, VWR) was evaporated at 225 °C and carried toward the reaction chamber by a H₂ flow. (Trimethyl)methylcyclopentadienylplatinum(IV) ((CH₃)₃(CH₃C₅H₄)Pt) (Strem Chemicals, 99% purity) was heated to 40 °C and used as metal–organic Pt precursor. The layer thickness was controlled by the process time, which is around 10–15 min for PtSe₂ thicknesses of approximately 3–5 nm.

**PtSe₂ Transfer.** The various PtSe₂ films were transferred to the target substrates using a frame-based temperature-assisted dry transfer method, as previously demonstrated for graphene.³⁹ A very thin layer of approximately 60 nm PMMA A2 950k was spin-coated onto the PtSe₂ films on their growth substrates. After baking at 180 °C, frames of transparent plastic foil and heat-resistant polyimide tape were

prepared and attached to the edges of the PMMA surface on the growth substrates. Here, polyimide tape with acrylic adhesive (instead of standard silicone adhesive) was used to enhance the chemical stability of the transfer frame in potassium hydroxide (KOH) solution. In the next step, each transfer frame with the attached PMMA/PtSe₂/growth substrate was placed inside a beaker filled with cured polydimethylsiloxane (PDMS), to which the back side of the growth substrate firmly adhered. A pipet was used to push a few milliliters of a 4 mol/L KOH solution below the transfer frame to the edge of the growth substrate. Intercalation of the KOH solution between the PtSe₂ and the growth substrate eventually entirely detached the transfer frame with PtSe₂/PMMA from the growth substrate (see Figure 1c). After careful removal from the KOH solution, the frame was rinsed in DI water thoroughly and finally placed in air to dry.

The PtSe₂/PMMA was then placed on top of a target substrate with its transfer frame on a hot plate at 95 °C, and the adhesive was attached to prevent any sideward motion of the transferred frame. The temperature of the hot plate was then increased to approximately 160 °C to soften the PMMA above its glass transition temperature and therefore allow the PtSe₂ to smoothly adhere to the target substrate. After successful complete adhesion, the PtSe₂/PMMA was carefully cut along the inner edge of the transfer frame with a sharp scalpel, and the frame was subsequently removed. The hot plate temperature was increased to 180 °C, and the samples were baked for 10 min.

**PtSe₂ Patterning.** PtSe₂/PMMA was patterned into the device channel shapes on all samples at a 2 cm chip level using contact lithography. The PMMA was not removed to mechanically support the PtSe₂ membranes during the fabrication process and the later device operation. LOR 3A was used between PMMA and the photoactive AZ5214E resist to prevent the mixing of the AZ5214E resist and PMMA and therefore the formation of an insoluble layer at their interface. The bottom-to-top layer stack during the lithography step was therefore PtSe₂, PMMA, LOR 3A, and AZ5214E. After exposure, AZ Developer was used for development. AZ Developer does not contain TMAH and therefore does not lead to any delamination or corrosion of the Al pads. AZ Developer also does not dissolve LOR 3A. LOR 3A, PMMA and PtSe₂ were then etched by a low-power CF₄/O₂ plasma during RIE. After etching, a low-power O₂ plasma treatment was used to remove any cross-linked polymer from the top of the photoresist layer that could otherwise remain after removal in solvents. Finally, on the chips with Al bond pads, the AZ5214E photoresist and LOR were removed by using DMSO at room temperature. Alternatively, in the case of substrates with Au bond pads and in the case of CMOS ASIC substrates, flood exposure and a 30 s dipping in a TMAH-containing developer were used to remove the LOR 3A and AZ5214E photoresist after etching and O₂ plasma treatment. This avoided the use of DMSO, which in some cases had led to the thinning or partial removal of the PMMA layer and therefore to the collapse of membranes. Optical microscope images of the final devices before wire bonding are shown in Figure 1d-e and Figure S2, as well as in Figure 5 (devices on CMOS ASIC substrates). The channel area on each fabricated device of the in-house-fabricated substrates, comprising the total membrane array area plus the surrounding passive PtSe₂ area, was 320 µm × 320 µm and included between 585 and 12,257 individual membranes, depending on the membrane diameter (see Table S1).

**Piezoresistive Characterization.** To determine the piezoresistive gauge factor (GF) of the various PtSe₂ films, small pieces of the same PtSe₂ films used for sensor fabrication were transferred onto prepared flexible polyimide (Kapton) substrates, bridging a few-mm gap between the nickel (Ni) contact pads. The samples were glued to a steel beam, and wires were soldered to the Ni contacts. The steel beam was then bent in a controlled way by applying a weight so that a tensile or compressive strain of ε = 0.0044% was applied to the sample. The setup is described in more detail in refs.¹⁸,²⁰ A Keithley 4200-SCS parameter analyzer was used for sampling the strain gauge resistance R while repeatedly applying and removing the attached mass over several minutes. The piezoresistive gauge factor GF was
then extracted using GF = ΔR/(R₀·ε),⁴⁸ where ΔR is the change in device resistance from the initial value R₀.

**Raman Spectroscopy.** A WITec alpha300 R Raman microscope with a 532 nm laser and a 1800 g/mm grating was employed for Raman cross-sectional depth scanning⁴² of the membrane devices. The focal point of the laser beam had an approximate diameter of 300 nm and a depth of ≤1 µm in the direction of the beam. We therefore chose ¹/₃ µm as lateral pixel size and set the pixel spacing in the z-direction was to 1 µm. A power of only 0.1 mW was used since a power of just 0.3 mW was found to be already sufficient to burn through and destroy the suspended PtSe₂/PMMA.

**Atomic Force Microscopy (AFM).** AFM scanning of the membrane devices was performed using a Bruker Dimension Icon atomic force microscope in tapping mode. In particular, 15 µm × 15 µm scans of the suspended PMMA/PtSe₂ membranes were recorded using a scan rate of 0.25 Hz.

**Electrical Characterization.** A Cascade Summit 12000 A semiautomatic probe station connected to a Hewlett-Packard 4156B Precision Semiconductor Parameter Analyzer and a Hewlett-Packard E5250A Low Leakage Switch Mainframe was used for electrical measurements of the back-gated test structures. Measurements were done by the Keysight WaferPro Express test routine software. The field-effect mobility was calculated according to $\mu_F = (\partial(I_D/V_{diff})/\partial V_{BG}) \cdot L_{inner} \cdot d_{ox}/(W \cdot \epsilon_{r,ox} \cdot \epsilon_0)$ from the four-probe field-effect measurements on the six-port devices, where $I_D$ is the current along the PtSe₂ channel, $V_{diff}$ is the voltage between the two inner contacts, $V_{BG}$ is the back-gate voltage, $L_{inner} \approx 25$ µm is the distance between the two inner contacts, $d_{ox} = 90$ nm is the thickness of the gate oxide, $W \approx 10$ µm is the PtSe₂ channel width, and $\epsilon_{r,ox} = 3.9$ and $\epsilon_0$ are the relative permittivity of the gate oxide and the vacuum permittivity, respectively. The values for W and $L_{inner}$ were estimated from the dimensions on the photomask. We also extracted the sheet resistance from the same measurements according to $R_{sheet} = V_{diff}W/(I_D \cdot L_{inner})$.

The 20 mm chips were manually diced into approximately 6 mm square pieces and then wire-bonded into 44-pin ceramic chip carriers (LCC44) using 25 µm diameter Au wire with a tpt HB16 wire bonder by ball bonding (see Figure 3a). The chip carriers were then inserted into a pressure chamber setup built in house and previously used by Wagner et al.²⁰ and Lukas et al.,³⁹ enabling automation of the valves for pressure control and facilitating synchronized data acquisition of the included reference sensors and the device under test (DUT) (see Figure 3b). The chamber pressure was repeatedly modulated between approximately 200 mbar and 1,500 mbar using a vacuum pump and nitrogen (N₂) gas. A Keithley 4200-SCS parameter analyzer was used for the electrical measurement of the PtSe₂-membrane-based pressure sensors by sampling for several minutes. The sensitivity S was extracted as in $S = \Delta R/(R_0 \cdot \Delta p)$, with device resistance $R_0$ at ambient pressure $p_0$, and the difference in resistance $\Delta R = R - R_0$ at the applied pressure difference $\Delta p = p - p_0$.

A technology demonstrator (see Figure 3c) was built to showcase the PtSe₂ pressure sensor functionality without the need for a pressure chamber or parameter analyzer. The demonstrator houses the pressure sensor chip inside a plastic enclosure glued to a printed circuit board (PCB). The PCB features an Arduino and a display, as well as small switches to select the device to be read. A rubber tube is connected to the plastic enclosure and to a manual 250 mL syringe, allowing to reduce the gas pressure by pulling the syringe. The sensor resistance is digitally filtered and then displayed. A change in the resistance under a change in pressure can be observed, qualitatively demonstrating the functionality of the sensor. The demonstrator is powered through a USB connection (5 V). Using the Arduino Integrated Development Environment (IDE) on a computer, multiple sensor responses over time can also be displayed in a graph.

The CMOS ASIC substrates were connected to an additional dedicated PCB to address the devices through the CMOS circuitry. The column and row of the device to be read were set through a Python script controlling the PCB. The Keithley 4200-SCS parameter analyzer was then connected to the PCB for the measurement.

# ASSOCIATED CONTENT

## Data Availability Statement

All data is available upon reasonable request to the authors.

## ● Supporting Information

The Supporting Information is available free of charge at https://pubs.acs.org/doi/10.1021/acsnano.4c15098.

Evaluation of the yield of devices, optical microscopy images of devices, AFM height maps and profiles, Raman depth scans, four-probe back-gated transfer measurements, measurement curves of the PtSe₂ resistance and two PtSe₂/PMMA pressure sensors, sensitivity plotted against $t^{-2/3}$, device resistance versus pressure curves, and different device dimensions (PDF)

# AUTHOR INFORMATION

## Corresponding Author

Max C. Lemme – Chair of Electronic Devices, RWTH Aachen University, S2074 Aachen, Germany; AMO GmbH, Advanced Microelectronic Center Aachen, S2074 Aachen, Germany; ● orcid.org/0000-0003-4552-2411; Email: max.lemme@rwth-aachen.de

## Authors

Sebastian Lukas – Chair of Electronic Devices, RWTH Aachen University, S2074 Aachen, Germany; ● orcid.org/0000-0002-8062-2832

Nico Rademacher – Chair of Electronic Devices, RWTH Aachen University, S2074 Aachen, Germany; AMO GmbH, Advanced Microelectronic Center Aachen, S2074 Aachen, Germany

Sofia Cruces – Chair of Electronic Devices, RWTH Aachen University, S2074 Aachen, Germany

Michael Gross – Chair of Electronic Devices, RWTH Aachen University, S2074 Aachen, Germany; ● orcid.org/0009-0001-9072-8200

Eva Desgué – THALES R&T, 91767 Palaiseau, France

Stefan Heiserer – Institute of Physics & SENS Research Centre, University of the Bundeswehr Munich, 85577 Neubiberg, Germany

Nikolas Dominik – Institute of Physics & SENS Research Centre, University of the Bundeswehr Munich, 85577 Neubiberg, Germany

Maximilian Prechtl – Institute of Physics & SENS Research Centre, University of the Bundeswehr Munich, 85577 Neubiberg, Germany

Oliver Hartwig – Institute of Physics & SENS Research Centre, University of the Bundeswehr Munich, 85577 Neubiberg, Germany; ● orcid.org/0000-0002-5409-4124

Cormac Ó Coileáin – Institute of Physics & SENS Research Centre, University of the Bundeswehr Munich, 85577 Neubiberg, Germany

Tanja Stimpel-Lindner – Institute of Physics & SENS Research Centre, University of the Bundeswehr Munich, 85577 Neubiberg, Germany

Pierre Legagneux – THALES R&T, 91767 Palaiseau, France

Arto Rantala – VTT Technical Research Centre of Finland Ltd, FI-02044 VTT Espoo, Finland

Juha-Matti Saari – VTT Technical Research Centre of Finland Ltd, FI-02044 VTT Espoo, Finland

Miika Soikkeli – VTT Technical Research Centre of Finland Ltd, FI-02044 VTT Espoo, Finland; ● orcid.org/0000-0002-8014-7875
Georg S. Duesberg – Institute of Physics & SENS Research
Centre, University of the Bundeswehr Munich, 85577
Neubiberg, Germany; orcid.org/0000-0002-7412-700X

Complete contact information is available at:
https://pubs.acs.org/10.1021/acsnano.4c15098

Notes

The authors declare no competing financial interest.

ACKNOWLEDGMENTS

This work received funding from the German Ministry of
Education and Research (BMBF) under grant agreement
16ES1121 (ForMikro-NobleNEMS), from the European
Union's Horizon 2020 research and innovation programme
under grant agreement 881603 (Graphene Flagship Core 3),
from the European Union's Horizon Europe research and
innovation programme under grant agreement 101135196
(2D-PRINTABLE), from the German Research Foundation
(DFG) under grant agreement LE 2441/11-1 (2D-NEMS),
and from the French ANR agency through the project ANR-
20-CE09-0026 "2DonDemand". The authors thank dtec.bw—
Digitalization and Technology Research Center of the
Bundeswehr for support (project VITAL-SENSE). dtec.bw is
funded via the German Recovery and Resilience Plan by the
European Union (NextGenerationEU).

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