ATLAS Simulation

<figure><img src="image_109.png" /><figcaption>Phase-II TDAQ Trigger Menu (TDR Table 6.4)</figcaption></figure>

Figure 6.26: Fraction of events passing Level-0 in the representative menu for which a tracking request needs a given module. This figure is constructed by summing readout fraction distributions for individual objects, such as those shown in Figures 6.24 and 6.25, multiplied by the object multiplicity for the event type and the fraction of events for which that trigger is active.

and track-based calibration of these jets (an estimate not accounting for duplicate requests of the same region 98% of the outer ITk pixel layer). It is therefore assumed that single jet, multi-jet, di-$\tau$, $E_T^{miss}$, and $H_T$ triggers will all use full-detector tracking. In addition, $e$, $\mu$, $\tau$, $\gamma$, and large-$R$ jet triggers will use gHTT as a regional tracker with a 1 GeV minimum track $p_T$ reconstructed.

Without the HTT, the nominal tracking requirements would require ≈ 10 times more CPUs than the baseline design with HTT (see Section 12.4). If less tracking is available, then the thresholds for the objects requiring tracking would need to be raised to reduce the rates. For example to reduce the tracking needs for the b-tagged four-jet the Level-0 threshold would have to be raised to an effective offline threshold of 85 GeV, which would raise the limit on the search for $HH → 4b$ by approximately 50%.
<figure><img src="image_110.png" /><figcaption>Figure 6.27: Four-jet invariant mass distribution for the $HH \to 4b$ search.</figcaption></figure>

## 6.13 Impact of the System on $HH \to 4b$

The upgrade system design has several key components which work together to provide excellent performance across a wide range of physics topics. In order to understand the interplay of the components, this section describes the $HH \to 4b$ sensitivity predictions and how they are related to the individual sub-systems.

Measurement of the non-resonant $HH \to 4b$ is a major goal of the HL-LHC because it places constraints on the Higgs self-coupling, $\lambda_{HHH}$, in the Standard Model. This parameter is related to the form of the Higgs potential, so its measurement is a direct test of the model of the spontaneous symmetry breaking mechanism in the SM. The Higgs self-coupling is also related to the order of the phase transition in the earlier universe [6.14], an important condition for the generation of the matter-antimatter asymmetry of the universe.

The projections are based on the Run 2 analysis [6.15] scaled to 14 TeV and an integrated luminosity of 3000 fb$^{-1}$. The analysis is based on a selection of four b-tagged jets with two pairs each having an invariant mass consistent with the Higgs boson mass. These event would be recorded by a four-jet trigger. Hadronic top quark decays are vetoed explicitly by constructing top quark candidates in the events. Additional mass-dependent requirements are made on the leading and sub-leading Higgs boson candidate $p_T$, and the $\Delta\eta$ and $\Delta R$ between the two Higgs boson candidates. Figure 6.27 shows the four-jet invariant mass, $m_{4j}$, of the resulting sample which is used as the final discriminant in a fit. Multi-jet QCD is the dominant background (≈ 90%) followed by $t\bar{t}$ (≈ 10%).
<figure><img src="image_111.png" /><figcaption>Figure 6.28: Non-resonant $HH \to 4b \sigma/\sigma_S M$ 95% exclusion sensitivity as a function of the minimum offline jet $p_T$ used in the analysis.</figcaption></figure>

The backgrounds are modelled using the data-driven model from Run 2 analysis because this background is difficult to model with simulation. The impact of the improved ITk b-tagging efficiency is included, but the potential degradation of the performance due to pile-up and detector ageing is not. There are also many potential future improvements in analysis technique that are possible but not yet explored.

Systematics uncertainties play an important role in this analysis, but are difficult to project out to high luminosity and HL-LHC conditions. Two extrapolations are therefore considered: one without systematic uncertainties, and one with the Run 2 systematics uncertainties applied without any scaling. The resulting sensitivity for the non-resonant cross-section as a function of the minimum jet $p_T$ requirement is shown in Fig. 6.28 for the two systematics scenarios. The sensitivity to $\lambda_{HHH}$ is shown in Fig. 6.29. Since the minimum jet $p_T$ used in the offline analysis is set by the four-jet trigger threshold, which in turn depends on the trigger architecture, these plots can be used to assess the impact on the analysis of various hardware scenarios.

All cases show substantial degradation with increased minimum jet $p_T$ requirements. Table 6.7 shows the impact on this analysis for three scenarios with reduced upgrades: a) no Global Trigger, b) no HTT, and c) no-upgrade as previously defined to mean the Phase-I system with an output rate for 100 kHz. Without the Global Trigger system, the threshold for the lowest $p_T$ jet in a four-jet trigger would have to be raised to approximately 75 GeV instead of 65 GeV to maintain the same Level-0 output rate. In addition, the loss of acceptance for near-by jets would cause an further efficiency loss of 10-15%. The impact of that reduction on the $HH \to 4b$ analysis would be to reduce the cross-section sensitivity by $\approx 25\%$. Without the HTT, the tracking would be CPU-limited, and the Level-0 trigger rate would need to be reduced by a factor of $\approx 10 \times$ to allow CPUs in the Event Filter to do the required tracking. Such a rate reduction corresponds to a 85 GeV threshold, and an $\approx 45\%$ loss of sensitivity. With no upgrade at all the loss is greater than $\approx 65\%$ A scenario with
<figure><img src="image_112.png" /><figcaption>Figure 6.29: Allowed intervals for the $\lambda_{HHH}$ parameter assuming the standard model as function of the minimum offline jet $p_T$ used in the analysis.</figcaption></figure>

<table><caption>Table 6.7: Estimated loss of sensitivity in the $HH \to 4b$ analysis in various reduced upgrade scenarios</caption><thead><tr><th rowspan="2">System Modification</th><th rowspan="2">Threshold raise from 65 GeV to ...</th><th colspan="2">Cross-section Sensitivity</th><th colspan="2">$\lambda_{HHH}$ Sensitivity</th></tr><tr><th>no syst</th><th>w/ syst</th><th>no syst</th><th>w/ syst</th></tr></thead><tbody><tr><td>No Global Trigger</td><td>75 GeV (and 10% loss of efficiency)</td><td>25%</td><td>62%</td><td>28%</td><td>26%</td></tr><tr><td>No HTT</td><td>85 GeV (needed to reduce tracking CPU by ≈ 10×)</td><td>47%</td><td>92%</td><td>43%</td><td>47%</td></tr><tr><td>No upgrade</td><td>100 GeV (Phase-I system with 100 kHz output rate)</td><td>97%</td><td>154%</td><td>79%</td><td>67%</td></tr></tbody></table>

a DAQ upgrade to 1 MHz, but no trigger upgrade would give similar performance to the no-HTT scenario, because the system would be limited by the Event Filter CPU.

## 6.14 System Flexibility and Dataset Quality

The menu presented in Section 6.11 shows that the system is capable of achieving the goals set in Section 2. The HL-LHC will run for a period of approximately a decade, and these data may be the best/only sample collected for a significant period after the end of data-taking. It is therefore critical that the resulting sample be sufficiently inclusive that innovations either in experimental technique or theory can be addressed with the sample. In particular, new models often have new signatures, and precision measurements require
calibration and control datasets, the full scope of which is difficult to anticipate a decade
before the final result is complete. The menu presented is therefore based on inclusive triggers that are not tuned to specific physics analysis targets, but designed to include high priority targets and provide a complete dataset for the future. The Level-0 is designed to maximise the physics entering the Event Filter, because the Event Filter being software-based can be modified near to or during data-taking and can support significantly more algorithm complexity. By providing tracking capabilities to the trigger similar to those of the offline reconstruction, the hardware tracking provides the computing resources to allow for future optimisations without being computing limited. This flexibility in the Event Filter also provides the capability to reduce the Event Filter output rate if needed by moving analysis-specific selections online for known analysis targets at the expense of reducing the richness and long-term value of the dataset.

References

[6.1] ATLAS Collaboration, *The ATLAS Experiment at the CERN Large Hadron Collider*, JINST 3 (2008) S08003.

[6.2] GEANT4 Collaboration, S. Agostinelli et al., GEANT4: A simulation toolkit, Nucl. Instrum. Meth. A 506 (2003) 250.

[6.3] T. Sjostrand, S. Mrenna, and P. Z. Skands, *A Brief Introduction to PYTHIA 8.1*, Comput. Phys. Commun. 178 (2008) 852, arXiv:0710.3820 [hep-ph].

[6.4] ATLAS Collaboration, G. Aad et al., *Topological cell clustering in the ATLAS calorimeters and its performance in LHC Run 1*, Eur. Phys. J. C77 (2017) 490, arXiv:1603.02934 [hep-ex].

[6.5] ATLAS Collaboration, *Electron efficiency measurements with the ATLAS detector using the 2012 LHC proton-proton collision data*, ATLAS-CONF-2014-032, 2014.

[6.6] ATLAS Collaboration, *Electron efficiency measurements with the ATLAS detector using the 2015 LHC proton-proton collision data*, ATLAS-CONF-2016-024, 2016.

[6.7] M. Cacciari, G. P. Salam, and G. Soyez, *The Anti-k(t) jet clustering algorithm*, JHEP 04 (2008) 063, arXiv:0802.1189 [hep-ph].

[6.8] ALEPH Collaboration, D. Buskulic et al., *Performance of the ALEPH detector at LEP*, Nucl. Instrum. Meth. A360 (1995) 481-506.

[6.9] ATLAS Collaboration, *Jet reconstruction and performance using particle flow with the ATLAS Detector*, Eur. Phys. J. C77 (2017) no. 7, 466, arXiv:1703.10485 [hep-ex].

[6.10] D. Krohn, J. Thaler, and L.-T. Wang, *Jet Trimming*, JHEP 02 (2010) 084, arXiv:0912.1342 [hep-ph].
[6.11] LHC Higgs Cross Section Working Group Collaboration, D. de Florian et al.,
*Handbook of LHC Higgs Cross Sections: 4. Deciphering the Nature of the Higgs Sector*,
arXiv:1610.07922 [hep-ph].

[6.12] ATLAS Collaboration, *Technical Design Report for the ATLAS Inner Tracker Strip Detector*, Tech. Rep. CERN-LHCC-2017-005, CERN, Geneva, Apr, 2017.
https://cds.cern.ch/record/2257755.

[6.13] ATLAS Collaboration, *Technical Design Report for the ATLAS Inner Tracker Pixel Detector*, Tech. Rep. CERN-LHCC-2017-021, CERN, Geneva, (in preparation).

[6.14] A. Noble and M. Perelstein, *Higgs self-coupling as a probe of electroweak phase transition*, Phys. Rev. D78 (2008) 063518, arXiv:0711.3018 [hep-ph].

[6.15] ATLAS Collaboration, *Search for pair production of Higgs bosons in the b¯b final state using proton–proton collisions at √s = 13 TeV with the ATLAS detector*,
Tech. Rep. ATLAS-CONF-2016-049, CERN, Geneva, Aug, 2016.
https://cds.cern.ch/record/2206131.
# Part II

## Detailed Description of System Components
<figure><img src="image_113.png" /></figure>
# 7 Level-0 Calorimeter Trigger

The Level-0 Trigger consists of the Level-0 Calorimeter Trigger, the Level-0 Muon Trigger, the Global Trigger and the CTP. Whereas the Calorimeter- and Muon-Trigger identify and determine the properties of TOBs, the Global Trigger refines the information using higher granularity calorimeter information and combines the information from the calorimeters and the muon system. It applies topological algorithms and sends the information to the CTP which issues the L0A signal. This chapter describes the Level-0 Calorimeter Trigger.

The basis of the Level-0 Calorimeter Trigger consists of the Level-1 Calorimeter Trigger which will be installed during the LHC Long Shutdown 2 and operated during Run 3 [7.1]. It is designed with forward compatibility to be operated during Run 4. Various hardware, firmware and software modifications are needed to accommodate the changes of the over-all TDAQ system and the new calorimeter signal paths. We expect to implement improvements to the feature extraction algorithms based on the experience of operation during Run 3. The performance of the system will be enhanced by an additional processing system, the fFEX, which targets at the precise reconstruction of forward electrons and jets. In this chapter the L0Calo system is described with special focus on the technical changes to the existing system and potential improvements.

## 7.1 Evolution of the Hardware Calorimeter Trigger

### 7.1.1 Enhancements and Interface changes of the Phase-I Level-1 Calorimeter Trigger

The Level-1 Calorimeter Trigger that is currently being built within the Phase-I upgrade is constrained by various requirements. These constraints become less stringent at Phase-II, due to changes of the overall detector and readout-electronics.

* The latency budget will be significantly relaxed. This will allow the implementation of more complex algorithms with a potentially longer execution time.

* The signals from the Tile Calorimeter are currently provided as analogue sums, so-called trigger towers. The L1Calo PreProcessor system which will digitise the Tile analogue trigger signal as input to the FEXs will become obsolete after the Phase-II upgrade. The processing will be performed within the Tile backend electronics similar to the LAr calorimeter.
* The LAr Calorimeter will provide signals, in particular cell information from the forward calorimeter FCal, in addition to the already provided super cell and Trigger Tower information. This will enable the implementation of better performing algorithms.

* The output signals will be sent to the Global Trigger as well as to the legacy L1Topo System, in the last case for commissioning purposes.

### 7.1.2 Requirements for the Level-0 Calorimeter Trigger

The core of the Level-0 Calorimeter Trigger will be the Level-1 Calorimeter Trigger of the Phase-I upgrade. The proposed upgrade of the calorimeter electronics and the TDAQ system leads to a number of new requirements which the Level-0 Calorimeter Trigger needs to follow. These requirements concern in particular the interfaces to upstream and downstream systems as well as the implementation of the new fFEX processing system.

* The Level-0 Calorimeter Trigger needs to implement the remapping of the digital input signals from the Tile Calorimeter.

* Inputs from the full granularity cell signal electronics for $|η| > 2.5$ need to be received.

* The processing of the fine granularity input signals in the forward region needs to be implemented.

* The acceptance to trigger on electrons and photons should be extended beyond the region which will not be covered by the Phase-I system ($2.5 < |η| < 4.9$).

* The triggering on jets for $|η| > 3.2$ should be improved using the high granularity inputs.

* The firmware that formats the output signals to the Global Trigger and to L1Topo needs to be revised.

* The arrival time differences between signals from different partitions need to be compensated.

## 7.2 Performance of the Level-0 Calorimeter Trigger

The Level-1 Calorimeter Trigger of the Phase-I system is designed such that it copes with the conditions of the LHC Run 3. The conditions during Run 4 will be harsher, e.g. the pile-up will increase to about $\mu = 200$. This will naturally increase the trigger rates and worsen the purity of the object identification by the trigger processors. In order to counteract this effect, the Level-0 system will be enhanced by the Global Trigger. The performance of the combined system (FEXs and Global Trigger) will be such that the trigger thresholds can be chosen reasonably low to cover the whole physics programme. The performance of the combined system is discussed in Section 6. Here we discuss the performance of the Level-0 Calorimeter Trigger object finding.
As discussed in Section 6.3, the electron selection of the eFEX will be enhanced by additional cluster shape variables which are determined in the Global Trigger. The performance of the combined system (Level-0 Calo and Global Trigger) allows to set the single electron threshold at about 20 GeV. Figure 7.1 a) displays the rates for triggering on electrons with the Level-0 system. The different curves show the effect of applying veto condition successively. The variables $R_{\eta}$ and $R_{HAD}$ will be used in the eFEX algorithm. The variable $E_{ratio}$ will be used in the Global Trigger algorithm. A substantial rate reduction from the initial selection which is based on finding energy maxima in the super cell grid, can be observed. Figure 7.2 shows the efficiencies for reconstructed taus as function of the offline transverse momentum of the tau candidates. Sharp turn-ons can be observed over a large range. The 90% efficiency is reached between 40 GeV and 60 GeV depending on the exact threshold value. The performance is sufficient to support the physics programme as discussed in Section 6.5.

Single jets are well triggered by the jFEX system (see Figures 6.10 a) and 6.10 b)). Multijets are handled by the Global Trigger. Jets in the forward direction suffer from harsher pile-up conditions compared to central jets. The fFEX is designed to process the cell level calorimeter input for $|\eta| > 2.5$. It will improve the current jet reconstruction for high $\eta$ which is based on trigger towers. Figure 7.1 b) shows the rate for forward jets using different reconstruction algorithms. The standard trigger algorithm leads to a rate which is about an order of magnitude higher compared to the offline algorithm. The usage of an anti-$k_t$ algorithm does not improve the situation. This leads to the conclusion that the amount of information is not sufficient to decrease the trigger rate. The cell information which is available for fFEX can be employed to reduce the rates below the values given by the Phase-I system.

The gFEX system will continue to trigger on boosted topologies by identifying large-radius jets that are characteristic of Lorentz-boosted objects. The jet-finding algorithm in the gFEX consists of building $\eta \times \phi = 0.6 \times 0.6$ fully overlapping regions as described in Section 3.2.1. The performance of the gFEX at $<\mu>= 200$ is shown in Fig. 7.3.

## 7.3 Architecture and Hardware Realisation

The core components of the Run 3 hardware described as the Level-1 Calorimeter Trigger in the Phase-I TDR [7.1] will stay untouched. Nevertheless various modifications, especially of the interfaces with upstream and downstream systems, are necessary.

### 7.3.1 Overview

Figure 7.4 shows a functional diagram of the Level-0 Calorimeter Trigger. The L0Calo system receives digital input signals from both calorimeter systems (LAr and Tile) through optical fibres. The signals are routed through the Fibre Optic eXchange (FOX) (described
<figure><img src="image_114.png" /><figcaption>Figure 7.1: a) Level-0 trigger rates for electrons. The different curves are for the successive application of veto conditions. b) The forward ($|η| > 3.2$) single-jet trigger rate vs. offline $p_T$ thresholds for jets reconstructed in the jFEX. The efficiency is evaluated using $HH → bbbb$ signal events, and the trigger rate is evaluated based on minimum bias background events at $\langle μ \rangle \simeq 200$. The jFEX algorithm, the offline anti-$k_t$ algorithm (run over $η \times φ = 0.1 × 0.1$ towers), and the full offline reconstruction are compared.</figcaption></figure>

<figure><img src="image_115.png" /><figcaption>Figure 7.2: Efficiency to trigger on taus for different trigger thresholds as function of the true transverse momentum of the tau.</figcaption></figure>

below) to the Feature Extractors (FEXs) which constitute the core of the Level-0 Calorimeter Trigger. Three different FEX systems, which are currently being built for the Phase-I upgrade, will operate complex algorithms to identify electrons, photons and taus (eFEX), jets, large area taus, missing and total energy (jFEX) as well as large area jets and alternat-
<figure><img src="image_116.png" /><figcaption>Figure 7.3: The expected performance of the gFEX at $<\mu> = 200$. The trigger rate vs. the leading $R = 1.0$ jet $p_T$ at 95% efficiency is shown. The gFEX “cone jet” algorithm is used.</figcaption></figure>

ive missing transverse energy algorithms (gFEX). During Run 3 the objects are sent to the L1Topo, which counts the number of trigger objects above configurable thresholds and performs topological algorithms like e.g. the calculation of invariant masses. With the Phase-II upgrade, these tasks are taken over by the Global Trigger (described in Section 9). The trigger objects will be sent optically to the Global Trigger which can use the full calorimeter granularity to run more sophisticated algorithms. The information sent to the CTP consists of multiplicities of objects (e.g. electrons above a $p_T$ threshold) and flags indicating if topological requirements, etc., have been satisfied.

In order to enhance the capabilities of the system, an additional FEX system will be built, the forward FEX (fFEX). It will operate on the full granularity FCal and HEC data as well as the cell information of the inner part of the EMEC ($|\eta| > 2.5$), which enables the reconstruction of forward electrons and forward jets. The hardware implementation will be based on the jFEX modules, which are currently being built within the Phase-I upgrade. At the beginning of Run 4 the L1Topo will be operated in parallel to the Global Trigger. Once the Global Trigger is fully commissioned, L1Topo will be decommissioned.
<figure><img src="image_117.png" /><figcaption>Figure 7.4: Functional diagram of the Level-0 Calorimeter Trigger: The input signals from calorimeters (LAr and Tile) are sent to the processing systems. Feature extractors eFEX, jFEX and gFEX will be built as part of the Phase-I upgrade programme. fFEX will be a new component. The identified trigger objects are sent to the Global Trigger as well as to L1Topo. The L1Topo will be operated during the commissioning phase. Once the Global Trigger is fully operational, L1Topo will be decommissioned. The different components of the detector backend electronic systems as well as the Fibre-Optic eXchange Plant (FOX) are not shown explicitly in this diagram.</figcaption></figure>

### 7.3.2 Input Signals

**Requirements** Figure 7.5 shows the connectivity between the different partitions of the calorimeter and the FEX processing systems. The input signals are sent as transverse energies per bunch crossing partially corrected for pile-up backgrounds. The preprocessing of the digitised signals take place in the calorimeter backend systems. Special algorithms are employed to determine the bunch crossing where the interaction of an energy deposition took place. The signal to noise ratio is improved using digital filter algorithms which correct also for in- and out-of-time pile-up.

**LAr Calorimeter Signals** The Level-0 Calorimeter Trigger receives digital input data from the backend electronics of the calorimeter systems. The calorimeter cells are summed up to super cells in the FE electronics. They consist of up to 32 detector cells. The information is sent to the LDPS and from there to the FEXs. The shape and the size of the super cells depends on the LAr layer and they are optimised for algorithms which aim to identify electromagnetic energy deposits. These data are sent to the eFEX system. The LDPS also provides coarser granularity data for the jFEX and the gFEX systems. For the jFEX system energy sums are computed over the full longitudinal depths and areas which extend over $\Delta\eta \times \Delta\phi$ of 0.1 × 0.1 whereas these sums for the gFEX extend over 0.2 × 0.2. The LDPS is part of the LAr Phase-I upgrade [7.2].

The Phase-II upgrade of the LAr electronics consists of the complete replacement of the cell readout chain from the frontend to the backend (the Phase-I upgrade trigger path will be kept) [7.3]. The 180k LAr cells will be digitised at 40 MHz on detector and signals will be available on the backend system (LASP). It provides detailed strip layer information to
<figure><img src="image_118.png" /><figcaption>Figure 7.5: The connectivity of the calorimeter partitions with the FEX systems through the different backend systems is shown. LDPS is the LAr Digital Processing System. The labels at the input to the different FEX systems describe the granularity of the input data. The acronym TT refers to trigger towers which cover an area in $\Delta\eta \times \Delta\phi$ of 0.1 × 0.1 for $|\eta| < 2.5$. Beyond this value the granularity increases 5.1; gT refers to the inputs to the gFEX and cover an area of 0.2 × 0.2; sCell are super cells, and Cell means cell-level information.</figcaption></figure>

the **Global Trigger**. The LASP system will also provide data for the Level-0 Calorimeter Trigger. It sends the signals from the hadronic endcap part (HEC), the inner part of the electromagnetic endcap (EMEC) and the forward calorimeter (FCal). The change of the data source for the legacy FEX systems (eFEX, jFEX and gFEX) will be transparent. The signals will be sent with the same granularity and data content as will be done for the Phase-I system, i.e. no hardware or firmware modification will be needed. The new feature extractor fFEX will receive cell level information for $|\eta| > 2.5$ including data from EMEC, HEC and FCal. This system will enhance the capabilities to trigger on forward electrons and jets using the high granularity inputs. The new feature extractor makes modifications of the FOX system necessary.

**Tile Calorimeter Signals** The signals from the Tile Calorimeter during Run 3 will be transmitted electrically and digitised and pre-processed within the Level-1 Calorimeter Trigger. For the Phase-II upgrade a complete redesign of the signal chain will be implemented. The Tile signal digitisation takes place within the Tile frontend electronics followed by optical transmission to the (TPPr) [7.4] where the cell energies are determined. The signals for the Level-0 Calorimeter Trigger are prepared within the TDAQ interface (TDAQi) and transmitted to the FEX systems. The TDAQi system consists of electronic boards which are connected at the rear of the shelves filled with TPPr modules. There are in total 32 TDAQi boards being built. Since the individual modules of the Level-1 Calorimeter PreProcessor (Phase-I) and the Tile PreProcessor (Phase-II) cover different calorimeter areas a redesign of the Fibre Optic eXchange (FOX) responsible for the distribution of the Tile signals is necessary.
<figure><img src="image_119.png" /><figcaption>Figure 7.6: This diagram shows the connectivity between the calorimeter backend electronics and the processing system of the Level-0 Calorimeter Trigger consisting of four FEX systems. The signals are processed within the LDPS and LASP modules for the LAr Calorimeter and the PPr-TDAQi modules for the Tile Calorimeter. The signals for the trigger processors are sent digitally on optical fibres. A Fibre Optic eXchange system (FOX) redistributes the signals to the according FEX processing system. The FOX consists of an input stage a remapping stage and an output stage.</figcaption></figure>

**The Fibre Optic eXchange (FOX)** The FOX (shown in Fig. 7.6) performs a remapping of the input signals between the calorimeter electronics and the FEX system. The signals are received in fibre bundles of 12 fibres and transmitted in bundles of 48 or 72 fibres. The receiving part of the FOX is partitioned in a LArFOX and a TileFOX. The output section is partitioned into 4 parts according to the four FEX systems. In between the signals are redistributed with custom made distribution ribbons. Figure 7.7 shows the detailed inter-connectivity for one of the FOX boxes. The Phase-II upgrade necessitates a redesign of the TileFOX and the LArFOX as well as the connected distribution ribbons which connect the input to the corresponding output FOX units. A special fFOX needs to be built as well. The whole system consists of passive components. The requirements concerning the signal integrity do not change, since the data rates are the same as before. The new components, the TDAQi and the LASP transmit data with the same rate as the legacy systems.

Table 7.1 lists the number of fibres which connect the backend electronics of the various detector regions and the FEX systems. Each fibre carries the signals of a fixed number of channels. The signals have a resolution of 10 bits for the LAr signals and 10 bits for the Tile signals. The optical transmission operates at a data rate of 11.2 Gb/s. Since the data transfer is synchronous, no algorithms for data reduction are employed. The amount of transmitted data is always the same for each event.

### 7.3.3 Processing System

The processing system consists of four FEX systems three of which are being built within the Phase-I upgrade. The three systems consist of a different number of processing modules: eFEX (24), jFEX (6) and gFEX (1). The hardware will stay untouched. All the necessary
<figure><img src="image_120.png" /><figcaption>Figure 7.7: Diagram of the interconnectivity within an example FOX box.</figcaption></figure>

<table><caption>Table 7.1: Number of fibres connecting the backend electronics of the respective detector regions and the FEX systems as well as the type of information which is transmitted. TT corresponds to the trigger towers which represent transverse energy sums over cells in areas of $\Delta\eta \times \Delta\phi = 0.1 \times 0.1$ and in full depths. gT refers to gTowers, which represent sums in $\Delta\eta \times \Delta\phi = 0.2 \times 0.2$ and in full depths. sCell corresponds to super cells and Cell corresponds to the individual detector cells.</caption><thead><tr><th rowspan="2"></th><th colspan="2">EMB</th><th colspan="2">EMB/EMEC</th><th colspan="2">EMEC</th><th colspan="2">EMEC/HEC</th><th colspan="2">FCal</th><th colspan="2">Tile</th></tr><tr><th>fibres</th><th>type</th><th>fibres</th><th>type</th><th>fibres</th><th>type</th><th>fibres</th><th>type</th><th>fibres</th><th>type</th><th>fibres</th><th>type</th></tr></thead><tbody><tr><th>eFEX</th><td>800</td><td>sCell</td><td>800</td><td>sCell</td><td>640</td><td>sCell</td><td>240</td><td>sCell</td><td>64</td><td>sCell</td><td>384</td><td>TT</td></tr><tr><th>jFEX</th><td>192</td><td>TT</td><td>192</td><td>TT</td><td>160</td><td>TT</td><td>336</td><td>TT</td><td>64</td><td>TT</td><td>384</td><td>TT</td></tr><tr><th>gFEX</th><td>32</td><td>gT</td><td>32</td><td>gT</td><td>32</td><td>gT</td><td>64</td><td>gT</td><td>18</td><td>gT</td><td>32</td><td>TT</td></tr><tr><th>fFEX</th><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>320</td><td>Cell</td><td>162</td><td>Cell</td><td>-</td><td>-</td></tr></tbody></table>

requirements to operate the system after Phase-II is taken into account during their design at Phase-I. The additional FEX, the fFEX will consist of two modules. It is described below.

The modules are characterised by a large number of input links, several high performance FPGAs for processing and a smaller number of output links sending the processing results to L1Topo during Run 3 and to the Global Trigger after the Phase-II upgrade. The main characteristics of the modules are summarised in Table 7.2.

The infrastructure firmware which handles the input and output signals on the FEX processor boards needs to be changed to accommodate the different routing paths of the input signals and to change the output to the Global Trigger instead of L1Topo.

### 7.3.4 The forward FEX System (fFEX)

The forward FEX system aims at the reconstruction of electron/photon and jet candidates in the forward direction ($|\eta| > 2.5$ for electrons and $|\eta| > 3.2$ for jets). It profits from the
<table><caption>Table 7.2: Main characteristics of the FEX systems.</caption><thead><tr><th></th><th>modules</th><th>shelves</th><th>power per module</th><th>coverage</th><th>available input links per module</th><th>processing FPGAs per module</th><th>available output links per module</th></tr></thead><tbody><tr><td>eFEX</td><td>24</td><td>2</td><td>400 W</td><td>|η| &lt; 2.5</td><td>144</td><td>4</td><td>48</td></tr><tr><td>jFEX</td><td>6</td><td>1</td><td>400 W</td><td>|η| &lt; 4.9</td><td>240</td><td>4</td><td>48</td></tr><tr><td>gFEX</td><td>1</td><td>1</td><td>300 W</td><td>|η| &lt; 4.9</td><td>312</td><td>4</td><td>108</td></tr><tr><td>fFEX</td><td>2</td><td>1</td><td>400 W</td><td>2.5 &lt; |η| &lt; 4.9</td><td>252</td><td>4</td><td>48</td></tr></tbody></table>

changes in the LAr readout electronics, which allow for the transmission of the individual cell information rather than trigger towers or super cells. This allows the application of sophisticated algorithms and a better rate control in this region where the background from pile-up is particularly large.

In order to implement this functionality a processing system consisting of two modules is foreseen. Each board covers one detector side (|η| > 2.5) and receives 241 fibres that carry the cell signals of the FCal, the inner part of the EMEC and the HEC part of the LAr calorimeter [7.3]. The implementation is based on the jFEX module, which is currently being designed in the context of the Phase-I upgrade.

## Requirements of the fFEX

* The modules need to connect to 241 input fibres.

* The input data need to be received and distributed to the processing FPGAs.

* Algorithms need to be implemented which identify electron/photon and jet candidates

* The processing output needs to be provided to the Global Trigger.

### Technical Implementation of the fFEX

The technical implementation of the fFEX is based on the jFEX modules which are currently being built in the framework of the Phase-I upgrade project. Figure 7.8 shows the final prototype of the jFEX module. The fFEX modules will be implemented using the ATCA standard. They are equipped with optical receivers and transmitters to connect to the upstream and downstream components (calorimeters, FELIX, TTC and DCS). The processing will be performed using four high speed grade FPGAs which provide the appropriate input resources to receive the calorimeter signals. In order to share information between FPGAs, inter FPGA communication will be implemented through high speed links. The output data will be formatted and transmitted through optical links to the Global Trigger. The configuration and control will be implemented and real time monitoring data will be sent to DCS using the FELIX interface.
<figure><img src="image_121.png" /><figcaption>Figure 7.8: Photograph of the final prototype of a jFEX blade. The board is equipped with four high speed grade FPGAs and the minipod connectors for the optical input and output. Missing on this module are various infrastructure components for control and power management of the board.</figcaption></figure>

### 7.3.5 Output Signals

During Run 3 the FEX systems send the information of the identified Trigger Objects (TOBs) to L1Topo, which counts the number of TOBs above various configurable thresholds and performs topological algorithms like the determination of the invariant mass of pairs of objects. The information is then sent to the central trigger processor (CTP), which determines the final trigger decision and issues the Level-1 accept signal leading to the readout of the event.

The task of L1Topo is taken over by the Global Trigger after the Phase-II upgrade. For this purpose the output fibres are connected to the Global Trigger hardware and the TOB information is sent to the Global Trigger. The TOBs will be sent directly from each of the FP-GAs to the Global Trigger. The TOBs contain the information about the type of the objects, their transverse momentum and their position.

In order to manage the transition during the commissioning phase the signals are still sent to L1Topo, which remains in operation until the Global Trigger is fully commissioned. A duplication of the signal output is therefore needed. For the gFEX system this can be performed at module level. There exists enough spare output capacity. The number of output fibres from the eFEX and jFEX system are limited, making the splitting of the optical output signals necessary.
<table><caption>Table 7.3: Number of output links and bits per TOB from each FEX system to the Global Trigger system.</caption><thead><tr><th></th><th>links to Global per FEX module</th><th>bits per TOB (Global)</th></tr></thead><tbody><tr><td>eFEX</td><td>48 (after splitting)</td><td>64</td></tr><tr><td>jFEX</td><td>48 (after splitting)</td><td>32</td></tr><tr><td>gFEX</td><td>32</td><td>64</td></tr><tr><td>fFEX</td><td>48</td><td>32</td></tr></tbody></table>

Apart from the changes of the routing of the optical fibres also firmware changes are foreseen to allow to send more data from the FEX systems to the Global Trigger. This allows sending more detailed information about the Trigger Objects. The amount of output for the Phase-I system is limited by the L1Topo design which allows a certain amount of input data only. The Global Trigger will be able to accept more information. The content of the TOBs will be enhanced by detailed information about the variables which are used for identification rather than whether a certain condition has been fulfilled. This additional information can then be used by the Global Trigger as input for e.g. a BDT. Table 7.3 summarises the number of output links to the Global Trigger along with the number of bits available for each TOB.

### 7.3.6 Latency

The input signals from the calorimeters arrive 1.1 µs (LAr) and 1.45 µs (Tile) after the time of the collision at the input to the FEX processors. The available processing time is 500 ns. This can be compared with the Phase-I processing time of 125 ns. The quadrupled available processing time therefore allows for significantly more complex algorithms to be deployed. The time needed to submit signals from the output of the FEXs to the inputs of the Global Trigger is 175 ns. Further details can be found in Section 5.2.8.

### 7.3.7 Readout and Monitoring

The main purpose of the readout of the Level-0 trigger data is the possibility to perform a detailed monitoring of the processing algorithms. This helps to identify possible hardware malfunctions, problems with the algorithms or potential problems with the input data (e.g. noise bursts). The readout data consist of the information of the TOBs. The calorimeter information will be read out by the calorimeter systems such that the algorithms can be emulated and the trigger decision simulated and compared to the actual hardware result.

The readout proceeds to the data acquisition system via FELIX after receiving a L0A signal. The system is equipped with several components that support the core part of the system. Each shelf, except the gFEX shelf, is equipped with two HUB modules that carry ROD modules to perform the event readout. The connectivity to the processing modules
is implemented through backplane connections. The gFEX module is directly read out via FELIX. The hardware and firmware stays untouched and will be used as it is used during Phase-I.

## 7.4 Firmware

### 7.4.1 Algorithmic Firmware

The general goal is to keep the firmware stable over long periods and we do not expect to update the algorithms except for bug fixing or in the case of a very substantial performance improvement. The Phase-II upgrade opens the possibility to upgrade also the algorithmic firmware based on the experience from Run 3. The relaxed latency budget allows to increase the available processing time from 125 ns to 500 ns (see Section 5.2.8).

### 7.4.2 Infrastructure Firmware

There is no major upgrade of the infrastructure firmware foreseen except for small adaptations due to the change of the interfaces to FELIX and the DCS. Depending on the mapping details of the input signals, minor changes of the input firmware of the FEX systems might be necessary. After the Phase-II upgrade also the bandwidth limits to the subsequent system (Global Trigger) are not anymore as stringent as in Run 3. This opens the possibility to send more information about the TOBs. This also necessitates a change of the output data formats.

## 7.5 R & D Programme

A large part of the Level-0 Calorimeter Trigger will consist of legacy components which are constructed in the framework of the Phase-I upgrade. The following components need to be modified or newly developed.

* Hardware

- The fFEX module needs to be designed and constructed.

- The FOX needs to be modified.

- The eFEX and jFEX output signals to L1Topo need to be split.

* Firmware

- The algorithms for the fFEX need to be developed.

- Possible improvements to the algorithms of the legacy components need to be updated.
- Anticipated modifications to the readout FW need to be implemented.

- Anticipated modification to the DCS FW need to be implemented.

* Software

The configuration and control software which supports the different components needs to be updated to account for the hardware and firmware changes.

## 7.6 Commissioning

The Level-0 Calorimeter Trigger (except the fFEX) should be fully operational at the beginning of Phase-II since it consists of the Phase-I legacy system. The functional commissioning of the new interfaces to the calorimeters (LASP and TDAQi) as well as to FELIX and DCS can be finalised well in advance of data taking, since the signals are all digital. The calibration of the calorimeter inputs can be performed using well established procedures using test pulses. The fFEX needs time for commissioning although a large part of its functionality can be tested before first collisions since it is a fully digital system. In order to support a managed transition of the tasks from L1Topo to Global Trigger we plan to operate L1Topo during the initial phase of Run 4. Once the Global Trigger is fully functional and has taken over all the L1Topo tasks in a reliably manner we will decommission L1Topo.

## References

[7.1] ATLAS Collaboration, Technical Design Report for the Phase-I Upgrade of the ATLAS TDAQ System, Tech. Rep. CERN-LHCC-2013-018. ATLAS-TDR-023, CERN, Geneva, Sep, 2013. https://cds.cern.ch/record/1602235.

[7.2] ATLAS Liquid Argon Calorimeter Group, ATLAS Liquid Argon Calorimeter Technical Design Report: Trigger Electronics for the LHC Phase-I Upgrade, Tech. Rep. CERN-LHCC-2013-017, CERN, Geneva, (in preparation).
https://twiki.cern.ch/twiki/bin/view/LAr/LArPhaseITDR.

[7.3] ATLAS Collaboration, Technical Design Report for the Phase-II Upgrade of the ATLAS LAr Calorimeter, Tech. Rep. CERN-LHCC-2017-018. ATLAS-TDR-027, CERN, Geneva, Sep, 2017. https://cds.cern.ch/record/2285582.

[7.4] ATLAS Collaboration, Technical Design Report for the Phase-II Upgrade of the ATLAS Tile Calorimeter, Tech. Rep. CERN-LHCC-2017-019; ATLAS-TDR-028, CERN, Geneva, Sep, 2017. http://cds.cern.ch/record/2285583.
# 8 Level-0 Muon Trigger

## 8.1 Introduction

The current Level-1 Muon Trigger System will be upgraded to form the Level-0 Muon Trigger System for HL-LHC. The Level-0 muon trigger will be based on the data of the upgraded muon spectrometer and the Tile calorimeter. The muon spectrometer upgrade is described in another TDR [8.1]. Figure 8.1 shows a cross-sectional view of the upgraded muon spectrometer. It consists of RPC ($0 < |η| < 1.05$), TGC ($1.05 < |η| < 2.4$), NSW ($1.3 < |η| < 2.7$), and sMDT/MDT ($|η| < 2.7$). The NSW consists of sTGC and MM [8.2]. The sMDT is implied by the word MDT throughout the chapter. The detectors constitute three groups ('stations') in both the barrel and the endcap: inner, middle, and outer stations in $|η| < 1.05$ and $1.3 < |η| < 2.7$ and inner, extra, and middle stations in $1.05 < |η| < 1.3$.

This chapter describes the design of the Level-0 Muon Trigger System, including the hardware and the trigger logic. Section 8.2 shows an overview of the current Level-1 Muon Trigger System and the Phase-I upgrade as well as the limitations. Section 8.3 gives an overview of the Phase-II upgrade. Sections 8.4, 8.5, and 8.6 describe the components of the Level-0 Muon Trigger System, the Sector Logic, the NSW Trigger Processor, and the MDT Trigger Processor, respectively. Section 8.7 summarises the latency estimates. Section 8.8 provides the R&D items.

## 8.2 Overview of the Current System and the Limitations

The original Level-1 muon trigger at the ATLAS experiment is based on the hit data from RPC in the barrel region ($|η| < 1.05$) and TGC in the endcap region ($1.05 < |η| < 2.4$) [8.3]. The muon track candidates are identified by simple coincidence logic in the on-detector boards. The transverse momentum is evaluated by look-up tables in the off-detector boards. At the beginning of Run 2, the signals from TGCs in the endcap inner station ($1.05 < |η| < 1.9$) were introduced in the coincidence to reduce the rate of triggers caused by the particles not directly from the interaction point ('fake triggers'). The coverage of the TGCs in the endcap inner station is about half in $1.05 < |η| < 1.3$, and thus the energy deposits in the outermost cells of the Tile calorimeter are being incorporated during Run 2 to reduce the fake triggers [8.4]. The detectors in the endcap inner station in $1.3 < |η| < 2.7$ will be
<figure><img src="image_122.png" /><figcaption>Figure 8.1: Cross-sectional view of the Phase-II ATLAS muon spectrometer layout, showing a so-called small sector, one of the azimuthal sectors that contain the barrel toroid coils. The drawing shows the new detectors to be added in the Phase-II upgrade (red text: BI RPC, sMDT, high-$\eta$ tagger), those to be installed during Long Shutdown 2 (green text: Micromegas and sTGC in the NSW and BIS78 RPC and sMDT), and those that will remain unchanged from the Run 1 layout (black text). In the so-called large sectors, which are the sectors in-between the barrel toroid coils, the TGCs and MDT chambers in the endcap inner station covers the $\eta-\phi$ range of the BIS78.</figcaption></figure>

replaced by NSW during Long Shutdown 2, which consists of sTGC and MM, for further suppression of the fake triggers [8.2].

The main reasons to upgrade the current Level-1 Muon Trigger System are the limited available latency and rate and the relatively low efficiency and momentum resolution. It is impossible for the original RPC and TGC electronics to cope with the latencies and the rates of the trigger and readout scheme for HL-LHC. The original systems of RPC and TGC are designed for maximum latencies of 6.4 µs and 3.2 µs, respectively, and for a maximum rate of 100 kHz. The limitations arise from the depth of the readout buffer to store the hit data before the arrival of the trigger accept signals and also from the readout bandwidth. The NSW was designed for a 60 µs latency and a 1 MHz rate to be compatible with the Phase-II system.

The current Level-1 muon trigger has limitations on the performance. The product of the acceptance and the efficiency for the barrel region is about 70% (Fig. 8.2). This is due to limited coverage of RPC in the barrel middle station, which is originating from the sup-
port structures of the toroid magnets [8.5]. The product for the endcap region is about 90%, which is due to the accumulation of minor effects including a relatively tight coincidence criterion. Additionally, there is a substantial contribution in the trigger rates from the muons with the transverse momentum $p_T$ smaller than the threshold (Fig. 8.3). This is due to a rapid increase of the production cross section of muons for lower $p_T$ and the limited $p_T$ resolution of the Level-1 muon trigger.

<figure><img src="image_123.png" /><figcaption>Figure 8.2: Product of the acceptance and the efficiency for single muon as a function of transverse momentum $p_T$ evaluated by an offline analysis. The plots are obtained from Run 2 data. The left and right plots are for the barrel and endcap regions, respectively. The circles show the values for the Level-1 muon trigger with 20 GeV threshold. The triangles show the values for the high-level trigger targeting isolated muons with 26 GeV threshold and non-isolated muons with 50 GeV threshold. The squares show the product of them. The values of the Level-1 muon trigger for $p_T$ higher than the threshold is about 70% in the barrel region.</figcaption></figure>

## 8.3 Overview of the Upgrade

The upgrade of the Level-0 Muon Trigger System is designed to increase the latencies and the rates of the trigger and readout system and to improve the trigger efficiency. The detector and on-detector electronics upgrades are described in Ref. [8.1]. This TDR focuses on the off-detector electronics upgrades.

Figure 8.4 shows a simplified block diagram of the proposed system. It consists of the Barrel Sector Logic, the Endcap Sector Logic, the NSW Trigger Processor, and the MDT Trigger Processor. The Sector Logic and the NSW Trigger Processor installed by the end of Long Shutdown 2 will be replaced, while the MDT Trigger Processor will be newly installed. The Barrel Sector Logic receives the hits and the energy flags from RPC and Tile calorimeter, respectively. The Endcap Sector Logic receives the hits from TGC and RPC in $1.05 < |η| < 1.3$. It also receives the track segments and the energy flags from NSW and Tile calorimeter, respectively. Since the track-segment reconstruction with NSW hits
<figure><img src="image_124.png" /><figcaption>Figure 8.3: Distribution of the transverse momentum $p_T$ evaluated by an offline analysis for the muon candidates selected by the current Level-1 muon trigger with 20 GeV threshold. The distribution is obtained from Run 2 data. The requirement based on NSW, which will be integrated after Run 2, has been simulated and applied based on the signals from the current detectors in the endcap inner station. Both barrel and endcap regions are included. The entries are dominated (~ 85%) by the muon candidates with $p_T$ smaller than the threshold.</figcaption></figure>

requires relatively large amount of resources, the hardware will be separate from the Sector Logic. The Sector Logic provides track candidates, and sends the results to the MDT Trigger Processors. The MDT Trigger Processor filter the track candidates with a better $p_T$ determination, and sends the results to the Sector Logic. The Sector Logic sends the track candidates to Level-0 MUCTPI.

### 8.3.1 Extension of the Latency and the Rate

To increase the latencies and the rates of the trigger and readout system, all the RPC and TGC electronics boards except for the amplifier-shaper-discriminator boards will require the replacements [8.1]. In the new design, all hit data will be transferred from the on-detector boards to the off-detector boards over high-speed optical links. The limitations by the bandwidth between the on-detector and off-detector boards will be eliminated. No trigger logic will be implemented in the on-detector boards. The trigger logic will be fully implemented in the Sector Logic, providing the flexibility of modifying and tuning the logic. The readout buffer will be implemented in the off-detector boards. It is designed to have a depth sufficient for the maximum latency of the Level-0 trigger for HL-LHC.

The NSW on and off-detector electronics delivered for Phase-I will remain for Phase-II. The main update foreseen for the system is for additional FELIX boxes to manage the additional data from the 1 MHz trigger rate [8.2]. The upgrade of the NSW Trigger Processor
<figure><img src="image_125.png" /></figure>

<figure><img src="image_126.png" /><figcaption>Figure 8.4: A simplified block diagram of the proposed Level-0 Muon Trigger System for HL-LHC. The top and bottom parts show the diagrams for the barrel and the endcap, respectively.</figcaption></figure>

(see Section 8.5) is proposed to improve the robustness and redundancy of the trigger by performing a combined track segment reconstruction by sTGC and MM.

8.3.2 Improvement of the Trigger Performance

Improvements in trigger performance will be achieved by increasing the detector accept-
ance, the trigger logic, and the momentum resolution. The upgrade of the muon system
towards Phase-II includes the addition of RPCs in the barrel inner station as described in
Ref. [8.1]. By allowing for coincidences of hits in the RPCs in the inner and outer stations,
the acceptance gaps in the barrel trigger system which are caused by the non-instrumented
regions in the barrel middle station due to the presence of the structures of the barrel toroid
coils will be closed. The expected value of the product of the acceptance and the efficiency
of the muon trigger in the barrel region is more than 90% depending on the coincidence
criteria. The Barrel Sector Logic in the new design includes the coincidence of the addi-
tional RPCs. The results of the performance studies are described in the former parts of Section 8.4.1. The Barrel Sector Logic also includes the coincidence of the Tile calorimeter for a trigger rate suppression.

The Endcap Sector Logic in the new design is based on a loosened TGC coincidence for an improvement of the efficiency by a few per cent. The Endcap Sector Logic reconstructs the track segments with TGC hits in the endcap middle station with a 4 mrad resolution. The NSW Trigger Processors reconstruct the track segments in the endcap inner station with a 1 mrad resolution [8.2]. The deflection angle between the TGC and NSW segments makes it possible to reduce the trigger rate in $1.3 < |η| < 2.4$, while retaining the efficiency for the muons with the transverse momentum higher than the threshold. The fake triggers in $1.05 < |η| < 1.3$ are suppressed by the coincidence between TGCs, RPCs in the BIS78 region [8.1], and the Tile calorimeter. The results of the performance studies of the trigger efficiency and rate are described in the latter parts of Section 8.4.1. The performance of the segment reconstruction based on NSW hits is described separately in Section 8.5.2.

In order to improve the $p_T$ resolution at the Level-0 muon trigger, it is proposed to include the MDT chambers, which are used for the high-level trigger and the precision tracking in the current system, in the Level-0 Muon Trigger System for HL-LHC. In the new design, the data of all MDT hits are transferred to the off-detector boards over high-speed optical links [8.1]. The data include the hit time measurements. The MDT trigger processing is only applied when muon track candidates are provided by the Sector Logic. The MDT drift time is measured with the time origin determined from the bunch crossing identified by RPCs and TGCs. The MDT Trigger Processor reconstructs the track segments and evaluates $p_T$ from the relation of the angles and the positions of the segments in different stations. The $p_T$ evaluated by MDT makes it possible to reduce the trigger rate. The results of the performance studies are described in Section 8.6.2.

## 8.4 Sector Logic

The trigger logic is provided for each sector defined by the boundaries of combinations of RPC and TGC chambers [8.3], and hence is called the Sector Logic. The Sector Logic is implemented in FPGAs on the off-detector boards. This section introduces the logic scheme, the expected performance, the hardware and firmware design, and the interfaces of the Sector Logic upgrade.
## 8.4.1 Trigger Scheme and Performance

### Barrel Trigger Scheme

The RPC trigger logic in Phase-II will use nine measurement planes, provided by four groups of RPC chambers: three planes (RPC0) on the barrel inner (BI) station, two planes (RPC1) in the inner part of the barrel middle (BM) station, two planes (RPC2) in the outer part of the BM station, and two planes (RPC3) on the barrel outer (BO) station. Figure 8.5 shows an example of a so-called “small” barrel sector, showing the positions of RPC0, RPC1, RPC2, and RPC3 chambers. The acceptance holes in the RPC1 and RPC2 chambers, caused by the magnet coils and their supports, are clearly visible.

<figure><img src="image_127.png" /><figcaption>Figure 8.5: Sketch of a transverse section of the barrel region. The four groups of RPC chambers (red) are shown as well as the MDT chambers (green and cyan) on the BI, BM, and BO stations. The three dashed lines represent muon trajectories traversing four, two, and three RPC chambers. The drawing represents one of the sectors that contain a barrel toroid coil and its support structures which cause the holes in the chamber coverage of the BM station.</figcaption></figure>

To take advantage of the redundancy of detector planes, a trigger algorithm that does not make use of a fixed pivot plane (as in present ATLAS scheme) has been developed, which selects patterns of hits with a minimal deviation from a straight line passing from the nominal interaction point, both in $\eta$ and in $\phi$. This makes it possible to define different trigger coincidence logic schemes without the constraint of requiring at least one hit on a fixed
pivot plane. The following logic schemes have been considered, based on different requirements on the four groups of RPC chambers which are explained in the following and summarised symbolically in Table 8.1:

* **3/3 chambers.** Hits in at least three out of four planes of the RPC1+RPC2 chambers and in at least one out of two planes of RPC3. This is equivalent to the present high-$p_T$ trigger.

* **3/4 chambers.** The previous requirement in logical OR with the requirement of hits in at least two planes out of three in RPC0 and in at least three planes out of six in RPC1+RPC2+RPC3. In this way, all combinations of three-chamber coincidences (satisfying the above hit requirements) are accepted.

* **3/4 chambers + BI-BO.** The previous requirement in logical OR with the requirement of at least two hits in RPC0 and at least one hit in RPC3. This enhances the trigger coverage in the regions where no BM RPCs are installed due to the mechanical support structure of the toroid coils.

<table><caption>Table 8.1: Detail of the hit requirements used in different RPC triggers. The cell with “x out of y” indicates the requirement of at least x planes out of y planes. The cell with “—” indicates no use of the layer. The requirements in a row is combined with logical AND. For each set of “3/4 chambers” and “3/4 chambers + BI-BO”, the requirements in different columns are combined with logical OR.</caption><thead><tr><th>Requirement</th><th>RPC0</th><th>RPC1</th><th>RPC2</th><th>RPC3</th></tr></thead><tbody><tr><td>3/3 chambers</td><td>—</td><td>3 out of 4</td><td>1 out of 2</td><td></td></tr><tr><td rowspan="2">3/4 chambers</td><td>—</td><td>3 out of 4</td><td>1 out of 2</td><td></td></tr><tr><td>2 out of 3</td><td></td><td>3 out of 6</td><td></td></tr><tr><td rowspan="3">3/4 chambers + BI-BO</td><td>—</td><td>3 out of 4</td><td>1 out of 2</td><td></td></tr><tr><td>2 out of 3</td><td></td><td>3 out of 6</td><td></td></tr><tr><td>2 out of 3</td><td>—</td><td>—</td><td>1 out of 2</td></tr></tbody></table>

The baseline of the RPC trigger uses the “3/4 chambers + BI-BO” scheme for all $p_T$ thresholds. The BI-BO coincidence is expected to be prone to accidental coincidences of uncorrelated background hits that are negligible in three-chamber coincidences. There is an option to apply the BI-BO coincidence only to the regions with acceptance holes in the “3/4 chambers” scheme (approximately 15% of the barrel) to control the trigger rate. The “3/4 chambers” and “3/3 chambers” schemes are other options to further control the trigger rate. For the “3/4 chambers” scheme, an additional requirement of at least one hit on the BO station can be included. The Tile calorimeter energy flags are used to suppress the accidental coincidences.
Barrel Trigger Acceptance and Efficiency

The performance of the RPC-based trigger was studied using simulated data with a sim-
plified description of the BI RPCs. In the simplified description, the geometrical coverage
of the BI RPC chambers was included according to the preliminary layout presented in
Ref. [8.1]. A dead region of 15 mm at the borders of each RPC chambers is included in
the simulation. The presence of these cut-outs reduces the geometrical acceptance of the BI
station, calculated with respect to reconstructed muons with |η| < 1.05, from 95% to 91%.

A Phase-II RPC-based trigger algorithm was implemented in the simulation. The algorithm searches for sequences of hits in different RPC planes based on pre-defined coincidence windows that define the maximum distance in η or φ to associate hits belonging to the same muon candidate. Not only the hits of the bending plane (η) but also the hits of the perpendicular plane (φ) are used to suppress the accidental coincidence. The requirement that two hits are inside a coincidence window is applied to each pair of hits in consecutive planes, as illustrated in Fig. 8.6. The centre of the coincidence window on the outer layer is obtained assuming a straight line passing from the nominal interaction point and the inner hit. This algorithm effectively measures the muon momentum from the deflection of the trajectory with respect to a straight line from the interaction point. Therefore the momentum resolution that can be obtained with this approach is limited by the spread of the interaction point along the beam line rather than the spatial hit resolution.

In the simulation a luminous region with a Gaussian distribution around the nominal in-
teraction point with σ = 5 cm was used. Only a simple digital readout was simulated, and
neither strip clustering nor any use of charge information was implemented. In addition
to the spatial coincidence, a timing requirement has been applied, by considering only hits
with |t<sub>hit</sub> − t<sub>0</sub>| < 6.25 ns. Here, t<sub>hit</sub> is the time of hit detection and t<sub>0</sub> is the time of an infin-
ite momentum muon which hits the centre of the strip and was generated at the nominal
interaction point at the nominal bunch crossing time.

The acceptance of the three coincidence logic schemes with respect to reconstructed muon tracks is shown in Fig. 8.7. The acceptance limitation of the “3/3 chambers” trigger, corresponding mostly to the ATLAS support structures at −2.2 < φ < −1 and to the supports of the toroid magnets (at |η| ≃ 0.4, 0.75, 1) are largely recovered by the “3/4 chambers” trigger which includes the new BI RPC chambers. The residual acceptance holes are recovered with the “3/4 chambers + BI-BO” trigger, with the exception of the region at |η| ≃ 0 where the acceptance is limited by the calorimeter services.

To study the robustness of the trigger against possible efficiency reductions due to aging of
the old RPCs in the BM and BO stations, the performance of different assumptions on the
old RPC detector efficiency has been studied with a simulation of single muons generated
with a fixed p<sub>T</sub> of 25 GeV and uniform distributions in the η and φ plane. Simulations were
performed with 100%, 90%, and 80% hit efficiency for the BM and BO RPCs and with the
“worst case scenario”. The worst case scenario corresponds to a reduction of high voltage
<figure><img src="image_128.png" /><figcaption>Figure 8.6: Illustration of the implemented RPC-based trigger algorithm. Hits are linked between consecutive planes based on pre-defined coincidence windows centred on a straight-line extrapolation from the nominal interaction point. Patterns of linked hits that satisfy quality requirements are selected as muon track candidates. The width of the coincidence windows defines the p$_{T}$ threshold.</figcaption></figure>

of old RPCs such that the expected current on the RPC chambers is always below the safe operation limit, estimated including a safety factor of two on the currents. In addition to the inefficiency from reduced HV, a 95% hit efficiency as measured in Run 2 was applied. In this scenario the RPC hit efficiency decreases with $|η|$ from approximately 90% at $η \simeq 0$ to 56%-75% at $η \simeq 1$, depending on the chamber type. Table 8.2 shows the product of the acceptance and the efficiency for the difference assumptions. Figure 8.8 shows the product of the acceptance and the efficiency for the worst case scenario. Adding the new BI RPC station, the dependency of the trigger efficiency on the hit efficiency of the current RPCs is strongly reduced.

## Barrel Momentum Selection and Trigger Rate

The performance of the proposed RPC trigger was studied for transverse momentum thresholds of $p_T > 20$ GeV, 15 GeV, 10 GeV, and 5 GeV. The dependencies of trigger efficiency on the muon $p_T$ are shown in Fig. 8.9. For the 20 GeV threshold, the plots for different coincidence schemes are shown. Some residual efficiency below 10 GeV is related to the class of
<figure><img src="image_129.png" /><figcaption>Figure 8.7: Geometrical acceptance of the Level-0 barrel muon trigger with respect to reconstructed muons with $p_T = 25$ GeV in the η-φ plane. The plots are obtained by assuming 100% hit efficiency and no pile-up. Figures (a), (b), and (c) show the acceptance for the different trigger coincidence logic “3/3 chambers”, “3/4 chambers”, and “3/4 chambers + BI-BO”, respectively. The white areas correspond to zero acceptance.</figcaption></figure>

<table><caption>Table 8.2: Acceptance × efficiency in per cent for the RPC trigger under different hypotheses on the hit efficiency of the present RPC detectors. The row with 100% “old” RPC efficiency gives the geometrical acceptance of the trigger requirements. The “worst case” corresponds to a scenario in which the RPC HV is reduced depending on the expected chamber rate to maintain the currents within a safe limit.</caption><thead><tr><th rowspan="2">"Old" RPC efficiency (%)</th><th colspan="3">Trigger acceptance × efficiency (%)</th></tr><tr><th>3/3 chambers</th><th>3/4 chambers</th><th>3/4 chambers + BI-BO</th></tr></thead><tbody><tr><td>100</td><td>78</td><td>91</td><td>96</td></tr><tr><td>90</td><td>73</td><td>90</td><td>95</td></tr><tr><td>80</td><td>62</td><td>87</td><td>93</td></tr><tr><td>Worst case</td><td>63</td><td>85</td><td>92</td></tr></tbody></table>
<figure><img src="image_130.png" /><figcaption>Figure 8.8: Acceptance × efficiency of the RPC trigger with respect to reconstructed muons as a function of η for the “worst case” hit efficiency scenario in which the RPC HV is reduced to maintain the chamber currents within a safe limit with a safety factor of two. The red histograms show the efficiency of the existing “3/3 chambers” trigger, the blue histograms the “3/4 chambers” trigger, and the green histograms the “3/4 chambers + BI-BO” trigger. The values are evaluated by the Monte-Carlo (MC) samples of muons with a fixed p$_{T}$ of 25 GeV and no pile-up involved.</figcaption></figure>

muons that leave hits only in BI and BM chambers, for which the resolution is worse than for muons with hits in the BO chambers.

<figure><img src="image_131.png" /><figcaption>Figure 8.9: Efficiency curves as a function of p$_{T}$ for RPC Level-0 trigger. Figure (a) shows the result for different coincidence schemes for a p$_{T}$ threshold of 20 GeV. Figure (b) shows the result for different p$_{T}$ thresholds for the “3/4 chambers + BI-BO” scheme. The figures assume 100% RPC hit efficiency and no pile-up.</figcaption></figure>
The rates of single muon selection based on RPC have been estimated using a simulation of minimum bias events generated with PYTHIA8 and passed through the standard GEANT4 ATLAS simulation, including the long-lifetime background component originating from slow neutrons (cavern background). Additional corrections have been applied by scaling the rate of muons from heavy-flavour decays in the simulation to agree with ATLAS measurements [8.6] and FONLL calculations [8.7] and by scaling the RPC hit rate obtained from the simulation in order to reproduce rate measurements. Figure 8.10 shows the estimated rate depending on the luminosity for a $p_T$ threshold of 20 GeV. The rate of “3/3 chambers” and “3/4 chambers” triggers increase linearly with luminosity as they are mainly generated by real muons from the decay of pions, kaons, and heavy flavours that scale linearly with the number of $pp$ interactions. The BI-BO trigger instead has an additional quadratic dependence on pile-up due to accidental coincidences of background hits. Figure 8.11 shows the estimated rate depending on the $p_T$ threshold for the “3/4 chambers + BI-BO” trigger. The estimated trigger rates for different $p_T$ thresholds and different schemes are summarised in Table 8.3.

<figure><img src="image_132.png" /><figcaption>Figure 8.10: Estimated rate of Level-0 single muon selection based on RPC depending on the luminosity. The result is shown for a $p_T$ threshold of 20 GeV and for different coincidence schemes.</figcaption></figure>

For the subset of muons with hits in the three stations of chambers (BI, BM, and BO), which correspond to an acceptance of approximately 80%, it is possible to obtain a $p_T$ measurement based on three points. This measurement is independent of the spread of the interaction point and therefore provides an improved $p_T$ resolution.

The effect of random coincidences on BI-BO triggers can be reduced by applying tighter timing cuts. The intrinsic time resolution of the RPC detectors is 1 ns for BM and BO and
<figure><img src="image_133.png" /><figcaption>Figure 8.11: Estimated rate of Level-0 single muon selection based on RPC depending on the $p_T$ threshold. The result is shown for a coincidence scheme of "3/4 chambers + BI-BO".</figcaption></figure>

<table><caption>Table 8.3: Estimated rate of Level-0 single muon selection based on RPC for different $p_T$ thresholds and different schemes at a luminosity of $7.5 \times 10^{34} \text{ cm}^{-2}\text{s}^{-1}$. The values are shown in units of kHz. These rates are reduced by the MDT trigger before the muon track candidates are sent to the Level-0 MUCTPI.</caption><thead><tr><th></th><th>$p_T$ > 20 GeV</th><th>$p_T$ > 15 GeV</th><th>$p_T$ > 10 GeV</th><th>$p_T$ > 5 GeV</th></tr></thead><tbody><tr><td>3/4 chambers + BI-BO</td><td>84 ± 25</td><td>142 ± 40</td><td>328 ± 80</td><td>1255 ± 322</td></tr><tr><td>3/4 chambers</td><td>32 ± 7</td><td>73 ± 11</td><td>187 ± 16</td><td>718 ± 31</td></tr><tr><td>3/4 chambers (with BO)</td><td>20 ± 6</td><td>52 ± 9</td><td>146 ± 14</td><td>516 ± 26</td></tr></tbody></table>

0.4 ns for BI. In the standard ATLAS offline reconstruction, a resolution of less than 2 ns is routinely achieved for the BM and BO chambers after offline calibration and corrections for the signal propagation along the strips. The current experience with the ATLAS barrel trigger shows that a simple online calibration allows the use of a timing window $|t_{hit} - t_0| < 6.25$ ns. A tighter window would require signal propagation corrections and finer calibrations at the Level-0 trigger.

## Endcap Trigger Scheme

The availability of the individual TGC hits in the Sector Logic makes it possible to reconstruct track segments in the endcap middle station with an average angular resolution of
4 mrad (Fig. 8.12). The track segments are reconstructed with the pattern matching algorithm, where the TGC hits are compared with predefined hit patterns. Each predefined hit pattern has associated angle and position of a track segment.

<figure><img src="image_134.png" /><figcaption>Figure 8.12: Distributions of the difference of the polar angle (Δθ) between the TGC track segment reconstructed by the pattern matching for the trigger threshold of 20 GeV and the track segment reconstructed by the ATLAS full offline analysis. MC sample is used, where a muon is produced with random p$_{T}$ in a range 1–100 GeV. No pile-up is involved. The red, blue, and green histograms are for the TGC track segments reconstructed with seven, six, and five hits, respectively, over the seven layers. The black histogram shows the sum of them.</figcaption></figure>

In the original Endcap Sector Logic, at least two (one) hits are required in the inner three (two) layers and at least three hits are required in the outer four layers for wires (strips) for the TGC hits in the endcap middle station. In the Endcap Sector Logic for HL-LHC, a looser coincidence of at least five (four) hits in seven (six) layers for wires (strips) will be used. The product of the acceptance and the efficiency is expected to be improved to more than 90%, a few per cent higher than the original system.

The muon track candidates are provided by the combination of the TGC track segments in the endcap middle station and the information from other detectors. Figure 8.13 shows the concept of the combination. The transverse momentum of a muon candidate in 1.05 < |η| < 1.3 is determined from a combination of the position and the angle of the TGC track segment and the positions of the hits in the TGCs in the endcap inner station, the RPCs in the BIS78 region, and the Tile calorimeter. The transverse momentum of a muon candidate in 1.3 < |η| < 2.4 is determined from the polar angle difference between the TGC track segment and the track segment reconstructed in NSW.

The baseline algorithm introduced above covers the region $1.05 < |\eta| < 2.4$. Although the number of TGC layers in $2.4 < |\eta| < 2.7$ is limited (three wire layers and two strip layers), the coverage could, in principle, be extended to the region $1.05 < |\eta| < 2.7$ by a coincidence between NSW track segments and the hits in the existing TGC layers.
<figure><img src="image_135.png" /><figcaption>Figure 8.13: Concept of the Endcap Sector Logic. Track segment is reconstructed by the TGC hits in the endcap middle (EM) station. It is combined with the position of the TGC hits in the endcap inner (EI) station, the position of the Tile calorimeter hit, and the track segment reconstructed by NSW, depending on the region. In this diagram, a detector slice in a so-called large sector is shown. In the so-called small sectors, the RPCs in the BIS78 region replaces the TGC hits in the endcap inner (EI) station.</figcaption></figure>

## Endcap Trigger Efficiency

The efficiency of the Level-0 muon trigger based on the loosened TGC coincidence for $1.05 < |η| < 2.4$ has been studied with MC samples. A muon is produced in an event randomly in $η, φ$, and $p_T$. A track segment is reconstructed by a minimum $\chi^2$ fit to the TGC hits which satisfy the coincidence requirement. The efficiency for $p_T$ thresholds of 5, 10, 15, and 20 GeV have been studied. Requirements are applied for the polar angle of the segment direction depending on the $p_T$ thresholds. Figure 8.14 shows the result of the efficiency estimation. The obtained efficiency in the plateau region is a few per cent higher than the original endcap system (see Fig. 8.2).

The efficiency has also been studied with the TGC segment reconstruction based on the pattern matching. The study focuses on the region covered by both TGC and NSW. A requirement on the polar angle difference between the TGC and NSW segments is applied depending on the $p_T$ thresholds. Figure 8.15 shows an estimate based on the single muon MC samples, described in the previous paragraph. The obtained efficiency in the plateau region is similar to the one obtained for the minimum $\chi^2$ method (see Fig. 8.14). The distribution around the threshold is steeper than the original system, indicating a better transverse momentum resolution.
<figure><img src="image_136.png" /><figcaption>Figure 8.14: Expected efficiency for the Level-0 muon trigger based on the loosened TGC coincidence for $1.05 < |η| < 2.4$. The values are estimated with a single muon MC sample, where a muon is produced for an event randomly in η, φ, and $p_T$. No pile-up is involved. The red, blue, green, and magenta plots are for $p_T$ thresholds of 20, 15, 10, and 5 GeV, respectively. The black plots show the efficiency for offline track reconstruction.</figcaption></figure>

<figure><img src="image_137.png" /><figcaption>Figure 8.15: (a) Expected efficiency for the muon trigger based on TGC and NSW in the region $1.3 < |η| < 2.4$ for a $p_T$ threshold of 20 GeV. The plots for the Run 1 scheme and a HL-LHC scheme are shown. In the HL-LHC scheme, a looser coincidence, five (four) hits over seven (six) layers for wires (strips) is used. The HL-LHC scheme provides a higher efficiency in the plateau region with better rejection of low $p_T$ muons. (b) Expected efficiency for the muon trigger based on a HL-LHC scheme with TGC and NSW for $p_T$ thresholds of 10, 15, and 20 GeV. No pile-up is involved in the MC simulation.</figcaption></figure>
### Endcap Trigger Rate

The Level-0 muon trigger rate for the endcap has been studied with the data samples taken in 2016. A zero-bias trigger is required [8.8]. The events have been overlaid to provide an expected environment at HL-LHC for the number of interactions per bunch crossing up to around 200 (Fig. 8.16). The distributions are shown for $p_T$ thresholds of 5, 10, 15, and 20 GeV. The efficiency in the plateau region is obtained to be 92%.

<figure><img src="image_138.png" /><figcaption>Figure 8.16: (a) Distributions of the number of interactions per bunch crossing ($\mu$) for the overlaid data samples. The overlay was done with the target average $\mu$ around 80, 120, 160, and 200. (b) Distributions of the number of TGC hits for the overlaid data samples. The number depends on the values of $\mu$.</figcaption></figure>

Figure 8.17 shows the result of the estimation of the Level-0 single-muon trigger for $1.05 < |\eta| < 2.4$ for $p_T$ thresholds of 15 GeV and 20 GeV. Figure 8.18 shows the estimated rate depending on the $p_T$ thresholds. Expected improvements, the looser TGC coincidence and the requirement based on the TGC and NSW segments, are both included. The TGC coincidence requires at least five (four) hits in seven (six) layers for wires (strips). The TGC segments are reconstructed by a minimum $\chi^2$ fit on the TGC hits, and requirement is applied for the angles. The NSW segments are emulated by the offline MDT and Cathode Strip Chamber (CSC) segments in $1.3 < |\eta| < 2.4$, and requirement is applied for the deflection angle between the TGC and NSW segments. The coincidence with the Tile calorimeter is required for $1.05 < |\eta| < 1.3$. A nonlinear relation between the trigger rate and the luminosity is obtained, which is related with a larger number of TGC hits for higher luminosity (Fig. 8.16). A tuning of the trigger algorithm is ongoing to remove or suppress the nonlinearity, while the estimated rate is already smaller in the total Level-0 rate of 1 MHz.
<figure><img src="image_139.png" /><figcaption>Figure 8.17: The estimated rate of the Level-0 single-muon trigger based on TGC, Tile calorimeter, and NSW for $1.05 < |η| < 2.4$. The curves show the result of the fit by a second-order polynomial. The luminosity has been extracted from the number of interactions per bunch crossing for the HL-LHC nominal colliding bunches.</figcaption></figure>

<figure><img src="image_140.png" /><figcaption>Figure 8.18: The estimated rate of the Level-0 single-muon trigger based on TGC, Tile calorimeter, and NSW for $1.05 < |η| < 2.4$. The values are evaluated from the overlaid data samples for a luminosity of $7.5 \times 10^{34} \text{ cm}^{-2}\text{s}^{-1}$. The values are estimated for $p_T$ thresholds of 5, 10, 15, and 20 GeV.</figcaption></figure>
Trigger for Exotic Signatures

Several new physics models that extend the Standard Model (SM) predict exotic signa-
tures such as the Long-Lived Particle (LLP) [8.9]. The sensitivity of the searches could
be improved by specific trigger algorithms. An example is the algorithm with loosened
interaction-point pointing constraint. The Sector Logic is designed not to kill the exotic
signatures.

8.4.2 Hardware Design

The Sector Logic is implemented in the off-detector boards housed in the ATCA shelves. The readout of the RPC and TGC hit signals and of the Level-0 trigger information is implemented in the same boards. Additionally, the control of the RPC and TGC on-detector boards is based on the same boards. The barrel and endcap systems are based on 2 × 16 and 2 × 24 boards (Fig. 8.19), where the number “2” represents the positive and negative sides of the beam axis.

<figure><img src="image_141.png" /></figure>

Figure 8.19: Structure of the detector and the coverage of the off-detector boards where the Sector Logic is implemented. The left and right figures are for the barrel and the endcap, respectively. The outermost layer of TGC is shown for the endcap. The regions surrounded by the red lines show the coverage of the boards. For the barrel, the coverage has two types, which is indicated by the red lines. For the endcap, the coverage for four boards are indicated by the red lines. The segmentation of the MDT Trigger Processor (green lines) is different, and a Sector Logic board is connected to three MDT Trigger Processor boards at maximum.

The requirement for the off-detector boards is similar between the barrel and the endcap.
A common board design is proposed to minimise the resources required for the develop-
ment. Figure 8.20 shows a block diagram. Each board has one FPGA, in which the Sector
Logic and the readout logic are implemented. The Xilinx Virtex UltraScale or UltraScale+ family is proposed for the implementation. For the barrel, the resource of the Sector Logic has been estimated with an extrapolation from the current coincidence matrix ASIC implementation. The implementation of the logic in the proposed FPGA family seems feasible. For the endcap, the resource estimation for the Sector Logic is an R&D item. Given the total number of TGC channels similar to RPC, the implementation in the proposed FPGA family is considered to be feasible. For the cost estimation, the FPGA models XCVU13P and XCVU190 are assumed for the barrel and the endcap.

The FPGA on the off-detector board is required to have 104 pairs of optical receivers and transmitters. Most of the receivers and transmitters are used to receive the detector signals and to transmit the control signals for on-detector boards. Some of the receivers and transmitters are used for the connection with the MDT Trigger Processor and the Level-0 MUCTPI to receive and transmit the muon track candidates. Four transmitters are used for the connection with FELIX to transmit the readout data. One receiver is used to receive the signals of TTC. Tables 8.4 and 8.5 show the number of receivers and transmitters depending on the connected electronics.

<figure><img src="image_142.png" /><figcaption>Figure 8.20: Block diagram of the off-detector board in which the Sector Logic is implemented. The readout logic and the control functions are also implemented. The blocks with the number "12" indicate the MiniPOD modules [8.10], each of which contains 12 channels. Two blocks with the number "4" constitute a QSFP+ module [8.11], which is used for four transmitters and four receivers. The board is connected to the electronics of various detectors employed for the Level-0 muon trigger. There are connections with Level-0 MUCTPI and FELIX. The board is controlled with a Xilinx Zynq® device.</figcaption></figure>
<table><caption>Table 8.4: Number of receivers and transmitters per blade depending on the connected elements for the barrel off-detector boards.</caption><thead><tr><th>Connected elements</th><th>Number of receivers</th><th>Number of transmitters</th></tr></thead><tbody><tr><td>RPC on-detector boards</td><td>36</td><td>36</td></tr><tr><td>Tile calorimeter boards</td><td>3</td><td>0</td></tr><tr><td>MDT Trigger Processor</td><td>6</td><td>10</td></tr><tr><td>Level-0 MUCTPI</td><td>0</td><td>2</td></tr><tr><td>FELIX</td><td>1</td><td>2</td></tr></tbody></table>

<table><caption>Table 8.5: Number of receivers and transmitters per blade depending on the connected elements for the endcap off-detector boards.</caption><thead><tr><th>Connected elements</th><th>Number of receivers</th><th>Number of transmitters</th></tr></thead><tbody><tr><td>TGC on-detector boards</td><td>67</td><td>35</td></tr><tr><td>NSW Trigger Processor</td><td>6</td><td>0</td></tr><tr><td>RPC (BIS78) boards</td><td>2</td><td>0</td></tr><tr><td>Tile calorimeter boards</td><td>2</td><td>0</td></tr><tr><td>MDT Trigger Processor</td><td>6</td><td>10</td></tr><tr><td>Level-0 MUCTPI</td><td>0</td><td>3</td></tr><tr><td>FELIX</td><td>1</td><td>4</td></tr></tbody></table>

### 8.4.3 Firmware Design

The firmware of the FPGA on the off-detector board includes the Sector Logic, the readout logic, and the control functions (Fig. 8.21). In the Sector Logic, the trigger scheme described in Section 8.4.1 is implemented. Primitive track candidates are identified from the signals of RPC and TGC for the barrel and the endcap, respectively. The Sector Logic makes a spatial and time coincidence, with a time resolution of one bunch crossing or better, as in the case of the barrel system. Additional coincidence is taken with other inner detectors. The Sector Logic is designed to simultaneously process multiple closeby muons to retain the acceptance of the multi-muon trigger. The muon track candidates are transmitted to the MDT Trigger Processor. The Sector Logic receives the muon track candidates confirmed by the MDT Trigger Processor, and transmits the list of candidates to the Level-0 MUCTPI.

The RPC and TGC hit signals are separated before the Sector Logic, and transferred to the readout logic. The trigger information from the Sector Logic, including the NSW and Tile calorimeter data with limited granularity, is also transferred to the readout logic. The readout functionality for the full-granularity data of the NSW and the Tile calorimeter are provided separately from the off-detector boards where the Sector Logic is implemented. In
the readout logic, the data are stored in a derandomiser buffer during the Level-0 decision time, and transmitted to FELIX after the Level-0 trigger accept signals are received. The control of the RPC and TGC on-detector boards are originating from Xilinx Zynq® device.

<figure><img src="image_143.png" /><figcaption>Figure 8.21: A simplified block diagram of the proposed firmware for the FPGA of the off-detector boards. The detector signals are transferred to the Sector Logic (blue), and muon track candidates are provided. The muon track candidates are transmitted to the MDT Trigger Processor. The Sector Logic receives the muon track candidates from the MDT Trigger Processor, and transmit to the Level-0 MUCTPI. The readout logic (green) handles the readout for RPC and TGC hit signals and trigger information. The TTC manager (red) and the control (yellow) blocks manage the control of the off-detector board and RPC and TGC on-detector board.</figcaption></figure>

### 8.4.4 Detector Signal Inputs

**Inputs from RPC** The hit data and time information for the RPCs in the barrel inner, middle, and outer stations are provided to the Barrel Sector Logic for each bunch crossing. The size of the transferred data is reduced by encoding and zero suppression. The optical links with a bandwidth of 9.6 Gbps per link are assumed, which manage the data transfer for possible highest hit rate evaluated from the actual measurement in Run 2 [8.1].
**Inputs from TGC** The hit data of the TGCs in the endcap inner station in $1.05 < |η| < 1.3$ and the endcap middle station are provided to the Endcap Sector Logic for each bunch crossing. The hit data comprise one bit per channel per bunch crossing as an identifier of the existence of a hit. The data are transferred without zero suppression. The optical links with a bandwidth of 8.0 Gbps per link are assumed, which manage the data transfer independently of the hit rate.

**Inputs from NSW** The NSW Trigger Processor is designed to reconstruct the track segments with an angular resolution of 1 mrad [8.2]. The position and the angle of the segments are provided to the Endcap Sector Logic for each bunch crossing. Further explanation is given in Section 8.5.6. The segmentation of the NSW Trigger Processor is different from that of the Sector Logic, and hence the output of single NSW Trigger Processor is divided and transferred to multiple off-detector boards where the Sector Logic is implemented (Fig. 8.19).

**Inputs from Tile Calorimeter** The Tile calorimeter system is divided into three layers in depth. The last layer, known as the D-layer, is used for the Level-0 muon trigger, since most of the charged particles other than muons stop before this layer and only muons deposit energy consistent with minimum ionising particles. The energy deposit is estimated using an optimal filter algorithm. For each calorimeter cell, an identifier of the energy deposit to be greater than the threshold or not is passed to the Endcap Sector Logic for each bunch crossing.

### 8.4.5 Realtime Output Data Format

The data transfer between the Sector Logic, the MDT Trigger Processor, and the Level-0 MUCTPI is based on optical links. A maximum transfer rate of 9.6 Gb/s is assumed for each link, where six 32-bit words are transferred every 25 ns (Table 8.6). The data are encoded with a 8b10b scheme. The data are transferred regardless of the results containing muon candidates or not. The first and the last words are the header and trailer words. The contents of the header and trailer words are shown in Tables 8.7 and 8.8. The data transfer of two muon candidates is possible per link, with maximum 64 bits per candidate. Each barrel (endcap) Sector Logic can transfer 4 (6) muon candidates to the Level-0 MUCTPI.

<table><caption>Table 8.6: Contents of the six 32-bit words transferred by an optical link every 25 ns.</caption><tr><td>32-bit Word Identifier</td><td>0</td><td>1</td><td>2</td><td>3</td><td>4</td><td>5</td></tr><tr><td>Content</td><td>Header</td><td>Muon candidate 1</td><td>Muon candidate 2</td><td>Trailer</td><td></td><td></td></tr></table>
<table><caption>Table 8.7: Contents of the 32-bit header word.</caption><thead><tr><td>Number of bits</td><td>Name</td><td>Comment</td></tr></thead><tbody><tr><td>12</td><td>BCID</td><td>Identifier of the bunch crossing</td></tr><tr><td>20</td><td>Reserved</td><td>Reserved bits</td></tr></tbody></table>

<table><caption>Table 8.8: Contents of the 32-bit trailer word.</caption><thead><tr><td>Number of bits</td><td>Name</td><td>Comment</td></tr></thead><tbody><tr><td>8</td><td>Comma</td><td>K28.5, K character of the 8b10b encoding</td></tr><tr><td>6</td><td>Board ID</td><td>Identifier of the boards</td></tr><tr><td>4</td><td>Fibre ID</td><td>Identifier of the fibres</td></tr><tr><td>8</td><td>Parity</td><td>Parity bits, one bit corresponds to 16 bits in the data words</td></tr><tr><td>6</td><td>Reserved</td><td>Reserved bits</td></tr></tbody></table>

**Barrel Sector Logic to MDT Trigger Processor** One 64-bit word is used for a muon candidate selected by the Barrel Sector Logic. It includes the information of the muon track candidate as well as the RPC hit positions and the coincidence type. The contents of the data words are shown in Table 8.9.

<table><caption>Table 8.9: Contents of the 64-bit word for the data from the Barrel Sector Logic to the MDT Trigger Processor.</caption><thead><tr><td>Number of bits</td><td>Name</td><td>Comment</td></tr></thead><tbody><tr><td>10</td><td>Position η<sup>RPC0</sup></td><td>η coordinate of the position on RPC0</td></tr><tr><td>10</td><td>Position η<sup>RPC1</sup></td><td>η coordinate of the position on RPC1</td></tr><tr><td>10</td><td>Position η<sup>RPC2</sup></td><td>η coordinate of the position on RPC2</td></tr><tr><td>10</td><td>Position η<sup>RPC3</sup></td><td>η coordinate of the position on RPC3</td></tr><tr><td>6</td><td>Position φ</td><td>φ coordinate of the position on the innermost layer used for the coincidence (inner or middle station)</td></tr><tr><td>2</td><td>Coincidence type</td><td>Identifier of the types of coincidence</td></tr><tr><td>4</td><td>p<sub>T</sub> threshold</td><td>Highest transverse momentum threshold satisfied</td></tr><tr><td>1</td><td>Charge</td><td>Muon candidate charge</td></tr><tr><td>11</td><td>Reserved</td><td>Reserved bits</td></tr></tbody></table>
**Endcap Sector Logic to MDT Trigger Processor** One 64-bit word is used for a muon candidate selected by the Endcap Sector Logic. It includes the information of the muon track candidate and the track segment reconstructed by the TGC hits. It also includes the track segment reconstructed in the NSW Trigger Processor, which is used for the $p_T$ evaluation in the MDT Trigger Processor. The contents of the data words are shown in Table 8.10.

<table><caption>Table 8.10: Contents of the 64-bit word for the data from the Endcap Sector Logic to the MDT Trigger Processor.</caption><thead><tr><td>Number of bits</td><td>Name</td><td>Comment</td></tr></thead><tbody><tr><td>10</td><td>Position η</td><td>η coordinate of the position on the outermost TGC layer</td></tr><tr><td>6</td><td>Position φ</td><td>φ coordinate of the position on the outermost TGC layer</td></tr><tr><td>6</td><td>Angle Δθ</td><td>Segment polar angle with respect to the vector from the interaction point to the segment position, the last bit assigned for the muon candidate charge</td></tr><tr><td>4</td><td>Angle Δφ</td><td>Segment azimuthal angle with respect to the vector from the interaction point to the segment position, the last bit assigned for the sign</td></tr><tr><td>4</td><td>p<sub>T</sub> threshold</td><td>Highest transverse momentum threshold satisfied</td></tr><tr><td>28</td><td>NSW segments</td><td>Identical to the NSW Trigger Processor output</td></tr><tr><td>3</td><td>Quality</td><td>Coincidence pattern (NSW, BIS78 RPC, etc.)</td></tr><tr><td>3</td><td>Reserved</td><td>Reserved bits</td></tr></tbody></table>

**Sector Logic to Level-0 MUCTPI** One 48-bit word is used for a muon candidate. The contents of the data words are shown in Table 8.11. The reserved bits can be used for the trigger information for exotic signatures.

## 8.5 NSW Trigger Processor

This section describes the motivation, the expected performance, the hardware and firmware design, and the interfaces of the NSW Trigger Processor upgrade.

### 8.5.1 Motivation for the Upgrade

The NSW project [8.2] is a Phase-I muon upgrade project slated for the installation during Long Shutdown 2. In the Phase-I system, signals from sTGC and MM are used separately
<table><caption>Table 8.11: Contents of the 48-bit word for the data from the Sector Logic to the Level-0 MUCTPI.</caption><thead><tr><td>Number of bits</td><td>Name</td><td>Comment</td></tr></thead><tbody><tr><td>14</td><td>Position η</td><td>η coordinate of the segment position on the innermost MDT layer</td></tr><tr><td>6</td><td>Position φ</td><td>φ coordinate of the position</td></tr><tr><td>8</td><td>p<sub>T</sub></td><td>Muon candidate transverse momentum</td></tr><tr><td>4</td><td>p<sub>T</sub> threshold</td><td>Highest transverse momentum threshold satisfied</td></tr><tr><td>1</td><td>MDT confirmation</td><td>Reconstructed by MDT or not</td></tr><tr><td>1</td><td>Charge</td><td>Muon candidate charge</td></tr><tr><td>2</td><td>0/1/2/3 stations</td><td>Number of MDT segments for the candidate</td></tr><tr><td>3</td><td>Quality</td><td>Average or worse segment quality</td></tr><tr><td>9</td><td>Reserved</td><td>Reserved bits</td></tr></tbody></table>

to form NSW track segments in the trigger processor electronics. A requirement is applied on the pointing of trigger segments back to the interaction region, and segment position information is transmitted to the Sector Logic, where a coincidence with TGC is taken. The latency budget for the Phase-I NSW Trigger Processor is extremely tight. The NSW trigger as designed for the installation after Run 2 already meets the Phase-II requirement of an angular resolution of 1 mrad. However, it is quite possible to further lower the thresholds for muon momentum and increase the efficiency by taking advantage of the increased latency to do a more refined calculation of muon pointing and momentum in the NSW, or to improve robustness and redundancy, for example in case of missing layers.

In the Phase-II Level-0 muon trigger, the NSW trigger segment reconstructed in the NSW Trigger Processor is used to determine not only the deflection angle with TGC in the Sector Logic but also the deflection angle and the sagitta (see Section 8.6.1) with MDT in the MDT Trigger Processor for a refined momentum resolution. Even though the resolution of the deflection angle measured with the NSW and TGC segments is dominated by the TGC, the deflection measurement using the more precise MDT information would benefit from a NSW segment with high precision. A combined segment fit with increased precision is possible if both sTGC and MM hits are combined into a single fit.

In the Phase-I NSW Trigger Processor, the sTGC and MM segments are derived separately and a procedure to remove duplicates is implemented before sending the segment information to the Sector Logic. A coincidence of hits is required in at least three out of four layers for each of the sTGC and MM quadruplets before fitting a segment. In the upgraded electronics, all sTGC and MM layers are available in the same trigger processor FPGA, allowing for improved background rejection and increased efficiency due to more flexible coincidence requirements.
Historically, triggering on forward muons can be challenging due to backgrounds from secondaries that can be difficult to eliminate and assess until the NSW detector is actually running. The trigger performance can be enhanced by improved granularity that can be achieved with more latency and increased resources.

### 8.5.2 Performance of the Segment Reconstruction

The performance of the track segment reconstruction by NSW could be affected by the background hits. Figure 8.22 shows the impact of large cavern background rates on the azimuthal precision of the MM-only segment. The current algorithm performance will be degraded, but the performance can be regained with a more sophisticated algorithm that takes more FPGA resources and more latency. This improvement in the azimuthal resolution will permit a finer tuned matching between segments in the TGC and the NSW.

<figure><img src="image_144.png" /><figcaption>Figure 8.22: Azimuthal angle ($\phi$) precision for different background rates for the standard algorithm (blue) and an improved algorithm (green) that uses higher granularity but requires longer latency and more FPGA resources.</figcaption></figure>

### 8.5.3 Hardware Design

In this proposed upgrade, the Phase-I trigger processor hardware (ATCA mezzanines and blades), excluding the ATCA crates and optical fibres, are replaced. Figure 8.23 shows a diagram of the proposed hardware. The new NSW Trigger Processor is designed to receive both sTGC and MM inputs from a 1/16th $\phi$ sector in a single FPGA. Two sectors are
processed in each board, and the full system requires 16 ATCA boards to operate. In the proposed implementation, the trigger processor firmware is implemented in an FPGA on a mezzanine card of an ATCA carrier blade. The input fibres from the NSW detectors and the output fibres to the Sector Logic connect directly to the mezzanine card. Some services are implemented on the carrier card, which adhere to ATCA standards and provide all required interfaces to meet the specifications for Phase-II.

<figure><img src="image_145.png" /><figcaption>Figure 8.23: Block diagram of the off-detector board in which the NSW Trigger Processor is implemented. This ATCA blade includes two FPGAs that each process a 1/16th φ sector of the detector. There are connections with the Sector Logic boards and FELIX/TTC. The board is controlled with a Xilinx Zynq® device.</figcaption></figure>

The trigger processor FPGA is required to have at least 72 high speed optical receivers for the NSW detector signals (36 for sTGC and 36 for MM), 12 transmitters to send the track segments to the Sector Logic, as well as additional receivers and transmitters for control signals. In particular, one additional receiver and one transmitter are used for the connection with FELIX to receive the TTC signals and to transmit the readout and monitoring signals (signal readout, statistics, sampled events, algorithm parameters, etc).

The Xilinx Virtex UltraScale+ family of FPGAs is proposed for the implementation, although the final decision will depend on the evolution of the technology in industry. The UltraScale+ FPGA includes devices that can process all NSW detector layers (sTGC and MM).

### 8.5.4 Firmware Design

The firmware includes the trigger processor and the control functions. Figure 8.24 shows a simplified block diagram of the proposed firmware. In the trigger processor, the sTGC
and MM inputs are processed and reformatted into a position on each of the 16 detector planes. In the case of the MM, the position of the strip with the first hit in time within each group of 64 strips is used (Address in Real Time or ART, data). In the case of the sTGC, a cluster centroid is calculated using the charge information in neighbouring strips. Coincidences are then taken with the sTGC and MM signals from the different planes to suppress fake triggers. The sTGC and MM information is finally combined in a fit that is used to derive the segment parameters to be transmitted to the Sector Logic. Additional firmware blocks implement functionality supporting the NSW Trigger Processor algorithm such as the monitoring, the readout, the TTC signal handling, the configuration, control and monitoring of the hardware (including the FPGAs), etc.

<figure><img src="image_146.png" /><figcaption>Figure 8.24: A simplified block diagram of the proposed firmware for the NSW Trigger Processor off-detector boards, indicating the input and output connections.</figcaption></figure>

### 8.5.5 Detector Signal Inputs

The detector signal inputs are identical to those in the Phase-I NSW Trigger Processor.

**Inputs from sTGC** The sTGC strip information identified from up to four pad-trigger towers are provided to the trigger processor for each bunch crossing. The radial and azimuthal information of the pad-trigger roads are also provided, and the pad-trigger provides the azimuthal measurement for the sTGC inputs. Charge thresholds are applied to select up to five strips in a band and a layer centroid calculation is performed to derive the position coordinates for each sTGC plane.

**Inputs from MM** The trigger input data from the MM detector provides the address of the strip that first crosses the threshold. The address of the ~ 450 µm strip is used to derive
the MM hit position per layer. Stereo strips are used in the middle layers to derive the azimuthal information.

## 8.5.6 Realtime Output Data Format

Each track segment reconstructed by NSW Trigger Processors will be presented as 28-bit data with the format shown in Table 8.12. This format allocates more bits to the $\eta$ and $\phi$ information compared to the format used in Run 3 to account for the increased precision from a combined sTGC and MM fit.

The required resolutions (1 bit) are approximately 1 mrad (±15 mrad full scale) for $\Delta\theta$, 15 mrad for $\phi$, and 0.0001 in pseudo-rapidity $\eta$. The $\Delta\theta$, $\phi$, and $\eta$ position information are included in the output, in addition to one flag. The monitor flag is set when this bunch crossing has been identified for further monitoring by the NSW trigger.

<table><caption>Table 8.12: Contents of the data from the NSW Trigger Processor to the Endcap Sector Logic.</caption><thead><tr><td>Number of bits</td><td>Name</td><td>Comment</td></tr></thead><tbody><tr><td>14</td><td>Position η</td><td>η coordinate of the NSW segment position</td></tr><tr><td>8</td><td>Position φ</td><td>φ coordinate of the NSW segment position</td></tr><tr><td>5</td><td>Δθ</td><td>Segment polar angle with respect to the vector from the interaction point to the segment position</td></tr><tr><td>1</td><td>Monitor</td><td>Monitoring bit</td></tr></tbody></table>

## 8.6 MDT Trigger Processor

The MDT chambers currently used for precision tracking will be included in the Level-0 muon trigger to improve the momentum resolution and the redundancy. This section describes the motivation, the expected performance, the hardware and firmware design, and the interfaces of the MDT Trigger Processor. The section also introduces the readout path for the MDT chambers and the resource estimation.

### 8.6.1 Motivation for the Implementation

The selectivity of the current Level-1 muon trigger is limited by the moderate spatial resolution of RPC and TGC (Fig. 8.3). It has been considered since the start of the R&D for HL-LHC to use the MDT chamber data in the Phase-II Level-0 muon trigger [8.12][8.13][8.14]
[8.15] The MDT chambers provide a better spacial resolution than RPC and TGC, and a $p_T$ resolution close to that of the offline reconstruction can be achieved.

The use of the MDT chambers improves the robustness of the Level-0 muon trigger. The rate of the accidental coincidences in the BI-BO trigger in the barrel is expected to have nonlinearity with the luminosity. This is suppressed by the requirement based on MDT, mitigating the risks on the unexpected rate increase.

Studies of the MDT trigger concept show that it is not needed to reconstruct the full muon track inside the muon spectrometer, but that it is sufficient to use the positions and the angles of track segments reconstructed in the muon chambers for a refined momentum measurement. This concept makes it possible to implement the hardware-based MDT trigger in the Phase-II Level-0 trigger.

Figure 8.25 shows schematically two variables that can be used to measure the muon $p_T$ in the MDT Trigger Processor. The first variable is the polar-angle difference between track segments in two chambers, referred to as the deflection angle hereafter. The second variable uses track segments in three chambers and is defined as the distance between the position of one segment from the straight line joining the other two, referred to as the “sagitta” hereafter. The two variables provide different rate rejections and coverages (see Sections 8.6.2 and 8.6.6), and the best performance is achieved by the combination.

### 8.6.2 Trigger Performance

The performance of the MDT trigger has been studied with MC samples after the requirements expected for the Sector Logic. For the barrel, the RPC trigger scheme of “3/4 chambers + BI-BO” is employed. For the endcap, the TGC segment is reconstructed by a minimum $\chi^2$ method. The track segments reconstructed by the ATLAS offline software are used to obtain the deflection angle and the sagitta for the MDT trigger.

The trigger efficiency has been studied with MC samples where a muon is produced in each event. The muon direction is random in the $\eta-\phi$ plane. No pile-up is involved. Figure 8.26 shows the efficiency for 20 GeV threshold as a function of the muon $p_T$ evaluated by the ATLAS offline tool. Figure 8.27 shows the relative efficiency of the MDT trigger with respect to the RPC and TGC trigger. The MDT trigger provides an improved selectivity for the muons with $p_T$ around the threshold, while keeping a high plateau efficiency. The same MC samples as in Section 8.4.1 are used for the study of the trigger rate of the MDT trigger in the barrel. Figure 8.28 shows the estimated Level-0 single muon rate depending on the luminosity for $p_T$ thresholds of 10 GeV and 20 GeV. Figure 8.29 shows the rates as a function of $|\eta|$ for the case of $\langle\mu\rangle = 200$. The distribution of offline reconstructed muon matching the RPC trigger with offline $p_T$ above the Level-0 threshold is shown for comparison. For the sample with $\langle\mu\rangle = 200$, the MDT trigger reduces the Level-0 RPC trigger by approximately 55% and 70% for $p_T$ thresholds of 10 GeV and 20 GeV, respectively. For the endcap, the trigger rate has been studied with Run 1 and Run 2 data samples, and the reduction by
<figure><img src="image_147.png" /><figcaption>Figure 8.25: (a) Schematic of the concept of the polar angle difference between the two segments. The combination considered for the barrel is the middle and outer stations, but any other combination can in principle be used as well. (b) Schematic of the concept of the distance between the position of a segment and the position extrapolated from two segments. The figures show the cross-sectional view for so-called even sectors. The variable is defined similarly in so-called odd sectors. For $1.05 < |η| < 1.3$, the endcap inner station is assumed alternatively to the barrel inner station.</figcaption></figure>
<figure><img src="image_148.png" /><figcaption>Figure 8.26: Trigger efficiency in $|η| < 2.4$ as a function of $p_T$ measured by the offline reconstruction. A $p_T$ threshold of 20 GeV is assumed. The values are estimated with single-muon MC with no pile-up. Figure (a) shows the efficiency for the angle difference, the sagitta, and the combination. Figure (b) shows the efficiency with and without the MDT.</figcaption></figure>

<figure><img src="image_149.png" /><figcaption>Figure 8.27: Relative efficiency of the MDT trigger with respect to the RPC and TGC trigger as a function of $p_T$ measured by the offline reconstruction. The values are estimated with single-muon MC with no pile-up. The range $p_T < 4$ GeV is not shown because of the large uncertainty due to low statistics. Figures (a) and (b) for $p_T$ thresholds of 10 GeV and 20 GeV, respectively.</figcaption></figure>
the MDT trigger with respect to the rate of TGC and NSW is found to be roughly 50% for $p_T$ threshold of 20 GeV [8.1].

<figure><img src="image_150.png" /><figcaption>Figure 8.28: The estimated rate of the Level-0 single-muon trigger based on RPC only and RPC plus MDT for the barrel region $|η| < 1.05$. The dots with error bars show the values estimated from MC samples with the $\langle μ \rangle$ values corresponding to various luminosity scenarios. The curves show the result of the fit by a second-order polynomial.</figcaption></figure>

<figure><img src="image_151.png" /><figcaption>Figure 8.29: The estimated rate of the Level-0 single-muon trigger based on RPC only and RPC plus MDT for the barrel region $|η| < 1.05$ in MC sample with $\langle μ \rangle = 200$. The full dot distribution is obtained by requiring that the RPC trigger matches an offline reconstructed muon with $p_T > 10 (20)$ GeV.</figcaption></figure>

As the deflection of the muon trajectory is greater for lower momentum, the Sector Logic already has a good selectivity and the relative reduction by the MDT trigger per muon is smaller for lower momentum. However, the lower $p_T$ thresholds will be used mainly for multi-muon triggers, and the rate reduction by the MDT trigger will be multiplied. The
10 GeV threshold will be used mainly for dimuon trigger, and the rate reduction would be approximately twice as large as that for single muon for the same threshold.

### 8.6.3 Hardware Overview

The MDT chambers are divided in $\phi$ into 16 sectors. They are further partitioned between barrel and endcap subsystems, A and C sides (divided at $\eta = 0$), and three stations (inner, middle, and outer). The MDT trigger system is partitioned into 64 processing elements, each handling one sector, one side (A/C), and one subsystem (barrel/endcap).

Figure 8.30 illustrates an ATCA blade which handles one out of the 64 sectors. The blade contains a total of 144 fibre receivers and transmitters, with the exact complement of each to be determined. The fibre transmitters may be located on a rear transition module. The ATCA services are provided by a CERN-designed IPMC mezzanine. This device controls and monitors operation of the module, including voltage, current, and temperature monitoring. Access to the IPMC is provided through the Intelligent Platform Management Bus (IPMB) on the ATCA backplane and Gigabit Ethernet.

<figure><img src="image_152.png" /><figcaption>Figure 8.30: Layout of the ATCA blade where the MDT Trigger Processor is implemented.</figcaption></figure>

The blade contains one Xilinx UltraScale FPGA, which handles receipt of the MDT hits, receipt of the Sector Logic track candidates, hit extraction, calibration, transmission of hits to the mezzanine boards, receipt of the segment data from the mezzanine boards, evaluation of $p_T$, and transmission of the muon track candidates to the Sector Logic. Each mezzanine board performs a segment reconstruction. The mezzanine boards are introduced in the design so that the segment reconstruction gets separate from the other functions and the task sharing of the development gets easier. A modular design allows to confine losses to
a given item during the production and maintenance phases. The blade FPGA also trans-
fers the MDT hits to FELIX. Connections are planed to receive and transmit control signal
such as TTC. The transmitters to the Chamber Service Module (CSM) send the TTC stream
and the configuration to the electronics. An external DDR memory device is required for
buffering of the data for readout.

The Xilinx Zynq® devices are anticipated for the system control functions including de-
tector controls, monitoring, and local data acquisition. The Xilinx Zynq® device requires
flash memory for programme storage, RAM, and an interface to a MicroSD card for remov-
able storage. A Gigabit Ethernet switch provides access to the Xilinx Zynq® devices from
the base fabric on the ATCA backplane, a front-panel RJ-45 connector or the IPMC.

A block diagram of the trigger logic is shown in Fig. 8.31. Raw MDT hits are received on three groups of Gigabit Bidirectional Trigger and Data Link (GBT) (or lpGBT) links from the inner, middle, and outer MDT stations. Since some MDT hits can arrive before the Sector Logic track candidates, they will need to be buffered. MDT hits can be calibrated where the (r-t) relation is stored in LUT. MDT hits in the RoI derived from the Sector Logic data are extracted by the hit extractor. Track segment is reconstructed and used for pT evaluation. Muon track candidates as well as the evaluated pT are transmitted to the Sector Logic. Additional links between adjacent sector MDT Trigger Processor blade are foreseen to pass segments found between sector so that to handle sector overlap as well as the transition region where muon can have segments from the barrel and the endcap.

An MDT Trigger Processor implements three separate processing pipelines for the hit ex-
traction and the segment reconstruction. The processing for three simultaneous RoIs is pos-
sible. The estimated busy fraction is 0.1% (0.5%) for an RoI rate of 100 kHz (180 kHz) per
MDT Trigger Processor. The MDT Trigger Processor is designed to be used for pT thresholds
down to around 5 GeV.

8.6.4 Hit Extraction

The hit extractor logic (Fig. 8.32) matches MDT hits with RoIs in space and time for further
processing of the segment reconstruction. The “RoI processor” converts the RoI informa-
tion from global coordinates to a range of tube ID numbers, which are passed to the “tube
range LUT”, and passes a time and position to the “MDT hit calibration” block. The block
“tube range LUT” converts the MDT ID number in the TDC data to a tube/layer number
format.

In the barrel, due to deflection by the magnetic field, the RoI directions and positions, at
the centre of the MDT chamber spacer frame, need to be determined separately for the
inner, middle, and outer MDT precision chambers, as shown in Fig. 8.33a. The algorithm
handles the different RPC coincidence requirements leading to distinct hit patterns. For
example, in the case where a layer does not have RPC hits, the RoI position and direction at
this layer can be determined from the extrapolation of the RoI positions and angles in the
<figure><img src="image_153.png" /><figcaption>Figure 8.31: Block diagram of the MDT Trigger Processor.</figcaption></figure>

<figure><img src="image_154.png" /><figcaption>Figure 8.32: Block diagram of the hit extractor. The MDT hits are matched with the RoIs derived from the Sector Logic track candidates, and calibrated data are transferred to the following logic.</figcaption></figure>
neighbouring layers, as seen in Fig. 8.33b. In the endcap, the RoI direction and position is determined from the TGC track segment information. Since there is no significant magnetic field between the endcap middle and outer stations, the direction of the RoI is defined to be the same for these stations. The position of the RoI in the middle of the spacer frame of these stations is determined by a linear extrapolation for the TGC track segment. For each station, the matching window is defined as a parallelogram centred on the RoI position as depicted in Fig. 8.33c.

<figure><img src="image_155.png" /><figcaption>Figure 8.33: (a) Cross sectional view of the position and the direction reconstructed in a barrel middle station. The red rectangles represent RPC1 and RPC2. The blue circles represent the MDT tubes while the white circles represent RPC η-hits. The double-sided arrow indicates the fit line with the plus sign marking its intersection with the centre of the spacer frame. (b) Cross-sectional view of the averaging used in cases where there are η-hits in BI and BO but only one RPC layer of BM. The long rectangles represent RPC layers and the circles represent RPC η-hits. The dotted lines indicate the fits used to determine the position, which is shown as a solid line. (c) Illustration of an RPC RoI window definition in terms of MDT tube identification. The solid line represents an RoI and the parallelogram represents the window opened around it with a size of ±3 MDT tubes. The solid circles represent the pair of MDT tubes used to identify the matching window. The numbers indicate the multilayer (ML), layer (L), and tube IDs used for each MDT chamber.</figcaption></figure>

Studies have shown that a window width of seven MDT tubes for the inner and middle stations, and a wider window of 13 tubes for the outer stations, to account for the inaccuracy in the RoI extrapolation to the outer layers due to residual magnetic field, is sufficient to achieve matching efficiencies better than 95% for hits originating from real muons. The matching of the MDT drift time to the bunch crossing identifier is expected to reject at least ~50% of background hits originating from pile-up and cavern background. With both the time and space matching applied, only ~3% of the hits within an RoI, corresponding to a maximum of 100 hits per station, remain to perform the segment reconstruction.

The TDC value, $t_{\text{TDC}}$, recorded by the frontend electronics and transmitted to the MDT Trigger Processor, is the sum of the delays in the readout electronics ($t_0$), the muon time of flight from the bunch crossing to the MDT chamber ($t_{\text{TOF}}$), the drift time ($t_{\text{Drift}}$) from the ionisation, and other smaller corrections. The $t_0$ and $t_{\text{TOF}}$ are the largest corrections, and a single pre-calculated time offset per MDT station is sufficient to extract MDT hit drift times.
The MDT hit drift time is converted into drift radius ($r_{Drift}$) using a space-to-drift time relationship, also called ($r-t$) relation. The ($r-t$) relation is nonlinear in the MDT [8.16] due to the tube geometry and the non-uniform electric field inside the tube. As the muon spectrometer momentum resolution is dominated by multiple scattering in the interested momentum range, only a moderate knowledge of the space drift-time relationship is required. In order to achieve a $p_T$ resolution better than 10% at 20 GeV, the sagitta has to be measured with a precision of 1 mm, which translates into a segment position resolution of 600 µm. The requirement on the segment angular resolution is driven by the angular resolution of the NSW, which is 1 mrad. Single ($r-t$) relation per MDT chamber is sufficient since the variation inside chamber due to temperature gradients, non-uniform magnetic field, and different $\gamma$ background levels is small.

### 8.6.5 Segment Reconstruction

The track segments are reconstructed on the mezzanine boards. There are two options for the design of the mezzanine board, which share the design of the main ATCA blade. One design has FPGA as the main element for the segment reconstruction. The other design is based on AM chips. The former is the current baseline, but the final choice will be given after the review.

#### Segment Reconstruction with FPGA

The mezzanine board with FPGA provides the flexibility for the algorithm of the segment reconstruction. The baseline algorithm is the Legendre transform, while another algorithm based on a seeded pattern recognition and a segment fit is also proposed. One has the option to use a segment fit after the Legendre transform for ambiguity resolving and refined angle and position determination. The concept and the performance for each algorithm are introduced in the following.

**Segment Reconstruction with Legendre Transform** The Legendre transform makes it particularly convenient to reconstruct segments using pattern recognition in the MDT chambers, since it does not require to calculate the exact position of the hits along the perimeter of the drift circle. Additionally, the algorithm can be easily parallelised for an FPGA implementation, which means that the processing time does not scale up with the number of hits.

The implementation of the Legendre transform for segment finding is based on the transform of each MDT tube position and drift time, ($R_0, z_0, r_{Drift}$), to the polar coordinates Legendre space ($r, \theta$) [8.17]. The basic principle of the transform is described in Fig. 8.34, and uses

$$r = z_0 \cos \theta + R_0 \sin \theta \pm r_{Drift} \qquad (8.1)$$
Each drift circle is represented by two lines in the Legendre space corresponding to its concave and convex parts, respectively. Each $(r, \theta)$ point in the Legendre coordinate space represents a line in the Cartesian coordinate system, tangent to the corresponding drift circle. If the Legendre transform is applied on all the drift circles of one chamber, the most populated $(r, \theta)$ bin of the Legendre space will represent the tangent line that is common to most of the drift circles.

<figure><img src="image_156.png" /><figcaption>Figure 8.34: Principle of the Legendre transform. The drift circle in Cartesian (left) and Legendre (centre) space as well as the basic principle and mathematical properties (right) are shown.</figcaption></figure>

Figure 8.35 shows a typical event display for the barrel middle station for $Z \to \mu\mu$ MC with the background hits. The top plot shows the hits for an event. The full blue circles on the top plot correspond to hits that are attached to the offline reconstructed segment, while the empty ones are background hits not belonging to the offline segment. All the hits within 90 mm distance, corresponding to $\pm 3$ tubes, are transformed in the Legendre space, that is shown on the bottom plot. The bin with maximum occupancy defines the slope and the intercept of the most popular tangent line.

Proposed granularity of the Legendre space is a bin size of 0.2 mm and 0.5 mrad for $r$ and $\theta$, respectively [8.17]. The performance of the segment reconstruction with the Legendre transform has been studied for different bin sizes and the proposed bin size has proved to give the best results. The limits of the Legendre space have to be sufficiently large such that the common tangent line bin is always within range. Studies have shown that a Legendre space of $\pm 64$ bins of 0.5 mrad along $\theta$ and $\pm 64$ bins of 0.2 mm along $r$ are sufficient to ensure that the tangent line is reconstructed in more than 95% of the cases.

The performance in terms of the segment angle and position reconstruction has been evaluated using a single-muon MC sample without background hits. To calculate the accuracy of the segment reconstruction that can be achieved, the position and angle between the reconstructed segment and the segment from the offline reconstruction are compared. Figure 8.36 shows the position and angle difference distributions. The position and angle resolution of the reconstructed segments can be estimated by fitting the core distribution in the range $\mu \pm 1.5\sigma$ with a Gaussian function. The Legendre transform algorithm is able to reconstruct segments with an accuracy for the core of the distributions of $\sim 0.6$ mrad in
<figure><img src="image_157.png" /><figcaption>Figure 8.35: Event display (a) and the corresponding representation in the Legendre space (b) for a $Z \to \mu\mu$ MC event with background hits. The event display is shown on a global plane, where R is the cylindrical radius with respect to the axis that passes through the middle of the sector in $\phi$ and Z is the coordinate along the beam axis.</figcaption></figure>

angle and ~90 µm in position over a $p_T$ range of 1–100 GeV. They satisfy the requirements of 1 mrad and 600 µm for the segment angle and position, respectively.

The hardware implementation of the segment reconstruction with Legendre transform fits the resources of modern FPGAs (see Section 8.6.9). In the initialisation stage, the sin and cos values are copied from a pre-computed LUT to local registers for a range of track angles around the RoI angle. The value of $r = z_0 \cos \theta + R_0 \sin \theta \pm r_{\text{Drift}}$ is calculated simultaneously for all 128 $\theta$ values using DSP blocks in the FPGA fabric. Each $r$ value is used to increment a histogram bin, while simultaneously keeping a record of the location of the most populated bin. Finally, a binary search is performed to find the most populated bin. From the most populated bin, the output of the segment is provided.

**Segment Reconstruction by Seeded Pattern Recognition and Fit** An alternative and resource-saving method of the segment reconstruction relies on the direction of the flight of the muon evaluated by the Sector Logic. An angular resolution expected is 15 mrad in
<figure><img src="image_158.png" /><figcaption>Figure 8.36: Distributions of the difference between reconstructed angle and position of the Legendre transform from the corresponding offline reconstructed segment in the same MDT station.</figcaption></figure>

the barrel inner and middle stations, 50 mrad in the barrel outer station, and 4 mrad in the endcap region. This angle measurement is used in the pattern recognition step [8.18][8.19]. The segment parameters can be determined by the fit with the embedded CPU by using a SoC device alternatively to FPGA.

For the following discussion of the seeded pattern recognition and fit, we use a coordinate system in which the z axis is orthogonal to the drift tube layers and the y axis is parallel to the tube layers (see Fig. 8.37). If (y, z) denotes the position of the anode wire of a tube, the distance r of a muon track from the anode wire of a traversed drift tube is given by

$$r = \frac{|m \cdot z + b - y|}{\sqrt{1 + m^2}},$$

where m and b denote the slope and the intercept of the straight segment and y and z are the horizontal and vertical coordinates of the tube in the chamber coordinate frame. Using the measurement of the drift radius r and the value of the slope m as provided by the Sector Logic, one can transform this equation into an equation for the intercept b. There are two solutions $b_{\pm}$ for the value of the intercepts:

$$b_{\pm} = \pm r\sqrt{1 + m^2} - (m \cdot z - y).$$

The values of $b_{\pm}$ obtained from the hits in the drift tubes in the RoI can be used to find the right hit pattern. If one treats the hits in the two multilayers of an MDT chamber separately and computes $b_{\pm}$ at the z position of the second layer of each multilayer, the limited resolution in the segment slope from the Sector Logic of up to 50 mrad translates into a $b_{\pm}$
resolution of ≲ 1 mm, which is sufficient to identify the hits which line up on a straight segment.

<figure><img src="image_159.png" /><figcaption>Figure 8.37: Schematic drawing illustrating the definition of the chamber coordinate system and the distance r of straight line from the anode wire of a drift tube.</figcaption></figure>

The computation of $b_{\pm}$ and the right MDT hits can be carried out on FPGA or programmable logic part of SoC. Choosing the centre of the y axis in the middle of the RoI, eight bits are enough to store $b_{\pm}$ in steps of 0.82 mm. The values of $b_{\pm}$ are filled in a histogram with 1 mm to 2 mm bin width. From the histogram, one finds the largest accumulation of equal $b_{\pm}$ values. The hits which are associated to the largest accumulation are the hits which lie on a common straight line.

The MDT hits which are found to line up on a straight line are then transferred to the embedded CPU via a fast AXI link for the determination of the segment parameters and the $\chi^2$ as goodness-of-fit estimator. For each of these hits, one knows the sign $\alpha$ in front of the $r\sqrt{1+m^2}$ term. By replacing the slope $m$ by $\bar{m} + \delta$ and linearising $\sqrt{1+(\bar{m}+\delta)^2}$ in $\delta$, one gets a single equation with two free parameters, $\delta$ and $b$, for each hit:

$$ \alpha r \sqrt{1 + \bar{m}^2} - (\bar{m}z - y) + \left( \frac{\alpha r \bar{m}}{\sqrt{1 + \bar{m}^2}} - z \right) \delta - b = 0. $$

The parameters $\delta$ and $b$ can be determined by a least-square fit to the following n points:

$$ \left( \alpha_k r_k \sqrt{1 + \bar{m}^2} - (\bar{m}z_k - y_k), \frac{\alpha_k r_k \bar{m}}{\sqrt{1 + \bar{m}^2}} - z_k \right)_{k \in \{1, \dots, n\}}. $$

The segment fitting procedure was tested by evaluating the deviations of the reconstructed segment slopes from the true segment slopes (Fig. 8.38). At a segment reconstruction efficiency close to 100%, this distribution shows negligible non-Gaussian tails. A similar distribution is obtained for the segment positions. Negligible non-Gaussian tails are important for a reliable momentum determination from the segment positions and segment slopes.
<figure><img src="image_160.png" /><figcaption>Figure 8.38: Distribution of the deviation between the reconstructed and true slopes in simulated data for the chambers of the barrel middle station. The distribution has negligible non-Gaussian tails. Background hits corresponding to Run 2 are included in the simulation.</figcaption></figure>

## Segment Reconstruction with AM Chips

In the alternative design, the AM chip developed for FTK [8.20] and Phase-II HTT is employed for the segment finding. The AM chip is a powerful pattern recognition device, which is widely used for the trigger upgrade programme at ATLAS. The application for MDT is designed so that the system may share the exact hardware design of the full custom AM chips and the mezzanine card named Pattern Recognition Mezzanine (PRM) with the other AM-based hardware tracking projects.

In the MDT segment reconstruction with the AM chips, a segment candidate requires a coincidence of hits in the eight tube layers in the barrel inner station, and six tube layers everywhere else. A hit is represented with the tube channel number, which uniquely identifies the position of the tube centre and an unsigned radius. For each MDT station, a set of 800k most probable coincidences (“patterns”) is computed offline with a MC simulation for high $p_T$ muons, typically for those with $p_T > 6$ GeV. The unsigned drift radius is divided into bins in the pattern computation with 3 mm binning for the outermost two layers and 5 mm binning for the other layers in an initial study. The coincidence patterns are computed and loaded into AM chips. A pattern might be consistent with more than one set of sign assignments (i.e. the left and right solution for each drift radius) for the six or eight tube hits. All the possible sets of sign assignment per pattern are stored so that it can be mapped for found patterns in the segment reconstruction. If a muon trajectory fires two tubes per layer according to its incident angle, one of the tubes will be taken as the representative in the pattern computation, avoiding duplication of patterns.
The main functional blocks of the segment reconstruction with the AM chips are the hit extraction, the segment finding, the mapping for sign assignments, the road warrior, and the segment calculation. The AM chips and the FPGAs on the PRM are interfaced with the parallel fast DDR buses, constituting the segment reconstruction engine. Two PRM cards cover an MDT sector, and a PRM card covers two MDT stations. Eight AM chips will be available per station so that four different majority logic thresholds in the pattern matching will run simultaneously. Either of 3-out-of-6 or 5-out-of-8 will be taken as the lowest possible coincidence, which minimises the segment reconstruction inefficiency due to the intrinsic hit-level inefficiency or incomplete pattern lists. The positions of tube centre, the full resolution drift radius, and the sign assignment will be given in advance to the segment calculation for the MDT hits of the coincided patterns. In addition, an initial value for the angle for a found pattern will be available in the segment calculation. They allow the track parameters of angle and position to be extracted by an online fit technique of linear approximation, which has been used for the FTK system, or $\chi^2$ minimisation for straight trajectories. The road warrior functionality followed by the segment calculation will discard patterns which share the same set of fired MDT tube hits for an event in order to minimise the segment calculations, which could be the case if more than one independent patterns share the subset of tubes hits.

Figure 8.39 shows performance plots for the segment finding with the AM approach at the endcap middle station, evaluated with the single muon MC sample without the background hits. The left figure shows the number of AM output after the sign assignment and before the road warrior algorithm runs, where the different colours correspond to different majority logic thresholds. The right figure shows the segment finding efficiency at the same station as a function of $p_T$ of muon candidates reconstructed by the offline tool. The efficiency is defined by the fraction of finding a segment reconstructed by the AM pattern finding which shares a hit with the segment reconstructed by the offline tool. An efficiency of about 99% is obtained.

## Segment Reconstruction Algorithm Choice

The performance of the MDT trigger is sensitive to the segment reconstruction efficiency and resolution including the non-Gaussian components of the angle and the position. The choice of the segment reconstruction will be given after the careful review of the following items. The review is planned to take place in the end of 2019. For the evaluation of the performance, common MC samples are used between different algorithms.

1. Segment resolution: resolution of the position and the angle for the segments of the MDT trigger with respect to the segments reconstructed by the ATLAS offline analysis

2. Trigger efficiency: trigger efficiency depending on $p_T$, $\eta$, and $\phi$, for single-muon and multi-muon MC samples with the background hits expected under the HL-LHC condition
<figure><img src="image_161.png" /><figcaption>Figure 8.39: Performance plots for the segment finding with the AM approach at the endcap middle station, evaluated with the single muon MC sample without the background hits. The left figure shows the number of AM output before the road warrior algorithm runs, where different colours correspond to different majority logic thresholds. The right figure shows the segment finding efficiency at the same station as a function of p$_{T}$ of muon candidates reconstructed by the offline tool.</figcaption></figure>

3. Fake efficiency: efficiency of finding segments not matched with the offline segments, for single-muon MC samples with background hits expected under the HL-LHC condition

4. Algorithm flexibility: flexibility of the algorithm to retain the exotic signatures such as displaced vertices and slow particles

5. Latency: maximum latency of the MDT Trigger Processor depending on the hit rate

6. Capability to handle multiple RoIs: maximum number of RoIs that can be handled simultaneously, as well as the expected deadtime depending on the RoI rates

7. Firmware implementation feasibility: feasibility of the firmware implementation including the resource usage in FPGA

8. Cost: cost of chips, engineering, and algorithm development

9. Risk: risk on the availability of the chips and possible future change in the cost

10. Power consumption: power consumption depending on the RoI and MDT hit rates

8.6.6 Transverse Momentum Evaluation

For each RoI, the track fitter receives up to three segments from the three stations.<fnref n="1" /> It evaluates the transverse momentum $p_T$ with the variables described in Section 8.6.1.

The applicability of the different methods is mostly defined by the detector structure geometry and the limited detector coverage in specific areas of the muon spectrometer in addition to the muon trigger acceptance. Using offline reconstructed muons of medium quality

<footnote n="1">¹ In the transition region up to four stations may be crossed by a muon and can be handled.</footnote>
from a single muon MC sample, the method applicability can be studied as a function of
the η, φ position along the spectrometer. The study shows that for 73% of muons the three-
stations method is applicable, and for 21% only the two-stations method is applicable. The
remaining 6% of the muons where neither methods is applicable are mostly concentrated
in the very forward region of |η| > 2.6 and the calorimeter service region at |η| ≃ 0.

In terms of performance, the sagitta method relies on the accuracy of the track segment
position reconstruction while the accuracy of the method that uses the deflection angle is
dependent on the angle resolution of the reconstructed track segments. Both the sagitta
and the deflection angle are correlated with the muon p<sub>T</sub> and the magnetic field. No pre-
cise magnetic field map is required because the momentum dependency on the deflection
of the muon trajectory can be parameterised with simple parabolic functions depending on
η and φ [8.21]. Figure 8.40 shows the p<sub>T</sub> resolutions of the reconstructed muon, using off-
line reconstructed segments as input, and applying the sagitta or deflection angle and the
parameterisation mentioned above to extract the p<sub>T</sub>. The p<sub>T</sub> resolution obtained for 20 GeV
muons is ~ 6%.

<figure><img src="image_162.png" /><figcaption>Figure 8.40: Resolution of p<sub>T</sub> as a function of the offline muon p<sub>T</sub>, defined as the standard deviation from a Gaussian fit to the p<sub>T</sub> imbalance between the reconstructed muon momentum as described in the text and the offline muon momentum. The values are obtained from MC samples with no pile-up. For the "sagitta or deflection angle" method, when track segments in three stations are available the sagitta is used, otherwise the deflection angle, computed using track segments in two stations, is used.</figcaption></figure>
### 8.6.7 Realtime Output Data Format

One 48-bit word is used for each muon candidate selected by the MDT Trigger Processor and sent back to the Sector Logic. The contents of the data word are the same as those for the data transfer from the Sector Logic to the Level-0 MUCTPI shown in Table 8.11.

### 8.6.8 Readout Path

In addition to the trigger processing described above, the MDT Trigger Processor will transfer to the DAQ all MDT hits matched to the L0A. Since the L0A rate foreseen is 1 MHz and the MDT maximum drift time is ~ 760 ns, close to 100% of the MDT hits will be transferred to the DAQ. The system must be able to process ≈ 1.2 GHz MDT hit rate per sector, buffer them for 10 µs L0A latency (or 35 µs which is the L1A latency for the evolution scenario) and match the hits within ≈ 760 ns window to 1 MHz L0A. A block diagram of the proposed DAQ logic for one sector is shown in Fig. 8.41. In order to handle the expected MDT data volume, 16 window-match processors and six FELIX links at 100% utilisation would be adequate. For safety, 12 links are foreseen. The multiplexer should aim to keep groups of hits assigned to one L0A together and in time order. A large buffer, implemented in a separate memory bank, is required to store data before transferring to FELIX. The data is transmitted up to 12 FELIX links using load-balancing to send roughly equal bandwidth across all links. The data format of the data received from the CSM and transmitted to FELIX depends on the final technology choice of the CSM and final specifications of the TDC ASIC, and thus has not yet been defined.

<figure><img src="image_163.png" /><figcaption>Figure 8.41: DAQ readout path for MDTs for one sector.</figcaption></figure>
### 8.6.9 Resource Estimates

A preliminary estimate of FPGA resources required to implement the design with the segment reconstruction based on the Legendre transform is given in Tables 8.13 and 8.14. For the main blade FPGA, the resources given in Table 8.13 represent a small fraction of the available resources in e.g. a Virtex UltraScale XCVU125 device, which is one of the small available parts with the required number of high-speed links. For the mezzanine FPGAs, the best choice currently is the Kintex UltraScale XCKU115. A preliminary estimate of the power consumption for a blade results in ≈ 250W, which is comfortably lower than the 350W limit.

<table><caption>Table 8.13: Preliminary FPGA resource estimate for ATCA blade. Note that this estimate includes resources which could be split between the main UltraScale-class FPGA and the logic fabric on the Zynq®.</caption><caption>Main Blade FPGA</caption><thead><tr><th>Function</th><th>Number</th><th>LUTs</th><th>Regs</th><th>BRAMs</th></tr></thead><tbody><tr><td>GBT-FPGA Inputs</td><td>54</td><td>71,000</td><td>51,000</td><td>0</td></tr><tr><td>Tube Number LUT</td><td>18</td><td>150</td><td>150</td><td>220</td></tr><tr><td>RoI Processing</td><td>57</td><td>7800</td><td>7800</td><td>0</td></tr><tr><td>Hit Calibration</td><td>54</td><td>1000</td><td>1000</td><td>1000</td></tr><tr><td>Hit Extraction</td><td>54</td><td>1000</td><td>1000</td><td>0</td></tr><tr><td>DAQ (VERY preliminary)</td><td>18</td><td>18,000</td><td>18,000</td><td>100</td></tr><tr><td><strong>Total</strong></td><td></td><td>99,000</td><td>79,000</td><td>1400</td></tr><tr><td>%Use (XCVU125)</td><td></td><td>14.0%</td><td>4.3%</td><td>28.0%</td></tr></tbody></table>

<table><caption>Table 8.14: Preliminary FPGA resource estimate for mezzanine board. This estimate is for three Legendre segment finder engines, handling inputs from three MDT stations. We expect these three to fit in one large FPGA (e.g. XCKU115). The mezzanine board will contain three such FPGAs which can operate in parallel to handle multiple simultaneous RoIs.</caption><caption>Mezzanine FPGA (1 of 3)</caption><thead><tr><th></th><th>Number</th><th>LUTs</th><th>Regs</th><th>BRAMs</th></tr></thead><tbody><tr><td>Legendre Engine</td><td>3</td><td>96,500</td><td>104,500</td><td>275</td></tr><tr><td><strong>Total</strong></td><td></td><td>289,000</td><td>313,500</td><td>825</td></tr><tr><td><strong>XCKU115</strong></td><td></td><td>663,360</td><td>1,326,700</td><td>4,320</td></tr><tr><td><strong>%Use</strong></td><td></td><td>44%</td><td>24%</td><td>19%</td></tr></tbody></table>

## 8.7 Latency Estimates

This section describes the latency estimates for the Level-0 Muon Trigger System. The values of CBE are shown throughout the section. The uncertainty and a margin are assigned
for each item, and MEV and MPV are obtained from the sum with CBE (Table 5.5). The latencies related to the optical links, including the serialisation, the optical transmission, and the deserialisation, are accounted on the transmitter side. This definition leads to slight difference from the values shown in other TDRs [8.1][8.22].

Estimations on the latency for the on-detector electronics of the new RPC and TGC systems are described in Ref. [8.1]. The latency from the RPC signal arrival at the on-detector boards named DCT to the RPC signal arrival at the barrel off-detector boards where the Sector Logic is implemented is shown as 0.725 µs. By taking a sum with the latency from the bunch crossing to the signal arrival at DCT, a latency estimate from the bunch crossing to the RPC signal arrival at the barrel off-detector boards is obtained to be 1.110 µs. The estimated latency from the bunch crossing to the TGC signal arrival at the endcap off-detector boards where the Sector Logic is implemented is 0.888 µs.

An estimate on the latency for the on-detector electronics of the new MDT system is also described in Ref. [8.1]. The latency for each MDT hit to arrive at the MDT Trigger Processors depends on the hit rate and the drift time of the hits. The latency estimate from the bunch crossing to the arrival of the latest MDT hits at the off-detector boards for possible maximum hit rate and drift time is shown as 2.137 µs. After the submission of Ref. [8.1], a further study of the latency was performed with a simulation based on the hardware description language. The maximum cable length has been updated to 90 m. The maximum value of the sum of the drift time and the propagation time has also been updated to 800 ns. The updated estimate on the latency from the bunch crossing to the arrival of the latest MDT hits at the off-detector boards is 2.358 µs. The value for the earliest MDT hits is 0.609 µs.

An estimate on the latency from the bunch crossing to the arrival of the NSW track segment at the Endcap Sector Logic for the Phase-I system is shown in Ref. [8.4] to be 41 clock ticks, corresponding to 1.025 µs. After further studies, the originally estimated value is found to be small. The current best estimate for the Phase-I system is 47 clock ticks, corresponding to 1.175 µs. For the Phase-II system, a value 1.425 µs is assumed. The additional latency is exploited for the upgrade of the algorithm of the NSW segment reconstruction. An estimate on the latency from the bunch crossing to the arrival of the Tile calorimeter energy flags at the Sector Logic is 1.425 µs [8.22].

Table 8.15 shows an overview of the estimate on the latency of the Level-0 Muon Trigger System for HL-LHC, including the on-detector and off-detector parts. After receiving the RPC and TGC hit signals, the Sector Logic processes the signals and provides primitive muon track candidates. A selection is applied on the primitive muon track candidates based on the information from NSW and the Tile calorimeter, and the results are sent to the MDT Trigger Processors. A latency estimate for the Sector Logic track candidate arrival at the MDT Trigger Processor is 1.675 µs. After that the MDT Trigger Processor starts further selection of the muon track candidates based on the MDT hits, and the results are sent to the Sector Logic. A latency estimate for the arrival of the muon track candidates at the
Sector Logic is 3.810 µs. A latency estimate for the Level-0 muon track candidate arrival at the Level-0 MUCTPI is 4.010 µs.

<table><caption>Table 8.15: Overview of the best estimate on the latency for the Level-0 Muon Trigger System for HL-LHC. The values are cumulative with the bunch crossing as the time origin.</caption><thead><tr><td>Contents</td><td>Latency</td></tr></thead><tbody><tr><td>RPC/TGC hit arrival at the Sector Logic</td><td>1.110 µs/0.888 µs</td></tr><tr><td>NSW Trigger Processor track segment arrival at the Sector Logic</td><td>1.425 µs</td></tr><tr><td>Tile calorimeter energy flag arrival at the Sector Logic</td><td>1.425 µs</td></tr><tr><td>Sector Logic track candidate arrival at the MDT Trigger Processor</td><td>1.675 µs</td></tr><tr><td>MDT hit signal arrival at the MDT Trigger Processor</td><td>2.358 µs</td></tr><tr><td>MDT Trigger Processor output arrival at the Sector Logic</td><td>3.810 µs</td></tr><tr><td>Level-0 muon track candidate arrival at the Level-0 MUCTPI</td><td>4.010 µs</td></tr></tbody></table>

Tables 8.16 and 8.17 show the estimates on the latency for the Barrel Sector Logic and the Endcap Sector Logic, respectively. After receiving the RPC hit signals, the Barrel Sector Logic processes the signals and provides primitive muon track candidates (1.360 µs). After receiving the TGC hit signals, the Endcap Sector Logic processes the signals of the TGCs in the endcap middle station and provides primitive muon track candidates (1.013 µs). The Endcap Sector Logic takes coincidence with the TGCs on the endcap inner station and also with the RPCs in the BIS78 region (1.113 µs). The Endcap Sector Logic applies a further selection with the NSW segments for $|η| > 1.3$ (1.450 µs). The Sector Logic takes coincidence with the Tile calorimeter cells for $|η| < 1.3$ (1.450 µs). Transverse momentum is evaluated and the muon track candidate is transferred to the MDT Trigger Processor (1.675 µs). The Sector Logic receives the muon track candidates from the MDT Trigger Processor (3.810 µs), and transmits the muon track candidates to the Level-0 MUCTPI (4.010 µs).

The processing time in the MDT Trigger Processor depends on the segment reconstruction algorithms. Table 8.18 shows the estimate on the latency for the baseline algorithm, where the segments are reconstructed by the Legendre transform. All MDT hit signals are transferred to a buffer with a depth of 0.967 µs after the decoding and the domain crossing which take 0.100 µs, to assure that the earliest MDT hit signals are stored until the arrival of the Sector Logic track candidates. The sum $0.967 \mu s + 0.100 \mu s = 1.067 \mu s$ is equal to the difference between the earliest MDT hit signal arrival and the Sector Logic track candidate arrival. The MDT hits which are used for further processing are extracted with the RoI provided based on the Sector Logic output (3.432 µs). The extracted hit signals are transferred to the mezzanine cards, the segments are reconstructed in the mezzanine cards, and the data of segments are transferred to the main board (3.560 µs). The muon track candidates are selected with the transverse momentum (3.635 µs). The data of selected muon track candidates are transferred to the Sector Logic (3.810 µs). If a least-square fit is applied to refine the segment angle and position, 0.500 µs is added. The estimate for the segment reconstruction based on the AM chips is 0.301 µs larger than the baseline.
<table><caption>Table 8.16: Summary table of the best estimate on the latency for the Barrel Sector Logic for HL-LHC. The values are cumulative with the bunch crossing as the time origin.</caption><thead><tr><th>Contents</th><th>Latency</th></tr></thead><tbody><tr><td>RPC hit signal arrival</td><td>1.110 µs</td></tr><tr><td>Hit signal decoding and preprocessing</td><td>1.210 µs</td></tr><tr><td>Majority logic and path reconstruction</td><td>1.310 µs</td></tr><tr><td>Combination coincidence</td><td>1.360 µs</td></tr><tr><td>Tile calorimeter energy flag arrival</td><td>1.425 µs</td></tr><tr><td>Coincidence with the Tile calorimeter cells</td><td>1.450 µs</td></tr><tr><td>Trigger candidate selection</td><td>1.475 µs</td></tr><tr><td>Transverse momentum encoding</td><td>1.500 µs</td></tr><tr><td>Optical link to the MDT Trigger Processor (10 m)</td><td>1.675 µs</td></tr><tr><td>MDT Trigger Processor output arrival</td><td>3.810 µs</td></tr><tr><td>Final trigger processing</td><td>3.835 µs</td></tr><tr><td>Optical link to Level-0 MUCTPI (10 m)</td><td>4.010 µs</td></tr></tbody></table>

<table><caption>Table 8.17: Summary table of the best estimate on the latency for the Endcap Sector Logic for HL-LHC. The values are cumulative with the bunch crossing as the time origin.</caption><thead><tr><th>Contents</th><th>Latency</th></tr></thead><tbody><tr><td>TGC hit signal arrival</td><td>0.888 µs</td></tr><tr><td>Coincidence of the TGCs on the endcap middle station</td><td>1.013 µs</td></tr><tr><td>Coincidence with the TGCs on the endcap inner station</td><td>1.063 µs</td></tr><tr><td>Coincidence with the RPCs in the BIS78 region</td><td>1.113 µs</td></tr><tr><td>NSW track segment and Tile energy flag arrival</td><td>1.425 µs</td></tr><tr><td>Selection with the NSW and Tile data</td><td>1.450 µs</td></tr><tr><td>Trigger candidate selection</td><td>1.475 µs</td></tr><tr><td>Transverse momentum encoding</td><td>1.500 µs</td></tr><tr><td>Optical link to the MDT Trigger Processor (10 m)</td><td>1.675 µs</td></tr><tr><td>MDT Trigger Processor output arrival</td><td>3.810 µs</td></tr><tr><td>Final trigger processing</td><td>3.835 µs</td></tr><tr><td>Optical link to Level-0 MUCTPI (10 m)</td><td>4.010 µs</td></tr></tbody></table>

## 8.8 R&D Items

R&D is needed to establish the final design of the components of the Level-0 Muon Trigger System. The schedule of the designing, the prototype development, and the demonstration is summarised in Chapter 19. The R&D items which can be worked on with evaluation boards or custom test boards available before full prototypes should be basically completed
<table><caption>Table 8.18: Summary table of the best estimate on the latency for the MDT Trigger Processor for HL-LHC. Segment reconstruction based on the Legendre transform is assumed. The values are cumulative with the bunch crossing as the time origin.</caption><thead><tr><td>Contents</td><td>Latency</td></tr></thead><tbody><tr><td>Earliest MDT hit signal arrival</td><td>0.609 μs</td></tr><tr><td>Sector Logic track candidate arrival</td><td>1.785 μs</td></tr><tr><td>Latest MDT hit signal arrival</td><td>2.358 μs</td></tr><tr><td>Decoding and domain crossing</td><td>2.458 μs</td></tr><tr><td>Buffering</td><td>3.424 μs</td></tr><tr><td>Hit extraction</td><td>3.432 μs</td></tr><tr><td>Data transfer to the mezzanine cards</td><td>3.457 μs</td></tr><tr><td>Segment reconstruction</td><td>3.510 μs</td></tr><tr><td>Conversion to the detector coordinates</td><td>3.535 μs</td></tr><tr><td>Data transfer to the main board</td><td>3.560 μs</td></tr><tr><td>Transverse momentum evaluation and selection</td><td>3.635 μs</td></tr><tr><td>Optical link to the Sector Logic (10 m)</td><td>3.810 μs</td></tr></tbody></table>

before PDR, which will take place component by component from 2020. The R&D items which require prototype developments should be worked on with prototypes and the final design should be prepared around FDR, which will take place component by component from 2021. The main R&D issues are shown in the following.

* Detailed design of the Sector Logic should be provided and demonstrated, including the logic of the RPC coincidence, the TGC track segment reconstruction, the requirement on the angle difference between the TGC and NSW track segments, and the coincidence with the Tile calorimeter. For the barrel, possibilities of a three point sagitta measurement to improve the momentum resolution and a tighter timing cut to suppress the accidental coincidence will be studied. For the endcap, a possibility of the coverage extension from $1.05 < |\eta| < 2.4$ to $1.05 < |\eta| < 2.7$ by a coincidence between NSW track segments and TGC hits will be studied. The acceptance for the exotic signatures will be investigated, and dedicated logic will be prepared if appropriate.

* Detailed design of the NSW track segment reconstruction in the NSW Trigger Processor should be provided and demonstrated. A combined reconstruction with the sTGC and MM hits will be designed. The logic will be tuned with the efficiency, the angle and position resolution, and the fake segment reconstruction rate.

* Detailed design of the MDT Trigger Processor should be provided and demonstrated. The hit extraction, the track segment reconstruction, and the transverse momentum evaluation require the demonstration. For the track segment reconstruction, the performance of the different algorithms will be carefully studied and an algorithm will be selected based on the results (see Section 8.6.5).
* Trigger logic to suppress multiple track candidates for single muon should be designed. The chamber overlaps will be carefully taken into account in the logic.

* Dependence of the trigger logic on the pile-up should be studied, and the logic less sensitive to the pile-up should be established.

* Precision of the resource estimation for the Sector Logic, the NSW Trigger Processor, and the MDT Trigger Processor should be improved with detailed design of the trigger logic. The trigger logic will be optimised to minimise the required resource.

* Detailed design of the readout logic should be provided and demonstrated.

* Data flow including ~ 100 input and output links and internal flow of FPGA should be demonstrated.

* Detailed design of the control functions for the on-detector boards of RPC, TGC, and MDT should be provided and demonstrated. The design of the control functions for the off-detector boards with Zynq® devices should also be provided and demonstrated.

* Latency estimation with the detailed trigger logic should be provided and demonstrated.

* Precision of the estimation for the power consumption should be improved with the detailed design of the trigger logic, the readout logic, and control functions.

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<figure><img src="image_164.png" /></figure>
# 9 Global Trigger

## 9.1 Introduction

The design goal of the Global Trigger subsystem is to bring Event Filter (Event Filter)-like capability to the Level-0 trigger system. Unlike the other hardware trigger upgrades, the emphasis in the Global Trigger is overwhelmingly on firmware rather than on hardware. Topologically the Global Trigger consists of a layer of incoming multiplexing MUX nodes<fnref n="1" /> feeding data into a layer of GEP processing nodes, where each GEP node receives the complete trigger data for an event, followed by a demultiplexing CTP Interface node providing the output to the CTP, illustrated in Fig. 9.1. Physically each node corresponds to one of the two large FPGAs on a Global Common Module (GCM). This is a natural step in the evolution away from custom hardware towards functionality being provided in firmware or software.

<figure><img src="image_165.png" /><figcaption>Figure 9.1: Illustration of the Global Trigger system processing and trigger decision flow.</figcaption></figure>

The overall design of the ATLAS Global Trigger is analogous to that of the successful Run 2 CMS Calorimeter Trigger upgrade [9.1] and learns from the experience with the commissioning of the ATLAS FTK and L1Topo subsystems. The use of common hardware, the GCM, simplifies system design and long-term maintenance, and minimises the complexity

<footnote n="1">¹ Throughout this chapter the term node is used in this topological sense and corresponds to a single large FPGA running a common firmware infrastructure into which the specific firmware for a particular function is embedded.</footnote>
of the firmware. Employing a common firmware framework, illustrated in Fig. 9.2, with rigorous interfaces minimises interference between firmware for different trigger algorithms. This also allows the firmware to be factorised along the lines of the HLT Trigger Signatures which simplifies organisation and improves overall support for software development and performance studies.

<figure><img src="image_166.png" /><figcaption>Figure 9.2: *Global Trigger system firmware flow and interfaces.*</figcaption></figure>

The design amalgamates the complete trigger data for each event onto a separate GEP processing node. This concentration of data maximises flexibility by minimising the distributed processing of data within the system. As the number of input fibres into the system far exceeds the capability of any single device, the data are time-multiplexed such that data corresponding to a particular BC are received by an incoming multiplexing (MUX) layer and re-transmitted over a number of BC to the single GEP destination. Suitable ordering of the data by the MUX for this long transmission allows two-dimensional data to be processed by a one-dimensional algorithm on the GEP node as the data arrive, which can reduce the FPGA resource usage for sliding window algorithms by some two orders of magnitude over the traditional regional implementation. The relatively long time to transmit the data moreover decouples each node from the LHC BC rate, allowing asynchronous complex algorithms including those based on machine learning techniques. These can more closely emulate trigger processing in the Event Filter, and provide additional triggering flexibility beyond what is currently feasible with the Phase-I hardware trigger.

### 9.1.1 Requirements for the Global Trigger System

The baseline requirements for the Global Trigger can thus be defined:

* receive and process trigger primitives from calorimeter subsystems to produce trigger objects (TOBs);

* receive TOBs from the L0Calo FEX system and from L0Muon (via the MUCTPI);

* multiplex input data for serial transmission and processing;

* apply EF-like trigger algorithms and hypotheses on suitable selections of these TOBs;
<figure><img src="image_167.png" /><figcaption>Figure 9.3: The functional design of the Global Trigger system, illustrating the detector inputs, multiplexing MUX layer, multiplexed event-processing GEP layer, demultiplexing CTP Interface, and connections to other systems.</figcaption></figure>

* transmit the resultant Global Trigger trigger input bits (TIP) to the CTP for processing.

The trigger hypotheses to be constructed will include those based on object multiplicities, energy thresholds, and topological relationships of objects. The resultant TIP contains flag bits indicating which Global algorithm requirements have been satisfied and may also include multiplicities of identified objects.

This structure thus subsumes and surpasses the functionality of the Phase-I L1Topo modules. In addition to the minimal requirements, extended physics opportunities have also been identified:

* the internal time-multiplexed implementation removes the limitation on the number of TOBs from the FEX and MUCTPI systems present in the Phase-I hardware trigger;

* the access to cell level data from the calorimeters at 40 MHz allows for improved trigger object definitions using clustering algorithms that cannot be implemented in the FEX systems; and,

* the time-multiplexed architecture decouples the GEP node from the LHC BC rate thereby allowing the use of asynchronous and iterative high-level algorithms impossible in the Phase-I hardware trigger.

## 9.1.2 Overview of Global Trigger System Design

The architecture of the Global Trigger can be seen in Fig. 9.3, and consists of three primary components: a MUX system, a GEP system, and a demultiplexing CTP Interface.
As illustrated in Fig. 9.4, each input detector and trigger system sends its data every BC with one packet per optical fibre to MUX nodes. The MUX receives these data packets from all the input optical fibres synchronously, collects and reorganises them, and then starts transmitting all of the event data from a specific BC to a GEP node. At the next BC the data for the next event are captured into the MUX buffers for the next GEP node and transmission of the data to that node begins.

<figure><img src="image_168.png" /><figcaption>Figure 9.4: Multiplexing of incoming synchronous data into the GEP layer. Each MUX node receives data from all the input optical fibres synchronously every BC, collects and reorganises them, and then starts transmitting all of the event data from a specific BC to a GEP node. Each GEP node takes up to 48 BC to receive the event. Results from the GEP are sent to the CTP Interface where they are demultiplexed and sent to the CTP.</figcaption></figure>

The time-multiplexed signals are transported to one of many GEP nodes over many BC where the inputs are processed by trigger algorithms, as illustrated in Fig. 9.4. The time required to transmit these data from the MUX to the GEP is a function of the number of optical fibres incident upon a given MUX, the number of GEP nodes, and the speeds of the data-sources-to-MUX and MUX-to-GEP links. With the 48 GEP nodes as described in Section 9.4.2, the inputs for the entire Global Trigger can then be mapped onto a single GEP node. The GEP nodes handle every BC in a round-robin fashion, with each one starting to receive a new event every 48 BC. The data for an event then takes up to 48 BC to be transferred from each MUX to the GEP node, before the data for the next event for that GEP node are captured. The processing on the GEP node can thus be decoupled from the LHC clock.

Suitable ordering of the data by the MUX for this long transmission can allow processing on the GEP node to begin as soon as first data arrive. Using the time of data transmission to scan across the full calorimeter allows two-dimensional data to be processed by a one-dimensional algorithm on arrival in the GEP. For example, having the MUX layer send data ordered in $\eta$ means that the GEP node can process that data in complete $\phi$ rings. This enables immediate regional processing as the data arrives, and the time for data transmission can then be exploited for regional data processing, including $\phi$-ring based pileup suppression, before starting iterative algorithms that require the full event to have been received. Ordering the data geometrically allows all algorithms to be fully pipelined which, in FPGAs, means that: processing is localised, fan-outs are reduced, routing delays are
<figure><img src="image_169.png" /><figcaption>Figure 9.5: Spatial pipelining of data into a GEP node. The 2D algorithm is reduced down to operations in a single dimension or localised 2D operations spread over time.</figcaption></figure>

minimised, and register duplication is eliminated. For any sliding-window algorithm this drastically reduces the FPGA resource usage as the 2D algorithm is reduced down to operations in a single dimension or localised 2D operations spread over time as illustrated in Fig. 9.5. The output from this stage can be pipelined into the next stage of the algorithm which can be similarly pipelined. This can reduce the FPGA resource usage for algorithms such as topoclustering described in Section 9.3.3 by some two orders of magnitude over the full-plane implementation.

Objects produced by the Global Trigger algorithms running on the GEP nodes are buffered for readout (via FELIX) while the resulting TIP are sent to the CTP Interface. The CTP Interface demutiplexes the TIP, re-synchronising the data stream to the LHC beam clock, so that it can be transmitted to the CTP on the correct BC.

Global Trigger thus builds upon the information available in the L0Calo and L0Muon sub-systems and uses zero-suppressed full granularity cell information ($|E_T| > 2\sigma$) from the calorimeters. It will perform event selection using a wide range of sub-detector trigger primitives (summary data on position and magnitude of energy depositions) allowing refined selections on electrons, taus, jets, $E_T^{miss}$, and muons.

## 9.2 Global Trigger Interfaces

The Global Trigger will receive inputs from the calorimeter and muon detector subsystems, as well as the L0Calo FEX trigger processors. The resultant Global Trigger TIP will be sent directly to the CTP system and to the Event Filter via FELIX. In addition to the TIP that
is sent to the CTP, FELIX has to receive all data necessary to support the EF processing, offline data analysis and monitoring. This includes a compact data structure that maps TIP items (flags or multiplicities) to the TOBs that contributed to these items. These interfaces are illustrated schematically in Fig. 9.3. All external interfaces on the realtime path are synchronous to the LHC clock, such that the MUX system and CTP Interface encapsulate the asynchronous time-multiplexed GEP system.

### 9.2.1 Calorimeter Subdetector Inputs

The Global Trigger will receive data from the LAr and Tile calorimeter subsystems every LHC bunch-crossing. The LAr Signal Processor (LASP) and Tile TDAQ Interface (TDAQi) will provide zero-suppressed cell information ($|E_T| > 2\sigma$) that will further be processed by a clustering algorithm (described in Section 9.3.3) to provide extended calorimeter information to the GEP algorithms.

### 9.2.2 L0Calo Inputs

The Global Trigger will receive the TOBs from the eFEX, jFEX, and gFEX processors every BC, providing pre-processed calorimeter features that can be implemented directly as seeds in trigger algorithms. Each TOB provides an object type ($e/\gamma$, $\tau$, jFEX jets, gFEX jets) and measurements of energy, $\eta$ and $\phi$.

### 9.2.3 L0Muon Inputs

The Global Trigger will receive the muon-track candidate information (TOBs) from the L0Muon trigger via the MUCTPI every BC. The muon track-candidates will contain information on candidate $p_T$, $\eta$ and $\phi$.

### 9.2.4 Central Trigger Processor Outputs

The Global Trigger will produce a 1024-bit TIP representing the results of the Global Trigger algorithms every BC. The TIP is made up of flags and multiplicity values, the meaning of each bit field being defined by the configuration of the Global Trigger and the CTP. The flags may indicate the presence of an individual object passing the corresponding criteria (e.g. $p_T$ threshold requirement), or more complex requirements on combinations of objects (e.g. invariant mass and charge-sign requirements on pairs of muons). Multiplicity values can be sent to the CTP counting objects passing criteria such as $p_T$ thresholds and isolation cuts. The Global Trigger TIP is produced on the GEP node processing the event and then demultiplexed in the CTP Interface and sent to the CTP.
### 9.2.5 Front-End LInk eXchange (FELIX) Inputs and Outputs

The Global Trigger will have an output interface to the FELIX system from every GEP module for the readout of the TIP and other trigger information. The MUX modules and CTP Interface will also have output links, but in the normal course of running these will only be used for reporting errors. Every module must also receive clock, configuration, and per-event TTC information from FELIX, as well as the Level-0 (and in the evolved scheme Level-1) trigger-accept signals.

For every L0A the Global Trigger will produce a compact data structure mapping the TIP onto the TOBs which caused those TIP bits to be fired as part of the readout data. This will allow the Event Filter to quickly identify the TOBs which caused the L0A and hence the RoI requiring regional tracking. All intermediate objects produced by the algorithms will also be read out, including the topoclusters, jets, and other derived TOBs. However, as with the L0Calo FEX modules, the full input data will in general not be read out from the Global Trigger; rather the data will be read out at their respective sources and the integrity of the data will be confirmed by suitable checksums.

### 9.2.6 Configuration and Control, Interface to Detector Control System

On power up each module in the Global Trigger will be configured from local SPI flash. Each module will have an Ethernet interface and IPbus will be used to control the operation of all FPGAs, allowing steering of the system, parametric control of the algorithms and control of the high-speed links. This interface will further support remote programming of the FPGA and SPI flash along with access to playback and spy memories attached to the real-time path and environmental monitoring such as currents, temperatures and voltages. Low-level, ATCA-compliant control will be achieved by an ATLAS standard IPMC module communicating with DCS via the ATCA Shelf Manager.

## 9.3 Trigger Strategy and Algorithms

The trigger strategy for the Global Trigger will use a two stage processing scheme, as illustrated in Fig. 9.1. In the first stage, the GEP node receives the fine-granularity calorimeter data and processes them in algorithms that produce inputs to the second stage of the trigger processing. The first stage also receives the TOBs from the L0Calo and L0Muon systems. In the second stage the Level-0 TOBs provide a seed for the calculation of electron/photon, tau, anti-$k_t$ jet, and muon trigger candidates, which are refined using topological clusters and isolation information and combined in more complicated hypotheses such as topological relationships.
More specifically, TOBs from the FEX and MUCTPI systems can be further processed with the topocluster and LAr first-layer strip information to produce refined trigger objects. Using jFEX and gFEX jets as RoI seeds, jets can be clustered using topoclusters with an anti-$k_t$ algorithm (as described in Section 9.3.4). Event-by-event local pile-up suppression for jets using baseline subtraction techniques comparable to those developed for offline analyses can be applied. At this stage of processing, boosted-jet and jet substructure information can be extracted for use in the Global Trigger calculations. Similarly, the eFEX TOBs provide seeds for electron, photon, and tau identification wherein topoclusters and LAr first-layer strip information can be used to calculate longitudinal and transverse energy distribution with improved resolution and for particle isolation. The topoclusters can further be used to extend electron identification to forward regions ($|η| > 2.4$). With access to the full list of muon trigger information from the MUCTPI, additional processing of muon candidates can proceed at the GEP. Muon isolation with topocluster and strip information will further improve background rejection. Global event observables will be calculated using topoclusters and muons, including $H_T$ and $E_T^{miss}$.

Each of these refined objects and global observables will provide input to the extended
trigger hypotheses evaluated by the GEP. Thresholds will be defined for each object or
combinations of objects (multiplicity and $E_T$ thresholds), corresponding to a series of hypo-
theses. Topological conditions based on the spatial relationship and energies of objects can
also be defined, for example (n-)jet+$E_T^{miss}$ triggers with specific $\Delta\phi$(jet, $E_T^{miss}$) requirements.
Specialised algorithms to support B physics and heavy ion physics are also anticipated to
be included for the GEP. The results of these hypotheses are passed to the CTP Interface.

### 9.3.1 Algorithm Performance

Preliminary studies of the Global Trigger system algorithm performance have been per-
formed. Descriptions of the preliminary algorithms are included below in this section, and
a description of the resultant trigger performance is given previously in this document for
topological clusters (Section 6.2), electrons and photons (Section 6.3), taus (Section 6.5) and
jets (Section 6.6).

### 9.3.2 Algorithm Implementation

These algorithms will be implemented on FPGAs, which will require significant modifications compared to any "normal" offline algorithms that have iterative sequences of steps. The original iterative processing steps can be redesigned as a single processing step that can be pipelined in parallel threads on the FPGA. The FPGA implementations of these algorithms will be constrained by the FPGA logic resources and by the maximum allowed latency. As these FPGA algorithms are developed, the number of clock cycles required per
iteration and the FPGA resources required by the algorithm are metrics for the overall performance of the algorithm. Optimising on these metrics allows the Global Trigger to maximise the number of algorithms that can operate simultaneously. Prototype algorithms for the GEP are expected to have a strategy for processing data (parallel, sequential or mixed). Bit-wise simulation of each algorithm to reproduce online results will be required to study and optimise algorithm physics performance and precision.

In this section, two proposed algorithms are described, which are expected to be the most FPGA resource intensive: topological clustering of calorimeter cell information and the “anti-$k_t$” jet-finding algorithm (see also Section 6). These algorithms represent important algorithms that are desired for the Global Trigger and provide benchmarks for the implementation metrics mentioned above. The topoclustering algorithm is a prerequisite for many of the other algorithms anticipated to be utilised in the GEP. The anti-$k_t$ jet-finding algorithm is an example of a challenging case of translating a highly-iterative algorithm to the FPGA environment. A third algorithm, which uses $E_{ratio}$ calculated using the LAr strips to form isolation variables, yields large factors of background rejection and is readily adaptable to implementation in FPGA. This algorithm’s physics performance potential is described in Section 6.3, but the firmware implementation is not yet ready for a detailed description here.

The topoclustering and strip isolation algorithms are targeted to achieve a small utilisation of 1-2% of the proposed FPGA logic resources with a low algorithm latency (<1 µs). The anti-$k_t$ jet-finding algorithm is expected to have a larger resource utilisation (10-20% of the proposed FPGA logic resources) and a longer latency. The total latency goal for producing topoclusters and processing with the anti-$k_t$ jet-finding algorithm is <2.5 µs, leaving a margin of roughly 1 µs on further trigger processing. The description of the algorithms below includes estimates of the performance metrics, which indicate that it will be possible to implement the suite of required algorithms together with the additional necessary firmware (control logic, data flow, readout, etc.) while respecting the constraints on latency and FPGA logic/memory resources.

### 9.3.3 Topological Clustering

ATLAS uses clusters of topologically connected calorimeter-cell signals (topoclusters) as its principle signal definition for use in the reconstruction of isolated hadrons, jets, and hadronically-decaying $\tau$ leptons [9.2]. In addition, topoclusters are used to represent the energy flow from soft particles which is needed for the reconstruction of $E_T^{miss}$ and for establishing the isolation of leptons. Individual topoclusters are not expected to contain the entire response to a single particle. Rather, depending on the incoming particle types, energies, spatial separation, and cell signal formation, individual topoclusters represent the full or fractional response to a single particle, the merged response of several particles, or a combination of merged full and partial showers. Topoclusters, which are at the electromagnetic
<figure><img src="image_170.png" /><figcaption>Figure 9.6: Distribution of the number of topoclusters inside anti-$k_T$ jets formed with $R = 0.4$ in the (left) barrel ($|\eta| < 0.6$), (central) endcap ($2.0 < |\eta| < 2.5$) and (right) FCal ($3.5 < |\eta| < 4.5$) regions of the ATLAS calorimeter, generated with a minimum $E_T$ threshold of 1 GeV for all topoclusters.</figcaption></figure>

energy scale, can be further calibrated using a local cluster weighting scheme (LCW) [9.3] that relies on the shape of the topocluster that reflects the type of incident particles.

The algorithm to build topoclusters uses the spatial distribution of cell signals in all three dimensions to establish connections between neighbouring cells to reconstruct the energy and directions of the incoming particles. Calorimeter cells with insignificant signals, not connected to neighbouring cells with significant signals, are considered noise and discarded from further use in jet, particle, and $E_T^{\text{miss}}$ reconstruction. A detailed description of the algorithm together with its performance can be found in Ref. [9.2]. Essentially the same algorithm is used to reconstruct topoclusters as in the EF and offline, albeit most likely based on $E_T$ rather than $E$. A first pass selects contiguous groups of cells with energy measurement exceeding two times the expected noise ($|E_T| > 2\sigma$) containing at least one seed cell with energy measurement exceeding four times the expected noise ($|E_T| > 4\sigma$). Such clusters are referred to 422 topoclusters (occasionally as 42 topoclusters). In the EF and offline all cells on the periphery of this topocluster are then added regardless of their energy significance (these topoclusters are referred to as 420 topoclusters). This provides a first mitigation of the impact of pileup at the cluster level. However, the resulting topoclusters might be too large to properly reflect local energy flow. In such cases, topoclusters will be split between the various local energy maxima above threshold in a second splitting step. The number of topoclusters reconstructed per event can be seen in Fig. 9.8 for both 420 and 422 algorithms, and for various $E_T$ thresholds on the clustered cells. This is particularly problematic in the FCal where a large fraction of jets are built from a single topocluster (Figures 9.6 and 9.7). Producing useful jets in this environment will be very expensive in terms of FPGA resources and latency. For this reason, the FCal detector region is treated by a dedicated electronics module, the fFEX, which is described further in Section 7.3.4.

The first stage of the GEP processing includes algorithms that build topoclusters. However, the offline topoclustering algorithm is an iterative algorithm in which calorimeter seeds are
<figure><img src="image_171.png" /><figcaption>Figure 9.7: Event display of a typical VBF quark jet in FCAL1 at $\mu = 200$.</figcaption></figure>

<figure><img src="image_172.png" /><figcaption>Figure 9.8: Multiplicity of topoclusters for 420 and 422 threshold algorithms (the latter labeled as 42), including variations of $E_T$ threshold requirements on the clustered cells. The left plot is for topoclusters within $|\eta| < 3.2$ and the right plot is for forward topoclusters ($|\eta| > 3.2$).</figcaption></figure>
<figure><img src="image_173.png" /><figcaption>Figure 9.9: Channel occupancy per LASP unit for minimum bias events, high-energy dijet events, and high-mass $Z^0 \to t\bar{t}$ events at $\mu = 200$. (left) LASP occupancy in the EMEC region $1.6 < |\eta| < 2.4$. (right) occupancy of a LASP unit covering $1.0 < |\eta| < 1.4$ of the EMB front layer and $|\eta| < 1.4$ of the EMB back layer. Each LASP unit is planned to process up to 512 cells. Figure extracted from [9.4].</figcaption></figure>

chosen, then additional cells are iteratively associated with the seeds based on a series of energy thresholds. To adapt such an algorithm to the FPGA environment, two primary challenges must be overcome: first, the large calorimeter data volume must be managed such that the algorithm can be parallelised to the greatest extent possible, and second, a non-iterative algorithm can be designed that satisfies FPGA resource and latency restrictions. The large volume of the fine-granularity calorimeter data represents a significant challenge in meeting the FPGA resource usage target. One important reduction in the data volume is the decision to exclude cells with $|E_T| > 2\sigma$ so that only 422-type topoclusters can be build on the GEP. On average, this corresponds to a fraction of cells of $\approx 5.5\%$ [9.4] or $\approx 30$ cells out of the 512 cells processed per LASP. However, for some events — especially events with noise bursts or other abnormal conditions — the fraction of high-energy significance cells can easily exceed this average value (Fig. 9.9). A contingency of 30% (153 out of 512 cells) has been assumed for bandwidth estimates. Two solutions are proposed in case this fraction is exceeded: sending cells ordered in energy until output bandwidth saturates, or sending large event fragments in an asynchronous mode to the MUX. If the number of cells is too large, then a forced accept should be issued and a mitigation of accept signals caused by regional calorimeter noise bursts is under investigation.

Processing challenges remain even with this significant reduction in the number of calorimeter cells. To address this, a dual serial-parallel data processing technique has been designed, which dramatically reduces the FPGA resources required. This implementation takes advantage of the serial delivery of calorimeter-cell input data to the GEP. Thus the topological clustering algorithm would receive one $\eta$ data slice at a time. In addition, various cluster granularities have been studied to understand the balance between the algorithm's physics performance and FPGA resource usage. Granularities at the level of calorimeter cells, super-cells ($\Delta\eta \times \Delta\phi = 0.025 - 0.1 \times 0.1$, varying by longitudinal layer), jFEX towers ($\Delta\eta \times \Delta\phi = 0.1 \times 0.1$, summed longitudinally), and gFEX towers ($\Delta\eta \times \Delta\phi = 0.2 \times 0.2$,
summed longitudinally) have been considered. In the following, we use the terminology "cell" to describe the smallest granularity of unique calorimeter data inputs used in the topoclustering algorithm, though the actual implementation could be a more coarse granularity. The calorimeter inputs are pre-processed to identify cells above a seed threshold energy, and all seeds are processed in parallel. Each longitudinal calorimeter layer is also processed in parallel, and the final output is formed by summing cluster energies from each layer. The output is thus the energy of the clustered object around each seed. In the event that two or more neighbouring seeds could be included in each other's clustered region, all clusters are generated and output to the next stage of GEP processing.

<figure><img src="image_174.png" /><figcaption>Figure 9.10: Example of the pseudo Linear Slice Thresholding (LST) topological clustering algorithm that could be implemented in the GEP.</figcaption></figure>

<figure><img src="image_175.png" /><figcaption>Figure 9.11: Illustration of the three topoclustering algorithm variants currently under study.</figcaption></figure>

Three versions of the topoclustering algorithm have been developed for the GEP: a Windowing algorithm, a pseudo Linear Slice Threshold (LST) algorithm, and a Spiral algorithm. Each algorithm variant is being studied for resource/latency requirements as well as physics performance. All three variants meet the target resource and latency goals. To illustrate the topoclustering algorithms, the LST algorithm is shown in Figures 9.10 and 9.11. The LST algorithm is a seeded algorithm that sums contiguous calorimeter cells above pre-defined
thresholds. Seeds are pre-identified in the input data for each layer of the calorimeter. For each seed, cells are associated if the energy is above a fixed clustering threshold. Starting at the seed's eta slice, the algorithm sequentially tests cells in $\eta$ slices in the direction of positive $\eta$ until a slice is found that doesn't have a contiguous cell above threshold or if a predefined boundary is reached. This process is repeated in the direction of negative $\eta$ starting from the seed. To improve performance, only the cells in a square window centred on the seed are considered in the algorithm (7×7 or 11×11 cells), which would define a predefined boundary as described above. Furthermore, the algorithm is typically limited to a central eta region, which defines an additional boundary for the clustering. The two alternative versions are also illustrated in Fig. 9.11. The Windowing algorithm is a simpler variant based on the assumption that the cluster energy deposition region can be approximated by the cells in a square window, centred on the seed. The spiral algorithm is also a seed-based implementation, but contrary to Windowing and LST, the cluster comprises only those cells which are on the first and, optionally, on the second spiral of contiguous cells around the seeds. The spiral algorithm is easily adoptable to the FPGA architecture and yields a very small latency.

Each algorithm version comprises several components, and each component is designed to process data within a strict number of clock cycles. The overall algorithm latency is determined by the total number of clock cycles used by all algorithm components. All algorithm versions, except the spiral algorithm, use a rising/falling edge clocking technique which reduces algorithm latency. The alternative method is to use only the rising edge and a higher system clock frequency. Thus the spiral algorithm components must run at a higher clock frequency compared to the Windowing and LST versions. In all algorithm instances, an adder tree is used to calculate the cluster energy deposition, and is implemented using the FPGA LUT resources. However, the latest Xilinx UltraScale+ products (e.g., the VU13P FPGA) are equipped with a large number of DSP slices, and thus a method to implement DSPs has been studied as an alternative solution to implementing adder trees. No algorithm variants have yet been through a full latency (or speed) optimisation at the firmware synthesis level. A summary of the algorithm performance on various FPGA targets is given in Table 9.1, in which the FPGA resource usage is given as a percentage of the total available and the latency is given in FPGA clock cycles (ticks). Even without optimisation, the topoclustering algorithms have been shown to be achievable within the target performance metrics. The maximum algorithm latency is found to be 6 clock ticks (Windowing, with 5 longitudinal layers) and can be as low as 3 clock ticks (Spiral, one longitudinal layer). For a 160 MHz reference clock these correspond to latencies below 50 ns, for a 320 MHz reference clock below 25 ns.

In the tested implementation using Xilinx development boards, the serial data transmission has not yet been included in firmware because it cannot be properly implemented on the development boards. Thus, the utilisation of the FPGA logic resources is typically more intensive for LUTs, than for flip-flops, due to the large amount of data being loaded on the FPGA. Therefore the anticipated FPGA logic resource budget for serial data processing can
be found by dividing the presented usage by the number of $\eta$ slices loaded. The numbers reported in Table 9.1 for the logic resource usage have been corrected for this difference. We find that the logic resources required are at or below 1% on the medium-sized Xilinx Ultrascale chips (VU095 and VU125), and at or below 0.1% for the Xilinx Ultrascale+ chips (VU9P and VU13P). The expected physics performance of the topoclustering is discussed in Section 6.2 and the final choice of algorithm will be made by considering criteria on the processing performance as well as physics performance, emphasising improvement to the reconstruction of jets, electrons, taus and $E_T^{\text{miss}}$.

<table><caption>Table 9.1: Summary of FPGA performance for various topological clustering algorithm instances. All FPGA targets are Xilinx chips from the Ultrascale and Ultrascale+ families. The FPGA resource utilisation is given as the fraction of total resources on the chip. The algorithm latency is given in FPGA clock cycles (ticks), algorithms have been run with both 160 MHz and 320 MHz reference clocks.</caption><thead><tr><th></th><th>V-US</th><th>V-US</th><th>V-US</th><th>V-US</th><th>V-US+</th><th>V-US+</th><th>V-US+</th></tr></thead><tbody><tr><td>FPGA Family:</td><td>XCVU095</td><td>XCVU095</td><td>XCVU095</td><td>XCVU095</td><td>VU9P</td><td>VU13P</td><td>VU13P</td></tr><tr><td>Part Number:</td><td>LST 11x11</td><td>Win 11x11</td><td>Win 7x7</td><td>Win 7x7</td><td>Win 7x7</td><td>Win 7x7</td><td>1-Spiral</td></tr><tr><td>Algorithm:</td><td>gTowers</td><td>gTowers</td><td>gTowers</td><td>gTowers</td><td>gTowers</td><td>gTowers</td><td>SuperCells</td></tr><tr><td>Granularity :</td><td>1.4</td><td>0.83</td><td>0.56</td><td>0.54</td><td>0.24</td><td>0.17</td><td>0.13</td></tr><tr><td>Flip-Flops (%):</td><td>2.1</td><td>1.5</td><td>0.88</td><td>0.83</td><td>0.37</td><td>0.25</td><td>0.21</td></tr><tr><td>LUTs (%):</td><td>2.1</td><td>1.5</td><td>0.88</td><td>0.83</td><td>0.37</td><td>0.25</td><td>0.21</td></tr><tr><td>Latency (ticks):</td><td>6</td><td>6</td><td>6</td><td>6</td><td>6</td><td>6</td><td>3</td></tr></tbody></table>

### 9.3.4 Anti-$k_t$ Jet Clustering

An important goal for the Global Trigger is to identify jets with algorithms similar to those used in EF and offline. In the following, studies of possible implementations of the standard anti-$k_t$ jet-finding algorithm [9.5] are summarised to highlight issues in implementing an iterative jet-finding algorithm in the Global Trigger. While we expect that the computational complexity of this algorithm makes it unsuitable for implementation in the GEP, we include here a pedagogical description to set up the following description of algorithm variants.

The *Exact anti-$k_t$ - E-merging* algorithm [9.5] is a sequential recombination jet clustering algorithm. It takes as input a list of *N* objects (the *Object List*), which may be clusters, calorimeter cells, trigger towers, etc. and returns a list of jets (the *Jet List*), which correspond to clusters of objects. Objects are clustered iteratively using the weighted separation between two objects (labeled *i* and *j*) compared to each object's $p_{T,i}^{-2}$:

$$d_{ij} = \min(p_{T,i}^{-2}, p_{T,j}^{-2}) \frac{\Delta R_{ij}^2}{R^2}; \quad d_{iB} = p_{T,i}^{-2} \qquad (9.1)$$