# A 1.2 V Low-Noise-Amplifier with Double Feedback for High Gain and Low Noise Figure

Ivan Bastos, F. Querido, D. Amoêdo, Luis B. Oliveira, J. P. Oliveira, João Goes, Manuel M. Silva

## ► To cite this version:

Ivan Bastos, F. Querido, D. Amoêdo, Luis B. Oliveira, J. P. Oliveira, et al., A 1.2 V Low-Noise-Amplifier with Double Feedback for High Gain and Low Noise Figure. 4th Doctoral Conference on Computing, Electrical and Industrial Systems (DoCEIS), Apr 2013, Costa de Caparica, Portugal. pp.573-581, 10.1007/978-3-642-37291-9_62. hal-01348804

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# A 1.2 V Low-Noise-Amplifier with Double Feedback for High Gain and Low Noise Figure

I. Bastos, F. Querido, D. Amoêdo, L. B. Oliveira, J. P. Oliveira and J. Goes

Manuel M. Silva
INESC-ID Lisboa
Tech. University of Lisbon
Lisbon, Portugal
manuel.silva@inesc-id.pt

CTS-UNINOVA, Dep. Eng. Electrotécnica, Faculdade de Ciências e Tecnologia,
Universidade Nova de Lisboa
Caparica, Portugal
bastos356@gmail.com, l.oliveira@fct.unl.pt

**Abstract.** In this paper we present a balun low noise amplifier (LNA) in which the gain is boosted using a double feedback structure. The circuit is based in a conventional Balun LNA with noise and distortion cancellation. The LNA is based in two basic stages: common-gate (CG) and common-source (CS). We propose to replace the resistors by active loads, which have two inputs that will be used to provide the feedback (in the CG and CS stages). This proposed methodology will boost the gain and reduce the NF. Simulation results, with a 130 nm CMOS technology, show that the gain is 23.8 dB and the NF is less than 1.8 dB. The total power dissipation is only 5.3(since no extra blocks are required), leading to an FOM of 5.7 mW⁻¹ from a nominal 1.2 supply.

**Keywords:** CMOS LNAs, Noise canceling, Wideband LNA.

## 1 Introduction

Nowadays, there is a high demand for wireless communications, which includes Industrial, Scientific, and Medical (ISM) and Wireless Medical Telemetry Service (WMTS) applications [1]. These low cost applications require low power, low voltage transceivers fully integrated in a single chip [2-4]. The LNA that is a key block in these systems will be investigated in this paper.

Wideband LNAs with high gain and low noise figure (NF), using noise and distortion cancelation have been proposed [5-7]. But, these circuits have large power dissipation for high gain and low noise figure.

In this paper our main goal is to design a very low area and low cost LNA, with very high gain and low NF using a 1.2 V supply. This is obtained by replacing the load resistors by transistors biased close to saturation. In [7]a circuit operating at 1.2
V with controllable gain was proposed. In this paper we investigate the possibility of introduce a double feedback technique to boost the gain and reduce the noise figure (NF).

Equations for gain and noise figure are presented, which can be used to optimize the circuit performance. A circuit prototype in a 130 nm standard CMOS technology at 1.2 V have been designed and simulated to demonstrate the proposed technique.

The circuit prototype has gain of 23.8 dB and NF below 2 dB, dissipating only 5.3 mW, leading to a FOM of 5.7 mW⁻¹, which is, to the authors’ knowledge, the best FOM in the literature for LNAs with a nominal 1.2 V supply.

## 2 Contribution for Internet of Things

Recently, more devices are being embedded with sensors and actuators with the ability to communicate and exchange information, creating a cloud environment. The physical communication plays a critical role in portable wireless devices equipped with transceivers where power consumption, immunity to noise, and signal amplification are important parameters to ensure a reliable and efficient communication in a crowded channel environment. With this goal in mind the design of RF front-end blocks for low power applications, in CMOS technology, will contribute towards the achievement of more cheap and robust devices. In this paper we will focus on the design of low power LNAs.

## 3 Balun LNA with Noise Cancellation

In a receiver path, since typically, the antenna and RF filters are single-ended, it is very important to have a LNA with single-ended configuration input. A differential signal in the receiver is preferred to reduce harmonic distortion and to reject power supply and substrate noise [6]. Traditionally, we have an external balun that converts single-ended signals to differential, but it introduces losses and degrades the receiver NF. A balun LNA is a very good solution to convert a single-ended to a differential signal, which simplifies the design avoiding the external balun [6].

A balun LNA, in which the thermal noise of CG-transistor is canceled because this noise appears in phase at two outputs and their gains are in opposition, is proposed in [6]. The gain is doubled and the noise is reduced when the output signals are balanced. It can also be shown that the distortion introduced by $M_1$ is also cancelled.
<figure><img src="image_2.png" /><figcaption>Fig.1. Balun LNA with noise canceling of CG-transistor [6].</figcaption></figure>

The differential voltage gain of the LNA is obtained from the difference of the common-gate (CG) stage and the common-source (CS) stage gains:

$$A_v|_{Diff} = g_{m1}(R_1//r_{ds1}) + g_{m2}(R_2//r_{ds2}). \quad (1)$$

where, $r_{ds}$ is the transistors output resistance and $g_m$ is the transconductance.

The input impedance is given, approximately:

$$Z_{in} = \frac{1}{g_{m1}}. \quad (2)$$

Note that the body and source of $M_1$ are connected to eliminate the body effect.

## 4 Proposed Circuit

Considering the traditional CG-CS LNA circuit (Fig. 1) as reference, we investigate a topology using active loads, by replacing the resistors by transistors, biased in the triode region, which behave, approximately, as linear resistors [7]. In order to enhance the gain, while maintaining a low noise figure, we investigate first the possibility to use local Feedforward and Feedback (FF), as shown in Fig. 2a).

Taking the advantage of using transistors, instead of resistors, we apply $V_{in}$ on the gate of transistor to the gate of $M_4$, which is amplified and added to $V_{out2}$. The resulting signal is amplified through $M_3$ by feedback and added to $V_{out1}$. With this structure we have a significant increase in the gain, mainly in the CG stage, which need to be carefully designed to ensure 50 Ohms input match. In this case the thermal noise of $M_1$ is only partially cancelled, which degrades the LNA noise figure. To
overcome this issue we propose a new circuit approach in which we apply a Double
Feedback structure (DF), as shown in Fig. 2b).

This proposed circuit boost the gain, and reduce the noise of $M_1$ that appears with the same level on the LNA outputs (load transistors $M_3$ and $M_4$), while the output signals remain balanced. This circuit is more simply and completely symmetrical, and therefore, is expected to achieve the best performance results.

In the feedback is used a high pass RC coupling, as shown in Fig. 2. With these connections, the parasites capacitances of $M_3$ and $M_4$ will reduce the bandwidth (the gate-source and gate-drain capacitances), but the main goal is achieved: high gain and low NF.

<figure><img src="image_3.png" /></figure>

<figure><img src="image_4.png" /><figcaption>**Fig.2.** a) LNA using FF. b) Proposed LNA using DF.</figcaption></figure>
In order to provide some circuit insight, we derive here the equations for gain (CG and CS stages) and LNA input impedance (for the proposed DF case):

$$ \frac{V_{out1}}{V_{in}} = \frac{g_{mCG}g_{2}+g_{m2}g_{m3}}{g_{1}g_{2}-g_{m3}g_{m4}}. \qquad (3) $$

$$ \frac{V_{out2}}{V_{in}} = - \frac{g_{m2}g_{1}+g_{mCG}g_{m4}}{g_{1}g_{2}-g_{m3}g_{m4}}. \qquad (4) $$

where,

$$ g_{1} = g_{ds1} + g_{ds3}. $$

$$ g_{2} = g_{ds2} + g_{ds4}. $$

Using (3) and (4), we obtain the LNA differential gain,

$$ A_{v|Diff} = \frac{V_{out1}-V_{out2}}{V_{in}} = \frac{g_{mCG}(g_{m4}+g_{2})+g_{m2}(g_{m3}+g_{1})}{g_{1}g_{2}-g_{m3}g_{m4}}. \qquad (5) $$

The input-impedance is given by

$$ Z_{in} = \frac{g_{1}g_{2}-g_{m3}g_{m4}}{g_{mCG}[g_{2}g_{ds3}-g_{m3}g_{m4}]-g_{m2}g_{m3}g_{ds1}}. \qquad (6) $$

Using equations (5) and (6), we can optimize the circuit performance in order to increase the gain, minimizing the impact in the input match.

From [6, 7], if it is assumed that $g_{m1} = g_{m2} = g_{m}$, the noise factor is:

$$ F_{LNA} = 1 + \frac{k_{f}}{8kTR_{S}c_{ox}f^{\alpha_{f}}} \left( \frac{1}{W_{1}L_{1}} + \frac{1}{W_{2}L_{2}} \right) + \frac{\gamma}{2R_{S}g_{m}} + \frac{1}{R_{S}r_{ds}g_{m}^{2}}. \qquad (7) $$

where k is Boltzmann's constant, $c_{ox}$ is the oxide gate capacitance per unit area, $W_{i}$ and $L_{i}$ are the transistor dimensions, T is the absolute temperature, $\gamma$ is the excess noise factor, $k_{f}$ and $\alpha_{f}$ are intrinsic process parameters, which depend on the size of the transistors [8, 9]. With the proposed circuit there is additional noise due to the double feedback structure, however, this can be minimized by proper design.

From [6], to improve the noise figure, the $g_{m2}$ should be greater than $g_{m1}$, while the $g_{ds4}$ is increased to keep the output signals balanced.

$$ g_{m2} = n \cdot g_{m1}. $$

$$ g_{ds4} = n \cdot g_{ds3}. $$

The optimal value of n is obtained by simulations.
## 5 Simulation Results

The circuit prototype is designed using a 130 nm CMOS standard technology with 1.2 V supply. The circuit parameters are given on Table 1. The length of each transistor channel is the minimum to maximize speed, and $V_{bias}$ is defined in 760 mV to define the biasing current at the CS stage.

<table><caption>**Table 1.** LNA circuit parameters using DF.</caption><thead><tr><th></th><th><i>I</i><sub>D</sub><br>(mA)</th><th><i>W</i><br>(μm)</th><th><i>r</i><sub>ds</sub><br>(Ω)</th><th><i>g</i><sub>ds</sub><br>(mS)</th><th><i>g</i><sub>m</sub><br>(mS)</th></tr></thead><tbody><tr><td><i>M</i><sub>1</sub></td><td>2</td><td>139.2</td><td>472</td><td>2.12</td><td>30.80</td></tr><tr><td><i>M</i><sub>2</sub></td><td>2.43</td><td>358.4</td><td>357</td><td>2.80</td><td>44.23</td></tr><tr><td><i>M</i><sub>3</sub></td><td>2</td><td>13.14</td><td>236</td><td>4.23</td><td>2.07</td></tr><tr><td><i>M</i><sub>4</sub></td><td>2.43</td><td>16.4</td><td>186</td><td>5.38</td><td>2.48</td></tr></tbody></table>

In Table 2 we compare the theoretical results with simulations. We use equation (1) to traditional LNA with resistors[6] and using MOS in triode [7], and equation (5) for the proposed DF approach.

<table><caption>**Table 2.** Gain (dB) for different topologies.</caption><thead><tr><th></th><th><i>Res</i></th><th><i>MOS</i></th><th><i>DF</i></th></tr></thead><tbody><tr><td>Theoretical</td><td>19.07</td><td>20.45</td><td>23.78</td></tr><tr><td>Simulation</td><td>19.03</td><td>20.50</td><td>23.81</td></tr></tbody></table>

In Table 3 we compare the simulation results for the traditional case with resistors, MOS transistors, and two approaches capable to boost the gain: 1) using feedback and feedforward (FF), and 2) the proposed case of double feedback (DF).

In order to investigate the influence of double feedforward in the LNA key parameters: gain, noise figure, linearity, and frequency band, several simulations are presented in Table 3. For a better comparison of the obtained results, the following figure of merit is used [10]:

$$ \text{FOM}[\text{mW}^{-1}] = \frac{\text{Gain}}{(\text{NF}-1)P_{\text{DC}}[\text{mW}]} \qquad (8) $$

<table><caption>**Table 3.** Circuit Simulations for different topologies.</caption><thead><tr><th></th><th><i>Gain</i><br>(dB)</th><th><i>NF</i><br>(dB)</th><th><i>IIP3</i><br>(dBm)</th><th><i>Power</i><br>(mW)</th><th><i>Band</i><br>(GHz)</th><th><i>FOM</i><br>(mW<sup>-1</sup>)</th></tr></thead><tbody><tr><td><i>Res</i></td><td>19.03</td><td>&lt; 2.34</td><td>3.62</td><td>5.16</td><td>0.2-7.4</td><td>2.43</td></tr><tr><td><i>MOS</i></td><td>20.50</td><td>&lt; 2.02</td><td>-3.47</td><td>5.30</td><td>0.2-6</td><td>3.37</td></tr><tr><td><i>FF</i></td><td>23.28</td><td>&lt; 2.39</td><td>-11.03</td><td>5.51</td><td>0.1-2.5</td><td>3.61</td></tr><tr><td><i>DF</i></td><td>23.81</td><td>&lt; 1.79</td><td>-9.92</td><td>5.32</td><td>0.1-2</td><td>5.72</td></tr></tbody></table>
In Table 3 is shown that the DF approach has the highest gain and the lower NF, leading to the highest FOM. The disadvantages are the increase of the circuit non-linearity and the reduction of the available bandwidth.

In figs. 3 to 5, the simulation results for the input match (S11), gain, and NF, for the proposed circuit (DF) are presented.

<figure><img src="image_5.png" /><figcaption>Fig.3. Simulated LNA S11 parameter.</figcaption></figure>

<figure><img src="image_6.png" /><figcaption>Fig.4. Simulated LNA Gain.</figcaption></figure>
<figure><img src="image_7.png" /><figcaption>Fig.5. Simulated LNA Noise Figure.</figcaption></figure>

Comparing these results with state-of the art inductorless LNA (table4), we observe that our circuit is very good in terms of gain and NF, and has very low power, which leads to the best FOM (please note that the results are obtained by simulation, some degradation is to be expected in the fabricated circuit; some of the references in table 4 are from measurements).

<table><caption>Table 4. Comparison with state-of-the art LNAs.</caption><thead><tr><th>Ref</th><th>Tech (nm)</th><th>Band (GHz)</th><th>Gain (dB)</th><th>NF (dB)</th><th>IIP3 (dBm)</th><th>Power (mW)</th><th>FOM (mW<sup>-1</sup>)</th></tr></thead><tbody><tr><td>[6]<sup>M</sup></td><td>65</td><td>0.2-5.2</td><td>13-15.6</td><td>&lt; 3.5</td><td>&gt;0</td><td>14</td><td>0.4</td></tr><tr><td>[11]<sup>M</sup></td><td>90</td><td>0.5-8.2</td><td>22-25</td><td>&lt; 2.6</td><td>-4/-16</td><td>42</td><td>0.5</td></tr><tr><td>[12]<sup>M</sup></td><td>90</td><td>0.8-6</td><td>18-20</td><td>&lt; 3.5</td><td>&gt;-3.5</td><td>12.5</td><td>0.6</td></tr><tr><td>[13]<sup>S</sup></td><td>90</td><td>0.1-1.9</td><td>20.6</td><td>&lt; 2.7</td><td>10.8</td><td>9.6</td><td>1.3</td></tr><tr><td>[14]<sup>S</sup></td><td>130</td><td>0.2-3.8</td><td>11.2</td><td>&lt; 2.8</td><td>-2.7</td><td>1.9</td><td>2.1</td></tr><tr><td>[15]<sup>M</sup></td><td>180</td><td>0.5-0.9</td><td>16</td><td>&lt; 4.3</td><td>-</td><td>22</td><td>0.2</td></tr><tr><td>[16]<sup>M</sup></td><td>180</td><td>0.1-0.9</td><td>15</td><td>&lt; 4.2</td><td>-</td><td>10</td><td>0.3</td></tr><tr><td>[7]<sup>S</sup></td><td>130</td><td>0.2-5</td><td>20.4</td><td>2.6</td><td>-10.9</td><td>4.8</td><td>2.7</td></tr><tr><td>[17]<sup>S</sup></td><td>130</td><td>0.2-6.6</td><td>19.8</td><td>&lt; 1.8</td><td>1.6</td><td>4.8</td><td>3.5</td></tr><tr><td><strong>This Work<sup>S</sup></strong></td><td><strong>130</strong></td><td><strong>0.1-2</strong></td><td><strong>21.7-23.8</strong></td><td><strong>1.6-1.8</strong></td><td><strong>-9.7</strong></td><td><strong>5.3</strong></td><td><strong>5.7</strong></td></tr></tbody></table>

(S) - Simulation results. (M) - Measurement results.
The proposed circuit approach is especially interesting in low power and low voltage biomedical applications [1]. Since in these applications low power is the key aspect and some non-linearity can be tolerated. There are ISM bands in 450 MHz and 900 MHz and WMTS band in 600 MHz and 1.4 GHz, for which this circuit can be a good alternative to the conventional solutions.

## 6 Conclusions

In this paper we present a low voltage and low power wideband balun LNA with DF for high gain and low NF. A circuit prototype operating at 1.2 V is presented in a 130 nm CMOS technology, which validates the proposed methodology. Simulation results show that the gain of the balun LNA is 23.8 dB, and the NF is below 2 dB for a power consumption of 5.3 mW. The proposed circuit is especially useful for low power and low voltage operation in biomedical applications (ISM and WMTS bands).

The proposed circuit, with 1.2 V supply, to the best of the authors' knowledge, has the high FOM (5.7 mW⁻¹) when compared with CMOS LNAs in the literature.

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