# An Experimental Approach to the Health-monitoring of a Silicon Carbide MOSFET-based Power Module

Malorie Hologne<fnref n="1" />, Pascal Bevilacqua<fnref n="1" />, Bruno Allard<fnref n="1" />, Guy Clerc<fnref n="1" />, Hervé Morel<fnref n="1" />, Hubert Razik<fnref n="1" />, Antoine Barrière<fnref n="2" />,
Vinaykumar Karode<fnref n="3" /> and Navien Devadass<fnref n="3" />,

**Abstract**— This paper deals with an overview of Silicon Carbide MOSFET-based power module failure modes and an experimental health-monitoring approach to detect them. The power module reliability question has recently emerged according to the development of converters in industrial fields such as: aerospace, automotive, traction... Nowadays, converters have a key role in the power transmission line. Besides, the power requirement of these converters is ever increasing. This constraint has pushed researchers into new technologies increasing the power density in converters which are increasingly more compact and lightweight. In our application, we use silicon carbide chips due to their better performance compared to other technologies. The interconnections and the materials have been adapted to the higher temperature range of a SiC chip. Despite optimization, the silicon carbide MOSFET-based power modules still present weaknesses and failures in use. The aim of this paper is to understand and moreover to highlight the power module physics of failure to trigger the most common failure types, to find a way to follow them. Finally, it presents a relevant test plan and the test circuits associated to trigger and study these expected failures.

**Keywords**— Silicon carbide MOSFET, health-monitoring, reliability, failure modes.

## I. INTRODUCTION

The power module reliability question has emerged with the development of converters for many industrial companies especially in the field of aerospace. Indeed, in a power transmission line actuators are not the only critical components and proven converter reliability is essential in system reliability considerations. A higher power demand has forced industries and researchers to find more efficient technology for power electronic components: Silicon carbide devices are an obvious choice for this research. After many improvements, the silicon carbide MOSFET, often chosen for its efficiency, presents some challenges. Besides, packaging and interconnections technologies which were well adapted to silicon technology, these have difficulties coping with the constraints imposed by silicon carbide chips. SiC devices provides ten times higher power than silicon devices for the same surface area. For these reasons researchers and industries are motivated to launch projects to discuss and investigate these issues. The present study is included in a European project called I²MPECT and must meet objectives defined by the consortium, such as to assure the reliability of a silicon carbide MOSFET based power converter in an aerospace application, to define the limits in terms of acceptable constraints, and to define how the remaining useful lifetime of the power converter can be predicted. Such converters are being installed at critical places in aircraft power systems.

Before discussing the entire converter, this study focuses on the major subcomponent, the power module. The expected failures in a power module will be discussed. Next, a test plan that will allow understanding the physics of failure, finding relevant failure indicators and predicting the remaining useful lifetime of the module will be discussed. The last two sections of this paper present experimental test benches dedicated to the test plan and the necessary preliminary tests to assure that the chosen indicators are relevant.

<footnote n="1">¹Univ Lyon, UCB Lyon1, INSA, CNRS, AMPERE, F-69100, VILLEURBANNE, France, malorie.hologne@insa-lyon.fr</footnote>

<footnote n="2">²CETHIL, INSA, F-69100, VILLEURBANNE, France, antoine.barriere@insa-lyon.fr</footnote>

<footnote n="3">³Dynex Semiconductor Ltd., Lincoln LN63LF, UK, vinaykumar.karode@dynexsemi.com, navien.devadass@dynessemi.com</footnote>
## II. EXPECTING FAILURE MODES IN SILICON CARBIDE MOSFET-BASED POWER MODULE AND HOW TO DETECT THEM

### A. Failure Modes in Silicon Carbide MOSFET-based Power Modules

In recent years several studies have been conducted on SiC modules presenting attractive performances to determine the failure modes of this new technology. Most of these studies are either chip oriented or interconnections and package oriented but it is difficult to find studies which deal with the whole system. Thus; it has been decided to approach this issue in this study. Concerning the MOSFET chip, the major failure type is the gate oxide degradation shown in Fig. 1, extracted from Ouaida's [4] article. This degradation can have many causes such as high temperature in the channel, high electric field across the gate and trapping effect near the oxide. Regarding die related processes, i.e. interconnections and metallizations, Bower [1], Durand [2] and Musallam [3] have conducted studies to highlight failure mechanisms shown in Fig. 2. The main failure modes are cracks in the solder joint even if it is sintered, bond wire lift-off and metallization reconstruction (wavelet appearance which create a bad electric contact). These failure modes are caused by temperature variations on materials which have different CTEs and therefore are subject to significant thermal/mechanical stresses as a result of the different expansion rates.

<figure><img src="image_1.png" /><figcaption>Fig 1. (a) Gate oxide before and after degradation, (b) Zoom on degraded oxide</figcaption></figure>

<figure><img src="image_2.png" /><figcaption>Fig 2. (a) Cracks in solder joint, (b) wire bond lift-off, (c) metallization reconstruction</figcaption></figure>

### B. Failure Indicators and Failure Triggering in Silicon Carbide MOSFET-based Power Modules

To detect the different failures which have been described previously, different indicators can be used. According to Ouaida [4], gate oxide degradation can be monitored by gate or drain leakage current and threshold voltage changes. Although high temperature is a well-known acceleration factor, Schrock [6] has shown that overcurrent is also a good way to trigger gate failure. Another study led by Santini [5] shows that constant high gate voltage triggers very early gate degradation. Concerning fatigue in the interconnections, the thermal resistance and the on-state resistance changes can be good indicators. However, these changes can't allow us to identify failure location precisely. According to Durand [2], overcurrent and high temperature are relevant accelerating factors. For each type of failure, knowledge of the junction temperature is essential but really difficult to obtain. Several techniques are used such as an adjustable thermal model or TSEP (Temperature Sensitive Electrical Parameters).

## III. EXPERIMENTAL TEST BENCH ESTABLISHMENT

### A. Module Description and Determination of Weak Points

The power module proposed by the project partners will be encapsulated and be without wire bonds. To replace wire bonds, a flexible PCB is pressed on the top metallization of the chips and bonded. For reliability tests, a simplified module with only one MOSFET per switch has been designed. Fig. 3 shows one module which is a power converter leg. With this prototype, the focus will be to trigger and observe MOSFET gate degradation, metallization reconstruction and solder joint cracks.

<figure><img src="image_3.png" /><figcaption>Fig 3. SiC MOSFET based power module 3D view</figcaption></figure>
## B. Experimental Test Plan

### a) Gate fatigue tests

To trigger gate failure, a High Temperature Gate Bias (HTGB<fnref n="1" />) test has been chosen. Two HTGB tests were performed, one with a positive voltage bias and the second one with a negative bias. This kind of test is designed to fatigue the gate oxide rapidly and allow observation of variations of indicators in a short time period. Each HTGB test will be performed on 4 identical modules to check repeatability of indicators behavior. During these tests, failure indicators will be gate leakage current and threshold voltage.

### b) Active Power Cycling (APC) Tests

The APC tests have been designed to trigger different failure types and try to dissociate die, from metallization from solder failures. The first test consists of long thermal cycles created by MOSFET self-heating under a nominal drain current. This test aims to trigger heat diffusion through all module layers and so triggers failures caused by CTE mismatching such as cracks in solder joints and metallization reconstruction. The second test consists of short thermal cycles created by MOSFET self-heating while subject to a drain current which is three times higher than nominal. This test aims to trigger the trapping effect in the conduction channel and metallization reconstruction because metallization is the nearest layer to the MOSFET in the module. During these two types of APC tests, the indicators of interest will be the gate leakage current, the drain current under the threshold voltage, the threshold voltage, the on-state resistance, the forward voltage and the thermal resistance. The crossing of these indicators in the two types of APC tests will allow us to dissociate gate oxide from metallization or solder joint issues. For the same reasons as previously in II.B.a, 4 identical modules will undergo the same tests. For these APC tests, only the low side MOSFET in a converter leg will be monitored, the high side MOSFET will be only used to study its internal diode. A last test will be performed to monitor the internal diode under APC tests by measuring the forward voltage, the junction temperature and drain leakage current to assure internal diode reliability to fully utilize the MOSFET internal diode in the final converter.

## IV. PRELIMINARY TESTS AND VERIFICATION

Before performing tests using the APC test bench, a check of the vailability of the indicators was done. In particular, Miller effect measurability had to be checked and a calibration for the TSEP method had to be performed.

### A. Measurement Capability of the Miller Effect

The Miller effect is a phenomenon which can be seen on the gate signal during turn on. A kind of plateau appears; it's a sign of internal capacitance loading. In Si technology, the plateau is sharp and easily identifiable. The physical model of SiC MOSFET shows that the plateau isn't sharp and is very short (several nanoseconds).

Fig. 4, illustrates the Miller effect measurement capability in SiC. A physical model has been simulated on a SABER simulator to choose a gate resistance which is sufficient to extend the Miller effect duration. Even if the plateau always has a slope, the duration of hundred nanoseconds is measurable by putting a fifty Ohms resistance on the gate. An experimental test circuit has been made to check this result. The obtained signal shape shows a flatter plateau and a duration of sixty nanoseconds which is measurable.

<figure><img src="image_4.png" /><figcaption>Fig 4. Simulation and experimental Miller effect measurement capability</figcaption></figure>

<footnote n="1">¹ Test established in JEDEC: Global Standards for the Microelectronics industry</footnote>
## B. Calibration of the Chip Temperature Indicator

To estimate the MOSFET junction temperature, the TSEP method was chosen with drain current under the threshold voltage $I_{DVGSTH}$ as indicator. This indicator gives information about temperature in the conduction channel. Compared to other indicators as reverse voltage, $I_{DVGSTH}$ gives an image of temperature near the chip junction which is a key element. To use this indicator during the APC tests, a pre-calibration is required. Fig. 11 shows the test bench in calibration configuration. The MOSFET will undergo a fixed drain voltage of 10 V using a Source Measure Unit (SMU), Gate voltage is adjustable between 0 and 5 Volts and temperature level is controlled by a hotplate. The module is thermally insulated by glass wool to create an adiabatic environment. The temperature was increased from ambient to 150°C in increments of 10°C, and at each temperature, the data of $I_D$ vs. $V_{GS}$, called transconductance, is recorded. First calibrations have been made on a commercial module from CREE composed of 80 mΩ, 1200 V SiC MOSFETs following the protocol described previously. However, after getting calibration curves, when heating phase was launched, drift in drain value was observed for a specific gate voltage while $I_{DVGSTH}$ measurement. This drift was not due to temperature evolution because any current was imposed during this establishment phase.

<figure><img src="image_5.png" /><figcaption>Transconductance at ambient temperature for different gate charge state</figcaption></figure>

- Initial time (MOSFET was off for days). Transconductance is plotted for $V_{GS}$ from 2 to 5 V with a return to $V_{GS}=0$ V between each point. After the test $V_{GS}=0$ V is applied during 5 minutes.
- Transconductance is plotted for $V_{GS}$ from 2 to 5 V with a return to $V_{GS}=15$ V between each point. After the test $V_{GS}=15$ V is applied during 5 minutes.
- Transconductance is plotted for $V_{GS}$ from 2 to 5 V with a return to $V_{GS}=15$ V between each point. After the test $V_{GS}=15$ V is applied during 25 min.
- Transconductance is plotted for $V_{GS}$ from 2 to 5 V with a return to $V_{GS}=15$ V between each point. After the test $V_{GS}=0$ V is applied during 7 minutes.
- Transconductance is plotted for $V_{GS}$ from 2 to 5 V with a return to $V_{GS}=0$ V between each point. After the test $V_{GS}=0$ V is applied during 1 hour.
- Transconductance is plotted for $V_{GS}$ from 2 to 5 V with a return to $V_{GS}=0$ V between each point. After the test $V_{GS}=0$ V is applied during 1 hour.
- The initial charge state is reached.

Fig 5. Illustration of charge trapping phenomenon (drift and initial state recovered)

To understand this phenomenon, specific tests have been performed. For a constant ambient temperature, the transconductance curve was established under different gate voltage conditions. Indeed, voltage applied on the gate creates a charge state of the gate oxide. According to the field applied on the gate oxide, some charges are trapped in the oxide. These charges modify the correlation between drain current and gate voltage. The drift observed is sufficient to bring mistakes in temperature establishment thanks to this TSEP. Fig. 5 shows how gate voltage modify transconductance curve. It also shows that the initial charge state can be recovered if the MOSFET is in off state during a long time (1 hour).

<figure><img src="image_6.png" /><figcaption>Transconductance at ambient temperature for different charge state</figcaption></figure>

Fig 6. Fast recover of initial charge state thanks to negative voltage

For the TSEP use in cycling tests, waiting one hour before realizing the measurement is foolish. Therefore, another solution was proposed. We can see that the charge trapping phenomenon is reversible but inversion by putting any voltage on the gate is very long. A negative voltage was applied in order to inverse charge trapping phenomenon. Fig 6 shows that a very brief time with -5 V allows to reestablish the initial charge state of the oxide and to correlate drain current and gate voltage correctly. Gate voltage between 0 and -4 V had also been tested but didn't allow recovering initial charge state of the oxide.

The chosen protocol to calibrate the TSEP is so the following one. DUT undergoes a drain voltage of 10 V to be in saturation conditions. Power module is in an adiabatic enclosure formed by glass wool. Gate voltage is fixed to -5 V by default and between each point of measurement of the transconductance. Fig. 7 is obtained when gate voltage varies from 2 to 5,4 V for several temperatures from 40 to 150°C.
<figure><img src="image_7.png" /><figcaption>Fig 7. Transconductance following temperature with VGS= -5 V between each point of measurement.</figcaption></figure>

Function (1) is used to fit each transconductance:

$$I_{DS} = (p3 \cdot V_{GS}^{p4} + p5)e^{(p1 \cdot V_{GS} + p2)} \quad (1)$$

Where pᵢ are parameters identified by a genetic algorithm for each temperature as shown in fig. 8. After each transconductance fitting, I<sub>DS</sub> vs. V<sub>GS</sub> for several temperatures is transformed into drain current vs. temperature for several V<sub>GS</sub> in saturation condition. This step will allow to create abacus to rapidly estimate MOSFET temperature knowing gate voltage. In the abacus fig. 9, each curve can be fitted by a function given by (2):

$$I_{DS} = A e^{B \cdot T} \quad (2)$$

Where A and B are parameters linked to gate voltage as shown in fig. 10. Parameter A is linked to gate voltage by an exponential function and B by a linear one as noted in (3).

$$\begin{cases} A = C_1 e^{C_2 \cdot V_{GS}} \\ B = C_3 \cdot V_{GS} + C_4 \end{cases} \quad (3)$$

<figure><img src="image_8.png" /><figcaption>Fig 8. Transconductance fitting with genetic algorithm</figcaption></figure>

Relations found previously will allow to calculate instantly temperature in MOSFET conduction channel by knowing gate voltage applied and drain current measured in saturation conditions (by applying 10 V on the drain). Previous functions can be combined to express temperature (4):
$$T(V_{GS}, I_{Dsat}) = \frac{1}{C_3 V_{GS} + C_4} \ln \left( \frac{I_{Dsat}}{C_1 e^{C_2 V_{GS}}} \right) \quad (4)$$

With $C_i$ according to each MOSFET

<figure><img src="image_9.png" /><figcaption>Fig 9. TSEP abacus</figcaption></figure>

A and B parameter evolution following gate voltage

<figure><img src="image_10.png" /><figcaption>Fig 10. Parameter evolution following gate voltage for $I_d$ vs. $T$ fitting</figcaption></figure>
V. TEST BENCH DESCRIPTION

A. Description of the gate fatigue test bench

<figure><img src="image_11.png" /><figcaption>Fig 11. Global APC test bench in a TSEP calibration configuration</figcaption></figure>

On this test bench, MOSFETs will undergo a constant positive or negative gate bias to accelerate gate ageing. The module containing MOSFETs will be placed on a hotplate to proceed at high temperature. A voltage generator and a load will allow us to put the MOSFET in a conduction state during all the test duration. To estimate gate degradation, gate leakage current and threshold voltage will be recorded during ageing. This test bench is currently used in the lab by other researchers and won't be detailed in this article.
## B. Description of the Power Active Cycling Test Bench

As shown in Fig. 12, the APC test bench is composed of a power circuit to trigger self-heating of the MOSFET, a drain current under threshold measurement circuit to follow junction temperature, and a double pulse characterization circuit to assure correct measurement of the threshold voltage and the on-state resistance.

Fig. 13 shows the logical sequences of driver signals. The timings are not to scale to allow them to be represented graphically. Self-heating pulses have duration in the range of several seconds, while drain current measurement pulses and double pulse have duration in the range of several microseconds. Characterization pulses (blue and purple traces) have to be timed to occur just after self-heating time to be as close as possible to the maximum junction temperature. Gate leakage current which is also an interesting indicator will be measured during the $I_D$ under threshold measurement because the power level is low during this phase and the noise will be reduced. Each heating phase is followed by a cooling phase in order to cycle the module between 40 and 150 °C. Every n cycles two characterization phases are performed. The cycle number between characterizations will evolve during cycling with distant characterization first and more and more often until the end of module life.

<figure><img src="image_12.png" /><figcaption>Fig 12. APC test bench scheme</figcaption></figure>

The first characterization phase (blue signals) consists in TSEP measurement. Three successive measurements are performed to obtain most information about temperature. The idea is to reconstruct the channel temperature during the heating phase by knowing the temperature curve during cooling phase.

The second characterization is a double pulse test. The first pulse allows an initialization of MOSFET internal capacitors to let show a correct turn on for the second pulse. During this turn on, the Miller effect is visible thanks to a kind of plateau as described in IV.A. The Miller plateau is an image of internal capacitances of the MOSFET. The modification of MOSFET internal capacitances is an indicator of MOSFET ageing. So by monitoring the Miller plateau, an ageing monitoring can be established. This second pulse is also ideal to measure drain current and drain voltage in order to get the on-state resistance. To realize this double pulse an inductor had been sized to specially deliver 5 A during the pulses. T1 transistor and DUT are on during only 130 µs which is sufficient to impose 5 A through the inductor. The second pulse has to occur just after inductor charge to be sure to stay around 5 A during this characterization.

<figure><img src="image_13.png" /><figcaption>Fig 13. Logical sequences of driver's signals with indicator measurement times</figcaption></figure>

During test bench establishment, main issues concerning monitoring have been met. Sensors and measurement accuracy have been discussed to choose the better solution to be able to see phenomena even they occur in a short time or have a very weak value. Consequently the test bench will be instrumented with an acquisition card from National Instrument completed by a Labview interface to have accurate and fast data treatment. Concerning the Miller effect observation, the plateau's length is so short that the acquisition
card isn't sufficient. In this case, an oscilloscope recording had been preferred. Data recorded by the scope will be then sent to the Labview interface to be treated.

To measure current during characterization phase, a circuit modification had been realized. To have accurate measurement, a shunt has been chosen to measure the drain current for temperature reconstruction and a LEM current sensor had been preferred to estimate current for on state resistance estimation. The LEM current is noninvasive and don't need any electrical link to provide current measurement. This solution allows to reduce perturbations imposed by additional sensors. The TSEP measurement shunt has been placed between DUT and ground modifying the circuit in this specific phase. In a noninvasive monitoring method, other solutions would have been preferred to avoid DUT behavior modifications. To counter the shunt influence, it has been decided to work on variables evolution and not on exact values. To be sure to analyze coherent values, calibrations were realized in the global test bench in order to avoid influence of certain circuit branches during cycling which were not connected during calibration.

## VI. CONCLUSION

In this paper, expected failures in silicon carbide power modules and a relevant test plan accompanied by test bench circuits have been presented. The APC test bench is currently showing promising results and will be validated with commercial modules. The results will allow us to confirm the reliability of the SiC MOSFET based power module. Main issues as parasitic physic phenomena have been met, especially concerning the TSEP choice. A special rigor in calibration test protocol had been found. This rigor concerning MOSFET gate voltage will be also applied during cycling before characterization phases. Sensors and measurement accuracy and influence of circuit modifications had been also discussed. The choice of working on indicators variations and not on exact values had been made.

First cycling of power modules are waited in the following weeks. As soon as the project modules will be produced, the test bench will be adapted to test them. However, first cycling and analyze will be conducted on commercial modules from CREE.

Future work will consist in finding methods to extract failure signature from data recorded along the module life. Furthermore, solutions have to be found to compare failure signature to data during MOSFET ageing in order to detect a failure and even predict a remaining useful lifetime.

## ACKNOWLEDGMENT

All results presented in this paper are possible thanks to collaboration between industrial and academic partners of the European project: SIEMENS, AIRBUS, ETHZ, USFD, DYNEX, SAFRAN Electrical & Power, INSA Lyon and K&S management.

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