# X-ray nanodiffraction analysis of residual stresses in polysilicon electrodes of vertical power transistors

Stefan Karner, Oliver Blank, Maximilian Rösch, Manfred Burghammer, Jakub

Zalesak, Jozef Keckes, Juraj Todt

► To cite this version:

Stefan Karner, Oliver Blank, Maximilian Rösch, Manfred Burghammer, Jakub Zalesak, et al. X-ray nanodiffraction analysis of residual stresses in polysilicon electrodes of vertical power transistors. Materialia, 2022, 24, pp.101484. 10.1016/j.mtla.2022.101484. hal-05075686

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# X-ray nanodiffraction analysis of residual stresses in polysilicon electrodes of vertical power transistors

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Stefan Karner<sup>a, c, *</sup>, Oliver Blank<sup>a</sup>, Maximilian Rösch<sup>a</sup>, Manfred Burghammer<sup>b</sup>, Jakub Zalesak<sup>c</sup>, Jozef Keckes<sup>c</sup>, Juraj Todt<sup>c</sup>

## ARTICLE INFO

Keywords:

X-ray

Nanodiffraction

Residual stresses

Silicon

Semiconductor devices

## ABSTRACT

The influence of residual stress concentrations on the mechanical stability and functional properties of vertical power transistors is not fully understood. In this work, residual stresses are analyzed in two polycrystalline Si electrodes using synchrotron X-ray nanodiffraction and finite element (FE) modeling. Diffraction scanning was performed over 42 transistors with a step size of 100 nm and the data were subsequently averaged in order to compensate for relatively poor diffraction statistics. The experiment revealed compressive in-plane and out-of-plane stresses of -185 to -225 MPa and -65 to -95 MPa, respectively, in the lower electrode and equiaxial tensile stresses of 70 to 150 MPa in the upper electrode, which appear to be dependent on doping and increase proportionally from compressive to tensile with the electrodes' dimensions and grain size. The results are interpreted in terms of processing route and correlated with the FE simulation. The comparison shows overall good agreement for in-plane and out-of-plane residual stresses but indicates a limitation of the FE stress simulation regarding the impact of doping and grain size effects.

## 1. Introduction

Residual stresses in microelectronic devices are of high scientific and industrial interest because they are essential for the mechanical stability and also have a decisive influence on the electronic, chemical and mechanical characteristics of Si across near-surface transistor cross-sections. Nowadays, power transistor devices represent complex, three-dimensional multi-material systems consisting of semiconductors, metals and insulators of monocrystalline, polycrystalline and amorphous nature [1]. Therefore, pronounced intrinsic residual stress concentrations are built up during device processing, which are superimposed by thermal stresses formed during subsequent cooling down and thermal cycling due to mismatch of multiple coefficients of thermal expansion (CTEs) [2–4]. The emerging strain in Si significantly alters the functional properties of the devices as a result of strain-induced changes in charge carrier mobilities, band-gap, diffusivity of dopants, oxidation rates and fracture properties [5,6]. However, unlike for planar devices, the complex vertical structure of Si trench power metal-oxide-semiconductor field-effect transistors (MOSFETs) causes the emergence of localized multi-axial stress concentrations that differ from stresses in planar systems [7,8]. Up to now, a significant effort has been made to predict the

stress fields within polycrystalline Si (poly-Si) electrodes of power MOSFETs after fabrication and subsequent thermal processing, especially using finite element (FE) modeling. The stress build-up, however, has been investigated mainly by FE models calibrated by bow measurements for planar layers as well as processed wafers [4,9,10].

Since the early 1990s, strain engineering in semiconductor devices has become an important method to further enhance their performance, leading to the development of various techniques to characterize residual stress and strain fields in microelectronic devices [11,12]. Local elastic strains and stresses can be investigated by means of electron imaging and diffraction [13] methods, X-ray [14] and neutron [15] diffraction techniques, as well as µ-Raman spectroscopy [16,17]. Regarding electron diffraction-based methods, scanning electron microscope (SEM) electron backscatter diffraction (EBSD) [18] as well as transmission electron microscope (TEM) convergent beam diffraction (CBED) [19], nanobeam diffraction (NBED) [20] and dark field electron holography (DFEH) [21] are the most important techniques. However, local elastic strains in polycrystalline materials are also commonly analyzed by using X-ray diffraction-based methods. When applying suitable X-ray elastic constants (XECs), residual stresses can be extracted from the measured X-ray elastic strains [22]. The characterization of inhomogeneous stress

## ARTICLE INFO

<footnote><sup>a</sup> Infineon Technologies Austria AG, Siemensstraße 2, 9500 Villach, Austria</footnote>

<footnote><sup>b</sup> European Synchrotron Radiation Facility, 71 avenue des Martyrs, 38000 Grenoble, France</footnote>

<footnote><sup>c</sup> Department of Materials Science, Montanuniversität Leoben, Jahnstraße 12, 8700 Leoben, Austria</footnote>

<footnote>* Corresponding author at: Infineon Technologies Austria AG, Siemensstraße 2, 9500 Villach, Austria.
E-mail address: stefan.karner@infineon.com (S. Karner).</footnote>
<figure><img src="image_4.png" /><figcaption>Fig. 1. Sketch (left) and BF STEM picture (right) of the cross-section of a Si trench power MOSFET, including a monocrystalline Si (100) substrate base, poly-Si, W, Ti/TiN and TiSi₂ regions as well as amorphous SiO₂ and BPSG regions. The source, body and body contact areas are also indicated. In this work, residual stresses were characterized in the two poly-Si electrodes.</figcaption></figure>

fields in thin films and near-surface regions and their correlation with the respective microstructure is possible, for instance, by means of scanning transmission techniques like cross-sectional X-ray nanodiffraction (CSnanoXRD), using an ordinary wide-angle X-ray diffraction transmission geometry [23,24]. Although the lateral resolution of synchrotron methods has been a critical factor to resolve strain fields in microelectronic devices for a long time, nowadays a resolution below 25 nm can be achieved along with a long working distance and high photon efficiency utilizing Multilayer Laue Lenses (MLLs) [25].

The aim of this work is to (I) locally quantify residual stresses in poly-Si electrodes embedded in a trench power MOSFET structure using synchrotron X-ray nanodiffraction, (II) to interpret and verify the build-up of process and geometry-dependent stresses in poly-Si, and (III) to correlate the obtained stress fields with a FE simulation.

## 2. Experiment

The Si trench power MOSFET (Fig. 1) investigated in this work is based on a 5 µm thick, monocrystalline epitaxial Si layer with a P doping concentration of several $10^{16}$ cm⁻³ deposited on a (100) oriented, extremely high P-doped Si substrate with a resistivity of 1.2 mΩcm. Vertical trench transistors, which are able to withstand a blocking voltage of 25 V, were formed within the epitaxial layer by applying various processing steps and lithography layers. The transistor structure (Fig. 1) consists of 1.2 µm deep stripe trenches, including two highly P-doped poly-Si electrodes embedded in amorphous SiO₂ with amorphous borophosphosilicate glass (BPSG) on top. The body and source areas in the epitaxial layer are made by B and As implantation, respectively, and subsequent diffusion into Si, resulting in doping concentrations in the range of $10^{17}$ atoms/cm⁻³ for the body area and $10^{20}$ atoms/cm⁻³ for the source area. To enhance the body contact, heavy B doping is additionally generated by BF₂ implantation into the bottom of the contact groove. The contact metal stack was built up by a Ti/TiN and a W layer. In the contact groove, TiSi₂ was formed due to direct contact

<figure><img src="image_5.png" /><figcaption>Fig. 2. Schematic representation of the position-resolved CSnanoXRD setup in transmission geometry. The sample (with a thickness of L = 50 µm) was moved along the x and y axes with a step size of 100 nm while the diffraction data were collected using a Dectris EigerX 4 M CCD detector at a distance of ~88.8 mm from the sample. Assuming plane stress conditions, residual stresses in poly-Si were evaluated using Si 111 and 220 reflections.</figcaption></figure>

of Ti and monocrystalline Si. The poly-Si electrodes were deposited in an amorphous state (a-Si) using low pressure chemical vapor deposition (LPCVD) at temperatures between 530 and 580 °C and were subsequently crystallized. This was done by rapid thermal annealing, where a-Si can be crystallized within minutes at temperatures as low as 700 °C [26].

For focused ion beam machining of a TEM lamella, a FEI Helios NanoLab 660 dualbeam workstation was used. Bright-field (BF) scanning TEM (STEM) analysis (Fig. 1) was performed using a JEOL 2200 FS system operated at 200 kV. The spot size was set to 0.7 nm.

A cross-sectional lamella with a thickness L of about 50 µm (Fig. 2) was fabricated from a processed Si wafer containing the transistor structures using a diamond wire saw and careful mechanical polishing. Afterwards, the lamella was characterized by non-destructive CSnanoXRD at the nano-focus extension of beamline ID13 [23,27] at the European Synchrotron Radiation Facility (ESRF) in Grenoble, France (Fig. 2). The monochromatic incident beam had a photon energy of 13.0 keV, a spot diameter of 200 nm and was oriented perpendicular to the transistor cross-section. The precise orientation and distance of the detector with respect to the direct beam and the sample were determined using the measurement of an Al₂O₃ powder calibration standard and the geometry refinement offered by the pyFAI software package [28]. Stress information with a relatively high strain sensitivity of better than $10^{-4}$ was obtained by using a scanning transmission setup with a 100 nm step size.

To improve the diffraction statistics of the collected data, a large sample area covering 42 transistors was scanned and the diffraction data were averaged to obtain representative information from the MOSFET transistors. Applying Bragg's law, the averaged two-dimensional diffraction data were used to calculate the lattice spacing $d(\delta, \theta)$ of the Si (111) and (220) crystallographic planes. The Bragg angles $\theta$ of Debye-Scherrer rings were analyzed at different azimuthal positions $\delta$ using the pyFAI software package and custom python code for peak fitting and strain evaluation [28]. X-ray elastic strains can be expressed as

$$ \epsilon^{hkl}(\delta, \theta) = \frac{d^{hkl}(\delta, \theta) - d_0^{hkl}}{d_0^{hkl}}, \qquad (1) $$
<figure><img src="image_6.png" /><figcaption>Fig. 3. (a) BF STEM image of exemplary transistor cross-sections. (b) CSnanoXRD phase map with a step size of 100 nm over the whole scan area (40 µm x 5 µm). (c) Phase map of averaged diffraction data. (green = poly-Si, blue = W, red = Ti/TiN).</figcaption></figure>

where $d_0^{hkl}$ is the unstrained lattice spacing of poly-Si for the respective reflection *hkl*. The relaxed lattice parameter $a_0$ for undoped Si is 5.43094 Å at 298.15 K [29]. However, when considering the P doping of the poly-Si electrodes, the unstrained lattice parameter is reduced due to the smaller atomic size of P compared to Si [30,31]. In fact, the relaxed lattice parameters for the upper and lower electrode were calculated to be 5.42715 Å and 5.42678 Å, respectively [32]. These values were then used to calculate $d_0^{111}$ and $d_0^{220}$ for both the upper and the lower poly-Si electrodes. During data treatment, a two-dimensional stress state was assumed with $\sigma_z = 0$ (cf. Fig. 2), which is a sensible assumption, as the transmission geometry is very insensitive to this stress component. This means, that any stress in the z-axis direction in the order of a few 100 MPa would not be noticeable above the background noise, because this direction is almost at a 90° angle with respect to the diffraction vectors corresponding to the Debye-Scherrer rings captured on the detector placed behind the sample. Consequently, the orientation-resolved stresses were calculated by applying suitable XECs, according to the following equation (presented also in earlier studies [33,34]):

$$ \epsilon^{hkl}(\delta, \theta) = S_1^{hkl}(\sigma_x + \sigma_y) + \frac{1}{2} S_2^{hkl} \cos^2(\theta) [\cos^2(\delta)\sigma_x + \sin(2\delta)\sigma_{xy} + \sin^2(\delta)\sigma_y], \quad (2) $$

where $S_1^{hkl}$ and $S_2^{hkl}$ are the XECs of Si for the two measured reflections $hkl = 111$ and $220$. $(\delta, \theta)$ denote detector coordinates of a fitted peak position and $\sigma_x, \sigma_{xy}, \sigma_y$ are the non-zero components of the stress state present in the probed volume. This yields a set of 24 equations [2 reflections × 12 selected orientations $(\delta, \theta)$] with the same three unknown stress components for each point $(x, y)$ in the scanned area. The resulting over-determined system of equations is fitted by least-squares error minimization to obtain these stress components at each real-space coordinate $(x, y)$. The applied XECs were calculated from literature single-crystal elastic constants ($C_{11} = 165.64, C_{12} = 63.94, C_{44} = 79.51$ GPa [35]) using a Hill-type grain interaction model [36]. Since Si is not a strongly mechanically anisotropic material, with a Zener ratio of approximately 1.5 and because the poly-Si crystallites were formed within surrounding amorphous SiO$_2$, where no epitaxial effects are to be expected, the influence of a potential preferred orientation of poly-Si crystallites on the evaluated stresses can be neglected.

FE stress simulation of the examined Si trench power MOSFET was conducted using Sentaurus™ process software from synopsis, being able to simulate the stress distribution along the whole process flow of the device fabrication. The simulation was carried out as a 2D simulation of the transistor cross-section, taking into account that the structure is

quasi-infinitely extended in the third dimension. In order to minimize the computational effort, only half of the transistor cell and half of the adjacent Si was considered during simulation and “reflect” boundary conditions were applied where the structure is mirrored on the left and right side. During process simulation, an adaptive mesh was used which is automatically tuned due to lattice doping as well as growth and deposition processes of oxides and metal layers. Nevertheless, manual fine tuning of the mesh was required at high stress regions since the mesh does not automatically adapt due to stress. The default material parameters of the simulation software like Young’s modulus E, Poisson’s ratio $\nu$, thermal expansion coefficient $\alpha$ as well as diffusion coefficients and oxidation rates were selected as input parameters. Stress-dependent oxidation rates were also considered by the FE software, allowing a prediction of locally thinner or thicker oxides. Accurate processing details of the investigated power transistor like individual layer thicknesses, temperature ramps and annealing times and temperatures were also used as input parameters as well as intrinsic stresses for poly-Si and W, which were determined by calibrating the thermomechanical simulation to wafer bow measurements. For this purpose, the wafer bow was recorded during chip processing of this power transistor, in order to obtain geometry-dependent information on the intrinsic stresses. For confirming the intrinsic stress values, wafer bow measurements were additionally conducted for planar layers with the exact same thicknesses and fabrication conditions as they were used in the examined semiconductor device.

### 3. Results and discussion

The size and grain microstructure of the two poly-Si electrodes are visualized in a BF STEM image (Fig. 3a) covering some exemplary transistors. The average grain size in the transistors’ cross-sectional plane $(x-y$ in Fig. 2) was evaluated using the software ImageJ 1.50 and was found to be 0.027 µm$^2$ in the lower (smaller) electrode and 0.055 µm$^2$ in the upper (larger) electrode. For both poly-Si electrodes, the average grain size is about 50% to 60% of the total electrode size, indicating a strong correlation between the electrode dimensions and grain size. In Fig. 3b, a phase map of the CSnanoXRD scan is displayed including 42 transistors in total, where the diffraction signal from poly-Si electrodes is represented in green, the W metallization is indicated in blue and the TiN layer on top of the BPSG is visible in red, resulting in a pink spot where both W and TiN were detected. The overall uneven positioning of
<figure><img src="image_7.png" /><figcaption>**Fig. 4.** Multiaxial residual stress distributions across a MOSFET cross-section in poly-Si electrodes derived by (a) CSnanoXRD experiments and (b) FE stress simulations using Sentaurus™ process software from synopsis.</figcaption></figure>

the transistors in Fig. 3b is attributed to the instability of the measurement setup itself, caused by thermal drift. In order to average the data of all 42 transistors (Fig. 3c), the data had to be interpolated with 1/10 of the step size, since the step size of 100 nm was not a multiple of the transistor spacing of 950 nm. Subsequently, the data from the individual transistors were aligned with respect to each other based on the center of mass of the poly-Si diffraction signal. In this study, only the residual stresses in poly-Si electrodes were evaluated due to insufficient spatial resolution for the thin W metallization layer.

The stress distributions in the poly-Si electrodes, derived from CSnanoXRD experiments, are presented in Fig. 4a. The residual stresses in the lower poly-Si electrode are in the range of -65 to -95 MPa in out-of-plane direction (vertical stress component $σ_x$) and -185 to -225 MPa in in-plane direction (lateral stress component $σ_y$), while the residual stresses range from 70 to 150 MPa for both directions in the upper electrode. Although the in-plane and out-of-plane stress values are almost the same for the upper electrode, the residual stresses in the lower electrode differ by 90 to 160 MPa between both directions. The shear stresses $σ_{xy}$ are ranging from -40 to 20 MPa and are generally at a very low level, which was expected due to a lack of external influences and high symmetry and compactness of the device structure.

The formation of residual stresses in both poly-Si electrodes can be interpreted according to the applied process conditions, electrode geometries and the respective phosphorus doping concentrations. The electrodes are formed from as-deposited a-Si, which undergoes a volume decrease during crystallization, leading to high intrinsic tensile stresses in the poly-Si electrodes [4]. Subsequent thermal processing above the crystallization temperature, at temperatures as high as 1000 °C, enables an almost complete relaxation of the initial intrinsic stresses in the highly doped poly-Si electrodes. This leads to dominant thermal stresses in poly-Si after cool down [9,37], which build up according to a higher coefficient of thermal expansion $\alpha$ of Si in contrast to SiO$_2$ [38].

Besides possible stress effects originating from the relative positions of the electrodes in the transistor structure and the influence of adjacent layers, the overall higher compressive residual stresses in the lower poly-Si electrode can be partially explained by higher P doping compared to the upper electrode, which facilitates relaxation of intrinsic stresses [9]. Additionally, the smaller grain size in the lower poly-Si electrode may also explain the overall higher compressive stresses due to a possible size effect [39,40]. The results generally indicate that the residual stresses are proportional to the electrodes' lateral dimensions, which are limiting the maximum grain size. As can be observed in Fig. 4a, the
residual stresses are shifted towards tensile values in the upper, bigger electrode with a larger grain size compared to the smaller electrode below. The anisotropic residual stresses in the lower electrode, meaning higher compressive residual stress $\sigma_y$ compared to $\sigma_x$, can be attributed to the geometry of the poly-Si electrode itself and the adjacent $SiO_2$ layers on the left and right. The width of the poly-Si is smaller and the oxide next to it is thicker at the top compared to the bottom of the electrode. This is caused by thermal oxidation directly after the formation of the lower electrode, when the poly-Si is still exposed at the top. Due to oxidation from top, a wedge-shaped oxide layer is produced along the interfaces of poly-Si and the already existing $SiO_2$, resulting in stronger compressive in-plane stresses in the poly-Si electrode due to an increased oxide thickness and a volume increase during oxidation [41]. Additionally, geometry-dependent relaxation processes during high temperature thermal processing may also contribute to the observed residual stress distributions.

In Fig. 4b, the results for simulated $\sigma_x$ and $\sigma_y$ are presented. For both electrodes, the measured residual stress component $\sigma_y$ (cf. Fig. 4a) is almost perfectly matching the FE stress simulation (Fig. 4b), which was calibrated using multiple wafer bow measurements after different processing steps. Although the wafer bow measurements are only providing an average information on in-plane stresses, it seems that the simulation results match the experimental results for $\sigma_y$ very well also on the local scale. Despite the fact that the data from the CSnanoXRD experiment show equiaxial stresses in the upper electrode, the FE simulation indicates an anisotropic distribution regarding the in- and out-of-plane residual stresses. The out-of-plane residual stress component $\sigma_x$ (Fig. 4a) in the upper electrode is measured to be much more tensile than indicated in the simulation (Fig. 4b), which could be attributed to the fact that wafer bow measurements are insensitive to residual stresses perpendicular to the wafer surface. The residual stresses in the lower electrode are, however, well predicted for both directions, which does not allow the assumption that the out-of-plane stresses in poly-Si electrodes are misjudged by FE simulation due to inaccurate calibration from wafer bow measurements. When looking at the simulated in-plane residual stress component $\sigma_y$, it is questionable whether the tensile residual stress caused by the $TiSi_2$, TiN and W layers at the bottom of the contact groove (indicated by arrows in Fig. 4b) really reaches far enough in the real device, to be able to influence the residual stresses in the upper poly-Si electrode to such a large extent. Although the FE simulation software is able to capture the emerging stresses due to silicide formation, small changes to the initial parameters like contact groove geometry, Ti thickness or $TiSi_2$ stoichiometry cause a significant difference in final stresses and may, therefore, also be a source of error especially for the simulated residual stresses in the upper poly-Si electrode. Furthermore, the influence of the metal stack in the contact groove may be compensated by lattice contraction due to heavy B doping in the adjacent monocystalline Si [30], which is not considered by the simulation software. In summary, the interpretation of the residual stress distributions in the upper electrode and its correlation to the FE simulation is not straightforward, since the real stress impact coming from the silicide is unclear and the FE software is not able to consider the influence of P doping or grain size on the residual stresses, which seem to be the main contributors for the observed equiaxial tensile stresses in the upper poly-Si electrode.

## 4. Conclusion

Local residual stresses were determined in polycrystalline Si electrodes, which are embedded in a modern Si trench power MOSFET, using synchrotron CSnanoXRD. In order to compensate for the poor grain statistics, the diffraction data were acquired from 42 transistors and subsequently averaged. With this method, the residual stresses in the poly-Si electrodes are shown to be dependent on geometry, grain size and doping concentration. For the lower and smaller electrode, in-plane compressive stresses are present in the range of -185

to -225 MPa compared to out-of-plane compressive stresses of -65 to -95 MPa. The residual stresses in the upper poly-Si range from 70 to 150 MPa for both directions and do not show a direction dependence. In general, the residual stress distributions in the lower electrode are in good agreement with the presented FE stress simulation. The remaining discrepancies between measured and simulated out-of-plane stress values in the upper electrode, however, indicate a limitation of the FE stress simulation regarding the impact of doping in poly-Si and monocrystalline Si, grain size of poly-Si, as well as $TiSi_2$ formation.

The drawback of the applied X-ray nanodiffraction approach is its relatively poor spatial resolution in contrast to TEM methods, as well as its dependence on a strain-free reference for volumes exhibiting multiaxial stresses. In the case of highly P-doped poly-Si, strain-free lattice parameters calculated from literature values in dependence of the P concentration are applicable, circumventing this limitation. Although TEM-based methods are able to deliver local strain information with a spatial resolution below 1 nm, they are limited to performing strain mapping in very thin lamellae with thicknesses around 100 nm, where information might not be representative anymore and stresses could easily relax.

In summary, the results show that CSnanoXRD is a reliable tool to quantify residual stresses in polycrystalline electrodes of vertical power transistors, enabling a more precise calibration of FE stress simulations. Together with complementary methods like TEM NBED, this will facilitate further improvement of mechanical and electrical properties of future power MOSFET technologies.

## Declaration of Competing Interest

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

## Acknowledgments

We acknowledge CzechNanoLab Research Infrastructure supported by MEYS CR (LM2018110).

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