# A Methodology for Design of Unbuffered Router Microarchitecture for S-Mesh NoC

Hao Liu, Feifei Cao, Dongsheng Liu, Xuecheng Zou, Zhigang Zhang

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Hao Liu, Feifei Cao, Dongsheng Liu, Xuecheng Zou, Zhigang Zhang. A Methodology for Design of Unbuffered Router Microarchitecture for S-Mesh NoC. IFIP International Conference on Network and Parallel Computing (NPC), Sep 2010, Zhengzhou, China. pp.442-451, 10.1007/978-3-642-15672-4_37. hal-01054965

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# A Methodology for Design of Unbuffered Router
Microarchitecture for S-mesh NoC

Hao Liu¹,³, Feifei Cao², Dongsheng Liu³,†, Xuecheng Zou³, Zhigang Zhang¹

¹ Henan Electric Power Research Institute, Zhengzhou 450052, China; ² Henan Electric Power Industrial School, Zhengzhou 450051, China; ³ Department of Electronic Science & Technology, Huazhong University of Science & Technology, Wuhan 430074, China)
freemansoc@126.com

**Abstract.** Currently, most of Network on-Chip (NoC) architectures have some limitation in routing decisions. And it makes router nodes overloaded, and sequentially forms deadlock, livelock and congestion. A simple unbuffered router microarchitecture for S-mesh NoC architecture is proposed in this paper. Unbuffered router transforms message without making routing decision. Simulation results showed that S-mesh could get optimal performance in message latency compared with 2D-mesh, Butterfly and Octagon NoC architectures. The Design Compiler synthesis results showed that unbuffered router has obvious advantages on area, and it gets higher operation speed.

**Key words:** NoC, separated-mesh (S-mesh), unbuffered, low-latency, low-cost.

# 1 Introduction

## 1.1 Background

With the arrival of multicore era, traditional bus-based interconnect architectures have became bottleneck for the multicores communication. The Network on-Chip [1], [2] design paradigm is seen as the ultimate solution of enabling the integration of exceedingly high number of cores for the future on-chip communication network architectures. In NoC based system, messages are exchanged between cores using a network and packet switching paradigm. The messages are relayed from one core to another along the path constructed by routers and links. The design of NoC communication network architectures would be facing a major design challenge that is to construct an area-efficiency, low-latency, scalable on-chip communication network.

NoC is an emerging paradigm for communications with large VLSI systems implemented on single silicon chip. It brings forward a networking method to on-chip communication and brings about notable improvements over conventional bus systems, such as ARM AMBA, Wishbone, STBus, Core Connect, and so on. There are several architectures for NoCs such as Fat-tree [3], Mesh [4], Octagon [5] and Spidergon [6]. Fat-tree and 2D-mesh as two of the most popular topologies. Some NoC implementation and research, such as Nostrum [7], Æthereal [8], Raw network [9], Xpipes [10], Eclipse [4] have been implemented on top of Fat-tree, 2D-mesh in some
extent. From a perspective of these authors, of course, these architectures are topology-independent.

## 1.2 Overview of NoC architecture

A typical NoC chip is a matrix of resource slots containing integrated embedded processors or systems connected to each other via a multi-dimensional mesh/tree network. Therefore, a typical NoC system includes resource nodes, router nodes, links and network interface unit, and routing algorithms for meet the requirements of the different architectures.

The router nodes include the routing controller and an arbiter for resolving local route conflicts. The routing algorithm currently under consideration can be labeled pseudo-dynamic since it's allowed only for restricted dynamic routing in case of router conflicts. In addition, router architecture should be adjusted with different routing algorithms. These influencing factors potentially increase uncertainty condition for system performances, especially network latency, congestion, cost and other limitations. Because the routers do not exactly know subsequent routers working conditions in real time. So local performance optimization always makes the whole system performance worse. Using these architectures for extremely large systems is very difficult [3]. We believe that NoC router architecture should be simple, low-latency, low-cost, and the number of data buffers should be minimal in the future. In accordance with the view of NoC as a research field of SoC. We focus on constructing feasible, low-latency and low-cost communication-centric design.

## 1.3 Outline of this paper

The methodology of multicores system based on NoC will be changed from computation-centered to communication-centered. Moreover, what its key goal of on-chip network is to construct a high-performance on-chip communication network with low-latency, and scalability for multicore chip system.

In this paper, an unbuffered router architecture for Separation of Control and Data-transmission NoC architecture is proposed. This NoC architecture decouples the routing decision from router. The routers employ a pre-connection mechanism for the input channels and output channels that help to reduce the complexity of the crossbar matrix design. It also meets the aforementioned features of simple, fast and less buffer. The studies of this paper mainly embody in several aspects, such as network architecture, unbuffered router microarchitecture.

This paper is organized as follows: In section II, S-mesh NoC architecture is discussed, and router microarchitecture is illuminated in Section III, the simulation results are presented in Section IV and conclusions are provided in Section V.

# 2. S-mesh NoC architecture

S-mesh NoC [11] network borrows features and design methods from those used in parallel computing clusters and communication networks. This includes design conception that separate service and bearer control in communication network. It also in-
cludes the implementation way of centralize-distribution in communication system and IP carrying network, as well as the Message Transfer Part [12], which is a part of the Signaling System #7 [13] used for communication network. Nevertheless, these methods cannot be adopted directly.

The S-mesh is based on 2D-mesh topology. In the S-mesh system, the kernel communication network adopts circuit-switching mode. And the edge devices, such as resource nodes, adopt the packet switching mode. The S-mesh network architecture consists of three types of sub-networks: mesh-based data transmission network (DN), butterfly-based control network (CN) and local bypass network (BN). The S-mesh NoC consists (Fig.1) of resources, routers and connection process unit. DN connects the resources to its nearest routers. Each router should be connected to the CN as well as four other neighboring routers through BN and DN. A BN or DN link consists of two one-directional point-to-point buses. The functionalities of router nodes only undertake link layer functionalities and physical layer functionalities. Routers do not need to store any packets before forwarding through dedicated path has been established advanced. CN is responsible for the system resource management, routing decisions, and flow control. All resources are connected to interconnection fabric with a Network Interface Unit (NIU). The NIUs handle all communication protocols, which are used to make the network as a transparent communication network.

<figure><img src="image_2.png" /><figcaption>Fig.1. S-mesh NoC architecture.</figcaption></figure>

## 2.1 Control Network and Datapath Network

Control Network architecture is similar to Fat-tree architecture. Routers are located at the leaf node of the Fat-tree, and CN is located at the root node of the Fat-tree. CN unit is designed not only for efficient commands between resources, but also for efficient movement of operands between special resources just like processors or computing units. CN uses iSLIP algorithm [14] to schedule each active request and acknowledge in turn or forward command. All on-chip dynamic data movement uses packet-based and connection-oriented communication over DN. This includes memory accesses, user-level DMA transfers, and I/O. In S-mesh, the packets header does not contain routing information, only contains labels and payload. DN network is
deadlock free and congestion-immunity due to connection-oriented communication mechanism.

## 2.2 Bypass Network

Using BN to transfer messages between adjacent cores would be better way than using DN. It responds only to its four neighbors, not acts as a router. It can efficiently reduce the traffic load of DN and signaling load of CN. Moreover, Router has two logically disjointed networks, which could be implemented as two separate networks, or as two logical networks using the two groups of physical wires. When we map the internal communications between process cores upon two-dimensional mesh networks, about 72.9% communication data occurs between the adjacent cores (routing distance is 1) [15]. The obvious local data would be transmitted through the BN. However, the global data would be transmitted through the DN. This mapping rule can ensure that local and global communication in different region could be transmitted at the same time, thereby to reduce congestion and promote transmission efficiency of the whole system.

The applicable condition is described in the pseudo code as below.

```pseudo
if (abs(X_{Destination} - X_{Source}) =1 or abs(Y_{Destination} - Y_{Source}) =1)
    and (abs(X_{Destination} - X_{Source}) ≠ abs(Y_{Destination} - Y_{Source}))
    {Data transmission via BN port without ControlNetwork;}
else
    {Data transmission via DN port with ControlNetwork;}
```

# 3 Router microarchitecture

The task of routers is to carry messages injected into the network to their final destination, following a defined determined routing path in advance. The router exchanges message flits from one of its input link to one or more of its output link under controlled by CN. Meanwhile, router can directly transfer message flits between adjacent resource nodes using BN port. The router microarchitecture consists (Fig.2) of DN crossbar, BN crossbar and controller.

In S-mesh architecture, messages are divided into packets in NIU, and packets are further divided into flits. Every packet is only composed of a header flit, a tail flit and some data flits. The every flit width is equal to N+2. The “2” is used as a packet label to indicate which packet belongs to idle, header, tail or payload. The link bandwidth also can be configured in 18-bit, 36-bit, 72-bit and others according to service demands. This attribute can increase data transmission efficiency and utilization of links. Meanwhile, it can overcome the effect of best-effort services using packet switching.

In 2D-mesh and Fat-tree NoC architectures, current routers do not predict any second hop router working condition. Therefore, routers need enough memory to buffer packets while the next routers might be stalled or under the condition of congesting possibility. Furthermore, local congestion is possible to cause global congestion, thus affect the whole system performance.
<figure><img src="image_3.png" /><figcaption>Fig. 2. S-mesh router logical implementation model.</figcaption></figure>

Regarding the buffer in routers, it is obviously different in router microarchitecture comparison S-mesh and other NoC architectures. Different switching techniques are implemented in current NoC architectures except S-mesh, which has different performance metrics along with different requirements on hardware resources. Routers in S-mesh do not need to packed/unpacked and make decisions. This property makes the design of the switches simple, and the buffer is reduced or eliminated. The transmission latency of each router can therefore be reduced to a cycle. And, transmission and control of packet in S-mesh are separated. This indicates clearly that the router microarchitecture would not be changed due to routing algorithms running in CN.

In computer networks, different techniques are used to perform message switching between different nodes. Popular switching techniques include Store-And-Forward (SAF), Virtual-Cut-Through (VCT) and WormHole (WH). When these switching techniques are implemented in NoC chips, they have different performance metrics along with different requirements on memory resources. The buffer requirement in various different routing models is shown in Table 1.

<table><caption>Table 1. Buffer requirements and latency for different routing techniques.</caption><thead><tr><th rowspan="2">Types</th><th rowspan="2">Message length</th><th colspan="2">per router buffer capacity</th><th rowspan="2">Resource @stalling</th><th rowspan="2">Occupied @stalling</th><th rowspan="2">Latency @stalling</th></tr><tr><th>normal</th><th>Stalling</th></tr></thead><tbody><tr><td>SAF</td><td>L</td><td>L×M</td><td>L×M</td><td>At two nodes</td><td></td><td>unpredictable</td></tr><tr><td>VCT</td><td>L</td><td>≤F×M</td><td>L×M</td><td>At the local node</td><td></td><td>unpredictable</td></tr><tr><td>WH</td><td>L</td><td>F×M</td><td>F×M</td><td>At all nodes spanned by the message</td><td></td><td>unpredictable</td></tr><tr><td>S-mesh</td><td>L</td><td>0</td><td>0</td><td>Good running</td><td></td><td>1clk</td></tr></tbody></table>

Table 1 indicates that router in S-mesh no longer need memory to buffer message flits. In SAF model [16], an entire packet should be received and stored prior to transmission to the next router. When the message size is big enough, it not only introduces extra delay at every router stage, but also requires a substantial amount of buffer to store multiple entire packets at the same time. VCT [17] requires the buffer for an
entire packet. It is forwarded as soon as the next router guarantees that the entire
packet will be accepted. However, when the next stage router is not available, the en-
tire packet still needs to be stored in the buffers of the current router. A WH routing
scheme can reduce routers memory requirements with low latency communication. If
a certain flit faces a busy channel, subsequent flits have to wait at their current loca-
tions, and therefore they are spreaded over multiple routers. While packets block each
other in a circular fashion such that no packets can advance, thus a deadlock is gener-
ated.

# 4 Simulation and analysis

We evaluated the S-mesh NoC by means of a Gpnocsim [18] simulator for NoC, an
architectural level cycle-accurate simulator using Java. We measured message latency
from the time a packet created in origination to the time the last flit arriving at desti-
nation message center. Nevertheless, in S-mesh architecture, the start time is the time
that message request is sent to CN. Every simulation initiates a warm-up phase of 2
percentage of all number of running cycles. All types of the topologies use the WH
switching technique except S-mesh.

## 4.1 Message length

In this scenario, we studied the relationships among latency and various message
lengths. In this case, size of network is fixed at 16 nodes; width of flit is 64-bit.

Average message latency was increased with message length in all NoC architec-
tures. However, the average latency of S-mesh rises slowly by comparison [13]. When
more and more message flits have been injected into network, contentions for re-
sources in routers have become more serious. As a result, time spent in data buffer and
queue process would be increased quickly in 2D-mesh and others. The utilization of
each router should rise sharply. Especially, fewer routers are in overload operation
when the packet length is up to 96 bytes. Then local congestion would be formed as
time goes by. On the other hand, when routers' output links have stalled, the routers
need more memory to buffer the injecting data. Additionally, local router cannot pre-
dict following link and router running states of next hop, so congestion would be eas-
ily formed. And, the next hop router refuse the previous router ejection traffic because
of resource exhausting. Further more a local congestion can quickly spread to a region
or the entire network. Some NoC architectures provide a local best solution easily, but
do not guarantee the global optimization performance. Because the datapath is
pre-connected in S-mesh architecture, it indicates that the S-mesh would provide
lower latency than other NoCs under bigger message application services.

## 4.2 Influence of buffer sizes

Buffer is the major part of any network router. In the most NoC architectures, buffers
occupy the main part of the router area. As such, it is a major concern to minimize the
amount of buffer under given performance requirements. Moreover the influencing
degree of buffer sizes on average network latency has also been studied. In this scenario, size of network is fixed at 16 nodes.

<table><caption>**Table 2.** The influence of input buffer size on network latency</caption><thead><tr><th>Flit/Buf</th><th>Fat-tree</th><th>2D-mesh</th><th>Torus mesh</th><th>Butterfly</th><th>Octagon</th><th>S-mesh</th></tr></thead><tbody><tr><td>1 -&gt; 2</td><td>12.3%</td><td>16.0%</td><td>15.5%</td><td>25.2%</td><td>15.9%</td><td>2.1%</td></tr><tr><td>2 -&gt; 4</td><td>9.9%</td><td>12.4%</td><td>9.6%</td><td>6.6%</td><td>6.9%</td><td>0.5%</td></tr><tr><td>4 -&gt; 8</td><td>6.0%</td><td>7.6%</td><td>10.1%</td><td>5.9%</td><td>4.8%</td><td>0.6%</td></tr><tr><td>8 -&gt;16</td><td>3.74%</td><td>-0.52%</td><td>8.18%</td><td>-4.98%</td><td>14.58%</td><td>-0.16%</td></tr><tr><td>16 -&gt;24</td><td>3.83%</td><td>4.16%</td><td>-0.15%</td><td>-1.12%</td><td>4.32%</td><td>-1.38%</td></tr></tbody></table>

Table 2 summarizes the propagation time reduction with various buffer sizes. Average network latency on five NoC architectures can be reduced as much as from 12.3% to 25.2% while buffer size changes from 1 to 2 flit/buffer. However, with the deepening of buffer size, the adverse impact on message latency is obvious. Such as 2D-mesh, Butterfly, and S-mesh architectures, the larger buffer sizes in routers wouldn't help to promote the network performance while buffer sizes are changed from 8 flits to 16 flits.

For further research, we gave impact degree of buffer sizes with different message length in three types of NoC architectures. For the large capacity of buffer sizes, it can efficiently reduce message latency in circumstance of large message packet as shown in Fig.3. Mainly because large buffer sizes reduce the network contention. But as shown in Fig.4, S-mesh architecture can get shorter network latency no matter what message is without buffer units. It is shown that increasing the buffer size is not a solution to avoid congestion. At best, it delays the onset of congestion since the throughput is not increased. That is, buffers are useful to absorb burst traffic, thus leveling the bursts. Moreover, the performance improves marginally in relation to the power and area overhead. Unbuffered router architecture can efficiently reduce buffer requirements without reducing network latency. It is great improvement because the cost of on-chip memory is much higher.

<figure><img src="image_4.png" /><figcaption>(a) 2D-mesh (b) Fat-tree
Fig. 3. Relative curve of message length and buffer sizes</figcaption></figure>
<figure><img src="image_5.png" /><figcaption>Fig.4. Relative curve of message length and buffer sizes in S-mesh architecture</figcaption></figure>

## 4.3 Area and power consumption results

Area figures were achieved with Design Complier logic synthesis tool targeting a Chartered 0.13µm CMOS High Performance (HP) technology. Power consumption was estimated by using the same tool that performs cycle-based simulations on the synthesized netlist.

The comparison of the alternative NoC architectures for area and power consumption are summarized in Table 3. It should be noted that the area of router of S-mesh is smaller than the area of other architectures except routers in 3D mesh. Because of using Chartered HP technology, the power dissipation of the router is slightly higher. Though the same traffic is transmitted, it's along with the optimal distances in S-mesh without more latency and no power is wasted on data buffer and congestion. These factors are all perfectly processed by Control Network. The operating frequency of Router in S-mesh is up to 1250 MHz, and achieves 200Gbps maximum bandwidth.

<table><caption>Table 3. Area and power consumption results</caption><thead><tr><td></td><td>Router</td><td>Buffer</td><td>Equivalent area (mm²)</td><td>Power (mw)</td></tr></thead><tbody><tr><td>1</td><td>3D mesh[19]</td><td>80 flits</td><td>0.0346</td><td>9.41@500M</td></tr><tr><td>2</td><td>S-mesh:2009</td><td>--</td><td>0.0411</td><td>7.39@200M</td></tr><tr><td>3</td><td>Reconfigurable [20]</td><td>Circuit-</td><td>0.051</td><td>n.a.</td></tr><tr><td>4</td><td>MaRS[21]</td><td>32-flits</td><td>0.052</td><td>4.47@432M</td></tr><tr><td>5</td><td>ReNoC [22]</td><td>40 flits</td><td>0.061</td><td>n.a.</td></tr><tr><td>6</td><td>Æthereal[23]</td><td>24-word</td><td>0.175</td><td>n.a.</td></tr><tr><td>7</td><td>Xpipes [24]</td><td>64b flits</td><td>0.19</td><td>n.a.</td></tr><tr><td>8</td><td>GT-BE[25]</td><td>8 flits</td><td>0.26</td><td>n.a.</td></tr><tr><td>9</td><td>QNoC[26]</td><td>input buffer</td><td>0.314</td><td>n.a.</td></tr><tr><td>10</td><td>GALS [27]</td><td>n.a.</td><td>0.884</td><td>n.a.</td></tr></tbody></table>
## 5 Conclusion

S-mesh NoC architecture borrows excellent architectural features of packet switching network, and unbuffered router microarchitecture borrows excellent architectural characteristic of circuit switching network. Therefore, S-mesh can gain higher performance than 2D-mesh and other NoC architectures under the condition of long message packet. The Equivalent area of router architecture is only 0.0411mm². And local network performances optimizing would interfere in overall network performances. The result shows that S-mesh architecture and unbuffered router architecture are feasible and effective.

**Acknowledgments.** We are grateful to thank the anonymous reviewers for their useful comments and suggestions. This research is supported by the High Technology Research and Development Program of China (No. 2009AA01Z105), the Postdoctoral Science Foundation of China under Grant (No.20080440942 and 200902432), and the Ministry of Education-Intel Special Foundation for Information Technology (No. MOE-INTEL-08-05).

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