# Comparison between a Cascaded H-Bridge and a conventional H-Bridge for a 5kW Grid-tied Solar Inverter

Thibault Bertin Riviere de la Souchere, Ghislain Despesse, Remy Thomas

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Thibault Bertin Riviere de la Souchere, Ghislain Despesse, Remy Thomas. Comparison between a Cascaded H-Bridge and a conventional H-Bridge for a 5kW Grid-tied Solar Inverter. Electronics, 2023, 12 (8), pp.1929. cea-04225957

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Article

# Comparison between a Cascaded H-Bridge and a Conventional H-Bridge for a 5-kW Grid-Tied Solar Inverter

Thibault Bertin <fnref n="1" />,*, Ghislain Despesse <fnref n="1" /> and Remy Thomas <fnref n="2" />

**Abstract:** This paper compares the cost and efficiency of two inverter topologies for a 5-kW grid-connected solar inverter application: the Conventional H-Bridge Inverter (CHB) and the Cascaded H-Bridge Multilevel Inverter (CHBMLI). Emphasis is put on power switches and passive elements with a detailed study of the losses. Both designs respect the same constraints (cost, efficiency, and junction temperature of the transistors) to ensure a fair comparison between both topologies. The work highlights the important parameters when choosing the components (MOSFETs, capacitors, and magnetic cores for the inductors). The DC-link voltage ripple and the output AC current ripple are the key parameters for the design of the passive elements (capacitors and inductors). On top of that, the transistors MOSFETs are chosen, in both topologies, to limit the conduction losses (by selecting the $R_{dson}$) and the switching losses (by selecting the $Q_{rr}$ and $dv/dt$). Real components are picked in order to make the comparison as complete as possible. Numerical simulations are performed using the MATLAB platform. All equations and parameters are provided. A CHBMLI prototype was built with eight independent H-Bridges to validate the proposed design with thermal and efficiency measurements.

**Keywords:** Cascaded H-Bridge Multilevel Inverter; solar panel; grid-tied inverter; solar inverter; losses; efficiency; passive elements; output filter

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**Citation:** Bertin, T.; Despesse, G.; Thomas, R. Comparison between a Cascaded H-Bridge and a Conventional H-Bridge for a 5-kW Grid-Tied Solar Inverter. *Electronics* **2023**, *12*, 1929. https://doi.org/10.3390/electronics12081929

Academic Editor: Ahmed Abu-Siada

Received: 7 March 2023

Revised: 13 April 2023

Accepted: 17 April 2023

Published: 19 April 2023

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**Copyright:** © 2023 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).

## 1. Introduction

The energy crisis issue due to the need to reduce CO₂ emissions and the shortage of fossil fuels has led most countries around the world to consider the use of renewable energy (solar PV (photovoltaics), wind power, hydropower, biopower) for electricity production. In 2019, over 200 GW of renewable energy was installed worldwide, including 120 GW of solar PV [1].

The PV inverter represents 10 to 15% of the total cost of a grid-connected PV system [2]. It is used to convert DC power from solar panels into AC power to be fed into the grid. Many solar inverter configurations can be defined [3–5]. Among them, the Central/Conventional H-Bridge Inverter (CHB) [6] and the Cascaded H-Bridge Multilevel Inverter (CHBMLI) [7] are studied in this paper. A Central H-Bridge Inverter usually consists of two power stages: a DC–DC boost converter as the front stage to get sufficient DC-bus voltage [8] and obtain a wider input voltage tracking range; and an inverter as the second stage to generate the AC utility line voltage. As an alternative to the boost DC–DC converter, a step-up transformer can be used to reach the grid voltage. This topology can reach peak efficiencies of up to 96% [9,10].

A cascaded inverter consists of several converters connected in a series, and it has many advantages in medium and large grid-connected PV systems [7,11–14]. In the CHBMLI topology, those converters are H-bridges. A DC–DC converter can be added between the solar panel and the H-bridge [15]. This helps to stabilize the voltage at the H-bridge from temperature and irradiation variations and to perform local Maximum Power Point

<footnote n="1">¹ CEA, Leti, Université Grenoble Alpes, F-38000 Grenoble, France; ghislain.despesse@cea.fr</footnote>

<footnote n="2">² CEA, Liten, Université Grenoble Alpes, F-38000 Grenoble, France; remy.thomas@cea.fr</footnote>

<footnote>* Correspondence: thibault.bertinrivieredelasouchere@cea.fr</footnote>
Tracking (MPPT) [16–18]. On top of that, due to its stair-shaped output waveform, the CHBMLI provides low switching voltages, which greatly reduces the output filter [19,20].

Furthermore, control techniques, such as Selective Harmonics Elimination Pulse Width Modulation (SHE-PWM), can be used to remove current harmonics and reduce the Total Harmonic Distortion (THD) [21]. As the Conventional H-Bridge Inverter switches higher voltages (~400 V), the output filter is costly and bulky [6]. However, the CHBMLI requires more transistors and drivers than the conventional H-bridge.

In the literature, CHBMLI prototypes have been developed and studied [13,22]. However, the number of modules is often limited (up to 5), and the switching frequency is also limited (up to 4 kHz). Those prototypes are, thus, not suited for a grid-tied solar application on the 230 V AC main grid. Most solar inverters on the market are based on the conventional H-Bridge topology. In a previous paper, the authors have demonstrated that, with a specific hardware architecture, it is feasible to control a CHBMLI with at least 8 modules (and up to 20) with a switching frequency of 20 kHz [23]. The prototype was built using low-cost local electronics on each H-Bridge without the need for isolated measurements and isolated drivers compared to other prototypes presented in the literature [24,25]. The prototype developed by the authors makes the CHBMLI suitable for a grid-tied solar application on the 230 V AC main grid.

Even though both topologies are quite familiar in the literature, there are no studies comparing, in detail, the design of both converters in terms of size and complete cost of passive elements and MOSFETs, with a 20 kHz switch and a high number of modules.

The aim of this paper is to present a comparison of the standard H-Bridge Inverter and the CHBMLI for solar applications under the same sizing constraints. For the study, we consider an output power of 5 kW without DC–DC converters for both topologies. For both topologies, a series of constraints (Table 1) is applied to the waveforms and the overall efficiency. First, the passive elements (DC-link capacitor $C_{PV}$ and output inductor $L_{grid}$) are designed based on the DC-link voltage ripple $\Delta V_{PV}$ and the output AC current ripple $\Delta I_{grid}$. The value of $\Delta V_{PV}$ is set to 4% of the optimum DC-link PV voltage $V_{MPPT}$ in both topologies. The impact of this voltage ripple on solar power extraction is detailed in Section 2. The value of $\Delta I_{grid}$ is set to 10% of the peak output grid current $I_{out}\sqrt{2}$. Furthermore, the MOSFETs and the drivers are both chosen to limit the conduction losses $P_{conduction}$ (by selecting the $R_{ds_{on}}$) and the switching losses $P_{switching}$ (by selecting the $Q_{rr}$ and $\dot{v}/dt$). Each loss is limited to 1% of the nominal output power $P_{out}$. In both cases, the junction temperature $T_{junction}$ of MOSFETs is studied, and a heatsink is selected to limit this value to 100 °C. The values of $V_{MPPT}$, $I_{out}$, and $P_{out}$ are presented in the next paragraph. Finally, based on those constraints, a series of comparisons are made in terms of cost, volume, and overall efficiency. Experimental measurements of the temperature rise, efficiency, and waveforms of the CHBMLI prototype are performed.

<table><caption>**Table 1.** Design constraints for both topologies.</caption><thead><tr><th>Design Constraints</th><th>Name</th><th>Value</th><th>Component</th></tr></thead><tbody><tr><td>DC-link Voltage Ripple</td><td>ΔV<sub>PV</sub></td><td>4% of V<sub>MPPT</sub></td><td>Capacitor C<sub>PV</sub></td></tr><tr><td>Output Current Ripple</td><td>ΔI<sub>Grid</sub></td><td>10% of I<sub>out</sub></td><td>Inductor L<sub>grid</sub></td></tr><tr><td>Conduction Losses</td><td>P<sub>switching</sub></td><td>1% of P<sub>out</sub></td><td>MOSFET + Driver</td></tr><tr><td>Switching Losses</td><td>P<sub>conduction</sub></td><td>1% of P<sub>out</sub></td><td>MOSFET</td></tr><tr><td>Junction temperature of the MOSFETs</td><td>T<sub>junction</sub></td><td>&lt;100 °C</td><td>Heatsink</td></tr></tbody></table>

Solar module, grid, and inverter parameters used in this paper are presented in Table 2. The two topologies presented in this study use LR460HPH365M solar panels placed in a series. When operating without a boost converter, the voltage of all the panels placed in a series must be higher than the maximum grid voltage. A 10% tolerance is considered. Furthermore, for a given temperature, the optimum voltage decreases when solar irradiation decreases. However, for low irradiation (under 100 W/m²), the output power is less sensitive to voltage variation around the optimum point. Thus, the voltage to
maximize the power extraction when the irradiation is 10% of the nominal one is chosen as the minimum voltage panel for the design. On top of that, an extra panel is added to improve the overall robustness. According to that, the following equation gives the number of solar panels required for a grid-tied inverter:

$$n = 1 + \frac{V_{\text{grid}} \cdot \sqrt{2} \cdot (1 + \Delta V_{\text{grid}})}{V_{\text{MPPT}_{\text{min}}} \approx 13} \quad (1)$$

where *n* is the number of solar panels, $V_{\text{grid}}$ is the RMS grid voltage (V), $\Delta V_{\text{grid}}$ is the grid voltage tolerance (%) and $V_{\text{MPPT}_{\text{min}}}$ is the minimum voltage required to ensure MPPT at 100 W/m² and 25 °C (V).

<table><caption>**Table 2.** Solar module, grid, and inverter parameters.</caption><thead><tr><th>Solar Module (LR460HPH365M)</th><th>Name</th><th>Value</th></tr></thead><tbody><tr><td>Rated Power</td><td>P<sub>MPPT</sub></td><td>362 W</td></tr><tr><td>Optimum voltage (1000 W/m<sup>2</sup>, 25 °C)</td><td>V<sub>MPPT</sub></td><td>34.1 V</td></tr><tr><td>Optimum voltage (100 W/m<sup>2</sup>, 25 °C)</td><td>V<sub>MPPT<sub>min</sub></sub></td><td>30.7 V</td></tr><tr><td>Optimum current (1000 W/m<sup>2</sup>, 25 °C)</td><td>I<sub>MPPT</sub></td><td>10.6 A</td></tr><tr><td>Open-circuit voltage</td><td>V<sub>oc</sub></td><td>41.1 V</td></tr><tr><td><strong>Grid parameters</strong></td><td><strong>Name</strong></td><td><strong>Value</strong></td></tr><tr><td>RMS Grid voltage</td><td>V<sub>grid</sub></td><td>230 V</td></tr><tr><td>Grid voltage tolerance</td><td>ΔV<sub>grid</sub></td><td>10%</td></tr><tr><td><strong>Inverter parameters</strong></td><td><strong>Name</strong></td><td><strong>Value</strong></td></tr><tr><td>Number of solar panels</td><td>N</td><td>13</td></tr><tr><td>Output power</td><td>P<sub>out</sub></td><td>4706 W</td></tr><tr><td>RMS Output current</td><td>I<sub>out</sub></td><td>20.46 A</td></tr></tbody></table>

Section 2 describes the design of the conventional H-Bridge based on parameters presented in Table 2. Section 3 applies the same design scheme as the CHBMLI. Section 4 gives a comparison between the two topologies. Section 5 presents the CHBMLI prototype and experimental measurements. Section 6 concludes the work.

## 2. Design of the Conventional H-Bridge

### 2.1. Main Characteristics

The H-Bridge is a well-known topology that converts DC into AC voltage [6,20]. The complete converter can be done with an H-Bridge driver and four N-channel MOSFETs. An inductor is used to filter the output grid current, and capacitors placed on the DC link limit the voltage ripple. For a 5-kW application, these passive elements represent an important part of the overall cost and volume of the converter. As for the semiconductors, power losses and temperature rise must be taken into account.

The conventional H-Bridge grid-tied solar inverter is shown in Figure 1. The DC side of the H-Bridge converter is powered by an array of $N = 13$ photovoltaic (PV) panels in series. The PV voltage $V_{PV}$ is stabilized by the capacitor $C_{PV}$ connected in parallel. The AC side of the H-Bridge converter is connected to the single-phase grid $V_{\text{grid}}$ through an L filter. The output current $I_{\text{grid}}$ of the PV array and the output voltage of the H-Bridge converter can, respectively, be described by Equations (2) and (3):

$$I_{PV}(t) = I_{C}(t) + I_{H}(t) = C_{PV} \cdot \frac{dV_{PV}(t)}{dt} + I_{H}(t) \quad (2)$$

$$V_{H}(t) = V_{L}(t) + V_{\text{Grid}}(t) = L_{\text{Grid}} \cdot \frac{dI_{\text{Grid}}(t)}{dt} + V_{\text{Grid}}(t) \quad (3)$$
where $I_{PV}(t)$ and $V_{PV}(t)$ are, respectively, the output current and the output voltage of the PV array. $I_H(t)$ and $V_H(t)$ are, respectively, the input current and output voltage of the H-Bridge converter. $I_c(t)$ is the current through the capacitor $C_{PV}$, $V_L(t)$ is the voltage across the inductor $L_{Grid}$. $I_{Grid}(t)$ and $V_{Grid}(t)$ are, respectively, the grid current and the grid voltage.

<figure><img src="image_4.png" /><figcaption>Figure 1. Configuration of the conventional H-Bridge grid-tied solar inverter.</figcaption></figure>

In this paper, solar production is considered with a unity power factor. Thus, the grid current and grid voltage are in phase and are defined by Equations (4) and (5):

$$I_{Grid}(t) = I_{Grid} \cdot \sqrt{2} \cdot \sin(\omega_{Grid} \cdot t) \quad (4)$$

$$V_{Grid}(t) = V_{Grid} \cdot \sqrt{2} \cdot \sin(\omega_{Grid} \cdot t) \quad (5)$$

where $I_{Grid}(t)$ and $V_{Grid}(t)$ are, respectively, the grid RMS current and the grid RMS voltage. $\omega_{Grid}$ is the grid angular frequency.

## 2.2. Passive Elements

### 2.2.1. DC-Link Capacitor

The DC-link capacitor is the first passive element that needs to be properly sized. It is a compromise between volume/cost and voltage ripple on the DC side of the H-Bridge converter. The equation for sizing the capacitor is presented in [26]:

$$C_{PV} = \frac{I_{MPPT}}{2 \cdot \Delta V_{PV} \cdot \omega_{Grid}} \quad (6)$$

where $I_{MPPT}$ is the optimum current (A), $\Delta V_{PV}$ is the 100 Hz voltage ripple (V) and $\omega_{Grid}$ is the grid angular frequency (rad·s⁻¹).

When selecting the voltage ripple value $\Delta V_{PV}$, it is important to consider its impact on PV power extraction. Figure 2 presents the evolution of the mean output power with the voltage ripple [23]. This figure was obtained considering the average output power of a single solar panel for a given voltage ripple around the optimum voltage and for a given solar irradiance. For the study conducted in this paper, we chose to limit the power drop to 1% of the Maximum Power Point. To achieve this, Figure 2 shows that the voltage ripple should not exceed 4%. To limit the voltage ripple to 4%, the filter capacitor must be at least:

$$C_{PV} \approx 950 \ \mu F \quad (7)$$

For the capacitor voltage rating, a 30% tolerance is applied from the DC link optimal voltage. Thus, 600 V capacitors are used. Capacitors chosen for both topologies in this paper are TDK aluminum electrolytic capacitors. For 600 V capacitors, B43541 capacitors are considered. As 900 μF/600 V capacitors do not exist, several smaller capacitors are placed in parallel. Considering the characteristics of those capacitors, particularly their Equivalent Series Resistance (ESR), the design of the inverter must take into account the associated losses. It is important to notice that, in a power converter, the cost of the capacitors is proportional to the energy stored. Thus, for a given total capacitor and voltage values,
choosing many small capacitors has a similar cost as choosing a few big capacitors. Typical parameters of the capacitors are presented in Table 3.

<figure><img src="image_5.png" /><figcaption>Figure 2. Power drop and voltage ripple [23].</figcaption></figure>

<table><caption>Table 3. Capacitor parameters (TDK aluminum electrolytic, B43541).</caption><thead><tr><td>Capacitor Value (100 Hz, 20 °C, μF)</td><td>Case Dimensions (mm)</td><td>ESR (100 Hz, 20 °C, mΩ)</td><td>Number of Capacitors in Parallel</td></tr></thead><tbody><tr><td>47</td><td>25 × 25</td><td>2.47</td><td>21</td></tr><tr><td>56</td><td>25 × 30</td><td>2.07</td><td>17</td></tr><tr><td>68</td><td>25 × 35</td><td>1.70</td><td>14</td></tr><tr><td>82</td><td>25 × 35</td><td>1.42</td><td>12</td></tr><tr><td>100</td><td>25 × 40</td><td>1.16</td><td>10</td></tr><tr><td>120</td><td>25 × 50</td><td>0.97</td><td>8</td></tr><tr><td>150</td><td>25 × 55</td><td>0.77</td><td>7</td></tr><tr><td>180</td><td>30 × 45</td><td>0.64</td><td>6</td></tr><tr><td>220</td><td>30 × 55</td><td>0.53</td><td>5</td></tr><tr><td>270</td><td>35 × 50</td><td>0.43</td><td>4</td></tr></tbody></table>

The losses in the function of the capacitor value (equations are detailed further in the article) are shown in Figure 3. First, the figure shows that the total ESR (at $f_{sw}$ = 20 kHz) of all capacitors placed in parallel for a given energy to store is independent of the number of parallel capacitors at the same global equivalent capacitor value: a high number of low-value capacitors or a low number of high-value capacitors. Indeed, for the same voltage rate, the ESR decreases as the capacitor value increases at the same rate. The second plot of Figure 3 highlights that whatever the configuration, total capacitor losses remain the same. However, losses per capacitor increase when the number of capacitors decreases. The temperature rise of each capacitor, which will greatly affect the lifespan of the inverter, increase when the number of capacitors decreases. Thus, 47 μF/600 V capacitors are the optimal choice, and 21 capacitors are placed in parallel. For both designs, the tolerance (20%) of the capacitor's value is not taken into account.
<figure><img src="image_6.png" /><figcaption>Figure 3. ESR and losses according to the capacitor value.</figcaption></figure>

The capacitor losses are mostly due to the ESR.

$$P_{cap} = n_{C} \cdot R_{C} \cdot \left( \frac{I_{C_{RMS}}}{n_{C}} \right)^{2} = \frac{R_{C}}{n_{C}} \cdot I_{C_{RMS}}^{2} = 4.6 \text{ W} \quad (8)$$

where $n_C$ is the number of capacitors placed in parallel ($n_C = 21$), $R_C$ is the ESR at $f_{sw} = 20$ kHz of a single capacitor ($R_c = 1.3 \Omega$) and $I_{C_{RMS}}$ is the RMS current through the capacitor at $f_{sw}$. Numerical simulations with MATLAB provide that: $I_{C_{RMS}} \approx 8.6 \text{ A}$.

The capacitor losses lead to a temperature rise for each capacitor [27]:

$$\Delta T_c = \alpha \cdot \frac{P_{cap}}{\beta \cdot S \cdot n_c} = 12.7 \,^{\circ}\text{C} \quad (9)$$

where $\Delta T_c$ is the surface heat rise (°C), $\beta$ is the heat radiation factor ($W^{-1} \cdot {}^{\circ}\text{C} \cdot \text{cm}^2$) and $\beta = 0.0023 \times S^{-0.2}$, $S$ is the surface area of the capacitor ($\approx 20 \text{ cm}^2$) and $\alpha$ is the factor of the temperature difference between the core and surface ($\alpha = 1.45$).

### 2.2.2. Output Inductor

The grid-tied solar inverter requires an output low-pass filter to eliminate the current ripple around the switching frequency. The values of the current ripple fundamental and its harmonics have to comply with the IEEE 1547 standards. The three main low-pass filters presented in the literature are the L-filter, the LC-filter, and the LCL-filter [28]. The LCL-filter is considered the most interesting due to its independence from the grid impedance and a better output response with the same inductance. However, designing such a filter has to consider many constraints, such as the resonance phenomenon or the capacitor's reactive power. As the aim of this paper is to compare two topologies, the same type of output filter is used. To ease the comparison, a classic L-filter will be designed for both topologies. It is important to note that elements of comparison (losses or size) are still relevant if an LC-filter or an LCL-filter is used for design.

The system has a unity power factor, and the control scheme adopted is a unipolar PWM. The inductance of the L-filter is given by the following formula [29]:

$$L_{Grid} = \frac{N \cdot V_{MPPT}}{4 \cdot \Delta I_{Grid} \cdot f_{sw}} = 1.9 \text{ mH} \quad (10)$$

where $\Delta I_{Grid}$ is the maximum current ripple (A) and $f_{sw}$ is the switching frequency (Hz). The maximum current ripple is chosen as 10% of the peak-rated inverter current ($I_{outpeak} = 28.9 \text{ A}$). A complete Fast Fourier Transform (FFT) analysis would normally be required to ensure that the grid-tied inverter complies with the IEEE 1547 standards for current harmonics. However, for comparison purposes, limiting the current ripple at the switching frequency is sufficient. Moreover, the switching frequency of a grid-tied solar
inverter with an output power of a few kW is often chosen within the range of 10 to 50 kHz. This choice is a compromise between the size of the output filter, the switching losses, the MCU performances, the leakage current etc. In this paper, the switching frequency ($f_{sw}$) is set to 20 kHz for both topologies.

The design of the inductor is done by using magnetic cores from the Ferroxcube Data Handbook 2013 [30]. As there is no magnetic core big enough to design a 1.9 mH/30 A inductor, two 950 µH/30 A are placed in series. The magnetic core of a single inductor is made using two E cores with an air gap on both center legs, as presented in Figure 4. For a 20 kHz application, the 3C90 ferrite has the maximum saturation magnetic field ($B_{sat}$ = 400 mT at $T$ = 50 °C).

<figure><img src="image_7.png" /><figcaption>Figure 4. Magnetic core of the inductor.</figcaption></figure>

In a 950 µH/30 A inductor, the energy stored $W_{mag}$ (W) in the air gap is:

$$W_{mag} = \frac{1}{2} \cdot \frac{L_{Grid}}{2} \cdot I_{rms}^2 = 0.2 \text{ W} \qquad (11)$$

The required air gap volume is:

$$V_{air gap} = \frac{2 \cdot W_{mag} \cdot \mu_0}{B_{sat}^2} \approx 3000 \text{ mm}^3 \qquad (12)$$

where $\mu_0$ is the vacuum permeability (H/m), $B_{sat}$ is the saturation magnetic field of the chosen core (3C90).

The chosen magnetic core is E71/33/32 with a 3900 µm air gap. The effective area of the core is $A_e$ = 683 mm². The datasheet of the core provides that the inductance factor is:

$$A_L = 315 \text{ nH/turns}^2 \qquad (13)$$

The number of turns $N_{turns}$ to reach a 950 µH inductance is:

$$N_{turns} = \sqrt{\frac{L_{grid}}{2 \cdot A_L}} \approx 55 \text{ turns} \qquad (14)$$

Given that the wiring must fit within the window area of the magnetic core, the copper section (mm²) is given by:

$$S_{copper} = \frac{W_a \cdot K}{N_{turns}} = 7 \text{ mm}^2 \qquad (15)$$

where $W_a$ is the window area (=569 mm²) and K is the fill factor (=0.7). This copper section had no issue handling the 20.46 $A_{rms}$ current.

The design of the coil must take into account the type of conductor chosen (litz wire or not). Indeed, for a cylindrical conductor with an alternating current, the current density
decreases exponentially from the surface toward the inside. This phenomenon, known as the skin effect, depends on the type of conductor and the frequency of the current [31]. It is characterized by the skin depth $\delta_{\theta}$ at temperature $\theta$, which must be higher than the radius of the conductor in order to minimize resistive losses.

$$ \delta_{\theta} = \sqrt{\frac{p_{\theta}}{\mu_{r} \cdot \mu_{0} \cdot \pi \cdot f}} \qquad (16) $$

where $p_{\theta}$ is the resistivity (Ω·m) of the conductor at temperature $\theta$, $\mu_{r}$ is the relative magnetic permeability of the conductor (1 for copper), $\mu_{0}$ is the permeability of free space (H·m⁻¹) and $f$ is the frequency of the current (Hz).

The copper resistivity depends on its temperature:

$$ p_{\theta} = p_{\theta_{0}} \cdot (1 + \alpha_{0} \cdot (\theta - \theta_{0})) \qquad (17) $$

where $\theta$ is the operating temperature (K), $\theta_{0}$ is the reference temperature (K), $\alpha_{0}$ is the temperature coefficient (K⁻¹), $p_{\theta}$ is the resistivity of the conductor at $\theta$ (Ω·m) and $p_{\theta_{0}}$ is the resistivity of the conductor at $\theta_{0}$ (Ω·m).

For copper, $p_{20^{\circ}\text{C}} = 1.68e^{-8} \Omega\text{m}$ and $\alpha_{0} = 4.04e^{-3} \text{ K}^{-1}$.

Thus:

$$ p_{75^{\circ}\text{C}} = 0.02 \ \mu\Omega\text{m} \qquad (18) $$

$$ \delta_{75^{\circ}\text{C}} = \sqrt{\frac{p_{75^{\circ}\text{C}}}{\mu_{r} \cdot \mu_{0} \cdot \pi \cdot f}} = 10 \text{ mm} \qquad (19) $$

The conductor used here has a much thinner radius (1.5 mm). There is no need to use litz wire for this application. Furthermore, the proximity effect is neglected in this topology due to the low frequency (50 Hz) of the AC current and the low RMS value of the high frequency (20 kHz) ripple (limited to 10% of the nominal current) [31].

Now that both the magnetic cores and the copper section have been designed, the copper and core losses of the two 950 µH inductors can be estimated:

$$ \begin{aligned} P_{\text{copper}} &= 2 \cdot \frac{N_{\text{turns}} \cdot l_{\text{turn}} \cdot \rho_{\text{copper}}}{S_{\text{copper}}} \cdot f_{\text{rms}}^2 \\ &= 50 \, \text{m}\Omega \times (20.46 \, \text{A})^2 = 20.9 \, \text{W} \end{aligned} \qquad (20) $$

where $l_{\text{turn}}$ is the average length of a turn (=160 mm) and $\rho_{\text{copper}}$ is the copper resistivity (Ω·m) at 75 °C.

The core losses can be calculated as follows:

$$ P_{\text{core}} = 2 \cdot P_{\text{core}_{20 \text{ kHz}}} = 2 \cdot V_e \cdot P_{\text{density}}(\Delta B, f_{\text{sw}}) \qquad (21) $$

where $P_{\text{core}_{20\text{kHz}}}$ are the core losses (W) of the 20 kHz ripple current $\Delta I_{\text{grid}}$, $V_e$ is the effective volume (m³) of the magnetic core and $P_{\text{density}}(\Delta B, f)$ is the core losses density (kW/m³) of the magnetic core for a given amplitude $\Delta B$ of the flux density B (T) and a given frequency f (Hz). The amplitude $\Delta B$ is calculated with the following formula [32]:

$$ \Delta B = \frac{1}{2} \cdot \frac{(N \cdot V_{\text{MPPT}} - V_{\text{grid}}) \cdot \frac{V_{\text{grid}}}{N \cdot V_{\text{MPPT}}} }{N_{\text{turns}} \cdot A_e \cdot f_{\text{sw}}} = 73 \, \text{mT} \qquad (22) $$

The datasheet provides:

$$ P_{\text{density}}(\Delta B, f) = k \cdot \Delta B^x \cdot f^y \qquad (23) $$

With $x = 1.46$, $y = 2.75$ and $k = 57$.

Thus, the core losses are:

$$ P_{\text{core}} = 700 \, \text{mW} \qquad (24) $$
The low core losses of the inductor are due to the low ripple current $\Delta I_{grid}$. A higher ripple would lead to a higher amplitude of the flux density $\Delta B$. The total losses in the inductor are:

$$P_{ind} = P_{copper} + P_{core} = 21.6 \text{ W} \qquad (25)$$

The characteristics of passive elements for the conventional H-Bridge are summarized in Table 4.

<table><caption>**Table 4.** Conventional H-Bridge design.</caption><thead><tr><th>Inverter Parameters</th><th>Name</th><th>Value</th><th>Reference</th><th>Series Resistance</th></tr></thead><tbody><tr><td>L-Filter</td><td>L<sub>Grid</sub></td><td>1.9 mH/30 A</td><td>E71/33/32 (×4)</td><td>R<sub>L</sub> = 50 mΩ</td></tr><tr><td>DC-link capacitor</td><td>C<sub>PV</sub></td><td>950 μF/600 V</td><td>B43541 (×21)</td><td>R<sub>c</sub> = 1.3 Ω (of a single capacitor)</td></tr><tr><td>Switching frequency</td><td>f<sub>sw</sub></td><td>20 kHz</td><td></td><td></td></tr></tbody></table>

## 2.3. MOSFET

The N-channel MOSFET chosen for this application must fulfill several requirements. First, a 25% tolerance is set for the maximum drain-to-source voltage based on the maximum DC-link voltage when all panels are at their open-circuit voltage. On top of that, a 25% tolerance is applied for the maximum drain current based on the maximum output current when all panels are at their optimum voltage under optimum weather conditions. Thus, the chosen MOSFET is at least a 650 V/35 A transistor.

In a grid-tied inverter with a conventional H-Bridge, the key power-loss contributors are the conduction losses, the switching losses, and the passive element (capacitors and inductors) losses. Indeed, the high maximum output current (~30 A) contributes to the maximal conduction losses, and the high maximum DC-link voltage (~500 V) contributes to the maximal switching losses. Most grid-tied solar inverters available on the market can reach a peak efficiency of around 97.5% at the nominal power level. For the design, it is decided that conduction and switching losses should not exceed 1% each of the total output power, and passive elements losses should not exceed 0.5% of the total output power. The efficiency at the nominal power point is thus set to be around 97.5%.

### 2.3.1. Conduction Losses

The conduction losses $P_{conduction}$ can be calculated using a MOSFET approximation with drain-source on-state resistance of $R_{ds-on}$. With a unipolar PWM, half of the transistors are on at any time. For each closed transistor, the complementary transistor is open. The conduction losses can be defined with the following formula:

$$P_{conduction} = 2 \cdot R_{ds-on} \cdot I_{out}^2 < 1\% \times P_{out} \qquad (26)$$

Then $R_{ds-on}$ (with a 100 °C junction temperature) is limited by the following equation:

$$R_{ds-on}(100 \,^{\circ}\text{C}) < 1\% \times \frac{P_{out}}{2 \cdot I_{out}^2} = 56 \text{ m}\Omega \qquad (27)$$

### 2.3.2. Switching Losses

The switching losses can be calculated as follow [33]:

$$P_{switching} = (E_{onMOSFET} + E_{onDiode} + E_{offMOSFET} + E_{offDiode}) \cdot f_{SW} \qquad (28)$$

where $P_{switching}$ are the switching losses, $E_{onMOSFET}$ and $E_{offMOSFET}$ are, respectively, the turn-on and turn-off energy for the MOSFET, $E_{onDiode}$ and $E_{offDiode}$ are, respectively, the turn-on and turn-off energy for the body diode during switching phases and $f_{sw}$ is the switching frequency.
The worst-case turn-on losses in a power MOSFET can be calculated as the sum of the switch-on energy without considering the reverse recovery process and the switch-on energy caused by the reverse recovery of the freewheeling diode [33]:

$$E_{on_{MOSFET}} = N \cdot V_{MPPT} \cdot I_{rms} \cdot \frac{t_{rise I} + t_{fall V}}{2} + Q_{rr} \cdot N \cdot V_{MPPT} \quad (29)$$

where $t_{rise I}$ is the rising current time (s) and $t_{fall V}$ is the falling voltage time (s) during switching phase, $Q_{rr}$ is the reverse recovery charge (C). The reverse recovery charge is selected for a 100 °C junction temperature and a $dI_F/dt$ rating current of 100 A/µs. The datasheet of a transistor usually only provides the reverse recovery charge for a 25 °C junction temperature.

$$Q_{rr}(T_j = 100 \,^{\circ}\mathrm{C}) \approx 2 \cdot Q_{rr}(T_j = 25 \,^{\circ}\mathrm{C}) \quad (30)$$

The switch-off losses in the diode are normally neglected ($E_{off_{diode}} = 0$) due to the low diode forward voltage compared to the DC-link voltage. The turn-on energy of the diode consists mostly of the reverse recovery energy:

$$E_{on_{Diode}} = \frac{1}{4} \cdot Q_{rr} \cdot N \cdot V_{MPPT} \quad (31)$$

The switch-off energy losses in the MOSFET can be calculated in the same way.

$$E_{off_{MOSFET}} = N \cdot V_{MPPT} \cdot I_{out} \cdot \frac{t_{fall I} + t_{rise V}}{2} \quad (32)$$

where $t_{fall I}$ is the falling current time (s) and $t_{rise V}$ is the rising voltage time (s) during switching phase.

By substituting (29), (31), and (32) into (28), the total switching losses are:

$$P_{switching} = N \cdot V_{MPPT} \cdot \left( \frac{l_{out}}{2} \cdot \left( t_{rise I} + t_{fall I} + t_{rise V} + t_{fall V} \right) + \frac{5}{4} \cdot Q_{rr} \right) \cdot f_{sw} \quad (33)$$

The rise time and fall time of the voltage are the only parameters that can be handled by external circuitry. Indeed, an external gate resistor is added between the driver and the gate of the MOSFET. It limits the noise and ringing in the gate drive path. However, increasing the rising and falling times leads to higher switching losses. On top of that, if transition times can no longer be neglected against the switching period $T_{sw} = 1/f_{sw}$, control issues may appear. For design purposes in this paper, the $dv/dt$ of the transistor is limited to 4 V/ns:

$$t_{rise V} + t_{fall V} = 2 \cdot \frac{N \cdot V_{MPPT}}{dv/dt} = 221 \text{ ns} \quad (34)$$

For information, the external gate resistor can be calculated based on the following equations [34]:

$$t_{fall V} = K_t \cdot \frac{C_{gd}(600 \text{ V}) + C_{gd}(0 \text{ V})}{2 \cdot (V_{driver} - V_{Miller})} \quad (35)$$

$$t_{rise V} = K_t \cdot \frac{C_{gd}(600 \text{ V}) + C_{gd}(0 \text{ V})}{2 \cdot V_{Miller}} \quad (36)$$

With:

$$K_t = (R_{gate}(ext) + R_{gate}(in)) \cdot (V_{MPPT} - R_{ds-on} \cdot I_{out})$$

where $R_{gate}(ext)$ is the external gate resistor (Ω), $R_{gate}(in)$ is the internal gate resistor (Ω), $V_{driver}$ is the voltage of the driver circuit (12 V), $V_{Miller}$ is the Miller voltage (V), $C_{gd}(Voltage)$ is the gate-drain capacitor (F) for a given voltage (V).
### 2.3.3. MOSFET Choice

The transistor chosen for the conventional H-Bridge design that complies with these constraints is the NTHL040N65S3F. Table 5 provides the parameters of the NTHL040N65S3F that are used to calculate all remaining losses.

<table><caption>**Table 5.** Parameters of the NTHL040N65S3F.</caption><thead><tr><th colspan="4">Parameters of the NTHL040N65S3F</th></tr></thead><tbody><tr><td>R<sub>ds-on</sub><sub>100 °C</sub> = 51 mΩ</td><td>Q<sub>rr</sub><sub>100 °C</sub> = 1.5 μC</td><td>V<sub>Miller</sub> = 6.2 V</td><td>Q<sub>g</sub> = 158 nC</td></tr><tr><td>t<sub>rise</sub> I = 41 ns</td><td>C<sub>gd</sub> (400 V) = 20 pF</td><td>R<sub>gate</sub>(int) = 2.4 Ω</td><td>V<sub>diode</sub> = 1.3 V</td></tr><tr><td>t<sub>fall</sub> I = 29 ns</td><td>C<sub>gd</sub> (0 V) = 2500 pF</td><td>t<sub>Dr</sub> = 41 ns</td><td>C<sub>oss</sub> = 140 pF</td></tr><tr><td></td><td></td><td>t<sub>Df</sub> = 101 ns</td><td></td></tr></tbody></table>

The conduction and switching losses are:

$$P_{\text{conduction}} = 43 \text{ W} \approx 1\% \text{ of } P_{\text{out}} \qquad (37)$$

$$P_{\text{switching}} = 43 \text{ W} \approx 1\% \text{ of } P_{\text{out}} \qquad (38)$$

The dead time losses depend on the body diode's forward voltage during phases when both transistors of a leg are off:

$$P_{\text{deadtime}} = V_{\text{diode}} \cdot I_{\text{rms}} \cdot (t_{\text{Dr}} + t_{\text{Df}}) \cdot f_{\text{SW}} = 70 \text{ mW} \qquad (39)$$

where $t_{Dr}$ and $t_{Df}$ are, respectively, the rising dead time (s) and falling dead time (s).

In unipolar PWM, gate charge losses for all the transistors are provided by the H-Bridge driver:

$$P_{\text{gate}} = 2 \cdot Q_g \cdot V_{\text{driver}} \cdot f_{\text{sw}} = 76 \text{ mW} \qquad (40)$$

where $Q_g$ is the gate charge (C).

The parasitic capacitance $C_{oss}$ of the MOSFET is also responsible for extra losses:

$$P_{\text{Coss}} = 2 \times \left( \frac{1}{2} \cdot C_{\text{oss}} \cdot (N \cdot V_{\text{MPPT}})^2 \cdot f_{\text{sw}} \right) = 550 \text{ mW} \qquad (41)$$

Approximately 3 W (including the gate charge losses) are necessary for the control side of the converter (microcontroller, sensors, and relays):

$$P_{\text{IC}} = 3 \text{ W} \qquad (42)$$

## 3. Design of the Cascaded H-Bridge Multilevel Inverter

### 3.1. Main Characteristics

The CHBMLI topology consists of several H-Bridge converters in a series. Each DC link is fed by a single solar panel. A capacitor, placed in parallel with the panel, is required to store the energy during phases when the H-Bridge's module output is bypassed [13]. The topology is presented in Figure 5.
<figure><img src="image_8.png" /><figcaption>Figure 5. Cascaded H-Bridge Multilevel Inverter (CHBMLI) configuration.</figcaption></figure>

## 3.2. Passive Elements

### 3.2.1. DC-Link Capacitor

The process of selecting the capacitor value is based on limiting the voltage ripple to 4% (the same limit as for the conventional H-Bridge). On the multilevel topology, the voltage ripple $\Delta V_{PV}$ is calculated from the voltage of a single solar panel at MPP (Maximum Power Point): $\Delta V_{PV} = 4\% \times V_{MPPT}$. The value of the capacitor per H-Bridge is calculated with the following formula:

$$C_{PV} = \frac{I_{MPPT}}{2 \cdot \Delta V_{PV} \cdot \omega_{Grid}} = 12.4 \, \text{mF} \qquad (43)$$

For 50 V capacitors, B41505 capacitors are considered (aluminum electrolytic capacitors from TDK). The capacitor $C_{PV}$ is made by paralleling four 3300 µF capacitors ($n_c = 4$).

The capacitor losses are mostly due to the ESR. The total capacitor losses are the sum of the capacitor losses per H-Bridge. On top of that, the ESR of those capacitors is estimated with an RMS capacitor current $I_{CRMS}$ at the switching frequency $f_{sw} = \frac{20 \, \text{kHz}}{N} = 1.5 \, \text{kHz}$ of each H-Bridge.

$$P_{cap} = N \cdot \left( \frac{R_c}{n_c} \cdot I_{rms}^2 \right) = 8.7 \, \text{W} \qquad (44)$$

where $R_c$ is the total ESR of the four ($n_c = 4$) capacitors at $f_{sw} = 1.5 \, \text{kHz}$ ($R_c = 36 \, \text{m}\Omega$) and $I_{CRMS}$ is the RMS current through the capacitor. Numerical simulations with MATLAB provide that: $I_{CRMS} \approx 8.6 \, \text{A}$.

The capacitor losses lead to a temperature rise for each capacitor:

$$\Delta T_c = \alpha \cdot \frac{P_{cap}}{\beta \cdot S \cdot n_c \cdot N} = 6.9 \, ^{\circ}\text{C} \qquad (45)$$

where $\Delta T_c$ is the surface heat rise (°C), $\beta$ is the heat radiation factor ($W^{-1} \cdot ^{\circ}\text{C} \cdot \text{cm}^2$) and $\beta = 0.0023 \times S^{-0.2}$, $S$ is the surface area of the capacitor ($\approx 30 \, \text{cm}^2$) and $\alpha$ is the factor of the temperature difference between the core and surface ($\alpha = 1.45$).
### 3.2.2. Output Inductor

As for the conventional H-Bridge, the switching frequency of the converter is set to 20 kHz, and the current ripple is chosen as 10% of the rated inverter current. The inductor is calculated by using the following equation:

$$L_{Grid} = \frac{V_{MPPT}}{4 \cdot \Delta I_{Grid} \cdot f_{sw}} = 147 \ \mu\text{H} \qquad (46)$$

The design of the inductor is done by using magnetic cores from the Ferroxcube Data Handbook 2013. As for the two inductors of the conventional H-Bridge, the magnetic core is made using two E cores with an air gap between both center legs. As for the design of the inductor in the conventional H-Bridge, a 3C90 ferrite is used.

In a 147 µH/30 A inductor, the energy stored $W_{mag}$ (W) in the air gap is:

$$W_{mag} = \frac{1}{2} \cdot L_{Grid} \cdot I_{rms}^2 = 0.031 \ \text{W} \qquad (47)$$

The required air gap volume is:

$$V_{air\ gap} = \frac{2 \cdot W_{mag} \cdot \mu_0}{B_{sat}^2} \approx 400 \ \text{mm}^3 \qquad (48)$$

The chosen magnetic core is E42/33/20 with a 1540 µm air gap to reach the proper air-gap volume. The effective area of the core is $Ae = 236 \text{ mm}^2$. The datasheet of the core provides that the inductance factor is:

$$A_L = 250 \ \text{nH/turns}^2 \qquad (49)$$

The number of turns $N_{turns}$ for a 147 µH inductance is:

$$N_{turns} = \sqrt{\frac{L_{Grid}}{A_L}} \approx 25 \text{ turns} \qquad (50)$$

Given that the wire must fit within the window area (=450 mm²) of the magnetic core, the copper section (mm²) is given by:

$$S_{copper} = \frac{W_a \cdot K}{N_{turns}} = 12.6 \ \text{mm}^2 \qquad (51)$$

Now that both the magnetic cores and the copper section have been designed, the copper and core losses can be estimated:

$$\begin{aligned} P_{copper} &= \frac{N_{turns} \cdot I_{turn} \cdot \rho_{copper}}{S_{copper}} \cdot I_{rms}^2 \\ &= 4 \ \text{m}\Omega \times (20.46 \ \text{A})^2 = 1.67 \ \text{W} \end{aligned} \qquad (52)$$

The core losses can be calculated as in Section 2. The low ripple current leads to a low amplitude of the flux density at 20 kHz (ΔB = 10 mT). This leads to a very low power loss density of the magnetic core. On top of that, the volume of the inductance is also very low. Thus, the core losses are neglected:

$$P_{core} \approx 0 \ \text{W} \qquad (53)$$

The total inductor losses are:

$$P_{ind} = P_{copper} + P_{core} = 1.67 \ \text{W} \qquad (54)$$
The characteristics of the chosen topology and its passive elements are summarized in Table 6.

<table><caption>**Table 6.** Cascaded H-Bridge Multilevel Inverter design.</caption><thead><tr><th>Inverter Parameters</th><th>Name</th><th>Value</th><th>Reference</th><th>Series Resistance</th></tr></thead><tbody><tr><td>L-Filter</td><td>L<sub>Grid</sub></td><td>147 µH/30 A</td><td>E42/33/20 (×2)</td><td>R<sub>L</sub> = 4 mΩ</td></tr><tr><td>DC-link capacitor</td><td>C<sub>PV</sub></td><td>12.4 mF/50 V</td><td>B41505 (4 in parallel per module, 52 in total)</td><td>R<sub>c</sub> = 36 mΩ</td></tr><tr><td>Switching frequency</td><td>f<sub>sw</sub></td><td>20 kHz</td><td></td><td>(ESR of a single capacitor)</td></tr></tbody></table>

### 3.3. MOSFET

For the N-channel MOSFET design, and as for the conventional H-Bridge, a 25% tolerance is applied on the maximum drain to source voltage and the maximum drain current. Thus, the chosen MOSFET is at least a 50 V/35 A transistor.

As for the design of the conventional H-Bridge, it is set that conduction and switching losses should not exceed 1% of the total output power, and passive element losses should not exceed 0.5% of the total output power.

#### 3.3.1. Conduction Losses

Given the fact that N H-Bridge converters are used in the CHBMLI instead of only one for the conventional H-Bridge under standard conditions, the current is passing through half the transistors of each H-Bridge. The limit for conduction losses is based on the following equation:

$$P_{\text{conduction}} = 2 \cdot N \cdot (R_{\text{ds-on}} \cdot I_{\text{out}}^2) < 1\% \times P_{\text{out}} \quad (55)$$

Then $R_{ds-on}$ (with a 50 °C junction temperature) is limited by:

$$R_{ds-on}(50 \,^{\circ}\text{C}) < 1\% \times \frac{P_{\text{out}}}{2 \cdot I_{\text{out}}^2 \cdot N} = 4 \, \text{m}\Omega \quad (56)$$

#### 3.3.2. Switching Losses

The full system switching losses are expressed by the following equation:

$$P_{\text{switching}} = N \cdot \left( V_{\text{MPPT}} \cdot \left( \frac{I_{\text{out}}}{2} \cdot t + \frac{5}{4} \cdot Q_{rr} \right) \cdot \frac{f_{sw}}{N} \right) \quad (57)$$

$$t = t_{\text{rise I}} + t_{\text{fall I}} + t_{\text{rise V}} + t_{\text{fall V}} \quad (58)$$

On average, each H-Bridge switches around $f_{sw}/N$ times per second.

#### 3.3.3. MOSFET Choice

The transistor chosen for the CHBMLI that complies with these constraints is the DMTH6004SK3. Table 7 provides the parameters of the DMTH6004SK3 that are used to calculate all the remaining losses.
<table><caption>**Table 7.** Parameters of the DMTH6004SK3.</caption><thead><tr><th colspan="4">Parameters of the DMTH6004SK3</th></tr></thead><tbody><tr><td>R<sub>ds-on50 C</sub> = 3.8 mΩ</td><td>Q<sub>rr50 C</sub> = 120 nC</td><td>V<sub>Miller</sub> = 4.5 V</td><td>Q<sub>g</sub> = 95 nC</td></tr><tr><td>t<sub>rise I</sub> = 11.7 ns</td><td>C<sub>gd</sub>(40 V) = 40 pF</td><td>R<sub>gate(int)</sub> = 660 mΩ</td><td>V<sub>diode</sub> = 0.9 V</td></tr><tr><td>t<sub>fall I</sub> = 12 ns</td><td>C<sub>gd</sub>(0 V) = 1 nF</td><td>t<sub>Dr</sub> = 13 ns</td><td>C<sub>oss</sub> = 1383 pF</td></tr><tr><td></td><td></td><td>t<sub>Df</sub> = 31 ns</td><td></td></tr></tbody></table>

The conduction and switching losses are:

$$P_{\text{conduction}} = 42 \text{ W} \approx 1\% \text{ of } P_{\text{out}} \qquad (59)$$

$$P_{\text{switching}} = 5 \text{ W} \approx 0.1\% \text{ of } P_{\text{out}} \qquad (60)$$

The dead time losses depend on the body diode's forward voltage during phases when both transistors of a leg are off:

$$P_{\text{deadtime}} = N \cdot \left( V_{\text{diode}} \cdot I_{\text{rms}} \cdot (t_{\text{Dr}} + t_{\text{Df}}) \cdot \frac{f_{\text{SW}}}{N} \right) = 21 \text{ mW} \qquad (61)$$

In unipolar PWM, gate charge losses for all the transistors are provided by the H-Bridge driver:

$$P_{\text{gate}} = 2N \cdot \left( Q_{g} \cdot V_{\text{driver}} \cdot \frac{f_{sw}}{N} \right) = 590 \text{ mW} \qquad (62)$$

The parasitic capacitance C<sub>oss</sub> of the MOSFET is also responsible for extra losses:

$$P_{\text{Coss}} = 2N \cdot \left( \frac{1}{2} \cdot C_{\text{oss}} \cdot V_{\text{MPPT}}^2 \cdot \frac{f_{sw}}{N} \right) = 410 \text{ mW} \qquad (63)$$

Approximately 300 mW (including the gate charge losses per H-Bridge) are necessary for the control side of each converter (microcontroller, sensors, communication), and 3 W are necessary for the Master control of the full converter (microcontroller, communication, and relays):

$$P_{\text{IC}} = N \times 300 \text{ mW} + 3 \text{ W} = 6.90 \text{ W} \qquad (64)$$

## 4. Discussion

The aim of this section is to compare the design of the two converters in terms of size and cost for the passive elements on the basis of simulations. Efficiencies of both converters are also assessed for the full range of output power. Finally, the costs of MOSFETs (+driver and heatsink) for both converters are compared. Simulations of both topologies are performed under the MATLAB/SIMULINK platform.

### 4.1. Circuit Simulations

The waveforms of both converters are shown in Figure 6. The parameters used for the two simulations are presented in Table 2. The multilevel ability of the CHBMLI offers much more possibilities in terms of reducing the harmonics than the Conventional H-Bridge [35]. However, the comparison made in this study only considers the grid current ripple and neglects the harmonics in order to use the control algorithm for the CHBMLI presented by the authors in a previous study [36], as these algorithms do not yet include specific harmonics elimination. Several control algorithms, such as Selective Harmonics Elimination Pulse Width Modulation (SHE-PWM), can be used to remove current harmonics and reduce Total Harmonic Distortion (THD) [21]. Conventional control with integrated control loops [37] is used for the Conventional H-Bridge (CHB) with a unipolar PWM.
<figure><img src="image_9.png" /><figcaption>**Figure 6.** (a) Grid Voltage (red) and Grid Current (blue) for the CHB (b) Grid Voltage (red) and Grid Current (blue) for the CHBMLI (c) Inverter Voltage (red) for the CHB (d) Inverter Voltage (red) for the CHBMLI (e) PV Voltage for the CHB (blue) (f) PV Voltages for the CHBMLI.</figcaption></figure>

The Conventional H-Bridge (CHB) and the CHBMLI both have a maximum output current ripple $\Delta I_{grid}$ limited to 10% of the peak output current $I_{grid,peak}$ (Figure 6a,b), which validate the design of both inductors. Furthermore, for both simulations, the current (blue) is set in phase with the grid voltage (red). The THD of the CHBMLI (1.9%) is slightly lower than the THD of the CHB (2.5%). This is due to the control algorithm that mitigates some harmonics. However, the THD of the CHBMLI could be further improved by using Selective Harmonics Elimination [21]. The output waveform of both inverters is presented in Figure 6c for the CHB and Figure 6d for the CHBMLI. The CHB has a three-level output voltage with high switching voltages (~450 V), and the CHBMLI has a stair-shaped output
waveform with low switching voltages (~34 V). The waveform of the CHBMLI, almost sinusoidal, visually explains why the inductor is much lower for a similar grid current ripple than the CHB. Finally, both converters have an identical DC-link voltage ripple $\Delta V_{PV}$ limited to 4% of the optimal voltage $V_{MPPT}$ (Figure 6e,f), which validates the design of both capacitors. In the case of the CHBMLI, the converter regulates each DC-link voltage of the N modules around $V_{MPPT}$ with the same ripple $\Delta V_{PV}$. The waveforms of the DC-link voltages of the CHBMLI are not as sinusoidal as the one of the CHB, because the average switching frequency of each module is $f_{sw}/N$.

## 4.2. Passive Elements

Elements of comparison for the design and the choice of the capacitor are presented in Table 8.

<table><caption>**Table 8.** Comparison of the capacitor design.</caption><thead><tr><th>Topology</th><th>Capacitance per H-Bridge</th><th>Number of Capacitor</th><th>Capacitor Losses</th></tr></thead><tbody><tr><td>Conventional H-Bridge</td><td>950 µF/600 V</td><td>21</td><td>4.5 W</td></tr><tr><td>CHBMLI</td><td>12.3 mF/50 V</td><td>52</td><td>8.8 W</td></tr></tbody></table>

For the conventional H-Bridge, the amount of stored energy ($E_{stored}$) to limit the ripple voltage $\Delta V$ on the DC-link voltage is:

$$E_{stored} = \frac{1}{2} \cdot (950 \ \mu\text{F}) \cdot (N \cdot V_{MPPT})^2 = 93 \ \text{J} \qquad (65)$$

For the CHBMLI:

$$E_{stored} = N \times \frac{1}{2} \cdot (12.3 \ \text{mF}) \cdot (V_{MPPT})^2 = 93 \ \text{J} \qquad (66)$$

The same amount of energy needs to be stored under both voltages because in both topologies, the global input DC power and the global output AC power are identical. The cost of capacitors is proportional to the energy stored $E_{stored}$. From that perspective, the CHBMLI has no direct advantages compared to the conventional H-Bridge regarding the cost and volume of the DC-link capacitors.

The capacitor choice for both topologies is presented in Table 8. For the CHBMLI, the required capacity can be divided into up to 52 capacitors. For the conventional H-Bridge, 21 capacitors (47 µF/600 V) are placed in parallel. The capacitor losses are higher on the CHBMLI topology because the RMS current per H-Bridge has a lower frequency ($f_{sw}/N$ = 1.5 kHz) than the RMS current on the H-Bridge of the conventional H-Bridge Inverter. As the ESR of a capacitor decrease with the frequency, the global capacitor ESR in a CHBMLI is higher than the global capacitor ESR in a conventional H-Bridge. However, the extra losses in the CHBMLI are very low compared to the other losses (conduction, switching, inductor). On top of that, the temperature rise (12 °C for the CHBMLI compared to 7 °C for the conventional H-bridge) of each capacitor is very low. As a result, the lifespan expectancy will not be affected by those losses.

The inductor choice for both topologies is presented in Table 9. The value of the inductor is proportional to the switched voltage ($N \cdot V_{MPPT}$ for the conventional H-Bridge and $V_{MPPT}$ for the CHBMLI). The use of N low voltage modules in a CHBMLI leads to a reduction of the inductor's value by a factor of N. Cost and volume are proportional to the value of the inductor at the same current value. Thus, a much cheaper and lighter inductor is used for the CHBMLI at the same current ripple. The volume (and the price) of the magnetic core of the inductor of the CHBMLI is reduced by almost a factor of N. On top of that, the volume (and cost) of the copper for the CHBMLI inductor is also reduced by almost a factor of N. This leads to low copper losses due to a very low ESR of the inductor
(4 mΩ for the CHBMLI and 50 mΩ for the conventional H-Bridge)—the low output current ripple leads, in both topologies, to reduced core losses. As a result, the inductor losses and the cost of this output filter in a CHBMLI are both very low.

<table><caption>**Table 9.** Comparison of the inductor design.</caption><thead><tr><th>Topology</th><th>Inductor</th><th>Magnetic Core</th><th>Inductor Losses (P<sub>ind</sub>)</th></tr></thead><tbody><tr><td>Conventional H-Bridge</td><td>1.9 mH/30 A</td><td>E71/33/32 (×4)</td><td>21.6 W</td></tr><tr><td>CHBMLI</td><td>147 μH/30 A</td><td>E42/33/20 (×2)</td><td>1.67 W</td></tr><tr><td><strong>Topology</strong></td><td><strong>Copper Cost (weight)</strong></td><td><strong>Magnetic Core Cost</strong></td><td><strong>Total cost</strong></td></tr><tr><td>Conventional H-Bridge</td><td>$21.2 (2.28 kg)</td><td>$48</td><td>$69.2</td></tr><tr><td>CHBMLI</td><td>$2.5 (0.27 kg)</td><td>$3.4</td><td>$6.0</td></tr></tbody></table>

### 4.3. Power Losses and Efficiency

The loss comparison between the conventional H-Bridge and the CHBMLI is shown in Figure 7a. The switching losses for the CHBMLI are much lower. Indeed, switching low voltages combined with the use of transistors that have a much lower reverse recovery charge (due to their low voltage rating) leads to a reduction by almost a factor of 10 of the switching losses. The conduction losses in both topologies are similar because both transistors were chosen as such. The CHBMLI requires more IC operating power than the unique control board of the conventional H-Bridge. It has been estimated in this case that the amount of power required is double. However, it does not affect the overall efficiency due to its low value. Inductor and capacitor losses have already been discussed.

<figure><img src="image_10.png" /><figcaption>**Figure 7.** (a) Losses distribution comparison at maximum output power (b) Efficiency comparison.</figcaption></figure>

The efficiency of both converters in the function of the total output power is shown in Figure 7b. The CHBMLI has better efficiency than the conventional H-Bridge for any output power. Overall, the key factors that contribute to the better efficiency of the CHBMLI are reduced switching and inductor losses. The reduced losses both come from the low switching voltages of the CHBMLI due to its multilevel ability. At low output power (<100 W), the efficiencies of both converters are affected by their IC operating losses because they remain constant regardless of the output power. As the power increases, the efficiency increases as well because the IC operating losses become negligible. Around 1500 W, both converters reach their peak efficiencies: 98.2% for the conventional H-Bridge and 99% for the CHBMLI. From that point, efficiencies decrease due to conduction and inductor losses. Indeed, unlike other losses, they are proportional to $I_{out}^2$ (when $P_{out}$ is proportional to $I_{out}$). At 4700 W, the efficiency of the conventional H-Bridge is 97.9%, and the efficiency of the CHBMLI is 98.4%. For any output power, the efficiency of the CHBMLI is at least superior to the efficiency of the conventional H-Bridge by 0.5%.
## 4.4. MOSFETs

### 4.4.1. Temperature Rise

Limiting the temperature rise is then a trade-off between the size and cost of the heatsink and MOSFETs lifespan and losses. A proper comparison of the transistors must be made by considering the same temperature rise. The losses per transistor in both topologies are:

$$P_{\text{Total MOSFET}} = P_{\text{conduction}} + P_{\text{switching}} \qquad (67)$$

$$(Losses_{perMOSFET})_{CHBMLI} = \left(\frac{P_{Total MOSFET}}{4N}\right)_{CHBMLI} = \frac{46.4W}{4N} = 890 \text{ mW} \qquad (68)$$

$$(Losses_{perMOSFET})_{HB} = \left(\frac{P_{Total MOSFET}}{4}\right)_{HB} = \frac{84.6 \text{ W}}{4} = 21.1 \text{ W} \qquad (69)$$

First, for the CHBMLI with maximum output power, the temperature rise of each transistor without any heatsink is:

$$\Delta T_{\text{MOSFET}_{\text{CHBMLI}}} = (Losses_{perMOSFET})_{\text{CHBMLI}} \times R_{j-a} = 36^{\circ}\text{C} \qquad (70)$$

where $R_{j-a}$ is the junction-to-ambient thermal resistance ($R_{j-a}$ = 40 K/W). In a converter design, the junction temperature of a transistor is usually limited to 100 °C. A 36 °C temperature rise at maximum output power is perfectly acceptable for a solar inverter. No heatsink is required for the CHBMLI. For the conventional H-Bridge with maximum output power, the temperature rise of each transistor without any heatsink is:

$$\Delta T_{\text{MOSFET}_{\text{HB}}} = (Losses_{perMOSFET})_{\text{HB}} \times R_{j-a} = 846^{\circ}\text{C} \qquad (71)$$

This high temperature rise is caused by complete losses distributed on a reduced number of transistors. On top of that, due to lower efficiency, the total transistors losses are higher for the conventional H-Bridge. Finally, compared to the CHBMLI, each transistor dissipates significantly more energy. In this case, a heatsink is required. We chose to use a single heatsink on which all the transistors are fixed. The value of the heatsink is calculated to limit the junction temperature to $T_{\text{junctionlim}}$ = 100 °C, which means a temperature rise of 75 °C from an ambient temperature of 25 °C:

$$\Delta T_{\text{MOSFET}_{\text{HB}}} = (Losses_{perMOSFET})_{\text{HB}} \times (R_{j-c} + R_{c-h} + 4 \cdot R_{h})_{\text{HB}} = 75^{\circ}\text{C} \qquad (72)$$

where $R_{j-c}$ is the junction-to-case thermal resistance (0.5 K/W), $R_{c-h}$ is the case-to-heatsink thermal resistance (0.5 K/W) and $R_h$ is the required heatsink thermal resistance (K/W).

Then:

$$R_h = \frac{1}{4} \left( \frac{\Delta T_{\text{MOSFET}_{\text{CHBMLI}}}}{(Losses_{perMOSFET})_{\text{HB}}} - R_{j-c} - R_{c-h} \right) \qquad (73)$$

Thus:

$$R_h = 0.6 \text{ K/W} \qquad (74)$$

The chosen heatsink is a 0.6 K/W heatsink from ABL components (109AB1500B, $14).

### 4.4.2. Gate Drivers

The selected MOSFET drivers for the conventional H-Bridge are two UCC21520 Isolated Dual-Channel Gate Drivers. These drivers are designed to power MOSFETs with a very low propagation delay (typically 19 ns) and a high common-mode transient immunity (up to 100 V/ns). On each driver, both channels are fully isolated and are guaranteed to operate with a DC voltage up to 1500 V.

For the CHBMLI, a unique H-bridge driver is used: the MIC4606. This driver also has a very low propagation delay (typically 35 ns) and very low power consumption. It uses
a bootstrap circuit to supply the two high-side transistors per H-Bridge up to a maximal voltage of 80 V. Those drivers do not need to be isolated because they are directly powered by the solar panel (through a small local power supply).

### 4.4.3. Overall Cost

The overall cost for the MOSFETs (including the drivers and the heatsink) is presented in Table 10. The CHBMLI uses N times more transistors than the conventional H-Bridge. However, those transistors are much cheaper due to their low voltage characteristics and compact packages. The addition of drivers (more expensive for the CHBMLI) makes the cost (MOSFETs + driver) similar between the two topologies. In the end, the need for a heatsink for the conventional H-Bridge leads to a higher overall cost (for the MOSFETs part) than for the CHBMLI.

<table><caption>**Table 10.** MOSFETs + Driver + Heatsink.</caption><thead><tr><th colspan="3">Conventional H-Bridge</th><th colspan="3">CHBMLI</th></tr><tr><th></th><th>Reference</th><th>Number</th><th>Cost</th><th>Reference</th><th>Number</th><th>Cost</th></tr></thead><tbody><tr><td>MOSFETs</td><td>NTHL040N65S3F</td><td>4</td><td>$44</td><td>DMTH6004SK3</td><td>52</td><td>$27</td></tr><tr><td>Driver</td><td>UCC21520</td><td>2</td><td>$6</td><td>MIC4606</td><td>13</td><td>$28</td></tr><tr><td>Heatsink</td><td>109AB1500B</td><td>1</td><td>$17</td><td></td><td></td><td></td></tr><tr><td><strong>Total</strong></td><td></td><td></td><td><strong>$67</strong></td><td></td><td></td><td><strong>$45</strong></td></tr></tbody></table>

This paragraph does not take into account the cost of the other components in the complete converter (AOP for measurements, microcontroller, onboard power supply). It is expected that, when adding the total cost of every component of the circuit, the CHBMLI might not keep its advantage.

### 4.5. Summary

All the comparison points of this section are summed up in Table 11.

<table><caption>**Table 11.** Summary of comparison points between both topologies.</caption><thead><tr><th></th><th>Conventional H-Bridge</th><th>CHBMLI</th></tr></thead><tbody><tr><td>MOSFETs-Conduction Losses</td><td>43 W</td><td>43 W</td></tr><tr><td>MOSFETs-Switching Losses</td><td>43 W</td><td>5 W</td></tr><tr><td>Temperature rise per MOSFET</td><td>75 °C</td><td>36 °C</td></tr><tr><td>Cost of MOSFETs (+driver + heatsink)</td><td>$67</td><td>$45</td></tr><tr><td>Capacitor-Losses</td><td>4.5 W</td><td>8.5 W</td></tr><tr><td>Inductor-Losses</td><td>21.6 W</td><td>1.7 W</td></tr><tr><td>Inductor-Cost</td><td>$69.2</td><td>$6.0</td></tr><tr><td>Peak efficiency</td><td>98.2%</td><td>99.0%</td></tr></tbody></table>

## 5. Experimental Measurements for the CHBMLI

The objective of this section is to validate the thermal design of the CHBMLI through a temperature measurement on a real prototype. Only the CHBMLI prototype was built to limit the time and resources required. Furthermore, due to limited equipment, this validation is performed by measuring the efficiency and temperature of a single module operating at its rated power (365 W). For this purpose, a sinusoidal four-quadrant power supply (TOE7610) is used on the output, while a DC power source (Cpx400D) is used on the input. On the other hand, a prototype composed of eight modules used at a lower power is tested to provide the inverter waveforms, such as the inverter voltage $V_{inverter}$, the module output voltage $V_H$ and the output grid current $I_{grid}$.

The control of the converter was detailed in previous work by the authors. First, it was demonstrated that it is possible to control the CHBMLI with a hardware architecture having up to 20 modules with a switching frequency of 20 kHz [36]. A second paper detailed how this topology can be controlled with a reduced number of sensors [23] while
operating, for each solar panel, an individual Maximum Power Point Tracking (MPPT) algorithm with minimum power oscillations. Those papers demonstrate that the CHBMLI can be controlled with low-cost components while maintaining a wide range of operations (number of modules > 20).

## 5.1. Experimental Setup

The experimental setup for the CHBMLI is presented in Figure 8. Figure 8a presents the prototype of the CHBMLI with 8 H-Bridge modules with all the output placed in series, Figure 8b presents the master controller of the inverter with the main MCU (STM32F446RE), and Figure 8c presents the circuit with isolated AC voltage and current sensors and relays to connect the inverter to the grid. This setup was designed according to the elements detailed in Section 3.

<figure><img src="image_11.png" /><figcaption>Figure 8. (a) Experimental setup of the Cascaded H-Bridge Multilevel Inverter with eight modules (b) Master controller of the CHBMLI (c) Circuit with isolated AC sensors and relays for the CHBMLI.</figcaption></figure>

## 5.2. Temperature Rise of a Single Module (CHBMLI)

A single module is detailed in Figure 9a. The left side of the board contains the power converter (H-Bridge and capacitors). Under an input power of 365 W and a switching frequency of 1.5 kHz (for the H-Bridge of this module), the power switches have a temperature rise of 32 °C (Figure 9b), which validates the thermal analysis presented in Section 4.4. The measured efficiency (including IC operating losses) is 98.5%. This measurement does not include inductor losses. However, with a full converter at nominal power, the low inductance value would not significantly modify the overall efficiency. This low temperature rise confirms that no heatsink is required to maintain the junction temperature of the MOSFETs below 100 °C. On top of that, in a conventional inverter, the heat released by the MOSFETs (with heatsink) usually increases the temperature of the DC-link capacitors, which have to be placed close to the H-Bridge in order to reduce the parasitic inductance of the track. This temperature rise of the DC-link capacitor often leads to faster aging and reduced lifetime [38]. Failure of the aluminum electrolytic of the DC-link capacitor is one of the most common faults on a conventional H-bridge.
<figure><img src="image_12.png" /><figcaption>Figure 9. (a) Prototype of a single module of the Cascaded H-Bridge Multilevel Inverter (CHBMLI) (b) Thermal image of a module at $P_{out}$ = 365 W.</figcaption></figure>

### 5.3. Waveforms of the CHBMLI

The waveform of the CHBMLI voltage $V_{inverter}$ (in red) and the output current (in blue) are shown in Figure 10a. This figure is zoomed over a half grid period in Figure 10b, including in green the output voltage of a single module. The low switching frequency (in green) of a single module (compared to the high switching frequency $f_{sw}$ = 20 kHz of the complete converter) can be observed.

$$f_{sw_{module}} = \frac{f_{sw}}{N} = 2.5 \text{ kHz} \qquad (75)$$

<figure><img src="image_13.png" /><figcaption>Figure 10. (a) Waveforms of the CHBMLI with $I_{grid,rms}$ = 3 A, N = 8, $V_{grid,rms}$ = 180 V: Current grid $I_{grid}$ (blue), Inverter Voltage $V_{inverter}$ (red), Grid voltage $V_{grid}$ (black) (b) Same as (a) but including the output voltage of a single module $V_{H_i}$ (green).</figcaption></figure>

Due to limited power on the experimental setup, the complete converter was tested with 70 W per module. This results in an output RMS current of 3 A, and an off-the-shelf inductor was chosen for this current (2 mH/5 A) to limit the harmonics. For the same output current, a high-frequency ripple, a bigger inductor would be required (by a factor N = 8). The output sinusoidal current (in blue) is set in phase with the grid voltage (in black) in order to ensure a unity power factor. On top of that, each solar panel is regulated around its own optimal voltage ($V_{MPPT_i}$). Thus, the energy extraction is maximized by the
CHBMLI. Under partially shaded weather conditions, the CHBMLI extracts more power than the conventional H-Bridge.

**6. Conclusions**

A comparison between the design of the conventional H-Bridge and the CHBMLI is presented in this paper. First, a series of constraints regarding the efficiency, the maximum solar power extraction, the components' lifespan, and the cost were established to make the comparison as realistic as possible. For both topologies, inductors, capacitors, transistors, and heatsink are sized. The multilevel ability of the CHBMLI makes it more interesting when it comes to filtering the output current of the inverter, thus reducing the size and cost of the inductor. As both topologies are DC-AC converters with the same amount of DC and AC power and considering the same DC-link voltage ripple ratio, the capacitor's energy sizing is similar in both cases. For the conventional H-Bridge, low-value and medium-voltage capacitors are used, and for the CHBMLI, medium-value and low-voltage capacitors are used. The reduced choices for capacitors for the CHBMLI lead to higher global ESR, which creates slightly higher losses. When it comes to global efficiency, the CHBMLI has a serious advantage due to very low switching losses compared to the conventional H-Bridge, thanks to low voltage levels. The reduced losses, which are furthermore spread over a higher number of transistors, lead to low temperature rise without the need for a heatsink for the CHBMLI. For the conventional H-Bridge, the trade-off between cost and efficiency leads to the use of a heatsink to cool transistors. The vast choice of small voltage transistors (for the CHBMLI), despite the large number of transistors required, makes it easier to select low-cost components for the design. The cost of medium voltage transistors combined with the cost of the heatsink and the isolated drivers is about 50% superior to the cost of transistors and the drivers for the CHBMLI with the same performances (same global conduction losses and same temperature rise). A real CHBMLI prototype with eight modules was built to validate several aspects of the design. The converter was tested with a 20 kHz switching frequency on the grid voltage with a sinusoidal output current of 3 Arms, a low current ripple, and a unity power factor. The low temperature rise (without a heatsink) of a single module at 365 W was also validated.

**Author Contributions:** Conceptualization, T.B., G.D. and R.T.; methodology, T.B., G.D. and R.T.; software, T.B.; validation, T.B.; formal analysis, T.B., G.D. and R.T.; investigation, T.B.; resources, T.B.; writing—original draft preparation, T.B.; writing—review and editing, T.B., G.D. and R.T. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research received no external funding.

**Conflicts of Interest:** The authors declare no conflict of interest.

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