# High-Power 4500 V 5000 A Press Pack IGBTs for HVDC Solid-State Circuit Breaker Application

Koushik Sasmal, Josef Schmidt, Markus Droldner, Christof Drilling, Jens

Przybilla, Hans-Peter Felsl, Martin Hennig

► To cite this version:

Koushik Sasmal, Josef Schmidt, Markus Droldner, Christof Drilling, Jens Przybilla, et al. High-Power 4500 V 5000 A Press Pack IGBTs for HVDC Solid-State Circuit Breaker Application. The 26th European Conference on Power Electronics and Applications, GDR SEEDS France & EPE Association, Mar 2025, Paris, France. 10.34746/epe2025-0146. hal-05105972

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# High-Power 4500 V 5000 A Press Pack IGBTs for HVDC Solid-State Circuit Breaker Application

K.Sasmal(1), J.Schmidt(2), M.Droldner(5), C.Drilling(6), J.Przybilla(7)

Infineon Technologies Bipolar GmbH & Co. KG
Max-Planck-Strasse 5, 59581, Warstein, Germany

Tel.: +49 2902 9899 1671

E-Mail: Koushik.Sasmal@infineon-bip.com, Josef.Schmidt@infineon-bip.com, Markus.Droldner@infineon-bip.com, Christof.Drilling@infineon-bip.com, Jens.Przybilla@infineon-bip.com

URL: https://www.ifbip.com/

H-P. Felsl(3), M.Hennig(4),

Infineon Technologies AG
Am Campeon 1-15, 85579, Neubiberg, Germany

Tel.: +49 89 234 26711

E-Mail: Hans-Peter.Felsl@infineon.com, Martin.Hennig@infineon.com

URL: https://www.infineon.com/

## Keywords

«Press-Pack IGBT», «Solid-state DC Circuit Breaker», «Short-time withstand current», «DC Grid», «DC Short Circuit».

## Abstract

Low Temperature Sintered Press-pack IGBTs (PPI) outperform modules, offering improved cooling efficiency, reliability, and significantly higher-current handling. A single 4500 V, 5000 A PPI is designed to withstand 20-30 kA DC system short-circuit currents for 150 ms, making PPI a robust and space-saving choice for solid-state DC breaker applications.

## Introduction

Europe aims to become climate-neutral by 2050, with Germany targeting net zero emissions by 2045. To achieve this, the production and distribution of clean energy must be optimized. The installation of wind turbines in the North Sea will significantly increase, with transmission system operator Tennet planning to triple its capacity to 40.4 GW by 2030 [1]. Pioneering projects, such as the High Voltage Multiterminal Hub in Heide, North Germany, will connect HVDC offshore lines and onshore cables, marking the first commercial use of HVDC circuit breakers in Europe [2]. This sets the stage

for the development of innovative DC circuit breaker technologies.

## DC Circuit Breakers

Beyond HVDC circuit breakers, there is a growing interest in MVDC circuit breakers for various applications, including meshed MVDC networks, industrial DC grids, vessel DC grids, traction DC grids, and electrolysis.

Currently, two DC circuit breaker concepts are being explored: the hybrid circuit breaker (HCB) and the solid-state circuit breaker (SSCB). The HCB design relies on a vacuum interrupt switch (VIS) to carry the load current during normal operation, while a semiconductor takes over for up to 1 ms during switching. The semiconductor's role is to conduct the current for a brief period and then turn off the current. IGBTs, either as discrete devices or modules, are commonly used in hybrid DC breakers. [3]

<figure><img src="image_2.png" /><figcaption>Fig.1: Hybrid Circuit Breaker</figcaption></figure>
In Solid-State Circuit Breakers (SSCBs), IGBTs must conduct DC current throughout the operation, necessitating cooling of the semiconductors. For bidirectional operation, a common approach is to use two IGBTs with anti-parallel diodes in an anti-series setup. In this configuration, diodes with low on-state losses, such as rectifier diodes, are beneficial, as they do not require high di/dt turn-off capability against negative voltage.

<figure><img src="image_3.png" /><figcaption>Fig.2: Schematic of a bidirectional SSCB [4]</figcaption></figure>

## Press Pack IGBT

Press-pack IGBTs (PPIs) have been widely used in high-power applications due to their efficient conversion of direct and alternating current. They offer advantages over solder bond modules in applications with strongly changing loads, eliminating errors such as delamination and bond wire detachment. The stackable design enables efficient cooling on both sides, while the hermetically sealed explosion resistant ceramic housing protects the semiconductors from environmental influences, ensuring a long lifetime. In DC circuit breaker applications, the internal chip stack structure and copper masses on the collector and emitter are particularly crucial.

## Chip Technology

For this press pack application for which low conduction losses, which means low Vcesat values are mandatory, the well-established 4.5 kV Infineon trench stop IGBT technology basis was used and was further optimized to adapt for this special low Vcesat requirement. The trench stop IGBT technology is in commercial production for many years up to now and provides proven high reliability and was therefore the right starting point for further optimization [5].

<figure><img src="image_4.png" /><figcaption>Fig.3: IGBT Structure</figcaption></figure>

The IGBT structure shown in the schematic in Fig.3, consists of the Infineon quadratic cell structure, and provides on the front side a gate trench, a p-body region and a p float region between the IGBT cells. Between front and backside of the IGBT the drift region is placed. At the collector side a field stop structure is implemented in front of the p emitter.

The first main features of the trench stop technology is the trench gate cell-structure to achieve low conduction losses with negligible influence on the tail current and turn-off losses. Compared to planar cell geometry the better carrier confinement and plasma profile results in lower conduction losses and therefore provides lower Vcesat. The second feature is the implemented field stop structure. The combination of a high resistive drift zone and the field stop region allows thickness reduction without losing blocking capability and cosmic ray ruggedness and results in further reduction of conduction losses due to a thinner possible IGBT drift region.

In the IGBT cell additionally a channel width as high as possible is realized to achieve low Vcesat values without sacrificing electrical short circuit ruggedness. At the collector side of the IGBT the implemented n doped field stop region provides besides the blocking capability, good switching off characteristics which means, that at application relevant switching conditions, a soft switching off behaviour without ringing is guaranteed [6]. In this special press pack chip design to further optimize with respect to conduction losses, the p emitter doping and design was chosen in a range and way that the Vcesat of the IGBT could be driven to the minimum possible value without violating overcurrent turn off ruggedness requirements.

Furthermore, only slight mechanical modifications were needed to adapt the chip for
use in press pack modules. One further big goal for the application of the trench stop technology is the increase of the maximum operation temperature from 125 °C up to 150 °C. Besides this benefit, the conduction losses are reduced significantly compared to IGBTs with planar cell technology as explained above. The typical on-state voltage Vcesat we can achieve with this further optimized trench stop technology @ Tj = 25°C (RT) is the very low value of 2.16 V and @ Tjmax = 150 °C a Vcesat of 2.7 V is achievable. The discrete IGBT chips are bonded with Molybdenum discs using Low Temperature Sintering process. Low-Temperature Sintering (LTS) is an innovative bonding technology that enables the creation of reliable and robust connections between silicon and molybdenum in high-power semiconductor devices. This technology offers several advantages, including improved robustness against thermal and mechanical stress and high power cycling capability as explained in [7].

## Packaging Concept

The packaging concept of the Infineon 4500V 5000 A P5000Z PPI with a required number of paralleled chips inside, is fairly straightforward. The chips, bonded to molybdenum disks on both sides using Low-Temperature Sintering (LTS), are pressure-contacted to solid copper terminals on the collector and emitter sides [9]. The copper serves as both an electrical conductor and heat spreader, while also functioning as a thermal reservoir to absorb power losses from short-term pulses and prevent overheating.

<figure><img src="image_5.png" /><figcaption>Fig.4: Construction of a PPI</figcaption></figure>

Generally, to achieve the required interrupting current, parallel connection of multiple IGBT modules is necessary. IGBT modules with single-sided cooling and limited internal heat sinks are a significant disadvantage in this regard. IGBT modules necessitate a larger installation space,

which in turn leads to increased complexity and a higher failure-in-time (FIT) rate, ultimately affecting the overall reliability of the system. Another big advantage is the ceramic housing providing electrical isolation, ensuring the necessary creepage and clearance distances for high-voltage applications. The hermetically sealed construction protects the semiconductors from environmental influences, such as dust and humidity.

## P5000Z Tests for SSCB Application

To qualify as a robust and improved solution for SSCB application, the P5000Z had to go through various tests to meet both the reliability and performance requirements for a lifetime of 20 years. During normal operation, when the PPI remains in a continuous on-state, a major requirement is to have minimum possible on-state loss.

<figure><img src="image_6.png" /><figcaption>Fig.5: Output Characteristics at 125°C</figcaption></figure>

Because of double sided cooling and a significantly good Rth of 3 K/kW, along with highest permissible continuous Gate Voltage of 25 V, the on-state voltage will remain low generating low on-state losses.

Another major point of investigation was also to check the stability of the IGBT Gate Oxide, at voltages higher than rated, for a short period of time during the fault condition. A numerical model was developed from all the available historical data to calculate the failure rate when a higher gate voltage is applied in regular interval for a period of 200 ms and 1000 times in lifetime. The result of the model indicated that higher voltages up to 40 V for a short period of time, has minimal effect in the device failure rate and hence for short time pulse application can be used.
## SSCB Requirements: Breaking current and Short time withstand current

The concepts of breaking current and short-time withstand current are crucial aspects of solid-state DC circuit breakers in High-Voltage Direct Current (HVDC) system.

Breaking current, also known as interrupting current, refers to the maximum current that a solid-state DC circuit breaker can safely interrupt or break without causing damage to itself or the surrounding electrical system. In HVDC systems, the breaking current is a critical parameter, as it determines the breaker's ability to clear faults and protect the system from damage. The breaking current in solid-state DC circuit breakers for HVDC is typically in the range of tens of kiloamperes to hundreds of kiloamperes, depending on the specific application and system requirements.

Short-time withstand current, also known as withstand current, refers to the maximum current that a solid-state DC circuit breaker can withstand for a short period, typically in the range of milliseconds to seconds, without suffering damage or malfunction. This current is usually higher than the breaking current, as the breaker is designed to withstand the high currents that occur during fault conditions.

In HVDC systems, the short-time withstand current is critical, as it determines the breaker's ability to ride through faults and maintain system stability. The short-time withstand current is typically specified as a function of time, with the current decreasing as the time increases. For example, a solid-state DC circuit breaker might be able to withstand 50 kA for 10 milliseconds, 30 kA for 100 milliseconds, and 20 kA for 1 second.

### Breaking Current capability

For our work with P5000Z, the breaking current reached a maximum of 2.5 times the nominal current, which is 12.5 kA at 3200 Vdc. The main challenge is to turn off the device very slowly without exceeding the overvoltage limit. As proof of concept in the lab, the tested device was actively turned off with a high Gate resistor at 12.5 kA and a temperature of 70°C.

<figure><img src="image_7.png" /><figcaption>Fig.6: Turn off at 3200 Vdc and 12.5 kA</figcaption></figure>

Metal Oxide Varistors (MOVs) provide overvoltage protection in the application, reliably absorbing short-circuit energy. A demonstration of an MOV assembly with IGBT/Diode is presented later. This extends the Reverse Bias Safe Operating Area (RBSOA) to 2.5 times the nominal current, enabling thousands of safe breaking events with proper overvoltage protection using MOVs.

### Short-time withstand capability

Another significant challenge was evaluating device performance during short-time withstand current, which typically exceeds the breaking current. Fig.7 illustrates the switchgear fault current in a DC grid [8], where the fault current is too high to be interrupted in time and must be safely passed through the device until the mechanical switch opens successfully. Such events, limited to a maximum of 1000 occurrences in a lifetime, are governed by specific parameters as per IEC 62271-5, which dictate the waveform shape.

<figure><img src="image_8.png" /></figure>
<figure><img src="image_9.png" /><figcaption>Fig 7: (a) DC Grid Fault scenario (b) Typical Fault current waveform (IEC 62271-5)</figcaption></figure>

To select the right device, the parameters $I_{pd}$, $I_{kd}$ ($I_f$ in Fig.7) and $t_k$ are very relevant, where $I_{pd}$ refers to the peak value of the short circuit current, $I_{kd}$ refers to the short circuit DC current that the switchgear can carry in closed position during its rated duration and $t_k$ is the interval of time of the SC current. According to the IEC 62271-5 Standard, its preferred that $I_{pd}$ is 1.5 times $I_{kd}$ and $t_k$ is taken as maximum of 150 ms. Since the idea is to test how much the IGBT can withstand while turned on without going into desaturation, exploring the Forward Bias Safe Operating Area (FBSOA) as a function of conduction time is investigated.

<figure><img src="image_10.png" /><figcaption>Fig.8: Test Pulse</figcaption></figure>

To replicate the real pulse waveform shown in Fig. 7, a third-party institution was engaged to generate a test pulse similar to Fig. 8, capable of producing sufficient current to flow through the device. The test objective was to determine the maximum current tolerance before damage, varying the pulse width, with an initial temperature of 70°C. This temperature was chosen as it represents the standard operating condition, where the IGBT continuously conducts DC current. When the fault current flows through

the IGBT, the device temperature increases, causing a significant shift in the operating point on the output characteristics, as evident in the Vce curve, leading to desaturation.

<figure><img src="image_11.png" /><figcaption>Fig. 9: Tests with 150 ms</figcaption></figure>

The tests have been done with 150 ms, 100 ms and 75 ms and every time the current is increased till the device is damaged. The cause of damage is the temperature rise in the device due to the rectangular pulse current.

<figure><img src="image_12.png" /><figcaption>Fig. 10: Test with 100 ms</figcaption></figure>

<figure><img src="image_13.png" /><figcaption>Fig. 11: Test with 75 ms</figcaption></figure>
It is to be noted with a start temperature of 70°C, a single P5000Z PPI can take at least 20 kA DC current for a maximum period of 150 ms. From Fig. 12, at least an $I^2t$ value of 70 $kA^2s$ and an energy absorption in the zone of 20 kJ depending on the duration of conduction can also be observed. In the next section, thermal simulation is also done to find out the temperature rise profile which is the major cause of damage.

<figure><img src="image_14.png" /><figcaption>Fig. 12: Energy absorption and $I^2t$</figcaption></figure>

<figure><img src="image_15.png" /><figcaption>Fig. 13: Different currents at different pulses</figcaption></figure>

Further analysis of the test results also indicates that as high as 30 kA DC current can be driven through a single device if pulse duration is reduced to 75 ms, in other way round if the mechanical switch is fast enough to interrupt. If the DC current remains same but the conduction time varies there will be a linear rise of voltage till desaturation.

<figure><img src="image_16.png" /><figcaption>Fig. 14: Pulse width variation</figcaption></figure>

As conclusion from the test, it's safe to say that a single P5000 PPI is able to withstand a DC current between 20 to 30 kA for a maximum period of 150 ms and also giving the system, design flexibility in case higher current is desired with shorter pulse width. This significant current density is achieved due to the LTS technology, lack of bond wires unlike in Modules and major improvement of heat dissipation because of the press pack packaging.

## Diode D6001N Surge Current Capability

For a bidirectional approach, to counter DC fault currents from both sides, a diode in series is needed with the IGBT. The major requirement of the diode is low on-state voltage during continuous conduction and a high surge current capability during fault current.

<figure><img src="image_17.png" /><figcaption>Fig. 15: Diode Characteristics</figcaption></figure>

D6001N from Infineon is the optimal diode for this application since it has significantly low on-state voltage and has a high surge current capability of about 120 kA. However, D6001N being of different dimension, the proper integration with P5000Z in the same assembly
stack can be challenging but a compact and effective engineering solution is also provided in the last section of the paper. In the next section the test results are further analysed in the light of thermal simulation to get an idea about the temperature profile.

## Thermal performance analysis

Understanding heat propagation within the device during short-time withstand current flow is crucial for mitigating thermal issues. However, measuring temperature distribution in real-time is challenging, especially for short electrical pulses. Simulation-based approaches offer a viable solution. To address thermal management challenges, we employed Ansys FEM simulation to model the entire PPI.

<figure><img src="image_18.png" /><figcaption>Fig. 16: Extract of entire PPI, with each chip having same heat propagation</figcaption></figure>

A mesh analysis was performed to ensure accurate results. Our approach consisted of two stages.

First, we simulated the entire PPI module to understand thermal distribution patterns, assuming even pressure distribution, which is ensured in our PPI stacks (Fig.16). The results showed identical thermal distribution for each chip stack, allowing us to focus on simulating a single chip stack.

In the second stage, we simulated the individual chip stack using measured power losses, resulting in a maximum chip temperature of approximately 350°C, corresponding to the point of device failure.

<figure><img src="image_19.png" /><figcaption>Fig. 17: Heat Propagation at the individual chip stack at the end of a 75 ms pulse</figcaption></figure>

The simulation results were obtained for three different current profiles for the failed devices: 26 kA for 150 ms, 29 kA for 100 ms and 31 kA for 75 ms.

<figure><img src="image_20.png" /><figcaption>Fig. 18: Temperature and current profile with different pulse widths</figcaption></figure>

The superior performance of the PPI can be attributed to its robust mechanical design. Furthermore, the heat dissipation is not only on one side, but on both sides with a full-surface connection. In conventional IGBT modules, the individual chips are connected to each other by bond wires. These cannot withstand the extreme heat development due to very high electrical currents. The free-floating transition between Mo and Cu absorbs the mechanical stress caused by the different thermal expansion of the different materials and thus protects the Mo-Si-Mo connection. In contrast, conventional IGBT modules have all layers firmly connected, making them more susceptible to mechanical stress.

<figure><img src="image_21.png" /><figcaption>Fig. 19: PPI Chip Stack Setup</figcaption></figure>

In conclusion, our simulation-based study has demonstrated the effectiveness of the PPI in withstanding high electrical currents and the resulting thermal loads. The robust chip, efficient thermal heat dissipation and optimized design of
the PPI make it an attractive solution for use as a DC breaker.

## HCB with P5000Z (Concept Level)

It was also of significant interest to explore the application feasibility of the P5000Z for the Hybrid Circuit Breaker concept.

<figure><img src="image_22.png" /><figcaption>Fig.20: Output Characteristics at 25°C</figcaption></figure>

One major difference than the SSCB is that the IGBT will be idle at room temperature till the fault comes and has to conduct the fault current for about 2 ms, 500 times in lifetime and then turn off softly while the MOVs absorb the energy.

In general, the breaking current is significantly higher and can be about 5 times the nominal current. Since 2 ms is a very short duration, the voltage rise because of temperature will also be slow and the device can be pushed to drive higher currents. As the initial tests, the device was tested with a series of gradually increasing 2 ms half-sinusoidal pulse with different gate voltages to understand the desaturation behaviour. After the first tests (Fig.20), with 40 V gate for 2 ms, currents as high as 50 kA can be achieved, as a result of the press pack packaging. However, switching events need to be tested intensively, as the next steps, to meet the Hybrid Breaker application. From a system perspective, higher the breaking current smaller the current limiting inductor. Also like before, for bidirectional approach D6001N fits perfectly in series and due to low on-state voltage, reduces the arc voltage requirements. In the last section, an idea about a compact and low-inductance optimized mechanical stack assembly has been provided for both the concepts.

## Design concepts of the Stack Assemblies along with MOVs

The basic stack concept is a fundamental principle that underlies the design and construction of various power devices and systems. A stack, in essence, refers to an arrangement of components, including power devices, cooling systems, and insulation, designed to manage electrical power efficiently. The tower stack is a specific type of stack configuration, where components are arranged in a vertical tower-like structure. This design allows for efficient cooling, reduced inductance, and improved insulation, making it an ideal choice for high-power applications, such as DC circuit breakers. Cooling boxes, an essential component of the stack, are responsible for dissipating heat generated by power devices. Effective cooling is critical to prevent overheating, which can lead to device failure or reduced performance. Clamping, a technique used to press power devices to the cooling box, ensures good thermal contact and efficient heat transfer.

<table><caption>Fig. 21: Basic Concept of DC Breaker</caption><thead><tr><th rowspan="2">Basic Concepts</th><th>Rectifier Input</th><th>Antiserial IGBT</th></tr><tr><th>B2 MOV PPI<br>DC2</th><th>MOV FWD+PPI<br>DC</th></tr></thead><tbody><tr><td>No of semiconductors</td><td>4 Diodes + 1 PPI</td><td>2 Diodes + 2 PPI</td></tr><tr><td>Voltage drop</td><td>Low<br>2 Diodes + 1 IGBT</td><td>Very Low<br>1 Diode + 1 IGBT</td></tr></tbody></table>

Pressure distribution is a critical aspect of stack design, as it affects the performance and reliability of power devices. In the context of PPI, special requirements must be met to ensure uniform pressure distribution, which is essential for reliable operation. One of the significant challenges in PPI design is the problem of different diameters, which can be addressed by using specialized clamping systems or adaptors that accommodate varying diameters. Two basic concepts may be applied to meet different aspects connected to a DC-Breaker, as shown in Fig. 21. The Rectifier Input concept is the most economical concept, as it saves the costs for a second PPI making it effective for a design of solid-state switch.
<figure><img src="image_23.png" /><figcaption>Fig.22: Tower Stack with input rectifier</figcaption></figure>

In case of a hybrid circuit breaker the commutation during the fault current conduction phase from the mechanical switch to the PPI is critical and a low voltage drop, because of arc voltage requirements, is most favorable. The anti-serial configuration supports this requirement, as only 1 Diode and 1 PPI adds up to the total on state voltage drop.

<figure><img src="image_24.png" /><figcaption>Fig.23: Tower Stack with anti-serial configuration</figcaption></figure>

The general requirements for stack construction include low inductance, high reliability, and efficient cooling. Insulation is critical in stack design, as it prevents electrical faults and ensures safe operation.

<figure><img src="image_25.png" /><figcaption>Fig.24: Low inductive MOV-Integration</figcaption></figure>

Low inductance is essential to minimize dynamic voltage drops and electromagnetic interference. In case of a hybrid DC breaker a low inductance is mandatory for a fast commutation of the load current from the mechanical switch to the DC-breaker. Finally, the basic concept for Metal Oxide Varistor (MOV) integration (Fig.24) involves the use of MOVs as surge protection devices in power systems. The requirements for MOV integration include high reliability, low inductance, and sufficient cooling.

## Conclusion

In conclusion, this work successfully evaluated the high current handling requirements of SSCB and HCB applications through the design of an optimized and robust Infineon trench stop IGBT chip in a press-pack Module. The P5000Z PPI provides exceptional short-circuit withstand capability, withstanding 20-30 kA currents for up to 150 ms, and Thermal simulations revealed, a maximum device temperature of 350°C. Furthermore, a low-inductive, scalable, and bidirectional mechanical design was realized, integrating MOVs for both breaker concepts, thereby completing a chip-to-stack optimized design for DC Circuit Breakers with PPI.

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