# Investigations on the recovery of the electrical properties of Smart Cut™-transferred SiC thin film using SiC-on-Insulator structures

Guillaume Gelineau, Cédric Masante, Emmanuel Rolland, Sophie Barbet, Lucie Corbin, Anne-Marie Papon, Simon Caridroit, Mathieu Delcroix, Stéphanie Huet, Alexandre Moulin, et al.

► To cite this version:

Guillaume Gelineau, Cédric Masante, Emmanuel Rolland, Sophie Barbet, Lucie Corbin, et al. Investigations on the recovery of the electrical properties of Smart Cut™-transferred SiC thin film using SiC-on-Insulator structures. Materials Science Forum, 2024, 1124, pp.57-65. 10.4028/p-yDH8Qb.cea-04752744

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# Investigations on the recovery of the electrical properties of Smart Cut™-transferred SiC thin film using SiC-on-Insulator structures

Guillaume GELINEAU ¹,ᵃ*, Cédric MASANTE ¹, Emmanuel Rolland ¹, Sophie BARBET ¹, Lucie CORBIN ¹, Anne-Marie PAPON ¹, Simon CARIDROIT ¹, Mathieu DELCROIX ¹, Stéphanie HUET ¹, Alexandre MOULIN ¹, Vladimir PRUDKOVSKIY ¹, Nicolas TROUTOT ¹, Séverin ROUCHIER ²,ᵇ, Loïc TURCHETTI ², Karine MONY ³ and Julie WIDIEZ ¹,ᶜ

¹ Univ. Grenoble Alpes, CEA, Leti, F-38000 Grenoble, France

² SOITEC, Parc technologique des fontaines, 38190 BERNIN, France

³ Univ. Grenoble Alpes, CEA, IRIG, Pheliqs, F-38000 Grenoble, France

ᵃ guillaume.gelineau@cea.fr (corresponding author), ᵇ severin.rouchier@soitec.com,

ᶜ julie.widiez@cea.fr

**Keywords:** SiC-on-insulator, layer transfer, ion slicing, Smart Cut™, electrical properties

**Abstract.** SiC-on-Insulator (SiCOI) structures fabricated using the Smart Cut™ technique can be of great interest in order to probe the properties of a silicon carbide (SiC) transferred layer, by electrically insulating it from the receiver substrate. In this study, we report the fabrication of such a SiCOI structure using a SiC receiver, as well as its electrical and TEM characterization after high temperature annealing. We highlight a decrease of the transferred layer electrical resistivity with increasing annealing temperature, due to doping reactivation and electron mobility enhancement. After low temperature annealing (1200°C to 1400°C), deep acceptor levels, possibly located in a damaged region near the substrate's surface, might be responsible of a non negligible electrical compensation. Beyond 1400°C however, the transferred SiC crystal is healed and electron transport is only subjected to shallow nitrogen ionization.

## Introduction

In the recent years, an increasing number of publications are focusing on the fabrication and characterization of composite SiC substrates [1–11] (often realized using ion slicing technologies, or Smart Cut™ [12]). Hence, it becomes necessary to comprehend acutely the effects of such manufacturing processes on the material properties, such as the crystalline quality of the transferred layer or its electrical and optical properties. Doing so may not be trivial as the said layer is bonded on a receiver substrate, which can influence experimental results.

In this extent, SiC-on-Insulator (SiCOI) structures can be of great interest for probing the properties of the transferred layer alone, electrically insulated from the receiver substrate. These structures are made of an active thin monocrystalline SiC layer, which thickness is typically about 500 nm, transferred on the top of a receiver substrate, itself consisting of a bulk silicon or SiC handle substrate covered by a thick oxide layer [13]. Using such, it is possible to measure the electrical properties of the transferred layer, affected by the ion implantation step [14], before the recovery of the material in the finishing steps. One can then unveil the ongoing mechanisms of material recovery when considering the use of a composite SiC substrate, whether for power electronics, for micro-electro-mechanical systems or for photonics applications.

Previous studies on SiCOI structures were carried out at the end of the last century, aiming to understand both the blistering mechanisms of SiC [13, 15, 16] (in order to ensure the reliability of the manufacturing process) and the electrical properties of the transferred layer [17, 18]. However, the substrates were then realized using an oxidized silicon wafer as the handle substrate; obviously allowing costs reductions, but also limiting the substrate's admissible temperature below the melting
point of Si. Published results [17] showed that the 6H-SiC layer, transferred using high dose H⁺ ion implantation and direct bonding on an oxidized Si wafer, still contains – after a 3-hours 1300°C anneal: (i) pseudo-acceptor such as the Z₁/₂-center or the C-center at densities of about 5×10¹⁷ cm⁻³ and (ii) a hydrogen concentration comprised between 3×10¹⁹ cm⁻³ and 1×10¹⁹ cm⁻³. The same study proposes that the electrical conductivity of the transferred layer is governed by the ratio of defect density to the doping level of the material. Hence, further healing of said defects – with, for instance, higher temperature annealing – seems to be mandatory, especially when the initial doping level of the transferred SiC layer is low (< 10¹⁸ cm⁻³). Other studies [18] report the characterization of non-optimized lateral Schottky Barrier Diodes, fabricated on a 1300°C-annealed 6H-SiCOI substrate with a Si handle. The authors mention an important difference between the expected (simulated) characteristics and the experimental results – the latter showing high on-state resistances, high reverse current leakages and some early breakdowns. Although that the reasons of such performances are not specified in the paper, one can infer that an incomplete healing of the transferred 6H-SiC layer might be at stake. More recently, the study of conductively bonded monocrystalline SiC and polycrystalline SiC bilayer substrates could allow us to assess the recovery of the crystalline order and of the effective doping level of the transferred layer with the application of annealing processes of particularly high temperatures (up to 1900°C) [19]. X-Ray diffraction (XRD) showed that the crystal recovers its initial quality and is relaxed at 1300°C, with no further evolution beyond this temperature. However, the n-type dopants (initially present in the monocrystalline SiC wafer before transfer) were found, using Raman spectroscopy, to be deactivated with the hydrogen implantation (possibly due to a combination of crystalline disorder and of carrier trapping) and to reactivate at higher temperatures: between 1600°C and 1700°C. The architecture of the substrates this second study deals with could however not permit to carry out electrical measurements due to current leakage from the transferred layer to the highly conductive polycrystalline SiC receiver. For this reason, we chose here to use the SiCOI structure as a tool for characterizing the electrical properties of the transferred SiC layer.

Hence, we report the fabrication process of such a SiCOI structure, using a monocrystalline 4H-SiC wafer as the handle substrate. The choice of the latter minimizes the difference off the thermal dilatation coefficients of the transferred layer and the substrate, as compared to the use of a Si handle, as well as benefitting of a higher melting point. Doing so, higher annealing temperatures were accessible, allowing a more acute understanding of the effects of such manufacturing processes.

## Experimental section

**Substrate preparation.** The Smart Cut™ process was first described by M. Bruel *et al.* [12] as a promising solution to manufacture Silicon-on-Insulator (SOI) wafers with very thin silicon films – advantageous for low-power and low-voltage applications. The method allows one to transfer a thin layer from a donor material on top of a receiver handle substrate. We report here an alternative fabrication process, which differs from the historical SOI process by the nature of the receiver substrate. In our study, we replaced the Si handle substrate with a monocrystalline 4H-SiC wafer in order to benefit from its higher temperature resilience as well as from the reduction of thermal dilatation coefficients (TEC) difference between the receiver substrate and the transferred layer.

**SiCOI structures fabrication.** The detailed process we used to manufacture SiCOI substrates is described on Fig. 1. First, tetraethoxysilane (TEOS) layers were deposited on the donor (550 nm) and on the receiver (3500 nm) substrates (both consisting of 4×10¹⁸ cm⁻³ n-doped bulk 4H-SiC), before densification at 1100°C (1 hour) under a N₂ atmosphere. The donor wafer was then H⁺-implanted at room temperature at 160 keV with a dose of several 10¹⁶ H⁺.cm⁻² as previously reported in [13, 14]. The two substrates were hydrophilically bonded [20] under atmospheric pressure after cleaning and mechanical-chemical polishing (CMP). A subsequent thermal treatment was then performed to split the donor wafer at the maximum hydrogen concentration depth (i.e. around 700 nm). The SiCOI substrates were eventually obtained after (i) a 1200°C annealing step – necessary to obtain a sufficient bonding strength – and (ii) polishing. The thicknesses of the oxide and transferred SiC layers of the substrate used for further characterizations were of 3.25 µm and 525 nm, respectively, with standard deviations of 71.5 nm and 21.6 nm over the entire wafer surface (see Fig. 2).
<figure><img src="image_2.png" /><figcaption>Fig. 1: Detailed process flow of the SiCOI substrates.</figcaption></figure>

Subsequently to the process described above, five 2×3 cm² samples were cleaved from the wafer of Fig. 2. Four of these samples were capped with a polymer resin and annealed at 800°C in order to obtain an effective surface protection. One was then annealed at 1300°C, one at 1400°C, one at 1500°C and one at 1600°C, for 30 minutes each. The last sample was left untouched in order to characterize the initial state of the transferred layer. Higher annealing temperatures could not be studied due to the creeping of the oxide layer.

<figure><img src="image_3.png" /><figcaption>Fig. 2: Mappings of (a) oxide and (b) transferred SiC thicknesses (with spectroscopic ellipsometry, 21 measurement points). The average values and standard deviations of SiO₂ and SiC thicknesses are indicated below the figures.</figcaption></figure>
**Electrical characterizations.** The above-described samples were subjected to various electrical characterizations aiming to measure and evaluate the electrical properties of the transferred SiC layer with increasing annealing temperature. To do so, coplanar structures such as TLM bars and van der Pauw were electrically insulated from one another with dry etching of the transferred SiC layer with 1.5 µm-deep MESA trenches. Ohmic contacts were formed with an 80 nm-thick Ni layer annealed at 1000°C during 3 minutes prior to the deposition of 500 nm-thick Al pads.

**Hall Effect.** Hall Effect measurements were carried out at room temperature on 700 µm-wide van der Pauw structures. The measured Hall voltages were about 1 mV under a magnetic field of 0.33 T. We considered a Hall factor equal to 1 – close to the values previously measured by Rutsch *et al.* [21] under similar magnetic field. The thickness if the SiC layer was considered to be of 525 nm (Fig. 2), with a 12 % relative error. The I-V characteristics acquired on the 1200°C-annealed sample were not linear and were excluded from the overall analysis of the Hall Effect measurements.

**Transfer Line Method.** The Transfer Line Method (TLM) measurements were carried out at room temperature (RT), 80°C, 130°C and 200°C on a 200 µm-wide bar with 100, 300, 600 and 1000 µm-spaced pads. The resistance values used for the extraction of the resistivity of the transferred SiC layer were measured by evaluating the slopes of the I-V curves in the voltage range of +5 V to +10 V in order not to be influenced by any non-linearity in the low-voltage region due to, for instance, poor electrical contact quality (especially after lowest annealing temperatures). The thickness of the SiC layer used for the calculations was the same as for Hall Effect measurements. Assuming the electrical conduction mechanisms follow an ionization regime and considering the electron mobility measured with Hall Effect at room temperature, charge carrier ionization energies could be determined from the Arrhenius plot of the resistivity of the SiC layer (log scale) versus the reciprocal temperature. We could thus estimate the trap energies levels using Fermi-Dirac statistics equations [22].

## Results and discussion

**Electrical characterizations.** The results of the Hall Effect are given on the Fig. 3 for both the carrier concentration, the electron mobility and the resistivity. The figure shows the evolution of these parameters as a function of the anneal temperature (between 1300°C and 1600°C), compared to the values obtained on a bulk 4H-SiC substrate before layer transfer (dashed lines). One can note an important drop of the resistivity of the transferred SiC layer with increasing annealing temperature, due to the increase of both the effective doping level and the electron mobility. Indeed, after a 1300°C anneal, we find that the transferred SiC layer is highly resistive (1.6×10⁵ mΩ.cm), although that the initial bulk SiC crystal had a resistivity of 20 mΩ.cm. This can be attributed to: (i) a deactivation of

<figure><img src="image_4.png" /><figcaption>Fig. 3: Hall measurements of (a) doping level, (b) electron mobility and (c) resistivity of the transferred SiC layer as a function of annealing temperature (measured at RT).</figcaption></figure>
the nitrogen dopants (already present in the material before layer transfer) and (ii) a drop of the electron mobility – both caused by the partial amorphization of the SiC crystal under H⁺ ion irradiation [23–25]. Such disorder, previously studied in the case of conductively bonded SiC substrates in ref [19], can indeed be responsible of both displacing the N atoms out of their active site (substitutional of C [26]) and creating traps that limit the free mean path of the electrons [14, 17]. With higher annealing temperature, the carrier concentration increases and nearly equals that of the initial bulk SiC after 1600°C. The same observation can be made for the electron mobility, which nears that of the bulk SiC with less than 2 % error after the 1600°C annealing.

Subsequently, TLM measurements allowed us to estimate the electrical resistivity of the transferred SiC layer as a function of the measurement temperature for all the considered samples (anneal temperature ranging from 1200°C to 1600°C). The Fig. 4a summarizes these results and compares them to those obtained from Hall Effect measurements. We confirm the tendency reported in the last paragraph (important decrease of the transferred SiC electrical resistivity with higher annealing temperatures), although that a certain discrepancy with Hall Effect results is to be noticed for the sample annealed at 1300°C. For every characterized sample, the electrical conductivity is decreasing with increasing measurement temperature. Based on this observation, we can conclude that the electron transport in the transferred SiC layer is likely driven by ionization phenomena rather than by scattering interactions (at least, in this given range of temperature). Moreover, one can notice that the electrical resistivity becomes less dependent to the measurement temperature with increasing annealing temperature, meaning that the ionization phenomena are becoming less important after higher annealing temperatures. Assuming constant electron mobility values (extracted from Hall Effect measurements), we could calculate the ionization energies of charge carriers using Fermi-Dirac statistics equations (see Fig. 4b). After 1200°C and 1300°C anneal, the ionization regime is likely driven by untrapping of electron from deep level centers 0.45 eV and 0.13 eV (± 10 %) below the conduction band, respectively – energies close to that of $EH_4/EH_5$ and $EH_1/Z_{1/2}$ centers [14, 17, 27]. At temperature over 1400°C, the ionization energies of charge carriers range from 0.05 to 0.02 eV. Because of the proximity of these energy values to that of nitrogen ionization in 4H-SiC [26, 28–31], we can assume that electron transport mechanisms in this second regime are likely due to shallow dopant ionization.

<figure><img src="image_5.png" /><figcaption>Fig. 4: (a) Electrical resistivity of the transferred SiC layer inferred from TLM measurements as a function of the measurement temperature and for samples annealed between 1200°C and 1600°C (Hall results are displayed with yellow crosses for comparison). (b) Activation energies (calculated from Arrhenius plots of TLM resistivity) as a function of annealing temperature.</figcaption></figure>
**Transmission Electron Microscopy.** To investigate the damage caused to the SiC crystal by ion implantation and its recovery, we carried out high-resolution transmission electron microscopy (TEM) observations and compared the crystalline quality near the surface of the substrate after annealing at 1200°C and 1600°C. These observations are shown on Fig. 5. For both samples, a low-magnification image shows the SiCOI stack. Higher magnification snapshots show the crystalline structure near the top surface of both samples. The red inset of Fig. 5a allows one to observe three particular features on the 1200°C-annealed sample: (i) crystalline c-planes of 4H-SiC are well visible on the uppermost dozens of nanometers below the surface of the substrate, indicating a good crystalline quality in this region. However, (ii) a 20 nm–thick brighter layer can clearly be seen under the sample surface (see red inset of Fig. 5a) and (iii) one can assess the presence of a 7 nm–thick layer of deteriorated crystalline quality buried approximatively 20 nm below the surface. The former is highlighted with the yellow dashed lines and arrows in the yellow inset of Fig. 5a. Nevertheless, after the 1600°C anneal, no particular contrast nor irregular crystalline feature in the near surface of the SiC layer was observed (green inset of Fig. 5b). We do not believe that the deteriorated layer of the 1200°C-annealed sample can be attributed to the CMP process done after the splitting of the donor wafer, as these observations do not resemble those reported in previous investigations of CMP-induced subsurface damage [32–34]. On the other hand, it can be assumed that this CMP process eliminated a portion of the implantation-damaged layer on the uppermost part of the transferred film. Hence, the removal of more SiC material during this step could allow to get rid of the defectuous layer, potentially allowing to eliminate the electrically active defects highlighted with TLM I-V measurements.

<figure><img src="image_6.png" /><figcaption>Fig. 5: TEM imagery of SiCOI structure after (a) 1200°C anneal and (b) 1600°C anneal. Magnifications on sub-surface region are shown in both case; the damaged layer of sample annealed at 1200°C is highlighted with yellow arrows. The black stains visible on the high-magnification snapshot of the (b) inset are likely due to unintentional carbon contamination deposited during the observations.</figcaption></figure>

The brighter-contrast region on the red inset of Fig. 5a is representative of a lighter region below the surface of the substrate, possibly correlated with in-plane residual tensile strain in the transferred SiC layer [19]. The SIMS hydrogen profile acquired after annealing at 1200°C (in red on Fig. 6) does not evidence any residual hydrogen pocket near the surface of the substrate (such as reporter after 900°C anneal in [17]), but a slightly decreasing concentration of about $1×10^{19}$ to $4×10^{18}$ at.cm$^{-3}$
(consistent with the previous measurement from E. Hugonnard-Bruyère *et al*. in the case of a 6H-SiCOI on silicon substrates annealed at 1300°C [17]). Together with the damaged layer (yellow inset of Fig. 5a), this can explain the strong ionization regime of charge carriers that was highlighted after the 1200°C anneal. Indeed, several published studies show that interstitial hydrogen can be associated with an acceptor level [32, 33] and that its implantation in SiC is responsible of the creation of deep acceptor levels such as $EH_4/EH_5$ or $Z_{1/2}$ [17, 35–37]. The fact that no such contrast nor damaged layer can be seen after the 1600°C treatment (Fig. 5b), as well as the absence of hydrogen – under the SIMS detection limit, see Fig. 5 –, testifies of the good recovery of the transferred SiC layer. This is consistent with the electrical results (Hall and TLM) and previously reported Raman spectroscopy and XRD analysis [19], showing that the pristine crystalline order was recovered after 1300°C to 1400°C, with no evolution beyond this point.

<figure><img src="image_7.png" /><figcaption>Fig. 6: SIMS hydrogen profiles in the SiC transferred layer after annealing at 1200°C (red) and 1600°C (blue).</figcaption></figure>

## Summary

In this study, SiC-on-Insulator (SiCOI) structures were used as a tool for analyzing the recovery of Smart Cut™-transferred n-doped 4H-SiC thin film with various electrical measurements and transmission electron microscopy. Thanks to the use of a SiC receiver, we could access particularly high annealing temperatures that could not be studied in previous studies [17, 18]. Hall Effect and TLM measurements could allow us to highlight a strong effect of the Smart Cut™ process over the electrical properties of the transferred SiC layer before the application of any thermal annealing step. An important drop of the effective doping level and of the electron mobility was assessed after 1200°C anneal, as well as the presence of deep level acceptors traps (likely $EH_4/EH_5$ and $EH_1/Z_{1/2}$). TEM observations permitted to correlate these findings with the presence of a damaged layer below the surface of the sample as well as to explain the recovery of the electrical properties with higher annealing temperatures. An annealing step of 1600°C hence seems to be mandatory in order to access a sufficient recovery of the transferred SiC material. Since the epitaxy deposition of the active drift layer – mandatory for the fabrication of power devices – is realized in the same range of temperature, one can then wonder if the crystalline recovery of the transferred SiC layer can be carried out during this step. Future studies will seek to shed light upon that point.
## Acknowledgments

This project has received funding from the Key Digital Technologies (KDT) under Grant Agreement No 101007237. The KDT receives support from the European Union's Horizon 2020 research and innovation programme and Germany, France, Italy, Sweden, Austria, Czech Republic, Spain. Part of this work, carried out on the Platform for Nanocharacterization (PFNC), was supported by the "Recherche Technologique de Base" program of the French National Research Agency (ANR).

## References

[1] S. Rouchier et al., Materials Science Forum, 1062 (2021) 131-135.

[2] K. Imakoa et al., UN patent 9 761 749 B2 (2017).

[3] A. Yi et al., Optical Materials, 107 (2020) 109990.

[4] F. Mu and T. Suga, presented at ICEP 2019, Japan (2019) 198-199.

[5] F. Mu et al., Journal of Solid State Science and Technology, 5(9) (2016) 451-456.

[6] W. Zhang et al., Micromachines, 12(12) (2021) 1575.

[7] W. Schwarzenbach et al., presented at ICSCRM 2022, Davos, Switzerland (2022).

[8] E. Cela et al., Defect and Diffusion Forum, 425 (2023) 57-61.

[9] B. Kallinger et al., Solid State Phenomena, 342 (2023) 91-98.

[10] D. Zhu et al., physica status solidi (a), 220(3) (2023) 2370005.

[11] H. Ou et al., Materials, 16(3) (2023) 1014.

[12] M. Bruel et al., in 1995 IEEE International SOI Conference Proceedings (1995) 178-179.

[13] L. Di Cioccio et al., Materials Science and Engineering: B, 46(1) (1997) 349-356.

[14] X. Zhang et al., Nuc. Inst. Methods Phys. Res. B, 436 (2018) 107-111.

[15] Y. Le Tiec, Ph.D. thesis, Science et Génie des Matériaux, INP Grenoble & CEA-Leti (1998).

[16] L. Di Cioccio et al., Compound Semiconductor Heterostructures by Smart Cut™: SiC On Insulator, QUASIC™ Substrates, InP and GaAs Heterostructures on Silicon, in: M. Alexe and U. Gösele (Eds.), Wafer Bonding: Applications and Technology, Springer, Berlin, 2004, pp. 263-314.

[17] E. Hugonnard-Bruyère et al., Materials Sciences and Engineering: B, 61-62 (1999) 382-388.

[18] F. Letertre et al., Materials Sciences Forum, 433-436 (2003) 813-818.

[19] G. Gelineau et al., Materials Science Forum, 1089 (2023) 71-79.

[20] C. Ventosa et al., Journal of Applied Physics, 104(12) (2008) 123524.

[21] G. Rutsch et al., Journal of Applied Physics, 84(4) (1998) 2062-2064.

[22] A. AlQurashi and C. R. Selvakumar, Superlattice Microstructures, 118 (2018) 308-318.

[23] F. Schmid et al., Phys. rev. B, 74 (2006) 245212.

[24] B. S. Li et al., Nuc. Inst. Methods Phys. Res. B, 316(239) (2013) 244.

[25] N. Daghbouj et al., Acta Materialia, 188 (2020) 609-622.

[26] Kimoto, T. and Cooper, J.A., Fundamentals of Silicon Carbide Technology: Growth Characterization Devices and Applications, John Wiley & Sons, 2014.

[27] X. Zhou et al., Mat. Sci. Forum, 963 (2019) 516-5159.

[28] M. A. Capano et al., J. Appl. Phys., 87(12) (2000) 8773.

[29] J. Pernot, Journal of Applied Physics, 90 (2001) 1869-1878.

[30] W. Götz et al., Journal of Applied Physics, 73(7) (1993) 3332-3338.

[31] G. Pensl and W. J. Choyke, Physica B: Condensed Matter, 185(1) (1993) 264-283.

[32] H. Li et al., Front. Phys., 9 (2022) 820637.

[33] H. Sako et al., Journal of Applied Physics, 119(13) (2016) 135702.

[34] W. Geng et al., J. Semicond., 43(10) (2022) 102801.

[35] F. Gendron et al., Appl. Phys. Lett., 67(9) (1995) 1253-1255.

[36] W. J. Choyke, H. Matsunami, and G. Pensl, Silicon Carbide: Recent Major Advances, Springer-Verlag, vol. 1. Berlin, Germany: Heidelberg GmbH, 2004.

[37] M. E. Bathen et al., Journal of Applied Physics, 127 (2020) 085701.
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