# Development of ScAlN/GaN High Electron Mobility Transistor on silicon substrate for RF applications

Seif El Whibi, Nagesh Bhat, Yassine Fouzi, N. Defrance, Zahia Bougrioua, Jean-Claude de Jaeger, Florian Bartoli, Maxime Hugues, Yvon Cordier, Marie Lesecq

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Seif El Whibi, Nagesh Bhat, Yassine Fouzi, N. Defrance, Zahia Bougrioua, et al.. Development of ScAlN/GaN High Electron Mobility Transistor on silicon substrate for RF applications. Wocsdice Exmatec 2025, Jun 2025, Cadiz, Spain. hal-05467212

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# Development of ScAlN/GaN High Electron Mobility Transistor on silicon substrate for RF applications

Seif El Whibi<fnref n="1" />, Nagesh Bhat<fnref n="1" />, Yassine Fouzi<fnref n="1" />, Nicolas Defrance<fnref n="1" />, Zahia Bougrioua<fnref n="1" />, Jean-Claude De Jaeger<fnref n="1" />, Florian Bartoli<fnref n="2" />, Maxime Hugues<fnref n="2" />, Yvon Cordier<fnref n="2" />, Marie Lesecq<fnref n="1" />

seif.el-whibi@iemn.fr

## Abstract

In this work, a 7 nm ScAlN barrier GaN High Electron Mobility Transistor (HEMT) structure is grown on silicon (111) substrate by ammonia-source molecular beam epitaxy (NH₃-MBE). On 75 nm T-shaped gate transistor, a saturated current density of 1.35 A/mm at a gate bias of 0V and a transconductance peak higher to 280 mS/mm are reached. Transition frequencies fT/fmax of 82 / 112 GHz are reported. At VDS = 8 V, continuous-wave (CW) output power density of 1 W/mm is achieved at 10 GHz with 16 % associated Power-Added Efficiency (PAE) and a linear power gain of 10 dB. These preliminary results demonstrate the potential of ScAlN/GaN-based HEMTs on low-cost silicon substrates.

## Introduction

AlGaN, AlN or InAlN have been widely investigated as barrier materials in GaN-based high electron mobility transistors [1-2-3]. However, the use of rather low aluminum content in AlGaN to avoid large lattice mismatch stress results in limited two-dimensional electron gas (2DEG) density around ~1x10¹³ cm⁻<fnref n="2" />. AlN barrier permits to achieve higher 2DEG density up to ~4x10¹³ cm⁻<fnref n="2" />. However, the bandgap of AlN (Eg=6.1 eV) and its very large lattice mismatch of 2% with GaN make the fabrication of transistors more difficult. The ternary InAlN can be grown lattice-matched with GaN which enables a strong decrease of the stress but its growth remains complex due to phase separation and compositional fluctuations.

In such a context, the ternary compound ScₓAl₁₋ₓN becomes a promising way for GaN devices [4]. It offers a bandgap ranging from 6.1 eV to 3.9 eV for scandium contents (x) ranging between 0 and 0.5, while higher spontaneous polarization theoretically enables 2DEG density up to ~5x10¹³ cm⁻<fnref n="2" /> in lattice matched ScAlN/GaN system. To our knowledge, all the reported RF and power performances of ScAlN based HEMTs are obtained on SiC substrate (table1).

<table><caption>Table 1: Reported performances of ScAlN/GaN HEMTs</caption><thead><tr><th>Ref</th><th>L<sub>G</sub> (nm)</th><th>I<sub>D</sub> at 0V (A/mm)</th><th>R<sub>ON</sub> (Ω.mm)</th><th>f<sub>T</sub> (GHz)</th><th>f<sub>max</sub> (GHz)</th><th>R<sub>C</sub> (Ω.mm)</th></tr></thead><tbody><tr><td>[5]</td><td>80</td><td>2</td><td></td><td>50</td><td>140</td><td>0.1</td></tr><tr><td>[6]</td><td>120</td><td>2.2</td><td>1.1</td><td>72</td><td>102</td><td>&lt; 0.1</td></tr><tr><td>[7]</td><td>150</td><td>1.7</td><td>2.9</td><td>52</td><td>-</td><td>0.9</td></tr><tr><td>[8]</td><td>90</td><td>2.1</td><td>0.59</td><td>92.4</td><td>134.3</td><td>0.31</td></tr></tbody></table>

Even though SiC is a very good choice for high performance at high frequencies, Si substrate offers interesting perspectives since it remains the first choice for commercial devices due to its mature, low-cost, and large wafer-scale manufacturing ecosystem. The fabrication of ScAlN/GaN HEMTs on Si substrate is reported in this paper and the first demonstration of RF and power performance will be discussed.

## Material growth and device technology

### Material growth

From a 3-inch AlN-on-Si (111) template, a stack of AlGaN and AlN layers is first grown to compensate lattice and thermoelastic mismatches and then to reduce residual strain in the buffer [9]. The highly resistive 1.33 µm thick GaN buffer is grown at about 800°C [10]. A 7 nm ScAlN barrier is grown at 670°C with a Sc molar fraction of 15% [11]. A thin 1.6 nm AlN exclusion layer is introduced between the ScAlN and GaN epilayers to limit intermixing and alloy scattering. Finally, a 2 nm GaN cap layer is grown in order to protect ScAlN from oxidation during device processing. Fig 1a. shows a sketch of the whole heterostructure.

<figure><img src="image_3.png" /><figcaption>Figure 1: NH₃-MBE grown ScAlN/GaN structure, Schematic of ScAlN/GaN HEMT highlighting the epilayers and transistor contacts (a). SEM micrograph of HEMT. T-Gate profile of a 75 nm gate (inset) (b).</figcaption></figure>

### Device technology

The process starts with the deposition of ohmic contacts metallization Ti/Al/Ni/Au (12/200/40/100 nm) by e-beam evaporation after in-situ-Argon (Ar) ion beam etching (IBE) to set the metallic sequential closer to the 2D channel. This is followed by rapid thermal annealing (RTA) at 850 °C for 30 s under nitrogen atmosphere. Then, devices are isolated by N+ ion multiple implantations. T-gates are fabricated through triple-layer resist electron-beam lithography, followed by Ni/Au (40/300 nm) metal deposition and lift-off. The Schottky contacts were annealed at 400°C for 20 minutes to enhance reliability and robustness. Then, Si₃N₄ passivation is performed by

<footnote n="1">¹Univ. Lille, CNRS, Centrale Lille, Univ. Polytechnique Hauts-de-France, UMR 8520 - IEMN-Institut d'Electronique de Microélectronique et de Nanotechnologie, F-59000, Lille, France</footnote>

<footnote n="2">²University Côte d'Azur, CNRS, CRHEA, rue B. Gregory, 06560 Valbonne, France</footnote>
Plasma Enhanced Chemical Vapor Deposition (PECVD) at 340 °C. Finally, a Ti/Au stack is deposited by evaporation to access transistor contacts. In this paper, device under test (DUT) (fig. 1b) features a two-finger configuration with a gate length L<sub>G</sub> = 75 nm, a gate width W = 2 x 25 µm and source-to-drain spacing L<sub>SD</sub> = 1.5 µm.

Measurements and results

DC Characteristics

Fig. 2a shows the output I<sub>DS</sub>(V<sub>DS</sub>) characteristics obtained on the DUT. From these measurements, a maximum DC current density I<sub>DS Max</sub> of 1.35 A.mm<sup>-1</sup> is reached at V<sub>GS</sub> = 0 V, associated with an ON-resistance of 2.05 Ω.mm. As shown in Fig. 2b, for V<sub>GS</sub> ranging from -6 V to 1 V, an extrinsic transconductance g<sub>m,ext</sub> peak of 280 mS.mm<sup>-1</sup> is obtained at V<sub>GS</sub> = -3.5 V and V<sub>DS</sub> = 4 V.

<figure><img src="image_4.png" /><figcaption>**Figure 2:** DC measurements of a 2X25X0.075 µm transistor (a) I-V drain current characteristics at V<sub>GS</sub>=1V to -8V and transconductance for varying gate voltage (b).</figcaption></figure>

RF Characteristics

The scattering S<sub>ij</sub> parameters are measured using a Vector
Network Analyzer (VNA). The current gain modulus
(|H21|) and Mason's unilateral gain (U) are extracted
from S-parameters versus frequency measurement. The
current gain transition frequency (f<sub>T</sub>) and the maximum
oscillation frequency (f<sub>Max</sub>) are directly extracted from the
first order linear frequency regression (- 20 dB/decade)
plots of |H21| and U respectively. These figures of merit
are depicted in Fig. 3a for a biasing corresponding to the
extrinsic transconductance peak. An intrinsic current gain
cut-off frequency f<sub>f</sub> of 82 GHz associated with a maximum
oscillation frequency f<sub>Max</sub> of 112 GHz are achieved.

<figure><img src="image_5.png" /><figcaption>**Figure 3:** Small signal RF gain performance at V<sub>D</sub>=6V (a), output power, power gain and power added efficiency versus absorbed power at 10 GHz for a 2 x 25 x 0.075 µm<sup>2</sup> ScAlN/GaN HEMT on silicon substrate (b).</figcaption></figure>

Microwave power measurements

Large-signal microwave power measurement was
performed at 10 GHz (fig.3b). It is based on an active load
pull setup under continuous wave CW conditions with a
Nonlinear Vector Network Analyzer (NVNA) working up to
50 GHz. At V<sub>DS</sub> = 8 V and I<sub>DS</sub> =500 mA.mm<sup>-1</sup> corresponding
to class A operation, the device exhibits an output power
density (P<sub>out</sub>) of 1 W.mm<sup>-1</sup> associated with a maximum

power-added efficiency (PAE) of 16 % and a linear gain of
10 dB.

Conclusion

ScAlN/GaN HEMTs were grown by NH₃-MBE on silicon
substrate and transistors were fabricated and
characterized. The devices delivered high DC
performance, with a drain current density of ~1.35 A/mm
and a transconductance of ~284 mS/mm. A 75 nm gate
device exhibited a cut-off frequency (f<sub>T</sub>) of 82 GHz and a
maximum oscillation frequency (f<sub>MAX</sub>) of 112 GHz. First
microwave power measurement at 10 GHz for ScAlN/GaN
HEMTs on Si (111) substrate is reported in this study. An
output power density of 1 W/mm is obtained associated
with a PAE of 16 % and a power gain in linear regime of 10
dB indicating the potential of ScAlN HEMTs for high-
performance RF applications on low-cost silicon
substrates.

Acknowledgments

The authors would like to thank the support of the French “Agence Nationale for the research” (ANR), through the ‘Investissements d’Avenir’ program GaNeX (ANR-11-LABX-0014), the project TWINS (ANR-23-CE51-0011) as well as the RENATECH and RFnet networks. This work was also supported in part by the European Project GaN4AP (Gallium Nitride for Advanced Power Applications). The project has received funding from the Electronic Component Systems for European Leadership Joint Undertaking (ECSEL JU), under grant agreement No.101007310. This Joint Undertaking receives support from the European Union’s Horizon 2020 research and innovation program, and Italy, Germany, France, Poland, Czech Republic, Netherlands.

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