# Online current limiting-based control to improve fault ride-through capability of grid-feeding inverters

Fayçal Benyamina, Abdeldjabar Benrabah, Farid Khoucha, Muhammad Fahad Zia, Yahia Achour, Mohamed Benbouzid

## ► To cite this version:

Fayçal Benyamina, Abdeldjabar Benrabah, Farid Khoucha, Muhammad Fahad Zia, Yahia Achour, et al.: Online current limiting-based control to improve fault ride-through capability of grid-feeding inverters. Electric Power Systems Research, 2021, 201, pp.107524. 10.1016/j.epsr.2021.107524. hal-05336250

HAL Id: hal-05336250

https://hal.univ-brest.fr/hal-05336250v1

Submitted on 29 Oct 2025

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# Online Current Limiting-based Control to Improve Fault Ride-Through Capability of Grid-Feeding Inverters

Fayçal Benyamina<sup>a,b</sup>, Abdeldjabar Benrabah<sup>a</sup>, Farid Khoucha<sup>a,b</sup>, Muhammad Fahad Zia<sup>c</sup>, Yahia Achour<sup>a</sup>, Mohamed Benbouzid<sup>b,d,*</sup>

## Abstract

Grid-feeding inverters require much better operation monitoring and improved performance for their safe and efficient integration into the power system. Specifically, these inverters must participate in grid stability enhancement under faulty conditions and without any disconnection. In this regard, a fault ride-through capability is proposed for an inductive filtered grid-feeding inverter, which is controlled in both positive and negative sequences to ensure dual current control. Grid voltage dips are tackled by injecting a reactive power according to grid codes requirements. Enhanced active power control is introduced by suppressing oscillations, which are twice the grid-frequency. In order to avoid the inverter and semi-conductor components tripping under grid faults, a new current limiting strategy is proposed. It is based on real-time active power reduction using a closed-loop current magnitude controller. The effectiveness and flexibility of the proposed control strategy are verified by numerical simulations in both balanced and unbalanced grid fault cases.

**Keywords:** Grid-feeding inverter, low voltage ride-through, grid codes, current limiter.

## 1. Introduction

Nowadays, electric power generation is mainly based on fossil fuels that are clearly affecting global climate due to greenhouse gas emissions [1, 2]. Therefore, research and industry developments on renewable and green energy sources are carried out by researchers, industrialists, and governments to provide clean and reliable energy supply to ever increasing energy demand. The trend towards the use of renewable energy as distributed energy resources (DERs) has made a significant contribution towards improving energy efficiency [3, 4].

DERs are exploited in two ways: standalone and grid-connected modes. In a standalone mode, the renewable generator feeds local loads while working in maximum power point tracking (MPPT) together with energy storage elements for mitigating their intermittent output. In grid-connected mode, the maximum available power will be injected into the grid [5, 6]. Nevertheless, these renewable generators will have a significant impact on the main grid with their increase integration in terms of instability, reliability, power quality, etc. Therefore, grid operators (GOs) are carrying out extensive research on developing rules and grid codes (GCs). These rules impose that renewable generators should comply with in order to ensure safe and seamless transfer of electric power to the main grid [7, 8, 9].

DERs are required to ensure the same performance as traditional energy supply systems, improved stability in terms of

voltage and frequency, noise rejection, enhanced power quality, reliability and grid safety [10, 11]. The already developed GCs highlight some recommendations to be implemented and they are regulation and stability of voltage and frequency, voltage ride through (VRT) including low voltage ride-through (LVRT), zero voltage ride-through (ZVRT), and high voltage ride-through (HVRT), power quality standards at the point of common coupling (PCC), active power control for frequency stability support, and injection of reactive power for the voltage stability support as depicted in Figure 1 [12, 13].

Voltage dip is a common grid fault that can be categorized into two types, balanced and unbalanced due to connection or disconnection of high power loads. This problem has been widely studied in literature under the name of LVRT [14, 15, 16]. LVRT is necessary to interface the DERs with the grid in order to stay connected in case of voltage dips and subsequently avoid grid problems like voltage flickers, power outages and system instability [17, 18].

Voltage dip, either balanced or unbalanced, increases the current injected into the grid to provide desired active and reactive powers, which can damage the converter due this overcurrent phenomenon. In addition, unbalanced voltage dips induce active and reactive power oscillations at twice the grid-frequency which will propagate to the DC-link and may even result in reducing the lifetime of the capacitors or damaging them due to over-voltage [4, 19]. To overcome this problem, various control strategies have been proposed in the literature to ensure power injection with improved oscillations under unbalanced voltage dips, such as average active and reactive power

<footnote><sup>a</sup>Ecole Militaire Polytechnique, UER ELT, 16111 Algiers, Algeria</footnote>

<footnote><sup>b</sup>University of Brest, UMR CNRS 6026 IRDL, 29238 Brest, France</footnote>

<footnote><sup>c</sup>Department of Electrical Engineering, National University of Computer and Emerging Sciences, 54000 Lahore, Pakistan</footnote>

<footnote><sup>d</sup>Shanghai Maritime University, Shanghai, China</footnote>

<footnote>*Corresponding author</footnote>

<footnote>Email address: Mohamed.Benbouzid@univ-brest.fr (Mohamed Benbouzid)</footnote>
<figure><img src="image_2.png" /><figcaption>Figure 1: Reactive current injection to support/ limit the voltage during low voltage ride-through/ high voltage ride-through.</figcaption></figure>

controller (AARC), balanced positive sequence controller (BP SC), positive and negative sequence controller (PNSC) and flexible positive and negative sequence controller (FPNSC) [14, 20].

Full LVRT control must ensure dynamic grid voltage enhancement under faulty conditions, which may lead to inverter tripping due to over-current [13, 21, 22]. To address this issue, peak current limiter is added after current references calculation. Various methods have been proposed in literature for four/ three wires three-phases grid-connected inverter [23, 24, 25]. Usually, inverter current should never exceeds the threshold limit set at the inverter design [26, 27].

In [14], authors proposed an LVRT strategy for LCL filtered grid connected photovoltaic inverter enabling current limitation under faulty conditions. The same system was studied in [13] but with three-level voltage source inverter VSI. Previous researches presented a non-MPPT control during the fault and defined a new nominal power to limit the current. The major disadvantage of this method is the injected active power loss during the fault, while the current is limited at the nominal value instead of the threshold value. In [23], fault strategy management was proposed for four/ three-wire inverter-based islanded microgrids. However, it focused on using hybrid reference frame for inverter control which is complex to be implemented especially with the defined current limiting factor based-on root mean square (RMS) calculation. The similar approach is used in [24] for grid-connected microgrids, but it is not suitable due to the switching between synchronous and natural reference frame and the unavoidable delay caused by RMS current calculation. To deal with this issue, a current magnitude predictor is adopted in [27] to calculate the current peak in order to limit the current in grid forming/feeding inverter. This technique uses two successive sequence separations in its proposed current limiter, which is very complex to implement in practice. Moreover, the limited current references do not address GC requirements and the suppressing of active power oscillations.

According to the aforementioned limitations, this paper proposes an online current limiter, which ensures a full LVRT of a

<figure><img src="image_3.png" /><figcaption>Figure 2: Three phase distributed grid-feeding system.</figcaption></figure>

grid-connected inverter. The major contributions of this paper are:

* An LVRT strategy based on GC requirements to support symmetrical and asymmetrical voltage dips.

* Current references generation method to suppress active power oscillations.

* A novel current limiter proposal based on an online active power decreases using a current magnitude regulator for three-wire three-phase inverter.

* A dual current controller to achieve current regulation under generic grid situations.

The remaining paper is organized as follows: Section 2 describes the system under study with the modeling in the synchronous reference frame (SYRF). In section 3, control structure, mainly the LVRT strategy, is presented. The proposed current limiter and its comparison with previous proposals are discussed in section 4. Section 5 discusses the simulation results of the proposed strategy under different faulty grid situations. Finally, section 6 concludes the paper.

## 2. System Description

The system under study is composed of a DC type energy source to act as renewable energy source. The used converter is a three-wire two-level VSI. The system is connected to the grid at the PCC on the AC side of the VSI through an output inductive filter. The studied system is depicted in Figure 2 while its parameters are listed in Table 1.

<table><caption>Table 1: System Parameters.</caption><thead><tr><td>Parameters</td><td>Symbol</td><td>Value</td></tr></thead><tbody><tr><td>Nominal power</td><td>P<sub>nom</sub></td><td>5 kW</td></tr><tr><td>DC link</td><td>V<sub>dc</sub></td><td>700 V</td></tr><tr><td>Grid voltage</td><td>V<sub>g</sub><sup>rms</sup></td><td>380 V</td></tr><tr><td>Grid frequency</td><td>f<sub>g</sub></td><td>50 Hz</td></tr><tr><td>Switching frequency</td><td>f<sub>sw</sub></td><td>10 kHz</td></tr><tr><td>Filter resistance</td><td>R</td><td>0.3 Ω</td></tr><tr><td>Filter inductance</td><td>L</td><td>11 mH</td></tr><tr><td>Sampling time</td><td>T<sub>s</sub></td><td>0.05 ms</td></tr></tbody></table>
The relationships between voltages and currents are obtained from Kirchoffs laws:

$$ egin{cases} L \frac{di_d}{dt} = v_{i_d} - v_a - R i_d \\ L \frac{di_b}{dt} = v_{i_b} - v_b - R i_b \\ L \frac{di_c}{dt} = v_{i_c} - v_c - R i_c \end{cases} \quad (1) $$

where, $v_{i_d}$, $v_{i_b}$, $v_{i_c}$ are the inverter output phase voltages. $i_d$, $i_b$, $i_c$ are the grid line currents. $v_a$, $v_b$, $v_c$ are the grid phase voltages. L is the line filter inductor, and R is the parasitic resistance of the line inductor.

With the help of SYRF for controlling the current, Eq. (1) is transformed using abc to dq transform as follow:

$$ egin{cases} L \frac{di_d}{dt} = -R i_d + L \omega i_q + v_{i_d} - v_d \\ L \frac{di_q}{dt} = -R i_q - L \omega i_d + v_{i_q} - v_q \end{cases} \quad (2) $$

where subscripts d and q represent the direct and quadrature axes of SYRF, respectively. Injected active and reactive powers under such conditions are expressed as [13]:

$$ egin{cases} p(t) = p_0 = \frac{3}{2} v_d i_d \\ q(t) = q_0 = -\frac{3}{2} v_d i_q \end{cases} \quad (3) $$

where $p_0$ and $q_0$ are the instantaneous active and reactive powers, respectively.

Under unbalanced grid voltage conditions, both positive and negative sequences exist. Equation (2) is modified by taking into account these sequences:

$$ egin{cases} L \frac{di_d^p}{dt} = -R i_d^p + L \omega i_q^p + v_{i_d}^p - v_d^p \\ L \frac{di_q^p}{dt} = -R i_q^p - L \omega i_d^p + v_{i_q}^p - v_q^p \\ L \frac{di_d^n}{dt} = -R i_d^n - L \omega i_q^n + v_{i_d}^n - v_d^n \\ L \frac{di_q^n}{dt} = -R i_q^n + L \omega i_d^n + v_{i_q}^n - v_q^n \end{cases} \quad (4) $$

where superscripts p and n represent the positive and negative sequence components of voltage and current terms, respectively. Injected active and reactive powers under unbalanced grid voltage conditions are modified as [4, 13]:

$$ egin{cases} p(t) = p_0 + p_{c2} \cos(2\omega t) + p_{s2} \sin(2\omega t) \\ q(t) = q_0 + q_{c2} \cos(2\omega t) + q_{s2} \sin(2\omega t) \end{cases} \quad (5) $$

where $p_{c2}$, $p_{s2}$, $q_{c2}$ and $q_{s2}$ are the oscillating active and reactive power with sin and cos terms. From Eq. (5), it is clear that both active and reactive powers will contain oscillations twice the grid-frequency under unbalanced grid voltages. This phenomenon is discussed in detail in the following section.

### 3. Control structure

The main purpose of the control structure based-on LVRT with peak current limiter is to enhance the stability of the grid under voltage dips, avoid inverter tripping by over-current, eliminate active power oscillations under asymmetrical faults, and stay on grid-connected (feeding) mode by riding through the fault. In order to achieve these goals, the designed control topology should inject reactive power under voltage dips according to GC requirements, update the current references in SYRF to obtain zero active power fluctuations, and ensure that the injected current is at most equal to the threshold value with decreased active power. Figure 3 shows the general control topology which is discussed in detail in the following subsections.

#### 3.1. Synchronization process

Active and reactive power control in grid-connected inverter can be achieved based-on a good estimation of grid-angular frequency, which can be obtained by using real-time information of grid voltage parameters [28]. In this paper, phase-locked loop (PLL) is considered due to its robustness against asymmetrical faults. Moreover, voltage fault quantification is necessary for applying GCs. Therefore, Eq. (6) provides an estimation of the fault level based on positive direct grid voltage compared to nominal value [29].

$$ V_g(pu) = \frac{v_d^p}{v_{nom}^{peak}} \quad (6) $$

where, $v_{nom}^{peak} = \sqrt{\frac{2}{3}} V_g^{rms}_{l-l}$, and $v_d^p$ is obtained through a sequence separation of measured grid voltages.

#### 3.2. Sequence components

Real-time sequence components of grid voltages and currents are essential to ensure a resilient control of the system under unbalanced and faulty conditions [30]. Instantaneous positive and negative sequence components, $x_{abc}^p$ and $x_{abc}^n$, of a generic signal $x_{abc}$ which can express grid voltages $v_{abc}$ or grid currents $i_{abc}$, are given by:

$$ egin{cases} x_{abc}^p = [x_a^p, x_b^p, x_c^p]^T = [T^p] \cdot x_{abc} \\ x_{abc}^n = [x_a^n, x_b^n, x_c^n]^T = [T^n] \cdot x_{abc} \end{cases} \quad (7) $$

$$ \text{where, } [T^p] = \begin{bmatrix} 1 & a & a^2 \\ a^2 & 1 & a \\ a & a^2 & 1 \end{bmatrix}, \text{ and } [T^n] = \begin{bmatrix} 1 & a^2 & a \\ a & 1 & a^2 \\ a^2 & a & 1 \end{bmatrix}. $$

with $a = e^{j\frac{2\pi}{3}}$. These operations are followed by abc to dq transformation to obtain both grid voltages and currents in positive and negative SYRF.

#### 3.3. Grid codes requirements

Control of active and reactive powers depends mainly on the grid voltage level. Under normal operation ($V_g(pu)= 1$), DERs supply only the active power $P_{nom}$ with a unity power
<figure><img src="image_4.png" /><figcaption>Figure 3: Grid-feeding inverter control structure.</figcaption></figure>

factor, i.e., $Q_{ref} = 0VAr$. However, under abnormal grid conditions ($V_g(pu)< 1$), a required amount of reactive power must be injected into the grid according to the GCs to improve the grid stability [9, 8]. As shown in Figure 1, the quotient of reactive current compared to rated current is given by the following equation:

$$Q_p = \begin{cases} 1, & 0 \le V_g < 0.5 \\ 2(1 - V_g), & 0.5 \le V_g < 0.9 \\ 0, & 0.9 \le V_g < 1.1 \end{cases} \quad (8)$$

where $V_g$ is the grid voltage in pu. Therefore, the required reactive power to be injected into the grid is:

$$Q_{ref} = Q_p \cdot P_{max} \quad (9)$$

where $P_{max}$ is the maximum available output power of the generator.

As mentioned above, injected currents increase under faulty grid conditions. Following section focuses on proposed current limiter for reducing active power reference to an optimal value, while limiting the peak current at the threshold value as a maximum allowable value.

### 3.4. Current reference calculation

In order to eliminate active power oscillations while maintaining desired active and reactive powers, $[i_{d_{ref}}^p, i_{q_{ref}}^p, i_{d_{ref}}^n, i_{q_{ref}}^n]$

are determined using Eq. (5), and they are expressed as:

$$\begin{bmatrix} p_0 \\ p_{c2} \\ p_{s2} \\ q_0 \\ q_{c2} \\ q_{s2} \end{bmatrix} = \frac{3}{2} \begin{bmatrix} v_d^p & v_q^p & v_d^n & v_q^n \\ v_d^n & v_q^n & v_d^p & v_q^p \\ v_q^n & -v_d^n & -v_q^p & v_d^p \\ v_q^p & -v_d^p & v_q^n & -v_d^n \\ -v_d^n & -v_q^n & v_d^p & v_q^p \end{bmatrix} \begin{bmatrix} i_d^p \\ i_q^p \\ i_d^n \\ i_q^n \\ i_d^p \\ i_q^n \end{bmatrix} \quad (10)$$

From Eq. (10), required current references to mitigate active power oscillations can be determined by putting both $p_{c2}$ and $p_{s2}$ to zero:

$$\begin{bmatrix} i_{d_{ref}}^p \\ i_{q_{ref}}^p \\ i_{d_{ref}}^n \\ i_{q_{ref}}^n \end{bmatrix} = \frac{2}{3} \begin{bmatrix} v_d^p & v_q^p & v_d^n & v_q^n \\ v_d^n & v_q^n & v_d^p & v_q^p \\ v_q^n & -v_d^n & -v_q^p & v_d^p \\ v_q^p & -v_d^p & v_q^n & -v_d^n \end{bmatrix}^{-1} \begin{bmatrix} P_{ref} \\ 0 \\ 0 \\ Q_{ref} \end{bmatrix} \quad (11)$$

where, $P_{ref}$ and $Q_{ref}$ represent the desired active and reactive power injected into the grid. $Q_{ref}$ calculation is based on GC requirements while $P_{ref}$ is determined using current limiter process.

Finally, SYRF current references are expressed as [13, 31]:

$$\begin{bmatrix} i_{d_{ref}}^p \\ i_{q_{ref}}^p \\ i_{d_{ref}}^n \\ i_{q_{ref}}^n \end{bmatrix} = \frac{2P_{ref}}{3A} \begin{bmatrix} v_d^p \\ v_q^p \\ -v_d^n \\ -v_q^n \end{bmatrix} + \frac{2Q_{ref}}{3B} \begin{bmatrix} v_d^p \\ -v_q^p \\ v_d^n \\ -v_q^n \end{bmatrix} \quad (12)$$

where,
<figure><img src="image_5.png" /><figcaption>Figure 4: Dual current control schematic.</figcaption></figure>

$$A = (v_d^p + v_q^p) - (v_d^n + v_q^n)$$

$$B = (v_d^p + v_q^p) + (v_d^n + v_q^n)$$

### 3.5. Dual current controller

When the main grid is working normal (fault-free state), only the positive sequence exists in the grid voltage. The control of positive sequence current is achieved in two loops, the external one is used to calculate the current references from the desired active and reactive powers according to Eq.(12). $i_{dref}^p$ is generated by an outer active power controller while $i_{dref}^p$ is kept at zero to operate the inverter at near unity power factor [32]. The internal loop calculates the error between the reference currents with the measured one, and proportional integrator (PI) correctors control SYRF currents with any steady-state error [33].

PI controller outputs are added to the feed-forward and cross-coupling terms to achieve a decoupled control of active and reactive power [1]. The obtained voltage references are then transformed into natural reference frame, then should be divided by $V_{dc}/2$. These references are sent to a pulse width modulation (PWM) block to generate the switching pulses for inverter.

However, under unbalanced grid voltages, both positive and negative sequence components are present in the grid voltages, which require a dual current controller in both positive and negative sequences. Negative sequence current control is similar to that of positive sequence current, except that the sign of cross-coupling terms is reversed. Figure 4 shows the schematic of the dual current controller.

For the controller parameters tuning, “modulus optimum” method is adopted to calculate the PI coefficients. This method is explained in [34, 35] where the proportional and integral gains $K_p$ and $K_i$, respectively, can be determined by:

$$ \begin{cases} K_p = L \cdot f_{sw} \\ K_i = \frac{K_p \cdot R}{L} \end{cases} \qquad (13) $$

For digital implementation, the system control is implemented in discrete time by discretizing the PI controller and sampling all signals using “Zero-Order Hold (ZOH)” with a sampling time of $T_s = 0.05$ms. In order to take into consideration the control system time delay to be closer to a real-world scenario, a delay of one sampling period is introduced before sending the converter commands.

In order to save the system control performance as continuous-time, the “Backward-Euler” differentiation method is applied to find the PI parameters. The PI discrete parameters can be written as:

$$ \begin{cases} K_{p,d} = K_p \\ K_{i,d} = K_i \cdot T_s \end{cases} \qquad (14) $$

## 4. Proposed Current Limiter

The proposed peak current limiter is designed to improve the LVRT strategy of a grid-feeding inverter under faulty conditions. The proposed method avoids the switching between synchronous and natural reference frame for current control. In order to ensure fast magnitude estimation, a magnitude current predictor [27] is used for current limiting, which is accurate and fast compared to RMS-based current limiting methods. Considering a sinusoidal signal given by:

$$x(t) = A \cos(\omega t + \varphi) \qquad (15)$$

where, A is the magnitude of signal, $\omega$ is the angular frequency, and $\varphi$ is the phase shift.

The magnitude A of the signal $x(t)$ can be determined after a negligible delay due to time differential operation introduced by the following equation:

$$A = \sqrt{(x(t))^2 + \frac{1}{\omega^2} \left(\frac{dx(t)}{dt}\right)^2} \qquad (16)$$

Generally, current limiter in grid-feeding inverter restricts inductor currents from exceeding a threshold value, which is the maximum allowable peak current. New limited current references are provided to the current controller to avoid damage of inverter and semiconductors. The following equation describes the limiting process in natural reference frame [23]:

$$ i_j^{ref} = \begin{cases} i_{th} \\ -i_{th} \\ i_{th}^{ref} \end{cases}, \quad \begin{cases} i_j^{ref} > i_{th} \\ i_j^{ref} < i_{th} \\ \text{otherwise} \end{cases} \qquad (17) $$

where, $j = a, b, c$ and $i_{th}$ is the threshold value of currents which is taken as 1.5 time of rated current in this paper, i.e., 1.5 pu.

The current limiter proposed in [27] is presented in Figure 5. The main drawback of this current limiting strategy is its non-compliance with GC requirements under faulty conditions. Moreover, generated current references after the limiter do not ensure the suppression of active power oscillations as they are modified by the saturation process.
<figure><img src="image_6.png" /><figcaption>Figure 5: Current limiter process in [27].</figcaption></figure>

As shown in Figure 5, current references are transformed into natural reference frame at $\theta(t)$, which is obtained using PLL for grid voltages. Then, natural reference current magnitudes are calculated using Eq. (16) and saturated at the threshold value. Saturated current references are also transformed to SYRF at $\theta(t)$ to ensure the current control in SYRF. This method is too complex to be implemented in active and reactive powers control because of the double sequence separation with the same phase angle $\theta(t)$.

The proposed current limiter is based on closed-loop reducing the active power and observing the resulting current references. This limiter should ensure that phase currents maximum magnitude be at most equal to the threshold value. This later is done by computing online active power reference that is also embedded in the current references generation.

Figure 6 shows the calculation method of the maximum currents error which can be expressed as:

$$ \epsilon_{max} = \max(A_{i_a}, A_{i_b}, A_{i_c}) - i_{th} \quad (18) $$

<figure><img src="image_7.png" /><figcaption>Figure 6: Current error computation process.</figcaption></figure>

Since the reactive power is fixed by GC requirements, the only solution to limit the phase currents is to reduce the active power reference. This idea is analog to perturb and observe approach, active power is decreased until the currents are less than the threshold value. This method maintains LVRT properties while working at inverter-limit to avoid active power losses under faulty conditions. The overall method is explained in Figure 7, which shows that the active power reference is updated in real-time to ensure limiting peak current under severe grid faults. Another point that should be mentioned is the response of the proposed current limiter under large grid voltage dips, i.e., the active power reference is decremented until zero, but the currents are more than the threshold value. Therefore, both GC requirements and power topology should also be taken into account. Under such conditions, the only way to limit the currents and protect the inverter from over-currents is to reduce the

<figure><img src="image_8.png" /><figcaption>Figure 7: Flowchart of the proposed peak current limiter.</figcaption></figure>

reactive power. Since the reactive power reference is fixed by GC requirements in Eq. (9), the best solution is to reduce the generator maximum available output power $P_{max}$ and recalculate the reactive power reference.

As shown in Figure 7, under high current references, the active power reference is decremented by $\Delta P$ at each sampling period. $\Delta P$ may continuously have a constant value. But this method induces active power losses again and a non-negligible delay in the control process. Addressing this issue, the proposed approach introduces a regulator to find the optimal $\Delta P$ that should be subtracted irrespective of the fault situation. Under large voltage dips when $\Delta P$ is higher than $P_{nom}$, $P_{max}$ is
<figure><img src="image_9.png" /></figure>

<figure><img src="image_10.png" /><figcaption>Figure 8: Active power reference calculation : (a) Schematic of updating active power process, and (b) Change of active power reference under severe faults.</figcaption></figure>

reduced in the same way using the following equation:

$$P_{max} = 2 \cdot P_{nom} - \Delta P \quad (19)$$

As shown in Figure 8a, an integrator corrector is chosen to determine the amount of active power to be reduced. The following equation provides ΔP expression with $k_i$ denoted as the integrator coefficient:

$$\Delta P = k_i \int \varepsilon_{max} dt \quad (20)$$

where $k_i = \frac{\sqrt{3} \cdot V_g^{rms}}{t_0}$. $t_0$ is a tuning parameter which characterizes the necessary time duration to find the suitable value of ΔP. In our case, $t_0$ is chosen to be in the range of one grid voltage cycle. Therefore, integrator coefficient value is $k_i = 32900$.

This process offers many advantages, like the fast determination of the active power reference due to the proportionality between the current error and ΔP. The integrator controller is equipped with a saturation block to ensure that ΔP will be limited between 0 and $P_{nom}$. Moreover, an anti-windup feature is important for this controller to avoid its over-charging when the current error is negative, i.e., in small grid faults. Finally this process is event-triggered which is enabled only under faulty conditions ($V_g(pu) \neq 1$). This later is done using an external reset to the controller.

Figure 8b shows an illustration of the proposed approach under grid fault conditions. It can be noticed that ΔP varies linearly with alternating positive and negative slopes until it becomes constant, which ensures a maximum phase current to be not more than threshold value. The obtained ΔP is subtracted from $P_{nom}$ to get the new reference of active power.

## 5. Results and Discussions

In order to demonstrate the effectiveness and the validity of the proposed control shown in Figure 3, extensive simulations are performed. Simulation parameters are listed in Table 1.

<figure><img src="image_11.png" /></figure>

<figure><img src="image_12.png" /></figure>

<figure><img src="image_13.png" /><figcaption>Figure 9: Unbalanced fault impact: (a) Grid voltages, (b) Injected currents, and (c) Injected active and reactive powers.</figcaption></figure>

<figure><img src="image_14.png" /></figure>

<figure><img src="image_15.png" /></figure>

<figure><img src="image_16.png" /><figcaption>Figure 10: Current limiter of [27] : (a) Grid voltages, (b) Natural reference frame current references, and (c) Produced active and reactive powers.</figcaption></figure>

To verify the fault impact on the phase currents, a first simulation is carried out without any current limiter process. Figure 9 shows the result of this simulation, in which an asymmetrical fault is occurred at $t = 0.3s$. During the faulty period, Fig-
<figure><img src="image_17.png" /></figure>

<figure><img src="image_18.png" /></figure>

<figure><img src="image_19.png" /></figure>

<figure><img src="image_20.png" /><figcaption>Figure 11: Proposed current limiter under unbalanced severe fault: (a) Grid voltages, (b) Injected currents, (c) Injected active and reactive powers, and (d) Desired change in active power.</figcaption></figure>

ure 9a illustrates grid voltages with $v_b = 0.4$pu and $v_c = 0.8$pu which indicate a grid voltage dip with $V_g = 0.73$pu.

This grid fault induces an increase in injected grid currents with different amplitudes as depicted in Figure 9b. In this result, we notice a clear over-currents comparing to threshold value, which can damage the inverter and its semi-conductor components. As shown in Figure 9c the LVRT strategy is applied by injecting a reactive power of $Q = 2.7kVA$r according to GCs during the faulty period. However, the active power is maintained at $P_{nom}$ without any oscillations due to the dual current controller.

In order to verify the output of the current limiter proposed by [27], the previous scenario is simulated while observing its current limiter outputs. Figure 10b shows the current references in natural reference frame, which are generated using the saturation block of current magnitudes and *PLL* of the injected currents. In this result, we notice that currents do not go beyond threshold value. However, if these currents are injected into the grid, the LVRT strategy under faulty grid voltages cannot be ensured. As shown in Figure 10c, GC requirements are not respected to support the grid voltage dip, because the reactive

<figure><img src="image_21.png" /></figure>

<figure><img src="image_22.png" /></figure>

<figure><img src="image_23.png" /><figcaption>Figure 12: SYRF current references: (a) Without using current limiter, (b) Using current limiter of [27], and (c) Using the proposed current limiter.</figcaption></figure>

power reference is not equal to the required value corresponding to this grid fault. Moreover, the active power always contains oscillations twice the grid-frequency. Hence, this current limiter is not able to ensure the LVRT strategy of grid-feeding inverter under faulty conditions. To overcome this issue, a novel current limiter is proposed in this paper, which is verified in the following simulations.

The proposed current limiter is tested under the same previous fault, which is a severe fault that requires a current exceeding the threshold value. Figure 11a illustrates grid voltages transition from healthy to faulty state at $t = 0.3$s. Before this instant, the inverter injects balanced currents equal to 1pu as shown in Figure 11b. Also, during this period, the injected active power equals to $P_{nom}$ with unity power factor, and the limiter output ($\Delta P$) is zero as shown by Figures 11c and 11d, respectively.

During faulty conditions, the current limiter is enabled to prevent over-currents. Figure 11b shows that the inductor currents are well limited at the threshold value after one grid-cycle of delay. The LVRT strategy is applied by injecting the suitable reactive power ($Q = 2.7kVA$r), and a reduced active power ($P = 3.4kW$) without any fluctuations as shown in Figure 11c. In Figure 11d, the output of current limiter regulator is presented. In which, the required change in active power ($\Delta P$) is calculated to obtain currents that are limited to the threshold value. This proposed approach avoids active power losses during faults, and it is also event-triggered, i.e., the limiter process is enabled only in presence of grid faults.

Since the proposed current controller regulates the injected currents in SYRF, current references are represented in Fig-
<figure><img src="image_24.png" /></figure>

<figure><img src="image_25.png" /></figure>

<figure><img src="image_26.png" /></figure>

<figure><img src="image_27.png" /><figcaption>Figure 13: Proposed current limiter under small unbalanced fault: (a) Grid voltages, (b) Injected currents, (c) Injected active and reactive powers, and (d) Desired change in active power.</figcaption></figure>

ure 12. It shows the difference between SYRF current refer-ences for considered case studies. Figure 12a shows the current references for any current limiter. The presence of negative se-quence helps in suppressing active power fluctuations during the fault. The SYRF current limiter references of [27] and our proposed limiter are presented in Figures 12b and 12c, respec-tively. The difference is clearly noticed in the SYRF current references between studied cases. This difference appears in both positive and negative sequences due to the saturation pro-cess in the limiter of [27]. The non-respect of the LVRT control in this later is justified by the modification in the current refer-ences after its saturation block.

In order to verify the response of the proposed current lim-
iter under a small grid fault which does not require overt-current,
a simulation is carried out by putting both v<sub>b</sub> and v<sub>c</sub> equal
to 0.8pu at t = 0.6s. An asymmetrical voltage dip occurs
with V<sub>g</sub> = 0.86pu as shown in Figure 13a. Injected currents
are represented in Figure 13b, which are unbalanced and less
than the threshold value. To avoid active power losses, Fig-
ure 13c shows that the injected active power has turned into
P<sub>nom</sub>, while injecting the reactive power according to GC re-

<figure><img src="image_28.png" /></figure>

<figure><img src="image_29.png" /></figure>

<figure><img src="image_30.png" /></figure>

<figure><img src="image_31.png" /><figcaption>Figure 14: Proposed current limiter under small to severe fault transition: (a) Grid voltages, (b) Injected currents, (c) Injected active and reactive powers, and (d) Desired change in active power.</figcaption></figure>

quirements (Q = 1.4kVAr) to ensure LVRT capability. In Fig-
ure 13d, the output of current magnitude regulator (ΔP) is plot-
ted, which is equal to zero and ensuring P<sub>ref</sub> = P<sub>nom</sub>. These
results prove the flexibility of the proposed current limiter un-
der different faulty situations.

For more illustration, Figure 14a shows the inverse transi-
tion, i.e., from small to severe fault, These results prove the
efficacy of using a limit-saturation associated with anti-windup
option in the current magnitude regulator. The latter avoids the
over-charging of the integrator during the small-intensity fault.
The response of current limiter is fast, and the power references
are instantly updated as shown in Figures 14b, 14c, and 14d.

The proposed current limiter is verified also under balanced
grid voltage dips. As shown in Figure 15a, a symmetrical fault
is occurred at t = 0.3s with Vg = 0.6pu. Figure 15b illustrates
injected currents which are balanced and limited to the thresh-
old value after fault appearance. LVRT strategy is applied to
manage this fault by injecting a reactive power of Q = 4kVAr,
which satisfy GC requirements. On the other hand, the active
power is reduced smoothly by subtracting the required ΔP. It
is obtained from the proposed current limitation controller as
<figure><img src="image_32.png" /></figure>

<figure><img src="image_33.png" /></figure>

<figure><img src="image_34.png" /></figure>

<figure><img src="image_35.png" /><figcaption>Figure 15: Proposed current limiter under balanced fault: (a) Grid voltages, (b) Injected currents, (c) Injected active and reactive powers, and (d) Desired change in active power.</figcaption></figure>

<figure><img src="image_36.png" /></figure>

<figure><img src="image_37.png" /></figure>

<figure><img src="image_38.png" /></figure>

<figure><img src="image_39.png" /><figcaption>Figure 16: Proposed current limiter under large voltage dips (from 40% to 60%): (a) Grid voltages, (b) Injected currents, (c) Injected active and reactive powers, and (d) Desired change in active power.</figcaption></figure>

depicted in Figures 15c and 15d.

Another simulation is performed to verify the proposed algorithm under large voltage dips. In this simulation, a transition from 40% to 60% voltage dips is introduced. As shown in Figure 16, a large balanced fault of 60% ($V_g = 0.4pu$) occurs at $t = 0.6s$.

The active power is decremented until it is equal to zero and the reactive power tends to increase to the maximum value ($Q_p = 1$). However, in such conditions, the injected currents will be higher than the threshold value. To overcome this problem, the reactive power is also reduced to $Q = 3.05kVAr$ by decrementing the maximum available output power of the generator.

## 6. Conclusion

An improved online current limiting-based LVRT strategy is proposed for grid-feeding inverter under faulty conditions. A new concept based on online active power decrement is introduced to limit inverter current. It is achieved using a closed-loop regulation to control phase currents magnitude, provide the

required decreased active power, and avoid the inverter damage. Moreover, LVRT capability ancillary services are satisfied, grid code requirements are respected to deal with grid voltage dips, and active power oscillations are suppressed under unbalanced grid faults using a dual current controller.

The archived simulation results clearly highlight the effectiveness and robustness of the proposed LVRT strategy under symmetrical/asymmetrical faults.

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