# Critical review of hybrid modular multilevel converters for HVDC transmission in offshore wind energy

Ratna Raj, Abdellatif Elmouatamid, Akhyurna Swain, Philip W.T. Pong

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Ratna Raj, Abdellatif Elmouatamid, Akhyurna Swain, Philip W.T. Pong. Critical review of hybrid modular multilevel converters for HVDC transmission in offshore wind energy. Energy Reports, 2025, 14, pp.1761-1778. 10.1016/j.egyr.2025.07.017. hal-05263514

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## Review article

# Critical review of hybrid modular multilevel converters for HVDC transmission in offshore wind energy

Ratna Raj<sup>a, ●</sup>, Abdellatif Elmouatamid<sup>b</sup>, Akhyurna Swain<sup>a</sup>, Philip W.T. Pong<sup>a, ∗</sup>

<figure><img src="image_2.png" /></figure>

### ARTICLE INFO

**Keywords:**

AC-DC power conversion

DC fault blocking

Hybrid Modular Multi-Level Converter

HVDC Transmission

Offshore Wind Energy

STATCOM

### ABSTRACT

For the integration of wind energy into the transmission system, High Voltage DC (HVDC) is the most efficient and cost-effective option. Modular multilevel converters have emerged as the most suitable converters for the required AC/DC conversions. To maintain power availability, stability, and reliability in the HVDC transmission, the converters' ability to offer fault ride-through (FRT) and work as static compensators (STATCOM) during DC faults have become important requirements. The conventional half bridge-based MMC is the most cost-effective, efficient, and widely used topology, but it cannot meet these requirements. Though full-bridge MMC has this ability, it doubles the converter cost, device count, and losses. In the present MMC topology, the capacitors occupy 50% of the volume and 80% weight of the converter. Reducing energy storage requirements is needed for their efficient use in offshore wind energy substations. Many Hybrid MMC (HMMC) topologies have been introduced in the last few years to offer a solution to meet these requirements, but no topology has been found yet that can fulfill all the required criteria. A comprehensive review of the existing topologies, their features, strengths, and drawbacks are needed to identify research gaps and guide future works. This paper provides a thorough and systematic review of the topology, fault handling, and STATCOM mode of all hybrid MMCs (HMMCs) for HVDC offshore wind energy transmission found in the literature. It compares these topologies' structure, losses, and functionality to guide future research. A case study calculates these topologies' losses and energy requirements by using time-domain analysis of a switching-based model in MATLAB of these converters, with a rating of 1500MVA with 1050KV DC voltage. The results present a quantitative comparison of losses and energy storage requirements across these topologies which would be useful to give directions to future works.

## 1. Introduction

Offshore wind energy has experienced substantial growth over the last decade. Driven by increasing energy demand, offshore wind farms (OWFs) are expanding in size and relocating to deeper waters, where stronger, more consistent winds allow for larger wind turbine installations. The electricity generated is initially converted to AC power and collected at an offshore substation (OSS). Conventionally, this power is then transmitted to shore via underground High Voltage AC (HVAC) cables. However, as the distance between the OWF and the shore increases, HVAC transmission becomes less efficient due to higher reactive power losses and cable costs (Li et al., 2021). Beyond the distance of 150 kms offshore, High Voltage Direct Current (HVDC) transmission emerges as a more economically viable solution compared to

HVAC (Li et al., 2021; Yang et al., 2022; Ryndzionek and Sienkiewicz, 2020).

The HVDC transmission from OSS requires rectification on OSS and inversion onshore to connect the HVDC to the grid. For these conversions modular multilevel converters (MMCs) are the most suitable voltage source converters (VSC) (Flourentzou et al., 2009) compared to the conventional line commuted converters (LCC) (Marquardt, 2010, 2018; Perez et al., 2015; Lesnicar and Marquardt, 2003) because they offer: (i) modularity, (ii) black start capability, (iii) independent control of active and reactive power, (iv) high quality output which eliminates requirement of large-sized filters, (v) lower dv/dt stress on devices which reduces the ratings of the devices, (vi) low switching frequency which reduces switching losses in the devices, (vii) power flow reversal by just changing current direction, and (viii) suitability for

<footnote><sup>a</sup> Electrical and Computer Engineering Department, New Jersey Institute of Technology, Newark, NJ 07102, USA</footnote>

<footnote><sup>b</sup> Sciences and Technology Department, University of French Guiana, UMR Espace-Dev, Cayenne, French Guiana</footnote>

<footnote>* Corresponding author.</footnote>

<footnote>E-mail addresses: ratna.raj@njit.edu (R. Raj), abdellatif.elmouatamid@univ-guyane.fr (A. Elmouatamid), as594@njit.edu (A. Swain), philip.pong@njit.edu (P.W.T. Pong).</footnote>
multi-terminal DC grid. Though the cost of MMC based system is higher than its counterpart LCC, in offshore wind energy HVDC transmission system, its advantages outweigh its cost.

To diversify energy sources and to increase energy density of offshore substation, floating solar farm (Bi and Law, 2023) and ocean energy harvesting, or their combination (Esteban and Leary, 2012; Panda et al., 2023) are gaining considerable attention. Placing solar farms on the open sea is viewed as a highly favorable proposition, freeing up valuable land-based real estate. Netherlands has taken lead in this area and has installed a pilot floating solar farm in North sea (Vlaswinkel et al., 2023). Cooler atmosphere and water in the offshore environment help in improving efficiency of solar farms. Co-locating solar farms with wind farms proves advantageous in many ways. Firstly, due to the efficient use of the busy sea space (Vlaswinkel et al., 2023), the wide space of about 1.5 km between the wind turbines is most suitable for placing the solar panels. Secondly, the resources of cable network of the wind farm make the integration of floating solar farms more economical and easier (Solomin et al., 2021). Thirdly, wind and solar resources have negative correlations which keep the output of the combined installation consistent throughout the year. Harvesting wave energy is another attractive green energy option. Wave energy transmission to onshore grids is not yet cost effective but utilizing it locally, like in oil and gas platforms, is an economical and greener option (Oliveira-Pinto et al., 2019). Due to the intermittency of wind energy, combining it with wave energy has been identified as a more consistent energy system. Methodology to identify zones where wind and wave energy can be harnessed together has been proposed in Weiss et al. (2018) and Astariz and Iglesias (2016). Oscillating water columns have been used by Sarmiento et al. (2019) to harness wave energy by installing them on wind turbines installed on monopile structure. The piezo electric energy harvester, which can be implemented to harness ocean energy along with wind has been reviewed in Liu et al. (2023). Turboelectric nano generators are being researched too (Rodrigues et al., 2020; Song et al., 2022) but these will be more helpful in IOT applications. All these technologies have very promising future prospects but are still in infancy stage. Since wind energy remains the main source of power for OSS, this paper focusses on wind energy based HVDC transmission system.

Due to wind intermittency and low inertia, wind energy is a weak A. C. system. To improve grid stability and reliability, recent grid codes require that these MMCs should be capable of handling FRT during AC and DC side faults (Tavakoli et al., 2022; Shi et al., 2020). Handling AC side faults are well established techniques, and the converters are capable of riding through these faults. But handling DC-side short circuit (SC) faults still remains a challenge for MMCs. The conventional approach to handle DC-side SC faults in MMCs is to turn off the IGBTs and activate the AC circuit breaker. Till the AC breaker is activated, the free-wheeling diodes (FWD) of the converter are burdened with carrying the high DC SC current and are open to AC side feed to the DC fault current. Due to the slow response time of the AC circuit breaker, which is a few cycles of the line frequency, the FWDs are exposed to high current for a long enough time to get damaged and thus have a high failure rate (Qin et al., 2015). Another approach to handle a DC-side SC fault is to use a DC-circuit breaker. The DC-circuit breakers, however, are presently bulky, and their technology is not advanced enough to handle the high DC fault current efficiently.

The DC-side SC faults in overhead transmission lines are mostly transient, and opening a circuit breaker to clear the fault increases the time needed to restore normal power transmission. DC-side SC faults in underground cables are of permanent type. With the collapse of DC voltage, the active power transfer between the AC and DC sides becomes zero, which may result in the AC grid's instability. To maintain grid stability the AC voltage needs to be maintained through reactive power transfer between the AC and DC side till the fault is cleared. The revised grid codes require that for grid reliability and stability, during AC-side and DC-side SC faults the converter should provide FRT and support

the AC grid by supplying reactive power by working as a static synchronous compensator (STATCOM) (Tavakoli et al., 2022; Shi et al., 2020). This approach eliminates the requirement of extra hardware and can be made as an efficient topology that has a very high response time to protect the devices in the converter.

Half-bridge based submodules (HB-SM) form the conventional building block of the MMC transmission (Teeuwsen, 2011; Li and Liang, 2022). They have the least amount of devices amongst all the submodules and hence minimum losses and cost, which have made them the conventional choice. The major challenges this topology faces are (1) it cannot handle DC short-circuit fault and cannot provide FRT during DC-side SC faults, (2) it cannot work as a STATCOM to provide reactive power to the AC grid during DC-side SC faults, (3) although the DC-side pole capacitor has been eliminated as compared to conventional VSC, the sub-module (SM) capacitors are bulky and together take more than 50% of the converter by volume and 80% by weight (Wang et al., 2023), (4) circulating currents increase the converter losses and device ratings, while adding complexity to the control system to mitigate them. By replacing HB-SMs with full-bridge SMs, the Full-Bridge-MMC (FB-MMC) meets these requirements, can interrupt the DC fault currents in a fraction of a second and can work as STATCOM during DC SC faults (Kontos et al., 2017; Lin et al., 2016). However, its device count becomes double the device count of HB-MMC, which increases the losses and cost (Kontos et al., 2017; Jovcic et al., 2017), and thus is not the optimum choice. It does not help with reducing the converter volume or the circulating current either. The present challenge is to find a topology that has losses comparable to HB-MMC, along with FRT and STATCOM features of FB-MMC, and a volume smaller than HB-MMCs.

Literature shows various approaches proposed by the researchers to address the drawbacks of HB-MMC. One approach has been to replace the HBSM with an existing or novel fault blocking SM topology which has losses less than FB-MMC (Yang et al., 2016; Hu et al., 2019a; Li et al., 2015a; Zhang and Zhao, 2015). A second approach has been to use hybrid MMCs (HMMCs) which are constructed either by mixing unipolar SM with fault blocking SM or by mixing MMCs with conventional VSC topology. A third hybrid approach is to mix LLC with MMC, where LCC is used at the sending end and MCC is used at the receiving end (Kjørholt, 2014; Tang and Xu, 2014). Though this approach makes the combination suitable for multiterminal HVDC and provides black start capability to the system, having LCC at the sending end is not suitable for a weak energy system like wind technologies.

Hybrid MMC topologies proposed in literature reduce losses by reducing the cost, and volume to a value smaller than that of FB-MMC. One of the approaches to reduce losses and costs is to use SMs which have device count smaller than FBSMs, as observed in mixed HMMCs. Another approach is to mix MMC and VSC topology to reduce voltage stress on arms that leads to fewer SMs and hence lower device count. In HMMCs, the converter volume reduction is approached by reducing the size or number of capacitors. The challenge of reducing the capacitor size has been addressed in a couple of ways. One approach is proposing different control technologies to reduce capacitor voltage ripples which reduces the capacitor rating and hence the size. One of the ways to reduce the ripple is by injecting appropriate harmonics in the circulating current (Picas et al., 2013; Zhao et al., 2019). Control techniques like asymmetric mode control (Yang et al., 2017) and switch cycle control (Jun et al., 2014) have also been applied to reduce the current ripple, which makes the converter control more complex. Another approach to reduce capacitor volume is to modify the MMC topology which reduces the number of SMs, and hence the capacitor count and the total energy requirement. Many hybrid topologies have been introduced by combining the two/three-level VSCs with MMC that promise to reduce the energy requirement by reducing the SM count and the size of the capacitors.

Since HMMCs promise to overcome the above-mentioned drawbacks of MMCs, they emerge as the most promising option for converters in HVDC transmission for offshore energy and are the focus of this review
paper. A critical review of all the proposed hybrid topologies in litera-
ture is essential to evaluate the existing solutions and design future
research. While there have been reviews of MMCs in general (Sakib
et al., 2022; Dekka et al., 2017; Perez et al., 2021; Erat et al., 2022; Wan
et al., 2020; Lang et al., 2017; Bakas et al., 2021; Konstantinou et al.,
2015), there is a notable lack of focus on HMMCs. Moreover, existing
research has often compared their introduced topologies with selected
alternatives, but comprehensive comparisons across all existing HMMC
topologies are still lacking. Additionally, new topologies have emerged
that have not been covered in existing reviews. Control of MMCs is
complex and hybrid MMC topologies add to the complexity. Discussion
of various control strategies applied to these hybrid MMCs is missing in
literature. These research gaps emphasize the need for a comprehensive
and up-to-date review of all HMMC topologies, to assess the advantages
and limitations of these topologies, and guide future research in this
technology. To address these gaps, this review paper makes a significant
contribution to literature by:

(i) Providing an updated overview of all proposed HMMC topologies to have a comprehensive insight into all the different topologies that have been investigated for HVDC offshore transmission, (ii) Categorizing these topologies based on their structure and functionalities to help compare and contrast the different features of these topologies, (iii) Analysis of various control strategies needed for seamless operation and co-ordination of hybrid topologies (iv) Present a techno-economic analysis of HMMCs (iv) Conduct a case study to calculate the losses (conduction and switching) and energy requirements of converters with the same power rating across various topologies for a fair comparison. For this a switching-based model was constructed in MATLAB having apparent power rating of 1 GW and DC side voltage of 1050KV. Extensive time-domain simulations were done for loss and energy requirement calculations. (v) Compare the DC SC response time of FB-SM based MMC with the most promising HMMC topology i.e. mixed HMMC.

## 2. Various hybrid mmc topologies, their DC Short circuit fault handling capabilities, and statcom operation

In the symmetrical monopole configuration, a pole-to-pole (PTP) DC link fault is the most common fault and poses a significant risk to MMC. It is composed of the DC fault current and AC feed to the DC SC as shown in Fig. 1 (Tang and Xu, 2014). The AC current makes the diodes work as an uncontrolled rectifier which can lead to device overheating and damage.

The converters are expected to protect themselves and the grid (Li et al., 2016) by (1) limiting peak fault currents to prevent device overheating and failure, and preserving capacitor energies (2) enabling DC fault current attenuation and extinction, (3) blocking AC side power supply to prevent uncontrolled rectification from the AC grid (4) supplying reactive power to the AC grid, when needed, to maintain its stability. Various hybrid topologies have been proposed to have DC fault blocking, a FRT feature, and a STATCOM mode that can provide reactive power during DC faults. These have been created by either adding extra devices to HBSM, mixing the submodules, or integrating two/three/five-level VSCs with MMC as discussed below.

### 2.1. Enhanced HBSM MMCs

Additional components are added to the classical HBSM-MMC to divert /divide the DC fault current from the diodes and prevent the free-wheeling action. One of the approaches (Li et al., 2020a) has three thyristors and an RC network connected in a series-parallel configuration across the bottom Insulated Gate Bipolar Transistor (IGBT) of the HBSMs as shown in Fig. 2(a). The thyristors are kept switched off in normal operation which bypasses the RC circuit. During DC faults, all the IGBTs are switched off and thyristors are turned ON bringing the RC network into the fault current path. The fault current is initially divided between the FWD and thyristor T₁, and subsequently transferred to

<figure><img src="image_3.png" /><figcaption>**Fig. 1.** AC and DC current flow during pole-to-pole DC-side short circuit fault in MMC.</figcaption></figure>

thyristor T₁, T₂ and T₃, to be attenuated and extinguished. The FWDs carry the divided fault current initially, which remains substantially high, and thus the probability of device failure still remains high.

Extra IGBT with an anti-parallel diode can be added in series at the output terminal to block the flow of fault current as shown in Fig. 2(b) (Nguyen and Lee, 2015). The IGBT remains ON during normal operation and is switched OFF once the DC fault is detected. The anti-parallel diode of the series IGBT blocks the fault current and the freewheeling of the bottom diode, thus closing all paths for fault current, as shown in Fig. 2(b). The series IGBT with the anti-parallel diode also prevents the AC grid from feeding into the fault current.

Another enhancement is proposed in Li et al. (2013a) where a reverse-connected IGBT with an anti-parallel diode is added in series to the bottom IGBT. The capacitor is split into two and its center is connected to the output via a diode as shown in Fig. 2(c). The IGBT remains ON for normal operation and is switched OFF after detecting a DC-side SC fault. This arrangement places the capacitor in reverse bias for the fault current and thus helps to attenuate and block it.

Approach in Fang et al. (2020) uses the HBSM’s inherent ability to block positive-direction fault currents by reorienting the flow of fault current with the help of thyristor-based director switches (DS), guiding it through the SM capacitor in the positive direction (Fig. 2(d)). The capacitor voltage is reverse biased to this current flow and can effectively attenuate and block the fault current.

Saleki et al. (2022) propose inserting a fault-tolerant SM (FTSM) in series between two HBSMs. This FTSM has two Reverse-Blocking IGBTs (RB-IGBTs) in parallel with an RC network (Fig. 2(e)). The RB-IGBTs remain ON for normal operation and are switched OFF during DC-side SC fault. This bypasses the RC network for normal operation and inserts it in series with the HBSM during fault. The capacitor of the RC network reverse biases the free-wheeling diode of HBSM and blocks the fault current as well as the AC feed into the fault current. By controlling the number of FTSMs in the path during the DC-side SC fault, this
<figure><img src="image_4.png" /><figcaption>Fig. 2. Various Enhanced HB-Sub-Modules with current flow during DC-side short circuit fault</figcaption></figure>

enhancement offers “Limited Mode” for non-permanent types of faults where the AC grid stability can be maintained by limiting the fault current instead of completely blocking it.

All these enhancements require a switch that remains ON during normal operation thus adding to the conduction losses of the converter. The advantage of these enhancements is that no change is needed in the existing control circuit for the HB-MMC, making their implementation easier and less complex. These enhancements provide FRT but cannot maintain grid stability by providing reactive power during DC-side short circuit faults. Since these enhancements cannot provide FRT, AC side circuit breaker needs to be activated to clear the fault.

## 2.2. Mixed SM HMMC

To get a trade-off between reduced losses and having DC-side SC fault blocking and FRT capabilities, researchers have used partial substitution of HBSMs in an MMC with fault-blocking SMs as shown in Fig. 3. Here SM1 is a unipolar SM like Half Bridge SM, and SM2 is an SM with fault blocking capability. Not all the modules presented in the literature are suitable for HVDC applications. The various submodules are enlisted in Sakib et al. (2022) and Tian et al. (2020) and the work discusses their limitations and highlights the ones that can be used for HVDC. Amongst them, the SMs that have been tried in Mixed Hybrid topology for HVDC applications are Unipolar-FBSM (UFBSM), Clamped-Double-SM (CDSM), 5-Level-Cross-Connected-SM (5LCCSM), Series-Connected-Double-SM (SCDSM), Switched-SM (Sw-SM), Modified-Active-Neutral-Point-Clamped-SM (M-ANPC-SM), Bidirectional-Reverse-Blocking-SM (RBSM), and Active-Neutral-point-SM (ACT-SM) (Qin et al., 2015; Li et al., 2015a; Al Hosani and Nguyen, 2018; Nguyen and Lee, 2017; Marquardt, 2011; Tian et al., 2021). Their topologies and the current flow during the DC-side SC fault have been shown in Fig. 4(a). The loss analysis of various SMs presented in Tian et al. (2022) shows the mixed HMMC of Modified-Active-Neutral-Point-Clamped-SM (M-ANPC-SM) with

<figure><img src="image_5.png" /><figcaption>Fig. 3. Topology of Mixed HMMC.</figcaption></figure>

Bidirectional-Reverse-Blocking-SM (BBSM/RBSM), and M-ANPC-SM with Active-Clamped-SM (ACTSM), to have losses comparable to HB-MMC. However, these SMs have different ratings for the capacitors
<figure><img src="image_6.png" /><figcaption>Fig. 4. (a) Various DC fault-blocking sub-modules for HVDC Mixed HMMC and path of DC fault current (i)HBSM; (ii)FBSM; (iii)Unipolar FBSM (UFBSM); (iv)Clamped Double SM (CDSM); (v)Five-Level Cross Connected SM (FLCCSM); (vi)Series Connected SM (SCSM); (vii)Modified Active Neutral-point Clamped Unipolar SM (M-ANPC-SM); (viii)Active Clamped T-type SM. (b) One phase of Arm-Multiplexing Topology.</figcaption></figure>

and non-switching IGBTs which makes them non-modular and hence unsuitable for MMCs. The topology presented in Wang et al. (2023) introduces a different approach to create mixed SM in the leg of an MMC. In this topology, each leg has three arms instead of two, each with an equal number of sub-modules (Fig. 4(b)). The upper and lower arms have FBSM while the middle arm has HBSMs. The middle arm SMs are inserted into the upper or lower arm, via a switch, depending on which arm needs to produce a higher voltage. This approach results in reducing the required number of SMs on each leg by 25 %.

**DC Fault Operation and STATCOM Mode:** To minimize device losses while retaining DC fault-blocking capability, the number of fault-blocking submodules substituted into the arms must be sufficient to ensure that their collective series voltage in the fault current path, during a DC-side SC event, exceeds the peak line-to-line AC voltage. This optimized number of substituted SMs can be calculated following the procedure discussed in Zeng et al. (2015). The MMC is assumed to have the DC voltage Vdc, and the voltage stress on all capacitors as Vc. Each arm of HB-MMC has N submodules such that

$$NV_c = V_{dc} \qquad (1)$$

In a hybrid MMC with FBSMs and HBSMs, let Ns be the number of substituted FBSMs in each arm. The line-to-line peak voltage across the leg will be: $v_{lpeak} = \sqrt{\frac{3}{2}}mV_{dc}$, where m is the modulation index of the converter. During DC faults the HBSMs are switched OFF and the FBSMs are used to block the fault current. The leg voltage during DC fault will be $= 2N_sV_c$. For modulation index of 1, DC fault blocking capability is given as follows:

$$2N_s V_c \geq \frac{\sqrt{3}}{2} V_{dc} \qquad (2)$$

Substituting for Vdc from (1)

$$N_s \geq \frac{\sqrt{3}}{4} N \qquad (3)$$

which gives $N_s \geq 0.5N$.

The number of fault-blocking SMs in any mixed HMMC can be calculated using the above approach (Zeng et al., 2015). For SMs with two capacitors, each capacitor is assumed to have the same voltage stress of Vc. A comparison of the number of SMs and the device counts can be made for various mixed hybrid topologies which is a good indicator for a converter volume and cost. The calculations are discussed

further in 4 and the results have been shown in Fig. 12.

The time taken for the fault current to die out is dependent on the reverse voltage applied by the SMs during the blocked stage. 5LCCSM, SCDSM, ACTSM, and M-ANPC-SM have a reverse voltage $2V_c$ because the two capacitors in the SM get series connected in the blocked state. So, the DC fault current decays much faster compared to using FBSM in the mixed HMMCs. On the other hand, in CDSM during DC faults, the two capacitors connect in parallel and apply just $V_c$ to the fault current and hence the fault current decay remains the same as the FBSM-based mixed HMMC.

The mixed HMMCs can operate in STATCOM mode during DC fault conditions. Under DC short circuit conditions, assuming the DC impedance to be negligible, the converter gets connected as a three-phase star-connected cascade-multilevel converter (CMC) (Al Hosani and Nguyen, 2018). The fault-tolerant SMs discussed above can produce bipolar voltage under the blocking state depending on the current direction. For a positive phase current the lower arm is blocked, and the SMs in the upper arm regulate the phase currents and the reactive power supplied to the grid. In the case of negative phase current, it is vice versa. The conducting and non-conducting arms for a scenario (ia>0; ib<0; ic<0) are shown in Fig. 5. In the conducting arm, all HBSMs are bypassed, the fault-blocking SMs are switched ON and controlled to produce the AC voltage, with the converter providing 1.0 p.u. of reactive power. In the case of bipolar fault-tolerant SMs, since bipolar voltage can be produced with either direction of phase current, the converter with these SMs produces 2.0 p.u. of reactive power (Nguyen et al., 2019).

The minimum number of SMs needed for STATCOM operation during DC-side SC fault can be calculated as follows. If there are $N_s$ fault blocking SMs, then during STATCOM mode the output voltage will have $N_s + 1$ levels. The maximum value of the fundamental component of the voltage generated in STATCOM mode has been calculated in Nguyen et al. (2019), Wu (2006) and Li et al. (2013b) as:

$$V_{max} = 0.816 N_s V_c \qquad (4)$$

To obtain full controllability of STATCOM operation during DC fault, this fundamental component should be higher than the grid voltage and is selected as (Li et al., 2013b):

$$V_{max} \geq 1.1 V_{lpk} \text{ OR, substitution from Eq. (4)} \qquad (4)$$

gives: $N_s V_c \geq 1.35 V_{lpk}$, where $V_{lpk}$ is the peak value of line-line AC grid voltage and under normal operation it is given by: $V_{lpk} = 1/2MV_{dc}$. Substituting for $V_c = V_{dc}/N$, where $V_c$ is the nominal capacitor voltage,
<figure><img src="image_7.png" /><figcaption>Fig. 5. Mixed HMMC for ia> 0; ib< 0; ic< 0.</figcaption></figure>

N is the total count of submodules in a HBSM-MMC, and M= 0.8, which is normally the maximum modulation index for mixed MMCs (Nguyen et al., 2019), the number of substituted SMs is given by:

$$N_s \geq 0.54N \qquad (5)$$

Taking this into account, the number of inserted SM has been taken as 0.6 N for calculating the total device count and devices count in the conduction path in 4.

The fault blocking capability of mixed HMMCs makes isolation of faulty part of the transmission system possible in multiterminal connections and also makes possibility of islanding. Since the semiconductor devices are switched off and the converter blocks the AC feed and the fault current of DC-side SC fault, the capacitor voltages are maintained. Once the fault clearance is detected, the switching signals are restored, and the converter can transition to normal operation smoothly.

## 2.3. Hybrid combination of MMC and two/three-level VSC

As previously mentioned, a notable drawback of Modular Multilevel Converters (MMCs) is the substantial space occupied by the capacitors, constituting 50 % of the total volume and 80 % of the total weight (Wang et al., 2023). Combining the simplicity of two/three-level Voltage Source Converters (VSCs) with the modularity and high efficiency inherent to MMCs gives rise to novel topologies such as Alternate Arm Converter (AAC), Hybrid Cascaded Converters (Merlin et al., 2014; Li et al., 2015b) and Hybrid Leg converters (Liu and Dong, 2022). These innovative configurations not only minimize the energy storage requirement in the converter but also reduce the overall number of SMs, thus significantly reducing the total volume required for capacitors. Consequently, this approach results in a notable enhancement in the power density of the converter. The different topologies of this hybrid approach are discussed below.

<figure><img src="image_8.png" /><figcaption>Fig. 6. (a) Alternate Arm Converter (AAC) (b) Flying capacitor AAC(FC-AAC).</figcaption></figure>
## 2.3.1. Alternate Arm Converter

The Alternate Arm Converter (AAC) introduced in Merlin et al. (2014), also known as Standard-Original-AAC (SO-AAC), is constructed by combining two-level VSC, called Director Switches (DS), and MMC as shown in Fig. 6(a). The upper arm of a leg conducts during the positive cycle of voltage and the bottom arm for the negative cycle with the help of the DSs. Since each arm constructs only half the cycle of the AC voltage, the stack produces half of the DC bus voltage. Thus, the arm rating of AAC is half of that of the arm of MMC which means fewer devices are needed to produce the same output as that of HB-MMC. Even though the DSs constitutes a stack of IGBTs, the total IGBT count remains smaller than the FB-MMC device count.

To keep the energy of the stacks close to the nominal value, the converter is operated to keep the net energy change over half cycle close to zero. By equating the energies of the DC and AC sides, the operating point of the converter is determined and has been shown in Merlin et al. (2014) as and is called the “sweet spot” of the converter (Wickramasinghe et al., 2019).

$$V_{ac_{pk}} = \frac{2}{\pi}V_{dc} \qquad (6)$$

This narrows the operating range of the converter. Another drawback of this converter is that the switching of the DSs generates sixth harmonics on the DC side which requires DC side filters for smooth output (Najmi et al., 2015). The need for extra capacitors compensates for the advantage of smaller SM capacitor sizes. The remediation to the above problems is given by extending the overlap period during DS switching by introducing improved Extended Overlap AAC (EO-AAC) in Merlin et al. (2018) and Liu et al. (2019). It improves SO-AAC by expanding the operating range by increasing the overlap angle and eliminating the need for a DC side filter but at the cost of more SMs. However, this configuration offers smaller device losses and reduced energy requirements compared to an FB-MMC, as will be demonstrated by the calculations in 6. Authors in Vozikis et al. (2018) proposes an improved SO-AAC by placing a Flying Capacitor (FC) across the DSs as depicted in Fig. 6(b), that eliminates the sixth harmonics and the need for a DC side filter.

**DC Fault Operation and STATCOM Mode:** Since the FBSMs in the arms of the AAC always work in over-modulation mode, its AC voltage, during normal operation, is higher than the DC voltage. Thus, during the DC-side SC fault, the stack has enough SMs to provide a reverse bias to the AC grid voltage and prevent AC-side feed. FBSMs in the arms are fault tolerant and remain operational during the DC-side SC fault and hence can work as a STATCOM to provide reactive power to the AC grid. The DSs can be controlled in different ways to work like one arm per half cycle as in the normal operation producing 1.0 p.u. reactive power, or one arm/two arms continuously increasing the reactive power to 2.0 p.u (Merlin et al., 2014). The FRT and STATCOM capability of this topology during DC-side SC faults helps the system stability just like mixed HMMCs.

## 2.3.2. Hybrid-Leg MMC

In Liu et al. (2021) the 3-level-Active-Neutral-Point converter (ANPC) integration with an MMC has been investigated in three unique configurations. Each pair of ANPC switches is individually substituted with chain link switches to create three different topologies. Though these configurations result in savings of approximately 30 % in devices, 50 % in total capacitors, and a 32 % reduction in power losses compared to the FB-MMC, they do not provide FRT, and the DC-side bus mutation capacitor limits its application. An improved approach to this has been presented in Liu and Dong (2022) creating a hybrid leg with a VSC in series with the chain link of HB-SMs as shown in Fig. 7. The VSC of the three upper legs and the three lower legs each have a common DC link capacitor, thus reducing the overall capacitor size. The VSCs are inserted when the arm voltage exceeds the VSC’s capacitor voltage. This greatly reduces the voltage handled by the chain link SMs and thus

<figure><img src="image_9.png" /><figcaption>Fig. 7. Hybrid-Leg-MMC with FRT circuit.</figcaption></figure>

reduces the required number of SMs compared to FB-MMC. The VSC operates at line frequency, resulting in smaller switching losses than the FB-MMC.

**DC Fault Handling and STATCOM operation:** This topology inherently does not provide FRT. Extra devices are needed to make it FRT-capable. An RC network, along with a circuit breaker (the shaded area of Fig. 7), connected to the top and another to the bottom VSC, has been proposed in Liu and Dong (2022) to handle the DC fault current. Since the sub-modules are all HBSM, this topology cannot provide reactive power to the AC grid.

## 2.3.3. Hybrid cascaded converter

Hybrid Cascaded Multilevel converters (Adam et al., 2010, 2013a; Xue et al., 2012; Yang et al., 2015), combine a 2-Level-VSC with Full-Bridge SMs (FBSMs) where the VSC is connected to the DC side while the FBSMs to the AC side. The general topology of Hybrid Cascaded MMC has been shown in Fig. 8. The 2-Level-VSCs operate at the fundamental frequency switching between ±1/2 Vdc (Fig. 8). The cascaded FBSMs work as wave-shaping circuits (WSC), injecting harmonics to shape two-level waveforms of the VSCs. This topology puts DC-side capacitors back into the converter topology, the elimination of which was a great advantage of MMC.

The two-level VSC switches experience a high voltage stress resulting in high charging inrush currents after fault clearance. To address these drawbacks many alterations have been suggested in the literature. Replacing the two-level VSCs with HBSMs (Li et al., 2015b) is one of the options that reduces voltage stress on the high-voltage two-level switch side, eliminates the requirement of a DC side capacitor and reduces losses too. The author in Huang and Li (2022) has experimented with using HBSMs as two-level VSCs and a split-capacitor-SM (SpC-SM) instead of FBSMs, significantly lowering the conduction losses. Another approach involves increasing DS levels by combining a 3-Level-VSC (Bieber et al., 2020a) or a 5-Level-VSC (Bieber et al., 2023) with cascaded FBSMs. In these two combinations, the voltage stress across the cascaded chain links is reduced to $Vdc/4$ and $Vdc/8$ respectively which brings down the count of SMs.

**DC Fault Handling and STATCOM operation:** In the Hybrid Cascaded two-level-MMC (H2LC-MMC) (Adam et al., 2010, 2013a; Xue et al.,
<figure><img src="image_10.png" /><figcaption>Fig. 8. Topology of Hybrid Cascaded-MMC.</figcaption></figure>

2012), the cascaded FBSMs' capacitors are charged to Vdc/2 voltage per phase, effectively providing enough reverse bias to diodes to control DC fault current and prevent AC feed. The hybrid cascaded topology with HBSM as the two-level switch and Split-Capacitor SM as the cascaded bipolar chain link sub-module, retains the fault blocking and FRT capability of the initial topology. In the approach where VSC levels are increased, as the VSC levels increase, the capacitor voltages of the cascaded FBSMs decrease, rendering the converter incapable of providing DC fault protection and necessitating additional circuitry to protect the converter against DC fault current damage. In Bieber et al. (2020a), as previously mentioned, the Hybrid Cascaded-3Level-MMC (H3LC-MMC) has FBSMs' total capacitor voltage of Vdc/4, while in the Hybrid Cascade-5Level-MMC (H5LC-MMC) (Bieber et al., 2023) this voltage is Vdc/8, which are insufficient to block the AC side current feed into the fault. These two papers discuss two approaches in providing DC fault blocking to the converter: i) implementing an FBSM-based electronic DC circuit breaker (DCCB) and ii) a Bypass Thyristor Valve in conjunction with a Fast Mechanical Switch (FMS) respectively. Since the cascaded FBSM voltage is much smaller than the AC side voltage, it cannot provide reactive power to the AC grid during DC-side SC faults.

## 2.4. Hybrid arm converter

The MMCs face 87 % overvoltage during internal AC phase to ground faults, necessitating a 70 % higher rating of switches (Nami, 2015). This overvoltage is mainly due to the bipolar SMs connected to the grounding pole. A hybrid-arm design is proposed in a bipolar configuration having two converters with the HBSMs placed in the arms connected to the grounding pole, and the bipolar SMs (FBSMs here) are connected to the arm away from the grounding pole (Fig. 9(a)). The two converters are connected in series on the DC side and can be controlled independently. This arrangement reduces the over-voltage stress by 37 %. To reduce the semiconductor device losses, the work in Yu et al. (2017) replaces the

<figure><img src="image_11.png" /><figcaption>Fig. 9. (a) Hybrid-Arm-MMC topology (b) STATCOM mode of Positive Converter.</figcaption></figure>

FBSM with Unipolar FBSM. Hou et al. (2020) experiment with a Hybrid Arm topology using a Diagonal Bridge SM (DBSM) as the bipolar cell, and show that it can continue to transfer bulk power even when the voltage dips within a threshold value due to small DC-side faults. In Inwumoh et al. (2022), a Single-Clamped-SM replaces FBSMs in a Hybrid Arm MMC reducing device count and maintaining control simplicity.

DC Fault Handling and STATCOM operation. During a DC-side short circuit fault, the arms with fault-tolerant SMs are used to attenuate and block the DC-side SC fault current. The HBSMs in the arms connected to the ground pole form star-connected cascaded STATCOM (Hou et al., 2020; Inwumoh et al., 2022) and are controlled to work as wave-shaping circuits to control the lower arm currents and provide reactive power to the AC grid, as shown in Fig. 9(b).

## 3. Control techniques for HMMC

An offshore HVDC transmission system has two converters which connect the weak AC side produced by wind energy to the onshore ac grid. Converter one is on OSS which converts ac into HVDC, and the other is an inverter on onshore substation that connects the HVDC to the AC grid. The control requirements for this system can be broadly categorized into two types (Gharaghani and Asadi, 2023):

(i) External control: This manages the overall dynamics of the MMC, focusing on the independent control of active and reactive power exchanged between the AC and DC sides.

(ii) Internal control: This handles the internal dynamics of the MMC, including modulation strategies and the suppression of circulating currents.

Modern grid codes require that converters not only protect themselves from overvoltage and overcurrent during grid disturbances but also actively contribute to maintaining grid stability. AC-side and DC-side SC faults, frequency fluctuations and AC voltage stability are the typical grid side disturbances which HVDC converters are expected to handle. During onshore AC-side fault, the power flow between DC and
AC grid on onshore gets disrupted while offshore AC is still pumping power, and hence can cause the DC voltage to swell (Tavakoli et al., 2022). The high voltage can be detrimental for the converter devices and can cause the tripping of circuit breakers. The converter is expected to control the voltage swell and prevent the disconnection of the converter from the AC grid. When offshore AC-side fault occurs, the power input to DC grid becomes zero and causes the DC voltage to sag (Jing et al., 2018). The converter is expected to stay connected to the grid by maintaining the AC voltage and injecting reactive power till the fault is cleared within the voltage range of 0.5 p.u. and provide FRT if the voltage falls below it, as per grid code (Tavakoli et al., 2022). Various techniques have been suggested in literature to achieve this control (Shi et al., 2020; Kumar et al., 2024). For wind energy systems, converters are typically treated as VSCs for these control techniques, implying that these methods should also be transferable and applicable to HMMCs.

As discussed in 2, HMMCs are expected to provide FRT during DC-side SC faults by preventing AC-side current from feeding the DC fault. This is typically achieved through a passive DC FRT approach, where the converter's semiconductor devices are switched off. While effective for the onshore converter, this passive method results in a complete loss of control over AC-side quantities like voltage, current, and instantaneous active and reactive power. For the offshore converter, which connects to a weak AC system (such as one generated by offshore wind farms), this passive control can significantly impact the stability of the AC grid (Hu et al., 2016). Therefore, for offshore converters active DC FRT is implemented. In this approach all the devices are not switched off. The converter not only reduces the DC fault current to zero but also actively provides reactive power to the AC side by operating as a STATCOM to maintain grid stability. Both passive and active DC FRT methods have been discussed in detail in 2.

The internal control of HMMCs involves managing circulating currents through one of the three primary strategies (i) arm current control (ii) capacitor voltage balancing (iii) circulating current control. The specific implementation methods for these strategies vary depending on the particular HMMC topology and are discussed below.

In mixed HMMCs, the controller maintains the modulation index of the converter. During steady state conditions the modulation index of the converter is less than or close to one. Under these conditions, the FBSMs and HBSMs output only positive voltages, and the SM capacitor voltages are kept balanced by the sorting algorithm used for conventional MMCs (Gharaghani and Asadi, 2023; Rohner et al., 2010). The SM voltage imbalance between the HB and FB SMs appear when the HMMC is made to work with overmodulation to handle abnormal situations of reduced DC voltages (Xu et al., 2021). The overmodulation helps in reducing capacitor voltage ripple and can also be used to reduce the capacitor size of the converters (Zhang et al., 2022a). These voltage imbalances are addressed by injecting second order harmonics circulating current (SHCC) as suggested in Dong et al. (2019), Hu et al. (2019b) and Bandaru et al. (2020). These approaches are challenged by the calculation of optimum value of reference value of SHCC. The work in Zhang et al. (2022b) studies different voltage balancing states to identify the critical voltage balancing state. This voltage is used for generating the optimal reference current for SHCC. Further linearized modelling of optimal SHCC injection is used for parameter selection of PI controller. Another approach has been presented by Xu et al. (2021) where second and third harmonic circulating currents are injected to reduce the capacitor voltage fluctuation between the HB and FB submodules. During DC-side SC faults, the controller bypasses all the HBSMs and switches ON all the FBSMs to block the AC current feed into the DC-side fault. The negative voltage generated by FBSMs is used to supply the reactive power to the AC-side to maintain stability (Al Hosani and Nguyen, 2018). This leads to capacitor voltage imbalance between the FBSMs and HBSMs. Various techniques have been suggested in literature to maintain the balance of SM voltages in fault conditions. One method is to inject second order harmonic circulating currents as shown in Bandaru et al. (2020). The work by Xu et al. (2021) proposes dual

injection of second order circulating current and third harmonic voltages into the controller to maintain the SM capacitor voltages. During AC-side faults, which can lead to either DC voltage sag or swell as mentioned earlier in the section, the controller helps the converter to generate reactive power to feed the healthy AC side to maintain grid stability as discussed in Tavakoli et al. (2022).

The EO-AAC, is an improvement of SO-AAC to remove the ripple introduced by switching DSs and expand the small operating range of the converter (Sharifabadi et al., 2016). The controller tracks the phase current direction and provides a wider overlap during arm current transition. The improvement gives a wider range of operation but increases the number of SMs in the converter (Merlin et al., 2018). The ratio of SM to DS can be optimized and the controller can improve the energy balance of the capacitor voltages by addition of zero sequence triple harmonic components to the voltage waveforms as shown in Moreno et al. (2015). By making either one or two arms to work together during DC-side SC fault, the controller for EO-AAC can be set to provide 1.0 p.u. or 2.0 p.u. of reactive power (Merlin et al., 2014).

In hybrid 2/3 LC-MMCs, the arms are DS while the cascaded FBSMs work as wave shaping circuits. The work in Adam et al. (2013a) discusses the complex control techniques employed to convert the two level voltage output of arms into sinusoidal waves by selective harmonic elimination. Reference (Shi et al., 2018) evaluates different SM voltage regulation techniques for topology with HB-SMs as DSs. In three level hybrid cascaded topology the arms output three-level voltage waveforms. The author in Bieber et al. (2020a) shows how third-order harmonic voltages can be injected by the cascaded FBSMs to shape this voltage into sinusoidal voltage. Since the FBSMs are used only as active harmonic filters, the capacitor energy over one fundamental cycle remains constant. But due to semiconductor losses, the SM capacitor voltage may drift from the rated value and cause the net arm voltage to deviate. The work in Adam et al. (2013b) shows that by injecting a small fundamental frequency voltage the chain link capacitor energy balance can be maintained. All these tasks make the controller of this topology very complex. For HVDC, where the SM numbers are very high, this complexity multiplies.

In HA-MMC, the SMs in each arm are similar, hence the challenges of circulating current and voltage balancing are similar to conventional HB-MMC. The strategies applied to HB-MMC can be directly transplanted to HA-MMC (Yu et al., 2017).

The wind energy systems are low inertia systems, and this lowers the inertia of the grid. The low inertia causes a high rate of change in frequency and can lead to grid instability. Apart from the above-mentioned services, the converters are supposed to provide frequency control too, to maintain the stability of the grid. The internal stored energy can be used to increase system inertia in MMC, has been shown in Spallarossa et al. (2016). This internal energy can be used for frequency response control in MMC, and this has been shown by work in Kim et al. (2019). The number of levels of the MMC can be altered during frequency variations and the energy of the redundant SMs can be used to improve the frequency response of the converter. This proposed approach has been demonstrated in this work in context of Jeju Islands power grid of South Korea. Since the HVDC converters considered in this paper are for weak and low inertia AC system of wind energy, they are expected to be grid forming instead of grid following to maintain grid stability. Literature presents various other methods of increasing inertia in grid forming converters (Khan et al., 2022; Alshahrani et al., 2024) but these are not specific to a type of converter.

# 4. Comparison of hybrid modular multilevel converters based on various criteria

## 4.1. Comparison of device count and number of devices in the conduction path

Calculating the number of SMs and the total devices compares the
volume and cost of the converters, while the number of devices in the conduction path is a good indicator of their conduction loss. For a fair comparison between all the topologies, the DC bus voltage is standardized as $V_{DC}$ for all topologies. All the capacitors are assumed to have the same voltage stress $V_C$ across them, and it is assumed that the voltage rating of the IGBT switch is equal to the nominal capacitor voltage $V_C$. For HB-MMCs, the total number of SMs needed, $N$, is calculated as $N = V_{DC}/V_C$. The total number of SMs in other topologies is calculated based on this normalized value $N$. The calculations for various topologies are discussed below:

### 4.1.1. Mixed HMMC

For mixed HMMC configuration, the total SMs are calculated as $L + k * N_s = N$ where $L$ represents the number of monopolar SMs (such as HBSM or Modified-Active-Neutral-Point-Clamped-SM), $N_s$ is the number of substituted fault-blocking SMs, and $k$ signifies the number of capacitors per SM. To provide fault blocking capability to the MMC, $N_s \ge 0.5N$ and to enable the converter to work as STATCOM during DC-side SC fault $N_s \ge 0.54N$. The principles used for these calculations have been discussed in section II. Device count calculations for the various mixed HMMC configurations were done using $kN_s = 0.6N$. Per-phase device counts and number of devices in conduction path were calculated, and the results are shown in Fig. 10. Total device count gives a comparison of cost and volume, while the number of devices in conduction path is reflective of total losses. Amongst them, M-ANPC-RBSM has the least devices in the conduction path, but its total device count is very high.

Standard-Original (or sometimes referred to as Short Overlap) AAC (SO-AAC): For a short overlap, the stack voltage $V_{stack}$ (that is the voltage across the submodules in an arm) is rated for $V_{ac}$ and the DSs for $V_{dc}/2$. The total IGBTs can be calculated as (Merlin et al., 2014):

$$N_{igbt\_total} = 6 \left( 4 * \frac{2}{\pi} \frac{V_{dc}}{V_c} + \frac{V_{dc}}{2V_c} \right) = 18.28N \quad (7)$$

Extended-Overlap AAC (EO-AAC): the stacks, and the DSs are rated for 2/3 Vdc and the IGBT count can be calculated as (Merlin et al., 2018).

$$N_{igbt\_total} = 6 \left( 4 * \frac{2}{3} \frac{V_{dc}}{V_c} + \frac{2}{3} \frac{V_{dc}}{V_c} \right) = 6 * 3.33 = 20N \quad (8)$$

### 4.1.2. Hybrid-Leg-MMC (HL-MMC)
In HL-MMC, the HBSMs are rated at 0.7 $V_{dc}$ while the two-level VSC are rated for 0.5 $V_{dc}$ with DC fault protection. This is used to calculate the number of submodules and the number of IGBTs in the VSC stack (Liu and Dong, 2022).

<figure><img src="image_12.png" /><figcaption>Fig. 10. Comparison of various Mixed HMMCs.</figcaption></figure>

$$ 
\begin{aligned}
N_{igbt_{total}} &= 6 \left( 2 * \frac{V_{max\_cl}}{V_c} + 2 * \frac{V_{max\_vsc}}{V_c} \right) \\
&= 6 \left( 2 * \frac{0.7V_{dc}}{V_c} + 2 * \frac{0.5V_{dc}}{V_c} \right) \\
&= 6 * 2.4N = 14.4N \quad (9)
\end{aligned}
$$

### 4.1.2. Hybrid cascaded MMC

For Hybrid Cascaded topologies, the DS stack must withstand $V_{dc}/2$ whereas the FBSM chain links have the voltage of $V_{dc}/2$, $V_{dc}/4$, and $V_{dc}/8$ across them for H2LC-MMC, H3LC-MMC, and H5LC-MMC respectively. In H3LC-MMC the upper and lower leg DS stack is rated for $V_{dc}$, and the midpoint connected DS is rated for $V_{dc}/2$. In H5LC-MMC the upper and lower DS stacks are rated for $V_{dc}/2$, and the midpoint-connected DS is rated for $V_{dc}/4$. The IGBT count for H3LC-MMC and H5LC-MMC is calculated by Bieber et al. (2020a, 2023) as:

$$N_{igbt_{H3LC-MMC}} = 3 \left( 4 \frac{V_{FBSM}}{V_c} + 2 \frac{V_{DS,ul}}{V_c} + 2 \frac{V_{DS,m}}{V_c} \right) = 12N \quad (10)$$

$$N_{igbt_{H5LC-MMC}} = 3 \left( 4 \frac{V_{FBSM}}{V_c} + 4 \frac{V_{DS,ul}}{V_c} + 4 \frac{V_{DS,m}}{V_c} \right) = 10.5N \quad (11)$$

### 4.1.3. Hybrid arm MMC (HA-MMC)

Since the Hybrid arm is used for Bipolar MMC, two independently controlled MMCs are connected in series on the DC side with a voltage of $V_{dc}/2$. In the case of DBSM-Hybrid-arm topology, the DBSM arm is rated for $V_{dc}/2$ while the HBSM arm is rated for 2/3 Vdc (Hou et al., 2020). These values are used for calculating the number of SMs and devices accordingly.

All the different hybrid combinations of VSC and MMC have been compared in Fig. 11 on the basis of device count and devices in the conduction path. Increasing the levels of director switches (DS), as in H3LC-MMC and H5LC-MMC, does reduce the device count considerably, however, it doesn't impact the count of devices in the conduction path equally.

Fig. 12 compares all the topologies on the basis of their device count and the number of devices in the conduction path. The hybrid cascaded

<figure><img src="image_13.png" /><figcaption>Fig. 11. Comparison of various topologies of Hybrid combination of VSC and MMC.</figcaption></figure>
<figure><img src="image_14.png" /><figcaption>Fig. 12. Device Count comparison of various Hybrid MMCs.</figcaption></figure>

configurations have the lowest device counts, and this topology looks very promising in reducing footprint and losses. Hybrid arm has a high device count however, the devices in the conduction path are comparable to other hybrid combinations.

## 4.2. Comparison of STATCOM mode

In mixed HMMCs, the DC fault-blocking SMs can supply reactive power, but this mode has not been tested for some recently introduced mixed configurations. Fig. 10 compares the various mixed HMMCs on their device count and STATCOM mode where “0” denotes that the STATCOM mode is not possible. Table I classifies the HMMCs based on STATCOM mode during DC-side SC faults. In the Hybrid combination of VSC and MMC, STATCOM mode is not possible except for AAC where all the topologies e.g., SO-AAC, EO-AAC, and FC-AAC can work as STATCOM.

## 4.3. Comparison of DC side bus capacitor requirement

Integrating VSC and MMC introduces the requirement of a DC-side bus capacitor in some configurations. Table II lists the H MMC configurations based on DC-side bus capacitors. Using HBSM as the two-level switch eliminates the need for a DC-side capacitor in Hybrid-Cascaded topology. EO-AAC is another enhanced topology that eliminates the

<table><caption>**Table I**
Classification based on STATCOM mode during DC short circuit faults.</caption><thead><tr><th>Yes</th><th></th><th>No</th></tr></thead><tbody><tr><td>HBSM+FBSM (M)</td><td>SO-AAC & EO-AAC</td><td>Enhanced MMCs</td></tr><tr><td>HBSM+ UFBSM</td><td>&FC-AAC</td><td>MANPC+RBSM(M)</td></tr><tr><td>(M)</td><td>HA-MMC</td><td>MANPC+ACTSM(M)</td></tr><tr><td>HBSM+CDSM(M)</td><td>HL-MMC</td><td>HC-2L-MMC</td></tr><tr><td>HBSM+ 5LCCSM (M)</td><td></td><td>Hybrid Arm-Multiplexing MMC (HAM-MMC)</td></tr><tr><td>HBSM+SCDSM(M)</td><td></td><td>H3L-ANPC-MMC</td></tr><tr><td>HBSM+SwSM(M)</td><td></td><td></td></tr></tbody></table>

(M): Mixed HMMC Configuration

<table><caption>**Table II**
Topologies requiring DC Side Pole Capacitors.</caption><thead><tr><th>NO</th><th>YES</th><th></th></tr></thead><tbody><tr><td>Mixed HMMC family</td><td>SO-AAC & FC-AAC</td><td>H-3L-ANPC-MMC</td></tr><tr><td>EO-AAC</td><td>HC-3L-MMC</td><td>HC-2L-MMC</td></tr><tr><td>HC-HBSM-MMC</td><td>HC-5L-MMC</td><td>HLE-2L-MMC</td></tr><tr><td>HA-MMC</td><td></td><td></td></tr></tbody></table>

need for a DC-side bus capacitor compared to the original topology of SO-AAC and FC-AAC.

## 4.4. Comparison of device losses

The losses in the semiconductor devices are the conduction and switching losses. These losses for the various converter topologies can be calculated by the methods followed in Rohner et al. (2010), Allebrod et al. (2008) and Jones and Davidson (2013), where the semiconductor V-I characteristics and the instantaneous current flowing through the devices are used to calculate the conduction losses. The on-state characteristics of the devices are non-linear functions of the current flowing through them. Piece-wise linear approximation is used by Rohner et al. (2010), Allebrod et al. (2008) and Jones and Davidson (2013) to simplify the calculations of the conduction losses. In this paper, the instantaneous currents of the converters are calculated using time-based simulation of the detailed switching-based models of the converters. The device resistances $R_T$ and $R_D$, and the saturation voltages ($V_{C0}$ and $V_{D0}$), are obtained from the manufacturer's datasheet. The total conduction losses are calculated using the following equations:

$$P_{\text{conT}} = \frac{1}{T} \int_{t_0}^{t_0+T} i_c(\tau) (V_{T0} + R_T i_c(\tau)) d\tau \quad (12)$$

$$P_{\text{conD}} = \frac{1}{T} \int_{t_0}^{t_0+T} i_F(\tau) (V_{D0} + R_D i_c(\tau)) d\tau \quad (13)$$

where $P_{\text{conT}}$ and $P_{\text{conD}}$ are the conduction losses of the IGBT and diode
respectively and t₀ is the instant from when the waveforms are steady, and iₐ, iₚ are the IGBT and diode current respectively.

The exact switching losses require the switching transitions' counts and the switching energies' values per switching event. The switching losses can be approximated with good accuracy by using the energy loss data from the manufacturer's data sheet. For a given reference voltage, reference current, and maximum junction temperature the turn-on and turn-off energies (Eon, Eoff) of IGBT and recovery loss (Erec) of the diode are selected and used in Eqs. (14) and (15) to calculate the switching losses within one fundamental period (Rohner et al., 2010; Allebrod et al., 2008; Jones and Davidson, 2013).

$$P_{sw,T} \approx \frac{1}{T} \sum_{i=1}^{N_i} \left\{ \left[ \frac{v_{T,on}(t_i)}{v_{T,ref}} E_{on}(i_{c,ref}) + \frac{v_{T,off}(t_i)}{v_{T,ref}} E_{off}(i_{c,ref}) \right] \frac{i_c(t_i)}{i_{c,ref}} \right\} \quad (14)$$

$$P_{sw,D} \approx \frac{1}{T} \sum_{k=1}^{N_k} \left\{ \frac{v_{D,rec}(t_k)}{v_{D,ref}} \frac{i_P(k)}{i_{F,ref}} E_{rec}(i_{F,ref}) \right\} \quad (15)$$

where Psw,T and Psw,D are the switching losses of IGBT and diode respectively. The total losses can be calculated by summing the conduction and switching losses of the IGBT and diode and multiplying them by the number of devices. The losses are calculated for various converters with the same rating and the results are discussed in 6.

### 4.5. Comparison of Energy Storage Requirements

Capacitor size is crucial in determining the volume of the converter. Energy storage required in an arm, or stack, is obtained by finding the energy deviation, ΔE<sub>c</sub>, which can be numerically calculated by the cumulative integration of the power of the capacitors as (Ilves et al., 2014; Bieber et al., 2020b; Vermeersch et al., 2019; Merlin and Green, 2015):

$$\Delta E_C = \max \int_0^t V_c(\tau) i(\tau) d(\tau) - \min \int_0^t V_c(\tau) i(\tau) d(\tau) \quad (16)$$

The capacitances of the submodules and DC side capacitors can be found by using the calculated values of the energy deviations (Ilves et al., 2014). For a fair comparison between converters, the energy deviation is normalized by the frequency ω, and apparent power S, of the system, given by:

$$\Delta \bar{E}_C = \frac{\Delta E_C \omega}{S} \quad (17)$$

The normalized energy deviations ΔE<sub>c</sub>, of the various topologies were calculated by using the above equations in 6.

## 5. Techno-economic analysis of HMMCs

Techno-economic analysis of converter circuits involves analyzing cost of power loss, reliability, and redundancy. Reliability is very important in offshore substations where the annual maintenance schedule is quarterly or semi-annually, making SM redundancy crucial for reliability (Razani et al., 2019). Extra SMs add to the cost and losses of the converter. Since adding SMs increases converter cost and losses, optimizing the number of redundant devices and submodules is essential for balancing cost and reliability. An optimization technique for mixed HMMCs (HB and FB) demonstrates that the cost of a redundant FBSM is approximately three times that of an HBSM (Li et al., 2020b). Furthermore, reliability modeling for active redundancy in mixed HMMCs indicates a significant reliability increase (0.7-0.9 on a 0-1 scale) with redundant FBSMs, despite their higher cost (Xie et al., 2019). Existing techno-economic analyses for offshore wind farms using HVDC with HB-MMC converters (Hardy et al., 2019) show its cost-effectiveness over HVAC beyond 150 km offshore. Similar project-specific analyses are available for HVDC projects in Afghanistan (Ludin et al., 2022) and in China (Liang et al., 2023). A research gap exists regarding the reliability

cost analysis of HMMC topologies.

As HMMC topologies are yet to be implemented in offshore HVDC transmission projects, conducting techno-economic evaluations and direct cost comparisons for manufacturing, maintenance, and operation remains challenging.

China's Kun-Liu-Long project (Rao et al., 2022) is the first HVDC transmission project that uses hybrid MMCs, with 30% HBSMs and 70% FBSMs. Despite the project's onshore location and the use of Line-Commutated Converters (LCCs) at the end, the comprehensive operational experience and performance metrics gathered from this real-world deployment will be highly beneficial. This data can serve as a crucial foundation for more accurate and insightful economic analyses aimed at evaluating the feasibility and cost-effectiveness of utilizing hybrid MMCs in the context of future offshore HVDC transmission links.

## 6. Case study

For a fair comparison of devices' losses and energy storage requirements across all the topologies, switching-based models of converters with the same rating were constructed in MATLAB. The models examined were HB-MMC, FB-MMC, mixed Hybrid MMC (with 60% FBSM and 40% HBSM), EO-AAC, H2LC-MMC, H2-LHBC-MMC (Hybrid cascaded with HB as two-level switches), and H3LC-MMC. The converters were operated as inverters with a rating of 1000 MVA and a DC bus voltage of 1050 kV. The SM capacitor rating was taken as 15 kV. The WESTGATE 4.5 kV IGBT (IXYS, 2016) is used for the switches. Each switch consists of a series of connected IGBTs with the voltage stress on each IGBT as 2.5 kV. In the topologies where director switches are used, each IGBT is assumed to have a voltage stress of 2.5 kV.

(a) Device count, Loss and Efficiency Calculation: The methodology and equations discussed in 4 on device count calculation was used to calculate the device count for each of the topologies for the above-mentioned rating. For loss calculation only switching and conduction losses of the semiconductor devices have been considered. The instantaneous currents in the various converters, calculated by time domain analysis of switching-based models of converters were used to calculate the losses in the semiconductor devices as per the Eqs. (12-15) for a power factor of 1. Loss calculations were based on the following assumptions and simplifications (a) all MMCs operate with sinusoidal AC current, constant DC voltage and sinusoidal modulating signals (b) all SMs have the same nominal capacitor voltages (c) all MMCs operate at same rated power and power factor, same AC and DC voltages (d) the losses are equally distributed amongst the arms and legs, losses in each SMs are identical (e) the switching losses are linearly or piecewise linearly proportional to current (f) switching instances are evenly distributed over one fundamental cycle.

The power losses were estimated by calculating the voltage drops across the IGBTs and internal diodes by using polynomials approximations to the datasheet curves following the procedures detailed in Rohner et al. (2010) and Rodrigues et al. (2016). For the mixed HMMCs the mean and average currents over a cycle were used as per equations in (Jones and Davidson, 2013) to calculate the conduction and switching losses.

The device count, conduction and switching losses, and efficiency for the studied topologies are presented in Table III with total losses in ascending order. Fig. 13 compares the switching, conduction and total losses of these topologies.

The Mixed HMMC reduces the losses of FBSM-MMC from 13.34 MW to 11.22 MW which is a reduction by 16%. The hybrid combination of VSC and MMC offers a significant reduction in losses compared to mixed HMMCs. HL-MMC has the minimum losses of 3.9 MW after HB-MMC. This topology lacks FRT and STATCOM ability during DC-side SC just like HB-MMC. The second closest is EO-AAC and has a minimum loss of 8.8 MW. The Hybrid-2-level Cascaded topology has losses higher than the mixed HMMC, however, they are still lower than FB-MMC.

Replacing director switches with HBSM in Hybrid 2-Level-Half-
<table><caption>**Table III**
Loss and Efficiency of Studied Topologies.</caption><thead><tr><th>Converter Type</th><th>Device count (IGBTs)</th><th>Conduction Losses (MW)</th><th>Switching losses (MW)</th><th>Total Losses (MW)</th><th>Efficiency %</th></tr></thead><tbody><tr><td>HB MMC</td><td>5040</td><td>4.8</td><td>3.32</td><td>8.12</td><td>99.45</td></tr><tr><td>HL-MMC</td><td>4788</td><td>4.6</td><td>3.9</td><td>8.5</td><td>99.43</td></tr><tr><td>EO-AAC</td><td>8448</td><td>7.7</td><td>1.1</td><td>8.8</td><td>99.41</td></tr><tr><td>Mixed MMC</td><td>8064</td><td>7.9</td><td>3.32</td><td>11.22</td><td>99.25</td></tr><tr><td>H2LHBC-MMC</td><td>7488</td><td>6.6</td><td>4.52</td><td>11.44</td><td>99.24</td></tr><tr><td>H3LC_MMC</td><td>4788</td><td>7.43</td><td>2.97</td><td>10.45</td><td>99.37</td></tr><tr><td>H2LC-MMC</td><td>4968</td><td>7.23</td><td>4.52</td><td>11.75</td><td>99.23</td></tr><tr><td>FB MMC</td><td>10080</td><td>10.02</td><td>3.32</td><td>13.34</td><td>99.11</td></tr></tbody></table>

Bridge-Cascaded-MMC (H-2LHBC-MMC) reduces the losses and makes it comparable to H3LC-MMC. In the approach of increasing DS levels to lower the device losses, increasing level to three brings down the losses by 30 % to that of FB-MMC from 13.34 MW to 10.45 MW in H3LC-MMC.

(b) *Total Energy Storage Requirement Calculations:* The energy storage requirements of various topologies were calculated using equations (23–24) and the results were plotted for a modulation range of 0.5–0.63 and a power factor from 0 to 1. Fig. 14 shows the variation of the normalized energy deviation with the power factor and modulation index.

The results show that the hybrid combination of VSC and MMC reduces the energy deviations substantially. The capacitance for the capacitors of the converter is calculated using the worst-case scenario i.e. using the maximum energy deviation. The results on Fig. 14 show that the energy deviation for H2LC-MMC is the least and hence the capacitance for this topology will be the smallest. This indicates that H2LC helps reduce the volume of the conventional HB-MMC. The normalized energy requirements for unity p.f. for the studied topologies have been tabulated in Table IV with energy requirements in ascending order.

(c) *DC Short Circuit fault response:* Response time of mixed HMMC and FB-MMC were studied using their Simulink models in MATLAB. A 4 SM based FB-MMC inverter was constructed for a DC voltage of 640 kV DC connected to a 110 kV AC voltage grid. As per the minimum FBSM requirement to maintain fault blocking calculated in the work of Zeng et al. (2015) the number of FBSM should be greater than 50 % of total SMs, this MMC was converted to a mixed HMMC by replacing one SM by HBSM. A DC-side SC fault was created at 0.2 s. The switches were switched off after sensing the fault and were switched ON once the fault was cleared. The response of both the MMCs were recorded and are shown on Fig. 15. As per literature, the mixed HMMC is capable of attenuating and blocking DC-side SC current and takes longer time for the fault current to become zero as compared to FB-MMC.

## 7. Discussion, future trends, and research

As more wind energy and other renewable sources are integrated into the grid, its structure and requirements are changing. In future, HVDC will become a major part of the grid system, and handling DC-side SC faults will become crucial in grid stability and power availability. As mentioned earlier, as per new grid codes DC FRT and reactive power generation during DC-side SC fault have become essential features of the converters. Moreover, the offshore substation demands a converter with a small footprint, high efficiency, and energy density along with the other advantages of MMCs to reduce its own footprint.

To overcome the drawbacks of the conventional HB-MMC various hybrid topologies presented in literature were reviewed in this paper. Enhanced HB-MMCs are easiest to implement as they don't require any change in the control block of the converter. However, it does not provide STATCOM ability or help reduce converter volume and its losses are a little higher than HB-MMC as the enhancements have at least one switch that must remain ON during normal operation which increases device conduction losses.

Mixed HMMCs reduce losses and add FRT and STATCOM abilities during DC-side SC faults. Loss calculations in 6 show that mixed HMMC of FB+HB SMs reduces the device losses from 13.34 MW to 11.22 MW which are 16 % less than that of FB-MMC. These device losses can be reduced further by replacing FBSM with other fault-blocking SMs that offer lower device losses or have two capacitors in the SM which would require fewer HBSM replacements. Fig. 10 compares the various fault-blocking sub-modules in the literature used in mixed HMMCs. The total device count and the total devices in the conduction path give a qualitative comparison of their cost, volume, and conduction losses. Although, the recently introduced SMs, M-ANPC (Adam et al., 2017), RBSM (Yang et al., 2016) and ACT-SM (Hu et al., 2019a) used in Mixed HMMC configurations, have losses comparable to HB-MMC (Tian et al., 2021), their non-modular structure, due to the different voltage ratings of the capacitors and non-switching IGBTs, makes them unsuitable for offshore HVDC applications. The arm multiplexing technique suggested by Wang et al. (2023) reduce the SM count by 25 %. This approach can be investigated further by replacing FBSM with other fault-blocking SMs which help in further reducing the device count and losses. All the mixed HMMC topologies provide FRT and can work in STATCOM mode too, providing 1.0 p.u. or 2.0 p.u. of reactive power depending on the fault-blocking SM used as discussed in 2. The only drawback is that this topology does not help in the reduction of capacitor volume. But the work in Dong et al. (2018) has shown that by injecting third harmonic circulating currents in HB+FB HMMC, it can reduce capacitor voltage ripple and hence the size of the capacitor by 38 %.

The hybrid combination of 2/3/5 level VSC with MMC helps in capacitor volume reduction by count and size. Table III shows that EO-AAC device count reduces to 8448 from device count of FB-MMC which is 10080, resulting in loss reduction from 13.34 MW to 8.8 MW, which

<figure><img src="image_15.png" /><figcaption>Fig. 13. Loss comparison for various converter topologies.</figcaption></figure>
<figure><img src="image_16.png" /><figcaption>Fig. 14. Normalized Energy (kJω/MVA) for various topologies.</figcaption></figure>

<table><caption>**Table IV**
Energy requirements of studied topologies.</caption><thead><tr><td>Topology</td><td>Energy Requirement kJω/MVA</td></tr></thead><tbody><tr><td>H2LC-MMC</td><td>0.25</td></tr><tr><td>EO-AAC</td><td>1.3</td></tr><tr><td>H3LC_MMC</td><td>2</td></tr><tr><td>HB MMC</td><td>3.2</td></tr><tr><td>FB MMC</td><td>3.2</td></tr><tr><td>Mixed MMC</td><td>3.2</td></tr></tbody></table>

accounts for 34 % reduction. Table IV shows that the energy requirement of EO-AAC is 1.3 kJω/MVA which is much smaller than 3.2 kJω/MVA of HB-MMC indicating that the capacitor volume of EO-AAC will be much smaller. The drawback of this converter is that the switching of

DS introduces third harmonics on the DC side which necessitates the use of bulky filters and negates the advantage gained in capacitor volume reduction. The hybrid cascaded approach offers to solve this by using FBSMs as the cascaded chain link connected to the AC side, as harmonic filters. This approach removes the need for extra filters and can provide FRT. The device losses of Hybrid 2-Level-cascaded-MMC (H2LC-MMC) are a little higher than mixed HMMCs, however, the stored energy deviation calculations in Table IV of 6 show that the energy storage requirements are reduced significantly. One of the proposed approaches to reduce the device losses is to increase the levels of DS as in Hybrid 3-Level-cascaded-MMC (H3LC-MMC) (Bieber et al., 2020a) and Hybrid 5-Level-Cascaded-MMC (H5LC-MMC) (Bieber et al., 2023). With the increase in levels in DS, the voltage stress of cascaded chain links reduces to $Vdc/4$ and $Vdc/8$ respectively from $Vdc/2$ of H2LC-MMC. This reduces the required number of SMs in the cascaded chain links and

<figure><img src="image_17.png" /><figcaption>Fig. 15. DC-side Short Circuit Fault response (a) FB-MMC (b) Mixed HMMC.</figcaption></figure>
hence the losses. The calculations in Table III show that the total losses in H3LC-MMC are reduced to 10.45 MW from 13.34 MW total losses in FB-MMC. However, these higher levels of DS make the converter incapable of providing FRT and makes it dependent on external devices for protection. Another approach to reducing the losses in H2LC-MMC has been to replace the two level VSCs with HBSM. This brings down the losses to 11.44 MW which is comparable to H3LC-MMC and maintains the FRT in topology too. Replacing FBSM with spC-SM reduce the losses by 32 % to that of FB-MMC (Huang and Li, 2022). Despite their advantages of lower energy storage requirements and device losses than the FB-MMC, these hybrid-cascaded topologies lack STATCOM mode during DC-side SC faults. The spC-SM and FBSM are bipolar submodules which are capable of providing reactive power, but in this configuration they are incapable of providing reactive power to the AC grid. Future research can work on control techniques to provide STATCOM ability to the converter using these SMs in the chain links. Future work can also experiment with replacing the FBSM with other fault-blocking submodules which can help reduce further losses.

Hybrid Leg-MMC (Liu and Dong, 2022) is another way of integrating VSC and MMC where HBSMs have been used as a two-level switch and also as SMs in the arms. This configuration uses a single parallel capacitor for the three VSCs connected to the upper arm and helps reduce the number of capacitors and SMs in the converter arm. However, due to HB as the SMs, this topology cannot provide FRT and reactive power during DC faults. It will be worthwhile investigating this topology with other SMs replacing HBSM or having Mixed SMs that can provide the FRT and STATCOM ability to this topology.

The study in 6 is based on the switched model which does not capture the real behavior of devices. To validate and further confirm these predictions experimental validation through Hardware-in-the-LOOP (HIL) simulations or a physical prototype would be beneficial in future investigations. These methodologies will be helpful in observing the dynamic real-time behavior of the converter and help in capturing the real-time losses, thermal performance, and overall system efficiency of the converter.

Apart from calculating and comparing the power loss of the various HMMC topologies, assessing reliability of these converter topologies are essential. As mentioned in 5, redundancy of SMs and devices improves reliability but increases the cost and losses of the converter. Optimizing techniques for it have been presented in literature for mixed HMMC configurations but there is a gap in these studies for other HMMC topologies. Future work will aim to develop methodologies for reliability model for other HMMC topologies.

Scalability to large scale HVDC is another important aspect which is important in adaptation of these topologies. A fundamental advantage of MMCs is their modular structure. They are built by stacking numerous identical or similar submodules (SMs) in series within each arm. This allows for straightforward scaling of the converter voltage by simply adding more SMs. HMMC topologies are also built on the same principles and thus offer ease of scalability to higher voltages. As the number of submodules increases significantly in large-scale systems (potentially hundreds per arm), maintaining precise voltage balance across all SM capacitors becomes a highly complex and computationally intensive control task. Efficient and robust capacitor voltage balancing algorithms will be vital for stable operation and preventing component overstress. Real-time control of large HMMCs with thousands of switches will require immense computational power. As mentioned in 5, only mixed HMMCs have been implemented recently and that too in an onshore HVDC transmission. Future study and analysis of this project will be beneficial in identifying other practical real-time implementation challenges.

The implementation of HMMCs offers notable environmental and sustainability advantages crucial for large-scale HVDC transmission infrastructure. The inherent efficiency improvements, though seemingly small in percentage, translate into significant megawatt-level reductions in power losses. This reduction in losses directly contributes to less heat

generation within the converter, leading to a lower ambient working temperature for the devices. Consequently, components experience reduced thermal stress, which enhances their lifespan and reliability, ultimately decreasing the frequency of replacements and associated waste. A cooler operating environment also simplifies the cooling system design, consuming less auxiliary power and leading to a more compact converter footprint. This ability to reduce capacitor size and/or number, combined with simpler cooling, allows for a significantly smaller and more streamlined offshore substation. Such a compact and efficient design will not only reduce material consumption during construction and eases installation and maintenance but will also align directly with the goals of sustainable infrastructure development for offshore wind energy integration. As mentioned earlier, offshore wind energy systems are weak AC systems with low inertia rendering them susceptible to voltage and frequency fluctuations. Due to this, the necessity for maintaining grid stability and reliability with renewable energy integration with offshore wind farms has driven a fundamental shift in grid requirements and the subsequent revision of grid codes. Being weak AC systems with low inertia, renders offshore wind farms susceptible to substantial voltage and frequency fluctuations. As stated earlier, the revised grid codes have transferred the responsibility of dynamic grid support onto the power converters. Hybrid MMCs are being engineered to address these requirements. As mentioned in previous sections, the HMMC topologies that provide FRT and can work as STATCOM during DC and AC faults, help in improving the system stability and reliability. Since the capacitor voltages are maintained during FRT, after the fault is cleared, transitioning to normal operation happens smoothly by restoring the blocked gate pulses to the semiconductor devices. For an improved frequency response, it has been shown for conventional MMCs that system inertia can be increased by using the internal energy of redundant SMs. As mentioned in 3, other works have been presented in literature to increase inertia of grid forming converters. Most of these works assume either a two level VSC or conventional MMC. HMMC focused frequency response analysis is lacking in literature, and it will be essential for successful implementation of HMMC based HVDC transmission systems. Information and data from the recent sole HMMC project will help the engineers study and analyze the frequency response of HMMCs better.

AC and DC FRT and black start capabilities improve the resilience of the converters for HVDC but the complex control techniques and integration with smart grid make them more vulnerable to cyber threats. Sophisticated cybersecurity measures and well-defined incident response strategies will be needed to protect against an evolving threat landscape and ensure the reliable operation of HVDC transmission systems.

As per the literature survey, it is evident that an optimal solution has not been found yet. Mixed HMMCs offer device and loss reduction while providing the FRT and reactive power support during DC-side SC faults when compared to FB-MMCs. EO-AAC has low losses and provides FRT, but the control of this topology is very complex. The overlap period, which improves working range of the converter, adds instability to the converter. The work in Jiang et al. (2022) shows that larger the overlap period higher the instability of AAC. Hybrid cascaded topology offers lower losses and footprint. The cascaded SMs which act like harmonic filters need complex control. As the number of SMs increase with higher voltages, the complexity increases. Three or Five level hybrid cascaded topologies tend to reduce the SM count of the chain links but at the cost of FRT. Moreover, this topology cannot provide reactive power.

Mixed HMMC has emerged as the most optimum solution as of now. It can attenuate and mitigate DC-side SC fault current as shown in Fig. 15. Future research work can explore mixed HMMC combinations with novel SM introduced as in Wang et al. (2019), Mao et al. (2023) and Xue et al. (2017) and help in reducing the losses further. Technological advancements have been working at replacing the conventional semiconductor devices with wide bandgap semiconductor power devices (Athwer and Darwish, 2023) which offer lower losses and size. Future
advanced control techniques can help in reducing capacitor voltage ripple impacting the overall capacitor sizes (Li et al., 2022). Other hybrid MMCs are promising too. Technological advancements which can improve their stability and reduce control complexity will be helpful in an easy adaptation into HVDC transmission system.

While the current study focuses on the technical performance of HMMCs, a critical area for future investigation is its economic viability, particularly in large-scale HVDC applications. Since these technologies are at a very nascent stage large scale offshore HVDC projects using HMMCs have not been implemented yet. As mentioned earlier there is only one mixed HMMC based implemented HVDC onshore transmission system i.e. China's Kun-Liu-Long project. It is relatively recent, and its data is not publicly available yet. With more projects implemented and public availability of data will help in economic analysis of various HMMC topologies. This will involve developing robust methodologies to estimate and compare capital, operational and maintenance costs. As mentioned earlier there is a gap in literature on techno-economic analysis of various HMMC topologies other than for mixed HMMCs. Future work will leverage emerging empirical data, coupled with detailed component-level cost modeling, to conduct a thorough techno-economic assessment. This will enable a more precise understanding of the break-even points and long-term financial advantages over conventional solutions.

## 8. Conclusion

This work has presented the different hybrid MMC combinations investigated in the literature, highlighting their advantages and drawbacks and the features that need further investigation. No converter has been proposed yet which has losses closer to HB-MMC, provides FRT and STATCOM ability, and has a smaller footprint than classical MMC. As shown in Table III, mixed HHMCs reduce the device count to 8064 as compared to the device count of 10080 in FB-MMC. The losses of mixed MMC are reduced from 13.34 MW in FB-MMC to 11.24 MW. However, as Table III shows, mixed HMMCs converter's energy requirements remain at 3.2 kJω/MVA for HB-MMC and FB-MMC. Hence it has no effect on the capacitor size and the converter footprint. Arm-multiplexing topology has presented that mixed HMMCs can be constructed in another way too. The literature shows that this topology brings in a 25% reduction in SM count. This approach could be a topic of future research. The hybrid combinations of VSC and MMC have been tried in various ways, and they not only reduce the number of sub-modules which result in the reduction of devices and their losses but also energy storage requirements which reduces the capacitor size. EO-AAC has total losses of 8.8 MW as compared to 13.34 MW of FB-MMC, while its energy requirements are reduced to 1.3 kJω/MVA from 3.2 kJω/MVA of FB-MMC. This makes it a perfect choice, but it needs extra filters on the DC side and also becomes unstable with increase in overlap period which outweighs its advantages as of now. Another way of combining VSC and MMC has been used in hybrid-cascaded topologies which do not need any filters to improve their output quality. H2LC-MMC has significantly lower energy storage requirements, at 0.25 kJω/MVA, and provides FRT but has losses at around 11.75 MW, which is higher than mixed HMMCs with losses at 11.22 MW. H3LC-MMC brings down the device losses to 10.54 MW but does not have the FRT capability. The losses of H2LC-MMC can be reduced by replacing the two-level VSC with HBSMs which helps in retaining the FRT of the converter. The VSC-MMC hybrid combination is done differently in hybrid-leg-MMC topology which provides reduced device losses and capacitor volume but cannot provide FRT and STATCOM mode. The review indicates that Hybrid combinations of VSC and MMC are emerging as an attractive solution due to their reduced losses and energy storage requirements. Future works can investigate techniques that can provide FRT and STATCOM ability during DC-side SC faults while keeping their footprints and energy requirements smaller. At present, mixed HMMC offer the best trade-off between losses and FRT

and STATCOM capabilities. Innovations in advanced control techniques and algorithms which could help reduce capacitor size or maintain capacitor voltage balance or reduce complexity will promote implementation of these HMMCs in real world. Another research path could be to find other ways of combining VSC and MMC that provides the best trade-off between all the desired qualities of the converter.

## CRediT authorship contribution statement

**Akhyurna Swain:** Writing – review & editing. **Abdellatif Elmouattamid:** Writing – review & editing. **Raj Ratna Deep:** Writing – review & editing, Writing – original draft, Visualization, Software, Methodology, Investigation, Conceptualization. **Philip W.T. Pong:** Writing – review & editing, Supervision, Project administration, Funding acquisition.

## Funding

This work was supported by “ASCENT: From sensors to digital twin to autonomous operation of resilient power grids”, NSF grant #2328241; “New Jersey Offshore Wind Training and Research Institute” (NJOWTRI), New Jersey Economic Development (NJEDA) grant #.00089196-NJOWTRI, and “Professional Offshore Wind Energy Certificate Program” POWERCERTS NJEDA grant.

## Declaration of Competing Interest

The authors declare the following financial interests/personal relationships which may be considered as potential competing interests: Dr Philip Pong reports article publishing charges was provided by National Science Foundation. If there are other authors, they declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper

## Appendix A. Supporting information

Supplementary data associated with this article can be found in the online version at doi:10.1016/j.egyr.2025.07.017.

## Data availability

No data was used for the research described in the article.

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