# Warpage study by employing an advanced simulation methodology for assessing chip package interaction effects

Jun-Ho Choy, Stéphane Moreau, Catherine Brunet-Manquat, Valeriy Sukharev, Armen Kteyan

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## ► To cite this version:

Jun-Ho Choy, Stéphane Moreau, Catherine Brunet-Manquat, Valeriy Sukharev, Armen Kteyan. Warpage study by employing an advanced simulation methodology for assessing chip package interaction effects. ISPD '24 - International Symposium on Physical Design, Mar 2024, Taipei, Taiwan. pp.85-90, 10.1145/3626184.3635284. cea-04521903

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Distributed under a Creative Commons Attribution 4.0 International License
# Warpage Study by Employing an Advanced Simulation Methodology for Assessing Chip Package Interaction Effects

Jun-Ho Choy†

D2S, Siemens EDA

Fremont, CA, USA

junho.choy@siemens.com

Stéphane Moreau

Univ. Grenoble Alpes, CEA, Leti

Grenoble, France

stephane-nico.moreau@cea.fr

Catherine Brunet-Manquat

Univ. Grenoble Alpes, CEA, Leti

Grenoble, France

catherine.brunet-manquat@cea.fr

Valeriy Sukharev

D2S, Siemens EDA

Fremont, CA, USA

valeriy.sukharev@siemens.com

Armen Kteyan

D2S, Siemens EDA

Yerevan, Armenia

armen.kteyan@siemens.com

## ABSTRACT

A physics-based multi-scale simulation methodology that analyses die stress variations generated by package fabrication is employed for warpage study. The methodology combines coordinate-dependent anisotropic effective properties extractor with finite element analysis (FEA) engine, and computes mechanical stress globally on a package-scale, as well as locally on a feature-scale. For the purpose of mechanical failure analysis in the early stage of a package design, the warpage measurements were used for the tool's calibration. The warpage measurements on printed circuit board (PCB), interposer and chiplet samples, during heating and subsequent cooling, were employed for calibrating the model parameters. The warpage simulation results on full package represented by PCB-interposer-chiplets stack demonstrate the overall good agreement with measurement profile. Performed study demonstrates that the developed electronic design automation (EDA) tool and methodology can be used for accurate warpage prediction in different types of IC stacks at early stage of package design.

## CCS CONCEPTS

* Hardware-Electronic design automation~Methodologies for EDA~Software tools for EDA

## KEYWORDS

Chip-package interaction; finite element analysis; thermomechanical stress; chiplet; warpage

<figure><img src="image_3.png" /></figure>

This work is licensed under a Creative Commons Attribution International 4.0 License.

## ACM Reference Format:

Jun-Ho Choy, Stéphane Moreau, Catherine Brunet-Manquat, Valeriy Sukharev, Armen Kteyan. 2024. Warpage Study by Employing an Advanced Simulation Methodology for Assessing Chip Package Interaction Effects. In *Proceedings of the 2024 International Symposium on Physical Design (ISPD '24), March 12-15, 2024, Taipei, Taiwan*. ACM, New York, NY, USA. 6 pages. https://doi.org/10.1145/3626184.3635284

## 1 INTRODUCTION

Latest advancements in technology have created demand for higher performance and compact electronic devices, which has led to the growing demand for increasing functionality, and density. For these needs, the technology of multi-stacking of IC chips, namely 3D stacking, emerges as a solution and is driving the need for thinned substrates, as well as new interconnects such as, copper pillars, TSVs (through Silicon Vias) or hybrid bonding. These structures may cause thermomechanical stress that originates from high temperature die packaging step due to mismatch in thermomechanical properties between die and package materials, which is termed as chip package interaction (CPI). Copper pillars, TSVs, die edges may induce mechanical stress locally. On a global scale, thinned dies and substrate packages can increase thermomechanical stress. CPI-induced stress may generate unexpected variations in device performance and reliability problems. The stress effect on device performance is referred here as electrical CPI (eCPI). Here, CPI-induced stress can shift carrier mobility, which changes parameters of devices, and results in parametric failure of circuits. We have previously reported the development of a physics-based multi-scale EDA tool that determines across die stress variations that are caused by 3D package fabrication, by employing a multi-scale simulation methodology that resolves down to the order of a layout feature size [1-3]. The tool's eCPI analysis capabilities have been demonstrated in [3] that includes a two step multi-scale stress analysis, a SPICE netlist back annotation of the obtained stress components for accurate circuit simulation. It was also demonstrated that the tool can be calibrated against electrical
measurements. Another known effect of stress on chip reliability is related to fracture in interconnects - we call it mechanical CPI (mCPI). As an example, stress can cause cracking in ultra-low k (ULK), or extreme-low k (ELK) dielectrics that are adopted for reducing interconnect delay, but have deteriorated mechanical properties due to incorporation of porosity [4]. The other issue is the out of plane displacement, or warpage, which is a growing concern as dies and package substrates tend to become thinner in order to improve electrical performances. In addition, the in-plane size tends to be wider particularly for high performance computing applications, which is a clear risk in term of warpage [5]. A study shows that severe warpage may cause problems in the manufacturability of IC packages, and can degrade reliability of devices and circuits [6].

For predicting and analyzing warpage, FEA has been widely used. To improve the accuracy of the warpage simulation on a substrate, many studies have tried to include the layout effects of metal patterns, whose thermomechanical properties are quite different from those of insulators. The layout-induced effects include metal's non-uniform distribution as well as anisotropy, which may influence warpage behavior differently [6-7]. However, these warpage studies were mainly focused on package substrate block alone, and did not extend to a die-substrate stack structure, in which CPI induced stress effects on a die can be analyzed. To expand the usage of our tool to mCPI issues, we now apply our CPI stress analysis tool to the study of warpage that is observed in a package stack. One of the obstacles is the tool calibration procedure. Unlike the tool's earlier practice that has been successfully done for eCPI analysis, the tool calibration on the electrical measurements may not be available, as it is performed at early, or pre-design stage during process development. Therefore, the tool calibration must be done with an alternative measurement.

In the present study, a possibility to perform the tool calibration against warpage of a package and a die is demonstrated. To optimize the model parameters, the simulation results were compared with experimental measurements on INTACT 3D package that consists of six chiplets on top of an active silicon interposer [8]. In the next sections, the warpage measurement samples, and measurement procedure will be briefly described, which will be followed by tool calibration and warpage simulation procedures: the altitude measurements are collected on individual package blocks, such as PCB, and a chiplet while heating and cooling, and are employed for the tool calibration. Once the calibration is complete, the tool's warpage prediction on fully stacked sample is made, and compared with altitude measurements.

## 2 TEST SAMPLE DESCRIPTION

The analyzed multi die stack, INTACT is designed with a chiplet-based 3D technology for high performance computing. The detailed description can be found in [8]. The package consists of the following three main layers:

- six identical chiplets with 28 nm technology,

- active interposer with TSVs, based on 65 nm technology, and,

- PCB.

There are bump layers between each chiplet and interposer, and interposer and PCB. The image of the test sample package and the die stack are shown in Figure 1.

<figure><img src="image_4.png" /><figcaption>Figure 1: (a) Test package for warpage experiment. (b) Schematic of INTACT package die stack [8].</figcaption></figure>

## 3 WARPAGE MEASUREMENTS

The warpage is measured by Altisurf © 520 (Altimet) with a hot plate that is an add-on feature. For altitude, or height measurements, a free-standing sample is put on a hot plate. Then the height of the top surface is measured at pre-selected temperatures during heating, and subsequent cooling. For post processing of the measurements, Gaussian filtering is employed. The measurement procedure was repeated on (1) PCB without ball grids and bumps, (2) chiplet without bumps, and (3) full stack package with face-down chiplets. The employed measurement grid sizes are (dx, dy) = (1, 50) µm for the chiplet sample, (1, 200) µm for PCB, and (1, 1000) µm for full stack package. At room temperature, the measurement uncertainty can be up to ±2 µm. The uncertainty can increase to ±5 µm when temperature increase up to 200 °C.

Figure 2 displays the 3-dimensional height profile that were measured on a full stack sample at room temperature, where the peaks for 2 x 3 array of chiplets and passive devices are shown. In a separate measurement, Figure 3 shows the height profiles on a chiplet BEoL (back-end of line) surface at room temperature. The 2-dimensional map pattern in (a) represents the copper pillar layer, as these pillars of individual diameter of ~10 µm, are exposed to air without underfill. The 1-dimensional height profiles across two diagonal directions are displayed in (b). The height profile for the two curves virtually match well, even though the local pattern may differ in some regions.

<figure><img src="image_5.png" /><figcaption>Figure 2: Measured surface height on a full stack structure at room temperature.</figcaption></figure>
<figure><img src="image_6.png" /><figcaption>Figure 3: Measured height on a chiplet BEOL surface at room temperature: (a) 2-dimensional height map, (b) 1-dimensional profiles along two diagonal directions.</figcaption></figure>

<caption>Figure 4: Tool flow for warpage simulation.</caption>

## 4 SIMULATION MODEL

Developed FEA tool has a capability to simulate strain/stress fields everywhere in the stack, which are generated by:

- high temperature package assembly process,

- non-uniform temperature distribution during chip's operation condition, with inputs from chip power management tool, and,

- externally applied force under the setting of four-point package bending test, a popular method for the device model calibration and validation by measurements of deterministic mechanical strain-induced variations in device characteristics [3], and for package reliability experiments and simulations [9-10].

Prior to running FEA for stress calculation, the tool extracts material properties of composite-like blocks included in the package (BEOL interconnect, bump layer). The anisotropic effective material properties extractor (EMP) employs the rules of mixtures from the theory of anisotropic composite materials [11], and adopts a bin-based approach. Each layer of a die or a substrate is divided into square bins. The bin size is user-defined, and needs to be as small as the feature size to be analyzed. The layout processor identifies the metal objects within each bin, and calculates area density. Then the density-dependent effective properties are calculated for each bin. The anisotropy is also considered by taking metal routing directions into account [3]. The EMP extractor eliminates the detailed geometry building in FEA, reduces memory consumption, and greatly enhances the performance [2]. In one of the FEA runs on chiplet, the virtual memory size was 3 giga bytes.

In the present study, the tool was employed for simulating warpage phenomena that is caused by thermo-mechanical stress due to temperature gap between temperature to be analyzed, and the highest uniform temperature the sample has undergone during package assembly process, such as solder reflow. At this highest temperature, the sample is considered to reach at stress-free state. The tool flow is shown in figure 4, in which the simulation is performed on a package-scale.

The schematic of model package structure for simulation is displayed in figure 5. PCB is represented by a three layer block: a thick core layer consisting of fiber-polymer composite separates top and bottom layers in which multi-level copper lines exist [6]. Both interposer and chiplets consist of two layers – silicon (or Si/TSV) and BEOL. For each of these layers, EMP extracts uniform smeared properties. Table 1 summarizes the extraction results of averaged, or smeared properties, which will be refined during calibration.

<figure><img src="image_7.png" /><figcaption>Figure 5: Package structure employed in the simulation.</figcaption></figure>

<table><caption>Table 1: Layer initial properties employed for simulation. *E* is Young's modulus, *α* is coefficient of thermal expansion, and *ν* is Poisson ratio. Anisotropic properties are represented by three (x, y, z) components.</caption><thead><tr><th>Block</th><th>Layer</th><th>(E<sub>xx</sub>, E<sub>yy</sub>, E<sub>zz</sub>) [GPa]</th><th>(α<sub>xx</sub>, α<sub>yy</sub>, α<sub>zz</sub>) x10<sup>-6</sup></th><th>(ν<sub>xx</sub>, ν<sub>yy</sub>, ν<sub>zz</sub>)</th></tr></thead><tbody><tr><td rowspan="3">chiplet</td><td>Si</td><td>148</td><td>2.60</td><td>0.23</td></tr><tr><td>inter</td><td>(113, 113, 115)</td><td>(6.89, 6.91, 7.14)</td><td>0.30</td></tr><tr><td>inter</td><td>109</td><td>(2.40, 2.49, 2.55)</td><td>0.28</td></tr><tr><td rowspan="2">Interposer</td><td>Si/TSV</td><td>148</td><td>2.64</td><td>0.23</td></tr><tr><td>inter Top</td><td>(18, 18, 11)</td><td>(37.48, 37.48, 35.42)</td><td>(0.32, 0.24, 0.24)</td></tr><tr><td rowspan="2">PCB</td><td>Core</td><td>33</td><td>(6.00, 6.00, 12.00)</td><td>0.30</td></tr><tr><td>inter Bottom</td><td>(23, 23, 15)</td><td>(34.13, 34.13, 32.67)</td><td>(0.32, 0.23, 0.23)</td></tr></tbody></table>

## 5 TOOL CALIBRATION

### 5.1 PCB Sample

The properties of PCB are further refined by calibrating against warpage measurements that were made on PCB alone structure. Figure 6(a) summarizes the measured warpage value, ΔZ, that is defined as the height different between center and edge locations,
along the two diagonal directions, during heating up to 150 °C, and then subsequent cooling. For both directions, ΔZ profiles are similar during heating and cooling, which allows us to collect all data points for each temperature, and obtain linear regression curve fit for measurements. The resulted linear curve is shown in (b), together with error bars. The figure also demonstrates the good fit between the measurements and simulation results after adjusting parameters.

<figure><img src="image_8.png" /><figcaption>Figure 6: (a) Measured warpage, $\Delta Z = Z_{center} - Z_{edge}$, across two diagonal directions during heating and cooling. See Figure 3 for two different directions, “diag”, and “diag2”. For each direction, two samples are measured, and numbered as “_1”, and “_2”. (b) Linear regression curve showing average measured $\Delta Z$ as a function of temperature. After parameters adjustment, simulated warpage values provide good agreement with average measured values. Here, the measurements are represented by the error bars at each temperature.</figcaption></figure>

## 5.2 Chiplet Sample

For chiplet alone sample without µ-bumps, the measurements were made on BEOL top surface. The sample's planar dimension is 6 x 4 mm² with a thickness ~600 µm silicon substrate. The calibration procedure that was performed for PCB is repeated here to obtain the linear regression curve fit for measured $\Delta Z$. Then the simulated warpage values are compared against the obtained curve. As shown in figure 7, good agreement between simulated and measured warpage values was obtained.

<figure><img src="image_9.png" /><figcaption>Figure 7: Linear regression by employing measured warpage across two diagonal directions during heating and cooling on chiplet's BEOL surface. After parameters adjustment, simulated warpage values provide good agreement with average measured values.</figcaption></figure>

So far in the calibration, individual copper pillars on top surface have not been resolved. The effects of the local pattern can easily be incorporated in simulation, by employing an EMP bin size that is small enough to resolve individual copper pillar. Then the pillar height is added in addition to the local height when the pillar is present. The effects of adding local pattern can be seen in figures 8-9. In figure 8 (a-c), the simulated 2D height map on chiplet BEOL surface without resolving copper pillars, and with resolved copper pillars at T=150 °C are compared with measured 2D height map. With resolved copper pillars, the simulated and measured maps are in good agreement. 1D measurement profile across diagonal direction is also compared with simulation results without resolving copper pillars in (d), and with resolved copper pillars in (e), where the central region showing micro-scale peaks corresponds to copper pillar pattern. Similarly, the results for 350 °C are depicted in figure 9. Here, the baseline warpage shape exhibits convex, as opposed to concave at lower temperature results as shown in figure 8. For the parameter calibration for interposer, the warpage data available in an earlier report has been used [8].

<figure><img src="image_10.png" /><figcaption>Figure 8: Simulated 2D height map on chiplet BEOL surface (a) without resolving copper pillars, and (b) with resolved copper pillars at T=150 °C. (c) Measured 2D height map. (Max, Min) of color bar scale is (4.9, 5.8) for (a), (-5, 7) for (b), and (-10, 4) for (c) in µm. 1D measurement profile across diagonal direction is compared with simulation results (d) without resolving copper pillars, and (e) with resolved copper pillars.</figcaption></figure>
<figure><img src="image_11.png" /><figcaption>Figure 9: Simulated 2D height map on chiplet BEOL surface (a) without resolving copper pillars, and (b) with resolved copper pillars at T=350 °C. (c) Measured 2D height map. (Max, Min) of color bar scale is (4.2, 5.2) for (a), (0, 7) for (b), and (-5, 5) for (c) in µm. 1D measurement profile across diagonal direction is compared with simulation results (d) without resolving copper pillars, and (e) with resolved copper pillars.</figcaption></figure>

## 6 WARPAGE PREDICTION ON FULL PACKAGE STACK

The calibrated parameters are now employed to simulate the surface profile on a full stack package. For this sample, the measurements are available only at room temperature. Temperature gap of -205 °C is employed by taking highest uniform die attach temperature of 230 °C by thermo-compression. [8] We compare our simulated top surface 1D profiles along horizontal, and vertical cutlines in figure 10. Both along the horizontal cutline in (a), and vertical cutline in (b), the simulation curves agree well within the measurement error. In (b), the chiplet width in measurement looks smaller, as the measurement grid is coarse along this direction, and therefore, develops sloped regions on sidewalls that are not drawn in the figure.

<figure><img src="image_12.png" /><figcaption>Figure 10: 1D profile along (a) horizontal cutline, and (b) vertical cutline, on a full stack package at room temperature. Simulation results are compared with measurements. Measurement uncertainty of ±2 µm is indicated as the error bars.</figcaption></figure>

In order to further improve the difference between the simulated and measured profiles along horizontal cutline, the following additional set of simulations have been performed.

(1) Initial strain: Each FEA stress calculation takes input temperature gap, which is the difference between highest package assembly process temperature, and room temperature, or temperature to be stress analyzed. Each component in the package is considered stress-free at the highest package assembly process temperature, unless initial strain, or pre-existing strain is taken into account. One of the sources for the initial strain can be thermal history of a package component prior to assembly, so that this particular component may not maintain stress-free state at the highest package assembly process temperature. Such initial strain must be accurately estimated and taken into account, in order to improve the simulation accuracy. When the initial strain for each of the package components is supplied as an input, FEA can add the initial strain to the existing strain that is coming from the temperature gap, and obtains the final solution. In our additional simulation, the initial strain has been given to each component by providing different highest processing temperatures: -100 ~ 230 °C for PCB, 452 °C for interposer, 248 °C for chiplet. On all these sets of simulation results, it turns out that the chiplet's top surface curvature along the horizontal cutline did not reverse the sign.

(2) coupled transient thermal and stress simulations: In these simulations, we employed effective thermal properties to perform coupled transient thermal and stress simulations. The temperature-dependent bump properties [12] were employed in the simulation, in order to observe the time-dependent surface profile that could be close to measured surface curvature.

(3) plasticity of the solder joints: bump/underfill layers are assumed to deform plastically, in order to investigate if such plastic deformation could lead to the change in top surface profile of the chiplets. Here, deformation with perfect plasticity (no hardening) and linear hardening were assumed.

It was found that the effects of all these additional implementations were not significant for further improving the simulation profiles.

## 7 SUMMARY

The warpage measurements on PCB, and chiplet samples, during heating and subsequent cooling, were employed for calibrating the tool's model parameters. After calibration was completed for individual PCB and chiplet blocks, the tool predicts well the global temperature dependent warpage profile as well as local layout dependent surface profile. The warpage simulation results on full stack package demonstrate the overall good agreement with measurement profile when taking measurement error into account. Additional simulations were performed to investigate the effects of prior thermal history of individual package blocks, transient thermal effects, and plasticity of solder joints, on the warpage behavior of the full stack package. The simulation results reveal that these additional factors do not significantly change the height profile of the full stack package. The study demonstrates that the warpage measurements performed on the individual components of the stack can be employed for the tool calibration for mCPI
applications, and for the prediction of the warpages of different types of stacked IC packages on early steps of development.

## ACKNOWLEDGMENTS

This work was supported by the French National Research Agency (ANR) under the "Investissement d'avenir" programs: ANR 10-AIRT-0005 (IRT NANO-ELEC).

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