# Dual Coupled Inductor-Based Current-Fed Dual-Active-Bridge Converter

Armin Miremad, Suzan Eren

► To cite this version:

Armin Miremad, Suzan Eren. Dual Coupled Inductor-Based Current-Fed Dual-Active-Bridge Converter. The 26th European Conference on Power Electronics and Applications, GDR SEEDS France & EPE Association, Mar 2025, Paris, France. 10.34746/epe2025-0065. hal-05081803

HAL Id: hal-05081803

https://utc.hal.science/hal-05081803v1

Submitted on 23 May 2025

HAL is a multi-disciplinary open access
archive for the deposit and dissemination of sci-
entific research documents, whether they are pub-
lished or not. The documents may come from
teaching and research institutions in France or
abroad, or from public or private research centers.

L'archive ouverte pluridisciplinaire HAL, est
destinée au dépôt et à la diffusion de documents
scientifiques de niveau recherche, publiés ou non,
émanant des établissements d'enseignement et de
recherche français ou étrangers, des laboratoires
publics ou privés.

<figure><img src="image_1.png" /></figure>

Distributed under a Creative Commons Attribution 4.0 International License
# Dual Coupled Inductor-Based Current-Fed Dual-Active-Bridge
Converter

Armin Miremad, and Suzan Eren

Energy and Power Electronics Research (ePOWER) Group
Department of Electrical and Computer Engineering, Queen's University
Kingston, Canada

E-Mail: armin.miremad@queensu.ca, suzan.eren@queensu.ca

*Index Terms*—«Coupled inductor (CI)», «current-fed converter», «dual-active bridge (DAB) DC-DC converter», «photovoltaic (PV)», «ZVS Converters».

*Abstract*—This paper presents a dual coupled inductor current-fed DAB converter. The introduction of the CIs enhances power transfer capability, reduces the input current ripple and filter size, increases the voltage gain, and expands ZVS the region through proper circuit design. Experimental results are provided to validate the theoretical analysis and performance of the proposed converter.

<figure><img src="image_2.png" /><figcaption>Fig. 1: Configuration of a two-stage grid-connected PV microinverter system.</figcaption></figure>

## I. INTRODUCTION

The growing global demand for energy has intensified efforts to integrate renewable energy systems into power grids. Among these, Photovoltaic (PV) systems have emerged as a highly promising solution due to their clean and unlimited energy production capabilities [1]. The configuration of a two-stage grid-connected PV microinverter system is illustrated in Fig. 1. Given the inherent fluctuations in PV panel output voltage, there is a critical need for efficient and compact DC-DC converters to interface with the low-voltage PV side, extract the maximum power, and step up the low input voltage to supply the high-voltage dc-link of the second-stage inverter [2], [3].

A particularly effective solution to meet these requirements is DAB DC-DC converter, which has gained widespread adoption in recent years due to its high-frequency galvanic isolation and soft-switching capability. Despite these advantages, optimizing DAB converters to achieve high efficiency across the whole operation range, obtaining zero-voltage switching (ZVS) over a wide range of voltage conversion ratios and load conditions, and minimizing energy circulation remain challenging with conventional single phase-shift (SPS)

modulation [4], [5]. Ongoing research aimed at improving both the modulation techniques and the topological modification to improve the performance of DAB converters, especially when voltage conversion deviates from unity gain.

Current-fed DAB converters are emerging as a promising solution for renewable energy applications, offering significant benefits such as low input current ripple, high step-up ratios, and reduced transformer turn ratios [6]. These advantages make CF-DAB converters well-suited for PV applications as the ability to control the input current can effectively reduce the size of the input capacitor filter, enhance maximum power point tracking (MPPT) efficiency, and extend the life time of the PV modules [7].

Replacing the inductor with a CI in CF-DAB can further increase the power transfer capability while reducing the RMS current and conduction losses in the primary switches, as studied in [8]. However, the reflected current on the primary-side of CI in [8] introduces additional ripple to the input current, which can offset its advantages in PV applications. In this paper, a dual CIs configuration is added to the input stage of DAB
<figure><img src="image_3.png" /><figcaption>Fig. 2: Topology of dual-CI CF-DAB.</figcaption></figure>

<figure><img src="image_4.png" /><figcaption>Fig. 3: Topology of dual-CI CF-DAB.</figcaption></figure>

converter with a 180° phase-shift between the two legs to eliminate the input current ripple and reduce the need for large electrolyte capacitors. The power portion through CIs can be adjusted without any adverse effect on the input current ripple due to the cancellation effect of

the interleaved structure. The CIs design parameters can regulate the power distribution and determine the ZVS range for both primary and secondary-side switches. A wider ZVS range can be obtained in the proposed converter compared to VF-DAB converters, specifically near unity gain, where ZVS can be maintained across the entire power range over a broader voltage conversion range. The current-stress analysis and the impact of CIs parameters are also presented, aiming to design the circuit with minimized current stress and turn-off switching losses. Finally, the experimental results are shown to validate the performance of the proposed converter.

## II. PROPOSED DUAL-CI CF-DAB CONVERTER

The schematic of the proposed dual-CI CF-DAB converter is depicted in Fig. 2. The primary-side of the converter is fed by a PV solar panel, and the secondary-side delivers power to the high-voltage dc bus. The front-end converter provides galvanic isolation and boosts the PV voltage to a suitable level for grid connection. The dual-CI structure reduces the input current ripple $i_{in}$, and there is no need for large electrolyte capacitors. The introduction of the CIs can also increase the power transfer capability by creating additional pathways for power delivery to the secondary-side without resorting to extra switches.

The key waveforms of the proposed converter during different intervals are depicted in Fig. 3. Here, $v_{inv}$ and $v_{sec}'$ represent the square-wave voltage at the output terminal of the primary and reflected voltage of the secondary-side, respectively. The currents through the series inductor and the secondary side are denoted as $i_{L_s}$ and $i_{sec}$. The input currents and coupled inductor currents are labeled $i_{L(1,2)}$ and $i_{L(k(1,2))}$. All gate signals
<figure><img src="image_5.png" /><figcaption>Fig. 4: Power flow curves when d = 1 and m = 3.</figcaption></figure>

are 50% duty pulses, which not only step up the input voltage $V_{dc} = 2V_{in}$ but also reduce the primary-side current. The voltage across inductors, which determines the slope of the current in each stage, can be written as follows

$$ \begin{cases} v_{L_s} = v_{inv} - \frac{v_{sec}}{n} \\ v_{L_{K1}} = -v_{sec} - n_p v_{L_1} \\ v_{L_{K2}} = -v_{sec} + n_p v_{L_2} \end{cases} \quad (1) $$

Where $n_p = \frac{N_{s1}}{N_{p1}} = \frac{N_{s2}}{N_{p2}}$. To simplify the analysis, the dead-time effect can be neglected. The operation modes can be described as follows

Stage 1, $t \in [t_0 - t_1]$; This stage begins when the power semiconductor $Q_2$ and $Q_3$ are turned off, and $Q_1$ and $Q_4$ turn on under ZVS condition. On the secondary-side, $S_2$ and $S_4$ are ON, causing $i_{L_s}$ to increase from $I_0$ to $I_1$ with a slope of $\frac{V_{dc} + \frac{V_o}{n}}{L_s}$. Similarly, the slopes of CIs leakage currents are $\frac{V_{in}n_p + V_o}{L_{k(1,2)}}$. Consequently, the power is transferred simultaneously through transformer and interleaved CIs, increasing the power transmission capability.

Stage 2, $t \in [t_1 - T_{hs}]$: During this stage, the primary switches maintain their state, generating $V_{dc}$ in the inverter terminal. On the secondary-side, $S_2$ and $S_3$ are turned off and $S_1$ and $S_4$ turn on under ZVS, resulting in $v_{sec} = V_o$. Each power path can be analyzed similar to conventional DAB converter with SPS modulation. Therefore, under optimal voltage-match condition, the series inductor $i_{L_s}$ and leakage currents $i_{L_{(1,2)}}$ remain constant during $t \in [t_1 - T_{hs}]$ interval. However, when deviating from unity gain, the slope of current changes, as depicted with dotted lines in Fig. 3. The first half cycle ends when $Q_1$ and $Q_4$ turn off, and the next half cycle can be analyzed similar to the first half cycle.

### III. STEADY-STATE ANALYSIS

To determine the power transmitted through the transformer and CIs, the expressions of instantaneous currents are needed in each stage. The instantaneous transformer current $i_{L_s}$ over a half switching cycle is represented as

$$ i_{L_s}(t) = \begin{cases} \frac{V_{dc} + \frac{V_o}{n}}{L_s}(t - t_0) + I_0, & t \in [t_0, t_1] \\ \frac{V_{dc} - \frac{V_o}{n}}{L_s}(t - t_1) + I_1, & t \in [t_1, T_{hs}] \end{cases} \quad (2) $$

In steady-state, the average leakage current over one switching period is zero, and half-wave symmetry implies: $I_0 = -I_2$. Consequently, the transformer current values at the beginning of each interval can be expressed as

$$ \begin{cases} I_0 = \frac{T_{hs} V_{dc}}{2L_s} \{-1 + d(1 - 2n_{\phi})\} \\ I_1 = \frac{T_{hs} V_{dc}}{2L_s} \{(-1 + 2n_{\phi}) + d\} \end{cases} \quad (3) $$

where $d = \frac{V_o}{2V_{in}}$ is the voltage conversion ratio.

The instantaneous CIs currents $i_{L_{k(1,2)}}$ over a half-switching cycle can be formulated as follows

$$ i_{L_{k(1,2)}}(t) = \begin{cases} \frac{n_p V_{in} + V_o}{L_{k(1,2)}}(t - t_0) + I_{k(1,2)0}, & t \in [t_0, t_1] \\ \frac{n_p V_{in} - V_o}{L_{k(1,2)}}(t - t_1) + I_{k(1,2)1}, & t \in [t_1, T_{hs}] \end{cases} \quad (4) $$

It can be observed that the CIs currents are periodic and symmetrical over a switching cycle as well. Thus, the initial values for CIs currents can be calculated as follows

$$ \begin{cases} I_{k(1,2)0} = \frac{T_{hs} n_p V_{in}}{2L_{k(1,2)}} \{-1 + d'(1 - 2n_{\phi})\} \\ I_{k(1,2)1} = \frac{T_{hs} n_p V_{in}}{2L_{k(1,2)}} \{(-1 + 2n_{\phi}) + d'\} \end{cases} \quad (5) $$

where $d' = \frac{V_o}{n_p V_{in}}$.

Having the equations of instantaneous currents, the power flow through each path can be calculated by integrating the instant power over a half-switching cycle. The average transmission power flows through transformer can be expressed as follows

$$ P_{tr} = \frac{1}{T_{hs}} \int_{t_0}^{T_{hs}} v_{inv}(t) i_{L_s}(t) dt = \frac{V_{dc} \frac{V_o}{n}}{4L_s f_s} (2n_{\phi}(1 - n_{\phi})) \quad (6) $$

By defining $P^* = \frac{P}{P_b}$, where $P_b = \frac{(\frac{V_o}{n})^2}{8L_s f_s}$ represents the maximum power through the transformer, the normalized transferred power can be written as:

$$ P_{tr}^* = \frac{P_{tr}}{P_b} = \frac{4n_{\phi}(1 - n_{\phi})}{d} \quad (7) $$
Similarly, the expression for normalized power through the CIs is given by

$$ P_{CI(1,2)}^* = \frac{P_{CI}}{P_b} = \frac{1}{T_{hs}} \int_{t_0}^{T_{hs}} v_{sec}(t) i_{L_{k(1,2)}}(t) dt \quad (8) \\ = \frac{2nL_s n_p n_\phi (1 - n_\phi)}{dL_{k(1,2)}} $$

The relative transmission power through CIs and transformer can be obtained from (7) and (8) as follows

$$ m = \frac{P_{CI(1,2)}^*}{P_{tr}^*} = \frac{nn_p L_s}{2L_{k(1,2)}} \quad (9) $$

To obtain the voltage-match condition for CIs power paths, $n_p = 2n$ needs to be satisfied, leading to $m = \frac{n^2 L_s}{L_{k(1,2)}}$. From the power equations derived in (7) and (8), the power flow variation with phase-shift is depicted in Fig. 4, with $d = 1$ p.u. and m=3. As observed, the total power is $P_o^* = P_{tr}^*(1 + 2m)$, with the maximum output power occurring at the central point where $n_\phi = 0.5$.

## IV. SOFT-SWITCHING CONDITION ANALYSIS

Turn-on ZVS can be obtained to effectively minimize the switching losses of the proposed converter by ensuring that a sufficiently large reverse current flows at the switching instants, discharging the parasitic capacitor voltage to zero within the dead time $t_d$. The ZVS region of the proposed converter is influenced by both the transformer current and CIs currents.

### A. Secondary-Side ZVS Condition Analysis

The symmetry of the secondary-side current $i_{sec}$ over a switching cycle implies that the ZVS conditions of the switches in each leg are identical. As shown in Fig. 3, the ZVS condition for the secondary-side switches can be expressed as

$$ i_{sec}(t_1) > 0 \rightarrow (\frac{I_1}{n} + i_{L_{k1}}(t_1) + i_{L_{k2}}(t_1)) > 0 \quad (10) $$

By substituting the instantaneous current from (3) and (5) into (10), the ZVS condition for the secondary switches can be obtained as

$$ n_{\phi} > 0.5 - \frac{d(1 + 2xm)}{2(1 + 2m)} \quad (11) $$

Where $x = \frac{2n}{n_p}$ and $mx = \frac{n^2 L_s}{L_{k(1,2)}}$. Therefore, the injected currents from CIs to the secondary-side introduce an additional coefficient $(\frac{1+2xm}{1+2m})$ in (11), expanding ZVS range when $d < 1$. Moreover, as shown in Fig. 3, the injected currents from CIs increase when $d' > 1$, further enhancing the ZVS range.

<figure><img src="image_6.png" /><figcaption>Fig. 5: ZVS zones associated with ($n_\phi, d$) where $u=0.2$.</figcaption></figure>

### B. Primary-Side ZVS Condition Analysis

Due to the CF structure of the proposed converter, the current waveforms of switches are non-symmetric in the primary-side, as the input inductors/CIs increase the current stress on the low-side switches while reducing the current stress on the high-side switches. Thus, the ZVS of primary switches can be easily satisfied if $Q_2$ and $Q_4$ are soft switched. The soft-switching analysis of $Q_4$ is considered to study, where ZVS condition can be expressed as

$$ i_{L_s}(t_0) + i_{L_2}(t_0) < 0 \rightarrow I_0 + (n_p i_{L_{k2}}(t_0) + i_{L_{m2}}(t_0)) < 0 \quad (12) $$

The magnetizing inductors of CIs $L_{m(1,2)}$ exhibit a triangular-shaped current waveform with an average value equal to the half of the input current. As a result, the minimum current of magnetizing inductor can be described as

$$ i_{L_{m2}}(t_0) = \langle i_{L_{m2}} \rangle - \frac{\Delta i_{L_{m2}}}{2} = \frac{P_o}{2V_{in}} - \frac{V_{in}T_{hs}}{2L_{m2}} \quad (13) $$

Substituting the expression of output power obtained by (7) and (8) into (13) leads to

$$ i_{L_{m2}}(t_0) = \frac{dV_{in}(1 + 2m)n_{\phi}(1 - n_{\phi})}{L_s f_s} - \frac{V_{in}}{4L_{m2}f_s} \quad (14) $$

Then, by substituting (3), (5), and (14) into (12) the expression of ZVS range for primary switches can be written as

$$ n_{\phi} > \sqrt{\frac{-2 + 2d - \frac{1}{u} + 4md - \frac{4m}{x}}{4d(1 + 2m)}} \quad (15) $$

Where inductor ratio is defined as $u = \frac{L_{m2}}{L_s}$.

The depicted areas in Fig. 5 indicate the ZVS zones of VF-DAB and dual-CI CF-DAB converters on the
(n<sub>φ</sub>, d) surface using SPS modulation. As observed, the incorporation of the CIs introduces additional design parameters that enhance power transfer capability and extend the ZVS region. Increasing *x* expands the ZVS area for the secondary-side while shrinking the primary-side ZVS area. Moreover, unlike the VF-DAB, where ZVS of both sides is only feasible under voltage-match condition (d=1), the dual-CI CF-DAB can achieve ZVS on both sides even at light-load conditions and across a broader range of voltage conversion ratios.

### C. Boundary Power Condition Analysis

To determine the boundary power conditions for achieving ZVS, the voltage gain can be written as:

$$d = \frac{4(1 + 2m)n_{\phi}(1 - n_{\phi})}{P_{o}^{*}} \quad (16)$$

Now by substituting voltage gain (d) from (16) into ZVS boundary conditions (11) and (15), the boundary power condition to achieve ZVS can be expressed as given by

$$\left\{ \begin{array}{ll} \frac{4n_{\phi}(1-n_{\phi})(1-2n_{\phi}^{2})(1+2m)^{2}}{1+\frac{1}{2m}+\frac{2m}{x}} < P^{*}: & [Q_{2}, Q_{4}] \\ P^{*} < \frac{4n_{\phi}(1-n_{\phi})(1+2mx)}{1-2n_{\phi}}: & [S_{1}-S_{4}] \end{array} \right. \quad (17)$$

Using these boundary equations, Fig. 6 shows the ZVS power range for all switches with variation of voltage gain and phase-shift. ZVS can be achieved on both sides when the converter operates within the region bounded by the blue and green lines. The red lines depict the trajectories of normalized power under different voltage gains. As observed in Fig. 6. (a), as voltage gain deviates from unity, a portion of power range falls into the non-ZVS area. Moreover, the ZVS range gets narrower when voltage gain deviates farther away from unity. As shown in Fig. 6. (b), the dual-CI CF-DAB offers higher maximum power transfer capability and an improved ZVS range. For instance, the ZVS on both sides can be maintained across the entire power range in dual-CI CF-DAB under *m* = 1, *x* = 1.3, and *d* = 0.8 operation condition, whereas VF-DAB loses secondary-side ZVS at light-load.

## V. CURRENT STRESS ANALYSIS

Turn-off switching loss is determined by peak current through the switches. High current stress not only increases switching losses and reduce efficiency but also necessitates switches with higher current ratings. The primary-side switches of the proposed converter are impacted by both the transformer current and input CIs. The input CIs contribute to increased current stress on the low-side switches ($Q_2: -i_{L_s} + i_{L_1}$; $Q_4: i_{L_s} + i_{L_2}$

<figure><img src="image_7.png" /><figcaption>Fig. 6: ZVS range comparison with variation of the voltage gain. (a) ZVS range of conventional VF-DAB, (b) ZVS range of dual-CI CF-DAB with (u=0.2).</figcaption></figure>

where $i_{Q_{2,peak}}^* = \frac{i_{Q_{2,peak}}}{i_b}$ and $i_b = \frac{v_o}{8L_s j_s}$. The peak current plane, influenced by phase-shift and conversion ratio variations, is illustrated in Fig. 7. (a). The trajectories of peak current are also depicted for $P_o^* = 1$ and $P_o^* = 2$, reveal increased current stress when $d < 1$. The effect of circuit parameters are illustrated in Fig. 7. (b). As shown, reducing *x* increases the peak current through CIs, and the reflected current on the primary side of the CIs elevates the current stress on

$$i_{Q_{2,peak}} = -I_0 + (-n_p i_{L_{k1}}(t_0) + i_{L_{m1}}(t_0)) \quad (18)$$

Then by substituting the expressions of currents into (18), the normalized peak current can be given by:

$$i_{Q_{2,peak}}^* = 4n_{\phi}(1 - n_{\phi})(1 + 2m) + \frac{1}{ud} + \frac{4m}{dx} + \frac{2}{d} + 2(2n_{\phi} - 1)(1 + 2m) \quad (19)$$
<figure><img src="image_8.png" /><figcaption>Fig. 7: Primary-side switches peak current curves. (a) Peak current curve of $Q_3$ where u=0.2, x=1, and m=1, (b) The effect of circuit parameters on current stress of primary switches.</figcaption></figure>

the primary switches. Additionally, the current stress is reduced with increasing of the inductor ratio u. However, large magnetizing inductors $i_{L_{m(1,2)}}$ limit the ZVS region.

## VI. EXPERIMENTAL VERIFICATION

To validate the performance of the proposed circuit, a 300 W laboratory prototype was designed and implemented using the design considerations discussed in the previous sections, as shown in Fig. 8. The system specifications are listed in Table I. The input voltage range represents the voltage variations of the input PV panel, and the dc-link output voltage feeds the second-

<figure><img src="image_9.png" /><figcaption>Fig. 8: Experimental setup.</figcaption></figure>

<table><caption>TABLE I: SYSTEM PARAMETERS</caption><thead><tr><th>Parameter</th><th>Symbol</th><th>Value</th></tr></thead><tbody><tr><td>Input Voltage</td><td>V<sub>in</sub></td><td>50-70 V</td></tr><tr><td>Output Voltage</td><td>V<sub>o</sub></td><td>400 V</td></tr><tr><td>Output Power</td><td>P<sub>o</sub></td><td>300 W</td></tr><tr><td>CIs Parameters</td><td>[x, m, u]</td><td>[1, 1, 0.2]</td></tr><tr><td>Output Capacitors</td><td>C<sub>o</sub></td><td>15 μF- Film capacitor</td></tr><tr><td>Clamp Capacitor</td><td>C<sub>o</sub></td><td>10 μF- Film capacitor</td></tr><tr><td>Series Inductor</td><td>L<sub>s</sub></td><td>150 μH</td></tr><tr><td>Transformer turns ratio</td><td>n</td><td>1:3</td></tr><tr><td>Switching frequency</td><td>f<sub>s</sub></td><td>100 kHz</td></tr></tbody></table>

stage inverter. The experimental setup utilized a Xantrex XDC 100–10 for the input DC power supply, a Chroma 63108 DC electronic load for the DC bus, and a LeCroy Wavepro 7000 oscilloscope for measurements.

Fig. 9. (a) and (b) illustrate the key waveforms of the proposed converter in steady-state where phase-shift is set to $n_{\phi} = 0.2$. The primary output voltage ($v_{inv}$), secondary-side voltage ($v_{sec}$), series inductor current $i_{L_s}$, and primary-side CI current $i_{L_1}$ are depicted in Fig. 9. (a). The primary-side full-bridge boosts the input voltage, resulting in a twofold voltage gain and reduced current levels on the primary-side. Additionally, with 50% duty-cycle pulses on the primary-side, the current ripple of the CIs can completely cancel out, effectively eliminating the input current ripple and the need for a bulky input filter capacitor. As observed, under voltage-match condition, the series inductor current remains constant during the interval where both sides have same polarity, minimizing the peak and RMS currents of the switches and transformer.

The injected current by CIs to the secondary-side are illustrated in Fig. 9. (b). The CIs are designed with $x, m=1$. Since $x=1$, the shape of the leakage inductors currents ($i_{L_{k(1,2)}}$) is similar to the series inductor under voltage-match condition. Moreover, $m=1$ ensures equal power flows through the transformer and CIs, with 100W flowing through each path. The power distribution between CIs and transformer can be regulated by adjusting $m$, however increasing $m$ and power through CIs narrows down the ZVS range on the primary-side. The coupling factor of the CIs can be calculated as follows

$$k = \sqrt{\frac{4mu}{4mu + x}} \qquad (20)$$

The soft-switching waveforms of the proposed converter are depicted in Fig. 9. (c) and (d). The secondary-side ZVS performance is depicted in Fig. 9. (c). On the
<figure><img src="image_10.png" /><figcaption>Fig. 9: Experimental results of the proposed converter. (a) Steady-state waveforms with $n_{\phi} = 0.2$, (b) Injected current by CIs and the transformer, (c) Secondary-side ZVS $S_2$, (d) Primary low-side switch ZVS $Q_4$ under d=1, (e) Primary low-side switch ZVS $Q_4$ under d=1.2 condition.</figcaption></figure>

primary-side, achieving ZVS is more challenging for the low-side switches. Consequently, the ZVS performance of the $Q_4$ is illustrated in Fig. 9. (d). In both graphs gate-source voltage increases after the drain-source voltage drops to zero, and switches are turned ON under ZVS. Fig. 9. (e) shows the ZVS waveforms of primary switch $Q_4$ when d=1.2.

## VII. CONCLUSION

This paper introduces a dual-CI-based CF-DAB converter as a promising solution for PV applications. By replacing conventional inductors with coupled inductors (CIs) in the CF-DAB converter, the power transfer capability is significantly increased, and conduction losses are reduced. In addition, utilizing interleaved CIs with a 180° phase-shift between the two legs eliminates the input current ripple and the requirement for a large electrolyte capacitor. Consequently, the power distribution between CIs and the transformer can be adjusted without any adverse effect on the input current ripple due to the cancellation effect of the interleaved structure. The CIs design parameters can regulate the power portion and determine the ZVS range of the primary and secondary-side switches. The soft-switching analysis demonstrates a wider ZVS range for the proposed circuit compared to the VF-DAB converter, particularly near unity gain, where ZVS can be maintained across the entire power

range for a wider voltage range conversion. The current-stress analysis of primary switches and the effect of CIs parameters are also presented to provide insights for designing the circuit with reduced current stress and turn-off switching losses. Finally, the experimental results are shown to validate the effective performance of the proposed converter.

## REFERENCES

[1] L. Schmitz, D. C. Martins and R. F. Coelho, "High Step-Up Nonisolated ZVS/ZCS DC-DC Converter for Photovoltaic Thin-Film Module Applications," in *IEEE Journal of Emerging and Selected Topics in Power Electronics*, vol. 7, no. 1, pp. 565-575, March 2019, doi: 10.1109/JESTPE.2018.2830650.

[2] Y. Shen, H. Wang, Z. Shen, Y. Yang and F. Blaabjerg, "A 1-MHz Series Resonant DC-DC Converter With a Dual-Mode Rectifier for PV Microinverters," in *IEEE Transactions on Power Electronics*, vol. 34, no. 7, pp. 6544-6564, July 2019, doi: 10.1109/TPEL.2018.2876346.

[3] M. Forouzesh, Y. Shen, K. Yari, Y. P. Siwakoti and F. Blaabjerg, "High-Efficiency High Step-Up DC-DC Converter With Dual Coupled Inductors for Grid-Connected Photovoltaic Systems," in *IEEE Transactions on Power Electronics*, vol. 33, no. 7, pp. 5967-5982, July 2018, doi: 10.1109/TPEL.2017.2746750.

[4] L. Li, G. Xu, D. Sha, Y. Liu, Y. Sun and M. Su, "Review of Dual-Active-Bridge Converters With Topological Modifications," in *IEEE Transactions on Power Electronics*, vol. 33, no. 7, pp. 5967-5982, July 2018, doi: 10.1109/TPEL.2017.2746750.
*Electronics*, vol. 38, no. 7, pp. 9046-9076, July 2023, doi: 10.1109/TPEL.2023.3258418.

[5] X. Chen, G. Xu, H. Han, D. Liu, Y. Sun and M. Su, "Light-Load Efficiency Enhancement of High-Frequency Dual-Active-Bridge Converter Under SPS Control," in *IEEE Transactions on Industrial Electronics*, vol. 68, no. 12, pp. 12941-12946, Dec. 2021, doi: 10.1109/TIE.2020.3044803.

[6] V. K. Goyal and A. Shukla, "Isolated DC-DC Boost Converter for Wide Input Voltage Range and Wide Load Range Applications," in *IEEE Transactions on Industrial Electronics*, vol. 68, no. 10, pp. 9527-9539, Oct. 2021, doi: 10.1109/TIE.2020.3029479.

[7] Y. Shi, R. Li, Y. Xue and H. Li, "Optimized Operation of Current-Fed Dual Active Bridge DC-DC Converter for PV Applications," in *IEEE Transactions on Industrial Electronics*, vol. 62, no. 11, pp. 6986-6995, Nov. 2015, doi: 10.1109/TIE.2015.2432093.

[8] S. Goudarzitaemeh and M. Pahlevani, "A Bidirectional DC-DC Converter With Direct Power Transfer," in *IEEE Open Journal of Power Electronics*, vol. 5, pp. 232-249, 2024, doi: 10.1109/OJPEL.2024.3359971.