# Comprehensive Analysis of High Bandwidth Converters Based on SiC Technology for Automotive and Aircraft Applications

Israel D L da Costa, Bernardo Cougo, Lenin M F Morais

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Israel D L da Costa, Bernardo Cougo, Lenin M F Morais. Comprehensive Analysis of High Bandwidth Converters Based on SiC Technology for Automotive and Aircraft Applications. The 26th European Conference on Power Electronics and Applications, GDR SEEDS France & EPE Association, Mar 2025, Paris, France. 10.34746/epe2025-0222. hal-05095779

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# Comprehensive Analysis of High Bandwidth Converters Based on SiC Technology for Automotive and Aircraft Applications

Israel D. L. da Costa¹,², Bernardo Cougo¹, Lenin M. F. Morais²

¹IRT SAINT-EXUPÉRY / ²GRADUATE PROGRAM IN ELECTRICAL ENGINEERING, FEDERAL UNIVERSITY OF MINAS GERAIS (UFMG)

¹³ Rue Tarfaya, 31400 / ²Antônio Carlos, 6627, 31270-901, MG

¹Toulouse, France / ²Belo Horizonte, Brazil

Tel.: +33 / (7) – 66.02.45.83

E-Mail: israel.divan@irt-saintexupery.com / bernardo.cogo@irt-saintexupery.com / lenin@cpdee.ufmg.br

URL: ¹https://www.irt-saintexupery.com/fr/ ²https://ppgee.ufmg.br/

## ACKNOWLEDGMENT

This work has received funding from IRT Saint Exupéry as part of an innovation project and was also financed in part by the Coordenação de Aperfeiçoamento de Pessoal de Nível Superior - Brasil (CAPES) - Finance Code 001.

**Index Terms**—High frequency power converter, High bandwidth application, Semiconductor technology, SiC MOSFET, Wide bandgap devices.

**Abstract**—This paper explores the influence of semiconductor technology on the bandwidth of power converters, with a particular focus on the loss mechanisms of Silicon Carbide (SiC) MOSFETs and the non-idealities of switching cells. A model for the harmonic content as a function of switching frequency to evaluate the potential bandwidth limits based on the total harmonic distortion (THD) of the output current is introduced. Given that the relationship between bandwidth and switching frequency is directly proportional to the THD limit of the output current, it becomes crucial to investigate the temperature limitations and loss mechanisms of the components used within the switching cell to ensure a viable converter. Both simulation and experimental results are employed to verify the accuracy of loss models and evaluate the relationship between THD and switching frequency, considering ripple current, the effect of output inductance parasitic capacitance, the saturation of the magnetic core, as well as the impact of dead time.

## I. INTRODUCTION

E-Mobility [1] and More Electric Aircraft (MEA) [2] are driving the shift from internal combustion engines to electric motors and batteries, relying heavily on advancements in power electronics and battery technology. Wide Bandgap (WBG) semiconductors like Silicon Carbide (SiC) and Gallium Nitride (GaN) are crucial in making power electronics more efficient and compact for both electric vehicles and aircrafts. These technologies allow higher switching frequencies, better thermal management, and reduced component size and weight [3], improving electric vehicles (EV) performance and MEA efficiency.

<figure><img src="image_2.png" /><figcaption>Fig. 1. Example of applications for high bandwidth power converter (HBWPC). (a) P-HIL for input impedance characterization (spectroscopy). (b) Differential Mode Active Power Filter.</figcaption></figure>

WBG technologies have transformed power electronics by enabling high power and switching frequencies, making them suitable for applications previously dominated by linear solutions. Examples include active power filters for electromagnetic compatibility (EMC) [4], Class D amplifiers for Power-Hardware-In-the-Loop (P-HIL) simulations [5], and MHz-frequency induction heating [6]. In E-Mobility, the demand for high-bandwidth converters is driven by two key needs: ultra-high bandwidth differential mode active filtering and P-HIL for large signal spectroscopy, both targeting 150kHz bandwidth, as shown in Figure 1. Large-signal spec-
troscopy tests require superposition on a direct current (DC) level of either 540V or 800V for network and input impedance characterization [7].

Electromagnetic Compatibility (EMC) requirements differ between automotive and aircraft sectors. The UN-ECE R10 regulation for automotive uses CISPR, ISO, and IEC standards, while aviation relies on MIL-STD-704 for the 0-150kHz range and RTCA/DO-160G for 150kHz-152MHz. Reference [8] shows that for a 1200V SiC aircraft power converter, passive filters may constitute up to 65% of the converter's total weight. This is primarily due to the filter's critical role in maintaining connection impedance and network stability [7]. Thus, using active filters with WBG technologies can offer a lighter filter design, as noted in [9].

In such applications, voltage standards profiles are defined as follows: E-Mobility for ground vehicles uses embedded DC distribution standard with variable voltage levels, typically 250V-400V DC for passenger vehicles. High-performance and heavy-duty vehicles are shifting to 800V DC systems [10], following SAE J1772 and IEC 62196-2 standards. In aviation, new designs propose higher or dual-voltage systems (540V and 270V) to improve power efficiency and handle larger electrical loads in commercial and military aircraft [11]. Studies [12], [7] support 800V DC for high-voltage systems, reducing current and allowing lighter components. For both sectors, 1200V SiC devices in a 2-Level topology are ideal for enhancing efficiency, power density, and reliability. Recent studies have proposed multilevel GaN-based high-bandwidth power converters [13], [14] aiming for an MHz output profile.

Bandwidth of power converters is mainly limited by four elements:

* Semiconductor Technology

* Converter Topology

* Control Strategy

* Measurement Techniques

This paper shows the influence of semiconductor technology in the bandwidth of power converters, aiming to optimize this bandwidth through critical factor analysis. This analysis will be presented by using two third-generation 1200V SiC transistors having on-state resistance of 75mΩ and 16mΩ references C3M0075120K and C3M0016120K in a 2 level topology as a current source. SiC devices are selected for their appropriate voltage capability. The impact of die size on performance is evaluated, noting that a larger die size (16mΩ) reduces conduction losses at the expense of higher switching losses, whereas smaller die size (75mΩ) offers the opposite effect.

This study is organized into key sections. Section II-A assesses converter bandwidth by examining Total Harmonic Distortion (THD) of the output current, using analytical method based on switching frequency and modulation index. It highlights how switching frequency affects bandwidth and stresses the importance of analysing the thermal behavior of SiC devices to ensure converter viability. Section II-B provides a thermal evaluation of SiC devices, considering device parameters, cooling, and loss mechanisms. Section III presents a software analysis modeling the impact of output inductor non-idealities, including core saturation and parasitic capacitance, as well as the effect of dead time on THD. Section IV presents experimental results to validate the analysis from previous sections, and Section V provides the conclusions.

## II. INFLUENCE OF SEMICONDUCTOR TECHNOLOGY ON BANDWIDTH

In power converters, bandwidth is the frequency range where the converter responds quickly to changes in load or input. Higher bandwidth means faster response. It is closely related to switching frequency, which controls how fast transistors regulate output. Increasing switching frequency improves bandwidth but also increases switching losses and electromagnetic interference (EMI). This study shows how to evaluate bandwidth while considering thermal limits of semiconductor technology, balancing switching and conduction losses for optimal performance.

### A. THD of Output Current as Bandwidth Evaluation

In a DC/AC power converter, such as shown in Figure 2, total harmonic distortion of the output current is influenced by high-frequency ripple and non-idealities such as dead time, body diode reverse recovery, magnetic saturation, and parasitic capacitance of the output filter. In this section, analysis focuses on the impact of high-frequency ripple current (harmonic content) on the output. Factors like supply voltage, output filter topology, switching frequency, and modulation index affect the RMS value of the ripple current $I_{out(h)}$. Equation 1 breaks down the harmonic content of the output current $I_{out}$ of converter in Figure 2, enabling the calculation of THD as shown in Equation 3. Additionally, Equation 2 presents the RMS value of the fundamental current $I_{out(1)}$ through inductance $L$, connected to an ideal voltage source as shown in Figure 2.

$$I_{out(h)} = I_{out} - I_{out(1)} \quad (1)$$
<figure><img src="image_3.png" /><figcaption>Fig. 2. Single-cell DC/AC converter, with output current comprising a fundamental component and high-frequency ripple, with a given modulation index.</figcaption></figure>

$$I_{out(1)_{RMS}} = \left( \frac{V_{DC} \cdot M_i}{2\sqrt{2}} \right) \cdot \frac{1}{2\pi \cdot \underbrace{f_{sin}}_{BW} \cdot L} \quad (2)$$

Where $V_{DC}$ denotes the voltage of the switching cell, $M_i$ represents the modulation index ranging from 0 to 1, $L$ specifies the output inductance value, and $f_{sin}$ is the frequency of the synthesized output current. The maximum value of $f_{sin}$ for a given THD denotes the converter bandwidth $BW$.

$$THD_{Iout} = \frac{\sqrt{\sum_{h=2}^{\infty} I_{out(h)_{RMS}}^2}}{I_{out(1)_{RMS}}} \cdot 100\% \quad (3)$$

In a 2-level switching cell, the relationship between the ripple current $\Delta I$ and the duty cycle $D$ is

$$\Delta I = \frac{V_{DC} \cdot D \cdot (1 - D)}{L \cdot F_{sw}} \quad (4)$$

Where $F_{sw}$ is the switching frequency.

A DC/AC converter exhibits a periodic sinusoidal variation in the duty cycle as a function of the modulation index $M_i$, as detailed in Equation 5. In a single cell topology, the modulation index determines the ratio of the maximum amplitude of the synthesized output voltage to half of the DC link voltage.

$$D(t) = \frac{M_i \cdot \sin \omega t}{2} + \frac{1}{2} \quad (5)$$

Where $\omega = 2\pi \cdot f_{sin}$ and $t$ is the time.

Substituting Equation 5 into 4, the resulting function outlines the envelope of $\Delta I$, attaining its maximum value when the duty cycle is equal to 0.5. With these values, we can calculate the normalized RMS value of the high frequency ripple current ($I_{out(h)_{RMS}norm}$) synthesized by the converter. The relationship between ($I_{out(h)_{RMS}norm}$) and the modulation index is shown in the upper curve of figure 3. The absolute RMS value of the ripple current ($I_{out(h)_{RMS}}$), as shown in Equation 6, depends on the

<figure><img src="image_4.png" /><figcaption>Fig. 3. Normalized RMS value of ripple current and k factor versus modulation index in a 2 level switching cell.</figcaption></figure>

converter's operating parameters: as DC voltage, output inductance $L$ and switching frequency $F_{sw}$.

$$I_{out(h)_{RMS}} = I_{out(h)_{RMS}norm} \cdot \frac{V_{DC}}{L \cdot F_{sw}} \quad (6)$$

Thus, the total harmonic distortion, relative to the converter's operating parameters, is calculated in 7. THD value decreases when $M_i$ and $F_{sw}$ increases.

$$THD_{Iout} = \frac{I_{out(h)_{RMS}norm} \cdot V_{DC}}{I_{out(1)_{RMS}} \cdot L \cdot F_{sw}} \cdot 100\% \quad (7)$$

Defining the harmonic content in the AC current synthesized by the switching cell enables the development of a generalized model to assess bandwidth. The bandwidth ($BW$) of the converter is defined as the maximum frequency of the output current with a THD below a specified threshold. Theoretically, $BW$ is proportional to the switching frequency by a factor $k$, denoting the relationship between $f_{sin}$ and $f_{sw}$ defined as follows:

$$\underbrace{f_{sin}}_{BW} = k \cdot F_{sw} \quad (8)$$

Substituting equation 8 and 2 in Equation 7, results in the Equation 9 which defines the $k$ factor as function of the desired THD and $M_i$. The right axis of Figure 3 depicts the $k$ as function of $M_i$ for different values of THD.

$$k = THD_{Iout} \cdot \frac{M_i}{\underbrace{4\pi\sqrt{2} \cdot I_{out(h)_{RMS}norm}}_{k_{M_i}}} \quad (9)$$

Where the second term $k_{M_i}$ is function of $M_i$.

Thus, Equation 10 describes the theoretical bandwidth limitation as a function of the desired THD value, the switching frequency and the modulation index.

$$\underbrace{f_{sin}}_{BW} = THD_{Iout} \cdot k_{M_i} \cdot f_{sw} \quad (10)$$
<figure><img src="image_5.png" /><figcaption>Fig. 4. Relationship between BW and switching frequency as function of THD and *Mi*.</figcaption></figure>

Figure 4 presents calculated bandwidth values for a 2-level switching cell comprising a range of *Mi* between 0.1 and 1 and THD limit of 5%. For *Mi*'s=0.1, the ripple current has RMS value 84% greater than for *Mi* equal to 1, whereas the fundamental RMS current synthesized in the converter output has a low amplitude, defined by equation 2.

Since the relationship between bandwidth and switching frequency is directly proportional and dependent on the THD limit, it is essential to investigate the temperature limitations and loss mechanisms of the components used in the switching cell. This will facilitate determining a balance between bandwidth and losses for a feasible and reliable final design of a high bandwidth power converter.

## B. Thermal Evaluation of SiC Devices

Junction temperature modeling involves specifying thermal impedance, which describe the device's heat dissipation pathway to the surrounding environment, along with computing conduction and switching losses for these devices. Figure 5 illustrates the mechanical setup of the SiC switching cell utilized in this study and its thermal path. The theoretical junction temperature of each component, $T_{j1}$ and $T_{j2}$, given by Equation 11, is determined by applying the total losses of each device to the thermal circuit constituted of thermal resistances from junction to case $R_{th_{jc}}$, case to heatsink $R_{th_{ch}}$, and heatsink to ambient $R_{th_{ha}}$, as specified in the component datasheets. Table I presents the theoretical thermal resistances of the switching cell, employing the chosen SiC devices.

$$T_j = T_{amb} + P_{tot} \cdot R_{th_{ha}} + P_{SiC} \cdot (R_{th_{jc}} + R_{th_{ch}}) \quad (11)$$

where $P_{tot} = 2 \cdot P_{SiC}$ and $P_{SiC} = P_{cond} + P_{sw}$ and $T_{amb}$ is the ambient temperature. $P_{tot}$ is the total power

<figure><img src="image_6.png" /><figcaption>Fig. 5. Mechanical assembly and thermal circuit of the SiC switching cell, mounted on an AAVID 0S517 heatsink with a length of 50 mm, incorporating a 414JHH cooler and a layer of Bergquist Hi-Flow 105 thermal interface material (TIM).</figcaption></figure>

dissipated by the switching cell, $P_{SiC}$ is the total losses dissipated in each device, constituted by conduction losses $P_{cond}$ and switching losses $P_{sw}$. Semiconductor

<table><caption>TABLE I
THERMAL PATH RESISTANCES FROM DATASHEETS.</caption><thead><tr><th>DEVICE</th><th>R<sub>thjc</sub> (K/W)</th><th>R<sub>thch</sub> (K/W)</th><th>R<sub>thha</sub> (K/W)</th></tr></thead><tbody><tr><td>C3M0016120K</td><td>0.27</td><td>0.95</td><td>0.489</td></tr><tr><td>C3M0075120K</td><td>1.1</td><td>0.95</td><td>0.489</td></tr></tbody></table>

Maximum losses per switching cell for $T_j=150°C$.

<sup>a</sup>P<sub>SiC max C3M0075120K</sub> per switching cell = 66.04W.

<sup>b</sup>P<sub>SiC max C3M0016120K</sub> per switching cell = 91.08W.

losses in power converters consist of conduction and switching losses. While conduction losses can be accurately estimated using datasheet information, switching losses for SiC and GaN components are frequently either not provided or inaccurately reported in datasheets. The methodology for estimating SiC losses, originally developed in [15], is revisited in this work. Conduction losses in the switching cell can be easily calculated by:

$$P_{cond} = R_{DSon} \cdot (I_{out(1)}_{RMS}^2 + I_{out(h)}_{RMS}^2) \quad (12)$$

The ON-state resistance $R_{DSon}$ of a MOSFET, varies with junction temperature and is readily available in component datasheets. This investigation calculates conduction losses at a junction temperature of 125°C, which is 50°C lower than the maximum allowed temperature specified by SiC MOSFET manufacturer. Furthermore, switching losses were estimated based on datasheet graphs illustrating how turn-on and turn-off energies changes with switching current under specific conditions, including drain-source voltage $V_{DS}$, gate resistance $R_G$, gate-source voltage $V_{GS}$, and $T_j$. Consequently, the cal-
<figure><img src="image_7.png" /><figcaption>Fig. 6. Maximum achievable switching frequency versus output current for the theoretical thermal path and max junction temperature of Tjmax of 125°C. Solid lines represents the theoretical model and the dashed lines represents the PLECS model provided by the manufacturer. VDC=800V and RG=10Ω.</figcaption></figure>

calculation of switching losses, Psw, can be performed as follows:

$$P_{sw} = \frac{F_{sw}}{N_p} \cdot \sum_{n=0}^{N_p} [E_{off}(i(n)) + E_{on}(i(n))] \quad (13)$$

where Np is the number of switching periods in a period of the output current, and Eoff, ion and Eon, ion are respectively turn-off and turn-on energies at current ion at the nth switching period.

When addressing switching losses, a key consideration are the energies linked to low and zero output currents, which are usually omitted in datasheets. Specifically, at lower currents, switching energies are predominantly governed by the charge and discharge of the transistor's output capacitance (Coss). The proposed methodology for evaluating switching losses combines classical datasheet methodology and the approach shown in [16]. In this reference, the average switching losses for device at zero current is determined by the sum of the energy stored in Coss, provided in device's datasheet Eoss and the energy loss generated by a small current bump generated by Qoss in the hard-switching turn-on, Eqoss. Eoss is the energy from the switching device's own capacitance self-discharging current, while Eqoss is due to the charging current of the capacitance from the opposite switching device [16].

The relationship between the half-bridge output current and the maximum switching frequency limited by maximum junction temperature is illustrated in Figure 6. It shows two models. Continuous lines were calculated using energy data from the datasheet, including calculated Eoss and Eqoss values. Dashed lines, were generated by simulation using PLECS software and the SiC MOSFET PLECS model given by the

manufacturer. Differences between the models are due to different methodologies in applying the correction factor relative to RG for manufacturer and the proposed model besides the manufacturer's model's omission of energy data at lower currents. This omission leads to an underestimation of switching losses at lower currents and an overestimation at higher currents within the manufacturer's model. Note that, after a small current, the higher the output current, the lower the maximum switching frequency limited by a maximum SiC junction temperature of 125°C. The 75mΩ device can achieve much higher switching frequency since it has lower parasitic capacitance. However it cannot achieve high output current than the 16mΩ device.

### III. PRECISE MODELING OF OUTPUT CURRENT THD

In a real converter, the total harmonic distortion of the output current is influenced by more than just the current ripple at the switching frequency. Three key factors that significantly affect THD are discussed below.

#### A. Magnetic Core Saturation

The larger part of magnetic cores used in output filters for DC/AC converters are iron powder cores. Each magnetic material is available in various geometries and properties. The permeability μ and magnetic field strength H exhibit an inverse and non-linear relationship. Higher permeability results in a design with fewer turns, leading to a more compact geometry; however, this tends to cause more pronounced inductance drops when compared to an opposite scenario for the same DC bias. Selecting the optimal geometry and permeability involves balancing iron and copper losses with the allowable variation in L under the converter's operating conditions. Figure 7 illustrates the variation in THD with respect to Iout for an inductor constructed using the Magnetics Kool-Mμ toroidal core 0079737A7 for different permeabilities. This study exclusively assesses the influence of nonlinear inductance variation on the fundamental value of the output current. Results of Figure 7 were taken for a designed inductor having an initial inductance L of 1.3mH. A fundamental frequency of 1kHz was considered, without high-frequency ripple. Results reveal that pronounced non-linearity at high current produces low-frequency harmonics, significantly impacting the THD of the synthesized output current.

#### B. Parasitic Capacitance in the Output Inductance

The parasitic capacitance associated with the inductor's winding introduces additional non-linearity into the current synthesized by the converter. This effect is
<figure><img src="image_8.png" /><figcaption>Fig. 7. THD of the output current as a function of the non-linearity of the inductor's magnetic core.</figcaption></figure>

negligible at low switching frequencies, but in designs with high bandwidth, where the switching frequency and the voltage derivative—dependent on $V_{GS}$, $R_G$, $C_{oss}$, and $I_{out}$—are high, the impact of this capacitance on the THD of the output current becomes significant. Figure 8 illustrates how THD varies as a function of parasitic capacitance under the same operational conditions previously analyzed, but employing a linear magnetic core. Given that capacitive current is proportional to the voltage derivative, the magnitude of the harmonic current related to parasitic capacitance is directly proportional to the $dv/dt$ of the voltage at the switching node. It is also important to highlight that the harmonic current contribution, calculated per low frequency period, is directly proportional to the switching frequency. How shown in Figure 8, with a null parasitic capacitance, only the switching ripple influences the THD. However, when accounting for the capacitance effect, THD increases, dependent on the capacitance value and the $dv/dt$. At a switching frequency of 100kHz, a tenfold rise in $dv/dt$ nearly doubles the THD for a capacitance of 800pF. The design trade-off lies in minimizing this capacitance to render its effect irrelevant.

<figure><img src="image_9.png" /><figcaption>Fig. 8. THD of output current as a function of the output inductor's parasitic capacitance. $V_{DC}=800$V, $M_i = 0.9$.</figcaption></figure>

### C. Dead Time

The selection of dead time for the switching cell is critical, as it is defined by the minimum time interval required between the switching of two transistors to avoid cross-conduction and catastrophic failure of the power stage. The effective dead time depends on the controller dead time in addition of component parameters such as input capacitance $C_{iss}$, $V_{GS}$, $R_G$, and the direction of the output current. Dead time leads to voltage-second errors, especially at low currents and zero crossings, significantly increasing the THD of the current produced by the switching cell.

An ideal inductance scenario was considered to analyze the influence of dead time on the THD of the output current. An RMS controller was used to maintain a consistent amplitude of the fundamental current throughout the range of dead time variations. Figures 9 and 10 illustrate the variation of THD as a function of the ideal dead time for different switching frequencies, considering the same relative dead time with respect to the switching period. The low-frequency THD induced by dead-time can be analytically calculated based on the harmonics currents imposed by the dead time voltage on the output inductance over the fundamental frequency,

$$V_{dead}(t) = V_{DC}(t-delay) \cdot dead_{rel} \cdot sign(I_{out}) \quad (14)$$

where $dead_{rel}$ is defined in Equation 15 and the delay time introduced by the dead time is defined in Equation 16.

$$dead_{rel.} = \frac{dead_{time}}{T_{sw}} \quad (15)$$

$$delay(s) = e^{-s(dead_{rel.} \cdot T_{sin})} \quad (16)$$

The current imposed by $V_{dead}$, defined in Equation 17 is a triangular current with the same frequency of $f_{sin}$, having the peak value equal to $i_{deadpeak}(t)$

$$i_{deadpeak}(t) = \frac{V_{dead} \cdot T_{sin}}{4 \cdot L} \quad (17)$$

Considering only the harmonic content of this low-frequency triangular current we have,

$$i_{dead}(h)_{RMS} = \sqrt{\frac{\pi^4 - 96}{3\pi^4}} \cdot |i_{dead}| \quad (18)$$

Substituting 14 and 17 in 18 and knowing that the THD is the quotient between the RMS of the harmonic content (Equation 18) and the fundamental value (Equation 2), we have an analytical expression in Equation 19 which defines the THD value of the output current as a function of the relative dead time.

$$THD_{Iout(dead)} = \frac{0.3085 \cdot dead_{rel.}}{M_i} \cdot 100\% \quad (19)$$
<figure><img src="image_10.png" /><figcaption>Fig. 9. THD of the output current for different switching frequencies as a function of the dead-time value. $I_{out}$ = 18A RMS, $Mi$ = 0.562.</figcaption></figure>

<figure><img src="image_11.png" /><figcaption>Fig. 10. THD of the output current as a function of the relative dead-time value. $I_{out}$ = 18A RMS, $Mi$ = 0.562.</figcaption></figure>

By disregarding the high-frequency harmonics caused by the switching frequency, the THD remains constant for a given relative dead-time, regardless of the switching frequency $F_{sw}$ as indicated by the $k'(Mi)$, Equation 20.

$$k'(Mi) = \frac{0.3085}{Mi} \qquad (20)$$

## IV. EXPERIMENTAL RESULTS

Figure 11 illustrates the experimental test bench composed of two independently evaluated switching cells. One cell employs SiC C3M0016120K, while the other utilizes SiC C3M0075120K. Each cell links to the midpoint of two series-connected 8.2mF capacitors via a 1.3mH/25ARMS inductor. This inductor, was fabricated using Kool-μ 60 magnetic material with a 0079737A7 geometry. This assembly exclusively allows the flow of AC current at the output of the switching leg. This inductor aims to minimize ripple currents in scenarios with an 800V nominal DC voltage and switching frequencies in the tens of kHz range, in order to evaluate the switching loss model. Bandwidth analysis employs current THD synthesis and examines the modulating and switching frequency relationship.

<figure><img src="image_12.png" /><figcaption>Fig. 11. Setup for testing the SiC High Bandwidth Converter and validate analysis shown in this paper.</figcaption></figure>

### A. Experimental Thermal Path

Thermal path characterization is done by shorting each half-bridge under a controlled voltage/current setting. Dissipated power ($P_{loss}$ = $V_{DS} \cdot I_{D}$) is measured for each device, and thermal resistances along the path are estimated using temperature measured by a FLUKE Ti401 PRO thermal camera (Figure 12). Table II lists the estimated resistance values for a single half-bridge of each device. The observed total thermal resistance deviates from the theoretical model, thereby constraining the maximum losses and highlighting the datasheet data's inaccuracies, primarily associated with the Thermal Interface Material (TIM) as a function of the pressure applied by the transistor's clips.

<figure><img src="image_13.png" /><figcaption>Fig. 12. Thermal picture of switching cell used to characterize thermal path by using a FLUKE Ti401 PRO thermal camera.</figcaption></figure>

### B. Loss Evaluation and Maximum Switching Frequency

Figure 13 shows the model outlined in Section II, showing the maximum switching frequency versus output current, updated with the thermal path characteristics described in the preceding subsection. A maximum junction temperature of 125°C was considered in the tests. The results of the model (solid lines) demonstrates a reduction for the maximum switching frequency by
<table><caption>TABLE II
THERMAL RESISTANCES CHARACTERIZATION</caption><thead><tr><th>DEVICE</th><th>Rth<sub>jh</sub> (K/W)</th><th>Rth<sub>ha</sub> (K/W)</th><th>P<sub>losses</sub> (W)</th></tr></thead><tbody><tr><td>C3M0016120K</td><td>2.55</td><td>0.488</td><td>70.9</td></tr><tr><td>C3M0075120K</td><td>2.62</td><td>0.488</td><td>69.52</td></tr></tbody></table>

<sup>a</sup>Rth<sub>jh</sub> is equals to Rth<sub>jc</sub> + Rth<sub>ch</sub>.

T<sub>case max</sub> = 150°C.

15.85% for the 75 mΩ SiC and 38.23% for the 16 mΩ SiC when compared with the theoretical thermal path results demonstrated in Figure 6. This is corroborated by the results represented by the points in the graph. Each point represents the experimental results, which are very closer to the updated model.

<figure><img src="image_14.png" /><figcaption>Fig. 13. Maximum achievable switching frequency versus output current for max junction temperature of T<sub>J max</sub> of 125°C. Lines represents the Section II model updated by experimental thermal path and points represents experimental measurements for each switching cell.</figcaption></figure>

### C. Bandwidth Evaluation

The objective of this evaluation is to identify a switching frequency that results in a THD below the standard required for the converter's application, thus achieving the desired bandwidth. Figure 14 gives an example of measured current. The distortion of this waveform originates from ripple current effects, the high-frequency harmonic currents due to the parasitic capacitance of the output inductor, and the impacts of magnetic saturation and dead time.

Figure 15 illustrates the comparison of the THD model, derived from Equation 10, with experimental results as a function of switching frequency and modulation index. The analysis reveals that switching ripple significantly influences THD at lower switching frequencies, whereas the role of output inductor's parasitic capacitance becomes prominent at higher frequencies due to increased number of commutations per fundamental

<figure><img src="image_15.png" /><figcaption>Fig. 14. Experimental waveform of the C3M0075120K switching cell with I<sub>out</sub>=18A<sub>RMS</sub>, F<sub>sw</sub>=50kHz and THD=15%.</figcaption></figure>

<figure><img src="image_16.png" /><figcaption>Fig. 15. THD evaluation versus Switching Frequency as function of ripple current and inductor's parasitic capacitance effect. Experimental results with I<sub>out</sub>=10A RMS and M<sub>i</sub>=0.3 usign switching cell C3M0075120K.</figcaption></figure>

period. The comparison involved evaluating the THD with and without accounting for the capacitive current effect. For the analysis, the maximum Fast Fourier Transform (FFT) frequency applied to the current vector was limited to 2MHz when omitting the capacitive effect and extended to 250MHz to encompass the full spectrum when considering it. The capacitive current component is within the 8 to 16MHz range. Ignoring capacitive current, experimental points are very close to the model, attributing the THD to the switching ripple effect exclusively.

Figure 16 illustrates experimentally the impact of magnetic core non-linearity on THD as a function of current. For that, the effects of switching ripple were minimized, given that the switching cell received a 50 V<sub>DC</sub> input and set a maximum frequency of 2.5 kHz for THD calculations. The findings match with those
<figure><img src="image_17.png" /><figcaption>Fig. 16. Experimental output current waveform and THD value as a function of the output current RMS value. Since the output inductors uses a soft saturation magnetic material, the higher the current, the higher the distortion.</figcaption></figure>

presented in the precise modeling subsection's evaluation metric. These THD values are close to those simulated and shown in Figure 7. Results shown in Figures 15 and 16 validate the developed THD models and the approach to calculate a 2-level converter bandwidth.

## V. CONCLUSION

This article introduces a method to evaluate the influence of semiconductor technology on the bandwidth of a 2-level switching cell, employing THD of the current as the evaluation metric. It details a technique for estimating the THD as a function of switching frequency and investigates the impact of power stage non-idealities such as saturation and parasitic capacitance of the output inductor, along with dead time. The findings suggest that higher bandwidth requires increased switching frequencies, but this introduces attention to the construction of the output inductance in order to mitigate parasitic capacitance effects. Additionally, this study assesses the conduction and switching loss characteristics of SiC MOSFETs, especially under high switching frequencies, considering thermal constraints relevant to the mission's requirements. Comparison of dies with RDSon of 75mΩ and 16mΩ revealed that the use of multiple smaller dies, instead of one single big die, is significantly more advantageous to increase bandwidth because they are more easily cooled and can switch faster, and consequently can achieve higher switching frequency. However, if these multiple smaller dies are connected in parallel interleaved topologies, e.g. parallel multilevel converters, the apparent switching frequency is even higher as well as the converter bandwidth.

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