# Hafnium oxide-based ferroelectric field effect transistors: From materials and reliability to applications in storage-class memory and in-memory computing

Agniva Paul, Gautham Kumar, Apu Das, Guilhem Larrieu, Sourav De

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Agniva Paul, Gautham Kumar, Apu Das, Guilhem Larrieu, Sourav De. Hafnium oxide-based ferroelectric field effect transistors: From materials and reliability to applications in storage-class memory and in-memory computing. Journal of Applied Physics, 2025, 138, pp.010701. 10.1063/5.0278057. hal-05226133

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# Hafnium oxide-based ferroelectric field effect transistors: From materials and reliability to applications in storage-class memory and in-memory computing

Agniva Paul; Gautham Kumar; Apu Das; Guilhem Larrieu ; Sourav De

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# Hafnium oxide-based ferroelectric field effect transistors: From materials and reliability to applications in storage-class memory and in-memory computing

Cite as: J. Appl. Phys. 138, 010701 (2025); doi: 10.1063/5.0278057

Submitted: 28 April 2025 · Accepted: 5 June 2025 ·

Published Online: 7 July 2025

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Agniva Paul,¹ Gautham Kumar,¹ Apu Das,¹ Guilhem Larrieu,²,ª ID and Sourav De¹,ª ID

## AFFILIATIONS

¹MiMi Lab—College of Semiconductor Research, National Tsing Hua University, College of Semiconductor Research Main Campus, 4F, General Building 3, No. 101, Section 2, Guangfu Road, Hsinchu City 30013, Taiwan

²MPN—Materials, Processes and Nanodevices, LAAS-CNRS, 7, av. du colonel Roche BP 54200, 31031 Toulouse Cedex 4, France

ª) Authors to whom correspondence should be addressed: sourav.de@mx.nthu.edu.tw and glarrieu@laas.fr

## ABSTRACT

Hafnium oxide-based ferroelectric field-effect transistors (FeFETs) are redefining non-volatile memory (NVM) by enabling low-power, high-speed, and compatibility with advanced complementary metal-oxide-semiconductor nodes. Exploiting polarization-induced threshold voltage shifts in ultra-scaled gate stacks, FeFETs achieve sub-5 V write voltages, <10 ns switching, on/off ratios >$10^3$, >$10^6$ s data retention, and endurance up to $10^8$ cycles under optimized stress. This review consolidates recent advances in orthorhombic phase stabilization via dopant engineering, interfacial optimization, and defect dynamics that dictate performance variability. Compared to resistive RAM, phase-change, magnetic, and flash memories, FeFETs demonstrate superior integration potential for storage-class memory and compute-in-memory applications. Silicon-channel devices already achieve <100 ns read/write speeds and programming energy near 100 fj/bit, with scalability beyond the 28 nm node. Innovations—such as La doping, asymmetric gate stacks, and oxide semiconductors, such as indium gallium zinc oxide and molybdenum sulfide—have enabled sub-1 V operation and endurance >$10^{10}$ cycles. Reliability concerns including wake-up and fatigue are linked to oxygen vacancy migration, interface trap formation, and phase boundary evolution, elucidated through cycling endurance, data retention, and low-frequency noise analysis. We also highlight industrial progress in stacked FeFET arrays and 3D NVM structures, targeting commercialization by 2028–2030. This article charts a complete trajectory from material to system level, establishing FeFETs as a cornerstone for secure, fast, and energy-efficient next-generation memory.

© 2025 Author(s). All article content, except where otherwise noted, is licensed under a Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/). https://doi.org/10.1063/5.0278057

## I. INTRODUCTION

The rapid evolution of data-centric applications—spanning artificial intelligence (AI), machine learning (ML), edge computing, and the Internet of Things (IoT)—has exposed the limitations of traditional memory architectures. The long-standing separation between processing and memory, often referred to as the “memory wall,” leads to bottlenecks in speed and energy efficiency. Conventional memory technologies, such as DRAM and Flash, while indispensable, face fundamental scaling and performance constraints.

DRAM is volatile and power-intensive, whereas Flash exhibits limited endurance and high write latency. As modern workloads demand higher performance and lower energy consumption, the need for next-generation non-volatile memory (NVM) that combines speed, endurance, and density has become urgent.¹⁻²⁶

Storage-class memory (SCM) has emerged as a promising solution to this challenge by aiming to unify the performance of DRAM with the non-volatility of Flash. Among the contenders—resistive RAM (ReRAM), phase-change memory (PCM), and
magnetoresistive RAM (MRAM)—ferroelectric memories based on hafnium oxide (HfO₂) have gained significant momentum. Traditional ferroelectric materials, such as lead zirconate titanate (PZT), suffer from integration difficulties, large physical thickness, and environmental concerns due to lead content. In contrast, ferro-electricity in doped HfO₂, discovered in 2011, offers scalability up to sub-10 nm thickness, complementary metal-oxide-semiconductor (CMOS) compatibility, and potential integration into back-end-of-line (BEOL) processes, making it uniquely suited for embedded applications.²⁷⁻³⁰

A particularly promising architecture is the ferroelectric field-effect transistor (FeFET), which leverages the remanent polarization of a HfO₂-based gate dielectric to modulate the threshold voltage (V<sub>T</sub>) of a transistor. This enables non-volatile data storage within a standard FET footprint, avoiding the need for external capacitors or complex selector elements. Compared to conventional one-transistor-one capacitor (1T1C) ferroelectric RAM (FeRAM), FeFETs offer simpler cell design, lower read power, and improved scalability. Recent demonstrations of FeFETs show fast switching speeds (<10 ns), low write voltages (<3 V), endurance exceeding 10<sup>9</sup> cycles, and retention times extending over years—figures that are increasingly aligned with the performance requirements of SCM.<sup>31-53</sup>

The flexibility of the FeFET platform has further been expanded through the use of advanced channel materials, such as IWO, MoS<sub>2</sub>, and Indium Gallium Zinc Oxide (IGZO), 3D gate-all-around (GAA) architectures, and BEOL-compatible integration schemes. These advancements not only enable dense memory arrays but also support logic-in-memory (LIM) and compute-in-memory (CIM) operations, which are highly desirable for edge-AI and neuromorphic computing. As such, FeFETs are emerging not only as memory cells but also as multifunctional components in hybrid digital-analog compute systems.<sup>25,54-56</sup>

Despite these advancements, several challenges remain before FeFETs can be widely adopted in commercial products. Key among them are device-to-device variability, wake-up and fatigue phenomena, and temperature-induced degradation. These effects are rooted in the complex switching behavior of ferroelectric domains, interfacial defects, and charge trapping mechanisms. Particularly for analog or multi-level storage applications, variability in coercive field and polarization switching can limit precision and system reliability. Addressing these issues requires deep understanding and control of the material stack, interface quality, and thermal processing conditions.

This review provides a comprehensive synthesis of the state of HfO₂-based FeFET research, from materials science to system-level implications. We begin by summarizing the origins and stabilization of ferroelectric phases in doped HfO₂, including the critical role of dopants, strain, and annealing. We then describe device operation mechanisms, emphasizing threshold voltage modulation, fatigue behavior, and memory window (MW) control. Special attention is given to reliability-limiting phenomena, such as wake-up, imprint, retention loss, and the transition from bulk-limited to interface-limited degradation during cycling.

To complement the technical discussion, we present a landscape of the field, showcasing technology node adoption, device-type distributions (FeFET, FeRAM, FeMFET), and fabrication

methodologies [atomic layer deposition (ALD), physical vapor deposition (PVD), etc.]. These trends provide context for the pace of development and highlight the growing industry interest. Industrial demonstrations from companies, such as Intel, TSMC, Powerchip, and Ferroelectric Memory GmbH (FMC), have shown functional FeFET arrays at 28 and 22 nm nodes, with early-stage 3D FeFET NVDRAM concepts also being explored. These developments support the forecast that commercial FeFET-based SCM products could begin to appear between 2028 and 2030.<sup>19,34,57-59</sup>

Moreover, we critically assess the suitability of FeFETs for CIM and neuromorphic computing applications. While their digital operation is robust, analog precision remains limited due to stochastic switching and V<sub>T</sub> overlap. This positions FeFETs as ideal candidates for binary inference and hybrid digital-analog accelerators, but less suited for high-resolution analog neuromorphic cores without further architectural innovations.

In summary, HfO₂-based FeFETs represent a rare convergence of material innovation, process compatibility, and circuit versatility. Their ability to integrate non-volatile memory directly into logic, with potential for in-memory computing, positions them uniquely for the future of embedded and edge-centric systems. This review aims to capture the breadth and depth of recent FeFET developments, offering researchers and engineers a roadmap toward overcoming current challenges and unlocking the full potential of ferroelectric memory.

## II. FERROELECTRICITY IN HAFNIUM OXIDE

The discovery of ferroelectricity in HfO₂ around 2007 by Qimonda<sup>28,60</sup> challenged the longstanding view that HfO₂ polymorphs were always centrosymmetric and, thus, incapable of exhibiting remanent polarization. Traditional ferroelectric materials, such as lead zirconate titanate [Pb(Zr,Ti)O<sub>3</sub>/PZT] or barium titanate (BaTiO<sub>3</sub>) feature non-centrosymmetric crystal structures in a bulk form. By contrast, bulk HfO₂ maintains a monoclinic structure at ambient pressures, only transforming to tetragonal or orthorhombic polymorphs at elevated pressures or temperatures.<sup>61</sup> Before these breakthroughs, none of its known polymorphs were thought to support intrinsic ferroelectricity.

### A. Microstructures and origin

Ferroelectricity in HfO₂ generally hinges on stabilizing a non-centrosymmetric orthorhombic phase (often denoted Pca2<sub>1</sub>), which emerges in thin films via doping, strain, or electrode-induced stress.<sup>4,62-65</sup> Doping HfO₂ thin films with elements, such as silicon (Si), zirconium (Zr), aluminum (Al), yttrium (Y), and lanthanum (La), significantly influences their crystal structure and ferroelectric properties. Si-doping was the first method reported to demonstrate ferroelectricity in HfO₂, highlighting its potential for industrial applications due to Si's well-established process integration in semiconductor manufacturing. Extensive research into dopant selection has shown that both the microstructure and the ferroelectric characteristics of HfO₂ films depend strongly on dopant type, size, and concentration. Smaller-sized dopants, such as Si and Al, induce transitions between paraelectric, ferroelectric, and antiferroelectric states as their concentration increases.
Specifically, silicon doping leads to antiferroelectric behavior at concentrations exceeding 4.3%, while Al-doping displays ferroelectricity at ≈4.8% and antiferroelectricity at 8.5%. Zr-doping, which can seamlessly replace hafnium (Hf) in the crystal lattice, maintains ferroelectric properties over a wide concentration range, achieving peak remanent polarization (P<sub>r</sub>) at approximately 50% Zr content and shifting toward antiferroelectric behavior beyond 70% Zr.<sup>30,66–69</sup>

In contrast, larger dopants, such as Y, gadolinium (Gd), and La, exhibit distinctly different behavior. With increasing dopant concentration, HfO<sub>2</sub> transitions from an initial paraelectric state to ferroelectric and then reverts to paraelectric, bypassing the antiferroelectric phase observed with smaller dopants. Schroeder et al. comprehensively investigated these differences, attributing the emergence of antiferroelectric properties in films with smaller dopants to a specific monoclinic-orthorhombic-tetragonal-cubic phase transition pathway.<sup>70</sup> Films doped with larger elements bypass the tetragonal phase, following a monoclinic-orthorhombic-cubic transition instead, thus avoiding antiferroelectric behavior. Beyond doped solid solutions, recent research has explored ferroelectric properties in superlattice structures consisting of alternating thin layers, notably HfO<sub>2</sub> and ZrO<sub>2</sub>. Lehninger et al. studied metal-ferroelectric-metal (MFM) superlattice structures with sublayer thicknesses varying from 0.25 to 5 nm, maintaining a total thickness of 10 nm.<sup>71</sup> Unlike solid solution films, pristine superlattice films initially exhibit antiferroelectric-like characteristics, showing pinched hysteresis loops. This behavior is attributed to the

stabilization of in-plane oriented domains or preferential crystallization in an antiferroelectric tetragonal phase. However, these superlattice structures demonstrate rapid wake-up to ferroelectricity, achieving a complete ferroelectric response after fewer than 1000 field cycles. Notably, factors, such as doping concentration, choice of electrode, and substrate type, also significantly influence the crystallization dynamics and ferroelectric characteristics of these multilayered films.<sup>22,71–73</sup>

Figure 1 illustrates key insights into the structural phases and polarization behaviors of HfO₂-based ferroelectrics. Panel (a) depicts various crystal structures of HfO₂ categorized into polar and non-polar phases, emphasizing their symmetry classifications. Panel (b) shows how the ferroelectric orthorhombic phase originates from the tetragonal phase during thermal processing under appropriate capping conditions. Panel (c) demonstrates the evolution of polarization loops from ferroelectric to antiferroelectric behavior with increasing dopant concentration. Finally, panel (d) compares polarization and displacement characteristics, highlighting the shift from piezoelectric behavior at lower dopant levels to an electrostrictive response at higher concentrations, confirming the impact of dopant concentration on functional properties.

## B. Wake-up

A defining feature of ferroelectric HfO₂ is the phenomenon known as the wake-up effect. This effect is characterized by a

<figure><img src="image_10.png" /><figcaption>FIG. 1. (a) Crystal structure variants of hafnium oxide. (b) Evolution of the polar ferroelectric phase during thermal processing. Reproduced with permission from Huan et al., Phys. Rev. B 90, 064111 (2014). Copyright 2014 American Physical Society.<sup>51</sup> (c) Polarization and switching current response of a ferroelectric material to an applied E<sub>ext</sub> as a function of dopant concentration. Reproduced with permission from Böscke et al., Appl. Phys. Lett. 99, 102903 (2011). Copyright 2011 AIP Publishing LLC.<sup>28</sup></figcaption></figure>
<figure><img src="image_11.png" /><figcaption>**FIG. 2.** The wake-up behavior in HfO₂-based ferroelectric devices can vary significantly depending on the stack configuration and processing conditions. Typically, devices are fabricated as metal–ferroelectric–metal (MFM) or metal–ferroelectric–insulator–metal (MFIS) structures. During repeated cycling, a classical wake-up effect is characterized by a gradual transition from an antiferroelectric to a ferroelectric phase. In textured films, the wake-up behavior often features a non-Gaussian distribution of coercive fields. Some devices exhibit narrowing of this distribution without a distinct separation in switching fields, referred to as non-split wake-up. In certain cases, ferroelectricity abruptly emerges in initially dielectric films—this phenomenon is known as sudden wake-up. MFIS stacks often display highly asymmetric hysteresis loops as a signature of their wake-up response. Across all scenarios, the associated displacement currents are typically shown as dotted lines in measurement plots. Reproduced from Lederer et al., Phys. Status Solidi RRL 15, 2100086 (2021). Copyright 2021 Author(s), licensed under a Creative Commons Attribution (CC BY) License.⁸⁷</figcaption></figure>

progressive increase in the $P_r$ with repeated application of an elec-
tric field through cycling.<sup>74-78</sup> Several mechanisms have been pro-
posed to explain this behavior, including the redistribution of
oxygen vacancies ($V_O$), which play a crucial role in charge trans-
port and polarization stability; domain depinning, where ferroelec-
tric domains, initially pinned by defects, begin to move freely,
enhancing polarization; and the gradual transition of non-polar
regions into polar phases, which further contributes to the increase
in remanent polarization. However, this wake-up effect can be
limited by a phenomenon known as fatigue. Prolonged electric
field cycling often leads to a fatigue regime that manifests as a deg-
radation of polarization along with an accumulation of defects, par-
ticularly at grain boundaries. These defects can hinder the mobility
of domain walls and impact the overall ferroelectric properties.
Notably, $V_O$ is integral to the stability of polarization and the
leakage characteristics of the material, especially in ultrathin films.
The presence of a sufficient concentration of $V_O$ is necessary for
maintaining the ferroelectric response, but excessive cycling can
lead to an imbalance that compromises the integrity of the ferro-
electric material and its performance in applications. These vacan-
cies cluster at electrode interfaces during annealing, influencing
device reliability by introducing pinched hysteresis or imprint
effects and increasing leakage through localized conduction paths.
Strain, induced by bottom electrodes or capping layers, is also

pivotal in promoting the metastable orthorhombic ferroelectric
phase over the thermodynamically favored monoclinic or tetrago-
nal phases. Figure 2 summarizes all types of wake-up scenario.<sup>79-86</sup>

C. Deposition technique

The choice of a deposition technique further shapes the ferro-
electric properties of HfO₂ thin films. Methods, such as atomic
layer deposition (ALD), physical vapor deposition (PVD), chemical
solution deposition (CSD), and pulsed laser deposition (PLD),
effectively stabilize the non-centrosymmetric orthorhombic phase
(Pca2₁). ALD commonly uses precursors, such as tetrakis
(ethylmethylamino)-based compounds and chloride-based Hf and
Si sources, with an argon (Ar) gas serving as a carrier and ozone or
water as oxygen sources. Films initially grown via ALD are amor-
phous and typically require rapid thermal annealing (RTA) under a
capping layer to crystallize and induce ferroelectricity due to
thermal strain. PVD techniques provide fine control over parame-
ters, such as sputtering conditions and substrate temperature,
enabling systematic tuning of the film phases and their ferroelectric
properties, thereby aiding fundamental studies of structure-prop-
erty relationships.<sup>79,88</sup>

The crystallization behavior and ferroelectric properties of
ALD-grown HfO₂ films are highly sensitive to both post-deposition
annealing and the choice of capping layers. Thermal expansion mismatch between the ferroelectric film and the capping layer induces strain during annealing, which plays a pivotal role in stabilizing the orthorhombic phase responsible for ferroelectricity. In parallel, the bottom electrode material exerts a strong influence on the film's grain orientation and internal strain profile. For example, Park *et al.* reported that HfO₂ films deposited on (111)-oriented platinum electrodes tend to develop a highly textured (111) grain orientation, whereas those grown on titanium nitride (TiN) electrodes exhibit largely random grain orientations.⁶³ Despite this difference, both electrode types generate significant in-plane tensile strain (≥1.5%), which is instrumental in driving the phase transition from the tetragonal to the orthorhombic phase. Interestingly, films on platinum electrodes require higher tensile strain to achieve this transformation, underscoring the complex interplay between electrode choice, strain engineering, and the resulting ferroelectric response.⁶²⁻⁶⁵,⁸⁹,⁹⁰

### III. TYPES OF FERROELECTRIC MEMORIES: THE CLASSICAL ONES

Classical ferroelectric memories mainly comprise Ferroelectric RAM (FeRAM) (1T-1C cells), FeFETs, and recently explored decoupled Ferroelectric Capacitor-based (FeCAP-based) transistor memories.⁹¹,⁹² FeRAM (1T-1C) employs a transistor coupled with a ferroelectric capacitor. Information storage is achieved by switching the polarization direction of ferroelectric capacitors, typically using materials such as lead zirconate titanate (PZT).⁹³⁻⁹⁵

This approach offers fast operation speeds, robust endurance (>10¹² cycles), excellent retention, and low-power consumption.

However, scalability is hindered by capacitor fabrication complexity and limited integration capability with advanced CMOS nodes.⁸⁴ FeFETs integrate ferroelectric materials directly into the transistor gate stack, modulating $V_T$ via polarization switching. FeFETs offer significant advantages, including simplified architecture, excellent scalability (especially with HfO₂-based films), low-voltage requirements, and direct CMOS integration. Challenges for FeFETs include polarization instability, reduced endurance (10⁷–10⁹ cycles), and the necessity to address phenomena, such as “wake-up” effects and defect-related fatigue.⁹⁶,⁹⁷ Decoupled FeCAP-based memories, also known as FeMFETs, separate the ferroelectric capacitor from the transistor gate through a metal interconnect, achieving memory functionality through capacitive coupling. This design preserves the benefits of FeRAM (high endurance, stable polarization) while providing superior flexibility in fabrication and transistor choice. Decoupled FeCAP memory is less sensitive to transistor gate stack defects and offers improved endurance than FeFETs. Nevertheless, the decoupled structure introduces additional complexity, slightly increased footprint, and potential parasitic capacitance challenges that must be carefully optimized. Figure 3 visually summarizes key distinctions among FeRAM, FeFET, and decoupled 1T1C-FeFET memory designs. While FeRAM relies on a destructive readout mechanism, FeFET and 1T1C-FeFET architectures enable non-destructive read operations, with trade-offs in endurance and voltage requirements. The decoupled 1T1C-FeFET offers a promising balance between endurance and non-volatility by isolating the ferroelectric capacitor from the transistor gate. Table 1 summarizes different types of ferroelectric memories.

<figure><img src="image_12.png" /><figcaption>**FIG. 3.** Schematic comparison of three classical ferroelectric memory architectures: FeRAM (1T-1C), FeFET, and 1T1C-FeFET. Each structure leverages ferroelectric polarization for non-volatile data storage, with differences in read mechanism, endurance, and operating voltage. FeRAM features a destructive read but excellent endurance; FeFET enables non-destructive access at the cost of limited endurance, while the decoupled 1T1C-FeFET design offers both non-destructive read and high endurance, albeit with increased operating voltage and complexity.</figcaption></figure>
<table><caption>TABLE I. Comparison of classical ferroelectric memory types.</caption><thead><tr><th>Feature</th><th>FeRAM</th><th>FeFET</th><th>FeMFET (1T-1C)</th></tr></thead><tbody><tr><th>Structure</th><td></td><td></td><td></td></tr><tr><th>Scalability</th><td>Moderate</td><td>High</td><td>Moderate to high</td></tr><tr><th>Integration complexity</th><td>Moderate to high</td><td>Low</td><td>Moderate</td></tr><tr><th>Non-volatility</th><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><th>Endurance</th><td>Excellent (&gt;10<sup>12</sup>)</td><td>Moderate (10<sup>7</sup>-10<sup>9</sup>)</td><td>High (10<sup>10</sup>-10<sup>12</sup>)</td></tr><tr><th>Read/write speed</th><td>Fast</td><td>Fast</td><td>Fast</td></tr><tr><th>Power consumption</th><td>Low</td><td>Very low</td><td>Low</td></tr><tr><th>Primary challenges</th><td>Fatigue, scaling issues</td><td>Wake-up, endurance, defects</td><td>Parasitics, layout complexity</td></tr></tbody></table>

# IV. FERROELECTRIC FIELD-EFFECT TRANSISTOR

## A. Fabrication and operating principle

A FeFET is a single-transistor non-volatile memory device that integrates a ferroelectric material into the gate stack, allowing the transistor's $V_T$ to shift based on the polarization state of the ferroelectric film. This concept dates back to the late 1950s at Bell Labs, where researchers first recognized that the ferroelectric $P_r$ could modulate the channel conductivity of a semiconductor layer in a non-destructive manner.²⁷,⁹⁸⁻¹⁰¹ Modern FeFETs typically employ $HfO_2$-based ferroelectrics—especially Si-doped $HfO_2$ (HSO)—due to their CMOS compatibility, scalability below 10 nm, and relatively low operating voltages.⁵¹,⁷⁸

In FeFETs, a thin $HfO_2$-based ferroelectric layer is integrated into the gate stack, sandwiched between a metal gate and a 2 nm interfacial layer (IL) [either thermally grown silicon dioxide ($SiO_2$) or rapid thermal annealing (RTA)-formed silicon oxynitride (SiON)] atop the Si channel (Fig. 4). This simple structural tweak introduces non-volatile behavior: by applying a sufficiently large positive gate voltage, the ferroelectric dipoles align “up” ($P_r \uparrow$), injecting bound charge into the channel and shifting the device into a low-threshold (LVT) “programmed” state. Reversing the bias flips the dipoles “down” ($P_r \downarrow$), depleting the channel and creating a high-threshold (HVT) “erased” state. Crucially, both states persist without power, so the FeFET remembers its last setting even after the gate bias is removed.¹⁰²

Reading is just as straightforward and truly non-destructive: a moderate gate sweep or pulse—kept below the coercive field— probes the drain current without flipping the polarization. A strong drain current signals LVT (a logical “1”), whereas a weak current indicates HVT (a logical “0”). Thanks to the nanosecond-scale switching speeds and modest write voltages (1–5 V) achievable in

doped $HfO_2$, FeFETs offer high-speed, energy-efficient memory operations fully compatible with standard CMOS processing.¹⁰³,¹⁰⁴

Figure 4(a) demonstrates the process flow of fabricating standard FeFET devices. The FeFET devices evaluated in this work were fabricated on 300 mm bulk Si wafers utilizing CMOS-compatible industry-standard manufacturing processes to ensure scalability and reproducibility. The devices feature gate lengths and widths of 1 µm, yielding an active area of 1 µm². A 2 nm-thick interfacial layer was introduced between the Si channel and the ferroelectric stack, employing either thermally grown $SiO_2$ or SiON formed via RTA. The interfacial engineering is critical, as it significantly influences defect densities and overall device stability. The 10 nm HSO ferroelectric layer was deposited using ALD at a chamber temperature of 300 °C. Hafnium tetrachloride ($HfCl_4$) and silicon tetrachloride ($SiCl_4$) precursors were sequentially cycled in a 16:1 ratio, with water ($H_2O$) serving as the oxidant. ALD was selected to ensure sub-nanometer control over film thickness and superior conformality, which are essential for achieving uniform ferroelectric properties across large wafer areas.⁵³,¹⁰⁵

Following ferroelectric layer formation, a titanium nitride (TiN) top electrode was deposited via PVD, and an amorphous silicon capping layer was subsequently formed by CVD. To activate dopants and crystallize the HSO layer into its desired ferroelectric orthorhombic phase, a RTA step was executed at 1050 °C for 5 s. The resulting gate stack integrity and the individual layer thicknesses were verified through cross-sectional transmission electron microscopy (TEM), as presented in Fig. 4(a). The fabricated devices provided a robust platform to systematically study the impact of interfacial engineering and ferroelectric quality on the electrical performance and reliability of advanced FeFET technologies.
<figure><img src="image_13.png" /><figcaption>FIG. 4. (a) Fabrication schematic and process flow of FeFETs incorporating a 10 nm HSO ferroelectric layer. The inset shows a high-resolution cross-sectional TEM image of the final device stack, highlighting the gate dielectric and interfacial layers. (b) Transfer characteristics of devices with a SiON interfacial layer exhibit an average memory window of approximately 1.5 V between the programmed and erased states, while (c) those with a SiO₂ interface show a reduced memory window of around 1.0 V under identical conditions. (d) Endurance characteristics for SiO₂- and SiON-integrated FeFETs under ±6 V stress highlight distinct fatigue behaviors over cycling. (e) Retention characteristics of the high- and low-V<sub>T</sub> states confirm stable non-volatile performance, with the SiON interface maintaining a consistently wider voltage margin. Reproduced from Raffel et al., ACS Appl. Electron. Mater. 4, 5292–5300 (2022). Copyright 2022 Author(s), licensed under a Creative Commons Attribution (CC BY) License.⁵³</figcaption></figure>

## B. Statistical variations in HfO₂-based ferroelectric memories

Over the past few years, statistical variation has emerged as a key bottleneck in scaling HfO₂-based FeFETs for memory arrays. While individual devices can demonstrate multiple stable $V_T$ states under ideal conditions, array-level measurements across 30 identically sized FeFETs reveal that device-to-device fluctuations—stemming from random coercive field distributions, ferroelectric-dielectric phase mixing, and interface trapping—lead to significant overlap in $V_T$ distributions. As shown in Fig. 5, this overlap restricts reliable operation to binary states, particularly when the temperature rises beyond 85–100 °C, causing further shrinkage of the memory window. These findings reflect a broader trend in the

field: despite promising multilevel switching in isolated cells, practical system-level FeFET deployment—especially for SCM and in-memory computing—must account for variation-aware design to ensure long-term functional stability.

## C. Defect analysis in FeFET: Low-frequency analysis

It is widely acknowledged that the function of FeFETs can be significantly influenced by charge trapping, mainly arising from the imbalance between the remnant polarization charge ($P_r$) and the maximum permissible surface carrier density ($N_c$) in the silicon channel. The polarization level in HfO₂ is approximately 10–30 µC/cm², implying a $P_r$ capable of inducing a surface charge density near 10¹⁴ cm⁻² upon programming. However, the $N_c$ limit

<figure><img src="image_14.png" /><figcaption>FIG. 5. (a) Voltage pulse sequence used to characterize long-term potentiation (LTP) and depression (LTD) behavior in FeFETs. (b) Measured LTD and (c) LTP characteristics across 30 devices show that threshold voltage distributions begin to overlap due to device-to-device variation, limiting reliable multilevel operation. Reproduced from Sunil et al., Adv. Intell. Syst. 6, 2300461 (2024). Copyright 2024 Author(s), licensed under a Creative Commons Attribution (CC BY) License.¹⁰²</figcaption></figure>

16 JUNY 2025 16:20:42
in a conventional Si-channel MOSFET is about 10¹³ cm⁻². As a result, trapped electrons—of the order of 10¹⁴ cm⁻²—accumulate near the HfO₂-Si interface to compensate the polarization mismatch.¹⁰⁶ To mitigate bond stress and assist in charge compensation, dielectric interfacial layers are commonly introduced in MFIS (metal-ferroelectric-insulator-semiconductor) stacks. Yet, this introduces high internal electric fields, promotes charge trapping, and ultimately degrades device performance. While dopant effects and interfacial engineering have been explored, comprehensive studies addressing the interplay of doping, low-frequency noise (LFN), and cycling stress remain sparse. This work investigates LFN characteristics in HSO-based FeFETs, emphasizing the effects of dopant concentration, interfacial layers, and write endurance.

LFN in semiconductor devices typically arises from two mechanisms: carrier number fluctuations (ΔN_c) and mobility fluctuations (Δμ). Carrier number fluctuations stem from charge trapping and de-trapping at the oxide-semiconductor interface, which modulates inversion charge and, thus, the drain current (I_D). Mobility fluctuations arise from Coulomb scattering induced by trapped charges. Consequently, both phenomena contribute to the LFN spectrum, whose drain current power spectral density (PSD) is expressed as¹⁰⁷⁻¹¹⁰

$$S_{ID} \propto f^{-\gamma}. \qquad (1)$$

The equivalent input gate voltage noise ($S_{V_g}$) relates to $S_{ID}$ via the transconductance $g_m$,

$$S_{V_g} = \frac{S_{ID}}{g_m^2} = S_{V_{fb}} \left( 1 + \frac{\Omega I_D}{g_m} \right)^2, \qquad (2)$$

where $S_{V_{fb}}$ is the flatband voltage fluctuation noise and $Ω$ is the mobility fluctuation factor.

Trap densities are categorized as follows:

* **Bulk oxide trap density ($D_{ox}$):** Defects throughout the oxide contributing to long-term charge storage, endurance loss, and memory window closure.

* **Interface trap density ($D_{it}$):** Localized traps at the oxide-semiconductor interface that affect carrier transport.

* **Total trap density ($D_t$):**

$$\lambda N_t = D_t = D_{ox} + D_{it}. \qquad (3)$$

While both $D_{ox}$ and $D_{it}$ influence LFN, $D_{ox}$ primarily governs ΔN_c, and $D_{it}$ impacts Δμ. The flatband voltage fluctuation noise is given by

$$S_{V_{fb}} = \frac{q^2 k T \lambda (N_t + P_{fluc})}{f^\gamma W L C_{ox}^2}, \qquad (4)$$

where $λ$ is the tunneling attenuation length, $P_{fluc}$ denotes polarization fluctuation noise unique to FE materials,¹¹¹ W, L are device width and channel length, and $C_{ox}$ is the oxide capacitance per unit area.

The noise exponent $γ$, reflecting the frequency dependence of LFN and the defect distribution, is expressed as

$$\gamma = \frac{kT \alpha_{sc} C_{ox}}{q N_t}, \qquad (5)$$

where $α_{sc}$ is the Coulomb scattering coefficient. A higher $α_{sc}$ in FeFETs signifies enhanced scattering due to charge trapping, supporting Δμ dominance in LFN. In FeFETs, LFN behavior differs between erase and program states. The erase state, characterized by a positive compensation charge, reduces Coulomb scattering, making ΔN_c dominant. Conversely, the programmed state, with a negative compensation charge, enhances Coulomb interactions and increases Δμ, consistent with larger $α_{sc}$ values. Extracting $α_{sc}$ involves analyzing the square root of $S_{V_g}$ as a function of $I_D/g_m$.¹¹²,¹¹³

LFN analysis is, thus, a sensitive probe of trap dynamics in FeFETs. Studies have shown that SiON interfacial layers yield lower LFN than SiO₂, especially in programmed states.¹¹⁴⁻¹¹⁸ This is attributed to stronger Si-N bonding in SiON, which passivates dangling bonds more effectively, reducing $D_{it}$ and suppressing trap-assisted conduction. Under prolonged write cycling, a shift from bulk ($D_{ox}$) to interface trap ($D_{it}$) dominance occurs. This defect evolution is evidenced by increasing subthreshold slopes and threshold voltage ($V_{th}$) shifts toward higher values, indicating trap level movement closer to the conduction band. These shifts contribute to memory window (MW) narrowing due to interface screening of polarization. The results underscore the importance of interfacial defect control for ensuring long-term endurance and stable FeFET performance (Figs. 6 and 7).

While FeFET reliability has been widely studied, LFN variations under endurance cycling remain comparatively underexplored. The study referenced here¹¹⁴⁻¹¹⁸ addresses this gap by systematically investigating the interplay of dopant composition, interfacial layer properties, and write cycling effects in FeFETs fabricated using a high-κ metal gate (HKMG)-compatible process flow. This ensures technological relevance and allows robust benchmarking across diverse material configurations. Although earlier efforts have individually optimized ferroelectric films and interfacial layers, the combined impact of dopants, noise behavior, and endurance degradation remains less understood.

By analyzing the effects of Si-doping in HfO₂, variations in interfacial layers, and their dynamic response to electrical cycling, the study delivers a holistic view of defect evolution in FeFETs. LFN measurements uncover how dopant concentration and interfacial bonding influence the noise spectrum, serving as sensitive probes of underlying reliability phenomena. Notably, the findings establish a direct correlation between endurance stress and a shift from bulk- to interface-dominated defect behavior—an insight vital for advancing FeFET-based non-volatile memory and neuromorphic computing technologies. These results go beyond conventional static performance metrics, highlighting the critical importance of integrated materials and process co-optimization to ensure long-term device stability and performance.
<figure><img src="image_15.png" /><figcaption>FIG. 6. (a) Normalized drain current noise spectral density ($S_{ID,norm}$) as a function of gate overdrive voltage shows minimal variation across doping ratios (1:14, 1:16, and 1:20), indicating stable trap energy levels near $V_{TH} + 0.1$ V, but a noticeable increase at higher overdrives. (b) Gate voltage noise spectral density ($S_{VG}$) reveals enhanced noise contributions with increased doping, underscoring the role of defect interactions and trap density. (c) Schematic of band alignment and polarization switching in FeFET stacks incorporating HSO, a TiN gate, and an interfacial layer (IL), illustrating trap accumulation near the IL during cycling. (d) LFN evolution under erase and program conditions shows cycle-dependent degradation, particularly beyond 4000 cycles, attributed to increased interface trap activity. (e) Energy band diagrams across three operational states—pristine, wake-up, and fatigue—highlight progressive trap migration and structural reorganization at the interface. In the pristine state, deep-level traps are located within the IL; during wake-up, redistribution and partial activation of interfacial traps occur; fatigue results in pronounced trap accumulation that screens polarization, deteriorating device performance. Reproduced with permission from Raffel et al., IEEE Trans. Electron Devices 72(6), 3307-3313. Copyright 2025 IEEE.¹⁰⁵</figcaption></figure>

# V. APPLICATIONS OF FeFETs

## A. FeFET as storage-class memory

The integration of HSO-based FeFETs into SCM architectures has attracted considerable attention in recent years. Positioned between DRAM and NAND flash in the memory hierarchy, SCM demands non-volatility, low latency, and endurance at elevated temperatures—criteria that silicon FeFETs are increasingly able to meet. In the study considered here,¹¹⁴⁻¹¹⁸ FeFET-based content-addressable memory (CAM) arrays were fabricated using a 28 nm HKMG process.

Device characterization under temperatures up to 120 °C revealed that while memory window narrowing and endurance degradation occur at elevated temperatures, binary operation remains highly robust. Through a 1FeFET–1T CAM design employing

cascoded current limiters and optimized read voltages, reliable search operations were sustained despite $V_T$ shifts.

These findings underscore the viability of binary FeFET arrays for high-speed, temperature-resilient SCM applications, particularly where long-term data retention is prioritized over frequent rewriting. Complementary studies on multilevel FeFET arrays¹¹⁹ highlight the role of current percolation paths (CPPs) in governing switching behavior and variability. While multilevel programming enables higher density, it remains more sensitive to microstructural variations and field-driven domain evolution, complicating operation at scaled nodes and elevated temperatures. Accordingly, binary FeFET operation currently offers the most reliable and manufacturable pathway toward SCM adoption. Taken together, silicon FeFETs demonstrate fast switching, high on/off ratios, and excellent compatibility with CMOS back-end-of-line processes. The ability to sustain robust
<figure><img src="image_16.png" /><figcaption>FIG. 7. Characterization of FeFET-based multi-level storage and temperature dependence. (a) Measured $I_D-V_G$ characteristics across gradual programming cycles, illustrating the continuous threshold voltage modulation and multiple distinct conductance states enabled by ferroelectric switching. The inset shows the readout strategy using fixed $V_{read}$ and $I_{read}$ thresholds. (b) Histogram of extracted programming states ("00," "01," and "10," "11") demonstrating clear separation at optimized read conditions ($I_{read}$ and $V_{read}$), supporting robust 2-bit storage capability. (c) Successful mapping of an 81-cell FeFET array encoding a grayscale Mona Lisa image into 2-bit-per-cell levels, demonstrating practical multi-level retention and write-verify robustness. Subfigures (a)–(c) reproduced with permission from Müller *et al.*, IEEE Electron Device Lett. 44, 757–760. Copyright 2023 IEEE.⁴⁷ (d) Temperature-dependent $I_D-V_G$ characteristics showing progressive shrinkage of memory window (MW) from ~1.2 V at 25 °C to ~0.5 V at 120 °C due to thermal effects on polarization and carrier mobility. (e) Extracted $V_T$ as a function of positive and negative programming pulse amplitudes under different temperatures, highlighting reduced switching efficiency and a narrower programmable range at elevated temperatures. Subfigures (d)–(f) are reproduced from Sunil *et al.*, Adv. Intell. Syst. 6, 2300461 (2024). Copyright 2024 Author(s), licensed under a Creative Commons Attribution (CC BY) License.¹⁰²</figcaption></figure>

binary operations under thermal stress positions FeFET-based CAM cells as strong candidates for future SCM solutions, particularly in edge computing and data-intensive applications.

The demonstrated ability to encode multiple stable conductance states and sustain memory functionality under elevated temperature conditions highlights the strong potential of FeFETs for next-generation storage and computing systems. In SCM applications, multi-level storage enables higher density without sacrificing access speed, offering a scalable solution to bridge the performance gap between DRAM and NAND Flash. Moreover, the inherent non-volatility, low programming voltage, and fast switching of FeFETs make them attractive candidates for energy-efficient edge computing architectures. From a neuromorphic perspective, the gradual modulation of $V_T$ and robust state retention at varying temperatures are essential for implementing synaptic weight

updates and stable inference in non-ideal environmental conditions. These findings reinforce that careful optimization of material stacks and programming schemes can unlock reliable multi-bit FeFET operation, paving the way toward practical deployment in high-speed, thermally stable memory and in-memory computing systems.

## B. Assessment of FeFETs for in-memory computing and neuromorphic applications

FeFETs have emerged as promising candidates for logic-compatible non-volatile memories, with increasing attention toward their use in CIM and neuromorphic systems (Fig. 8). Their low-voltage operation, fast switching speed, and full CMOS compatibility give FeFETs a natural advantage for embedded and
<figure><img src="image_17.png" /><figcaption>FIG. 8. (a) Schematic diagram of the ADC-integrated FeFET memory array, including circuit layout and an optical micrograph of the fabricated structure. (b) Voltage configuration applied along bitlines (BLs), wordlines (WLs), and sourcelines (SLs) during the write operation, enabling targeted programming of selected cells. (c) Read voltage protocol applied along the BL, WL, and SL for selective bit-wise readout, while ensuring non-targeted cells remain inactive. (d) Measured output current ($I_{BL}$) vs wordline voltage ($V_{WL}$) from an 8 × 8 crossbar sub-array, demonstrating parallel MAC behavior. (e) Precision MAC operation achieved through embedded current-limiters at the tile edge, ensuring linear current response and high accuracy. (f) Cumulative distribution function (CDF) of $I_{BL}$ across multiple tiles confirms tight distribution and array-level uniformity. (g) Retention characteristics of programmed current levels, stable up to 5 × 10⁻⁵ s and extrapolated for 10-year non-volatile operation. (h) Measured $I_{DS}$-VGS characteristics of a 1FeFET-1R device programmed into four distinct conductance states. (i) Input voltage waveform applied to the FeFET gate to sequentially trigger readout of stored states. (j) Measured output current ($I_{DS}$) responses corresponding to each state, exhibiting time-staggered rise patterns reflecting analog multiply behavior. (k) Simulated $I_{DS}$-VGS and output currents validate experimental results and demonstrate high-speed, accurate single-cell multiply operation. Reproduced from De et al., IEEE Electron Device Lett., 43, 2081-2084 (2022). Copyright 2022 Author(s), licensed under a Creative Commons Attribution (CC BY) License.¹⁰³ Soliman et al., Nat. Commun. 14, 6348 (2023). Copyright 2023 Author(s), licensed under a Creative Commons Attribution (CC BY) License.¹¹⁹</figcaption></figure>
<table><caption>TABLE II. Benchmarking of FeFETs compared to other non-volatile memory technologies. Adapted from Ref. 135.</caption><thead><tr><th>Performance metrics</th><th>NOR Flash</th><th>NAND Flash</th><th>RRAM</th><th>PCM</th><th>FeRAM</th><th>Si-FeFET</th></tr></thead><tbody><tr><td>On/off ratio</td><td>10<sup>4</sup></td><td>10<sup>4</sup></td><td>10<sup>2</sup></td><td>10<sup>4</sup></td><td>2</td><td>10<sup>6</sup></td></tr><tr><td>Write voltage</td><td>&lt;10 V</td><td>&gt;10 V</td><td>&lt;3 V</td><td>&lt;3 V</td><td>&lt;1.5 V</td><td>&lt;5 V</td></tr><tr><td>Write energy (/bit)</td><td>100 pJ</td><td>10 fJ</td><td>0.1-1 pJ</td><td>10 pJ</td><td>100 fJ</td><td>100 fJ</td></tr><tr><td>Write time</td><td>1-10 &mu;s</td><td>0.1-1 ms</td><td>&lt;10 ns</td><td>&lt;10 ns</td><td>&lt;10 ns</td><td>100 ns</td></tr><tr><td>Read time</td><td>50 ns</td><td>10 &mu;s</td><td>&lt;10 ns</td><td>&lt;10 ns</td><td>&lt;10 ns</td><td>&lt;10 ns</td></tr><tr><td>Endurance</td><td>10<sup>5</sup></td><td>10<sup>4</sup></td><td>10<sup>5</sup></td><td>10<sup>6</sup></td><td>10<sup>12</sup></td><td>10<sup>8</sup></td></tr><tr><td>Retention</td><td>Long</td><td>Long</td><td>Medium</td><td>Long</td><td>Medium</td><td>Long</td></tr><tr><td>Drift</td><td>No</td><td>No</td><td>Weak</td><td>Yes</td><td>No</td><td>No</td></tr><tr><td>Integration density</td><td>High</td><td>Very high</td><td>Moderate</td><td>High</td><td>High</td><td>Very high</td></tr></tbody></table>

edge-AI applications. However, their suitability for analog or vector-matrix multiply (VMM) operations remains limited by intrinsic device-level challenges. While individual FeFETs can exhibit multiple $V_T$ states under ideal conditions, array-level measurements reveal significant device-to-device variation, stemming from random coercive field distributions, interfacial defects, and material non-uniformities.

This leads to substantial overlap in $V_T$ distributions, restricting practical operation to binary or low-resolution multibit states. In neuromorphic applications requiring stable analog weight updates, this variation undermines precision learning and long-term stability. Temperature sensitivity is another critical barrier. The memory window (MW) shrinks with increasing temperature due to reductions in remanent polarization and coercive field, further degrading analog programmability. Additionally, endurance under frequent update cycles is lower than in ReRAM or MRAM, and fatigue-related degradation can impact training accuracy in learning systems.

Nevertheless, FeFETs show great potential for read-heavy inference engines, binary neural networks, and secure, low-power IMC applications, especially in edge devices where tight integration with logic is essential. Industry demonstrations, such as Intel's embedded FeFET at 22 nm and recent 3D FeFET NVDRAM prototypes, highlight the feasibility of FeFETs for SCM and CIM readout accelerators. However, for analog neuromorphic cores or high-resolution IMC, substantial material and architectural innovations are still required. In summary, FeFETs are approaching maturity for digital CIM and binary neural inference but require further improvement in variability control and fatigue resilience to compete with ReRAM or PCM in analog IMC systems.<sup>37,38,120-133</sup>

## VI. BENCHMARKING, RECENT DEVELOPMENTS, TRENDS, AND APPLICATIONS OF FeFETs TOWARD STORAGE-CLASS MEMORY AND BEYOND

In parallel with academic advancements, industry leaders, such as Intel, TSMC, and GlobalFoundries, have actively pursued FeFET research, exploring its integration into advanced CMOS nodes for embedded non-volatile memory and compute-in-memory applications. Ferroelectric Memory GmbH (FMC), a key player in this domain, has reported significant milestones in endurance and retention performance, with a growing patent portfolio targeting

logic-compatible FeFETs. Powerchip Semiconductor Manufacturing Corp. (PSMC) and other foundry partners have outlined roadmaps positioning FeFET-based SCM as a potential replacement for SRAM blocks in AI accelerators and edge devices. Of particular note is the demonstration of a dual-layer 3D NVDRAM FeFET array with near-DRAM bandwidth and retention robustness, setting the stage for pre-commercial deployment. Based on current technology readiness levels, the first commercial-grade FeFET-based SCM products are expected to enter the market between 2028 and 2030.<sup>124,134</sup>

To contextualize the recent advancements in FeFET technologies, it is helpful to benchmark their performance against existing NVM solutions. Table II provides a comparative overview of key performance metrics across various memory types, including NOR Flash, NAND Flash, RRAM, PCM, FeRAM, and SOT-MRAM. As shown, Si-based FeFETs offer favorable characteristics, such as low write voltages (below 5 V) and fast access times, achieving sub-100 ns for both write and read operations. Their data retention is also comparable to that of traditional Flash memories. However, endurance remains a notable challenge, typically limited to around 10<sup>8</sup> cycles, and the integration density is still lower compared to more mature technologies. These bottlenecks have motivated extensive research efforts focused on material innovation, device engineering, and architectural optimization.

FeFETs have advanced rapidly from an emerging memory concept to a leading contender for SCM, CIM, and security-critical applications. Historically, Si-based FeFETs demonstrated nonvolatile switching but suffered from limitations in endurance, MW degradation, and relatively high write voltages. Recent material, device, and system-level innovations have addressed many of these challenges, opening new application horizons. Material engineering has been pivotal. The adoption of oxide semiconductor (OS) channels, such as IGZO, indium tin oxide (ITO), and amorphous indium oxide,<sup>70,136</sup> has enabled sub-1 V programming and enhanced channel mobility, while novel defect passivation strategies have reduced $V_{TH}$ instability under bias stress. The integration of two-dimensional materials, such as $MoS_2$,<sup>137</sup> into FeFET channels has further pushed switching voltages below 1 V, offering a path to extremely low-power embedded non-volatile memories.

Simultaneously, new ferroelectric material stacks—such as La: HZO<sup>136</sup> and metal-doped interfacial layers—have stabilized polarization switching, improved endurance beyond 10<sup>10</sup> cycles, and minimized $V_O$ generation. Advanced engineering of asymmetric stacks
and tunnel dielectric inserts<sup>56,138</sup> have achieved record-high capaci-
tive memory windows (>8 at 0 V) and decoupled read and write
endurance, crucial for practical CIM operations. Architectural inno-
vations have further expanded FeFET potential. Charge-trap
enhanced FeFETs<sup>139</sup> and multi-gate FeFETs<sup>140</sup> enable spatiotempo-
ral learning capabilities, while encrypted NAND FeFET arrays<sup>141</sup>
introduce lightweight, *in situ* security for CIM systems—allowing
direct matrix-vector multiplication on encrypted weights with
minimal overhead. These developments support both secure
storage and edge inference.

On the system level, FeFET-based 32 Gb dual-layer 3D
NVDRAM<sup>124</sup> demonstrates near-DRAM performance suitable for
AI workloads, while pulse-based non-destructive read schemes<sup>138</sup>
ensure high read endurance (&gt;10<sup>11</sup> cycles), enhancing longevity for
lifelong learning and retraining applications. FeFETs have also
shown significant promise in neuromorphic computing. Reservoir
computing architectures utilizing HZO-based FeFETs,<sup>142</sup> program-
mable V<sub>T</sub> FeFET clusters for power-efficient learning,<sup>143</sup> and
hybrid FeRAM-RRAM synaptic circuits<sup>144</sup> illustrate FeFETs'
unique ability to combine storage, learning, and inference within a
compact, low-power framework. The convergence of advanced
materials, scalable integration flows, and smart circuit design has
brought HfO<sub>2</sub>-based FeFETs to the threshold of commercial reality.
Backed by major industry players and validated through foundry-
scale prototypes, FeFETs are no longer just academic milestones—
they are becoming viable memory solutions. In the next three to
five years, we expect to see FeFETs move from cleanroom test
benches into real-world deployment, especially in embedded SCM
and edge-AI systems.

What sets FeFETs apart is their ability to combine fast switch-
ing, low-voltage operation, and CMOS compatibility in a single
device stack. They offer a credible path to bridging the long-
standing gap between DRAM speed and Flash non-volatility, while
also opening doors to new computing paradigms. Whether it is
enabling secure in-memory operations, accelerating AI inference at
the edge, or powering neuromorphic cores, FeFETs bring both per-
formance and versatility. In short, they are not just ready for the
future—they are beginning to shape it.

VII. CONCLUDING PERSPECTIVES ON FeFETs FOR STORAGE-CLASS MEMORY

HfO₂-based ferroelectric field-effect transistors have matured
rapidly from a research curiosity to serious contenders for next-
generation storage-class memory and compute-in-memory systems.
This review has outlined how careful material innovation—includ-
ing doping strategies, interfacial engineering, and deposition tech-
niques—has enabled robust ferroelectric behavior in ultra-thin
films compatible with CMOS manufacturing. Alongside material
advances, device-level optimizations in endurance, retention, and
LFN behavior have significantly improved the reliability and opera-
tional stability of FeFET architectures. Benchmarking studies posi-
tion Si-FeFETs favorably against traditional non-volatile memories,
such as NAND Flash, and emerging competitors, such as RRAM
and PCM, especially in terms of write voltage, switching speed, and
integration potential. Nevertheless, endurance degradation and
integration density remain areas requiring continued attention.

Recent developments, including the integration of two-dimensional channels (e.g., MoS₂), engineering of asymmetric stacks, pulse-based non-destructive readout schemes, and hybrid FeFET-RRAM architectures, further expand the application landscape of FeFETs toward secure storage, neuromorphic computing, and edge-AI acceleration. These innovations bridge the long-standing performance gap between volatile and non-volatile memories while opening new opportunities for energy-efficient, high-bandwidth computing. Collectively, HfO₂-based FeFETs emerge as strong candidates to meet the escalating demands of future data-centric applications. Continued interdisciplinary efforts in materials science, device physics, and circuit-level co-optimization will be pivotal in translating FeFET-based SCM and CIM architectures into widespread commercial reality.

ACKNOWLEDGMENTS

This work was supported in part by the Taiwan
Semiconductor Research Institute (TSRI) under Project No.
JDP114-Y1-002 and in part by the National Science and
Technology Council (NSTC), Taiwan, under Grant Nos. NSTC
114-2222-E-007-001 and NSTC 114-2811-E-007-001. The authors
gratefully acknowledge the support and infrastructure provided by
TSRI and NSTC that enabled this research. I acknowledge the use
of Grammarly and ChatGPT for English language refinement only.
However, we have not used any AI tools or technologies to generate
this manuscript.

AUTHOR DECLARATIONS

Conflict of Interest

The authors have no conflicts to disclose.

Author Contributions

Agniva Paul and Gautham Kumar contributed equally to this
work.

**Agniva Paul:** Conceptualization (equal); Data curation (equal); Formal analysis (equal); Investigation (equal); Methodology (equal); Writing – original draft (equal). **Gautham Kumar:** Conceptualization (equal); Supervision (equal); Writing – review & editing (equal). **Apu Das:** Conceptualization (equal); Data curation (equal); Investigation (equal); Methodology (equal); Writing – original draft (equal); Writing – review & editing (equal). **Guilhem Larrieu:** Writing – review & editing (equal). **Sourav De:** Conceptualization (equal); Funding acquisition (equal); Project administration (equal); Resources (equal); Supervision (equal); Writing – review & editing (equal).

DATA AVAILABILITY

Data sharing is not applicable to this article as no new data
were created or analyzed in this study.
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