# A Bayesian System with Neuron Clocks for Biosignal Classification

Zonglong Li, Laurie E Calvet

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Zonglong Li, Laurie E Calvet. A Bayesian System with Neuron Clocks for Biosignal Classification. 2026. [hal-05525429](https://hal.science/hal-05525429v1)

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# A Bayesian System with Neuron Clocks for Biosignal Classification

Zonglong Li, Member, IEEE, Laurie E. Calvet, Senior Member, IEEE

**Abstract**— A compact Bayesian system for end-to-end inference that uses time-encoded probabilistic computing is presented. The architecture integrates (1) a neuron clocking scheme for timing sequential phases of the system, (2) a feature-extraction module based on rate-coding information with neuron circuits, (3) a circuit able to extract likelihoods from a probability distribution and then calculate Bayes' rule and (4) a race-to-threshold winner-take-all circuit that can drive downstream actuation circuits. All circuits were implemented and simulated at the transistor level in TSMC 130 nm CMOS using a 1.0 V supply. The system was benchmarked using a two-category sleep-stage classification task, and achieved an accuracy of 80.8%, which closely matches the 81.5% result of an equivalent inference in software. The complete architecture uses less than 150 transistors, making it suitable for ultra-low-power edge biosignal processing.

**Index Terms**— Bayesian inference, time encoding, stochastic computing, neuromorphic circuits, biosignal classification, sleep stage classification, EOG

## I. INTRODUCTION

In the context of ageing populations and overstretched healthcare systems [1], wearable biosensors are emerging as critical tools for continuous health monitoring [2]. Conventional biosignal processing typically relies on front-end processing for filtering and amplifying, followed by analog-to-digital conversion (ADC) and transmission to a device or the cloud for analysis by machine learning algorithms [3]. While these implementations are significantly streamlined compared to conventional computers, there is a growing need for developing alternative architectures that can improve the energy efficiency, latency and overhead for biosignal monitoring.

This paper introduces a new end-to-end architecture that employs a Bayesian inference system in a probabilistic computing paradigm. Bayesian networks in hardware have recently attracted interest because their operations can map

naturally into hardware and enable interpretable inference [4]. It uses Bayes' theorem to determine the posterior probability $P(C|F)$ of a class C to occur given the observed feature F, expressed as:

$$P(C|F) = \frac{P(C)P(F|C)}{P(F)}, \quad (1)$$

where $P(C)$ represents the prior probability of class C, and $P(F|C)$ is the likelihood probability of observing feature F given class C. $P(F)$, sometimes called “model evidence”, is the same for all classes and is often omitted to simplify the calculation. The system explored here consists of neuromorphic elements, including artificial neuron circuits for feature extraction [5], time encoding [6] and clock signals, and synaptic circuits that provide the conversion of the features into likelihoods based on a pre-determined distribution [7]. In addition, a winner-take-all (WTA) circuit that functions as a race to threshold [8] manner and can be used for stochastic computing is introduced. All components operate in the mixed-signal domain, eliminating the need for a clock and reducing the system overhead.

Probabilistic reasoning is particularly relevant in health monitoring applications, where clinical decisions often involve weighing probabilities, such as the likelihood of a disease given the observed symptoms. In addition, Bayesian models are inherently explainable, making them well suited for diagnostics where transparent reasoning is very important. The proposed architecture is therefore validated on a binary sleep-stage classification task [9], demonstrating performance comparable to a software classification of Bayesian inference. While prior work has focused on the circuit-level realization of probabilistic primitives such as likelihood distributions [7], this paper addresses the system-level integration, timing, and decision mechanisms required to realize a complete Bayesian inference engine in hardware.

<footnote>Zonglong Li is with LPICM, CNRS, Ecole Polytechnique, Institut Polytechnique de Paris, Palaiseau (91120), France and Université Paris-Saclay, Gif-sur-Yvette, France. (e-mail: zonglong.li@polytechnique.edu)</footnote>

<footnote>Laurie E. Calvet is with LPICM, CNRS-Ecole Polytechnique, Institut Polytechnique de Paris, Palaiseau (91120), (e-mail: laurie.calvet@cnrs.fr).</footnote>

<footnote>This work was funded by ANR contract ANR-21-FAI1-0006-01 and the European Union under the European Innovation Council (EIC) / Horizon Europe program (BAYLEX, Grant Agreement No. 101099555). In accordance with the Horizon Europe open-access policy, the authors retain the right to make the accepted manuscript publicly available under a CC BY license upon publication.</footnote>
<figure><img src="image_3.png" /><figcaption>**Fig. 1.** Overview of the system. The timing mechanism ensures sequential timing of the feature extraction and the Bayesian inference. The feature extraction mechanism uses rate encoded characteristics from sensor data. The Bayesian classification relies on synapses which encode the probability distributions of $P(F|C_x)$ for the likelihoods and neurons that realize time-encode streams representing probabilities. A coincidence detection computes the posteriors for each class. The decision module uses a race-to-threshold WTA circuit and feedback.</figcaption></figure>

The main contributions of this work are: 1) The design and transistor-level simulation of an end-to-end Bayesian machine that integrates artificial neuron circuits for time-encoding and synaptic circuits that embed the probability distribution of features in order to calculate the likelihood values; 2) A clocking mechanism that uses cascaded neuron circuits to enable sequential phases; 3) A feature-extraction module that allows a stable analog representation of data characteristics for the classification; 4) A race to threshold WTA circuit with feedback that suppresses unnecessary switching activity and improves energy efficiency; 5) A full CMOS implementation in 130-nm technology validated with circuit simulations, demonstrating 80.8% classification accuracy on a sleep-stage discrimination task, with performance equivalent to the reference implementation in software. The architecture operates without stored probability tables, clocked finite-state control, or a global clock, and relies instead on event-driven neuron dynamics for sequencing and making decisions. The remainder of this paper describes the system architecture and timing strategy, followed by circuit-level implementation details, classification results, and a discussion of scalability and future directions.

## II. SYSTEM OVERVIEW

Fig. 1 illustrates the architecture of the proposed Bayesian system, which consists of four functional blocks. A timing module defines ordered timing phases that enable sequential operation of feature selection and Bayesian inference within a classification epoch. During feature selection, a neuron circuit converts the biosignal data into a rate-encoded characteristic that is accumulated on a capacitor and subsequently used as a feature for the classification.

When the feature extraction is complete, the Bayesian

inference begins. The heart of the system is the posterior calculation for each class. Here we use coincidence detection circuit that accumulates evidence when time-encoded streams representing $P(C)$ and $P(F|C)$ are coincident, enabling the calculation of the unnormalized posterior. It is also possible to use a Muller C-element [10], which can calculate the exact probability and is generally more time efficient. Here we explore two classes and a single feature, but the method can be extended to include multiple features and classes, with the transistor count increasing linearly.

This circuit relies on probabilistic time encoding, in which the duty cycle of deterministic artificial neuron circuits represents the probability values. Related approaches have been explored deterministic stochastic computing using pulse-width modulation and is often called [6], but have not been previously been applied to Bayesian inference. Other research has implemented Bayesian inference using populations of Poisson neurons to represent Hidden Markov Model states, in which posterior probabilities are dynamically encoded in stochastic spike rates [11]. In contrast, our approach does not perform sequential state estimation: the prior and likelihood functions are learned prior to classification, stored in a dedicated likelihood circuit, and encoded as static voltage values. As a result, our technique is well suited for classification tasks based on time-averaged signal statistics.

The Bayesian inference is completed using a WTA circuit, a variant of a pulse-coded WTA [12], that detects which category has the higher posterior probability and enables an output decision.

The transistor-level circuits are simulated in the weak inversion regime because the available models do not accurately predict deep subthreshold behavior. Nevertheless, the architecture is well suited for the latter regime and would result in a significantly reduced power consumption. The total
<figure><img src="image_4.png" /><figcaption>**Fig. 2.** a) The timing module of the Bayesian machine. Three cascaded neuron clocks are used to partition each epoch into three ordered signals. When the first neuron produces an output pulse, it results in an input current at the second neuron and subsequently its output pulse produces an input current for the third neuron. The output pulse of each neuron in the cascade cannot be activated prior to that of the preceding neuron. b) Neuron clock signals. Each of the three pulse signals last less than 2 ms.</figcaption></figure>

system uses approximately 150 transistors. The extraction of features is done with a straightforward rate-encoding neuron, but this can be extended to include other options such as the positive correlation between two EEG channels [13].

### III. TIMING WITH CASCADED NEURON CLOCKS

The timing module coordinates the operation of the Bayesian machine by partitioning each classification cycle into well-defined

temporal phases. Each classification is divided into an epoch $t_{epoch}$, during which the sensor data are first processed during the feature extraction stage ($t_{feal}$), and subsequently classified by the Bayesian inference engine ($t_{class}$). In the classification considered here, the first stage dominates $t_{epoch}$, significantly reducing the overall power consumption. The two phases can be adjusted depending on the classification complexity and the desired accuracy.

The neurons in the module were chosen to be an integrate-and-fire circuit [14] inspired by the axon hillock. Although they are inspired by biological models, their operation in this work is

<caption>TABLE I</caption>

Values of the supply voltages, capacitors and transistor dimensions used in the end-to-end circuit simulation.

<table><thead><tr><th colspan="3">(a)</th><th colspan="5">(b)</th></tr><tr><th colspan="3">Supply Voltages</th><th colspan="5">Capacitors</th></tr><tr><th>V<sub>DD</sub></th><th>V<sub>DD2</sub></th><th>V<sub>SS2</sub></th><th>C<sub>fc1</sub>, C<sub>fc2</sub>, C<sub>fc3</sub>, C<sub>fe</sub>, C<sub>s</sub></th><th>C<sub>ss</sub></th><th>C<sub>f1</sub>, C<sub>f2</sub>, C<sub>f3</sub>, C<sub>f4</sub></th><th>C<sub>cr1</sub>, C<sub>cr2</sub></th></tr></thead><tbody><tr><td>1V</td><td>0.5 V</td><td>- 0.5 V</td><td>1 nF</td><td>1 pF</td><td>26 fF</td><td>1.4 pF</td></tr></tbody></table>

<table><thead><tr><th colspan="11">(c)</th></tr><tr><th colspan="11">Transistors: W / L (µm / µm)</th></tr></thead><tbody><tr><td>MP1,3,5,7,9,11,12-15,21, 23-27, 33-36, 37, 39-43, 49-52, 54-55, 57-58, 59-74</td><td>MP18-20, 53, 56</td><td>MP17</td><td>MP22, 38</td><td>MP2, 6, 10, 16</td><td>MP4, 8</td><td>MP30-31, 46-47</td><td>MP32, 48</td><td>MP29, 45</td><td>MN25-26, 42-43</td><td>MN24, 27, 41, 44</td><td>MN29-30, 46-47</td></tr><tr><td>MN1-3, 5-7, 10-12, 15-21, 31-33, 36-38, 48-50, 55-70</td><td>MN8, 13, 22, 34, 39, 51</td><td></td><td></td><td>MN4, 9, 14, 23, 35, 40, 52, 53, 54</td><td></td><td>MN28, 45</td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>0.15 / 0.13</td><td>2 / 0.13</td><td>10 / 0.13</td><td>0.15 / 2</td><td>0.15 / 10</td><td>0.15 / 15</td><td>0.5 / 2</td><td>0.6 / 0.15</td><td>0.6 / 0.4</td><td>0.8 / 0.4</td><td>2 / 0.5</td><td>2 / 2</td></tr></tbody></table>
deterministic, and each neuron produces a single, well-defined control transition per epoch. Further, the timing signals generated by the neuron cascade control the sequencing of operations but do not encode data values themselves, ensuring a clear separation between control and computation. We use a relatively large feedback capacitors of 1 nF in order to realize the long pulse duration. Note that if operated at lower currents, the same timing behavior can be achieved with substantially smaller capacitors by reducing the bias currents (i.e., maintaining $t \approx C\Delta V/I$) and/or by using capacitance-multiplication or pseudo-resistor techniques. These optimizations are left for a follow-up implementation study.

Fig. 2a depicts the timing module, designed to ensure the ordering between feature extraction, classification and capacitor reset operations. The three cascaded neuron circuits generate three ordered control signals, denoted as $V_{c0}$, $V_{c1}$, $V_{c2}$. The duration of each epoch $t_{epoch}$ is determined by the input current $I_{ex}$, applied to the first neuron. When the first neuron produces an output transition on $V_{c0}$, the event is converted into an input current for the second neuron, ensuring that the output transition of the second neuron cannot occur before that of the first ($V_{c1}$). Likewise, the output transition of the second neuron triggers the third neuron, producing the control signal $V_{c2}$. Representation neuron clock signals are shown in Fig. 2b.

The transition of $V_{c1}$ marks the end of the feature extraction phase and initiates the transfer of the stored feature voltage from the large accumulation capacitor to the smaller one used during classification (see Fig 3). The Bayesian classification takes place during the interval defined by the active duration of $V_{c1}$. Subsequently the activation of $V_{c2}$ enables the reset of the capacitors, and when $V_{c2}$ returns to its inactive state, the system is

ready for the next epoch. The neuron circuit parameters used in this work are summarized in Table I.

The duration of the feature-extraction and classification phases can be adjusted by tuning the parameters of the neuron circuits, allowing longer computation times for applications requiring additional features. Additional timing phases can also be added if necessary by extending the cascade with additional neuron stages, without modifying the core inference circuitry. Using neuron circuits as timing elements thus negates the need for a global digital clock while naturally accommodating process variations and analog computation delays. Further, the cascaded structure guarantees correct temporal ordering even in the presence of device mismatch and process variations, since each control signal is generated only in response to the preceding event.

## IV. FEATURE EXTRACTION

Fig 3a shows the feature extraction module. Its main component is a spiking artificial neuron circuit that receives data from an analog sensor after it has been filtered, amplified and converted into a current by front end electronics. The resulting spikes from the neuron are accumulated on a storage capacitor $C_s$, which results in a voltage $V_{fb}$, whose final value corresponds to the feature used for the classification. Although the axon-hillock circuit produces a binary output, it does not operate as a static threshold detector. Instead, it performs a temporal and dynamical filtering of the input signal, responding selectively to specific combinations of amplitude, duration, and temporal structure. The integration allows the rejection of high-frequency noise and isolated spikes common in EEG and responds preferentially to oscillatory events intrinsic to EEG. As such, it acts essentially as

<figure><img src="image_5.png" /><figcaption>**Fig. 3.** a) Feature extraction module with two capacitors. During the feature extraction phase, voltage $V_{f0}$ accumulates on $C_s$. When $V_{c1}$ is activated, the voltage from $V_{f0}$ is transferred to $C_{ss}$, resulting in an increase in $V_{f1}$, which is used in the posterior probability calculation. b) Example of the behavior of $V_{f0}$ and $V_{f1}$, corresponding to the signals in Fig. 2.</figcaption></figure>
<figure><img src="image_6.png" /><figcaption>Fig. 4. (a) Bump circuit used to transform the feature data into a current that is input into the likelihood neuron. Note that the 130 nm technology node enables tuning of the wells. (b) Example of how the values of the bump circuit are obtained from data. The histograms are a plot of the training dataset and are fit to a Gaussian. These values are used to convert the output current of the bump circuit (I<sub>out</sub>) into a good representation of the likelihood distribution.</figcaption></figure>

an event detector with temporal selectivity. Learning in such an
implementation consists of acquiring previous data and adjusting
the parameters of the feature extraction so that they are on average
in the appropriate range for the classification task. The final tuning
can be done in the conversion from the EEG voltage to current at
the front end.

At the end of each epoch, V<sub>f0</sub> reflects the characteristic feature
of the raw signals. The voltage across the capacitor C<sub>s</sub> is then
transferred to the smaller capacitor C<sub>ss</sub>, noted as V<sub>f1</sub>. V<sub>f1</sub> can
activate the synapse circuit only during the classification phase,
i.e., when V<sub>c1</sub> is 0V. At other times, V<sub>f1</sub> is 0V, and the synapse
circuit remains inactive, as shown Fig. 3b.

V. POSTERIOR CALCULATION

To realize the Bayesian inference, the prior and likelihood are
first obtained. The prior is the probability of each class and is
determined during the set-up of the classification task based on
previous data. The likelihood is the conditional probability that
the observed evidence from the sensor data corresponds to a
category. The likelihood distribution is thus also obtained from
previous data and must be stored in the inference engine. The
most typical method is to store the distribution in a digital
memory [15], [16], however here we use a synapse circuit that
sufficiently reproduces the initial distribution by tuning circuit
parameters. We have explored implementations using both

<figure><img src="image_7.png" /><figcaption>Fig. 5. (a) Stochastic WTA circuit with feedback. When either $V_{m1}$ or $V_{m2}$ reaches the threshold, the capacitor of the other class is discharged. (b) Behavior of WTA circuit for each case. A falling edge of $V_{c0}$ discharges all capacitors, resetting the classification, and a rising edge initiates a new classification. When $V_{m1}$ or $V_{m2}$ reaches the threshold, the system will immediately discharge the other capacitor and maintain a continuous positive voltage at (V<sub>Output1</sub> or V<sub>Output2</sub>) to drive the corresponding subsequent circuit until the next falling edge of $V_{c0}$ arrives.</figcaption></figure>

Gaussian and arbitrary distributions, but here focus on the Gaussian distribution using a bump circuit [17]. The likelihood is obtained by inputting the $V_{f1}$ from the feature extraction module into the bump circuit and subsequently feeding its output current into a neuron circuit that produces a time-encoded stream representing a probability. We use the tunable Gaussian-like circuit [18], illustrated in Fig. 4. The likelihood distribution is determined offline and then translated into the circuit using three bias parameters. It is described in greater detail in [7]. Note that the circuit exploits the availability of independently biased wells in the TSMC 130 nm CMOS technology, enabling the tuning of the threshold voltage for transistors MN27 and MN24.

The prior and likelihood are encoded using spiking
neuron circuits whose duty cycle encodes the probability. An
analog coincidence circuit implements the unnormalized
Bayesian inference by accumulating charge on a capacitor only
when the prior and likelihood neurons generate overlapping
events. This calculation is done for each class, to obtain the
posterior voltages $V_{m1}$ and $V_{m2}$.
## VI. WINNER TAKE ALL DECISION WITH FEEDBACK

WTA circuits are commonly employed in inference circuits to determine the class with the maximum value of the computation. We employ a time dependent WTA that can sustain a voltage to drive a subsequent circuit. Fig. 5 illustrates three-stage cascaded inverters used as comparators. NAND gates then receive both the clock signal $V_{c0}$ and the signal when the threshold is reached to control the discharge of capacitors $C_{r1}$ and $C_{r2}$. Before each classification cycle $V_{c0}$ is at 0 V, and both $C_{r1}$ and $C_{r2}$ are discharged. When $V_{c0}$ returns to 1 V and $V_{c1}$ is 0 V, the classification begins, and the capacitor voltages, $V_{m1}$ and $V_{m2}$ start to increase. When the voltage on either capacitor, $V_{m1}$ or $V_{m2}$, reaches the threshold, it immediately discharges the capacitor of the other class. In addition, the output signals $V_{Output1}$ and $V_{Output2}$, are used to drive the subsequent circuits. This sub-module essentially functions as a race to threshold WTA circuit: the values of the posteriors are translated into voltage on a capacitor and the first one to cross the threshold of the inverter, corresponding to the larger, is the winner. The circuit integrates activity onto a capacitor and selects the earliest threshold-crossing event, which naturally operates on rate/time information rather than on discrete stochastic bitstreams.

Streams representing different probabilities often require different durations to ensure reliable coincidence detection. The feedback sub-circuit allows for an adaptive time for each

classification to reduce the system power consumption. To achieve this, two cascaded OR gates are employed. Once the capacitor of one class reaches the threshold, this sub-module immediately deactivates the classification phase. Note that due to the large difference in the timing of the $t_{feat}$ (~ 30 s) and $t_{class}$ (< 2 ms), the feedback will not significantly affect the overall timing of the classification.

Fig. 6 illustrates the final circuit that depicts the essential concept which represents a complete Gaussian Naïve Bayes classifier for a binary classification. For simplicity, we have used a single EEG channel, but it can easily be expanded to include multiple channels and more complex feature selection.

## VII. APPLICATION: SLEEP STAGE CLASSIFICATION

We demonstrate the end-to-end architecture on a sleep stage classification task. The data was provided by Bitbrain [19]. It consists of five stages: wake, transitional sleep, light sleep, deep sleep, and rapid eye movement sleep. In this task, light sleep and deep sleep are grouped as class 2, and the other stages as class 1. The goal is to develop a stimulation system that delivers electrical impulses to the brain during class 1 stages to enhance cognitive function. The dataset contained 850 thirty second epochs for a single person over one night of sleep. There were 266 epochs labeled as class 1 and 584 as class 2. The dataset was randomly split into 70% for training and 30% for testing. The training set was used to determine the bias parameters of

<figure><img src="image_8.png" /><figcaption>Fig. 6. End-to-end Bayesian classification architecture.</figcaption></figure>
<caption>TABLE II.</caption>

Performance metrics of the software compared with the circuit.

<table><thead><tr><th rowspan="2">Class</th><th colspan="2">Precision</th><th colspan="2">Recall</th><th colspan="2">Specificity</th><th colspan="2">F1 Score</th></tr><tr><th>Software</th><th>Circuit</th><th>Software</th><th>Circuit</th><th>Software</th><th>Circuit</th><th>Software</th><th>Circuit</th></tr></thead><tbody><tr><td>C<sub>1</sub></td><td>0.8305</td><td>0.8033</td><td>0.5698</td><td>0.5698</td><td>0.9408</td><td>0.9289</td><td>0.6759</td><td>0.6676</td></tr><tr><td>C<sub>2</sub></td><td>0.8112</td><td>0.8093</td><td>0.9408</td><td>0.9286</td><td>0.5698</td><td>0.5698</td><td>0.8712</td><td>0.8640</td></tr></tbody></table>

<figure><img src="image_9.png" /><figcaption>Fig. 7. (a) Results of the simulated end-to-end Gaussian Naïve Bayesian classification system (b) Software-based Gaussian Naïve Bayesian classification results. $C_1$ includes wake, $N_1$ and REM stages, $C_2$ includes $N_2$ and $N_3$ stages.</figcaption></figure>

the Gaussian-like synapses, and the test set was used to evaluate performance. We use only EOG signals for classification, mapping their amplitudes to the neuron's input current range (0 to 500 nA), and feeding them into the neuron circuit within the feature extraction module.

To benchmark our system, we considered a Gaussian Naïve Bayes software classification on a PC using scikit-learn [20]. The same feature used by the hardware system, the output voltage $V_{out}$, was provided as input into software and no additional preprocessing or dimensionality reduction was applied. The GNB model assumes class-conditional Gaussian likelihoods with diagonal covariance, and the means, variances, and class priors were estimated from the training set without additional hyperparameter tuning. This software implementation therefore represents an ideal floating-point realization of the same probabilistic model implemented in hardware.

The results are reported in Fig. 7 and Table. II. The system achieved 80.8% accuracy on the test set, closely matching the 81.5% accuracy of the software classifier. This demonstrates that the proposed hardware architecture faithfully reproduces the intended probabilistic computation. Table 2 compares the performance metrics between the software Gaussian Naïve Bayes baseline and the proposed circuit implementation, showing that the mixed-signal realization preserves class-balanced performance with minimal degradation. The small differences observed are primarily due to slight reductions in precision, while recall and specificity remain largely unaffected, indicating that the circuit preserves the decision structure of the classifier.

Table. III presents the power and energy analysis of the circuit classification.

VIII. DISCUSSION

This work demonstrates an end-to-end Gaussian Naïve Bayes classifier implemented using time-encoded probabilistic computing and neuromorphic elements. Key to our implementation is the use of spiking neuron circuits, not only for the probabilistic time encoding, but also for the feature extraction and timing. Here we employed a simple integrate-and-fire neuron based on the axon hillock model, which provides an excellent trade-off between architectural efficiency and functional robustness for prior, likelihood, and timing neurons.

The feasibility of this approach is demonstrated through transistor-level simulations in TSMC 130-nm CMOS at a 1.0 V supply using typical-typical device models. Classification occurs in two phases: a low-power front-end (timing and feature extraction) that operates continuously over the 30 s analysis window, and a short posterior computation and WTA phase lasting < 2 ms. Although the instantaneous power of the classification block is higher, its contribution to average power is negligible compared to the always-on feature extraction, resulting in an average inference power on the order of hundreds of nanowatts. This separation between long-duration ultra-low-power processing and short decision bursts is a key architectural distinction relative to microcontroller-based approaches.

In contrast, a microcontroller-based implementation typically requires continuous data acquisition and feature extraction in software, preventing deep sleep over the analysis window, or alternatively requires buffering large volumes of EEG data in memory before processing. As a result, even aggressive duty-cycling generally leads to milliwatt-scale active power during feature extraction, several orders of magnitude higher than the proposed analog front-end.

We note that the simulations correspond to operation in the weak-inversion regime, where foundry compact models are well validated. This does not represent a fundamental lower bound and further improvements in power efficiency are expected in a physical implementation operating in the deep subthreshold. Similar neuron and inference circuits have previously been demonstrated operating at supply voltages down to 100 mV and in deep subthreshold regimes [14]. In such
<table><caption>TABLE III
Power and energy for the sleep-stage classification (30 s window)</caption><thead><tr><th>Block</th><th>Mode</th><th>Power (µW)</th><th>Active time per use (s)</th><th>Energy per Decision (µW)</th><th>Avg power over 30 s (nW)</th></tr></thead><tbody><tr><td>Timing Module</td><td>Always on</td><td>≈ 0.3</td><td>30</td><td>≈ 9 µJ</td><td>≈ 300</td></tr><tr><td>Feature Extraction</td><td>Always on</td><td>≈ 0.3</td><td>30</td><td>≈ 9 µJ</td><td>≈ 300</td></tr><tr><td>Posterior Computation</td><td>Burst</td><td>≈ 5</td><td>≤ 0.002</td><td>≤ 10 nJ</td><td>≈ 0.33</td></tr><tr><td>WTA</td><td>Always on</td><td>≈ 0.01</td><td>30</td><td>≈ 300 nJ</td><td>≈ 10</td></tr><tr><td>Total</td><td></td><td></td><td></td><td>≈ 18.31 µJ</td><td>≈ 610.3</td></tr></tbody></table>

operating modes, both static and dynamic power consumption would be reduced by orders of magnitude, suggesting substantial headroom for further energy scaling beyond the values reported here. The complete system requires less than 150 transistors, and overall power consumption is expected to be dominated by the analog front-end circuitry for amplification and filtering rather than the inference engine itself [11].

This implementation can be compared to implementations of a Naïve Bayes classifier using field-programmable gate arrays (FPGAs), see [21] and references therein. These techniques target Naïve Bayes accelerators for maximum throughput, use look up tables digital signal processors and block RAM and are limited by the clock rate. Here, however, our objective is ultra-low duty cycle biosignal inference and the appropriate comparison is energy per epoch and minimization of circuit overhead through the elimination of memory. Moreover, our algorithmic fidelity (80.8% hardware versus 81.5% sklearn Gaussian NB) demonstrates that the realization closely matches the intended classifier.

During the WTA selection phase, it is possible that the accumulated voltage never activates the threshold of the final circuit. In this case, the epoch would be left without a classification and/or without a subsequent action. In the classification considered here, this never occurred and all of epochs were classified. This type of decision, essentially when the information is not sufficient, is very promising for tuning the precision and recall preferentially. That is, one can decide to have less false positives at the expense of reduced precision, so that the subsequent action is limited to only when the classification is very high confidence.

Biomimetic neuron models, such as the Morris-Lecar neuron [22], were initially considered for the feature-extraction stage. Their richer dynamics could in principle enable richer information extraction [5]. Circuit simulations, however, showed little or no improvement in classification performance compared to the simpler Axon-Hillock implementation. For the present work, which focuses on demonstrating a complete and compact system, we therefore adopted a basic rate coding strategy for feature extraction. For more complex classification tasks, biomimetic circuits or additional feature selection circuits working in conjunction with cascaded neuron stages could be

incorporated to implement more advanced feature-extraction mechanisms.

The proposed mixed-signal architecture achieves a compact and efficient implementation by leveraging neuron dynamics, capacitive integration, and spike-based representations of probabilistic quantities. One main advantage is the absence of an analog-to-digital converter. An alternative implementation of the proposed Bayesian classifier would consist of digitizing the extracted features, mapping them to probabilities using a lookup table (LUT), and performing the Bayesian inference digitally or with mixed-signal arithmetic. Such an approach benefits from deterministic behavior, straightforward calibration, and robustness to device variations. However, it inherently requires analog-to-digital conversion and memory access for each classification cycle. In contrast, the architecture presented here implements the likelihood functions and posterior computation directly in the analog and time domains, avoiding both explicit memory storage and continuous digital processing. As a result, the energy cost of the inference engine scales primarily with the brief classification window rather than with the duration of the sensing epoch.

This distinction is particularly relevant for epoch-based biosignal analysis, such as sleep staging, where sensor data are accumulated over long periods (e.g., 30 s) and classification is performed only intermittently. In the proposed system, the probability circuits and stochastic WTA operate for only a few milliseconds per epoch, leading to sub-nanowatt average power consumption. In a LUT-based implementation, even if feature extraction is performed locally, digitization of the feature values and subsequent memory access introduce a non-negligible energy overhead. Therefore, while LUT-based approaches remain attractive for higher-rate or fully digital systems, the probability-circuit approach adopted here is well matched to ultra-low-power, low-duty-cycle inference tasks at the edge.

Beyond enabling real-time, ultra-low-power classification, the proposed architecture also offers substantial advantages in terms of data storage and communication. Rather than recording raw EEG signals at high sampling rates, the system naturally produces event-based representations in the form of neuron spike streams. These spike trains encode salient signal features and probabilistic information using sparse temporal
events, allowing relevant information to be logged as spike
times or inter-spike intervals instead of continuous voltage
samples [5]. Consequently, the amount of data stored over long
monitoring periods can be reduced by orders of magnitude
compared to raw signal recording, with a corresponding
reduction in memory access, data movement, and storage
energy. Event logging further strengthens the suitability of the
proposed system for always-on biosignal monitoring under
strict energy constraints.

Future work includes extending the architecture for multi-
feature classification, performing robustness analysis under
mismatch and noise, and integrating the design into sensor
interfaces for fully embedded edge inference.

IX. CONCLUSION

This paper presented a compact neuromorphic Bayesian
system using neuron-generated clocks and mixed-signal
stochastic computing. The full circuit performs feature
extraction, likelihood evaluation, posterior accumulation, and
makes decisions entirely in the mixed-signal domain.
Transistor-level simulations confirm correct Bayesian
inference and show high accuracy on a representative biosignal
task. The low transistor count and compact analog architecture
make this design well suited for future ultra-low-power edge
computing systems.

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