# GaN-on-silicon transistors with reduced current collapse and improved blocking voltage by means of local substrate removal

Idriss Abid, Eleonora Canato, Matteo Meneghini, Gaudenzio Meneghesso, Kai Cheng, F Medjdoub

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Idriss Abid, Eleonora Canato, Matteo Meneghini, Gaudenzio Meneghesso, Kai Cheng, et al.. GaN-on-silicon transistors with reduced current collapse and improved blocking voltage by means of local substrate removal. Applied Physics Express, 2021, 14 (3), pp.036501. 10.35848/1882-0786/abdca0. hal-03113165

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GaN-on-silicon transistors with reduced current collapse and improved blocking voltage by means of local substrate removal

Idriss Abid<fnref n="1" />*, Eleonora Canato<fnref n="2" />, Matteo Meneghini<fnref n="2" />, Gaudenzio Meneghesso<fnref n="2" />, Kai Cheng<fnref n="3" />, and Farid Medjdoub<fnref n="1" />*

Received December 23, 2020; revised January 12, 2021; accepted January 14, 2021; published online January 29, 2021

We report on the demonstration of low trapping effects above 1200 V of GaN-on-silicon transistors using a local substrate removal (LSR) followed by a thick backside ultra-wide-bandgap AlN deposition. Substrate ramp measurements show reduced hysteresis up to 3000 V. It has been found that the LSR approach not only enables the extension operation voltage capabilities of GaN-on-silicon HEMTs with low on-resistance but also allow for the reduction of trapping effects directly affecting their dynamic behavior. This work points out that a large part of the electron trapping under high bias occurs at the AlN nucleation layer and Si substrate interface. © 2021 The Author(s). Published on behalf of The Japan Society of Applied Physics by IOP Publishing Ltd

For future efficient and low-cost power electronics, GaN high-electron-mobility transistors (HEMTs) on silicon (Si) substrate are highly promising owing to their superior intrinsic properties such as large bandgap, high breakdown field strength and high electron saturation velocity. <fnref n="1" />⁻¹²) GaN-on-Silicon HEMTs offer the potential to revolutionize power electronics by enabling important energy savings and new flexibility for advanced power circuits. ¹³) However, these types of devices suffer from poor critical electric field strength of the Si substrate together with a parasitic conduction at the buffer/substrate interface leading to device breakdown. ¹⁴⁻¹⁷)

That is why, the highest reported three-terminal breakdown voltage (VBD) values for grounded GaN-on-Si HEMTs defined at an off-state leakage current of 1 µA mm⁻<fnref n="1" /> are still below 1.5 kV, which is basically limited by the Si substrate and material quality. Consequently, applications requiring voltage operation above 1 kV cannot currently be covered by GaN-on-Si HEMTs, although thicker buffers with high associated material quality have been developed. ¹⁸⁻²⁰)

A solution to suppress the parasitic conduction phenomenon and thus enhance the breakdown voltage (BV) is to remove the Si substrate.²¹⁻²⁴) Indeed, the Si substrate removal around the drain electrode enabled electrical isolation of the gate and source contacts from the drain across the buffer layer/Si interface. Using this approach, GaN–on–Si based transistors with a significantly improved blocking voltage of 3000 V have been reported.²⁵) Recently, we have demonstrated GaN-on-Si metal insulator semiconductor HEMTs (MISHEMTs) with LSR under the entire device followed by a backside deposition of the ultra-wide bandgap AlN material.²⁶) The use of an in situ SiN gate dielectric and local substrate removal (LSR) technique combined with 15 µm thick AlN layer enabled state-of-the-art GaN based HEMTs with remarkably low off-state leakage current (<1 µA mm⁻<fnref n="1" />) up to 3000 V. On the other hand, a key figure of merit for GaN power devices is the current collapse that hindered for instance the commercialization of 650 V-rated GaN–on–Si devices.

In this work, we assessed the DC, high voltage and dynamic characteristics of high voltage transistors with and without LSR. We demonstrate the possibility to benefit from low electron trapping effects on lateral GaN-on-Si based transistors while extending the blocking voltage capabilities as compared to transistors without LSR.

The AlGaN/GaN heterostructure has been grown by meta-
lorganic chemical vapor deposition (MOCVD) on a 6 inch Si
(111) substrate. The HEMT structure consists in a 5 µm buffer
thickness, a 310 nm undoped GaN channel followed by a
24 nm Al0.25Ga0.75N barrier layer and an 11 nm in situ Si3N4
cap layer. Ohmic contacts were formed directly on top of the
AlGaN barrier by alloying Ti/Al/Ni/Au stack using an 875 °C
rapid thermal annealing resulting in contact resistances of
0.3 Ω . mm. Device isolation was performed by N2 implanta-
tion. Hall measurements reveal a sheet carrier concentration of
0.9 × 1013 cm−2 with a mobility of 2100 cm2 V−1 s−1, and a
sheet resistivity of 330 Ω/[]. Metal-insulator-semiconductor
(MIS) gate structure was employed by using Ni/Au metal stack
inside the in situ Si3N4 cap layer without any additional field-
plate. A 200 nm thick SiN film was deposited by plasma
enhanced chemical vapor deposition (PECVD) as extra
passivation. Once the front-side processing was completed,
the Si substrate was locally etched up to the AlN nucleation
layer around the entire device using a highly selective Bosch
process etching. It is important to note that our mask design
consists of devices with and without LSR patterns, which
eliminates any processing or epi variation during the device
characterization. Then, 15 µm thick nanocolumnar crystalline
AlN was deposited on the backside by physical vapor
deposition (PVD) at 300 °C, which is post front-side process
compatible as it complies with the thermal budget. The AlN
film delivers a high breakdown field well-above 4 MV cm−1
despite the low temperature deposition as checked through
vertical measurements on a reference doped silicon wafer.
Finally, 2 µm of copper is deposited on top of the PVD AlN
into the backside trenches. Hall measurements remains iden-
tical after full backside processing and subsequent AlN and
metal depositions.

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<footnote n="1">¹Institut d'Electronique, de Microélectronique et de Nanotechnologie, Centre National de la Recherche Scientifique (IEMN-CNRS), 59652 Villeneuve d'Ascq, France</footnote>

<footnote n="2">²Department of Information Engineering, University of Padova, 35131 Padova, Italy</footnote>

<footnote n="3">³Enkris Semiconductor, Inc., Suzhou, People's Republic of China</footnote>

<footnote>*E-mail: idriss.abid.etu@univ-lille.fr; farid.medjdoub@iemn.fr</footnote>
<figure><img src="image_4.png" /><figcaption>**Fig. 1.** (Color online) Room temperature vertical leakage characteristics of the AlGaN/GaN epitaxial structure with and without LSR.</figcaption></figure>

As expected, the vertical leakage current measurements conducted on isolated patterns with LSR show a remarkable increase from 1000 V to above 3000 V (limitation of our set-up) as compared to patterns without LSR (Fig. 1). This confirms the suppression of the substrate conduction phenomena and effectiveness of the AlN dielectric thick film.

DC characterizations were carried out on devices with a gate width/length = 50 µm/2 µm and various gate-to-drain spacing (L<sub>GD</sub>) with and without LSR on the same wafer. Maximum current density of transistors with L<sub>GD</sub> = 5 µm at V<sub>DS</sub> = 10 V and V<sub>GS</sub> = 0 V decreased from 490 to 340 mA mm<sup>-1</sup> after the Si substrate removal under the active region due to self-heating [Fig. 2(a)]. It can be pointed out that a significant recovery of the maximum current density occurs after the Cu deposition, which in turn enables the reduction of self-heating.<sup>27,28)</sup> Consequently, a thicker Cu heat sink (>10 µm) is expected to mitigate the current density reduction. Nevertheless, the extracted static specific on-resistance (R<sub>ON-STATIC</sub>) values are found to be below 10 mΩ cm<sup>-2</sup> in both cases. The corresponding transfer characteristics of AlGaN/GaN MISHEMTs with L<sub>GD</sub> of 5 µm are shown in Fig. 2(b). Despite a slight shift of the threshold voltage, it appears that the off-state leakage currents with and without LSR are similar and well-below 0.1 µA mm<sup>-1</sup> at low drain bias.

The three-terminal off-state leakage characteristics of the AlGaN/GaN MISHEMTs are plotted as a function of L<sub>GD</sub> in

Fig. 3(a). The devices without LSR show a BV plateau around 1000 V due to the buffer thickness limitation. For devices with LSR, the BV as a function of the gate-drain distance increases almost linearly reaching more than 3000 V for large designs (L<sub>GD</sub> > 30 µm). In the same way, lateral buffer BV conducted on isolated patterns as a function of contact distances with and without LSR show a strong improvement from 1900 V to well above 3000 V [Fig. 3(b)] with a reduction of the leakage current, confirming the suppression of the substrate conductive path contribution.

The substrate bias ramp technique has been shown to be very efficient in order to highlight the trapping effects and related current collapse in GaN-on-Si power switching transistors.<sup>29,30)</sup> As a matter of fact, in properly passivated structures, buffer charge storage is the main source of dynamic on-resistance.<sup>31)</sup> Substrate bias measurements have been performed on a Keysight B1505A Power Device Analyzer. Two ohmic contacts with a spacing of 20 µm have been used and the bias is set at 1 V. By ramping the substrate to a high (negative) potential, mimicking the off-state operation under the drain contact in a transistor, any charge redistribution in the buffer upon reverse bias will change the electric field. As such, the buffer charge trapping or storage will be visible in the substrate ramp characteristic. This approach is surface insensitive and applies a 1-D vertical field. The sweep rate was set to 22 V s<sup>-1</sup>. The devices without LSR reveals low hysteresis in the substrate ramps performed up to 600 V [see Fig. 4(a)]. This reflects the excellent material quality and the low charge storage within the heterostructure. Trapping effects are observed above 600 V as seen Fig. 4(b) through 1 kV substrate ramp measurements. Interestingly, the devices with LSR show low hysteresis and thus reduced charge storage all the way to 3000 V [Fig. 4(c)]. This means that the substrate removal followed by the additional thick AlN deposition not only preserve the integrity of a low charge trapping buffer but could also extend significantly the trap-free bias operation capability.

In order to verify these observations and further assess the trapping effects of transistors with and without LSR, we performed back-gating current transient measurements at room temperature on both samples. This technique allows to separate buffer charge trapping effects from surface ones. The measurement procedure is divided into stress and

<figure><img src="image_5.png" /><figcaption>**Fig. 2.** (Color online) (a) I<sub>D</sub>-V<sub>DS</sub> and (b) DC transfer characteristics of AlGaN/GaN MISHEMTs (L<sub>GD</sub> = 5 µm) with and without LSR characteristics.</figcaption></figure>

© 2021 The Author(s). Published on behalf of

036501-2 The Japan Society of Applied Physics by IOP Publishing Ltd
<figure><img src="image_6.png" /><figcaption>**Fig. 3.** (Color online) (a) Evolution of $L_{GD}$-dependent three-terminal breakdown voltage and (b) buffer breakdown versus contact distances of AlGaN/GaN MISHEMTs with and without LSR.</figcaption></figure>

<figure><img src="image_7.png" /><figcaption>**Fig. 4.** (Color online) Substrate ramps performed on TLM for the AlGaN/GaN epitaxial structure (a) at 1000 V without LSR and (b) at 3000 V with LSR.</figcaption></figure>

recovery phases. For the stress phase, the device is kept in trapping conditions for 10 s, during which a high electric field is induced on the buffer, as a result of charge trapping occurs mainly in this region. Then, the recovery phase is immediately carried out by keeping the device in rest conditions. The recovery drain current transient is recorded for 120 s. Several bulk bias stresses are tested, from -200 V up to -1.3 kV. During the stress the drain, gate and source terminals are kept at 0 V, whereas during the recovery the drain terminal is at

1 V, the source at 0 V and the gate is at 0 V. The plots of the drain current transients as a function of time for the different bulk bias stress are reported in Figs. 5(a) and 5(b). In agreement with the substrate ramp characterizations, the back-gating measurements show no trapping effects all the way to 1.3 kV for devices with LSR with a monotonic behavior over time regardless of the back bias. On the other hand, the same devices without LSR under similar conditions deliver significant trapping above 600 V. Figure 5(c)

© 2021 The Author(s). Published on behalf of
<figure><img src="image_8.png" /><figcaption>**Fig. 5.** (Color online) Back-gating current transient measurements with various trapping voltages and normalized current after stress as a function of the back bias of AlGaN/GaN MISHEMTs with and without LSR.</figcaption></figure>

summarizes the back-gating transient measurements of devices with and without LSR by showing the normalized current after stress (initial current after stress over current after 120 s recovery) as a function of the back bias. The remarkable monotonic evolution of the current after stress for devices with LSR while observing a drastic drop for devices without LSR within the same wafer show that under high bias most of the electron trapping occurs at the AlN nucleation layer/silicon substrate vicinity.

In conclusion, current collapse characteristics of GaN-based MISHEMTs with and without LSR followed by thick PVD AlN and Cu deposition were investigated on the same wafer. Trapping effects directly affecting the dynamic behavior of power switching transistors have been studied by means of high voltage substrate ramps as well as back-gating current transient measurements. This work demonstrates that the substrate removal approach not only enables the drastic extension of operation voltage capabilities of GaN-on-Silicon HEMTs but also potentially enables a drastic trapping reduction. This key additional benefit provided by the LSR approach is attributed to the removal of the interface between the AlN nucleation layer and the silicon substrate. Further removal of the full AlN nucleation layer and eventually part of the transition layers may allow GaN devices with current collapse-free operating well-beyond 1 kV. These results show that power applications above 1000 V covered currently by SiC and silicon-based

devices could benefit from the high electron mobility offered by GaN-on-silicon heterostructures enabling much lower R<sub>ON</sub>.

**Acknowledgments** This project has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 720527 (Inrel-NPower). This work is supported by the French RENATECH network and the French National grant ANR-17-CE05-00131 within the project called BREAKUP. The authors would also like to gratefully acknowledge the company Kyma for the thick PVD AlN deposition.

**ORCID iDs** Farid Medjdoub https://orcid.org/0000-0002-4753-4718

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