# Effects of Removing Bottom-side Copper in Baseplate-less Power Modules

Nikolaj Helmer Kristensen, Jakob Iversen Deichgraeber, Kerim Brackovic,

Szymon Bęczkowski, Stig Munk-Nielsen, Asger Bjørn Jørgensen

► To cite this version:

Nikolaj Helmer Kristensen, Jakob Iversen Deichgraeber, Kerim Brackovic, Szymon Bęczkowski, Stig Munk-Nielsen, et al.. Effects of Removing Bottom-side Copper in Baseplate-less Power Modules. The 26th European Conference on Power Electronics and Applications, GDR SEEDS France & EPE Association, Mar 2025, Paris, France. 10.34746/epe2025-0190. hal-05105916

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# Effects of Removing Bottom-side Copper in Baseplate-less Power Modules

Nikolaj Helmer Kristensen, Jakob Iversen Deichgraeber, Kerim Brackovic, Szymon Bęczkowski, Stig Munk-Nielsen, Asger Bjørn Jørgensen
AAU Energy
Aalborg University
Aalborg, Denmark
+45 99408756
nhkr@energy.aau.dk

## Keywords

<<Packaging>>, <<SiC MOSFET>>, <<Parasitic elements>>, <<Thermal management>>.

## Abstract

Performance of SiC MOSFETs are limited by the inherent parasitic elements originating from the packaging structure. In this paper, the parasitic capacitance of a 1.2 kV SiC MOSFET half-bridge power module is significantly reduced by removing the bottom-side copper, and the influence on its electrical and thermal performance is experimentally evaluated. Finally it is concluded that even though the modified module show significant advantages in turn-on switching energy, an increase in turn-off energy offsets it while also achieving a worse thermal performance.

## I Introduction

Silicon Carbide (SiC) devices offer significant benefits for power electronic converters due to SiC's superior material properties compared to traditional silicon. SiC devices can operate at higher voltages and temperatures and have lower switching losses, thereby improving efficiency and reducing heat losses. This allows for smaller and more compact converter designs with reduced cooling demands [1].

However, SiC devices are more sensitive to parasitic inductances and capacitances present in the surrounding packaging [2], when compared to silicon devices with similar voltage and current rating due to their comparatively smaller size. Parasitic inductances can cause voltage overshoot and ringing during switching events, potentially damaging the SiC devices or increasing electromagnetic interference (EMI) [3]. Likewise, parasitic capacitances can lead to unintended energy storage and oscillations, affecting the efficiency and stability during switching [4], [5], [6].

At elevated voltages, the energy stored in parasitic capacitances increases, since the energy stored is

proportional to the voltage squared. As a result, managing parasitic capacitance is critical at higher voltage and fast-switching speeds [7], [8]. Since SiC devices turn on and off more rapidly, minimizing the parasitics in the packaging design becomes critical to fully leverage their high-performance capabilities, ensuring robust and efficient operation [9]. In studies of novel 10 kV SiC MOSFET custom power module packages, the elimination of parasitic capacitance to the bottom-side copper has shown a reduction of up to 48% in the high-side switching losses [10], [11], [12].

Applications such as electric vehicles and photovoltaics, are seeking to employ SiC devices in the 800 V - 1200 V voltage range to achieve efficiency improvements. In this paper it is investigated to what degree the influence of parasitic capacitance already impacts the performance of the power modules at these voltage levels. In contrast to the development of new custom power module packages, as done in previous research, this paper seeks to retrofit the suitable commercial packages to mitigate the parasitic capacitance and evaluate the impact on its electrical switching capabilities, along with an assessment of the potential drawbacks in terms of thermal performance that these changes present. A schematic of parasitic baseplate couplings can be seen in Fig. 1. Section II describes the commercial power module structures suitable for removal of parasitic capacitance, its assembly, and a description of the test platform for this study. The experimental performance evaluation on electrical switching is presented in Section III, while the influence on the thermal performance is experimentally tested in Section IV. Section V discusses the practical implications of the modifications on the module and findings that could be investigated in future research. The paper is concluded in Section VI.
<figure><img src="image_2.png" /><figcaption>Fig. 1: Schematic of parasitic capacitive couplings to the bottom-side copper of a half-bridge power module.</figcaption></figure>

## II Power Module Structure

Different internal and external structures of power modules are shown in Fig. 2 and Fig. 3, respectively. The packaging structure of a discrete device is shown in Fig. 2(a), like the TO-package shown in Fig. 3(a). In these discretes, the back of the device is not isolated as it is connected to the drain of the MOSFET. The isolation to the heat sink is often achieved by an insulating Mylar or thermal interface material with insulation

<figure><img src="image_3.png" /><figcaption>Fig. 2: Power module packaging structure and the origin of parasitic capacitance in (a) discrete devices mounted to a heat sink (b) a power module with baseplate (c) direct liquid cooling of a baseplateless power module (d) the proposed baseplateless module structure with its bottom-side copper removed and a non-conductive heat sink material.</figcaption></figure>

<figure><img src="image_4.png" /><figcaption>Fig. 3: Physical package assemblies (a) discrete package (b) power module with baseplate (c) baseplate-less packages adoptable for removal of bottom-side copper.</figcaption></figure>

capabilities. However, in both cases the insulator maintains a parasitic capacitance to the cooling surface.

Fig. 2(b) shows the structure of a conventional power module with a direct bonded copper (DBC) and baseplate design. In these modules, the isolation from the DBC to the bottom-side copper is provided by a layer of ceramic substrate. The parasitic capacitance is inherently present in this structure, with copper layers on either side of the ceramic. As the bottom-side copper is soldered and electrically connected to the baseplate, it is not straight forward to eliminate the parasitic capacitive coupling. Fig. 3(b) shows an example of a commercial power module with a baseplate.

A baseplate-less design shown in Fig. 2(c) is a power module structure where the baseplate is removed. An example of commercially available baseplate-less power module is shown in Fig. 3(c). Baseplate-less designs often comes with some limitations regarding cooling, but integrated with direct liquid cooling this provides light and compact designs [13], [14].

In this paper we propose the solution shown in Fig. 2(d) as a further evolution of the baseplate-less design. Without a baseplate the bottom-side copper is exposed and can be removed and etched chemically. Without the bottom-side copper the parasitic capacitance of the DBC is eliminated. However, with a metallic heatsink for cooling, some parasitic coupling might still persist. By changing the heatsink to a non-conductive material, the hypothesis is that the parasitic capacitance is eliminated, thereby mitigating the phenomena
<figure><img src="image_5.png" /><figcaption>Fig. 4: Pictures of the double pulse testing setup while conducting double pulse testing of the modules</figcaption></figure>

related to parasitic capacitances as reported in [9], [10], [12]. These include reduced slew rates of high-side drain-source voltage and increased switching losses.

This paper examines the impacts of the electrical and thermal performance of the Wolfspeed CAB016M12FM3, an industrial-proven base-plateless power module, with and without the bottom-side copper. To do this the four configurations shown in Fig. 5 are created. First, the module is tested with and without the bottom-side copper. Secondly, a direct liquid cooled heatsink is manufactured in either a conductive (aluminum) or non-conductive (acrylic) material. For the switching characteristics in Section III, the data are presented for the setup with an aluminum heatsink and bottom-side copper, referred to as the “reference design”, and with an acrylic heatsink without bottom-side copper, which is referred to as the “modified design”. Next, all four possible combinations are presented in the thermal evaluation of the module. This means that the effects of changing the heatsink material and modifying the module can be evaluated individually.

<figure><img src="image_6.png" /><figcaption>Fig. 5: Configuration options of power modules with and without bottom-side copper (right), and conductive/non-conductive direct liquid-cooled heat exchangers (left).</figcaption></figure>

### III Switching Characteristics

The proposed power module structure modified by removing the bottom-side copper of a Wolfspeed CAB016M12FM3 SiC MOSFET half-bridge power module, is tested in a double pulse test to compare its switching characteristics with and without the parasitic capacitive coupling to a direct liquid-cooled heat sink.

It is tested in the two cases where the DC-link voltage is 400 V and 800 V. The tests were conducted at 60 A. The output voltage is measured using a Teledyne Lecroy PPE 4 kV passive probe on a 400 MHz Teledyne Lecroy HRO64Zi scope. The current $I_{ds}$ is measured using PEM CWT UM Rogowski coils with a bandwidth of 30 MHz.

Furthermore PCBs were designed for both powerboards to the power module and optically isolated gate drivers with a focus on minimizing parasitics. These PCBs and the general test setup is shown in Fig. 4. The tests were done using a 103 µH air-core inductor as load to mitigate saturation and non-linear effects, and with an external gate resistor of 5 Ω. All testing was conducted on the high-side of the SiC MOSFET half-bridge.

By having measurements of both $I_{ds}$ and $V_{ds}$ allows us to calculate the instantaneous power loss by the use of (1)

$$P_{\text{loss}}(t) = I_{\text{ds}}(t) \cdot V_{\text{ds}}(t) \quad (1)$$

This then provide the ability to compare the instantaneous power losses during switching. The instantaneous power loss curves can be seen as the third graph in each segment of Fig. 6. From the power curves the energy lost during switching can be found by integration of the power curves.

The measured waveforms of the double pulse test are presented in Fig. 6 for 400 V and 800 V respectively. The tests of the turn-on of the high-side MOSFET at 400 V show a fall time of 31.9 ns with the bottom-side copper (reference design)
<figure><img src="image_7.png" /><figcaption>Fig. 6: Switching waveforms of $V_{ds}$ and $I_{ds}$ for turn-on and turn-off of the high side MOSFET measured during double pulse testing at 400 V and 800 V.</figcaption></figure>

and is reduced to 26.6 ns when the bottom copper is removed (modified design). Likewise, at 800 V the fall time is reduced from 30.3 ns to 22.5 ns by implementing the modified design. This results in slew rates $\frac{dV_{ds}}{dt}$ of 10.1 V/ns and 12.0 V/ns at 400 V. While at 800 V it results in slew rates of 20.8 V/ns and 28.0 V/ns.

These waveforms in Fig. 6 show that the turn-on slew rates of the high-side SiC MOSFET are increased by removing the bottom-side copper. This follows the findings of [9] which states that

the turn-on should be slower with the bottom-side copper compared to the modified design without these parasitic capacitive couplings present. In conclusion, the experimental tests demonstrate an increase of 19-35% in turn-on slew rates of the modified design, depending on the testing conditions.

When examining the turn-off switching waveforms in the right side of the Fig. 6, the turn-off of the high-side MOSFET show the following rise-times and voltage slew rates. At 400 V the
<figure><img src="image_8.png" /><figcaption>Fig. 7: Barchart of the total switching energy for the different configurations evaluated.</figcaption></figure>

rise-time is 29.7 ns resulting in a slew-rate of 10.7 V/ns for the reference design. Likewise the rise-time for the modified design is 30.8 ns resulting in a slew-rate of 10.4 V/ns. At 800 V the rise-time of the reference design is 33.8 ns resulting in a slew-rate of 18.6 V/ns. For the modified design the rise-time is 34.0 ns resulting in a slew-rate of 18.5 V/ns.

The results show that the voltage slew rates, unlike for the turn-on of the MOSFET, does not change significantly for the turn-off. This analysis is only focussed on the voltage measurements but to establish the actual performance of the module the energy losses need to be analyzed.

The calculated switching energies can be seen in Fig. 7. It can be seen that the influence of the turn-on energy is as expected with the modified module showing a significant decrease in energy loss especially at high voltages. The turn-on energy for the module at 400 V is 268 µJ for the reference module and 251 µJ for the modified module. This is a decrease of 6.3%. At 800 V the turn-on energy is 546 µJ for the reference module and 364 µJ for the modified module. A reduction of 33.3%. The reduction of the turn-on energy due to the modifications are therefore significant at higher voltage when it comes to turn on energy. Unfortunately this changes when analyzing the turn-off energies. At 400 V the turn-off energy is 550 µJ for the reference design and 698 µJ for the modified. For 800 V the turn-off energy is 926 µJ for the reference design and 1476 µJ for the modified module.

Based on the results presented it can be concluded that even though the turn-on energy is significantly reduced as expected from [12] and [9]. But during the analysis of the switching energies it can

be seen that the turn-off energies are significantly increased with approximately 27% at 400 V and 60% at 800 V due to the modifications proposed. This means that the overall energy loss during switching is increased by implementing the modifications suggested.

## IV Thermal Performance

The thermal impedance curves will be established to evaluate the thermal performance of the power module configurations explained above. The laboratory setup consists of the Julabo CD200F circulator that was capable of maintaining a fixed liquid coolant temperature of 25 °C for the experiments. The coolant used for the setup is the Julabo Thermal H10 coolant. This coolant has some specific properties different from water.

The specific heat capacity of this liquid at room temperature is $1.5 \text{ kJ/(kg} \cdot \text{K)}$ approximately a quarter of waters. Furthermore the kinematic viscosity is $10 \text{ mm}^2\text{/s}$ around 10 times more than water and a thermal conductivity of $0.14 \text{ W/(m} \cdot \text{K)}$. Overall this fluid is compromised in its ability to remove heat from the power module in respect to other cooling liquids. The main reason why this liquid is used is due to its stability in different environments as it has good resistance to algae growth and a wide temperature operating range increasing the ease of use in laboratory environments.

The junction temperature is measured using the Opsens OTG-F sensors to ensure direct contact with the die and low response times of the measurements as seen in Fig. 8. The tests are conducted by applying a drain-source current on the module and then measuring the temperature response of the chip temperature when this current is applied. The tests are conducted at a mass-flow of 3.8 g/s.

The power dissipated by the module can be determined by the ohmic losses using (2)

<figure><img src="image_9.png" /><figcaption>Fig. 8: A module with encapsulation removed and chip surface temperature measurement using Opsens optic fiber OTG-F measurement probe.</figcaption></figure>
$$P_{\text{loss}} = R_{\text{dson}} \cdot I_{\text{ds}}^2 \quad (2)$$

This assumption is deemed valid as the temperature rise during experimentation is limited to around 25 °C degrees. As seen in the datasheet of the device [15] it stays fairly constant during these temperatures. Utilizing the formula for thermal impedance in (3)

$$Z_{\text{th}}(t) = \frac{T_j(t) - T_{\text{amb}}}{P_{\text{loss}}} \quad (3)$$

Where $T_j$ is the measured chip temperature and $T_{amb}$ is the liquid temperature maintained by the Julabo CD200F. Plotting this data on a logarithmic time scale then gives the thermal transient impedance curve as seen in Fig. 9. Based on this it can be seen that the four different configurations tested divide into two distinct branches depending on whether the module has its bottom-side copper or it is removed. Therefore, it can be concluded that the defining factor in the thermal performance is the removal of the bottom-side copper and not the heatsink material. From the analysis, it can be found that the increase in steady-state thermal resistance is around 5-7% due to the material change of the heatsink. The removal of the bottom-side copper provides an increase of around 28-30% in thermal resistance. The combined increase in thermal resistance 37% between the reference design and the modified design. The thermal performance of the module is therefore significant impacted by the removal of the bottom-side copper.

## V Discussion

During this study, it was observed that the removal of the bottom copper, had a negative impact on the robustness of the power module due to the alumina substrate's brittle nature. Mechanically, removing the bottom-side copper weakens the power module's structural integrity

<figure><img src="image_10.png" /><figcaption>Fig. 9: Measured thermal impedance for the four different setups. Notice the two distinct branches based on with or without bottom-side copper</figcaption></figure>

because copper adds mechanical strength to the module. During handling the power modules without bottom-side copper they were noticeably more fragile compared to the modules maintaining the bottom-side copper. Increasing the thickness of the insulating ceramic layers can offer more mechanical strength, however this also increases the thermal resistance. In this study, the substrate ceramic is aluminum oxide $Al_2O_3$ which has a thermal conductivity of 24 W/(m·K). A possible solution that may allow increasing ceramic thickness, without significant penalty to the thermal performance is by the use of aluminum nitride (AlN) which has a thermal conductivity of up to 170 W/(m·K). Another possible solution is adding more robust encapsulation materials inside the module as a substitute for the silicone gel found in the tested modules, such that the substrate does not withstand the entire pressure without support. Slight modifications to the housing design could also provide additional mechanical support to offset the mechanical weakness caused by the lack of bottom-side copper, such as additional supporting pillars of the plastic housing onto the substrate.

In Section III it is found that the modifications done to the module significantly increases the energy losses of the module during turn-off to the extent that the overall switching energy increases as seen in Fig. 7. This finding was surprising as the impact to the turn-off in the reviewed literature was not as significant. Making the modifications proposed in the paper will therefore only make sense in converter topologies where turn-off energies are significantly reduced due to zero current switching or discontinuous operation where turn-off happens at low currents. In this case the reduced turn-on losses can be beneficial.

The finding that there exist a trade off between turn-on energy and turn-off energy when it comes to parasitic capacitance also means that there might exist an optimum where the overall energy is decreased and the thermal performance is not impacted to the same extent.

In some previous research, the back-side copper of the power modules has been used for providing a return path for the current on the upper layer of the DBC, effectively reducing the power-loop inductance of the module. Even though this paper did not directly investigate this impact or experienced any characteristics, that are expected to be due to an increase in power-loop inductance, an ANSYS Q3D model of the power module DCB with and without back-side copper has been
<figure><img src="image_11.png" /><figcaption>Fig. 10: Screenshot of the ANSYS Q3D model used to evaluate power loop inductance for the power module.</figcaption></figure>

developed to further investigate this phenomena. Power loop inductance is defined from the DC+ pins of the module through the shorted high and low side MOSFET and back to the DC- pins. From the simulation it is clear that there is an increase in power-loop inductance in the modified design thus limited to an increase of approximately 0.5 nH from 6.76 nH with the back-side copper to 7.27 nH without the back-side copper at 400 MHz. A screenshot of the used model can be seen in Fig. 10.

## VI Conclusion

In applications that utilize SiC devices at voltage levels approaching 800 to 1200 V, like electric vehicles and photovoltaics, parasitic capacitance becomes an increasing issue, especially with faster-switching transients. At elevated voltages, the energy stored in parasitic capacitances increases. Retrofitting of existing baseplate-less power modules, by removal of the bottom side copper is a proposed solution to mitigate the parasitic capacitance. Electrically, the reduction of parasitic capacitance can be beneficial because it eliminates unwanted energy storage. In this paper, it was found that this results in an increase in switching speed during turn-on of 19-35%. further leading to a significant reduction in turn-on losses for the high-side MOSFET of 6-33% depending on voltage level. It is also found that removing the parasitic capacitance increase the turn-off energy with 27-60% dependent on voltage level. This increase in turn-off energy make the reduction seen in turn-on energy immaterial for hard switched applications. Overall the switching energy increases due to the removal of the bottom-side copper and the modification is therefore only relevant in applications where turn-on energy is of uttermost importance.

Furthermore, thermally if there is no bottom-side copper for heat spreading, the device's ability to dissipate heat is compromised. Copper acts as a thermal conductor, helping to distribute heat away from the device. For a direct liquid-cooled system the thermal resistance saw an increase of 37% when removing the bottom-side copper. It must therefore be concluded that the proposed modifications, at the voltage levels presented in this paper do not increase the performance in current EV drives and PV inverters.

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