# Tackling Hardware Trojan Horses via Hardware-based Methodologies

Alessandro Palumbo

<figure><img src="image_1.png" /></figure>

## To cite this version:

Alessandro Palumbo. Tackling Hardware Trojan Horses via Hardware-based Methodologies. RISC-V Summit Europe 2025, May 2025, Paris, France. pp.1-1, 2025. hal-05287158

HAL Id: hal-05287158

https://hal.science/hal-05287158v1

Submitted on 28 Sep 2025

HAL is a multi-disciplinary open access
archive for the deposit and dissemination of sci-
entific research documents, whether they are pub-
lished or not. The documents may come from
teaching and research institutions in France or
abroad, or from public or private research centers.

L'archive ouverte pluridisciplinaire HAL, est
destinée au dépôt et à la diffusion de documents
scientifiques de niveau recherche, publiés ou non,
émanant des établissements d'enseignement et de
recherche français ou étrangers, des laboratoires
publics ou privés.

<figure><img src="image_2.png" /></figure>

Distributed under a Creative Commons Attribution 4.0 International License
# Tackling Hardware Trojan Horses
via Hardware-based Methodologies

<figure><img src="image_3.png" /></figure>

<figure><img src="image_4.png" /></figure>

Alessandro Palumbo

CentraleSupélec, Inria, CNRS, IRISA

alessandro.palumbo@inria.fr

<figure><img src="image_5.png" /></figure>

CentraleSupélec

université
PARIS-SACLAY

Inria

**Abstract**—Hardware-based approaches to detect bit-flips, unauthorized program runs, and tampering.

<figure><img src="image_6.png" /><figcaption>Fig. 1. The Hardware Security Checker implementation</figcaption></figure>

## I. THE HARDWARE SECURITY CHECKER CONFIGURATION

**Configuration:** Recording legitimate instruction-address pairs.

<figure><img src="image_7.png" /><figcaption>Fig. 2. Configuration phase of the Hardware Security Checker [1]</figcaption></figure>

## II. THE HARDWARE SECURITY CHECKER VERIFICATION

**Verification:** Fetched instructions runtime verification.

<figure><img src="image_8.png" /><figcaption>Fig. 3. Verification phase of the Hardware Security Checker [1]</figcaption></figure>

<table><caption>TABLE I
BEST ANOMALIES DETECTION RATES AND OVERHEADS</caption><thead><tr><th>References</th><th>Acc.</th><th>FP</th><th>FN</th><th>#LUT</th><th>#FF</th><th>#BRAM</th></tr></thead><tbody><tr><td>[1] Fig. 2, 3</td><td>100%</td><td>0%</td><td>0%</td><td>75 (0.49%)</td><td>31 (0.31%)</td><td>8</td></tr><tr><td>[2] Fig. 4</td><td>100%</td><td>0%</td><td>0%</td><td>82 (0.53%)</td><td>31 (0.31%)</td><td>8.5</td></tr><tr><td>[3] Fig. 5</td><td>100%</td><td>0%</td><td>0%</td><td>NA</td><td>NA</td><td>NA</td></tr></tbody></table>

## III. THE HARDWARE SECURITY CHECKER & HAMMING

Enhancing detection capabilities, integrating Hamming code-based verification.

<figure><img src="image_9.png" /><figcaption>Fig. 4. Improving the Hardware Security Checker [2]</figcaption></figure>

## IV. DETECTING FPGA BITSTREAM TAMPERING WITH ML

Integrating supply chain phases with ML-based anomaly detection for FPGA security.

<figure><img src="image_10.png" /><figcaption>Fig. 5. The workflow for detecting FPGA tampering [3]</figcaption></figure>

## REFERENCES

[1] A. Palumbo et al., "A lightweight security checking module to protect microprocessors against hardware trojan horses," in *DFT*, pp. 1–6, 2021.

[2] A. Palumbo et al., "Improving the detection of hardware trojan horses in microprocessors via hamming codes," in *DFT*, pp. 1–6, 2023.

[3] S. Ribes et al., "Machine learning-based classification of hardware trojans in fpgas implementing risc-v cores.," in *ICISSP*, pp. 717–724, 2024.