# Breakdown voltage capability of vertical 4H-SiC power devices

Philippe Godignon, Jérôme Biscarrat, Miya Tranchesset, Romain Lavieville, Pierre Brosselard, Josep Montserrat

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Philippe Godignon, Jérôme Biscarrat, Miya Tranchesset, Romain Lavieville, Pierre Brosselard, et al. Breakdown voltage capability of vertical 4H-SiC power devices. Materials Science in Semiconductor Processing, 2024, 178, pp.108347. 10.1016/j.mssp.2024.108347. cea-04742479

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Submitted on 17 Oct 2024

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# Breakdown voltage capability of vertical 4H-SiC power devices

Philippe Godignon<sup>a, *</sup>, Jérôme Biscarrat<sup>a</sup>, Miya Tranchesset<sup>a</sup>, Romain Lavieville<sup>a</sup>, Dominique Tournier<sup>b</sup>, Pierre Brosselard<sup>b</sup>, Josep Montserrat<sup>c</sup>

## ARTICLE INFO

### Keywords:

- Silicon carbide

- Power devices

- Edge termination

- JTE

- Avalanche capability

- UIS

## ABSTRACT

Power semiconductor devices are constructed to endure high voltages (>30 V) and manage high current density. Edge termination is a specific feature that must be integrated into the device architecture to achieve high voltage capability in vertical power components. It is necessary to design these edge terminations while taking into account the device's architecture and technology. Termination efficiency is the main factor, but its area is also of great significance. Many edge termination designs with efficiency close to 100 % have been reported and are currently used in commercial devices. However, having a near-100 % static breakdown voltage is not the only requirement in modern power devices. Today, most power applications rely on the avalanche capability as a key parameter. Avalanche capability is defined by the device ability to enter in non-destructive avalanche mode, where the component can temporarily sustain a high voltage and a high current in blocking mode. The Unclamped Inductive Switching (UIS) test can be used to measure the avalanche mode, and it can be customized to define a safe operating area for a full avalanche mode (SOA). The safe operation of both single pulse and repetitive pulsed avalanche limits can be characterized. Such operation mode is now controlled in both Silicon and Silicon Carbide based power devices. However, the development of novel wide and ultra-wide band gap semiconductors in regards to avalanche capability and SOA still require a lot of work.

## 1. Introduction

Electrification is one of the most important strategies for driving the transition from fossil fuel to renewable energy. Power electronics form a crucial part of this transition [1]. In fact, power devices [2] are semiconductor-based architectures able to manage high voltage and/or high current for conditioning electrical energy. They are used in almost all the electronic systems and applications, usually to control the energy supply to the electronic systems or to electrical loads (motors, actuators ...). Power electronics use these devices in different family of circuits such as rectifiers, converters or breakers. Typically, the semiconductor power devices can suffer from electrical parasitic's such as overvoltage or surge energy generated by the load or the power circuit. Consequently, the design of such components must be robust and take into account safety margins defined in the so-called Safe Operating Areas (SOA) [2,3].

Two primary architectures are used for power semiconductor devices: lateral and vertical, depending on the direction of dominant

current flow [2]. A schematic illustration of these architectures is represented in Fig. 1. In lateral devices, the current flows laterally between two electrodes located on the surface of the semiconductor, like many other semiconductor devices such as CMOS circuits. The vertical architecture results in current flowing from the top to the bottom of the semiconductor die, between two electrodes on either side. In both architecture configurations, the component's maximum voltage capability requires the addition of specific features to the device structure. In a vertical device, this feature is called edge termination and is located at the periphery (see Fig. 2.) of the active area driving the current [4].

Power devices are often qualified using their on-resistance (Ron) and breakdown voltage (BV). In the scientific literature, breakdown voltage is often identified by a sharp increase of the reverse current in the I-V curve, which, in some cases, may result in misleading results analysis. The two main ways to define the BV parameter in current commercial device data sheets are: 1) reaching the avalanche mode breakdown voltage, 2) reaching a given leakage current density level, typically 1 mA/cm². Nonetheless, as we will discuss in this paper, power system

<footnote><sup>a</sup> Université Grenoble Alpes, CEA LETI, Grenoble, France</footnote>

<footnote><sup>b</sup> Univ Lyon, INSA Lyon, Univ. Claude Bernard Lyon 1, Ecole Centrale Lyon, CNRS, Ampère, F-69621, France</footnote>

<footnote><sup>c</sup> IMB-CNM-CSIC, Campus UAB, 08193 Bellaterra, Barcelona, Spain</footnote>

<footnote>* Corresponding author.
E-mail address: philippe.godignon@cea.fr (P. Godignon).</footnote>
developers prefer power components showing an avalanche breakdown capability.

Today's power semiconductor devices are mostly Silicon based but Silicon Carbide (SiC) emerged as the most viable candidate material for next-generation efficient solutions, notably thanks to its wider bandgap and critical electric field and good thermal conductivity [5]. As their Si counterparts, SiC vertical power devices need a properly designed edge termination. However, the high voltage edge termination design and optimization of SiC devices is partially different from Si ones due to several specificities [5]. The higher critical electric field in SiC compared to Si makes the management of the electric field distribution different, particularly at the interfaces with dielectrics. The use of field plates for edge termination is limited by this [6]. In terms of technology, SiC has significantly lower dopant diffusion coefficients than Si. Producing deep and laterally graded junctions [7], which are useful for building efficient terminations in Si, is not as straightforward to do in SiC. Beside, deep SiC etching is slower than Si, which limits trench-based termination. The charge trapping at the SiC/SiO₂ interface is much higher, which necessitates special care in the termination design to prevent surface charges from affecting it. Consequently, the design of high voltage terminations in SiC becomes more complex due to these aspects.

The present trends in periphery protection for high voltage vertical 4H-SiC devices are discussed in this paper. After some general considerations about 4H-SiC parameters related to breakdown phenomenon, we will have a look to the currently used solutions and to the recently proposed improvements, especially regarding the reduction of the edge termination area consumption. Then, we will look at a crucial requirement in high-power systems applications, which is the power device's ability to withstand an avalanche.

## 2. Voltage breakdown in 4H-SiC devices

Power semiconductor devices have the ability to block high voltage to protect the load from its power supply. High voltage vertical architecture requires a critical active layer called the drift region to allow for the spread of equipotential lines when the structure is in blocking mode. In the semiconductor device, the applied voltage can be increased for a given drift layer until it reaches a maximum value, which is known as the breakdown voltage. Table I provides a list of possible breakdown modes, with some of them being destructive and others being reversible [8] (see Table 2).

Avalanche is usually the preferred breakdown type in blocking mode since it is usually reversible and non-destructive below a given thermally dissipated energy limit, which depends on the device design [8,9]. Avalanche mode occurs when there is an impact ionization and multiplication phenomena caused by a high electric field inside the semiconductor, which results in the generation of carriers. Under high electric fields, charge carriers that are accelerated transfer energy through impact ionization, creating more electron-hole pairs that lead to the multiplication of charges, which results in a rapid increase in current. The avalanche phenomenon and its associated multiplicative factor are influenced by the electrons and holes impact ionization coefficients [2,9]. The electric field is the primary factor that influences these coefficients. As the electric field increases, the coefficients increase. In

Silicon, both electrons and holes impact ionization coefficients decrease with temperature, resulting in an increase of the avalanche voltage when temperature increases. In SiC, impact ionization rates are lower than in Si. Niwa [10] reported that the hole impact ionization coefficient for 4H-SiC decreases at higher temperatures while the electron impact ionization increases slightly. Even though electrons in 4H-SiC have a positive temperature coefficient, properly designed devices still see an increase in avalanche voltage as temperature increases, provided that carrier removal is effective enough. Ideally, avalanche should take place in a plane parallel pn junction to favor generated carriers extraction.

As SiC doping decreases, the critical electric field that activates avalanche phenomena decreases [11,12]. This could be seen as a drawback for high voltage devices where low doped thick epilayers are used, and lower critical field means lower avalanche voltage. However, it is equally important to consider that the device's interface dielectrics and passivation layers will be submitted to lower electric field stress, and may consequently be more reliable on the long term. Table II lists the drift layer parameters (epi doping and thickness) for the primary power application voltage classes, as well as the critical electrical field extracted from Ref. [11].

The higher doping level of SiC epilayer of SiC devices compared to Si at same voltage range makes SiC more robust to specific degradation mechanisms such as dynamic avalanche, second breakdown, and cosmic rays impact.

## 3. High efficiency edge terminations

The purpose of edge terminations is to maximize the static breakdown voltage and, if possible, to facilitate a non-destructive avalanche phenomenon in the power device [13]. The key parameter of an edge termination is its efficiency, which is the ratio between the termination breakdown voltage versus the maximum breakdown voltage of a 1D plane parallel junction made on the same drift layer configuration (epilayer doping and thickness). The latter is the maximum voltage we can applied between the top and bottom electrodes before activating an avalanche phenomena in the semiconductor at the pn junction level. Therefore, designers aim to construct edge terminations with the utmost efficiency, as close as possible to 100%.

The edge termination of most recent vertical power devices in Si or SiC is achieved by using selective P doped wells obtained through ion implantation. Usually, these edge terminations are built either with P rings with high doping (>1E19 cm⁻³) or/and with Junction Termination Extension (JTE) with moderate doping (few 1e17 cm⁻³) [14–17]. There are numerous and diverse combinations of both structures that have been reported and are currently employed in commercial SiC diodes and transistors. Fig. 1 displays a non-complete list of suggested architectures [14–32]. Pure P⁺ rings edge termination (Fig. 3a) is advantageous because nearly all power devices have implanted P⁺ profiles in their active cell process flow. This simplifies the fabrication process and reduces costs by eliminating the need for extra photolithography or p-type implantation steps to implement the termination. However, this ring termination requires meticulous control of the photolithography dimensions, particularly regarding the first ring position, and typically takes up a large area (>20 rings). The JTE structure (Fig. 3b)

<figure><img src="image_3.png" /><figcaption>Fig. 1. Power MOSFET lateral (left) and vertical (right) architecture schematic.</figcaption></figure>
necessitates an additional mask level and implantation step, but when combined with internal or external rings, it leads to optimal efficiency and a shorter termination length. In power MOSFETs, a deep P-body is implanted to form the channel area. One may consider to use this implant to form an edge termination. However, up to now, tentative to use this P-body layer as JTE failed [26] due to a higher p-doping than the optimal one. Therefore, it is necessary to perform a specific Al implantation step or multiple mask levels etching of the P-body (Fig. 3i) as required. A gradual lateral doping along the x-axis is highly beneficial for efficient termination in the JTE design. In silicon, it can be done by opening variable width implantation windows and playing with the lateral diffusion of the dopants during thermal treatment [6,33]. In SiC, dopants do not diffuse at reasonable temperatures (<1800 °C). An alternative technique to obtain lateral doping variation of the JTE is to combine the single implantation step with multiple etching steps as proposed in Ref. [28] and shown in Fig. 3f.

It is now possible to design edge terminations with maximum efficiency and safety using 4H-SiC using TCAD modeling and standard processing tools. Besides the correct design of the JTE and rings geometry, there are other factors that need to be considered. The first one is the high density of interface traps typically obtained on a SiC/SiO₂ interface. The breakdown voltage can fluctuate depending on these charges. Interface charges may help increase the apparent static breakdown voltage, but they can also cause voltage instability during switching, which could result in a potential change in the dynamic avalanche voltage. All Fig. 3's edge terminations are sensitive to surface charges with a more or less degree of sensitivity. The efficiency of single JTE relies on whether or not there are positive or negative charges in the dielectric, while JTE with inner and outer guard rings only exhibit degradation when positive charges are present. On the contrary, guard rings are more sensitive to negative charges. This behavior is illustrated in Fig. 4 for 3.3 kV PiN diodes. Two edge terminations (b and d in Fig. 3) have been modelled with Sentaurus TCAD tool, calculating the breakdown voltage versus the p-doping of the JTE for different dielectric interface charge concentrations. The experimental results are also mentioned. For both termination types, experiment fits only with a zero or a negative charge at the interface, which corresponds to the best combination for this termination type. According to theory, the termination shown in Fig. 3d is the most effective for high voltage power devices (>1200 V), but it is quite area-consuming.

## 4. Optimization of edge termination area

Edge terminations with near 100 % efficiency are now regularly obtained. The current optimization step involves reducing the termination area. Edge termination does not contribute to device current conduction, but it may take up a significant amount of semiconductor die space. Since the development trend is to increase the device current capability versus the semiconductor area, or equivalently to reduce the specific on-resistance per die, the termination area dead zone (in terms of current capability) plays a major role in the SiC die output current

<table><caption>**Table 1**

Typical breakdown phenomena observed in power semiconductor devices [8].</caption><thead><tr><th>Breakdown phenomena</th><th>Breakdown type</th><th>Specificities</th></tr></thead><tbody><tr><td>Avalanche in a pn junction</td><td>reversible</td><td>Limited by maximum critical avalanche energy</td></tr><tr><td>Avalanche elsewhere</td><td>reversible</td><td>Limited by (minority) carriers extraction efficiency</td></tr><tr><td>Punch-through</td><td>reversible</td><td>Limited by carriers extraction efficiency and dissipated power. Depends on doping and junctions barrier potentials</td></tr><tr><td>Parasitic BJT turn-on (latch-up)</td><td>destructive</td><td>Depends on junctions built-in potential (related to the band gap of the semiconductor)</td></tr><tr><td>Carriers trapping</td><td>reversible</td><td>Depends on traps density and detrapping rate of deep traps levels</td></tr><tr><td>Percolation breakdown</td><td>Time dependent</td><td>Depends on switching frequency</td></tr></tbody></table>

efficiency. In a current 10 kV device, the edge termination takes up roughly 45 % of the die area. If there was no termination required, the die could have twice the current capability value. Fortunately, for a 1.2 kV component, a total edge termination length of 50 µm–100 µm has shown to be sufficient.

In the edge termination structures listed above (Fig. 3), some of them can help to reduce the total die area. For instance, the termination of Fig. 3e [27] is claimed to reduce the termination length by 30 % compared to the termination of Fig. 3d. Regardless, it is important to consider other relevant parameters when reducing the termination width. A critical parameter is the presence and position of the channel stopper. This feature can be found at the ends of the die (as depicted in Fig. 5a). It consists of a highly doped thin ring with the same doping type as the drift region. A floating metal layer can be also deposited on top of the ring. As a result, the channel stopper is self-biased at the same voltage as the electrode on the backside (drain, cathode, collector). It helps to have a uniform distribution of the electric field at the die top surface, prevents from a parasitic inversion channel and acts as a parasitic charge collector eventually generated at the SiC/dielectric interface. However, to prevent surface arcing (Fig. 5b), it is necessary to maintain a specific distance between the end of the active area metal (anode, source, emitter) and the channel stopper. Excessive contraction of the termination length can lead to instabilities in the dielectric strength caused by charges or humidity effects in the passivation top layer.

The edge terminations depicted in Fig. 3 are the most frequently employed in modern commercial devices, and they can either be planar or combined with a MESA etch. In this sense, the management of the electric field in the periphery is done laterally along the axe parallel to the surface. Reducing the edge termination area can be achieved by using the vertical axis to partially or fully withstand the electric field in the periphery. This approach allows for significantly reducing the size of the edge termination. It is possible to utilize buried rings as described in Ref. [34] or deep implantation for JTE rings [35], but the

<figure><img src="image_4.png" /><figcaption>**Fig. 2.** Schematic of a high voltage termination concept in a vertical power diode architecture.</figcaption></figure>
<table><caption>**Table 2**
Drift region's parameters used for standard power application voltage classes and corresponding critical electric field value.</caption><thead><tr><th>Voltage class</th><th>650V</th><th>1.2 kV</th><th>1.7 kV</th><th>2.3 kV</th><th>3.3 kV</th><th>6.5 kV</th><th>10 kV</th><th>15 kV</th></tr></thead><tbody><tr><td>Epilayer thickness doping (cm<sup>-3</sup>)</td><td>5 µm 2 ×<br>10<sup>16</sup></td><td>9 µm 1 ×<br>10<sup>16</sup></td><td>14 µm 6 ×<br>10<sup>15</sup></td><td>18 µm 5 ×<br>10<sup>15</sup></td><td>30 µm 3 ×<br>10<sup>15</sup></td><td>55 µm 1 ×<br>10<sup>15</sup></td><td>90 µm 7 ×<br>10<sup>14</sup></td><td>130 µm 4 ×<br>10<sup>14</sup></td></tr><tr><td>Critical electric field (MV/cm)</td><td>2.71</td><td>2.5</td><td>2.44</td><td>2.33</td><td>2.21</td><td>2</td><td>1.94</td><td>1.85</td></tr></tbody></table>

<figure><img src="image_5.png" /><figcaption>**Fig. 3.** Schematics and corresponding literature references of the main planar edge terminations used in SiC power devices.</figcaption></figure>

implementation is quite complex with SiC technology. Most approaches involve etching a trench over the entire thickness of the drift layer and filling it with a dielectric like SiO₂, polyimide or BCB [36–39]. However, since a high electric field is usually present at the end of the active area p/n junction on the trench top side, additional features are required to properly block the high voltage. By using a field plate with an optimized shape [40,41], the equipotential crowding can be reduced (Fig. 6a). Another efficient approach is to implant a p-type layer on the trench sidewalls, as proposed in Refs. [42,43] (Fig. 6b). By utilizing this 3D termination configuration, the electric field at the SiC top surface can be reduced, which prevents issues with top side passivation arcing under humidity effect. However, these termination architectures are limited by several process limitations. Among them, SiC dry etching is much slower than Si technology, and it generates a high number of surface defects and roughness, both on the trench bottom and sidewalls. In SiC, trenches that are deeper than 10 µm pose a challenge. As a result, these trench edge terminations are challenging to use for voltage ranges greater than 1.2 kV. Furthermore, the standard conventional SiC dry-etching process utilizes fluorine-based chemistry, particularly the use of sulfur hexa-fluoride (SF₆). According to studies, this gas has a high global warming potential (GWP) of around 23,500 kg of CO₂ equivalent per kg over a 100-year time horizon [44]. The increasing attention to the

environmental pollution issue has to motivate the studies of eco-friendly SiC dry etching processes using low GWP etch chemistry or, at least, to limit the use of deep trench-based termination. On the other hand, sidewall implantation (Fig. 6b) is performed using a high ion beam angle and several steps are required to implant the different orientations of the trench sidewall, making the process costly and time consuming.

Therefore, it may be possible to incorporate a partial trench etching at a technologically realistic depth with P⁺ rings implanted at the bottom of the trench, as described in Refs. [45,46]. In this case, the trench does not need to reach the N⁺ buffer below the drift region. By utilizing conventional ion implant and SiC etching processes, devices with higher voltage ranges can be made.

## 5. Avalanche mode

To take full advantage of SiC's superior electro-thermal properties, most SiC power devices are with a vertically based architecture (JBS and PiN, MOSFETs, JFETs). A power device that qualifies for a breakdown voltage class (650 V, 1200 V, 1700 V, etc.) has an actual breakdown voltage higher than that voltage class value. If the device breaks down in a destructive manner, a significant derating margin must be implemented, such as 50 % for 650 V GaN HEMT. Independently of the
<table><caption>Fig. 3. (continued).</caption><tr><td>(e) JTE rings + P<sup>+</sup> rings</td><td>[27]</td></tr><tr><td>(f) JTE + SiC dry etching</td><td>[28]</td></tr><tr><td>(g) Buried P<sup>+</sup> rings</td><td>[29]</td></tr><tr><td>(h) JTE + N-compensation</td><td>[30]</td></tr><tr><td>(i) Multiple SiC etching P-body of P-base</td><td>[31, 32]</td></tr></table>

<figure><img src="image_6.png" /><figcaption>Fig. 4. Simulation and experimental measurement of PiN diodes with (a) a single JTE and (b) a hybrid ring assisted JTE (d) in Fig. 1) edge termination. 4 interface charges density have been used (–2e12, -1e12, 0 and +1e12 cm⁻²).</figcaption></figure>

derating, the power device operation will be safer if it is capable to enter in a non-destructive and repetitive avalanche breakdown mode, and to sustain this avalanche state during a given time duration or number of cycles. Avalanche robustness is highly desired for power devices in power electronics applications to protect against overvoltage and surge energy. By clamping the voltage peak, devices can conduct high avalanche current, which dissipates the excessive energy generated in the circuit.

The breakdown of power PiN diodes and MOSFET transistors occurs due to an avalanche process that takes place in the p/n junctions of the

edge termination or active area. When the avalanche mode is reached, the voltage at the device electrodes is clamped and does not increase anymore (at low power). The device will then take care of dissipating the surge energy generated by the power circuit. Depending on the device design, a given maximum energy rate will be dissipated before the device enters in thermal breakdown.

Measurement of avalanche behavior directly on-wafer would be a better method to receive faster feedback on a device's design and technology regarding its avalanche capability. By doing so, the die's real behavior can be studied without the packaging effect, which may affect
<figure><img src="image_7.png" /><figcaption>Fig. 5. (a) Schematic representation of the device edge termination and its channel stopper, (b) top image of a power diode suffering from a surface electrical arcing between the main electrode and the channel stopper.</figcaption></figure>

<figure><img src="image_8.png" /><figcaption>Fig. 6. (a) Trench termination with optimized with field plate (from Ref. [42]) (b) Trench termination with lateral side implantation.</figcaption></figure>

its avalanche performance. For this purpose, we intended to measure the
avalanche behavior using static I–V measurement, as well as with re-
petitive avalanche mode biasing limiting the dissipated power and
temperature raise.

**5.1. Static avalanche mode**

In static on-wafer I–V measurements of PiN diodes and MOSFETs, the breakdown mode can be detected by a sudden change in the leakage current slope under high voltage biasing. According to Table I, some breakdown modes are destructive. In this case, when performing I–V measurements again, the I–V curves behave completely differently, usually with a much higher leakage current starting at a low bias voltage (short-circuit mode breakdown). However, other breakdown modes than avalanche are reversible (such as junction punch-through). To segregate avalanche mode from other non-destructive breakdown, on-wafer temperature dependent I–V measurements can be used. As stated above, increasing the operation temperature should result in a slight increase in the measured avalanche voltage. Due to the temperature’s behavior of the impact ionization coefficient in SiC mentioned earlier, the increase of the avalanche voltage with temperature is relatively low, around 0.38 V/K in our 1.2 kV diodes case. Power semiconductors like PiN and MOSFETs tend to exhibit this behavior easily, but it still depends on the edge termination efficiency.

However, other devices such as Schottky power diodes and JBS diodes may have a different I–V characteristic behavior [2,5]. In these components, a high leakage tunneling current due to thermionic field emission (TFE) conduction related to the Schottky contact is appearing in the I–V measurement (see Fig. 7). The presence of high leakage currents may mask the activation of the avalanche mode or reach the measurement system (SMU) current limits before the avalanche is reached.

Besides, in the event of an avalanche, we can limit the current flowing in the device by setting a current compliance to control its self-

<figure><img src="image_9.png" /><figcaption>Fig. 7. Reverse i-V characteristics of SiC PiN and Schottky diodes measured at different measurement temperatures. Schottky diodes exhibit soft breakdown while PiN enter in avalanche mode.</figcaption></figure>

heating and prevent from thermal breakdown. In this way, the
avalanche mode is kept repetitive for a long time. By using a repetitive
avalanche mode biasing with limited power dissipation, it is possible to
investigate secondary effects that affect the device's long-term reli-
ability. For example, there may be drifts caused by hot carrier injection
and charge trapping.

The results presented in Fig. 7 corresponds to 2 wafers with 1.2 kV Schottky and JBS diodes processed at CNM-CSIC Barcelona. Both wafers had a drift region of 12 µm and 7e15 cm⁻³ doped. The Schottky metal, Ti, and W, and P⁺ doping profile were the primary elements that
differentiated these two wafer processes. The extracted barrier height was 1.04eV and 1.14eV for Ti and W, respectively. Different active area parameters and edge terminations were designed on the same wafer. We also implemented PiN bipolar diodes using the JBS P⁺ implantation profile for the anode formation.

The distance between JBS P⁺ wells is one of the designed parameters that was analyzed (see Fig. 8a). This parameter has a significant impact on the leakage current value at which avalanche mode is activated. We can see in Fig. 8b that the avalanche voltage is the same for three of the Wp/Wn designs (Schottky ratios of 0,63, 1, and 1.33) and for the reference PiN, despite the avalanche mode appears at different reverse current levels. Both PiN and JBS experience a small increase in their BV when temperature rises.

The next step was to compare the impact of the termination design on the avalanche voltage. For this purpose, we selected the design with a Schottky ratio of 1 (Wp 2µm/Wn 2 µm) for the wafer with W as Schottky metal. These devices allow us to observe the repeated avalanche mode mentioned earlier. Table III summarizes the design parameters for terminations. The total termination length up to the channel stopper is also given. All devices show a similar avalanche voltage around BV = 2080V, corresponding to the PiN diode one. It seems to confirm that the impact ionization and avalanche take place in the active area of the JBS for this particular design. We can see that a termination with a JTE of 35 µm length is sufficient to support the 2050V avalanche voltage.

We are unable to determine if the avalanche occurred in the active area or the edge termination area based solely on these electrical measurements. Fig. 9a displays a diagram of the different locations (A, B, C) where avalanche phenomena can occur. The JBS with a 0.63 Schottky/ PiN ratio was pushed to destruction through an increase in power during avalanche mode. The active area (location A in Fig. 9a) at the center of the diode is where destruction occurs, as shown in Fig. 9b. The thermal breakdown is likely caused by a heat transfer from the SiC near surface area to the top metal layers (W and Al). An excessive temperature is produced that is higher than the metals' fusion point. The location of the avalanche process can be determined after using TCAD modeling or failure morphological analysis.

## 5.2. Dynamic breakdown voltage and maximum avalanche energy

The previous static avalanche evaluation method is not completely trustworthy to determine the avalanche behavior in a real application when the device is operating in hard-switching mode. Parasitic impedances of the power circuit and inductive loads can initiate single pulse avalanche mode in a power device. Depending on the power circuit and

<caption>**Table 3**</caption>

Main termination designs tested up to avalanche mode in wafer with W as Schottky metal.

<table><thead><tr><th>JTE length (µm)</th><th>Internal rings number and width (µm)</th><th>Internal rings distances (µm)</th><th>Distance to channel stopper (µm)</th><th>Total termination length(µm)</th><th>Breakdown voltage (V)</th></tr></thead><tbody><tr><td>35</td><td>2 rings/3 µm</td><td>4.5/5</td><td>60</td><td>95</td><td>2050</td></tr><tr><td>50</td><td>3 rings/3 µm</td><td>4.5/5/5.5</td><td>60</td><td>110</td><td>2080</td></tr><tr><td>75</td><td>3 rings/3 µm</td><td>4.5/5/5.5</td><td>60</td><td>135</td><td>2075</td></tr><tr><td>100</td><td>3 rings/3 µm</td><td>4.5/5/5.5</td><td>60</td><td>160</td><td>2080</td></tr><tr><td>150</td><td>3 rings/3 µm</td><td>4.5/5/5.5</td><td>120</td><td>270</td><td>2070</td></tr><tr><td>150</td><td>0</td><td>0</td><td>120</td><td>270</td><td>2065</td></tr></tbody></table>

overvoltage event characteristics, the avalanche mode activates and induces high energy and current flow inside the device, which can lead to its thermal runaway. Internal and package thermal limitations determine the device's ability to sustain a maximum current and voltage combination for a certain duration. The single pulse avalanche energy parameter has been established to quantify the component electro-thermal limits during avalanche mode [47]. A dynamic characterization method has been developed in Si technology to evaluate the single pulse avalanche capability limit and related avalanche energy parameters of power devices. This methodology, named Unclamped Inductive Switching (UIS) [48,49], has been adapted to 4H-SiC power diodes and transistors and is now regularly reported for new SiC device generations. The procedure for measuring UIS involves releasing energy that was previously stored in an inductor in the device under test (DUT). The electrodes of the device under test (DUT) experience an overvoltage due to the energy stored in the inductance. An example of an electrical circuit we use for UIS testing on a diode (D1) is shown in Fig. 10. Linear charging of the inductance occurs during the conduction phase of transistor M1 (phase 1) in Fig. 10. When M1 is turn-off, an overvoltage appears at the M1 and DUT electrodes while the current starts to decrease (phase 2) in Fig. 10. Note that a similar circuit configuration would be used to test the UIS capability of the transistor M1, removing the diode D1.

The UIS test can be utilized for three different purposes. The primary objective is to determine the device's maximum avalanche energy, as

<figure><img src="image_10.png" /><figcaption>**Fig. 8.** JBS with different designs breakdown measurements (a) JBS cell schematic (b) I-V reverse measurement (voltage applied on the cathode).</figcaption></figure>
<figure><img src="image_11.png" /><figcaption>Fig. 9. a) Schematic representation of possible breakdown location in a JBS diode, b) pictures of two diodes after destructive thermal breakdown on different locations: b) active area (location A) and c) die edge surface (location D).</figcaption></figure>

<figure><img src="image_12.png" /><figcaption>Fig. 10. Example of Unclamped Inductive Switching (UIS) test circuit and corresponding voltage versus time signals.</figcaption></figure>

done for Silicon. In this case, we need to reach the thermal breakdown of the device. The second use is to measure the avalanche voltage of devices exhibiting high leakage current levels in soft breakdown mode, such as Schottky and JBS diodes or similar devices. For this purpose, we will limit the discharged energy (or current peak) playing with the inductance value and the gate pulse duration. By limiting the current level during avalanche operation, we can prevent excessive self-heating and thermal runaway to maintain a safe avalanche mode. A third use of the circuit is to test the repetitive avalanche mode capability, keeping the current peak below the thermal destruction value [50,51]. SiC

MOSFETs in dc–dc boost and flyback converters are often subjected to repetitive avalanche shocks, which easily result in electrical degradation and parameter drift. Then, such repetitive pulses measurement is also relevant to fully characterize the MOSFET behavior.

Fig. 11 displays UIS measurement waveforms for Caly Technologies’ 1.2 kV JBS diodes. In these reported measurements, different charging pulse durations (Tp) were employed to store energy in inductor L1. In Fig. 11a, we measured the voltage at the JBS electrodes when the control switch M1 was turned off. We can infer a sharp increase of the voltage VKA up to a plateau corresponding to the avalanche voltage of the JBS
<figure><img src="image_13.png" /><figcaption>Fig. 11. (a) Voltage peak versus inductance charging pulse length (b) Current peak in the Device Under Test during the avalanche mode for different charging pulse length.</figcaption></figure>

<figure><img src="image_14.png" /><figcaption>Fig. 12. Evolution of the a) avalanche energy capability b) avalanche current, versus the nominal current (meaning the die area) of several commercial SiC power diodes.</figcaption></figure>
diode. The plateau appears at 1670 V, which corresponds to the avalanche breakdown voltage at a junction temperature near room temperature operation. When the inductor charging pulse Tp is elevated, the current flowing through the diode in avalanche mode rises (explained in Fig. 11b). After a charging pulse duration Tp = 800 µs, the corresponding energy released is enough to cause a thermal breakdown on our DUT. This destructive breakdown occurs after 5.2 µs in avalanche mode. Failure is in short circuit. The maximum avalanche energy of a single pulse can be calculated using the voltage and current curves obtained at Tp = 750 µs previously. For this purpose we used the methodology and equations reported in Ref. [52]. The extraction process resulted in a total energy of 180 mJ and an avalanche energy density of 6.16 J/cm².

In Fig. 11a, we can observe that in the avalanche mode, the voltage is not fully clamped and slightly increases due to device internal self-heating. As the junction temperature increases, the avalanche voltage increases accordingly, resulting in the convex shape of the voltage curve. The avalanche voltage is also affected by the length of the pulse. Occasionally, we can observe a discrepancy between the static avalanche voltage measured on-wafer and the dynamic avalanche voltage measured with UIS, even when limiting the device self-heating.

Fig. 11b indicates that the avalanche current is 22 A while the nominal current of the diode is 10 A. The value of this avalanche current is dependent on the inductance value selected for the test. Changing the inductance values can result in the generation of a complete safe operating area (SOA), as illustrated in Ref. [52]. For each inductance value, the supply voltage is increased up to the device thermal runaway. The corresponding avalanche current and energy can then be determined. It is possible to obtain inductance values that lead to a higher maximum avalanche current than the nominal DC current of the device. The ratio is greatly influenced by the diode design (planar, trench, critical dimensions), technology (Schottky metal), and the manufacturer's definition of its device's nominal current. In Fig. 12, we have drawn the distribution of the avalanche energy and maximum avalanche current versus nominal current for several commercial SiC diodes with different voltage ranges. For a given device technology, avalanche energy increases almost linearly with the current, which is related to the die area. Regarding current ratio, it is highly dependent on the technology and the measurement parameters used (inductance value, charging time, etc.).

With the introduction of SiC and other WBG devices in real power applications, and especially power systems with inductive loads (like electric motors in electric vehicles), higher frequencies and high switching transitions (dV/dt) are used. Under these more rigorous conditions, it is frequently observed that the device avalanche voltage during circuit operation is drifting. The BV drift may be greatly influenced by charge trapping near the avalanche location inside the semiconductor. Another charge trapping effect could be caused by the presence of deep-level point defects in the semiconductor [8,53]. Adequate processing steps must be taken to minimize these deep levels, particularly during the ion implantation and activation steps of dopants. At device design level, we need to mitigate electric field peaks from charge trapping sensitive areas.

Finally, the avalanche operation generates a bipolar conduction mode, with the presence of the two types of carriers, electrons and holes. It is well known that bipolar current can cause stacking faults (SFs) to propagate in SiC devices. The SFs impact the blocking characteristics and reverse leakage currents of power SiC devices, including Schottky and JBS diodes [54]. Then, it is possible that a repetitive avalanche mode in a unipolar device generates activation of stacking faults and corresponding electrical parameters degradation. This must also be taken into account in the final device's ruggedness.

On the other hand, Silicon bipolar devices also suffer from dynamic avalanche effect [55]. The avalanche mode occurs if the stored free carriers do not recombined fast enough and lead to an increase of the electric field gradient in the structure, which may reach critical value at

lower voltage bias than static avalanche mode. However, due to the higher doping, lower carrier's lifetimes and lower impact ionization rates, it is considered that dynamic avalanche can hardly be seen for SiC device ranges below 10 kV [56].

## 6. Impact of cosmic rays

Cosmic rays are high radiation energy particles that can lead to spontaneous failures in semiconductor devices biased in blocking mode or under high electric field. The impact of cosmic rays on power semiconductor component for terrestrial applications have been shown first for Silicon devices [57]. The underlying mechanism for failure of power device have been identified as massive charge multiplication triggered by a nucleon-nucleus collision that creates an energetic recoil. Similarly to Si, in high electric field regions of SiC devices, the strong avalanche charge carrier multiplication is sufficient for causing single event burnout [58]. In terrestrial applications, these particles are typically neutrons and their flux exponentially increase with the altitude. In Si, mitigation is done through specific design allowing a reduction of the electric field peaks at the p/n junctions, or using a voltage range derating. In SiC, involved electric fields are usually 10 times higher. However, this is mitigated by a thinner drift layer and a smaller die area for a given voltage capability and nominal current. It helps to reduce the probability of a collision with a particle. Indeed, experimental results show a higher robustness of SiC devices versus their Si counterparts [59, 60].

Up to now, the impact of the termination design on device ruggedness regarding Cosmic Rays has not been established. Again, the thinner and shorter SiC termination dimensions should favor a lower probability of collision in the critical high field area. However, devices with similar electric field typically show similar failure rates. For a given technology or application, it is usually not possible to provide a single number of cosmic radiation failure rate. The higher the device voltage rating, the more susceptible it is to cosmic ray induced failures. Then, manufacturers will recommend a voltage derating which will depend on the breakdown voltage range and mission profile [61].

## 7. Conclusions

Solid-state SiC power devices with breakdown voltages of up to 15 kV can be regularly demonstrated using the established design guidelines and technology procedures for active and edge termination zones. High breakdown effectiveness is the main reason for the widespread use of terminations that are based on guard rings or JTE with rings. Certainly, the majority of commercial SiC devices are designed to withstand avalanches. Single pulse avalanche current easily reaches the nominal forward DC current ratings, while repetitive avalanche mode is also possible with very low performance's drift. These avalanche modes capabilities are required in most modern power circuit applications where inductive loads and parasitic interconnection inductances are present. The measurement of avalanche capability directly on-wafer is not straightforward, as misunderstandings are possible when analyzing a static I-V curve. Then, either temperature-dependent measurement on wafers or dynamic tests (UIS) on packaged devices are required. UIS test results may be influenced by the transient dV/dt rates applied to the device under test. UIS test standards have been developed for Si devices, with operation frequencies in the 10th of kHz range. However, new power semiconductors such as SiC and GaN operate at higher frequencies. Then, high frequency pulse tests may be necessary to emulate the operating conditions of the novel power application.

GaN and novel UWBG materials (Ga₂O₃, Diamond) are particularly affected by this. Although these materials have high BV, the absence of avalanche requires significant voltage degrading and prevents the device from being applied in many inductive-load systems. Strong efforts done in GaN vertical devices start to give promising results. UWBG requires similar efforts to be performed. In addition to avalanche mode,
other capabilities like high peak surge current or short circuit capability
are also necessary in such new WGB devices to be competitive with Si
and SiC.

CRediT authorship contribution statement

**Philippe Godignon:** Writing - original draft, Validation, Conceptualization. Jérôme Biscarrat: Investigation, Formal analysis, Validation. Miya Tranchesset: Investigation, Formal analysis, Data curation. Romain Lavieville: Supervision, Methodology, Conceptualization. Dominique Tournier: Methodology, Formal analysis, Data curation, Conceptualization. Pierre Brosselard: Supervision, Conceptualization, Validation. Josep Montserrat: Investigation, Methodology, Data curation.

Declaration of competing interest

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

Data availability

No data was used for the research described in the article.

Acknowledgement

From CNM-CSIC side, this work has been partially supported by the research project OPTO-FET (PID2020-117201RB-C22) from the Spanish Ministry of Science and Innovation, cofounded by FEDER.

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