# Enabling multi-programming mechanism for quantum computing in the NISQ era

Siyuan Niu, Aida Todri-Sanial

► To cite this version:

Siyuan Niu, Aida Todri-Sanial. Enabling multi-programming mechanism for quantum computing in the NISQ era. Quantum, 2023, 7, pp.925-959. 10.22331/q-2023-02-16-925. hal-03615593

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# Enabling Multi-programming Mechanism for Quantum Computing in the NISQ Era

Siyuan Niu¹ and Aida Todri-Sanial²,³

¹LIRMM, University of Montpellier, 34095 Montpellier, France

²LIRMM, University of Montpellier, 34095 Montpellier, CNRS, France

³Eindhoven University of Technology, 5612 AE, Eindhoven, Netherlands

NISQ devices have several physical limitations and unavoidable noisy quantum operations, and only small circuits can be executed on a quantum machine to get reliable results. This leads to the quantum hardware under-utilization issue. Here, we address this problem and improve the quantum hardware throughput by proposing a Quantum Multi-programming Compiler (QuMC) to execute multiple quantum circuits on quantum hardware simultaneously. This approach can also reduce the total runtime of circuits. We first introduce a parallelism manager to select an appropriate number of circuits to be executed at the same time. Second, we present two different qubit partitioning algorithms to allocate reliable partitions to multiple circuits – a greedy and a heuristic. Third, we use the Simultaneous Randomized Benchmarking protocol to characterize the crosstalk properties and consider them in the qubit partition process to avoid the crosstalk effect during simultaneous executions. Finally, we enhance the mapping transition algorithm to make circuits executable on hardware using a decreased number of inserted gates. We demonstrate the performance of our QuMC approach by executing circuits of different sizes on IBM quantum hardware simultaneously. We also investigate this method on VQE algorithm to reduce its overhead.

## 1 Introduction

Quantum computing promises to achieve an exponential speedup to tackle certain computational tasks compared with the classical computers [20, 21, 36]. Quantum technologies are continuously improving, and IBM recently released the largest quantum chip with 127 qubits. But, current quantum devices are still qualified as Noisy Intermediate-Scale Quantum (NISQ) hardware [32], with several physical constraints. For example, for superconducting devices, which we target in this paper, connections are only allowed between two neighbouring qubits. Besides, the gate operations of NISQ devices are noisy and have unavoidable error rates. As we do not have enough number of qubits to realize Quantum Error Correction [5], only small circuits with limited depth can obtain reliable results when executed on quantum hardware, which leads to a waste of hardware resources.

With the growing demand to access quantum hardware, several companies such as IBM, Rigetti, and IonQ provide cloud quantum computing systems enabling users to execute

Siyuan Niu: siyuan.niu@lirmm.fr

Aida Todri-Sanial: a.todri.sanial@tue.nl
their jobs on a quantum machine remotely. However, cloud quantum computing systems
have some limitations. First, there exists a latency when submitting jobs. Second, there
are a large number of jobs pending on the quantum device in general, so that users need
to spend a long time waiting in the queue.

The low hardware usage and long waiting time lead to a timely issue: how do we use
quantum hardware more efficiently while maintaining the circuit fidelity? As the increase of
hardware qubit number and the improvement of qubit error rates, the multi-programming
problem was introduced by [10, 23] to address this issue. It has been demonstrated that the
utilization (usage/throughput) of NISQ hardware can be enhanced by executing several cir-
cuits at the same time. However, their results showed that when executing multiple quan-
tum circuits simultaneously, the activity of one circuit can negatively impact the fidelity
of others, due to the difficulty of allocating reliable regions to each circuit, higher chance
of crosstalk error, etc. Previous works [10, 23] have left these issues largely unexplored
and have not addressed the problem holistically such that the circuit fidelity reduction
cannot be ignored when executing simultaneously. Moreover, detrimental crosstalk impact
for multiple parallel instructions has been reported in [1, 2, 26] by using Simultaneous
Randomized Benchmarking (SRB) [14]. In the presence of crosstalk, gate error can be
increased by an order of magnitude. Ash-Saki et al. [1] even proposed a fault-attack model
using crosstalk in a multi-programming environment. Therefore, crosstalk is considered in
the multi-programming framework [29].

Multi-programming, if done in an ad-hoc way would be detrimental to fidelity, but
if done carefully, it can be a very powerful technique to enable parallel execution for
important quantum algorithms such as Variational Quantum Algorithms (VQAs) [6]. For
example, the multi-programming mechanism can enable to execute several ansatz states in
parallel in one quantum processor, such as in Variational Quantum Eigensolver (VQE) [19,
31], Variational Quantum Linear Solver (VQLS) [4], or Variational Quantum Classifier
(VQC) [17] with reliability. It is also general enough to be applied to other quantum
circuits regardless of applications or algorithms. More importantly, it can build the bridge
between NISQ devices to large-scale fault-tolerant devices.

In this work, we address the problem of multi-programming by proposing a novel Quan-
tum Multi-programming Compiler (QuMC), taking the impact of hardware topology, cal-
ibration data, and crosstalk into consideration. Our major contributions can be listed as
follows:

* We introduce a parallelism manager that can select the optimal number of circuits to execute simultaneously on the hardware without losing fidelity.

* We design two different qubit partition algorithms to allocate reliable partitions to multiple circuits. One is greedy, which provides the optimal choices. The other one is based on a heuristic that can give nearly optimal results and significantly reduce the time complexity.

* We consider crosstalk effect during the partition process to achieve crosstalk mit-
igation during simultaneous executions. This is the first crosstalk-aware partition
algorithm.

* We improve the mapping transition step to execute multiple quantum circuits on quantum hardware with a reduced number of additional gates and better fidelity.

* We present a use case of applying our multi-programming framework to the VQE al-
gorithm to reduce its overhead, which demonstrates the application of multi-programming
on NISQ algorithms.
<figure><img src="image_2.png" /></figure>

<figure><img src="image_3.png" /><figcaption>Figure 1: An example of the multi-programming mechanism. (a) A four-qubit circuit is executed on a 10-qubit device. The hardware throughput is 40%. (b) Two four-qubit circuits are executed on the same device in parallel. The hardware throughput becomes 80%.</figcaption></figure>

We evaluate our algorithm on real quantum hardware by first executing circuits of different sizes at the same time, and then investigating it on VQE to estimate the ground state energy of deuteron. To the best of our knowledge, this is the first attempt to propose a complete multi-programming process flow for executing an optimal number of workloads in parallel ensuring the output fidelity by analyzing the hardware limitations, and the first demonstration of multi-programming application on NISQ algorithms.

## 2 Background

### 2.1 NISQ computing

Quantum computing has made huge progress in recent years. IBM launched the first cloud-based quantum computing service with a 5-qubit quantum machine in 2016, and the hardware qubit number reached 127 in only five years. In the meanwhile, the capabilities and error rates of the quantum hardware are continuously improving such that the Quantum Volume [9] arrived 128 for IBM quantum machines. However, today's quantum computers are considered as NISQ devices yet. The hardware topology is limited and the qubits are prone to different errors, such as (1) coherent errors due to the fragile nature of qubits, (2) operational errors including gate errors and measurement errors (readout errors), (3) crosstalk errors that violate the isolated qubit state due to the parallel operations on other qubits. NISQ computing still promises to realize quantum advantages using variational quantum algorithms despite the errors. Cloud-based quantum computing services facilitate researchers and developers to work in this area. However, it causes some online traffic. For example, there are usually more than 100 jobs pending on IBM Q 27 Toronto, which requires several hours to retrieve the result. Therefore, efficient and reliable cloud quantum computing services are demanded while taking good care of hardware utilization and qubit errors.

### 2.2 Multi-programming mechanism

The idea of the multi-programming mechanism is quite simple: executing several quantum circuits in parallel on the same quantum hardware. An example is shown in Fig. 1. Note that, the simultaneous circuits can always be scheduled using As Late As Possible (ALAP) method, allowing qubits to remain in the ground state as long as possible to avoid additional decoherence error caused by circuits with different depths. Since the waiting time is usually much longer than the circuit execution time, the difference between execution time for circuits with different depths can be ignored (see experimental demonstration in Section 8.2). By executing two circuits at the same time, the hardware throughput doubles and the total runtime (waiting time + execution time) is reduced twice. It is not trivial to achieve the multi-programming mechanism. The main concern is how to trade-off between
the circuit output fidelity and the hardware throughput (also indicates the reduction of total runtime). Even though it is possible to simply combine several programs to one large circuit and compile it directly, it has been shown in [23] that the circuit fidelity is decreased significantly due to the unfair allocation of partitions, unawareness of increased crosstalk, inflexibility of reverting back to independent executions for the case of serious fidelity drop, etc. Therefore, a new compilation technique for the multi-programming mechanism is required. Several problems need to be addressed to enable the multi-programming mechanism: (1) Find an appropriate number of circuits to be executed simultaneously such that the hardware throughput is improved without losing fidelity. (2) Allocate reliable partitions of the hardware to all the simultaneous circuits to make them execute with high fidelity. (3) Transform multiple circuits to make them executable on the hardware. (4) Reduce the interference between simultaneous circuit executions to lower the impact of crosstalk.

## 2.3 State of the art

The multi-programming mechanism was first proposed in [10] by developing a Fair and Reliable Partitioning (FRP) method. Liu et al. improved this mechanism and introduced QuCloud [23]. There are some limitations for the two works: (1) Hardware topology and calibration data are not fully analyzed, such that allocation is sometimes done on unreliable or sparse-connected partitions ignoring the robust qubits and links. (2) These works use only SWAP gate for the mapping transition process and the modified circuits always have a large number of additional gates. (3) Crosstalk is not considered when allocating partitions for circuits. For example, the X-SWAP scheme [23] can only be performed when circuits are allocated to neighbouring partitions, which is the case of more crosstalk. Ohkura et al. designed palloq [29], a crosstalk detection protocol that reveals the crosstalk impact on multi-programming. A similar idea of Concurrent Quantum Circuit Sampling (CQCS) [34] was proposed to increase the hardware usage by executing multiple instances of the same program simultaneously. The concept of multi-programming was also explored in quantum annealers of DWAVE systems to solve several QUBO instances in parallel [30].

In our work, we focus on the multi-programming mechanism and propose QuMC framework with different crosstalk-aware partition methods and mapping transition algorithm to increase the hardware usage while maintaining the circuit fidelity.

# 3 Our multi-programming framework

Our proposed QuMC workflow is schematically shown in Fig. 2, which includes the following steps:

* Input layer. It contains a list of small quantum circuits written in OpenQASM language [8], and the quantum hardware information, including the hardware topology, calibration data, and crosstalk effect.

* Parallelism manager. It can determine whether executing circuits concurrently or separately. If the simultaneous execution is allowed, it can further decide the number of circuits to be executed on the hardware at the same time without losing fidelity based on the fidelity metric included in the hardware-aware multi-programming compiler.

* Hardware-aware multi-programming compiler. Qubits are partitioned to several reliable regions and are allocated to different quantum circuits using qubit partition
<figure><img src="image_4.png" /><figcaption>Figure 2: Overview of our proposed QuMC framework. The input layer includes the quantum hardware information and multiple quantum circuit workloads. The parallelism manager decides whether to execute circuits simultaneously or independently. For simultaneous executions, it works with the hardware-aware multi-programming compiler to select an optimal number of shared workloads to be executed in parallel. These circuits are allocated to reliable partitions and then passed to the scheduler. It makes all the circuits executable on the quantum hardware and we can obtain the results of the output circuits.</figcaption></figure>

<figure><img src="image_5.png" /><figcaption>Figure 3: Process flow of each block that constitutes our QuMC approach. (a) The parallelism manager selects *K* circuits according to their densities and passes them to the hardware-aware multi-programming compiler. (b) The qubit partition algorithms allocate reliable regions to multiple circuits. $\Delta S$ is the difference between partition scores when partitioning independently and simultaneously, which is the fidelity metric. $\delta$ is the threshold set by the user. The fidelity metric helps to select the optimal number of simultaneous circuits to be executed. (c) The scheduler performs mapping transition algorithm and makes quantum circuits executable on real quantum hardware.</figcaption></figure>

algorithms. Then, the partition fidelity is evaluated by the post qubit partition process. We introduce a fidelity metric here, which helps to decide whether this number of circuits can be executed simultaneously or the number needs to be reduced.

* Scheduler. The mapping transition algorithm is applied and circuits are transpiled to be executable on real quantum hardware.

* Output layer. Output circuits are executed on the quantum hardware simultaneously or independently according to the previous steps and the experimental results are obtained.

In this paper, we only focus on IBM quantum architecture. Our QuMC method can be generally adapted to quantum hardware with nearest-neighbor connectivity and also allows parallel operations if applied to different qubits.

# 4 Parallelism manager

In order to determine the optimal number of circuits that can be executed on the hardware in parallel without losing fidelity, here, we introduce the parallelism manager, shown in
<figure><img src="image_6.png" /><figcaption>Figure 4: A motivational example of qubit partition problem. (a) No crosstalk between partition P1 and partition P3. (b) Crosstalk exists between partition P2 and partition P3.</figcaption></figure>

Fig. 3(a).

Suppose we have a list of *n* circuit workloads with *n*<sub>*i*</sub> qubits for each of them, that are expected to be executed on *N*-qubit hardware. We define the circuit density metric as the number of CNOTs divided by the qubit number of the circuit, #CNOTs/*n*<sub>*i*</sub>, and the circuit with higher density is considered to be more subject to errors. Firstly, the circuits are ordered by their "density" metric. Note that, the users can also customize the order of circuits if certain circuits are preferred to have higher fidelities. Then, we pick *K* circuits as the maximum number of circuits that can be executed on the hardware at the same time, Σ<sup>*K*</sup><sub>*i=1*</sub> *n*<sub>*i*</sub> ≤ *N*. If *K* is equal to one, then all the circuits should be executed independently. Otherwise, these circuits are passed to the hardware-aware multi-programming compiler. It works together with the parallelism manager to decide an optimal number of simultaneous circuits to be executed.

# 5 Hardware-aware multi-programming compiler

The hardware-aware multi-programming compiler contains two steps. First, perform qubit partitioning algorithm to allocate reliable partitions to multiple circuits. Second, compute the fidelity metric during post qubit partition process and work with parallelism manager to determine the number of simultaneous circuits.

## 5.1 Qubit partition

We develop two qubit partition algorithms by accounting for the crosstalk, hardware topology, and calibration data. In this section, we first introduce a motivational example for qubit partition. Second, we explain the approach for crosstalk characterization. Finally, we present two qubit partition algorithms, one greedy and one heuristic.

### 5.1.1 Motivational example

We consider two constraints when executing multiple circuits concurrently. First, each circuit should be allocated to a partition containing reliable physical qubits. Allocated physical qubits (qubits used in hardware) can not be shared among quantum circuits. Second, qubits can be moved only inside of their circuit partition during the routing process, in other words, qubits can be swapped within the same partition only. Note that, in this work, we performed routing inside of the reliable partition but other approaches can be
<figure><img src="image_7.png" /><figcaption>Figure 5: Results of the motivational example. (a) No crosstalk corresponds to Fig. 4(a) where no crosstalk exists between P1 and P3. (b) Crosstalk corresponds to Fig. 4(b) where crosstalk exists between P2 and P3. Note that "only P1" means the fidelity of the circuit when it is executed independently on P1, whereas "P1|P3" means the fidelity of circuit on P1 when two circuits are executed on P1 and P3 simultaneously.</figcaption></figure>

applied as well such as to route to other neighboring qubits that are outside of the reliable partition.

Finding reliable partitions for multiple circuits is an important step in the multi-programming problem. In order to illustrate the impact of partitions with different error sources on the output fidelity, first, we execute a small circuit `alu-v0_27` (the information of this circuit can be found in Table 3) on three different partitions independently to show the impact of operational error (including `CNOT` error and readout error): (1) Partition P1 with reliable qubits and links. (2) Partition P2 with unreliable links. (3) Partition P3 with unreliable links and qubits with high readout error rate. Note that, the `CNOT` error rate of each link is shown in Fig. 4 and the unreliable links with high `CNOT` error rates and qubits with high readout error rates are highlighted in red. Second, we execute two of the same circuits simultaneously to show the crosstalk effect: (1) P1 and P3 without crosstalk (Fig. 4(a)). (2) P2 and P3 with crosstalk (Fig. 4(b)). For the sake of fairness, each partition has the same topology. It is important to note that if we have different topologies, the circuit output fidelity will also be different since the number of additional gates is strongly related to the hardware topology.

The result of the motivational example is shown in Fig. 5. The fidelity is calculated using PST metric explained in Section 7.1.1 and higher is better. For independent execution, we have P1 > P2 > P3 in terms of fidelity, which shows the influence of operational error on output fidelity. For simultaneous execution, the circuit fidelities are approximately the same for the two partitions P1 and P3 compared with the independent execution in the case of no crosstalk. Whereas, the fidelities are decreased by 36.8% and 23.1% respectively for P2 and P3 when the two circuits are executed simultaneously due to the crosstalk. This example demonstrates the importance of considering crosstalk effect in the multi-programming mechanism.

### 5.1.2 Crosstalk effect characterization.

Crosstalk is one of the major noise sources in NISQ devices, which can corrupt a quantum state due to quantum operations on other qubits [35]. There are two types of crosstalk. The first one is quantum crosstalk, which is caused by the always-on-ZZ interaction [24, 42]. The second one is classical crosstalk caused by the incorrect control of the qubits. The calibration data provided by IBM do not include the crosstalk error. To consider
the crosstalk effect in partition algorithms, we must first characterize it in the hardware. There are several protocols presented in [3, 12, 14, 33] to benchmark the crosstalk effect in quantum devices. In this paper, we choose the mostly used protocol – Simultaneous Randomized Benchmarking (SRB) [14] to detect and quantify the crosstalk between CNOT pairs when executing them in parallel.

We characterize the crosstalk effect followed by the optimization methods presented in [26]. On IBM quantum devices, the crosstalk effect is significant only at one hop distance between CNOT pairs [26], such as ($CX_{0,1}|CX_{2,3}$) shown in Fig. 6(a), when the control pulse of one qubit propagates an unwanted drive to the nearby qubits that have similar resonant frequencies. Therefore, we perform SRB only on CNOT pairs that are separated by one-hop distance. For those pairs whose distance is greater than one hop, the crosstalk effects are very weak and we ignore them. It allows us to parallelize SRB experiments of multiple CNOT pairs when they are separated by two or more hops. For example, in IBM Q 27 Toronto, the pairs ($CX_{0,1}|CX_{4,7}$), ($CX_{12,15}|CX_{17,18}$), ($CX_{5,8}|CX_{11,14}$) can be characterized in parallel.

Previous works [1, 26, 27] show that, although the absolute gate errors vary every day, the pairs that have strong crosstalk effect remain the same across days. We confirm that validation by performing the crosstalk characterization on IBM Q 27 Toronto twice and we observe the similar behavior. The SRB experiment on CNOT pairs ($g_i|g_j$) gives error rate $E(g_i|g_j)$ and $E(g_j|g_i)$. Here, $E(g_i|g_j)$ represents the correlated CNOT error rate of $g_i$ when $g_i$ and $g_j$ are executed in parallel. If there is a crosstalk effect between the two pairs, it will lead to $E(g_i|g_j) > E(g_i)$ or $E(g_j|g_i) > E(g_j)$. The crosstalk effect characterization is expensive and time costly. Some of the pairs do not have crosstalk effect whereas the correlated CNOT error affected the most by crosstalk effect is increased by more than five times. Therefore, we extract the pairs with significant crosstalk effect, i.e., $E(g_i|g_j) > 3 \times E(g_i)$ and only characterize these pairs when crosstalk properties are needed. We choose the same factor 3 to quantify the pairs with strong crosstalk error like [26]. The result of crosstalk effect characterization on IBM Q 27 Toronto is shown in Fig. 6(b).

<figure><img src="image_8.png" /><figcaption>Figure 6: Characterization of crosstalk effect. (a) Crosstalk pairs separated by one-hop distance. The crosstalk pairs should be able to be executed at the same time. Therefore, they cannot share the same qubit. One-hop is the minimum distance between crosstalk pairs. (b) Crosstalk effect results of IBM Q 27 Toronto using SRB. The arrow of the red dash line points to the CNOT pair that is affected significantly by crosstalk effect, e.g., $CX_{7,10}$ and $CX_{12,15}$ affect each other when they are executed simultaneously. In our experiments, $E(CX_{10,12}|CX_{4,7}) > 3 \times E(CX_{10,12})$, whereas $E(CX_{4,7}|CX_{10,12}) \approx 1.5 \times E(CX_{4,7})$. As we choose 3 as the factor to pick up pairs with strong crosstalk effect, there is no arrow at pair $CX_{4,7}$.</figcaption></figure>
5.1.3 Greedy sub-graph partition algorithm.

We develop a Greedy Sub-graph Partition algorithm (GSP) for qubit partition process which is able to provide the optimal partitions for different quantum circuits. The first step of the GSP algorithm is to traverse the overall hardware to find all the possible partitions for a given circuit. For example, suppose we have a five-qubit circuit, we find all the subgraphs of the hardware topology (also called coupling graph) containing five qubits as the partition candidates. Each candidate has a score to represent its fidelity depending on the topology and calibration data. The partition with the best fidelity is selected and all the qubits inside of the partition are marked as used qubits so they cannot be assigned to other circuits. For the next circuit, a subgraph with the required number of qubits is assigned and we check if there is an overlap on this partition to partitions of previous circuits. If not, the subgraph is a partition candidate for the given circuit and the same process is applied to each subsequent circuit. To account for crosstalk, we check if any pairs in a subgraph have strong crosstalk effect caused by the allocated partitions of other circuits. If so, the score of the subgraph is adjusted to take crosstalk error into account.

In order to evaluate the reliability of a partition, three factors need to be consid-
ered: partition topology, error rates of two-qubit links, and readout error of each qubit.
One-qubit gates are ignored for simplicity and because of their relatively low error rates
compared to the other quantum operations. If there is a qubit pair in a partition that has
strong crosstalk affected by other partitions, the CNOT error of this pair is replaced by the
correlated CNOT error which takes crosstalk into account. Note that the most recent cali-
bration data should be retrieved through the IBM Quantum Experience before each usage
to ensure that the algorithm has access to the most accurate and up-to-date information.
To evaluate the partition topology, we determine the longest shortest path (also called
graph diameter) of the partition, denoted L. The smaller the longest shortest path is, the
better the partition is connected. Eventually, fewer additional gates would be needed to
connect two qubits in a well-connected partition.
**Algorithm 1** GSP algorithm

**Input:** Quantum circuit QC, Coupling graph G, Calibration data C, Crosstalk properties crosstalk, Used_qubits $q_{used}$

**Output:** A list of candidate partitions sub_graph_list

1: qubit_num ← QC.qubit_num

2: Set sub_graph_list to empty list

3: **for** sub_graph ∈ combinations(G, qubit_num) **do**

4: **if** sub_graph is connected **then**

5: **if** $q_{used}$ is empty **then**

6: sub_graph.Set_Parition_Score(G, C, QC)

7: sub_graph_list.append(sub_graph)

8: **end if**

9: **if** no qubit in sub_graph is in $q_{used}$ **then**

10: crosstalk.pairs ← Find_Crosstalk.pairs(sub_graph,

11: crosstalk props, $q_{used}$)

12: sub_graph.Set_Parition_Score(G, C, QC, crosstalk.pairs)

13: sub_graph_list.append(sub_graph)

14: **end if**

15: **end if**

16: **end for**

17: **return** sub_graph_list

We devise a fidelity score metric for a partition that is the sum of the graph diameter L, average CNOT error rate of the links times the number of CNOTs of the circuit, and the sum of the readout error rate of each qubit in a partition (shown in (1)). Note that the CNOT error rate includes the crosstalk effect if it exists.

$$ Score_g = L + Avg_{CNOT} \times \#CNOTs + \sum_{Q_i \in P} R_{Q_i} \quad (1) $$

The graph diameter L is always prioritized in this equation, since it is more than one order of magnitude larger than the other two factors. The partition with the smallest fidelity score is selected. It is supposed to have the best connectivity and the lowest error rate. Moreover, the partition algorithm prioritizes the quantum circuit with a large density because the input circuits are ordered by their densities during the parallelism manager process. The partition algorithm is then called for each circuit in order. However, GSP algorithm is expensive and time costly. For small circuits, the GSP algorithm gives the best choice of partition. It is also useful to use it as a baseline to compare with other partition algorithms. For beyond NISQ, a better approach should be explored to overcome the complexity overhead.

### 5.1.4 Qubit fidelity degree-based heuristic sub-graph partition algorithm.

In order to reduce the overhead of GSP, we propose a Qubit fidelity degree-based Heuristic Sub-graph Partition algorithm (QHSP). It performs as well as GSP but without the large runtime overhead.

In QHSP, when allocating partitions, we favor qubits with high fidelity. We define the fidelity degree of a qubit based on the CNOT and readout fidelities of this qubit as in (2).

$$ F\_Degree_{Q_i} = \sum_{Q_j \in N(Q_i)} \lambda \times (1 - E(Q_i, Q_j) + (1 - R_{Q_i}) \quad (2) $$
$Q_j$ are the neighbour qubits connected to $Q_i$, $E$ is the CNOT error matrix which is constructed by applying the Floyd-Warshall algorithm to the hardware coupling graph with CNOT error rate as edge weights, and $R$ is the readout error rate. $\lambda$ is a user defined parameter to weight between the CNOT error rate and readout error rate. Such parameter is useful for two reasons: (1) Typically, in a quantum circuit, the number of CNOT operations is different from the number of measurement operations. Hence, the user can decide $\lambda$ based on the relative number of operations. (2) For some qubits, the readout error rate is one or more orders of magnitude larger than the CNOT error rate. Thus, it is reasonable to add a weight parameter.

The fidelity degree metric reveals two aspects of a qubit. The first one is the connectivity of the qubit. The more neighbours a qubit has, the larger its fidelity degree is. The second one is the reliability of the qubit accounting for readout error rates. Thus, the metric allows us to select a reliable qubit with good connectivity. Instead of trying all the possible subgraph combinations (as in the GSP algorithm), we propose a QHSP algorithm to build partitions that contain qubits with high fidelity degree while significantly reducing runtime.

To further improve the algorithm, we construct a list of qubits with good connectivity as starting points. We sort all physical qubits by their physical node degree, which is defined as the number of links in a physical qubit. Note that, the physical node degree is different from the fidelity degree. Similarly, we also obtain the largest logical node degree of the logical qubit (qubits used in the quantum circuit) by checking the number of different qubits that are connected to a qubit through CNOT operations. Next, we compare these two metrics.

Suppose the largest physical node degree is less than the largest logical node degree. In that case, it means that we cannot find a suitable physical qubit to map the logical qubit with the largest logical node degree that satisfies all the connections. In this case, we only collect the physical qubits with the largest physical node degree. Otherwise, the physical qubits whose physical node degree is greater than or equal to the largest logical node degree are collected as starting points. By limiting the starting points, this heuristic partition algorithm becomes even faster.
**Algorithm 2** QHSP algorithm

**Input:** Quantum circuit *QC*, Coupling graph *G*, Calibration data *C*, Crosstalk properties *crosstalk*, Used_qubits *q*<sub>used</sub>, Starting points *starting_points*

**Output:** A list of candidate partitions *sub_graph_list*

1: *circ_qubit_num* ← *QC*.qubit_num

2: Set *sub_graph_list* to empty list

3: **for** *i* ∈ *starting_points* **do**

4: Set *sub_graph* to empty list

5: qubit_num ← 0

6: **while** qubit_num < *circ_qubit_num* **do**

7: **if** *sub_graph* is empty **then**

8: *sub_graph*.append(*i*)

9: qubit_num ← qubit_num + 1

10: continue

11: **end if**

12: best_qubit ← find_best_qubit(*sub_graph*, *G*, *C*)

13: **if** best_qubit ≠ None **then**

14: *sub_graph*.append(best_qubit)

15: qubit_num ← qubit_num + 1

16: continue

17: **end if**

18: **end while**

19: **if** len(*sub_graph*) = *circ_qubit_num* **then**

20: **if** *q*<sub>used</sub> is empty **then**

21: *sub_graph*.Set_Partition_Score(*G*, *C*, *QC*)

22: *sub_graph_list*.append(*sub_graph*)

23: **end if**

24: **if** no qubit in *sub_graph* is in *q*<sub>used</sub> **then**

25: crosstalk.pairs ← Find_Crosstalk.pairs(*sub_graph*,

26: crosstalk props, *q*<sub>used</sub>)

27: *sub_graph*.Set_Partition_Score(*G*, *C*, *QC*, *crosstalk.pairs*)

28: *sub_graph_list*.append(*sub_graph*)

29: **end if**

30: **end if**

31: **end for**

32: **return** *sub_graph_list*

For each qubit in the starting points list, the algorithm explores its neighbours and finds the neighbour qubit with the highest fidelity degree calculated in (2), and merges it into the sub-partition. Then, the qubit inside of the sub-partition with the highest fidelity degree explores its neighbour qubits and merges the best one. The process is repeated until the number of qubits inside of the sub-partition is equal to the number of qubits needed. This sub-partition is considered as a subgraph and is added to the partition candidates.

After obtaining all the partition candidates, we compute the fidelity score for each of them. As we start from a qubit with a high physical node degree and merge to neighbour qubits with a high fidelity degree, the constructed partition is supposed to be well-connected, hence, we do not need to check the connectivity of the partition using the longest shortest path *L* as in (1), GSP algorithm. We can only compare the error rates. The fidelity score metric is simplified by only calculating the CNOT and readout error rates
as in (3) (crosstalk is included if it exists). It is calculated for each partition candidate and the best one is selected.

$$ Score_h = Avg_{CNOT} \times \#CNOTs + \sum_{Q_i \in P} R_{Q_i} \quad (3) $$

<figure><img src="image_9.png" /><figcaption>Figure 7: Example of qubit partition on IBM Q 5 Valencia for a four-qubit circuit using QHSP. Suppose the largest logical node degree of the target circuit is three. (a) The topology and calibration data of IBM Q 5 Valencia. The value inside of the node represents the readout error rate (in%), and the value above the link represents the CNOT error rate (in%). (b) Process of constructing a partition candidate using QHSP.</figcaption></figure>

<table><caption>Table 1: The physical node degree and the fidelity degree of each qubit on IBM Q 5 Valencia.</caption><thead><tr><th>Qubit</th><th>Q<sub>0</sub></th><th>Q<sub>1</sub></th><th>Q<sub>2</sub></th><th>Q<sub>3</sub></th><th>Q<sub>4</sub></th></tr></thead><tbody><tr><td>Fidelity degree</td><td>1.96</td><td>3.93</td><td>1.95</td><td>2.94</td><td>1.97</td></tr><tr><td>Physical node degree</td><td>1</td><td>3</td><td>1</td><td>2</td><td>1</td></tr></tbody></table>

Fig. 7 shows an example of applying QHSP on IBM Q 5 Valencia (ibmq_valencia) for a four-qubit circuit. The calibration data of IBM Q 5 Valencia, including readout error rate and CNOT error rate are shown in Fig. 7(a). We set $\lambda$ to two and the physical node degree and the fidelity degree of qubit calculated by (2) are shown in Table 1. Suppose the largest logical node degree is three. Therefore, $Q_1$ is selected as the starting point since it is the only physical qubit that has the same physical node degree as the largest logical node degree. It has three neighbour qubits: $Q_0$, $Q_2$, and $Q_3$. $Q_3$ is merged into the sub-partition because it has the highest fidelity degree among neighbour qubits. The sub-partition becomes $\{Q_1, Q_3\}$. As the fidelity degree of $Q_1$ is larger than $Q_3$, the algorithm will again select the left neighbour qubit with the largest fidelity degree of $Q_1$, which is $Q_0$. The sub-partition becomes $\{Q_1, Q_3, Q_0\}$. $Q_1$ is still the qubit with the largest fidelity degree in the current sub-partition, its neighbour qubit $-Q_2$ is merged. The final sub-partition is $\{Q_1, Q_3, Q_0, Q_2\}$ and it can be considered as a partition candidate. The merging process is shown in Fig. 7(b).

### 5.1.5 Runtime analysis

Let $n$ be the number of hardware qubits (physical qubits) and $k$ the number of circuit qubits (logical qubits) to be allocated a partition. The GSP algorithm selects all the combinations of $k$ subgraphs from $n$-qubit hardware and takes $O(C(n, k))$ time, which is $O(n \cdot \text{choose } k)$. For each subgraph, it computes its fidelity score including calculating the longest shortest path, which scales at $O(k^3)$. It ends up being equivalent to $O(k^3 \min(n^k, n^{n-k}))$. In most
cases, the number of circuit qubits is less than the number of hardware qubits, thus the time complexity becomes $O(k^3n^k)$. It increases exponentially as the number of circuit qubits augments.

The QHSP algorithm starts by collecting a list of $m$ starting points where $m \le n$. To get the starting points, we sort the $n$ physical qubits by their physical node degree, which takes $O(n\log(n))$. Then, we iterate over all the gates of the circuit (e.g., circuit has $g$ gates) and sort the $k$ logical qubits according to the logical node degree, which takes $O(g+k\log(k))$. Next, for each starting point, it iteratively merges the best neighbour qubit until each sub-partition contains $k$ qubits. To find the best neighbour qubit, the algorithm finds the best qubit in a sub-partition and traverses all its neighbours to select the one with the highest fidelity degree. Finding the best qubit in the sub-partition is $O(p)$ where $p$ is the number of qubits in a sub-partition. The average number of qubits $p$ is $k/2$, so this process takes $O(k)$ time on average. Finding the best neighbour qubit is $O(1)$ because of the nearest-neighbor connectivity of superconducting devices. Overall, the QHSP takes $O(mk^2 + n\log(n) + g + k\log(k))$ time, and it can be truncated to $O(mk^2 + n\log(n) + g)$, which is polynomial.

## 5.2 Post qubit partition

By default the multi-programming mechanism reduces circuit fidelity compared to stand-alone circuit execution mode. If the fidelity reduction is significant, circuits should be executed independently or the number of simultaneous circuits should be reduced even though the hardware throughput can be decreased as well. Therefore, we consistently check the circuit fidelity difference between independent versus concurrent execution.

We start with the qubit partition process for each circuit independently and obtain the fidelity score of the partition. Next, this qubit partition process is applied to these circuits to compute the fidelity score when executing them simultaneously. The difference between the fidelity scores is denoted $\Delta S$, which is the fidelity metric. If $\Delta S$ is less than a specific threshold $\delta$, it means simultaneous circuit execution does not significantly detriment the fidelity score, thus circuits can be executed concurrently, otherwise, independently or reduce the number of simultaneous circuits. The fidelity metric and the parallelism manager help determine the optimal number of simultaneous circuits to be executed.

# 6 Scheduler

The scheduler includes the mapping algorithm to make circuits executable on real quantum hardware.

## 6.1 Mapping transition algorithm

Two steps are needed to make circuits hardware-compliant: initial mapping and mapping transition. The initial mapping of each circuit is created while taking into account swap error rate and swap distance, and the initial mapping of the simultaneous mapping transition process is obtained by merging the initial mapping of each circuit according to its partition. We improve the mapping transition algorithm proposed in [28] by modifying the heuristic cost function to better select the inserted gate. We also introduce the **Bridge** gate to the simultaneous mapping transition process for multi-programming.

First, each quantum circuit is transformed into a more convenient format – Directed Acyclic Graph (DAG) circuit, which represents the operation dependencies of the circuit without considering the connectivity constraints. Then, the compiler traverses the DAG
circuit and goes through each quantum gate sequentially. The gate that does not depend on other gates (i.e., all the gates before execution) is allocated to the first layer, denoted $F$. The compiler checks if the gates on the first layer are hardware-compliant. The hardware-compliant gates can be executed on the hardware directly without modification. They are added to the scheduler, removed from the first layer and marked as executed. If the first layer is not empty, which means some gates are non-executable on hardware, a SWAP or Bridge gate is needed. We collect all the possible SWAPs and Bridges, and use the cost function $H$ (see (5)) to find the best candidate. The process is repeated until all the gates are marked as executed.

A SWAP gate requires three CNOTs and inserting a SWAP gate can change the current mapping. Whereas a Bridge gate requires four CNOTs and inserting a Bridge gate does not change the current mapping. It can only be used to execute a CNOT when the distance between the control and the target qubits is exactly two. Both gates need three supplementary CNOTs. A SWAP gate is preferred when it has a positive impact on the following gates, allocated in the extended layer $E$, i.e., it makes these gates executable or reduces the distance between control and target qubits. Otherwise, a Bridge gate is preferred.

A cost function $H$ is introduced to evaluate the cost of inserting a SWAP or Bridge. We use the following distance matrix (see (4)) as in [28] to quantify the impact of the SWAP or Bridge gate,

$$D = \alpha_1 \times S + \alpha_2 \times \mathcal{E} \quad (4)$$

where $S$ is the swap distance matrix and $\mathcal{E}$ is the swap error matrix. We set $\alpha_1$ and $\alpha_2$ to 0.5 to equally consider the swap distance and swap error rate. In [28], only the impact of a SWAP and Bridge on other gates (first and extended layer) was considered without considering their impact on the gate itself. As each of them is composed of either three or four CNOTs, their impact cannot be ignored. Hence, in our simultaneous mapping transition algorithm, we take self impact into account and create a list of both SWAP and Bridge candidates, labeled as "tentative gates". The heuristic cost function is as:

$$H = \frac{1}{|F + N_{\text{Tent}}|} \left( \sum_{g \in F} D[\pi(g.q_1)][\pi(g.q_2)] + \sum_{g \in \text{Tent}} D[\pi(g.q_1)][\pi(g.q_2)] \right) + W \times \frac{1}{|E|} \sum_{g \in E} D[\pi(g.q_1)][\pi(g.q_2)] \quad (5)$$

where $W$ is the parameter that weights the impact of the extended layer, $N_{\text{Tent}}$ is the number of gates of the tentative gate, $\text{Tent}$ represents a SWAP or Bridge gate, and $\pi$ represents the mapping. SWAP gate has three CNOTs, thus $N_{\text{Tent}}$ is three and we consider the impact of three CNOTs on the first layer. The mapping is the new mapping after inserting a SWAP. For Bridge gate, $N_{\text{Tent}}$ is four and we consider four CNOTs on the first layer, and the mapping is the current mapping as Bridge gate does not change the current mapping. We weight the impact on the extended layer to prioritize the first layer. This cost function can help the compiler select the best gate to insert between a SWAP and Bridge gate.

Our simultaneous mapping transition algorithm outperforms HA [28] thanks to the modifications of the cost function while not changing its asymptotic complexity. Let $n$ be the number of hardware qubits, $g$ the CNOT gates in the circuit. The simultaneous mapping transition algorithm takes $O(gn^{2.5})$ assuming nearest-neighbor chip connectivity and an extended layer $E$ with at most $O(n)$ CNOT gates. The detailed explanation about the complexity can be found in [28].
**Algorithm 3** Simultaneous mapping transition algorithm

**Input:** Circuits *DAGs*, Coupling graph *G*, Distance matrices *Ds*, Initial mapping $\pi_i$, First layers *Fs*

**Output:** Final schedule

1: $\pi_c \leftarrow \pi_i$

2: **while** not all gates are executed **do**

3: Set swap\_bridge\_lists to empty list

4: **for** $F_i$ in $Fs$ **do**

5: **for** gate in $F_i$ **do**

6: **if** gate is hardware-compliant **then**

7: schedule.append(gate)

8: Remove gate from $F_i$

9: **end if**

10: **end for**

11: **if** $F_i$ is not empty **then**

12: swap\_bridge\_candidate\_list $\leftarrow$ FindSwapBridgePairs($F_i$, $G$)

13: swap\_bridge\_lists.append(swap\_bridge\_candidate\_list)

14: **end if**

15: **end for**

16: **for** swap\_bridge\_candidate\_list $\in$ swap\_bridge\_lists **do**

17: **for** $g_{tmp} \in$ swap\_bridge\_candidate\_list **do**

18: $\pi_{tmp} \leftarrow$ Map\_Update($g_{tmp}$, $\pi_c$)

19: $H_{basic} \leftarrow 0$

20: **for** gate $\in F_i$ **do**

21: $H_{basic} \leftarrow H_{basic} + D_i(\text{gate}, \pi_{tmp})$

22: **end for**

23: $H_{tentative} \leftarrow g_{tmp}.cost(G, D_i, \pi_{tmp})$

24: Update the extended layer *E*

25: $H_{extend} \leftarrow 0$

26: **for** gate $\in E$ **do**

27: $H_{extend} \leftarrow H_{extend} + D_i(\text{gate}, \pi_{tmp})$

28: **end for**

29: $H \leftarrow \frac{1}{|F+H_{tentative}|}(H_{basic} + H_{tentative}) + \frac{W}{|E|}H_{extend}$

30: **end for**

31: Choose the best gate $g_n$ according to $H$

32: $\pi_c \leftarrow$ Map\_Update($g_n$, $\pi_c$)

33: **end for**

34: Update $Fs$

35: **end while**

36: **return** schedule

# 7 Evaluation

In this section, we compare our QuMC method with the state of the art and showcase its different applications.
# 7.1 Methodology

## 7.1.1 Metrics

Here are the explanations of the metrics we use to evaluate the algorithms.

1. Probability of a Successful Trial (PST) [38]. This metric is used to represent the circuit output fidelity and is defined by the number of trials that give the expected result divided by the total number of trials. The expected result is obtained by executing the quantum circuit on the simulator. To precisely estimate the PST, we execute each quantum circuit on the quantum hardware for a large number of trials (8192).

2. Number of additional CNOT gates. This metric is related to the number of SWAP or Bridge gates inserted. This metric can show the ability of the algorithm to reduce the number of additional gates.

3. Trial Reduction Factor (TRF). This metric is introduced in [10] to evaluate the improvement of the throughput thanks to the multi-programming mechanism. It is defined as the ratio of the number of trials/shots needed when quantum circuits are executed independently to the number of trials/shots needed when they are executed simultaneously.

## 7.1.2 Comparison

Several published qubit mapping algorithms [16, 18, 22, 25, 28, 40] and multi-programming mapping algorithms [10, 23] are available. We choose HA [28] as the baseline for independent execution, a qubit mapping algorithm taking hardware topology and calibration data into consideration to achieve high circuit fidelity with a reduced number of additional gates. Due to the different hardware access and code unavailability of the state-of-the-art multi-programming algorithms, we only compare our QuMC with independent executions to show the impact of the multi-programming mechanism. Moreover, our qubit partition algorithms can also be applied to the qubit mapping algorithm for independent executions if running a program on a relatively large quantum device.

To summarize, the following comparisons are performed:

* For independent executions, we compare the partition + improved mapping transition algorithm based on HA (labeled as PHA) versus HA to show the impact of partition on large quantum hardware for a small circuit.

* For simultaneous executions, we compare our QuMC framework, 1) GSP + improved mapping transition (labeled as GSP) and 2) QHSP + improved mapping transition (labeled as QHSP), with independent executions, HA and PHA, to report the fidelity loss due to simultaneous executions of multiple circuits.

A detailed summary of the comparisons for independent and simultaneous executions is shown in Table 2. Note that, PHA allows each quantum circuit to be executed on the best partition selected according to the partition fidelity score metric.

## 7.1.3 Benchmarks

We evaluate our QuMC framework by executing a list of different-size benchmarks at the same time on two quantum devices, IBM Q 27 Toronto (ibmq_toronto) and IBM Q 65
<table><caption>Table 2: A summary of comparisons for independent and simultaneous executions.</caption><thead><tr><th rowspan="2">Comparison</th><th colspan="2">Independent</th><th colspan="2">Simultaneous</th></tr><tr><th>HA</th><th>PHA</th><th>GSP</th><th>QHSP</th></tr></thead><tbody><tr><td>Methods</td><td>HA</td><td>PHA</td><td>GSP</td><td>QHSP</td></tr><tr><td>Partition</td><td>N/A</td><td>Algorithm. 2</td><td>Algorithm. 1</td><td>Algorithm. 2</td></tr><tr><td>Mapping</td><td>[28]</td><td></td><td>Algorithm. 3</td><td></td></tr></tbody></table>

HA method does not include partition process.

<table><caption>Table 3: Information of benchmarks.</caption><thead><tr><th>Type</th><th>ID</th><th>Name</th><th>Qubits</th><th>Num_g</th><th>Num_CNOT</th><th>Depth</th></tr></thead><tbody><tr><td>Small</td><td>1</td><td>3_17_13</td><td>3</td><td>36</td><td>17</td><td>22</td></tr><tr><td>Small</td><td>2</td><td>4mod5-v1.22</td><td>5</td><td>21</td><td>11</td><td>12</td></tr><tr><td>Small</td><td>3</td><td>mod5mils_65</td><td>5</td><td>35</td><td>16</td><td>21</td></tr><tr><td>Small</td><td>4</td><td>alu-v0.27</td><td>5</td><td>36</td><td>17</td><td>21</td></tr><tr><td>Small</td><td>5</td><td>decod24-v2.43</td><td>4</td><td>52</td><td>22</td><td>30</td></tr><tr><td>Medium</td><td>6</td><td>qaoa_6</td><td>6</td><td>49</td><td>24</td><td>26</td></tr><tr><td>Medium</td><td>7</td><td>qaoa_8</td><td>8</td><td>80</td><td>42</td><td>38</td></tr><tr><td>Medium</td><td>8</td><td>qaoa_10</td><td>10</td><td>102</td><td>54</td><td>38</td></tr><tr><td>Medium</td><td>9</td><td>qft_6</td><td>6</td><td>81</td><td>39</td><td>40</td></tr><tr><td>Medium</td><td>10</td><td>qft_8</td><td>8</td><td>147</td><td>68</td><td>56</td></tr><tr><td>Medium</td><td>11</td><td>qft_10</td><td>10</td><td>233</td><td>105</td><td>72</td></tr><tr><td>Medium</td><td>12</td><td>ising_5</td><td>5</td><td>91</td><td>40</td><td>48</td></tr><tr><td>Medium</td><td>13</td><td>ising_10</td><td>10</td><td>481</td><td>90</td><td>70</td></tr><tr><td>Large</td><td>14</td><td>adr4_197</td><td>13</td><td>3439</td><td>1498</td><td>1839</td></tr><tr><td>Large</td><td>15</td><td>radd_250</td><td>13</td><td>3213</td><td>1405</td><td>1781</td></tr><tr><td>Large</td><td>16</td><td>z4_268</td><td>11</td><td>3073</td><td>1343</td><td>1644</td></tr><tr><td>Large</td><td>17</td><td>rd73_252</td><td>10</td><td>5321</td><td>2319</td><td>2867</td></tr><tr><td>Large</td><td>18</td><td>cycle10_2_110</td><td>12</td><td>6050</td><td>2648</td><td>3386</td></tr><tr><td>Large</td><td>19</td><td>sqn_258</td><td>10</td><td>10223</td><td>4459</td><td>5458</td></tr><tr><td>Large</td><td>20</td><td>16QBT_10CYC_TFL_4</td><td>16</td><td>73</td><td>29</td><td>10</td></tr><tr><td>Large</td><td>21</td><td>16QBT_15CYC_TFL_3</td><td>16</td><td>109</td><td>44</td><td>15</td></tr><tr><td>Large</td><td>22</td><td>16QBT_100CYC_QSE_4</td><td>16</td><td>1136</td><td>320</td><td>100</td></tr><tr><td>Large</td><td>23</td><td>16QBT_200CYC_QSE_1</td><td>16</td><td>2272</td><td>640</td><td>200</td></tr></tbody></table>

Qubits: number of qubits. Num_g: number of gates. Num_CNOT: number of CNOTs. Depth: circuit depth.
Manhattan (ibmq_manhattan). The benchmarks are collected from QUEKO circuits [37], application-specific benchmarks, and RevLib [39]. These benchmarks are widely used in the quantum community and their details are shown in Table 3. We execute small quantum circuits with shallow-depth on the selected two quantum devices since only they can obtain reliable results. For medium and large quantum circuits, we compile them on the chips without hardware execution.

### 7.1.4 Algorithm configurations

Here, we consider the algorithm configurations of different multi-programming and stand-alone mapping approaches. We select the best initial mapping out of ten attempts for HA, PHA, GSP, and QHSP. Weight parameter *W* in the cost function (see (5)) is set to 0.5 and the size of the extended layer is set to 20. Parameters $\alpha_1$ and $\alpha_2$ are set to 0.5 respectively to consider equally the swap distance and swap error rate.

For the experiments of simultaneous executions of multiple different-size circuits (Section 7.2), the weight parameter $\lambda$ of QHSP (see (2)) is set to 2 because of the relatively large number of CNOT gates in benchmarks, whereas for the deuteron experiment (Section 7.3), $\lambda$ is set to 1 because of the small number of CNOTs of the parameterized circuit. The threshold $\delta$ for post qubit partition is set to 0.1 to ensure the multi-programming reliability. Due to the expensive cost of SRB, we perform SRB only on IBM Q 27 Toronto and collect the pairs with significant crosstalk effect. Only the collected pairs are characterized and their crosstalk properties are provided to the partition process. The experimental results on IBM Q 65 Manhattan do not consider the crosstalk effect. For each algorithm, we only evaluate the mapping transition process, which means no optimisation methods like gate commutation or cancellation are applied.

The algorithm is implemented in Python and evaluated on a PC with 1 Intel i5-5300U CPU and 8 GB memory. Operating System is Ubuntu 18.04. All the experiments were performed on the IBM quantum information science kit (Qiskit) [13] and the version used is 0.21.0.

## 7.2 Application: simultaneous executions of multiple circuits of different sizes

### 7.2.1 Experimental results

<figure><img src="image_10.png" /><figcaption>Figure 8: Comparison of average fidelity and total number of additional gates on IBM Q 27 Toronto when executing two small circuits independently and simultaneously. TRF=2. (a) Fidelity. (b) Number of additional gates.</figcaption></figure>
<figure><img src="image_11.png" /><figcaption>Figure 9: Comparison of average fidelity and total number of additional gates on IBM Q 65 Manhattan when executing three small circuits independently and simultaneously. TRF=3. (a) Fidelity. (b) Number of additional gates.</figcaption></figure>

<figure><img src="image_12.png" /><figcaption>Figure 10: Comparison of average fidelity and total number of additional gates on IBM Q 65 Manhattan when executing four small circuits independently and simultaneously. TRF=4. (a) Fidelity. (b) Number of additional gates.</figcaption></figure>

We first run two small quantum circuits on IBM Q 27 Toronto independently and simultaneously. Results on average output state fidelity and the total number of additional gates are shown in Fig. 8. Note that, all the circuit output fidelities are calculated by PST metric explained in Section 7.1.1.

For independent executions, the fidelity is improved by 46.8% and the number of additional gates is reduced by 8.7% comparing PHA to HA. For simultaneous executions, QHSP and GSP allocate the same partitions except for the first experiment – (ID1, ID1). In this experiment, GSP improves the fidelity by 6% compared to QHSP. Note that partition results might be different due to the various calibration data and the choice of $\lambda$, but the difference of the partition fidelity score between the two algorithms is small. The results show that QHSP is able to allocate nearly optimal partitions while reducing runtime significantly (from exponential to polynomial complexity). Therefore, for the rest experiments, we only evaluate QHSP algorithm. Comparing QHSP (simultaneous executions) versus
<figure><img src="image_13.png" /><figcaption>Figure 11: Comparison of total number of additional gates for medium benchmarks when (a) compiling two benchmarks on IBM Q 27 Toronto (TRF=2). (b) compiling three benchmarks on IBM Q 65 Manhattan (TRF=3).</figcaption></figure>

<figure><img src="image_14.png" /><figcaption>Figure 12: Comparison of total number of additional gates for large benchmarks when compiling two benchmarks on IBM Q 65 Manhattan (TRF=2).</figcaption></figure>
HA (independent executions), the fidelity is even improved by 31.8% and the number of additional gates is reduced by 9.2%. Whereas comparing QHSP with PHA, the fidelity is decreased by 5.4% and the gate number is almost the same, with only 0.3% increase. During the post-partition process, $\Delta S$ does not pass the threshold for all the combinations of benchmarks so that TRF is two, which means that the hardware throughput is improved by two times.

Next, we execute on IBM Q 65 Manhattan three and four simultaneous quantum circuits and compare the results with the independent executions. Fig. 9 and Fig. 10 show the comparison of fidelity and the number of additional gates. PHA outperforms HA for independent executions in most of the cases. Comparing QHSP with HA, the fidelity is improved by 5.3% and 13.3% for three and four simultaneous executions, and the inserted gate number is always reduced. Whereas the fidelities decrease by 1.5% and 6.4% respectively for the two cases when comparing QHSP versus PHA, and the additional gate number is always almost the same. The threshold is still not passed for each experiment and TRF becomes three and four.

Then, to evaluate the hardware limitations of executing multiple circuits in parallel, we set the threshold $\delta$ to 0.2. All the five small benchmarks are able to be executed simultaneously on IBM Q 65 Manhattan. Partition fidelity difference is 0.18. The average fidelity of simultaneous executions (QHSP) and independent executions (PHA) is 0.493 and 0.54, respectively, corresponding to a fidelity loss of 9.5%.

Finally, to illustrate our QHSP algorithm's performance on medium and large benchmarks, we compile two medium-size circuits on IBM Q 27 Toronto, two medium-size circuits and three large-size circuits on IBM Q 65 Manhattan, simultaneously. We compare the results with HA and PHA for independent compilation. Since these benchmarks are not able to obtain meaningful results due to the noise, we do not execute them on the real hardware and only use the number of additional gates as the comparison metric. The results are shown in Fig. 11 and Fig. 12. The additional gate number is reduced by 23.2%, 15.6%, and 13.2% respectively comparing QHSP with HA. When compared with PHA, the additional gate number is increased by 0.9% and 6.4%, and is reduced by 4.5% respectively. All the program-wise experimental results are listed in Appendix A.

### 7.2.2 Result analysis

PHA is always better than HA for independent executions for two reasons: (1) The initial mapping of the two algorithms is based on a random process. During the experiment, we perform the initial mapping generation process ten times and select the best one. However, for PHA, we first limit the random process into a reliable and well-connected small partition space rather than the overall hardware space used by HA. Therefore, with only ten trials, PHA finds a better initial mapping. (2) We improve the mapping transition process of PHA, which can make a better selection between SWAP and Bridge gate. HA is shown to be sufficient for hardware with a small number of qubits, for example a 5-qubit quantum chip. If we want to map a circuit on large hardware, it is better to first limit the search space into a reliable small partition and then find the initial mapping. This qubit partition approach can be applied to general qubit mapping problems for search space limitation when large hardware is selected to map.

Comparing simultaneous process QHSP to independent process HA, QHSP is able to outperform HA with higher fidelity and a reduced number of additional gates. The improvement is also due to the partition allocation and the enhancement of the mapping transition process as explained before. When comparing QHSP with PHA (where independent circuit is executed on the best partition), QHSP uses almost the same number of
additional gates whereas fidelity is decreased less than 10% if the threshold is set to 0.1. However, the hardware throughput increases by two and four times respectively for the two devices. Note that, it also corresponds to a huge reduction of total runtime of these circuits (waiting time + circuit execution time).

## 7.3 Application: estimate the ground state energy of deuteron

In order to demonstrate the potential interest to apply the multi-programming mechanism to existing quantum algorithms, we investigate it on VQE algorithm. To do this, we perform the same experiment as [11, 15] on IBM Q 65 Manhattan, estimating the ground state energy of deuteron, which is the nucleus of a deuterium atom, an isotope of hydrogen.

Deuteron can be modeled using a 2-qubit Hamiltonian spanning four Pauli strings: $ZI, IZ, XX$, and $YY$ [11, 15]. If we use the naive measurement to calculate the state energy, one ansatz corresponds to four different measurements. Pauli operator grouping (labeled as PG) has been proposed to reduce this overhead by utilizing simultaneous measurement [7, 15, 19]. For example, the Pauli strings can be partitioned into two commuting families: $\{ZI, IZ\}$ and $\{XX, YY\}$ using the approach proposed in [15]. It allows one parameterized ansatz to be measured twice instead of four measurements in naive method.

We use a simplified Unitary Coupled Cluster ansatz with a single parameter and three gates, as described in [11, 15]. We apply our QuMC method on the top of the Pauli operator grouping approach (labeled as QuMCPG) to estimate the ground state energy of deuteron and compare the results with PG.

In our QuMC method, the parallelism manager works with the hardware-aware multi-programming compiler to determine the number of circuits for simultaneous execution. Eight circuits are selected in order not to pass the fidelity threshold, which correspond to four parameterized circuits with four different parameters since one parameterized circuit requires two measurement circuits using PG. It is also equivalent to perform four times of optimizations. These circuits can be executed simultaneously using QuMCPG, which reduces the total circuit runtime by eight times compared with PG for independent execution. We perform this experiment five times across days with different calibration data. Note that, if we use the naive measurement, the number of measurement circuits needed will be reduced by a factor of 16. The results of the five experiments using PG (independent process) and QuMCPG (simultaneous process) are shown in Fig. 13. We use simulator to perform the same experiment and set the result as baseline. The sum of the difference between the obtained result (independent or simultaneous process) and baseline (using simulator) is represented by the error rate. All the partition fidelity differences $\Delta S$ of the five experiments (on average $\Delta S=0.06$) are less than the threshold $\delta$ (set to 0.1). Compared to the baseline, the average error rates are 9% and 13.3% for PG and QuMCPG, respectively. Despite the augmented errors, the hardware throughput is improved by eight times. Note that, the users can tune the threshold $\delta$ according to the tolerance of the increase of error rate while using multi-programming. More information about the experimental results can be found in Table 4.

<table><caption>Table 4: The information of the five experiments.</caption><thead><tr><th>Experiments</th><th>$n_c$<sup>1</sup></th><th>Error rate(%)</th><th>Hardware throughput</th></tr></thead><tbody><tr><td>PG</td><td>1</td><td>9</td><td>0.03</td></tr><tr><td>QuMCPG</td><td>8</td><td>13.3</td><td>0.25</td></tr></tbody></table>

<footnote n="1">¹ the number of simultaneous circuit number.</footnote>
<figure><img src="image_15.png" /><figcaption>Figure 13: The estimation of the ground state energy of deuteron under PG and QuMCPG with four optimisations. (a) PG result (independent process) with eight measurements. (b) QuMCPG result (simultaneous process) with one measurement. TRF=8.</figcaption></figure>

# 8 Discussion

## 8.1 Multi-programming mechanism and fidelity loss

The aforementioned experimental results have shown that, the multi-programming mechanism can improve the hardware utilization and reduce the total circuit runtime, but with a cost of slightly losing circuit fidelity. However, the multi-programming mechanism is not always detrimental to circuit fidelity. Especially for large quantum hardware, the partition that has high fidelity is not limited to one region. We choose the largest superconducting quantum hardware, IBM 127 Q Washington (ibmq_washington) to demonstrate it. We pick the two partitions with the highest fidelities according to our partition score metric (3) and execute two of the same circuits on the two partitions simultaneously. The score difference between the two partitions is around 0.01 and they are not adjacent to each other, so that no additional crosstalk. The benchmarks are taken from Table 3 and represented by their IDs. We repeat this experiment five times and the results are shown in Fig. 14. P1 is the partition with the highest score and P2 with the second highest score. From the experimental results, the fidelity of the circuit on P1 cannot always outperform P2 (see benchmarks 2 and 5). It might be due to the following reasons: (1) The calibration data are not 100% precise. Since the partitions have almost the same fidelity scores, the circuits executed on the two partitions should also have similar results. (2) The calibration data are not constant. If the circuits are waiting for a long time in the queue, the calibration data might get updated, so that the partition with the highest fidelity score when submitted the circuit might not be the best one when the circuit is executed.

## 8.2 Multi-programming on circuits with varying depths

The depths of benchmarks that we have executed on quantum hardware in Section 7.2 are not dramatically different, i.e., the longest circuit depth (decod24-v2_43) is 2.5 times longer than the shortest one (4mod5-v1_22). The program-wise results from Table 5, Table 7, and Table 9 have shown that the fidelity of the circuit with slightly shorter depth is not influenced by the parallel execution.

In this section, we further discuss the impact of multi-programming on circuits with
<figure><img src="image_16.png" /><figcaption>Figure 14: Comparison of fidelity on IBM Q 127 Washington when executing two of the same circuits on partitions P1 and P2 simultaneously.</figcaption></figure>

<figure><img src="image_17.png" /><figcaption>Figure 15: IBM Q 7 Nairobi hardware topology. P1 and P2 are selected to execute circuits with varying depths.</figcaption></figure>
<figure><img src="image_18.png" /><figcaption>Figure 16: Comparison of fidelity on IBM Q 7 Nairobi when executing two circuits with varying depths on P1 and P2 independently and simultaneously. The blue and red columns represent the fidelities of the original circuit (fixed depth 22). The gray and yellow columns represent the fidelities of the modified circuit (depth from 22 to 88).</figcaption></figure>

comparable or dramatically different depths. We use the largest IBM public chip IBM Q 7 Nairobi (ibm_nairobi) to perform the experiment<fnref n="1" />, and its hardware topology is shown in Fig. 15. We choose two partitions P1 and P2, which are more than one hop distance so that no additional crosstalk impact exists. First, we execute a three-qubit small circuit 3_17_13 with circuit depth of 22 (the information of this circuit can be found in Table 3) in P1 individually. Second, we repeat the circuit to increase its depth from one to four times and execute the circuit with varying depths in P2 individually. Finally, we execute the original circuit (depth 22) and the modified circuit (depth from 22 to 88) on P1 and P2 simultaneously. Based on the results shown in Fig. 16, the fidelities of circuits with varying depths are not influenced by parallel executions, since all the circuit operations are scheduled “as late as possible”.

## 9 Conclusion

In this article, we presented QuMC, a multi-programming approach that allows to execute multiple circuits on a quantum chip simultaneously without losing fidelity. We introduced the parallelism manager and fidelity metric to select optimally the number of circuits to be executed at the same time. Moreover, we proposed a hardware-aware multi-programming compiler which contains two qubit partition algorithms taking hardware topology, calibration data, and crosstalk effect into account to allocate reliable partitions to different quantum circuits. We also demonstrated an improved simultaneous mapping transition algorithm which helps to transpile the circuits on quantum hardware with a reduced number of inserted gates.

We first executed a list of circuits of different sizes simultaneously and compared our algorithm with the state of the art. Experimental results showed that our QuMC can even outperform the independent executions using state of the art qubit mapping approach. Then, we investigated our QuMC approach on VQE algorithm to estimate the ground state energy of deuteron, showing the added value of applying our approach to existing

<footnote n="1">¹During the preparation of the manuscript, we do not have access to IBM private chips any more due to the end of the contract.</footnote>
quantum algorithms. The QuMC approach is evaluated on IBM hardware, but it is general enough to be adapted to other quantum hardware.

Based on the experimental result, we found that the main concern with multi-programming mechanism is a trade-off between output fidelity and the hardware throughput. For example, how one can decide which programs to execute simultaneously and how many of them to execute without losing fidelity. Here, we list several guidelines to help the user to utilize our QuMC approach.

* Check the target hardware topology and calibration data. The multi-programming mechanism is more suitable for a relatively large quantum chip compared to the quantum circuit and with low error rate.

* Choose appropriate fidelity threshold for the post qubit partition process. A high threshold can improve the hardware throughput but lead to the reduction of output fidelity. It should be set carefully depending on the size of the benchmark. For benchmarks of small size that we used in experiments, it is reasonable to set the threshold to 0.1.

* The number of circuits that can be executed simultaneously will mainly depend on the fidelity threshold and the calibration data of the hardware.

* The QHSP algorithm is suggested for the partition process due to efficiency and GSP is recommended to evaluate the quality of the partition algorithms. Using both algorithms, one can explore which circuits can be executed simultaneously and how many of them within the given fidelity threshold.

Quantum hardware development with more and more qubits will enable execution of multiple quantum programs simultaneously and possibly a linchpin for quantum algorithms requiring parallel sub-problem executions. The Variational Quantum Algorithm is becoming a leading strategy to demonstrate quantum advantages for practical applications. In such algorithms, the preparation of parameterized quantum state and the measurement of expectation value are realized on shallow circuits [41]. Taking VQE as an example, the Hamiltonian can be decomposed into several Pauli operators and simultaneous measurement by grouping Pauli operators have been proposed in [7, 15, 19] to reduce the overhead of the algorithm. Based on our experiment, we have shown that the overhead of VQE can be further improved by executing several sets of Pauli operators simultaneously using a multi-programming mechanism. For future work, we would like to apply our QuMC to other variational quantum algorithms such as VQLS or VQC to prepare states in parallel and reduce the overhead of these algorithms. Moreover, in our qubit partition algorithms, we take the crosstalk effects into consideration by characterizing them and adding them to the fidelity score of the partition, which is able to avoid the crosstalk error in a high level. There are some other approaches of eliminating the crosstalk error, for example inserting barriers between simultaneous CNOTs to avoid crosstalk in a gate-level [26]. However, it has some challenges of trading-off between crosstalk and decoherence. More interesting tricks for crosstalk mitigation need to be targeted for simultaneous executions.

## Supplementary material

The source code of the algorithms used in this paper is available on the Github repository https://github.com/peachnuts/Multiprogramming.
Acknowledgment

This work is funded by the QuantUM Initiative of the Region Occitanie, University of
Montpellier and IBM Montpellier. The authors are very grateful to Adrien Suau for the
helpful suggestions and feedback on an early version of this manuscript. We acknowledge
use of the IBM Q for this work. The views expressed are those of the authors and do not
reflect the official policy or position of IBM or the IBM Q team.

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<table><caption>Table 5: Comparison of fidelity when executing two small circuits simultaneously on IBM Q 27 Toronto.</caption><thead><tr><th colspan="2">Benchmarks</th><th colspan="10">Independent</th><th colspan="2">Correlated</th><th colspan="2">Comparison</th></tr><tr><th colspan="2">ID</th><th colspan="3">HA</th><th colspan="3">PHA</th><th colspan="3">QHSP</th><th colspan="3">GSP</th><th colspan="2">Δ<sub>PST</sub>%</th></tr><tr><th>ID1</th><th>ID2</th><th>PST1</th><th>PST2</th><th>Avg</th><th>PST1</th><th>PST2</th><th>Avg</th><th>PST1</th><th>PST2</th><th>Avg</th><th>t</th><th>PST1</th><th>PST2</th><th>Avg</th><th>t</th><th>HA</th><th>PHA</th></tr></thead><tbody><tr><td>1</td><td>1</td><td>0.571</td><td>0.558</td><td>0.565</td><td>0.686</td><td>0.676</td><td>0.681</td><td>0.675</td><td>0.641</td><td>0.658</td><td>0.009</td><td>0.641</td><td>0.682</td><td>0.662</td><td>0.4</td><td>16.5</td><td>-3.4</td></tr><tr><td>1</td><td>2</td><td>0.334</td><td>0.75</td><td>0.542</td><td>0.661</td><td>0.789</td><td>0.725</td><td>0.69</td><td>0.789</td><td>0.74</td><td>0.012</td><td>0.69</td><td>0.789</td><td>0.74</td><td>7.4</td><td>36.5</td><td>2.1</td></tr><tr><td>1</td><td>3</td><td>0.547</td><td>0.412</td><td>0.48</td><td>0.687</td><td>0.591</td><td>0.639</td><td>0.619</td><td>0.552</td><td>0.586</td><td>0.007</td><td>0.619</td><td>0.552</td><td>0.586</td><td>7.4</td><td>22.1</td><td>-8.3</td></tr><tr><td>1</td><td>4</td><td>0.476</td><td>0.45</td><td>0.463</td><td>0.574</td><td>0.642</td><td>0.608</td><td>0.626</td><td>0.647</td><td>0.637</td><td>0.016</td><td>0.626</td><td>0.647</td><td>0.637</td><td>7.4</td><td>37.6</td><td>4.8</td></tr><tr><td>1</td><td>5</td><td>0.495</td><td>0.445</td><td>0.47</td><td>0.673</td><td>0.582</td><td>0.628</td><td>0.647</td><td>0.511</td><td>0.579</td><td>0.012</td><td>0.647</td><td>0.511</td><td>0.579</td><td>1.6</td><td>23.2</td><td>-7.8</td></tr><tr><td>2</td><td>2</td><td>0.647</td><td>0.53</td><td>0.589</td><td>0.78</td><td>0.775</td><td>0.778</td><td>0.808</td><td>0.591</td><td>0.7</td><td>0.006</td><td>0.808</td><td>0.591</td><td>0.7</td><td>14.4</td><td>18.8</td><td>-10</td></tr><tr><td>2</td><td>3</td><td>0.428</td><td>0.304</td><td>0.366</td><td>0.787</td><td>0.626</td><td>0.707</td><td>0.764</td><td>0.529</td><td>0.647</td><td>0.013</td><td>0.764</td><td>0.529</td><td>0.647</td><td>15</td><td>76.8</td><td>-8.5</td></tr><tr><td>2</td><td>4</td><td>0.561</td><td>0.607</td><td>0.584</td><td>0.791</td><td>0.645</td><td>0.718</td><td>0.788</td><td>0.467</td><td>0.628</td><td>0.008</td><td>0.788</td><td>0.467</td><td>0.628</td><td>14.7</td><td>7.5</td><td>-12.5</td></tr><tr><td>2</td><td>5</td><td>0.573</td><td>0.311</td><td>0.442</td><td>0.796</td><td>0.568</td><td>0.682</td><td>0.774</td><td>0.531</td><td>0.653</td><td>0.006</td><td>0.774</td><td>0.531</td><td>0.653</td><td>8.7</td><td>47.7</td><td>-4.3</td></tr></tbody></table>

Avg: average of PSTs. t: runtime in seconds of the partition process. Δ<sub>PST</sub>: comparison of average fidelity.

<table><caption>Table 6: Comparison of number of additional gates when executing two small circuits simultaneously on IBM Q 27 Toronto.</caption><thead><tr><th colspan="2">Benchmarks</th><th colspan="3">Independent</th><th colspan="3">Correlated</th><th colspan="2">Comparison</th></tr><tr><th colspan="2">ID</th><th colspan="3">HA</th><th colspan="3">PHA</th><th colspan="2">Δ<sub>g</sub>%</th></tr><tr><th>ID1</th><th>ID2</th><th>g<sub>1</sub></th><th>g<sub>2</sub></th><th>Sum</th><th>g<sub>1</sub></th><th>g<sub>2</sub></th><th>Sum</th><th>g<sub>1</sub></th><th>g<sub>2</sub></th><th>Sum</th><th>HA</th><th>PHA</th></tr></thead><tbody><tr><td>1</td><td>1</td><td>12</td><td>12</td><td>24</td><td>12</td><td>12</td><td>24</td><td>12</td><td>12</td><td>24</td><td>0</td><td>0</td></tr><tr><td>1</td><td>2</td><td>12</td><td>9</td><td>21</td><td>12</td><td>6</td><td>18</td><td>12</td><td>6</td><td>18</td><td>14.3</td><td>0</td></tr><tr><td>1</td><td>3</td><td>12</td><td>15</td><td>27</td><td>12</td><td>15</td><td>27</td><td>12</td><td>15</td><td>27</td><td>0</td><td>0</td></tr><tr><td>1</td><td>4</td><td>12</td><td>24</td><td>36</td><td>12</td><td>24</td><td>36</td><td>12</td><td>21</td><td>33</td><td>8.3</td><td>8.3</td></tr><tr><td>1</td><td>5</td><td>12</td><td>18</td><td>30</td><td>12</td><td>18</td><td>30</td><td>12</td><td>18</td><td>30</td><td>0</td><td>0</td></tr><tr><td>2</td><td>2</td><td>6</td><td>12</td><td>18</td><td>6</td><td>6</td><td>12</td><td>6</td><td>9</td><td>15</td><td>16.7</td><td>-25</td></tr><tr><td>2</td><td>3</td><td>9</td><td>15</td><td>24</td><td>6</td><td>15</td><td>21</td><td>6</td><td>12</td><td>18</td><td>25</td><td>14.3</td></tr><tr><td>2</td><td>4</td><td>9</td><td>24</td><td>33</td><td>6</td><td>21</td><td>27</td><td>6</td><td>21</td><td>27</td><td>18.2</td><td>0</td></tr><tr><td>2</td><td>5</td><td>6</td><td>18</td><td>24</td><td>6</td><td>18</td><td>24</td><td>6</td><td>18</td><td>24</td><td>0</td><td>0</td></tr></tbody></table>

g: number of additional gates. Sum: sum of number of additional gates. Δ<sub>g</sub>: comparison of sum of number of additional gates.

## A Supplementary experimental results

The program-wise experimental results of executing two small circuits simultaneously on IBM Q 27 Toronto (Table 5, Table 6), three small circuits (Table 7, Table 8) and four small circuits (Table 9, Table 10) on IBM Q 65 Manhattan, medium and large circuits on the two devices are listed (Table 11, Table 12, Table 13).
<table><caption>Table 7: Comparison of fidelity when executing three small circuits simultaneously on IBM Q 65 Manhattan.</caption><thead><tr><th colspan="3">Benchmarks</th><th colspan="10">Independent</th><th colspan="2">Correlated</th><th colspan="2">Comparison</th></tr><tr><th colspan="3">ID</th><th colspan="4">HA</th><th colspan="4">PHA</th><th colspan="4">QHSP</th><th colspan="2">Δ<sub>PST</sub>%</th></tr><tr><th>ID1</th><th>ID2</th><th>ID3</th><th>PST1</th><th>PST2</th><th>PST3</th><th>Avg</th><th>PST1</th><th>PST2</th><th>PST3</th><th>Avg</th><th>PST1</th><th>PST2</th><th>PST3</th><th>Avg</th><th>t</th><th>HA</th><th>PHA</th></tr></thead><tbody><tr><td>1</td><td>2</td><td>3</td><td>0.61</td><td>0.566</td><td>0.624</td><td>0.6</td><td>0.651</td><td>0.624</td><td>0.555</td><td>0.61</td><td>0.609</td><td>0.526</td><td>0.714</td><td>0.616</td><td>0.047</td><td>2.7</td><td>1</td></tr><tr><td>1</td><td>2</td><td>4</td><td>0.521</td><td>0.683</td><td>0.289</td><td>0.5</td><td>0.637</td><td>0.703</td><td>0.48</td><td>0.607</td><td>0.559</td><td>0.708</td><td>0.531</td><td>0.599</td><td>0.048</td><td>19.8</td><td>-1.3</td></tr><tr><td>1</td><td>2</td><td>5</td><td>0.627</td><td>0.725</td><td>0.368</td><td>0.573</td><td>0.623</td><td>0.653</td><td>0.487</td><td>0.588</td><td>0.609</td><td>0.592</td><td>0.528</td><td>0.576</td><td>0.047</td><td>0.5</td><td>-2</td></tr><tr><td>2</td><td>3</td><td>4</td><td>0.644</td><td>0.434</td><td>0.389</td><td>0.489</td><td>0.631</td><td>0.566</td><td>0.544</td><td>0.58</td><td>0.633</td><td>0.565</td><td>0.498</td><td>0.565</td><td>0.04</td><td>15.5</td><td>-2.6</td></tr><tr><td>2</td><td>3</td><td>5</td><td>0.689</td><td>0.617</td><td>0.488</td><td>0.598</td><td>0.585</td><td>0.542</td><td>0.486</td><td>0.538</td><td>0.7</td><td>0.528</td><td>0.34</td><td>0.523</td><td>0.04</td><td>-12.5</td><td>-2.8</td></tr></tbody></table>

Avg: average of PSTs. t: runtime in seconds of the partition process. Δ<sub>PST</sub>: comparison of average fidelity.

<table><caption>Table 8: Comparison of number of additional gates when executing three small circuits simultaneously on IBM Q 65 Manhattan.</caption><thead><tr><th colspan="3">Benchmarks</th><th colspan="10">Independent</th><th colspan="2">Correlated</th><th colspan="2">Comparison</th></tr><tr><th colspan="3">ID</th><th colspan="4">HA</th><th colspan="4">PHA</th><th colspan="4">QHSP</th><th colspan="2">Δ<sub>g</sub>%</th></tr><tr><th>ID1</th><th>ID2</th><th>ID3</th><th>g<sub>1</sub></th><th>g<sub>2</sub></th><th>g<sub>3</sub></th><th>Sum</th><th>g<sub>1</sub></th><th>g<sub>2</sub></th><th>g<sub>3</sub></th><th>Sum</th><th>g<sub>1</sub></th><th>g<sub>2</sub></th><th>g<sub>3</sub></th><th>Sum</th><th>HA</th><th>PHA</th></tr></thead><tbody><tr><td>1</td><td>2</td><td>3</td><td>12</td><td>12</td><td>12</td><td>36</td><td>12</td><td>6</td><td>12</td><td>30</td><td>12</td><td>6</td><td>12</td><td>30</td><td>16.7</td><td>0</td></tr><tr><td>1</td><td>2</td><td>4</td><td>12</td><td>9</td><td>21</td><td>42</td><td>12</td><td>6</td><td>18</td><td>36</td><td>12</td><td>6</td><td>18</td><td>36</td><td>14.3</td><td>0</td></tr><tr><td>1</td><td>2</td><td>5</td><td>12</td><td>9</td><td>18</td><td>39</td><td>12</td><td>6</td><td>18</td><td>36</td><td>12</td><td>6</td><td>18</td><td>36</td><td>7.7</td><td>0</td></tr><tr><td>2</td><td>3</td><td>4</td><td>9</td><td>15</td><td>18</td><td>42</td><td>6</td><td>12</td><td>18</td><td>36</td><td>6</td><td>15</td><td>18</td><td>39</td><td>7.1</td><td>-8.3</td></tr><tr><td>2</td><td>3</td><td>5</td><td>9</td><td>15</td><td>18</td><td>42</td><td>9</td><td>12</td><td>18</td><td>39</td><td>6</td><td>12</td><td>18</td><td>36</td><td>14.3</td><td>7.7</td></tr></tbody></table>

g: number of additional gates. Sum: sum of number of additional gates. Δ<sub>g</sub>: comparison of sum of number of additional gates.

<table><caption>Table 9: Comparison of fidelity when executing four small circuits simultaneously on IBM Q 65 Manhattan.</caption><thead><tr><th colspan="3">Benchmarks</th><th colspan="10">Independent</th><th colspan="2">Correlated</th><th colspan="2">Comparison</th></tr><tr><th colspan="3">ID</th><th colspan="4">HA</th><th colspan="4">PHA</th><th colspan="4">QHSP</th><th colspan="2">Δ<sub>PST</sub>%</th></tr><tr><th>ID1</th><th>ID2</th><th>ID3</th><th>ID4</th><th>PST1</th><th>PST2</th><th>PST3</th><th>PST4</th><th>Avg</th><th>PST1</th><th>PST2</th><th>PST3</th><th>PST4</th><th>Avg</th><th>t</th><th>HA</th><th>PHA</th></tr></thead><tbody><tr><td>1</td><td>2</td><td>3</td><td>4</td><td>0.512</td><td>0.622</td><td>0.486</td><td>0.35</td><td>0.493</td><td>0.588</td><td>0.644</td><td>0.572</td><td>0.443</td><td>0.562</td><td>0.443</td><td>0.747</td><td>0.542</td><td>0.443</td><td>0.544</td><td>0.06</td><td>10.3</td><td>-3.2</td></tr><tr><td>1</td><td>2</td><td>3</td><td>5</td><td>0.44</td><td>0.644</td><td>0.608</td><td>0.203</td><td>0.474</td><td>0.648</td><td>0.638</td><td>0.561</td><td>0.491</td><td>0.585</td><td>0.612</td><td>0.645</td><td>0.581</td><td>0.373</td><td>0.553</td><td>0.058</td><td>16.7</td><td>-5.5</td></tr><tr><td>1</td><td>3</td><td>4</td><td>5</td><td>0.6</td><td>0.542</td><td>0.228</td><td>0.289</td><td>0.415</td><td>0.592</td><td>0.504</td><td>0.497</td><td>0.404</td><td>0.499</td><td>0.557</td><td>0.53</td><td>0.32</td><td>0.426</td><td>0.458</td><td>0.058</td><td>10.4</td><td>-8.2</td></tr><tr><td>2</td><td>3</td><td>4</td><td>5</td><td>0.643</td><td>0.544</td><td>0.287</td><td>0.278</td><td>0.438</td><td>0.699</td><td>0.53</td><td>0.525</td><td>0.465</td><td>0.555</td><td>0.691</td><td>0.477</td><td>0.492</td><td>0.369</td><td>0.507</td><td>0.048</td><td>15.8</td><td>-8.6</td></tr></tbody></table>

Avg: average of PSTs. t: runtime in seconds of the partition process. Δ<sub>PST</sub>: comparison of average fidelity.

<table><caption>Table 10: Comparison of number of additional gates when executing four small circuits simultaneously on IBM Q 65 Manhattan.</caption><thead><tr><th colspan="3">Benchmarks</th><th colspan="10">Independent</th><th colspan="2">Correlated</th><th colspan="2">Comparison</th></tr><tr><th colspan="3">ID</th><th colspan="4">HA</th><th colspan="4">PHA</th><th colspan="4">QHSP</th><th colspan="2">Δ<sub>g</sub>%</th></tr><tr><th>ID1</th><th>ID2</th><th>ID3</th><th>ID4</th><th>g<sub>1</sub></th><th>g<sub>2</sub></th><th>g<sub>3</sub></th><th>g<sub>4</sub></th><th>Sum</th><th>g<sub>1</sub></th><th>g<sub>2</sub></th><th>g<sub>3</sub></th><th>g<sub>4</sub></th><th>Sum</th><th>g<sub>1</sub></th><th>g<sub>2</sub></th><th>g<sub>3</sub></th><th>g<sub>4</sub></th><th>Sum</th><th>HA</th><th>PHA</th></tr></thead><tbody><tr><td>1</td><td>2</td><td>3</td><td>4</td><td>12</td><td>9</td><td>15</td><td>24</td><td>60</td><td>12</td><td>9</td><td>15</td><td>18</td><td>54</td><td>12</td><td>6</td><td>15</td><td>18</td><td>51</td><td>15</td><td>5.6</td></tr><tr><td>1</td><td>2</td><td>3</td><td>5</td><td>12</td><td>9</td><td>15</td><td>12</td><td>48</td><td>12</td><td>6</td><td>12</td><td>18</td><td>48</td><td>12</td><td>6</td><td>15</td><td>18</td><td>51</td><td>-6.3</td><td>-6.3</td></tr><tr><td>1</td><td>3</td><td>4</td><td>5</td><td>12</td><td>15</td><td>18</td><td>18</td><td>63</td><td>12</td><td>12</td><td>18</td><td>18</td><td>60</td><td>12</td><td>12</td><td>18</td><td>18</td><td>60</td><td>4.8</td><td>0</td></tr><tr><td>2</td><td>3</td><td>4</td><td>5</td><td>6</td><td>15</td><td>21</td><td>18</td><td>60</td><td>6</td><td>15</td><td>18</td><td>18</td><td>57</td><td>6</td><td>12</td><td>18</td><td>18</td><td>54</td><td>10</td><td>5.3</td></tr></tbody></table>

g: number of additional gates. Sum: sum of number of additional gates. Δ<sub>g</sub>: comparison of sum of number of additional gates.
<table><caption>Table 11: Comparison of number of additional gates when executing two medium benchmarks on IBM Q 27 Toronto.</caption><thead><tr><th colspan="2">Benchmarks</th><th colspan="6">Independent</th><th colspan="2">Correlated</th><th colspan="2">Comparison</th></tr><tr><th colspan="2">ID</th><th colspan="3">HA</th><th colspan="3">PHA</th><th colspan="3">QHSP</th><th colspan="2">Δ<sub>g</sub>%</th></tr><tr><th>ID1</th><th>ID2</th><th>g<sub>1</sub></th><th>g<sub>2</sub></th><th>Sum</th><th>g<sub>1</sub></th><th>g<sub>2</sub></th><th>Sum</th><th>g<sub>1</sub></th><th>g<sub>2</sub></th><th>Sum</th><th>HA</th><th>PHA</th></tr></thead><tbody><tr><td>6</td><td>7</td><td>33</td><td>72</td><td>105</td><td>24</td><td>39</td><td>63</td><td>24</td><td>36</td><td>60</td><td>42.9</td><td>4.8</td></tr><tr><td>6</td><td>8</td><td>33</td><td>129</td><td>162</td><td>24</td><td>81</td><td>105</td><td>24</td><td>84</td><td>108</td><td>33.3</td><td>-2.9</td></tr><tr><td>6</td><td>9</td><td>33</td><td>51</td><td>84</td><td>24</td><td>48</td><td>72</td><td>24</td><td>54</td><td>78</td><td>7.1</td><td>-8.3</td></tr><tr><td>6</td><td>10</td><td>33</td><td>120</td><td>153</td><td>24</td><td>105</td><td>129</td><td>24</td><td>117</td><td>138</td><td>9.8</td><td>-7</td></tr><tr><td>6</td><td>11</td><td>33</td><td>210</td><td>243</td><td>24</td><td>183</td><td>207</td><td>24</td><td>198</td><td>222</td><td>8.6</td><td>-7.2</td></tr><tr><td>6</td><td>12</td><td>33</td><td>45</td><td>78</td><td>24</td><td>39</td><td>63</td><td>24</td><td>39</td><td>63</td><td>19.2</td><td>0</td></tr><tr><td>6</td><td>13</td><td>33</td><td>90</td><td>123</td><td>24</td><td>60</td><td>84</td><td>24</td><td>48</td><td>72</td><td>41.5</td><td>14.3</td></tr></tbody></table>

g: number of additional gates. Sum: sum of number of additional gates. Δg: comparison of sum of number of additional gates.

<table><caption>Table 12: Comparison of number of additional gates when executing three medium benchmarks on IBM Q 65 Manhattan.</caption><thead><tr><th colspan="3">Benchmarks</th><th colspan="6">Independent</th><th colspan="3">Correlated</th><th colspan="2">Comparison</th></tr><tr><th colspan="3">ID</th><th colspan="3">HA</th><th colspan="3">PHA</th><th colspan="3">QHSP</th><th colspan="2">Δ<sub>g</sub>%</th></tr><tr><th>ID1</th><th>ID2</th><th>ID3</th><th>g<sub>1</sub></th><th>g<sub>2</sub></th><th>g<sub>3</sub></th><th>Sum</th><th>g<sub>1</sub></th><th>g<sub>2</sub></th><th>g<sub>3</sub></th><th>Sum</th><th>g<sub>1</sub></th><th>g<sub>2</sub></th><th>g<sub>3</sub></th><th>Sum</th><th>HA</th><th>PHA</th></tr></thead><tbody><tr><td>6</td><td>7</td><td>8</td><td>27</td><td>69</td><td>111</td><td>207</td><td>18</td><td>39</td><td>93</td><td>150</td><td>18</td><td>42</td><td>93</td><td>153</td><td>26.1</td><td>-2</td></tr><tr><td>6</td><td>7</td><td>9</td><td>27</td><td>69</td><td>42</td><td>138</td><td>18</td><td>39</td><td>42</td><td>99</td><td>18</td><td>42</td><td>51</td><td>111</td><td>19.6</td><td>-12.1</td></tr><tr><td>6</td><td>7</td><td>12</td><td>27</td><td>69</td><td>42</td><td>138</td><td>18</td><td>39</td><td>39</td><td>96</td><td>18</td><td>45</td><td>48</td><td>111</td><td>19.6</td><td>-15.6</td></tr><tr><td>7</td><td>8</td><td>9</td><td>69</td><td>111</td><td>42</td><td>222</td><td>39</td><td>93</td><td>42</td><td>174</td><td>42</td><td>78</td><td>51</td><td>171</td><td>23</td><td>1.7</td></tr><tr><td>7</td><td>8</td><td>12</td><td>69</td><td>111</td><td>42</td><td>222</td><td>39</td><td>93</td><td>39</td><td>171</td><td>42</td><td>78</td><td>48</td><td>168</td><td>24.3</td><td>1.8</td></tr><tr><td>8</td><td>9</td><td>10</td><td>111</td><td>42</td><td>96</td><td>249</td><td>93</td><td>42</td><td>90</td><td>225</td><td>90</td><td>45</td><td>93</td><td>228</td><td>8.4</td><td>-1.3</td></tr><tr><td>9</td><td>10</td><td>12</td><td>42</td><td>96</td><td>42</td><td>180</td><td>42</td><td>90</td><td>39</td><td>171</td><td>42</td><td>117</td><td>42</td><td>201</td><td>-11.7</td><td>-17.5</td></tr></tbody></table>

g: number of additional gates. Sum: sum of number of additional gates. Δg: comparison of sum of number of additional gates.

<table><caption>Table 13: Comparison of number of additional gates when executing two large benchmarks on IBM Q 65 Manhattan.</caption><thead><tr><th colspan="2">Benchmarks</th><th colspan="6">Independent</th><th colspan="3">Correlated</th><th colspan="2">Comparison</th></tr><tr><th colspan="2">ID</th><th colspan="3">HA</th><th colspan="3">PHA</th><th colspan="3">QHSP</th><th colspan="2">Δ<sub>g</sub>%</th></tr><tr><th>ID1</th><th>ID2</th><th>g<sub>1</sub></th><th>g<sub>2</sub></th><th>Sum</th><th>g<sub>1</sub></th><th>g<sub>2</sub></th><th>Sum</th><th>g<sub>1</sub></th><th>g<sub>2</sub></th><th>Sum</th><th>HA</th><th>PHA</th></tr></thead><tbody><tr><td>14</td><td>14</td><td>2676</td><td>2682</td><td>5358</td><td>2400</td><td>2496</td><td>4896</td><td>2463</td><td>2469</td><td>4932</td><td>7.9</td><td>-0.7</td></tr><tr><td>14</td><td>15</td><td>2766</td><td>2475</td><td>5241</td><td>2382</td><td>2325</td><td>4707</td><td>2529</td><td>2289</td><td>4818</td><td>8.1</td><td>-2.4</td></tr><tr><td>14</td><td>16</td><td>2556</td><td>2277</td><td>4833</td><td>2388</td><td>2055</td><td>4443</td><td>2472</td><td>2166</td><td>4638</td><td>4</td><td>-4.4</td></tr><tr><td>14</td><td>17</td><td>2670</td><td>4026</td><td>6696</td><td>2502</td><td>3915</td><td>6417</td><td>2481</td><td>3789</td><td>6270</td><td>6.4</td><td>2.3</td></tr><tr><td>14</td><td>18</td><td>2685</td><td>4344</td><td>7029</td><td>2430</td><td>3942</td><td>6372</td><td>2403</td><td>3249</td><td>5652</td><td>19.6</td><td>11.3</td></tr><tr><td>14</td><td>19</td><td>2733</td><td>7458</td><td>10191</td><td>2445</td><td>6759</td><td>9204</td><td>2457</td><td>6795</td><td>9252</td><td>9.2</td><td>-0.5</td></tr><tr><td>15</td><td>15</td><td>2409</td><td>2538</td><td>4947</td><td>2214</td><td>2193</td><td>4407</td><td>2226</td><td>2193</td><td>4419</td><td>10.7</td><td>-0.3</td></tr><tr><td>15</td><td>16</td><td>2328</td><td>1986</td><td>4314</td><td>2049</td><td>1983</td><td>4032</td><td>2295</td><td>2052</td><td>4347</td><td>-0.8</td><td>-7.8</td></tr><tr><td>15</td><td>17</td><td>2454</td><td>4215</td><td>6669</td><td>2121</td><td>3555</td><td>5676</td><td>2058</td><td>3756</td><td>5814</td><td>12.8</td><td>-2.4</td></tr><tr><td>15</td><td>18</td><td>2448</td><td>3693</td><td>6141</td><td>2157</td><td>3792</td><td>5949</td><td>2202</td><td>3417</td><td>5619</td><td>8.5</td><td>5.5</td></tr><tr><td>15</td><td>19</td><td>2643</td><td>7395</td><td>10038</td><td>2112</td><td>6741</td><td>8853</td><td>2325</td><td>6915</td><td>9240</td><td>7.9</td><td>-4.4</td></tr><tr><td>20</td><td>20</td><td>75</td><td>84</td><td>159</td><td>69</td><td>75</td><td>144</td><td>60</td><td>54</td><td>114</td><td>28.3</td><td>20.8</td></tr><tr><td>20</td><td>21</td><td>81</td><td>87</td><td>168</td><td>81</td><td>78</td><td>159</td><td>51</td><td>81</td><td>132</td><td>21.4</td><td>16.9</td></tr><tr><td>20</td><td>22</td><td>78</td><td>723</td><td>801</td><td>69</td><td>615</td><td>684</td><td>63</td><td>552</td><td>615</td><td>23.2</td><td>10.1</td></tr><tr><td>20</td><td>23</td><td>87</td><td>1416</td><td>1503</td><td>45</td><td>1275</td><td>1320</td><td>78</td><td>1050</td><td>1128</td><td>25</td><td>14.5</td></tr><tr><td>21</td><td>22</td><td>102</td><td>693</td><td>795</td><td>72</td><td>648</td><td>720</td><td>105</td><td>555</td><td>660</td><td>17</td><td>8.3</td></tr><tr><td>21</td><td>23</td><td>120</td><td>1326</td><td>1446</td><td>78</td><td>1266</td><td>1344</td><td>75</td><td>1152</td><td>1227</td><td>15.1</td><td>8.7</td></tr></tbody></table>

g: number of additional gates. Sum: sum of number of additional gates. Δg: comparison of sum of number of additional gates.