# A Feedback-Enhanced Approach to Modeling Semiconductor Ageing in Electric Vehicle Inverters

Sebastian Rode ID

Chair of Power Electronics

TU Dresden

Dresden, Germany

sebastian.rode@tu-dresden.de

Hulin Liang ID

TU Berlin

Berlin, Germany

Steffen Bernet ID

Chair of Power Electronics

TU Dresden

Dresden, Germany

*Index Terms*—reliability, electric vehicle (EV), lifetime, predictive fatigue modeling, drive train

*Abstract*—With the increasing adoption of electric vehicles as a sustainable solution to curb greenhouse gas emissions, the reliability and lifetime calculation of power electronic converters, particularly semiconductor components, in traction inverters, become paramount. Utilizing a mission profile based on the worldwide harmonized light-duty test cycle, this paper introduces an advanced approach to calculate semiconductor lifetime of an EV traction inverter. Employing a functional model to calculate power losses and device temperatures. An ageing model, incorporating power cycling capability data in a LESIT model, determines consumed lifetime. The feedback loop integrates the consumed lifetime into the functional model, degrading thermal properties in proportion allowing the changing system characteristics to be taken into account during calculation. This positive feedback loop accelerates ageing, highlighting the significant influence on the lifetime assessment compared to conventional implementations.

## I. INTRODUCTION

In the context of climate change, many areas of technical development are currently facing the major challenge of achieving drastic reductions in greenhouse gas emissions in various branches of industry. The road transport sector accounted for 12% of global greenhouse gas emissions in 2021 [1]. A reduction of these in said sector can therefore make a contribution to achieving global climate targets. A key step towards reducing emissions is switching from internal combustion (IC) engines to a (partially) electric powertrain in hybrid electric vehicles (HEV) and fully electric vehicles (EV).

Modern electric powertrains are used in HEVs since the introduction of the first Toyota Prius in 1997 [2]. However, the widespread use in EVs without an ad-

ditional IC engine started only in the first decade of the 21st century. Consequently, the consideration of the lifetime and ageing of traction converters in EVs is therefore not yet as advanced as it is for converters in industrial applications, for example. However, it is of great interest to understand ageing of components under vehicle requirements. With rising car numbers an incorrect determination of component lifetime in high-volume production means either excessive manufacturing costs if margins are too large, or customer dissatisfaction or even compensation payments if the product does not meet the lifetime requirements.

Overall, research in the field of lifetime prediction and ageing calculations for converters in EVs is still at an early stage compared to other industrial application areas. Current ageing and lifetime estimation models assume linear ageing without considering damage effects on the converter parameters and operation [3]. In the field of wind energy conversion systems, there are already approaches that reflect the influence of component ageing on their functionality [4].

The model presented in this paper can be split into two sub-models. The operating parameters, power losses and resulting temperatures of the converter components based on a mission profile are calculated in a functional model. In parallel, the progressive ageing of the components is calculated in an ageing model. For the investigation at hand the focus will lie on the ageing of semiconductor devices due to load cycles.

This paper proposes an approach that takes the ageing related system changes into account and therefore allows a more accurate lifetime calculation for EV traction inverters. Furthermore, it serves as a basis for further modeling of couplings with regard to component ageing in converter systems with high power-density such as those found in EVs.
<figure><img src="image_1.png" /><figcaption>Fig. 1. Schematic representation of the electric powertrain components.</figcaption></figure>

## II. SYSTEM DEFINITION

The investigated setup of this work is characterized by a small SUV-type vehicle with a system power of 200 kW and rear-wheel drive. A battery voltage of 800 V is assumed, following the trend of recently introduced vehicle generations such as those from the Hyundai Motor Group or the J1 and PPE platforms from Porsche and Audi, which use 800 V electrical systems in contrast to the previously more widespread 400 V system [5], [6].

The traction inverter consists of a two-level voltage source converter (2L-VSC) topology utilizing silicon insulated gate bipolar transistors (IGBTs) with inverse diodes as semiconductor switches. With little effort the described methods can be adapted for silicon-carbide (SiC) metal oxide field effect transistors (MOSFETs) as well. Sinusoidal-modulation is assumed with a fixed switching frequency $f_{sw}$ of 10 kHz.

Figure 1 displays a schematic representation of the electric powertrain of an EV, consisting of the HV-battery, motor and inverter with DC-link capacitor and semiconductors. Components such as interconnecting elements or EMI-filters are omitted from this analysis in order to focus on the function and ageing of the semiconductor power modules.

This paper will use the SKiM400GD126DM module from Semikron as an exemplary case study, since the relevant data sheet parameters on semiconductor properties and reliability data from power cycling tests are available online [7].

The lifetime requirements for traction inverters in EVs are defined by 8000 operating hours, 300 000 km, or 15 years of service life [8]. For better comprehensibility, the vehicle life is represented in this work by repeated sequences of the worldwide harmonized light-duty test cycle (WLTC) as depicted in fig. 2 [9]. The WLTC consists of a 30 minute driving profile during which around 23 km are covered. The cycle in turn consists of four sub-cycles that cover low-speed to high-speed

<figure><img src="image_2.png" /><figcaption>Fig. 2. Velocity plot for the WLTC Class 3 driving cycle.</figcaption></figure>

sections. Therefore, it is a realistic reflection of the vehicle's life in ordinary usage.

The modeling presented here is implemented in MATLAB. Finally, an executable file is compiled from generated code in order to optimize the computation time.

## III. FUNCTIONAL MODEL

Since the mission profile is only specified as a time-discrete speed signal, a rudimentary vehicle model is used to calculate the converter variables required to determine the semiconductor power losses. According to the WLTC specification, the temporal resolution is 1 s, however for this study a discrete time step of 100 ms is selected for all further calculations.

Following [10], the driving resistances consisting of acceleration force, aerodynamic force and rolling friction are calculated. These are used in conjunction with a permanent magnet synchronous machine (PMSM) model and the maximum torque per ampere (MTPA) strategy to calculate the converter quantities: phase-current and -voltage, DC-link voltage and phase angle. [10]

The determined values can then be used to calculate the power losses occurring in the converter. This work solely focuses on the aspect of the semiconductor modules and neglects the losses in the interconnections, such as screwed joints or welds and busbars, as well as other components such as the DC-link capacitor.

In the following, $I_{ac}$ denotes the RMS-value of the three symmetric sinusoidal phase currents $i_U$, $i_V$ and $i_W$. Where the peak-value is defined by $\hat{I}_{ac} = \sqrt{2}I_{ac}$. Likewise, $U_{ac}$ defines the RMS-value of the three phase voltages. Where $u_{UV}$, $u_{VW}$ and $u_{WU}$ are the respective line-to-line voltages.

### A. Loss Modeling

Corresponding to [11], [12] the losses of transistor and diode are calculated as mean values over the duration
<figure><img src="image_3.png" /><figcaption>Fig. 3. Time profile of the calculated power loss and resulting junction temperature for the IGBT chip over the course of a section of the WLTC.</figcaption></figure>

<figure><img src="image_4.png" /><figcaption>Fig. 4. Thermal impedance of the transistor and diode. [7]</figcaption></figure>

of one fundamental period. The calculation of instantaneous quantities in a switched model is not feasible in terms of computing time for simulated profiles with durations of several thousand hours. The conduction losses are obtained by

$$P_{l,c,T} = U_{CE0} \hat{I}_{ac} \left( \frac{1}{2\pi} + \frac{M}{8} \cos(\varphi) \right) + r_{CE} \hat{I}_{ac}^2 \left( \frac{1}{8} + \frac{M}{3\pi} \cos(\varphi) \right) \quad (1)$$

and

$$P_{l,c,D} = U_{F0} \hat{I}_{ac} \left( \frac{1}{2\pi} - \frac{M}{8} \cos(\varphi) \right) + r_{F} \hat{I}_{ac}^2 \left( \frac{1}{8} - \frac{M}{3\pi} \cos(\varphi) \right) \quad (2)$$

respectively. Where

$$M = \frac{2\sqrt{2}U_{ac}}{U_{dc}} \quad (3)$$

denotes the modulation index. The switching losses can be calculated by

$$P_{l,sw,T} = f_{sw}(E_{on} + E_{off}) \frac{\sqrt{2} I_{ac}^{k_1}}{\pi I_{ref}} \frac{U_{dc}^{k_1}}{U_{dc,ref}} \quad (4)$$

and

$$P_{l,sw,D} = f_{sw} E_{\text{rec}} \frac{\sqrt{2} I_{ac}^{k_1}}{\pi I_{\text{ref}}} \frac{U_{dc}^{k_1}}{U_{\text{dc,ref}}} \quad (5)$$

It should be noted that the semiconductor variables (i.e. $U_{CE0}$, $r_{CE}$, $U_{F0}$, $r_{F}$, $E_{on}$, $E_{off}$, $E_{rec}$) have dependencies on junction temperature, voltage or current, and must be scaled accordingly at each operating point. In

[12] it is suggested that the aforementioned parameters can be scaled to the actual junction temperature $T_j$ by the factor $(1 + k_T(T_j - T_{ref}))$ using a temperature coefficient $k_T$. The coefficient needs to be determined for each parameter by data sheet values or own measurements. Further, the switching energies are scaled to the value of $I_{ac}$ and $U_{dc}$. The corresponding exponential coefficients for the power functions have to be calculated from measurements. [12]

## B. Thermal Modeling

As described in the previous section, the semiconductor properties are temperature-dependent, which is why the specific junction temperature of each time step must be calculated. Furthermore, the temperature is also required for further analysis in the ageing model. It is assumed that the semiconductor modules are mounted on an ideal liquid cooler. The coolant temperature and flow rate are presumed to be constant. The thermal modeling is carried out using electro-thermal analogies with a thermal RC-network that reflects the thermal impedance.

The term thermal impedance is used to describe the step response of the thermal system in the time domain, consistent with its common use in semiconductor literature. Strictly speaking, impedance is a frequency-domain concept, and the time-domain equivalent would be referred to as the unit step response of the thermal system, but the term thermal impedance is retained for continuity and ease of understanding.

Utilizing the power losses of the IGBT and diode and the time-dependent thermal impedance from junction to coolant

$$Z_{\text{th,j-c}}(t) = \sum_{n=1}^{N} R_{\text{th},n} \left( 1 - \exp \left( \frac{-t}{\tau_{\text{th},n}} \right) \right), \quad (6)$$

the junction temperatures

$$T_{j,T}(t) = (P_{l,c,T}(t) + P_{l,sw,T}(t)) * \dot{Z}_{\text{thT},j-c}(t) + T_c \quad (7)$$
<figure><img src="image_5.png" /><figcaption>Fig. 5. Schematic cross-section through a power module.</figcaption></figure>

<figure><img src="image_6.png" /><figcaption>Fig. 6. Cycle capability according to Table I depicted by number of cycles to failure $N_f$ as a function of the temperature swing $\Delta T_j$ and mid temperature $T_{jm}$.</figcaption></figure>

and

$$T_{j,D}(t) = (P_{l,c,D}(t) + P_{l,sw,D}(t)) * \dot{Z}_{th,D,j-c}(t) + T_c \quad (8)$$

can be calculated for each device. For more detailed modeling, the thermal coupling between the IGBT and diode chips can also be taken into account and be represented by a so-called cross-impedance. The value of $Z_{th,j-c}(t \to \infty)$ for the thermal steady state is denoted as thermal resistance $R_{th,j-c}$.

At this point it should be noted that, from the standpoint of the functional model, it is sufficient to represent the thermal impedance in the form of a Foster network with a few links. However, it should be mentioned that a Cauer network with RC elements for the individual material layers would be necessary for the correct physical modeling of the ageing in all layers of the module.

## IV. AGEING MODEL

The ageing model is used to reflect the ageing of individual components of the power converter. In this case, the focus is on the ageing of the transistor and semiconductor module. Semiconductor power modules are a complex component in themselves, made up of many layers of different materials in order to achieve the desired functionality and properties. Figure 5 shows a schematic cross-section of a module. Each material in the structure has a specific coefficient of thermal expansion (CTE). The CTE specifies how much a material expands when the temperature changes. Consequently, a CTE mismatch occurs at the interfaces between different materials, which means that the adjacent layers expand differently for an identical temperature change. As a result, mechanical stress occurs in the contact plane. For common module designs, the CTE is in the range of $3 \cdot 10^{-6} \text{ K}^{-1}$ for silicon and $28 \cdot 10^{-6} \text{ K}^{-1}$ for solder. Repeated heating up and cooling down leads to long-term accumulating thermo-mechanical stress. As a result, cracks form, particularly in the solder layer, which continue to spread as the component ages. These cracks consequently have an effect on the properties of the module. The solder layer under the chip is used for

the electrical contacting on the one hand, but on the other hand it also represents the primary path for the heat flow to cool the chip. As a result of the reduced cross-sectional area, the thermal resistance increases, which leads to an increase in the junction temperature under equal power loss conditions. This issue leads to a self-accelerating effect that needs to be modeled by a feedback loop.

### A. Fatigue Modeling

Power cycling tests are carried out to specify the lifetime capability of semiconductor modules. The tests determine how many cycles a component can withstand when a cyclic DC current is imprinted that leads to the damaging $\Delta T_j$ swings before characteristic parameters of the component exceed certain fail criteria. These are commonly set to an increase in forward voltage by 5% or a rise of the static $R_{th}$ of 20% in comparison to the initial values [13]. As an extension to this the same $\Delta T_j$ can be applied at different cycle mid-temperatures $T_{jm}$.

The test results can then be used to parameterize cycle-dependent lifetime models for the semiconductor power module. Following the equations derived in the LESIT-project [14], the permissible number of cycles

$$N_f = A \Delta T_j^\alpha \exp \left( \frac{E_a}{k_b T_{jm}} \right) \quad (9)$$

can be calculated for any $\Delta T_j$ and $T_{jm}$ if the model was previously generated with data from at least two $\Delta T_j$ and two $T_{jm}$ tests. The parameters required in eq. (9) for the Semikron SKiM module utilized in this example can be found in Table I.

### B. Cycle Counting

To extract the stress-strain-cycles from the temperature profile calculated in the functional model, the
<table><caption>TABLE I
PARAMETERS UTILIZED IN THE LESIT-MODEL FOR SKIM4 POWER MODULES. [15]</caption><thead><tr><th>Symbol</th><th>Parameter</th><th>Value</th><th>Unit</th></tr></thead><tbody><tr><td>A</td><td>acceleration factor</td><td>648 · 10<sup>3</sup></td><td>K<sup>-α</sup></td></tr><tr><td>α</td><td>Coffin-Manson exponent</td><td>-5.039</td><td></td></tr><tr><td>E<sub>a</sub></td><td>activation energy</td><td>98.91 · 10<sup>-21</sup></td><td>J</td></tr><tr><td>k<sub>b</sub></td><td>Boltzmann constant</td><td>13.80 · 10<sup>-24</sup></td><td>J/K</td></tr></tbody></table>

widely used rainflow-algorithm [16] is applied. Here, the temperature time history is analyzed for peaks and valleys in order to identify individual cycles of different amplitudes. All the obtained cycles are then binned according to their $\Delta T_j$ and $T_{jm}$ (see fig. 7). The consumed lifetime $clt$ for one $\Delta T_{j,k}$ and $T_{jm,l}$ bin is then calculated as

$$clt(\Delta T_{j,k}, T_{jm,l}) = \frac{N(\Delta T_{j,k}, T_{jm,l})}{N_f(\Delta T_{j,k}, T_{jm,l})} \quad (10)$$

Utilizing Miners-Rule, the total lifetime consumption

$$clt = \sum_{k} \sum_{l} clt(\Delta T_{j,k}, T_{jm,l}) \quad (11)$$

can be simply expressed as the sum of the individual consumed lifetime per bin, as linear cumulative damage is assumed [17].

In the model presented here, cycle counting and binning are carried out in an online algorithm with the result that a new value for the lifetime consumption is calculated in every 100 ms time step. Various algorithms were tested that first accumulate data and then perform the two evaluation steps according to a specified criterion. In the end, however, the online implementation was chosen as it offered the fastest computing time for the overall model.

### C. Feedback Loop

At this point it should be noted that the results of the power cycling tests are used as a pair of values in the form of $N_f$ cycles to fail at a given $\Delta T_j$ swing. However, it has to be considered that power cycling tests are usually performed with a fixed load current, also in line with the guideline AQG 324 [13]. Consequently, as the thermal resistance increases during the test due to accumulating damage, the temperature rise $\Delta T_j$ also increases as a result. This already reflects system changes and exponential ageing to a certain extent in the resulting $N_f$ of the power cycling test. However, the lifetime predictions made are only correct for considerations covering the entire lifetime under the given test circumstances. In the case of calculated intermediate steps,

<figure><img src="image_7.png" /><figcaption>Fig. 7. Extracted and binned $\Delta T_j$ cycles for one WLTC. For simplification the binning into $T_{jm}$-bins is not shown here.</figcaption></figure>

there is an error, as the system change is assumed to be evenly distributed linearly over the course of the test by the Miner-Rule in conjunction with the power cycling results.

In order to correctly model a feedback loop in the following, parameters from tests performed at constant $\Delta T_j$ would be required. In [18], power cycling tests were conducted with different control strategies, including constant $\Delta T_j$ over the entire test. The achieved cycle capability increased by around 25% in comparison to the standard scheme [18]. The additional acceleration due to increasing $\Delta T_j$ in a standard power cycling test can be calculated in a simple form by utilizing the Coffin-Manson term. In [18] good agreement of measurements and the calculation method was demonstrated and a 23% higher cycle capability was calculated. The evaluation of own tests showed an increase in the range of 20% as well. Thus, to adjust the given parameter set in table I the acceleration factor $A$ for the model in the feedback loop will be increased by 25%.

As explained previously, the ageing of the solder layer particularly influences the thermal properties of the module, which were represented in the functional model. For this reason, a feedback loop is introduced in this proposed model, which provides the current value of the consumed lifetime $clt$ back to the thermal calculation in the functional model. Figure 8 shows a complete overview of the individual models and the feedback from the ageing model.

In the thermal model, the value of the thermal impedance is then adjusted to match the current damage progress. This is achieved by adjusting the thermal resistance. From a physical point of view, the link in a Cauer model that represents the thermal properties of the chip-solder connection should be adapted. However,
<figure><img src="image_8.png" /><figcaption>Fig. 8. Overview chart showing the individual models and their linkage.</figcaption></figure>

since the calculation step size of this model is 0.1 s (already considerably small for lifetime modeling), which is significantly higher than the typical time constants of chip near connections, it can be assumed that the ageing-related change in thermal impedance in the larger time constants can simply be modeled as an offset over the entire range of the thermal impedance. This can be written as

$$Z_{\text{th,j-c}}(t, \text{clt}) = Z_{\text{th,j-c,ini}}(t) + f(\text{clt})R_{\text{th,j-c}}, \quad (12)$$

where $f(clt)$ denotes a function modeling the change in thermal impedance in dependence on clt. Assuming linear cumulative damage, with the failure criterion defined in IV-A for end-of-life the increase leads to

$$Z_{\text{th,j-c}}(t, \text{clt} = 1) = Z_{\text{th,j-c,ini}}(t) + 0.2R_{\text{th,j-c}}. \quad (13)$$

The feedback of the accumulated damage results in correct modeling of the non-linear ageing process. The influence of this becomes apparent in fig. 9. At the end of the specified vehicle life of 300 000 km, the clt is actually around 8% lower compared to the conventional linear approach. 100% damage accumulation occurs about 20% earlier with the implemented feedback loop compared to linear modeling.

In this context, it should be reiterated that a higher cycle capability is assumed to adjust the power cycling test results in the ageing model. The exact result of the lifetime calculation varies depending on the applied factor and should be reviewed for a generally applicable form in further investigations.

## V. CONCLUSION

This study presents a feedback-enhanced modeling approach for analyzing the ageing of semiconductor modules in EV traction inverters. By linking functional and ageing models with a feedback loop, the model reflects system-level changes driven by ageing processes, such as thermal degradation in the power module layers. This dynamic interaction enables accurate, ageing-dependent calculations of system parameters at every operating point, thereby reflecting real-world performance more reliably.

<figure><img src="image_9.png" /><figcaption>Fig. 9. Comparison of the calculated consumed lifetime with and without feedback of ageing-related component changes.</figcaption></figure>

The inclusion of the feedback mechanism refines lifetime predictions by accounting for the nonlinear progression of damage. The results demonstrate that the feedback loop significantly impacts lifetime consumption estimates during a typical vehicle life compared to traditional models without feedback. This approach offers a realistic insight into the self-accelerating nature of thermal degradation in semiconductor devices and accurate modeling of their power losses and temperatures, which is critical for improving reliability and optimizing design margins for EV powertrains.

Future research may involve the application of this modeling strategy to other ageing mechanisms in semiconductor modules, as well as exploring the coupling effects between different components of traction inverters. Such advancements could further improve prediction accuracy and contribute to the development of more robust and efficient powertrains.

## REFERENCES

[1] A. Rivera, S. Movalia, E. Rutkowski, Y. Rangel, H. Pitt, and K. Larsen, "Global greenhouse gas emissions: 1990-2021 and preliminary 2022 estimates," Rhodium Group, 2023

[2] J. Clifford, "History of the Toyota Prius," Toyota UK Magazine, 2015

[3] C. Morel and J-Y. Morel, "Power Semiconductor Junction Temperature and Lifetime Estimations: A Review," in Energies, 17(18):4589, 2024.

[4] B. Gao, F. Yang, M. Chen, Y. Chen, W. Lai and C. Liu, "Thermal lifetime estimation method of IGBT module considering solder fatigue damage feedback loop," in Microelectronics Reliability, vol. 82, pp. 51-61, 2018.

[5] I. Aghabali, J. Bauman, P. J. Kollmeyer, Y. Wang, B. Bilgin and A. Emadi, "800-V Electric Vehicle Powertrains: Review and Analysis of Benefits, Challenges, and Future Trends," in IEEE Transactions on Transportation Electrification, vol. 7, no. 3, pp. 927-948, Sept. 2021.
[6] “Premium Platform Electric (PPE): A technological leap for the next generation of fully electric premium mobility from Audi.” Audi AG, 2024

[7] “SKiM400GD126DM,” Semikron Danfoss, https://www semikron-danfoss.com/de/produkte/produktklassen/igbt- module/detail/skim400 gd126dm-23916530.html

[8] “ZVEI: Basic qualification of DC-link capacitors for automo- tive use,” German Electrical and Electronic Manufacturers’ Association, Tech. Rep., 2020.

[9] “Addendum 153 – UN Regulation No. 154 Revision 1,” United Nations Economic Commission for Europe, 2021, https://unece.org/sites/default/files/2022-01/R154r1e.pdf

[10] M. Schlüter, M. Gentejohann and S. Dieckerhoff “Driving Cy- cle Power Loss Analysis of SiC-MOSFET and Si-IGBT Trac- tion Inverters for Electric Vehicles,” in 2023 25th European Conference on Power Electronics and Applications (EPE’23 ECCE Europe), pp. 1–11, 2023.

[11] J. W. Kolar, H. Ertl, and F. C. Zach, “Influence of the modu- lation method on the conduction and switching losses of a PWM converter system,” in Conference Record of the 1990 IEEE Industry Applications Society Annual Meeting, vol.1, pp. 502–512, October 1990.

[12] A. Wintrich, U. Nicolai, W. Tursky and T. Reimann, “Applika- tionshandbuch Leistungshalbleiter,” 2015.

[13] “ECPE Guideline AQG 324: Automotive Qualification Guide- line,” ECPE European Center for Power Electronics e. V., 2021,

[14] M. Held, P. Jacob, G. Nicoletti, P. Scacco and M.-H. Poech, “Fast power cycling test of IGBT modules in traction appli- cation,” in Proceedings of Second International Conference on Power Electronics and Drive Systems, pp. 425–430 vol.1, Singapore, 1997.

[15] M. Santoro, “Technical Explanation SKiM4 MLI & TMLI,” Rev. 1.5, Semikron, 2017.

[16] D. Socie, “Rainflow Cycle Counting: A Historical Perspec- tive,” in The Rainflow Method in Fatigue, pp. 3–10, 1992.

[17] M. A. Miner, “Cumulative Damage in Fatigue,” in J. Appl. Mech., 12(3), pp. A159–A164, Sept. 1945.

[18] G. Zeng, F. Wenisch-Kober, J. Lutz, “Study on power cycling test with different control strategies,” in Microelectronics Reliability, Vol. 88–90, pp. 756–761, Sept. 2018.