# A Real-time Condition Monitoring Technique for SiC MOSFET Gate Oxide Degradation Based on Turn-Off Delay Time Interval

Mojtaba Jazayeri, Javad Naghibi, Sadegh Mohsenzade, Kamyar Mehran

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Mojtaba Jazayeri, Javad Naghibi, Sadegh Mohsenzade, Kamyar Mehran. A Real-time Condition Monitoring Technique for SiC MOSFET Gate Oxide Degradation Based on Turn-Off Delay Time Interval. The 26th European Conference on Power Electronics and Applications, GDR SEEDS France & EPE Association, Mar 2025, Paris, France. 10.34746/epe2025-0251. hal-05087874

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# A Real-time Condition Monitoring Technique for SiC MOSFET Gate Oxide Degradation Based on Turn-Off Delay Time Interval

Mojtaba Jazayeri¹, Javad Naghibi¹, Sadegh Mohsenzade², Kamyar Mehran¹

¹Queen Mary University of London, Mile End Road, London, United Kingdom

²K. N. Toosi University of Technology, Tehran, Iran

Emails: s.jazayeri@qmul.ac.uk, s.naghibinasab@qmul.ac.uk, s.mohsenzade@kntu.ac.ir,

k.mehran@qmul.ac.uk

***Index Terms***—Condition monitoring, SiC MOSFET, Reliability, Gate oxide failure, Degradation.

***Abstract***—Gate oxide degradation can be regarded as one of the major categories of chip-related reliability issues in Silicon Carbide MOSFETs. This paper proposes an online condition monitoring technique (CMT) based on turn-off delay time as a precursor for gate oxide degradation. The method is real-time and does not need any change into the device's normal operation. The experimental results showed the proposed technique can provide a high-resolution assessment of the gate oxide degradation level of the device.

## I. INTRODUCTION

Silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) can be adopted in a wide range of power electronic applications thanks to their inherent capabilities in delivering high levels of frequency, power, and temperature during their operation [1], [2]. However obtaining reliable performance is regarded as a basic requirement that needs to be given more attention in SiC power MOSFET switches. [2]. Package-related and chip-related are considered as two main groups of long-term failure for SiC MOSFET switches [3]. Package-related failure modes are mainly a consequence of thermo-electrical stresses, which lead to solder fatigue and wire bond lift-off, and open-circuit is regarded as the ultimate outcome of the degradation process of the device [4]. Chip-related failure modes such as body diode and gate oxide degradation occur due to electrical stresses like irradiation, electrostatic discharge (ESD), and time-dependent dielectric breakdown (TDDB) [4]. The switch fails to short-circuit at the final stage of the degradation process due to chip-related degradation [5], [6]. In systems with overvoltage

possibility at device's gate-source or drain-source terminals, gate oxide degradation is a prevalent reliability risk [7]. The gate oxide failure typically derives from the tunneling current in the oxide layer. [9]. *SiC/SiO<sub>2</sub>* interface exhibits approximately twice the charged interface defect density compared to the *Si/SiO<sub>2</sub>*, as a result of carbon presence [8]. Furthermore, there is a higher leakage current value in SiC MOSFETs than Si MOSFETs, which are directly related to the reduced conduction band offset at the interface of *SiC* and *SiO<sub>2</sub>* [1]. Thus, addressing vulnerabilities in SiC MOSFET devices against gate oxide degradation is a necessity.

Several CMTs have been recommended to evaluate device gate oxide degradation. *V*<sub>th</sub> is introduced as a gate oxide degradation precursor in [13]. However, two high-frequency sensors are required to determine the *V*<sub>th</sub> value. A sensor monitors the current value of the device during the turn-on time interval to identify when the device starts conducting. Another sensor is required to assess the gate-source voltage (*V*<sub>GS</sub>) and record the value of *V*<sub>th</sub>. The Miller plateau voltage (*V*<sub>GP</sub>) over the turn-on process is recommended as a gate oxide degradation precursor in [14] and [15]. According to [15], a sensor is mandatory to measure the *V*<sub>GS</sub> value, and another sensor is required to observe the falling edge of drain-source voltage (*V*<sub>DS</sub>) during turn-on interval. In addition to two wide-band sensors, a sample and follow circuit is essential with the aim of recording the *V*<sub>GS</sub> value to measure *V*<sub>GP</sub>. Liu et al. [4] evaluated the Miller plateau time in the turning-on transient duration as a device gate oxide degradation precursor. However, a large-value external gate resistance is mandatory to lengthen this duration to obtain a satisfactory resolution. In other words, switching loss and appropriate switching operation are sacrificed for condition monitoring (CM) aims. Therefore, this CMT can not be consid-
ered an appropriate method in applications demanding high efficiency. In addition to the mentioned precursors, drain leakage current [16], gate leakage current [2], gate current during the Miller plateau time [17], ON-state resistance ($R_{DS-on}$) [18] have been introduced as indicators for monitoring gate oxide failure. Some of the precursors, typically extracted from the Si-based MOSFETs, have a different behaviour within the gate oxide degradation process of SiC MOSFETs compared to those of Si MOSFETs. Take Miller plateau time as an example; its value experiences a rebound during the degradation of the oxide layer in Si-based MOSFETs while it has an upward trend during SiC MOSFET degradation [10]. Since electrons are injected into gate oxide traps throughout the degradation process, $V_{th}$, in some cases, encounters instability during the degradation of the oxide layer in SiC MOSFETs [2], [4]. Hence, it is necessary to address specialized failure precursors to evaluate SiC MOSFET gate oxide degradation.

The majority of CM systems now in use for the device gate oxide degradation evaluation rely on several sensors. CM systems based on multiple sensors increase the complexity of the system. Furthermore, certain CM systems require high-precision digital units raising the cost of the system. Moreover, the other significant challenge is the vulnerability of these sensors against generated noise in the industrial environment.

This paper presents a practical, online, and cost-efficient CM system for evaluating the aging level of oxide layer in SiC MOSFETs, which employs the device turn-off delay time interval as the precursor. To accelerate the gate oxide degradation, high electric field stress (HEFS) test is employed. The turn-off delay duration declines during the HEFS test. The proposed CM employs a straightforward analog system to detect the turn-off duration and transform it into a DC signal. The recommended CM exhibits strong noise immunity and boosts its resistance to electromagnetic interference because of the DC output voltage. Therefore, the proposed technique can be applicable for high-frequency and high-power applications because of this feature. The achieved outcomes demonstrate that when the switch experiences gate oxide degradation, the output DC level of the recommended circuit is considerably reduced.

## II. GATE OXIDE DEGRADATION PROCESS

To obtain better $g_{fs}$ and $V_{th}$ values, the oxide layer in SiC MOSFETs is intended to be thinner than Si-based MOSFETs [19]. The $SiC/SiO_2$ structure has a significantly higher number of oxide traps, which are called Near-Interfacial Oxide Traps (NIOTs), compared

to the $SiC/SiO_2$ structure [20], [21]. These NIOTs can significantly play a part in the charge-trapping process. The degradation of the oxide layer in SiC MOSFETs derives from the direct tunneling of channel electrons into the existing NIOTs [22]. The trapped electrons in NIOTs lead to the increase of $V_{th}$ value because they tend to oppose the oxide electric field applied throughout the oxide layer, therefore, a greater electric field strength is required for the channel inversion.

### A. EFFECT OF GATE OXIDE DEGRADATION ON $V_{th}$ AND $V_{GP}$

The charge-trapping process can be carried out by NIOTs. The overall charge delivered into NIOTs ($Q_{NIOT}$) following applying a stress time ($t_{stress}$) purposes a logarithmic time dependency which is described in as (1) [10], [23].

$$Q_{NIOT}(t_{stress}) = \frac{eN}{2\beta} [\ln \frac{t_{stress}}{t_0} + \gamma] \quad (1)$$

Where $e$ is the electron charge, $N$ is the arbitrary oxide trap density, $\beta$ is the parameter of tunneling that is associated with the barrier height faced by the tunneling electrons, $t_0$ is the early tunneling transition duration and $\gamma$ is Euler's constant. The trapped charge directly affects $V_{th}$ of the device which can be written as (2) [22].

$$V_{th} = V_{th_0} + \frac{Q_{NIOT}(t_{stress})}{C_{ox}} \quad (2)$$

Where $C_{ox}$ is the oxide capacitance and $V_{th_0}$ is the initial value of the threshold voltage. Based on (1), there is a direct relationship between the stress time and $Q_{NIOT}$. Therefore, as the stress time rises, the amount of $Q_{NIOT}$ increases, which leads to the increment of $V_{th}$ value. The variation of $V_{th}$ has an appreciable effect on $V_{GP}$ and the turn-on and turn-off time intervals. The equation for $V_{GP}$ is written as (3) [4], [24].

$$V_{GP} = V_{th} + \sqrt{\frac{L_{CH}I_{D}}{\mu C_{ox}Z}} \quad (3)$$

Where $L_{CH}$, $I_D$, $\mu$, and $Z$ are the channel length, drain current, carrier mobility, and channel width, respectively. Due to $\mu$ being a decreasing function of stress time, $V_{GP}$ behaves as a rising function with respect to the stress time.

### B. VARIATION IN TURN-ON/OFF DELAY TIMES DURING GATE OXIDE DEGRADATION

For clarification of the change in the turning-on and turning-off intervals of the device throughout the gate
<figure><img src="image_2.png" /><figcaption>Fig. 1. Circuit schematic of the SiC MOSFET used for analysis</figcaption></figure>

oxide degradation process, the first step is to provide a comprehensive explanation of the device's ON/OFF switching procedure. Therefore, Fig. 1 represents the considered circuit with the intention of explaining the mentioned procedures. The gate current ($I_{Gate}$) during turning-ON and turning-OFF processes can be written as (4) [25].

$$I_{Gate} = C_{GS} \frac{dV_{GS}}{dt} + C_{GD} \frac{dV_{GS}}{dt} - C_{GD} \frac{dV_{DS}}{dt} \quad (4)$$

Fig. 2 (a) demonstrates the turn-on process of SiC MOSFETs. The time when the gate terminal of the device receives a positive voltage from the driver is regarded as the beginning of the turn-on process. Once the driver voltage is applied to the gate terminal of the device, the gate-source capacitor is extremely charged by the gate current, while the $V_{DS}$ stays steady. This time interval is defined as $t_{D-on}$, which can be written as (5) [26].

$$t_{D-on} = -R_{Gate}(C_{GS} + C_{GD}) \ln(1 - \frac{V_{GP}}{V_{CC}}) \quad (5)$$

Based on (5), the turn-on delay time is regarded as a function of $V_{GP}$ that increases. The other subintervals are not related to the focus of research; however, [3] provided the details about them.

Fig. 2 (b) illustrates the waveforms of the SiC MOSFET throughout the turn-off process. According to Fig. 2 (b), a zero voltage is applied to the gate-source terminal by the driver at the start of the turn-off process. $V_{DS}$, however, does not rise promptly at this time. The term "turn-off delay" refers to this delay that happens between the applied drive's zero voltage and the rise in

<figure><img src="image_3.png" /><figcaption>Fig. 2. The voltage and current waveforms of SiC MOSFET within (a) turn-on and (b) turn-off duration</figcaption></figure>

$V_{DS}$. During this period, the third component of equation (4) is zero, therefore, $t_{D-off}$ can be written as (6).

$$t_{D-off} = -R_{Gate}(C_{GS} + C_{GD}) \ln(\frac{V_{GP}}{V_{CC}}) \quad (6)$$

(9) indicates that $t_{D-off}$ has a reverse relation with $V_{GP}$. As a result, $t_{D-off}$ gradually decreases during the oxide layer aging process.

To validate the change of turn-off delay time in brand-new and degraded phases, a PSPICE simulation is developed. PSPICE helps to evaluate the device in the degraded stage by applying an increment in $V_{th}$ value in the device's PSPICE model (details in Table I). The variation in $V_{th}$ amount within the degradation process of SiC MOSFETs is considered based on the provided outcomes of the related research [10]. Fig. 3(a) indicates the gate-source voltage waveform of the device simulated for brand-new and fully-degraded phases. As demonstrated in 3(a), the $V_{GP}$ value is higher in the degraded phase than in the brand-new stage. The variation of $t_{D-off}$ throughout the oxide layer aging process is provided in Fig. 3(a). As indicated in Fig. 3(b), $t_{D-off}$ decreases significantly throughout the oxide layer degradation, consistent with the theoretical discussions.

<table><caption>TABLE I
CONSIDERED PARAMETERS OF SIMULATION</caption><thead><tr><th>SiC MOSFET part number</th><th>C3M0120065D</th></tr></thead><tbody><tr><td>$V_{Bus}$</td><td>300 V</td></tr><tr><td>Drain current</td><td>10 A</td></tr><tr><td>Driver voltage</td><td>17 V</td></tr><tr><td>$R_{gate}$</td><td>20 Ω</td></tr><tr><td>$V_{th}$ in brand-new stage</td><td>3.5 V</td></tr><tr><td>$V_{th}$ in degraded stage</td><td>8 V</td></tr></tbody></table>
<figure><img src="image_4.png" /><figcaption>Fig. 3. Results from PSPICE simulations: (a) $V_{GS}$ waveform characteristics; (b) turn-off delay durations across different degradation states of the device.</figcaption></figure>

### III. PROPOSED CMT

The time interval for turn-off delay is reduced during the gate oxide breakage, as discussed in part II-B. Fig. 4 indicates the proposed condition-monitoring technique in which the turn-off delay duration is captured and transformed into a DC signal. With due attention to the defined turn-off transient duration, the proposed MOSFET structure in Fig.4 is employed to extract this time interval. This structure is comprised of 2 series P-channel ($Q_1$ and $Q_2$ in Fig.4) and 2 parallel N-channel MOSFETs ($Q_3$ and $Q_4$ in Fig.4). In this structure, each of the N and P channel MOSFETs is considered a set, and a common signal is applied to the gate terminal of each MOSFET within the set. As a result, the gate terminal of each set functions as an input, while the junction of the series P-channel MOSFETs and the parallel N-channel MOSFETs serves as the output. The output will be at high level if both inputs are at low levels. To this end, sampled $V_{DS}$ through the resistive divider inclusion $R_1$ and $R_2$, called $kV_{DS}$, is applied to one input. The other input is provided by the driver's output ($V_{Pulse}$ in Fig. 4). Therefore, the output ($V_{CM}(t)$ in Fig. 4) is high (equal to $V_{DD}$) during the turn-off

<figure><img src="image_5.png" /><figcaption>Fig. 4. Circuit diagram of the suggested CMT</figcaption></figure>

period because both input signals (i.e. $kV_{DS}$ and $V_{Pulse}$) are at the low level during this time. $V_{CM}(t)$ converts into DC value via the low-pass filter (LPF in Fig. 4). A gain unit is employed in order to produce the suggested condition-monitoring output, represented as $<V_{CM}>$ in Fig. 4, which has an appropriate value. $<V_{CM}>$ can be written as (7).

$$ <V_{CM}> = k \frac{1}{T_s} \int_{0}^{T_s} V_{CM}(t) dt \quad (7) $$

Where $T_s$ is the device's switching period and $k$ is the circuit's considered gain, which can be adjusted by $R_{P1}$ and $R_{P2}$ in Fig. 4. Expression (7) can be rewritten as (8).

$$ <V_{CM}> = kV_P \frac{t_{D-off}}{T_s} \quad (8) $$

Where $V_P$ represents the constant value of $V_{CM}(t)$ during $t_{D-off}$.

The waveform schematics of CM output under the device's brand-new and degraded stages are illustrated in Fig. 5. As shown, the pulse length of the CM output is shorter in the degraded stage compared to the brand-new state. Additionally, the average value $<V_{CM}>$ is lower in the device's degraded condition. This reduction can be readily measured and used to assess the device's degradation in practical applications.

### IV. SPECIFICATION OF THE DEGRADATION SET-UP

To assess the proposed condition-monitoring technique during the degradation process of the oxide layer, an experimental set-up is needed to accelerate the aging process. To this end, the HEFS test is regarded as a common method in order to accelerate the device degradation
<figure><img src="image_6.png" /><figcaption>Fig. 5. Comparison of CM outputs between (a) brand-new and (b) degraded stages</figcaption></figure>

<figure><img src="image_7.png" /><figcaption>Fig. 6. Schematic of the HEFS circuit</figcaption></figure>

process in isolated gate bipolar transistors (IGBTs), Si, and SiC MOSFETs. In this test, a stress voltage ($V_{Stress}$) is imposed on the gate terminal; simultaneously, the drain and source terminals are connected directly (see Fig.6). Thus, the gate-oxide layer goes through expedited degradation, and the applied stress voltage to the gate-source terminal specifies the intensity of the degradation [4], [13], and [14]. For IGBTs and MOSFETs, the stress voltage value is often more than 60 V [4], [13], and [17], however, SiC MOSFETs are more vulnerable and have a reported value of 30 to 40 V [3] [12]. In this paper, 37.5 V is considered the $V_{Stress}$ value for the SiC MOSFET case study. To record all stages of degradation and their results, the period of each HEFS test is specified as 10 minutes. The device is allowed to rest until its surface temperature returns to 25 °C following each HEFS test. Then, the device operates in the defined switching condition. The DUT undergoes the HEFS test until it fails. The device breakdown can be identified by monitoring the gate-source current, as it results in a short circuit between the gate and source terminals. Therefore, the dc value of the gate current rises significantly according to [4], [13], and [14]. The

<figure><img src="image_8.png" /><figcaption>Fig. 7. Overview of experimental set-up.</figcaption></figure>

practical test details are outlined in Table II.

<table><caption>TABLE II
DETAILS OF PARAMETERS AND EMPLOYED COMPONENTS IN
THE PRACTICAL TEST</caption><thead><tr><th>Case study device part number</th><th>C3M0120065D</th></tr></thead><tbody><tr><td><i>V</i><sub>Bus</sub></td><td>200 V</td></tr><tr><td><i>I</i><sub>Load</sub></td><td>15 A</td></tr><tr><td><i>V</i><sub>CC</sub></td><td>17 V</td></tr><tr><td><i>V</i><sub>Stress</sub></td><td>37.5 V</td></tr><tr><td><i>f</i><sub>s</sub></td><td>20 kHz</td></tr><tr><td><i>R</i><sub>gate</sub></td><td>20 Ω</td></tr><tr><td>Driver IC</td><td>TC4427</td></tr><tr><td><i>R</i><sub>1</sub>/<i>R</i><sub>2</sub></td><td>1/40</td></tr><tr><td>P-channel MOSFET</td><td>SSF2219Y</td></tr><tr><td>N-channel MOSFET</td><td>SSF2220Y</td></tr><tr><td>LPF cut-off frequency</td><td>200 Hz</td></tr><tr><td>k (gain value)</td><td>100</td></tr></tbody></table>

As demonstrated in Fig.8, the device's voltage wave-forms are used to record the important parameters of the device. $V_{DS}$ and $V_{Pulse}$ are both essential for detecting $t_{D-off}$, as seen in Fig.8. $V_{GP}$ is simply visible in the $V_{GS}$ waveform during the Miller plateau.

## V. DEGRADATION RESULTS

Fig. 9 (a) and (b) demonstrate the $V_{DS}$ waveform of SiC MOSFET throughout the aging process in both the turning on and off transient duration. Using the identical
<figure><img src="image_9.png" /><figcaption>Fig. 8. $V_{DS}$, $V_{GS}$, $V_{Drive}$, and $V_{CM}$ over the degradation process</figcaption></figure>

<figure><img src="image_10.png" /><figcaption>Fig. 9. $V_{DS}$ waveform during the degradation process in (a) the turn-on and (b) the turn-off process</figcaption></figure>

<figure><img src="image_11.png" /><figcaption>Fig. 10. $V_{GS}$ waveform during the degradation process</figcaption></figure>

<figure><img src="image_12.png" /><figcaption>Fig. 11. Comparison of the turn-off time in brand-new and degraded stages</figcaption></figure>

driver input signal, the $V_{DS}$ waveform exhibits a shorter pulse length at the latter phases of gate oxide degradation, as seen in Fig. 9. As stated in Section II-B, this is caused by a rise in turn-on delay duration and a fall in turn-off delay duration. Fig. 10 represents the waveforms of $V_{GS}$ during the aging process of the oxide layer. As it is obvious in Fig. 10, the $V_{GP}$ increases gradually over the oxide layer aging process. Fig. 11 demonstrates $V_{DS}$ and $V_{Drive}$ to accurately compare the difference in turn-off delay time interval between a brand-new and a degraded SiC MOSFET. According to the results shown in Fig. 11, $t_{D-off}$ decreases significantly in the last stage of the degradation. Moreover, The change of $t_{D-off}$ in terms of stress time is provided in Fig. 12. As shown

in Fig. 12, the $t_{D-off}$ value in the degraded state is approximately equivalent to half of its initial amount.

The SiC MOSFET's $V_{CM}(t)$ waveforms during gate oxide degradation are demonstrated in Fig. 13. According to Fig. 13, the pulse length of CM output experiences a significant reduction in the ultimate phases of the degradation process. The suggested CMT output which is the amplified average of $V_{CM}(t)$, is demonstrated in Fig. 14. The output of CMT declines significantly in the last phases of gate oxide degradation, as predicted. Given the mV range of the CM output pulse average, a gain of 100 is used. As shown in Fig. 4, buffer gain blocks can be used to generate this voltage gain. The resolution (O.R.)
<figure><img src="image_13.png" /><figcaption>Fig. 12. Variation in $t_{D-off}$ during the gate oxide degradation</figcaption></figure>

<figure><img src="image_14.png" /><figcaption>Fig. 13. $V_{CM}(t)$ within the gate oxide degradation process</figcaption></figure>

achieved by the introduced CM system is described as (9).

$$O.R. = \frac{\langle V_{CM} \rangle_{BN} - \langle V_{CM} \rangle_{D}}{\langle V_{CM} \rangle_{BN}} \quad (9)$$

Where $\langle V_{CM} \rangle_{BN}$ is the output of CM in the brand-new state and $\langle V_{CM} \rangle_{D}$ is the CM output in the degraded stage, respectively. The recommended CMT achieves a resolution of roughly fifty percent, as can be observed in Fig.14. This resolution is acceptable to assess how the device is doing in terms of gate oxide degradation while it is operating.

<figure><img src="image_15.png" /><figcaption>Fig. 14. $\langle V_{CM}(t) \rangle$ in the brand-new and degraded stages</figcaption></figure>

The impact of key operational parameters such as $I_D$, $V_{DS}$ in the off-state, and device temperature has been analyzed to provide valuable insights for designers, emphasizing the importance of understanding these parameters to ensure accurate and effective CM. An inverse relationship between the average CM voltage output and the $I_D$ has been observed. This relationship arises from the increase in the $V_{GP}$ as the drain current rises, leading to a reduction in the turn-off delay time interval. Therefore, higher drain currents result in a lower due to the shortened turn-off delay duration. Furthermore, with regard to the $V_{DS}$ in the off-state, experimental results, including those conducted in [12], indicate an approximate independence of $\langle V_{CM} \rangle$ from variations in $V_{DS}$. This suggests that the influence of off-state $V_{DS}$ on the degradation indicator is minimal, enhancing the robustness of the proposed CMT under varying voltage conditions. Similarly, device temperature also plays a role in influencing the turn-off delay time. Previous studies have validated that the turn-off delay is directly related to the operating temperature of the device [12], [27]. However, the temperature dependency of $\langle V_{CM} \rangle$ has been demonstrated to be negligible compared to the pronounced reduction observed during gate oxide degradation, as supported by experimental findings in [12].

## VI. CONCLUSION

This paper presents an approach for evaluating the reliability of SiC MOSFET devices by focusing on the reduction in turn-off delay time as a key indicator of gate oxide degradation. An online CM system for SiC MOSFET gate oxide degradation is suggested based on the proposed precursor. To this end, an analog circuit is developed to measure the turn-off delay time interval, providing a DC output signal for straightforward measurement and analysis. Experimental results reveal a significant 50 percent reduction in the CM circuit's output during the gate oxide degradation process, demonstrating a satisfactory resolution for monitoring the degradation level during the device operation.

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