# Hardware/Software Co-design of Power Level Difference Based Noise Cancellation

Van Phu Ha, Minh Nguyen, Quang Hieu Dang

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Van Phu Ha, Minh Nguyen, Quang Hieu Dang. Hardware/Software Co-design of Power Level Difference Based Noise Cancellation. International Conference on Advanced Technologies for Communications (ATC), 2015, Ho Chi Minh City, Vietnam. hal-04194191

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Distributed under a Creative Commons CC BY 4.0 - Attribution - International License
# Hardware/Software Co-design of Power Level Difference Based Noise Cancellation

Van Phu Ha, Duc Minh Nguyen and Quang Hieu Dang

Hanoi University of Science and Technology

Email: minh.nguyenduc1@hust.edu.vn

**Abstract**—In this paper, the Power Level Difference (PLD)-based noise cancelling algorithm is implemented in a Xilinx FPGA SoC using hardware/software co-design methodology. Thanks to the hardware/software co-design, the complex control part of the algorithm can be fast deployed in software meanwhile the computational part is effectively implemented in hardware. Therefore, the system can not only process the real-time input data but also consumes few hardware resource.

**Keywords**—Hardware/Software Co-Design, Verilog, FPGA.

## I. INTRODUCTION

Noise cancelling is one of important steps in speech processing and voice communication systems because input speech of these systems is always recorded with the inevitable and ubiquitous noise. In order to obtain clean speech signal from its corrupted observation, noise cancelling techniques that reduce unwanted background noise while limiting the signal distortion are essential. Noise cancelling techniques can be applied in cellular phones, speech recognition, teleconferencing, etc.

Normally, proposed noise cancelling techniques exploit the sparseness of the speech signal in time and frequency domains. In the past, the proposed techniques can only process the signal source recorded from one microphone. However, the performance of single microphone algorithms is somehow limited especially in the case of fast changing background noise. Recently, several works [1]–[5] focus on processing signal recorded by microphone arrays with arbitrary geometry. That improves the performance of the reduction algorithms.

The Power Level Difference (PLD) algorithm using dual microphone for noise reduction was first introduced in [6], which exploits the difference in power level of speech signal arriving at the two microphone (about 10 dB) and the same level of noise. The proposed method inserts a scaling factor into a Wiener filter to further reduce noise at the expense of severe speech signal distortion. The PLD algorithm is modified in [7], where a PLD-based noise estimator is proposed for three cases with a constant updating parameter.

Besides noise cancelling implementations using single microphone in recent years [8], [9], there are various implemented algorithms using two microphones to reject speech noise. In [10], authors propose an implementation of Active Sound-Noise Cancellation System based on a dual-microphone method to be used in a cockpit intercommunication system. The system uses an adaptive FIR filter and LMS algorithm and is designed on Hardware/Software Co-design environment. In 2009, Wolfgang Fohl et.al. have published design studies of

the implementation of an adaptive noise cancellation system on an FPGA board. The system consists of a Spartan -3 FPGA XC3S400 board connected with a Philips Stereo-AudioCodec UCB 1400, [11].

In this paper, we concentrate on the implementation of Power Level Difference (PLD) algorithm [7]. By comparing the performance requirement of components in the improved algorithm, the implemented system is partitioned into hardware and software to obtain high performance and save hardware resources. Finally, noise cancelling system is placed in some noisy environments to assess the algorithm quality through specific targets. A prototype was validated on FPGA development boards (Xilinx XC6SLX45).

The rest of the paper is organized as follows. Section II briefly describes the Power Level Difference algorithm. After that, noise cancelling system architecture is given particularly in Section III. The test procedure and measurement results are presented in Section V. Finally, Section VI concludes the paper.

## II. NOISE CANCELLING ALGORITHM

The Power Level Difference (PLD)-based noise cancelling algorithm [12] using two microphones can be illustrated by Figure1. The algorithm takes two signals from two microphones ($x_1(t)$ and $x_2(t)$) and uses an adaptive Wiener filter to remove the noise from the speech. The input signals are digitized by an Analog-Digital Converter and then partitioned into frames and are converted into frequency domain using short-time Fourier transform. The signals in frequency domain $X_1(l, k)$, $X_2(l, k)$ are then processed frame by frame. The PLD algorithm updates and tracks the changes in speech and noise signal of present frame from previous frames to estimate the coefficient of Wiener filter $G(l, k)$ [7]. Then, noise is suppressed by the filter with the coefficient $G(l, k)$. The output of the algorithm is the reduced noise speech signal and is converted into analog form, $\hat{x}(t)$. The coefficient of Wiener filter $G(l, k)$ is calculated as the function of the $\Delta\Phi_X$, $\Phi_N$, $H_{12}$, and $\gamma$ as follows [7].

$$G(l, k) = \frac{\Delta\Phi_X(l, k)}{\Delta\Phi_X(l, k) + \gamma(l, k) \cdot (1 - |H_{12}(l, k)|^2) \cdot \Phi_N(l, k)} \quad (1)$$

Where

* $\Delta\Phi_X = \Phi_{X_1} - \Phi_{X_2}$, where $\Phi_{X_1}$ and $\Phi_{X_2}$ which are power spectral density (PSD) of $X_1(l, k)$ and $X_2(l, k)$, respectively
* $\Phi_N(l, k)$ is PSD of noise signal.

* $H_{12}(l, k)$ is the transfer function representing the channel.

* $\gamma(l, k)$ is a factor calculated through coherence function $\Gamma(l, k)$

The coherence function $\Gamma(l, k)$ is calculated based on $\Phi_{X_1}$, $\Phi_{X_2}$ and $\Phi_{X_{12}}$ which is the cross power spectral density between $X_1$ and $X_2$ as follow:

$$ \Gamma(l, k) = \frac{\Phi_{X_{12}}(l, k)}{\sqrt{\Phi_{X_1}(l, k) \cdot \Phi_{X_2}(l, k)}} \quad (2) $$

The PSD of noise $\Phi_N(l, k)$ is estimated based on the Power Level Difference Noise Estimator $\Delta\phi_{PLDNE}(l, k)$ as follows [7].

Firstly, the PLDNE is calculated as the difference between the PSDs of two input signals.

$$ \Delta\phi_{PLDNE}(l, k) = \left| \frac{\Phi_{X_1}(l, k) - \Phi_{X_2}}{\Phi_{X_1}(l, k) + \Phi_{X_2}} \right| \quad (3) $$

Next, the noise PSD is estimated in three different ranges of the PLDNE.

(i) Case 1: In case of background noise-only periods, $\Delta\phi_{PLDNE}(l, k)$ is close to zeros as the input power levels almost equal

$$ \begin{gathered} \Phi_N(l, k) = \alpha_N \cdot \Phi_N(l - 1, k) + (1 - \alpha_N) \cdot |X_1(l, k)|^2, \\ \text{if } \Delta\Phi_{PLDNE}(l, k) < \phi_{min} \end{gathered} \quad (4) $$

(ii) Case 2: Regarding the noise-free case, the value of $\Delta\phi_{PLDNE}(l, k)$ will be close to one

$$ \begin{gathered} \Phi_N(l, k) = \Phi_N(l - 1, k), \\ \text{if } \Delta\Phi_{PLDNE}(k, l) > \phi_{max} \end{gathered} \quad (5) $$

(iii) Case 3: In between these two thresholds

$$ \begin{gathered} \Phi_N(l, k) = \alpha_N \cdot \Phi_N(l - 1, k) + (1 - \alpha_N) \cdot |X_2(l, k)|^2, \\ \text{if } \phi_{min} < \Delta\Phi_{PLDNE}(k, l) < \phi_{max} \end{gathered} \quad (6) $$

The channel transfer function $H_{12}(l, k)$ is derived as described in [13].

$$ \gamma(l, k) = \begin{cases} \sqrt{1 - D_{min}} & \Gamma(l, k) \ge D_{min} \\ \sqrt{1 - \Gamma(l, k)} & D_{min} < \Gamma(l, k) < D_{max} \\ \sqrt{1 - D_{max}} & \Gamma(l, k) \le D_{max} \end{cases} \quad (7) $$

where $D_{min}$ and $D_{max}$ is set 0.2 and 0.8, respectively.

$$ H_{12}(l, k) = \left| \frac{\Phi_{X_{12}} - \gamma(l, k) \cdot \Phi_N(l, k)}{\Phi_{X_1}(l, k) - \Phi_N(l, k)} \right| \quad (8) $$

$\Phi_{X_1}(l, k)$, $\Phi_{X_2}(l, k)$, and $\Phi_{X_{12}}(l, k)$ are calculated by a recursive equation from previous frame.

$$ \Phi_{X_1}(l, k) = \alpha_X \cdot \Phi_{X_1}(l - 1, k) + (1 - \alpha_X) \cdot |X_1(l, k)|^2 \quad (9) $$

<figure><img src="image_2.png" /><figcaption>Fig. 1: Block diagram of noise reduction algorithm</figcaption></figure>

$$ \begin{aligned} \Phi_{X_2}(l, k) &= \alpha_X \cdot \Phi_{X_2}(l - 1, k) + (1 - \alpha_X) \cdot |X_2(l, k)|^2 && (10) \\ \Phi_{X_{12}}(l, k) &= \alpha_X \cdot \Phi_{X_{12}}(l - 1, k) + (1 - \alpha_X) \cdot X_1(l, k) \cdot X_2^*(l, k) && (11) \end{aligned} $$

### III. SYSTEM ARCHITECTURE

In this section, we design the system architecture from the PLD algorithm described in Section II. The algorithm is implemented by the datapath shown in Figure 1. The analog signals from two microphones $x_1(t)$, $x_2(t)$ are digitized by an audio CODEC at sample rate 8KHz to obtain digital signal $x_1(m)$, $x_2(m)$ respectively.

Next, digital signals $x_1(m)$, $x_2(m)$ are refined by the Hanning window, then partitioned into 50% overlapped frames $x'_1(l, n)$, $x'_2(l, n)$ where n is sample index, and l is frame index. These signals are then converted into frequency domain $X_1(l, k)$ and $X_2(l, k)$ using N-point FFT. Next, Power Spectrum Density Functions $\Phi_{X_1}(l, k)$, $\Phi_{X_2}(l, k)$, $\Phi_{X_{12}}(l, k)$ are calculated recursively. Using the PSD functions, the PSD of noise signal $\Phi_N(l, k)$, the channel transfer function $H_{12}(l, k)$ and the coherence factor $\gamma(l, k)$ are calculated. These values are used to determine the Wiener filter coefficients $G(l, k)$ which are used to remove noise from the input signal $X_1(l, k)$. The filtered signal $\hat{X}(l, k)$ is then transferred to time domain by IFFT block. Finally, the overlap-add block is used to rearrange the output signal by combining the head of present frame and the tail of previous frame before converting into analog form.

In order to implement the algorithm, first the FFT size should be determined, and then the system blocks are partitioned into hardware and software parts that are implemented using Hardware Description Language and C program language, respectively.

<table><caption>TABLE I: Algorithm performance for different FFT sizes (noise F-16, SNR = 5dB) All measures are in dB</caption><thead><tr><th></th><th>FFT64</th><th>FFT128</th><th>FFT256</th><th>FFT512</th></tr></thead><tbody><tr><td>Output SINR</td><td>31.3642</td><td>34.4014</td><td>35.2736</td><td>37.26</td></tr><tr><td>Noise reduction factor</td><td>23.0788</td><td>25.7841</td><td>26.6565</td><td>27.17</td></tr><tr><td>Signal distortion index</td><td>-12.9108</td><td>-14.27</td><td>-15.1209</td><td>-13.14</td></tr></tbody></table>

#### A. FFT size

In paper [7], the author proposed to use 512-point FFT to transfer the 50% overlapped signal frames into frequency domain. The authors have shown that it resulted in satisfactory
<table><caption>TABLE II: Algorithm execution time (perfomanced by Xilinx Microblaze processor 100MHz)</caption><thead><tr><td>Task</td><td>execution time (ms)</td><td>percentage</td></tr></thead><tbody><tr><td>Hanning window and FFT</td><td>38.9230</td><td>47.67</td></tr><tr><td>Calculation of noise PSD, coherence function, etc.</td><td>5</td><td>6.12</td></tr><tr><td>IFFT and overlap-add</td><td>37.7295</td><td>46.21</td></tr></tbody></table>

simulated quality. In order to satisfy real-time requirement and balance between algorithm performance and implementation ability, we assess again the PLD algorithm to estimate optimal FFT size for implementation. Four algorithms based on 64-point, 128-point, 256-point, and 512-point FFT are compared with regards to 3 parameters: output SINR, noise reduction factor, and signal distortion index. Table I shows simulation results of 4 algorithms. Values of parameters of FFT128 and FFT256 do differ slightly. Besides, results when using FFT512 is better in two first parameters but worse in signal distortion and FFT64 is worse in three parameters. Thus, 128-point FFT is chosen. As consequence, signal frames consists of 128 data samples which are 50% overlapped. It means that 128 sample frames input to the algorithm datapath every 64 samples.

## B. Hardware-Software Partition

As the algorithm is implemented on hardware/software SoC, the separation of hardware and software plays a significant role in efficiency of the system. In order to partition the algorithm into hardware and software reasonably, we start with all functionality implemented in software and move functional blocks into hardware. The moved block are time-critical and can not be allocated to software.

First, the algorithm is implemented using C language and is executed in Xilinx Microblaze processor. The execution time is shown in Table II. As we can realized, the FFT, IFFT, Hanning window, overlap-add blocks require most computational time occupied 93.88% of the CPU. Meanwhile, the control of ADC/DAC converters, the calculation of noise PSD, coherence function, transfer function and coefficients only needs 6.12% CPU time. Besides, the control and calculation tasks use I/O interface and complex equations such as multiplier, division, square root of complex numbers that can be easily implemented on software. Consequently, the FFT, IFFT, Hanning window, overlap-add blocks are partitioned into hardware of the system. Meanwhile, the control and calculation tasks are performed using software. As results, the system architecture is shown in Figure 2. The system consists of a Microblaze processor executing the software part, an AC97 CODEC controlling the ADC/DAC blocks, and USER LOGIC implementing the FFT, IFFT, Hanning window, overlap-add blocks. The software running on the processor control the overall behavior of the system as well as the data movement among blocks as follows.

Step 1 CPU reads sampled signals $x_1(m), x_2(m)$ from the AC97 Audio CODEC every 125us (arrows 1a and 1b in Figure 2) until it gets 64 samples.

Step 2 CPU writes 64 samples from microphone 1 and 2 to Hanning Window 1 and 2, respectively. The Hanning Window 1, 2 refine the input signal and writes the refined signals $x'_1, x'_2$ to the FIFO C1A/B, C2A/B

respectively. The FIFO C1A/B store 50% overlapped 128 sample frames from microphone 1 where FIFO C1A stores 64 samples ealier than FIFO C1B. It means that FIFO C1A/B stores samples $x'_1(l, 0:127)$ (arrow 2a) and $x'_1(l, 64:191)$ (arrow 2b), respectively. Similarly, the data frames from the microphone 2 is stored in FIFO C2A/B (arrows 2c/d).

Step 3 When the FIFOs are full, the FFT calculation is started to convert frames stored in FIFOs into frequency domain. First, frames $x'_1(l, 0:127)$ is converted into frequency domain $X_1(l, 0:127)$ (arrow 3a). Next, frames $x'_2(l, 0:127)$ is converted into $X_2(l, 0:127)$ (arrow 3c). Note that, $x'_1(l, 64:191), x'_2(l, 64:191)$ in FIFO C1B, C2B are converted 64 samples afterward (arrows 3b, 3d). The signal in frequency domain $X_1(l, 0:127), X_2(l, 0:127)$ are stored in FIFO FFT_C1 and FFT_C2, respectively. The real and imaginary values of the signal $X_1(l, 0:127)$ are stored in FFT_C1RE, and FFT_C1IM, respectively.

Step 4 CPU reads $X_1(l, 0:127), X_2(l, 0:127)$ from FIFO FFT_C1RE, FFT_C1IM, FFT_C2RE, FFT_C2IM (arrows 4a, 4b, 4c, 4d).

Step 5 CPU performs calculation of noise PSD, the coherence function, the transfer functions, the Wiener coefficients and the cancelling filter. The result data is noise-reduced signal frames in frequency domain $\hat{X}(l, 0:127)$ which is outputed into FIFO NC_RE/IM (arrows 6a, 6b).

Step 6 When FIFO NC is full, the IFFT starts and performs the FFT calculation to convert the data back to time domain. The result frames $\hat{x}(l, 0:127)$ are consecutively stored in FIFO IFFT, ODD and IFFT_EVEN when $l$ is odd and even, respectively (arrows 7a and 7b).

Step 7 The overlap-add block takes 64 samples from each IFFT_ODD and IFFT_EVEN to construct the final result signal frames and writes into FIFO FINISH (arrow 8).

Step 8 CPU reads the data from FINISH sample by sample every 125us and writes it to the AC97 which converts signal into analog form (arrows 9, 10).

Figure 3 illustrates the concurrent and sequential behavior of the system components. The input and output of data samples are concurrently performed by the CPU every 125us (step 1, 10). For the frame $l$, the CPU writes 64 input data samples to the FFT hardware in the period of the sample $x(l, 63)$ and $x(l, 127)$. After that, the FFT block converts two input data frames into frequency domain in the same period of the sample $x(l, 63)$ and $x(l, 127)$. Then, the CPU perform the noise cancelling algorithm for the input data samples in frequency domain during the period from sample $x(l, 65)$ to sample $x(l, 125)$. It then writes output of the noise cancelling algorithm (in frequency domain) to the IFFT at the period of the sample $x(l, 126)$. After the IFFT hardware finishes the calculation, the CPU read the results in time domain in the period of sample $x(l + 1, 0)$ of the next frame $l + 1$. The noise-removed data samples of the input frame $l$ are sent to the CODEC in the period of the frame $l + 1$. From the
<figure><img src="image_3.png" /><figcaption>Fig. 2: Hardware/Software System architecture</figcaption></figure>

timing diagram shown in Figure 3, several timing constraints
are derived as follows:

* The execution time of the Hanning window and the two FFT blocks should fit in one sample period, i.e., 125us.

* The execution time of the noise cancelling algorithm in frequency domain by the CPU should not be longer than 61 samples, i.e., 7.625ms.

* The execution time of the IFFT block and the *overlap_add* block should fit in one sample period, i.e., 125us.

## IV. SYSTEM IMPLEMENTATION

In this section, the system is implemented based on Xilinx
FPGA and the Microblaze processor. First, we describe the
hardware implementation of the FFT/IFFT block. Then, soft-
ware implementation is shown. We also analyze the latency
of the implemented blocks to validate the above mentioned
timing constraints.

### A. FFT/IFFT implementation

In this paper, a 128-point FFT design is based on the archi-
tecture proposed in [14] which uses a single-delay-feedback
[15] and pipeline architecture simultaneously. The 128-point
FFT architecture uses mix-radix with 7 stages in which radix-
2 is used for stage 7 and radix-2² is used for stage 1 to stage
6. The design takes data input sample by sample and produces
the output after 307 clock cycles. It means that the latency of

FFT/IFFT conversions is 307 cycles. Consequently, the above
mentioned timing constraints can easily be fulfilled.

### B. Software implementation

The software part is implemented based on interrupt and
polling mechanism: (i) the I/O communication between CPU
and AC97 CODEC is interrupt based and (ii) the data transfers
between CPU and FFT/IFFT is polling and FIFO based.

The AC97 CODEC controller generates interrupt signal at
the data sample rate (8 Khz). The interrupt is handled by
an interrupt routine executed by the CPU that collects input
data samples from the CODEC as well as outputs the result
samples to the CODEC. The interrupt routine also updates the
controlling variables that are polled by the main routine to start
the noise cancelling algorithm in software. The code portions
of the interrupt routine is given in Listing 1.

<caption>Listing 1: Audio CODEC interrupt routine</caption>

```c
void AC97Handler() // freq 8khz
{
    static Xuint32 cnt=0;
    int p;
    static int LDATA[64];
    static int RDATA[64];
    cnt++; // increase sample index
    if (cnt>=64) cnt = 0;

    // Read samples from codec
    // and store in static software buffer
    LDATA[cnt-1] = XIo_In32(AC97LeftAddr);
    RDATA[cnt-1] = XIo_In32(AC97RightAddr);
    // Write noise-removed samples to codec
    XIo_Out32(AC97RightAddr, PDATA[cnt]);
    // set controling variables for main routines
    if (cnt==0)
        start_cancelling=1;
    if (cnt==62)
        finish_overlap=1;
    if (cnt==63){
        // send half frames to Hanning windows
        for (p=0;p<64;p++){
            XIo_Out32(Hanning1Addr, LDATA[p]);
            XIo_Out32(Hanning2Addr, RDATA[p]);
        }
    }
}
```

The interrupt routine keeps track of the sample index by a
variable cnt. Whenever, it gets one input samples and writes
out one resulted sample from/to the AC97 CODEC, the cnt
variable is increased by one. When a half of a data frame is
completely collected, i.e., cnt = 63, the data is sent to the
Hanning Window blocks. At the beginning of the next half of
data frames, i.e., cnt = 0 the flag variable start_cancelling is
set to 1 such that the main routine can start to perform the noise
cancelling algorithm. Here, note that, the Hanning Window
and FFT blocks need to finish their calculation within the
time between two samples. That can be fulfilled because the
timing distance between two samples is 125us corresponding
to 12500 clock cycles (the system runs at 100MHz clock).
<figure><img src="image_4.png" /><figcaption>Fig. 3: Timing of system</figcaption></figure>

At the sample 62 of the half of frames, the noise cancelling algorithm should be finished, the flag variable *finish_overlap* is set to 1 such that the main routine can get the noise-reduced samples from the FIFO and output them to the CODEC. The main routine is shown in Listing 2 which polls the variables *start_cancelling* and *finish_overlap* in an endless loop to start the noise cancelling algorithm and get back the results.

<caption>Listing 2: Main routine</caption>

```c
void main()
{
    int v1[128], v2[128], v3[128], v4[128], v5[64];
    float Xesto[2]; // out
    int k=0; // var for ALG
    while (1)
    {
```

```c
        if (start_cancelling) {
            start_cancelling = 0;
            // get data from FFT result fifos
            for (k=0; k<128; k++) {
                v1[k] = XIo_In32(FFT_C1RE);
                v2[k] = XIo_In32(FFT_C1IM);
                v3[k] = XIo_In32(FFT_C2RE);
                v4[k] = XIo_In32(FFT_C2IM);
            }
```

```c
        // cancelling algorithm
        NoiseCancel(v1, v2, v3, v4, Xesto);
        // output to IFFT
        for (k=0; k<128; k++) {
            XIo_Out32(FFTAddr, Xesto[k]);
        }
        else if (finish_overlap) {
            // get results
            finish_overlap = 0;
            for (k=0; k<64; k++) {
                PDATA[k] = XIo_In32(FINISHFIFOAddr);
```

# V. EXPERIMENTAL RESULTS

## A. Performance and resource utilization

The proposed system design was synthesized using the Xilinx ISE Design Suite tool (version 14.7); target device is Spartan6 XC6SLX45-3csg324. Table III presents the resource usage as well as the maximum frequency speed of the system implementation. Our proposed system is also compared with 50 inputs XOR circuit as design parameter normalization.
<table><caption>TABLE III: Hardware Synthesis Result</caption><thead><tr><th></th><th>Our system</th><th>50 XORs</th><th>Ratio</th></tr></thead><tbody><tr><td>max frequency (MHz)</td><td>191.9</td><td>129.9</td><td>1.48</td></tr><tr><td>Number of Slice Registers</td><td>11712</td><td>0</td><td>-</td></tr><tr><td>Number of Slice LUTs</td><td>11357</td><td>11</td><td>1032.45</td></tr><tr><td>Number of LUT Flip Flop pairs</td><td>9424</td><td>11</td><td>856.73</td></tr></tbody></table>

<table><caption>TABLE IV: Performance of the system (All measures are in dB)</caption><thead><tr><th rowspan="2">Filter</th><th colspan="3">PLD algorithm</th></tr><tr><th>F-16</th><th>Babble</th><th>White</th></tr></thead><tbody><tr><td>Interference noise</td><td></td><td></td><td></td></tr><tr><td>Output SINR</td><td>11.36</td><td>11.47</td><td>13.04</td></tr><tr><td>Noise reduction factor</td><td>14.91</td><td>12.79</td><td>16.03</td></tr><tr><td>Signal distortion index</td><td>-12.60</td><td>-11.11</td><td>-13.12</td></tr></tbody></table>

## B. System Validation

To validate the system, we generate the input signals from two channel noise-free speech signals and three noise sources. The two channel speech signals include six the utterances, three from female speakers and three from male speakers. Meanwhile, the noise are taken from Noise database [16] which are white Gaussian noise (WGN), F-16 cockpit noise and babble noise. For each speech signal, we create two instances of interfering noise F-16 and babble for two channels.

This implemented system is validated in two scenarios: interfering signals F-16 and babble, in addition to the white Gaussian noise. We choose SIR = 5dB and SNR = 10dB, hence, the overall input SINR is 3.8dB. The performance of the algorithm in term of output SINR, noise reduction factor and signal distortion index are given in the Table IV. Figure 4 illustrates the noise-free speech signal, the input signal (noisy signal) and the output signal (processed signal) of the system.

## VI. CONCLUSION

The PLD algorithm is successfully implemented based on Hardware/Software Co-Design approach to achieve satisfy real-time requirement and save hardware resources by considering design size, speed performance, design time and the flexibility for future system improvement. As a result, the

<figure><img src="image_5.png" /><figcaption>Fig. 4: (a) Noise-free speech signal, (b) Noisy signal, (c) Output of PLD algorithm on Hardware/Software system</figcaption></figure>

FFT, IFFT, Hanning window, overlap-add blocks are implemented into hardware of the system, while estimating noise PSD, coherence function, transfer function and coefficients is performed in software to increase the flexibility. In order to evaluate hardware resources and measure performance of system, proposed system is implemented in FPGA development board (Xilinx XC6SLX45) and then placed in some noisy environments which are white Gaussian noise (WGN), F-16 cockpit noise and babble noise to assess the algorithm quality through specific targets.

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