# Integration of diamond in fully-depleted silicon-on-insulator technology as buried insulator: A theoretical analysis

Jean-Paul Mazellier, Olivier Faynot, Sorin Cristoloveanu, Simon Deleonibus, Philippe Bergonzo

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## ► To cite this version:

Jean-Paul Mazellier, Olivier Faynot, Sorin Cristoloveanu, Simon Deleonibus, Philippe Bergonzo. Integration of diamond in fully-depleted silicon-on-insulator technology as buried insulator: A theoretical analysis. Diamond and Related Materials, 2008, 17 (7-10), pp.1248-1251. 10.1016/j.diamond.2008.03.026. cea-05469204v2

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https://cea.hal.science/cea-05469204v2

Submitted on 12 Feb 2026

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# Integration of diamond in fully-depleted silicon-on-insulator technology as buried insulator: A theoretical analysis

Jean-Paul Mazellier<sup>a,b, □</sup>, Olivier Faynot<sup>a</sup>, Sorin Cristoloveanu<sup>b</sup>, Simon Deleonibus<sup>a</sup>, Philippe Bergonzo<sup>c</sup>

a CEA-LETI, CEA-Grenoble 17 rue des Martyrs 38054 Grenoble, France

b IMEP-INP Grenoble MINATEC, 3 Parvis Louis Néel BP 257 38016 Grenoble, France

c CEA-LIST, CEA-Saclay, 91191 Gif sur Yvette, France

Keywords: Diamond properties and applications, Silicon-on-insulator (SOI), Thermal properties, Electrical properties

## ABSTRACT

We examine here by electro-thermal simulation tools (SILVACO's Atlas) a configuration of Silicon-OnInsulator substrate for Fully-Depleted MOSFET architectures, incorporating diamond as buried insulator, and compare it with traditional silicon dioxide BOX for the future technological nodes of the ITRS (90 nm and below). Our aim is to give major trends to be followed in order to optimize diamond integration from electrical and thermal points of view, constraints that must be kept in mind in parallel with the technological work on thin diamond films. In this theoretical study, we perform a benchmarking between SiO2 and diamond BOX. We first point out that the BOX thickness should not be more than few hundred nanometers to maintain electrical performances. From thermal point of view, we demonstrate that the replacement of 100 nm thick buried oxide by a 100 nm thick diamond layer can lead to about 50% reduction of the temperature when only 33% decrease can be obtained with Ultra Thin SiO2 BOX (20 nm). Furthermore, thick diamond BOX avoids the parasitic capacitances issue that reduces Ultra Thin BOX devices working frequency.

## 1. Introduction

As electronic devices dimensions shrink to fulfill the ITRS [1] requirements, new phenomena, which until now were of second order, are now to be considered. The first are the Short Channel Effects (SCE) which are exacerbated with channel length reduction. Devices based on Silicon-On-Insulator (SOI) technology (cf. Fig. 1), especially Fully Depleted SOI (FDSOI) devices [2], are a suitable solution to overcome this issue. But SOI configuration, by modifying the transistor thermal environment, gives rise to a new limiting issue: self-heating [2]. The generated heat makes the temperature increase, and as a consequence the electrical current decreases (carriers mobility decreases in silicon with increasing temperature above 300 K [3]). The conventional buried insulator SiO2, due to its poor thermal conductivity (1.4 W m⁻¹ K⁻¹ [4] compared to 148 W m⁻¹ K⁻¹ for bulk silicon [4] at 300 K), is a barrier to heat evacuation from the device to the substrate. Two main concepts have been proposed to solve this problem: thinning the BOX [5] or replacing the BOX material [5,6]. We study here the implications of replacing SiO2 by diamond from both electrical and thermal points of view.

## 2. Why a buried insulator? On the usefulness of diamond for SOI technology

Conventional buried insulator used for SOI is SiO2. This insulator layer is referred to as BOX (for Buried Oxide). Introducing BOX underneath the active silicon layer, called body (cf. Fig. 1), allows insulating this active region from the underlying substrate. In such a way, parasitic effects like latchup or substrate hot carrier degradation are reduced [2].

From a thermal point of view, the heat generated by the current flowing in the device has to be evacuated. Two main paths are available for the heat flow Φ (cf. Fig. 1): metal interconnections (ΦI) and substrate (Φs). Heat evacuation by interconnections is not desired because it can induce degradation (electromigration, ...). But the presence of the buried layer influences this flow distribution. SiO2 is a poor thermal conductor, so the heat flow to the substrate is reduced, leading to increased temperature of the

device compared to bulk transistors. This temperature increase results in degraded performances [7].

From the electrostatic point of view, we only want the gate to control the electrical state of the body. Introducing a BOX and limiting the active silicon film thickness in FDSOI allows, by limiting both the body depletion and junctions depth, to give higher control of the gate on the channel than in bulk configuration. But now, reaching deep submicron dimensions of channel, source and drain have a non negligible part in the channel control, due to lateral field: this leads to the so-called Short Channel Effects (SCE). But the control of the gate is also dependent on the vertical electric field generated in the body. This field can be divided into two components: the first is due to the coupling of the gate and the substrate, the second is the two dimensional coupling of source (resp. drain) to the body via the BOX. This second part is parasitic. It is known as the fringing field effect

(corresponding to C<sub>S-B</sub> and C<sub>D-B</sub> in Fig. 1) [8]. This effect is exacerbated by BOX thickness and dielectric permittivity. However, we can note

<figure><img src="image_3.png" /><figcaption>Fig. 1. Representation of electrical couplings and heat flow paths in a SOI transistor. See text for symbols meaning.</figcaption></figure>

<figure><img src="image_4.png" /><figcaption>Fig. 2. Dielectric permittivity versus thermal conductivity of eligible BOX materials.</figcaption></figure>
that the presence of the BOX, by spacing source (resp. drain) from substrate, decreases the associated parasitic capacitance C<sub>S-Sub</sub> (resp. C<sub>D-Sub</sub>) represented in Fig. 1. This allows SOI based transistors to have enhanced working frequency compared to bulk transistors.

As a result, the perfect BOX has to fulfill the following requirements:

i) high film to substrate capacitance to ensure good electrical control of the gate

ii) low source (drain) to substrate capacitance

iii) low dielectric permittivity to reduce fringing fields

iv) high thermal conductivity to ensure good heat evacuation to substrate

On Fig. 2, we have reported materials eligible as BOX considering their technological management. As point i) is incompatible with points ii) and iii), a tradeoff between these specifications has to be done, considering the application. To synthesize, the BOX material must have the highest thermal conductivity combined with the lowest dielectric permittivity. As a result, diamond is a perfect candidate under two main assumptions: firstly it must offer sufficiently high thermal conductivity in thin film configuration with no dramatic increase of the boundary thermal resistance with silicon compared to SiO2. Secondly, diamond integration must be compatible with a standard CMOS technology process. Note that this second point has been already validated because diamond has already been integrated as BOX in previous works [9–11]. From these works, we know that Silicon-On-Diamond (SOD) structure can be obtained with the following process: diamond is grown the silicon film of an initial SOI substrate. Then diamond is bonded to a mechanical substrate. Finally, the substrate and BOX of the initial SOI are left off. We will assume such SOD structure in the following.

### 3. Electrostatic impact of diamond: the capacitance tradeoff

We have studied diamond influence from pure electrical point of view, particularly the diamond thickness range suitable for low power applications.

First, in order to get convenient results, we have to take care about defects states present at the silicon-diamond interface. These defects have a huge importance for the device behavior, especially during commutation phases. We consider SOD substrate with diamond directly grown on silicon film. Previous work have shown significant defects density at silicon-diamond interface [12], but recent results [13] show that for diamond, grown by MPCVD on silicon, the silicon-diamond interface has similar electrical quality compared to silicon-SiO2 interface. As a consequence, the diamond-silicon interface is always considered defect free in our simulations. We can also note the lack of information about carrier mobility in silicon film on diamond. We consider here that the diamond does not impact this parameter and we use standard CVT model for transport equations [14].

One important parameter to monitor the SCE is the Drain Induced Barrier Lowering (DIBL). DIBL is defined as the threshold voltage shift between low and high polarization of the drain (typically 0.05 V and 1 V). Minimum DIBL is required from performance point of view.

Evolution of this parameter as a function of BOX equivalent thickness is reported on Fig. 3. Equivalent thickness of diamond is defined as the thickness of SiO2 giving the same 1D capacitance C<sub>1D</sub> =ε/t (ε dielectric permittivity of the material, t its thickness). Equivalent thickness of material A t<sub>A</sub><sup>eq</sup>, with physical thickness t<sub>A</sub> and permittivity ε<sub>A</sub>, is given by t<sub>A</sub><sup>eq</sup> =t<sub>A</sub>×ε<sub>SiO2</sub> / ε<sub>A</sub>.

As can be seen on Fig. 3, DIBL saturates to high values with BOXs thicker than 1 µm. Below this value, diminishing BOX thickness allows reduced SCE. This is due to fringing field reduction and stronger electrical vertical field in the body.

$$C_{BD}(x) = C_{BOX} \times [\exp(-\pi \times x/t_{BOX}) - 1]^{-1} \quad (1)$$

From the expression of Body to Drain capacitance C<sub>B-D</sub>, given by [8]:

where x is the distance to drain junction (negative) and C<sub>BOX</sub> the 1D capacitance value of the BOX.

From Eq. (1), we can deduce that fringing fields effect is reduced by BOX thinning. That is what is observed on Fig. 3: both SiO2 and diamond thin BOX (few tens of nanometers) devices have the same DIBL because the 1D coupling is dominating. On the contrary, for

<figure><img src="image_5.png" /><figcaption>Fig. 3. DIBL of 20 nm and 45 nm transistor channel lengths as a function of oxide equivalent BOX thickness. C<sup>*</sup> stands for diamond.</figcaption></figure>

<figure><img src="image_6.png" /><figcaption>Fig. 4. Drain temperature elevation ΔT<sub>Drain</sub> as a function of BOX thickness. For SiO2 BOX: full symbols correspond to a constant thermal conductivity of 1.4 W m<sup>-1</sup> K<sup>-1</sup>, open symbol corresponds to thermal conductivity of 0.8 W m<sup>-1</sup> K<sup>-1</sup>. For diamond (C<sup>*</sup>): full symbols correspond to fitted experimental values of thermal conductivity in inset, open symbol corresponds to constant thermal conductivity of 23 W m<sup>-1</sup> K<sup>-1</sup>. Inset: Experimental thermal conductivities as a function of diamond thickness (straight stands for linear fit).</figcaption></figure>
thicker diamond-BOX, devices exhibit higher DIBL due to exacerbated SCE, resulting from higher fringing fields due to the value of diamond dielectric permittivity (5.5 compared to 3.9 for SiO2).

Nevertheless, one has to remind that thin BOX increases parasitic capacitances (C<sub>D-Sub</sub> and C<sub>S-Sub</sub> on Fig. 1): 20 nm thin BOX devices have been proved to have reduced work frequency by 20% compared to 145 nm thick BOX [15], mainly due to the parasitic capacitance increase. We can conclude that a diamond BOX of 100 nm is a good tradeoff between speed and SCE. We now investigate the efficiency of diamond to evacuate the heat from the device.

4. Thermal management of diamond

Diamond is attractive because of its high thermal conductivity. Here we study how this property can help us to achieve heat
evacuation to the substrate. As mentioned before, we consider the diamond layer to be grown on the silicon film. This implies that we
consider polycrystalline diamond layer of NCD or UNCD type, with grains of typical size ranging from few nanometers to few tens of
nanometers. Numerous thermal conductivities are reported for diamond depending on process, morphology (randomly distributed,
columnar, ...), grain size, film thickness, .... For layer of submicron thickness, range of interest for our application, we have computed
thermal conductivity from [16–20] versus film thickness. Result is presented in inset of Fig. 4. This dependence is taken into account in our
simulations in order to compare with SiO2-BOX. Note that the reported thermal conductivities are out of plane from the layer (normal to
the surface of growth) and integrate the thermal boundary resistance with silicon into account. But to the extent of our knowledge no
works have been performed on thermal conductivity in the plane of such thin layers, so we have considered isotropic thermal conductivity
in the diamond layer, assuming randomly distributed grains. Furthermore, as the silicon–diamond interface acts as a thermal resistor (as
for silicon–SiO2 case) and grains in diamond have lower size than bulk diamond phonon mean free path (~300 nm [21] at 300 K) for thin
films, we expect the transport to be diffusive and so no phonon reflection (grain boundary, impurity, ...) effect is taken into account.

We have considered a single transistor with one metal level and realistic structure in order to compare the impact of BOX material replacement. Each transistor dissipates 1 mW by micron width. Substrate is maintained at 300 K 50 µm far from the device. Lateral boundaries are set at 25 µm from the device and they are adiabatic. Top surface is maintained at 300 K, 500 nm above the device and a lumped thermal resistance connects the device to this surface: the thermal resistance corresponds to 500 nm of oxide (thickness of the passivation layer) except at contact location where thermal resistance corresponds to 500 nm thick tungsten material. Contacts are reported 400 nm laterally in order to be in accordance with our standard device architecture. Note that in integrated circuits, contacts are only few nanometers away from the gate. If we consider such design, we overestimate the dissipation factor of the metal lines because here we have only one metal level with metal lines typically 100 µm long. For this configuration we have a large fin effect that is not characteristic from real integrated device with up to 10 metal levels, each embedded in SiO2 matrix and thus with little or no fin action. Here we do not suffer such effect and the thermal weight of the BOX in the total thermal resistance is considered to be relevant of an integrated circuit configuration. The drain junction is the heat main source because of high electric field. Its temperature is taken as the probe for the device. Results are reported on Fig. 4.

For SiO2-BOX, the drain temperature decreases as BOX thickness is decreased. This is a pure geometrical result. We will take the 100 nm SiO2- BOX as reference for comparison: device temperature is increased by 148 K in this case. We can however notice that thermal conductivity is reported to be reduced with thicknesses lower than few tens of nanometers [22] and can reach value as low as 0.8 W m⁻¹ K⁻¹. The temperature for 20 nm SiO2-BOX with thermal conductivity of 0.8 W m⁻¹K⁻¹ is the same as temperature for 32 nm SiO2-BOX with thermal conductivity of 1.4Wm⁻¹K⁻¹ . We can remark that both sets have the same 1D thermal resistance: in this range of thermal conductivity, BOX behaves as 1D heat resistor.

For diamond-BOX, a different behavior of temperature variation can be observed. Drain junction temperature is increased by BOX thinning. This is due to the thermal conductivity decrease that masks the diamond thickness shrinking. From a pure thermal point of view, the thicker the diamond layer, the lower the temperature of the device. But as we have seen, from electrical point of view, which still remains the first criteria for technology development, diamond layers on the order of 100 nm have to be considered for FDSOI transistors. Nevertheless, comparing 100 nm thick SiO2 and diamond-BOX, diamond leads to 52% decrease in ΔTDrain (with thermal conductivity of 8 W m⁻¹ K⁻¹) compared with the 33% decrease that can be performed with 20 nm thick SiO2-BOX. If we assume a thermal conductivity of 23 W m⁻¹ K⁻¹ for diamond, 100 nm thick diamond-BOX leads up to 66% gain in temperature variation. Note that simulated results for diamond BOX thinner than 100 nm are purely informative because literature presents in general this thickness as the typical minimum thickness to get continuous diamond films on silicon substrate. Furthermore, boundary resistance would largely dominate the whole thermal conduction for such thicknesses, point that is not taken into account here.

5. Conclusion

We have demonstrated here that diamond-BOX is a serious candidate for FDSOI technology as it can, at the same time, fulfill the electrical role of a buried insulator and allows heat to be efficiently evacuated from the device to the substrate. Electrical performances impose the use of diamond thickness on the order of 100 nm: equivalent performances, in term of SCE management, can be obtained compared with as thick SiO2-BOX. From thermal point of view, diamond exhibit notable improvement in heat evacuation leading to more than 50% limitation of temperature variation in 100 nm thick configuration compared with as thick SiO2-BOX and is even better than 20 nm SiO2-BOX. Such thickness range is challenging today in terms of large surface deposition and uniformity control but is needed for FDSOI technology. Optimization of thermal conductivity and thermal boundary resistance are also important points that are to be addressed.

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