# Voltage generation for Sawyer-Tower Coss loss measurement based on resonant converters

Paul Korn, Marcus Praast, Thomas Komma

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Paul Korn, Marcus Praast, Thomas Komma. Voltage generation for Sawyer-Tower Coss loss measurement based on resonant converters. The 26th European Conference on Power Electronics and Applications, GDR SEEDS France & EPE Association, Mar 2025, Paris, France. 10.34746/epe2025-0299. hal-05080171

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# Voltage generation for Sawyer-Tower Coss loss measurement based on resonant converters

Paul Korn, Marcus Praast, Thomas Komma

FTZ LEIPZIG E.V., AT LEIPZIG UNIVERSITY OF APPLIED SCIENCES

Karl-Liebknecht-Str. 132
04277 Leipzig, Germany

Tel.: +49 / (0) - 341 3076 1101

paul.korn@stud.htwk-leipzig.de

http://www.ftz-leipzig.de

## Acknowledgment

This article is funded by the German Federal Ministry for Economic Affairs and Climate Action within the program elektro-mobil as a part of the project noLIMIT.

## Keywords

«Device characterization», «Super junction devices», «MOSFET», «Power losses», «Resonant converter».

## Abstract

Output capacitance losses in modern semiconductor devices become increasingly relevant with fast switching power converters. A new voltage generation approach is proposed to handle the highly variable capacitive load in a Sawyer-Tower circuit. An LLC resonant converter is applied to generate the high voltage, high frequency sinusoidal excitation voltage, overcoming limitations of HF amplifiers. An external DC voltage source is introduced to prevent reverse conduction of the device under test, ensuring accurate charge-voltage (Q-V) characterization. Measurements under this voltage excitation are presented. The calculated dissipated energy is verified by thermal measurements observing the temperature rise of the DUT, showing less than 6% deviation. This article presents a scalable and practical setup for power semiconductor characterization at high voltages.

## Introduction

Newer generations of superjunction and wide bandgap transistors enable higher switching frequencies, contributing to the goal of increased efficiency. Reduced switching losses allow for

smaller cooling systems and more compact converter designs. Losses due to hysteresis in the output capacitance of modern semiconductor devices ($C_{oss}$-losses) have been observed even under Zero-Voltage switching (ZVS) conditions [1]. These additional frequency dependent losses can become a predominant loss mechanism in power transistors [1], [2]. Such unexpected losses can affect the performance of cooling systems designed for only small dissipated power.

Previous research has shown that $C_{oss}$-losses occur in various types of superjunction MOS-FETs [3], as well as wide-bandgap transistors based on gallium nitride (GaN) [4], [5] and silicon carbide (SiC) [6] technologies. However, the severity of these losses varies significantly between transistors, depending on their internal structures [3], [7]. It is currently not possible to evaluate $C_{oss}$-loss characteristics from the small-signal output capacitance values provided in data sheets. The measurement and reporting of these losses is not yet standardized, despite several existing recommendations [3], [8]. It is up to designers of power electronic circuits to evaluate and select suitable devices for the intended application. Since the required data is not readily available, own measurements based on design parameters are necessary.

Several measurement methods for $C_{oss}$-losses have been proposed [4], [6], [5], [8]. One widely used method is the Sawyer-Tower (ST) circuit, originally developed to characterize the dielectric properties of crystalline materials [9]. When applied to power semiconductors, this method requires operation at higher voltages and frequencies. Accurate measurements demand careful selection of components and equipment [10], [11]. However, the use of linear HF-amplifiers [3], [8] is constrained by their drive capabilities,
as evaluated in [10].

To address these limitations, this paper proposes a novel approach for generating the voltage excitation in the measurement circuit by utilizing the sinusoidal voltage present in the resonant tank of an LLC resonant converter. An external bias voltage source $V_{\text{offset}}$ is introduced to prevent reverse conduction of the device under test (DUT). Measurements of the ST circuit under this excitation voltage are presented and the measured $C_{\text{oss}}$-losses are compared with thermal measurements of the DUT in the measurement circuit.

## Measurement Method

### Electrical Measurement of Hysteresis Losses

The ST circuit consists of the DUT with its output capacitance connected in series with a known reference capacitor $C_{\text{ref}}$. The voltage-dependent output capacitance $C_o(v_{\text{DS}})$ and the reference capacitance $C_{\text{ref}}$ form a capacitive voltage divider. Since the DUT and the reference capacitor are in series, the same current flows through both components. An AC voltage source drives this circuit, as shown in Fig. 1(a). There is a short-circuit connection between the Gate and the Source of the DUT to keep the transistor permanently turned off.

<figure><img src="image_2.png" /><figcaption>Fig. 1: (a) Basic circuit arrangement for Sawyer-Tower measurements of MOSFETs consisting of the DUT and the reference capacitor $C_{\text{ref}}$. (b) The measurement circuit implemented in this paper. A high frequency AC voltage $v_{\text{ac}}$ is superimposed by a DC Voltage source $V_{\text{offset}}$ to adjust the voltage bias across $C_{\text{ref}}$ and the DUT.</figcaption></figure>

The voltages $v_{\text{DS}}(t)$ across the DUT and $v_{\text{ref}}(t)$ across $C_{\text{ref}}$ are measured to determine the DUT's capacitance behavior. Calculations are based on the assumption of equal charge change $dQ$ in both capacitances. The relation between $C_o(v_{\text{DS}})$ and the voltages is described in (1).

$$C_o(v_{\text{DS}}) = \frac{dQ_o(v_{\text{DS}})}{dv_{\text{DS}}} = C_{\text{ref}} \cdot \frac{dv_{\text{ref}}}{dv_{\text{DS}}} \quad (1)$$

The energy difference due to hysteresis $E_{\text{diss}}$ is determined according to (2) as the area enclosed between the paths in the Q-V curve over one full charge- and discharge cycle.

$$E_{\text{diss}} = \oint v_{\text{DS}}(Q_o) \cdot dQ_o \quad (2)$$

To obtain the dissipated power $P_{\text{diss}}$, the calculated energy $E_{\text{diss}}$ is multiplied by the excitation frequency $f_e$ as stated in (3).

$$P_{\text{diss}} = E_{\text{diss}} \cdot f_e \quad (3)$$

## Offset Voltage Adjustment

A negative voltage ($v_{\text{DS}} < 0$) across the DUT can lead to reverse conduction, potentially introducing errors in the charge curve calculations and subsequently in $E_{\text{diss}}$ and $P_{\text{diss}}$ [10]. To mitigate this issue, a DC voltage $V_{\text{offset}}$ is applied in series with the driving voltage $v_{\text{ac}}$. This configuration is shown in Fig. 1(b). It allows fine adjustment of the low point of $v_{\text{DS}}$, ensuring that it remains above zero ($v_{\text{DS}} > 0$) and preventing excessive reverse conduction. There is no active power contribution to the circuit by $V_{\text{offset}}$, therefore only a low current, high voltage power supply with an output voltage in the range of the desired $V_{\text{DS-max}}$ is required.

## LLC Resonant Converter for Excitation Voltage

A signal generator combined with a high voltage amplifier is often used to generate the high excitation voltage required for the ST circuit [10], [3], [8]. Such amplifiers are able to precisely reproduce the input signal with an amplification gain, but feature a significant output resistance and the maximum current that can be driven into a load is limited [10]. High voltage amplifiers capable of driving a ST circuit to the rate voltage of the are typically large and expensive. To overcome these limitations, a new method of providing an excitation voltage to an ST circuit is presented.

Figure 2 shows a simplified schematic of the LLC resonant converter topology used in this work. It consists of a switching bridge, the resonant tank formed by the elements $L_r$, $C_r$ and $L_m$ as well as a load represented by the resistor
$R_{Load}$. The output voltage of the switching bridge is a square wave that excites the resonant tank, resulting in a filtered resonant current $i_r$.

<figure><img src="image_3.png" /><figcaption>Fig. 2: Basic topology of the resonant converter used to generate the high frequency sinusoidal excitation voltage for the Sawyer-Tower measurements.</figcaption></figure>

For the resonant converter operating near its resonant frequency $f_r = 1/(2\pi\sqrt{C_r \cdot L_r})$, the current waveform of $i_r$ is nearly sinusoidal. The voltage $v_{ac}$ across the resonant capacitor $C_r$ is $v_{C_r} = v_{ac} = 1/C_r \int i_r(t)dt$.

For a sinusoidal current $i_r$, the voltage $v_{ac}$ will also be sinusoidal with a phase shift of 90° relative to $i_r$. This phase shift does not affect the operation of the ST circuit.

$v_{ac}$ can easily reach amplitudes of several hundred volts even at relatively low input voltages, depending on the design of the converter. The converter applied in this work provides an amplitude of 450 V with an input voltage to the switching bridge of only 70 V. It is capable of providing amplitudes of up to 800 V.

The resonant current $i_r$ is much larger than the current through the ST circuit and can drive highly variable capacitive loads as seen in the ST. Especially superjunction MOSFETs can show a large variation of their output capacitance over more than two orders of magnitude. Unlike high frequency amplifiers, the resonant converter has negligible internal resistance, ensuring that the voltage $v_{ac}$ remains undistorted, even under low impedance capacitive loads when $v_{DS}$ is low.

Near the resonant frequency $f_r$, the current $i_r$ is sinusoidal. Therefore $f_e$ can be varied to a certain extent. However, if large variations in the excitation frequency for the ST circuit are desired, e.g. changing $f_e$ from 100 kHz to 500 kHz, a reconfiguration of the resonant tank is required to ensure a sinusoidal voltage shape.

## Thermal Verification of Losses

In order to verify the power losses determined by the ST method, a thermal measurement

is carried out. For this, the approach from [12], [13] is used. The theory of this thermal method is based on (4), which shows that the rise rate, which is constant at the beginning of the temperature rise curve, is directly proportional to the thermal capacity $C_{th}$ and the power loss $P_{loss}$.

$$ \frac{\Delta T}{\Delta t} = \frac{P_{loss}}{C_{th}} \qquad (4) $$

To determine an unknown power loss $P_{loss}$, a reference measurement with a known power loss in the DUT is first conducted. For the reference the temperature rise rate $\Delta T/\Delta t_{ref}$ and the power loss $P_{ref}$ are recorded. After that the unknown power loss $P_{loss}$ must be induced, and the temperature rise rate $\Delta T/\Delta t_{loss}$ must be measured. According to (5) and (6) the power losses also depend on their $C_{th}$.

$$ P_{ref} = C_{th} \cdot \frac{\Delta T}{\Delta t_{ref}} \qquad (5) $$

$$ P_{loss} = C_{th} \cdot \frac{\Delta T}{\Delta t_{loss}} \qquad (6) $$

In both the reference measurement and the loss measurement with the unknown power loss $P_{loss}$, this paper ensures the same initial temperature and determines the rise rate within the same temperature range $\Delta T$. This approach guarantees that the thermal capacity $C_{th}$ of the DUT can be treated as a constant in both cases [13]. This allows (5) and (6) to be set in relation to each other and $C_{th}$ can be removed from the equation. With that, the unknown power losses $P_{loss}$ of the DUT can be easily calculated with (7).

$$ \frac{P_{loss}}{P_{ref}} = \frac{\frac{\Delta T}{\Delta t_{loss}}}{\frac{\Delta T}{\Delta t_{ref}}} \qquad (7) $$

By measuring the temperature rise with an infrared (IR) camera at the case of the MOS-FET, power losses in the milliwatt range can be recorded [13].

## Circuit setup

The complete circuit setup combining the resonant converter, the filtered offset voltage and the measurement circuit with the DUT and $C_{ref}$ is depicted in Fig. 3.

For the measurements presented in this paper the resonant converter is operated at a fixed excitation frequency $f_e = 105$ kHz, slightly above its resonance frequency $f_r$.
<figure><img src="image_4.png" /><figcaption>Fig. 3: Complete equivalent circuit diagram with LLC and filter</figcaption></figure>

In a given converter and resonant tank the magnitude of the flowing resonant current $i_r$ is affected by the load and the input voltage of the switching bridge. The load is set in a way that the switching bridge of the converter is operating in ZVS and soft switching is achieved at the desired $v_{ac}$. If the converter is hard switching, overshoots and resonances of the commutations are visible as unwanted noise and distortion in the measurements of the connected ST circuit.

The current $i_r$ and therefore the voltage $v_{ac}$ can then be finely adjusted by varying the input voltage to the switching bridge. Experiments have shown that the operation of the converter is not affected by the connection of the ST circuit as long as the resonant current $i_r$ is larger than the current $i_{ST}$ through the ST. The converter used for the measurements in this paper is shown in Fig. 4.

<figure><img src="image_5.png" /><figcaption>Fig. 4: Resonant converter and Sawyer-Tower circuit with DUT in a thermal chamber</figcaption></figure>

$V_{offset}$ is a DC voltage, and the high frequency current through the DUT and $C_{ref}$ needs to pass

through this source. A two stage RC filter is applied to filter $V_{offset}$ to prevent AC ripple current from affecting the power supply. The effective decoupling capacitance used to filter $V_{offset}$ is much larger than the capacitances of $C_{ref}$ and $C_{oss}$.

$C_{ref}$ is a Class I C0G type ceramic capacitor (TDK CGA5L4C0G2J103J160AA) with a nominal capacitance of 10 nF. It is selected for its high voltage rating of 630 V and its linear behavior with no influence of DC bias to the capacitance. The capacitance is constant up to around 5 MHz, which is much higher than the frequency for the intended measurements of 105 kHz. The capacitance of the used $C_{ref}$ was measured with an RLC-Meter to a value of 10.129 nF at 100 kHz.

Figure 5 shows the measurement setup used to quantify the power losses of the DUT.

<figure><img src="image_6.png" /><figcaption>Fig. 5: Measurement setup for Sawyer-Tower measurements with resonant converter and IR camera</figcaption></figure>

The voltages $v_{DS}(t)$ and $v_{ref}(t)$ are measured using two isolated channels of a Rohde&Schwarz RTH1004 oscilloscope, while the temperature rise is recorded using an InfraTec ImageIR 8300 thermal camera. For the thermal reference measurements, the dissipated power $P_{ref}$ in the DUT is measured with a Yokogawa WT5000 power analyzer. The resonant converter, the DUT and $C_{ref}$ are placed inside the measurement chamber, while the measurement equipment, power sources and control circuits are positioned externally to minimize interference with the thermal measurements.
Measurements and Results

The DUT used for the measurements pre-
sented in this paper is a STB33N60M2 from
STMicroelectronics. It is an N-Channel MOS-
FET in superjunction technology with 600 V
Drain-Source breakdown voltage and an R<sub>DS(on)</sub>
of 108 mΩ in a TO-263 package [14]. The DUT
is excited to a voltage of V<sub>DS max</sub> = 440 V. The
measured voltage waveforms are shown in Fig. 6.

<figure><img src="image_7.png" /><figcaption>Fig. 6: Measured voltage waveforms in Sawyer-Tower circuit. V<sub>offset</sub> = 444 V, f<sub>e</sub> = 105 kHz, C<sub>ref</sub> = 10.129 nF</figcaption></figure>

The enlarged view in Fig. 6 shows that re-
verse conduction of the DUT is prevented, since
the voltage v<sub>DS</sub> always remains in the positive
region. The low point of v<sub>DS</sub> is finely adjustable
by setting the voltage V<sub>offset</sub>. For the measure-
ment shown in Fig. 6 it is set to V<sub>offset</sub> = 444 V
to avoid a negative v<sub>DS</sub> entirely.

C<sub>o</sub>(v<sub>DS</sub>) and Q<sub>o</sub>(v<sub>DS</sub>) are calculated from the
measurements using equation (1). The resulting
curves are shown in Fig. 7 and Fig. 8.

A different path between charging and dis-
charging is visible in the C<sub>o</sub>(v<sub>DS</sub>) plot in Fig. 7.
A small signal output capacitance curve extracted
from the manufacturer's data sheet [14] is shown
as a black dotted line. As v<sub>DS</sub> across the DUT
increases during the charging phase, a steady
decrease of its capacitance can be observed.
Between 20 and 230 V the capacitance decreases
less than indicated in the data sheet. At high v<sub>DS</sub>

<figure><img src="image_8.png" /><figcaption>Fig. 7: Resulting C<sub>o</sub>(v<sub>DS</sub>) curve for the DUT.
Small signal values from data sheet indicated as
dotted black line</figcaption></figure>

the capacitance change is close to the slope of
the data sheet curve.

As the voltage across the DUT decreases
during discharge, a different path is formed.
Above 200 V the capacitance initially remains
very close to the charging curve. The capacitance
change in this region follows the indicated curve
from the data sheet. Below 70 V an increasingly
steep climb in capacitance is started, leading to
an almost immediate rise, where the capacitance
changes by almost an order of magnitude be-
tween 40 and 30 V.

The Q<sub>o</sub>(v<sub>DS</sub>) plot in Fig. 8 also shows the
two different paths for charge and discharge.
The area within the curve is a measure of the
energy dissipated in one full charge-discharge
cycle. Equation (2) is applied to calculate the
hysteresis energy to E<sub>diss</sub> = 2.38 µJ. At the
excitation frequency f<sub>e</sub> = 105 kHz this energy
results in a dissipated power of P<sub>diss</sub> = 250 mW
using (3).

<figure><img src="image_9.png" /><figcaption>Fig. 8: Extracted Q<sub>o</sub>(v<sub>DS</sub>) curve of the DUT.
Hysteresis is visible as the area encircled be-
tween the different paths for charging and dis-
charging of the output capacitance.</figcaption></figure>
To verify the power losses of the DUT, temperature heating curves were recorded at the same time as the voltages in Fig. 6. The measured temperature curves of the DUT in loss and reference measurements are shown Fig. 9. The temperature range used for evaluation is identical for both measurements and visible as an enlarged view.

<figure><img src="image_10.png" /><figcaption>Fig. 9: Temperature rise at the case of the DUT measured with IR camera for reference power $P_{\text{ref}}$ and dissipated Power $P_{\text{loss}}$ during ST measurement. The zoomed-in view shows the temperature range of the curve with constant temperature rise rate $\Delta T/\Delta t$ evaluated for the calculations.</figcaption></figure>

The dissipated power determined by the thermal measurements can be calculated with the captured temperature rise rates shown in Fig. 9 and the reference power dissipation $P_{\text{ref}}$. Equation (7) results in $P_{\text{loss}} = 264$ mW.

The resulting power dissipation of the DUT determined using the ST method and the thermal method are both shown in Fig. 10.

The resulting power losses both match very closely. The calculated power dissipation from the ST method differs from the thermal method by less than 15 mW or below 6%. With the applied voltage formed by $v_{\text{ac}}$ and $V_{\text{offset}}$ it is possible to accurately determine the power losses due to output capacitance hysteresis in the DUT.

<figure><img src="image_11.png" /><figcaption>Fig. 10: Comparison of the Power losses $P_{\text{diss}}$ calculated from electrical ST measurements and the thermally radiated Power $P_{\text{loss}}$ calculated from temperature rise monitoring</figcaption></figure>

## Conclusion

Losses due to output capacitance hysteresis have been measured both electrically and thermally. The proposed voltage generation by a resonant converter has been successfully applied to characterize the large signal output capacitance and charge profile of a superjunction MOSFET. It shows excellent drive capabilities for the highly variable capacitive loads of a Sawyer-Tower circuit even with a high value $C_{\text{ref}}$. The driving method is easy to apply and adapt to the desired parameters, however large variations in the excitation frequency require a reconfiguration of the resonant tank components. Measurements were conducted at high voltages of $v_{\text{DS}}$ in the range of typical applications. Output capacitance hysteresis losses were observed, calculated from the measurements and successfully verified by thermal measurements. The application of the offset voltage $V_{\text{offset}}$ has proven to be a usable measure to prevent the reverse conduction of the DUT.

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