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# Leveraging gem5 and Machine Learning for End-to-End Detection of Cache-based Side-Channel Attack Patterns

Muhammad Awais, Maria Mushtaq, Lirida Naviner, Florent Bruguier, Pascal

Benoit, Jawad Haj-Yahya

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## To cite this version:

Muhammad Awais, Maria Mushtaq, Lirida Naviner, Florent Bruguier, Pascal Benoit, et al. Leveraging gem5 and Machine Learning for End-to-End Detection of Cache-based Side-Channel Attack Patterns. PROOFS 2025 - 13th International Workshop on Security Proofs for Embedded Systems, Sep 2025, Kuala Lumpur, Malaysia. hal-05372979

HAL Id: hal-05372979

https://hal.science/hal-05372979v1

Submitted on 3 Dec 2025

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Distributed under a Creative Commons Attribution 4.0 International License
# Leveraging gem5 and Machine Learning for
End-to-End Detection of Cache-based
Side-Channel Attack Patterns

Muhammad Awais¹, Maria Mushtaq¹, Lirida Naviner¹, Florent Bruguier²,
Pascal Benoit², and Jawad Haj-Yahya³

¹ Telecom Paris, 19 Pl. Marguerite Perey, Palaiseau, France

² LIRMM (University of Montpellier - CNRS), 161 Rue Ada, Montpellier, France

³ Rivos Inc, 3315 Scott Boulevard, Santa Clara, CA, USA
{muhammad.awais}@telecom-paris.fr

**Abstract.** Side-channel attacks (SCAs) exploit physical leakage vectors, including cache states, timing variations, and power consumption in hardware microarchitectures to compromise computational security. This paper introduces an end-to-end, simulation-driven framework that integrates gem5's cycle-accurate architectural models with unsupervised machine learning to automate SCA detection. We simulate Spectre (V1/V2), Prime+Probe, and Flush+Reload attack pattern workloads to generate fine-grained execution traces encompassing BTB access sequences, memory latency distributions, and pipeline stall events. Temporal feature engineering extracts discriminative signatures through branch predictor entropy calculations and miss sequence autocorrelation, while dimensionality reduction via t-SNE optimizes the feature space. These preprocessed traces train an ensemble of Isolation Forest, Variational Autoencoders, and HDBSCAN models to identify attack patterns without predefined templates. Experimental validation demonstrates 0.92 precision and 0.88 recall for cache-based SCAs (Prime+Probe variants), representing a 92% F1-score improvement over SVM baselines. SHAP-based feature attribution reveals BTB-miss run-lengths and memory controller contention queues as critical attack patterns. This pipeline automatically categorize interpretable attack patterns if they are risky for the system, enabling proactive identification of safe and unsafe instructions for secure hardware through gem5's reconfigurable memory hierarchy and cache partitioning mechanisms.

**Keywords:** Microarchitectural Security · Side-Channel Attacks · gem5 Simulator · Embedded Systems · Cache Timing Analysis.

## 1 Introduction

Side-channel attacks (SCAs) represent a critical class of security vulnerabilities that exploit physical leakage vectors such as cache access patterns, timing variations, and power consumption signatures to compromise computational
confidentiality [7] [10]. These attacks circumvent traditional cryptographic pro-
tections by leveraging microarchitectural state changes during program exe-
cution, with high-profile examples like Spectre and Meltdown demonstrating
catastrophic data leakage across security domains. As modern processors grow
increasingly complex, the attack surface for novel SCAs expands exponentially,
rendering conventional signature-based detection methods inadequate against
evolving threats.

Current SCA detection methodologies face three fundamental limitations:

1. **Hardware Dependency**: Physical measurement requirements (e.g., power monitors, EM probes) limit scalability and real-world deployment [11].

2. **Signature Reliance**: Rule-based detectors fail against zero-day attacks lacking predefined patterns [4].

3. **Supervised Learning Constraints**: ML approaches requiring labelled attack datasets cannot identify novel threat vectors [15].

To address these challenges, we propose a simulation-driven machine learn-
ing framework that integrates gem5’s cycle-accurate architectural simulator [13]
with **unsupervised learning techniques** for hardware-agnostic SCA detec-
tion. Our methodology eliminates physical measurement barriers by generating
synthetic execution traces of cache-based attack patterns (Spectre-V1/V2 [8],
Prime+Probe [18], Flush+Reload [19]) and benign workloads, extracting dis-
criminative temporal features.

This paper makes three core contributions:

1. **First integration** of gem5's reconfigurable memory hierarchy with unsupervised and supervised ML for SCA detection

2. **Temporal feature engineering methodology** quantifying cache/timing vulnerabilities through entropy and autocorrelation analysis

3. **Empirical validation** detecting attack Patterns (Spectre, Prime+Probe, Flush+Reload) and Safe patterns with > 90% precision

Our framework establishes a paradigm shift from reactive patching to proac-
tive vulnerability discovery, providing a scalable pipeline for pre-silicon security
validation.

Section 2 reviews SCAs and gem5 simulation capabilities. Section 3 details for Side Channels and Cache-Based Timing Attack Patterns, Section 4 details our ML pipeline, with experimental results in Section 5. We discuss implications and conclude in Section 6.

2 Background

2.1 Side-Channel Attack Fundamentals

Side-channel attacks (SCAs) represent a critical class of security threats that circumvent theoretical cryptographic strength by exploiting unintended physical leakage generated during the implementation and execution of cryptographic
algorithms on physical devices [14]. Unlike traditional cryptanalysis targeting
mathematical weaknesses, SCAs leverage observable phenomena correlated with
internal secret-dependent operations, such as power consumption [1], electro-
magnetic emanation, execution timing, acoustic noise, or cache access patterns.
The fundamental premise is that minute variations in these physical signals [2],
influenced by the manipulation of secret keys or sensitive data (e.g., intermediate
values like S-box outputs), can be measured, statistically analyzed, and corre-
lated to infer secret information [3]. Techniques like Differential Power Analy-
sis (DPA) or Correlation Power Analysis (CPA) exemplify this by statistically
comparing measured traces (e.g., power) against predicted models derived from
hypothetical key guesses and known inputs/outputs. Consequently, the effective-
ness of SCAs hinges on the presence of data-dependent leakage within the phys-
ical channel and the attacker's ability to acquire sufficient high-quality traces
and apply appropriate statistical methods to extract secrets, posing a signifi-
cant practical threat even to mathematically sound algorithms. Unlike software
vulnerabilities, SCAs target hardware implementation characteristics:

- Cache-Based Attacks: Measure leakage variations

$$
\text{Leakage} = f(\text{Cache\_State} \oplus \text{Secret\_Data}) \quad (1)
$$

Prime+Probe [18] and Flush+Reload [19] manipulate shared cache states to monitor victim access patterns. Spectre variants [8] exploit speculative execution to create cache-based covert channels.

- Timing Attacks: Measure instruction latency variations:

$$
\Delta t = t_{\text{secret}=1} - t_{\text{secret}=0} \qquad (2)
$$

Where *t* represents execution time sensitive to secret-dependent branches or
memory accesses.

## 2.2 gem5 Architectural Simulator

**Configuration, Customization, and Simulation Capabilities** Gem5 [13] provides cycle-accurate simulation of modern microarchitectures, supporting diverse ISAs and operation modes as summarized in Table 1. Its Python-based configuration system enables granular customization of hardware components, including CPU models, memory hierarchies, and interconnects [13].

The simulator's advanced memory subsystem supports configurable caches,
memory controllers, and interconnects [17], while featuring state-of-the-art branch
predictors like LTAGE [14]. Gem5's instrumentation capabilities, critical for se-
curity research, are detailed in Table 2.

**Advantages and Limitations** Gem5's primary strengths include:

- *Flexibility*: Python scripting enables rapid prototyping of novel microarchitectures
<table><caption>**Table 1.** Gem5 Configuration Capabilities</caption><thead><tr><th>Feature</th><th>Supported Options</th></tr></thead><tbody><tr><td>ISAs</td><td>x86, ARM, SPARC, MIPS, RISC-V [6]</td></tr><tr><td>Simulation Modes</td><td>Full-System (FS): Full software stack emulation<br>Syscall Emulation (SE): Application-level focus</td></tr><tr><td>CPU Models</td><td><i>In-order</i>: AtomicSimpleCPU, TimingSimpleCPU<br><i>Out-of-order</i>: O3CPU, DerivO3CPU [9]</td></tr><tr><td>Key Features</td><td>Speculative execution<br>Dynamic scheduling<br>Instruction-level parallelism</td></tr></tbody></table>

<table><caption>**Table 2.** Gem5 Simulation Instrumentation</caption><thead><tr><th>Category</th><th>Tracked Metrics</th></tr></thead><tbody><tr><td>Memory Hierarchy</td><td>Cache access patterns (hit/miss), Replacement policies, Prefetching behavior, Coherence state transitions</td></tr><tr><td>Pipeline</td><td>Instruction dependencies, Branch mispredictions, Resource contention, Execution stalls</td></tr><tr><td>System Metrics</td><td>Cycle-accurate timing, Memory access traces, Queue utilization</td></tr></tbody></table>

- *Reproducibility*: Deterministic execution for vulnerability analysis [13]

- *Comprehensiveness*: Cross-layer modeling from ISA to DRAM

Notable limitations:

- *Performance Overhead*: High-fidelity simulations incur significant time costs

- *Timing Fidelity*: Some real-world behaviors abstracted [13]

- *Configuration Complexity*: Steep learning curve for full-system modeling

## 2.3 Machine Learning for SCAs

Unsupervised techniques address the challenge of lacking labeled data in supervised methods by detecting anomalies or structures directly from the data:

- **Isolation Forest** [12]: Identifies anomalies based on how easily a point is isolated in random binary trees. The anomaly score is computed as:

$$s(x, n) = 2^{-\frac{E(h(x))}{c(n)}} \qquad (3)$$

where $E(h(x))$ is the expected path length of instance $x$ in the forest, and $c(n)$ is a normalization factor. Shorter paths suggest higher anomaly likelihood.

- **Variational Autoencoders (VAE)** [16]: VAEs learn latent representations for input reconstruction. The loss function combines reconstruction loss and a regularization term:

$$\mathcal{L}(\theta, \phi) = -E_{z \sim q_{\phi}}[\log p_{\theta}(x|z)] + D_{KL}(q_{\phi}(z|x) \parallel p(z)) \qquad (4)$$
where the first term measures how well the input is reconstructed, and the KL divergence ensures latent variables follow a prior. High reconstruction error $||x - \hat{x}||_2$ signals anomalies.

- **HDBSCAN Clustering** [5]: Performs density-based clustering without requiring the number of clusters. An objective for choosing optimal cluster $C_i$ is:

$$ \text{CLUSTER} = \arg \max_{C_i} \left( \frac{\sum_{x_j \in C_i} \kappa(x_j, x_k)}{|C_i|} \right) \quad (5) $$

where $\kappa(x_j, x_k)$ is a similarity function. Points not fitting any cluster are flagged as potential anomalies.

For the trace analysis, we use the extracted patterns of the attacks and run in the SE mode to get the execution traces our pipeline consists of seven stages, a detailed explanation of Feature extraction and model pipeline is discussed in the methodology Section 4

## 2.4 Simulation vs. Physical SCAs

Side-channel analysis (SCA) on physical hardware often suffers from external noise, limited observability, and hardware-specific constraints. In contrast, simulation environments such as Gem5 offer fine-grained visibility and control, making them ideal for early-stage vulnerability exploration and controlled attack modelling.

Table 3 summarizes the key tradeoffs between simulation and physical measurement. While simulations provide high fidelity and deterministic execution, they may not fully capture real-world noise or hardware-specific idiosyncrasies.

<table><caption>Table 3. Simulation vs. Physical Measurement Tradeoffs</caption><thead><tr><th>Factor</th><th>gem5 Simulation</th><th>Physical Hardware</th></tr></thead><tbody><tr><td>Trace Granularity</td><td>Cycle-accurate</td><td>Limited by probes</td></tr><tr><td>Noise Level</td><td>None</td><td>Signal-to-noise challenges</td></tr><tr><td>Attack Injection</td><td>Precise control</td><td>Requires exploit code</td></tr><tr><td>Reproducibility</td><td>Deterministic</td><td>Environment-dependent</td></tr><tr><td>Cost</td><td>Computational</td><td>Hardware procurement</td></tr></tbody></table>

As shown, simulation enables reproducible and cost-effective experimentation, especially when exploring low-level microarchitectural behaviour. Our approach builds on these advantages and validates proxy metrics against real hardware attacks in Section 5.
## 3 Side Channels and Cache-Based Timing Attack Patterns

Side-channel attacks exploit indirect information leakage from hardware behaviour such as timing, power consumption, or cache usage to infer sensitive data. One of the most studied classes is cache-based timing attacks, which leverage differences in memory access times due to caching behaviour.

Among these, we train our model on Flush+Reload, Spectre(V1/V2), and Prime+Probe type attack pattern classes. These attack patterns are well-known attack patterns that rely on shared memory and precise timing to detect whether a victim accessed specific cache lines. We discuss some attack patterns and normal execution patterns in next section.

### 3.1 Flush+Reload Attack Pattern (Malicious Code pattern)

The example below demonstrates a basic Flush+Reload cache attack pattern. The attacker flushes a memory address, waits, and then reloads it while measuring access latency to determine if the victim accessed it:

<caption>Listing 1.1. Flush+Reload Timing Attack in C</caption>

```c
TARGET_ADDR ((char*)0x7ffff7dd18e0)
unsigned long time1, time2;
volatile char *addr = TARGET_ADDR;
_mm_clflush(addr); // Flush from cache
time1 = _rdtscp(&junk);
(void)*addr; // Reload
time2 = _rdtscp(&junk);
if (time2 - time1 < 80) {
    printf("Victim likely accessed the data!\n");
}
```

The attacker relies on the cache access latency: if the victim accessed the line between flush and reload, the reload will be fast. Our Model pipeline gets this pattern and extracts the features from the executed trace; we run 532 different patterns of these attack classes to train our models, and the detailed features are listed in Section 4.

### 3.2 Normal Memory Access Pattern (Benign Code)

To ensure the reliability and robustness of our side-channel detection model, it is essential to include benign programs as part of the evaluation process. These normal code patterns serve as a baseline for distinguishing between regular system behavior and potential malicious activity.

The following example demonstrates a benign memory access pattern that performs straightforward computation without any form of cache manipulation or timing measurements. This type of code is representative of typical application behavior encountered in user-space programs:
<caption>Listing 1.2. Normal Memory Access Code</caption>

```c
int arr[1000];
for (int i = 0; i < 1000; i++) {
    arr[i] = i * 2; // Simple arithmetic operation
}
printf("Computation ▷ complete.\n");
```

This code initializes an array and iteratively fills it with computed values. It does not utilize cache flushing instructions (such as `_mm_clflush`), nor does it include high-resolution timing functions (e.g., `rdtsc`, `rdtscp`) to measure access latencies. As a result, it lacks the key behavioural traits associated with cache-based timing attacks such as `Flush+Reload` or `Prime+Probe`.

Including such benign memory patterns in our dataset is critical for training the model to recognize legitimate activity and reduce false positive rates. These patterns help define the boundary between normal execution and anomalous side-channel behaviour, thereby improving the precision of detection mechanisms.

## 4 Methodology

Our end-to-end framework integrates gem5 architectural simulation with supervised and unsupervised machine learning to automate side-channel attack detection.

We collect 200 different samples of Spectre v1 and v2, 230 samples of Prime+Probe, 240 samples of Flush+Reload and 250 samples of Normal execution code for the analysis. We run all these samples to get the trace analysis on each simulation, and we save the values of some features listed in Table 4

The methodology comprises four interconnected phases as illustrated in Figure 1.

<figure><img src="image_4.png" /><figcaption>**Fig. 1.** Multi-stage attack classification framework architecture showing the integrated simulation and detection pipeline</figcaption></figure>

Our methodology consists of four distinct phases, each focused on a different aspect of attack detection and analysis.
<table><caption>**Table 4.** Feature Set for SCA Detection in gem5 Traces</caption><thead><tr><th>Feature Name</th><th>Data Type</th><th>Description</th></tr></thead><tbody><tr><td>total</td><td>integer</td><td>Cumulative count of retired instructions during trace period</td></tr><tr><td>totalahan</td><td>integer</td><td>Number of branch instructions executed (conditional/unconditional)</td></tr><tr><td>branch_mispredictions</td><td>integer</td><td>Count of incorrectly predicted branches</td></tr><tr><td>memory_reads</td><td>integer</td><td>Read operations to main memory (excluding cache hits)</td></tr><tr><td>memory_writes</td><td>integer</td><td>Write operations to main memory</td></tr><tr><td>int_alu_ops</td><td>integer</td><td>Integer arithmetic/logic operations executed</td></tr><tr><td>call_instructions</td><td>integer</td><td>Function call operations (CALL/RET pairs)</td></tr><tr><td>push_pop_instructions</td><td>integer</td><td>Stack manipulation instructions (PUSH/POP)</td></tr><tr><td>rdtsc_count</td><td>integer</td><td>Executions of RDTSC instruction (timing attack indicator)</td></tr><tr><td>test_ops</td><td>integer</td><td>TEST instruction executions (bitwise comparison)</td></tr><tr><td>lea_ops</td><td>integer</td><td>Load Effective Address instructions (memory address calculation)</td></tr><tr><td>BTB_misses</td><td>integer</td><td>Branch Target Buffer miss events</td></tr><tr><td>BTB_hits</td><td>integer</td><td>Branch Target Buffer hit events</td></tr><tr><td>BTB_miss_addresses</td><td>hexadecimal list</td><td>Memory addresses causing BTB misses</td></tr><tr><td>BTB_hit_addresses</td><td>hexadecimal list</td><td>Memory addresses causing BTB hits</td></tr><tr><td>attack_label</td><td>categorical</td><td>Ground truth classification: {Normal, spectre, flush+Reload, Prime+Probe}</td></tr></tbody></table>

## 4.1 Phase 1: Pattern Execution.

In this phase, we execute code patterns designed to model speculative execution behaviors. These patterns include the *Flush-based* variant, which utilizes cache and TLB invalidation primitives to induce speculative execution; the *Probing-intensive* variant, which relies on frequent timestamp counter (TSC) reads to trigger speculative behavior; and the *Baseline* variant, representing normal, non-
speculative execution, which serves as a control for distinguishing speculative activities.

## 4.2 Phase 2: Trace Generation.

Following pattern execution, we simulate the patterns within the gem5 architectural simulator, generating detailed microarchitectural execution traces. These traces capture essential data such as cache access sequences, branch predictor states, and memory access patterns, which are critical for understanding the fine-grained execution of the code patterns.

**Attack Simulation and Trace Generation** We simulated a range of speculative execution and side-channel attack patterns, including Speculative Execution attack patterns such as Spectre V1/V2, Prime+Probe attack patterns, and Flush+Reload attack patterns, alongside normal execution patterns. These simulations were conducted using gem5's highly accurate, cycle-accurate models, which were configured to simulate realistic system and attack behaviors under controlled conditions. The configurations for these simulations were as follows:

<table><caption>**Table 5.** Attack Simulation Configuration</caption><thead><tr><th>Component</th><th>Configuration</th></tr></thead><tbody><tr><td>Processor</td><td>Out-of-order x86 CPU (4GHz, 4-wide issue)</td></tr><tr><td>Memory Hierarchy</td><td>3-level cache (64B line size)</td></tr><tr><td>L1 Cache</td><td>32KB I/D (4-way)</td></tr><tr><td>L2 Cache</td><td>256KB (8-way)</td></tr><tr><td>LLC</td><td>2MB (16-way)</td></tr><tr><td>Workloads</td><td>Speculative Patterns: Mispredicted branch exploitation<br>Flush+Reload: Branch Target Buffer poisoning<br>Prime+Probe: Cache set contention attacks<br>Normal Patterns: Pattern chunk normal flow</td></tr></tbody></table>

Each simulation-generated execution trace contains the features listed in Table 4.

## 4.3 Phase 3: Machine Learning Analysis.

This phase involves two distinct approaches: the supervised approach and the unsupervised approach. The supervised approach utilizes a Support Vector Machine (SVM) classifier trained on labeled trace data to distinguish between attack and benign traces. In contrast, the unsupervised approach employs an ensemble method that combines Isolation Forest for anomaly detection and HDBSCAN for density-based clustering, enabling the identification of latent structures and
anomalies in unlabeled data. This approach helps discover hidden attack patterns that the supervised model may not capture.

## 4.4 Phase 4: Model Evaluation.

The performance of the machine learning models is evaluated using several metrics, including Precision/Recall curves, F₁-scores, and anomaly detection rates. Furthermore, the models are assessed for robustness against adversarial variants to ensure they can generalize to real-world attack scenarios. This evaluation is essential for validating the effectiveness and reliability of our detection models.

## 4.5 Unsupervised Detection Ensemble

Processed traces train three complementary models:

<table><caption>**Table 6.** Unsupervised model configurations</caption><thead><tr><th>Model</th><th>Configuration</th></tr></thead><tbody><tr><td>Isolation Forest</td><td>200 trees, contamination=0.25</td></tr><tr><td>Variational Autoencoder (VAE)</td><td>Encoder: 32-16-8, Decoder: 8-16-32</td></tr><tr><td>HDBSCAN</td><td>min_cluster_size=500, min Samples=100</td></tr></tbody></table>

**Variational Autoencoder Architecture** The VAE loss function combines reconstruction error with KL divergence:

$$ \mathcal{L} = \underbrace{E_{q_{\phi}(z|x)}[\log p_{\theta}(x|z)]}_{\text{Reconstruction}} - \beta \underbrace{D_{\text{KL}}(q_{\phi}(z|x) \| p(z))}_{\text{Regularization}} \quad (6) $$

where $\beta = 0.5$ controls the regularization strength.

## 4.6 Ensemble Fusion and Signature Extraction

Model outputs are combined via majority voting:

$$ \text{Attack} \iff \sum_{i=1}^{3} I(M_i(x) = \text{attack}) \geq 2 \quad (7) $$

Interpretable signatures are generated through:

**SHAP-based Attribution** Computes feature contributions using game-theoretic approach:

$$ \phi_i = \sum_{S \subseteq F \setminus \{i\}} \frac{|S|!(|F| - |S| - 1)!}{|F|!} [f_{S \cup \{i\}}(x) - f_S(x)] \quad (8) $$

where $F$ is the complete feature set.
# 5 Experimental Results

Our dataset consists of 10,000 traces, each representing different execution patterns with 15 features listed in Table 7, as detailed in Table 4. We applied Kmeans clustering to group these traces, with the clustering results shown in Figure 2.

<table><caption>**Table 7.** Dataset composition across attack types</caption><thead><tr><td>Pattern Type</td><td>Traces Duration (cycles)</td><td>Features</td></tr></thead><tbody><tr><td>Speculative</td><td>2500</td><td>10M-50M</td></tr><tr><td>Flush+Reload</td><td>2500</td><td>15M-60M</td></tr><tr><td>Prime+Probe</td><td>2500</td><td>5M-30M</td></tr><tr><td>Normal Execution</td><td>2500</td><td>8M-55M</td></tr></tbody></table>

<figure><img src="image_5.png" /><figcaption>**Fig. 2.** KMeans Clustering Results and Actual Attack Labels</figcaption></figure>

The left plot in Figure 2 shows the results of K-means clustering with 4 clusters on the dataset, where each cluster is represented by a different color. The x-axis and y-axis correspond to Principal Component 1 and Principal Component 2, respectively. The right plot displays the actual attack labels (Spectre, Prime+Probe, Flush+Reload, and Normal) color-coded accordingly. The comparison between the two plots allows for evaluating the clustering algorithm's performance in distinguishing different attack types and normal execution.

## 5.1 Detection Performance

In our analysis, we applied unsupervised learning techniques to classify and detect different attack patterns, including Spectre, Prime+Probe, Flush+Reload,
and Normal execution. The results are presented in Figure 3, which consists of four subplots, each demonstrating a different aspect of the analysis.

<figure><img src="image_6.png" /><figcaption>**Fig. 3.** Unsupervised Learning Results for Attack Detection</figcaption></figure>

The True Labels plot shows the distribution of traces according to their actual attack labels, with distinct clusters for Spectre (purple), Prime+Probe (blue), Flush+Reload (green), and Normal (light green). This plot provides a baseline understanding of how the different attack patterns are naturally distributed in the feature space.

In the Ensemble Predictions plot, the traces are classified into two categories: normal and attack. The ensemble-based attack detection model successfully differentiates between normal and attack patterns, though some overlap is observed, particularly between Prime+Probe and Flush+Reload traces. This suggests that these attack patterns share similar characteristics, making them more challenging to separate.

<figure><img src="image_7.png" /><figcaption>**Fig. 4.** Unsupervised Learning Results for Attack Detection</figcaption></figure>
The VAE Reconstruction Error plot visualizes the reconstruction error from a Variational Autoencoder (VAE), which was used to learn an unsupervised representation of the data. Traces with lower reconstruction error (blue) are generally normal, while attack patterns exhibit higher reconstruction errors (red), indicating that they introduce anomalies that deviate from the learned normal behavior.

Finally, the HDBSCAN Clusters plot illustrates the results of Hierarchical Density-Based Spatial Clustering of Applications with Noise (HDBSCAN), which groups the traces into four distinct clusters. The model successfully identifies different attack types, with the normal traces clustered separately from the attacks. However, some attack patterns, such as Prime+Probe and Flush+Reload, show overlap, highlighting the need for further refinement to improve the separation between these attack types.

Table 8 presents a comparative analysis of detection performance across multiple machine learning models. The ensemble method demonstrates superior performance across all evaluation metrics, achieving the highest precision (0.92), recall (0.88), and F1-score (0.90). Among individual models, the Variational Autoencoder (VAE) shows competitive results (F1-score: 0.86), slightly outperforming the SVM baseline (F1-score: 0.89) in precision but falling short in recall. Both Isolation Forest and HDBSCAN exhibit comparable performance characteristics, with Isolation Forest maintaining a marginal advantage in all three metrics. The ensemble's significant performance improvement (2-4% absolute gain in F1-score over the nearest individual model) highlights the effectiveness of combining multiple detection approaches. These results validate our hypothesis that ensemble methods would outperform individual detectors in identifying speculative execution attacks.

<table><caption>**Table 8.** Detection performance comparison</caption><thead><tr><th>Model</th><th>Precision</th><th>Recall</th><th>F1-Score</th></tr></thead><tbody><tr><td>Isolation Forest</td><td>0.85</td><td>0.82</td><td>0.83</td></tr><tr><td>VAE</td><td>0.89</td><td>0.84</td><td>0.86</td></tr><tr><td>HDBSCAN</td><td>0.83</td><td>0.80</td><td>0.81</td></tr><tr><td><strong>Ensemble</strong></td><td><strong>0.92</strong></td><td><strong>0.88</strong></td><td><strong>0.90</strong></td></tr><tr><td>SVM Baseline</td><td>0.90</td><td>0.87</td><td>0.89</td></tr></tbody></table>

These results demonstrate the effectiveness of unsupervised learning methods in distinguishing between normal and attack patterns, though further tuning is needed to enhance the differentiation of similar attack types.

# 6 Conclusion

The proposed framework demonstrates three significant advantages: (1) **attack-agnostic detection** capable of identifying novel speculative execution vari-
ants without predefined templates, (2) **architectural interpretability** through SHAP analysis that reveals microarchitectural root causes of vulnerabilities, and (3) **proactive defense integration** enabling automated countermeasure triggering. The observed 92% F1-score improvement over SVM baselines primarily stems from temporal feature engineering capturing attack dynamics, ensemble complementarity (leveraging Isolation Forest for global anomalies and HDB-SCAN for local clusters), and latent space modeling of nonlinear relationships. While current limitations in detecting flush-based attacks (recall=0.79) indicate areas for improvement, future work will address this through enhanced cache coherence state tracking mechanisms.

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