# Beyond Silicon Area: Co-Product Allocation for a Binning-Aware Carbon Footprint of Processors

Olivier Weppe, Thibaut Marty, Jean-Christophe Prévotet, Maxime Pelcat

► To cite this version:

Olivier Weppe, Thibaut Marty, Jean-Christophe Prévotet, Maxime Pelcat. Beyond Silicon Area: Co-Product Allocation for a Binning-Aware Carbon Footprint of Processors. Sustech, Apr 2026, Orange county, United States. hal-05488413

HAL Id: hal-05488413

https://hal.science/hal-05488413v1

Submitted on 2 Feb 2026

HAL is a multi-disciplinary open access
archive for the deposit and dissemination of sci-
entific research documents, whether they are pub-
lished or not. The documents may come from
teaching and research institutions in France or
abroad, or from public or private research centers.

L'archive ouverte pluridisciplinaire HAL, est
destinée au dépôt et à la diffusion de documents
scientifiques de niveau recherche, publiés ou non,
émanant des établissements d'enseignement et de
recherche français ou étrangers, des laboratoires
publics ou privés.

<figure><img src="image_1.png" /></figure>

Distributed under a Creative Commons CC BY 4.0 - Attribution - International License
# Beyond Silicon Area: Co-Product Allocation for a Binning-Aware Carbon Footprint of Processors

Olivier Weppe, Thibaut Marty, Jean-Christophe Prévotet and Maxime Pelcat

Univ. Rennes, INSA Rennes, CNRS, IETR – UMR 6164, F-35000 Rennes, France

olivier.weppe@insa-rennes.fr thibaut.marty@insa-rennes.fr

jean-christophe.prevotet@insa-rennes.fr maxime.pelcat@insa-rennes.fr

*Abstract*—Central Processing Unit (CPU) manufacturing is a major contributor to the environmental footprint of digital technology. State-of-the-art Life Cycle Assessment (LCA) and embodied Greenhouse Gasses (GHG) emission models evaluate carbon impacts of CPU manufacturing based on chip area and lithography resolution, which results in a uniform carbon footprint for an entire range of products derived from the same design. However, this simplification masks the heterogeneity arising from industrial binning, where chips from the same lot are differentiated according to their performance. To resolve this inconsistency, we propose a new analytical framework that considers the different variants of a processor as co-products. We develop and compare several allocation methods for CPU manufacturing impact, including an economic allocation (price-based) and a physical allocation (performance-based). Moreover, we model the influence of production yield by contrasting a uniform distribution hypothesis with a more realistic Gaussian yield distribution. Our results reveal a significant redistribution of the environmental burden when applying our methods: the carbon impact of high-end processors is substantially higher than current estimates, while that of entry-level models is reduced by up to 87%. This methodological framework provides a fairer and more accurate picture, essential for guiding eco-design strategies and hardware acquisition policies for enhancing electronics sustainability.

*Index Terms*—Environmental Impact, Greenhouse Gas (GHG) Emissions, Global Warming Potential (GWP), Manufacturing, Silicon Devices, Integrated Circuits (ICs), Life Cycle Assessment (LCA), Central Processing Unit (CPU)

## I. INTRODUCTION

The recent rise in Artificial Intelligence (AI) computing demands highlights the environmental impact of data centers and, more specifically, the carbon footprint of computing. Although the energy consumption of computing is the main contributor to carbon impact of digital services [1], the manufacturing contribution to this carbon footprint shall not be overlooked [2]. Semiconductor devices contribute the largest share of the carbon impact of electronics devices manufacturing [3]. For this reason, device carbon footprint estimation must accurately reflect the reality of the environmental impacts of those components.

Consistently with LCA methodologies, we refer to the GHG emissions of CPUs at manufacturing as embodied carbon footprint, expressed in kg of equivalent CO₂ (CO₂e). State-of-the-art models for estimating this footprint rely on a “flat” allocation, where the environmental burden is assumed

<figure><img src="image_2.png" /><figcaption>Fig. 1: Representation of the estimated embodied carbon footprint of CPUs depending on their performance (The color indicates the processing node in nm.). Horizontal clusters reflect the binning industrial process.</figcaption></figure>

to be uniform across all devices derived from a common design. This approach, however, overlooks common industrial practices such as product binning, which creates co-products of varying performance levels with similar die surface.

This paper argues that this flat allocation is an extreme position, as would be allocating the entire footprint to only the highest-performing chips. We therefore propose a nuanced, realistic middle-ground allocation strategy that better reflects the manufacturing realities of CPUs.

To test our proposed framework, we apply it to a comprehensive database of over 3800 commercial CPUs [4], allowing for a large-scale analysis of real-world product series. The remainder of this paper is organized as follows. Section II details the state-of-the-art methodology and exposes the problem originating from its flat allocation hypothesis. Section III introduces our proposed allocation framework. Section IV presents the experimental setup and the results of our large-scale analysis, followed by a discussion in Section V and our conclusions in Section VI.

## II. PROBLEM STATEMENT

1) Silicon area estimation: As there is no direct way to measure the carbon emission due to silicon fabrication, mod-
els to estimate the embodied footprint of a given integrated circuit have been developed that build on macroscopic data collection. Current methodologies rely on technical [5], [6] or physical characteristics of those components, such as the technology node and total silicon area [7]. Indeed, recent studies show that, for advanced technologies below 130nm, the embodied carbon footprint increases with the reduction of feature sizes, such as transistor channel length [8].

Most models hypothesize a proportional relationship between embodied carbon footprint and silicon area, employing a scaling factor that is technology node dependent. This type of model is expressed as:

$$G = \alpha_{nm} \cdot S, \qquad (1)$$

where G is the carbon footprint of the chip in kg CO₂e, αₙₘ is a scaling constant dependent on the technology node (the size of the features embedded into the silicon in nanometers) in kg CO₂e/cm², and S is the die silicon area in cm². This methodology is particularly useful as it is compliant with the internal operations of LCA databases such as Ecoinvent [9]. Moreover, having a surface proportional model eases the calculation of variations between devices or number of units, as it is consistent with the linear hypothesis of most LCA calculators [10], where a reference flow is evaluated from a given entry in the LCA database with a unique amount parameter.

However, a limitation of this conventional approach becomes obvious when representing the estimated carbon impact using the usual methodology versus the synthetic performance from benchmark software<fnref n="1" />. In Figure 1, a peculiar pattern can be observed. Instead of the scattered points that could intuitively be expected, we observe horizontal clusters of CPUs, which span more than an order of magnitude of benchmark score. These patterns are the sign of an industrial process called “Binning”.

2) The impact of binning: Indeed, a typical series of CPUs is composed of devices that are based on the same silicon design. In a perfectly optimized production environment, only one type of CPU would be produced for the whole production. However, some random manufacturing defects cannot be fully controlled in practice. Temperature, impurities and dust expose variations that produce discrepancies in the fabrication of transistors and their associated connectivity network, and consequently create inconsistencies in the physical parameters of the CPU at the end of production line [11]. Variations occur, for instance, in the operating frequency the CPU can operate at. A CPU rated at 3GHz is guaranteed to run without flaw, under sufficient voltage and temperature conditions, at this frequency. Yet, process variations lead to the fabrication of some devices that fail to operate at such a frequency; those will be rated (categorized), for example at 2.8GHz or 2.4GHz, depending on their performance during qualification tests. In order to rationalize the market and

simplify the commercial and logistics costs, the produced CPUs do not come with a continuous set of frequency ratings; instead, CPUs are grouped according to their performance and the corresponding market needs to form a Stock Keeping Unit (SKU) that will be branded as a particular product [12]. These groups of chips sharing common characteristics are called “bins”, hence the name “binning” for the action of sorting devices in this manner. This variation of functionality and performance from one chip to the next manufactured one from a common design is illustrated in Figure 2 where a single chip with 156mm² die can be derived into various products with different characteristics such as frequency and number of cores [13].

<figure><img src="image_3.png" /><figcaption>Fig. 2: Example of a series of CPUs based on the same silicon die (156mm², 7nm) but with different characteristics in terms of number of cores, ranging from 4 to 8, and frequencies from 1.8GHz to 3.8GHz.</figcaption></figure>

This method of classifying devices based on performance to form different product categories with different prices allows revenue from lower-performing devices —which would otherwise be discarded— to be included in the overall return on investment for the entire product line.

Other than frequency and core count, the power efficiency of the transistors can also vary from chip to chip [14]. This time, the product line is segmented in low power target devices (e.g. laptops), mid-range target devices (e.g. desktop) and high performance (e.g. gaming/High Performance Computing (HPC) machines).

When process variations are too large, local defects can occur, either leading to the failure of one or several transistors, or inability to reach an acceptable clock frequency. For a dedicated non-programmable Application-Specific Integrated Circuit (ASIC), such defects would be considered as prohibitive and the chip would be discarded. This is where the definition of yield comes from: production efficiency is the proportion of viable chips -in terms of performance an functionality- compared to the total number of chips that are manufactured. Without a binning strategy, the economical model of most product series would not be viable. The low performance devices, that would have been by-products, are

<footnote n="1">¹Performance metric based on composite benchmark scores (https://www.cpubenchmark.net/) used as consistent, hardware-centric proxy for silicon capability, mitigating variability across specific workloads.</footnote>
considered as co-products when using binning.

This discussion leads to the question of which allocation strategy is best suited for this technology. As an alternative to the “flat” allocation per silicon surface currently in use in existing studies, an alternative strategy consists in considering that highest performance products are responsible for most, if not for the whole production, of silicon wafers in the factory. The rationale here is to assume that, ultimately, the goal of the manufacturer is to produce only those high-performance chips, all chips with lower performance being considered as degraded versions of the “good” product. In this point of view, all the carbon emitted by the whole chip production would be allocated to the only chips that have the highest specifications.

Obviously, this is an extreme way to distribute the environmental impact on a production having so many variables. However, it is important to notice that the current way to allocate carbon footprint, (i.e. no allocation at all, all chips being considered as equal) is also an extreme position.

### III. METHODOLOGY

Our study relies on the idea that the embodied carbon footprint of fabricating a single chip shall be evaluated from the environmental cost of all the processors of the same series, by allocating cost to the different final products (co-products) proportionally to their respective bin-value. This bin-value, which is the key parameter for this allocation [15], should be computed from economical (market price) [16], [17] or technical performance (in our case, Million Instructions per Second (MIPS) performance).

According to this allocation, high-end processors, that represent the rarest devices (low yield) and the most valued products from the fabrication process, will be allocated a higher embodied carbon footprint than their low-end counterparts, even if they have dies of the same surface. Consequently, these high-end devices carry a larger portion of the production line’s environmental burden. This mechanism acknowledges that the production line, whose viability is increasingly challenged by weakened return on investment from technology costs [18], is ultimately sustained by the economic returns generated from the sale of these co-products.

In order to hold sufficient information, representative of the variety of CPUs in the market from the main Personal Computer (PC) CPU vendors (Intel and AMD), we rely on a large database [4] where over 3800 CPUs are referenced with detailed characteristics among their physical characteristics such as die area, number of cores, frequency, or technology node. The database also provides release dates and launch prices. The raw data underwent a cleaning and normalization process. Notably, launch prices were adjusted for inflation to 2025 US dollars<fnref n="2" /> to ensure fair temporal comparison. Entries with missing essential data points, such as die area or technology node, were excluded from the relevant analyses.

Around 1400 devices were included in our study after this filtering process.

With silicon area and technology node, we are able to determine a first approximation of the carbon footprint using Equation (1). The $\alpha_{nm}$ rely on the IMEC Netzero model [19], which encompasses the latest technologies in accordance with the studied CPUs. As IMEC Netzero model [19] does not report carbon footprint for technologies larger than 65nm, such legacy components (pre-2000) are excluded from our study.

Starting from the state-of-the-art carbon footprint estimation proportional to the die surface area, we propose a progressive allocation were carbon impact $C_i$ is dependent on the bin-value $K_i$ of the chip $i$ in equation 2.

$$C_i = C_{avg} \frac{K_i}{Z}, \qquad (2)$$

where $C_{avg}$ is the average carbon footprint for the series (which is the reported footprint when no allocation is performed), and $Z$ is a normalization factor.

This model makes carbon footprint proportional to a factor $K_i$. Instead of evenly allocating the same average carbon footprint $C_{avg}$ to all devices according solely to their silicon area and process node, we distribute the total quantity of carbon depending on one characteristic factor $K_i$, which we call bin-value. For example, we study 1) raw performance and 2) price as relevant $K_i$ bin-value parameters for chip $i$. In this respect, the carbon proportionality hypothesis is supported by the fact that a CPU with twice the performance could replace two slower CPUs to perform the same task, or that the cost of two low-end CPUs could be spent on a single high-end product. One may note the normalization factor $Z$ that ensures that the overall carbon quantity matches the estimations for the whole production. To meet this requirement, we need to set $Z$ as the average value $K_{avg}$ for the series: $Z = \frac{1}{N} \cdot \sum K_i = K_{avg}$. This parameter is mandatory to maintain the coherence of the model with top-down production analyses that have provided the large scale numbers for the construction of CPU LCA models currently in use. The next sections discuss two options for computing these bin-value parameters: “Tilt” and “Tilt-yield” methods.

#### A. Tilt allocation

To allocate binning-aware embodied carbon footprint to individual CPUs, one needs to know the distribution of products within the series. The proportion of products per bin is usually unknown, so we must make assumptions to perform the analysis.

In order to show a simplified version of the principle of binning-aware allocation, we first assume that the yield is flat all along the CPU series, which means that each new product is expected to belong to each bin with equal probability. For sake of simplicity, we use the raw MIPS measure as a proxy for the global performance of the chip. Indeed, the raw MIPS value is accessible for most devices if considering an average Cycle per Instruction (CPI) per core of 1. Its computation only requires core count and the clock frequency

<footnote n="2">²Correction based on US Consumer Price Index accessed through https://www.usinflation calculator.com/</footnote>
of the device. By multiplying the number of cores $N_{CORES_i}$ by the nominal frequency of the device $f_i$, we obtain the number of raw MIPS, which is a rough approximation of the number of operations that can be performed per second by the CPU. In this case, $K_i = N_{CORES_i} \cdot f_i$, and equation (2) becomes:

$$C_i = C_{avg} \frac{K_i}{K_{avg}} \qquad (3)$$

A typical application of this allocation model is shown in Figure 3, where raw MIPS is used as bin-value for a series of AMD CPUs. The red line shows the slope resulting from the “Tilt” allocation, compared to the flat blue line from the standard embodied carbon estimation, hence the name “Tilt”.

<figure><img src="image_4.png" /><figcaption>Fig. 3: Carbon footprint estimations for a series of AMD CPUs according to their performance (MIPS): standard embodied carbon footprint estimation (blue) shows a flat line (same estimation for all devices) despite a wide spectrum of bin-values. Allocation correction based on “Tilt” (red) and “Tilt-yield” (dashed green) methodologies show a progressive carbon footprint that reflects the bin-value of devices. One may note that relative proportions of processors in bins differ slightly from “Tilt” to “Tilt-yield”, explaining why all “Tilt-yield” impacts can be larger than “Tilt” impacts while average carbon footprint remains equal.</figcaption></figure>

## B. Tilt-yield allocation

A more realistic model of CPU classification than the Tilt one is a Gaussian model, where a middle performance typical component has the highest probability of occurrence, and characteristics that are further from this average value occur with a lower probability. Since the underlying distribution of components across the production series is unknown, this model necessitates assuming the distribution mean ($\mu$) and standard deviation ($\sigma$).

First, the mean will be assumed to be the center point $\mu$ of the bin-value range such that:

$$\mu = \frac{K_{max} + K_{min}}{2} \qquad (4)$$

Then, as we ignore the real share of each products, we need take an estimated value for the standard deviation $\sigma$. Due to the relative secrecy of actual yield values in industrial production, an estimated 0.39 of the value span has been selected for the standard deviation of the Gaussian value distribution to perform the carbon allocation. This value sets the production outcomes that have value below the lowest bin $K_0$ (discarded devices) at 10%, which corresponds to a global yield $Y_{Global}$ over the whole series of 90%. Such production yield is in accordance with the IRDS Roadmap, which expects a yield above 80% [20].

<figure><img src="image_5.png" /><figcaption>Fig. 4: Example of a product yield distribution. Parameters $K_i$ indicate the advertised performance for a given product, which is lower that its maximum value. The probability of a given value is randomly distributed according to the Gaussian distribution, but the yield $Y_i$ for a given bin is the total probability accumulated between the boundaries of that bin and the next. Some bins are larger due to the gap between successive values (in performance or price).</figcaption></figure>

$$C'_{i} = Y_{Global} \cdot C_{avg} \frac{K_{i}}{\sum K_{i} \cdot Y_{i}} \qquad (5)$$

Here the normalization is computed as $\sum K_i \cdot Y_i$. Since the individual bin yields $Y_i$ sum up to $Y_{Global}$ (rather than 1, because of the discarded devices below $K_0$), the weighting factor $Y_{Global}$ ensures that the yield-weighted average of the distributed carbon impacts matches the global average $C_{avg}$. This computation is compliant with the previous flat yield model: in the flat yield hypothesis, where all bins have equal outcomes and no discards are considered ($Y_{Global} = 1$), $Y_i = \frac{1}{N}, \forall i$. In this case, the denominator $\sum K_i \cdot Y_i$ simplifies to the arithmetic mean $K_{avg} = \frac{1}{N} \sum K_i$, effectively reducing the model to a linear allocation.

When determining the yield of a product manufacturing, it is important to distinguish the probability of outcome of a given value from the probability of a CPU to belong to a certain bin. This notion of bin yield is necessary to avoid miscounting the total probability over the complete series. As shown in Figure 4, the probability of obtaining a CPU with a given value can be hypothesized to be a normal distribution as a generalization of the models applied in the industry for clock frequency [21], [22].

Any value point $K$ can be associated in a continuous manner to a probability $P$ on this Gaussian curve. However,
once the series is segmented into discrete products, only the lower and upper bounds of the value are exposed. The exact bin-value of a CPU belonging to this bin is only known to be between these boundaries. The manufacturer guarantees that the bin-value $K_i$ is at least the lowest value of performance, which gives the identity of the bin $i$. That is why the bin yield $Y_i$ must be calculated as the area below the probability curve $P(k)$ between the lower bound $K_i$ of the current bin and the lower bound $K_{i+1}$ for the next bin (with more value). The last bin, corresponding to the high-end product, is gathering the remaining sum of products above the lower bound of highest bin $N$. This is summarized in equation (6):

$$ egin{cases} Y_i = \int_{K_i}^{K_{i+1}} P(k)dk, i \in [0, N-1] \\ Y_{N-1} = \int_{K_{N-1}}^{\infty} P(k)dk \end{cases} \quad (6) $$

One may note that, due to this random process, some CPUs will fall below $K_0$ bin-value mark. Such components will not make it to the market and will be discarded. Our correction model is impacted by this quantity, as the effect of the loss of these components is already incorporated in the various silicon-area models from IMEC used to determine the average impact $C_{avg}$ of the CPUs in the series.

Using the same AMD CPU series, in Figure 3, the “Tilt-yield” model is showing in green a slight offset, compared to the “Tilt” model in red.

### C. Application example

To illustrate the actual usage of the two allocation methods and for the sake of reproducibility, we propose a fictive example. Let us imagine a processor series comprised of SKUs with MIPS bin-values of respectively 10k, 15k and 40k MIPS. The embodied carbon footprint, based on the established area and technology methodology, reports 2 kg CO₂e for each of the CPUs. When we apply our “Tilt” and “Tilt-yield” allocations to this series, the carbon estimations are changed, according to the results found in Table I.

<table><caption>TABLE I: Tilt and Tilt-yield allocations example</caption><thead><tr><th>CPU</th><th>Low-end</th><th>mid-range</th><th>high-end</th></tr></thead><tbody><tr><td>K<sub>i</sub> (MIPS)</td><td>10k</td><td>15k</td><td>40k</td></tr><tr><td>"Flat" alloc. C<sub>avg</sub> (kg CO<sub>2</sub>e)</td><td><b>2</b></td><td><b>2</b></td><td><b>2</b></td></tr><tr><td>Z = 1/N &sum; K<sub>i</sub> = 21.7k</td><td></td><td></td><td></td></tr><tr><td>K<sub>i</sub>/Z</td><td>0.46</td><td>0.69</td><td>1.85</td></tr><tr><td>"Tilt" alloc. (kg CO<sub>2</sub>e)</td><td><b>0.92</b></td><td><b>1.38</b></td><td><b>3.7</b></td></tr><tr><td>P(k):&mu; = 25k,&sigma; = 0.39 &middot; 30k</td><td></td><td></td><td></td></tr><tr><td>Y<sub>i</sub> (Y<sub>Global</sub> = &sum; Y<sub>i</sub> = 90%)</td><td>0.10</td><td>0.70</td><td>0.10</td></tr><tr><td>Z = &sum; K<sub>i</sub> &middot; Y<sub>i</sub> = 15.5k</td><td></td><td></td><td></td></tr><tr><td>Y<sub>Global</sub> &middot; K<sub>i</sub>/Z</td><td>0.58</td><td>0.87</td><td>2.32</td></tr><tr><td>"Tilt-yield" alloc. (kg CO<sub>2</sub>e)</td><td><b>1.16</b></td><td><b>1.74</b></td><td><b>4.65</b></td></tr></tbody></table>

The first step is to determine the normalisation factor $Z$. In the simple “Tilt” allocation this is just the average of the bin values $K_i$ (here in MIPS). Once $Z$ is known, the allocation for each bin is obtained by scaling the original, physically

based carbon estimate $C_{avg}$ with the corresponding bin value $K_i$, and then dividing by $Z$.

In the case of the “Tilt-yield” allocation, the bin yield is involved. For each bin we first compute a yield factor $Y_i$ from a normal distribution. The distribution $P(k)$ is centered at the mid-point of the bin-values (see Equation 4), and its spread is chosen as a fraction of the bin-value span $\sigma = 0.39 \cdot \Delta K$. This choice guarantees that 90% of the total production falls within the series of bins ($Y_{Global} = 0.9$). Using the cumulative normal distribution we then obtain the expected outcome $Y_i$ for each bin. The normalisation factor $Z$ is calculated as the sum of the products $K_i \cdot Y_i$. Finally, the allocated carbon for each bin is derived exactly as in the Tilt scheme, weighting the average carbon $C_{avg}$ by $K_i$, and then normalising by both dividing by the new $Z$ factor and multiplying by $Y_{Global}$.

The “Tilt-yield” allocation shows higher embodied-carbon estimates, especially for the high-end product, exceeding the original 3 kg CO₂e. This can be misinterpreted as an inconsistency in the total carbon accounted for the series. In reality, the higher embodied-carbon figure is a consequence of the low production share (only 10% of units) of the high-end CPUs. This is a typical illustration of the effect of our allocation, designed to concentrate the environmental burden on these premium components.

## IV. RESULTS

We apply binning-aware embodied carbon allocation to the whole set of CPUs in our databases, grouping CPUs by silicon area and process node to extract the series. Results are shown in Figures 5, illustrating the carbon footprint of these series. Leftmost figures use the $K$ parameter based on MIPS for the flat and “tilt” allocations. Rightmost figures display the same comparison using the $K$ parameter based on launch price.

Our results show the tilted allocation which respects a global proportional trend, that increases with bin-value as observable in the regression line showed in Figure 5 which was not present within each CPU series. The spread of carbon estimations for a fixed MIPS performance is reduced, from a 23× ratio to a 7× ratio. The impact on price-based allocation, is limited with a reduction from 12× ratio to 11×. Compared to the original result (“Flat” allocation on Figure 5), a difference can be observed for the CPUs in the low-end or high-end of each series, especially on the extremes of the series where a ratio for high-end to average can reach up to 2.3 with MIPS as bin-value and 3.3 with price as bin-value for our dataset. In the low-end, the variation, can go even further, with up to a 8× reduction of the estimation.

### A. Sensitivity analysis

As the value of $\sigma = 0.39$ for the standard deviation has been arbitrarily selected, it is interesting to assess the significance of this setting in our model. To evaluate the impact of this parameter on our results, we perform a sensitivity analysis by varying the relative $\sigma$ on all CPU series at our disposal, and reporting the difference with our $\sigma = 0.39$ (90% yield) reference.
<figure><img src="image_6.png" /><figcaption>Fig. 5: Carbon impact across performance (left) or price (right) of CPU. Product ranges are grouped in black lines. Products belonging to the same range, despite having different bin-value, share the same carbon impact with the usual “flat” allocation. Our “tilt” allocation methodology enables a progressive embodied carbon distribution across each CPU series.</figcaption></figure>

<figure><img src="image_7.png" /><figcaption>Fig. 6: Sensitivity analysis for the Gaussian distribution, based on variation of standard deviation σ around the 0.39 value used for our estimations using MIPS (a) and price (b) as allocation factor. The darker regions report a higher density of results for a given variation.</figcaption></figure>

Our results show that the variation is quite contained, below 15%, with a σ spanning from 0.3 to 0.6 (yield of 95% down to 80%) of the bin-value range for each series. Note that the highest deviations are due to the series that have a highly non uniform distribution, for instance, a large central Stock Keeping Unit (SKU), and few outliers (very high and/or low performance). Those types of distributions are highly affected by the variation of yield across the series. For example, in Figure 6 (b), the excursion line on the lower right side is due to a product of AMD Ryzen5 CPUs with only 3 SKUs, a single basic reference having a performance of 6.4k MIPS, and two outliers at 14k and 19k MIPS. This weak variation must be put in perspective with the shift introduced by our models which can offset the carbon footprint by more than 100% for some devices, compared with the original area-based estimations.

These results demonstrate the validity of the “flat yield” hypothesis used in the “tilt” model. Despite the non-realistic nature of the hypothesis, a sensitivity analysis shows that using a Gaussian yield hypothesis in the model does not drastically offset the result, as the resulting variations do not exceed 10%.

Overall, the sensitivity analysis shows a certain robustness against variations of σ. Given the opacity of actual return fig-

ures, the simple “Tilt” allocation model, based on a uniform return assumption, represents an excellent compromise between simplicity and accuracy when no detailed information is available on the binning process.

## B. Allocation metric robustness

To assess the robustness of our allocation principle, a comparison of overall regression metrics ($R^2$ or RMSE) is not relevant. This is because the allocation is primarily designed to preserve the overall mean while correcting for local outliers, and thus does not necessarily improve the global fit to the initial data (i.e., the original $R^2$). Nonetheless, a cross-analysis using different bin-value metrics can expose the sensitivity of our model to the chosen input. We therefore allocated carbon impact using Price as the bin-value metric and then plotted this allocated impact against Performance (MIPS); the reverse analysis was also performed (Figure 7). The result is a high coefficient of determination, such as $R^2 = 0.85$ in both cases. This strong correlation demonstrates that the choice of metric (Price vs. MIPS) does not fundamentally change the resulting allocation. This confirms that our methodology is robust, providing a consistent value-based carbon allocation regardless of whether the value is quantified by an economic proxy or a technical metric.

# V. DISCUSSION

## A. Allocation metrics

We used two different metrics, raw MIPS and introduction price, to perform this allocation on a CPU series.

The introduction price is a comprehensive proxy to summarize the intrinsic value of such a product. In fact, the price of a CPU does not only reflect its raw performance in terms of MIPS, but also a set of additional features, like the presence of integrated GPU, the integration of video or crypto accelerator, its cache size, etc. Indeed, a higher price can be seen as both a signal of the manufacturing complexity and user demand. This joint pressure pushes manufacturers towards always higher performance products, yet with an ever growing environmental toll. It is therefore reasonable to consider the idea of having devices priced in the higher range
<figure><img src="image_8.png" /><figcaption>Fig. 7: Cross-representation of our allocation using MIPS as bin-value plotted against price (Left) and using Price as bin-value plotted against MIPS (Right). The preservation of a strong linear trend ($R^2$ = 0.85) across this cross-comparison demonstrates the robustness of the methodology, as the resulting allocation is consistent regardless of whether an economic (Price) or technical (MIPS) metric is used as the basis for differentiation.</figcaption></figure>

to bear more of the carbon impact. As prices may fluctuate over the lifetime of a given product, the introduction price can be seen as a common reference of bin-value for CPUs.

The use of raw MIPS, defined as the product of core count and frequency, is less straightforward as it is less prone to capture the absolute performance of a CPU. Although this characteristic fails to include other important performance parameters such as the number of instructions per cycles (IPC) [23], it constitutes a good proxy for the processor performance. MIPS Performance alone is not enough to define the grade of a CPU in terms of desirability. However, we discovered in this study that this is a proxy that is able to perform a sufficient classification of devices within a CPU series. This metric can thus also be considered as relevant for carbon allocation.

One way to encompass a wider set of characteristics of a CPU is to use a performance efficiency metric. For instance the MIPS/W estimation can reflect how much a CPU is able to compute with a certain amount of power. This is one characteristic that differs from one component to another. It represents one of the axis along which components are sorted at the end of production line. The TDP is not an interesting parameter by itself for our allocation, as too few discrete values are kept, (45W and 65W for instance) that make too poor discrimination between devices. That is why a composite metric like MIPS/W could become highly relevant. However, although correlation between the release price and raw MIPS is high ($\rho$ = 0.84), it is not case when combining with the TDP, where the correlation becomes much lower ($\rho$ = 0.17). This raises the idea that power efficiency is not as much a concern for the market as computing power is. We thus keep this question for future work.

As a whole, as far as the total embodied emissions of the whole CPU series is preserved, any type of binning-aware allocation leads to the same total carbon footprint. This is mandatory, as it avoids missing some part of the

product manufacturing Global Warming Potential (GWP) or, conversely, exceeding the initial impacts. LCAs are becoming an influential instrument for purchasing, advertising, designing and taking political decisions [24], [25]. When evaluating the impact of a particular product, getting a precise estimation is thus expected. This paper aims to participate to the ongoing rise in the accuracy of LCA methodologies, with the introduction of more comprehensive practices, in particular on carbon footprint.

## B. Limitations

This methodology is not based on direct physical measurement to link price or performance to the carbon impact. Instead it proposes a redistribution of the total carbon of one series among its different products. A first consequence is that low end devices can receive a fairly low amount of carbon for their production. For instance a CPU with many deactivated cores and a lower frequency can be estimated at few 100s g of $CO_2e$. This order of magnitude may seem surprising compared to existing data. One way to understand this result is to consider that those kinds of devices have very poor performance and features. Without a comprehensive co-production scheme, these co-products would have been directly discarded, in turn diminishing the global yield of the product series as less functional devices would have been produced, and increasing the embodied carbon per device. Tagging those low performance devices as low-cost products is indeed a way to output as many functional CPUs from the production line as possible, thus lowering the overall embodied carbon impact of the series. On this sense it is rational to consider their contribution to the carbon footprint as much lower than average.

The proposed binning-aware allocation method raises a subsequent issue about the complexity of this allocation. Classic estimation methodologies are fairly simple, as they require only a few physical parameters to determine the carbon footprint of a CPU. As we move towards a methodology that encompasses the series production as a whole, more information is needed, and it can be discouraging when the full LCA of a large and complex system has to be done. Fortunately, we were able to perform our study by relying on extensive databases available online [4], [26]. Moreover, even though the CPU industry is very prolific, there is not an infinite number of CPUs, and this estimation must only be done once to be available to the community. In this regard, we make our carbon estimation available for the devices we worked on, this represents around 1400 devices. Regarding new upcoming products, we also publish the code [27] to perform the allocation so that databases can be completed with updated information.

## VI. CONCLUSION

This work has questioned the relevance of conventional area-based carbon footprint models for processors, which assign a uniform environmental impact to all products derived from a single silicon design. By re-framing the output of the binning process as a set of distinct co-products, we
introduced a novel allocation framework that distributes the shared manufacturing impact more fairly. Leveraging both economic (launch price) and physical (raw performance) characteristics, our model demonstrates a significant redistribution of the environmental burden, and reduced carbon footprint variations w.r.t price and performance.

The significance of this methodology extends beyond CPUs. We have established a generalizable principle for any manufacturing process where binning is central to economic viability. This framework is directly applicable to other digital ICs, such as GPUs or FPGAs. For practitioners, the model requires only standard specifications (e.g., core count and frequency), facilitating its integration into LCA databases to enable fairer comparisons and guide sustainable hardware procurement.

Future research will aim to refine this model by incorporating more complex manufacturing realities. The rise of chiplet-based designs, for instance, presents a compelling new frontier. Allocating impact in these heterogeneous systems—where multiple dies from potentially different wafers or even process nodes are integrated into a single package—will require an extension of this co-product framework to handle multiple, distinct sources of manufacturing impacts.

## ACKNOWLEDGMENT

This study is funded by the France2030 ESOS Project - Electronics: Sustainable, Open and Sovereign, operated by French ANR (Agence Nationale de la Recherche).

## REFERENCES

[1] S. Luccioni, Y. Jernite, and E. Strubell, "Power hungry processing: Watts driving the cost of ai deployment?" in *Proceedings of the 2024 ACM Conference on Fairness, Accountability, and Transparency*, ser. FAccT '24. New York, NY, USA: Association for Computing Machinery, 2024, p. 85–99. [Online]. Available: https://doi.org/10.1145/3630106.3658542

[2] D. Kline, N. Parshook, X. Ge, E. Brunvand, R. Melhem, P. K. Chrysanthis, and A. K. Jones, "GreenChip: A tool for evaluating holistic sustainability of modern computing systems," *Sustainable Computing: Informatics and Systems*, vol. 22, pp. 322–332, Jun. 2019. [Online]. Available: https://www.sciencedirect.com/science/article/pii/S2210537917300823

[3] U. Gupta, Y. G. Kim, S. Lee, J. Tse, H.-H. S. Lee, G.-Y. Wei, D. Brooks, and C.-J. Wu, "Chasing Carbon: The Elusive Environmental Footprint of Computing," Oct. 2020, arXiv:2011.02839 [cs]. [Online]. Available: http://arxiv.org/abs/2011.02839

[4] "TechPowerUp — cpu specs database," https://www.techpowerup.com/cpu-specs/, 2025, [Accessed 20-06-2025].

[5] J. Malmodin and N. Lövehagen, "A Methodology for Simplified LCAs of Electronic Products," in *2024 Electronics Goes Green 2024+ (EGG)*, Jun. 2024, pp. 1–12. [Online]. Available: https://ieeexplore.ieee.org/document/10631258

[6] U. Gupta, M. Elgamal, G. Hills, G.-Y. Wei, H.-H. S. Lee, D. Brooks, and C.-J. Wu, "ACT: designing sustainable computer systems with an architectural carbon modeling tool," in *Proceedings of the 49th Annual International Symposium on Computer Architecture*, ser. ISCA '22. New York, NY, USA: Association for Computing Machinery, Jun. 2022, pp. 784–799. [Online]. Available: https://doi.org/10.1145/3470496.3527408

[7] X. Chen, L. Han, A. Bhagavathula, and U. Gupta, "CarbonClarity: Understanding and Addressing Uncertainty in Embodied Carbon for Sustainable Computing," Jul. 2025, arXiv:2507.01145 [cs]. [Online]. Available: http://arxiv.org/abs/2507.01145

[8] T. Pirson, T. P. Delhaye, A. G. Pip, G. Le Brun, J.-P. Raskin, and D. Bol, "The Environmental Footprint of IC Production: Review, Analysis, and Lessons From Historical Trends," *IEEE Transactions on Semiconductor Manufacturing*, vol. 36, no. 1, pp. 56–67, Feb. 2023. [Online]. Available: https://ieeexplore.ieee.org/document/9979766/

[9] R. Hischier, M. Classen, M. Lehmann, and W. Scharnhorst, "Life Cycle Inventories of Electric and Electronic Equipment: Production, Use and Disposal (Ecoinvent)," 2007, v2.0.

[10] Y. Yang and R. Heijungs, "On the use of different models for any consequential life cycle assessment," *The International Journal of Life Cycle Assessment*, vol. 23, no. 4, pp. 751–758, 2018.

[11] S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De, "Parameter variations and impact on circuits and microarchitecture," in *Proceedings of the 40th annual Design Automation Conference*, 2003, pp. 338–342.

[12] A. Datta, S. Bhunia, J. H. Choi, S. Mukhopadhyay, and K. Roy, "Speed binning aware design methodology to improve profit under parameter variations," in *Asia and South Pacific Conference on Design Automation*, 2006., Jan. 2006, pp. 6 pp., iSSN: 2153-697X. [Online]. Available: https://ieeexplore.ieee.org/document/1594770

[13] D. Cheng and S. K. Gupta, "Ppb: Partially-working processors binning for maximizing wafer utilization," in *2015 IEEE 33rd VLSI Test Symposium (VTS)*. IEEE, 2015, pp. 1–6.

[14] M. Omaña, M. Padovani, K. Veliu, C. Metra, J. Alt, and R. Galivanche, "New Approaches for Power Binning of High Performance Microprocessors," *IEEE Transactions on Computers*, vol. 66, no. 7, pp. 1159–1171, Jul. 2017. [Online]. Available: https://ieeexplore.ieee.org/abstract/document/7822988

[15] I. O. for Standardization, "ISO 14040:2006." [Online]. Available: https://www.iso.org/standard/37456.html

[16] W. Ijassi, H. Ben Rejeb, and P. Zwolinski, "Environmental impact evaluation of co-products: decision-aid tool for allocation in LCA," *Int J Life Cycle Assess*, vol. 26, no. 11, pp. 2199–2214, Nov. 2021. [Online]. Available: https://doi.org/10.1007/s11367-021-01984-0

[17] O. Jolliet, M. Saadé, and P. Crettaz, *Analyse du cycle de vie: comprendre et réaliser un écobilan*. EPFL Press, 2010, vol. 23.

[18] G. Roussilhe. (2025, jul) How to use Computing Power Faster: On the weird Economics of Semiconductors and GenAI'. [Online]. Available: https://gauthierroussilhe.com/en/articles/how-to-use-computing-power-faster

[19] "Methodology - imec.netzero." [Online]. Available: https://netzero.imec-int.com/methodology

[20] "IRDS™ 2024: Yield Enhancement - IEEE IRDS™." [Online]. Available: https://irds.ieee.org/editions/2024/irds%2E%84%A2-2024-yield-enhancement

[21] K. Bowman, S. Duvall, and J. Meindl, "Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration," *IEEE Journal of Solid-State Circuits*, vol. 37, no. 2, pp. 183–190, Feb. 2002. [Online]. Available: https://ieeexplore.ieee.org/document/982424

[22] M. Orshansky, L. Milor, P. Chen, K. Keutzer, and C. Hu, "Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits," *IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, vol. 21, no. 5, pp. 544–553, May 2002. [Online]. Available: https://ieeexplore.ieee.org/document/998626

[23] I. Ratković, N. Bežanić, O. S. Ünsal, A. Cristal, and V. Milutinović, "An overview of architecture-level power- and energy-efficient design techniques," *Advances in computers*, vol. 98, pp. 1–57, 2015.

[24] M. D. Bovea and V. Pérez-Belis, "A taxonomy of ecodesign tools for integrating environmental requirements into the product design process," *Journal of Cleaner Production*, vol. 20, no. 1, pp. 61–71, Jan. 2012. [Online]. Available: https://www.sciencedirect.com/science/article/pii/S0959652611002538

[25] Y. Dong, S. Miraglia, S. Manzo, S. Georgiadis, H. J. D. Sørup, E. Boriani, T. Hald, S. Thöns, and M. Z. Hauschild, "Environmental sustainable decision making– The need and obstacles for integration of LCA into decision analysis," *Environmental Science & Policy*, vol. 87, pp. 33–44, Sep. 2018. [Online]. Available: https://www.sciencedirect.com/science/article/pii/S1462901118302776

[26] "Wikichip, semiconductor & computer engineering," https://wikichip.org/, 2026, [Accessed 15-01-2026].

[27] Author, "Python source code used to generate figures and carbon estimations for cpus using allocation," https://gitlab.insanrennes.fr/esos/cpuallocation, 2025, accessed: 2025-10-31.