# A Method for Detecting the Start of Delamination at the Corners of Solder Joint in a 3D PCB Power Electronic Assembly of SiC MOSFETs

Souhila Bouzerd, Laurent Dupont

► To cite this version:

Souhila Bouzerd, Laurent Dupont. A Method for Detecting the Start of Delamination at the Corners of Solder Joint in a 3D PCB Power Electronic Assembly of SiC MOSFETs. The 26th European Conference on Power Electronics and Applications, GDR SEEDS France & EPE Association, Mar 2025, Paris, France. 10.34746/epe2025-0109 . hal-05095921

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# A Method for Detecting the Start of Delamination at the Corners of Solder Joint in a 3D PCB Power Electronic Assembly of SiC MOSFETs

Souhila BOUZERD¹, Laurent DUPONT¹

1 Univ. Gustave Eiffel, Univ. Paris-Saclay, ENS Paris-Saclay, CNRS, SATIE, Versailles, France

Tel. : +33 7 49 80 52 85

E-Mail : Souhila BOUZERD souhila.bouzerd@univ-eiffel.fr

URL: https://satie.ens-paris-saclay.fr

## Acknowledgments

The authors would like to thank the French National Research Agency (ANR - DESTINI - ANR-21-CE05-0037-01) for funding this research, as well as Mr. Philippe Lassere from Deep-Concept for his support in the development of the prototypes and the 3DPhi platform in Toulouse

## Keywords

«Packaging», «Failure modes», «Degradation», «Aging», «Damage indicator».

## Abstract

The article discusses a method for evaluating the delamination initiation at solder joint corners in a 3D power electronic assembly of SiC MOSFET transistors integrated into a PCB substrate to design a half bridge. This assembly leads to soldering two metallic materials and addresses the integration of small active chips with larger heat-sinks. This technological development is part of future robustness evaluation of the new assembly model for wide band Gap components. This assembly consists of metallic base-plate corresponding to the heat-sink soldered on the copper foil of a PCB substrate. Conventional methods fail to detect delamination initiation effectively due to the optimized commutation cell design. Finite element simulations are carried out to assess the sensitivity in comparison with another method. Then, prototypes with controlled delamination rate are developed to consolidate the results. The first conclusion demonstrates the interest of that electrical method which is more sensitive to detect the low delimitation rates comparing to thermal method generally used.

## Introduction

Global efforts to reduce CO₂ emissions, driven by growing concerns about the effects of greenhouse gases on the climate, have been a major factor in the rise of electrification. More than 70% of electrical energy will use static converters by 2050 [1]. The challenges for these future converters are partly related to improving semiconductor packaging [2], [3]. New power modules are designed to reduce electrical and electromagnetic disturbances to be used with high-speed switching devices [4]. This can only be achieved by using wide-bandgap components basing on a comparison of isolation converters [5]. However, these semiconductors require optimized packaging. Consequently, reducing the size of the switching cell is essential to limit the adverse effects of parasitic elements in the design (such as overvoltages, electrical oscillations, current distribution...) which are amplified by the high performance of wide bandgap semiconductors. Moreover, a 3D packaging solution with double-sided water cooling has been proposed to improve cooling efficiency [6]. Nevertheless, this cooling method adds weight, complexity, cost, and overall inefficiency to the system. Thus, it is beneficial to enhance module cooling while maintaining a lighter weight to satisfy the demands of electric mobility, where weight is a critical factor [7]. Air cooling has been suggested as a solution, but to achieve an adequate thermal performance, the arrangement of power components must be optimized. TAPIR technology (Compact and Modular Power Modules with Integrated Cooling) [8] introduces
<figure><img src="image_2.png" /><figcaption>Figure 1: Presentation of the 3D integration model TAPIR [8]</figcaption></figure>

a 3D integration approach with a minimal number of thermal interfaces. This approach incorporates SiC MOSFET transistors 1200 V, 89 A (5 mm × 5 mm) into a dedicated PCB substrate that includes the active devices, copper layers, epoxy resin, and glass fibers. The cooling configuration involves air-cooled heat-sinks mounted on both sides of the technological PCB substrate structure for power electronic double-sided cooling, as shown in figure 1. These heat-sinks are soldered onto each side of the PCB substrate using a solder joint made from a SnAgCu (SAC305) alloy. Also, these heat-sinks are positioned at the same electrical potentials as both top and bottom faces of the active components embedded within the PCB substrate (Figure 1). Air cooling necessitates a large heat exchange surface due to its lower heat transfer coefficient compared to water cooling. This requirement results in substantial dimensions for the heat exchanger, but these heat-sinks are attached to a PCB substrate composed of epoxy and glass fibers. However, there are differences in the coefficients of thermal expansion (CTE) and in the behaviors of the materials used. Where, the copper CTE is 16.5 ppm/K, the aluminum CTE is 23 ppm/K, and the substrate CTE in the (X-Y) plane ranges between 10 and 20 ppm/K, relatively low and close to that of conductors like copper. Additionally, a common issue with soldering technology is the thickness variation between the center and the edges of the solder joint, particularly with larger geometric dimensions. This can cause one corner of the solder joint to support higher stresses, increasing the probability of delamination initiation at that corner [9]. The failure mode examined is delamination caused by solder joint cracking due to thermal cycling [10]. Figure 2 illustrates typical evolution of delamination (b),

comparing the solder initial joint (a). Delamination, highlighted by a red circle, must be detected to assess damage thresholds and the behavior of different technologies before cycling and after 8000 thermal cycles. Consequently, it is essential to develop indicators for non-destructive detection and accurate measurement of delamination initiation and progression at the solder joint corners. The literature outlines several traditional methods for detecting solder joint delamination in power modules. For instance, thermal performance measurement methods [11] are not suitable for the specific assembly under study due to the disproportionate surface area and the reduced distance between the active component and the heat-sink solder joint. This method demonstrates sufficient sensitivity only when the heat flux density is high enough in the thermal path. Therefore, it can be modified by damage, enabling the detection of degradation. Similarly, electrical capacitance measurement [12] is also ineffective for this assembly because of the continuous electrical potential across the heat-sink, solder joint, and substrate metallization of the PCB. Moreover, alternative techniques such as phase-lock thermography[13], X-ray tomography [14], reflectometry technology [15], and acoustic microscopy [12] are not applicable in this case, as continuous damage monitoring during scheduled tests is impractical. Finally, a discussion details the results, leading to a conclusion and exploring future research directions. This article introduces a preliminary approach for detecting the initiation of solder joint delamination. A preliminary electrical measurement method has achieved one percent sensitivity in detecting delamination, providing robust basis for comparing various technological design options.
<figure><img src="image_3.png" /><figcaption>Figure 2: Geometries and boundary conditions of the FEM showing current injection and electrical potential measurements positions.</figcaption></figure>

<figure><img src="image_4.png" /><figcaption>Figure 3: Means of ultrasonic imaging (USM) image of the substrate-to-baseplate delamination (a) before cycling (b) after 8000 thermal cycles [10]. This article proposes a preliminary solution for detecting the initiation of solder joint delamination. An initial electrical measurement method has achieved approximately one percent sensitivity for detecting delamination, enabling a detailed comparison of different technological options. The article first outlines the numerical model linked to an experimental study conducted on specially designed test prototypes. Then, a comparison between the thermal performance measurement and the electrical measurement method is presented. Finally, a discussion details the results, leading to a conclusion and exploring future research directions.</figcaption></figure>

# 1. Numerical analysis

A numerical study is used to identify the main parameters that affect the sensitivity of methods for detecting the delamination initiation at one or more corners of the solder joint. A finite element simulation was carried out using COMSOL Multiphysics software. In this section, the numerical model on which the calculations are based is presented. Then, the two methods, thermal and electrical, are introduced. Finally, the results of a comparison between the two methods are demonstrated.

## 1.1 Numerical model

The finite element model (FEM) studied is a 3D geometry comprising three parts (Fig. 3). The PCB substrate metallization (35 mm × 35 mm) with 105 µm thick copper on a PCB substrate, the base-plate of the heat-sink (17 mm × 17 mm) with copper with a thickness of 3 mm. The third part is the solder joint (17 mm × 17 mm) using Sn-3.0Ag-0.5Cu (SAC305) alloy with a thickness of 100 µm and an electrical resistivity of 1.04×10⁻⁶ Ωm [16]. The active chip is represented by a (5 mm × 5 mm) area on the PCB substrate, simulating the upper metallization of the MOSFET that dissipates heat equivalent to the active part of the MOSFET. An experimental campaign was conducted to verify the resistivity of the copper metallization of the PCB substrate, which was found to be 1.40×10⁻⁸ Ωm [17]. The numerical model is configured to align with this experimentally measured value.

## 1.2 Thermal resistivity method

Thermal resistance, expressed in °C/W or K/W, is the resistance that a device offers to the dissipation of heat generated by components power loss. Thermal resistance is calculated by the equation 1[18].

$$R_{th} = \frac{\Delta T}{P} = \frac{T_j - T_a}{P} \quad (1)$$

Where; parameters P, Tj and Ta are respectively the dissipated power (W), the junction temperature and the temperature of the backside of the substrate in °C.

In our model, a condition of 30 W/cm² is applied to the surface representing the active part density of power dissipation. Then, average temperatures Tj and Ta are calculated from the surface
representing the active chip and the upper surface of the base-plate of the heat-sink respectively. These values are used in order to calculate the thermal resistance using equation

## 1.3 Electrical method

This method involves injecting a current of 100 A at the corner of the PCB substrate metallization on the same side as corner designed A of the solder joint. The injection ground Mm is applied to the base-plate of the heat-sink. As illustrated in Figure 3 the electrical potential evaluations VA are performed on the PCB substrate metallization near corner A of the solder joint, while the measurement ground Mm is applied to the base-plate of the heat-sink. The reduced dimensions of the substrate metallization, resulting in shorter distance between the current injection point and the electrical potential measurement positions, significantly increase the sensitivity of the electrical potential measurements to their positions. Simulations were carried out for models with uniform thickness solder joint and no degradation. Additional simulations were performed for cases with delamination imposed at one or more corners of the solder joint with different rates presented in Table 1. This delamination rate imposed is represented by a material gap in the model. The delamination is represented by the red circle in Figure 3. A controlled mesh was employed for this study to refine the simulation results. Specifically, an adaptive triangular mesh is used on the edges of the solder joint to enhance the simulation accuracy in the delamination area, which is distributed throughout the volume of the geometry. Calculation time and measurement robustness values are used to set the boundaries of the controlled mesh.

<table><caption>Table 1: Different delamination rates and their distribution at solder joint corners.</caption><thead><tr><th rowspan="2">Case number</th><th colspan="4">Delamination rate<br>at solder joint corner (%)</th></tr><tr><th>A</th><th>B</th><th>D</th><th>Total</th></tr></thead><tbody><tr><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td></tr><tr><td>2</td><td>1</td><td>0</td><td>0</td><td>1</td></tr><tr><td>3</td><td>3</td><td>0</td><td>0</td><td>3</td></tr><tr><td>4</td><td>5</td><td>0</td><td>0</td><td>5</td></tr><tr><td>5</td><td>3</td><td>1</td><td>1</td><td>5</td></tr><tr><td>6</td><td>1</td><td>3</td><td>1</td><td>5</td></tr><tr><td>7</td><td>1</td><td>1</td><td>3</td><td>5</td></tr></tbody></table>

The evaluated values of the electrical potential are analyzed to evaluate the sensitivity of the method and also to assess a delamination indicator

relative to the delamination rates imposed on one or more corners of the solder joint. The delamination indicator is calculated using the following equation describe for the corner A:

$$ \Delta VA = \frac{VA_D - VA_0}{VA_D} \times 100 \quad (2) $$

Where ΔVA (%) is the delamination indicator, VA_D (V) is the electrical potential of the delaminated prototype, and VA_0 (V) is the electrical potential of the non-delaminated prototype.

## 1.4 Numerical results

Simulations were performed on the numerical model with a copper PCB substrate metallization thickness of 105 µm. The results of the simulations indicate sensitivity to the delamination rates imposed on one or more corners of the solder joint. Additional simulations were conducted for all the cases illustrated in Table 1 to study the effect of the delamination rate on the delamination indicator ΔVA. The reference for calculating the delamination indicator is the electrical potential on the prototype without imposed delamination. The electrical potential VA on the reference prototype is 4.05 mV.

<figure><img src="image_5.png" /><figcaption>Figure 4: Comparison of the sensitivity rates of the two methods: electrical and thermal measurements.</figcaption></figure>

The simulation results presented in the figure 4 compare the two methods, the thermal resistance measurements method and the electrical measurements method. This comparison is based on the numerical model described in the previous section, with different delamination rates imposed on corner A of the solder joint. These results demonstrate that the electrical measurements method exhibits greater sensitivity to low delamination rates of the solder joint at corner A. The thermal resistance measurement method offers less sensitivity to the lowest rates
of the delamination but better sensitivity starting
from a delamination rate of more than 45%. This
makes the method unsuitable for detecting the
initiation of delamination, comparing with the
threshold level of 20% of the criteria of a damage
evaluation in aging campaigns of power
electronic devices. To achieve sensitivity to
higher delamination rates using the electrical
method, additional values were considered near
corner B. These values demonstrate also greater
sensitivity compared to the thermal resistance
method.

## 2. Electrical method evaluation

After obtaining encouraging simulation results,
prototypes were developed for experimental
testing. First, a presentation of the prototypes and
their characterization is provided. Then, an
experimental study is conducted to demonstrate
the method's sensitivity to the imposed
delamination rate and the distribution of the
delamination rate across the corners of the solder
joint.

### 2.1 Test prototype definition

For this study, simplified prototypes were
developed to validate the promising simulation
results. These prototypes feature a PCB substrate
(35 mm x 35 mm) made of copper layer thickness
of 105 µm, epoxy, and glass fibers. Additionally,
they include a copper block (17 mm x 17 mm)
with a 3 mm thickness, representing the base-
plate of the heat-sink, assembled with a SnAgCu
solder joint (SAC305) with a thickness of 100
µm. The PCB substrate is metallized with a gold
finish to enhance wettability and minimize voids
in the solder joint. Furthermore, the PCB
substrate lacks an insulating coating to allow for
current injections and electrical potential
measurements. The copper block, serving as the
base-plate of the heat-sink, is nickel-plated to
prevent copper oxidation before soldering onto
the PCB substrates. Controlled solder joint
delamination is done by applying a solder-stop in
the targeted corner of the solder joint, shaped to
control the delamination rate. Even if the solder
covers the solder-stop, no electrical contact
occurs between the PCB substrate metallization
and the base-plate of the heat-sink at the
designated delamination corners, ensuring
robustness for the imposed degradation design.
Even if the solder covers the upside of the solder-
stop, it nevertheless electrically represents a
failure propagation between the base-plate of the
heat-sink and the PCB substrate metallization.

This represents the delamination initiation that we
want to detect using the electrical method. Figure
5 depicts the prototypes with delamination
imposed on one and three corners before
soldering.

<figure><img src="image_6.png" /><figcaption>Figure 5: Dedicated PCB substrate before the base-plate of the heat-sink soldering.</figcaption></figure>

The condition of the solder joint is evaluated
through Scanning Acoustic Microscopy (SAM),
as shown in Figure 6. The acoustic scan is
performed to take in consideration the presence of
voids in the solder joint and their location. Also,
established in order to explain the gap between
the values calculated in simulation and the values
measured experimentally.

<figure><img src="image_7.png" /><figcaption>Figure 6: Scanning Acoustic Microscopy of prototypes with imposed delamination.</figcaption></figure>

### 2.2 Experimental campaigns

Following the simulation results, an experimental
study is conducted to validate these numerical
results. A test bench is configured for current
injection and electrical potential measurements.
To enhance the signal-to-noise ratio, a high
current injection is used to assess the sensitivity
of the electrical method. Given the small size of
the prototypes, the accuracy of electrical potential
measurements is highly dependent on the
measurement location. Therefore, probes are
employed to improve measurement location
precision. These probes can only handle currents
up to 3 A in DC mode. To accommodate a DC
current of 100 A and mitigate the effects of self-
heating, the test bench is designed to allow pulsed
<figure><img src="image_8.png" /><figcaption>Figure 7: Panoramic view of the experimental test bench.</figcaption></figure>

current injection of approximately 100 A for 300 µs. Electrical measurements are conducted using the HBM GEN3i acquisition unit, which provides a sampling rate of 2 MS/s and an ADC resolution of 18 bits. Figure 7 illustrates a panoramic view of the test bench.

A series of electrical potential measurements were conducted on all prototypes. These prototypes include all the cases listed in Table 2. The prototypes have a metallization thickness of 105 µm on the PCB substrate. Based on the measurements taken, the delamination indicator is calculated using Equation 2. A series of electrical measurements were conducted on all prototypes. These prototypes include all the cases listed in Table 2.

## 2.3 Method's sensitivity evaluation

The electrical method demonstrated high sensitivity to different delamination rates as well as to their location. This method showed greater sensitivity to the delamination rates imposed on corner A of the solder joint, which is facing the current injection point. Also, this method is sensitive to the delamination rates imposed on the corners adjacent corners B and D of the solder joint to corner A close to the current injection location. It is important to note that only a single current injection is performed in the corner which is facing the corner A and only one potential measurement is taken at corner A (VA). The table 2 resume the all the cases with the delamination indicator ΔVA (%), for simulation and experimental results. A comparison between the cases presented in Tables 1 and 2 is made to demonstrate the sensitivity of the method to the distribution of the delamination rate on the solder joint. For example, cases 3 (3% delamination rate

was imposed only on corner A), 4 (5% delamination rate was imposed only on corner A), and 5 (5% delamination rate was distributer on three corners A, B et D) were compared. First, we compare case 4 to case 5. The measured value VA is higher in case 4 compared to case 5.

<table><caption>Table 2: Delamination indicator ΔVA for all prototypes.</caption><thead><tr><th rowspan="2">Case number</th><th colspan="4">Delamination rate at solder joint corner (%)</th><th colspan="2">Delamination indicator ΔVA (%)</th></tr><tr><th>A</th><th>B</th><th>D</th><th>Total</th><th>Simu</th><th>Exp</th></tr></thead><tbody><tr><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr><tr><td>2</td><td>1</td><td>0</td><td>0</td><td>1</td><td>14.56</td><td>15.05</td></tr><tr><td>3</td><td>3</td><td>0</td><td>0</td><td>3</td><td>28.12</td><td>37.54</td></tr><tr><td>4</td><td>5</td><td>0</td><td>0</td><td>5</td><td>37.21</td><td>53.73</td></tr><tr><td>5</td><td>3</td><td>1</td><td>1</td><td>5</td><td>28.21</td><td>44.07</td></tr><tr><td>6</td><td>1</td><td>3</td><td>1</td><td>5</td><td>14.68</td><td>26.98</td></tr><tr><td>7</td><td>1</td><td>1</td><td>3</td><td>5</td><td>14.67</td><td>19.01</td></tr></tbody></table>

This is due to the fact that in case 4, the entire delamination rate is localized at corner A close to the current injection location, condition that conduct to the greatest sensitivity. However, the measured value VA in case 5 remains higher than that measured in case 3. This demonstrates that, although there is greater sensitivity at corner A, this method is also sensitive to the delamination rates imposed at corners B and D of the solder joint.

## 2.4 Comparison between simulation and experimental results

A comparison was made between the simulation and experimental results. All the cases presented in Tables 1 and 2 are compared and presented in Figure 8. Where Figure 8 shows the variation of the delamination indicator as a function of the delamination (Delam) rate imposed at corners A,
B and D for both the experimental campaigns and the simulations.

<figure><img src="image_9.png" /><figcaption>**Figure 8: Comparison between simulation (Simu) and experimental (Exp) results.**</figcaption></figure>

In Figure 8, the simulation results are represented by the gray bar, while the experimental results are represented by the multicolored bar. Post-it notes are added in Figure 8 to assign each label to its corresponding number cases presented in the table 2. The colored circle extending beyond the gray one represents the difference between the simulation and experimental results. This difference varies from one prototype to another depending on its soldering condition and ranges from 1% to around 15%. It demonstrates a good correlation for using numerical model for evaluations of most complicated configurations and to propose an optimization of the method. The main reason for the differences can be addressed to the very sensitive position of the probes in the experimental measurements. This is due to the small dimensions of the available metallization, as seen in the prototypes and the solder joint, make the electrical potential measurements highly sensitive to positioning due to the distribution of current lines in the thin copper layer of the PCB, which is very close to the injection point.

## Conclusion

This study introduces an electrical method for detecting the initiation of delamination in a solder joint within a metal-to-metal assembly in power electronics for WGB components. This assembly represents a more and more generalized situation where an active wide-bandgap chip is integrated into a PCB substrate. The chip is small compared to the size of the heat-sinks, and these components are set at the same electrical potential. A finite element simulation was conducted to study the sensitivity of the method. A comparison between the thermal method and

the electrical method was made. The results of this comparison showed that, at 20% delamination imposed on a single corner A, the thermal method shows no sensitivity, while the electrical method demonstrates a sensitivity of 50%. The comparison was primarily focused on the 20% threshold since it represents the historical degradation threshold that define a limit of damage status for an evaluation of the lifetime expectancy during accelerated ageing test of power electronics module assembly. After the encouraging simulation results, prototypes were developed for testing. The experimental results obtained were compared to the simulation results. The comparison revealed a correlation between the two sets of results. The experimental results show that the method is sensitive to the delamination rate imposed at corner A of the solder joint, which is facing the current injection point. The results also showed that the method is sensitive to the delamination rates imposed at corners B and D, even with a single current injection and a single potential measurement closest to corner A. Both the experimental and simulation results are satisfactory, demonstrating the method's sensitivity to low delamination rates as small as one percent. Despite promising outcomes, several challenges persist. Furthermore, it is essential to use it for accelerated aging to accurately distinguish between various integration technologies within the DESTINI research project. The next steps will involve enhancing the sensitivity assessment at corner A as well as at the other corners, C, B and D. Additionally, it will be important to evaluate the robustness of the proposed solution by considering different delamination rates and locations, as well as optimizing geometries "Design to Sensors". Another critical step will be conducting a study to integrate this solution into the PCB substrate, enabling real-time degradation detection. Also, an alternating current injection will be investigated to take advantage of skin effects, aiming to enhance the sensitivity of the method. Finally, the method will be applied to other electrical excitation modes compatible with power electronics technologies (e.g., sintered or intermetallic diffusion joints, electrical or mechanical connections) characterized by a form factor where thickness is minimal relative to surface area.
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