# Design of a Hybrid ANPC Three Level Inverter for High Speed Bearingless Permanent Magnet Synchronous Machines

Maximilian Weigelt, Fabian Lorenz, Ralf Werner

► To cite this version:

Maximilian Weigelt, Fabian Lorenz, Ralf Werner. Design of a Hybrid ANPC Three Level Inverter for High Speed Bearingless Permanent Magnet Synchronous Machines. The 26th European Conference on Power Electronics and Applications, GDR SEEDS France & EPE Association, Mar 2025, Paris, France. 10.34746/epe2025-0100. hal-05088976

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# Design of a Hybrid ANPC Three Level Inverter for High Speed Bearingless Permanent Magnet Synchronous Machines

Maximilian Weigelt, Fabian Lorenz, Ralf Werner

Chemnitz University of Technology, 09126 Chemnitz, Germany

## Keywords

«ANPC Three Level Inverter» «Bearingless Permanent Magnet Synchronous Drive», «Multi Level Inverter», « High speed drive», «Bearingless drive».

## Abstract

This paper presents an experimental validated Hybrid ANPC Three Level Inverter for High Speed Bearingless Motors. The design process and implementation of the hybrid ANPC inverter system considers the requirements for power electronics set by the Bearingless PMSM.

## Introduction

Bearingless permanent magnet synchronous machines (BPMSM) are typically used in centrifugal machines, turbomolecular pumps and turbo compressors. These applications often require speeds in the region of 100.000 rpm. Due to the low number of turns of the stator winding, the resulting inductance is typically very low. The use of conventional two-level inverter technology with medium switching frequency (6-20 kHz) leads to very high current ripples. This has a negative effect on the stability range of the control system and the operating behaviour of the drive and radial suspension unit of the BPMSM. A stable behaviour of the radial position control and the speed control over the entire speed range is required for the high performance operation of the BPMSM. This results in the need for a very fast and robust field oriented current control. The use of highly dynamic inverter systems with low latency times is required to realize fast current controls. In order to achieve stable control behaviour of the BPMSM over the entire speed range, switching frequencies in the range of 50 kHz - 100 kHz are usually required when using two-level inverter topology. Fast-switching

power electronic components such as SiC MOSFETs or GaN HEMTs are used to provide the high switching frequencies. The resulting steep switching edges lead to a high dv/dt, which causes common mode interference that couples into the position and current sensor signals due to parasitic capacitances. This results in a reduction in the stability range of the PID radial position control, which means that restrictions in the possible bearing stiffness must be accepted [8]. To master these disadvantages and challenges, the objective is to investigate the operating behaviour of the BPMSM and the stability range of the radial position control with three-level inverter supply. Specifically, this paper initially pursues the goal of designing and implementing a Si/SiC hybrid Active Neutral Point Clamped (ANPC) inverter system, as this topology enables the introduction of a third voltage level with the same number of fast-switching power electronic components with regard to the previously used two-level topology. Simultaneously, the design process and implementation of the hybrid ANPC inverter system considers the requirements for power electronic components set by the BPMSM. The boundary condition of a drive-related and function-integrated inverter system should be taken into account in order to be able to neglect the influence of the motor cable. With the help of the hybrid ANPC converter system presented, the investigation of the operating behaviour of the BPMSM and stability range of the radial position control with two-level and three-level inverter supply with the same inverter system are possible. Taking these aspects into account, further three-level modulation and control methods can be implemented with this inverter system and investigated in conjunction with the BPMSM. To be able to derive the specific requirements of the Bearingless Permanent Magnet Synchronous Machine for the inverter system, the principle of the BPMSM drive system is considered below.
## Bearingless PMSM drive system

The unique feature of the bearingless permanent magnet synchronous machine is that the electromagnetic assemblies of the drive and radial bearing units are integrated in a common stator. In contrast to separate magnetic bearing systems, this topology allows comparatively shorter axial lengths, which is an important criterion for high-speed applications due to their rotor dynamics. The basic structure of the BPMSM prototype is shown in Fig. 1. For the basic structure of the BPMSM prototype, a twin arrangement was specified. This arrangement offers the advantage that the total motor power is divided between two bearingless motors, which together provide the entire torque and provide two radial suspension points. It follows that the magnetically active part of the rotor shaft is also divided into two sections.

<figure><img src="image_2.png" /><figcaption>Fig. 1: Structure of the BPMSM [2]</figcaption></figure>

To compensate for possible axial disturbance forces, an active magnetic thrust bearing was arranged in the center of the shaft. The design specification of the BPMSM is summarized in Table I [2].

<table><caption>Table I: BPMSM design specification</caption><thead><tr><td>Parameter</td><td>Specification</td></tr></thead><tbody><tr><td>mech. power</td><td>10 kW</td></tr><tr><td>speed</td><td>100.000 rpm</td></tr><tr><td>torque</td><td>1 Nm</td></tr><tr><td>phase voltage</td><td>230 V<sub>rms</sub></td></tr><tr><td>phase current</td><td>25 A<sub>rms</sub></td></tr></tbody></table>

In contrast to a classic permanent magnet synchronous machine (PMSM), which contains one three phase winding, the BPMSM stator has two separate three phase windings. The two three phase windings were composed of a suspension and motor winding which are installed in a 12 slot stator. The stator carries a 2-pole suspension winding on the outer layer and a 4-pole drive winding on the inner layer. The poles between the drive winding and the suspension windings meet the constraint $p_m=p_s \pm 1$, which implies that the suspension force and torque can be controlled and adjusted independently [1]. The drive winding and the suspension winding are specified for the same rated voltage and current, so the same inverter system can be used for operation. For a four-pole rotor the high speed of 100.000 rpm requires high electrical fundamental frequencies up to 3,3 kHz. Due to the four three-phase stator windings, four three-phase inverters are required to operate the BPMSM. The control diagram of one drive and suspension unit is shown in Fig. 2.

<figure><img src="image_3.png" /><figcaption>Fig. 2: Control diagram of one drive and suspension unit</figcaption></figure>

The drive and suspension winding are each fed by a separate inverter. The phase currents of the two winding systems are field-oriented controlled using PI controllers which provide the desired reference voltage vector to be pulsed by the inverter. A speed controller is superimposed on the current controller of the drive unit, which provides the torque required to reach the setpoint speed. Two PID controllers are superimposed on the current controller of the suspension unit to control the radial position in the x- and y-directions. These output a force in the x- and y-direction that are necessary to keep the rotor in the desired radial position.
# Three level hybrid ANPC Inverter

## Topology and principle operation

General observations on NPC and ANPC converter topologies and their control methods have already been made in other works [4], [5], [6], [9]. Specifically, for the BPMSM a Si/SiC hybrid ANPC inverter topology is used, as this topology enables the introduction of a third voltage level with the same number of fast-switching power electronic components with regard to the previously used 2-level topology. Fig. 3 shows the circuit diagram of one phase of the three-level hybrid ANPC inverter. The half bridge of one phase consists of two SiC-MOSFETs ($S_2$, $S_3$) and four Si-IGBTs ($S_1$, $S_4$, $S_5$, $S_6$).

<figure><img src="image_4.png" /><figcaption>Fig. 3: Circuit diagram for one phase of the three-level hybrid ANPC inverter</figcaption></figure>

A hybrid modulation technique is used, where four Si-IGBTs ($S_1$, $S_4$, $S_5$, $S_6$) are controlled with the fundamental frequency and the two SiC-MOSFETs ($S_2$, $S_3$) modulating with high switching frequency. Due to the switch arrangement, all 6 switches only must block half the DC link voltage. This arrangement leads to four possible switching states (P, O+, O- and N), which are shown in Table II.

<table><caption>Table II: Switching states of the three-level hybrid ANPC-inverter</caption><thead><tr><th>State</th><th>Output</th><th>S<sub>1</sub></th><th>S<sub>2</sub></th><th>S<sub>3</sub></th><th>S<sub>4</sub></th><th>S<sub>5</sub></th><th>S<sub>6</sub></th></tr></thead><tbody><tr><td>P</td><td>+V<sub>DC</sub>/2</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr><tr><td>O<sup>+</sup></td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td></tr><tr><td>O<sup>-</sup></td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td></tr><tr><td>N</td><td>-V<sub>DC</sub>/2</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr></tbody></table>

Regarding the switching states of a phase shown in Table II, the current paths shown in Fig. 4 result.

<figure><img src="image_5.png" /><figcaption>Fig. 4: Current paths for the switching states of the three-level hybrid ANPC inverter</figcaption></figure>

Based on the NPC topology, there are usually 3³=27 voltage vectors available. Due to a further redundancy of the O-state of the hybrid ANPC topology, there are 4³=64 possible voltage vectors. To control the hybrid ANPC inverter, a modulation of the voltage space vectors is required, which is described below. The pulse pattern of the hybrid three level pwm for one phase is shown in Fig. 5.

<figure><img src="image_6.png" /><figcaption>Fig. 5: Gate signals of one phase</figcaption></figure>
## Modulation technique

As already described in the previous section, a hybrid modulation method is used for the hybrid ANPC inverter. Based on the switching states of a phase shown in Fig. 4, the space vector diagram shown in Fig. 6 results for the ANPC inverter in the three-phase compound.

<figure><img src="image_7.png" /><figcaption>Fig. 6: Three-level space vector diagram</figcaption></figure>

The space vector diagram consists of 24 active voltage vectors which are composed of 12 small vectors, 6 medium vectors and 6 large vectors. In addition, there are 3 zero vectors (PPP, NNN, OOO). Based on the position of the large vectors, the space vector diagram is separated into six main sectors (sector I to VI). Furthermore, each main sector is divided into four subsectors (subsector A to D). The implementation of the space vector PWM first requires the determination of the main sector and its subsector in which the reference voltage vector is located. Secondly, the nearest vectors are determined to generate a suitable switching pattern. The relative on times of the power switches are then calculated using the switching pattern. Specifically, the relative switch-on times for the hybrid ANPC topology refer to the fast-switching SiC MOSFETs.

The starting point for the calculation of relative on-times is the definition of the reference vector $V_{ref}$, which corresponds to the three-phase voltage.

$$ \vec{V}_{ref} = \frac{2}{3}(V_{ao} + V_{bo} \cdot e^{j\frac{2\pi}{3}} + V_{co} \cdot e^{-j\frac{2\pi}{3}}) \quad (1) $$

By using the clarke transformation, the three-phase abc-system is transformed to 2-dimensional $\alpha$-$\beta$ frame which is used in sector identification.

$$ \begin{bmatrix} V_{ref,\alpha} \\ V_{ref,\beta} \end{bmatrix} = \frac{2}{3} \begin{bmatrix} 1 & -0.5 & -0.5 \\ 0 & \sqrt{3}/2 & -\sqrt{3}/2 \end{bmatrix} \begin{bmatrix} V_a \\ V_b \\ V_c \end{bmatrix} \quad (2) $$

The reference voltage vector can be located in any main sector (I-VI) and its subsector (A-D). For example, considering that the reference vector $V_{ref}$ is located in subsector B of the main sector I, the nearest three voltage vectors for this subsector are $V_1$, $V_2$ and $V_8$ are shown in Fig. 7.

<figure><img src="image_8.png" /><figcaption>Fig. 7: Three-level space vector in main sector I and subsector B</figcaption></figure>

After identification of nearest three vectors, the following expressions can be developed for the on-time calculations of the corresponding vectors where $T_s$ is the switching period, $t_a$, $t_b$ and $t_c$ are the on-times for the voltage vectors $V_1$, $V_8$ and $V_2$.

$$ \vec{V}_{ref} T_s = \vec{V}_1 t_a + \vec{V}_8 t_b + \vec{V}_2 t_c \quad (3) $$

$$ T_s = t_a + t_b + t_c \quad (4) $$

By solving equation (3), the on time of the corresponding voltage vectors can be computed by (5).

$$ \left. \begin{array}{l} t_a = T_s - 2\sin(\theta) \\ t_b = 2\sin\left(\theta + \frac{\pi}{3}\right) - T_s \\ t_c = T_s - 2\sin\left(\theta + \frac{\pi}{3}\right) \end{array} \right\} \quad (5) $$
# Design and Implementation of the three-level hybrid ANPC inverter

## Requirements of the BPMSM for the inverter system

At first, the requirements of the BPMSM for the inverter must be considered to derive the corresponding design specifications for the hybrid ANPC inverter system. A DC-Link voltage of 565 V is selected to provide the nominal output phase voltage of 230 V for the BPMSM. The suspension and drive windings require a rated rms phase current of 25 A each. An inverter output current of 30 A<sub>rms</sub> is provided for the possibility of short-term overload capability. With a four-pole rotor, the high speed of 100.000 rpm of the BPMSM requires fundamental electrical frequencies up to 3,3 kHz. Due to the high electrical fundamental frequencies and low inductances, high switching frequencies are required. In this context, only short latency times are permissible to be able to impress the corresponding phase current into the low-inductance winding. A low latency leads to an increase in the stability range of the PID position control, which makes it possible to increase the stiffness of the suspension unit [8]. As the intended hybrid ANPC inverter system is to be operated as a three-level topology or two-level topology, a maximum switching frequency of 100 kHz is selected. The design specification of the hybrid ANPC inverter is summarized in Table III.

<table><caption>Table III: ANPC inverter design specification</caption><thead><tr><td>Parameter</td><td>Specification</td></tr></thead><tbody><tr><td>rated power</td><td>20 kVA</td></tr><tr><td>DC-Link voltage</td><td>565 V</td></tr><tr><td>DC-Link capacitor</td><td>50 μF</td></tr><tr><td>switching frequency</td><td>100 kHz</td></tr><tr><td>output current</td><td>30 A (RMS)</td></tr><tr><td>output frequency</td><td>3,3 kHz</td></tr></tbody></table>

A total of four three-phase inverters with the design specifications shown in Table III are required to operate the BPMSM.

## Power Semiconductors

Taking the hybrid three-level ANPC topology into account, the power switches only must block half the DC-Link voltage. The prerequisite for this assumption is that an appropriate three-level modulation technique is used. As this inverter system is also to be operated as a two-level inverter for test purposes, the full DC-Link voltage must be considered when dimensioning the power switches. The power module F3L11MR12W2M1_B74 from Infineon is used. 12 power modules are required for complete operation of the BPMSM. This results in a total of 72 switching power devices to be controlled.

## DC-Link

As can be seen from the circuit topology already shown, a split DC-Link is required. A DC-Link capacitance of 50 μF is selected for each three-phase inverter. Low parasitic inductance is aimed for to keep overshoot-voltage low. This concerns the properties of the capacitor itself on the one hand and the connection of the DC-Link capacitor to the power board on the other. A custom designed full-ceramic DC-Link is realized and is shown in Fig. 8.

<figure><img src="image_9.png" /><figcaption>Fig. 8: DC-Link with ceramic capacitors</figcaption></figure>

To provide the DC-Link capacity of 50 μF, ten capacitors of Ceralink B58035U5106M001 TDK EPCOS 10 μF/500V are used.
## Power PCB

The design of the power PCB is necessary for connecting the power modules to the DC-Link capacitors and providing the phase outputs. To enable the carrying capacity of the required phase and DC-Link currents, the power PCB consists of 6 layers, each with 105 µm end copper. The principle layer stack of the power PCB is shown in

<figure><img src="image_10.png" /><figcaption>Fig. 10: Exploded view drawing of the DC-Link layer stack</figcaption></figure>

The power PCB is divided into two areas, the DC-Link and phase output. The areas are separated to prevent parasitic capacitance between the phase outputs and the DC-Link, as this leads to undesirable leakage currents at high switching frequencies [7]. Due to the expected steep voltage rises and high switching frequency of 100 kHz, a low parasitic inductance is required in the DC-Link to limit overshoot voltage during the switch-off process. The stray inductance between the DC-Link capacitor and the terminals of the power modules affects the most the switch turn-off overshoot voltage [7]. This results in the objective of short commutation paths. Taking into account the current paths of the switching states shown in Fig. 5, it is indicated that all commutations of the hybrid three-level ANPC inverter happen between P-layer and O-layer, or between O-layer and N-layer. As the inverter system is also to be operated with a two-level PWM, a P- and N-layer are initially arranged as close as possible around the PCB core to ensure short commutation paths for this control method. The minimum permissible distance between the two layers is limited by the creepage requirements. To ensure a suitable insulation between the P- and N-layer, these are separated by a 0.32 mm thick PCB core of FR4. To realize short commutation paths for the three-level PWM control method, two O-layers are arranged around the P- and N-Layer. This ensures a symmetrical division of the commutation paths and at the same time serves as shielding of the P- and N-layer, which leads to improved EMI behaviour. The top and bottom layers are used to connect the power modules and DC-Link capacitors.

An exploded view drawing of the layer stack is shown in Fig. 10.

<figure><img src="image_11.png" /><figcaption>Fig. 10: Exploded view drawing of the DC-Link layer stack</figcaption></figure>

For a low-inductance design and optimum heat dissipation, the phase outputs are distributed across all 6 layers and connected with stiching vias. The GO 20-SME/SP3 current sensor from LEM is used to measure the phase currents, which has a current measuring range of ± 50A. The CAD model of the designed Power PCB is shown in Fig. 11. The dimensions of the power PCB are 180 mm x 93mm x 23mm

<figure><img src="image_12.png" /><figcaption>Fig. 11: CAD model of the Power PCB</figcaption></figure>

For the low-inductance connection of the gate driver boards to the gates of the power modules, pin sockets are used in which the gate line is split over several pins. The design of the gate driver boards is considered in the following section.

## Gate Driver

Taking the circuit topology into account, six isolated gate drivers are required to control one phase. A total of 72 isolated gate drivers are
therefore required for the complete operation of
the BPMSM. The gate driver PCB consists of four
layers. For controlling the power switches a gate
source voltage of +15V and -5V is used. The
driver circuits UCC15241 from TI are used. Each
gate driver requires a separate galvanically
isolated auxiliary power supply to provide the
+15V and -5V switching voltage. The UCC21750
Push-pull converters are used to generate the
galvanically isolated auxiliary power supply for
the individual drivers. The CAD model of the gate
driver PCB is shown in Fig. 12. The dimensions
of the driver PCB are 57 mm x 78 mm.

<figure><img src="image_13.png" /><figcaption>Fig. 12: CAD model of the Gate-driver PCB for one phase</figcaption></figure>

The connectors for the logic signals are arranged
in such a way that the real-time system can be
connected directly to the driver boards. This
minimizes the risk of interference coupling into
the logic signals. The concept of the real time
system for the hybrid ANPC inverter is
considered in the following section.

Realtime-system and control section

The central part of the hybrid ANPC inverter is
the real-time system. For this purpose, a control
card evaluation board of the microcontroller
C2000 Delfino F28388D from TI is used. This
contains two CPU cores with a clock frequency
of 200 MHz, which enables the control of all four
three phase ANPC inverters simultaneously with
only one microcontroller chip. This reduces the
effort of synchronizing the ANPC inverters,
which is necessary to minimize the influence of
EMC and allows a more robust control. All power
switches are controlled by PWM-signals
generated from the ePWM-modules or via logical
signals of the GPIO-module. To control the four
ANPC inverter systems and the BPMSM, signals
of current transducers and radial position signals
need to be captured by the ADC channels of the
microcontroller. The ADC channels are driven in
a 12-bit single-ended mode. A bearingless
incremental encoder is used to measure the rotor
angle of the BPMSM. To evaluate the signals of

the bearingless incremental encoder the enhanced
Quadrature Encoder Pulse (eQEP) module is
used. Furthermore, each CPU of the C2000
F28388D microcontroller includes a Control Law
Accelerator (CLA), which is an independent,
fully programmable, 32-bit floating point math
processor. This allows a parallel processing of
math operations. Because of the low interrupt
latency of the CLA, ADC samples can be read
just-in-time, which reduces the sample to output
delay. Due to these properties, the CLA is used
for implementing a fast current control loop with
low latency. Utilizing the CLA for time-critical
tasks frees up the main CPU to perform other
functions like speed control and communication
tasks. In order to be able to transfer the
measurement signals to a host PC, the Ethernet-
Interface of the included ARM Cortex M4-
Processor is used. Conversely, parameter values
of the ANPC inverter can be changed with the
host PC via this interface. This enables a live
monitoring of the measurement signals and
parameter values, which simplifies the direct and
step-by-step comparison of the measurement with
the simulation model. The real-time model of the
C2000 F28388D microcontroller and the GUI of
the host PC are programmed by
MATLAB/Simulink. Due to this modular and
freely programmable inverter system, different
modulation techniques and control algorithms
can be tested [3].

Integration of the inverter system

The CAD model of the BPMSM with the
integrated hybrid ANPC inverter is shown in Fig.
13.

<figure><img src="image_14.png" /><figcaption>Fig. 13: CAD model of the BPMSM with integrated hybrid ANPC inverter</figcaption></figure>
The integration of the bearingless PMSM and the ANPC inverter in a common housing offers advantages in terms of power density and EMI behaviour. The direct connection of the drive- and suspension winding to the ANPC inverter has proved to be advantageous. The elimination of an additional motor cable minimizes the risk of reflections and parasitic leakage currents at high switching frequencies. Furthermore, the power modules of the ANPC inverter are cooled directly on the housing of the bearingless PMSM, which has an active water cooling. In addition, the housing has integrated eddy current sensors for measuring the radial position in the x- and y-directions on both sides of the machine. The ITD49H00 bearingless incremental encoder from Baumer is used to measure the rotor angle of the BPMSM [10].

## Experimental Setup

A concept for the test setup is realized to validate the operation of the ANPC inverter system. The experimental setup of the three-level hybrid ANPC inverter is shown in Fig. 14.

<figure><img src="image_15.png" /><figcaption>Fig. 14: Three level ANPC inverter testbench</figcaption></figure>

A WT 5000 power analyzer from Yokogawa is used to measure the line-to-line phase voltage and the line phase current. External current sensors IN 200-S from LEM are used to measure the phase currents. For the initial test of the ANPC inverter, it was mounted on a provisional water heat sink. The hybrid ANPC inverter is operated with a small RL load, to investigate whether the inverter is able to injecting the phase current into a low-inductance load at the specified DC-Link voltage of 565 V. The test parameters for the experimental validation are summarized in Table IV.

<table><caption>Table IV: Experimental parameters</caption><thead><tr><td>Parameter</td><td>Specification</td></tr></thead><tbody><tr><td>DC-Link voltage</td><td>565 V</td></tr><tr><td>switching frequency MOSFET</td><td>100 kHz</td></tr><tr><td>switching frequency IGBT</td><td>3,3 kHz</td></tr><tr><td>output current</td><td>8 A (peak)</td></tr><tr><td>output frequency</td><td>3,3 kHz</td></tr><tr><td>load resistance</td><td>0,2 Ω</td></tr><tr><td>load inductance</td><td>200 μH</td></tr></tbody></table>

## Measurement Results

The operation of the designed and implemented hybrid ANPC inverter is validated by experimental test. First, the line to line phase voltage waveform is considered under no load condition for a output frequency of 3,3 kHz shown in Fig. 15.

<figure><img src="image_16.png" /><figcaption>Fig. 15: line to line phase voltage no load</figcaption></figure>

The abnormal voltage pulses are caused by asymmetrical dead time effects that form in the area of the zero crossing [7]. In this case, this affects the outer switches ($S_1, S_4$) and the clamping switches ($S_5, S_6$), as their pulses are controlled by software. At the high output frequency of 3.3 kHz, the effect is more apparent than at lower frequencies. This requires further optimization of the control method for high output frequencies. The deadband of the SiC MOSFET is set to 0,8 µs.
A controlled current of 8 A<sub>peak</sub> with a fundamental frequency of 3.3 kHz is subsequently injected into a low RL load. The phase current waveforms are shown in Fig. 16.

<figure><img src="image_17.png" /><figcaption>Fig. 16: phase current waveforms with RL load condition</figcaption></figure>

The corresponding line to line phase voltage for the operating point is shown in Fig. 17.

<figure><img src="image_18.png" /><figcaption>Fig. 17: line to line phase voltage with RL load condition</figcaption></figure>

Due to the effects of the asymmetrical dead time already shown in Fig. 15, the phase current is distorted at the high output frequency. This requires further optimization of the control method for high output frequencies.

## Conclusion and future work

In this paper a hybrid ANPC Three Level Inverter for a High Speed Bearingless PMSM was presented. The design process and implementation of the hybrid ANPC inverter was presented based on the BPMSM requirements for the inverter system. In addition, an experimental setup was realized to validate the hybrid ANPC inverter. The operation of the designed and implemented hybrid ANPC inverter was validated by experimental test. With the help of the hybrid ANPC converter system presented, the

investigation of the operating behaviour of the BPMSM and stability range of the radial position control with two-level and three-level inverter supply with the same inverter system are possible for future work. Taking these aspects into account, further three-level modulation and control methods can be implemented with this inverter system and investigated in conjunction with the BPMSM. This requires the simultaneous operation of four three-phase ANPC inverter systems.

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[10] Baumer: Datasheet ITD49H00 Rectangular signal