# A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors

Patsy Cadareanu, Ganesh Gore, Edouard Giacomin, Pierre-Emmanuel Gaillardon

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Patsy Cadareanu, Ganesh Gore, Edouard Giacomin, Pierre-Emmanuel Gaillardon. A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors. 27th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC), Oct 2019, Cusco, Peru. pp.307-322, 10.1007/978-3-030-53273-4_14. [https://doi.org/10.1007/978-3-030-53273-4_14](https://doi.org/10.1007/978-3-030-53273-4_14). [hal-03476610](https://HAL.inria.fr/hal-03476610)

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Distributed under a Creative Commons Attribution 4.0 International License
A Predictive Process Design Kit for Three-Independent-
Gate Field-Effect Transistors

Patsy Cadareanu, Ganesh Gore, Edouard Giacomin, and Pierre-Emmanuel Gaillardon

Electrical and Computer Engineering Department, University of Utah
Salt Lake City, Utah, USA

patsy.cadareanu@utah.edu,
ganesh.gore@utah.edu,
edouard.giacomin@utah.edu,
pierre-emmanuel.gaillardon@utah.edu

**Abstract.** The *Three-Independent-Gate Field-Effect Transistor* (TIGFET) is a promising beyond-CMOS technology which offers multiple modes of operation enabling unique capabilities such as the dynamic control of the device polarity and dual-threshold voltage characteristics. These operations can be used to reduce the number of transistors required for logic implementation resulting in compact logic designs and reductions in chip area and leakage current.

However, the evaluation of TIGFET-based design currently relies on a close approximation for the *Power, Performance, and Area* (PPA) rather than traditional layout-based methods. To allow for a systematic evaluation of the design area, we present here a publicly available Predictive *Process Design Kit* (PDK) for a 10 nm-diameter silicon-nanowire TIGFET device. This work consists of a SPICE model and full custom physical design files including a *Design Rule Manual*, a *Design Rule Check*, and *Layout Versus Schematic* decks for Calibre®. We validate the design rules through the implementation of basic logic gates and a full-adder and compare extracted metrics with the FreePDK15nm™ PDK. We show 26% and 41% area reduction in the case of an XOR gate and a 1-bit full-adder design respectively. Applications for this PDK with respect to hardware security benefits are supported through a differential power analysis study.

# 1 Introduction

In the past decade, the semiconductor industry has seen exponential growth in computationally intensive applications such as artificial intelligence, augmented reality, and machine learning. Scaling down the standard semiconductor technologies based on standard *Metal-Oxide-Semiconductor Field-Effect Transistors* (MOSFET) devices has been the primary solution for achieving these performance requirements. However, with a reduction in transistor size, undesired short-channel effects such as increased leakage current start dominating the device operation. Several 3D semiconductor structures such as *Fin Field-Effect Transistor* (FinFET) or *Gate-All-Around* (GAA) configurations have been proposed to enhance channel electrostatic control and reduce
leakage current [1]. However, their fabrication in the sub-10 nm regime is increasingly
difficult and expensive [2] and so there is a need to investigate devices which can be
scaled functionally rather than physically.

To continue supporting ever-increasing performance demand substantial research
has been devoted to novel semiconductor structures with enhanced functionality [3-5].
Device level innovations such as novel geometries and materials are used in improved
logic devices including Spintronics-based FETs, Tunnel FETs, and Ferroelectric FETs
[6-7].

Of particular interest are *Multiple Independent Gate FETs* (MIGFETs), which are
Schottky-based devices using additional gate terminals to configure the device to dif-
ferent modes of operation [8-11]. Due to their compatibility with the standard CMOS
manufacturing process and their increased logic benefits, these devices are considered
promising both as superlatives and alternatives to conventional MOSFETs. A wide
range of studies showing the benefits of these devices have been carried out in different
domains including digital, analog, and RF design [12-13].

One promising MIGFET device is the *Three-Independent-Gate FET* (TIGFET) [14],
which introduces two gate terminals called *Polarity Gates* (PG) to a traditional FET
structure. The PG terminals are used to modulate Schottky-barriers at the source and
drain of the FET and effectively allow for a dynamic configuration of the device to n-
or p-type. A massive benefit to these devices is their extremely low leakage current
when compared to standard MOSFETs, which is due to the current cutoff provided by
the Schottky-barriers. Meanwhile, the ability to dynamically control device polarity
gives TIGFETs a higher expressive logic capability than conventional devices, result-
ing in a compact logic gate implementation and lower leakage current per cell. As a
result, the circuit-level benefits of TIGFETs have been largely investigated in literature
in the past few years and have shown promising implementations for a wide range of
logic circuits such as multiplexers [15], adders [16], flip-flops [17] or for use in differ-
ential power attack mitigation techniques with reduced power line variation [18].

However, performance evaluation of TIGFET-based design currently relies on an
area approximation rather than traditional layout-based methods since no TIGFET-
based *Process Design Kit* is publicly available.

In this work, we introduce an open-source TIGFET PDK available online [19], cre-
ated for simple integration with Cadence® Virtuoso.

The *Design Rule Manual* for the proposed PDK is derived from previously fabri-
cated MIGFET devices [4] and the publicly available FreePDK15nm™ [20]. Our PDK
consists of a SPICE Verilog-A model for a 10 nm diameter *Silicon Nanowire* (SiNW)
TIGFET and includes full custom design files, *Design Rule Check* (DRC), and *Layout
Versus Schematic* (LVS) decks. The availability of this PDK will allow universities and
researchers to explore the benefits of TIGFETs in various domains. The benefits of the
proposed PDK are as follows:

* It provides design rules and a layout consistency check for a more reliable and reproducible system design,
* It allows accurate metric evaluations, such as area or delay, of TIGFET-based designs,

* It enables the system designer to explore higher-level designs using state-of-the-art TIGFET circuit techniques,

* It showcases the area benefits of compact TIGFET gates for an XOR and a 1-bit full adder.

* It provides a detailed regular cell placement method which helps mitigate additional routing overhead.

The rest of this chapter is organized as follows: Section II provides an overview of TIGFET technology including its circuit-level opportunities. Section III introduces the TCAD work and resulting electrical SPICE model of the proposed TIGFET device. Section IV describes the physical TIGFET design and briefly describes the DRC and LVS decks. Section V evaluates the regular layout technique for TIGFETs, and Section VI includes a differential power analysis which further showcases the benefits of TIGFET-based applications. Finally, Section VII concludes the chapter.

# 2 Technical Background

In this section, we establish the necessary background to understand TIGFET technology. We then briefly review circuit-level opportunities brought by TIGFET devices and discuss publicly available design kits.

## 2.1 TIGFET Operation

The TIGFET is composed of drain and source contacts as well as three independent gate contacts, as shown in Fig. 1 (a). The *Control Gate* (CG) controls the potential barrier in the channel in the same manner the gate contact works in a conventional MOSFET device and turns the device on or off.

The *Polarity Gates* (PG) at the source and drain modulate their respective Schottky-barriers, selecting the type of carriers (electrons or holes) which will enter the channel and dominate the current flow; the ability to make this selection is called device reconfigurability and is unique to Schottky-barrier-based devices. TIGFET devices have been successfully fabricated with several channel technologies such as FinFET [21], 2D materials [22], and SiNW [23]. In this paper, we will consider a SiNW TIGFET which is fabricated using a fully CMOS-compatible process. A scanning electron microscopy picture of a previously fabricated TIGFET device with labeled terminals is seen in Fig. 1 (b) [23].
<figure><img src="image_2.png" /><figcaption>**Fig. 1.** (a) TIGFET general structure; (b) Scanning Electron Microscopy image of a fabricated TIGFET device comprising of four vertically stacked silicon nanowires [23].</figcaption></figure>

**2.2 Circuit-level Opportunities**

Due to their reconfigurability, TIGFETs show richer switching capabilities per given transistor and this ability is used to implement compact logic gates. For instance, as shown in Fig. 2 (a), a TIGFET NAND requires 1 fewer transistor than its CMOS counterpart. Similarly, as illustrated in Fig. 2 (b) and (c), while a CMOS two-input XOR and three-input majority gate require 8 and 10 transistors respectively, using TIGFETs reduces this amount to only 4 transistors in both cases. This leads to an area reduction, as is demonstrated in Section V. Note also that a two-input XOR, three-input XOR, and three-input majority gate can all be made from the same four TIGFET transistors by adjusting the terminal voltages [10]. This essentially means that a TIGFET circuit does not need to be programmed until after it has been fabricated and can also be reprogrammed for multiple differing functions, a feat not possible with standard CMOS technology.

<figure><img src="image_3.png" /><figcaption>**Fig. 2.** TIGFET compact gates: (a) 2-input NAND; (b) 2-input XOR; (c) 3-input majority gate.</figcaption></figure>

**2.3 Publicly Available Physical Design Kits**

Previous PDKs based on predictive technologies include the FreePDK45nm™ [24] and FreePDK15nm™ [20] which present the design rules and standard cell library [25] for planar and FinFET CMOS technologies respectively. In addition, the ASAP7 PDK
[26] was created to describe the aggressive 7 nm FinFET technology node. The set of realistic assumptions included in the ASAP7 PDK simplifies its use in an academic setting. Most recently, an add-on for the FreePDk15nm™ was proposed for CMOS-compatible Resistive RAM technology [27].

# 3 Proposed TIGFET Device Properties

In this section, we evaluate the proposed TIGFET device electrical properties and present the TIGFET SPICE model used in the PDK as well as the TCAD model upon which it is based.

## 3.1 Device TCAD Work

TCAD simulations of a 10 nm SiNW TIGFET device with gates of 10 nm and separations of 10 nm were performed in Synopsys Sentaurus. Nickel silicide-silicon is the assumed Schottky barrier contact and the dielectric layer is HfO₂ with a thickness of 8 nm. Electrical properties, such as the ON-current ($I_{ON}$), the OFF-current ($I_{OFF}$) and the nominal voltage $V_{DD}$ were extracted from these simulations. The maximum current drive for *n*-type operation is 90.20 µA/µm and for *p*-type is 89.25 µA/µm, as seen in Fig. 3. Thanks to the Schottky barrier cutoff, $I_{OFF}$ is extremely low at 3.3 nA/µm and 0.1 nA/µm for *n*- and *p*-type operation respectively. Further work and discussion of this simulation is available in [28].

<figure><img src="image_4.png" /><figcaption>**Fig. 3.** $I_{DS}-V_{GS}$ characteristics of the simulated device at $V_{DD}$= 0.7 V. The switching is centered around $V_{GS}$ =0.3 V. The linear scale results show the maximum ON-current and the log scale results show the minimum OFF-current.</figcaption></figure>

These current drives are approximately 10 X lower than the previous 22 nm TIGFET device simulations [7] which used a supply voltage of 1.2 V. This loss is primarily due to the 0.7 V supply voltage used in the 10 nm devices as is standard for technology at
this node. This lowered supply voltage is necessary for fair comparisons with the cor-
responding CMOS technology.

The real benefit to these devices is their reconfigurability, as used in Section V and
this is enhanced with this new model: the 10 nm TIGFET device was designed in TCAD
to be extremely symmetric in its ON-current drives for *p*-type and *n*-type switching.
This is seen in Fig. 4 which compares the 10 nm TIGFET TCAD device to the previ-
ously used 22 nm TIGFET TCAD device using normalized drain current and gate volt-
age characteristics; from this plot we can see a decrease in asymmetry from approxi-
mately 9% with the 22 nm simulations to less than 1% with this new model.

<figure><img src="image_5.png" /><figcaption>Fig. 4. Normalized I<sub>DS</sub>-V<sub>GS</sub> characteristics of the simulated 10 nm and 22 nm TIGFET devices.</figcaption></figure>

**3.2 SPICE Verilog-A Model**

The TCAD simulation results have been used to develop a TIGFET macro model in
Verilog-A, as shown in Fig. 5.

<figure><img src="image_6.png" /><figcaption>Fig. 5. Macro model of a SiNW TIGFET.</figcaption></figure>

The nonlinear current source *I*(*D*,*S*) is modeled using TIGFET macro model approach and a function of the drain, source and all three gate voltages. The table stores the current *I*(*D*,*S*) for each bias point combination applied on the device terminals. We chose a bias point granularity of 0.1 V on the PG gates at the source and drain and the
CG terminal, and a 0.05 V bias on the drain terminal, totaling to 67,536 bias points. For other bias points, the model uses linear interpolation and extrapolation techniques. Linear interpolation provides relatively better convergence in transient simulation and avoids any spurious false peaks. To model transient behavior, the capacitance between each terminal pair is extracted by AC simulations from TCAD and the average value obtained under all the bias conditions is considered in the proposed model. The terminal access resistances are also extracted using TCAD simulations. The coupling capacitance between gate terminals is very small and omitted from the model. Since TIGFETs are built using vertically stacked SiNWs, as explained in Section II, the proposed SPICE model assumes a single SiNW by default. To change the number of wires in the stack, a *nw* design parameter can be changed. A comparison of SPICE model and TCAD simulation result indicates less than 0.1% mean square error for both DC and transient simulations.

# 4 TIGFET Physical Design

In this section, we briefly present the TIGFET fabrication process requirements and corresponding constraints. Then, we summarize the sets of DRC and LVS rules. Finally, we discuss the implications of a TIGFET-based physical design.

## 4.1 Process Assumptions

The fabrication of a SiNW-based TIGFET is completely CMOS-compatible and straightforward, the most challenging step for fabricating these devices at the 10 nm node being patterning. Each TIGFET has three independent gates, which are patterned with a spacing of 15 nm and reliable fabrication of these features is required for correct functionality of the device. The traditional 193 nm (ArF) lithography process is inadequate for realizing features this small, and the most advanced lithography process of *Extreme Ultraviolet Lithography* (EUVL) is as yet prohibitively expensive for high volume production [29]. An alternative option to the latter is *Dual Patterning Lithography* (DPL) at 193nm. DPL allows patterning at half the pitch size of the corresponding single patterning technique [29]. Hence, in the proposed PDK, we consider DPL for patterning of the gate layer and the first four metal layers. Every DPL layer requires decomposition before the fabrication process. In commercial PDKs this decomposition is achieved by providing different colors for each DPL layer. When two patterns have to be drawn in the same layer with spacing smaller than the pitch, double patterning is realized by using two separate colors which correspond to different masks. These two separate masks are then connected together by inserting a stitch to form an electrical connection between them [30]. A minimum number of stitches must be introduced into each layer to stall printability degradation [31]. Process modeling is also recommended to ensure correct decomposition of layers. In an academic setting, placement and design using all the constraints of the DPL technique can get increasingly difficult. The layer decomposition task is better automated using many proposed layout decomposition
EDA tools [32]. To simplify the use of the proposed PDK, we represent each DPL layer with a single color. This results in the gate layer and the first four metal layers being represented using a single color. To simplify further, this PDK does not provide any additional layers for threshold adjustment or a gate cut mask. The proposed PDK's *Back-End-Of-Line* (BEOL) process supports ten layers of metal. The list of key layers is given in Table I.

<table><thead><tr><th>Layer Name</th><th>Drawn Width (nm)</th><th>Pitch (nm)</th></tr></thead><tbody><tr><td>Active</td><td>166</td><td>32</td></tr><tr><td>GATE</td><td>20</td><td>64*</td></tr><tr><td>PG-CG</td><td>20</td><td>35</td></tr><tr><td>SDC</td><td>28</td><td>40</td></tr><tr><td>GC</td><td>56</td><td>40</td></tr><tr><td>IL</td><td>24</td><td>40</td></tr><tr><td>V0</td><td>28</td><td>36</td></tr><tr><td>Metal 1-4</td><td>28</td><td>36</td></tr><tr><td>VM0 5-10</td><td>28</td><td>36</td></tr><tr><td>Metal 5-10</td><td>56</td><td>72</td></tr><tr><td>VM5 5-10</td><td>56</td><td>72</td></tr></tbody></table>

* Pitch between the gate of two different devices.

<caption>**Table 1.** List of key layers in the proposed PDK.</caption>

## 4.2 Single Device Layout and Dimensions

The layout of a single TIGFET is shown in Fig 6. As discussed earlier, all three gates of the TIGFET are drawn using the same color to represent the gate layer; these are separated later using EDA tools for fabrication of separate PG and CG masks. Vertical strips of polysilicon are patterned uniformly across the chip with a *Contacted Poly Pitch* (CPP) of 44 nm. The gate cut mask generated using the automated EDA tools is used to cut the excess polysilicon from around the active region with a 20 nm extension. Fig. 6 shows the cross-section view of the *Front-End-Of-Line* (FEOL) and *Middle-Of-Line* (MOL) of the proposed predictive process model. Contact to all the gate terminals is made using the *Gate Contact* (GC) layer. Source and drain terminals of the device are connected using *Source Drain Connect* (SDC) layer. Both GC and SDC layers are connected to the first layer of the metal using *Interconnect Layer* (IL).
<figure><img src="image_7.png" /><figcaption>Fig. 6. TIGFET layout and the FEOL/MOL process cross-section.</figcaption></figure>

The drain and source terminals of the device have a height and width of 100 nm and 30 nm respectively. The side view in Fig. 6 shows the channel as formed with a maximum stack of four SiNW. Based on the height of the active region, multiple such stacks can be formed with a pitch of 40 nm. Fig. 6 depicts a device with a total of 5 stacks of 4 nanowires. Some of the other key layers are summarized in Table I, along with the drawn width and minimum pitch.

## 4.3 Cell Layout and DTCO Consideration

Meeting fabrication yield and cost targets are particularly challenging tasks when fabricating new semiconductor structures. *Design for Manufacturability* (DFM) and *Design Technology Co-optimization* (DTCO) are widely used techniques to ensure successful device fabrication using novel processes. Using the DTCO approach, manufacturing yield and device density can be improved by customizing the layouts of some widely used structures [26, 33]. In the traditional fabrication processes, the DTCO approach is used for optimizing the highly regular pattern such as an SRAM cell. The SRAM pattern can be carefully tuned using actual manufacturing data allowing tighter tolerance, higher device density, but very few variations in the layout.

In the case of TIGFET-based designs, transistors connected in series (i.e., with shared source and drain contacts) and tied polarity gates are very common, and these are called grouped devices. We use the DTCO approach to optimize the layout of the grouped devices. Fig. 7 shows the schematic and the layout of two grouped TIGFETs. The polarity gates of both devices are shorted together by allowing horizontal routing of the gate layer to the top of the device. The DRC rule for vertical spacing of gates
with different potentials is compromised to achieve higher device density. This struc-
ture is also very helpful in designing a regular layout using TIGFET devices, as will be
shown in Section V.

<figure><img src="image_8.png" /><figcaption>Fig. 7. TIGFET grouped transistors: (a) Schematic; (b) Layout view.</figcaption></figure>

**4.4 Sea-of-Tile Implementation**

The enhanced functionality of TIGFETs comes at the cost of two additional gate terminals per device. Using traditional layout and routing methods, the TIGFET-based physical design may not give the best possible results due to the addition of these extra gates. Here, we explore some techniques to mitigate the additional routing complexity. In particular we look at the dual metal power grid routing and then explore the novel layout approach for increasing regularity of the TIGFET-based design, which was first proposed in [34-35].

At advanced technology nodes, one of the prerequisites for robustness is a layout
regularity. This makes the design less sensitive to process variation and improves the
yield of fabrication. *Sea-of-Tiles* (SoT) is a fully configurable architecture in which an
array of logic tiles is uniformly spread across the chip. A tile is an array of TIGFET
devices in which the devices are placed horizontally and adjacent to each other with
shorted polarity gates in case they share the same logic on polarity gates. If the devices
share the same logic on the control gate, they are aligned vertically with shorted control
gates. Based on the number of devices grouped together, many different sizes of tiles
are possible. In this work, we will consider *Tile*<sub>G1</sub> and *Tile*<sub>G2</sub> [35], whose corresponding
schematics are shown in Fig. 8 (a) and (b) respectively.
<figure><img src="image_9.png" /><figcaption>**Fig. 8.** Logic tiles: (a) *Tile*<sub>G1</sub> stick diagram; (b) *Tile*<sub>G1</sub> schematic; (c) *Tile*<sub>G2</sub> stick diagram; (d) *Tile*<sub>G2</sub> schematic.</figcaption></figure>

Each tile can be configured for different logical operation based on the input provided to its nodes (n1-n6) and gates (g1, g2, G1, and G2).

Many other configurations are possible using *Tile*<sub>G2</sub>, and these are listed in Table II.

<table><caption>**Table 2.** Area comparison of tile-based logic gates implementation.</caption><thead><tr><th>Logic Gate</th><th>Tile</th><th>Area TIGFET (µm²)</th><th>Area CMOS (µm²)</th></tr></thead><tbody><tr><td>1-bit HA</td><td>2 × <i>Tile</i><sub>G2</sub></td><td>0.34</td><td>0.59</td></tr><tr><td>XNOR2</td><td><i>Tile</i><sub>G2</sub></td><td>0.37</td><td>0.49</td></tr><tr><td>NAND2</td><td><i>Tile</i><sub>G2</sub></td><td>0.17</td><td>0.15</td></tr><tr><td>NOR2</td><td><i>Tile</i><sub>G2</sub></td><td>0.17</td><td>0.15</td></tr><tr><td>INV</td><td><i>Tile</i><sub>G1</sub></td><td>0.10</td><td>0.10</td></tr><tr><td>BUF</td><td><i>Tile</i><sub>G1</sub></td><td>0.10</td><td>0.10</td></tr></tbody></table>

We implement *Tile*<sub>G1</sub> and *Tile*<sub>G2</sub> using the proposed design rules in Cadence® Virtuoso, as shown in Fig. 9.
<figure><img src="image_10.png" /><figcaption>**Fig. 9.** SoT layout using the proposed PDK: (a) *TileG1* (Area=0.10 µm²); (b) *TileG2* (Area=0.17 µm²).</figcaption></figure>

**4.5 Grid based Power Routing**

A TIGFET device can be configured as a pull-up (*p*-type) network by applying logic 0 to its polarity gates or a pull-down (*n*-type) by applying logic 1. This additional requirement creates a sparse connection of $V_{DD}$/GND connectivity in the cell. Consequently, traditional power distribution schemes with alternate $V_{DD}$ and GND lines are not efficient. As proposed in [35], we used two metal approach to route power around the cell. Fig. 8 shows the horizontal $V_{DD}$ and vertical GND lines. Comparison of this approach with tradition single metal based power routing has been demonstrated in [34] and shows delay reduction by approximately 28% with minimum routing complexity.

**5 PDK Showcases**

In this section, we showcase the area benefits of TIGFET technology by presenting two TIGFET compact logic cells designed using the proposed PDK.

**5.1 Compact XOR Cell**

Using the higher expressive logic capabilities of the TIGFET device, it is possible to build a compact XOR gate. As illustrated in Fig. 2 (b), a TIGFET-based XOR gate only requires 4 transistors, whereas its CMOS counterpart requires 8 transistors. This compact implementation of a TIGFET-based XOR gate results in an area benefit and leakage power reduction. It is interesting to note that the TIGFET design requires a
single device for a pull-up or a pull-down operation, unlike CMOS which requires a
series of two transistors. As a result, it reduces the total resistance in the charging and
discharging load paths. A TIGFET-based XOR is implemented using 2 X $Tile_{G2}$. One
is configured as two individual inverters, and another as an XOR gate, as shown in Fig.
2. The complete layout of the CMOS-based XOR gate. The resulting area of the
TIGFET-based XOR cell is 0.37 $\mu m^2$, which is ~26% smaller than the CMOS imple-
mentation which resulted in an area of 0.49 $\mu m^2$. Due to its symmetric structure, the
TIGFET-based XNOR has the same area and power benefits. This work was previously
shown in [36].

**5.2 Compact 1-bit Full Adder**

We also built a 1-bit full adder using compact TIGFET-based XOR and MAJ logic gates, and compared it to its CMOS counterpart [25], the schematic of which is seen in Fig. 10.

<figure><img src="image_11.png" /><figcaption>Fig. 10. TIGFET-based compact implementation of a 1-bit full adder.</figcaption></figure>

The layout of the TIGFET (Area= 0.66 µm²) and CMOS-based (Area=1.13 µm²) full adder are shown in Fig. 11 (a) and (b) respectively. As explained, the richer switching capabilities of TIGFET devices allow them to realize the same CMOS logic function while reducing the number of devices. In the case of the 1-bit full adder, this results in a 41% area reduction. [36]

<figure><img src="image_12.png" /></figure>
<caption>Fig. 11. Layout view of a full adder: (a) CMOS; (b) TIGFET.</caption>

Similar to the XOR and MAJ gates, various logic functions can be realized by con-
figuring *Tile*<sub>GI</sub> and *Tile*<sub>G2</sub>.

6 Differential Power Analysis Resilience Study

Simulations for power line variation and integral charge were performed using the TIGFET 10 nm PDK for various TIGFET-based logic gate designs including XOR-only, XOR-XNOR, DCVSL-XOR, NAND HP, NAND LL, DCVSL-NAND, NOR HP, NOR LL, and DCVSL-NOR. These results were then compared to simulations performed using a PTM 10 nm LSTP CMOS design. Table III shows these simulation results.

<table><caption>**Table 3.** Power line variation and integral charge studies for TIGFET-based designs compared to CMOS-based designs.</caption><thead><tr><th rowspan="3"></th><th colspan="4">TIGFET 10nm</th><th colspan="3">PTM 10nm LSTP CMOS-CMG</th></tr><tr><th>Only XOR Gate</th><th>XOR-XNOR Gate</th><th>DCVSL XOR Gate</th><th>PTM CMOS XOR</th><th>PTM CMOS XOR/XNOR</th><th>PTM CMOS DCVSL</th></tr><tr><th>ISupply (uA)</th><th>ISupply (uA)</th><th>ISupply (uA)</th><th>ISupply (uA)</th><th>ISupply (uA)</th><th>ISupply (uA)</th></tr></thead><tbody><tr><td rowspan="2">XOR</td><td>Power Line Variation %</td><td>21.16%</td><td>5.81%</td><td>0.58%</td><td>57.46%</td><td>4.51%</td><td>38.52%</td></tr><tr><td>IVDD Integral - Charge (10E-16 C) ([Max-Min])</td><td>0.65</td><td>0.01</td><td>1.05</td><td>0.76</td><td>0.17</td><td>7.34</td></tr><tr><td rowspan="3">NAND</td><td></td><td>NAND HP</td><td>NAND LL</td><td>DCVSL NAND</td><td>4T NAND</td><td>DCVSL NAND</td><td>Charge Sharing*</td></tr><tr><td>Power Line Variation %</td><td>34.55%</td><td>32.38%</td><td>18.64%</td><td>51.77%</td><td>24.64%</td><td>15.29%</td></tr><tr><td>IVDD Integral - Charge (10E-16 C) ([Max-Min])</td><td>0.23</td><td>0.11</td><td>0.96</td><td>0.94</td><td>1.65</td><td>4.83</td></tr><tr><td rowspan="3">NOR</td><td></td><td>NOR HP</td><td>NOR LL</td><td>DCVSL NOR</td><td>NAND</td><td>DCVSL NOR</td><td></td></tr><tr><td>Power Line Variation %</td><td>17.61%</td><td>9.27%</td><td>18.64%</td><td>79.38%</td><td>22.50%</td><td></td></tr><tr><td>IVDD Integral - Charge (10E-16 C) ([Max-Min])</td><td>0.05</td><td>0.17</td><td>0.95</td><td>1.61</td><td>1.89</td><td></td></tr></tbody></table>

Power line variation was lower for almost all TIGFET-based gate configurations (the only exception being for the XOR-XNOR gate). One of the most impressive of these was for a TIGFET-based NAND design which showed 2 X the power line variation when compared to its CMOS-based counterpart. The integral charge was similarly consistently and significantly lower for the TIGFET-based design, with benefits of over 7 X being seen for the DCVSL-XOR simulations. These two metrics are extremely important in designing circuits that are resilient to hardware attacks.

7 Conclusion

This work has exhibited a predictive PDK for a 10 nm-diameter SiNW TIGFET. The design kit is derived using TCAD simulations and realistic assumptions made for large-
scale production of TIGFET-based systems. We detailed key assumptions made while designing the PDK and derived the set of design rules for physical design in Cadence® Virtuoso. Using the TIGFET PDK, we evaluated previously proposed grouped transistor and grid-based power-line distribution overhead introduced because of the TIGFET's additional terminals. We validated the design rules by implementing an XOR and a 1-bit full adder, and compared those with the FreePDK15nm™ CMOS process, which shows 26% and 41% area reduction respectively. The TIGFET PDK was also used to compare against CMOS-based logic cell designs for power variation analysis, and it was showed to be optimal when compared to the CMOS designs for almost all logic cells.

# 8 Acknowledgements

This work was supported by the NSF Career Award number 1751064, and the SRC Contract 2018-IN-2834.

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