AlN/SI interfaces properties revealed by broadband
characterization of coplanar waveguides

Adrien Cutivet, Alain Agboton, Philippe Altuntas, François Lecourt, Marie Lesecq, Nicolas Defrance, Yvon Cordier, Magdalena Chmielowska, Stephanie Rennesson, Julien Camus, et al.

► To cite this version:

Adrien Cutivet, Alain Agboton, Philippe Altuntas, François Lecourt, Marie Lesecq, et al. AlN/SI interfaces properties revealed by broadband characterization of coplanar waveguides. 37th Workshop on Compound Semiconductor Devices and Integrated Circuits held in Europe, WOCSDICE 2013, 2013, Warnemünde, Germany. pp.37-38. hal-00828412

HAL Id: hal-00828412

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# AIN/Si interfaces properties revealed by broadband characterization of Coplanar Waveguides

A. Cutivet¹,⁴, A. Agboton¹, P. Altuntas¹, F. Lecourt¹, M. Lesecq¹, N. Defrance¹, Y. Cordier², M. Chmielowska², S. Rennesson², J. Camus³, Keltouma Ait Aissa³, L. Le Brizoual³, M.A. Djouadi³, J.-C. De Jaeger¹, F. Boone⁴, H. Maher⁴

¹IEMN, CNRS UMR8520, 59652 Université de Lille, France

²CRHEA, CNRS UPR10, rue Bernard Grégory, 06560 Valbonne, France

³Institut des Matériaux-Jean Rouxel, CNRS UMR6502, Université de Nantes, France

⁴CRN², 3000 boul. Université Sherbrooke, QC J1K2R1, Canada

E-mail: adrien.cutivet@iemn.univ-lille1.fr

## ABSTRACT

This paper focuses on the electrical investigation of various AIN/Si interfaces by means of broadband characterization and modeling of CPW (coplanar waveguide) for frequencies up to 50 GHz. These electric measurements are performed under different biases and temperatures in order to investigate the electrical properties. The obtained results are correlated with physical/structural properties of the AIN/Si interface.

## 1. INTRODUCTION

In the context of GaN-based devices (HEMT and LED), AIN thick buffer is considered as a heat sink to improve thermal dissipation between the hot area located within the active layer and the Si substrate. The foreseen advantages of this innovating fabrication process are an improved GaN crystalline quality by a GaN decreased stress, higher thermal dissipation and reduced substrate cost thanks to the PVD deposition of the AIN buffer. Despite these attractive properties, the electrical behavior of AIN/Si interfaces is still not well established. In this study, the complex permittivity of AIN/Si stacks is extracted up to 50GHz, and the effects of both bias and temperature permit to highlight the existence of electrically active defects in the studied layers.

## 2. ELECTRICAL CHARACTERIZATION METHODOLOGY

The electrical broadband characterization permits to extract the complex dielectric permittivity up to 50GHz. The measurements done in this study are obtained from a Network Analyzer permitting $S_{ij}$ parameters acquisition. A LRRM calibration is used to remove all error terms related to non-idealities in the set-up. The CPW structures feature central conductor width of 80µm and space gap of 54µm so that the characteristic impedance is close to $Z$ 50Ω. Adequate modeling of the propagation phenomenon occurring within these structures leads to the calculation of the broadband complex permittivity (i.e. loss angle). This modeling procedure is described hereafter.

### 2.1. Extraction of the AIN/Si dielectric constant

Assuming that CPW lines are matched with the measurement instrumentation, the effective permittivity can be directly evaluated through the propagation constant knowing that:

____ and ______

With $\lambda_0$ and $l$ the wavelength and the CPW length respectively, $\beta$ is the propagation constant. The substrate permittivity can then be deduced using conformal mapping. In the CPW case, Davis model [1] indicates, in a first order approximation:

In our case, the extracted dielectric constant is close to the silicon permittivity since AIN thickness remains negligible compared with the substrate one. Consequently, most of the electromagnetic energy concentrates within the silicon material.

### 2.2. Evaluation of the AIN/Si loss tangent

In the case of quasi-TEM propagation [2], the loss angle can be expressed as:

$$ \frac{(\alpha_d \cdot \lambda_0 \cdot (\varepsilon'_{r} - 1) \cdot \sqrt{\varepsilon_r})}{0.273(\varepsilon_{eff} - 1)} $$

Where $\alpha_d$ is the dielectric loss. Furthermore, the modeling of the propagation loss (directly obtained through $S_{21}$ parameter) leads to the following expression:

Where $\alpha_r$ and $\alpha_g$ are the radiation and conductance losses respectively. Both values are approximated as null, although ______ can be evaluated by static current measurement. Metallic conductor loss ______ is also evaluated using topological parameters: (metallization thickness), (central conductor width) and $\sigma$ (metal conductivity):

$\sqrt{\varepsilon_r}$

and being the low-frequency and high-frequency conductor resistance respectively, with [3]:

____ and $\sqrt{\varepsilon_r}$
Conductor loss value is then de-embedded to the measured propagation loss, so that can be evaluated and then the loss angle of AlN/Si material.

### 3. SAMPLES UNDER TEST

Several samples were investigated. They differ in terms of AlN thickness and deposition method, i.e. either MBE (molecular beam epitaxy) or PVD (pulsed vapor deposition). Layer thickness and crystalline properties of PVD AlN layers (evaluated through XRD and Raman spectroscopy) are detailed in table 1. A HR-Si[111] substrate is also investigated as a reference.

<table><caption>Tab. 1: Samples characteristics</caption><thead><tr><th></th><th>A1</th><th>A2</th><th>B1</th><th>B2</th><th>B3</th></tr></thead><tbody><tr><td>Thickness (nm)</td><td>360</td><td>1600</td><td>350</td><td>600</td><td>950</td></tr><tr><td>Rocking curve FWHM (°)</td><td>2,9</td><td>2</td><td>2,8</td><td>2,4</td><td>2</td></tr><tr><td>Raman peak FWHM (cm<sup>-1</sup>)</td><td>17</td><td>11</td><td>16</td><td>15</td><td>12</td></tr></tbody></table>

Physical characterizations show that the crystalline quality of AlN layers enhances as the layer thickness increases. This phenomenon can be correlated with grain size expansion inherent to PVD method.

### 4. RESULTS AND ANALYSIS

#### 4.1. Bias variation at ambient temperature

First, results obtained for a bias ranging from -10V to +10V are presented in figure 1. Loss angles are extracted at 40 GHz for all the samples.

<figure><img src="image_2.png" /><figcaption>Fig. 1: Loss angles versus bias at 25°C</figcaption></figure>

A bias dependency of loss angle is observed. Positive biases involve a dielectric losses increase, which effect is not present on the silicon reference. The presence of defects, likely located at the AlN/Si interface, can be assumed. Explanations about the electrical behavior of sample A1 are more problematic insofar as the extracted tan(δ) do not follow the aforementioned tendency. Results about the MBE material are not presented in this graph, since no obvious bias dependence was observed on the loss angle.

#### 4.2. Measurements at higher temperatures

In order to obtain further information, similar measurements for higher temperatures (up to 100°C) were carried out. shown, Loss angles according to temperatures and for +10V bias are shown in figure 2.

<figure><img src="image_3.png" /><figcaption>Fig. 2: Loss angles versus temperature for +10V bias</figcaption></figure>

All samples show a loss angle value increasing with temperature except the standard one. This tends to confirm the presence of donor-like defects in PVD samples. Sample B1 shows a much higher loss angle increase and is therefore not plotted. This result can be explained by the existence of static current behavior significantly larger (five order of magnitude) than for the other samples. This static current implies a strong conductance loss, which is considered as null in the calculation procedure. Therefore, the result for B1 is not relevant. This strong DC current is likely caused by grain boundary conduction in the AlN crystalline structure. This assumption is corroborated with the crystalline analysis, indicating a 2.8° rocking curve value and 16 cm⁻¹ Raman peak. Furthermore, AlN thickness parameter does not imply obvious loss angle evolution with bias or temperature. It is assumed that the donors-like defects responsible for tan(δ) thermal dependency are located at the AlN/Si interface. Similar measurements were performed on AlN/MBE samples wherein thermal dependency is much slighter. Further investigation should be led to analyze the physical mechanisms responsible for defects generation during both PVD and MBE growths.

### 5. CONCLUSION

The proposed study permits to extract the complex permittivity of AlN/Si material under different bias and temperature conditions. The obtained results indicate an increasing dielectric loss with temperature on AlN/Si samples, whereas standard Si sample shows no particular evolution. Thus, the existence of donors-like caused by defects at AlN/Si interface is assumed to be at the origin of such dispersion. Further investigation needs to be done to explain the physical mechanism responsible for the different behaviors observed on either PVD or MBE AlN/Si stacks. Interface state density $D_{it}$ and distribution should be determined [4]. In addition, C-V thermal measurements would permit determination of the interface trap levels.

### 6. REFERENCES

[1] M. Davis, E. Williams, and A. Celestini, "Finite boundary corrections to the coplanar waveguide analysis (short papers)," *IEEE Transactions on Microwave Theory and tech niques*, vol. 21, no. 9, pp. 594–596, sep 1973.

[2] A. K. Verma, Paramjeet Singh, "Loss Computation of Multilayer Coplanar Waveguide using Single Layer Reduction
Method" *International Journal of Electromagnetics and Applications*, 2012, 2(6): 174-181

[3] Baudouin MARTINEAU, "Potentialités de la technologie CMOS 65nm SOI pour des applications sans fils en bande millimétrique", IEMN, France, may 2008

[4] D.J. Xi, Y.D. Zheng, P. Chen, R.M. Chu, S.L. Gu, B.Shen, R.Zhang, "Study on the AlN/Si(111) interface properties", *Optical Materials 23 (2003) 143-146*