# Mobility Extraction Using Improved Resistance Partitioning Methodology for Normally-OFF Fully Vertical GaN Trench MOSFETs

Valentin Ackermann, Blend Mohamad, Hala El Rammouz, Vishwajeet

Maurya, Eric Frayssinet, Yvon Cordier, Matthew Charles, Gauthier Lefevre,

Julien Buckley, Bassem Salem

► To cite this version:

Valentin Ackermann, Blend Mohamad, Hala El Rammouz, Vishwajeet Maurya, Eric Frayssinet, et al. Mobility Extraction Using Improved Resistance Partitioning Methodology for Normally-OFF Fully Vertical GaN Trench MOSFETs. Electronics, 2024, 13 (12), pp.2350. 10.3390/electronics13122350. hal-04673055

HAL Id: hal-04673055

https://hal.science/hal-04673055v1

Submitted on 11 Sep 2024

HAL is a multi-disciplinary open access
archive for the deposit and dissemination of sci-
entific research documents, whether they are pub-
lished or not. The documents may come from
teaching and research institutions in France or
abroad, or from public or private research centers.

L'archive ouverte pluridisciplinaire HAL, est
destinée au dépôt et à la diffusion de documents
scientifiques de niveau recherche, publiés ou non,
émanant des établissements d'enseignement et de
recherche français ou étrangers, des laboratoires
publics ou privés.

<figure><img src="image_1.png" /></figure>

Distributed under a Creative Commons Attribution 4.0 International License
<figure><img src="image_2.png" /></figure>

Article

# Mobility Extraction Using Improved Resistance Partitioning Methodology for Normally-OFF Fully Vertical GaN Trench MOSFETs

Valentin Ackermann<sup>1,2,*</sup> and Blend Mohamad<sup>1,*</sup>, Hala El Rammouz<sup>1</sup>, Vishwajeet Maurya<sup>1</sup>, Eric Frayssinet<sup>3</sup>, Yvon Cordier<sup>3</sup>, Matthew Charles<sup>1</sup>, Gauthier Lefevre<sup>2,4</sup>, Julien Buckley<sup>1,*</sup> and Bassem Salem<sup>2,*</sup>

**Abstract:** In this work, fully vertical GaN trench MOSFETs were fabricated and characterized to evaluate their electrical performances. Transistors show a normally-OFF behavior with a high ION/IOFF (~10⁹) ratio and a significantly small gate leakage current (10⁻¹¹ A/mm). Thanks to an improved resistance partitioning method, the resistances of the trench bottom and trench channel were extracted accurately by taking into account different charging conditions. This methodology enabled an estimation of the effective channel and bottom mobility of 11.1 cm<fnref n="2" />/V·s and 15.1 cm<fnref n="2" />/V·s, respectively.

**Keywords:** GaN; MOSFET; vertical device; resistance partitioning

<figure><img src="image_3.png" /></figure>

check for
updates

**Citation:** Ackermann, V.; Mohamad, B.; El Rammouz, H.; Maurya, V.; Frayssinet, E.; Cordier, Y.; Charles, M.; Lefevre, G.; Buckley, J.; Salem, B. Mobility Extraction Using Improved Resistance Partitioning Methodology for Normally-OFF Fully Vertical GaN Trench MOSFETs. *Electronics* **2024**, *13*, 2350. https://doi.org/10.3390/electronics13122350

Academic Editors: Yimeng Zhang, Yuming Zhang and Lejia Sun

Received: 19 May 2024

Revised: 11 June 2024

Accepted: 12 June 2024

Published: 15 June 2024

<figure><img src="image_4.png" /></figure>

**Copyright:** © 2024 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).

## 1. Introduction

Over recent years, vertical gallium nitride (GaN) power transistors have demonstrated increasing potential for efficient power switching applications. The wide-bandgap GaN material is known to have superior intrinsic material properties over its silicon (Si) and silicon carbide (SiC) material counterpart. Indeed, its larger critical electric field, higher electron mobility, and higher saturation velocity favor the technological development of high breakdown voltage and low on-state resistance devices. In addition, the vertical topology is expected to be more adapted for high-power switching applications compared to the lateral one (like the HEMT), due to its capability of reaching higher breakdown voltages, its robustness to high electric fields, and its potentially higher power capability.

Nowadays, different vertical technology concepts have been under development, such as the CAVET [1,2], the semipolar gate structure [3], the fin-FET [4], or the well-known vertical power trench MOSFET [5–7]. Among these architectures, the vertical power trench MOSFET shows even higher potential regarding the benefits granted by MOS gate technology (high switching capability, low gate leakage current, gate robustness to voltage overshoot...).

To improve its quality (and also its control), different research groups have tried to fabricate vertical GaN trench MOSFETs and study the effects of MOS gate module variation on the devices’ electrical performance (p-GaN doping [8], GaN trench surface optimization [9,10], GaN trench orientation [7,11], gate stack comparison [12–14]). Some studies have demonstrated, for instance, groundbreaking results with devices showing adequate normally-OFF operation (Vth ~ 3–8 V [5,7]), very low RON,sp (<10 mΩ·cm<fnref n="2" /> [6,7]), a high ION/IOFF ratio (~10⁹), a significantly low gate leakage current (<10⁻¹¹ A·mm⁻<fnref n="1" />

<footnote n="1">¹ Univ. Grenoble Alpes, CEA, LETI, F-38000 Grenoble, France; hala.elrammouz@cea.f (H.E.R.); vishwajeet.maurya@cea.fr (V.M.); matthew.charles@cea.fr (M.C.)</footnote>

<footnote n="2">² Univ. Grenoble Alpes, CNRS, CEA/LETI Minatec, Grenoble INP, LTM, F-38054 Grenoble, France; gauthier.lefevre@cea.fr</footnote>

<footnote n="3">³ Univ. Côte d'Azur, CNRS, CRHEA, rue Bernard Grégory, 06560 Valbonne, France; eric.frayssinet@crhea.cnrs.fr (E.F.); yvon.cordier@crhea.cnrs.fr (Y.C.)</footnote>

<footnote n="4">⁴ Univ. Grenoble Alpes CEA, LITEN, F-38000 Grenoble, France</footnote>

<footnote>* Correspondence: valentin.ackermann@cea.fr (V.A.); blend.mohamad@cea.fr (B.M.); julien.buckley@cea.fr (J.B.); bassem.salem@cea.fr (B.S.)</footnote>
for instance), as well as encouraging channel mobility results (~10–130 cm²/V·s [5,7]). However, for the latter key parameter, the common methodology used in the literature to estimate it is based on the calculation of the transconductance, extracted from the transfer characteristic in the MOSFET linear stage of operation [7,10]. While this method allows us to easily extract the effective field-effect mobility on a single device, its main drawback is that it overestimates the channel mobility value considering the drift layer mobility contribution in the output current value during the mobility calculation.

On the other hand, mobility extraction methods related to the more mature lateral recessed MOS-HEMT use either the transconductance method [15,16], the Y-function method [17], or the resistance partitioning one [18,19]. For the latter method, the resistance and effective mobility are evaluated for the trench bottom and trench sidewalls separately. To do so, sheet resistance and carrier density of the different trench regions must be evaluated under the assumption of a uniform carrier density and identical electrostatic behavior between the trench bottom and trench sidewall. While this methodology can be used in the case of a lateral recessed MOS-HEMT, it is not the case for a vertical GaN MOSFET since it does not take into account the difference in electrostatic behavior between the n⁻ GaN trench bottom and the p-GaN trench sidewall is this technology.

In this study, we present an improved methodology that aims to separate the resistance contributions in the trench region and then extracts the effective mobilities of the trench channel and trench bottom. Firstly, the fabrication and electrical characterization of fully vertical GaN trench MOSFETs are reported. The transistors' key parameters are extracted by means of vertical I-V and C-V measurements, showing devices with a threshold voltage V<sub>th</sub> of ~1 V, a significantly small gate leakage I<sub>G</sub> (10<sup>-11</sup> A/mm), and adequate switching capability (I<sub>ON</sub>/I<sub>OFF</sub> ~ 10<sup>9</sup>). Then, using an improved resistance partitioning methodology that takes into account the difference in electrostatic behavior between the trench bottom and trench channel, we evaluate the effective mobilities of both of these areas as being 15.1 cm²/V·s and 11.1 cm²/V·s, respectively.

## 2. Materials and Methods

The epitaxy layers were grown on a free-standing (FS) 2-in n-type GaN wafer using metal-organic vapor phase epitaxy (MOVPE). From bottom to top, the different doped GaN layers were grown as follows: 100 nm n⁺ GaN drain layer (Si, $1 \times 10^{19} \text{ cm}^{-3}$), 10 µm n⁻ GaN drift layer (Si, $1 \times 10^{16} \text{ cm}^{-3}$), 700 nm p-GaN (Mg, $N_A - N_D = 3.5 \times 10^{18} \text{ cm}^{-3}$), and 200 nm n⁺ GaN source layer (Si, $6 \times 10^{18} \text{ cm}^{-3}$).

The process flow starts with the deposition of a 1 µm SiO₂ hardmask by PECVD. Then, the drain contact is fabricated with a Ti/Al/Ni/Au metal stack deposited on the wafer backside by e-beam evaporation. The deposition is followed by rapid thermal annealing (RTA) at 750 °C in N₂ atmosphere for 3 min 30 s.

The process continues with the patterning through photolithography of the GaN gate trench and a mesa structure that will terminate the n-p-n heterostructure. Firstly, the resist pattern is transferred into the hardmask by performing CF₄ dry etching in an inductive couple plasma reactor (ICP-RIE). Secondly, the GaN trenches and the mesa are etched to a depth of 1.1 µm through the epi layers by ICP-RIE using a Cl₂ dry-etch process. Afterwards, 10 min RTA at 600 °C in O₂ atmosphere is performed for p-GaN layer activation.

To reduce the etch-induced damages and remove the etch residues on the trench sidewalls, a HCl pre-deposition wet surface treatment is applied to the sample for 4 min at an ambient temperature. Immediately after this step, 20 nm of thermal Al₂O₃ is deposited by ALD at 300 °C using a trimethylaluminium (TMA) precursor and H₂O vapor oxidant for the deposition. A total of 40 nm of TiN is then deposited as the gate metal through sputtering. To finalize gate fabrication, the metal gate is patterned and etched on top of the mesa structures by ion beam etching (IBE). Finally, 3 min RTA at 400 °C in N₂ is performed on the sample.

The process flow is followed by the fabrication of the source contacts. A dry-etch fluorocarbide process is used to open the gate oxide as well as the SiO₂ hardmask in the
source contact region. The source contact is made of a Ti/Al metal stack defined by a lift-off step to finalize MOSFET processing.

A schematic diagram of a processed vertical MOSFET along with its top-view SEM image is shown in Figure 1a. As can be seen, the resulting MOS gate is located inside the trench as well as all around the mesas, as a consequence of the deposition and etching steps of the gate dielectric and gate metal. The dimension of the expected gate trench width ($W_{tr}$) varies from 1 to 6 µm depending on the device studied. In addition to these test structures, planar capacitors located on the drift layer are also included in the initial layout, as illustrated in Figure 1.

<figure><img src="image_5.png" /><figcaption>Figure 1. (a) A cross-sectional schematic of a given processed vertical MOSFET (device A) and planar capacitor (device B) test structures, each device being linked to their top-view SEM image (b). The main process flow steps to fabricate the vertical MOSFETs and planar capacitor test structures.</figcaption></figure>

The high-angle annular dark field (HAADF)-STEM image in Figure 2a shows the gate of a given processed trench MOSFET. While the dielectric and gate metal deposited seems sufficiently conformal with the GaN surface, etch-induced non-uniformities can still be observed along the trench sidewalls, as observed in Figure 2b.

<figure><img src="image_6.png" /><figcaption>Figure 2. HAADF-STEM images of (a) the cross-section of a given vertical MOSFET and (b) the right trench sidewall of the device.</figcaption></figure>
### 3. Results and Discussion

The transfer characteristics of a given fully vertical MOSFET are shown in Figure 3, with the current values normalized to the mesa width ($Z_{mesa}$, cf. Figure 1a). The transfer characteristic on a linear scale (Figure 3a) confirms the transistor behavior and demonstrates the normally-OFF switching operation of the device with a threshold voltage ($V_{th}$) of ~1 V, determined through extrapolation of the linear region of the characteristic at $V_D = 2$ V (correlation factor $r$ of the fitting as being around ~1). As shown in Figure 3b, the device demonstrates a good ON/OFF current ratio of $10^9$ and a significantly low gate leakage current of $10^{-11}$ A/mm, indicating the benefits of both the n-p-n heterostructure and the MOS gate building blocks. The value of the subthreshold slope calculated is around ~139 mV/dec.

<figure><img src="image_7.png" /><figcaption>Figure 3. (a) Linear and (b) semi-log transfer characteristics: gate leakage current versus applied gate voltage; (c) output characteristics of given vertical GaN-on-GaN MOSFET.</figcaption></figure>

Focusing on the $V_{th}$ value, different hypotheses can be made to explain its origins. In our case, this $V_{th}$ result could be related to the thinner gate dielectric (~20 nm) compared to what can be found in previous works (80–100 nm [6,7,20]). Also, the presence of a positive charge density trapped at the dielectric/GaN interface or inside the dielectric bulk could have a detrimental effect on the $V_{th}$ by shifting it toward negative values [21–23], thus reducing the $V_{th}$ of the device. Finally, the issue of the insufficient electrically activated Mg doping concentration is still a major process concern nowadays, since a low Mg doping concentration drastically reduces the $V_{th}$ value [6,8,24].

The normalized C-V curves related to both the MOSFET and planar capacitor are illustrated in Figure 4a. Firstly, a different capacitance behavior is clearly noticed as device A is based on charge inversion and device B on charge accumulation. Consequently, a higher $V_{th}$ is observed for device A compared to the $V_{FB}$ for device B. This result can be explained due to the p-type GaN layer integrated into the MOSFET heterostructure that should enhance the work function of the GaN and thus enhance the $V_{FB}$. A small hysteresis of ~100 and ~47 mV is shown for device A and B, respectively, suggesting a dielectric/GaN interface of good quality, despite the sidewall macroscopic roughness observed in Figure 2b.

Since the capacitance is by definition related to a variation in charge with the applied voltage $V_S$, one can calculate the charge density ($Q_c$) simply by combining the capacitance from the onset voltage value $V_{onset}$ (defined either by $V_{FB}$ (device B) or $V_{th}$ (device A)) with the maximum voltage value $V_{max}$ of the applied voltage sweep, as described in Equation (1):

$$Q_c = \int_{V_{onset}}^{V_{max}} C.dV_S \qquad (1)$$

Thus, Figure 4b represents the calculated charge density as a function of the applied voltage. Since the onset of the charge inversion ($V_{th} \sim 0.14$ V) in the channel regions for device A occurs at a different gate voltage than the charge accumulation in the bottom region ($V_{FB} \sim -2.64$ V), a difference in charge densities is clearly noticed at a given voltage value.
<figure><img src="image_8.png" /><figcaption>Figure 4. (a) The capacitance–voltage characteristics measured at 10 kHz for device A and device B (cf. Figure 1a for the schematic diagram of the test structures’ cross-section). (b) The evolution of the calculated characteristics with applied voltage, calculated at the Vth (A) or VFB (B) for the same set of devices.</figcaption></figure>

To extract the mobility contributions in the trench region, based on our test structures, we used an improved resistance partitioning method that takes into account the evolution of the output current with the gate trench width [17,18], as well as the different electrostatic conditions of device A and B illustrated in Figure 4. To do so, lateral ID–VG characteristics based on the planar MOSFET configuration were measured. In this measurement configuration, one of the source electrodes was considered the drain on our MOSFET devices, which means the current flows laterally from one source to the other.

Figure 5a shows the lateral ID – VG characteristics as a function of the gate trench width at VD = 0.5 V. A clear reduction in output current is visible when increasing the gate trench width (i.e., the trench bottom), meaning the total lateral resistance Rtot should increase as well with this parameter. Thus, in Figure 5b, a visible linear dependence of the total lateral resistance on the gate trench width can be observed (for ID values selected at VG = 3 V, symbolized by the dashed line in Figure 5a). Since the current flows laterally (Figure 5c), Rtot can be divided into different resistance contributions, defined as follows:

$$R_{\text{tot}} = 2R_{\text{S}} + 2R_{\text{ch}} + R_{\text{bot}} \cdot W_{\text{tr}} = 2(R_{\text{acc}} + R_{\text{con}}) + 2R_{\text{ch}} + R_{\text{bot}} \cdot W_{\text{tr}} \quad (2)$$

where RS is the source resistance, Racc is the access resistance, Rcon is the contact resistance, Rch is the channel resistance, and Rbot is the trench bottom resistance.

<figure><img src="image_9.png" /><figcaption>Figure 5. (a) The transfer characteristics of a lateral GaN-on-GaN MOSFET with different gate trench widths, when one of the source contacts of the MOSFET is considered the drain. (b) The evolution of the total lateral resistance with the expected gate trench width, calculated for ID values at VG = 3 V. (c) A schematic diagram of resistance partitioning around the trench area in the planar MOSFET configuration.</figcaption></figure>

The Rbot term can be directly determined by the slope of the fitted curve shown in Figure 5b and is evaluated as ~39.0 Ω·mm. The sheet resistance Rsheet,bot is then easily deduced as being around ~39.0 kΩ·sq. In addition, one can estimate through extrapolation
the resistance value for which $W_{tr}$ tends to 0 (i.e., a very thin gate), symbolized by the red cross on the y-axis. In that case, the associated resistance value is estimated at around ~179.4 Ω·mm and takes into consideration the source and channel resistance components from the left and right trench sidewalls. The source contribution $R_S$ can then be measured with transfer length measurements (TLMs), as shown in Figure 6. From these measurements, for one source electrode, the contact and access resistance contributions can be calculated, estimated as being around ~7.1 Ω·mm and ~5.9 Ω·mm, respectively.

<figure><img src="image_10.png" /><figcaption>Figure 6. Transfer length measurements on n⁺ GaN source layer of GaN-on-GaN epitaxy.</figcaption></figure>

After removing the $R_S$ contribution (measured with TLMs as being around ~13 Ω·mm for one source electrode) from the $R_{tot}$, and by considering the thickness of the p-GaN layer, we estimated a channel sheet resistance $R_{sheet,ch}$ of ~91.0 kΩ·sq.

At this point, since the resistance contributions and the charge densities are known, one can extract the mobilities ($\mu$) from the trench bottom and trench channel areas with Equation (3):

$$ \mu = \frac{1}{QR_{\text{sheet}}} = \frac{1}{qNR_{\text{sheet}}} \qquad (3) $$

where $\rho$ is the material resistivity, $Q$ is the charge density, $q$ is the elemental charge, $N$ is the charge carrier density, and $R_{sheet}$ is the sheet resistance. The charge density and the charge carrier density values chosen for devices A and B correspond to those selected at $V_S = 3$ V by the black dashed line in Figure 4b (i.e., the same gate voltage used for the previous $R_{tot}$ calculation in Figure 5b). Finally, synthesis of the main parameters extracted from resistance partitioning (cf. Figure 5) and the C-V measurements (cf. Figure 4) is exposed in Table 1.

<table><caption>**Table 1.** Synthesis of parameters extracted from improved resistance partitioning method for trench bottom and trench sidewall areas.</caption><thead><tr><th>Trench Area</th><th>Sheet Resistance (kΩ·sq)</th><th>Q (C·cm<sup>-2</sup>)</th><th>N (cm<sup>-2</sup>)</th><th>μ (cm<sup>2</sup>/V·s)</th></tr></thead><tbody><tr><td>Channel</td><td>~91.0</td><td>9.86 × 10<sup>-7</sup> (A)</td><td>6.15 × 10<sup>12</sup> (A)</td><td>11.1</td></tr><tr><td>Bottom</td><td>39.0</td><td>1.70 × 10<sup>-6</sup> (B)</td><td>1.06 × 10<sup>13</sup> (B)</td><td>15.1</td></tr></tbody></table>

Consequently, applying Equation (3) with the parameters in Table 1 leads to the extraction of the effective trench bottom and channel mobilities of 15.1 and 11.1 cm²/V·s, respectively. As explained in [25], this poor channel mobility value could be mainly related to the damaged trench sidewalls following the GaN trench etching step, which is a critical process step for the fabrication of vertical GaN trench MOSFETs [7,26,27]. This should result, on the one hand, in carrier scattering coming from surface roughness (as seen in Figure 2b), and on the other hand, in oxide interface traps at the dielectric/GaN interface, significantly reducing channel mobility.
Finally, a way higher channel mobility of 30 cm²/V·s is obtained when using the transconductance method defined as follows:

$$ \mu_{ch} = g_m \cdot \frac{L}{Z} \cdot \frac{1}{C_{ox}} \cdot \frac{1}{V_D} \quad (4) $$

where $g_m$ is the transconductance, $L$ is the channel width of 200 µm, $Z$ is the channel length of 0.7 µm, $C_{ox}$ is the gate oxide conductance of 354.8 nF.cm⁻², and $V_D$ is the drain voltage defined at 1 V. This low channel mobility is in agreement with the values reported in the literature for state-of-the-art vertical GaN MOSFETs. Indeed, among the research groups that extracted the mobility using the transconductance method, studies from Khadar et al. [7], Ishida et al. [10], and Zhu et al. [28] have fabricated vertical GaN MOSFETs that demonstrate channel mobilities ranging from 15 to 41 cm²/V·s, while the current record has been reached by Otake et al. [5], with a channel mobility of ~131 cm²/V·s.

Consequently, the mobility results estimated in this study pave the way for further improvements, especially by applying a finer post-etch GaN surface treatment to mend the trench sidewalls from etching damages [10], or by improving the critical dielectric/GaN interface with a higher-quality gate dielectric [13].

## 4. Conclusions

This study aimed to evaluate the electrical performances of a fully vertical GaN trench by means of I-V and C-V measurements. We first proved the normally-OFF behavior ($V_{th} \sim 1$ V), the adequate switching operation ($I_{ON}/I_{OFF} \sim 10^9$), as well as the significantly small gate leakage current ($10^{-11}$ A/mm) of our devices. Then, the resistances of the trench bottom and trench channel were also extracted using an improved resistance partitioning method. Subsequently, by considering the difference in electrostatic behavior between the devices linked to these trench areas, we estimated the effective channel and bottom mobilities to be 11.1 cm²/V·s and 15.1 cm²/V·s, respectively. These mobility values are promising and act as a starting point to be improved upon thanks to the optimization of the gate module, with, for instance, a well-controlled trench etching process, a better pre-deposition GaN surface treatment, or the integration of an alternative alumina dielectric into the MOS gate.

**Author Contributions:** Conceptualization, V.A., H.E.R., V.M., E.F., Y.C., M.C., J.B., and B.S.; methodology, V.A. and B.M.; investigation, V.A., B.M., B.S., and J.B.; writing—original draft preparation, V.A.; writing—review and editing, V.A., B.M., H.E.R., V.M., E.F., Y.C., M.C., G.L., J.B., and B.S.; visualization, V.A.; supervision, B.S., B.M., and J.B. All authors have read and agreed to the published version of the manuscript.

**Funding:** This study was partially supported by the Labex GANEXT (ANR-11-LABX-0014), the VERTIGO project supported by the French Agence Nationale de la Recherche as part of France 2030 with reference ANR-22-PEEL-0004, and the French RENATECH network through the PTA technological platforms.

**Data Availability Statement:** The original contributions presented in the study are included in the article, further inquiries can be directed to the corresponding authors.

**Conflicts of Interest:** The authors declare no conflicts of interest.

## References

1. Ji, D.; Laurent, M.A.; Agarwal, A.; Li, W.; Mandal, S.; Keller, S.; Chowdhury, S. Normally OFF Trench CAVET With Active Mg-Doped GaN as Current Blocking Layer. *IEEE Trans. Electron Devices* **2017**, 64, 805–808. [CrossRef]

2. Nie, H.; Diduck, Q.; Brian, A.; Edwards, A.P.; Kayes, B.M.; Zhang, M.; Ye, G.; Prunty, T.; Bour, D.; Kizilyalli, I.C. 1.5-kV and 2.2-mΩ.Cm² Vertical GaN Transistors on Bulk-GaN Substrates. *IEEE Electron Device Lett.* **2014**, 35, 939–941. [CrossRef]

3. Shibata, D.; Kajitani, R.; Ogawa, M.; Tanaka, K.; Tamura, S.; Hatsuda, T.; Ishida, M.; Ueda, T. 1.7 KV/1.0 MΩcm² Normally-off Vertical GaN Transistor on GaN Substrate with Regrown p-GaN/AlGaN/GaN Semipolar Gate Structure. In Proceedings of the 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 3–7 December 2016; IEEE: Piscataway, NJ, USA, 2016. [CrossRef]
4. Zhang, Y.; Sun, M.; Perozek, J.; Liu, Z.; Zubair, A.; Piedra, D.; Chowdhury, N.; Gao, X.; Shepard, K.; Palacios, T. Large Area 1.2 KV GaN Vertical Power FinFETs with a Record Switching Figure-of-Merit. *IEEE Electron Device Lett.* **2018**, *40*, 1. [CrossRef]

5. Otake, H.; Chikamatsu, K.; Yamaguchi, A.; Fujishima, T.; Ohta, H. Vertical GaN-Based Trench Gate Metal Oxide Semiconductor Field-Effect Transistors on GaN Bulk Substrates. *Appl. Phys. Express* **2018**, *1*, 011105. [CrossRef]

6. Oka, T.; Ina, T.; Ueno, Y.; Nishii, J. 1.8 MΩ·cm 2 Vertical GaN-Based Trench Metal-Oxide-Semiconductor Field-Effect Transistors on a Free-Standing GaN Substrate for 1.2-KV-Class Operation. *Appl. Phys. Express* **2015**, *8*, 054101. [CrossRef]

7. Khadar, R.A.; Liu, C.; Soleimanzadeh, R.; Matioli, E. Fully Vertical GaN-on-Si Power MOSFETs. *IEEE Electron Device Lett.* **2019**, *40*, 443-446. [CrossRef]

8. Zhu, R.; Jiang, H.; Tang, C.W.; Lau, K.M. Effects of P-GaN Body Doping Concentration on the ON-State Performance of Vertical GaN Trench MOSFETs. *IEEE Electron Device Lett.* **2021**, *42*, 970-973. [CrossRef]

9. Kodama, M.; Sugimoto, M.; Hayashi, E.; Soejima, N.; Ishiguro, O.; Kanechika, M.; Itoh, K.; Ueda, H.; Uesugi, T.; Kachi, T. GaN-Based Trench Gate Metal Oxide Semiconductor Field-Effect Transistor Fabricated with Novel Wet Etching. *Appl. Phys. Express* **2008**, *1*, 021104. [CrossRef]

10. Ishida, T.; Nam, K.P.; Matys, M.; Uesugi, T.; Suda, J.; Kachi, T. Improvement of Channel Property of GaN Vertical Trench MOSFET by Compensating Nitrogen Vacancies with Nitrogen Plasma Treatment. *Appl. Phys. Express* **2020**, *13*, 124003. [CrossRef]

11. Gupta, C.; Chan, S.H.; Lund, C.; Agarwal, A.; Koksaldi, O.S.; Liu, J.; Enatsu, Y.; Keller, S.; Mishra, U.K. Comparing Electrical Performance of GaN Trench-Gate MOSFETs with a-Plane and m-Plane Sidewall Channels. *Appl. Phys. Express* **2016**, *9*, 121001. [CrossRef]

12. Mukherjee, K.; De Santi, C.; Borga, M.; You, S.; Geens, K.; Bakeroot, B.; Decoutere, S.; Meneghesso, G.; Zanoni, E.; Meneghini, M. Use of Bilayer Gate Insulator in GaN-on-Si Vertical Trench MOSFETs: Impact on Performance and Reliability. *Materials* **2020**, *13*, 4740. [CrossRef] [PubMed]

13. Goncalez Filho, W.; Borga, M.; Geens, K.; Cingu, D.; Chatterjee, U.; You, S.; Bakeroot, B.; Decoutere, S.; Knaepen, W.; Arnou, P.; et al. AlON gate dielectric and gate trench cleaning for improved reliability of vertical GaN MOSFETs. In Proceedings of the CIPS 2022; 12th International Conference on Integrated Power Electronics Systems, Berlin, Germany, 15–17 March 2022; pp. 1–5.

14. Zhu, R.; Jiang, H.; Tang, C.W.; Lau, K.M. Enhancing ON- and OFF-State Performance of Quasi-Vertical GaN Trench MOSFETs on Sapphire With Reduced Interface Charges and a Thick Bottom Dielectric. *IEEE Electron Device Lett.* **2022**, *43*, 346–349. [CrossRef]

15. Wang, Y.; Wang, M.; Xie, B.; Wen, C.P.; Wang, J.; Hao, Y.; Wu, W.; Chen, K.J.; Shen, B. High-Performance Normally-Off Al₂O₃/GaN MOSFET Using a Wet Etching-Based Gate Recess Technique. *IEEE Electron Device Lett.* **2013**, *34*, 1370–1372. [CrossRef]

16. Hu, Q.; Hu, B.; Gu, C.; Li, T.; Li, S.; Li, S.; Li, X.; Wu, Y. Improved Current Collapse in Recessed AlGaN/GaN MOS-HEMTs by Interface and Structure Engineering. *IEEE Trans. Electron Devices* **2019**, *66*, 4591–4596. [CrossRef]

17. Le Royer, C.; Mohamad, B.; Biscarrat, J.; Vauche, L.; Escoffier, R.; Buckley, J.; Becu, S.; Riat, R.; Gillot, C.; Charles, M.; et al. Normally-OFF 650V GaN-on-Si MOS-HEMT Transistor: Benefits of the Fully Recessed Gate Architecture. In Proceedings of the 2022 IEEE 34th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Vancouver, BC, Canada, 22–25 May 2022; IEEE: Piscataway, NJ, USA, 2022; pp. 49–52. [CrossRef]

18. Kammeugne, R.K.; Leroux, C.; Cluzel, J.; Vauche, L.; Le Royer, C.; Krakovinsky, A.; Gwoziecki, R.; Biscarrat, J.; Gaillard, F.; Charles, M.; et al. Accurate Statistical Extraction of AlGaN/GaN HEMT Device Parameters Using the Y-Function. *Solid-State Electron.* **2021**, *184*, 108078. [CrossRef]

19. Piotrowic, C.; Mohamad, B.; Fernandes Paes Pinto Rocha, P.; Malbert, N.; Ruel, S.; Pimenta-Barros, P.; Jaud, M.-A.; Vauche, L.; Le Royer, C. Impact of Gate Morphology on Electrical Performances of Recessed GaN-on Si MOS Channel-HEMT for Different Channel Orientations. In Proceedings of the 2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Hong Kong, 28 May–1 June 2023; IEEE: Piscataway, NJ, USA, 2023; pp. 382–385. [CrossRef]

20. Ruzzarin, M.; Geens, K.; Borga, M.; Liang, H.; You, S.; Bakeroot, B.; Decoutere, S.; De Santi, C.; Neviani, A.; Meneghini, M.; et al. Exploration of Gate Trench Module for Vertical GaN Devices. *Microelectron. Reliab.* **2020**, *114*, 113828. [CrossRef]

21. Esposto, M.; Krishnamoorthy, S.; Nath, D.N.; Bajaj, S.; Hung, T.-H.; Rajan, S. Electrical Properties of Atomic Layer Deposited Aluminum Oxide on Gallium Nitride. *Appl. Phys. Lett.* **2011**, *99*, 133503. [CrossRef]

22. Bisi, D.; Chan, S.H.; Liu, X.; Yeluri, R.; Keller, S.; Meneghini, M.; Meneghesso, G.; Zanoni, E.; Mishra, U.K. On Trapping Mechanisms at Oxide-Traps in Al2O3/GaN Metal-Oxide-Semiconductor Capacitors. *Appl. Phys. Lett.* **2016**, *108*, 112104. [CrossRef]

23. Rrustemi, B.; Piotrowicz, C.; Jaud, M.-A.; Triozon, F.; Vandendaele, W.; Mohamad, B.; Gwoziecki, R.; Ghibaudo, G. Effect of Doping on Al2O3/GaN MOS Capacitance. *Solid-State Electron.* **2022**, *194*, 108356. [CrossRef]

24. Götz, W.; Johnson, N.M.; Walker, J.; Bour, D.P.; Street, R.A. Activation of Acceptors in Mg-Doped GaN Grown by Metalorganic Chemical Vapor Deposition. *Appl. Phys. Lett.* **1996**, *68*, 667–669. [CrossRef]

25. Treidel, E.B.; Hilt, O.; Hoffmann, V.; Brunner, F.; Bickel, N.; Thies, A.; Tetzner, K. On the Conduction Properties of Vertical GaN N-Channel Trench MISFETs. *IEEE J. Electron Devices Soc.* **2021**, *9*, 215–228. [CrossRef]

26. Zhang, Y.; Sun, M.; Liu, Z.; Piedra, D.; Hu, J.; Gao, X.; Palacios, T. Trench Formation and Corner Rounding in Vertical GaN Power Devices. *Appl. Phys. Lett.* **2017**, *110*, 193506. [CrossRef]
27. Yamada, S.; Sakurai, H.; Osada, Y.; Furuta, K.; Nakamura, T.; Kamimura, R.; Narita, T.; Suda, J.; Kachi, T. Formation of Highly Vertical Trenches with Rounded Corners via Inductively Coupled Plasma Reactive Ion Etching for Vertical GaN Power Devices. *Appl. Phys. Lett.* **2021**, *118*, 102101. [CrossRef]

28. Zhu, R.; Jiang, H.; Tang, C.W.; Lau, K.M. GaN quasi-vertical trench MOSFETs grown on Si substrate with ON-current exceeding 1A. *Appl. Phys. Express* **2022**, *15*, 121004. [CrossRef]

**Disclaimer/Publisher's Note:** The statements, opinions and data contained in all publications are solely those of the individual author(s) and contributor(s) and not of MDPI and/or the editor(s). MDPI and/or the editor(s) disclaim responsibility for any injury to people or property resulting from any ideas, methods, instructions or products referred to in the content.