readout neurons, the pipeline depth is the depth of the adder-tree, as there is no threshold, firing and leakage. After that, the pipeline depth of the comparator is the depth of the tree of maximum operators.

$$ \Delta T_{\text{pipe}}^{\text{Readout}} = \log2(N^{\text{input}}) + \log2(N^{\text{output}}) \qquad (7.10) $$

Where $N^{output}$ is the number of output neurons. Those equations have been validated through hardware simulation.

## 7.4 Conclusions & Outlooks

In this chapter, we have described a novel model of SNNs proposed by Neftci et. al. in [32]. The model represents the network of LIF neurons as a Recurrent Neural Network (RNN) in order to use a variant of the Backpropagation Through Time algorithm: the Surrogate Gradient Learning. This model was adapted and simplified by Zimmer et. al. in the S2NET framework, which provides GPU-accelerated Surrogate Gradient Learning on timestep-constrained SNNs. This model uses the Send-on-Delta spike encoding method, whose parameters are also learned during training. Thanks to those features, the resulting SNN demonstrates lower Synaptic Activity Ratio than conversion and rate-coding on the benchmark of static datasets (Chapter 4). That is while maintaining acceptable or better accuracy than the previous technique used in this thesis. Moreover, the literature now describes state-of-the-art accuracy using this method.

The PADS architecture has been adapted to the S2NET SNN model, notably through adding a leakage factor to the membrane potential and integrating spike encoding in a layer of FISO neurons. PADS-V2 benefits from the fixed and low number of timesteps thanks to a fully-parallel implementation and an end-to-end pipeline. In doing so, the architecture achieves drastically reduced inference times compared to PADS-V1. On a 784-100-10 MLP applied to MNIST dataset, PADS-V2 demonstrates a constant inference time of 39 clock cycles per image. On the other hand, PADS-V1 implies variable inference time for an average 15 000 clock cycles. Thus, the time-constrained SNN model seems more adapted to hardware implementation, and could leverage drastic energy savings. However, further work is required to deploy the architecture in hardware and measure resource, power and energy consumption.

Moreover, PADS-V2 remains a prototype: an operational architecture should involve an intermediate level of parallelism. Indeed, a fully-parallel implementation like PADS is not realistic to deploy state-of-the-art models with several millions of neurons. Like explained in Chapter 5, parallelism can be tailored at layer level according to SAR: layers with higher SAR are implemented with more parallel NPUs than others. Such intermediate level of parallelism will be addressed in further works.
# Chapter 8

## Conclusions and outlooks

The field of Neuromorphic Computing has emerged recently as an answer to the energy requirements of Deep Learning models in view of their deployment in embedded systems. Deep neural networks are particularly appealing for autonomous and smart devices. Through the use of bio-inspired spiking neurons, the goal of Neuromorphic Computing is to leverage energy savings in hardware neural network accelerators. This widespread approach in the literature relies on the strong hypothesis that the biological brain draws its energy efficiency from spike-based processing. Those expectations are backed by the respective computational costs of formal and spiking neurons: the accumulation operation of the latter is more hardware-friendly than the multiplication-accumulation operation of formal neurons. Moreover, the sparsity of spike encoding enables a sparse computation, i.e. the system is only active upon receiving information. That is, in contrast with FNN in which computation does not depend on data. Additionally, the lightweight communication between neurons should further reduce the hardware footprint of spiking implementations. However, to the best of our knowledge, there was a lack of fair, extensive and quantitative comparison between formal and spiking accelerators in the literature. This matter was the main topic of the thesis: determine and quantify the potential energy savings offered by Neuromorphic Computing.

In the literature, it appeared that the number of spikes generated by the network (i.e spiking activity) is often considered as a reliable high-level metric to assess energy consumption of spiking hardware accelerators relatively to an FNN baseline. This approach is based on the number of synaptic operations (MAC in formal neurons, ACC in spiking ones). However, the correlation between this metric and the actual energy consumption of SNNs remained unclear, and unproven when we started our study. Therefore, one other goal of this thesis was to propose a finer energy consumption model based on synaptic activity and confront the results with actual energy measurements.

Additionally, the last important goal of this thesis was to propose a cartography of applications and neural coding domains, in order to find specific use-cases in which neuromorphic acceleration could bring game-changing energy savings for deployment in embedded systems. In addition to exploring application cases, we were interested in finding "conditions" that enhance the energy savings of spiking implementations. Those conditions vary from the resolution of input data, the quantity of classes, the distribution of pixels... In other words, one of our concerns was to determine what makes an application suitable for spiking domain.

### 8.1 Conclusion

In this thesis, we have chosen to primarily address rate-coded Spiking Neural Networks and conversion training techniques, since those two methods were the most widespread and documented in the literature. Moreover, this family of SNNs is supported by several machine learning frameworks like N2D2. Several contributions were proposed to fulfill the thesis goals and answer its initial
questions.

First, we have proposed a high-level energy estimation model for FPGA neural network accelerators. This model is based on the Synaptic Activity Ratio metric (number of spike per synapse), and a modeling of MAC and ACC implementations on FPGA. The model proposes to compute the ratio of energy consumption between a MAC and ACC operations in a specific design, for a specific target board. This value, $\lambda$, depends on the saturation of DSP resources in the FPGA. If the average number of spike per synapses (SAR) is greater than $\lambda$, this means that the model is not suited for spiking acceleration. Thanks to this comparison method, one can rapidly determine which type of application seems suitable for spiking acceleration. The model was confronted to energy estimations on a few datasets. On most tested cases, for fully-parallel architectures, the SAR&$\lambda$ model accurately predicted the preferable coding domain in terms of energy consumption. That was not the case for fully-sequential architectures, since the two implementations (SPLEAT and C-HLS) have two much different low-level design choices (pipeline). On the other hand, the model is not quantitatively correlated with the estimated ratios of energy consumption. Our hypothesis is that the model does not take the temporal sparsity of spikes into account, which is a strong bias considering that the tested architectures maintain their power consumption in idle state (i.e. between two spikes). This matter will be addressed further in the outlooks.

Second, we have proposed a framework for estimation of logic resource usage, power consumption, inference time and energy of FPGA neural network accelerators. This framework is based on the interpolation of a hardware-footprint database and low level simulation of spiking inference. It is able to determine the hardware footprint of a typical spiking or formal hardware accelerator, under high or low levels of parallelism. In doing so, the goal is not to provide an absolute estimation of hardware footprint, but rather to facilitate the rapid comparison of coding domains and levels of parallelism in the application space. Thanks to the framework, the cartography of neural coding domain and architectural choices on a benchmark of seven datasets was possible in a few hours. Without the framework, this study could have taken hundreds of hours of synthesis, simulation and result extraction. Using our framework, the extensive comparison of hardware FNNs and SNNs has shown that spikes are not always better in terms of energy consumption (far from it). Indeed, the temporal sparsity of rate-coded spike trains causes a substantial overhead in inference time, and in turns, in energy consumption. To cope with this issue, specific strategies have to be settled, like reducing temporal sparsity of spikes or number of spikes per synapses. The estimation framework led to a publication in ACM Transaction on Embedded Computing Systems, Special Issue : Accelerating AI on the edge [112].

To answer this matter, we have proposed two different approaches. On the one hand, this thesis is among the first to study the concept of neural network hybridization. The motivations for this approach are numerous: tailoring the neural coding domain to layer-wise synaptic activity, using the formal feature-extraction stage as a pre-processing to lower resolution and widen data distribution. Both energy estimations and hardware implementations demonstrate that this approach could indeed leverage energy savings where spiking domain alone could not. Our hybrid architecture led to a publication in ISCAS 2020 conference [113], and to a use-case chapter in the Tulipp Book [114]. On the other hand, we use our high-level SAR-based energy model to find a more suitable family of SNN models. In doing so, we address the timestep-constrained SNNs trained through Surrogate Gradient Learning proposed for the very first time in 2019 by Neftci et. al.. This family of model demonstrates lower SAR and spike temporal sparsity than rate-based approaches, while offering state-of-the-art classification accuracy. We proposed an hardware accelerator based on this family of SNN models (PADS-V2), and obtained substantially lower inference time than with the former rate-coding and conversion approach. Hence, this approach seems
promising to reduce the energy consumption of neuromorphic implementations. In PADS V2 im-
plementation, we used the FISO neuron model which was patented during the first year of this
thesis. The PADS V2 implementation will be the main topic of an upcoming conference paper.

Additionally, this thesis has led to the deployment of the first ever neuromorphic accelerator in space, as well as the first hybrid accelerator, on-board ESA's OPS-SAT experimental satellite. The satellite was launched in December 2019, and the VGT-PADS hybrid architecture (Chapter 6) was successfully tested in-flight. This world premiere was achieved in collaboration with IRT Saint-Exupéry and CIAR project. This led to a publication for the European OBDP workshop [93].

Lastly, one of the main assessments of this work is that rate-coding is not suited to energy efficiency in digital neuromorphic circuits compared to classical floating-point approaches. As demonstrated in Chapter 5, rate-coding often leads to an energy consumption overhead, whether due to the number of operations (i.e. number of spikes) or to the temporal sparsity of spikes. The latter implies a higher inference time, and an energy overhead due to both idle and static power consumptions (particularly on FPGAs). However, those conclusions are not inevitably true for SNNs in general, since other methods than rate-coding exists. Other encoding schemes should be studied in this regard, such as temporal [68] or rank-order [66] coding. While reducing the number or temporal sparsity of spikes, those methods are also more biologically plausible. They indeed reproduce the mechanism observed in retina sensory fibers since they are interpreted as intensity-to-latency encoders [115]. Addressing temporal and rank-order encoding is therefore coherent with the bio-inspiration approach of neuromorphic engineering, in our hunt for brain-inspired energy efficiency.

8.2 Outlooks

All along this document, retrospective analysis of our development and results have led to several
short-term outlooks. Those propositions are either intended to strengthen our results, or to delve
deeper on some aspects that were left apart.

8.2.1 Short term and work-specific perspectives

Since PADS and SPLEAT are two prototypes with extreme (high and low) levels of parallelism,
those are only laboratory prototypes unsuitable for state-of-the-art model emulation or opera-
tional deployment. Hence, one of the first short-term development to make is the development
of a neuromorphic accelerator featuring an intermediate, configurable levels of parallelism. For
example, such an architecture might be based on the SPLEAT Neural Processing Core, which is
already adapted to multiplexing. The goal is therefore to deploy several SPLEAT cores in parallel
for each layer. Since we have found that SAR was an indicator of parallelism requirements, it can
be used to determine the optimal number of parallel cores in each layers. Thus, further studies
on the relation between SAR and parallelism requirements will be addressed in further works.
Similarly, the exploration of intermediate levels of parallelism might also be a future feature of the
hardware-footprint and energy estimation framework. In doing so, the framework can estimate
energy consumption for parallelism configuration, allowing to find a Pareto-optimal solution. Ad-
ditionally, the architecture should be adapted to the timestep-constrained SNN model [32] [21]
studied in Chapter 7, rather than the original rate-based model it was designed for. The goal is
indeed to benefit from the temporal compactness and low SAR of such novel SNN models.
Moreover, we are also interested in improving further the SAR metric and the subsequent high-level energy model. The SAR metric must take the temporal sparsity of spikes into account to provide a quantitative estimation of energy ratios. Indeed, the current approach neglects the idle power usage of hardware architectures, which represents an important part of the overall energy consumption. Indeed, our measurements have shown that the idle dynamic power usage (i.e. dynamic component of power consumption of a neural core waiting for input spikes) was nearly as high as the active dynamic power usage (i.e. dynamic component of a neural core actively processing spikes). That is mostly due to the clock toggle signals, which are independent from the presence or absence of input stimuli. In temporally sparse SNNs, idle state represents a large portion of time in each neurons, which should be accounted for in the SAR metric. The effect of idle state is less of a problem in temporally compact SNNs. However, if there is no mean to decrease temporal sparsity of spikes in a given application, the problem might also be addressed the other way around. Instead of adapting the metric, a clock-gating mechanism in the architecture could preclude the influence of dynamic power consumption in idle state. By deactivating the clock signals locally when a core is in idle state, such low-level optimization could provide substantial energy savings in neuromorphic implementations. Moreover, the result would be closer to the SAR-based model.

Additionally, this study has shown that FPGA was not the best suited device for neuromorphic acceleration. That is because of the large static power consumption which has two noticeable effects. First, the static power offset masks the dynamic power savings, particularly for small designs in which the dynamic component of power consumption is negligible in front of the other (on Zedboard). Preliminary experiments targeting other and larger boards have shown the same issue, if not worse. Second, a high static power consumption further penalizes the energy cost of idle state in temporally sparse SNNs (rate-coding & conversion). Clock-gating can drastically reduce the dynamic power usage in idle state, but not the static component. One way to cope with this issue is to address Application Specific Integrated Circuits (ASICs), which demonstrate much lower static power consumption. ASICs are integrated circuits specifically manufactured according to the RTL description, in contrast with FPGAs which are array of re-configurable elements. The hardware of ASICs being dedicated and specific, the static power consumption can be much lower. The deployment of neuromorphic accelerators on ASICs rather than FPGAs could therefore enhance the low-power capabilities of spiking neurons, and in turns leverage the expected energy savings.

Furthermore, this study focuses on feed-forward CNN architectures. In future works, we will extend our cartography of neural coding domains to other models, such as Recurrent Neural Network, Reservoir Computing or Residual architectures. Lastly, one of the most promising application of Spiking Neural Networks are their use in combination with Dynamic Vision Sensors (i.e. Event-based cameras). Therefore, the neuromorphic acceleration applied to event-based sensors will be addressed in further work.

### 8.2.2 Middle term outlooks and insights

We certainly still have a lot to learn from the energy efficiency of our biological brain. Since it is the most efficient (by far) neural processor anyone has ever heard of, taking inspiration from Neurosciences models must be a fruitful approach. The most important thing to learn from this thesis is: using a naive approach of hardware implementation is not sufficient to benefit from the energy efficiency of spike encoding. Three major necessary conditions to take advantage from spikes were identified in this work.
* First, the number of spikes can compensate the energy efficiency of the ACC operation over the MAC. Therefore, the SAR should be studied to evaluate the potential energy savings brought by spiking acceleration for a given neural network model and application.

* Second, one must ensure of the temporal compactness of spike encoding, since the idle energy consumption (i.e. waiting between spikes) can compensate the energy savings obtained on active processing.

* Third, when temporal sparsity of spikes is not an option (in specific application cases for example), systems should involve a clock-gating mechanism to preclude idle energy consumption.

* Fourth and last, ASIC technology seems more suited to neuromorphic acceleration than FPGAs. That is thanks to the lower static power consumption of ASICs. Indeed, this feature enhances the dynamic power savings offered by the spiking synaptic operation, and further reduces the idle dynamic power consumption.

When looking towards ASICs and power-gating techniques, a particularly appealing emerging technology arises from literature: Non Volatile RAM devices (NVRAM) [116]. This technology is able to retain information when turned off like an hard drive, but offers much faster read and right accesses. Using this RAM technology, parts of the system can be instantly turned off and on for a strong and efficient power-gating: idle neurons can be turned-off while waiting for input spikes. Moreover, NVRAMs demonstrate very low, if not negligible energy consumption compared to standard RAM technologies. Some specific types of NVRAMs, such as RRAMs [117] or STT-RAMs [118] [119], have even more appealing features for Neuromorphic Computing. Indeed, such devices are able to physically emulate synapses: their internal resistivity can be tuned according to the intensity of current passing through. This mechanism is analogous to synaptic plasticity, and this devices are better known under the name of Memristor [120]. Using Memristor crossbar arrays, researchers are currently working on emulating simple neural networks and even local learning rules like Spike Time Dependent Plasticity [121] [122] [123]. This technology promises a breakthrough reduction of energy consumption in neuromorphic systems [124] [125]. However, this field of research is still in its very early stages, since the Memristor technology itself is very immature. The intrinsic variability of the production method, and the difficulty to stabilize them on large scales are still limiting the technology deployment. The latest experiments on Memristor crossbars only involve a few dozens of synapses, which is far from supporting basic CNN models, let alone state-of-the-art Deep Learning topologies. Still, the Logic-in-Memory approach of this emerging field of research could be the key to the brain-inspired energy efficiency.
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# APPENDIX 1: CIAR project

The CIAR (Autonomous and Reactive Image Chain) project [126] is a project led by Saint-Exupery Technical Research Institute (IRT) involving several private and public research partners, including ActiveEon, AViSTO, ELSYS Design, GEO4i, Thales Alenia Space and the LEAT laboratory. The CIAR project is dedicated to the development of Neural Network accelerators for on-board satellite image processing, targeting OPS-SAT Cyclone V SoC. This project has an access to the OPS-SAT platform provided by ESA. The CIAR project thus represents a valuable opportunity for architecture testing in real-world conditions.

The CIAR project use-case answers to a very concrete problem for observation satellites: the limited communication bandwidth between the satellite and its ground control. Indeed, imaging satellites role is to take high-resolution pictures of the Earth from space. Those pictures are then sent to the ground for exploitation. However, the bandwidth between the satellite and its ground station is very limited. Thus, sending high-resolution pictures is not a trivial concern and sending useless images should be avoided.

The specific use-case of the CIAR project is to automatically segment clouds on pictures. In doing so, the system is able to extract the parts where the ground is visible. Using this method, only useful information is sent to the ground to help relieve the communication bandwidth. Therefore, our goal is to build a cloud segmentation system and deploy it on the OPS-SAT SoC. The system separates full-size (1920x1080p) images in 28x28p patches, and classifies each as "cloud" or "no-cloud". The results are recombined after classification to form full-size cloud segmentation maps. The cloud segmentation process is illustrated in Figure 1. The original picture is on the left. On the right, patches classified as cloud appear in yellow.

Several Artificial Neural Networks models and hardware architectures have been developed to address the cloud classification task. Each model has been evaluated in terms of performance, resource and power usage, execution time and energy consumption. The goal is to determine which type of application would suit best to the cloud segmentation use-case in the context of highly constrained satellite systems. The various Neural Network models are:

* LeNet CNN architecture designed using VGT generator (Section 2.2.2.1),

* Spiking Multilayer Perceptron coded by hand in VHDL (PADS architecture),

* Tiny-Yolo CNN architecture generated using VGT,

* Fully-Convolutional Neural Network (FCN) architecture without fully-connected layers generated using VGT,

* Spiking CNN (S-CNN) coded by hand in VHDL.

* Hybrid Neural Network (HNN) mixing VGT-generated and hand-coded VHDL.

## OPS-SAT LIST OF MODULES:

* The Satellite Experimental Processing Platform (SEPP): an Altera Cyclone V System-on-Chip (SoC), also called MitySOM, with large memory capabilities in order to support advanced software and hardware experiments. This SoC is made of an FPGA Fabric, a dual-
<figure><img src="image_84.png" /><figcaption>Figure 1: Illustration of the CIAR cloud segmentation task. On the left, the original image taken by OPS-SAT. On the right, the resulting segmentation map, with cloudy patches in yellow. Source: [15]</figcaption></figure>

core ARM Cortex-A9 CPU, 1GB of on chip DD3 memory and 8GB of additional external memory. The board uses 5W in average.

* Optical Camera: a BST IMS-100 camera designed specifically for space applications. At an altitude of 600km, the camera has a field of view of 135 × 105kms, with a resolution of 53m.

* Fine Attitude Control and Determination System (ACDS): a system composed of sun sensors and gyroscopes to measure and control the attitude of the satellite.

* Optical Receiver: a laser communication receiver, embedded for the first time in a CubeSat.

* Software Defined Radio (SDR) front-end: a radio communication system where hardware components (amplifiers, filters, mixers...) have been replaced by software elements. The SDR is used to measure the level of interference in various communication experiments.

* GPS for satellite localization.

* S-Band, X-Band and UHF antennas for communication with the ground base.
# APPENDIX 2: Custom SoC platform

In order to test and deploy PADS on FPGA, a custom SoC platform was designed targeting Xilinx Zynq UltraScale+ (ZUS+) boards. An overview of the SoC architecture is provided in Figure 2. The platform has been developed to validate the architecture in hardware, and serve as a testbench for hardware measurement of power consumption. However, probing power on FPGA devices requires specific knowledge and material that were not immediately available. Therefore, this aspect was let aside in the thesis. However, hardware measurements using the custom SoC architecture should take place in further works. Moreover, the platform will be used in other projects at the laboratory and support other FPGA accelerators in further works.

The SoC involves 3 distinct elements:

* The embedded CPU (ARM Cortex A53 MPCore) of the ZUS+ SoC

* The embedded Memory (RAM DDR) of the ZUS+ SoC

* The embedded FPGA (Programmable Logic) of the ZUS+ SoC

The CPU is used to control and exchange data with the Neuromorphic Accelerator synthesized on the FPGA. The FPGA and the CPU are connected through an AXI bus. In the following subsections, each element of the platform is described in details.

## 1 Programmable Logic modules

PADS is integrated in the system as an AXI Stream slave peripheral. In doing so, an AXI Stream slave port is added to the IP. Input samples are streamed to PADS trough the AXI Stream interface. Moreover, the AXI Stream slave port is customized for the architecture. First, the data is arranged in a pixel by pixel stream as required by the GenCell (3.1.1). Second, the interface manages PADS control signals and ensures synchronization. The interface also manages the *stop_network*, which triggers a reset signal for PADS.

Additional Xilinx built-in modules are added to the design. For instance, GPIO and AXI Direct Memory Access (DMA) cores are used. The GPIO core provide an interface between external signals of PADS (*o_class* and *stop_network*) and the memory-mapped AXI bus. It should be noted that the *stop_network* GPIO is configured to enable CPU interruption. The AXI DMA core provides a direct interface between the DDR memory and AXI Stream slave peripherals through the memory-mapped AXI bus. The AXI DMA is used to transfer the input samples stored in the DDR to PADS.

This design is configured in Vivado Design Suite, synthesized and implemented for ZCU102 board (ZUS+ family). The Vivado block design synthesized on the FPGA is available in Figure 3. This figure features four distinct areas. The Processing System is the CPU of the board. The Interconnects area contains auto-generated modules for AXI memory-mapping. The Interfaces contains the GPIO and AXI DMA modules. Finally, the PADS area contains the neuromorphic accelerator.

The SoC DDR is mapped on the AXI bus memory-map. The FPGA modules are also mapped on the AXI memory map. DDR and FPGA modules can thus be accessed using those addresses through the AXI bus. The CPU communicates with the accelerator through by this mean.
<figure><img src="image_85.png" /><figcaption>Figure 2: Custom FPGA platform for neuromorphic accelerator deployment. The software stack is in shades of red, and the hardware stack is in shades of blue.</figcaption></figure>

## 2 CPU & Embedded Linux

A Petalinux distribution [127] is deployed on the CPU of the Zynq UltraScale+ SoC. The distribution is configured specifically for the platform using a hardware specification file. This file is generated after FPGA synthesis and contains specifications on the hardware design. The Kernel is also configured to enable DMA Drivers and SysFs virtual file-system. The AXI memory-map (containing DDR and FPGA peripheral addresses) is also specified in the device-tree of the Kernel. The Kernel is cross-compiled targeting the ARM-A53 of the SoC.

A C++ program is used to control the SNN accelerator. The software runs on the ARM-A53 core. It is used for data transfer to and from the accelerator. It also manages the control signals (enable, start, stop...)

* Step 1: Initialize AXI DMA and GPIO interfaces.

* Step 2: Write the input sample in the DDR.

* Step 3: Transfer data from DDR to PADS using the AXI DMA.

* Step 4: Wait for the *stop_network* to raise an interruption.

* Step 5: Retrieve the prediction on the GPIO connected to *o_class*.

* Step 6: Wait a few milliseconds and go back to step 2 for a new sample.

This program uses two medium of communication with the peripherals. First, the AXI DMA is accessed through two layers of drivers. At the bottom of the stack, a DMA Engine Driver and a Xilinx DMA Driver enable to control the DMA with a kernel-level API. Additionally, a DMA Proxy Driver is used as an overlay on top of those two drivers. The DMA Proxy Driver enables
<figure><img src="image_86.png" /><figcaption>Figure 3: Vivado block design of the FPGA part of the SNN deployment platform.</figcaption></figure>

access to the kernel-level DMA API directly from Linux user-space. This DMA Proxy Driver thus drastically simplifies development. The C++ Program uses the Proxy DMA Driver API manages data transfer between PADS and DDR.

Second, GPIO interfaces are configured and used through a SysFs virtual file-system interface. This interface enables a mapping between the kernel virtual addresses and the AXI bus physical addresses. GPIO addresses are accessed, configured, read and written through the SysFs. It is thus used to access *o_addr* and *stop_network* signals through GPIOs. The SysFs also enables to use the *stop_network* signal as an interruption. Indeed, the C++ program waits for this interruption before starting the next sample. The C++ program is cross-compiled for the custom Petalinux distribution. The Linux image, boot files and compiled C++ application are stored in an SD card alongside data samples. The ZCU102 board is configured in SD mode, thus Petalinux boots automatically when the board is started.
APPENDIX 3: Additional figures

<figure><img src="image_87.png" /><figcaption>Figure 4: Estimations on Flip-FLop usage for OPS-SAT and Spoken Digits associated CNNs</figcaption></figure>
<figure><img src="image_88.png" /><figcaption>Figure 5: Validation of the SAR metric & λ energy model for SPLEAT versus C-HLS on the benchmark of datasets for full-networks. Top: SAR vs λ SEQ, Bottom: SPLEAT vs C-HLS energy consumption.</figcaption></figure>
# APPENDIX 4: Measurements

<table><caption>Table 1: LUT, FF, Block RAM and DSP occupation measures for Convolution layers at design-space measurement points. Measures obtained after hardware synthesis on Xilinx Vivado Design Suite, targeting Xilinx Zedboard</caption><thead><tr><th rowspan="2">#K - INSIZE</th><th colspan="3">Look Up Tables</th><th colspan="3">Flip Flops</th><th colspan="3">Block RAM</th><th colspan="3">DSP</th></tr><tr><th>SPLEAT</th><th>ANN SEQ.</th><th>ANN PAR.</th><th>SPLEAT</th><th>ANN SEQ.</th><th>ANN PAR.</th><th>SPLEAT</th><th>ANN SEQ.</th><th>ANN PAR.</th><th>SPLEAT</th><th>ANN SEQ.</th><th>ANN PAR.</th></tr></thead><tbody><tr><td>1 - 5</td><td>29</td><td>156</td><td>290.5</td><td>19</td><td>148</td><td>12374.5</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>10</td></tr><tr><td>1 - 10</td><td>88</td><td>294</td><td>581</td><td>68</td><td>240</td><td>24749</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>10</td></tr><tr><td>1 - 25</td><td>121</td><td>233</td><td>1057</td><td>106</td><td>301</td><td>1811</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>19</td></tr><tr><td>1 - 50</td><td>146</td><td>259</td><td>1566</td><td>117</td><td>338</td><td>2985</td><td>2</td><td>4</td><td>0</td><td>2</td><td>1</td><td>20</td></tr><tr><td>10 - 5</td><td>48</td><td>155</td><td>4083</td><td>35</td><td>152</td><td>2767</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>10</td></tr><tr><td>10 - 10</td><td>106</td><td>295</td><td>8166</td><td>100</td><td>250</td><td>5534</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>10</td></tr><tr><td>10 - 25</td><td>143</td><td>232</td><td>9082</td><td>127</td><td>301</td><td>10509</td><td>4</td><td>1</td><td>0</td><td>2</td><td>1</td><td>8</td></tr><tr><td>10 - 50</td><td>176</td><td>247</td><td>10476</td><td>152</td><td>340</td><td>14946</td><td>17</td><td>4</td><td>0</td><td>2</td><td>2</td><td>10</td></tr><tr><td>25 - 5</td><td>48</td><td>158</td><td>9135</td><td>41</td><td>159</td><td>6291.5</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>10</td></tr><tr><td>25 - 10</td><td>107</td><td>296</td><td>18270</td><td>107</td><td>255</td><td>12583</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>10</td></tr><tr><td>25 - 25</td><td>145</td><td>231</td><td>20080</td><td>136</td><td>301</td><td>24014</td><td>8</td><td>1</td><td>0</td><td>2</td><td>2</td><td>10</td></tr><tr><td>25 - 50</td><td>182</td><td>242</td><td>24280</td><td>213</td><td>342</td><td>34095</td><td>34</td><td>4</td><td>0</td><td>2</td><td>2</td><td>10</td></tr><tr><td>50 - 5</td><td>102</td><td>152</td><td>16207.5</td><td>87</td><td>164</td><td>11765</td><td>0</td><td>0.5</td><td>0</td><td>0</td><td>1</td><td>10</td></tr><tr><td>50-10</td><td>166</td><td>293</td><td>32415</td><td>156</td><td>264</td><td>23530</td><td>1</td><td>0.5</td><td>0</td><td>0</td><td>1</td><td>10</td></tr><tr><td>50-25</td><td>214</td><td>222</td><td>36598</td><td>188</td><td>313</td><td>45978</td><td>17</td><td>1.5</td><td>0</td><td>2</td><td>2</td><td>10</td></tr><tr><td>50-50</td><td>320</td><td>235</td><td>32995</td><td>251</td><td>351</td><td>24637</td><td>68</td><td>4.5</td><td>0</td><td>2</td><td>2</td><td>10</td></tr><tr><td>128-5</td><td>107</td><td>155</td><td>32482</td><td>96</td><td>176</td><td>26178</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>10</td></tr><tr><td>128-8</td><td>141</td><td>287</td><td>64964</td><td>134</td><td>268</td><td>52356</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>10</td></tr><tr><td>128-16</td><td>193</td><td>291</td><td>57994</td><td>193</td><td>273</td><td>49386</td><td>17</td><td>1</td><td>0</td><td>0</td><td>1</td><td>10</td></tr></tbody></table>

<table><caption>Table 2: LUT, FF, Block RAM and DSP occupation measures for Pooling layers at design-space measurement points. Measures obtained after hardware synthesis on Xilinx Vivado Design Suite, targeting Xilinx Zedboard</caption><thead><tr><th rowspan="2">#K - IN WIDTH</th><th colspan="3">Look Up Tables (#)</th><th colspan="3">Flip Flops (#)</th><th colspan="3">Block RAM (#)</th><th colspan="3">DSP (#)</th></tr><tr><th>SPLEAT</th><th>ANN SEQ.</th><th>ANN PAR.</th><th>SPLEAT</th><th>ANN SEQ.</th><th>ANN PAR.</th><th>SPLEAT</th><th>ANN SEQ.</th><th>ANN PAR.</th><th>SPLEAT</th><th>ANN SEQ.</th><th>ANN PAR.</th></tr></thead><tbody><tr><td>1 - 5</td><td>107.0</td><td>73</td><td>116</td><td>90.0</td><td>80</td><td>241</td><td>0.0</td><td>0</td><td>0</td><td>0.0</td><td>0</td><td>0</td></tr><tr><td>1 - 10</td><td>171.0</td><td>85</td><td>117</td><td>136.0</td><td>102</td><td>242</td><td>0.0</td><td>0</td><td>0</td><td>0.0</td><td>0</td><td>0</td></tr><tr><td>1 - 25</td><td>420.0</td><td>100</td><td>234</td><td>157.0</td><td>123</td><td>513</td><td>0.0</td><td>0</td><td>0</td><td>0.0</td><td>0</td><td>0</td></tr><tr><td>1 - 50</td><td>1260.0</td><td>114</td><td>387</td><td>215.0</td><td>143</td><td>909</td><td>0.0</td><td>0</td><td>0</td><td>0.0</td><td>0</td><td>0</td></tr><tr><td>10 - 5</td><td>182.0</td><td>78</td><td>885</td><td>124.0</td><td>86</td><td>2176</td><td>0.0</td><td>0</td><td>0</td><td>0.0</td><td>0</td><td>0</td></tr><tr><td>10 - 10</td><td>559.0</td><td>83</td><td>966</td><td>167.0</td><td>104</td><td>2177</td><td>0.0</td><td>0</td><td>0</td><td>0.0</td><td>0</td><td>0</td></tr><tr><td>10 - 25</td><td>2587.0</td><td>85</td><td>1809</td><td>246.0</td><td>115</td><td>4788</td><td>0.0</td><td>0</td><td>0</td><td>2.0</td><td>0</td><td>0</td></tr><tr><td>10 - 50</td><td>10606.0</td><td>89</td><td>3292</td><td>615.0</td><td>127</td><td>8658</td><td>0.0</td><td>0</td><td>0</td><td>2.0</td><td>1</td><td>0</td></tr><tr><td>25 - 5</td><td>305.0</td><td>83</td><td>2164</td><td>134.0</td><td>93</td><td>5401</td><td>0.0</td><td>0</td><td>0</td><td>0.0</td><td>0</td><td>0</td></tr><tr><td>25 - 10</td><td>1248.0</td><td>82</td><td>2163</td><td>198.0</td><td>106</td><td>5402</td><td>0.0</td><td>0</td><td>0</td><td>1.0</td><td>0</td><td>0</td></tr><tr><td>25 - 25</td><td>6236.0</td><td>81</td><td>4455</td><td>381.0</td><td>119</td><td>11913</td><td>0.0</td><td>0</td><td>0</td><td>3.0</td><td>1</td><td>0</td></tr><tr><td>25 - 50</td><td>28199.0</td><td>84</td><td>9058</td><td>1045.0</td><td>128</td><td>21582</td><td>0.0</td><td>0</td><td>0</td><td>3.0</td><td>2</td><td>0</td></tr><tr><td>50 - 5</td><td>494.0</td><td>89</td><td>4291</td><td>144.0</td><td>100</td><td>10778</td><td>0.0</td><td>0</td><td>0</td><td>0.0</td><td>0</td><td>0</td></tr><tr><td>50-10</td><td>2278.0</td><td>87</td><td>4302</td><td>215.0</td><td>117</td><td>10780</td><td>0.0</td><td>0</td><td>0</td><td>3.0</td><td>0</td><td>0</td></tr><tr><td>50-25</td><td>12146.0</td><td>88</td><td>8827</td><td>648.0</td><td>126</td><td>23780</td><td>0.0</td><td>0</td><td>0</td><td>3.0</td><td>1</td><td>0</td></tr><tr><td>50-50</td><td>65196.0</td><td>83</td><td>11233</td><td>1356.0</td><td>136</td><td>27552</td><td>0.0</td><td>0</td><td>0</td><td>3.0</td><td>2</td><td>0</td></tr><tr><td>128-16</td><td>13715.0</td><td>88</td><td>15935</td><td>1016.0</td><td>123</td><td>40104</td><td>0.0</td><td>0</td><td>0</td><td>0.0</td><td>1</td><td>0</td></tr></tbody></table>
<table><caption>Table 3: LUT, FF, Block RAM and DSP occupation results for Fully-Connected layers at design-space measurement points. Measures obtained after hardware synthesis on Xilinx Vivado Design Suite, targeting Xilinx Zedboard</caption><thead><tr><th rowspan="2">#IN - #OUT</th><th colspan="4">Look Up Tables (#)</th><th colspan="4">Flip Flops (#)</th><th colspan="4">Block RAM (#)</th><th colspan="4">DSP (#)</th></tr><tr><th>SPLEAT</th><th>PADS</th><th>ANN SEQ.</th><th>ANN PAR.</th><th>SPLEAT</th><th>PADS</th><th>ANN SEQ.</th><th>ANN PAR.</th><th>SPLEAT</th><th>PADS</th><th>ANN SEQ.</th><th>ANN PAR.</th><th>SPLEAT</th><th>PADS</th><th>ANN SEQ.</th><th>ANN PAR.</th></tr></thead><tbody><tr><td>10-1</td><td>43</td><td>136</td><td>41</td><td>127</td><td>20</td><td>140</td><td>29</td><td>207</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>5</td></tr><tr><td>10-10</td><td>43</td><td>1251</td><td>46</td><td>973</td><td>20</td><td>1109</td><td>34</td><td>1676</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>50</td></tr><tr><td>10-50</td><td>76</td><td>6276</td><td>48</td><td>5417</td><td>39</td><td>5198</td><td>43</td><td>8615</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>192</td></tr><tr><td>10-100</td><td>47</td><td>9279</td><td>50</td><td>16486</td><td>29</td><td>6205</td><td>47</td><td>18647</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>220</td></tr><tr><td>10-250</td><td>45</td><td>31398</td><td>47</td><td>24673</td><td>26</td><td>25570</td><td>52</td><td>40767</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>220</td></tr><tr><td>50-1</td><td>72</td><td>467</td><td>46</td><td>367</td><td>35</td><td>555</td><td>38</td><td>452</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>14</td></tr><tr><td>50-10</td><td>69</td><td>4216</td><td>51</td><td>3584</td><td>41</td><td>4636</td><td>50</td><td>4161</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>134</td></tr><tr><td>50-50</td><td>68</td><td>21432</td><td>45</td><td>31349</td><td>44</td><td>21635</td><td>64</td><td>25306</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>220</td></tr><tr><td>50-100</td><td>77</td><td>43682</td><td>46</td><td>56926</td><td>40</td><td>43247</td><td>69</td><td>47932</td><td>2</td><td>0</td><td>2</td><td>0</td><td>1</td><td>0</td><td>1</td><td>220</td></tr><tr><td>50-250</td><td>78</td><td>111381</td><td>46</td><td>93149</td><td>41</td><td>111815</td><td>71</td><td>100092</td><td>1</td><td>0</td><td>4,5</td><td>0</td><td>1</td><td>0</td><td>1</td><td>220</td></tr><tr><td>100-1</td><td>75</td><td>824</td><td>49</td><td>867</td><td>38</td><td>1036</td><td>48</td><td>828</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>25</td></tr><tr><td>100-10</td><td>43</td><td>7702</td><td>52</td><td>9198</td><td>20</td><td>8596</td><td>52</td><td>8089</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>220</td></tr><tr><td>100-50</td><td>79</td><td>41505</td><td>46</td><td>67460</td><td>42</td><td>41445</td><td>66</td><td>47814</td><td>2</td><td>0</td><td>2</td><td>0</td><td>1</td><td>0</td><td>1</td><td>220</td></tr><tr><td>100-100</td><td>76</td><td>83034</td><td>47</td><td>131657</td><td>39</td><td>82358</td><td>71</td><td>93282</td><td>1</td><td>0</td><td>3,5</td><td>0</td><td>1</td><td>0</td><td>1</td><td>220</td></tr><tr><td>100-250</td><td>73</td><td>216270</td><td>47</td><td>187192</td><td>36</td><td>220899</td><td>78</td><td>182121</td><td>0</td><td>0</td><td>7</td><td>0</td><td>1</td><td>0</td><td>1</td><td>220</td></tr><tr><td>250-1</td><td>78</td><td>2060</td><td>53</td><td>2803</td><td>41</td><td>2532</td><td>59</td><td>2617</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>66</td></tr><tr><td>250-10</td><td>43</td><td>17739</td><td>48</td><td>44119</td><td>20</td><td>20731</td><td>61</td><td>31081</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>220</td></tr><tr><td>250-50</td><td>74</td><td>96902</td><td>51</td><td>216015</td><td>37</td><td>98998</td><td>70</td><td>147959</td><td>1</td><td>0</td><td>4</td><td>0</td><td>1</td><td>0</td><td>1</td><td>220</td></tr><tr><td>250-100</td><td>75</td><td>196948</td><td>52</td><td>361862</td><td>38</td><td>198768</td><td>74</td><td>265192</td><td>0</td><td>0</td><td>7</td><td>0</td><td>1</td><td>0</td><td>1</td><td>220</td></tr><tr><td>250-250</td><td>72</td><td>547792</td><td>48</td><td>610794</td><td>35</td><td>628317</td><td>82</td><td>545554</td><td>0</td><td>0</td><td>14</td><td>0</td><td>1</td><td>0</td><td>1</td><td>220</td></tr><tr><td>800-120</td><td>66</td><td>212369</td><td>61</td><td>2363622</td><td>43</td><td>238607</td><td>82</td><td>1867470</td><td>0</td><td>0</td><td>27</td><td>0</td><td>1</td><td>0</td><td>1</td><td>220</td></tr></tbody></table>

<table><caption>Table 4: Power measures for Fully-Connected layers at design-space measurement points. Measures obtained after hardware synthesis and simulation on Xilinx Vivado Design Suite targeting Xilinx Zedboard</caption><thead><tr><th rowspan="2">#IN - #OUT</th><th colspan="4">Power (mW)</th></tr><tr><th>SPLEAT</th><th>PADS</th><th>ANN SEQ.</th><th>ANN PAR.</th></tr></thead><tbody><tr><td>10-1</td><td>4</td><td>5</td><td>2</td><td>10</td></tr><tr><td>10-10</td><td>4</td><td>29</td><td>2</td><td>64</td></tr><tr><td>10-50</td><td>5</td><td>108</td><td>2</td><td>243</td></tr><tr><td>10-100</td><td>4</td><td>154</td><td>2</td><td>497</td></tr><tr><td>10-250</td><td>4</td><td>467</td><td>2</td><td>749</td></tr><tr><td>50-1</td><td>5</td><td>11</td><td>2</td><td>16</td></tr><tr><td>50-10</td><td>6</td><td>65</td><td>2</td><td>105</td></tr><tr><td>50-50</td><td>4</td><td>279</td><td>2</td><td>486</td></tr><tr><td>50-100</td><td>8</td><td>535</td><td>2</td><td>826</td></tr><tr><td>50-250</td><td>6</td><td>1259</td><td>2</td><td>1283</td></tr><tr><td>100-1</td><td>5</td><td>22</td><td>2</td><td>24</td></tr><tr><td>100-10</td><td>4</td><td>94</td><td>2</td><td>155</td></tr><tr><td>100-50</td><td>8</td><td>405</td><td>2</td><td>682</td></tr><tr><td>100-100</td><td>6</td><td>732</td><td>2</td><td>1218</td></tr><tr><td>100-250</td><td>5</td><td>1887</td><td>2</td><td>1792</td></tr><tr><td>250-1</td><td>6</td><td>32</td><td>2</td><td>49</td></tr><tr><td>250-10</td><td>4</td><td>164</td><td>2</td><td>349</td></tr><tr><td>250-50</td><td>6</td><td>679</td><td>2</td><td>1318</td></tr><tr><td>250-100</td><td>5</td><td>1338</td><td>2</td><td>2216</td></tr><tr><td>250-250</td><td>5</td><td></td><td>2</td><td></td></tr><tr><td>800-120</td><td>4</td><td>1174</td><td>2</td><td>3000</td></tr></tbody></table>
<table><caption>Table 5: Power measures for Convolution layers at design-space measurement points. Measures obtained after hardware synthesis and simulation on Xilinx Vivado Design Suite targeting Xilinx Zedboard</caption><thead><tr><th rowspan="2">#K - INSIZE</th><th colspan="3">Power (mW)</th></tr><tr><th>SPLEAT</th><th>ANN SEQ.</th><th>ANN PAR.</th></tr></thead><tbody><tr><td>1 - 5</td><td>2</td><td>4</td><td>11</td></tr><tr><td>1 - 10</td><td>4</td><td>5</td><td>22</td></tr><tr><td>1 - 25</td><td>4</td><td>4</td><td>31</td></tr><tr><td>1 - 50</td><td>8</td><td>5</td><td>39</td></tr><tr><td>10 - 5</td><td>3</td><td>4</td><td>48</td></tr><tr><td>10 - 10</td><td>5</td><td>5</td><td>96</td></tr><tr><td>10 - 25</td><td>19</td><td>4</td><td>103</td></tr><tr><td>10 - 50</td><td>066</td><td>5</td><td>97</td></tr><tr><td>25 - 5</td><td>3</td><td>4</td><td>96</td></tr><tr><td>25 - 10</td><td>5</td><td>4</td><td>192</td></tr><tr><td>25 - 25</td><td>36</td><td>4</td><td>180</td></tr><tr><td>25 - 50</td><td>138</td><td>5</td><td>167</td></tr><tr><td>50 - 5</td><td>5</td><td>4</td><td>155</td></tr><tr><td>50 - 10</td><td>8</td><td>5</td><td>311</td></tr><tr><td>50 - 25</td><td>71</td><td>6</td><td>274</td></tr><tr><td>50 - 50</td><td>144</td><td>7</td><td>541</td></tr><tr><td>128 - 5</td><td>5</td><td>4</td><td>251</td></tr><tr><td>128 - 8</td><td>8</td><td>5</td><td>503</td></tr><tr><td>128 - 16</td><td>73</td><td>5</td><td>525</td></tr></tbody></table>

<table><caption>Table 6: Power measures for Pooling layers at design-space measurement points. Measures obtained after hardware synthesis and simulation on Xilinx Vivado Design Suite targeting Xilinx Zedboard</caption><thead><tr><th rowspan="2">#K - IN_WIDTH</th><th colspan="3">Power (mW)</th></tr><tr><th>SPLEAT</th><th>ANN SEQ.</th><th>ANN PAR.</th></tr></thead><tbody><tr><td>1 - 5</td><td>0.003</td><td>0,01</td><td>0,006</td></tr><tr><td>1 - 10</td><td>0.003</td><td>0,01</td><td>0,004</td></tr><tr><td>1 - 25</td><td>0.004</td><td>0,01</td><td>0,01</td></tr><tr><td>1 - 50</td><td>0.011</td><td>0,01</td><td>0,014</td></tr><tr><td>10 - 5</td><td>0.003</td><td>0,01</td><td>0,038</td></tr><tr><td>10 - 10</td><td>0.005</td><td>0,01</td><td>0,024</td></tr><tr><td>10 - 25</td><td>0.014</td><td>0,01</td><td>0,069</td></tr><tr><td>10 - 50</td><td>0.03</td><td>0,01</td><td>0,098</td></tr><tr><td>25 - 5</td><td>0.004</td><td>0,01</td><td>0,08</td></tr><tr><td>25 - 10</td><td>0.011</td><td>0,01</td><td>0,045</td></tr><tr><td>25 - 25</td><td>0.021</td><td>0,01</td><td>0,156</td></tr><tr><td>25 - 50</td><td>0.059</td><td>0,01</td><td>0,23</td></tr><tr><td>50 - 5</td><td>0.004</td><td>0,01</td><td>0,147</td></tr><tr><td>50 - 10</td><td>0.013</td><td>0,01</td><td>0,079</td></tr><tr><td>50 - 25</td><td>0.033</td><td>0,01</td><td>0,296</td></tr><tr><td>50 - 50</td><td>0.067</td><td>0,01</td><td>0,358</td></tr><tr><td>128 - 16</td><td>0.039</td><td>0,01</td><td>0,535</td></tr></tbody></table>
<table><caption>Table 7: Duration results for Fully-Connected layers at design-space measurement points. Measures obtained by calculation and validated using post-synthesis simulation.</caption><thead><tr><th rowspan="2">#IN - #OUT</th><th colspan="4">Duration (ns)</th></tr><tr><th>SPLEAT</th><th>PADS</th><th>ANN SEQ.</th><th>ANN PAR.</th></tr></thead><tbody><tr><td>10-1</td><td>40</td><td>60</td><td>340</td><td>70</td></tr><tr><td>10-10</td><td>130</td><td>60</td><td>3310</td><td>70</td></tr><tr><td>10-50</td><td>530</td><td>60</td><td>16510</td><td>70</td></tr><tr><td>10-100</td><td>1030</td><td>60</td><td>33010</td><td>70</td></tr><tr><td>10-250</td><td>2530</td><td>60</td><td>82510</td><td>70</td></tr><tr><td>50-1</td><td>40</td><td>80</td><td>1540</td><td>90</td></tr><tr><td>50-10</td><td>130</td><td>80</td><td>15310</td><td>90</td></tr><tr><td>50-50</td><td>530</td><td>80</td><td>76510</td><td>90</td></tr><tr><td>50-100</td><td>1030</td><td>80</td><td>153010</td><td>90</td></tr><tr><td>50-250</td><td>2530</td><td>80</td><td>382510</td><td>90</td></tr><tr><td>100-1</td><td>40</td><td>90</td><td>3040</td><td>100</td></tr><tr><td>100-10</td><td>130</td><td>90</td><td>30310</td><td>100</td></tr><tr><td>100-50</td><td>530</td><td>90</td><td>151510</td><td>100</td></tr><tr><td>100-100</td><td>1030</td><td>90</td><td>303010</td><td>100</td></tr><tr><td>100-250</td><td>2530</td><td>90</td><td>757510</td><td>100</td></tr><tr><td>250-1</td><td>40</td><td>100</td><td>7540</td><td>110</td></tr><tr><td>250-10</td><td>130</td><td>100</td><td>75310</td><td>110</td></tr><tr><td>250-50</td><td>530</td><td>100</td><td>376510</td><td>110</td></tr><tr><td>250-100</td><td>1030</td><td>100</td><td>753010</td><td>110</td></tr><tr><td>250-250</td><td>2530</td><td>100</td><td>1882510</td><td>110</td></tr><tr><td>800-120</td><td>1230</td><td>120</td><td>3333910</td><td>130</td></tr></tbody></table>

<table><caption>Table 8: Duration results for Convolution layers at design-space measurement points. Measures obtained by calculation and validated using post-synthesis simulation.</caption><thead><tr><th rowspan="2">#K - INSIZE</th><th colspan="3">Duration (ns)</th></tr><tr><th>SPLEAT</th><th>ANN SEQ.</th><th>ANN PAR.</th></tr></thead><tbody><tr><td>1 - 5</td><td>290</td><td>5020</td><td>34</td></tr><tr><td>1 - 10</td><td>290</td><td>163820</td><td>109</td></tr><tr><td>1 - 25</td><td>290</td><td>1979870</td><td>685</td></tr><tr><td>1 - 50</td><td>290</td><td>9476620</td><td>2509</td></tr><tr><td>10 - 5</td><td>2540</td><td>9420</td><td>34</td></tr><tr><td>10 - 10</td><td>2540</td><td>325420</td><td>109</td></tr><tr><td>10 - 25</td><td>2540</td><td>3946720</td><td>685</td></tr><tr><td>10 - 50</td><td>2540</td><td>18902220</td><td>2509</td></tr><tr><td>25 - 5</td><td>6290</td><td>22620</td><td>34</td></tr><tr><td>25 - 10</td><td>6290</td><td>810220</td><td>109</td></tr><tr><td>25 - 25</td><td>6290</td><td>9847270</td><td>685</td></tr><tr><td>25 - 50</td><td>6290</td><td>47179020</td><td>2509</td></tr><tr><td>50 - 5</td><td>12540</td><td>44620</td><td>34</td></tr><tr><td>50 - 10</td><td>12540</td><td>1618220</td><td>109</td></tr><tr><td>50 - 25</td><td>12540</td><td>19681520</td><td>685</td></tr><tr><td>50 - 50</td><td>12540</td><td>94307020</td><td>2509</td></tr><tr><td>128 - 5</td><td>32040</td><td>113260</td><td>34</td></tr><tr><td>128 - 8</td><td>32040</td><td>2252140</td><td>73</td></tr><tr><td>128 - 16</td><td>32040</td><td>25806500</td><td>265</td></tr></tbody></table>
<table><caption>Table 9: Duration results for Pooling layers at design-space measurement points. Measures obtained by calculation and validated using post-synthesis simulation.</caption><thead><tr><th rowspan="2">#K - INSIZE</th><th colspan="3">Duration (ns)</th></tr><tr><th>SPLEAT</th><th>ANN SEQ.</th><th>ANN PAR.</th></tr></thead><tbody><tr><td>1 - 5</td><td>50</td><td>3110</td><td>50</td></tr><tr><td>1 - 10</td><td>50</td><td>27860</td><td>1040</td></tr><tr><td>1 - 25</td><td>50</td><td>102110</td><td>6290</td></tr><tr><td>1 - 50</td><td>50</td><td>440110</td><td>25040</td></tr><tr><td>10 - 5</td><td>50</td><td>6210</td><td>50</td></tr><tr><td>10 - 10</td><td>50</td><td>60971</td><td>1040</td></tr><tr><td>10 - 25</td><td>50</td><td>226583</td><td>6290</td></tr><tr><td>10 - 50</td><td>50</td><td>977317</td><td>25040</td></tr><tr><td>25 - 5</td><td>50</td><td>15510</td><td>50</td></tr><tr><td>25 - 10</td><td>50</td><td>157260</td><td>1040</td></tr><tr><td>25 - 25</td><td>50</td><td>582510</td><td>6290</td></tr><tr><td>25 - 50</td><td>50</td><td>2513010</td><td>25040</td></tr><tr><td>50 - 5</td><td>50</td><td>31010</td><td>50</td></tr><tr><td>50 - 10</td><td>50</td><td>541510</td><td>1040</td></tr><tr><td>50 - 25</td><td>50</td><td>1165010</td><td>6290</td></tr><tr><td>50 - 50</td><td>50</td><td>5026010</td><td>25040</td></tr><tr><td>128 - 16</td><td>50</td><td>1950470</td><td>2600</td></tr></tbody></table>
APPENDIX 5: Raw Estimations

SPLEAT

<table><thead><tr><th></th><th></th><th>LUT (#)</th><th>FF (#)</th><th>RAM (#)</th><th>DSP (#)</th><th>Dyn. Pow. (W)</th><th>Time (ns)</th><th>Energy (nJ)</th></tr></thead><tbody><tr><td rowspan="7">MNIST</td><td>C1</td><td>258</td><td>289</td><td>4</td><td>2</td><td>0.023</td><td>439044</td><td>10098</td></tr><tr><td>P1</td><td>1626</td><td>221</td><td>0</td><td>2</td><td>0.009</td><td>852340</td><td>7671</td></tr><tr><td>C2</td><td>228</td><td>265</td><td>1</td><td>1</td><td>0.010</td><td>1384758</td><td>13847</td></tr><tr><td>P2</td><td>696</td><td>174</td><td>0</td><td>1</td><td>0.006</td><td>325090</td><td>1950</td></tr><tr><td>FC1</td><td>123</td><td>119</td><td>7</td><td>1</td><td>0.018</td><td>272561</td><td>4906</td></tr><tr><td>FC2</td><td>106</td><td>91</td><td>0</td><td>0</td><td>0.005</td><td>25199</td><td>125</td></tr><tr><td>TOTAL</td><td>3035</td><td>1157</td><td>12</td><td>5</td><td>0.071</td><td>1384758</td><td>444507</td></tr></tbody></table>

PADS

<table><thead><tr><th></th><th></th><th>LUT (#)</th><th>FF (#)</th><th>RAM (#)</th><th>DSP (#)</th><th>Dyn. Pow. (W)</th><th>Time (ns)</th><th>Energy (nJ)</th></tr></thead><tbody><tr><td rowspan="7">MNIST</td><td>C1</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>P1</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>C2</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>P2</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>FC1</td><td>164934</td><td>166842</td><td>0</td><td>0</td><td>0.896</td><td>18300.0</td><td>16396</td></tr><tr><td>FC2</td><td>6587</td><td>7329</td><td>0</td><td>0</td><td>0.062</td><td>23104.0</td><td>1432</td></tr><tr><td>TOTAL</td><td>171520</td><td>174171</td><td>0</td><td>0</td><td>0.958</td><td>23104</td><td>27909</td></tr></tbody></table>

VGT

<table><thead><tr><th></th><th></th><th>LUT (#)</th><th>FF (#)</th><th>RAM (#)</th><th>DSP (#)</th><th>Dyn. Pow. (W)</th><th>Time (ns)</th><th>Energy (nJ)</th></tr></thead><tbody><tr><td rowspan="7">MNIST</td><td>C1</td><td>4396</td><td>3824</td><td>0</td><td>10</td><td>0.098</td><td>6680</td><td>654</td></tr><tr><td>P1</td><td>1099</td><td>2871</td><td>0</td><td>0</td><td>0.098</td><td>6390</td><td>626</td></tr><tr><td>C2</td><td>72532</td><td>50272</td><td>0</td><td>60</td><td>0.962</td><td>4010</td><td>3857</td></tr><tr><td>P2</td><td>1442</td><td>3466</td><td>0</td><td>0</td><td>0.048</td><td>3090</td><td>148</td></tr><tr><td>FC1</td><td>315191</td><td>227678</td><td>0</td><td>220</td><td>1.928</td><td>13290</td><td>25623</td></tr><tr><td>FC2</td><td>7402</td><td>6833</td><td>0</td><td>193</td><td>0.138</td><td>5770</td><td>796</td></tr><tr><td>TOTAL</td><td>402060</td><td>294940</td><td>0</td><td>483</td><td>3.220</td><td>15780</td><td>54756</td></tr></tbody></table>
## C-HLS

<table><thead><tr><th></th><th></th><th>LUT (#)</th><th>FF (#)</th><th>RAM (#)</th><th>DSP (#)</th><th>Dyn. Pow. (W)</th><th>Time (ns)</th><th>Energy (nJ)</th></tr></thead><tbody><tr><td rowspan="6">MNIST</td><td>C1</td><td>233</td><td>286</td><td>4</td><td>1</td><td>0.014</td><td>125036600</td><td>1750512.4</td></tr><tr><td>P1</td><td>91</td><td>118</td><td>1</td><td>0</td><td>0.016</td><td>977800</td><td>15644.8</td></tr><tr><td>C2</td><td>303</td><td>262</td><td>1</td><td>1</td><td>0.011</td><td>60130800</td><td>661438.8</td></tr><tr><td>P2</td><td>81</td><td>98</td><td>0</td><td>0</td><td>0.016</td><td>445800</td><td>7132.8</td></tr><tr><td>FC1</td><td>60</td><td>78</td><td>10</td><td>1</td><td>0.019</td><td>6325300</td><td>120180.7</td></tr><tr><td>FC2</td><td>45</td><td>54</td><td>1</td><td>1</td><td>0.017</td><td>255100</td><td>4336.7</td></tr><tr><td></td><td>TOTAL</td><td>811</td><td>893</td><td>17</td><td>4</td><td>0.095</td><td>193171400</td><td>66644133</td></tr></tbody></table>

## SPLEAT

<table><thead><tr><th></th><th></th><th>LUT (#)</th><th>FF (#)</th><th>RAM (#)</th><th>DSP (#)</th><th>Dyn. Pow. (W)</th><th>Time (ns)</th><th>Energy (nJ)</th></tr></thead><tbody><tr><td rowspan="6">OPSSAT</td><td>C1</td><td>246</td><td>265</td><td>3</td><td>1</td><td>0.017</td><td>1024304.0</td><td>17413</td></tr><tr><td>P1</td><td>907</td><td>192</td><td>0</td><td>1</td><td>0.006</td><td>296333.0</td><td>1777</td></tr><tr><td>C2</td><td>202</td><td>210</td><td>1</td><td>1</td><td>0.009</td><td>315095.0</td><td>2835</td></tr><tr><td>P2</td><td>210</td><td>146</td><td>0</td><td>0</td><td>0.003</td><td>591702.2</td><td>1775</td></tr><tr><td>FC1</td><td>106</td><td>91</td><td>0</td><td>0</td><td>0.005</td><td>58480.0</td><td>292</td></tr><tr><td>FC2</td><td>65</td><td>51</td><td>0</td><td>0</td><td>0.002</td><td>38455.0</td><td>76</td></tr><tr><td></td><td>TOTAL</td><td>1733</td><td>952</td><td>4</td><td>3</td><td>0.042</td><td>1024304</td><td>299096</td></tr></tbody></table>

## PADS

<table><thead><tr><th></th><th></th><th>LUT (#)</th><th>FF (#)</th><th>RAM (#)</th><th>DSP (#)</th><th>Dyn. Pow. (W)</th><th>Time (ns)</th><th>Energy (nJ)</th></tr></thead><tbody><tr><td rowspan="6">OPSSAT</td><td>C1</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>P1</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>C2</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>P2</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>FC1</td><td>6308</td><td>7012</td><td>0</td><td>0</td><td>0.062</td><td>46076</td><td>2856</td></tr><tr><td>FC2</td><td>260</td><td>248</td><td>0</td><td>0</td><td>0.004</td><td>38395</td><td>153</td></tr><tr><td></td><td>TOTAL</td><td>6568</td><td>7260</td><td>0</td><td>0</td><td>0.066</td><td>46076</td><td>14560</td></tr></tbody></table>

## VGT

<table><thead><tr><th></th><th></th><th>LUT (#)</th><th>FF (#)</th><th>RAM (#)</th><th>DSP (#)</th><th>Dyn. Pow. (W)</th><th>Time (ns)</th><th>Energy (nJ)</th></tr></thead><tbody><tr><td rowspan="6">OPSSAT</td><td>C1</td><td>6737</td><td>7047</td><td>0</td><td>30</td><td>0.19</td><td>6680</td><td>1269.2</td></tr><tr><td>P1</td><td>571</td><td>1446</td><td>0</td><td>0</td><td>0.022</td><td>6390</td><td>140.58</td></tr><tr><td>C2</td><td>11500</td><td>8702</td><td>0</td><td>30</td><td>0.202</td><td>4020</td><td>812.04</td></tr><tr><td>P2</td><td>492</td><td>1100</td><td>0</td><td>0</td><td>0.014</td><td>3100</td><td>43.4</td></tr><tr><td>FC1</td><td>6953</td><td>6518</td><td>0</td><td>185</td><td>0.135</td><td>1450</td><td>195.75</td></tr><tr><td>FC2</td><td>221</td><td>371</td><td>0</td><td>10</td><td>0.016</td><td>350</td><td>5.6</td></tr><tr><td></td><td>TOTAL</td><td>26472</td><td>25183</td><td>0</td><td>255</td><td>0.58</td><td>9850</td><td>8175.5</td></tr></tbody></table>
C-HLS

<table><thead><tr><th></th><th></th><th>LUT (#)</th><th>FF (#)</th><th>RAM (#)</th><th>DSP (#)</th><th>Dyn. Pow. (W)</th><th>Time (ns)</th><th>Energy (nJ)</th></tr></thead><tbody><tr><td rowspan="7">OPSSAT</td><td>C1</td><td>207</td><td>266</td><td>3</td><td>1</td><td>0.012</td><td>113235399</td><td>1358824.788</td></tr><tr><td>P1</td><td>96</td><td>120</td><td>1</td><td>0</td><td>0.016</td><td>971600</td><td>15545.6</td></tr><tr><td>C2</td><td>276</td><td>232</td><td>1</td><td>1</td><td>0.011</td><td>19399300</td><td>213392.3</td></tr><tr><td>P2</td><td>83</td><td>96</td><td>0</td><td>0</td><td>0.016</td><td>377600</td><td>6041.6</td></tr><tr><td>FC1</td><td>45</td><td>54</td><td>0</td><td>1</td><td>0.017</td><td>33100</td><td>562.7</td></tr><tr><td>FC2</td><td>22</td><td>29</td><td>0</td><td>1</td><td>0.016</td><td>6433</td><td>102.928</td></tr><tr><td>TOTAL</td><td>727</td><td>796</td><td>5</td><td>4</td><td>0.09</td><td>134023432</td><td>45567966.88</td></tr></tbody></table>

SPLEAT

<table><thead><tr><th></th><th></th><th>LUT (#)</th><th>FF (#)</th><th>RAM (#)</th><th>DSP (#)</th><th>Dyn. Pow. (W)</th><th>Time (ns)</th><th>Energy (nJ)</th></tr></thead><tbody><tr><td rowspan="7">GTSRB</td><td>C1</td><td>294</td><td>366</td><td>18</td><td>2</td><td>0.081</td><td>32616662</td><td>2641949.622</td></tr><tr><td>P1</td><td>10543</td><td>552</td><td>0</td><td>3</td><td>0.028</td><td>13090140</td><td>366523.92</td></tr><tr><td>C2</td><td>240</td><td>295</td><td>5</td><td>1</td><td>0.026</td><td>59256398</td><td>1540666.348</td></tr><tr><td>P2</td><td>1551</td><td>218</td><td>0</td><td>1</td><td>0.011</td><td>5332540</td><td>58657.94</td></tr><tr><td>FC1</td><td>148</td><td>128</td><td>37</td><td>1</td><td>0.035</td><td>4618640</td><td>161652.4</td></tr><tr><td>FC2</td><td>122</td><td>118</td><td>4</td><td>1</td><td>0.013</td><td>886004</td><td>11518.052</td></tr><tr><td>FC3</td><td>115</td><td>106</td><td>2</td><td>1</td><td>0.008</td><td>332371</td><td>2658.968</td></tr><tr><td>TOTAL</td><td>13011</td><td>1780</td><td>65</td><td>10</td><td>0.202</td><td>59256398</td><td>26783891.9</td></tr></tbody></table>

PADS

<table><thead><tr><th></th><th></th><th>LUT (#)</th><th>FF (#)</th><th>RAM (#)</th><th>DSP (#)</th><th>Dyn. Pow. (W)</th><th>Time (ns)</th><th>Energy (nJ)</th></tr></thead><tbody><tr><td rowspan="7">GTSRB</td><td>C1</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>P1</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>C2</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>P2</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>FC1</td><td>580849</td><td>741511</td><td>0</td><td>0</td><td>3.443</td><td>139830</td><td>481434.69</td></tr><tr><td>FC2</td><td>84934</td><td>84788</td><td>0</td><td>0</td><td>0.472</td><td>144558</td><td>68231.376</td></tr><tr><td>FC3</td><td>32069</td><td>32131</td><td>0</td><td>0</td><td>0.202</td><td>196552</td><td>39703.504</td></tr><tr><td>TOTAL</td><td>697851</td><td>858429</td><td>0</td><td>0</td><td>4.117</td><td>196552</td><td>858342.584</td></tr></tbody></table>

VGT

<table><thead><tr><th></th><th></th><th>LUT (#)</th><th>FF (#)</th><th>RAM (#)</th><th>DSP (#)</th><th>Dyn. Pow. (W)</th><th>Time (ns)</th><th>Energy (nJ)</th></tr></thead><tbody><tr><td rowspan="7">GTSRB</td><td>C1</td><td>56740</td><td>45131</td><td>0</td><td>30</td><td>0.955</td><td>8920</td><td>8518.6</td></tr><tr><td>P1</td><td>6287</td><td>16397</td><td>0</td><td>0</td><td>0.204</td><td>8590</td><td>1752.36</td></tr><tr><td>C2</td><td>671751</td><td>489375</td><td>0</td><td>320</td><td>8.884</td><td>5870</td><td>52149.08</td></tr><tr><td>P2</td><td>2762</td><td>6908</td><td>0</td><td>0</td><td>0.098</td><td>4830</td><td>473.34</td></tr><tr><td>FC1</td><td>2606894</td><td>1967153</td><td>0</td><td>220</td><td>10.667</td><td>19050</td><td>203206.35</td></tr><tr><td>FC2</td><td>141808</td><td>101654</td><td>0</td><td>221</td><td>1.179</td><td>19680</td><td>23202.72</td></tr><tr><td>FC3</td><td>51046</td><td>36912</td><td>0</td><td>205</td><td>0.552</td><td>14230</td><td>7854.96</td></tr><tr><td>TOTAL</td><td>3537286</td><td>2663527</td><td>0</td><td>995</td><td>22.542</td><td>33160</td><td>755782.72</td></tr></tbody></table>
C-HLS

<table><thead><tr><th></th><th></th><th>LUT (#)</th><th>FF (#)</th><th>RAM (#)</th><th>DSP (#)</th><th>Dyn. Pow. (W)</th><th>Time (ns)</th><th>Energy (nJ)</th></tr></thead><tbody><tr><td rowspan="7">GTSRB</td><td>C1</td><td>270</td><td>318</td><td>15</td><td>2</td><td>0.02</td><td>691612500</td><td>13832250</td></tr><tr><td>P1</td><td>86</td><td>123</td><td>4</td><td>2</td><td>0.02</td><td>9772700</td><td>195454</td></tr><tr><td>C2</td><td>293</td><td>273</td><td>4</td><td>2</td><td>0.013</td><td>1873068800</td><td>24349894.4</td></tr><tr><td>P2</td><td>84</td><td>110</td><td>1</td><td>0</td><td>0.016</td><td>1616000</td><td>25856</td></tr><tr><td>FC1</td><td>67</td><td>80</td><td>48</td><td>1</td><td>0.025</td><td>28836100</td><td>720902.5</td></tr><tr><td>FC2</td><td>53</td><td>72</td><td>6</td><td>1</td><td>0.018</td><td>3145300</td><td>56615.4</td></tr><tr><td>FC3</td><td>47</td><td>63</td><td>3</td><td>1</td><td>0.017</td><td>255100</td><td>4336.7</td></tr><tr><td></td><td>TOTAL</td><td>897</td><td>1036</td><td>77</td><td>9</td><td>0.132</td><td>2608306500</td><td>996373083</td></tr></tbody></table>

SPLEAT

<table><thead><tr><th></th><th></th><th>LUT (#)</th><th>FF (#)</th><th>RAM (#)</th><th>DSP (#)</th><th>Dyn. Pow. (W)</th><th>Time (ns)</th><th>Energy (nJ)</th></tr></thead><tbody><tr><td rowspan="7">CIFAR-10</td><td>C1</td><td>294</td><td>366</td><td>18</td><td>2</td><td>0.081</td><td>141491930</td><td>11460846.33</td></tr><tr><td>P1</td><td>10543</td><td>552</td><td>0</td><td>3</td><td>0.028</td><td>38334740</td><td>1073372.72</td></tr><tr><td>C2</td><td>247</td><td>318</td><td>6</td><td>1</td><td>0.03</td><td>742796350</td><td>22283890.5</td></tr><tr><td>P2</td><td>2917</td><td>250</td><td>0</td><td>3</td><td>0.014</td><td>16405740</td><td>229680.36</td></tr><tr><td>C3</td><td>159</td><td>189</td><td>1</td><td>0</td><td>0.006</td><td>898385570</td><td>5390313.42</td></tr><tr><td>FC1</td><td>107</td><td>92</td><td>1</td><td>0</td><td>0.004</td><td>218635</td><td>874.54</td></tr><tr><td>TOTAL</td><td>14265</td><td>1765</td><td>26</td><td>9</td><td>0.163</td><td>898385570</td><td>371033240.4</td></tr></tbody></table>

PADS

<table><thead><tr><th></th><th></th><th>LUT (#)</th><th>FF (#)</th><th>RAM (#)</th><th>DSP (#)</th><th>Dyn. Pow. (W)</th><th>Time (ns)</th><th>Energy (nJ)</th></tr></thead><tbody><tr><td rowspan="7">CIFAR-10</td><td>C1</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>P1</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>C2</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>P2</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>C3</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>FC1</td><td>9576</td><td>10862</td><td>0</td><td>0</td><td>0.077</td><td>218585</td><td>16831.045</td></tr><tr><td>TOTAL</td><td>9576</td><td>10862</td><td>0</td><td>0</td><td>0.077</td><td>218585</td><td>71477.295</td></tr></tbody></table>

VGT

<table><thead><tr><th></th><th></th><th>LUT (#)</th><th>FF (#)</th><th>RAM (#)</th><th>DSP (#)</th><th>Dyn. Pow. (W)</th><th>Time (ns)</th><th>Energy (nJ)</th></tr></thead><tbody><tr><td rowspan="7">CIFAR-10</td><td>C1</td><td>56740</td><td>45131</td><td>0</td><td>30</td><td>0.955</td><td>10290</td><td>9826.95</td></tr><tr><td>P1</td><td>6287</td><td>16397</td><td>0</td><td>0</td><td>0.204</td><td>8940</td><td>1823.76</td></tr><tr><td>C2</td><td>1172139</td><td>901745</td><td>0</td><td>320</td><td>12.663</td><td>8670</td><td>109788.21</td></tr><tr><td>P2</td><td>5494</td><td>13791</td><td>0</td><td>0</td><td>0.165</td><td>5890</td><td>971.85</td></tr><tr><td>C3</td><td>2070432</td><td>1624128</td><td>0</td><td>320</td><td>17.504</td><td>4920</td><td>86119.68</td></tr><tr><td>FC1</td><td>15717</td><td>12381</td><td>0</td><td>220</td><td>0.191</td><td>1850</td><td>353.35</td></tr><tr><td>TOTAL</td><td>3326807</td><td>2613572</td><td>0</td><td>890</td><td>31.683</td><td>12350</td><td>394372.55</td></tr></tbody></table>
C-HLS

<table><thead><tr><th></th><th></th><th>LUT (#)</th><th>FF (#)</th><th>RAM (#)</th><th>DSP (#)</th><th>Dyn. Pow. (W)</th><th>Time (ns)</th><th>Energy (nJ)</th></tr></thead><tbody><tr><td rowspan="6">CIFAR-10</td><td>C1</td><td>270</td><td>318</td><td>15</td><td>2</td><td>0.02</td><td>691612500</td><td>13832250</td></tr><tr><td>P1</td><td>86</td><td>123</td><td>4</td><td>2</td><td>0.02</td><td>9772700</td><td>195454</td></tr><tr><td>C2</td><td>307</td><td>282</td><td>5</td><td>2</td><td>0.015</td><td>2204025600</td><td>33060384</td></tr><tr><td>P2</td><td>94</td><td>120</td><td>1</td><td>0</td><td>0.017</td><td>6066900</td><td>103137.3</td></tr><tr><td>C3</td><td>198</td><td>176</td><td>2</td><td>1</td><td>0.011</td><td>72486400</td><td>797350.4</td></tr><tr><td>FC1</td><td>46</td><td>56</td><td>1</td><td>1</td><td>0.016</td><td>387100</td><td>6193.6</td></tr><tr><td></td><td>TOTAL</td><td>999</td><td>1073</td><td>26</td><td>8</td><td>0.1</td><td>2984351200</td><td>1044522920</td></tr></tbody></table>

SPLEAT

<table><thead><tr><th></th><th></th><th>LUT (#)</th><th>FF (#)</th><th>RAM (#)</th><th>DSP (#)</th><th>Dyn. Pow. (W)</th><th>Time (ns)</th><th>Energy (nJ)</th></tr></thead><tbody><tr><td rowspan="3">MVR</td><td>FC1</td><td>127</td><td>130</td><td>4</td><td>1</td><td>0.013</td><td>513805</td><td>6679.465</td></tr><tr><td>FC2</td><td>60</td><td>51</td><td>0</td><td>0</td><td>0.003</td><td>24460</td><td>73.38</td></tr><tr><td>TOTAL</td><td>186</td><td>181</td><td>4</td><td>1</td><td>0.016</td><td>513805</td><td>136672.13</td></tr></tbody></table>

PADS

<table><thead><tr><th></th><th></th><th>LUT (#)</th><th>FF (#)</th><th>RAM (#)</th><th>DSP (#)</th><th>Dyn. Pow. (W)</th><th>Time (ns)</th><th>Energy (nJ)</th></tr></thead><tbody><tr><td rowspan="3">MVR</td><td>FC1</td><td>96686</td><td>96782</td><td>0</td><td>0</td><td>1.053</td><td>3221</td><td>3391.713</td></tr><tr><td>FC2</td><td>2413</td><td>2874</td><td>0</td><td>0</td><td>0.036</td><td>3239</td><td>116.604</td></tr><tr><td>TOTAL</td><td>99098</td><td>99655</td><td>0</td><td>0</td><td>1.089</td><td>3239</td><td>4337.021</td></tr></tbody></table>

VGT

<table><thead><tr><th></th><th></th><th>LUT (#)</th><th>FF (#)</th><th>RAM (#)</th><th>DSP (#)</th><th>Dyn. Pow. (W)</th><th>Time (ns)</th><th>Energy (nJ)</th></tr></thead><tbody><tr><td rowspan="3">MVR</td><td>FC1</td><td>96021</td><td>91776</td><td>0</td><td>220</td><td>1.209</td><td>31850</td><td>38506.65</td></tr><tr><td>FC2</td><td>3084</td><td>2828</td><td>0</td><td>74</td><td>0.055</td><td>31850</td><td>1751.75</td></tr><tr><td>TOTAL</td><td>99105</td><td>94603</td><td>0</td><td>294</td><td>1.264</td><td>2780</td><td>4208.92</td></tr></tbody></table>

C-HLS

<table><thead><tr><th></th><th></th><th>LUT (#)</th><th>FF (#)</th><th>RAM (#)</th><th>DSP (#)</th><th>Dyn. Pow. (W)</th><th>Time (ns)</th><th>Energy (nJ)</th></tr></thead><tbody><tr><td rowspan="3">MVR</td><td>FC1</td><td>55</td><td>72</td><td>4</td><td>1</td><td>0.018</td><td>1830100</td><td>32941.8</td></tr><tr><td>FC2</td><td>41</td><td>50</td><td>1</td><td>1</td><td>0.017</td><td>423766</td><td>7204.022</td></tr><tr><td>TOTAL</td><td>95</td><td>122</td><td>5</td><td>2</td><td>0.035</td><td>2253866</td><td>642351.81</td></tr></tbody></table>
SPLEAT

<table><thead><tr><th></th><th>LUT (#)</th><th>FF (#)</th><th>RAM (#)</th><th>DSP (#)</th><th>Dyn. Pow. (W)</th><th>Time (ns)</th><th>Energy (nJ)</th></tr></thead><tbody><tr><td>C1</td><td>233</td><td>249</td><td>1</td><td>1</td><td>0.011</td><td>196172</td><td>2157.892</td></tr><tr><td>P1</td><td>873</td><td>189</td><td>0</td><td>1</td><td>0.006</td><td>2947540</td><td>17685.24</td></tr><tr><td>C2</td><td>215</td><td>228</td><td>2</td><td>1</td><td>0.014</td><td>377495</td><td>5284.93</td></tr><tr><td>P2</td><td>1174</td><td>197</td><td>0</td><td>1</td><td>0.007</td><td>5568490</td><td>38979.43</td></tr><tr><td>C3</td><td>199</td><td>205</td><td>1</td><td>1</td><td>0.008</td><td>604133</td><td>4833.064</td></tr><tr><td>P3</td><td>1174</td><td>197</td><td>0</td><td>1</td><td>0.004</td><td>3049290</td><td>12197.16</td></tr><tr><td>FC1</td><td>125</td><td>124</td><td>10</td><td>1</td><td>0.023</td><td>4058808</td><td>93352.584</td></tr><tr><td>FC2</td><td>106</td><td>91</td><td>0</td><td>0</td><td>0.005</td><td>55539</td><td>277.695</td></tr><tr><td>TOTAL</td><td>3420</td><td>1450</td><td>14</td><td>7</td><td>0.078</td><td>5568490</td><td>1826464.72</td></tr></tbody></table>

PADS

<table><thead><tr><th></th><th>LUT (#)</th><th>FF (#)</th><th>RAM (#)</th><th>DSP (#)</th><th>Dyn. Pow. (W)</th><th>Time (ns)</th><th>Energy (nJ)</th></tr></thead><tbody><tr><td>C1</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>P1</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>C2</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>P2</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>C3</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>P3</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>FC1</td><td>216639</td><td>233426</td><td>0</td><td>0</td><td>1.402</td><td>29431</td><td>41262.262</td></tr><tr><td>FC2</td><td>7702</td><td>8596</td><td>0</td><td>0</td><td>0.071</td><td>38369</td><td>2724.199</td></tr><tr><td>TOTAL</td><td>224341</td><td>242022</td><td>0</td><td>0</td><td>1.473</td><td>38369</td><td>66109.787</td></tr></tbody></table>

VGT

<table><thead><tr><th></th><th>LUT (#)</th><th>FF (#)</th><th>RAM (#)</th><th>DSP (#)</th><th>Dyn. Pow. (W)</th><th>Time (ns)</th><th>Energy (nJ)</th></tr></thead><tbody><tr><td>C1</td><td>2225</td><td>2208</td><td>0</td><td>10</td><td>0.059</td><td>5510</td><td>325.09</td></tr><tr><td>P1</td><td>556</td><td>1410</td><td>0</td><td>0</td><td>0.022</td><td>4810</td><td>105.82</td></tr><tr><td>C2</td><td>10785</td><td>8852</td><td>0</td><td>30</td><td>0.228</td><td>6270</td><td>1429.56</td></tr><tr><td>P2</td><td>832</td><td>2147</td><td>0</td><td>0</td><td>0.032</td><td>5410</td><td>173.12</td></tr><tr><td>C3</td><td>19463</td><td>14441</td><td>0</td><td>50</td><td>0.326</td><td>5700</td><td>1858.2</td></tr><tr><td>P3</td><td>832</td><td>2147</td><td>0</td><td>0</td><td>0.032</td><td>2790</td><td>89.28</td></tr><tr><td>FC1</td><td>562019</td><td>409155</td><td>0</td><td>220</td><td>3.075</td><td>15850</td><td>48738.75</td></tr><tr><td>FC2</td><td>9198</td><td>8089</td><td>0</td><td>220</td><td>0.155</td><td>5770</td><td>894.35</td></tr><tr><td>TOTAL</td><td>605626</td><td>447577</td><td>0</td><td>530</td><td>3.921</td><td>15070</td><td>62856.97</td></tr></tbody></table>
C-HLS

<table><thead><tr><th></th><th></th><th>LUT (#)</th><th>FF (#)</th><th>RAM (#)</th><th>DSP (#)</th><th>Dyn. Pow. (W)</th><th>Time (ns)</th><th>Energy (nJ)</th></tr></thead><tbody><tr><td rowspan="8">SPOKEN</td><td>C1</td><td>212</td><td>256</td><td>1</td><td>1</td><td>0.012</td><td>19302733</td><td>231632.796</td></tr><tr><td>P1</td><td>94</td><td>118</td><td>1</td><td>0</td><td>0.016</td><td>872600</td><td>13961.6</td></tr><tr><td>C2</td><td>262</td><td>247</td><td>2</td><td>1</td><td>0.013</td><td>48369700</td><td>628806.1</td></tr><tr><td>P2</td><td>85</td><td>108</td><td>1</td><td>0</td><td>0.016</td><td>575600</td><td>9209.6</td></tr><tr><td>C3</td><td>279</td><td>229</td><td>1</td><td>1</td><td>0.011</td><td>20261166</td><td>222872.826</td></tr><tr><td>P3</td><td>85</td><td>108</td><td>1</td><td>0</td><td>0.016</td><td>328100</td><td>5249.6</td></tr><tr><td>FC1</td><td>62</td><td>80</td><td>13</td><td>1</td><td>0.02</td><td>8880100</td><td>177602</td></tr><tr><td>FC2</td><td>45</td><td>54</td><td>0</td><td>1</td><td>0.017</td><td>303100</td><td>5152.7</td></tr><tr><td>TOTAL</td><td></td><td>1122</td><td>1192</td><td>20</td><td>5</td><td>0.123</td><td>98893099</td><td>3040962.794</td></tr></tbody></table>

SPLEAT

<table><thead><tr><th></th><th></th><th>LUT (#)</th><th>FF (#)</th><th>RAM (#)</th><th>DSP (#)</th><th>Dyn. Pow. (W)</th><th>Time (ns)</th><th>Energy (nJ)</th></tr></thead><tbody><tr><td rowspan="8">RADIOML</td><td>C1</td><td>294</td><td>366</td><td>18</td><td>2</td><td>0.081</td><td>19938770</td><td>1615040.37</td></tr><tr><td>P1</td><td>14058</td><td>659</td><td>0</td><td>3</td><td>0.035</td><td>260275990</td><td>9109659.65</td></tr><tr><td>C2</td><td>288</td><td>372</td><td>23</td><td>2</td><td>0.099</td><td>196932750</td><td>19496342.25</td></tr><tr><td>P2</td><td>12579</td><td>685</td><td>0</td><td>3</td><td>0.034</td><td>24896490</td><td>846480.66</td></tr><tr><td>C3</td><td>265</td><td>350</td><td>17</td><td>1</td><td>0.075</td><td>50042510</td><td>3753188.25</td></tr><tr><td>P3</td><td>12579</td><td>685</td><td>0</td><td>3</td><td>0.007</td><td>3595730</td><td>25170.11</td></tr><tr><td>FC1</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>FC2</td><td>126</td><td>126</td><td>10</td><td>1</td><td>0.023</td><td>1366975</td><td>31440.425</td></tr><tr><td>FC3</td><td>111</td><td>98</td><td>2</td><td>1</td><td>0.005</td><td>325310</td><td>1626.55</td></tr><tr><td>TOTAL</td><td></td><td>28892</td><td>2849</td><td>68</td><td>16</td><td>0.359</td><td>260275990</td><td>158508077.9</td></tr></tbody></table>

PADS

<table><thead><tr><th></th><th></th><th>LUT (#)</th><th>FF (#)</th><th>RAM (#)</th><th>DSP (#)</th><th>Dyn. Pow. (W)</th><th>Time (ns)</th><th>Energy (nJ)</th></tr></thead><tbody><tr><td rowspan="8">RADIOML</td><td>C1</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>P1</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>C2</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>P2</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>C3</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>P3</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>FC1</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>FC2</td><td>265065</td><td>283572</td><td>0</td><td>0</td><td>1.249</td><td>338255</td><td>422480.495</td></tr><tr><td>FC3</td><td>29874</td><td>30837</td><td>0</td><td>0</td><td>0.16</td><td>324715</td><td>51954.4</td></tr><tr><td>TOTAL</td><td></td><td>294939</td><td>314408</td><td>0</td><td>0</td><td>1.409</td><td>338255</td><td>561165.045</td></tr></tbody></table>
VGT

<table><thead><tr><th></th><th></th><th>LUT<br>(#)</th><th>FF<br>(#)</th><th>RAM<br>(#)</th><th>DSP<br>(#)</th><th>Dyn. Pow.<br>(W)</th><th>Time<br>(ns)</th><th>Energy<br>(nJ)</th></tr></thead><tbody><tr><td rowspan="10">RADIOML</td><td>C1</td><td>56740</td><td>45131</td><td>0</td><td>30</td><td>0.955</td><td>10590</td><td>10113.45</td></tr><tr><td>P1</td><td>6888</td><td>17943</td><td>0</td><td>0</td><td>0.215</td><td>10570</td><td>2272.55</td></tr><tr><td>C2</td><td>1148879</td><td>901156</td><td>0</td><td>320</td><td>15.062</td><td>13230</td><td>199270.26</td></tr><tr><td>P2</td><td>10317</td><td>26535</td><td>0</td><td>0</td><td>0.337</td><td>12650</td><td>4263.05</td></tr><tr><td>C3</td><td>4165095</td><td>3362637</td><td>0</td><td>640</td><td>44.595</td><td>13030</td><td>581072.85</td></tr><tr><td>P3</td><td>10317</td><td>26535</td><td>0</td><td>0</td><td>0.337</td><td>8410</td><td>2834.17</td></tr><tr><td>FC1</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>FC2</td><td>435017</td><td>336722</td><td>0</td><td>220</td><td>2.833</td><td>43450</td><td>123093.85</td></tr><tr><td>FC3</td><td>57320</td><td>40687</td><td>0</td><td>220</td><td>0.458</td><td>14570</td><td>6673.06</td></tr><tr><td>TOTAL</td><td>5881084</td><td>4732955</td><td>0</td><td>1430</td><td>64.49</td><td>27820</td><td>1801066.8</td></tr></tbody></table>

C-HLS

<table><thead><tr><th></th><th></th><th>LUT<br>(#)</th><th>FF<br>(#)</th><th>RAM<br>(#)</th><th>DSP<br>(#)</th><th>Dyn. Pow.<br>(W)</th><th>Time<br>(ns)</th><th>Energy<br>(nJ)</th></tr></thead><tbody><tr><td rowspan="10">RADIOML</td><td>C1</td><td>270</td><td>318</td><td>15</td><td>2</td><td>0.02</td><td>691612500</td><td>13832250</td></tr><tr><td>P1</td><td>88</td><td>124</td><td>4</td><td>2</td><td>0.02</td><td>12861500</td><td>257230</td></tr><tr><td>C2</td><td>283</td><td>309</td><td>14</td><td>2</td><td>0.02</td><td>6904563200</td><td>138091264</td></tr><tr><td>P2</td><td>96</td><td>127</td><td>5</td><td>1</td><td>0.02</td><td>13211100</td><td>264222</td></tr><tr><td>C3</td><td>320</td><td>297</td><td>15</td><td>2</td><td>0.02</td><td>14482726400</td><td>289654528</td></tr><tr><td>P3</td><td>96</td><td>127</td><td>5</td><td>1</td><td>0.02</td><td>19504700</td><td>390094</td></tr><tr><td>FC1</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>FC2</td><td>60</td><td>79</td><td>14</td><td>1</td><td>0.021</td><td>10088500</td><td>211858.5</td></tr><tr><td>FC3</td><td>48</td><td>60</td><td>2</td><td>1</td><td>0.017</td><td>1147299</td><td>19504.083</td></tr><tr><td>TOTAL</td><td>1248</td><td>1420</td><td>66</td><td>12</td><td>0.158</td><td>22135715199</td><td>9031371801</td></tr></tbody></table>