# ScAlN/GaN High Electron Mobility Transistor Heterostructures Grown by Ammonia Source Molecular Beam Epitaxy on Silicon Substrate

Caroline Elias, Sébastien Chenot, Florian Bartoli, Maxime Hugues, Yvon Cordier

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Caroline Elias, Sébastien Chenot, Florian Bartoli, Maxime Hugues, Yvon Cordier. ScAlN/GaN High Electron Mobility Transistor Heterostructures Grown by Ammonia Source Molecular Beam Epitaxy on Silicon Substrate. Physica Status Solidi A (applications and materials science), 2025, 10.1002/pssa.202400963. hal-04935622

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# ScAlN/GaN High Electron Mobility Transistor Heterostructures Grown by Ammonia Source Molecular Beam Epitaxy on Silicon Substrate

Caroline Elias, Sébastien Chenot, Florian Bartoli, Maxime Hugues, and Yvon Cordier*

In this work, ammonia source molecular beam epitaxy is explored as an alternative technique to grow ScAlN/GaN high electron mobility transistor heterostructures on a silicon substrate with thin buffer layers. The effect of ScAlN barrier thickness is investigated. A transistor with a maximum drain current superior to 1 Å mm⁻¹ has been fabricated on a silicon substrate despite the ohmic contacts having a resistance around 1 ohm.mm, and functional transistors with barriers as thin as 10 nm have been demonstrated.

## 1. Introduction

ScAlN is a wide bandgap semiconductor with very large piezoelectric and spontaneous polarization coefficients[1,2] that induce a very high charge density at the interface with GaN.[3] Moreover, ScₓAl₁₋ₓN alloy with x = 0.14–0.18 can be grown strain-free (lattice-matched) on GaN, which makes this alloy a promising barrier layer candidate for high electron mobility transistors (HEMTs) in view of power switching and radio frequency (RF)/millimeter wave power amplifier applications.[3,4] The epitaxial growth of ScAlN/GaN heterostructures was developed by several groups using plasma-assisted molecular beam epitaxy (PA-MBE)[5-7] and metal-organic chemical vapor deposition (MOCVD).[8-11] On the one hand, PA-MBE necessitates an accurate control of the nitrogen to group-III elements ratio but it allows growth at a relatively low temperature. Recently, the resulting good control of interfaces allowed the growth of multichannel transistor structures.[12] On the other hand, MOCVD is more challenging due to the need for precursors with sufficient vapor pressure and the necessity to adapt the reactor to allow sufficient and controlled Sc incorporation into AlN. Despite its very recent history, high-performance RF-HEMTs have already been

demonstrated with the epitaxial ScAlN alloy.[13,14] High-performance RF devices have been obtained on AlGaN/GaN HEMTs grown on silicon with ammonia-source MBE (NH₃-MBE)[15,16] but in spite of few papers reporting on ScGaN,[17] there was no report about ScAlN grown by this technique until the publication of our first study.[18] In the present work, the electrical properties of ScAlN/GaN heterostructures grown by NH₃-MBE are studied. The structures are grown under nitrogen-rich condi-

tions, which makes the growth easier to master compared to PA-MBE. The electrical properties of the heterostructures are studied with capacitance-voltage (C–V) and Hall effect measurements. Functional transistors with barrier thicknesses of 25 and 10 nm are demonstrated.

## 2. Experimental Section

The samples were grown in a Riber Compact 21 T reactor equipped with effusion cells for gallium, aluminum, and scandium, while ammonia was provided via an injector with a flow rate of 200 sccm. For all the samples, the temperatures of the scandium and the aluminum effusion cells were kept constant at 1200 and 1070 °C, corresponding to beam equivalent pressures of 1.1 × 10⁻⁸ and 1.0 × 10⁻⁷ Torr, respectively. The samples were grown on 2 in. diameter Si(111) substrate with the buffer structures depicted in **Figure 1**. In these structures, the AlN layer was nucleated at 650 °C and growth temperature was ramped up to 920 °C for the rest of the layer while AlₓGa₁₋ₓN (x ≈ 14%) and GaN layers were grown around 800 °C as usual for GaN transistor applications.[15,16] Thanks to a lower concentration of residual donors, NH₃-MBE permits to achieve high resistivity GaN buffer layers, which is critical for HEMTs.[19] Prior to the barrier growth, a 1 nm-thick AlN interlayer is deposited to reduce the penetration of the two-dimensional electron gas (2DEG) wave function into the barrier and limit the alloy scattering responsible for electron mobility degradation. In order to facilitate the direct characterization of the barrier, the HEMT structures were not capped with in situ grown layers such as GaN, AlN, or SiN. However, ScAlN is prone to oxidation. Considering the effective ScAlN barrier thickness is reduced by roughly 2 nm due to the generation of a surface oxide layer, the total barrier thickness is close to the nominal thickness of ScAlN. The ScAlN barrier was grown at 670 °C, the optimum temperature determined in our previous study.[18] The elemental composition of the ScₓAl₁₋ₓN alloy x = 15% was

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The ORCID identification number(s) for the author(s) of this article can be found under https://doi.org/10.1002/pssa.202400963.

© 2025 The Author(s). physica status solidi (a) applications and materials science published by Wiley-VCH GmbH. This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

DOI: 10.1002/pssa.202400963

<footnote>C. Elias, S. Chenot, F. Bartoli, M. Hugues, Y. Cordier
Université Côte d'Azur, CNRS, CRHEA
rue Bernard Grégory, 06560 Valbonne, France
E-mail: yc@crhea.cnrs.fr</footnote>
<figure><img src="image_4.png" /><figcaption>**Figure 1.** Cross-sectional views of a) the 25 nm and b) the 10 nm barrier HEMT grown on silicon.</figcaption></figure>

determined using X-ray photoelectron spectroscopy (XPS) with an aluminum source and confirmed by secondary ion mass spectroscopy (SIMS) on dedicated calibration samples. The crystalline quality of the epitaxial films and especially the ScAlN barrier was assessed using X-ray diffraction (XRD) ω scans (rocking curves) for symmetric (002) and asymmetric (103) reflections. Tapping mode atomic force microscopy (AFM) was used to evaluate the surface roughness of the grown samples. The 2DEG density induced at the barrier/GaN interface was deduced from C–V measurements performed with a mercury probe. Devices for electrical tests were fabricated with a photolithography process similar to the one previously developed for AlGaN/GaN HEMTs[20] and now starting with chlorine-based inductive coupled plasma reactive ion etching (ICP-RIE) followed by e-beam evaporation and 30 s duration rapid thermal annealing (RTA) of Ti/Al/Ni/Au ohmic contacts and deposition of Ni/Au Schottky contacts and access pads for on-wafer measurements with a probe station. Two Keithley 4200 source meters and an Agilent 4284A LCR meter were used for I–V and C–V measurements respectively.

## 3. Results

An example of the surface morphology of grown samples is shown in **Figure 2**. For 5 × 5 µm² scans, it is mainly determined by the kinetic roughening of GaN that generates micrometer diameter mounds with a resulting root mean square (rms) roughness of about 1.5 nm. At a smaller scale (0.5 × 0.5 µm²), the surface morphology of the 25 nm thick ScAlN film is revealed and consists of about 20 nm diameter patterns similar to the ones

<table><caption>**Table 1.** Structural properties of the studied structures.</caption><thead><tr><th>Sample</th><th>XRD FWHM ScAlN (002)/GaN (002)</th><th>XRD FWHM ScAlN (103)/GaN (302)</th></tr></thead><tbody><tr><td>25 nm barrier on Si(111)</td><td>0.63°/0.29°</td><td>0.89°/1.0°</td></tr><tr><td>25 nm barrier on sapphire<sup>[18]</sup></td><td>0.17°/0.10°</td><td>0.20°/0.14°</td></tr><tr><td>10 nm barrier on Si(111)</td><td>0.76°/0.31°</td><td>1.06°/1.17°</td></tr></tbody></table>

observed for films grown on thick GaN buffer layers on sapphire substrate[18] with a rms roughness of 0.44 nm. On the 10 nm barrier structure, such patterns tend to vanish and the roughness is reduced to 0.3 nm. The full width at half maximum (FWHM) of XRD ω scans peaks around the (002) and (103) diffraction planes of ScAlN are reported in **Table 1**, as well as the ones for (002) and (302) diffraction planes of GaN. The FWHM for (002) reflections is more sensitive to threading dislocations with a tilt component Burgers vector (c type dislocations) while for (103) and (302) it is more sensitive to threading dislocations with twist components (a and a + c type dislocations). The FWHM values obtained for a reference structure previously grown on a GaN-on-sapphire template with a threading dislocation density around 4 × 10⁸ cm⁻² are also shown.[18] As shown in Table 1, the comparison of both thick barrier structures reveals diffraction peaks with FWHMs proportional to the ones of GaN. On the silicon substrate, the threading dislocation density in the thin GaN buffer layer is around 10¹⁰ cm⁻² which is considerably larger than on sapphire and explains noticeably larger FWHM values. The 10 nm ScAlN barrier shows even broader diffraction peaks, but according to Debye–Scherrer formalism, the fact that the FWHM values are increased by about 12% only in spite of a thickness reduction by a factor of 2.5 indicates that the crystal quality of the thinner barrier is better than the one of the 25 nm barrier.

The presence of a 2DEG at the interface between the barrier and GaN is attested by the presence of a capacitance plateau as shown in **Figure 3**. The charge density calculated by the integration of the capacitance from pinch-off up to a given bias is also reported. At Vg = 0 V, it reaches around 4 × 10¹³ cm⁻² and 3.1 × 10¹³ cm⁻² for the 25 nm and the 10 nm barrier HEMT respectively while the pinch-off voltage ranges from –20 to –7 V.

The first attempts to make ohmic contacts on the 25 nm barrier HEMT heterostructure with an RTA step at 750 °C failed, but a second annealing at 800 °C enabled to reach a contact resistance below 2 ohm.mm for some parts of the sample. Despite

<figure><img src="image_5.png" /><figcaption>**Figure 2.** AFM views of the surface of HEMTs grown on silicon. a,b) 25 nm barrier with 5 × 5 µm² scan (z-scale 10 nm) and 0.5 × 0.5 µm² scan (z-scale 5 nm) respectively. c) 10 nm barrier with 0.5 × 0.5 µm² scan (z-scale 5 nm).</figcaption></figure>
<figure><img src="image_6.png" /><figcaption>**Figure 3.** C–V measurements performed at 10 kHz with a mercury probe on as-grown sample with a) 25 nm and b) 10 nm barrier.</figcaption></figure>

these large resistances, a saturated drain current $I_{ds}$ superior to 1 A mm⁻¹ (at $V_{gs}$ = 0 V) and a total on-resistance $R_{on}$ below 6 Ω mm⁻¹ have been achieved for a transistor with a 2 µm × 150 µm gate and 9 µm source-drain spacing (**Figure 4a**). This is typically twice the current density we generally achieved on AlGaN/GaN HEMTs. For instance, a similar process on a structure with a 21 nm thick AlₓGa₁-ₓN (x = 30–31%) barrier on 1 nm AlN achieved a contact resistance of 0.6 Ω mm⁻¹ but a maximum drain current $I_{ds}$ = 533 mA mm⁻¹ at $V_{gs}$ = 0 V.[20] At $V_{ds}$ = 6 V, the maximum transconductance of the ScAlN barrier transistor is 100 mS mm⁻¹ whereas the one of the AlGaN barrier one was around 120 mS mm⁻¹. On the 10 nm barrier heterostructure, a single RTA step at 750 °C produced ohmic contacts with resistances ranging from 4 to 10 Ω mm⁻¹. Despite the drain current (Figure 4b) being limited by such contact resistances (maximum $I_{ds}$ of about 200 mA mm⁻¹ at $V_{gs}$ = 0 V, maximum transconductance of 72 mS mm⁻¹ at $V_{ds}$ = 5 V, and total on-resistance $R_{on}$ = 13 Ω mm⁻¹), the transistors are functional with low leakage currents remaining below 1 A mm⁻¹ up to $V_{ds}$ = 100 V, a bias limit imposed by the buffer breakdown voltage as shown in **Figure 5**. This result is encouraging since leakage is a concern for ScAlN barrier HEMTs.[21] Another concern is the discrepancy we can notice for the pinch-off voltage of processed devices compared to values initially recorded by mercury-probe C–V. Measurements performed on 100 µm diameter circular Schottky diodes processed jointly with transistors

<figure><img src="image_7.png" /><figcaption>**Figure 4.** DC output characteristics $I_{ds}$ ($V_{ds}$, $V_{gs}$) of 2 µm gate transistors with 9 µm source-drain spacing fabricated on the ScAlN/GaN HEMT grown with a) a 25 nm and b) a 10 nm barrier.</figcaption></figure>

<figure><img src="image_8.png" /><figcaption>**Figure 5.** Three-terminal off-state leakage currents of 2 µm gate transistors with 9 µm source-drain spacing fabricated on the ScAlN/GaN HEMT grown with a 10 nm barrier. The GaN-on-Si buffer leakage current is also represented.</figcaption></figure>

reveal a noticeable shift of the pinch-off voltage accompanied by an increase of the capacitance attesting to a significant reduction of the barrier thickness (**Figure 6**). Such change is probably due to the lack of stability of the scandium oxide formed at the surface with respect to chemical products like the photoresist developer. As a result, the charge density in the fabricated devices is reduced to about 3 × 10¹³ cm⁻² and 2 × 10¹³ cm⁻² for the 25 nm and the 10 nm barrier HEMT respectively, consistent with the 2DEG sheet carrier concentration measured by Hall effect. Thus, a capping strategy will be necessary to benefit the very high carrier density achievable in such heterostructures.
<figure><img src="image_9.png" /><figcaption>**Figure 6.** Comparison of C–V measurements performed with a mercury probe (Hg probe) on as-grown sample (continuous lines) and on a 100 µm diameter circular diode (dashed lines) for a) 25 nm and b) 10 nm barrier HEMTs.</figcaption></figure>

**4. Conclusion and Perspectives**

As was the case for the AlGaN/GaN system, the present study shows that ammonia source MBE can be considered as an alternative technique to grow ScAlN/GaN HEMTs on a silicon substrate. In the present work, the heterostructures have been grown with thin buffer layers. Despite the difficulties in achieving low resistance ohmic contacts, transistors with drain current superior to 1 A mm⁻¹ have been fabricated on a thick barrier HEMT structure. The regrowth of highly doped GaN ohmic contacts could be envisaged to reduce contact resistances[22] and to achieve even larger currents, especially for thin barrier structures, but a priority will be a capping strategy to protect ScAlN from etching during the device process. According to Manz et al.[8] in situ deposited Si₃N₄ may be an interesting way for this purpose. On the other hand, limited drain and gate leakage currents were obtained for a transistor fabricated on a resulting sub-10 nm barrier whose breakdown seems limited by the leakage in the thin buffer layer. The growth of such HEMT on a more robust thin[23] or thick[24] buffer may be a way to answer the question if the leakage is limited by defects in the barrier or by the buffer itself.

**Acknowledgements**

This work was supported in part by the European Project GaN4AP (Gallium Nitride for Advanced Power Applications). The project has received funding from the Electronic Component Systems for European Leadership Joint Undertaking (ECSEL JU), under grant agreement no. 101007310. This Joint Undertaking receives support from the European Union's Horizon 2020 research and innovation program and Italy, Germany, France, Poland, Czech Republic, Netherlands. It was also supported by the French National Research Agency (ANR) through the "Investissements d'Avenir" program GaNeX (ANR-11-LABX-0014), and the French technology facility network RENATECH.

**Conflict of Interest**

The authors declare no conflict of interest.

**Data Availability Statement**

The data that support the findings of this study are available from the
corresponding author upon reasonable request.

**Keywords**

high electron mobility transistors, molecular beam epitaxy, scandium
aluminum nitride

Received: December 2, 2024

Revised: January 9, 2025

Published online:

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