# Process Variability Impact on the SET Response of FinFET Multi-level Design

Leonardo H. Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Reis

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Leonardo H. Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Reis. Process Variability Impact on the SET Response of FinFET Multi-level Design. 27th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC), Oct 2019, Cusco, Peru. pp.89-113, 10.1007/978-3-030-53273-4_5. hal-03476601

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# Process Variability Impact on the SET Response of FinFET Multi-level Design

Leonardo H. Brendler¹, Alexandra L. Zimpeck², Cristina Meinhardt³, and
Ricardo Reis¹

¹Institute of Informatics, PGMICRO/PPGC,
Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, RS, Brazil
{lhbrendler, reis}@inf.ufrgs.br

²Graduate Program in Electronic and Computer Engineering,
Catholic University of Pelotas (UCPEL), Pelotas, RS, Brazil
alexandra.zimpeck@ucpel.edu.br

³Department of Informatics and Statistics,
Federal University of Santa Catarina (UFSC), Florianópolis, SC, Brazil
cristina.meinhardt@ufsc.br

**Abstract.** Challenges were introduced in integrated circuits design due to the technology scaling. The evolution of integrated circuits has made them more susceptible to the radiation effects, besides increasing the manufacturing process variability. These challenges can lead to circuits operating outside their specification ranges. Transistor arrangement influences the performance of logic cells; complex logic gates can be used to minimize area, delay and power consumption. However, with the increasing relevance of nanometer challenges, it is necessary also to consider these factors at logic level design. This work explores different transistor arrangements for a set of logic functions at the layout level to evaluate the SET response under the process variability. The process variability is analyzed through the work-function fluctuations of the metal gate. The complex gate and the multi-level of NAND2 topologies, that implement the same function, were designed using the 7nm FinFET ASAP7 Process Design Kit. Results show that the multi-level topology is more robust to the radiation effects at both ideal fabrication process and considering the process variability impact. The LETth value considering the multi-level topology is on average 55% higher than the values considering the complex topology. Moreover, all the logic functions analyzed independently of the topology are more sensitive to the SETs considering the impact of the process variability.

**Keywords:** FinFET technology · Multi-level design · Process variability · Soft errors · Single event transient

## 1 Introduction

The radiation-induced soft errors and the process variability are an essential reliability concern for nanotechnologies, affecting integrated circuits used for
space or even terrestrial applications [1, 2]. Variability is related to the random
deviation, which causes an increase or decrease of typical design specifications.
The primary variability issue is the uncertainty about the correct operation of
the circuit. There is no guarantee that a circuit will behave as expected after the
manufacturing process. Due to the variability effects, each circuit can present a
different electrical behavior such as abnormal power consumption, performance
deviation, or both. The unexpected behavior due to variations can stimulate
circuit degradation besides make it inappropriate for your initial purpose.

Electronic circuits operating in space, especially in harsh environments, may be exposed to significant radiation doses as well as to the incidence of heavy particles from the sun or from outside the galaxy. From this exposure to radiation, changes and disturbances in the circuit can occur with high probability. Degradations that arise due to the incidence of a single particle are called Single Event Effects (SEE). If this single-particle causes a permanent failure in the circuit, it is considered a hard error. In case of an error in the system that does not cause permanent damage, it is called Single Event Transient (SET) or Non-Destructive (soft error) [3, 4].

For a long time, SETs were not considered a significant reliability concern. The logical, electrical and latching window masking present in digital logic, were enough to minimize the importance of considering the phenomenon. However, with technology scaling, lower supply voltages and reduced nodal capacitances, the minimum charge required to induce a transient pulse was decreased [2, 5]. Also, it is more likely that a SET generated in combinational logic will be captured at the storage element due to the higher operating frequencies. Thus, to overcome some of these problems, new device architectures and novel materials are being used.

Multigate devices have allowed the further scaling of transistors by providing better control of Short-Channel Effects (SCE), lower leakage currents and better yield [6]. On multigate devices, variability effects are mainly due to the work-function fluctuation (WFF) of the metal gate [7, 8]. FinFET (Fin-Shaped Field Effect Transistor) technology is the main multigate device replacing bulk MOSFET devices in sub-22nm technology nodes [7]. Due to its limited sensitivity volume compared to planar devices, the charge collection region is reduced in this technology [9, 10], showing a better response to radiation effects, even considering the technology scaling. However, the radiation effects are not negligible on multigate devices [11].

The proper estimation of Threshold Linear Energy Transfer (LETth) along with the SET pulse width is of utmost importance for soft error (SE) mitigation and radiation-tolerant circuit design [12]. Also, few papers analyze the impact of process variability on the SET. The impact of process variability on on-state ($I_{on}$) and off-state ($I_{off}$) currents using FinFET technology in a set of technological nodes ranging from 20nm to 7nm is compared in [13]. The prominence is in the evaluation of Metal Gate Granularity (MGG) impact on the work-function (WF) of the gate. The results demonstrate the importance of not only evaluating
variations in threshold voltage but also in other parameters and the significant
influence of WFF in the threshold voltage and the I<sub>on</sub> and I<sub>off</sub> currents.

Regarding the radiation effects, a comparative soft error evaluation of logic gates in bulk FinFET technology using various technological nodes is presented in [9]. The main objective is allowing for estimating the SER of logic gates for ground applications, as well as for understanding the impact of voltage and drive strength through analysis o the sensitivity to soft errors. Also, similar work highlights the robustness of the 7nm FinFET technology, considering other logic functions [14] and also majority voter circuits [15]. The latter also analyzes the impact of process variability on the SET.

In this context, this work investigates the radiation robustness, considering
the process variability effects, of a set of logic functions implemented in two dif-
ferent transistor topologies using 7nm FinFET technology [16]. The SET pulse
width was obtained and the LETth was calculated to characterize the SET re-
sponse. First, a radiation robustness analysis is performed considering only the
ideal behavior, and then the process variability impact is considered. The main
contributions of this work are: 1) to provide an evaluation of the SET sensi-
tivity trends for complex logic gates, exploring the use of different transistor
arrangements; 2) to consider the impact of process variability effects and radia-
tion sensibility together on the analysis, and 3) to present a detailed investigation
about the topology relation with the FinFET logic cells robustness through the
LETth.

Next Section summarizes the main radiation effects, including their origins
and the behavior on FinFET devices. Section 3 presents the process variability
effects on FinFET technology, focusing on the WFF of the metal gate. Section 4
describes the methodology steps to observe these effects on multi-level and com-
plex gate designs. With the set of information from the evaluations, this work
discusses the results in Section 5 and present the main conclusions in Section 6.

## 2 Radiation Effects

The dynamic scaling alongside the low supply voltages, large transistor density, and the high-frequency operation introduce new reliability issues in integrated circuits, such as the high Single Event Effects (SEE) sensitivity and multi-charge collection [9, 17]. This chapter presents the main concepts and characteristics of the radiation effects on electronic circuits. The focus is on SEEs, especially the impact of transient faults on devices. Before detailing these effects, it is important to present their origins.

Anomalies induced by the radiation effects on electronic circuits are known
from the beginning of space exploration. The research aimed at the study of the
radiation effects on electronic circuits was initially considered a concern of utmost
relevance only in projects developed for military or space applications. The Earth
is protected by the atmosphere, which acts as a semi-permeable “screen”, to let
throughout light and heat, while stopping radiation and ultraviolet rays (UVs)
[3]. The intensity of the radiation basically increases according to the increase
in altitude relative to ground level. However, due to phenomena related to the
earth's magnetic field (the polar regions are an example), some regions suffer
from a higher intensity of radiation even though they are located at low altitudes.

In space and the Earth's atmosphere, there is a diverse range of radiation, which is classified into two broad groups: ionizing particles and non-ionizing particles. The main particles that may cause unwanted effects in electronic circuits are electrons, protons, neutrons, muons, alpha particles and heavy ions, as well as electromagnetic radiation, such as x-rays and gamma rays [4]. At sea level, muons are the most numerous terrestrial species [18]. The primary components of radioactive phenomena encountered in space can be classified into four categories by origin: Radiation belts, solar flares, solar wind and cosmic rays [3]. Fig. 1 shows the relationship between the Sun and the Earth that gave rise to these phenomena.

<figure><img src="image_2.png" /><figcaption>Fig. 1. Radiation effects from the Sun-Earth relationship [19].</figcaption></figure>

**2.1 Characterization of the Radiation Effects on Electronic Devices**

The effects related to the incidence of radiation in electronic components have
been studied for a long time by the international scientific community, mainly
for space and military applications. The integrated circuits that experience the
interaction of ionizing particles basically suffer from two types of degradation:
those of singular character, occurring due to the incidence of a single particle, and those of a cumulative nature, which occur due to the accumulation of doses of ionizing radiation over the lifetime of the circuit.

Cumulative effects have their origin due to the dose of ionizing radiation accumulated over the life of the device and are classified as Total Ionizing Dose (TID). Prolonged exposure to ionizing radiation, due to accumulated (radiation-induced) electric charges, causes parts of the circuit to change in their electrical characteristics, such as a change in threshold voltage ($V_{th}$) and the increase in the leakage current of the device. These electrical changes impair the correct functioning of the device and may, depending on the amount of accumulated dose, permanently damage it.

The TID response of bulk silicon and SOI FinFETs are significantly different in terms of radiation-induced $V_{th}$ and $I_{off}$ current. Bulk silicon FinFET radiation tolerance is reduced due to an increase in $I_{off}$, and SOI FinFET radiation tolerance is reduced due to $V_{th}$ shifts [20]. Bulk FinFETs have a similar TID response as planar bulk MOSFETs, that is, the buildup of oxide-trapped charge in the STI triggers a parasitic lateral transistor that modifies the electrical characteristics (higher $I_{off}$) [21]. Degradations that occur due to the incidence of a single particle are called Single Event Effects (SEE), these effects will be presented with more details next.

**Single Event Effects** The Single Event Effects occur due to the interaction of large ionizing particles (protons, neutrons, $\alpha$ particles and heavy ions) that pass through insulation, semiconductor layers, or even all MOS device. These particles, when entering the silicon material, generate a transient path composed of ionized elements (electron-hole pairs - $e^/-h$) arranged under a radial distribution that permeates the path of the incident particle. This transient path may have sufficient mobile charge to drive a current pulse against the presence of the external electric field due to the polarization of the transistor [22].

SEEs indicate any measurable or observable change in a state or performance of a nanoelectronic device, component, subsystem or system (digital or analog) as a result of the incidence of a single energetic particle. According to the intensity and the region in which this current flows, it is capable of causing faults that may be permanent in the device structure, called destructive events (hard error), or non-destructive (soft errors), represented by the Single Event Transient (SET) and the Single Event Upset (SEU) [23]. Fig. 2 presents the classification of the major SEEs in the literature. The focus of this work is the SET effect, which occurs in combinational circuits.

The most common transient effects on combinational circuits are the SETs, in which the incidence of an ionized particle produces a transient pulse that can propagate through a logic path and be latched by memory elements. The transient pulse is generated by the interaction of energetic particles near a sensitive region of a transistor when the collected charge ($Q_{coll}$) exceeds the critical charge ($Q_{crit}$). However, in sub-22nm technological nodes other phenomena must also be considered in the characterization of the transient pulse. The influence of charge-
<figure><img src="image_3.png" /><figcaption>Fig. 2. Classification of major Single Event Effects. Modified from [24].</figcaption></figure>

sharing (charge collected by multiple transistors for a single incident particle) mechanism does not seem to have diminished for the FinFET technology. TCAD results show the extent of electrical perturbations and charge-sharing similar to what has been observed for older technologies. This effect can cause the pulse quenching in ion-induced transients, resulting in a reduced overall sensitivity of the system against SEE [25].

To quantify the SET effects, characteristics such as amplitude, shape and current pulse duration are important quantities [26]. The amplitude and duration of a SET depend on factors such as the fabrication technology, the circuit geometry, the bias voltage of the affected node, node load impedance, location of the transistor reached by the particle, in addition to factors related to the SEE itself, as the type and energy of the incident particle [26].

The energy deposited by a particle due to its ionization in silicon is an essential metric in the study of radiation effects in nanotechnologies because it is directly related to the magnitude of the generated transient pulse. Linear Energy Transfer (LET) (shown in Eq. 1) is the amount of energy that a particle releases per unit of compliance from the path traveled by it.

$$LET = \frac{\partial E}{\partial x} \qquad (1)$$

The LET is dependent on the mass and energy of the particle and the ionized material, so particles with higher mass and energy ionized in denser materials have higher LETs [27]. Threshold LET (LETth) is the minimum LET to cause an effect in the circuit [11].
The disruptive nature of the FinFET structure introduces questions in terms of understanding, predicting and mitigating SEEs in circuits. The 3D structure of FinFET devices is favorable to reduce the soft error vulnerability according to several works available in the literature [10, 28, 29]. This reduction of the soft error vulnerability happens because the sensitive areas of FinFETs are little exposed to the charge collection region as shown in Fig 3. FinFET technologies collect significantly less charge than conventional planar technologies. The work of [30] indicates that charge collection for semiconductor regions in FinFET technologies is approximately reduced by 70% compared to planar technologies. From a design standpoint, the accurate estimation of SEE susceptibility is crucial to ensure reliable circuits.

<figure><img src="image_4.png" /><figcaption>**Fig. 3.** Comparison of charge collection mechanism between FinFET devices and Planar CMOS technologies [29].</figcaption></figure>

Although FinFET technology is more robust to soft errors than planar tech-
nologies, there are still many concerns that justify the study of this device. The
process variability, one of the main challenges in sub-22nm technologies, can
modify the LETth to induce a soft error. Ultra-Low-Power (ULP) circuits are
increasingly being used, and low voltages increase the probability of SE occur-
rence. Also, with the demand for devices increasingly faster, the operation fre-
quency increases, also increasing the possibility of a memory element capturing
a SE.

3 Process Variability Effects on FinFET Devices

The variability in electronic circuits can be divided into three different factors: environmental, reliability and physical [31]. Environmental factors appear during the circuit operation; variations in supply voltage and temperature are examples
of environmental factors. Reliability factors are related to the transistor aging, due to the high electric fields presented in modern circuits. Finally, physical factors are associated with variations in electrical and geometrical parameters, which may occur due to the manufacturing process of the devices [31]. The latter is best known for process variability and is the focus of this study. This chapter details the main features of the process variability, showing its impact on FinFET devices and highlighting the most significant parameter for their effects.

The primary sources of process variability at nanometer nodes are due to the sub-wavelength lithography [31, 32]. The variability on geometric parameters impact directly the transistor threshold voltage. These variations can compromise the entire blocks of cells or reduce the performance and energy efficiency of the chip. Some expected sources of variability for FinFETs are highlighted in [33]: the influence of variations in the fins height, the width variations across the double-standard layers, the variations of the fin to fin, the dependent variations the width of the pitch, the resistance of MOL (Middle of Line), and variations due to the overlap and the epitaxy. The main FinFET parameters and possible variability sources are shown in Fig. 4.

<figure><img src="image_5.png" /><figcaption>Fig. 4. Possible sources of FinFET variability [34].</figcaption></figure>

For nanotechnology bulk CMOS devices, the geometric variability in the gate length has the greatest impact on the change of $I_{on}$ current due to the random fluctuation in the dopants of the channel [35]. However, in FinFET devices, another parameter has a more significant impact. As a result of the active format of the fins, the fin channel is weakly doped to minimize variations in $V_{th}$. As
a consequence, the $V_{th}$ of weakly doped channels is mainly configured by the working-function of the metals adopted in the gate. The use of metal as gate material introduced some fluctuation in the work-function of the gate, mainly due to the presence of MGG.

Thus, although variations in gate length, fin height and fin width influence the electric behavior of FinFET devices, the fluctuations of the metal gate work-function are the main source of expected variability for FinFETs sub 20nm [36, 37, 13]. Fig. 5 illustrates this behavior considering the impact on the $I_{on}$ current.

<figure><img src="image_6.png" /><figcaption>Fig. 5. Impact on $I_{on}$ current due to work-function fluctuation [13].</figcaption></figure>

In the ideal fabrication process, metal gates devices have the gates produced with a unique metal uniformly aligned and very lower work-function deviation. Nevertheless, in a real fabrication process, metal gate devices are generally produced with metals with different WF randomly aligned that implies in higher WFF. WFFs are locally induced due to the polycrystalline nature of the metal lead to potential surface variations, and it is caused by the dependency of metal WF on the orientation of its grains, as illustrates the Fig. 6. The $V_{th}$ fluctuation due to MGG is close to a Gaussian distribution, and the standard deviation is almost linearly proportional to metal-grain size [32].

# 4 Methodology

This work explores different transistor arrangements for a set of four logic functions (OAI21, OAI22, AOI211 and XOR) at the layout level to evaluate the SET
<figure><img src="image_7.png" /><figcaption>**Fig. 6.** FinFET devices: main geometric parameters and the random alignment of metal in real devices. Modified from [32] and [13].</figcaption></figure>

response under the process variability. Two different topologies of transistor arrangement are investigated: 1) complex gate: optimized functions designed as a complex logic gate CMOS topology; and 2) the multi-level logic of NAND2 gates: the functions are converted using De Morgan's theorem into the only NAND2 transistor arrangements. Previous experiments also considered topologies using only NOR2 and a mix of NAND2-NOR2-INV. However, the only NAND2 topology proved to be better, and it was chosen for this study [38]. Table 1 and Table 2 present the logic functions and the equations for the complex gate version and the converted multi-level logic composed by NAND2 version, respectively. Although they represent the same functions, the versions are intrinsically different, which is interesting, since the comparison of similar versions does not present many advantages about the variability [39]. Fig. 7 presents the schematics of the OAI21 gate in its two versions highlighting all the sensitive nodes that were considered in the worst radiation sensitive case evaluation, which will be described in subsection 4.1.

<table><caption>**Table 1.** Complex gate functions. Modified from [40]</caption><thead><tr><td>Logic Function</td><td>Complex Gate</td></tr></thead><tbody><tr><td>OAI21</td><td>Y = (A+B . C)'</td></tr><tr><td>OAI22</td><td>Y = (A+B . C+D)'</td></tr><tr><td>AOI21</td><td>Y = (A.B + C + D)'</td></tr><tr><td>XOR</td><td>Y = A.B' + A'.B</td></tr></tbody></table>

All layouts were designed using the 7nm FinFET ASAP7 Process Design Kit (PDK), developed by Arizona State University in partnership with ARM [16]. Among the different models and corners available on this PDK, this work considers the regular threshold voltage (RVT) transistor model at typical (TT)
<table><caption>**Table 2.** Multi-Level Logic functions. Modified from [40]</caption><thead><tr><th>Logic Function</th><th>Multi-level version with NAND2 gates</th></tr></thead><tbody><tr><td>OAI21</td><td>Y = (((A.A)' . (B.B)')' . C)'</td></tr><tr><td>OAI22</td><td>Y = (((A.A)' . (B.B)')' . ((C.C)' . (D.D)')')'</td></tr><tr><td>AOI211</td><td>Y = (X . X)' | X = (((A.B)' . (((C.C)' . (D.D)')' . ((C.C)' . (D.D)')')'')'</td></tr><tr><td>XOR</td><td>Y = ((A . (B.B)')' . ((A.A)' . B)')'</td></tr></tbody></table>

<figure><img src="image_8.png" /><figcaption>**Fig. 7.** OAI21 schematic in complex and multi-level transistor arrangements. Modified from [40].</figcaption></figure>

corner. Table 3 summarizes the key devices parameters of 7nm FiFET ASAP technology. The nominal supply voltage is 0.7V, at a typical temperature of 25°C.

The layout of all cells adopts three fins as transistor sizing as recommended in the PDK to allow the internal routing of the cells [16]. The cell height is set to 7.5 tracks of metal 2 (M2) that correspond to 0.27µm for all evaluated cells. The PDK assumes Extreme Ultraviolet (EUV) lithography for key layers, a decision based on its present near cost-effectiveness and resulting simpler layout rules. Non-EUV layers assume appropriate multiple patterning schemes, i.e., self-aligned quadruple patterning (SAQP), self-aligned double patterning (SADP) or litho-etch litho-etch (LELE), based on 193nm optical immersion lithography [16]. The design rules, actual dimensions and underlying assumptions for some major layers are shown in Table 4.

The specific design rule derivation is explained for key layers at the front end of line (FEOL), middle of line (MOL) and back end of line (BEOL) of the predictive process modeled. As an example, the layout of OAI21 gate is
<table><caption>**Table 3.** Key parameters of 7nm FinFET ASAP technology [16]</caption><thead><tr><th>Parameters</th><th>7nm</th></tr></thead><tbody><tr><td>Supply Voltage</td><td>0.7V</td></tr><tr><td>Gate Length (L<sub>G</sub>)</td><td>21nm</td></tr><tr><td>Fin Width (W<sub>FIN</sub>)</td><td>6.5nm</td></tr><tr><td>Fin Height (H<sub>FIN</sub>)</td><td>32nm</td></tr><tr><td>Oxide thickness (Tox)</td><td>2.1nm</td></tr><tr><td>Channel Doping</td><td>1&times;10<sup>22</sup>m<sup>-3</sup></td></tr><tr><td>Source/Drain Doping</td><td>2&times;10<sup>26</sup>m<sup>-3</sup></td></tr><tr><td>Work Function</td><td>NFET 4.3720eV<br>PFET 4.8108eV</td></tr></tbody></table>

presented on Fig. 8a and Fig. 8b in complex gate and multi-level logic topologies, respectively.

All layouts were validated by Design Rule Check (DRC) and Layout Versus Schematic (LVS) steps. The extracted netlist with parasite capacitances is obtained and it was used for the radiation sensitivity evaluation. From the extracted netlist, SPICE simulations are performed. The input switching frequency is set at 500MHz and inverters are connected to the input sources introducing realistic delays to the cells. The project flow carried out in this work can be seen in Fig. 9.

<table><caption>**Table 4.** Key layer lithography assumptions, widths and pitches [16]</caption><thead><tr><th>Layer</th><th>Lithography Width/drawn (nm)</th><th>Pitch (nm)</th></tr></thead><tbody><tr><td>Fin</td><td>SAQP</td><td>6.5/7</td></tr><tr><td>Active (horizontal)</td><td>EUV</td><td>54/16</td></tr><tr><td>Gate</td><td>SADP</td><td>21/20</td></tr><tr><td>SDT/LISD</td><td>EUV</td><td>25/24</td></tr><tr><td>LIG</td><td>EUV</td><td>16/16</td></tr><tr><td>VIA0-VIA3</td><td>EUV</td><td>18/18</td></tr><tr><td>M1-M3</td><td>EUV</td><td>18/18</td></tr><tr><td>M4 and M5</td><td>SADP</td><td>24/24</td></tr><tr><td>VIA4 and VIA5</td><td>LELE</td><td>24/24</td></tr><tr><td>M6 and M7</td><td>SADP</td><td>32/32</td></tr><tr><td>VIA6 and VIA7</td><td>LELE</td><td>32/32</td></tr><tr><td>M8 and M9</td><td>SE</td><td>40/40</td></tr><tr><td>VIA8</td><td>SE</td><td>40/40</td></tr></tbody></table>

<footnote>a Corner to corner spacing as drawn.</footnote>

<footnote>b Horizontal only.</footnote>
<figure><img src="image_9.png" /><figcaption>(a) OAI21</figcaption></figure>

<figure><img src="image_10.png" /><figcaption>(b) OAI21_NAND</figcaption></figure>

**Fig. 8.** OAI21 layout in the two topologies: (a) complex and (b) multi-level of NAND2 [40].

The SET fault injection is modeled as the Messenger’s equation shown in Eq. 2 [41], where $Q_{coll}$ is the collected charge, $\tau_{\alpha}$ ($1.64 \times 10^{-10}$ s) is the collect charge timing constant, $\tau_{\beta}$ ($5 \times 10^{-11}$ s) is the timing constant to establish the ion track and $L$ (21 nm) is the charge collection depth. The values used in this work are the typical values used for simulations and experiments in silicon presented in [42], but modified to better characterize recent technologies, such as FinFET. This effect is reproduced on the SPICE simulation as a current source, simulating the SET effects on the transistors.
<figure><img src="image_11.png" /><figcaption>Fig. 9. Project flow for all analyzes [40].</figcaption></figure>

$$I(t) = \frac{Q_{coll}}{\tau_{\alpha} - \tau_{\beta}} (e^{-\frac{t}{\tau_{\alpha}}} - e^{-\frac{t}{\tau_{\beta}}}) \qquad (2)$$

$$Q_{coll} = 10.8 \times L \times LET$$

## 4.1 Worst Radiation Sensitive Case

The first step in the radiation sensitivity evaluation was to identify the most sensitive node and input vector at each circuit. A fault injection campaign for a particle with LET estimated to 58 Mev.cm²/mg was performed at each node of the circuits, as shown in Fig. 7 considering all possible input vectors. The definition of 58 Mev.cm²/mg as the LET value used for the fault injection campaign was performed considering the highest LET that still characterizes a simulation at the ground level (LET ≤ 60 Mev.cm²/mg) [43, 44]. Two inverters were used for each input of the circuit and a single inverter for the output, to emulate the worst fan-out scenario, i.e. lowest fan-out (FO1). Consider the amplitude and the width of the SET pulses allow determining which node and input vector are the most sensitive [11] and characterize the worst radiation sensitive case. After the worst radiation sensitive case was obtained, each logic gate was fault injected considering this sensitive scenario, i.e., the most critical node, the sensitive input vector and the waveform of the pulse (strikes at P-type devices or N-type devices).

## 4.2 The SET response at the Ideal Fabrication Process

This step evaluates the circuit under radiation effects but the effects of process variability are not considered. The LETth and the SET pulse width are used to characterize the SET response. Before starting the fault injection in the circuit, it is important to know the worst-case delay of each logic gate, which will be used to determine the LETth. Thus, the worst-case delay of each logic function considering both topologies was obtained. In this work, it is considered the SET effects, more specifically, when a transient pulse propagates to the inverter
chain output. To calculate the LETth, two characteristics of the SET pulse were considered: amplitude and width. A fault in the circuit is considered when the SET pulse amplitude exceeds half of the nominal supply voltage ($V_{DD}$/2) and the SET pulse width is greater than the circuit worst-case delay. That is, the metrics of the worst-case delay and the SET pulse width are used in obtaining the LETth, which is the primary metric used in this work. These values are used as a form of reference values to evaluate the process variability effects.

## 4.3 Process Variability Analysis

The analysis considering the process variability effects is performed keeping the same configurations of the previous step, however, considering the impact of the process variability through the WFF. Metal gate devices suffer from the WFF caused by the misalignment of metal grains in the gate. This fluctuation exhibits a multi-nominal distribution, which can be approximated by a Gaussian distribution if the number of grains on the surface of metal-gate is high enough (>10) [45], which corresponds to the FinFET ASAP7 model characteristics. The WFF effect due to process variation is explored through the statistical Monte Carlo simulation process, considering a Gaussian distribution with a 3-sigma deviation of 5% the WFF [13]. Two thousand simulations were run for each logic gate [45]. No correlation between different types of transistors was assumed, which means that PFET and NFET devices may come up with different variations in its parameters. Timing, SET pulse amplitude and width measurements were taken for each Monte Carlo simulation. The mean ($\mu$) of these values is considered to calculate a new LETth, i.e., a LETth that considers the process variability impact. Also, the standard deviation ($\sigma$) of the mean values is obtained and a robustness analysis is performed using the normalized standard deviation ($\sigma/\mu$) of the SET pulse width. The $\sigma/\mu$ is used to define how much a circuit is sensitive to process variability. The lower are the values of this ratio; the more robust to variability are the circuits.

# 5 Results

The worst radiation sensitive case was obtained before characterizing the SET response. The critical node, the most sensitive input vector and the transient pulse format, which compose the worst-case scenario for each logic function in both topologies are presented in Table 5.

To characterize the fault at a given node of the circuit, it is evaluated whether the SET pulse propagates to the circuit output. Thus, the probability of the critical node being the output itself is very high and this behavior is proven in the obtained results for both topologies. It can be seen that the most sensitive input vectors vary even considering the same logic function, due to the use of a different transistor arrangement. For OAI21 and AOI211 gates this difference between the input vectors is reflected in the format of the transient pulse (SET 101 or SET 010) that will be inserted in the node. Fig. 10 demonstrates this behavior in more detail for the OAI21 gate.
<table><caption>Table 5. Worst Radiation Sensitive Case [40]</caption><thead><tr><th>Logic Function</th><th>Worst Radiation Sensitive Case</th><th colspan="2">Complex Gate Multi-level</th></tr></thead><tbody><tr><td rowspan="3">OAI21</td><td>Critical Node</td><td>OUT</td><td>OUT</td></tr><tr><td>Input Vector</td><td>001</td><td>011</td></tr><tr><td>Transient Pulse</td><td>1-0-1</td><td>0-1-0</td></tr><tr><td rowspan="3">OAI22</td><td>Critical Node</td><td>OUT</td><td>OUT</td></tr><tr><td>Input Vector</td><td>1001</td><td>0101</td></tr><tr><td>Transient Pulse</td><td>0-1-0</td><td>0-1-0</td></tr><tr><td rowspan="3">AOI211</td><td>Critical Node</td><td>OUT</td><td>OUT</td></tr><tr><td>Input Vector</td><td>0000</td><td>0101</td></tr><tr><td>Transient Pulse</td><td>1-0-1</td><td>0-1-0</td></tr><tr><td rowspan="3">XOR</td><td>Critical Node</td><td>OUT</td><td>OUT</td></tr><tr><td>Input Vector</td><td>11</td><td>11</td></tr><tr><td>Transient Pulse</td><td>0-1-0</td><td>0-1-0</td></tr></tbody></table>

## 5.1 SET evaluation under the ideal fabrication process

The worst-case propagation delays of the four logic functions in the two topologies, considering the ideal fabrication process, are shown in Table 6. In addition to presenting some differences in performance between the use of complex and multi-level topologies, the propagation times are necessary to obtain the LETth.

<table><caption>Table 6. Worst-case propagation delay at nominal conditions [40]</caption><thead><tr><th rowspan="2">Logic Function</th><th colspan="2">Worst-case delay (ps)</th></tr><tr><th colspan="2">Complex Gate Multi-level</th></tr></thead><tbody><tr><td>OAI21</td><td>7.79</td><td>18.29</td></tr><tr><td>OAI22</td><td>9.63</td><td>18.48</td></tr><tr><td>AOI211</td><td>13.42</td><td>36.63</td></tr><tr><td>XOR</td><td>11.68</td><td>20.02</td></tr></tbody></table>

Fig. 11 shows the SET pulse width measured when the amplitude of this same pulse exceeds half of the nominal supply voltage. To calculate the LETth of each logic gate, it is important to note that all values of the SET pulse width shown in Fig. 11 are greater than the worst-case delays shown in Table 6, characterizing the fault in the circuit output. The SET pulse width values follow much the same behavior as the delay values. The multi-level topology presents SET pulse width about 77% larger in comparison to the complex topology. This behavior does not necessarily mean a higher sensitivity of the multi-level topology to the radiation effects. The SET pulse width considering ideal fabrication tends to be higher for the multi-level topology since the functions implemented in this transistor arrangement are slower than the same ones implemented in the
<figure><img src="image_12.png" /><figcaption>**Fig. 10.** The difference of transient pulse format inserted in the critical node (OUT) of complex and multi-level topologies of OAI21 gate [40].</figcaption></figure>

complex topology. That is, if the SET pulse width is less than the logic gate delay, the fault would be masked.

The larger SET pulse width of the multi-level topology is not reflected in the LETth calculation, as can be seen in Table 7. LETth values may seem high considering the analyzed logic gates. However, similar work highlights the robustness of the 7nm FinFET technology, considering other logic functions [14] and also majority voter circuits [15]. NAND and NOR voters have no-fault event (at nominal supply voltage) considering a LET value of 15 Mev.cm²/mg, for example [15]. For the OAI21 and AOI211, the LETth considering the multi-level topology is 40.54% and 72% higher than the LETth of the complex topology, respectively. XOR gate and the OAI22 gate present a difference practically null, approximately 1%. The results demonstrate that multi-level topology is more robust to the radiation effects considering the ideal fabrication process since it presents higher LETth values in comparison with complex topology. This behavior is related to the regularity of the layouts developed. The OAI22 and XOR gates, even in the complex topology, are already quite regular. Therefore, the use of multi-level topology for these functions has practically no impact.
<figure><img src="image_13.png" /><figcaption>Fig. 11. SET pulse width at the ideal fabrication process [40].</figcaption></figure>

<table><caption>Table 7. LETth at ideal conditions [40]</caption><thead><tr><th rowspan="2">Logic Function</th><th colspan="2">LETth (Mev.cm<sup>2</sup>/mg)</th></tr><tr><th>Complex Gate</th><th>Multi-level</th></tr></thead><tbody><tr><td>OAI21</td><td>33.3</td><td>46.8</td></tr><tr><td>OAI22</td><td>47.4</td><td>46.8</td></tr><tr><td>AOI211</td><td>27.5</td><td>47.3</td></tr><tr><td>XOR</td><td>46.8</td><td>46.9</td></tr></tbody></table>

## 5.2 The SET response under WFF

As the analysis carried out considering only the radiation effects, in the process variability analysis, the worst-case propagation delay of each logic gate is also measured but considering the WFF impact. Table 8 shows the mean ($\mu$), standard deviation ($\sigma$) and normalized standard deviation ($\sigma/\mu$) of the delays for all analyzed logic gates.

Fig. 12 shows the mean of the SET pulse width for each logic function implemented in the two topologies, considering the WFF impact. Unlike the analysis under ideal conditions, on average the SET pulse width for complex topology is higher ranging from 4ps to 9ps of difference in comparison with the multi-level topology. Only for the AOI211 gate that this ratio is not established and the SET pulse width for the multi-level topology is still about 4ps higher. Considering only the SET pulse width, the complex topology is more sensitive to the process variability effects.
<table><caption>**Table 8.** Worst-case propagation delay under WFF [40]</caption><thead><tr><th rowspan="3">Logic Gates</th><th colspan="6">Worst-case delay (ps)</th></tr><tr><th colspan="3">Complex Gate</th><th colspan="3">Multi-level</th></tr><tr><th>μ</th><th>σ</th><th>σ/μ (%)</th><th>μ</th><th>σ</th><th>σ/μ (%)</th></tr></thead><tbody><tr><td>OAI21</td><td>8.43</td><td>2.56</td><td>30.37</td><td>19.21</td><td>4.00</td><td>20.83</td></tr><tr><td>OAI22</td><td>11.18</td><td>3.43</td><td>30.71</td><td>19.42</td><td>4.08</td><td>21.02</td></tr><tr><td>AOI211</td><td>14.71</td><td>4.64</td><td>31.56</td><td>38.52</td><td>7.62</td><td>19.78</td></tr><tr><td>XOR</td><td>12.49</td><td>2.84</td><td>22.73</td><td>20.95</td><td>4.39</td><td>20.98</td></tr></tbody></table>

<figure><img src="image_14.png" /><figcaption>**Fig. 12.** Impact of WFF on SET pulse width [40].</figcaption></figure>

The normalized standard deviation of the SET pulse width is shown in Fig 13. The smaller this deviation, the more robust to the variability effects is the topology used in each logic function. Although the complex topology presents higher mean values of the SET pulse width, these values deviate less than the values considering the multi-level topology for three logic functions. This difference between the deviations is not very significant, being 2.75% for the XOR gate and approximately 19% for the OAI21 gate. As in the previous analysis, for the AOI211 gate, the behavior is inverse and the multi-level topology ends up having the smallest deviation. Although the complex topology suffers from increasing the SET pulse width due to the impact of the WFF, these values have a smaller deviation than the ones considering the multi-level topology.

In the current analysis, the deviations are normalized by the mean, i.e., a smaller value of the SET pulse width means for the 2000 Monte Carlo simulations performed, tends to a more significant deviation. Still, this analysis allows
<figure><img src="image_15.png" /><figcaption>Fig. 13. Normalized standard deviation of SET pulse width [40].</figcaption></figure>

observing the quantity and how much the values deviate from the mean values presented in the previous analysis. This behavior is reflected in the probability that the WFF will more or less impact the circuit. The multi-level topology has a slightly higher probability of having a SET pulse width value greater than the mean.

After obtaining the SET pulse width mean values and confirming that they are higher than the mean worst-case delay of each logic gate, the fault characterization in the circuit output is complete. Then a new LETth can be calculated considering the WFF impact. Fig. 14 shows the difference between the LETth obtained considering the ideal fabrication process and the impact of the WFF for all the logic functions in the two topologies of the study. For all logic functions regardless of the adopted topology, the LETth considering the WFF impact is smaller than the LETth at ideal fabrication process. That is, due to WFF, a smaller amount of energy transferred by the particle is required to cause a disturbance in the circuit. All evaluated circuits become more sensitive to the radiation effects. Also, in the comparison between the different transistor arrangements used in each logic gate, the multi-level topology presents the best results. For the OAI21 and AOI211 gates, the LETth considering the impact of the WFF is significantly larger in comparison with the complex topology, being 38.4% and 88% respectively. For the OAI22 and XOR gates, the LETth is smaller in the same comparison. However, signalizing a not statistically significant difference, 3.1% and 1.3%, respectively.
<figure><img src="image_16.png" /><figcaption>Fig. 14. Difference of LETth considering ideal fabrication process and WFF impact [40].</figcaption></figure>

## 5.3 Area Impact

It is important to highlight one more important metric when comparing the two topologies used in this study. Table 9 shows the number of transistors and the area of each logic gate in the two topologies. All gates designed with the multi-level logic arrangement show an increase in the area used. In most cases, the area using the multi-level topology is more than three times larger than the complex gate topology. The OAI22 and AOI211 gates have the largest variation, the multi-level layout is about 4.5 times larger than the traditional layout. The XOR gate has the smallest increase in the comparison between the two topologies, approximately 67%.

<table><caption>Table 9. Comparison of number of transistors and area for complex gate and multi-level logic topologies</caption><thead><tr><th rowspan="2">Logic</th><th rowspan="2"># Transistors</th><th colspan="4">Area (µm²)</th></tr><tr><th>Complex Gate</th><th>Multi-level Complex Gate</th><th>Multi-level</th></tr></thead><tbody><tr><td>OAI21</td><td>6</td><td>16</td><td>0.085</td><td>0.271</td></tr><tr><td>OAI22</td><td>8</td><td>28</td><td>0.102</td><td>0.475</td></tr><tr><td>AOI211</td><td>8</td><td>28</td><td>0.102</td><td>0.475</td></tr><tr><td>XOR</td><td>10</td><td>20</td><td>0.203</td><td>0.339</td></tr></tbody></table>
## 6 Conclusion

This work evaluated the radiation robustness through the SET response, considering the process variability effects. A set of logic functions implemented in two different transistor topologies was compared using the 7nm FinFET ASAP7 PDK.

Regarding the ideal fabrication process, the multi-level topology presents the largest SET pulse widths; however, it also shows the highest LETth values for three of the four analyzed logic functions. That is, at least considering the ideal fabrication, the SET pulse width has no direct relation to the LETth value. If the design objective is a more robust circuit to radiation effects, regardless of performance, power and area penalties, the multi-level topology is the best option.

Considering the process variability impact, the complex topology presents a large variation of SET pulse width values, even exceeding the multi-level topology values. Even with this variation, the LETth of the multi-level topology remains larger for two of the four logic functions and practically the same for the other two. This behavior confirms the conclusion of the previous analysis, in which the SET pulse width does not have a direct relation with the LETth value and the multi-level topology is the best option to deal with the SET effects.

The LETth values of each circuit can also be related to the environment where they will operate. On average, the LETth values of this study are around 42 Mev.cm²/mg considering ideal conditions and around 36 Mev.cm²/mg considering the WFF impact. Despite being high values, the logic functions are still susceptible to faults at the ground level. That is, the robustness of the this types of circuits must be considered even for applications that operate in a terrestrial environment.

In addition to the analysis of the behavior of each topology considering ideal fabrication and process variability, the impact of the WFF on the SET response was also evaluated. For all logic functions regardless of the topology used, the LETth value is lower, i.e., the logic gates become more sensitive to the radiation effects when considering the process variability impact. This analysis is of utmost importance because it indicates that to determine the LETth of a circuit, one must also consider other reliability factors such as process variability.

**Acknowledgments.** This research is partially supported by the Brazilian Coordination of Improvement of Higher Level Personnel (CAPES) - Finance Code 001, by CNPq and by FAPERGS.

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