# Simple nine-level inverter with 10 switches and a floating capacitor

Do-Hyeon Kim, Jung-Min Kwon

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Do-Hyeon Kim, Jung-Min Kwon. Simple nine-level inverter with 10 switches and a floating capacitor. The 26th European Conference on Power Electronics and Applications, GDR SEEDS France & EPE Association, Mar 2025, Paris, France. 10.34746/epe2025-0132 . hal-05098859

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# Simple nine-level inverter with 10 switches and a floating capacitor

Do-Hyeon Kim, Jung-Min Kwon

Hanbat National University
Daejeon, South Korea
E-Mail:jmkwon@hanbat.ac.kr

## Acknowledgements

This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government under Grant (RS-2024-00354468).

## Keywords

«Multi-level inverters», «DC-AC converter», «Neutral Point Clamped inverter», «Total harmonic distortion (THD)», «Converter control».

## Abstract

This paper presents a simple nine-level inverter with 10 switches and a floating capacitor. The proposed inverter consists of a five-level active-neutral-point-clamped (ANPC) leg and an unfolding leg. The ANPC leg generates a pulsating AC waveform with five voltage levels. The unfolding leg operates at the grid frequency and unfolds the pulsating AC waveform to convert it into a nine-level waveform. Also, a floating capacitor voltage balancing algorithm is introduced to ensure voltage stability. To show the feasibility and performance of the proposed inverter, 1.5 kW prototype is developed.

## Introduction

Multilevel inverters have become increasingly popular due to their ability to reduce device voltage stress, lower common-mode voltage, and minimize overall losses [1]. Furthermore, in high-voltage and high-power conversion applications, multilevel inverters are widely utilized for their superior voltage/current waveform quality, reduced switching losses, and low total harmonic distortion (THD) [2]. The conventional multilevel inverter topologies include the neutral-point-clamped (NPC), the flying-capacitor (FC), and the cascaded H-bridge (CHB) [3]. However, as the number of voltage levels increases, each topology has several drawbacks. In the NPC topology, the complexity of controlling the DC-

link capacitor voltage increases significantly, and many clamping diodes are required to achieve high output voltage levels. Similarly, FC topology has increased difficulty in balancing the flying capacitor voltages, necessitating many capacitors. In the CHB topology, the demand for isolated DC power sources increases with the number of levels, along with the need for additional isolation transformer windings to reach high output voltage levels [4]-[6].

To overcome drawbacks of these topologies, hybrid-type multilevel inverters have been developed by combining the fundamental topologies [7]-[8]. Among these hybrid topologies, the ANPC topology eliminates the need for clamping diode, uses fewer capacitors, and does not require multiple isolated DC sources. Additionally, it features a simpler structure and requires fewer switches compared to FC and NPC topologies [9].

This paper presents a nine-level inverter based on the five-level ANPC topology. By adding two line-frequency switches to the conventional five-level ANPC inverter, a nine-level output voltage is provided using only ten switches. Floating capacitor voltage balancing is easily accomplished by utilizing redundant switching states based on the voltage levels of the floating capacitors.

<figure><img src="image_2.png" /><figcaption>Fig. 1: Proposed nine-level ANPC inverter with the three-level step-up converter.</figcaption></figure>
<table><caption>Table I: Switching state of nine-level ANPC inverter</caption><thead><tr><th>State</th><th>S<sub>1</sub></th><th>S<sub>2</sub></th><th>S<sub>3</sub></th><th>S<sub>4</sub></th><th>S<sub>5</sub></th><th>Level Voltage</th><th>Floating capacitor state</th></tr></thead><tbody><tr><td>V<sub>4+</sub></td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>V<sub>dc</sub></td><td>No effect</td></tr><tr><td>V<sub>3A+</sub></td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td rowspan="2">3V<sub>dc</sub>/4</td><td>Charging</td></tr><tr><td>V<sub>3B+</sub></td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>Discharging</td></tr><tr><td>V<sub>2A+</sub></td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td rowspan="2">V<sub>dc</sub>/2</td><td>No effect</td></tr><tr><td>V<sub>2B+</sub></td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>No effect</td></tr><tr><td>V<sub>1A+</sub></td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td rowspan="2">V<sub>dc</sub>/4</td><td>Charging</td></tr><tr><td>V<sub>1B+</sub></td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>Discharging</td></tr><tr><td>V<sub>0+</sub></td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td rowspan="2">0</td><td>No effect</td></tr><tr><td>V<sub>0-</sub></td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>No effect</td></tr><tr><td>V<sub>1A-</sub></td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td rowspan="2">- V<sub>dc</sub>/4</td><td>Discharging</td></tr><tr><td>V<sub>1B-</sub></td><td>1</td><td>1</td><td>0</td><td>1</td><td>1</td><td>Charging</td></tr><tr><td>V<sub>2A-</sub></td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td rowspan="2">- V<sub>dc</sub>/2</td><td>No effect</td></tr><tr><td>V<sub>2B-</sub></td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>No effect</td></tr><tr><td>V<sub>3A-</sub></td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td rowspan="2">- 3V<sub>dc</sub>/4</td><td>Discharging</td></tr><tr><td>V<sub>3B-</sub></td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>Charging</td></tr><tr><td>V<sub>4-</sub></td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>- V<sub>dc</sub></td><td>No effect</td></tr></tbody></table>

## Topological Description

Fig. 1 shows the example configuration of the two-stage power conversion system using the proposed nine-level inverter. The three-level step-up converter increases the DC-link voltage and balances the voltages of the two DC-link capacitors. The proposed nine-level inverter consists of two DC-link capacitors, floating capacitors $C_F$, ten IGBT switches, and output inductor $L_o$. Each pair of switches ($S_1, \bar{S}_1$), ($S_2, \bar{S}_2$), ($S_3, \bar{S}_3$), ($S_4, \bar{S}_4$), and ($S_5, \bar{S}_5$) operates complementarily.

The five-level ANPC leg operates at high frequency to provide five voltage levels. The switches $S_1-S_2$ and $\bar{S}_1-\bar{S}_2$ operate simultaneously for 1/4 cycle of the fundamental period, which reduces switching losses. $S_5$ and $\bar{S}_5$ operate alternately over one output voltage period; $\bar{S}_5$ is turned on during the positive half-cycle, and $S_5$ is turned on during the negative half-cycle. As shown in Table I, the proposed nine-level inverter has nine different voltage levels ($V_{dc}, 3V_{dc}/4, V_{dc}/2, V_{dc}/4, 0, -V_{dc}/4, -V_{dc}/2, -3V_{dc}/4, -V_{dc}$) and sixteen switching states ($V_{4+} \sim V_{4-}$). '0' indicates a switch is off, while '1' indicates it is on. Multiple different switching states can realize the same voltage level. For example, the output voltage level $3V_{dc}/4$ can be generated by two different switching states $V_{3A+}$ or $V_{3B+}$ depending on whether the switch $S_3$ or $S_4$ is on.

<table><caption>Table II: Selected switching sequence for floating capacitor voltage balancing</caption><thead><tr><th>Floating capacitor voltage</th><th>Switching sequence</th></tr></thead><tbody><tr><td>V<sub>f</sub> ≤ V<sub>dc</sub>/4</td><td>V<sub>4+</sub> - V<sub>3A+</sub> - V<sub>2A+</sub>/V<sub>2B+</sub> - V<sub>1A+</sub> - V<sub>0+</sub>/V<sub>0-</sub> - V<sub>1B-</sub> - V<sub>2A</sub>/V<sub>2B-</sub> - V<sub>3B-</sub> - V<sub>4-</sub></td></tr><tr><td>V<sub>f</sub> > V<sub>dc</sub>/4</td><td>V<sub>4+</sub> - V<sub>3B+</sub> - V<sub>2A+</sub>/V<sub>2B+</sub> - V<sub>1B+</sub> - V<sub>0+</sub>/V<sub>0-</sub> - V<sub>1A-</sub> - V<sub>2A</sub>/V<sub>2B-</sub> - V<sub>3A-</sub> - V<sub>4-</sub></td></tr></tbody></table>

## Floating Capacitor Voltage Balancing

Floating capacitor voltage balancing control is implemented using the redundant switching state. There are redundant states at each level of input voltage level except $\pm V_{dc}$. These redundant states can either charge or discharge the floating capacitor, depending on which state is selected. By properly choosing these redundant states, the floating-capacitor voltage can be maintained at one-quarter of the DC-link ($=V_{dc}/4$).

During the positive half-cycle of the output voltage, the floating capacitor charges when switch $S_3$ is on and $S_4$ is off, and discharges when the switches are in opposite states. In contrast, during the negative half-cycle, the floating capacitor charges when switch $S_3$ is off and $S_4$ is on, and discharges when their states are in opposite states. Consequently, the switching groups can be effectively controlled by categorizing them into two groups based on the charging and discharging states of the floating capacitor, as shown in Table II.

## Operating Principle and Control

Fig. 2 shows the operation circuit diagram, which includes twelve switching states. Fig. 2(a)-(f) show the switching states for the positive half-cycle, while Fig. 2(g)-(l) show those for the negative half-cycle. Redundant switching states are employed to ensure that only one switching state changes during each level transition. This control strategy minimizes unnecessary switching actions and reduces switching losses during transitions.

The output voltage $v_o$ can be divided into eight sections based on the nine voltage levels, and these sections determine the switching modes:
<figure><img src="image_3.png" /><figcaption>Fig. 2: Operation circuit diagrams of the proposed nine-level inverter;</figcaption></figure>

(a) $v_{ab} = V_{dc}, v_o > 0, i_o > 0$;

(b) $v_{ab} = 3V_{dc}/4, v_o > 0, i_o > 0$;

(c) $v_{ab} = V_{dc}/2, v_o > 0, i_o > 0$;

(d) $v_{ab} = V_{dc}/2, v_o > 0, i_o > 0$;

(e) $v_{ab} = V_{dc}/4, v_o > 0, i_o > 0$;

(f) $v_{ab} = 0, v_o > 0, i_o > 0$;

(g) $v_{ab} = 0, v_o < 0, i_o < 0$;

(h) $v_{ab} = -V_{dc}/4, v_o < 0, i_o < 0$;

(i) $v_{ab} = -V_{dc}/2, v_o < 0, i_o < 0$;

(j) $v_{ab} = -V_{dc}/2, v_o < 0, i_o < 0$; (k) $v_{ab} = -3V_{dc}/4, v_o < 0, i_o < 0$;

(l) $v_{ab} = -V_{dc}, v_o < 0, i_o < 0$.

mode 1, $3V_{dc}/4 \le v_o < V_{dc}$; mode 2, $V_{dc}/2 \le v_o < 3V_{dc}/4$; mode 3, $V_{dc}/4 \le v_o < V_{dc}/2$; mode 4, $0 \le v_o < V_{dc}/4$; mode 5, $-V_{dc}/4 \le v_o < 0$; mode 6, $-V_{dc}/2 \le v_o < -V_{dc}/4$; mode 7, $-3V_{dc}/4 \le v_o < -V_{dc}/2$; mode 8, $-V_{dc} \le v_o < -3V_{dc}/4$.

In mode 1, $S_4$ operates at high frequency; Fig. 2(a) and (b) shows the operation circuit diagram in mode 1. During the on-state and off-state of $S_4$ the inductor voltage $v_L$ is obtained as

$$v_L = V_{dc} - v_o, \quad \text{on-state of } S_4 \qquad (1)$$

$$v_L = 3V_{dc}/4 - v_o, \quad \text{off-state of } S_4 \qquad (2)$$

where $v_L > 0$ at on-state, and $v_L < 0$ at off-state; mode 1 has the operation voltage range $3V_{dc}/4 < v_o < V_{dc}$ as shown in Fig. 3. Because of the principle of the inductor volt-second balance, the nominal duty $D_{n4}$ of $S_4$ can be obtained as

$$D_{n4}(V_{dc} - v_o) + (1 - D_{n4}) \left( \frac{3V_{dc}}{4} - v_o \right) = 0 \qquad (3)$$

$$D_{n4} = \frac{4v_o}{V_{dc}} - 3 \qquad (4)$$

In contrast, $S_1, S_2, S_3$, and $S_5$ have a fixed nominal duty $D_{n1}, D_{n2}, D_{n3}, D_{n5}$ given as follows, individually:
$$D_{n1} = D_{n2} = D_{n3} = \frac{t_{on}}{T_s} = \frac{T_s}{T_s} = 1 \qquad (5)$$

$$D_{n5} = \frac{t_{on}}{T_s} = \frac{0}{T_s} = 0 \qquad (6)$$

where $t_{on}$ is on-time during the switching period, and $T_s$ is the switching period. Thus, the five duty ratios in all modes can be obtained as follows:

$$D_{n1} = D_{n2} = D_{n3} = 1, \\ D_{n4} = \frac{4v_o}{V_{dc}} - 3, D_{n5} = 0 \qquad \text{for mode 1} \qquad (7)$$

$$D_{n1} = D_{n2} = 1, D_{n3} = \frac{4v_o}{V_{dc}} - 2, \qquad \text{for mode 2} \qquad (8)$$

$$D_{n4} = D_{n5} = 0 \\ D_{n1} = D_{n2} = 0, D_{n3} = 1, \\ D_{n4} = \frac{4v_o}{V_{dc}} - 1, D_{n5} = 0 \qquad \text{for mode 3} \qquad (9)$$

$$D_{n1} = D_{n2} = 0, D_{n3} = \frac{4v_o}{V_{dc}}, \qquad \text{for mode 4} \qquad (10)$$

$$D_{n4} = D_{n5} = 0 \\ D_{n1} = D_{n2} = 1, D_{n3} = \frac{4v_o}{V_{dc}} + 1, \qquad \text{for mode 5} \qquad (11)$$

$$D_{n4} = D_{n5} = 1 \\ D_{n1} = D_{n2} = 1, D_{n3} = 0, \\ D_{n4} = \frac{4v_o}{V_{dc}} + 2, D_{n5} = 1 \qquad \text{for mode 6} \qquad (12)$$

$$D_{n1} = D_{n2} = 0, D_{n3} = \frac{4v_o}{V_{dc}} + 3, \qquad \text{for mode 7} \qquad (13)$$

$$D_{n4} = D_{n5} = 1 \\ D_{n1} = D_{n2} = D_{n3} = 0, \\ D_{n4} = \frac{4v_o}{V_{dc}} + 4, D_{n5} = 1 \qquad \text{for mode 8} \qquad (14)$$

## Experimental Results

To verify the operation and control of the proposed nine-level topology, 1.5 kW prototype was developed as shown in Fig. 4. The overall control diagram is implemented fully in software using Texas Instrument TMS320F28388D. Voltage and current signals are measured by the 12-bit analog-to-digital converter in the microprocessor. The Implementation of the

<figure><img src="image_4.png" /><figcaption>Fig. 3: Nine-level voltage $v_{ab}$ and output voltage $v_o$ waveform.</figcaption></figure>

<figure><img src="image_5.png" /><figcaption>Fig. 4: Experimental platform of the proposed nine-level inverter.</figcaption></figure>

<table><caption>Table III: Parameters of the prototype circuit</caption><thead><tr><th>Parameters</th><th>Symbols</th><th>Value</th></tr></thead><tbody><tr><td>Rated Power</td><td>P<sub>o</sub></td><td>1.5 kW</td></tr><tr><td>DC-link voltage</td><td>V<sub>dc</sub></td><td>350 V</td></tr><tr><td>Output voltage</td><td>v<sub>o</sub></td><td>220 V</td></tr><tr><td>Output frequency</td><td>f<sub>o</sub></td><td>60 Hz</td></tr><tr><td>Switching frequency</td><td>f<sub>s</sub></td><td>10 kHz</td></tr><tr><td>DC-link capacitance</td><td>C<sub>T</sub>, C<sub>B</sub></td><td>680 μF</td></tr><tr><td>FC capacitance</td><td>C<sub>F</sub></td><td>470 μF</td></tr><tr><td>Output inductance</td><td>L<sub>o</sub></td><td>2 mH</td></tr></tbody></table>

controllers is performed every sample period of 50 µs. The major components and parameters of the prototype are presented in Table III.

Fig. 5 shows the nine-level voltage $v_{ab}$, output voltage $v_o$, and output current $i_o$. In accordance with the theoretical analysis, $v_{ab}$ shows nine distinct voltage levels. The output voltage $v_o$ and current $i_o$ maintain sinusoidal forms and show the rated output power. Fig. 6 shows that the floating capacitor voltage $V_f$ reaches at the quarter of the DC-link. Fig. 7 shows the floating capacitor
<figure><img src="image_6.png" /><figcaption>Fig. 5: The nine-level voltage $v_{ab}$, output voltage $v_o$, and output current $i_o$.</figcaption></figure>

<figure><img src="image_7.png" /><figcaption>Fig. 6: The floating capacitor voltage after operation starting point.</figcaption></figure>

<figure><img src="image_8.png" /><figcaption>Fig. 7: The floating capacitor voltage and output current waveforms when the load changes abruptly from 750 W to 1.5 kW.</figcaption></figure>

voltage and output currents waveforms when the load changes from 750 W to 1.5 kW. The floating capacitor voltage $V_f$ was maintained at 87.5 V ($=V_{do}/4$), with instantaneous voltage fluctuations not exceeding 10%.

## Conclusion

This paper presented the simple nine-level inverter based on five-level ANPC topology. The output voltage levels were increased from five to nine by incorporating two line-frequency switches. The switch on-state times are derived and can be effectively applied to achieve stable floating capacitor voltages. Experimental results confirm the validity, effectiveness, and feasibility of the proposed inverter and its control algorithm.

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