# Electrical devices from top-down structured platinum diselenide films

Chanyoung Yim, Vikram Passi, Max C. Lemme, Georg S. Duesberg, Cormac Ó Coileáin, Emiliano Pallecchi, Dalal Fadil, Niall Mcevoy

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Chanyoung Yim, Vikram Passi, Max C. Lemme, Georg S. Duesberg, Cormac Ó Coileáin, et al. Electrical devices from top-down structured platinum diselenide films. npj 2D Materials and Applications, 2018, 2 (1), pp.5. 10.1038/s41699-018-0051-9. hal-03185616

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# Electrical devices from top-down structured platinum diselenide films

Chanyoung Yim<sup>1,2</sup>, Vikram Passi<sup>1,3</sup>, Max C. Lemme<sup>1,3</sup>, Georg S. Duesberg<sup>2,4,5</sup>, Cormac Ó Coileáin<sup>4</sup>, Emiliano Pallecchi<sup>6</sup>, Dalal Fadil<sup>6</sup> and Niall McEvoy<sup>4,5</sup>

Platinum diselenide (PtSe<sub>2</sub>) is an exciting new member of the two-dimensional (2D) transition metal dichalcogenide (TMD) family. It has a semimetal to semiconductor transition when approaching monolayer thickness and has already shown significant potential for use in device applications. Notably, PtSe<sub>2</sub> can be grown at low temperature making it potentially suitable for industrial usage. Here, we address thickness-dependent transport properties and investigate electrical contacts to PtSe<sub>2</sub>, a crucial and universal element of TMD-based electronic devices. PtSe<sub>2</sub> films have been synthesized at various thicknesses and structured to allow contact engineering and the accurate extraction of electrical properties. Contact resistivity and sheet resistance extracted from transmission line method (TLM) measurements are compared for different contact metals and different PtSe<sub>2</sub> film thicknesses. Furthermore, the transition from semimetal to semiconductor in PtSe<sub>2</sub> has been indirectly verified by electrical characterization in field-effect devices. Finally, the influence of edge contacts at the metal–PtSe<sub>2</sub> interface has been studied by nanostructuring the contact area using electron beam lithography. By increasing the edge contact length, the contact resistivity was improved by up to 70% compared to devices with conventional top contacts. The results presented here represent crucial steps toward realizing high-performance nanoelectronic devices based on group-10 TMDs.

npj 2D Materials and Applications (2018)2:5; doi:10.1038/s41699-018-0051-9

## INTRODUCTION

Over the last decade, the need for further miniaturization and increased functionality of electronic devices has triggered massive research in two-dimensional (2D) channel materials such as graphene and transition metal dichalcogenides (TMDs).<sup>1–3</sup> Reliable electrical contacts between devices/materials and metal electrodes are crucial, as the contact resistance can strongly influence or dominate the behavior of the entire device. Depending on the contact status at the metal–channel junction, Ohmic or Schottky, the flow of charge carriers across the device can be decisively deteriorated.<sup>4</sup> Thus, the reliable formation of contacts to each new channel material proves challenging and has to be investigated in detail.

Graphene has been considered one of the most promising candidates for future nanoelectronics due to its unique electrical properties.<sup>5</sup> Contact resistivity in graphene devices has been widely studied and a wide range of contact resistances (~10<sup>2</sup> to ~10<sup>3</sup> Ω µm) has been reported, depending on the contact metal, surface states, and contact geometry.<sup>6–9</sup> Following the impressive advances in graphene, various layered 2D TMDs have been tested in a wide range of device applications, including field-effect transistors (FETs),<sup>10,11</sup> photodetectors,<sup>12–14</sup> and sensors.<sup>15,16</sup> Up to now, molybdenum and/or tungsten-based materials have been the main focus of 2D TMD research, and the majority of studies on electrical contacts to 2D TMDs have concentrated on these materials.<sup>17–19</sup> However, compared to classical silicon-based

devices, these TMDs still show relatively inferior performance and less environmental stability in device applications.<sup>20–23</sup> Moreover, the high growth temperature (>600 °C) associated with TMD synthesis by chemical vapor deposition (CVD), which is typically used for large-scale TMD film synthesis,<sup>24–26</sup> can limit their compatibility with current semiconductor processing.

On the other hand, there are other relatively unexplored members of the TMD family such as group-10 TMDs. Recently, the electronic structure and properties of these materials have been theoretically evaluated and, as a consequence of their promising characteristics, they have been proposed for use in electronic device applications.<sup>27,28</sup> Platinum diselenide (PtSe<sub>2</sub>) is one such group-10 TMD which is known to be a semimetal in bulk form with zero bandgap.<sup>29</sup> Theoretical calculations suggested a transition from semimetal to semiconductor with reduced PtSe<sub>2</sub> thickness<sup>27,30</sup> and it was shown experimentally by Wang et al. that monolayer PtSe<sub>2</sub> has a bandgap of ~1.2 eV.<sup>31</sup> In addition, we recently reported that layered PtSe<sub>2</sub> can be synthesized in a scalable manner at low temperature (400 °C) by thermally assisted conversion (TAC) of pre-deposited Pt layers and utilized as the active material in optoelectronic and gas-sensor devices.<sup>32,33</sup> Such low-temperature synthesis may potentially have a high impact on practical device applications since it allows integration of PtSe<sub>2</sub> with standard semiconductor back-end-of-line processing.<sup>34–36</sup> In this regard, it is critical to evaluate electrical properties and contacts to PtSe<sub>2</sub> in electronic devices.

Received: 28 November 2017 Revised: 31 January 2018 Accepted: 2 February 2018

Published online: 28 February 2018

<footnote n="1"><sup>1</sup>Department of Electrical Engineering and Computer Science, University of Siegen, Hölderlinstraße 3, 57076 Siegen, Germany; <sup>2</sup>Institute of Physics, EIT 2, Faculty of Electrical Engineering and Information Technology, Universität der Bundeswehr München, Werner-Heisenberg-Weg 39, 85577 Neubiberg, Germany; <sup>3</sup>Faculty of Electrical Engineering and Information Technology, RWTH Aachen University, Otto-Blumenthal-Str. 25, 52074 Aachen, Germany; <sup>4</sup>Centre for the Research on Adaptive Nanostructures and Nanodevices (CRANN) and Advanced Materials and BioEngineering Research (AMBER), Trinity College Dublin, Dublin 2, Ireland; <sup>5</sup>School of Chemistry, Trinity College Dublin, Dublin 2, Ireland and <sup>6</sup>Institut d'Electronique, de Microélectronique et de Nanotechnologie (IEMN), 59652 Villeneuve d'Ascq, France

Correspondence: Niall McEvoy (nmcevoy@tcd.ie)</footnote>
<figure><img src="image_2.png" /><figcaption>Fig. 1 Device fabrication and characterization. a Schematic diagram of the PtSe₂ channel synthesis process using a TAC method. b Raman spectra of PtSe₂ films of different Pt deposition thickness normalized to the E_g mode intensity. Initial Pt deposition thicknesses are 0.5, 2, and 5 nm. c SEM image of the fabricated PtSe₂ channel device with a TLM structure (left, scale bar 50 µm) and its enlarged image (right, scale bar 5 µm). The contact spacing increases from 1 to 9 µm with a step of 1 µm</figcaption></figure>

Here, PtSe₂ channels with controlled dimensions and thick-
nesses were grown using a TAC method. Electron beam
lithography (EBL) was used to fabricate transmission line method
(TLM) structures to extract contact resistivity and sheet resistance
of the PtSe₂ devices. In addition, electrical characterization of
PtSe₂ FETs was conducted to study the charge-transport
characteristics of the PtSe₂ devices. Finally, we investigated the
effect of “edge” or side contacts on the contact resistivity using
well-defined hole patterns in the contact region of the PtSe₂
channel.

RESULTS AND DISCUSSION

PtSe₂ device channels were synthesized by direct selenization of
pre-deposited Pt layers with different thicknesses. As reported in
our previous studies,³²,³³ the PtSe₂ synthesized by a TAC process
has a polycrystalline structure, which is also observed in scanning
electron microscopy (SEM) images (Fig. S1 of the Supplementary
Information) of the PtSe₂ film surface. According to atomic-force
microscopy (AFM) measurements of the thicknesses of Pt layers
before and after selenization, it has been found that the initial Pt
thickness expands approximately four times after selenization.
Details of the AFM characterization are presented in Figs. S2 and
S3 of the Supplementary Information. Previous studies on TAC
growth of TMDs have shown that the orientation of the resultant
films depends on the starting metal thickness with thicker metal
films leading to horizontal growth, perpendicular to the growth
substrate.³⁷ A recent study on the electrocatalytic properties of
PtSe₂ indicated that this holds true for TAC growth of PtSe₂, with
significant contributions from perpendicular growth seen for PtSe₂
thicknesses >20 nm.³⁸ This is consistent with our observations, our
PtSe₂ films looked “cloudy” if thick (>5 nm) Pt films were used and
so for the purpose of this study only Pt films with thickness of
5 nm or less were used. In this thickness regime we expect the

growth to be mostly vertical, or parallel to the growth substrate. A
schematic diagram of the film growth process is presented in
Fig. 1a. First, the channel area was defined on the substrates by
EBL. After Pt deposition and lift-off, the Pt samples were selenized
via a TAC method. Raman spectra of the PtSe₂ layers grown from
various Pt thicknesses (0.5, 2, and 5 nm) are shown in Fig. 1b. Two
prominent peaks at ~177 cm⁻¹ and ~210 cm⁻¹ can be seen in the
spectra. They represent the typical Raman fingerprint of layered
PtSe₂ with a 1T type crystal structure and are related to the E_g
(~177 cm⁻¹) and A₁g (~210 cm⁻¹) Raman active modes, respec-
tively.³² The E_g mode indicates an in-plane vibrational mode of Se
atoms and the A₁g mode is an out-of-plane vibration of Se atoms.
As the films get thicker, a slight red shift of the E_g mode is
observed, alongside an increase in the relative intensity of the A₁g
mode, consistent with previous reports.³²,³³ Such an increase in
the relative intensity of the A₁g mode implies a greater out-of-
plane contribution, which may be due to enhanced van der Waals
interactions in the thicker films. Additionally, we investigated the
sulfurization of Pt films using a S source in place of Se.
Interestingly, our preliminary studies suggest the formation of
PtS rather than PtS₂ as detailed in Fig. S4 of the Supplementary
Information.

TLM measurements were used at room temperature to
determine the contact resistance of the PtSe₂ devices in this
work.³⁹ TLM structures were patterned on the substrates with
predefined PtSe₂ channels by EBL. The contact spacing was varied
from 1 to 9 µm in 1 µm steps. SEM images of a TLM structure on a
PtSe₂ channel are shown in Fig. 1c. Two representative metals
with low and high work functions, Ti and Ni, were chosen and
used to contact the PtSe₂ channels, both of which were selenized
from 5 nm thick initial Pt layers. The contact resistances of these
were compared through dc current-voltage (I-V) measurements
of the TLM structures. Figure 2a and b shows I-V data measured
from Ti and Ni-contacted PtSe₂ TLM structures with a channel
<figure><img src="image_3.png" /><figcaption>**Fig. 2** Electrical characterization of PtSe₂ TLM devices. I–V plots of the TLM structure with various PtSe₂ channel length values (L) for a Ti/Au and b Ni/Au-contacted devices, and the associated plots of the total resistance (R<sub>T</sub>) vs. PtSe₂ channel length for the c Ti/Au and d Ni/Au-contacted devices. The initial Pt deposition thickness and the channel width of the devices are 5 and 3 µm, respectively. e Contact resistivity and f sheet resistance values extracted from the TLM measurements for the Ti/Au and Ni/Au-contacted devices with different PtSe₂ channel width values</figcaption></figure>

width of 3 µm, respectively. The linear I–V curves indicate that both Ti and Ni electrodes form good ohmic contacts with PtSe₂ channels. Values of the contact resistance for each metal and the sheet resistance of the PtSe₂ channel can be extracted by extrapolation from linear fits of the plots of the total resistance (R<sub>T</sub>) vs. the contact spacing (Fig. 2c, d), wherein the y-intercept and the slope of the fits provide information on the contact resistance and sheet resistance. Figure 2e shows contact resistivity values of each metal for different PtSe₂ channel widths, where the contact resistance values were normalized to channel width for direct comparison. It was found that the Ti-contacted device had a contact resistivity more than one order of magnitude higher than the Ni-contacted device. Considering the work function values of the contact metals (Ti: 4.3 eV, Ni: 5.2 eV), we observe that the metal with a higher work function has a lower contact resistance with PtSe₂. The sheet resistance values of the PtSe₂ channels in Fig. 2f are quite similar to each other (500–600 Ω/□) for both contact metals, which can be expected from the identical PtSe₂ channel thicknesses for both devices.

Ni-contacted TLM structures were then fabricated on PtSe₂ channels with different thicknesses, which were selenized from 0.5, 2, and 5 nm thick initial Pt layers. The Ni–PtSe₂ contact resistivity and sheet resistance were extracted by analyzing the TLM measurement data, R<sub>T</sub> vs. contact spacing, in Fig. 3a and b. The extracted values of the contact resistivity and sheet resistance are plotted against the film thickness in Fig. 3c and d. When the same Ni electrodes were deposited on the PtSe₂ channels with various thicknesses, devices with thinner PtSe₂ channels show much higher contact resistivity and larger sheet resistance. This can be attributed to the nature of layered PtSe₂, whereby the electronic character changes from semimetallic to semiconducting as the number of layers decreases.<sup>27,30,31</sup> The thinner PtSe₂ can be expected to be more semiconducting than the thicker, resulting in higher contact resistivity with metal electrodes as well as larger sheet resistance. The semiconducting characteristics of the thinner PtSe₂ are also supported by the results of electrical measurements at low temperatures. The I–V plots of a PtSe₂ film, derived from a 0.5 nm thick Pt layer and measured in a temperature range of 78–340 Kelvin (K), reveal clear temperature dependence. As the
<figure><img src="image_4.png" /><figcaption>**Fig. 3** Investigation of the effect of PtSe₂ thickness on device performance. Plots of the total resistance ($R_T$) vs. PtSe₂ channel length for the Ni-contacted TLM structures with different PtSe₂ thicknesses, synthesized from the **a** 2 nm and **b** 0.5 nm thick Pt layers with 1 µm of channel width. Summary of **c** contact resistivity and **d** sheet resistance values extracted using TLM method for the different PtSe₂ thicknesses</figcaption></figure>

temperature is reduced there is a consistent rise in resistance, indicating the semiconducting nature of the PtSe₂. Details of the temperature-dependence measurements are presented in Fig. S5 of the Supplementary Information.

Charge-transport measurements of PtSe₂ FETs were carried out at room temperature in ambient conditions to further investigate the electrical properties of PtSe₂ films with different thicknesses. PtSe₂ channels with a length of 5 µm and a width of 1 µm were probed via two separate metal source and drain electrodes, with gate biases applied to the silicon substrate in a back-gate configuration. The output characteristics of the FETs with PtSe₂ channels synthesized from 5, 2, and 0.5 nm thick initial Pt layers are plotted in Fig. 4a–c, respectively. For all devices, the drain–source current ($I_{ds}$) increases linearly with the applied dc drain–source voltage ($V_{ds}$), implying good ohmic contact of the Ni electrodes with the PtSe₂ channels. As expected, the device with a thicker PtSe₂ layer shows higher conductivity. The gating characteristics of the FETs were examined under a dc back-gate bias ($V_{gs}$) in the range of –80 to +80 volts (V). While the FETs with PtSe₂ channels synthesized from the 5 and 2 nm thick Pt layers show hardly any gate dependence, the PtSe₂ FET from the 0.5 nm thick initial Pt layer shows a clear gate dependence with p-type conduction. This is consistent with the previous results that contact formation with a high work function metal reduces the contact resistance at the metal-PtSe₂ junction. Also, this data supports the hypothesis that PtSe₂ becomes more semiconducting as it gets thinner. The field-effect mobility ($\mu$) was extracted from the transfer characteristics of the PtSe₂ FETs selenized from the 0.5 nm thick Pt layer in Fig. 4d, using the expression $\mu = [L/(W \times C_{ox} \times V_{ds})] \times [\partial I_{ds}/\partial V_{gs}]$, where L is the channel length, W is the channel width, $C_{ox}$ is the capacitance of the insulating layer between the gate and the channel. The mobility was estimated to be a maximum of 0.6 cm² V⁻¹ s⁻¹, which is lower than previously reported values (7–210 cm² V⁻¹ s⁻¹) obtained from high-temperature CVD-grown single crystalline, or mechanically

exfoliated PtSe₂.⁴⁰,⁴¹ However, considering the benefits of our growth process, namely, the low synthesis temperature, scalability and ease of controlling layer thickness, this is quite striking. Such a relatively low mobility likely originates from the polycrystalline structure, with randomly distributed PtSe₂ grains, observed for TAC-grown PtSe₂.³²,³³ This polycrystallinity, and associated thickness variation over large areas, is also the most likely cause of the relatively poor gate control seen in our gate-response curves. Additional efforts to optimize the synthesis process, through the use of epitaxially deposited Pt or highly crystalline substrates, and the realization of local top-gates with high-k dielectrics, are expected to improve the mobility. Furthermore, better control over the Pt deposition conditions, and the use of post-growth treatments such as annealing, can be expected to improve the film uniformity leading to better gate control. In order to assess the stability of PtSe₂ channels, we repeated I–V measurements on the same device (PtSe₂ channel with a length of 5 µm and a width of 1 µm) in ambient conditions with an interval of 20 days and monitored the variation of $R_T$ of the device for 40 days. As presented in Fig. S6 of the Supplementary Information, the measured $R_T$ was 8.1 MΩ from the first measurements, 8.3 MΩ from the second measurements after 20 days, and 9.4 MΩ from the last measurements after 40 days. This indicates that the PtSe₂ channel is quite stable with a resistance increase of 15% of the initial value after 40 days without any passivation or post-treatment.

Lastly, we investigated the effect of "edge contacts" on the contact resistance of PtSe₂ TLM structures. There have been continuous efforts to achieve low contact resistance in 2D-material-based devices, including local plasma or ultraviolet/ozone treatment of the contact area⁴²,⁴³ and molecular doping of the channel materials.⁴⁴ However, these methods require additional processes and can cause damage to the channel materials. Forming an "end-contacted" interface between metal and graphene was proposed as another way to reduce contact
<figure><img src="image_5.png" /><figcaption>**Fig. 4** Gate-dependent electrical measurements of PtSe₂ devices. Output characteristics (I<sub>ds</sub> vs. V<sub>ds</sub>) of PtSe₂ FET devices with PtSe₂ channels selenized from a 5 nm, b 2 nm, and c 0.5 nm thick Pt layers under various back-side gate biases (V<sub>gs</sub>) from -80 to 80 V. d Transfer characteristics (I<sub>ds</sub> vs. V<sub>gs</sub> at V<sub>ds</sub> = 1 V) of the PtSe₂ FET device with a PtSe₂ channel selenized from a 0.5 nm thick Pt layer</figcaption></figure>

resistance,⁴⁵ wherein the end-contacted structure at the graphene-metal contacts facilitates chemical bonding between the graphene and the contact metal, enhancing the carrier injection at the contact area. Such an approach has previously been experimentally adopted for graphene-based devices, resulting in a significant improvement in the contact resistance.⁴⁶⁻⁴⁸ Based on this principle, we expect that the edge-contacted structure shown here improves the carrier injection at the metal–PtSe₂ interface. Arrays of holes with a hole size of 200 × 200 nm were included on the contact area of the Pt channel design for EBL, generating channel patterns with empty holes on the contact areas by EBL, as presented in Fig. 5a and b. As the PtSe₂ is aligned parallel to the growth substrate these holes leave many edges exposed. The contact metal fills in these holes leading to the formation of edge contacts between the PtSe₂ channel and metal electrodes and increasing the total area of exposed channel edges at the contact region in the TLM structures. The PtSe₂ channels of all the devices were selenized from 0.5 nm thick Pt layers with a width of 2 µm, and three different types of hole array patterns (side 1-line, side 2-line, and center 2-line) were fabricated with Ni electrodes. The contact resistivity of the normal PtSe₂ TLM device without holes and the device with holes at the contact region were extracted and are compared in Fig. 5c. While there is no clear dependence of the contact resistivity on the number and location of hole arrays at the contact region, distributed between 2 × 10⁵ and 6 × 10⁵ Ω µm, all the devices with the hole patterns at the contact region exhibit 50–70% lower contact resistivity than the conventional device. In contrast, no significant difference in the sheet resistance was observed for all the PtSe₂ channel devices in Fig. 5d, indicating that the quality of the PtSe₂ channels is nearly constant for all devices.

In summary, we have investigated the electrical contact properties of PtSe₂ channels by the TLM method. Initial Pt layers with thicknesses of 0.5, 2, and 5 nm were selenized at low temperature using a TAC method, realizing robust PtSe₂ layers with different thicknesses. When comparing the contact resistivity values of the PtSe₂ TLM devices with two different contact metals,

Ti and Ni, it was found that Ni forms a better electrical contact to the PtSe₂ channel. We also observed that the thinner PtSe₂ films have a higher contact resistivity and larger sheet resistance from the TLM measurements, implying that thinner PtSe₂ films become more semiconducting. In addition, the charge transport characteristics of PtSe₂ FETs were investigated. Only the device derived from the thinnest PtSe₂ layer (0.5 nm) showed a clear gate dependence with p-type conduction, which confirms the transition of PtSe₂ from semimetal to semiconductor with decreasing thickness. Furthermore, the effect of edge-contacted structures on the contact resistance was examined. Arrays of holes were patterned in PtSe₂ to increase the “edge-contacted” area of the layered PtSe₂ film at the metal interface. We found that the edge-contacted structures reduce the contact resistivity, which we attribute to enhancement of the carrier injection at the contacts. Though more comprehensive studies should be carried out in the future to fully understand the fundamentals of the electrical contact properties, our findings provide a quick insight into the realization of high-performance nanoelectronic devices based on layered PtSe₂.

## METHODS

P-type silicon wafers (boron, 3 × 10¹⁵ cm⁻³, <100>) with a thermally grown silicon dioxide (SiO₂, thickness: 290 nm) layer were prepared as substrates for the devices. An EBL system (Raith EBPG-5000Plus) was used to pattern the PtSe₂ channels and contacts. Initial Pt layers with different thicknesses were sputtered onto the substrates using a Gatan coating system (Gatan 682 PECS) with a deposition rate of <0.1 nm per second, followed by a lift-off process.

A TAC process was used to synthesize layered PtSe₂ thin films, as described in our previous work.³²,³³ The sputtered Pt samples and the Se source (Sigma-Aldrich) were placed in two separate, independently controlled heating zones of a quartz tube furnace. The primary heating zone where the Pt samples were located was heated to 400 °C and the second heating zone for the Se source was heated to the melting point of Se (~220 °C) under Ar/H₂ (9:1) gas flow, leading to the formation of layered PtSe₂ thin films. Different metal electrodes of titanium/gold (Ti/Au,
<figure><img src="image_6.png" /><figcaption>**Fig. 5** Edge contacting of PtSe₂ TLM structures. **a** Schematic diagram of the metal (Ni)-PtSe₂ contact area with/without holes on the PtSe₂ channel. **b** SEM image of the PtSe₂ channel with 2-line holes at the side of the metal contact area before metal electrode deposition (scale bar, 1 µm). Extracted **c** contact resistivity and **d** sheet resistance values from the PtSe₂ TLM structures (0.5 nm of starting Pt thickness, 2 µm of channel width) with and without holes on the PtSe₂ channel at the metal-PtSe₂ contact area</figcaption></figure>

20/150 nm) and nickel/gold (Ni/Au, 20/150 nm) were deposited to form TLM structures using an electron beam evaporation system (Plassys) without doing any additional process before evaporation, followed by a lift-off process.

Edge-contacted structures between the channel and metal electrodes were realized by including arrays of holes (a hole size of 200 × 200 nm) in the contact area of the channel design for EBL. The channel patterns, with hole arrays on the contact area, were generated by EBL, resulting in a contact area with empty holes on the channel after Pt deposition. These holes remain in the channel area post selenization. The metal electrodes were patterned by EBL after the selenization of the Pt. The contact metal was evaporated on to the contact region of the PtSe₂ channel with holes, without doing any additional processing at the contact area before evaporation. Further information on the formation of the edge contacts is given in Fig. S7 of the Supplementary Information.

Raman spectra were recorded with a Witec Alpha 300R confocal Raman microscope, using an excitation wavelength of 532 nm and a spectral grating with 1800 lines/mm. SEM images were taken using a JEOL SEM (JSM-IT300) at a high-vacuum mode with an accelerating voltage of 2 kV. Electrical measurements were performed at room temperature under ambient conditions using a Karl Süss probe station connected to a Keithley semiconductor analyzer (SCS4200).

### Data availability

The data sets generated during and/or analyzed during the current study are available from the corresponding author on reasonable request.

### ACKNOWLEDGEMENTS

Support from an ERC grant (InteGraDe, 307311), the German Research Foundation (DFG, LE 2440/2-1), European Regional Funds (HEA2D), the French RENATECH network and Science Foundation Ireland (15/SIRG/3329; 15/IA/3131; 12/RC/2278) is gratefully acknowledged. V.P. would like to acknowledge Prof. Henri Happy for providing access to the cleanroom facilities and fruitful discussions.

### AUTHOR CONTRIBUTIONS

C.Y. wrote the paper and designed the experiments. C.Y., V.P., E.P., and D.F. made devices. C.Y. and C.O.C. measured AFM measurements.

N.M. grew films and performed spectroscopy. M.C.L. and G.S.D. supervised the research. All authors contributed to the discussion of the results and improvement of the manuscript.

### ADDITIONAL INFORMATION

Supplementary Information accompanies the paper on the npj 2D Materials and Applications website (https://doi.org/10.1038/s41699-018-0051-9).

**Competing interests:** The authors declare no competing financial interests.

**Publisher's note:** Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

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