# Design and Implementation of A Configurable Transmitter Baseband in CMOS 28nm FDSOI

The configurable semi-digital FIR DAC part of the proposed transmitter baseband architecture was fabricated using STMicroelectronics CMOS 28nm FDSOI. In the previous chapter, the discussion was mainly system level validation using MATLAB® based simulation results. In this chapter, transistor level discussions of the circuits used for implementing the explained system, and some layout related issues are explored.

It starts from a brief introduction of the specification drawn in the previous chapter for the configurable FIR DAC. While the implementation is based on the direct form FIR filter structure discussed, there are some challenges in placement of UCCs. The placement method followed in the implementation of the FIR DAC chip is explained by comparing it to those in traditional multi-bit DACs. Part of this discussion is also part of a published work in [GFK16b]. The next section explores circuit blocks of the implemented chip. A brief discussion of circuit operation, design, and layout related issues is included.

## 6.1 From System Level to Floorplan

The FIR DAC works in two modes. The 802.11ac mode, which from now on refers to the 160 MHz channel bandwidth, and the LPSC 802.11ad. The impulse responses of these two modes are presented in Chapter 5. The 802.11ac mode has 63 coefficients with 8-bit quantization, and the 802.11ad mode has 17 coefficients with 6-bit quantization. The direct-form FIR filter structure discussed in Chapter 4 is used to implement both impulse responses. In this section, the changes to the normal FIR structure when it is operating in the two standards is explained. The explanation is based on Figure 6.1.

There are 63 delay cells as is expected in the 802.11ac mode. The output of these delay cells are taken to drive the UCCs. The total number of UCCs are placed as one current source and an indication
<figure><img src="image_66.png" /><figcaption>Figure 6.1: FIR DAC block diagram</figcaption></figure>

of their values is placed using their coefficient number ($C_{1}toC_{63}$). In the 802.11ac mode, coefficients $C_{64}toC_{76}$ does not contribute to the output.

In the 802.11ad mode, the mode selection signal, *SEL*, switches the input of the drivers to the second input, in blue in Figure 6.1. All of these inputs are taken from the outputs of the first 17 delay cells. This is consistent with the length of the 802.11ad impulse response. Some of the 17 outputs of the first 17 delay cells are inputs to more than one driver. In other words, that particular tap is driving the sum of the 802.11ac coefficients which correspond to all the drivers connected to that tap. The *RoutingMatrix* is discussed later in the next section. Coefficients $C_{64}toC_{76}$ are small valued coefficients which are added to the summed coefficients of the 17 taps to arrive at the exact coefficient values of the 802.11ad.

## 6.2 Mismatch Errors and Layout Floorplan

FIR DAC performance is highly dependent on the accuracy of its coefficients. Coefficient accuracy is in turn dependent on the absolute and relative accuracy of the method used to implement the coefficient. For example, the FIR DAC is realized using a current-steering DAC structure where current sources are used for implementing the coefficients. Accuracy, in this case, depends on the random errors that are independently defined by the characteristics of the current source implementing a particular coefficient; and the systematic errors across the array of current sources which contribute a relativistic inaccuracy to that particular coefficient.

MOS transistor mismatch errors are classified as random errors and systematic errors. Random errors are uncorrelated errors that are specific to a particular device. They are defined by technological constants, the area a device occupies and the biasing conditions [Pel+89]. The systematic errors are a combination of first order linear errors and higher order errors. The linear errors are caused mainly by
IR drop along a ground line, oxide thickness gradients, doping gradients; and the main contributors to the higher order errors are thermal gradients, oxide stress, etc [CG00]. It can be understood that the systematic errors are there because of the distance between two or more devices. There is a short enough distance at which the systematic errors are insignificant; or their values are less than the random errors and can be neglected. One design strategy is, then, to make the systematic errors smaller than the random errors regardless of distance.

The random errors can be tackled by sizing the area of the current sources according to the standard deviation required. The bigger a MOS transistor is the lower its random mismatch errors. However, this contributes to the systematic mismatch errors by making the chip large. Some of the systematic errors such as the IR drop along the ground line can be minimized by using power and ground distribution grid for the chip and wide ground lines. However, for large number of devices this results in a significant increase in the total area of the chip. A more effective solution is to place the devices in an array and target the mismatch errors with a systematic placement or switching scheme that results in the cancellation of gradients effects and minimization of higher order errors. This is the solution used in many high resolution current-steering DAC implementation [BSS04]. Unfortunately, this solution is not effective for a current-steering FIR DAC with long filter lengths.

### 6.2.1 Pseudo-Double Centroid Placement Method

Unit current cell layout in many high resolution DACs is divided into two or, maybe three, transistor array blocks. The switching parts are placed in one array and the current source transistors in a different array [BSS04]. Some of the reasons are the following: to minimize the current source array area, to separate the switching and the current source devices, reduce wiring capacitance between switch and cascode transistors [PS10].

One reason that makes the adoption of the aforementioned method possible is the symmetrical power of two weights present in a conventional multi-bit DAC. Since weights are implemented by scaling the width of the current source transistor, total current is divided evenly into each current source transistor. The errors that occur due to distance can be dealt with effectively if the current source elements are placed in one array. If some of the weights were not power of two, each current source transistor element would carry different current. Error reduction mechanisms such as switching schemes would not be effective. If the non-power-of-two weights are few, they can be implemented as lumped elements. Dummy elements can be used to compensate for any spatial asymmetry that results. However, if all the weights are random, non-power-of-two, dummy elements are the solution.

Another enabling reason for the adoption of that method is because of the relatively reduced number
Chapter 6. Design and Implementation of A Configurable Transmitter Baseband in CMOS 28nm
88 FDSOI

<figure><img src="image_67.png" /><figcaption>Figure 6.2: A Pseudo double common-centroid placement for UCC fo FIR DAC coefficients. The blue shaded coefficients in the left of the impulse response are placed in the outer sections of each quadrant, and those in green inside. The unmatched center tap is placed in all quadrants.</figcaption></figure>

of routing required from the switch array block to the current source array block. For instance, an 8-6
segmented 14-bit DAC has 255x16 unit current sources in unary implementation [Van+99]. These num-
ber of current sources are close to those number of unit current cells, 4974, that could have implemented
the 802.11ac mode in this FIR DAC. Here, an assumption is made that the smallest coefficient of the FIR
DAC is not divided into power of two units. Otherwise, the number of unit current source transistors
would be 4974x16. In the example, the distinct number of signals routed from the switch array block to the current source array are only eight. This reduced number allows for employing a switching scheme where the current sources that share the same routing signal can be dispersed as desired. Nonetheless, in the FIR DAC case, this number would have been 63—equal to the number of filter taps. If the current sources are as dispersed as a particular switching scheme may demand them to be, then the complexity and speed penalties corresponding to routing 63 signals from a switch array block to a current source array block would be immense. To put it in perspective, if a 64x68 matrix is used for the current source array as the switching scheme in this example [Dev+04], twelve out of the 63 coefficients of the 802.11ac would have one unit current source in each column and also in each row. That is there would have been at least twelve interconnects in each column since there are twelve coefficients whose values are greater than or equal to 68. The amount of parasitic capacitance mainly due to sidewall capacitance between parallel routing metals would significantly affect the output impedance of those current sources, Equation (4.21) in Chapter 4. Therefore, the idea of placing the current sources in a block separate from the switching blocks was dropped.

To target high speed operation, the placement method for FIR DAC has to be such that the whole unit current cell is placed as if it was a unit current source transistor. The unit current cell, also UCC, contains the digital latch and analog current source that implements a unit coefficient. The unit coefficient is a value which can be combined to arrive at all other coefficients only using addition or subtraction. In a placement method where the UCC is placed as one unit element in an array, the analog signals within one UCC are routed short distance. The only analog signals which will be routed long distance are the output signals of the FIR DAC. Digital signals from the drivers to the UCC are routed vertically or horizontally, but long distance. Now instead of long distance routing of current source analog signals, it is digital signals that drive the switches which will be routed long distance.

The only problem to high speed operation with this placement method increased time constant due to parasitic capacitance and wire resistance. The digital signals are routed in parallel in the array, so resulting parasitic capacitance between them contributes to increase of time constant and signal may be degraded due to crosstalk. These problems can be tackled with careful choice of metals, shielding and wire sizing.

Other placement methods which were explored to be utilized for FIR DACs are those that are used in switched-capacitor filters. These filters have capacitors whose ratios are random, not power of two as traditional multi-bit DAC weights. The switched capacitor filters can also be long. These characteristics of switched-capacitor filters makes their placement method interesting enough for adoption in FIR DACs. There are many placement methods that are designed for capacitor arrays where linear and quadratic mismatch errors are cancelled even when the values of the capacitors and their ratios are random [SP15].
If the diagonals of the device array are assumed to be aligned with the axes of the systematic errors, mathematically, the errors for a device implemented as one unit can be expressed as follows:

$$ \epsilon(x, y) = \epsilon_{\text{lin}}(x, y) + \epsilon_{\text{quad}}(x, y) \qquad (6.1) $$

$$ \epsilon_{\text{lin}}(x, y) = k_{l,x}x + k_{l,y}y \qquad (6.2) $$

$$ \epsilon_{\text{quad}}(x, y) = k_{q,x}(x^2) + k_{q,y}(y^2) \qquad (6.3) $$

$$ k_q = k_{q,x}\cos(\theta), \quad \text{and} \quad k_q = k_{q,y}\sin(\theta) \qquad (6.4) $$

$k_x$ and $k_y$ are gradient error constants in the x and y directions respectively, and $k_{q,x}$ and $k_{q,y}$ are constant in the x and y directions of the quadratic error, and $\theta$ is the angle the axes of the error makes with the x-axis.

<figure><img src="image_68.png" /><figcaption>Figure 6.4: Systematic error differences between even valued coefficients left and right of the center tap</figcaption></figure>

In a common-centroid scheme, one device is divided in four units which are placed in each quadrant. Clearly, the linear errors of the device are canceled, but not the quadratic errors. The strategy is to equalize the quadratic errors of all the devices. The best strategy for that is double common-centroid as shown in Figure 6.2. In this scheme, all the devices with more than four unit elements have at least one unit element in each quadrant. For those that have a multiple of four, the quotient are placed in each quadrant in a common-centroid scheme around the center of each quadrant, and the remainder in the center of the UCC array. The units elements of the devices with less than four unit elements including the remainders of those devices represented by more than four units are placed symmetrically around the center of UCC array, i.e. in the **CENTER**. This scheme approximates the net quadratic error of each device to be equal to the value if the devices were placed as a single device at the center each quadrant.
Let $N_i$ be the number of UCCs required to implement a coefficient $C_i$, where $1 \le i \le N_{tap}$, and $N_{tap}$ is the number of taps of the filter.

$$N_i = 4Q_i + R_i \qquad (6.5)$$

$Q_i$ are number of UCCs of $C_i$ placed in each quadrant, and $R_i$ are placed in the **CENTER** of the UCC array. $Q_i$ of each quadrant are placed in a common-centroid configuration within that quadrant.

Since the impulse response is symmetrical about the center coefficient, the UCCs that belong to the coefficients that are in the left of the impulse response, in Figure 6.2, are placed in the left parts of each quadrant. Those in the right are mirrored horizontally from those in the left. Quadrant-I is quadrant-II mirrored horizontally, and quadrants III and IV are copied from II and I by mirroring them vertically. The center coefficients of this odd-numbered impulse response appears in all quadrants in both **LEFT** and **RIGHT**. Because of the fact that the placement in each quadrant is not strictly common-centroid, it is called pseudo double common-centroid. A more thorough common-centroid placement method could be used for the $Q_i$ in each quadrant using methods reported in [SP15]. However, since coefficients with units in one quadrant have also units in other quadrants, the linear parts of their systematic errors are generally canceled. Moreover, the other placement methods come with additional costs in routing area and complexity.

The linear and quadratic components of the systematic errors are reduced by this method. For coefficients that has $Q_i \ge 4$, the center of their net quadratic error will be at each section of the quadrant. For example, quadratic errors for two hypothetical coefficients, $C_1$ and $C_2$, with 12 UCCs each in the four quadrants of the UCC array and positioned as the coefficients $C_{68}$ and $C_{72}$ are shown in Figure 6.4. The figure is scaled with focus on the center of each quadrant so that it fits the page with good visibility. The axis of the quadratic error are assumed to be aligned with the X and Y axis. The three UCCs of $C_1$ and $C_2$ in each quadrant have a quadratic error of:

$$\epsilon_{quad,C1,i} = k_q(x_{C1,i}^2 + y_{C1,i}^2) \qquad (6.6)$$

$$\epsilon_{quad,C2,i} = k_{q,x}(x_{C2,i}^2 + k_{q,y}y_{C2,i}^2) \qquad (6.7)$$

and the total error for $C_1$ and $C_2$ in all the four quadrants can approximated as:

$$\epsilon_{quad,C1} \approx 4(3(k_{q,x}x_{C1,IIL}^2 + k_{q,y}y_{C1,IIL}^2)) \qquad (6.8)$$

$$\epsilon_{quad,C2} \approx 4(3(k_{q,x}x_{C2,IIR}^2 + k_{q,y}y_{C2,IIR}^2)) \qquad (6.9)$$

Thus, the net resultant quadratic error for a coefficient is proportional to the distance between the center of a section of a quadrant and the center of the array. This creates a difference between the
coefficients in the right side of the impulse response and those in the left as those in the right are placed
near the center. For $C_1$ and $C_2$, this difference can approximated as:

$$ \epsilon_{quad,C1} \approx 4(3(k_{q,x}\Delta_{X,C1C2}^2)) \quad (6.10) $$

Besides, there is also quadratic error difference between coefficients with $Q_i \ge 4$ and the small-valued coefficients that has $Q_i < 4$. The latter has all their UCCs in the **CENTER**, so their quadratic error is expected to be relatively much smaller. Besides, those coefficients that are around the center of the impulse response have the highest because of they are implemented with higher number of UCCs. For example, the quadratic error difference between the coefficients $C_1$ and $C_2$ and the coefficients $C_{31}$ and $C_{33}$ highlighted in Figure 6.3 can be approximated as:

$$ \epsilon_{quad,C1C31} \approx 4(k_{q,x}(63x_{C1,IIL}^2 - 3x_{C31,IIL}^2) + k_{q,y}(63y_{C1,IIL}^2 - 3y_{C31,IIL}^2)) \quad (6.11) $$

$$ \epsilon_{quad,C2C33} \approx 4(k_{q,x}(63x_{C2,IIR}^2 - 3x_{C33,IIR}^2) + k_{q,y}(63y_{C2,IIR}^2 - 3y_{C33,IIR}^2)) \quad (6.12) $$

This estimate can be used in the design of the UCC. The effect of the error on the transfer function can be simulated by incorporating this relative error into the value of each coefficient. Since each coefficient experiences different error magnitude, it is preferable to simulate the transfer function with this non-uniform error distribution. However, it is also possible to design the UCCs for a random error which is large enough to accommodate the quadratic error.

One advantage of the placement method is, then, to distribute the UCCs of the highest coefficients around each quadrant so that the cumulative quadratic error of a big coefficient is a sum of the errors that belong to the UCCs near the center of the array, this error is relatively close to zero, and those far away from the center of the quadrant. This way the total sum is reduced.

This advantage is obtained while still canceling the major contributor of the systematic errors—the linear part. The fact that the UCCs of a coefficient are distributed around the array is also a positive feature of this method.

### 6.2.2 Layout Floorplan

The layout floorplan of the FIR DAC is shown in Figure 6.5. The single bit input data pass vertically to the UCC array, the clock is supplied horizontally from the left using a clock tree and the outputs are summed with a similar output tree in the right. The digital **Delay Line** outputs are fed to the **Routing Matrix** which is a matrix of interconnects that enables the UCCs to be driven by the digital data outputs from one or more taps of the delay line. The routed matrix of interconnects are inputs to the **Mode Selection**
block which basically selects the data out of the delay line. This is done using a mode selection *SEL* input. The **DATA DRIVERS** are inserted to compensate for the speed degradation that may result from routing the data to the latches in the UCC array. At the center is the UCC array where the UCCs of the coefficients are placed according to the method discussed in subsection 6.2.1. At the center of the UCC array are the biasing circuits for each section of the four quadrants. The biasing circuits are divided into two parts—**Global** and **Local**. The **Global** circuits at the center of the chip (GCM block) mirror the input reference current and are supplied with a separate voltage supply. The supply, *VDD_BIAS* and the reference current are fed to chip from the bottom side as shown in Figure 6.5 and 6.7.

<figure><img src="image_69.png" /></figure>

Figure 6.5: FIR DAC floorplan. The current mirrors are local and global—LCM and GCM. The data is propagated from the top starting from 63-flip-flop delay line, to 76-multiplexers mode selection, then to 76 drivers. The clock tree has 64-rows and the output is obtained from differential outputs of a 64-row tree.

There is a common supply voltage, *VDD<sub>DIG</sub>* , to all circuits except the biasing circuits. The supply to
the biasing circuits is $VDD_{BIAS}$, and the reasons for this are explained in 6.3.7. The common $VDD_{DIG}$ is routed along with the ground line using a distribution grid. The grid lines pass through each one of the 64 rows and 82 columns of the UCC array. This density is maintained also on the clock tree, and vertically up to the *DelayLine*. The empty space outside the circuit blocks is filled with decoupling capacitors.

In the UCC array, two high speed analog outputs, power and ground lines, high speed digital clock and data lines, an asynchronous mode selection signal, and two current mirror biases are routed—a total of nine distinct signals. The clock is routed using thick top metal in one side, and the two outputs and two bias current signals in the other side of the UCC. The data lines are propagated vertically on one side and the mode selection *SEL* signal on the other as shown in Figure 6.20.

<figure><img src="image_70.png" /><figcaption>Figure 6.6: A section of the UCC array. Dummy UCCs surround the edge of the array as shown. The data, clock, output, bias and select signal lines of the UCC are routed such that the array area is exactly the sum of the areas of the UCCs.</figcaption></figure>

Design rules require for some distance between power and ground lines. A decoupling capacitor is
placed in this gap to stabilize the supply voltage on each UCC. There are six UCC layout variants. They are those that are turned-on only in 802.11ac, only in 802.11ad and those that are shared. To keep the global UCC array structure stable, positive and negative coefficient variants are prepared for each of the three UCC types mentioned.

The mode selection *SEL* signal was optimized to turn-off the UCC if it is not operating in the selected mode. The *SEL* signal is also used to: select data inputs in the multiplexers of the mode selection block, set the input of the non-selected multiplexers to ground, and to turn-on and turn-off UCCs.

The digital lines from the output of the *DATADRIVERS* are routed to the columns where their corresponding UCCs are accessible. There are two data lines in the first column, three in the second column, increasingly towards the middle of a section of a quadrant. This is because most the of UCC in the middle belong to a coefficient with small number of $Q_i$ (the number of UCC that belong to a coefficient in one quadrant). As a result, there are more parallel data lines, up to eight, in the middle of a section of each quadrant. For this reason, the data lines in the middle are more loaded with sidewall parasitic capacitance than those data lines on the left and right side of the a section of a quadrant of the UCC array. However, with respect to total parasitic capacitance looking from the output of their respective drivers, the data lines in the middle feed to only a few UCCs and experience smallest input capacitance loading. On the other hand, those at the edge are driving up to 16 UCCs in one section of a quadrant, and experience more loading. This, nevertheless, has been discussed more precisely in subsection 6.3.4.

Since it is a custom layout, careful column by column optimization was done to decrease the number of data lines routed vertically. For example, horizontally propagating data lines using a free metal layer to UCC that belong to the same coefficient. In the UCC layout, the nearby analog signals in one side of the UCCs, the two outputs and two biasing signals, are separated by some horizontal gap and vertically by using different metal layers. The fringe capacitances that resulted were minimal.

## 6.3 Design and Layout of Each Block

The circuit blocks are briefly introduced in subsection 6.2.2 when discussing the floorplan. In this sub-section, the circuit topology used, and design strategies followed in each circuit block are discussed.

### 6.3.1 Digital Delay Line

The outputs of the digital delay line are taken through the routing matrix to the input of the Mode Selection block. Depending on the mode, the output can drive up to seven multiplexers. In the 802.11ac mode, the outputs of each of the flip-flops of the delay line are connected one-to-one with the inputs of the
<figure><img src="image_71.png" /><figcaption>Figure 6.7: FIKRDAC Layout</figcaption></figure>

multiplexers of the mode selection. However, in the 802.11ad mode, where smaller number of outputs, 17, of a shorter delay line are driving the same number of multiplexers, the flip-flops may experience a fan-in up to seven. Thus, the flip-flops are designed for the maximum load.

To reduce clocking timing errors, and the added area and power consumption needed for complementary clocking, the delay line is based on a TPSC flip-flops. Although only a single output is needed, the clock loading for the positive-edge triggered differential semi-static flip-flops, shown in Figure 6.8, is minimized and, hence, have the lowest power consumption [YS97]. Moreover, they can be implemented without additional circuitry, only a low power single-to-complementary buffer-inverter combo is needed, Figure 6.19.

The first stage is an CVSL-based circuit which evaluates the differential inputs when the clock is low. These outputs are forwarded to the output of the second stage when the clock goes high. The inverters hold the outputs steady. There is a chance a *HIGH* data input can go to second stage before the clock goes low in the PMOS transistor, but the outputs do not change before the NMOS is clocked by a rising edge.
<figure><img src="image_72.png" /><figcaption>Figure 6.8: A semi-static Flip-Flop for the delay line of the FIR DAC</figcaption></figure>

### 6.3.2 Mode Selection

In the 802.11ac mode, the mode selection block is a line of multiplexers with as many multiplexers as there are flip-flops in the delay line. There is a one-to-one matching between the delay line outputs and the mode selection inputs. In the 802.11ad mode, these line of multiplexers are driven by a shorter delay line, 17. Since the coefficients of the 802.11ad are only approximated when the 802.11ac coefficients are combined, additional coefficients are needed for fine-tuning. The inputs to these additional coefficients still come from the delay line but they operate only in the 802.11ad mode. Hence, similar to the multiplexers corresponding to the coefficients working only in the 802.11ac mode, one of their inputs are tied to the ground.

The multiplexers are designed based on a transmission gate logic to transfer both high and low values effectively as shown in Figure 6.9. Input and output inverters are inserted to balance loading experienced by the outputs of the delay line and the inputs of the data drivers respectively.

### 6.3.3 Routing Matrix

The routing matrix is the main block which enables configurability of the FIR DAC. The function of this matrix is to route delay line outputs to multiple coefficients so that a new set of coefficients can be
<figure><img src="image_73.png" /><figcaption>Figure 6.9: A 2-by-1 multiplexer for mode selection</figcaption></figure>

created. In the 802.11ac mode, the coefficients match one-to-one with the delay line outputs according to the filter impulse response of 802.11ac in chapter 5. In the 802.11ad mode, they have to be routed according to a summation table.

The delay line of 802.11ad is created from the first 17 flip-flops in the delay line of 802.11ac. The remaining flip-flops can be turned-off for power saving. Below each of the 17 outputs are the taps which are driven by these same outputs. For example, The output of the first flip-flop drives both the 18th tap; likewise, the output of the third drives taps 1, 3, 15, and 17. Coefficients from 64 to 76 are added for fine-tuning the coefficient values of the 802.11ad. Here they are being driven by one of the 17 outputs of the 802.11ad mode delay line. Their inputs are grounded in 802.11ac mode.

<table><caption>Table 6.1: Weights of the 802.11ad mode fine-tuning coefficients</caption><tr><td>Taps</td><td>64</td><td>65</td><td>66</td><td>67</td><td>68</td><td>69</td><td>70</td><td>71</td><td>72</td><td>73</td><td>74</td><td>75</td><td>76</td></tr><tr><td>Values</td><td>11</td><td>-2</td><td>-1</td><td>5</td><td>14</td><td>4</td><td>2</td><td>4</td><td>14</td><td>5</td><td>-1</td><td>-2</td><td>11</td></tr></table>

At the output of the mode selection, there are 76 data values. Each one of the first 63 values drive some number of UCC as defined in the impulse response, the remaining 13 values drive UCC as defined in Table 6.1. The UCC array occupies large area. Routing the outputs of the mode selection block directly to the UCC inputs incurs significant speed reduction. Therefore, data drivers are inserted to drive both the total UCC input impedance and to compensate speed losses due to routing.
<figure><img src="image_74.png" /></figure>

Figure 6.10: This shows how the coefficients of 802.11ad are created from 802.11ac. The number at the top indicate taps of the 802.11ad. Each tap is drives the taps 802.11ac taps listed below it and the taps for fine-tuning from 64–76.

<figure><img src="image_75.png" /></figure>

Figure 6.11: The layout of the digital delay line, routing matrix and the mode selection blocks. One of the inputs of the Muxs is directly connected to the flip-flops whereas the other is connected according to the matrix shown above in the table.

### 6.3.4 Data Drivers

The input data to the FIR DAC are sampled first time at the flip-flops of the delay line, and they are synchronized again at the latches that drive the differential switches of the UCCs. Thus, there are two set of paths between the arrival of the data at the input of the *DelayLine* and at the differential switches of the UCCs. The data time delay between the delay line and the latches has to be less than one clock period minus the hold time required at the flip-flops and the setup time required at the latches. To ensure the data arrives ahead of the clock edge, drivers are inserted between the mode selection and the UCC array. The delay from the output of the delay line to the driver is a small fraction of the period of the clock. However, the delay from the output of the drivers to the input of the latches may not be within the expected margin.
### Bandwidth Limitation

The design of data drivers depends on the total load of each data line. For smaller number of UCCs and when the input capacitance of the UCCs, $C_{UCC}$, is such that the total input capacitance defines the time constant, tapered buffer design which only considers the capacitance as a load can be followed to arrive at the size the drivers. Parity in time delay for each data line can then be reached by sacrificing some area and power consumption by choosing drivers with equal number of stages for even the data lines with smaller number of UCCs.

<figure><img src="image_76.png" /><figcaption>Figure 6.12: The placement of 254 UCCs of coefficient 32 and a depiction of the routing of the data line from driver to the UCCs</figcaption></figure>

Nevertheless, in some cases, the data lines on the left and right edges of a section of a quadrant drive a high number of UCCs. This is because the UCCs that belong to the biggest coefficients in the impulse response of the FIR DAC are placed in the outer edges of the quadrants with the UCCs that belong to the smallest coefficients in the middle of the quadrants. This is done to equalize the quadratic errors of the randomly-valued coefficients. These data lines normally drive up to 256 UCCs, for example, for the center tap. On the other hand, when there is a long RC interconnect in such a way that the $\tau_{rc} > \tau_{driver}$, the equivalent load impedance of the wires should be calculated. The driver has to be designed to make sure the required data rate, and the required bandwidth of the system can be met.

To further explain the point above, Figure 6.12 shows the routing from the output of the driver for coefficient 32 in the 802.11ac impulse response, which is realized with 254 UCCs. The UCCs, as expected, are in common-centroid configuration with two remainders in the center. Each UCC has different RC interconnect delay between itself and the driver. This is clearly shown in Figure 6.13. The
RC segments are represented by an equivalent impedance. The UCC in one location are represented by a box whose equivalent circuit is shown to the right. The model for *N* number of UCCs has *N* number of input capacitances and *N* − 1 RC segments between them. The equivalent circuit of the rest of the quadrants is the same as that of the first quadrant.

<figure><img src="image_77.png" /><figcaption>Figure 6.13: Model of equivalent impedance of routed data lines for coefficient 32 with 254 UCCs</figcaption></figure>

All the latches of all the UCCs are clocked with the same signal. The delay difference between the clock edges at two different latches of the 254 UCCs is insignificant; or it is expected to be corrected by the binary tree of the output network. As a result, it is only enough to estimated the worst delay from the driver to one of the latches of the 254 UCCs. The UCCs placed furthest away from the driver are the obvious candidates. To find the worst delay, the total RC interconnect between the driver and the UCC of interest has to be modeled.

A simple *RC* lumped wire model from the driver output to the input of the UCC of interest may not give us an accurate estimation of the delay—tends to be pessimistic [RCN03]. Hence, unnecessary over design of wire widths, usage of higher metals while not needed could result. Common approximation for a distributed wire model are shown in Figure 6.14. A distributed wire model with the Π-model
<figure><img src="image_78.png" /><figcaption>Figure 6.14: RC interconnect models that can be used for fast, less accurate estimation of delay</figcaption></figure>

approximation results in a more accurate, compared with the lumped model, delay estimation. However, the amount of calculation required to estimate the component values could be complex even for a few interconnects. An elaborate wire model may consider metal-to-substrate capacitance, metal-to-metal fringe capacitance, overlap cap, routing resistance, via resistance, etc. In advanced technologies where there are up to ten metal levels, and in a dense layout, this may not be an easy feat.

One formula which gives a practical delay estimation for an RC network with simpler calculations is the Elmore delay formula. The formula assumes a network with one source node where there are no resistive loops and all the capacitors are between a node and ground [RCN03]. Although it is a first-order approximation, its simpler calculation makes it attractive.

Depending on the complexity of the coefficients, the RC segments in Figure 6.13 can be replaced with lumped model of the approximation in Figure 6.14. The Elmore delay from a source S, the driver, to node i, one of the UCCs, is given as [RCN03]:

$$ \tau_{si} = \sum_{k=1}^{N} C_k R_{ik}. \qquad (6.13) $$

Where k is a capacitive node in the circuit, and N is the number of nodes. There is a possibility that the formula can result in large errors. However, it is predicted to work better when the node of interest is farther from the source [ADK01].

It is interesting to derive some quantitative expression for bandwidth limitation calculation using the pseudo double common-centroid UCC array placement. It is observed that the RC interconnect associated with the biggest coefficient results in higher time constants. The biggest coefficients are placed in the perimeter of the sections of the quadrants. A driver for a coefficient whose value is almost equal to the biggest coefficient, the center tap in a symmetrical FIR DAC impulse response, requires four data line routing. Two lines in the left and right side of a section of a quadrant, and two in the other. A
fifth for the center if it has a remainder after division by four.

The value of the coefficient can be approximated to $2^B$, $B$ is quantization bits. Out of four data lines routed to four quadrants, $\frac{2^B}{4}$ UCCs are connected to one. Considering Figure 6.13, each one-fourth of $\frac{2^B}{4}$ are placed in one location feeding from a tap from this line. The RC segment between the UCC in each group is neglected. The Elmore delay from the driver output to the furthest UCC along the data line in the left-end of the figure can be calculated as a sum of:

$$ \tau_{si} \geq \frac{2^B}{4} C_{in\_UCC} R_1 + \frac{2^B}{4} C_{in\_UCC} R_2 + \frac{2^B}{4} C_{in\_UCC} R_3 + (\frac{2^B}{4} - 1) R_4 + C_{in\_UCC} R_{total\_line} \quad (6.14) $$

Where $R_1, R_2, R_3$, and $R_4$ are resistive approximation of $Z_{eq0} + Z_{eq1} + Z_{eq2}, Z_{eq0} + Z_{eq1} + Z_{eq2} + Z_{eq4}, Z_{eq0} + Z_{eq1} + Z_{eq2} + Z_{eq4} + Z_{eq8}$, and $Z_{eq0} + Z_{eq1} + Z_{eq2} + 2Z_{eq4} + Z_{eq8}$. $R_{total_line}$ can be approximated as a sum of: $Z_{eq0} + 2Z_{eq1} + Z_{eq2} + 2Z_{eq4} + Z_{eq8}$ because the RC segment between two UCCs of the same group is neglected. This leads to

$$ \tau_{si} \geq \frac{2^B}{4} C_{in\_UCC} (R_1 + R_2 + R_3 + R_4 + R_{total\_line}) \quad (6.15) $$

$$ \tau_{si} \geq \frac{2^B}{4} C_{in\_UCC} (4(Z_{eq0} + Z_{eq1} + Z_{eq2} + Z_{eq4}) + 2Z_{eq8}) \quad (6.16) $$

If $Z_{eq8}$ RC segment is close in length as the other segments, $4(Z_{eq0} + Z_{eq1} + Z_{eq2} + Z_{eq4}) + 2Z_{eq8}$ can be approximated to be around $3.5R_{total_line}$. Then the maximum time constant of this particular line is given as:

$$ \tau_{si} \geq 3.5 \frac{2^B}{4} R_{total\_line} C_{in\_UCC} \quad (6.17) $$

For example, to achieve a bandwidth of 3.52 GHz with 8-bit quantized coefficient and with $C_{in\_UCC}$ of around 400 fF, the left-end data line has to be $\leq 1.3K\Omega$. This can be difficult to fulfill, so it is advisable to use non-shared data lines to a group of UCCs when possible.

The data drivers have a fan-out of four and range from two stage to five stage. A more square layout is obtained by breaking down the longest stages into layers as shown in Figure 6.15. After the final layout of the UCC array, the wire resistance and capacitance were again estimated, and the widths of the wires were changed and choices of adjacent metals changed adjusted in some cases to shorten time delay.

### 6.3.5 Clock Tree and Output Tree

Two circuit blocks in the chip require clocking. They are the digital delay line, and the synchronizing latches in the UCC array. Due to its size, the clock in the UCC array is distributed with the help of a
<figure><img src="image_79.png" /></figure>

Figure 6.15: The layout view of the a five-stage driver used for the biggest coefficients in the center of the 802.11ac impulse response. Additional stage inserted not to invert the data. Supply connected using parallel thin wires to ensure low current density.

binary clock tree. The delay line occupies SMALLER area compared to the array. No clock tree is used for the delay line. The clock is supplied with a single metal running across all 63 flip-flops in the delay line. The delay from the clock at the PAD output to the delay line and to that of the clock tree output are equalized by using identical structures. The clock to the digital delay lien is driven by a seven stage buffer whose sizing is equal to a single *leaf* of the binary clock tree as shown in Figure 6.18. To maintain equal loading at each stage of buffer for the delay line, dummy inverters which have the same sizing as their counterparts in the binary clock tree are used.

The UCC array is arranged by taking the clock distribution into consideration into 64 equally-spaced rows. A top metal is used to route the clock signal along each row from the output of the tree to decrease the capacitance to adjacent metals and to the substrate. The output clock signal of all the 64 rows is shorted with a top metal spine. This is done to reduce timing differences between rows.

The binary clock has seven stages. Each buffer stage is designed at a fan-out of four. The layout is such that the loading at the nodes of a stage are the same; for example, equal width, length and level of wires, and same size of vias.

Although the final clock signal at the output of the binary tree is distributed with a low capacitance top metal routing, there are still timing differences among the UCCs along a single row. Practically, the UCCs to the side of the clock tree are clocked earlier than those farthest in the right. That is the output of those in the left will appear earlier. To balance this difference, a similar binary tree is used for summing
<figure><img src="image_80.png" /><figcaption>Figure 6.16: The clock is distributed with a seven stage clock tree to the UCC array, and a single leaf of this tree to the delay line. The inverters in the tree are sized have a fan out of 4. This is kept in the inverter chain to the delay line using dummy inverters.</figcaption></figure>

the outputs.

### 6.3.6 Unit Current Cell

The UCC comprises both the digital and analog current source in one block. A single-ended data is its input. A circuit consisting of a transmission gate and an inverter create the signal for differential switching of the current source. The PMOS and NMOS transistors of the transmission gate are sized in the same ratio as those of the inverter. The differential signals are clocked using a steep transition latch [Lin+09]. The output of the latches drive the differential switches of the current source. Off-chip loads resistors are used.

Since the data is routed a long distance, a synchronizing latch is added. Each UCC has a synchronizing latch. Some power and area savings could be obtained by sharing one latch for a number of UCC,
<figure><img src="image_81.png" /></figure>

Figure 6.17: The layout view of the final stage buffers of the clock tree. Each PMOS and NMOS are sized $2^6$ times the first stage transistors. The fingers are arranged as such so that the clock tree outputs of each of the 64 rows are routed straight to the UCC array with short wires and with minimum distance between the rows of the UCC array.

<figure><img src="image_82.png" /><figcaption>Figure 6.18: The layout view of the clock tree</figcaption></figure>

i.e. data out of one latch to drive switches of multiple current sources that belong a coefficient. The disadvantage in this case is the errors that are incurred due to small timing differences in the switching of the current source of the different UCCs being driven by one latch. This errors depend on the layout and sizing of the latch and the UCCs, but the hard task of placing UCCs in different locations to mitigate mismatch and sharing an equidistant latch for all of them remains. To decrease SFDR degradation due distortion caused by timing differences, the latches of a UCC are placed as close as possible to the differential switches.

One of the advantages of the selected latch is the fact that the output of the latches intersect below the middle point of the signals. By following the latches with inverters, the outputs which control the switches are crossing above the middle point This prevents the possibility of the NMOS differential switches turning off simultaneously. It also guarantees the current never is interrupted as the controls signals allow smooth transition of current from one branch to the other. The crossing point is also set high enough so that the common source node fluctuation is minimized [Bas+98].

The latch was sized so as to decrease its contribution to the total local timing error of the FIR DAC.
<figure><img src="image_83.png" /><figcaption>Figure 6.19: Transistor level schematic of a Unit Current Cell which works in 802.11ac mode and is controlled by SEL signal to turn-off in 802.11ad</figcaption></figure>

The following expression for SDR due to random local timing errors is used in the simulation [DRL06]:

$$ SDR = \frac{N}{(8f_{sig}f_{s}\sigma^{2})} \qquad (6.18) $$

where N is the number of unary elements in the 802.11ac or 802.11ad modes of the FIR DAC, $f_{sig}$ is the data bandwidth, $f_s$ is clock rate and $\sigma$ is the standard deviation of the random timing errors. Contribution to the spread of the timing errors is calculated from mismatch of clocked transistors using capacitive loading, biasing current and technological parameters. Similar approach was used to estimate and consider the error that can be contributed due to capacitive loading difference between the gates of the differential switches of the UCC and the final driving tri-state inverters' output load capacitance. The tri-state inverters are sized taking the timing errors, and the high crossing control signals for the differential switches into consideration [TG06].

A combo of tri-state inverters and input grounding is used to turn-off the UCC when it is not part of the operating mode impulse response. This mechanism ensures that the differential switches stay turned-off. The same signal as the mode selection signal is the input to the tri-state buffers. Therefore, the signal that selects a standard in the *ModeSelection* block all turns off unused UCCs of the other mode. These arrangement does not change the high-crossing output expected of the tri-state inverters.

The back-to-back inverters are sized small, and they help in reducing the clock feedthrough to the output [BSS04]. The gate-to-drain charge feedthrough in the differential switches introduces distortion in the outputs. Different methods to mitigate this problem: one is to add a cascode transistor on top of the switches. This method does not suit advanced CMOS nodes as it requires higher analog voltage
supply. It is also possible to lower the swing of the control signals. This method negatively affects the maximum speed at which the UCC can operate [CG07]. A method preferred here is to add two dummy switches with floating sources and are driven opposite to the switches with the same complementary control signals. If they are sized the same as the switches, the problem of charge feedthrough is reduced [LCD00].

<figure><img src="image_84.png" /><figcaption>Figure 6.20: The layout view of a unit current cell used in both modes.</figcaption></figure>

The overdrive voltage and size of the current source transistor are designed to meet the random mismatch requirement as given by Equation (4.13) in Chapter 4. That is the drain voltage of the current source transistor, $M_{CS}$, is set to $V_{OV} + V_{tol}$ higher than the overdrive voltage. $V_{tol}$ is a to ensure saturation operation. To operate the cascode transistor in saturation region, the common source node of the switch transistors has to be at least $2V_{OV} + 2V_{tol}$. The unit current is set by the dynamic range required at the
output as explain at the end of Chapter 4. Large number of UCCs, 4974 in the 802.11ac mode, sum up to a large output swing. This takes big part of the voltage headroom in a low voltage supply operation of the UCC. To ensure saturation region operation of the differential switch transistors

$$VDD_{ANA} - N_{unit}R_{load}I_{unit} \geq 3V_{OV} + 3V_{tol}. \qquad (6.19)$$

The effect of data dependent output impedance on the dynamic performance of the FIR DAC is already discussed in chapter 4. To ensure high output impedance up to higher frequencies, minimizing unnecessary interconnects during layout of the UCC is important. The contribution of the parasitic capacitances due to interconnect is minimum in this implementation. That means the output impedance will stay flat up to higher frequencies, but the actual values depends on the sizing and biasing of the transistors. This was set through simulation in Cadence® and MATLAB® by tweaking the biasing voltages and sizes of the transistors.

To obtain a more square layout of the current source transistor, it is realized using two identical transistors in series. The current source and cascode transistors are placed inside a guard ring. To stabilize the supply voltage of the UCC, a NMOS decap is connected in the gap between VDD and GND planes.

### 6.3.7 Biasing circuits

For best dynamic performance of the UCC, the current mirror needs to target ideal requirements. The relationship between SFDR of UCC and output impedance is already stated in Chapter 4. Ideally, a current mirror should also have low input resistance. Technological limits such as supply voltage also limit the input and output voltage swings a particular topology of a current mirror can offer. These practical parameters can be used from the selection of the circuit topology to its sizing.

Although supply voltage limit in advanced CMOS nodes discourages use of cascoding, the high speed operation targeted requires high output impedance, and cascode current mirrors generally fulfill that requirement. A classic cascode current mirror circuit is shown in Figure 6.21a. It offers high output resistance and low input resistance given by the equation (6.20).

$$r_{out} = (g_{mCS} + g_{mCAS})r_{oCAS} + 1)r_{oCS} + r_{oCAS} \qquad (6.20)$$

$$r_{in} \approx r_{o1} \qquad (6.21)$$

However, it has a high minimum output voltage which eats away on the possible load voltage swing of the UCC. An alternative is to use two simple current mirroring biases as shown in Figure 6.22. It solves the problem of high minimum output voltage by lowering it to 2V<sub>OV</sub> and still maintains high
<figure><img src="image_85.png" /><figcaption>Figure 6.21: A simple Cascode current mirror and small signal analysis of its output resistance</figcaption></figure>

output impedance. However, the current gain of such an approach suffers due to effect of drain-source voltage difference of $M_{CS}$ and $M_1$ on the output current [Bak10].

<figure><img src="image_86.png" /><figcaption>Figure 6.22: Cascode current mirror biased with two branches</figcaption></figure>

The circuit used in this implementation is shown in Figure 6.23. It offers the same output resistance that is derived in (6.20). By adding transistor $M_2$, the problem of drain-source voltage stability is solved, and in turn the systematic gain error. The origin of $M_3$ is understood by studying the single input reference current configuration of this circuit[Gra01]. In a single reference current case, transistors $M_4$ and $M_3$, as a single transistor, are connected on top of $M_2$. Gates of $M_{CS}$ and $M_{CAS}$ are biased from drains of $M_2$ and $M_3$ respectively. The gate voltage levels $M_{CAS}$ and $M_{CS}$ in Figure 6.21a have a difference of
$V_T + V_{OV}$. To cut the gate voltage of $M_{CAS}$ to one overdrive voltage more than that of $M_{CS}$, transistor $M_3$ is used. This is because transistor $M_4$ forces $M_3$ into triode region operation. This can be easily shown as follows. The gate and drain of transistor $M_4$ are tied and it operates in active region. Thus,

$$V_{G4} - V_{S4} - VT > 0. \qquad (6.22)$$

Assuming the threshold voltages of both transistors are equal to $V_T$, replacing $V_{G4}$ by $V_{G3}$, and $V_{S4}$ by $V_{D3}$,

$$V_{G3} - VT > V_{D3}, \qquad (6.23)$$

$$V_{G3} - VT - V_{S3} > V_{D3} - V_{S3}. \qquad (6.24)$$

As a result, $V_{DS}$ of $M_3$ is normally one $V_T$ lower than gate voltage of $V_4$.

<figure><img src="image_87.png" /><figcaption>Figure 6.23: Sooch cascode current mirror for local and global biasing</figcaption></figure>

In a two input reference currents configuration of Figure 6.23, its purpose is to bias the source of $M_4$. It is also useful to note that the aspect ratio of $M_3$ is a fraction of the sizes of the other transistors($M_1, M_2, M_4$) which have identical sizes. This can introduce some non-uniformity in the layout. In this implementation $M_3$ is replaced with two gate-shorted transistors $M_{3b}$ and $M_{3a}$ whose length should effectively add.

With some assumptions of equal threshold voltages, an approximate size of $M_3$ can be calculated. Both are working in triode, then their input drain current can be approximated by this equation

$$I_{in1} = \frac{K}{2} \left(\frac{W}{L}\right)_{3b} \left(2(V_{GS3b} - V_T)V_{DS3b} - V_{DS3b}^2\right) = \frac{K}{2} \left(\frac{W}{L}\right)_{3a} \left(2(V_{GS3a} - V_T)V_{DS3a} - V_{DS3a}^2\right) \qquad (6.25)$$
$K$ is a technological constant.

$$2(V_{GS3b} - V_T)V_{DS3b} - V_{DS3b}^2 = 2(V_{GS3a} - V_T)V_{DS3a} - V_{DS2}^2 \quad (6.26)$$

If we make further assumption that drain-source voltage of $M_{3b}$ is $V_{OV}$, and that of $M_{3a}$ to be $\frac{V_{OV}}{2}$, (6.26) leads to

$$2(V_G - \frac{V_{OV}}{2} - V_T)V_{OV} - V_{OV}^2 = 2(V_G - V_T)\frac{V_{OV}}{2} - \frac{V_{OV}^2}{4} \quad (6.27)$$

$$V_G - V_T = \frac{7V_{OV}}{4} \quad (6.28)$$

Another equation can be derived from the drain currents of $M_4$ and $M_{3b}$ as follows:

$$I_{in1} = \frac{K}{2}\left(\frac{W}{L}\right)_4(V_{GS4} - V_T)^2 = \frac{K}{2}\left(\frac{W}{L}\right)_{3b}(2(V_{GS3b} - V_T)V_{DS3b} - V_{DS3b}^2) \quad (6.29)$$

The ratio of transistor $M_4$ to $M_3$ can then be written as:

$$\frac{\left(\frac{W}{L}\right)_4}{\left(\frac{W}{L}\right)_{3b}} = \frac{2(V_{GS3b} - V_T)V_{DS3b} - V_{DS3b}^2}{\left(V_{GS4} - V_T\right)^2} \quad (6.30)$$

Equating (6.28) and (6.29) and substituting the previous assumption on the drain-source voltages of $M_{3a}$ and $M_{3b}$ and , the ratio can be simplified to

$$\frac{\left(\frac{W}{L}\right)_4}{\left(\frac{W}{L}\right)_{3b}} = \frac{2\left(\frac{7V_{OV}}{4} - \frac{V_{OV}}{2}\right)\frac{3V_{OV}}{2} - \frac{V_{OV}^2}{4}}{\left(\frac{7V_{OV}}{4} - V_{OV}\right)^2} \quad (6.31)$$

$$\frac{\left(\frac{W}{L}\right)_4}{\left(\frac{W}{L}\right)_{3b}} \approx 6. \quad (6.32)$$

While the design is robust with respect to output resistance, input resistances, and minimum output voltage, the input voltages of this configuration proposed in this implementation are higher compared to those in Figure 6.21a and Figure 6.22. As a result, it is important to calculate the minimum input voltage for both branches so that the minimum supply voltage can be known. This helps in determining the suitability of this configuration for low voltage operation.

$$V_{in1,min} = V_{GS4} + V_{DS3b} + V_{DS3a} \geq V_T + V_{OV} + V_{OV} + \frac{V_{OV}}{2} \geq V_T + \frac{5V_{OV}}{2} \quad (6.33)$$

$$V_{in2,min} = V_{GS1} \geq V_T + V_{OV} \quad (6.34)$$
<figure><img src="image_88.png" /><figcaption>Figure 6.24: A simulation of minimum bias VDD that ensures flat current gain</figcaption></figure>

The trade-off to the robustness and flexibility offered by the configuration in 6.23 is that the required supply voltage is high. It is interesting, then, to determine how low the supply voltage can become. In this implementation, only one reference current is used. To create a robust mirroring of this reference current to the two branches, a cascode circuit is used as shown in Figure 6.23.

$$V_{DD\_BIAS,min} = \max(V_{in1,min}, V_{in2,min}) + 2(V_T + V_{OV}) = 3V_T + \frac{9V_{OV}}{2} \quad (6.35)$$

To support this theoretical calculation, a simulation of the circuit shown is done in CMOS 28nm FDSOI. The result can be seen in Figure 6.24.

## 6.4 Summary and Conclusions

In this chapter, the system-level results of a configurable FIR DAC from the previous chapter were used to design the circuit blocks of the FIR DAC. A thorough discussion starting from the floorplan to the circuit blocks of the DAC has been provided. A pseudo-double common centroid placement method for current steering FIR DAC architectures is introduced. The strength and weakness of this placement method based on its resilience to systematic mismatch errors is also discussed. The layout floorplan of the FIR DAC chip is detailed.

Besides, the different challenges faced during circuit design of each block are examined. Layout level discussion are included as needed to clarify the approaches followed. In the next chapter, a report of measurement of the designed circuit is included.
# Measurement Results of FIR DAC
## Prototype

A configurable high pass FIR DAC was fabricated in ST 28nm FDSOI with a 10 metal layer CMOS process. The chip is fully custom designed, and occupies an active area of $0.84mm^2$. The chip micrograph is shown in Figure 7.1. Due to metal filling, the circuit blocks are not visible. It has a 4x10 PAD ring.

<figure><img src="image_89.png" /><figcaption>Figure 7.1: Configurable FIR DAC prototype die micrograph. It is fabricated in ST 28nm CMOS FDSOI.</figcaption></figure>

To characterize the prototype FIR DAC circuit, it was first packaged in a QFN40 plastic open cavity package. Then a test PCB was designed using Altium® PCB designer. The package has small leads and only in its underneath. An efficient and reliable way to solder the package is to use an automatic or a
semi-automatic machine. The JFP Microtechnic® PP7 semi automatic pick and place die bonder was
used for soldering the packaged die to the PCB at the right temperature gradient.

This chapter begins with the experimental setup section. Any specific choices with the designed
PCB, or the instruments and connectors used are discussed in this section. The prototype FIR DAC is
characterized using different inputs. Thus, the transmitter setup in Matlab® from which the input data
is generated is also explained. In the next section, the actual measurement results for the two modes
of operation of the FIR DAC are discussed separately. Discrepancies between theoretical or simulated
results and the measured results are also presented in the same section. Finally, the chapter is closed with
a last section which compares the obtained results to other works in the same area.

**7.1 Experimental Setup**

The designed circuit is that of a high pass FIR DAC that implements two impulse responses. The proto-
type chip in Figure 7.1 has eleven distinct PADs. The rest of the PADs are used for VDDDIG and GND
to lower IR drop. Two of the inputs: DATA and CLOCK are high speed digital; one is static DC input:
SEL; four are current reference and voltage supplies: IREF, VDDDIG, VDDBIAS, GND, and VDDANA;
two are analog high speed outputs: VOUTPOS, and VOUTNEG; and two are DC outputs: VOUTCAS,
and VOUTCS.

**7.1.1 PCB Design**

The *SEL* input is switched *HIGH* for the impulse response of the 160 MHz 802.11ac, and it is *LOW*
for that of IEEE 802.11ad. It can be supplied from *VDDDIG* and *GND*. The *DATA* input takes 1-bit
digital data with the *HIGH* value set at *VDDDIG* and the *LOW* value set at *GND*. The clock is also
a digital input, set on the same levels. Since both *DATA* and *CLOCK* have on-chip input drivers, the
*CLOCK* input can also be driven with a sinusoidal waveform and a DC offset. For standard 802.11ac
measurement, the *DATA* is first generated in Matlab® and then transferred to a Data Timing Generator.
The supply inputs are all within a range of any standard source meter, so they are directly connected on
the board. The differential outputs have to be connected to load resistors.

The chip was packaged in QFN40 plastic package using standard wirebond techniques. The PCB
was separately designed using standard FR4 material in two layers. The instrument-generated high
speed inputs are connected using SMAs, so a 50Ω track from the SMAs was terminated with 50Ω SMD
resistors close to the package pads of *CLOCK* and *DATA* as shown in a circuit depiction in Figure 7.2a.
Stabilizing capacitors are connected to *VDDDIG* and *VDDBIAS*. The rest of the inputs are connected
using screw connected power connectors.
<figure><img src="image_90.png" /><figcaption>Figure 7.2: Schematic of test board and the test board with the packaged die on board. The high speed input and outputs are connected with SMAs, and power connectors were used for the static signals.</figcaption></figure>

The analog outputs were initially designed to be connected to 25Ω load resistors. The initial solution was to use a transformer. However, the available bandpass baluns were not suitable for low frequency measurement. Besides, directly connecting the outputs to probes was found to be less susceptible to noise. The final measurement was carried out using 50Ω load resistors from probes. The analog outputs were directly connected to an oscilloscope and spectrum analyzer using Agilent E2695A differential SMA probe head and Agilent U1818A active differential probe. The probe head has a bandwidth of around 7 GHz which is above the expected maximum output frequency. The circuit of the probes is
<figure><img src="image_91.png" /><figcaption>Figure 7.3: Instruments used in the measurement Setup</figcaption></figure>

shown in Figure 7.2a.

There is an internal 50Ω resistor that connects the analog supply voltage to the common point of the load resistors. To account for the voltage drop in this resistor, the analog supply voltage is increased by 50 times the full-scale current as indicated in the figure. The full-scale current is different in the two modes because of the difference in the total number of UCCs. To keep the drain-source voltage of the switch transistors of the UCCs to within the safety limit, the analog supply voltage in the 802.11ad mode was lowered by about 150 mV.

<figure><img src="image_92.png" /><figcaption>Figure 7.4: The test bench</figcaption></figure>
**7.1.2 Input Data Generation**

For measurements involving random data, the *CLOCK* and *DATA* inputs were taken directly from Tektronix DTG5334 data timing generator. However, for measurement with modulated signals, the input data in the 802.11ac mode was imported to the data timing generator as a text file from a computer. The transmitter architecture used to generate the data is shown in Figure 7.5. The DTG can take at once, without repetition, a pattern file of $64e^6$ length of 1-bit values. The length of the 1-bit baseband data from the 802.11ac waveform generator oversampled by 22 is below this value. Hence, no special synchronization was needed between signal analyzers and data generators.

The circuit was clocked with a sinusoidal waveform from an RF signal generator with a DC Bias Tee connection as shown in Figure 7.3. This arrangement permits for better control to compensate any cable and termination losses from instrument to the chip. Also in this arrangement, the DTG was provided with a 10 MHz external reference from the RF signal generator.

A Keithley 2636A accurate source meter was used for supplying the digital supply voltage and the reference current. Additional DC supply was used to provide the analog supply voltage, the bias supply voltage for the current mirrors, and for the Bias tee. Output signal analysis was carried out with Agilent Infiniium DSO81204A oscilloscope and N9030A spectrum analyzer. A picture of the test bench is shown in Figure 7.4.

**Transmitter Model in Matlab®**

For 802.11ac measurements, a BPF FIR DAC transmitter architecture was assumed. The block diagram of the transmitter in Matlab® is shown in Figure 7.5. The input to this function is taken from an IEEE 802.11ac waveform generator interface. This matlab interface was used to generate complex 160 MHz, 802.11ac signals in VHT single transmitter mode.

<figure><img src="image_93.png" /><figcaption>Figure 7.5: The transmitter architecture used to generate 802.11ac data for the chip characterization</figcaption></figure>
The transmitter function implements half-band filter and resampler blocks for oversampling. Then the data is converted to 1-bit using a low pass delta-sigma modulator. A complex mixer is used for frequency translating the data to $\frac{f_s}{2}$. The 1-bit input sequence is loaded on the data timing generator as an input to the FIR DAC chip.

<figure><img src="image_94.png" /><figcaption>Figure 7.6: Transfer functions of the 802.11ac and 802.11ad modes with reference current 2.7µA and load resistance of 50Ω. The passband is expected to be attenuated by around 6.5 dB and 10 dB in the 802.11ac and 802.11ad modes respectively.</figcaption></figure>

The complex baseband data of a IEEE 802.11ad is not windowed. Only oversampling by a factor of two is needed before the data is frequency translated to $\frac{f_s}{2}$. To simplify the test of this mode of the FIR DAC, non-oversampled PRBS data at the same rate as the clock was used.

## 7.2 Measured Results

The expected transfer functions for the two modes are recalled in Figure 7.6. The coefficient values of the two transfer functions are adjusted to the reference current and load resistors used in the measurement.
The unit coefficient is equivalent to a drop of 2.7 µA on a 50 Ω load, and the current values for the rest of the coefficients are an integer multiples of $I_{REF}$ on the same load. The passband of the magnitude responses experience a drop of 6.5 dB and 10 dB, compared to the a 0 dB gain full-scale values, for the 802.11ac and 802.11ad modes respectively. The reason this value of reference current was selected is to adjust the DC bias conditions to the load resistors of the output differential probes. High reference current results in the triode operation of the switch transistors of the UCC for the analog supply voltage indicated in Figure 7.2a. In cases where a different value of reference current is used, for different reasons, it will be indicated. However, the figures should help as a reference at this value of current.

The FIR DAC was characterized for its performance as a standalone filter and as a FIR DAC as part of a transmitter in each mode of operation. In the 802.11ac mode, actual 802.11ac modulated signal was used to test the chip for wideband operation with different MCSs. Then PRBS input data was used to characterize the FIR DAC as a filter. Single-tone signals were also used to check the dynamic performance of the FIR DAC, and they are included in the last parts of 802.11ac sub-sections.

### 7.2.1 Biasing Circuits

The first sub-section is measurement of the wide-swing biasing circuits used in the FIR DAC. A detailed analysis of the circuits in transistor level of abstraction is already included in Chapter 6. During measurement, the operation of the mirroring circuits at different parts of the FIR DAC chip was tested by varying the biasing voltage.

<figure><img src="image_95.png" /><figcaption>Figure 7.7: The biasing voltages of the current source of the UCC, and the current gain, $\frac{I_{UCC}}{I_{REF}}$, for different values of the biasing voltage supply. The current gain plateau</figcaption></figure>
There were wide-swing mirroring circuits in each of the quadrants of the UCC array. An additional replica circuit was used to generate the UCC current source biasing voltages—$V_{CAS}$ and $V_{CS}$—for testing purposes. The measurement shown in Figure 7.7 is the values of these output UCC bias voltages.

As their name suggests, $V_{CS}$ is the gate bias voltage of the current source transistor and $V_{CAS}$ is the gate bias voltage of the cascode transistor of the current source of the UCC. The current flow is mainly controlled by $V_{CS}$. This value also sets the overdrive voltage which is critical to the value of random current source transistor threshold voltage mismatch used in design. Both voltages set the DC bias, output impedance of the cascode current source. Thus, it is important the circuit works where both the bias voltages are stable.

The current gain is estimated by dividing the measured total current flow in analog supply voltage to the product of the total number of UCCs in the 802.11ac, 4974, and the reference current, 2.7 µA. This measurement is independent of input signal type and clock frequency.

<figure><img src="image_96.png" /><figcaption>Figure 7.8: Power consumption of the digital circuits, supplied by $VDD_{DIG}$, of the FIR DAC chip at different clock frequencies in the 802.11ac mode and in the 802.11ad modes.</figcaption></figure>

The result as can be seen in Figure 7.7 closely follows the transistor level simulation plot at the end of Chapter 6. The bias supply voltage, $VDD_{BIAS}$, is selected, as expected, at values where the current gain plateaus and the bias voltages are stable.

### 7.2.2 Power Consumption

The total power consumption of the chip in each mode of the FIR DAC chip is obtained by summing the power consumption of the digital circuits, which are supplied by $VDD_{DIG}$, the static current sources,
which are supplied by $VDD_{ANA}$, and the biasing circuits, whose supply is $VDD_{BIAS}$.

The digital part of the power consumption changes with frequency of the clock. In order to find the maximum average power consumption, the chip was run at the highest input bandwidth, up to $f_s/2$, at different clock frequencies. A PRBS input which has a pattern cycle period of $2^{23} - 1$ and a mark density of $1/2$ was employed as an input. The measured power consumption and supply voltages for the two modes of the chip up to 1.4 GHz clock frequency is plotted in Figure 7.8. As explained in sub-section 7.2.3 in this chapter, the digital circuit were run at higher supply voltages after 650 MHz. The value of the digital supply voltage is taken where no significant change in the current consumption of the digital circuits was observed. The circuit was run up to a maximum value of 1.325 V in 1.4 GHz as shown in Figure 7.8.

<table><caption>Table 7.1: Power Consumption of the FIR DAC chip in two modes</caption><thead><tr><th>Part</th><th>Mode</th><th>Current</th><th>Voltage</th><th>Power Consumption</th></tr></thead><tbody><tr><td rowspan="2">Digital Circuits at 600 MHz</td><td>802.11ac</td><td>19.4 mA</td><td>1 V</td><td>19.4 mW</td></tr><tr><td>802.11ad</td><td>16.4 mA</td><td>1 V</td><td>16.4 mW</td></tr><tr><td rowspan="2">Digital Circuits at 1.4 GHz</td><td>802.11ac</td><td>65 mA</td><td>1.325 V</td><td>86.13 mW</td></tr><tr><td>802.11ad</td><td>56 mA</td><td>1.32 V</td><td>73.92 mW</td></tr><tr><td rowspan="2">Analog Circuits</td><td>802.11ac</td><td>14.07 mA</td><td>1.2 V<sup>*</sup></td><td>16.88 mW</td></tr><tr><td>802.11ad</td><td>10.76 mA</td><td>1.2 V</td><td>12.91 mW</td></tr><tr><td rowspan="2">Biasing Circuits</td><td>802.11ac</td><td>51.3 μA<sup>†</sup></td><td>1.2 V</td><td>61.56 μW</td></tr><tr><td>802.11ad</td><td>51.3 μA</td><td>1.2 V</td><td>61.56 μW</td></tr><tr><td rowspan="2">Total Power Consumption at 600 MHz</td><td>802.11ac</td><td></td><td><strong>36.34 mW</strong></td><td></td></tr><tr><td>802.11ad</td><td></td><td><strong>29.37 mW</strong></td><td></td></tr><tr><td rowspan="2">Total Power Consumption at 1.4 GHz</td><td>802.11ac</td><td></td><td><strong>103.07 mW</strong></td><td></td></tr><tr><td>802.11ad</td><td></td><td><strong>86.89 mW</strong></td><td></td></tr></tbody></table>

As expected the power consumption of the digital circuits in the 802.11ad mode is lower owing to the smaller number of UCCs in this mode. It is also true that the consumption increases linearly with frequency: first in the 100 MHz to 600 MHz range for a constant $VDD_{DIG}$ of 1 V, and then beyond 650 MHz. The effect of the small incremental changes in the digital supply voltage beyond 650 MHz is more pronounced in the 802.11ad power consumption.

Similarly, the consumption of the analog current sources is higher in the 802.11ad mode than the 802.11ac mode. It shows a proportional increase, independent of the clock frequency or type of input signal, due to the fact that the number of unit current sources in the 802.11ac mode are approximately 1.3 times those in 802.11ad mode. The results are shown in Table 7.1. Although the power consumption

<footnote>* Actually, ≈ 1.9 V including IR-drop in 50Ω common mode resistor</footnote>

<footnote>† For a 2.7 μA reference current</footnote>
contribution from the biasing circuits is minimal, their power consumption is also tabulated in Table 7.1.
The power consumption of the biasing circuits are the same for the two modes.

The table also contains total power consumptions for both the 802.11ac and the 802.11ad modes.
Two results at two clock frequencies, 600 MHz and 1.4 GHz, are shown to put the change in the digital
supply voltage in perspective.

Finally, when the measured power consumption at 1.4 GHz is compared with the simulated values, it has almost doubled. For example, a total power consumption of 115 mW from a 1 V digital supply was simulated in the 802.11ac mode at 3.52 GHz clock frequency. If the power consumption contribution from the digital circuits was adjusted to 1 V assuming the same current is drawn, as with the 1.325 V supply, at 1.4 GHz, the consumption would still be higher by around 50% compared to the simulated value. Similar comparisons can be made in the 802.11ad mode.

**7.2.3 IEEE 802.11ac Mode**

In this sub-section, sub-GHz clock frequencies were used to test the FIR DAC. The tests with clock
frequency beyond 650 MHz are included in the last part. The data driver circuits of the FIR DAC were
not operating at the GHz speeds for a digital supply voltage of 1 V. This was ascertained by observing
the time domain output signals at near 1 GHz clock frequencies where some of the outputs values was
achieving expected swing albeit at lower update rate during a test with known input sequences. The
simulation results showed functionality up to 3.52 GHz with a PRBS DATA at a digital supply volt-
age of 1 V. The possible source of this problem is increased capacitive loading on the outputs of the
DATA DRIVERS than what was expected during chip simulation. This could have resulted from less
accurate models. Moreover, the transistor flavor used for the implementation of the digital circuits might
not have the expected high frequency functionality. This problem was remedied by increasing the digital
supply voltage up to 1.325 V depending the clock frequency.

Performance of the DAC for a Wideband Modulated DATA

In this mode, the bandwidth of the filter is set to $\frac{f_{CLK}}{22}$. The output of the FIR DAC for a QPSK modulated OFDM 802.11ac signal at a clock frequency of 600 MHz is shown in Figure 7.9. The signal is generated with a frequency plan of 3.52 GHz at the FIR DAC using Matlab®. Thus, the bandwidth of the actual measured signals is approximately 27.3 MHz.

As explained in Chapter 5, the raising quantization noise is canceled by the roll-off in the filter
transition band. The quantization noise is reduced by almost 40 dB for the 600 MHz clock frequency.
Besides, it can be seen that the ripple in the desired band has changed due to the NRZ clocking used in
<figure><img src="image_97.png" /><figcaption>Figure 7.9: Output of the FIR DAC for a ΔΣ input in the 802.11ac mode. It is measured at a clock frequency of 600 MHz.</figcaption></figure>

the FIR DAC. The output of the FIR DAC experience a $\frac{\sin(x)}{x}$ attenuation across the desired band. This introduces a ripple in the passband which degrades the desired spectral flatness. The smaller the desired bandwidth, the smaller the ripple due to the holding nature of the clock. The effect of this for a bandwidth of 27.3 MHz at a 600 MHz clock is about 1.6 dB as can be seen in Figure 7.9.

<figure><img src="image_98.png" /><figcaption>Figure 7.10: Output of the FIR DAC for a thrice oversampled ΔΣ input in the 802.11ac mode. It is measured at a clock frequency of 100 MHz.</figcaption></figure>
To further demonstrate the functionality for modulated signals, the chip is tested with a smaller bandwidth ΔΣ modulator output. The same modulated signal from the first test is oversampled by three at the output of the ΔΣ modulator and frequency translated with the transmitter model shown in Figure 7.5.

The FIR DAC is expected to have a bandwidth of 4.54 MHz output at 100 MHz clock. However, the input is only $\frac{1}{3}$ at 1.51 MHz. The filter attenuates the images as can be seen in Figure 7.10 with the ΔΣ modulator input superimposed on the output. Besides, a power level of -18 dBm is reached with a reference current of 3.2 μA. The input is plotted by DC blocking the Matlab®-generated pattern.

**Characterization as a Filter with PRBS DATA**

The FIR DAC 802.11ac mode was further characterized with a 1-bit PRBS data which has a pattern cycle period of $2^{23} - 1$ and a mark density of $\frac{1}{2}$. The data is generated using a Tektronix® DTG 5334 data timing generator. The test was carried out at different clock frequencies.

<figure><img src="image_99.png" /><figcaption>Figure 7.11: Filtered output at 50 MHz and 600 MHz clock of a PRBS input generated from the DTG</figcaption></figure>

The output for a 600 MHz clock is shown in Figure 7.11. Normally, an attenuation close to 55 dB at $0.6f_s$ is expected. However, due to device mismatch reducing the effect of the small-valued coefficients on the transfer function, the filter attenuates by only 40 dB.

This test can be used to characterize the dynamics of the transfer function of the FIR DAC with clock frequency. A transfer function is defined by its passband ripple, stopband rejection and the width of the transition band. This PRBS input can be used to observe how one or all of these parameters of the transfer function are affected.

The supply voltages and the reference current are fixed at the values shown in Figure 7.2a. The input is data is clocked at a ratio of $\frac{1}{11}$ of the FIR DAC update rate. This odd multiple of the OSR, 22, is selected so that the desired band at $\frac{f_s}{2}$ is always flat across different update rates of the FIR DAC. During
measurement of the output, the resolution bandwidth is scaled proportional to the update rate of the FIR DAC to exclude any reading differences.

<figure><img src="image_100.png" /><figcaption>Figure 7.12: Passband AND Stopband ripple deviations for a PRBS input in the 802.11ac mode</figcaption></figure>

The output PRBS passband and stopband ripples were recorded from 50 MHz to 650 MHz update rates, clock frequencies of the FIR DAC. The change of these ripple from their mean values are shown in Figure 7.12. It can be observed that the passband ripple across a wide range of update rates stay flat whereas the stopband ripple varies by almost 9 dB.

The change in the stopband ripple was caused by slow decrease in the power of the passband when the clock frequency of the FIR DAC increases. The actual stopband power stays constant, only the rejection changed. This can be expected as the static parameters, those that cause change in coefficient values, are constant. The result in Figure 7.12 is then an indication of the failure of the output node of the current sources of the FIR DAC to charge and discharge fast enough to achieve the maximum output swing at each cycle of the clock.

### Characterization of Dynamic Performance

It is customary to use single tones sinusoidal waves for DAC dynamic performance measurement. The signals can be filtered to a degree where the noise floor of the input sinusoid is not higher than the noise floor of the spectrum analyzer. While it is fairly straightforward to do that when the input is multi-bit, it becomes harder to generate 1-bit test signals. This is because a ΔΣ modulator has to be used for converting the multi-bit low noise single-tone signal to a stream of 1-bit input data. The SNR of the 1-bit data depends on the SNR of the modulator used. For our case, only a 3rd-order modulator was used, i.e.
a theoretical maximum SNR of 53 dB. This degrades the output spectrum due to additional mixing of the unneeded tones in the passband of the modulator output.

<figure><img src="image_101.png" /><figcaption>Figure 7.13: The signal used as an input for this experiment, b) The measured plot, and c) SFDR in dBc in the bandwidth of the FIR DAC for a clock frequency of 600 MHz.</figcaption></figure>

A measurement result for a 600 MHz clock shows the SFDR in the bandwidth of the filter, $(\frac{f_s}{2} - \frac{f_s}{22})$ to $(\frac{f_s}{2} + \frac{f_s}{22})$, is approximately around 15 dBc in the first Nyquist zone, and almost 20 dBc in the second. The difference is due to ZOH response. The value of the SFDR across the bandwidth is not different from the one shown for a 32 MHz baseband sinusoid. In Figure 7.13c, SFDR with four different input tones is plotted for a 600 MHz clock frequency. It shows the SFDR further degrades by almost 10 dB across the filter bandwidth.
### 7.2.4 IEEE 802.11ad Mode

In this mode, the bandwidth of the filter was set to $\frac{f_{CLK}}{2}$ by connecting the *SEL* input to ground. The setup from Figure 7.2a is also used here except the analog supply voltage is decreased to 1.6 V. This is because the full-scale output current decreases in this mode and the switch transistors of the current sources in the UCCs has to be protected from drain-to-source over-voltage.

To test the chip as a DAC in the 802.11ad, the 1-bit input data has to be upsampled by two as indicated in the transmitter architecture discussed in Chapter 5. For the high pass FIR DAC circuit implemented in this work, the input has to be mixed and upconverted so that the center of its bandwidth lies at $\frac{f_s}{2}$. For a truly random signal, this process does not change the frequency characteristics of the signal. Hence, a PRBS signal clocked at the update rate of the FIR DAC is employed for characterizing the chip in this mode of operation.

#### Characterization of Channelization of PRBS DATA

A measurement is conducted to show the filtering characteristics in this mode. The measurement result in Figure 7.14 was carried out at 200 MHz clock frequency and the same speed PRBS input data from the data timing generator.

<figure><img src="image_102.png" /><figcaption>Figure 7.14: Filtered output at 200 MHz clock in the 802.11ad mode for a PRBS input generated from the DTG</figcaption></figure>

As can be seen, the broadband response of the FIR DAC in this mode is observed. However, the effect of the $\frac{\sin(x)}{x}$ response of the clock is more pronounced in this mode than in 802.11ac. The passband
ripple increases by around 10 dB due to only the ZOH behavior of the clock.

The large clock feedthrough observed in Figure 7.14 normally should be at a level which is a fraction of the maximum output swing. In this case, it tends to be on the same power as the frequency components in the passband of the FIR DAC.

<figure><img src="image_103.png" /></figure>

Figure 7.15: Filtered output at 200 MHz clock in the 802.11ad mode for a PRBS input generated from the DTG

Tests even at more than 1 GHz clock frequency has been done, the response degrades further with the added problems observed during measurement of the 802.11ac mode. The measured channel powers of the fundamental and the first image output is shown in Figure 7.15. Although the 802.11ad have higher channel power at the same clock frequency than the 802.11ac, given its broadband operation, the performance is limited to a maximum clock frequency of 1.4 GHz. This is observed by increasing the digital supply voltage up to 1.55 V.

<figure><img src="image_104.png" /></figure>

Figure 7.16: Time domain measurement for an input sequence at a clock frequency of 10 MHz.

To mitigate the problem of ZOH, other DAC responses can be used. An RZ-clocked DAC has a flatter response near $f_s/2$ than an NRZ one as discussed in Chapter 4. Unfortunately, this case was not
tested in this implementation.

Another mechanism is to select the output at the first image. One reason for this is that there is less passband ripple at around $1.5f_s$ as the NRZ response of the FIR DAC plateaus at the middle of the first side lobe. Another advantage for selecting this image is to obtain a higher carrier frequency for transmission. However, this comes at a cost. One disadvantage is that output has a large power reduction as the lobes of the $\frac{\sin(x)}{x}$ response of the FIR DAC decrease by more than 10 dB at around $1.5f_s$.

## Characterization of Impulse Response with Known Sequence

The 802.11ad mode unit coefficient is scaled 20 times the 802.11ac mode unit coefficient. For this reason the impulse response of the 802.11ad have bigger sized coefficients, and it is easier to measure even with low reference current values. Since this measurement is strictly about the coefficient sizes, it is measured at lower clock frequencies to avoid effect of high frequency dynamic errors.

The output of the FIR DAC in the 802.11ad mode for a repetitive 34 sample sequence, given as:

$$ Data = \{1, 1, 0, 0, \dots, 0, 0\} \qquad (7.1) $$

is shown in Figure 7.16. The simulated resulted, from Matlab, is shown in red. The measured result is shown in the second plot. The oscilloscope samples this input at 10 GHz. The superimposed plot at the top is obtained by downsampling the measured data points fro 10 GHz to the clock frequency of 10 MHz. As can be seen, the measured data trace almost exactly as the simulated one; they have equal peak-to-peak voltages, and also their periods are the same. This shows that the static part of the FIR DAC is working as expected at least at 10 MHz clock frequency.

<figure><img src="image_105.png" /><figcaption>Figure 7.17: Filtered output at 1 GHz and 1.4 GHz clock frequencies of a PRBS input generated from the DTG</figcaption></figure>
7.2.5 Characterization of the FIR DAC for *f*<sub>CLK</sub> beyond 600 MHz

Tests were carried out with increased digital supply voltage. In the 802.11ac mode, PRBS data was used
to check the output power performance of the chip at 1 GHz and 1.4 GHz. As can be seen in Figure 7.17,
the output swing of the UCC drops fast as the update rate increases. For a 1 GHz clock rate, the power
spectral density is barely crossing -54 dBm/1.1 MHz.

Decreasing the input bandwidth does improve the filtering performance of the chip. In Figure 7.18,
the output power reaches a -44 dBm/3 MHz spectral density across the bandwidth.

<figure><img src="image_106.png" /><figcaption>Figure 7.18: Output of the FIR DAC for a thrice oversampled ΔΣ input in the 802.11ac mode. It is measured at a clock frequency of 2.4 GHz. The input digital pattern *DATA* from the data timing generator is shown in yellow, and the measured output in blue.</figcaption></figure>

Measurement with ΔΣ output as the input *DATA* to the FIR DAC were carried out by increasing the
digital supply voltage further up to 1.55 V. Figure 7.19 shows the channel power, ACPR and alternate
CPR across different clock frequencies for this type of input. We can see that the standard requirement
of 11 dBc ACPR is barely fulfilled almost at all frequencies. However, the alternate CPR requirement of
27 dBc for a 160 MHz channel is only met up to around 1 GHz clock frequency. It must be noted that,
though, the measured channel bandwidth is less than 160 MHz. A maximum channel power of -14 dBm
is obtained at sub-100 MHz clock frequencies.

<figure><img src="image_107.png" /><figcaption>Figure 7.19: Channel power, ACPR, and alternate CPR measurements across different clock frequencies for a ΔΣ output pattern as an input to the FIR DAC in the 802.11ac mode.</figcaption></figure>

The out-of-band profile of the FIR DAC in the 802.11ac mode with the same ΔΣ input data is plotted in Figure 7.20. Two plots of out-of-band attenuation from baseband to $\frac{f_s}{2}$ and from $\frac{f_s}{2}$ to $f_s$ are shown. The third plot indicates the difference between these two plots to quantify the effect of ZOH holding on the out-of-band performance across different clock frequencies. Although its effect on the passband is less significant, it can be seen that the out-of-band profile experiences up to 14 dB difference between the fundamental and image stop bands.

<figure><img src="image_108.png" /><figcaption>Figure 7.20: Out-of-band profile of the fundamental and image stop bands measured at two points for a ΔΣ output signal as an input. The effect of ZOH clocking on these two stop bands is also shown.</figcaption></figure>
### 7.2.6 Comparison with the State of the Art

In this subsection, the performance of the test chip is compared with other digital-to-RF converters targeting low power all-digital wireless transmitters. Some of the interesting differences are tabulated in Table 7.2.

<table><caption>Table 7.2: Comparison with the state of the art in digital-to-RF converters of all-digital transmitters</caption><thead><tr><th>REF.</th><th>Tech.</th><th>Type of DAC</th><th>Mode</th><th>Max. BW [MHz]</th><th>Max. f<sub>s</sub> [MHz]</th><th>Max. f<sub>out</sub> [MHz]</th><th>Max. P<sub>out</sub> [dBm]</th><th>P<sub>Cons</sub><sup>‡</sup> [mW]</th></tr></thead><tbody><tr><td>[Ala+14]</td><td>65nm CMOS</td><td>RF DAC</td><td>—</td><td>154.1</td><td>3500</td><td>2400</td><td>22.8</td><td>—</td></tr><tr><td>[Tal+08]</td><td>0.25μm CMOS</td><td>FIR RF DAC</td><td>—</td><td>15</td><td>250</td><td>1062</td><td>-5.4</td><td>122</td></tr><tr><td rowspan="2">[McC+15]</td><td rowspan="2">130nm SiGe CMOS</td><td rowspan="2">TI ΔΣ RF DAC</td><td>BP</td><td rowspan="2">50</td><td rowspan="2">2000</td><td>510</td><td>-4.5</td><td rowspan="2">55</td></tr><tr><td>HP</td><td>990</td><td>-7.5</td></tr><tr><td rowspan="2">This Work</td><td rowspan="2">28nm CMOS FDSOI</td><td rowspan="2">HP FIR DAC</td><td>11ac</td><td>136</td><td>3000</td><td>1500</td><td>3.93</td><td>103.07<sup>§</sup></td></tr><tr><td>11ad</td><td>700</td><td>1400</td><td>700</td><td>1.61</td><td>86.89<sup>§</sup></td></tr></tbody></table>

It can be seen that, the work outperforms in processing wideband signals, up to 700 MHz in the 802.11ad mode. This bandwidth is measured with a clock frequency of 1.4 GHz. In the 802.11ac mode, higher clock frequency, a maximum of 3 GHz, are reached by increasing the digital supply voltage. However, due to the medium bandwidth targeted with this mode, the input signal bandwidth is limited to 136 MHz.

The advantage of the high pass FIR DAC structure over the LPF and BPF structures is its ability to achieve higher carrier frequency for the same clock speed. A maximum output carrier frequency of 1.5 GHz in the 802.11ac mode and 700 MHz in the 802.11ad mode.

The output power is reported for the full-scale current at a 50 Ω output load network. The output swing is improved compared with what is reported in the other works with an exception to the value reported in [Ala+14] where a combining output network is used to reach a peak output power of 22.8 dBm.

Although this work is expected to take advantage of technology scaling to lower the power consumption, it suffers from increased number of UCCs. This is mainly due to the targeted out-of-band noise profile of -60 dBr required up to 4974 UCCs. The power consumption values in the table are at a clock frequency of 1.4 GHz. The power consumption for measurements with a wideband OFDM input signal

<footnote>§ $f_{CLK} = 1.4GHz$ ‡ $P_{Cons}$ = Total power consumption</footnote>
tend to plateau when the clock frequency increases to its maximum value of 3 GHz.

<table><caption>Table 7.3: Performance summary of the configurable FIR DAC</caption><thead><tr><th>Parameter</th><th>802.11ac mode</th><th>802.11ad mode</th></tr></thead><tbody><tr><td>Bandwidth</td><td>f<sub>s</sub>/22</td><td>f<sub>s</sub>/2</td></tr><tr><td>Maximum Output Carrier Frequency</td><td>1500 MHz</td><td>700 MHz</td></tr><tr><td>Maximum Measured Input BW</td><td>136 MHz</td><td>700 MHz</td></tr><tr><td>Full-Scale Output Current, I<sub>REF</sub> = 2.7µA</td><td>14.07 mA</td><td>10.76 mA</td></tr><tr><td>Power Consumption at 1.4 GHz</td><td>103.07 mW</td><td>86.89 mW</td></tr><tr><td>Total Number of UCCs</td><td>4974</td><td>3804</td></tr><tr><td>Clock Speeds, f<sub>s</sub></td><td>10MHz ≤ f<sub>s</sub> ≤ 3GHz</td><td>10MHz ≤ f<sub>s</sub> ≤ 1.4GHz</td></tr><tr><td>Supply Voltages</td><td>VDD<sub>DIG</sub> VDD<sub>BIAS</sub> VDD<sub>ANA</sub><br>0.6 to 1.55 V 1.2 V 1.2 V</td><td></td></tr><tr><td>Hardware Sharing</td><td colspan="2">98% 802.11ad UCCs used in 802.11ac</td></tr><tr><td>Maximum Stopband Rejection</td><td colspan="2">55 dB in 802.11ac mode</td></tr><tr><td>Output Load Network</td><td colspan="2">50 Ω differential probes</td></tr><tr><td>Clock and Data Input</td><td colspan="2">Single-ended, 50 Ω to ground</td></tr><tr><td>Die Packaging</td><td colspan="2">QFN40 plastic package</td></tr><tr><td>Active Circuit Area</td><td colspan="2">0.83 mm<sup>2</sup></td></tr><tr><td>Transistors Used</td><td colspan="2">Regular V<sub>th</sub></td></tr><tr><td>Technology</td><td colspan="2">28nm CMOS FDSOI</td></tr></tbody></table>

## 7.3 Conclusions

A summary of the measurement results of the FIR DAC chip is presented in Table 7.3. The maximum input bandwidth for 802.11ac mode is at a clock frequency of 1.4 GHz for a PRBS input shown in Figure 7.17b. It would have strengthened the claim to present EVM results, but it has not been possible to carry out these measurements so far. For the 802.11ad, the maximum input bandwidth is at 600 MHz clock frequency. Nonetheless, the circuit can operate in the 802.11ac mode up to clock speeds of 2.4 GHz starting at a 1.325 V digital supply voltage. Further tests at higher supply voltages were not carried out at the moment. The chip has also functionality up to 1.4 GHz in the 802.11ad starting at a digital supply voltage of 1.325 V.

In the 802.11ac mode, results are obtained at digital supply voltage as low as 0.6 V. As expected,
this happens when the data and clock signal levels are scaled to the corresponding *VDD<sub>DIG</sub>* level and at
frequencies below 100 MHz. Further tests with varying digital supply voltage were not possible at this
moment.

One observation common to all cases of measurement was the robustness of the circuit to delay
difference between the *CLOCK* and *DATA* signals. The delay could be varied up to 5 ns with the data
timing generator. The circuit was tested with a ΔΣ modulator output signal where the input *DATA* was
delayed, sweepingly, from 0 ns upto 1/2f_s. The circuit was able to deliver expected output even when the
input pattern was run for a fixed number of loops. The reason for this is the robustness of the digital
delay line against set-up time errors.

There are many conclusions that can be drawn for the measurements presented in this chapter. De-
spite the fact that the measurement results differ from the theoretically expected results, the validity of
the configurable FIR DAC concept is shown. The concept of digitally switching unit current sources and
summing them in analog to implement a DAC with different filtering behavior is validated.

While the static part of the FIR DAC circuit has worked reliably. The expected parametric results in
the dynamic parts of the circuit were not obtained. Common to both modes is the failure in high clock
frequency. The contribution of technology maturity is not to be underestimated, but there are also some
improvements that should have been made in circuit implementation that could have decreased the noise
level observed in the single-tone measurements results.

The next chapter will include some recommendations for improving the performance of configurable,
high speed, high resolution FIR DACs.
# Conclusions and Future Directions

## Conclusions

This work provides theoretical analysis, simulation-based validation of FIR DAC based circuits and transmitter architectures. Besides, a prototype chip is measured to validate the use of FIR DAC for multi-standard transmitter implementation. The circuit is tested to work up to a clock frequency of 3 GHz in the medium bandwidth mode while consuming a power consumption of 108.9 mW. It is also characterized in the wide bandwidth mode up to a clock frequency of 1.4 GHz while consuming 86.89 mW of power.

## Future Directions

Some recommendations are listed below to improve the multi-mode FIR DAC circuit to achieve a state-of-the-art performance at multi-GHz digital-to-RF conversion.

* As discussed in Chapter 6, the data drivers were placed on one-side of the UCC array. A discussion was included on the possible bandwidth limitation that could result due to parasitic loading. To solve this problem, another set of data driver can be inserted in the middle of the UCC array. There will not be a significant increase in power consumption as the load is divided. Similar technique can be followed for the clock. Additional set of driver can be inserted in the *CENTER* of the UCC array to balance the delay between two UCC at each end of the clock line.

* As mentioned in the Chapter 7, the output of the HP FIR DAC suffered from the ZOH nature of the clocking used. To improve this, the FIR DAC UCC can be redesigned for an RZ implementation, or better yet other types of implementation which have a peak at around $\frac{f_s}{2}$.

* The FIR DAC circuit area can be improved by designing a UCC which exploits the symmetry that exists in a linear-phase FIR filter impulse response. The obvious method is to use some decoding logic to reuse the same UCC. The way this works is that the UCC is turned-off when the two coefficients have opposite data values and works normally for the other two cases. To turn-off the
UCC, the current source or the two switches can be turned-off. Thus, there will be two control
signals for each tap. However, this can affect the speed that can be reached and, more importantly,
distortion may be caused due to mismatches on the timing of turn-off and operation of UCC.

To decrease this distortion, an easier way is to redesign the UCC to have three switches to smoothly transfer $I_{UCC}$ into two output and one additional redundant branches for the possible combination values of two taps i.e. -2, 0, and 2. However, still two control signals are needed.

* The clock and data signals are on metal layers four and ten respectively. This prevents cross-talk. However, to separate them, the placement method has to change. A new placement which maintains the strengths of the pseudo-double common centroid placement method, but separates the digital and analog grounds, crossing of digital signals among other things can bring improvement.

* There are works at multi-GHz frequencies that embedded filtering in a DAC. However, the FIR DAC structure is yet to be reported at those frequencies. Had there been one, it would have been a good reference for comparing a 1-bit, *N*-tap digital-to-RF processor performance against a traditional *L*-bit, 1-tap DAC. Transistor level simulation of the work reported in [GFK15] showed promising results. A demonstrator chip of the system-level findings in that paper could provide the reference work to appraise the strengths and weakness of the FIR DAC approach.

* A final recommendation is on the general FIR DAC structure. It would be interesting to quantitatively compare the three structures presented in Chapter 4: *L*-bit, *N*-tap; 1-bit, *N*-tap; and *L*-bit, 1-tap.
# Appendix

## 1 Transmitter Chain Simulation in Matlab

The matlab code given here is used for simulation of the transmitter chain in Chapter five. The function is also used improved for generating the patterns used in the test of the prototype FIR DAC chip in Chapter seven.

There may be some codes here and there that are mistakenly commented or some values which were chosen for some particular frequency plan, but generally the code can be easily improved to be used for a DSP of transmitter chain simulation.

Unfortunately, the other codes that has been written for each block of the transmitter are not included here. Hopefully, they will available somewhere sometime.

### .1.1 IEEE 802.11ac Transmitter Baseband

1. `function [SigAnalogOut, ACPR, SpecFlat] = TxModel_THESIS(SigType, Fs, Order, NTFGain, QBits, topo, Coeff)`
2. `% function [SigAnalogOut] = TxModel(SigType, Fs, Order, NTFGain, QBits, topo, Coeff)`
3. `%`
4. `% Test case - [SigAnalogOut, SigDelSigOut] = TxModelWiFi(real(SigWiFi)/max(real(SigWiFi)), [], 8)`
5. `% Modified to [SigAnalogOut, ACPR, SpecFlat] = TxModelWiFi(real(SigWiFi), [], 160e6, 11, 1/(11*8))`
6. `% For EVM simulation: [SigAnalogOut, ACPR, SpecFlat] = TxModelWiFi([], [], 160e6, 11, 1/(11*8))`
7. `% Generate a Signal with the input characteristics`
8. `% SigIn = TestSignals(SigType, 50, 1, Fsig, Fs);`
9. `% Fsig = [];` % was useful when generating input signal within this function for single-tone
10. `%% percent useful when generating input signal within this function for single-tone`
11. `close all;`
12. `Fs_Original = Fs;`
13. `Fs = 320e6;` % After HBF, Frequency of operation is 320MHz mode
14. `OSR = 11;`
15. `OSRDS = 11*Fs/(1*Fs_Original);` % Fixed for Fs = 320MHz * 11 = 2*1.76GHz, WiGig Fs
16. `GrpDelay_DS = 5;` % 6 for optimized CRFB, 170 for CIFB and others
17. `FIRDLY = grpdelay(Coeff);`
18. `FIRDLY = ceil(max(FIRDLY(1:22)));`
19. `N_OFDM = 12;` % OFDM BITS = 3 + 0.5*log2(512/3*(M-1)), M is constellation
20.
21 ~~% Scale Input to amplitude of maximum delta-sigma SNR~~
22 AmpFS = 0.9; % what if the quantizer full scale were 2, 0, -2?

23 SigInReal = (real(SigType).*AmpFS)/max(abs(SigType));

24 SigInImag = (imag(SigType).*AmpFS)/max(abs(SigType));

25 % SigInReal = real(SigType);

26 % SigInImag = imag(SigType);

27 ~~% Quantize to N_OFDM bits~~

28 SigInRealQuant = round(SigInReal/max(abs(SigInReal)) * (2^(N_OFDM)-1));

29 SigInRealNBit = SigInRealQuant*(max(abs(SigInReal))/max(abs(SigInRealQuant)));

30 SigInImagQuant = round(SigInImag/max(abs(SigInImag)) * (2^(N_OFDM)-1));

31 SigInImagNBit = SigInImagQuant*(max(abs(SigInImag))/max(abs(SigInImagQuant)));

32 ~~%~~

33

34 ~~% Interpolation for 20MHz, 40MHz and 80MHz using half-band filters~~
35 if ismember(Fs_Original, [20e6, 40e6, 80e6, 160e6])

36 [SigInRealHF, SigInImagHF] = InterpolateTo320(SigInRealNBit, Fs_Original, SigInImagNBit);

37 % [SigInRealHF, SigInImagHF] = InterpolateTo320(SigInReal, Fs_Original, SigInImag); end

39 ~~% Quantize to N_OFDM bits~~

40 % [SigInRealHF,B] = interp(SigInRealHF,OSR);

41 % BNor = B/sum(B);

42 % SigInRealHF = filter(BNor,1,[SigInRealHF,zeros(1,grpdelay(BNor))]);

43 % SigInRealHF = SigInRealHF(grpdelay(BNor)+1:end);

44 SigInRealQuant = round(SigInRealHF/max(abs(SigInRealHF)) * (2^(N_OFDM)-1));

45 SigInRealHFNBit = SigInRealQuant*(max(abs(SigInRealHF))/max(abs(SigInRealQuant)));

46 ~~% Quantize to N_OFDM bits~~

47 SigInImagQuant = round(SigInImagHF/max(abs(SigInImagHF)) * (2^(N_OFDM)-1));

48 SigInImagHFNBit = SigInImagQuant*(max(abs(SigInImagHF))/max(abs(SigInImagQuant)));

49 ~~%~~

50 ~~%~~

51 ~~% Interpolate~~

52 % [SigShapedR, ~] = OverSample(SigInReal, OSR); % Zero-Order-Hold

53 ZOH = ones(1,OSR);

54 SigInRealUP = upsample(SigInRealHFNBit,OSR);

55 % SigInRealUP = upsample(SigInRealHF,OSR);

56 SigShapedR = filter(ZOH,1,[SigInRealUP,zeros(1,ceil((OSR-1)/2))]);
% Zero-Order-Hold delay compensation

57 SigShapedR = SigShapedR(ceil((OSR-1)/2)+1:end);

58 ~~%~~

59 ~~% Delta Sigma Modulator with Delay Compensation~~

60 FuncDelSig.OSR = OSRDS; % OSR decreases -> SNR decreases, but -> delta-sigma NTF curve is f
61 FuncDelSig.Fs = Fs * OSR; FuncDelSig.Name='DeltaSigma'; FuncDelSig.Order = Order; FuncDelSig.topo
62 SigShapedR = [SigShapedR, zeros(1,GrpDelay_DS)];
63 [SigDelSigOutR] = DeltaSigma3rdOrder(SigShapedR, FuncDelSig);
64 SigDelSigOutR = SigDelSigOutR(GrpDelay_DS+1:end);
65 PlotFrequencyResponse(SigDelSigOutR, 3.52e9);
66 %% Semidigital FIR DAC
67 SigAnalogOutR = filter(Coeff, 1, [SigDelSigOutR, zeros(1,FIRDLY)]);
68 SigAnalogOutR = SigAnalogOutR(FIRDLY+1:end);
69 %% For Q-part
70 % if isempty(SigType)
71 % [SigShapedQ, ~] = OverSample(SigInImag, OSR); % Zero-Order-Hold
72 %% ZOH phase compensation ZOH = [1, 1, 1, ..., OSR times, 1]; grpdelay = (osr-1)/2;
73 SigInImagUP = upsample(SigInImagHFNBit, OSR);
74 % SigInImagUP = upsample(SigInImagHF, OSR);
75 SigShapedQ = filter(ZOH, 1, [SigInImagUP, zeros(1,ceil((OSR-1)/2))]);
76 %% Zero-Order-Hold delay compensation
77 SigShapedQ = SigShapedQ(ceil((OSR-1)/2)+1:end);
78 %% Delta Sigma Modulator with Delay Compensation
79 SigShapedQ = [SigShapedQ, zeros(1,GrpDelay_DS)];
80 [SigDelSigOutQ] = DeltaSigma3rdOrder(SigShapedQ, FuncDelSig);
81 SigDelSigOutQ = SigDelSigOutQ(GrpDelay_DS+1:end);
82 PlotFrequencyResponse(SigDelSigOutQ, 3.52e9);
83 %%
84 SigAnalogOutQ = filter(Coeff, 1, [SigDelSigOutQ, zeros(1,FIRDLY)]);
85 SigAnalogOutQ = SigAnalogOutQ(FIRDLY+1:end);
86 %% Scale Back to Original Magnitudes
87 SigAnalogOut.R = (SigAnalogOutR./AmpFS).*max(abs(SigType));
88 SigAnalogOut.Q = (SigAnalogOutQ./AmpFS).*max(abs(SigType));
89 %% SigAnalogOut.R = SigAnalogOutR;
90 %% SigAnalogOut.Q = SigAnalogOutQ;
91 %% ACPR simulation
92 [ACPR.QInter, ~, ~] = ACPRTest(SigShapedQ, ACPRPara);
93 [ACPR.QDelSig, ~, ~] = ACPRTest(SigDelSigOutQ, ACPRPara);
94 [ACPR.QSemi, ~, ~] = ACPRTest(SigAnalogOut.Q, ACPRPara);
95 %% SPECTRAL FLATNESS
96 [SpecFlat.Q] = SpectralFlatnessTxWiFi(SigAnalogOutQ, Fs_Original, OSR);
97 % else
98 %% ACPR Simulation Input Data
99 [ACPR.RInter, MainChPowerR, AdjChPowerR] = ACPRTest(SigShapedR, ACPRPara); %#ok
100 [ACPR.RDelSig, MainChPowerR, AdjChPowerR] = ACPRTest(SigDelSigOutR, ACPRPara); %#ok
101 [ACPR.RSemi, MainChPowerR, AdjChPowerR] = ACPRTest(SigAnalogOut.R, ACPRPara); %#ok
101 %%

102 [SpecFlat.R] = SpectralFlatnessTxWiFi(SigAnalogOutR, Fs_Original, OSR);

103 %% Output of three blocks on the same plot

104 % ScaleTXPower(SigAnalogOut.R, Fs_Original); % Includes out-of-band noise profile

105 close all;

106 figure(1);

107 dBFactor = 30; % +30 for dBm

108 FreqFactor = 1e6; % 1e6 for /MHz

109 % dBFactor = 0; % +0 for dB

110 % FreqFactor = 1; % 1 for Hz

111 [Pxx, Fxx] = pwelch(SigDelSigOutR, rectwin(length(SigDelSigOutR)), [], length(SigDelSigOutR), Fs*OSR,

112 plot(Fxx, 10*log10(Pxx.*FreqFactor)+dBFactor, 'answidt', 1.5, 'anscolor', [.1 .1 .9])

113 hold on;

114 [Pxx, Fxx] = pwelch(SigShapedR, rectwin(length(SigShapedR)), [], length(SigShapedR), Fs*OSR, 'onesided'

115 plot(Fxx, 10*log10(Pxx.*FreqFactor)+dBFactor, 'answidt', 1.5, 'anscolor', [.1 .9 .1])

116 hold on;

117 [Pxx, Fxx] = pwelch(SigAnalogOut.R, rectwin(length(SigAnalogOut.R)), [], length(SigAnalogOut.R), Fs*OSR,

118 % PxxMax(1) = max(10*log10(Pxx(length(Fxx)/2 + 1 : length(Fxx)/2 + length(Pxx)/(2*OSR)).*FreqFactor;
% For centered plotting ... max for transmit mask taken over some Fbb samples range in dBm/MHz

119 % PxxMax(1) = max(10*log10(Pxx(1:length(Fxx)/(2*OSR))));
% For twosided plotting

120 PxxMax(1) = max(10*log10(Pxx(1 : length(Fxx)/2 + length(Pxx)/(2*OSR)).*FreqFactor)+dBFactor);
% For onesided

121 % if gt(PxxMax(1),1) || lt(PxxMax(1),-1)
% Scale power to set peak dB/Hz or dBm/MHz at 0

122 % Pxx = ((10^(-1*dBFactor/10))/(FreqFactor*max(Pxx))).*Pxx;

123 % PxxMax(1) = max(10*log10(Pxx(length(Fxx)/2 + 1 : length(Fxx)/2 + length(Pxx)/(2*OSR)).*FreqFactor;
124 % end

125 %% Transmit Mask

126 if le(Fs_Original, 160e6)

127 % TxMaskVector = [0, 9e6, 11e6, 20e6, 30e6, Fs-30e6, Fs-20e6, Fs-11e6, Fs-9e6, Fs; PxxMax(1),
PxxMax(1)]; %ieee802.11ac-20MHz Mask ... for twosided plotting

128 TxMaskVector = [0, (Fs_Original/(2*1e6) - 1)*1e6, (Fs_Original/(2*1e6) + 1)*1e6, Fs_Original,
129 plot(TxMaskVector(1,:), TxMaskVector(2,:), 'answidt', 4, 'anscolor', [.6 .1 .4]);

130 axis([0 1.76e9 PxxMax(1)-130 PxxMax(1)+10])

131 % PlotFrequencyResponse(SigAnalogOut, OSR*Fs);

132 end

133xlabel('Sampling_frequency');

134 if FreqFactor==1e6 && dBFactor==30

135 ylabel('PSD_in_dBm/MHz');

136 elsif FreqFactor==1 && dBFactor==30
137 ylabel('PSD_in_dBm/Hz');

138 else

139 ylabel('PSD_in_dB/Hz');

140 end

141 title('PSD_of_transmitted_signal_at Output_of_the_WiFi_Tx');

142 % legend('Delta-Sigma', 'Interpolation Filter', 'FIR DAC', 'Location', 'NorthEastOutside');

143 legend('Delta-Sigma', 'FIR DAC', 'Transmit Mask', 'Location', 'NorthEast');

144 end

## 1.2 IEEE 802.11ad Transmitter Baseband

The 802.11ad transmitter is has a simple architecture with only an oversampling by two DSP block
before the FIR DAC. Therefore, it is not included.
## .2 EVM Simulation

### .2.1 Code for EVM Simulation of 802.11ac

1 function [ SigRx, EVM, MER ] = EVMWiFi_THESIS( Coeff, Fs)
2 %EVMWiFi Simulates an OFDM system in WiFi IEEE802.11ac standard
3 % Some blocks are not included to simplify the OFDM system for easy EVM estimation in the WiFi T
4 % All channel bandwidths are can be simulated by choosing the right Fs.
5 %
6 %% Constants variables
7 SEL = 1+log2(Fs/20e6);
8 OSR = 11 * 320e6/Fs; % oversampling by 11 in ZOH and x320/Fs in HBF
9 NcpALL = [16,32,64,128]; % Guard Interval 1/4*3.2us = 0.8us*Nsc/3.2us= or 0.8us*Fs = S
10 NscALL = [64,128,256,512]; % Total number of subcarriers for Fs
11 % NdscALL = [56,114,242,484]; % Number of data and pilot subcarriers
12 NdscALL = [56,114,242,468];
13 Ncp = NcpALL(SEL);
14 Ndsc = NdscALL(SEL);
15 Nsc = NscALL(SEL);
16 N = 16; % 16-PSK/16-QAM with N = 16
17 Nsym = 1; % Number of Symbols
18 Nsam = Ndsc*Nsym; % Random data for simulation = integer multiple of Ndsc
19 %% Create Signals for each block output
20 SigZP = zeros(Nsc,Nsym); % Zero padding Nsc-Ndsc = subcarriers
21 SigIFFT = zeros(Nsc, Nsym);
22 SigFFT = zeros(Nsc, Nsym);
23 SigGI = zeros(Nsc+Ncp, Nsym);
24 SigOFDMRx = zeros(Nsc+Ncp, Nsym);
25 SigGIRx = zeros(Nsc, Nsym);
26 SigRx = zeros(Ndsc, Nsym);
27 SigRf = zeros(OSR*(Nsc+Ncp), Nsym);
28 %% Constellation Mapper
29 PhOff = pi/4;
30 % hModulator = comm.PSKModulator(N, 'PhaseOffset', PhOff, 'BitInput', false);
31 hModulator = commRectangularQAMModulator(N, 'PhaseOffset', PhOff, 'BitInput', false);
32 SigRand = randi([0,N-1], Nsym, 1);
33 SigIdeal = step(hModulator, transpose(linspace(0,N-1, N)));
34 SigMapped = step(hModulator, SigRand); % Output of constellation mapper
35 %% Serial to Parallel Converter
36 SigMapped = reshape(SigMapped, Ndsc, Nsym);
37 for i=1:Nsym
38 % map the data to the data subcarriers
```c
39 if eq(SEL, 1)
40     SigZP(3:30, i) = SigMapped(1:28, i);      % position of pilot and data subcarriers is not
41     SigZP(35:62, i) = SigMapped(29:56, i);
42 else if eq(SEL, 2)
43     SigZP(4:60, i) = SigMapped(1:57, i);       % position of pilot and data subcarriers is not
44     SigZP(69:125, i) = SigMapped(58:114, i);
45 else if eq(SEL, 3)
46     SigZP(4:124, i) = SigMapped(1:121, i);
% position of pilot and data subcarriers is not exact
47     SigZP(133:253, i) = SigMapped(122:242, i);
48 else
49     % position of pilot and data subcarriers is exact for the 160 MHz
50     % mode
51     SigZP(5:23, i) = SigMapped(1:19, i); SigZP(24, i) = 1;
52     SigZP(25:51, i) = SigMapped(20:46, i); SigZP(52, i) = 1;
53     SigZP(53:87, i) = SigMapped(47:81, i); SigZP(88, i) = 1;
54     SigZP(89:115, i) = SigMapped(82:108, i); SigZP(116, i) = -1;
55     SigZP(117:125, i) = SigMapped(109:117, i); % DC = 3sc
56     SigZP(129:137, i) = SigMapped(118:126, i); SigZP(138, i) = -1;
57     SigZP(139:165, i) = SigMapped(127:153, i); SigZP(166, i) = 1;
58     SigZP(167:201, i) = SigMapped(154:188, i); SigZP(202, i) = 1;
59     SigZP(203:229, i) = SigMapped(189:215, i); SigZP(230, i) = 1;
60     SigZP(231:249, i) = SigMapped(216:234, i); % DC = 11sc
61     SigZP(261:279, i) = SigMapped(235:253, i); SigZP(280, i) = 1;
62     SigZP(282:308, i) = SigMapped(254:280, i); SigZP(309, i) = 1;
63     SigZP(310:344, i) = SigMapped(281:315, i); SigZP(345, i) = 1;
64     SigZP(346:372, i) = SigMapped(316:342, i); SigZP(373, i) = -1;
65     SigZP(374:382, i) = SigMapped(343:351, i); % DC = 3sc
66     SigZP(386:394, i) = SigMapped(352:360, i); SigZP(395, i) = -1;
67     SigZP(397:423, i) = SigMapped(361:387, i); SigZP(424, i) = 1;
68     SigZP(425:459, i) = SigMapped(388:422, i); SigZP(460, i) = 1;
69     SigZP(461:487, i) = SigMapped(423:449, i); SigZP(488, i) = 1;
70     SigZP(489:507, i) = SigMapped(450:468, i);
71 end
72 % IFFT
73 SigIFFT(:,i) = Nsc.*ifft(SigZP(:,i), Nsc);
74 % Guard Interval (GI) Insertion using Cyclic Prefix
75 SigGI(:,i) = [SigIFFT(end-(Ncp-1):end, i); SigIFFT(1:end, i)];
76 % Call WiFi Tx Model
77 [SigAnalogOut] = TxModel(transpose(SigGI(:,i)), Fs, 3, 1.6, 1, 'CRFB', Coeff);
78 SigRf(:,i) = SigAnalogOut.R + 1j.*SigAnalogOut.Q; % create the complex output
```
% Downsample

SigDn = downsample(SigRf(:,i), OSR); % OSR for Fs mode

SigOFDMRx(:,i) = SigDn;

%% Gl Removal

SigGIRx(:,i) = SigOFDMRx(Ncp+1:Nsc+Ncp,i);

%% FFT

SigFFT(:,i) = 1/Nsc .* fft(SigGIRx(:,i), Nsc);

%% Removal of zero-padding

if eq(SEL,1)

SigRx(1:28,i) = SigFFT(3:30,i);

SigRx(29:56,i) = SigFFT(35:62,i);

elif eq(SEL,2)

SigRx(1:57,i) = SigFFT(4:60,i);

SigRx(58:114,i) = SigFFT(69:125,i);

elif eq(SEL,3)

SigRx(1:121,i) = SigFFT(4:124,i);

SigRx(122:242,i) = SigFFT(133:253,i);

else

% Exact Position of pilot and data subcarriers for the 160 MHz mode

SigRx(1:19,i) = SigFFT(5:23,i);

SigRx(20:46,i) = SigFFT(25:51,i);

SigRx(47:81,i) = SigFFT(53:87,i);

SigRx(82:108,i) = SigFFT(89:115,i);

SigRx(109:117,i) = SigFFT(117:125,i);

SigRx(118:126,i) = SigFFT(129:137,i);

SigRx(127:153,i) = SigFFT(139:165,i);

SigRx(154:188,i) = SigFFT(167:201,i);

SigRx(189:215,i) = SigFFT(203:229,i);

SigRx(216:234,i) = SigFFT(231:249,i);

SigRx(235:253,i) = SigFFT(261:279,i);

SigRx(254:280,i) = SigFFT(282:308,i);

SigRx(281:315,i) = SigFFT(310:344,i);

SigRx(316:342,i) = SigFFT(346:372,i);

SigRx(343:351,i) = SigFFT(374:382,i);

SigRx(352:360,i) = SigFFT(386:394,i);

SigRx(361:387,i) = SigFFT(397:423,i);

SigRx(388:422,i) = SigFFT(425:459,i);

SigRx(423:449,i) = SigFFT(461:487,i);

SigRx(450:468,i) = SigFFT(489:507,i);

end

119 end
120 % Parallel to Serial Converter

121 SigRx = transpose(SigRx);

122 SigMapped = transpose(SigMapped);

123 % Scatterplot and EVM Estimation

124 close all;

125 Pavg = sum( (real(SigIdeal(:))).^2 + (imag(SigIdeal(:))).^2 )/N;

% Average power of ideal constellation

126 Vavg = sum( sqrt((real(SigIdeal(:))).^2 + (imag(SigIdeal(:))).^2) )/N;

% Average Amplitude of ideal constellation

127 for k=1:Nsym

128 % EVM Calculation

129 Ierr = real(SigRx(k,:)) - real(SigMapped(k,:));

130 Qerr = imag(SigRx(k,:)) - imag(SigMapped(k,:));

131 Verr = sumqticksqrt(Ierr.^2 + Qerr.^2))/Ndc;

% average Amplitude of error constellation

132 EVM.SyV(k) = 20*log10( Verr / Vavg );

% EVM

133 % EVM.SyLin(k) = sqrt( Verr / Vavg );

134 % Modulation Error Ratio

135 Perr = sum(Ierr.^2 + Qerr.^2);

% power of error constellation

136 Psig = sum((real(SigMapped(k,:))).^2 + (imag(SigMapped(k,:))).^2 );

% power of signal constellation

137 MER.SydB(k) = 10*log10( Psig / Perr );

% MER(k) = 10*log10(Psig/Perr)

138 % Plotting per symbol

139 scatter(real(SigRx(k,:)), imag(SigRx(k,:)), 2, [.2 .6 .9], 'answidwidth', 4);

% downsampled

140 hold on;

141 scatter(real(SigMapped(k,:)), imag(SigMapped(k,:)), 3, [.2 .1 0.1], 'answidwidth', 5);

% ideal

142 hold on;

143 end

144 for n=1:Ndsc

145 % Relative Constellation Error (RCE) calculation ... EVM per subcarrier

146 Ierr = real(SigRx(:,n)) - real(SigMapped(:,n));

147 Qerr = imag(SigRx(:,n)) - imag(SigMapped(:,n));

148 Perr = sum(Ierr.^2 + Qerr.^2)/Nsym;

149 EVM.ScdB(n) = 10*log10( Perr / Pavg );

150 end

151 % EVM.SyLinAver = 20*log10(mean(EVM.SyLin));
152 EVM. SydBVolAvg = mean(EVM. SyV);

% average of EVM of symbols

153 MER. Avg = mean(MER. SydB);

% Mean of Modulation Error Ratio

154 EVM. ScdBAvg = mean(EVM. ScdB);

% average of EVM of subcarriers

155

156 %% Spectral Flatness

157 if eq(SEL,1)

158 Eavg = mean(mean(abs(SigRx(:,1:16)).^2));

159 end

160 end
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# List of Publications

## Journal

* F. T. Gebreyohannes, A. Frappe, and A. Kaiser, "A Configurable Transmitter Architecture for IEEE 802.11ac and 802.11ad Standards," *IEEE Trans. Circuits Syst. II Express Briefs*, vol. 63, no. 1, pp. 9-13, Jan. 2016.

## Conferences

* F. T. Gebreyohannes, A. Frappe, and A. Kaiser, "Semi-digital FIR DAC for low power single carrier IEEE 802.11ad 60 GHz transmitter," in *New Circuits and Systems Conference (NEW-CAS), 2015 IEEE 13th International*, 2015, pp. 1-4.

* F. T. Gebreyohannes, A. Frappe, and A. Kaiser, "Multi-standard Semi-digital FIR DAC: A Design Procedure," in *2016 IEEE MTT-S International Wireless Symposium (IWS)*, Mar. 2016, pp. 1-4.

* "Next Generation of Wireless Access: Disruptive Transceivers," in 2016 IEEE MTT-S International Wireless Symposium (IWS) Workshop (co-author of one of the workshop papers)

## Lecture Presentations

* "A Configurable Transmitter Architecture for IEEE 802.11ac and 802.11ad Standards," in *IEEE International Symposium of Circuits and Systems (ISCAS)*, Montreal, 2016

* "Semi-digital FIR DAC for Low Power Single Carrier IEEE 802.11ad 60GHz Transmitter," in *Journées Nationales du Réseau Doctoral en Micro-nanoélectronique (JNRDM)*, Bordeaux, 2015

## Master's Thesis

* "Design of Ultra-Low Power Wake-Up Receiver in 130nm CMOS Technology," Department of Electrical Engineering, Linkoping University, Sweden, 2012
Abstract en Français

La prolifération des standards de communication sans fil, spécifiques aux applications, a abouti à la mul-
tiplication des standards et des dispositifs pour un seul scénario utilisateur daujourd'hui. Par conséquent,
le domaine de la recherche dans les multi-standard, les systèmes multi-bandes, architectures, et circuits a
été un thème populaire. La perspective est d'avoir des dispositifs qui peuvent être adaptés aux différents
réseaux tout en offrant d'excellentes fonctionnalités sur les différentes technologies d'accès radio.

Les architectures d'émetteurs configurables ciblant les cas d'utilisation complémentaires des multistan-
dards multi-Gb/s WiFi-WiGig ont été étudiés. Des approches novatrices basées sur des DAC FIR semi-
numériques configurables à grande vitesse sont proposées et publiés dans une revue internationale. Dans
ces architectures, le masque émetteur et les exigences de linéarité sont respectées, car le FIR DAC à
un seul bit est linéaire et combine dans sa fonctionnalité à la fois la conversion numérique-analogique
et le filtrage du bruit. Un modulateur delta-sigma peut être utilisé pour la conversion de résolution de
sorte que les signaux en bande de base avec une large gamme de bandes passantes et de résolutions sont
traités.

Les DAC de FIR nécessitent des filtres longs avec des coefficients de résolution élevés pour atteindre des
niveaux d'atténuation de stopband satisfaisants aux exigences de bruit hors bande. Normalement, cela
limite le fonctionnement multi-standard à grande vitesse et se traduit par une grande surface de silicium et
un layout complexe. Dans ce travail, les techniques de conception de circuits sont développées de sorte
qu'un élément de circuit unitaire réalisant un coefficient d'une fonction de transfert peut être réutilisé
dans la réalisation d'un coefficient d'une autre fonction de transfert. Cette capacité multimodale de
partage du matériel du FIR DAC est maximisée par optimisation du coefficient au niveau du système.

Le travail propose également des topologies qui exploitent le traitement du signal numérique sur des
nœuds avancés pour mettre en œuvre la modulation en quadrature tout en réalisant la conversion, la
conversion numérique-analogique, filtrage d'image et la quantification dans un bloc FIR DAC à bande
passante configurable. Une puce prototype de filtre passe-haut FIR DAC qui peut être configuré pour le
fonctionnement de l'IEEE 802.11ac et l'IEEE 802.11ad a été mise en œuvre sur une technologie CMOS
28nm FDSOI de STMicroelectronics. Le test De cette puce a démontré la validité des architectures
d'émetteur proposées. Le prototype de puce peut traiter des signaux OFDM de bande passante aussi
larges que 136 MHz à une fréquence d'horloge de 3 GHz et atteint une fréquence porteuse de sortie de
1.5 GHz en mode 802.11ac. Il peut également canaliser des signaux SC aléatoires aussi larges que 700
MHz à une fréquence d'horloge de 1.4 GHz et atteint une fréquence porteuse de sortie de 700 MHz.
La puce a une consommation totale de 103.07 mW dans les modes 802.11ac et 86.89 mW dans les
modes 802.11ad à une fréquence d'horloge de 1.4 GHz. Il est fourni avec trois alimentations de tension
séparées: les circuits numériques fonctionnent de 0.6 V à 1.55 V, le réseau de sortie analogique nécessite
une alimentation de 1.2 V et les circuits de polarisation sont fournis avec une tension séparée de 1.2 V.

**Mots-clés:** Convertisseurs numérique-analogique, MOS complémentaires, Ondes millimétriques, Radio-Émetteurs et transmission, Filtrage du signal, Multi-bandes, Multi-standard, IEEE 802.11ac, IEEE 802.11ad

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Abstract

The vision of research on multi-standard and multi-band wireless communication systems, architectures, and circuits has been to develop devices which can hop seamlessly from one network to the other while delivering excellent functionality in different radio access technologies.

This work proposes a transmitter architecture based on FIR DACs able to work with very dissimilar high data rate standards for wireless communications at 5 GHz and 60 GHz, namely WiFi (802.11ac) and WiGig (802.11ad). FIR DACs require long filters with high resolution coefficients to meet high out-of-band noise attenuation. Normally, this limits speed and results in large area. In this work, circuit techniques are developed so that a unit circuit elements can be assembled to realize programmable transfer functions. The work also proposes topologies that exploit digital signal processing in advanced technology nodes to implement up-conversion, digital-to-analog conversion and image and quantization filtering in one configurable FIR DAC block.

A prototype high pass FIR DAC chip which can be configured for processing IEEE 802.11ac and IEEE 802.11ad signals was implemented in ST 28nm CMOS FDSOI technology. Experimental results demonstrate the potential of the proposed transmitter architecture. The prototype chip can process baseband signals as wide as 63.63 MHz and 300 MHz at a clock frequency of 1.4 GHz while consuming 103.07 mW in the 802.11ac mode and 86.89 mW in the 802.11ad mode.

Résumé

La recherche dans le domaine des communications multi-standards et multi-bandes vise des architectures et circuits pouvant s'adapter parfaitement aux différents réseaux tout en offrant d'excellentes fonctionnalités sur les différentes technologies d'accès radio.

Ce travail propose une architecture de transmetteur radio utilisant des FIRDAC capable de supporter des standards haut débit à 5 GHz et 60 GHz ayant des caractéristiques très différentes. Il s'agit ici des standards WiFi (802.11ac) et WiGig(802.11ad). Les FIRDAC nécessitent des filtres longs avec des coefficients de résolution élevés pour atteindre des niveaux d'atténuation dans la bande coupée satisfaisants aux exigences de bruit hors bande. Normalement, cela limite la vitesse et se traduit par une grande surface de silicium. Dans ce travail, une approche programmable de la fonction de transfert à partir de cellules DAC unitaire est introduite.

Une puce prototype de passe-haut FIRDAC qui peut être configuré pour le fonctionnement des standards l'IEEE 802.11ac et l'IEEE 802.11ad a été mise en œuvre sur une technologie CMOS 28nm FDSOI de STMicroelectronics. Le test de cette puce a démontré la validité des architectures d'émetteur proposées. La puce prototype peut traiter des signaux avec des bande utiles aussi larges que 63.63 MHz et 300 MHz à une fréquence d'horloge de 1.4 GHz avec une consommation de 103.07 mW dans le 802.11ac et 86.89 mW dans le mode 802.11ad.