# Grey Box Identification of SiC MOSFET Modules in Short Circuit

Jorge Mari, Michael Kirner

► To cite this version:

Jorge Mari, Michael Kirner. Grey Box Identification of SiC MOSFET Modules in Short Circuit. The 26th European Conference on Power Electronics and Applications, GDR SEEDS France & EPE Association, Mar 2025, Paris, France. 10.34746/epe2025-0081 . hal-05081999

HAL Id: hal-05081999

https://utc.hal.science/hal-05081999v1

Submitted on 23 May 2025

**HAL** is a multi-disciplinary open access
archive for the deposit and dissemination of sci-
entific research documents, whether they are pub-
lished or not. The documents may come from
teaching and research institutions in France or
abroad, or from public or private research centers.

L'archive ouverte pluridisciplinaire HAL, est
destinée au dépôt et à la diffusion de documents
scientifiques de niveau recherche, publiés ou non,
émanant des établissements d'enseignement et de
recherche français ou étrangers, des laboratoires
publics ou privés.

<figure><img src="image_1.png" /></figure>

Distributed under a Creative Commons Attribution 4.0 International License
# Grey Box Identification of SiC MOSFET Modules in Short Circuit

Jorge Mari, Michael Kirner

SEMIKRON DANFOSS GmbH

Carl-Zeiss-Ring 5, 85737 Ismaning, Germany

E-Mail: jorge.mari@semikron-danfoss.com, michael.kirner@semikron-danfoss.com

URL: https://www.semikron-danfoss.com/

## Keywords

«parameter identification», «system identification», «SiC MOSFET», «short circuit», «thermal model».

## Abstract

In this work we apply the paradigm of grey box identification of dynamical systems to the recovery of unknown parameters appearing in the equations governing short circuit type I in SiC MOSFET high current 2kV modules.

## Introduction

Short circuit characterization of modules is significantly more complex than that of simple discrete devices. One reason for this is that the dynamics of multi-chip modules is far richer than that of single chips. Often, short circuit tests result in module destruction. Per se then, the investment in time and materials is an order of magnitude greater than when chip suppliers perform tests on single chip devices. Also, the catastrophic failures not only destroy the modules but the equipment surrounding the module, including gate drivers, busbars, voltage and current probes. This problem is exacerbated for high voltage and power modules since then the energies stored in the links grow quadratically with voltage. One of the problems that arises in practice is then how to fully characterize modules, how to find the limits of performance across a wide operating range, with a limited time and budget. Ideally, if we had a predictive tool that based on some limited experimentation allows to infer the results of new tests, the planning, avoiding material and infrastructure destruction can be made more intelligently. This is one of the gaps that the work behind this paper tries to fill.

## Grey box model identification

There are two main approaches to mathematical model building: physical “bottom-up” modeling and empirical modeling. In the latter one, a set of models or model structure is proposed, for example linear model structures, and the artillery of systems identification [1] is applied. Grey-box modeling on the other hand [2], is a hybrid approach that starts with a physics based or a priori information and complements it with experimental observations or a posteriori information. Mathematically the paradigm used is that of nonlinear parametrized differential equations (state x) whose parameters Θ are then identified through minimization of errors in the trajectories predicted by the model vs the actually measured ones.

$$ \dot{x} = f(x, u(t), \theta) \quad (1) $$

$$ y = g(x, u(t), \theta) \quad (2) $$

In practice, the numerical estimation process is very conveniently done with ad hoc software like the MATLAB™ function nlgreyest in the Systems Identification Toolbox. However, this seemingly straightforward process does not render good results if the models have too many parameters and if the trajectories chosen are not chosen to bear the influence of those parameters. In system identification terms what this implies is that the models should be parsimonious, and the experiments performed for trajectory fitting should be informative, i.e. that the data set collected allows discrimination between different models in the set of possible chosen models. This condition is far from trivial and is illustrated for the short circuit cases in a later section.

## Physics during the short circuit

A seminal paper for compact modeling of SiC MOSFETs during short circuits is [3]. Extensions
and expansions of this approach are found in subsequent papers e.g. [4],[5]. The basic ideas are the following.

1. Assume a static characteristic for the MOSFET saturation current $I_{ds}$ as a function of gate-source $V_{gs}$ and drain-source voltage $V_{ds}$.

2. State the dynamic equations for $V_{gs}$ including the driving circuitry and the equations for $I_{ds}$ including the link voltage, the parasitic commutation inductance and module source side inductance. This we do in the simple context of a laboratory testbench.

3. Using a one-dimensional model of the vertical structure of the MOSFET state a Cauer-like thermal model whose heat generated at each node will be a function of the traversing current and the voltage drop in each slice of the epitaxial layer where the electric fields are high.

Point 1 is difficult for several reasons. On the one hand because classical curve tracers are not suitable to describe the stationary forward characteristics in the whole operating regimes of a SiC MOSFET (ohmic, quasi-saturation, active saturation). To overcome this difficulty, one can use the methodology of [6]. In the context of this paper this is not necessary. On the other hand, the temperature excursion during demanding short circuits far exceeds the operating temperatures under which most characterizations are performed. In particular, there is little information about the behavior of the threshold voltage of the MOSFET $V_{th}$ over temperatures past 200°C. It appears as if the linear rate at which the threshold decreases with increasing temperature slows down at an inflexion point past the 200°C [7], [8], [9].

For Point 2 the critical assumption is made that the module is *well designed*. This means that all parallel chips working inside the module balance the currents approximately uniformly. This belongs to the realm of good methodologies for module design as illustrated in [10]. Once this is assumed, instead of posing multiple differential equations for each of the chips in the multi-chip module, a single “lumped” model for the whole module is used. This reduces the data size demands and speeds up the numerical integration routines used by the grey box identification. Fundamental though --and different to papers dealing with short circuit in single chip MOSFETS packaged in discretes-- is the correct

assessment of the magnetic coupling between power loop and gate circuitry in the module. The importance of this coupling has been thoroughly investigated in [11]. The balanced current assumption is a technical prerequisite for compact small models to keep the mathematical complexity at a reasonable level.

With regards to Point 3, several papers have shown the strongly 2D or even 3D character of the thermal flow in a SiC MOSFET chip [12],[13],[14], so the reduction to 1D is again a technical assumption to make the problem relatively quickly solvable. Full FEA simulations take quite some time in the computers accessible to most engineers.

## Mosfet forward model

Retaining the spirit of using as simple as possible models, we use a variant of a Level 1 Spice model with current in saturation quadratic in the voltage overdrive $v_{gs} - V_{th}$. The starting formulation is:

$$I_{ds} = K_p(T) (v_{gs}(t) - V_{th}(T, v_{ds}))^2 \quad (3)$$

The Mosfet gain $K_p$ in A/V² is made to explicitly depend on the temperature at the channel interface to the gate oxide. This is consistent with the channel electron mobility $\mu_{ch}$ depending on temperature and together with other key MOSFET geometric parameters relates to the specific transconductance $\kappa$

$$K_p(T) = \frac{\kappa}{2} = \frac{\mu_{ch}(T)C_{ox}}{2} \frac{W}{L} \quad (4)$$

Modern SiC MOSFETs have very short channels. Initially we assumed that the threshold voltage would have a double dependency on temperature on the one hand and on drain-source voltage through a *drain induced barrier lowerage* mechanism or DIBL. Inspired on [15] for trench MOSFETS, we hypothesized that DIBL is linear on voltage, affecting the “low voltage” threshold with a multiplication factor as follows:

$$\left[ 1 - \frac{v_{ds}|_{+}}{U_{dss}} (1 - DIBL) \right] \quad (5)$$

However, for the symmetrical trench chip MOSFET in our module (see also [14]) this kind of threshold voltage reduction could not be confirmed from the application of the grey-box methodology. Instead, we resorted to a classical first order approximation for the short channel effect and introduced a factor $1 + \lambda v_{ds}$ in the saturation current, modifying equation (3) to
$$I_{ds} = K_p(T) (v_{gs} - V_{th}(T))^2 (1 + \lambda v_{ds}) \quad (6)$$

Furthermore, the channel length modulation factor $\lambda$ was made first order channel temperature dependent as:

$$\lambda = \lambda_0 + \lambda_1 (T_j - T_0) \quad (7)$$

A key objective in the identification procedure is to reveal the temperature dependency of the transconductance and the threshold. Since we have two variables that strongly depend on temperature, the system identification procedure, assuming $T_j$, $i_{ds}$, $v_{gs}$ and $v_{ds}$ are known is still undetermined. To remove the indeterminacy, we employ a functional continuation method on the measured threshold voltage. We need to extend this curve in a rational way to temperatures past 600°C even when we cannot do classical static measurements of this threshold at those temperatures (the module package does not allow it). The model that we adopt is a 2nd order exponential.

$$V_{th}(T) = a \exp bT + c \exp dT \quad (8)$$

<figure><img src="image_2.png" /><figcaption>Fig. 1 Fitted threshold vs temperature</figcaption></figure>

Fitting to the data sheet values is perfect in the range -50°C to 175°C with parameters a = 0.1325 b= -0.0157 c= 4.1466 d = -0.0017 and T is in degree Celsius. Because data sheet values are taken at moderate inversion, these parameter values are only used as starting values but are afterwards left free around a small range. The strong inversion threshold resulting from operation in short circuit conditions is thus also part of the identification procedure.

A further objective of the grey-box system identification procedure is to find the remaining T-dependency on $K_p(T)$. For silicon IGBTs it is

generally assumed this dependency is monotonic decreasing, but it is clear from [3], [16], [17] and Mathiessen's rule for channel mobility that this does not necessarily hold for SiC MOSFETs. Hence, we adopt a general analytic form which allows both monotonic (in temperature) and unimodal shapes, since we a priori do not know what the shape of this variable will be for SiC.

$$y = x^a \exp(-bx)c + d \quad (9)$$

The fitting of this expression is done for all available waveforms (at each link voltage) at the same time, with the same set of 4 parameters.

## Circuit equations

The rest of the ordinary differential equations in the nonlinear model used for grey-box identification are displayed next.

$$V_{cc} = (R_g + R_{gint})i_g + L_g \frac{di_g}{dt} \quad (10)$$

$$+ v_{gs} + L_{ss} \frac{d(i_g + i_{ds})}{dt}$$

$$v_{ds} = U_{dc} - L_{\sigma} \frac{di_{ds}}{dt} \quad (11)$$

$$C_{gs} \frac{dv_{gs}}{dt} = i_g + C_{dg} \frac{dv_{dg}}{dt} \quad (12)$$

$$i_{ds} = I_{ds} + C_{ds}(v_{ds}) \frac{dv_{ds}}{dt} \quad (13)$$

$$+ C_{dg}(v_{dg}) \frac{dv_{dg}}{dt}$$

The variables in these equations include the DC-link voltage $U_{dc}$, the commutation inductance $L_\sigma$, the driver output voltage $V_{cc}$, the gate current $i_g$, the gate loop inductance $L_g$, (made of two parts, external $L_{gext}$ to the module and internal $L_{gint}$) the internal module resistance $R_{gint}$ (which depends on the externally set baseplate temperature), the external driver resistance $R_g$ (which changes for ON and OFF transients), the source side coupling inductance $L_{ss}$ and the MOSFET capacitances $C_{gs}$, $C_{ds}$ and $C_{dg}$. These are nonlinear models which can be made as simple or complicated as desired [18]. For simplicity we kept $C_{gs}$ constant, used an inverse voltage law for $C_{ds}$

$$C_{ds} = C_0 / \left(1 + \frac{v_{ds}}{V_0}\right)^m \quad (14)$$

and a Spice-related formulation for $C_{dg}$.

The nonlinear functions were fitted to the measured curve tracer values (assuming they approximately hold also under short circuit
conditions!) and are known a priori, before the identification starts.

Compared to the standard formulation (1), there are 4 states $x = [i_g, v_{gs}, i_{ds}, v_{ds}]'$ after deflation and suitable reformulation of (10) to (13). Similarly, the outputs in (2) are selected as $y = [V_{gs}, i_{ds}, v_{ds}]'$ which include the current $i_{ds}$ through the commutation inductance, the voltage $v_{ds}$ across the output capacitance $C_{ds}$ and the module terminal voltage (not to be confused with the internal MOSFET gate-source voltage)

$$V_{gs} = V_{cc} - R_g i_g - L_{gext} \frac{di_g}{dt} \quad (15)$$

The input vector $u(t)$ includes the time-varying signals $V_{cc}(t)$, $U_{dc}$, $T_j(t)$.

## The Fourier equation

To uncover the temperature dependency of several of the expressions introduced above, it is necessary to estimate the temperature evolution inside the chips and in particular at the interface between the p-well and the N-drift layer of the MOSFET [5], [19]. The temperatures cannot be measured during such fast and potentially destructive events. The approach followed –as in many other previous papers, see reference list– is to simplify the three-dimensional problem into a lumped one-dimensional heat conduction problem as governed by the 1D Fourier equation:

$$\rho c_p(T, x) \frac{\partial T(x)}{\partial t} = Q(x) + \frac{\partial}{\partial x} \left( \lambda(T, x) \frac{\partial T}{\partial x} \right) \quad (16)$$

All properties (density $\rho$, specific heat coefficient $c_p$, heat transfer coefficient $\lambda$) must be programmed temperature dependent for the results to be accurate [12], [20]. The dependency on $x$ of the thermal properties reflects the different materials in the chip vertical stack.

The approach we followed was to discretize this equation into a multi-node Cauer model, where the number of nodes can be controlled by the user. The whole interval of the short circuit event is subdivided in a sufficiently large number of short subintervals where the thermal properties are fixed constant to the prevailing starting temperatures. The duration of these subintervals was 50ns, user controllable too. In the subinterval the system is simulated as a linear time invariant model very easily. The whole vertical structure is

made up of multiple transversal slices, each of them assigned a temperature (see Fig. 11). We chose several nodes in the epitaxial layer, one at the p-well, a few on the top chip metallization, and a couple in the lower SiC substrate. In the short duration, the system is adiabatic with an internal heat generation deposited mostly in the epitaxial layer. The volumetric heat density $Q(x)$ generated in each layer is then $JE(x)$ where $J = i_{ds}/N_{chip}A_e$ is the chip current density obtained from the total measured current, the number of chips in the switch and the active area of the chip.

## The Poisson equation

In the formulations used in [18], [5] and several other papers the simple assumption of a triangular field with the same extension as the vertical MOSFET in static blocking conditions is used. However, all modern MOSFETs are of punch through (PT) type, so the extension of the epitaxial layer is shorter than in non-punch through devices and the corresponding fields may become trapezoidal at high DC-link voltages. Moreover, the flow of electrons in the drift layer under high field conditions alters the penetration depth of the space charge region significantly compared to the pure blocking case. With the methodology of [21] we estimate the key dimensioning parameters of the 2kV MOSFET to comprise 18 µm epi-layer at a background doping of 5.5E15 cm-3. The electric field $E(x)$ at each slice where the thermal model is to be solved is obtained at each time step by solving the Poisson equation (in space):

$$\frac{dE}{dx} = -\frac{q}{\epsilon}(N_D - N_e) \quad (17)$$

in such a way that the integral over the time-varying space charge region length equals the instantaneous voltage $v_{ds}$. Here, $N_e$ is the effective electron concentration. This is found assuming that the only moving carriers are electrons obeying the transport equation

$$J = N_e q \mu(E, T(x)) E \quad (18)$$

with $\mu$ the bulk electron mobility [21]. For the mobility we relied on literature values, including the temperature dependency, the electric field dependency stemming from the Canali model and the doping concentration from the Masetti model [16], [17]. Once the electric field is found, its values are plugged into the heat injection of the Fourier equation, and finally the temperatures are
found. This is done for each of the experiments conducted. The corresponding pn-interface temperature is used as an input to each of the systems in the nonlinear *grey box* model identification routine. An example of the result of this field simulation is shown in Fig. 2.

<figure><img src="image_3.png" /></figure>

<figure><img src="image_4.png" /><figcaption>Fig. 2 Results of solving the 1D Poisson equation in short circuit conditions, 25°C, 1300V, 24kA through the module.</figcaption></figure>

## Post identification predictions

For model predictions in cases not tested, a second identification run is done, with the MOSFET and system parameters identified, and a simple thermal model adopted and identified. This is not reported here.

## Parameter values

The parameters in equations (10) to (13) are more or less well known from the module construction, the testbench setup, the chip main characteristics, the material properties. However, the parameters in equations (3) to (9) are not known due to the impossibility to perform controlled experiments at very high temperatures. This is where the value of grey-box identification should manifest.

<table><caption>Table I: Parameters in the equations</caption><thead><tr><td>Symbol</td><td>Description</td><td>Value</td></tr></thead><tbody><tr><td>V<sub>cc</sub> [V]</td><td>Driver on-state voltage</td><td>15 .. 18</td></tr><tr><td>R<sub>g</sub> [Ω]</td><td>Driver turn on resistance</td><td>0.75 .. 2</td></tr><tr><td>R<sub>gint</sub> [Ω]</td><td>Module internal gate resistance</td><td>0.35</td></tr><tr><td>L<sub>g</sub> [nH]</td><td>Total gate loop inductance</td><td>~80</td></tr><tr><td>L<sub>ss</sub> [nH]</td><td>Common source inductance</td><td>Grey-box</td></tr></tbody></table>

<table><tr><td>U<sub>dc</sub> [V]</td><td>Link voltage</td><td>300..1500</td></tr><tr><td>L<sub>σ</sub> [nH]</td><td>Commutation inductance</td><td>20,30</td></tr><tr><td>K<sub>p</sub></td><td>ka,kb,kc,kd</td><td>Grey-box</td></tr><tr><td>V<sub>th</sub> [V]</td><td>a,b,c,d</td><td>Grey-box</td></tr><tr><td>λ<sub>0</sub>, λ<sub>1</sub></td><td>channel length modulation</td><td>Grey-box</td></tr></table>

In total, 17 parameters were programmed, but some of them turned out not to bring any value to the identified system, as *U*<sub>dss</sub>, DIBL, *L*<sub>g</sub>, *k*<sub>d</sub> and a few related to lateral electric field in the channel. Their effect was nullified and is not further considered.

## Module description

The module used was a development-phase half-bridge fitted with 28 2kV MOSFET chips in parallel at each of the two switch positions [10], top and bottom.

<figure><img src="image_5.png" /><figcaption>Fig. 3 Circuit diagram of the half-bridge module</figcaption></figure>

It has a nominal current rating of 1700A and is to be driven with -2V in the off-mode and +18V in conduction. The static and dynamic performance was assessed separately and is quite impressive. For example, it exhibits very small switching losses and 2 mΩ *R*<sub>dson</sub> at 150°C. The dynamic performance at turning on and off is mostly devoid of any troublesome ringing so this is not a concern when moving towards short circuit characterization. The target application of this module is high power industrial applications, renewable energy conversion and energy storage.

## Testbench description

With the latest improvements in optical measurement probes, we can now reach bandwidths beyond 1 GHz and common mode rejections above 150dB, maintaining the precision requirements, needed to correlate *V*<sub>gs</sub>,
$V_{ds}$ and $I_{ds}$. To reduce any common mode disturbances and avoid grounding loops the whole testbench has been setup floating, respective to common ground, increasing the technical demands of the measurement system.

<figure><img src="image_6.png" /></figure>

Fig. 4 Floating DP testbench with DUT in the center and single channel drivers to the sides. Below is the support for oil-based heating of the DUT.

Having an appropriate oscilloscope with sampling speeds above 2.5GHz per Channel (e.g. LeCroy HD8000 series), the following probes were used: LeCroy DLO7 for $v_{gs}$ and Testec TT-SI 8110 for $v_{ds}$.

The starting temperatures of the devices were set with the help of an oil-based heater with a regulated temperature feedback loop.

## Short circuit setup

The device under test is a high-power dual module in leg configuration, i.e. upper and lower switches series connected with an intermediate AC output phase (Fig. 3). Each of the switches consists of 2 substrates fitted with multiple chips in parallel. To visualize this aspect the circuit diagram in Fig. 5 uses a representation of 2 MOSFETs in parallel per side. However, the intention is to understand the module endurance in a short circuit type I (SC1, see also IEC 60747-9), so recourse must be made to an external shorting bar of the switch not being tested. As a matter of fact, the bypass shorting bar is used and additionally the non-tested device is biased at high voltage so that the short circuit current of the DUT traverses mostly in the complementary device and partly in the shorting bar. The switch not used is kept biased all the time to avoid interference with the switching dynamics of the DUT.

<figure><img src="image_7.png" /></figure>

Fig. 5 Simplified circuit diagram. The $R_{goff}$ resistance (not shown) is selected to avoid dangerous overshoots at turn-off.

<figure><img src="image_8.png" /></figure>

Fig. 6 Picture showing driver connections and external shorting bars.

Connecting the driver to the module terminal is realized via dedicated high voltage interface PCB and low inductive flex-PCBs to protect the auxiliary hardware.

<figure><img src="image_9.png" /></figure>

Fig. 7 Setup with increased $L_{σ}$ and protective varistor.
To understand the impact of short circuit inductance, several aluminum rods of specific AC inductances were applied between module terminal and DC terminals. On the left lower part of Fig. 7 a varistor can be seen to protect the fragile optical probes and the output stage of the driver in case of catastrophic failure.

## Design of experiments

In order to create a set of experiments informative enough, where all the dynamics during the short are manifested at some experiment, we chose to vary 6 key variables: the on-state output voltage of the driver $V_{cc}$ in {15, 18}, the pulse length $t_p$ in {1, 1.5} us, the turn-on resistance $R_{gon}$ {0.75, 1.35} Ω, the commutation inductance $L_σ$ {20, 30} nH, the starting temperature $T_0$ {25, 100, 150} °C and the DC-link voltage $U_{dc}$ [300:100:1500]. All possible combinations were targeted to be tested. In principle the DOE table (excluding link voltage) for a full factorial has 48 rows some of which are shown next.

<table><caption>Table II: Excerpt for full factorial DOE</caption><thead><tr><th>V<sub>cc</sub></th><th>t<sub>p</sub></th><th>R<sub>g</sub></th><th>L<sub>σ</sub></th><th>T<sub>0</sub></th></tr></thead><tbody><tr><td>15</td><td>1</td><td>0.75</td><td>20</td><td>25</td></tr><tr><td>18</td><td>1</td><td>0.75</td><td>20</td><td>25</td></tr><tr><td>...</td><td>...</td><td>...</td><td>...</td><td>...</td></tr><tr><td>18</td><td>1.5</td><td>1.35</td><td>30</td><td>150</td></tr></tbody></table>

To maximize the chances of survival of the module, and hence to minimize the amount of material destroyed the experiments are always done in sequence: increasing link voltage, increasing on-state voltage, increasing pulse length, increasing temperature varying inductance (which requires special studs) and varying resistance in the programmable driver.

## Results obtained

Due to lack of space, we can only show a few results.

<figure><img src="image_10.png" /><figcaption>Fig. 8 R<sub>gon</sub> = 0.75 Ω, L<sub>σ</sub> = 30 nH, V<sub>cc</sub> = 15V</figcaption></figure>

In Fig. 8 the green trace is the gate-source voltage measured at the DUT terminals. The first spike and reversal before 0.2us are symptomatic of the inductances in the gate loop. The voltage at chip levels inside the module is expected to rise steadily following essentially an overdamped 2nd order system response to a step input.

$$ \xi = \frac{R}{2} \sqrt{\frac{C}{L}} = 1.18 \quad (19) $$

At about 0.75 us the terminal module voltage settles at the driver output $V_{cc}$ = 15V. The voltage on the module is almost constant at $v_{ds} = U_{dc} - L_σ di_{ds}/dt \approx 1500 - 30 \cdot 7.6 = 1272V$. If the situation were stationary, we would not expect any change in $i_{ds}$. But $i_{ds}$ continues to rise all the way until the end of the externally applied pulse. Key to explain this rise is that the unobserved variable “temperature” T is growing inducing a $V_{th}(T)$ reduction and possibly a $K_p(T)$ increase.

<figure><img src="image_11.png" /><figcaption>Fig. 9 R<sub>gon</sub> = 0.75 Ω, L<sub>σ</sub> = 30 nH, V<sub>cc</sub> = 18V</figcaption></figure>

It is apparent that the chips and module have not reached the prospective peak short circuit current
level $I_{scpk}$ before falling back to a quasi-stationary value $I_{sc}$, which is what most publications dealing with single chip discrete short circuit tests show, [8], [22], [23],[24].

## Grey-box models identified

The methodology used to identify the single set of parameters to explain all the experiments done can be summarized as follows:

* Parse the whole experimental data set, fix a common time interval, down-sample to a reasonable data size per experiment. Compute the electric field and the temperatures in the MOSFET and save that data for later use.

* Build multi-experiment data sets by merging iddata structures in MATLAB™ System Identification Toolbox selecting subsets of the whole DOE performed.

* Set up a nonlinear grey-box model idnlgrey object calling all the subroutines programmed with the ordinary differential equations you have written beforehand. The integration solver used a Runge-Kutta ode45.

* Enforce lower, upper and start values for all parameters.

* Run the grey-box identification routine nlgreyest using the multi-experiment data set. The least squares solver used a trust region reflective algorithm from the Optimization Toolbox.

An example of the pre-parsed electric field and temperatures estimated for one experiment with 1300V DC-link, 18V driver voltage and 1.5us pulse length is seen in Fig. 10 and Fig. 11.

<figure><img src="image_12.png" /><figcaption>Fig. 10 Evolution of the 1D simulated electric field at different depths of the epi-layer in one of the experiments done.</figcaption></figure>

<figure><img src="image_13.png" /><figcaption>Fig. 11 Estimated temperatures at different depths of the SiC chip with a 1D model.</figcaption></figure>

Tuning to match 3D FEA simulations is not done in this study but see the encouraging results in [12]. Also, no attempt to model the Aluminum change of state (cf. [4]) occurring at temperatures around 660°C was made.

<figure><img src="image_14.png" /><figcaption>Fig. 12 comparison between the measured signals and the identified model for the case depicted above.</figcaption></figure>

On top of Fig. 12 you can see the comparison between the measured $V_{gs}$ at module terminals (black) and the simulated with the identified parameters (blue). The parameters were identified out of 42 short circuit experiments. The green line is the driver output voltage, and the red line is the $v_{gs}$ internal to the MOSFET excluding the chip resistance. Notice the big voltage difference between the driver voltage and the internal voltage. This can be explained by the voltage drop in the power to gate loop inductance introduced on purpose in the module design. This drop can be seen in the 3rd graph of Fig. 13. The other two graphs in Fig. 12 show the very nice replication of $I_{ds}$ and $V_{ds}$ at module terminals. Essentially all other experiments were judged to be sufficiently
well represented. The model does not capture a
few ringings originated from further parasitics
which were not modelled.

<figure><img src="image_15.png" /></figure>

Fig. 13 Evolution of internal variables during the short, recovered thanks to the modeling effort.

Fig. 13 shows the temperature used by the
identification algorithm and the time evolution of
the short channel modulation factor in the same
experiment as before.

<figure><img src="image_16.png" /></figure>

Fig. 14 Transconductance and threshold identified out of a set of 42 experiments selected from the DOE and plotted vs temperature.

It is interesting to plot some of the MOSFET
characteristics identified. Fig. 14 shows the
results obtained for the two key MOSFET
parameters, V<sub>th</sub> (strong inversion values) and K<sub>p</sub>.
The beauty of the method is in returning the
values of those parameters at temperature
conditions which cannot be tested by stationary
means. Similarly, the theoretical short circuit
stationary saturation current value is seen in Fig.
15.

<figure><img src="image_17.png" /></figure>

Fig. 15 *I*<sub>sc</sub> at 25°C for different *V*<sub>ds</sub> and *V*<sub>gs</sub> values.

Validation vs VI curve at high Vds

As an independent experimental validation
procedure after the grey box modeling effort, it is
interesting to compare the predicted outcome of
the MOSFET saturation current from the grey-
box model against the value obtained by direct
extraction. To do this, we performed with the
module a dedicated set of double pulse tests with
high turn-on resistance to slow down the
transient, get rid of the nuisance ringing, and infer
the full set of I<sub>ds</sub> vs V<sub>ds</sub> curves for each V<sub>gs</sub>, even
in the high V<sub>ds</sub> region where curve tracers cannot
operate continuously due to the high internal
dissipation and corresponding temperature drift.
The extraction procedure is exemplified in Fig. 16

<figure><img src="image_18.png" /></figure>

Fig. 16 Blue line v<sub>ds</sub>, green v<sub>gs</sub>, red i<sub>ds</sub>.

The vertical lines suggest the sampling and
creation of data structures (v<sub>ds</sub>, v<sub>gs</sub>, i<sub>ds</sub>) which after
some pre-processing, filtering, etc. are assembled
into a saturation function isat = f(v<sub>gs</sub>, v<sub>ds</sub>). The
process works well up to the Miller voltage. This
function is plotted together with the grey-box
output in Fig. 17.
<figure><img src="image_19.png" /><figcaption>Fig. 17 Comparison of the grey-box identified saturation current of the MOSFET at high drain-source voltage vs the extended VI characteristic obtained with the method of [6].</figcaption></figure>

## Conclusion

Grey-box model identification is a general paradigm suitable to identify parameters in structured models. It is possible to apply this paradigm to identify a combination of physical based parameters and mathematical parameters used in behavioral compact model descriptions of short circuit transients of SiC MOSFET power modules. An extensive and cleverly conceived set of experiments was performed to excite different dynamics of the transient compact model. The results of this set were used in combination with the theoretical model derived and surprisingly good agreement with measured results were obtained. The purpose of this work is to predict future excursions of variables in other scenarios, without the need to perform further possible costly destructive tests. It is thus a valuable guiding tool during the development phases of new high-power modules. It is recognized that some of the developments used require a deep understanding of physics modeling. It would be interesting to see if black-box modeling approaches, like for example the paradigm of neural state-space models can work as satisfactory as the grey-box models here pursued. This is left for future research.

## References

[1]. L. Ljung "System Identification: Theory for the User" 2nd edition, 1999 Prentice Hall. ISBN 978-0-13-656695-3

[2]. T. Bohlin "A case study of grey box identification", Automatica, 30(2):307-318, 1994

[3]. T. H. Duong, J. M. Ortiz, D. W. Berning, A. R. Hefner, S. -H. Ryu and J. W. Palmour, "Electro-thermal simulation of 1200 V 4H-SiC MOSFET short-circuit SOA," 2015 IEEE 27th Semiconductor Devices & IC's (ISPSD), Hong Kong, China, 2015, pp. 217-220.

[4]. Y. Pascal, M. Petit, D. Labrousse and F. Costa, "Thermal simulations of SiC MOSFETs under short-circuit conditions: influence of various simulation parameters," 2019 IEEE International Workshop on Integrated Power Packaging (IWIPP), Toulouse, France, 2019, pp. 137-142

[5]. F. Boige, F. Richardeau, S. Lefebvre, M. Cousineau, "SiC power MOSFET in short-circuit operation: Electro-thermal macro-modelling combining physical and numerical approaches with circuit-type implementation", Mathematics and Computers in Simulation, Volume 158, 2019, pp 375-386

[6]. H. Sakairi, T. Yanagi, H. Otake, N. Kuroda, H. Tanigawa, "Measurement Methodology for Accurate Modeling of SiC MOSFET Switching Behavior Over Wide Voltage and Current Ranges," in IEEE Transactions on Power Electronics, vol. 33, no. 9, pp. 7314-7325, Sept. 2018.

[7]. C. Unger and M. Pfost, "Energy capability of SiC MOSFETs," 2016 28th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Prague, Czech Republic, 2016, pp. 275-278

[8]. B. Maxime, O. Remy, C. Thibault, B. Pierre, O. Sebastion and T. Dominique "Electrical performances and reliability of commercial SiC MOSFETs at high temperature and in SC conditions," 2015 17th European Conference on Power Electronics and Applications (EPE'15 ECCE-Europe), Geneva, Switzerland, 2015, pp. 1-9.

[9]. Cheng, L., Agarwal, A.K., Dhar, S. et al. Static Performance of 20 A, 1200 V 4H-SiC Power MOSFETs at Temperatures of
−187°C to 300°C. *J. Electron. Mater.* **41**, 910–914 (2012).

[10].J. Mari, T. Schuetz, X. Dong, Y. Shen, M. Kirner and L. Findanno, "The Design of a 2kV 1700A SiC MOSFET Dual Module," *PCIM Europe 2024*; Nuremberg, Germany, 2024, pp. 1-6

[11].C. Baeumler, et al., "Influence of Magnetic Coupling Effects between Load and Gate Commutation Loop on the Short Circuit Behavior," PCIM Europe 2022; pp. 1-10

[12].A. Tsibizov, I. Kovačević-Badstübner, B. Kakarla and U. Grossner, "Accurate Temperature Estimation of SiC Power MOSFETs Under Extreme Operating Conditions," in *IEEE Transactions on Power Electronics*, vol. 35, no. 2, pp. 1855-1865, Feb. 2020.

[13].G. Romano et al., "A Comprehensive Study of Short-Circuit Ruggedness of Silicon Carbide Power MOSFETs," in *IEEE Journal of Emerging and Selected Topics in Power Electronics*, vol. 4, no. 3, pp. 978-987, Sept. 2016.

[14].X. Deng et al., "Short-Circuit Capability Prediction and Failure Mode of Asymmetric and Double Trench SiC MOSFETs," in *IEEE Transactions on Power Electronics*, vol. 36, no. 7, pp. 8300-8307, July 2021

[15].X. Liu, X. Li and T. Basler, "Short Circuit Type II and III Behavior of 1.2 kV Power SiC-MOSFETs," *2022 24th European Conference on Power Electronics and Applications (EPE'22 ECCE Europe)*, Hanover, Germany, 2022, pp. 1-9.

[16].M. Roschke and F. Schwierz, "Electron mobility models for 4H, 6H, and 3C SiC [MESFETs]," in *IEEE Transactions on Electron Devices*, vol. 48, no. 7, pp. 1442-1447, July 2001

[17].A. Pérez-Tomás, et al., "Field-effect mobility temperature modeling of 4H-SiC metal-oxide-semiconductor transistors" *J. Appl. Phys.* 1 December 2006; 100 (11): 114508.

[18].R. Stark, et al., "Gate Capacitance Characterization of Silicon Carbide and Silicon Power MOSFETs Revisited," *IEEE Transactions on Power Electronics*, vol. 37, no. 9, pp. 10572-10584, Sept. 2022

[19].F. Richardeau, F. Boige, "Circuit-type modelling of SiC power MOSfet in short-circuit operation including selective fail-to-open and fail-to-short modes competition",

Microelectronics Reliability, Volumes 100–101, 2019

[20].D. Kim, A. J. Morgan, N. Yun, W. Sung, A. Agarwal and R. Kaplar, "Non-Isothermal Simulations to Optimize SiC MOSFETs for Enhanced Short-Circuit Ruggedness," 2020 IEEE International Reliability Physics Symposium (IRPS), Dallas, TX, USA, 2020, pp. 1-6.

[21].J. Lutz, H. Schlangenotto, U. Scheuermann, R. De Doncker, "Semiconductor Power Devices" Springer 2011.

[22].A. E. Awwad and S. Dieckerhoff, "Short-circuit evaluation and overcurrent protection for SiC power MOSFETs," *2015 17th European Conference on Power Electronics and Applications (EPE'15 ECCE-Europe)*, Geneva, Switzerland, 2015, pp. 1-9.

[23].S. Brandt, M. Rasch, T. Wanagat and K. F. Hoffmann, "Characterisation of 1200 V SiC-MOSFETs - Influence of Repetitive Short-Circuit Events on Device Parameters," CIPS 2024; 13th International Conference on Integrated Power Electronics Systems, Düsseldorf, Germany, 2024, pp. 540-546

[24].Claudiu Ionita, Muhammad Nawaz, Kalle Ilves, "On the short-circuit and avalanche ruggedness reliability assessment of SiC MOSFET modules", Microelectronics Reliability, Volume 71, 2017, Pages 6-16.