# Scalable digital-to-RF processor for multi-standard and multi-band low power wireless transmitter in 5 GHz and 60 GHz

Fikre Gebreyohannes

► To cite this version:

Fikre Gebreyohannes. Scalable digital-to-RF processor for multi-standard and multi-band low power wireless transmitter in 5 GHz and 60 GHz. Micro and nanotechnologies/Microelectronics. Universite Lille 1; Isen-lille, 2016. English. NNT: tel-04345185

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Submitted on 14 Dec 2023

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UNIVERSITÉ DE LILLE 1

ÉCOLE DOCTORALE SCIENCES POUR L'INGÉNIEUR

THÈSE

EN VUE DE L'OBTENTION DU GRADE DE

DOCTEUR DE L'UNIVERSITÉ DE LILLE

DISCPLINE: MICRO ET NANOTECHNOLOGIE, ACOUSTIQUE ET TÉLÉCOMMUNICATION

PRÉSENTÉE ET SOUTENUE PUBLIQUEMENT LE 19 DÉCEMBRE 2016 PAR

FIKRE TSIGABU GEBREYOHANNES

PROCESSEUR NUMÉRIQUE/RF ADAPTATIF POUR ÉMETTEUR SANS FIL MULTI-BANDES

MULTI-STANDARD FAIBLE CONSOMMATION À 5 GHz ET 60 GHz

SCALABLE DIGITAL-TO-RF PROCESSOR FOR MULTI-STANDARD AND MULTI-BAND LOW

POWER WIRELESS TRANSMITTER IN 5 GHz AND 60 GHz

JURY :

PRÉSIDENT DU JURY : M. Christophe GAQUIERE Professeur à Université Lille 1, IEMN, Lille

RAPPORTEURS : M. Yann DEVAL Professeur à Université de Bordeaux, IMS, Bordeaux
M. Hassan ABOUSHADY Maître de Conférences à UPMC, LIP6, Paris

EXAMINATEURS : Mme Patricia DESGREYS Professeur à Télécom ParisTech, LTCI, Paris
M. Didier BELOT HDR, CEA-Leti, Grenoble

ENCADRANT : M. Antoine FRAPPÉ Enseignant-Chercheur, ISEN Lille

DIRECTEUR DE THÉSE : M. Andreas KAISER Directeur de Recherche CNRS, IEMN, Lille

<figure><img src="image_1.png" /></figure>

Université
de Lille

<figure><img src="image_2.png" /></figure>

<figure><img src="image_3.png" /></figure>

ISEN
ALL IS DIGITAL!

<figure><img src="image_4.png" /></figure>

Université
de Valenciennes
et du Hainaut-Cambresis

<figure><img src="image_5.png" /></figure>

<figure><img src="image_6.png" /></figure>

Institut d'Électronique, de Microélectronique et de Nanotechnologie
Abstract

Proliferation of application specific wireless communication standards have resulted in the multiple stan-
dards, multiple devices for one user scenario of today. Consequently, research in multi-standard, and
multi-band systems, architectures, and circuits has been a popular theme. The vision is to have devices
which can hope seamlessly from one network to the other while delivering excellent functionality on
different radio access technologies.

Configurable transmitter architectures targeting complementary use cases of the multi-Gb/s WiFi-WiGig standards have been studied. Novel approaches based on high speed configurable semi-digital FIR DACs are proposed and published in international journal. In this architectures, transmitter mask and linearity requirements are respected because the single-bit FIR DAC is inherently linear and combines in its functionality both digital-to-analog conversion and filtering of noise. A delta-sigma modulator can be employed for resolution conversion so that baseband signals with wide range of bandwidths and resolutions are processed.

FIR DACs require long filters with high resolution coefficients to achieve stopband attenuation levels that meet out-of-band noise requirements. Normally, this limits high speed multi-standard operation, and results in large silicon area and complex layout. In this work, circuit techniques are developed so that a unit circuit element realizing a coefficient of one transfer function can be re-used in realizing a different-valued coefficient of another transfer function. This multi-modal hardware-sharing capability of the FIR DAC is maximized by system-level coefficient optimization.

The work also proposes topologies that exploit digital signal processing at advanced nodes to imple-
ment quadrature modulation while realizing up conversion, digital-to-analog conversion and image and
quantization filtering in one configurable passband FIR DAC block.

A prototype high pass filter FIR DAC chip which can be configured for the operation of the IEEE 802.11ac and IEEE 802.11ad standards was implemented in STMicroelectronics® CMOS 28nm FDSOI technology. The test of this chip has demonstrated the validity of the proposed transmitter architectures. The prototype chip can process passband OFDM signals as wide as 136 MHz at a clock frequency of 3 GHz and reaches an output carrier frequency of 1.5 GHz in the 802.11ac mode. It also can channelize random SC signals as wide as 700 MHz at a clock frequency of 1.4 GHz and reaches an output carrier frequency of 700 MHz. The chip has a total power consumption 103.07 mW in the 802.11ac and 86.89 mW in the 802.11ad modes at 1.4 GHz clock frequency. It is supplied with three separate voltage
supplies: the digital circuits work from 0.6 V to 1.55 V, the analog output network requires a supply of 1.2 V and the biasing circuits are supplied with a separate 1.2 V.

**Key words:** WiFi, WiGig, IEEE 802.11ac, IEEE 802.11ad, WLAN, Transmitter, Multi-standard, Multi-band, Multi-mode, Configurable, DAC, FIR, DRFC, DDRM, High pass, Low pass, Band pass, Delay line, Filter, Delta-Sigma, Half-Band, DSP, CMOS, FDSOI, 28nm
Acknowledgments

These past three years and eight months have been a period of personal journey. It was also a period of education and development for me as a researcher. More importantly, though, it has given the opportunity to interact with a number of wonderful people. This PhD work has come to fruition due to the enormous help many individuals have been kind enough to provide it me.

I would like to bestow my heartfelt gratitude to my director of research, Prof. Andreas Kaiser. I have been fortunate enough to learn from him and work with him. His guidance through out my research work has been invaluable, and the standard he sets as a professional is something I have personally admired. I would also like to thank my supervisor, Dr. Antoine Frappé, for his dedication, kindness and keeping his office door always open for every one of my questions.

Since my initial correspondence with the SMART Integrated Circuits Design Group in early 2013, I have benefited immensely from the generosity of the team members. Dr. Bruno Stefanelli has shared with me his valuable experience during my presentations, design reviews, chip assembly and measurement. Dr. Jean-Marc Capron was always there for my presentations, and he is a genuinely nice person. I thank Dr. Axel Flament for his comments and for coming to my presentations. Thank you, Axel, also for the enjoyable afterwork football matches. Florence Alberti welcomed me to this beautiful city on a Sunday morning at Euralille. I would like to thank her for guiding me through the intricate world of French administration.

I would like to thank members of the Silicon Microelectronics Group at IEMN, specifically Prof. Emmanuel Dubois, Dr. Jean-François Robillard, and Matthieu Berthomé. Thank you Dr. Pascale Diener for helping me with the pick and place machine during the chip assembly.

My test chip characterization has been carried out at the IRCICA Telecom Platform during many months. I would like to extend my sincere gratitude to Rédha Kassi and his coworkers for making it convenient for me to work there.

I would like to thank the following past and present members of the SMART-ICD Group: fellow PhD students Dr. Baptiste Grave, Dr. Ilias Sourikopoulos, Cristian Marin, Justine Philippe, Matteo Causo, Dr. Camilo Salazar and Dipal Ghosh; postdocs Dr. Pietro Maris, Dr. Stephane Mebaley Ekome, Dr. Walid Bourennane and Dr. Benoit Larras for their support. I have shared the office with Dipal and Walid for a year now, but it is like they were here for a couple of months. It was great discussing with you all the interesting questions of Science, Technology, History and, of course, 140 GHz oscillator.
I have shared the longest part of my stay with Ilias and Cristian. I thank them for their advices and friendship. It was a pleasure to have shared with you the many fun lunch times. They are some of the highlights of my stay in Lille. Pietro, Stephane and Bruce Ferrer for their friendship during their stay here in Lille. It was great to have you guys around.

I also would like to thank the employees of ISEN Lille which were always glad to help me in the rare cases I had asked for it. Thank you Nathalie Rousseau, Josée Vanbouvelen, and others. Valérie Vandenhende is a pleasant person and a great ambassador to the school.

My work was initially funded through the French ANR WENDY project. It was a collaborative project among IEMN, STMicroelectronics and IMS Bordeaux. I would like to thank the team members of that project: Prof. Yann Deval, Dr. Didier Belot, Dr. Mathieu Vallet, Dr. Olivier-cro Richard, and Dr. Sebastien Dedieu. Yann and Didier are also members of my doctoral jury. I would like thank them and the other members of the jury for accepting the invitations. I am also grateful to Dr. Andreia Cathelin and Dr. Philippe Cathelin for the important comments and suggestions they had given me at different periods of my research.

Finally, I would like to thank my friends and my family members. My brothers, my sisters and my parents have always been supportive, considerate and appreciative of whatever endeavor I have taken. I send them my heartfelt gratitude. The last eight months of my doctoral study have been the most satisfying. I thank Seli for her support and love!
<table><tr><td>3.4</td><td>Summary and Conclusions</td><td>34</td></tr><tr><td>4</td><td>Configurable Finite Impulse Response Digital-to-Analog Converter</td><td>35</td></tr><tr><td>4.1</td><td>Operation of a DAC</td><td>35</td></tr><tr><td>4.1.1</td><td>Traditional Multi-bit DAC</td><td>35</td></tr><tr><td>4.1.2</td><td>Multi-bit DAC Specification</td><td>36</td></tr><tr><td>4.2</td><td>Traditional DAC Topologies</td><td>38</td></tr><tr><td>4.2.1</td><td>R-2R Ladder DAC</td><td>39</td></tr><tr><td>4.2.2</td><td>Resistor String DAC</td><td>39</td></tr><tr><td>4.2.3</td><td>Current Steering DAC</td><td>39</td></tr><tr><td>4.3</td><td>Finite Impulse Response DAC</td><td>40</td></tr><tr><td>4.3.1</td><td>FIR DAC Implementation Issues</td><td>41</td></tr><tr><td>4.3.2</td><td>L-bit, N-tap FIR DAC Design Challenges</td><td>42</td></tr><tr><td>4.3.3</td><td>N-tap, 1-bit FIR DAC Design Challenges</td><td>43</td></tr><tr><td>4.3.4</td><td>Frequency Translation of FIR DACs</td><td>44</td></tr><tr><td>4.4</td><td>FIR DAC Architectures in Literature</td><td>48</td></tr><tr><td>4.4.1</td><td>Multi-bit FIR DACs</td><td>48</td></tr><tr><td>4.4.2</td><td>1-bit Semi-digital Reconstruction Filter</td><td>49</td></tr><tr><td>4.4.3</td><td>Programmable Filtering DAC</td><td>50</td></tr><tr><td>4.4.4</td><td>Receive-band Noise Filter</td><td>51</td></tr><tr><td>4.4.5</td><td>FIR Power DAC</td><td>51</td></tr><tr><td>4.5</td><td>High Speed 1-bit, N-tap FIR DAC Design</td><td>52</td></tr><tr><td>4.5.1</td><td>Current Steering Architecture</td><td>52</td></tr><tr><td>4.5.2</td><td>Performance Metrics and Modeling</td><td>53</td></tr><tr><td>4.6</td><td>Summary and Conclusions</td><td>64</td></tr><tr><td>5</td><td>Proposed IEEE 802.11ac/ad Transmitter Baseband Architecture</td><td>65</td></tr><tr><td>5.1</td><td>Specification of the standards</td><td>65</td></tr><tr><td>5.1.1</td><td>IEEE 802.11ac</td><td>65</td></tr><tr><td>5.1.2</td><td>IEEE 802.11ad</td><td>66</td></tr><tr><td>5.2</td><td>System Level Simulation of Proposed Transmitter Architecture</td><td>67</td></tr><tr><td>5.2.1</td><td>Standard Coexistence</td><td>68</td></tr><tr><td>5.2.2</td><td>Transmitter Baseband Architecture</td><td>69</td></tr><tr><td>5.2.3</td><td>DSP Blocks of 802.11ad</td><td>70</td></tr></table>
Contents

vii

<table><tr><td>5.2.4 DSP Blocks of 802.11ac</td><td>72</td></tr><tr><td>5.2.5 FIR DAC In Three Modes</td><td>76</td></tr><tr><td>5.3 From Transfer Function to Circuit Parameters</td><td>80</td></tr><tr><td>5.3.1 Coefficient Quantization</td><td>80</td></tr><tr><td>5.3.2 Multi-standard FIR DAC Specifications</td><td>80</td></tr><tr><td>5.4 Summary and Conclusions</td><td>83</td></tr></table>

6 Design and Implementation of A Configurable Transmitter Baseband in CMOS 28nm FD-SOI

85

<table><tr><td>6.1 From System Level to Floorplan</td><td>85</td></tr><tr><td>6.2 Mismatch Errors and Layout Floorplan</td><td>86</td></tr><tr><td>6.2.1 Pseudo-Double Centroid Placement Method</td><td>87</td></tr><tr><td>6.2.2 Layout Floorplan</td><td>93</td></tr><tr><td>6.3 Design and Layout of Each Block</td><td>96</td></tr><tr><td>6.3.1 Digital Delay Line</td><td>96</td></tr><tr><td>6.3.2 Mode Selection</td><td>98</td></tr><tr><td>6.3.3 Routing Matrix</td><td>98</td></tr><tr><td>6.3.4 Data Drivers</td><td>100</td></tr><tr><td>6.3.5 Clock Tree and Output Tree</td><td>104</td></tr><tr><td>6.3.6 Unit Current Cell</td><td>106</td></tr><tr><td>6.3.7 Biasing circuits</td><td>110</td></tr><tr><td>6.4 Summary and Conclusions</td><td>114</td></tr></table>

7 Measurement Results of FIR DAC Prototype

115

<table><tr><td>7.1 Experimental Setup</td><td>116</td></tr><tr><td>7.1.1 PCB Design</td><td>116</td></tr><tr><td>7.1.2 Input Data Generation</td><td>119</td></tr><tr><td>7.2 Measured Results</td><td>120</td></tr><tr><td>7.2.1 Biasing Circuits</td><td>121</td></tr><tr><td>7.2.2 Power Consumption</td><td>122</td></tr><tr><td>7.2.3 IEEE 802.11ac Mode</td><td>124</td></tr><tr><td>7.2.4 IEEE 802.11ad Mode</td><td>129</td></tr><tr><td>7.2.5 Characterization of the FIR DAC for f<sub>CLK</sub> beyond 600 MHz</td><td>132</td></tr><tr><td>7.2.6 Comparison with the State of the Art</td><td>134</td></tr></table>
<table><thead><tr><th>viii</th><th>Contents</th></tr></thead><tbody><tr><td>7.3 Conclusions</td><td>135</td></tr><tr><td><b>8 Conclusions and Future Directions</b></td><td><b>137</b></td></tr><tr><td><b>Appendix</b></td><td><b>139</b></td></tr><tr><td>.1 Transmitter Chain Simulation in Matlab</td><td>139</td></tr><tr><td>.1.1 IEEE 802.11ac Transmitter Baseband</td><td>139</td></tr><tr><td>.1.2 IEEE 802.11ad Transmitter Baseband</td><td>143</td></tr><tr><td>.2 EVM Simulation</td><td>144</td></tr><tr><td>.2.1 Code for EVM Simulation of 802.11ac</td><td>144</td></tr><tr><td><b>Bibliography</b></td><td><b>149</b></td></tr><tr><td><b>List of Publications</b></td><td><b>159</b></td></tr><tr><td><b>Abstract en Français</b></td><td><b>161</b></td></tr></tbody></table>
List of Figures

<table><tbody><tr><td>2.1</td><td>Evolution of theoretical data rates of wireless technologies from first generation networks to current giga-bit data rate 4G networks</td><td>6</td></tr><tr><td>2.2</td><td>Mobile data traffic by 2020 as predicted by Cisco in [CVM16]. Global mobile data traffic is expected to grow eightfold between 2015 and 2020 with a compound annual growth rate of 53%</td><td>7</td></tr><tr><td>2.3</td><td>Expected IMT-2020 capabilities as compared with those of IMT-Advanced [ITU15]</td><td>8</td></tr><tr><td>2.4</td><td>A 5G device will have to support multiple existing RATs and new ones. The expected capabilities that different parts of the device are shown here[Ban+14b]</td><td>9</td></tr><tr><td>2.5</td><td>Block diagram of a configurable transceiver for WiFi and WiGig applications</td><td>10</td></tr><tr><td>3.1</td><td>Essentials blocks of a basic WLAN transmitter. In traditional transmitter, the mixer follows the DAC. However, they can also be implemented in the same circuit.</td><td>14</td></tr><tr><td>3.2</td><td>Constellation diagrams of 16-QAM modulation in 802.11ac and 802.11ad standards, and π/2-QPSK modulation of the LP SC mode of the 802.11ad standard</td><td>16</td></tr><tr><td>3.3</td><td>Basic blocks in the generation of one OFDM symbol</td><td>16</td></tr><tr><td>3.4</td><td>PSD of a 160 MHz, 802.11ac OFDM symbol using a hann window</td><td>17</td></tr><tr><td>3.5</td><td>Time domain plot of a 160 MHz, 802.11ac OFDM symbol</td><td>17</td></tr><tr><td>3.6</td><td>Direct Conversion transmitter</td><td>19</td></tr><tr><td>3.7</td><td>Heterodyne transmitter</td><td>19</td></tr><tr><td>3.8</td><td>General block diagram of a polar transmitter</td><td>20</td></tr><tr><td>3.9</td><td>The ACPR is defined based on the spacing of the main, adjacent and alternate channels in this figure. The ACPR and Alternate CPR measurement results of Chapter 7 are also consistent with this definition.</td><td>22</td></tr><tr><td>3.10</td><td>Block diagram of the digital quadrature mixer based on LPF ΔΣ modulator in [Fra+09]</td><td>24</td></tr><tr><td>3.11</td><td>Block diagram of the DDRM in [Elo+07]</td><td>25</td></tr><tr><td>3.12</td><td>Block diagram of the digital-IF direct conversion transmitter in [JS07]</td><td>26</td></tr><tr><td>3.13</td><td>Block diagram of the digital-IF transmitter with embedded FIR filtering RF DAC in [Tal+08]</td><td>27</td></tr><tr><td>3.14</td><td>Block diagram direct conversion transmitter architecture for IEEE 802.11ac based on LPF FIR DAC</td><td>32</td></tr></tbody></table>
<table>
  <tbody>
    <tr>
      <td>3.15</td>
      <td>Block diagram direct conversion transmitter architecture with upconverted ΔΣ input to a BPF FIR DAC. r is ratio of f<sub>IF</sub> to f<sub>CLK</sub>.</td>
      <td>33</td>
    </tr>
    <tr>
      <td>3.16</td>
      <td>Block diagram of digital-IF transmitter architecture based on ΔΣ BPF/HPF FIR DAC</td>
      <td>33</td>
    </tr>
    <tr>
      <td>4.1</td>
      <td>Time domain operation of a DAC</td>
      <td>36</td>
    </tr>
    <tr>
      <td>4.2</td>
      <td>Frequency domain operation of a DAC</td>
      <td>36</td>
    </tr>
    <tr>
      <td>4.3</td>
      <td>Metrics of the dynamic performance of a DAC</td>
      <td>38</td>
    </tr>
    <tr>
      <td>4.4</td>
      <td>A N-bit R-2R resistance ladder DAC</td>
      <td>39</td>
    </tr>
    <tr>
      <td>4.5</td>
      <td>A N-bit resistor string DAC</td>
      <td>40</td>
    </tr>
    <tr>
      <td>4.6</td>
      <td>A thermometric current steering DAC</td>
      <td>40</td>
    </tr>
    <tr>
      <td>4.7</td>
      <td>A segmented current steering DAC</td>
      <td>41</td>
    </tr>
    <tr>
      <td>4.8</td>
      <td>A general L-bit, N-tap FIR DAC architecture</td>
      <td>43</td>
    </tr>
    <tr>
      <td>4.9</td>
      <td>Impulse response of LPF FIR and its frequency translated HPF version</td>
      <td>45</td>
    </tr>
    <tr>
      <td>4.10</td>
      <td>Magnitude response of LPF FIR and its frequency translated HPF version</td>
      <td>45</td>
    </tr>
    <tr>
      <td>4.11</td>
      <td>Impulse response of LPF FIR and its frequency translated BPF version</td>
      <td>46</td>
    </tr>
    <tr>
      <td>4.12</td>
      <td>Magnitude response of LPF FIR and its frequency translated BPF version</td>
      <td>47</td>
    </tr>
    <tr>
      <td>4.13</td>
      <td>Transformation of a 1-bit FIR DAC from LPF to BPF and HPF using a configurable delay line</td>
      <td>47</td>
    </tr>
    <tr>
      <td>4.14</td>
      <td>An optimized configurable delay line with only 2(N − 1) switches and 2N − 1 delay cells.</td>
      <td>48</td>
    </tr>
    <tr>
      <td>4.15</td>
      <td>Current-mode FIR DAC architecture in [SW93]</td>
      <td>50</td>
    </tr>
    <tr>
      <td>4.16</td>
      <td>Current steering FIR DAC architecture in [AR01]</td>
      <td>51</td>
    </tr>
    <tr>
      <td>4.17</td>
      <td>General structure of the reconfigurable bandpass FIR power DAC architecture in [Fla+08]</td>
      <td>52</td>
    </tr>
    <tr>
      <td>4.18</td>
      <td>Current-steering structure for implementing a FIR DAC</td>
      <td>53</td>
    </tr>
    <tr>
      <td>4.19</td>
      <td>Impulse response of the 802.11ad FIR DAC. The values from Equation (4.11)</td>
      <td>55</td>
    </tr>
    <tr>
      <td>4.20</td>
      <td>The change in passband ripple is small as predicted. The transfer function can withstand coefficient mismatches up to 14%, and still fulfill the stopband attenuation with at least 5 dB margin. The percentage yield is plotted against random coefficient mismatch of unary current sources with coefficients realized as a sum of independent unary current sources.</td>
      <td>56</td>
    </tr>
    <tr>
      <td>4.21</td>
      <td></td>
      <td>57</td>
    </tr>
    <tr>
      <td>4.22</td>
      <td>a) Differentially switched cascode current source, b) Small signal model to find the output-referred noise due to I&#773;<sub>n1</sub></td>
      <td>60</td>
    </tr>
    <tr>
      <td>4.23</td>
      <td>Small signal model to find the output-referred noise due a) I&#773;<sub>n2</sub> b) I&#773;<sub>n3</sub></td>
      <td>61</td>
    </tr>
    <tr>
      <td>5.1</td>
      <td>The transmit masks of the IEEE 802.11ac and IEEE 802.11ad standards</td>
      <td>67</td>
    </tr>
    <tr>
      <td>5.2</td>
      <td>160 MHz Baseband Signal at 802.11ac Transmitter Input</td>
      <td>69</td>
    </tr>
  </tbody>
</table>
<table><tr><td>5.3</td><td>Proposed transmitter architecture for IEEE 802.11ac/ad standards and the DSP part of the 802.11ac</td><td>71</td></tr><tr><td>5.4</td><td>Schematic of the multiplierless half-band filter with coefficients of sub-filter F1 shown</td><td>73</td></tr><tr><td>5.5</td><td>Schematic of the sub-filter F2 with its 14 long coefficients</td><td>73</td></tr><tr><td>5.6</td><td>The frequency responses of the main interpolation by two half-band filter and its sub-filters</td><td>74</td></tr><tr><td>5.7</td><td>Signal at the Output of Half-band Filters for 160 MHz Input</td><td>75</td></tr><tr><td>5.8</td><td>Output of Zero-Order-Hold for 160 MHz Baseband Input</td><td>75</td></tr><tr><td>5.9</td><td>Schematic of a 3<sup>rd</sup>-order, 1-bit Delta-Sigma modulator with CRFB topology</td><td>76</td></tr><tr><td>5.10</td><td>Noise and signal transfer functions of the 3<sup>rd</sup>-order, 1-bit Delta-Sigma modulator with CRFB topology</td><td>76</td></tr><tr><td>5.11</td><td>The output of the 802.11ad FIR DAC for 6-bit quantized and 16-bit quantized coefficients. The output fulfills the transmit mask requirements with more than 15dB margin.</td><td>77</td></tr><tr><td>5.12</td><td>The FIR DAC filter roll-off cancels the rising quantization noise from the ΔΣ-modulator output in the 160MHz mode of the 802.11ac</td><td>78</td></tr><tr><td>5.13</td><td>Simulated EVM with 16-QAM modulation in the 160MHz mode of the 802.11ac</td><td>79</td></tr><tr><td>5.14</td><td>The transfer function of the 160MHz of the 802.11ac mode with a unit coefficient mismatch of 1.7% standard deviation.</td><td>81</td></tr><tr><td>5.15</td><td>The transfer functions and impulse responses of the 20/40/80 MHz, 160 MHz of the 802.11ac and the LP SC 802.11ad mode. The samples in the impulse responses are scaled according to the number of unit coefficient elements required to implement each coefficient.</td><td>82</td></tr><tr><td>6.1</td><td>FIR DAC block diagram</td><td>86</td></tr><tr><td>6.2</td><td>A Pseudo double common-centroid placement for UCC for FIR DAC coefficients. The blue shaded coefficients in the left of the impulse response are placed in the outer sections of each quadrant, and those in green inside. The unmatched center tap is placed in all quadrants.</td><td>88</td></tr><tr><td>6.3</td><td>The placement of the UCCs in II_LEFT and II RIGHT of the UCC array. Two coefficients, C<sub>31</sub> and C<sub>33</sub>, equidistant from the center tap, C<sub>32</sub>, of the 802.11ac impulse response are highlighted. Two fine-tuning 802.11ad only coefficients, C<sub>68</sub> and C<sub>72</sub>, are also highlighted. They are also equidistant from the center tap, C<sub>70</sub>, of the fine-tuning coefficient set.</td><td>90</td></tr><tr><td>6.4</td><td>Systematic error differences between even valued coefficients left and right of the center tap</td><td>91</td></tr></table>
<table><tr><td>6.5</td><td>FIR DAC floorplan. The current mirrors are local and global—LCM and GCM. The data is propagated from the top starting from 63-flip-flop delay line, to 76-multiplexers mode selection, then to 76 drivers. The clock tree has 64-rows and the output is obtained from differential outputs of a 64-row tree.</td><td>94</td></tr><tr><td>6.6</td><td>A section of the UCC array. Dummy UCCs surround the edge of the array as shown. The data, clock, output, bias and select signal lines of the UCC are routed such that the array area is exactly the sum of the areas of the UCCs.</td><td>95</td></tr><tr><td>6.7</td><td>FIKRDAC Layout.</td><td>97</td></tr><tr><td>6.8</td><td>A semi-static Flip-Flop for the delay line of the FIR DAC.</td><td>98</td></tr><tr><td>6.9</td><td>A 2-by-1 multiplexer for mode selection.</td><td>99</td></tr><tr><td>6.10</td><td>This shows how the coefficients of 802.11ad are created from 802.11ac. The number at the top indicate taps of the 802.11ad. Each tap is drives the taps 802.11ac taps listed below it and the taps for fine-tuning from 64–76.</td><td>100</td></tr><tr><td>6.11</td><td>The layout of the digital delay line, routing matrix and the mode selection blocks. One of the inputs of the Muxs is directly connected to the flip-flops whereas the other is connected according to the matrix shown above in the table.</td><td>100</td></tr><tr><td>6.12</td><td>The placement of 254 UCCs of coefficient 32 and a depiction of the routing of the data line from driver to the UCCs.</td><td>101</td></tr><tr><td>6.13</td><td>Model of equivalent impedance of routed data lines for coefficient 32 with 254 UCCs.</td><td>102</td></tr><tr><td>6.14</td><td>RC interconnect models that can be used for fast, less accurate estimation of delay.</td><td>103</td></tr><tr><td>6.15</td><td>The layout view of the a five-stage driver used for the biggest coefficients in the center of the 802.11ac impulse response. Additional stage inserted not to invert the data. Supply connected using parallel thin wires to ensure low current density.</td><td>105</td></tr><tr><td>6.16</td><td>The clock is distributed with a seven stage clock tree to the UCC array, and a single leaf of this tree to the delay line. The inverters in the tree are sized have a fan out of 4. This is kept in the inverter chain to the delay line using dummy inverters.</td><td>106</td></tr><tr><td>6.17</td><td>The layout view of the final stage buffers of the clock tree. Each PMOS and NMOS are sized 2<sup>6</sup> times the first stage transistors. The fingers are arranged as such so that the clock tree outputs of each of the 64 rows are routed straight to the UCC array with short wires and with minimum distance between the rows of the UCC array.</td><td>107</td></tr><tr><td>6.18</td><td>The layout view of the clock tree.</td><td>107</td></tr><tr><td>6.19</td><td>Transistor level schematic of a Unit Current Cell which works in 802.11ac mode and is controlled by SEL signal to turn-off in 802.11ad.</td><td>108</td></tr><tr><td>6.20</td><td>The layout view of a unit current cell used in both modes.</td><td>109</td></tr></table>
<table><tr><td>6.21</td><td>A simple Cascode current mirror and small signal analysis of its output resistance</td><td>111</td></tr><tr><td>6.22</td><td>Cascode current mirror biased with two branches</td><td>111</td></tr><tr><td>6.23</td><td>Sooch cascode current mirror for local and global biasing</td><td>112</td></tr><tr><td>6.24</td><td>A simulation of minimum bias VDD that ensures flat current gain</td><td>114</td></tr><tr><td>7.1</td><td>Configurable FIR DAC prototype die micrograph. It is fabricated in ST 28nm CMOS FDSOI.</td><td>115</td></tr><tr><td>7.2</td><td>Schematic of test board and the test board with the packaged die on board. The high speed input and outputs are connected with SMAs, and power connectors were used for the static signals.</td><td>117</td></tr><tr><td>7.3</td><td>Instruments used in the measurement Setup</td><td>118</td></tr><tr><td>7.4</td><td>The test bench</td><td>118</td></tr><tr><td>7.5</td><td>The transmitter architecture used to generate 802.11ac data for the chip characterization</td><td>119</td></tr><tr><td>7.6</td><td>Transfer functions of the 802.11ac and 802.11ad modes with reference current 2.7μA and load resistance of 50Ω. The passband is expected to be attenuated by around 6.5 dB and 10 dB in the 802.11ac and 802.11ad modes respectively.</td><td>120</td></tr><tr><td>7.7</td><td>The biasing voltages of the current source of the UCC, and the current gain, <i>I</i><sub>UCC</sub>/<i>I</i><sub>REF</sub>, for different values of the biasing voltage supply. The current gain plat</td><td>121</td></tr><tr><td>7.8</td><td>Power consumption of the digital circuits, supplied by VDD<sub>DIG</sub>, of the FIR DAC chip at different clock frequencies in the 802.11ac mode and in the 802.11ad modes.</td><td>122</td></tr><tr><td>7.9</td><td>Output of the FIR DAC for a ΔΣ input in the 802.11ac mode. It is measured at a clock frequency of 600 MHz.</td><td>125</td></tr><tr><td>7.10</td><td>Output of the FIR DAC for a thrice oversampled ΔΣ input in the 802.11ac mode. It is measured at a clock frequency of 100 MHz.</td><td>125</td></tr><tr><td>7.11</td><td>Filtered output at 50 MHz and 600 MHz clock of a PRBS input generated from the DTG</td><td>126</td></tr><tr><td>7.12</td><td>Passband AND Stopband ripple deviations for a PRBS input in the 802.11ac mode</td><td>127</td></tr><tr><td>7.13</td><td>The signal used as an input for this experiment, b) The measured plot, and c) SFDR in dBc in the bandwidth of the FIR DAC for a clock frequency of 600 MHz.</td><td>128</td></tr><tr><td>7.14</td><td>Filtered output at 200 MHz clock in the 802.11ad mode for a PRBS input generated from the DTG</td><td>129</td></tr><tr><td>7.15</td><td>Filtered output at 200 MHz clock in the 802.11ad mode for a PRBS input generated from the DTG</td><td>130</td></tr><tr><td>7.16</td><td>Time domain measurement for an input sequence at a clock frequency of 10 MHz.</td><td>130</td></tr></table>
<table><tr><td>7.17 Filtered output at 1 GHz and 1.4 GHz clock frequencies of a PRBS input generated from the DTG</td><td>131</td></tr><tr><td>7.18 Output of the FIR DAC for a thrice oversampled ΔΣ input in the 802.11ac mode. It is measured at a clock frequency of 2.4 GHz. The input digital pattern DATA from the data timing generator is shown in yellow, and the measured output in blue.</td><td>132</td></tr><tr><td>7.19 Channel power, ACPR, and alternate CPR measurements across different clock frequencies for a ΔΣ output pattern as an input to the FIR DAC in the 802.11ac mode.</td><td>133</td></tr><tr><td>7.20 Out-of-band profile of the fundamental and image stop bands measured at two points for a ΔΣ output signal as an input. The effect of ZOH clocking on these two stop bands is also shown.</td><td>133</td></tr></table>
List of Tables

<table><tbody><tr><td>3.1</td><td>Summary of the reviewed digital transmitters</td><td>28</td></tr><tr><td>3.2</td><td>A summary of RF DACs for cable TV transmitters</td><td>30</td></tr><tr><td>4.1</td><td>Comparison among the three structures of an FIR DAC</td><td>44</td></tr><tr><td>4.2</td><td>Switch states of delay line for frequency translation of the 1-bit FIR DAC</td><td>48</td></tr><tr><td>5.1</td><td>Summary of the Specifications of the 802.11ac and 802.11ad standards</td><td>67</td></tr><tr><td>5.2</td><td>Frequency Planning for IEEE 802.11ac/ad Transmitter</td><td>72</td></tr><tr><td>5.3</td><td>Summary of the specifications of the multi-standard FIR DAC</td><td>83</td></tr><tr><td>6.1</td><td>Weights of the 802.11ad mode fine-tuning coefficients</td><td>99</td></tr><tr><td>7.1</td><td>Power Consumption of the FIR DAC chip in two modes</td><td>123</td></tr><tr><td>7.2</td><td>Comparison with the state of the art in digital-to-RF converters of all-digital transmitters</td><td>134</td></tr><tr><td>7.3</td><td>Performance summary of the configurable FIR DAC</td><td>135</td></tr></tbody></table>
# Nomenclature

## SYMBOLS

* $\omega$ & $f$ Angular frequency & frequency

* $\sigma$ Standard Deviation

* $A_p$ Passband Ripple

* $A_{st}$ Stopband Ripple

* $f_{out}$ Output Frequency

* $f_s$ Sampling rate, also clock frequency

* $g_m$ Transconductance

* $g_{ds}$ & $r_o$ Drain-to-source conductance & resistance

* $L$ Transistor length

* $P_{out}$ Output Power

* $V_{OV}$ Overdrive voltage

* $W$ Transistor width

## ABBREVIATIONS

* **1G** First Generation Wireless Communication

* **3G** Third Generation Wireless Communication

* **4G** Fourth Generation Wireless Communication

* **5G PPP** 5G Infrastructure Public Private Partnership

* **5GNOW** Fifth Generation Non-Orthogonal Waveforms for Asynchronous Signalling

* **5G** Fifth Generation Wireless Communication

* **ACPR** Adjacent Channel Power Ratio

* **AM** Amplitude Modulation

* **ASK** Amplitude Shift Keying

* **BPF** Band Pass Filter

* **BPSK** Binary Phase Shift Keying

* **BW** Signal Bandwidth

* **CDMA** Code Division Multiple Access

* **CIFB** Cascade-of-Integrators, Feedback Form

* **CMOS** Complementary Metal Oxide Semiconductor
<table><tr><td>CRFB</td><td>Cascade-of-Resonators, FeedBack Form</td></tr><tr><td>CVSL</td><td>Cascode Voltage Switch Logic</td></tr><tr><td>DAC</td><td>Digital to Analog Converter</td></tr><tr><td>DBPSK</td><td>Differential Binary Phase Shift Keying</td></tr><tr><td>DCO</td><td>Digitally Controlled Oscillator</td></tr><tr><td>DC</td><td>Direct Current</td></tr><tr><td>DIDIMO</td><td>Direct Digital Modulation</td></tr><tr><td>DMG</td><td>Directional Multi Gigabit</td></tr><tr><td>DNL</td><td>Differential Non-Linearity</td></tr><tr><td>DR</td><td>Dynamic Range</td></tr><tr><td>DSP</td><td>Digital Signal Processing</td></tr><tr><td>EDGE</td><td>Enhanced Data rates for GSM Evolution</td></tr><tr><td>ETSI</td><td>Mobile and wireless communications Enablers for the Twenty-twenty Information Society</td></tr><tr><td>EVM</td><td>Error Vector Magnitude</td></tr><tr><td>FDMA</td><td>Frequency Division Multiple Access</td></tr><tr><td>FDSOI</td><td>Fully Depleted Silicon On Insulator</td></tr><tr><td>FEC</td><td>Forward Error Correction</td></tr><tr><td>FIR</td><td>Finite Impulse Response</td></tr><tr><td>FM</td><td>Frequency Modulation</td></tr><tr><td>FSK</td><td>Frequency Shift Keying</td></tr><tr><td>GCD</td><td>Greatest Common Divisor</td></tr><tr><td>GPS</td><td>Global Positioning System</td></tr><tr><td>GSM</td><td>Global System for Communications</td></tr><tr><td>HDMI</td><td>High Definition Multimedia Interface</td></tr><tr><td>HD</td><td>Harmonic Distortion</td></tr><tr><td>HPF</td><td>High Pass Filter</td></tr><tr><td>I/Q</td><td>Inphase-Quadrature</td></tr><tr><td>IDFT</td><td>Inverse Discrete Fourier Transform</td></tr><tr><td>IFFT</td><td>Inverse Fast Fourier Transform</td></tr><tr><td>IF</td><td>Intermediate Frequency</td></tr><tr><td>IIR</td><td>Infinite Impulse Response</td></tr><tr><td>IMD3</td><td>Third-Order Intermodulation</td></tr><tr><td>INL</td><td>Integral Non-Linearity</td></tr></table>
<table><tr><td>ISI</td><td>Intersymbol Interference</td></tr><tr><td>LO</td><td>Local Oscillator</td></tr><tr><td>LP</td><td>Low Power</td></tr><tr><td>LSB</td><td>Least Significant Bit</td></tr><tr><td>LTE-AG</td><td>Long Term Evolution Advanced</td></tr><tr><td>MAC</td><td>Media Access Control</td></tr><tr><td>MCS</td><td>Modulation and Coding Scheme</td></tr><tr><td>MIMO</td><td>Multiple Input and Multiple Output</td></tr><tr><td>MU-MIMO</td><td>Multi-User MIMO</td></tr><tr><td>NRZ</td><td>Non-Return to Zero</td></tr><tr><td>NTF</td><td>Noise Transfer Function</td></tr><tr><td>OFDM</td><td>Orthogonal Frequency Division Multiplexing</td></tr><tr><td>OSR</td><td>Oversampling Ratio</td></tr><tr><td>PAPR</td><td>Peak to Average Ratio</td></tr><tr><td>PA</td><td>Power Amplifier</td></tr><tr><td>PDAC</td><td>Power DAC</td></tr><tr><td>PHY</td><td>Physical layer</td></tr><tr><td>PLL</td><td>Phase Locked Loop</td></tr><tr><td>PM</td><td>Phase Modulation</td></tr><tr><td>PRBS</td><td>Pseudo-Random Bit Stream</td></tr><tr><td>PSD</td><td>Power Spectral Density</td></tr><tr><td>PSK</td><td>Phase Shift Keying</td></tr><tr><td>QAM</td><td>Quadrature Amplitude Modulation</td></tr><tr><td>QFN</td><td>Quad Flat Non Leaded</td></tr><tr><td>QPSK</td><td>Quadrature Phase Shift Keying</td></tr><tr><td>RAT</td><td>Radio Access Technology</td></tr><tr><td>RRC</td><td>Root Raised Cosine</td></tr><tr><td>RZ</td><td>Return to Zero</td></tr><tr><td>SC</td><td>Single Carrier</td></tr><tr><td>SDR</td><td>Signal to Distortion Ratio</td></tr><tr><td>SFDR</td><td>Spurious Free Dynamic Range</td></tr><tr><td>SNR</td><td>Signal to Noise Ratio</td></tr><tr><td>STA</td><td>Station</td></tr><tr><td>TDMA</td><td>Time Division Multiple Access</td></tr></table>
**TPSC** True Single Phase Clock

**UCC** Unit Current Cell

**UMTS** Universal Mobile Telecommunications System

**VCO** Voltage Controlled Oscillator

**VHT** Very High Throughput

**WCDMA** Wideband Code Division Multiple Access

**WENDY** WiGig FlExible TraNsceiver ADvanced SYstem

**WiGig** Wireless Gigabit

**WiGig** Wireless Gigabit

**WiHD** Wireless High Definition

**WiMAX** Worldwide Interoperability for Microwave Access

**WLAN** Wireless Local Area Network

**ZOH** Zero Order hold
# Introduction

## 1.1 The Scope of this Study

The aim of this work has been to analyze, design, and demonstrate a digital-to-IF/RF converter circuit that can be configured for processing both high resolution, medium bandwidth and low resolution, wideband baseband signals of recent WiFi standards. Initially, FIR DACs were proposed as ideal blocks to achieve the required design objectives, such as low power consumption and small area, of such a mixed-signal circuit block. Along the course of this PhD work, however, the work has evolved to study and determine how much a performance can be expected from the digital signal processing blocks in a baseband of such transmitters.

The initial goal of this work was to validate at system-level a transmitter baseband architecture for processing IEEE 802.11ac and IEEE 802.11ad signals. Subsequently, given time constraints, it was important to demonstrate a key circuit block, by measuring a CMOS implementation, of the multi-standard transmitter architecture proposed. A configurable FIR DAC was identified as the bottleneck in the transmitter chain as it determines the maximum achievable carrier frequency and the corresponding signal bandwidth, spectral purity of the analog output, and the lowest power consumption and circuit area that can be targeted.

Even though the solid literature in the area of traditional multi-bit DAC has eased the burden of derivation required in the design of a configurable multi-standard FIR DAC, the scarcity of works in the specific area of high speed configurable FIR DACs required analysis of each design decision and has led to some original contributions.

A top-down research methodology was followed during implementation of the FIR DAC chip. The specifications for the baseband transmitter system were based largely on IEEE 802.11ac and IEEE 802.11ad transmitter standard requirements. Specification for each block in the baseband chain, mainly the FIR DAC block, were then drawn; and those were translated as targets for the parameters of the FIR DAC circuit. Then, simulation at transistor, layout and extracted abstraction levels were carried out until the desired margin was respected.
1.2 Original contributions

These are the main original contributions of this PhD work:

* Novel digital wireless transmitter architectures based on:
  - low pass filter FIR DAC

- high pass filter FIR DAC

- band pass filter FIR DAC

* System-level validation of a configurable low pass filter FIR DAC transmitter as communicated in [GFK16a]

* A semi-digital FIR DAC for LP SC 60 GHz IEEE 802.11ad as communicated in [GFK15]

* Matlab based modeling and simulation algorithms for EVM of a IEEE 802.11ac/ad transmitter

* A delay-line of a 1-bit FIR DAC configurable for a LPF/BPF/HPF operations

* Thorough small-signal analysis of the noise-limited dynamic range of a differentially-switched cascode current source

* A novel pseudo double common centroid placement method for unary-implementation of a FIR DAC as communicated in [GFK16b]
  - Analysis of its bandwidth limitation

- A novel floorplan based on this placement method

* A yield model for thermometric FIR DACs based on stopband rejection of their filtering transfer function

* Design of a prototype FIR DAC that
  - is configurable for 160MHz channel bandwidth of the IEEE 802.11ac and IEEE 802.11ad standards

- proves for the first time a low power, multi-GHz operation of a 63-order 1-bit high pass filtering FIR DAC

* The prototype high pass FIR DAC chip is characterized up to a clock frequencies of 3 GHz in the 802.11ac mode, consumes 103.07 mW at 1.4 GHz, and can process passband OFDM signals as wide as 136 MHz. In the 802.11ad case, it can processes SC signals up to a bandwidth of 700 MHz at a clock frequency of 1.4 GHz and consumes 86.89 mW.
**1.3 Outline**

The work is divided into eight chapters as follows:

* Chapter 1: introduces the problem statement the work has tried to solve. It sets the scope of the study, lists the main original contributions, and gives an outline of the dissertation.

* Chapter 2: examines the historical background of the application area of this work. It recapitulates the predictions related to the capabilities of future 5G standards, and introduces the principal challenges and solutions. The chapter puts the application of this PhD work in perspective with the predicted possible evolution of radio systems.

* Chapter 3: briefly introduces theoretical operation of a modern wireless transmitter. It reviews digital cartesian transmitter architectures. It further delves into review of multi-modal digital transmitters architectures in recently published works. The chapter closes with a proposal of novel FIR DAC based multi-modal transmitter architectures.

* Chapter 4: starts with basics of a traditional multi-bit DAC: its operation, specifications, and architectures. Then it follows it with a general discussion of the design challenges of L-bit, N-tap FIR DACs. It introduces a novel configurable delay-line for a 1-bit FIR DAC. A thorough review of published transmitter-side filtering DACs paves the way for analysis of high speed 1-bit FIR DAC design. Main performance metrics of a 1-bit current-steering FIR DAC architecture and its modeling is derived.

* Chapter 5: presents the system-level validation of the baseband of a digital transmitter based on a low pass filter FIR DAC. High level design and simulation results of each block of the transmitter are included. The chapter ends with further discussion of the high level design of a configurable FIR DAC.

* Chapter 6: details the circuit implementation of a prototype configurable FIR DAC in 28nm CMOS FDSOI. A novel pseudo double common centroid placement method, and the FIR DAC floorplan are discussed. Design of each block of the prototype converter are presented in great detail.

* Chapter 7: is where the results of the measurement of the prototype are explored. The experimental setup, the different ways by which the configurable FIR DAC is characterized are elaborated.

* Chapter 8: stipulates the main conclusions. It also extends the scope of this work by proposing plausible future research directions.
# Wireless Communication Systems

The aim of this chapter is to give an overview of wireless communication standards. It covers a bit of history and a bit of the expected future of communication standards. Since the focus of this work is on multi-mode DAC for multi-standard transmitters, some motivations are listed in this chapter. It starts with evolution of standards in section I. In section II, a discussion of challenges and solutions with regard to 5G networks is included. The prototype chip targets the complementarity that exists in the WiFi-WiGig use cases; it is in section 3. The chapter closes with a customary summary and conclusions section.

## 2.1 Aggregation of Standards

Cellular technology has evolved from the analog, voice only 1G to the current Gb/s data rate LTE-A 4G standard. To accommodate this increase in throughput, the transmission frequencies has also increased from sub-GHz carrier frequency to 2–3 GHz range that is at work today. However, this increase is not totally attributed to increase in available transmission bandwidth. One technology that contributed to this increase is the evolution of access technologies from FDMA to TDMA to CDMA to contemporary access technology based on OFDM.

The same can be said of the evolution of the WLAN standards, namely WiFi. It has evolved from the early 2 Mb/s data rate local area network to the current multi-Gb/s 802.11ac/ad standards. Other standards including short distance, low power Zigbee and Bluetooth, and long distance, low data rate GPS still add their own set of requirements on the design of devices.

Therefore, the proliferation of application specific wireless communication standards have resulted in the multiple standards, multiple devices per user scenario of today. The need for design of multi-standard devices is exacerbated by the crowded spectrum, and the resulting tough out-of-band requirements. Moving to higher carrier frequency, and, thus, broader bandwidths could relax the requirements, and fulfill the increasing demand for faster communication rates. However, the challenges of designing multi-standard devices at higher carrier frequencies or broader bandwidths will be harder to overcome.

Innovation in access technologies, similar to the gains made by using OFDM, will not suffice either. A single innovation in either of transmission frequency, access technologies, channel bandwidth, or type
<figure><img src="image_7.png" /><figcaption>Figure 2.1: Evolution of theoretical data rates of wireless technologies from first generation networks to current giga-bit data rate 4G networks</figcaption></figure>

of antenna may not satisfy the expected needs. A radical change combining all of the above solutions
have a better probability of addressing the problem.

The evolution of theoretical data rates of cellular and WiFi standards through the years is plotted in Figure 2.1. The latest standards of WiFi achieve several Gb/s data rates—with the 802.11ac at 160MHz and the IEEE 802.11ad at 2.16GHz maximum channel bandwidths. The uplink and downlink data rates of the latest cellular standard also reaches Gb/s with a maximum of 20MHz channel bandwidth. There is, however, a difference in the achievable distance between these standards. For example, IEEE 802.11ad has an expected reach of less than 10 m. Future networks can be envisioned where the capabilities in both short and long distance standards are combined seamlessly for best user experience. In the next section, a brief summary of the discussion on future 5G networks is presented.

## 2.2 Networks of the future

Current networks are not expected to support the data demand of the future. This is because of the explosive rise in user data demand coupled with the increasing number of new applications that require low latency, high data rate communications. The 2015 virtual networking index report by Cisco shows that 4G mobile networks account for 47% of mobile data traffic with just 14% of mobile connections while 3G networks contribute for 43% traffic with 34% of connections. In general, a 4G traffic takes the biggest share with 85% more traffic than a non-4G connection. It also reports an increase of more than half a billion in global mobile devices and connections in 2015. Although the growth in mobile data and
increase in mobile devices does not imply similar proportion of growth in other networks, it does show the exponential demand for faster data. The mobile data traffic growth from 2015 to 2020 is shown in Figure 2.2 [CVM16].

These exponential demands have pushed many governing bodies to plan for the networks of the future. Flagship projects such as METIS 2020 project, 5GNOW, and 5G PPP in Europe, and IMT-2020 under the International Telecommunication Union have led the way for the development and standardization of 5G networks—a generic name for the networks of 2020.

<figure><img src="image_8.png" /><figcaption>Figure 2.2: Mobile data traffic by 2020 as predicted by Cisco in [CVM16]. Global mobile data traffic is expected to grow eightfold between 2015 and 2020 with a compound annual growth rate of 53%</figcaption></figure>

Although a clear set of requirements have not yet been developed for what the 5G networks should look like, there are some targets which show the capacity of the networks of the future. Under the IMT-2020, initiative, the expected capabilities and needed enhancement compared against the current IMT-Advanced are depicted graphically in Figure 2.3.

The METIS project, in its initial project, had also set five requirements that a mobile network in 2020 should support with the same cost and energy dissipation of contemporary networks. These are 1000x increase in mobile data throughput, 10 to 100x increase in number of connected devices and increase in user data, 10x longer battery life for low power massive machine communication, and 5x reduced end-to-end latency [Ola15]. These are achievable objectives with the technologies available today, but require innovation at the network, system and architecture levels.

Some of the techniques that has been mentioned for meeting these requirements include increase in bandwidth by moving to new unincensed spectrum, denisification of networks with shorter transmission distance, massive MIMO with greater antenna elements, more efficient transmission schemes to improve OFDM, and flexible radio interfaces [Ola15].
<figure><img src="image_9.png" /><figcaption>Figure 2.3: Expected IMT-2020 capabilities as compared with those of IMT-Advanced [ITU15]</figcaption></figure>

### 2.2.1 Challenges and Solutions

Many of the proposed solutions are an extension of the current technologies. Still, there are many challenges that have to be overcome. A good depiction of the capabilities of a 5G device, with a focus to the communication block, is in Figure 2.4. It shows the challenges and the expected innovations at different parts of the device. For example, of interest to the scope of this work are the number of RATs the transceiver baseband is expected to process, the multi-standard design at the RF parts of the transceiver and the resulting challenges at the front-end module, and the expected challenges of a multi-antenna operation. In this subsection, a brief discussion of the challenges and solutions proposed for future 5G networks are presented.

One of the proposed solutions to free up spectrum and serve more users is decreasing the distance between base stations also called densification. While this allows the incorporation of short-distance communication standards in the 5G network, it faces some challenges, among which the cost of increased infrastructure due to deployment of large number of base stations within small area, and the support of fast and efficient handoff in an environment where there are many RATs [And+14].

A more viable solution for future high data rate networks is increasing bandwidth in an unlicensed spectrum. The challenges to this solution in the PHY layer are design of power efficient and small form factor transceiver architectures that can support MU-MIMO, and antennas that overcome the propagation
<figure><img src="image_10.png" /><figcaption>Figure 2.4: A 5G device will have to support multiple existing RATs and new ones. The expected capabilities that different parts of the device are shown here [Ban+14b].</figcaption></figure>

loss and atmospheric absorption at mm-waves. These challenges are already being tackled by circuit and antenna designers at this time to some degree. Yet, novel architectures may be needed if massive MIMOs are to be part of mobile terminals [Ban+14b].

Another solution for increasing throughput is novel spectral efficient modulation technique and access technology. While OFDM is a widely used modulation technique, it presents drawbacks. One is the high PAPR that limits the linearity and efficiency of power amplifiers although this may not be a critical problem in a dense network where the transmitted signal does not need to have high power. The other is the need for synchronization and the fact that a big part of an OFDM symbol is taken by the guard interval. It is also a usual practice to fill the edge of an OFDM symbol with null subcarriers. This also results in decreasing the spectral efficiency of OFDM. A technology where the advantages of OFDM are kept with improvements on its drawbacks will be important for 5G networks. Some candidate technologies are already being proposed to supercede OFDM in a 5G network. They are discussed in detail in [Ban+14a].

## 2.3 The WiFi-WiGig Complementarity

The 802.11ad was developed from the WiGig MAC and PHY. However, WiGig has now merged with WiFi under the WiFi Alliance and standardized in 802.11ad.

Initially released in 1997, WiFi, as standardized by the IEEE 802.11, has hugely impacted the
medium distance local area and personal communications. The latest flavor, 802.11ac, enables WiFi to keep its medium distance capability and reach multi-Gb/s using MIMO. On the other hand, 802.11ad strengthens WiFi in for low power, short distance applications by increasing its capability to multi-Gb/s data rate without the need for MIMO and using simpler modulation schemes. The two standards have made WiFi an indispensable standard, and a candidate for highly dense future networks [VFC13].

<figure><img src="image_11.png" /><figcaption>Figure 2.5: Block diagram of a configurable transceiver for WiFi and WiGig applications</figcaption></figure>

The 802.11ac and 802.11ad standards have created a good test case for seamless operation of short distance and medium distance communications. Due to its high data rate at low power capabilities, 802.11ad can be used for tasks that require small time duration. For instance, device-to-device data transfer, wireless sync, and wireless display to name a few. Hence, it can be turned on for such tasks. On the contrary, the 802.11ac requires higher power consumption to reach Gb/s data rates. Thus, it is better suited for medium distance, traditional local area network applications.

### 2.3.1 Tri-band WiFi Radio

The 802.11n, 802.11ac and 802.11ad stretch the reach of WiFi from the crowded 2.4 GHz bands, to 5 GHZ, and mm-wave frequencies respectively. Both 802.11ac and 802.11ad are backward compatible. 802.11ac can be considered as a 5 GHz, wide channel bandwidth version of 802.11n. The idea of tri-band radio is to employ 2.4 GHz 802.11n for existing networks, 802.11ac for new faster medium distance applications, and 802.11ad for short distance, low power applications [VL11].

There has been some demonstration of this idea in commercial products with the Intel® Tri-band
Wireless-AC 17265 and WiGig Antenna-M10041R. The research in this area is to maximize hardware sharing between the mm-wave 802.11ad and 5 GHz 802.11ac while guaranteeing good performance.

Under the WENDY project of the French National Research Agency, the idea of tri-band radio was targeted. The objective of the project was to research techniques by which a 60 GHz standard could be part of the WiFi ecosystem with respect to how its use cases are entertained and how its circuits are implemented. It targeted the second generation of WiGig based products—the first being standalone WiGig chipsets. Although WiHD was released earlier than WiGig, it specifically targets video streaming application as HDMI cable replacement and was not suited, for instance, with respect to cost, for wireless transfer of general data of other nature.

To implement a highly integrated, configurable and low power tri-band transceiver, the MAC, digital baseband, and the RF front-end circuits should be configurable for operations in all bands. A common frequency synthesizer can deliver a low phase noise signal to all the baseband and mixing blocks at low power constraints. In the RF front-end, the project investigated among other issues how to:

* digitally process baseband signals ranging from 20 MHz to 2 GHz,

* implement digital-to-analog conversion of those baseband signals, and

* upconvert and downconvert IF and RF transmission frequencies of as diverse as 2.5 GHz, 5 GHz, 20 GHz and 60 GHz.

The general block diagram of the transceiver is shown in Figure 2.5. Prototype chips were fabricated for some parts of the transceiver. In the receiver side, subsampling techniques were employed to solve the problems listed above [GFK13]. In the frequency synthesizer, a wide tuning range mm-wave voltage controlled oscillator was implemented in CMOS 28nm FDSOI [Val+14]. In the transmitter side, it should be understood that the starting objective of this thesis work was to investigate the questions listed above.

## 2.4 Summary and conclusions

An overview of wireless communication standards commensurate with the scope of this dissertation is presented. Special attention has been given to future networks in line with the initial aim of this PhD work. Recent literature on future 5G networks from both academia and industry is briefly introduced with focus on the challenges and proposed solutions.

Finally, a summary of the ANR project, WENDY, under which this work was started is introduced. The objective of the project was to demonstrate next generation tri-band WiFi transceiver. Design of a configurable mixed-signal block in the transmitter part of such a transceiver was the initial goal for this work.
# Multi-standard Digital Transmitters

This chapter investigates the methods that can be implemented for multi-standard transmitter operation. Before that, it will introduce briefly the theoretical operation of a transmitter. Signal processing in cartesian, polar and outphasing transmitter systems is discussed along with modulation schemes. The first section is closed with a highlight of the fundamental transmitter metrics such as transmit mask, EVM, and ACPR.

In the next section, I/Q transmitter architectures are discussed with additional details. It starts with classical architectures such as direct conversion or low-if, heterodyne or two-step transmitter architectures, and ends with a review of modern architectures used in wireless devices. Only the architectures with relevant specs will be discussed.

The last part of this chapter is a theoretical discussion of the possible methods available for implementing a multi-standard transmitter using the traditional architectures. The focus is on the opportunities in the baseband part of the transmitter. Similar to the previous section, this section closes with a mention of recent publications of multi-standard transmitters.

## 3.1 Brief Theory of Transmitter Operation

From the scope of this dissertation, the name transmitter will refer to the blocks in the lower part of Figure 3.1. However, for completeness, a general block diagram of a WLAN transmitter is shown including the MAC layer. The MAC layer prepares the data units that are exchanged with the PHY according to the transmission format of the standard. It adds the necessary header and defines the payload structure for each user. For example, the 802.11ac standard defines a MU-MIMO capability where an access point transmits data units to multiple receiving stations with one or more antennas. In this case, the MAC layer could define multiple independent data units. The data bits are filled in the PHY layer.

The physical layer mainly performs FEC, and modulation in its digital baseband part and, traditionally, frequency translation, digital-to-analog conversion, filtering and amplification in its analog/RF part. Modulation consists of constellation mapping where bit streams are mapped to complex constellation points, and where the complex symbols are converted to time domain blocks. In a single carrier
modulation transmitter, only constellation mapping is done, and the rest of the functions fall under the
responsibility of the analog/RF designer. In other words, they are not necessarily implemented in digital
baseband. That is the case in 802.11ad where the mapped high speed baseband data can be upconverted
and converted to analog without much digital processing (more on this later).

However, advancement in digital signal processors have enabled digital implementation of traditionally analog blocks. The possibility to tune and calibrate digital circuits for best performance have relegated the analog implementation only to the blocks close to the antenna such as the power amplifier or co-existence band pass filter. With this comes the opportunity to implement different standards using one digital hardware. This is the main topic of the final section of this chapter.

<figure><img src="image_12.png" /><figcaption>Figure 3.1: Essentials blocks of a basic WLAN transmitter. In traditional transmitter, the mixer follows the DAC. However, they can also be implemented in the same circuit.</figcaption></figure>

**3.1.1 Modulation**

Modulation is the mapping of information carried in one electrical signal, called the modulating signal, into the amplitude, frequency, and/or phase of another signal, called the carrier. Modulation has many advantages in wireless communication which are well covered in many wireless communication text books [Hay09].

**Single Carrier**

There are three main modulation types. AM is when the modulating signal controls the amplitude of the carrier, it is FM when it controls the frequency, and PM if the modulation is on the phase of the carrier. Both FM and PM are called angle modulation because, ultimately, both phase and frequency variation can be obtained by varying the angle of the carrier. Each modulation types have different bandwidth efficiency. Probability of error versus energy per bit per spectral noise density ($\frac{E_b}{N_0}$) graphs are used for
comparing different modulations schemes.

An analog signal modulated by a single carrier of frequency, $f_c$, can be generally expressed in polar form as:

$$y(t) = a(t)\cos(2\pi f_c t + \theta(t)). \quad (3.1)$$

This can be expanded to:

$$y(t) = a(t)\cos(\theta(t))\cos(2\pi f_c t) - a(t)\sin(\theta(t))\sin(2\pi f_c t). \quad (3.2)$$

The cartesian form of the modulated signal is then:

$$y(t) = x_I(t)\cos(2\pi f_c t) - x_Q(t)\sin(2\pi f_c t). \quad (3.3)$$

Where $x_I(t) = a(t)\cos(\theta(t))$ and $x_Q(t) = a(t)\sin(\theta(t))$. The modulating signal $x(t)$ is generally given by: $x_I(t) + jx_Q(t) = a(t)e^{j\theta(t)}$.

The amplitude $a(t)$ follows the modulating signal, $x(t)$, in AM with no modulating signal information on the phase $\theta(t)$; and the angle $\theta(t)$ varies according to the modulating signal, $x(t)$, in angle modulation with no modulating signal information on the amplitude $a(t)$. In digital modulation, the modulating signal is a sequence symbols. ASK, FSK, and PSK are the digital modulation versions of AM, FM and PM respectively. There are higher order digital modulation schemes such as M-PSK, M-ASK, and M-QAM which are more spectrally efficient. The constellations of 16-QAM and $\frac{\pi}{2}$-QPSK are shown as an example in Figure 3.2.

## OFDM

Modern wireless communication standards such as IEEE 802.11ac rely on different mechanisms to increase spectral efficiency. Higher order modulation schemes are used to reach Gb/s data rates, for example, 256-QAM in 802.11ac. In addition, OFDM is used to increase throughput in a crowded spectrum.

The basic stages in the generation of one OFDM symbol in the baseband of a transmitter is shown in Figure 3.3. The stream of bits are converted to parallel and are mapped to $N$ subcarriers according to the complex constellation points of the modulation scheme selected. Then the orthogonal subcarriers are summed using an IFFT or IDFT block and converted to time domain. A guard interval is inserted at the end of the summed signal to prevent inter-symbol interference due to multi-path propagation. The IFFT output and the guard interval, can be implemented using cyclic prefix, form an OFDM symbol.

An example based on the 802.11ac standard is given in Figure 3.4 and 3.5. The symbol is generated by mapping a random bit stream to 468 16-QAM data subcarriers, 16 pilot subcarriers and the remaining
<figure><img src="image_13.png" /><figcaption>Figure 3.2: Constellation diagrams of 16-QAM modulation in 802.11ac and 802.11ad standards, and π/2-QPSK modulation of the LP SC mode of the 802.11ad standard</figcaption></figure>

<figure><img src="image_14.png" /><figcaption>Figure 3.3: Basic blocks in the generation of one OFDM symbol</figcaption></figure>

of a 512-subcarriers OFDM to zeroes or null subcarriers. The windowed spectral plot of the IFFT output is shown in Figure 3.4. The null subcarriers are placed in the middle of the symbol and at the end as guards subcarriers.

The roles of the remaining transmitter blocks are, basically, converting this signal to analog, frequency translating it to the band allocated to the standard and amplifying it. The first task can be carried out by using multi-bit DAC. The output signal, in time-domain, shown in Figure 3.5, has multi-bit resolution with the high magnitude samples occuring less frequently. The high magnitude samples can be clipped to relax the requirements on the DAC [MSB94]. The SNR loss that results from this process should not degrade the EVM to a degree where the remaining transmitter blocks are put on stringent EVM requirements. Depending on the constellation size, number of subcarriers of the OFDM modulator,
<figure><img src="image_15.png" /><figcaption>Figure 3.4: PSD of a 160 MHz, 802.11ac OFDM symbol using a hann window</figcaption></figure>

<figure><img src="image_16.png" /><figcaption>Figure 3.5: Time domain plot of a 160 MHz, 802.11ac OFDM symbol</figcaption></figure>

the resolution of the DAC could be higher than 10 bits.

Frequency translation of the OFDM modulator output can be carried out in single stage or two-step depending on the transmitter architecture. It can also be implemented by digital upconversion if the mixer precedes the DAC, but this requires an RF DAC. If cartesian transmission is required, then the real and imaginary components of the OFDM output signal has to be transmitted separately using I/Q transmitter architecture [Raz12]. One of the main alterantive is to convert the complex samples to their amplitude and phase components and impart the amplitude on the phase modulated component in the amplifying block or upconversion block in a polar transmitter architecture [Yua03].
### 3.1.2 Cartesian Transmitters Architectures

Frequency translation is basically time-domain multiplication of the baseband output by an exponential signal at the desired carrier frequency, $f_c$. It is generalized by Equations (3.1) and (3.3) for SC signal. Mathematically,

$$y(t) = x(t)e^{j2\pi f_c t} \qquad (3.4)$$

For a complex modulating signal $x(t)$, $y(t)$ can be expressed by expanding the real, $x_I(t)$, and imaginary, $x_Q(t)$, components of $x(t)$ and multiplying by the exponential. Further, the exponential can be expanded using Euler's formula to its trigonometric equivalents:

$$y(t) = (x_I(t) + jx_Q(t)) (\cos(2\pi f_c t) + j\sin(2\pi f_c t)) \qquad (3.5)$$

$$y(t) = x_I(t) \cos(2\pi f_c t) - x_Q(t) \sin(2\pi f_c t) + j(x_Q(t) \cos(2\pi f_c t) + x_I(t) \sin(2\pi f_c t)) \qquad (3.6)$$

Therefore, complex upconversion can be achieved with four multipliers, two adders and a single-tone signal and its 90° shifted component [Mar04]. Downconversion of the transmitted output is easily down by replicating the upconversion process in the receiver. There are practical problems resulting from the difference of the carrier signals in the receiver and transmitter sides, but theoretically $x(t)$ is fully recovered.

In I/Q modulation transmitter, upconversion is carried out with only the real part of Equation (3.4) as shown in Equation (3.7). This is possible because a real upconverted signal has also an image on the negative frequency. If the transmitted output signal is multiplied by the same orthogonal functions, cosine and sine, in the receiver, $x(t)$ can still be recovered after filtering. The clear advantage is the ease of generating the cosine and sine signals and the reduced number of multiplication and additions required. Both $x_I(t)$ and $x_Q(t)$ are translated to $f_c$ and $-f_c$. The downside of using real version of the complex modulation is the image filtering problem in the receiver. Quadrature modulation is then:

$$y(t) = x_I(t) \cos(2\pi f_c t) - x_Q(t) \sin(2\pi f_c t) = \mathfrak{R}[x(t)e^{j2\pi f_c t}] \qquad (3.7)$$

#### Direct Conversion Transmitter

Direct implementation of Equation (3.7) results in a single-step upconversion transmitter architecture, also known as direct conversion transmitter, shown in Figure 3.6. If there is no filter between the summed output of the mixers and the power amplifier, carrier leakage to the output from the mixers could be problematic [Raz12]. Another problem is the receive band noise floor can be affected by the output from
<figure><img src="image_17.png" /><figcaption>Figure 3.6: Direct Conversion transmitter</figcaption></figure>

the transmitter. This problem can be addressed using digital signal processing techniques, or using a sufficiently high stopband rejection filtering after the DAC. The direct conversion architecture also suffers from injection pulling where the spurs of the power amplifier affect the phase of the local oscillator resulting in the output frequency of the oscillator shifting [Raz12].

**Two-step Upconversion Transmitter**

<figure><img src="image_18.png" /><figcaption>Figure 3.7: Heterodyne transmitter</figcaption></figure>

Some of the problems of the direct conversion transmitter such as carrier leakage, and mainly injection pulling, can be solved by adding another stage of frequency translation in a two-step conversion transmitter or Heterodyne transmitter shown in Figure 3.7. The first stage mixers upconvert the baseband signal to an IF. Then the second mixer translates the IF to the final transmission carrier frequency at $f_{LO1} + f_{LO2}$. Quadrature modulation is performed at lower frequency with less effect from the PA. Nevertheless, the mixing products in the two blocks can interfere with each other and proper filter is required [Raz12]. Another problem of the heterodyne transmitter is the effect of the increased number of filtering and mixing stages on silicon area and power consumption.
### 3.1.3 Polar Transmitter Architecture

An alternative architecture to the cartesian-based transmitters is a polar transmitter architecture shown in Figure 3.8. The amplitude, also envelope, and the phase of the OFDM or SC baseband output are extracted for separate digital or analog processing. In a conventional architecture, the envelope controls the supply of a non-linear amplifier while the angle modulated bandpass signal is its input. It performs both PM and FM as $\omega(t) = \frac{d\theta(t)}{dt}$. The angle modulator can be a PLL with a DCO or a VCO.

One of the main limitation of this architecture is inherent to the nature of its amplitude and phase inputs. The fact that amplitude and the phase can change abruptly lowers the spectral efficiency of this architecture. This can be explained by following how the amplitude and the phase change during constellation mapping.

Any two consecutive data to be transmitted can take any two values in the complex constellation of the modulation scheme selected. This means the in-phase and quadrature components can assume any two values, 0 or 1, and change to the other in the next. Then there is a chance that the amplitude or magnitude of the complex points can move from a III-Quadrant to the I-Quadrant, from the IV-Quadrant to the II-Quadrant, or vice versa. This causes the amplitude component to abruptly change its time-domain value which creates a wideband spectra full of harmonics in the frequency domain. Similarly, there is a chance the phase component can change its value abruptly by 180° which requires also broad bandwidth.

Thus, the polar architecture needs around 3 times bandwidth of their cartesian counterparts for effective representation of its amplitude and phase components [Wer13]. With limitation in maximum sampling frequency due to technological and power consumption issues, this main problem of the polar architecture limits its applicability to narrow-band applications.

<figure><img src="image_19.png" /><figcaption>Figure 3.8: General block diagram of a polar transmitter</figcaption></figure>

Another major disadvantage with this architecture is the different amplitude and phase branches. For perfect operation, the timing of the two branches has to be matched. This is difficult given the fact that they have different circuit blocks in each branch unlike the I/Q modulator. Dummy blocks can be inserted to lower the timing misalignments [NRD14].
A critical difference between the polar and the I/Q modulator transmitter is the way the output is obtained. In I/Q modulator, the output is a linear sum, at least ideally, but in the polar architecture it is a product of amplitude and phase components. This means spurs from each of the branches can mix and move to the desired bandwidth [NRD14].

Innovative circuit techniques have been used to mitigate most of the problems discussed above. A great deal of that discussion is in [NRD14; HS11]. For the sampling frequencies, and signal bandwidths targeted in this work, the polar transmitter is less effective. Hence, the reviews of the transmitters in this remaining part of this chapter are focused on the I/Q modulation architecture.

**3.1.4 Transmitter Performance Metrics**

Here some important transmitter parameters are defined. They are useful to the discussions in this manuscript. The main metrics are EVM, the spectral mask of the transmitter output, ACPR in the case of a simulation/measurement carried out using a proper channel of a standard. The simulation of the proposed transmitter architecture in Chapter 5 is assessed based on the parameters that will be briefly discussed in this subsection. There are also some less reported results at the baseband part of the transmitter such as the spectrum flatness. It is a measure of how much difference in power there is between the spectral tones of a desired channel bandwidth. A brief discussion of the rest follows.

**Error Vector Magnitude**

EVM is one of the parameters by which the modulation accuracy of a transmitter is measured. It is a measure of the degree by which the actually transmitted bits, after reception, decoding and measurement, are different from the intended ideal constellation. For example, for the SC PHY EVM of the 802.11ad, the EVM is calculated according to the formula [Int+14]:

$$EVM = 20 \log_{10} \left( \sqrt{\left( \frac{1}{N_s P_{avg}} \sum_{i=1}^{N_s} \left[ (I_i - I_i^* - I_0)^2 + (Q_i - Q_i^* - Q_0)^2 \right] \right)} \right) \text{dB} \quad (3.8)$$

Where $N_s$ is the number of samples, $P_{avg}$ is the average power of the ideal constellation, $I_i^*$ and $Q_i^*$ and $I_i$ and $Q_i$ are the coordinates of the complex points of the $i^{th}$ ideal and measured symbols respectively. $I_0$ and $Q_0$ are complex DC components which the designers can chose so that the EVM is reduced.

Several factors contribute to the degradation of the EVM. In an I/Q transmitter, an imbalance, whether in gain or phase, between the two channels leads to a shift of the received constellation points. Every circuit block in each channel contributes to this imbalance. In baseband, the bits to be transmitted are shaped using a pulse shaping filter to reduce ISI [Gu05]. These filters are designed for a flat passband so
that the frequencies components, or subcarriers in the case of OFDM, at the edge of the band does not
experience a different gain.

Transmitter Spectrum Mask

The transmit mask defines the level of the output transmitted power at different frequencies from the center of the band. It is a primary restriction of a given standard. There are additional far-out spectrum restrictions such as the out-of-band noise profile. The transmitter output power spectral density should be such that it does not raise the receive-band noise floor of communication standards at nearby frequencies. A discussion of this in relation to IEEE 802.11ad and IEEE 802.11ad standards is in available in Chapter 5.

Adjacent Channel Power Ratio

The occupied power is integrated for a given channel at a given resolution bandwidth of the output transimtted spectrum. The ratio of the occupied power of the main desired channel bandwidth to be transmitted to the adjacent channel is expressed by ACPR. ACPR is also sometimes called Adjacent Channel Leakage Ratio. The center of the upper and lower adjacent channels are usually defined as BW, the desired bandwidth, away from the center of the main channel bandwidth, i.e. with no gap between the main and the adjacent channels. Similar expression can be specified also for the upper and lower alternate, sometimes nonadjacent, channels. The ratio of the power occupied in the main channel to that of the upper or lower alternate channel is called the Alternate CPR.

<figure><img src="image_20.png" /><figcaption>Figure 3.9: The ACPR is defined based on the spacing of the main, adjacent and alternate channels in this figure. The ACPR and Alternate CPR measurement results of Chapter 7 are also consistent with this definition.</figcaption></figure>
An illustration of these definitions are shown in Figure 3.9. In this figure, $f_c$ is the carrier frequency at which the desired channel is transmitted. Some standards such as GSM and CDMA specify the width of the adjacent channel and the offset frequencies at which the estimation or measurement should be done.

**3.2 Review of Digital Transmitter Architectures**

Advanced CMOS technologies have opened the opportunity to leverage digital signal processing in as-
sisting or replacing the analog front-end of wireless transmitters. The objective in the design of trans-
mitter has been then to push the realm of DSP towards the antenna at the same time reducing the
pure analog blocks. As the DSP blocks are more scalable, and configurable, the transmitter as a system
becomes more flexible for multi-modal operation.

Architecturally, there has been attempts, regardless of their effectiveness, in simplifying or totally
taking out the analog reconstruction filter following the DAC, even pushing the digital implementation
all the way to the final amplifying stages by driving the PA by digital signals in PDAC-based transmitters.
In this section, recent digital transmitters in literature are discussed.

**3.2.1 Digital Quadrature Modulators**

Traditionally, quadrature modulation is carried out using multipliers. Multiplier-free digital domain im-
plementation of quadrature modulation is reported in [Van+03]. Selected samples of the orthogonal
Cosine and Sine signals are multiplied with input I and Q digital signals for frequency translating these
inputs to fractional frequencies of $f_s$—anywhere from baseband (low pass) to $f_s/4$ (band pass) to $f_s/2$ (high
pass) sections of the first Nyquist zone. The output summed complex data was used to drive a 12-bit
segmented DAC to obtain the analog IF. The concept is validated for GSM, EDGE, and WCDMA. The
desired transmit filters are met by oversampling the input I and Q signals using half-band interpolation
filters.

Due to the limit on the highest sampling rate of the DAC, 500 MHz, the digital quadrature modulation
of the above implementation was valid only as replacement for the first analog mixer stage. Another
frequency translation stage is required.

A more advanced CMOS node was used in [Fra+09] where the first 1-bit digital RF signal generator
using delta-sigma modulation was reported. It implements the baseband DSP and I/Q modulation of a
delta-sigma based digital-IF transmitter in 90nm CMOS chip. A low pass delta-sigma modulator converts
a moderately oversampled high resolution input to single-bit as shown in Figure 3.10. This architecture
is validated for WCDMA application and some cases of the UMTS standard.
<figure><img src="image_21.png" /><figcaption>Figure 3.10: Block diagram of the digital quadrature mixer based on LPF $\Delta\Sigma$ modulator in [Fra+09]</figcaption></figure>

A higher frequency band is achieved in this work, and it shows that the 1-bit digital I/Q modulated output, $\frac{f_{\text{lk}}}{4}$, can be directly used to drive a DAC without the need for analog frequency translation. In [Fra+08] the realm of the digital is further pushed to the antenna by feeding the digital 1-bit output to PDACs to implement the power amplifier. Quantization noise filtering is performed using bandpass FIR filters embedded in the PDAC structure.

The above two works show that for below 3-GHz bands, an analog frequency translation circuit may not be needed. Direct digital-to-analog conversion of the output of a digital quadrature modulator may suffice. To reach higher bands, though, different architectures have been proposed. One of them is using RF DACs. In the following sub-section, works employing the RF DAC concept are reviewed.

### 3.2.2 The RF DAC Concept

The RF DAC concept is the merger of the digital-to-analog converter and mixing stages of a direct conversion transmitter into a common circuitry. In a current-steering architecture, the unit cell of the conventional DAC is replaced by the circuit of a Gilbert mixer whose RF inputs are driven by digital data destined to the DAC [Moh+12]. With some design choices, such as the LO frequency being at integer multiples of the clock driving the digital data so that the output power is higher than what is normally achieved with a $sin(x)/x$ response of the DAC, the conversion and mixing functionalities are delivered [LSH04].
### RF DAC In Direct Conversion Architectures

Early demonstration of the RF DAC concept is in [YJ03] using L-fold interpolation. In ZOH sampling, a data is sampled by a clock rising or falling edge and the next data in the next clock cycle. The idea with L-fold interpolation is instead of waiting for the next clock cycle holding the actual value, the output of the DAC can be made to progressively increase/decrease, L times, in one clock cycle. Since the holding times are shorter, Fourier Series indicates that the frequency response rolls faster for a high image rejection. However, due to increased number of unit current cells and high number of clock activity, high power consumption is expected. The concept is demonstrated for L=16, for a 3.3 MHz input bandwidth at 50 MHz clock and 1 GHz carrier frequencies.

<figure><img src="image_22.png" /><figcaption>Figure 3.11: Block diagram of the DDRM in [Elo+07]</figcaption></figure>

Another early demonstration of the RF DAC concept using an RZ output is in [LSH04] for a half-GSM bandwidth of 17.5 MHz at a center frequency of 942 MHz in 0.18µm CMOS. The carrier frequency reached, however, does not show the advantage of the RF DACs over the digital quadrature modulators discussed above.

Naturally, a high order analog output LC BPF is used for filtering of emissions in RF DACs. In [Elo+07], a DDRM, shown in Figure 3.11, was implemented in 0.13µm CMOS. Front-end digital filters are used for performing most of the transmit mask requirements of GSM/WCDMA/WLAN standards. In this work, the output of the DDRM can be transmitted without an additional frequency translation circuit.

The number of mixing unit cells of the RF DAC can be lowered by inserting a delta-sigma modulator. The shaped quantization noise is filtered by a combination of output analog filter and high OSR. This method increases the operating speed and results in higher power consumption. In [Poz+08], a combination of FIR and IIR digital filters perform most of the channel shaping while oversampling the data by
more than 60. The delta-sigma modulator is used to decrease resolution of data input to the RF DACs.
Similar techniques are used in [Moh+12].

<figure><img src="image_23.png" /><figcaption>Figure 3.12: Block diagram of the digital-IF direct conversion transmitter in [JS07]</figcaption></figure>

## RF DAC and Digital PA

In [Ala+14], digital IQ modulation is further pushed to include some level of power amplification using digital-to-RF amplitude converters. The converters are formerly used in a polar transmitter architecture in [Cru+05]. They are combined with the RF DAC concepts in a direct conversion transmitter architecture. The I/Q modulation is carried out using four 25% duty-cycle non-overlapping LO signals. Each LO phase switches either positive or negative components of the in-phase or quadrature inputs. Output summing is realized by using an on-chip balun combining network. The concept is demonstrated in a 2x13-bit DAC 65nm CMOS implementation. ACPR of -19dBr is obtained for a 154.1 MHz bandwidth, 1024-QAM, SC input at 2.4 GHz output frequency, and up to -44 dBr ACPR for 7 MHz input using digital predistortion.

## RF DAC in Heterodyne Architectures

In [JS07], shown in Figure 3.12, two-step upconversion is implemented in a direct-conversion transmitter architecture. Delta-sigma modulators are used for lowering input data resolution in a moderate OSR operation. The first-step complex mixing translates the digital data to $\frac{f_{atk}}{4}$ while canceling either negative or positive frequency replicas. The second-stage upconversion is implemented using an RF DAC with an output 4th-order Bessel LC BPF tunable for a wideband 260 MHz transmission.

In two-step upconversion digital transmitters, the RF DAC can implement second stage mixing of summed complex data. Thus, the I/Q modulation can be performed in the first stage mixing at lower
<figure><img src="image_24.png" /><figcaption>Figure 3.13: Block diagram of the digital-IF transmitter with embedded FIR filtering RF DAC in [Tal+08]</figcaption></figure>

speeds. In [Tal+08], shown in Figure 3.13, a digital-IF heterodyne transmitter [LLG04] inspired architecture implements a bandpass delta-sigma modulator that converts the high resolution quadrature output to single-bit stream for second-stage upconversion using FIR RF DAC. The filtering of the shaped quantization noise is performed using the embedded six-tap bandpass FIR filter of the RF DAC. Depending on the order of the FIR filter, the output analog filter is relaxed. Any analog filter implemented is only for far-out spectra filtering to mitigate emission to nearby communication. For high stopband rejection and meeting the transmit mask requirements of modern wireless standards, the FIR filter has to be high order with high resolution coefficients. This digital-IF transmitter reports a bandwidth of up to 15 MHz bandwidth at 1 GHz LO frequency.

The summary of the reviewed digital transmitters is in Table 3.1. The main characteristics of the works are tabulated. The differences in their architecture with respect to their upconversion stages, the number of RF signals processed in their conversion stage, the main co-existence filtering mechanisms, order of a $\Delta\Sigma$ used and the resolutions of their DACs are contrasted. In addition, measurement results relevant to the discussion in this section are compared. Although some of the works have higher clock rates, and most of the RF DACs have both clock and LO frequencies, they are compared by the final $f_c$, carrier frequency, at which the data can be transmitted.

## 3.3 Multi-standard Digital Transmitters

Due to the various applications and radio standards that address them, devices are expected to operate over wide spectrum while maintaining the usual requirements such as efficient power management and small form factor. To address these demands, system, and architectural level solutions have been proposed [Mit09]. On transmitter circuit design, the challenges boil down to hardware reusability and ability to reconfigure the hardware for a range of channel bandwidths, modulation and coding indexes, power

<footnote>* LO and $LO/2$ † L-fold Interpolation</footnote>

<footnote>‡ Not Used</footnote>

<footnote>§ Not Implemented, but can be embedded in PDAC</footnote>
<table><caption>Table 3.1: Summary of the reviewed digital transmitters</caption><thead><tr><th>Parameters</th><th>[YJ03]</th><th>[LSH04]</th><th>[EIo+07]</th><th>[Poz+08]</th><th>[Moh+12]</th><th>[JS07]</th><th>[Tal+08]</th><th>[Fra+09]</th><th>[Ala+14]</th></tr></thead><tbody><tr><td>Conversion Stages</td><td>Direct</td><td>Direct</td><td>Direct</td><td>Direct</td><td>Direct</td><td>Two</td><td>Two</td><td>Direct</td><td>Direct</td></tr><tr><td>RF Signals</td><td>Clock + LO</td><td>Clock + LO</td><td>Clock + LO</td><td>LO*</td><td>Clock + LO</td><td>Clock + LO</td><td>Clock + LO</td><td>Clock</td><td>LO</td></tr><tr><td>Structure</td><td>RF DAC</td><td>RF DAC</td><td>RF DAC</td><td>RF DAC</td><td>RF DAC</td><td>RF DAC</td><td>RF FIR DAC</td><td>Digital Quadrature</td><td>RF PDAC</td></tr><tr><td>Co-existence Filtering</td><td>sin(x)<sup>2</sup> / x<sup>2</sup> +</td><td>sin(x) / x</td><td>Digital Filters + sin(x) / x</td><td>Digital Filters + sin(x) / x</td><td>sin(x) / x</td><td>4<sup>th</sup>-Order LC</td><td>Embedded FIR</td><td>N/I<sup>‡</sup></td><td>sin(x) / x</td></tr><tr><td>DAC Resolution</td><td>10-bit</td><td>3-bit</td><td>10-bit</td><td>9-bit</td><td>9-bit</td><td>3-bit</td><td>9-bit</td><td>N/I</td><td>13-bit</td></tr><tr><td>ΔΣ Order</td><td>N/U<sup>§</sup></td><td>Off-chip</td><td>N/U</td><td>3<sup>rd</sup></td><td>3<sup>rd</sup></td><td>2<sup>nd</sup></td><td>4<sup>th</sup></td><td>3<sup>rd</sup></td><td>N/U</td></tr><tr><td>Bandwidth</td><td>3.3 MHz</td><td>17.5 MHz</td><td>10 MHz</td><td>20 MHz</td><td>20 MHz</td><td>200 MHz</td><td>15 MHz</td><td>5 MHz</td><td>154.1 MHz</td></tr><tr><td>f<sub>c</sub></td><td>1 GHz</td><td>0.9 GHz</td><td>1.9 GHz</td><td>2.4 GHz</td><td>1 GHz</td><td>5.25 GHz</td><td>1 GHz</td><td>1 GHz</td><td>2.4 GHz</td></tr><tr><td>Supply Voltage</td><td>3.3 V</td><td>1.8 V</td><td>1.2 V</td><td>1.2 V</td><td>2.5—3.3 V</td><td>2.5 V</td><td>2.5 V</td><td>1 V</td><td>1.3 V</td></tr><tr><td>Technology</td><td>0.35μm CMOS</td><td>0.18μm CMOS</td><td>0.13μm CMOS</td><td>90nm CMOS</td><td>65nm CMOS</td><td>0.13μm SiGe 8HP BiCMOS</td><td>0.18μm CMOS</td><td>90nm CMOS</td><td>65nm CMOS</td></tr></tbody></table>
levels, and spectrum mask requirements.

Multi-standard operation could be achieved by reconfigurable circuit block, or an innovative architecture. Reconfigurability in circuit blocks is usually achieved by leveraging most transmitter operations to DSP or based on digitally-assisted analog circuits. A purely analog reconfigurable circuit would require big area, is less tunable, and power hungry. In this section, a review of recent multi-standard digital transmitters is presented with a focus to novel solutions in the digital-analog interface.

### 3.3.1 Multi-modal Transmitters in Literature

Wireless standards that are transmitted at nearby carrier frequencies with similar channel bandwidths, and whose transmitter parametric requirements—EVM, ACPR for instance—are quantitatively close to each other offer the best scenario for multi-modal circuit design. A set of common requirements can be drawn for each parameter, and a common circuit can be designed on those requirements. The multi-standard transmitter in some cases can have only one signal chain and without a need for complex external reconfiguration. This scenario was exploited in [Elo+07] with digital-to-RF converter based direct conversion transmitter for GSM/EDGE, WCDMA and WLAN. The WLAN transmitter has the stringent requirement in channel bandwidths (16.6 MHz), MCS (64-QAM), and EVM (5.6% with 64-QAM); the WCDMA transmitter has additional requirement which is a power control range of 74 dB; and the GSM/EDGE transmitter also requires a receive band noise of -162 dBc/Hz. The multi-standard transmitter in [Elo+07] has 10-bit digital-to-RF converters with an OSR of eight. This fulfills the receive band noise requirement. Filtering of images and quantization noise is done by a digital front-end IIR filter which also incorporates FIR filter with notches to target specific input signal replicas. Power control is provided by digital control of biasing current sources of the DRFC.

The innovative DRFC circuit block simplified the multi-standard design by eliminating the circuit blocks (mixer and analog reconstruction filter) which contribute highly to non-ideal performance in a traditional direct conversion transmitter. However, if one of the standards, say IEEE 802.11a WLAN, were replaced by a one with wider channel bandwidth, say 80 MHz of the IEEE 802.11ac, the approach would be difficult to follow. For one thing, high oversampling requirement, due to wider channel bandwidth, would push the clock rate to multi-GHz ranges, and design of a multi-bit, multi-GHz RF DAC while still fulfilling narrow channel bandwidth mask requirements is challenging. Additional DSP signal chains, or circuit blocks only specific to one standard, could be used with a common digital-analog interface. Otherwise, the DSP chain would be overly complex.

This is true in [Poz+08] where an RF DAC based direct conversion transmitter is demonstrated for all bands of WiFi-WiMAX standards. Additional oversampling signal chains are included to arrive at the
needed sample rates at the input of the digital-analog interface. Although many interpolation stages are used in the digital front-end to oversample the data by a factor larger than 60, the reliability of the digital circuits even at advanced CMOS nodes should enable them to deliver the expected performance.

In some works, only the blocks that are bottlenecks for realizing a multi-standard transmitter are presented. An implicit performance expectation is put on the remaining blocks of the transmitter. In [McM+14; Spi+13; EKR12], although their target applications are cable TV transmitters, they can be used for wireless communication standards. Direct sampling digital-to-RF converters are designed to support wideband input frequencies with the assumption that digital quadrature modulation is carried out at low IF frequencies using standard DSP blocks. Their input is then a complex output of that quadrature modulator. The clock speed of these converters reaches up to 5 GHz [Spi+13], 4.6 GHz [McM+14], 3 GHz [EKR12] and this enables them to convert GHz range input data frequencies. They do not support any filtering, mask requirements are fulfilled with sheer increase in resolution of the converters as shown in Table 3.2. In other words, the baseband quadrature modulation is carried out with no reduction in resolution. An analog filter at the output is necessary at least for image rejection.

<table><caption>Table 3.2: A summary of RF DACs for cable TV transmitters</caption><thead><tr><td>References</td><td>Sampling rate</td><td>Resolution</td><td>Power</td><td>Effective Bandwidth</td><td>Technology</td></tr></thead><tbody><tr><td>[Spi+13]</td><td>5 Gs/s</td><td>9-bit</td><td>375 mW</td><td>2.2 GHz</td><td>40nm CMOS</td></tr><tr><td>[McM+14]</td><td>4.6 Gs/s</td><td>14-bit</td><td>2.3 W</td><td>1 GHz</td><td>0.18μm CMOS</td></tr><tr><td>[EKR12]</td><td>3 Gs/s</td><td>14-bit</td><td>600 mW</td><td>1.5 GHz</td><td>0.18μm CMOS</td></tr></tbody></table>

While the approach is novel for multi-standard transmitter operation, they come at large power consumption cost even disregarding the power consumption of the remaining transmitter blocks. The reported bandwidth may be enough for most cellular applications. However, the output frequency of the quadrature modulator can not be guaranteed to be within that bandwidth.

Rather than increase the sampling speed of the DAC, it is possible to use n-path parallel RF DACs to target images which are very close to the fundamental signal so as to increase the supported input bandwidth [DPS04; Bal+12]. This is demonstrated in [McC+15] where a reconfigurable 2-path parallel delta-sigma RF DACs sample the quadrature digital output of a digital-IF transmitter. The parallel ΔΣ RF DACs are clocked with 180° phase-shifted clocks to cancel input images. The ΔΣ modulators can be configurable for band pass or high pass noise shaping, at $f_s/4$, $f_s/2$, and $3f_s/4$, for processing wideband IF inputs. Although not shown, the digital quadrature modulator has also to support this reconfigurability. The concept is implemented in 130nm SiGe BiCMOS; it can process up to 50 MHz bandwidth at maximum sampling clock rate of 2 GHz for all ΔΣ modes.
Even though the achieved bandwidth is not wide enough for modern wireless applications, such as
IEEE 802.11ac, the method of using n-path parallel ΔΣ RF DACs after the quadrature modulator is novel
and interesting. The bandwidth can be improved by increasing the clock rate or the resolution. The image
rejection is highly dependent on the timing delay difference between the two clocks. Thus, increasing
the clock rate or the resolution does not scale linearly with image rejection as the former increases timing
errors and the latter contributes to timing errors by increasing the number of elements to be clocked and
the area. For high image rejection, incorporating an embedded image filtering into the structure and
finding a trade-off between the filter order and the clock rate to improve timing alignment could enhance
performance.

**3.3.2 FIR DAC Based Multi-modal Transmitter Architectures**

As a continuation to the discussion on multi-standard transmitters, in this sub-section, digital transmitter architectures based on FIR DACs are proposed. They are original contributions of this work. They are not previously published except one, in [GFK16a]. The system level results of this published work are presented in Chapter 5. The others are qualitatively discussed in relation with the IEEE 802.11ac standard.

Three of the architectures have similarity to those architectures based on mixing-DACs except they
incorporate semi-digital filtering with no analog mixing. The second architecture is similar to the RF
DAC implementation in [JS07] except it does not incorporate analog mixing.

**LPF in Direct Conversion Transmitter**

A LPF FIR DAC based direct conversion transmitter is shown in Figure 3.14. To maximize hardware
sharing, the different input rates are resampled to a common sample rate. Then a delta-sigma modulator
is used to decrease the resolution and its coefficients can be reconfigured to realize different OSR set-
tings. The FIR DAC coefficients are also reconfigurable to meet the transmit mask requirements of each
channel bandwidth. Finally, quadrature modulation is performed in analog domain at the desired carrier
frequency.

The advantages of using FIR DAC are three fold. Firstly, even with long filters and high resolution
coefficients, the embedded FIR filter can be designed to fulfill the desired mask, EVM, and out-of-
band noise floor requirements. This is the difference between RF DAC approaches where a missing
reconstruction filter results in using LC bandpass filter to attenuate images and generally high OSR.
Secondly, the FIR DAC coefficients can be reconfigured to realize a different impulse response with the
same number of elements used representing the coefficient set of the first filter. Although using long
<figure><img src="image_25.png" /><figcaption>Figure 3.14: Block diagram of direct conversion transmitter architecture for IEEE 802.11ac based on LPF FIR DAC</figcaption></figure>

filter with high resolution coefficients for a standard that can be implemented with a simpler filter and coefficient resolution is not efficient, reconfigurability in similar channel bandwidths can be carried out efficiently. Thirdly, the 1-bit FIR DAC, for $L = 1$, is inherently linear, and coefficient mismatch errors only result in changes in the stopband rejection of the filter.

However, the limitation of this architecture also emanates from the FIR DAC. To achieve high stopband rejection, a 40 dB mask for 802.11ac transmit masks at $\frac{3f_{CH-BW}}{2}$, the filter tends to be long and the coefficients have high resolution. This could result in big area which, in turn, can increase the clock timing errors, and decrease the maximum achievable SFDR.

The quadrature mixers in Figure 3.14 can be implemented in analog. The passive voltage up-conversion mixers discussed in [HSR10] can also be used for SAW-less implementation so that the output can directly drive a power amplifier.

## BPF in digital-IF Direct Conversion Transmitter

A BPF FIR DAC in a direct conversion architecture is shown in Figure 3.15. To generate a bandpass input signal to the FIR DAC, the output of the delta-sigma modulator is fed to a digital complex mixer with complex output. The output is at $\frac{n f_s}{2}$ for band pass or high pass operation of the FIR DAC. The final mixing is carried using $90^\circ$ phase shifted clocks of the two FIR DACs.

Image suppression in this architecture is achieved by the $90^\circ$ shifted clocks, i.e., at the summed output. The effectiveness of this is left for investigation.

The summed signal at the output of the FIR DACs can reach up to $\frac{f_s}{2}$. A HPF mode achieves higher carrier frequency than the BPF implementation.

## BPF/HPF in Digital-IF Transmitter

A BPF/HPF FIR DAC based digital-IF transmitter architecture is shown in Figure 3.16. In this case, the quadrature modulation is carried out digitally. The delta-sigma modulator and the FIR DAC are operating
<figure><img src="image_26.png" /><figcaption>Figure 3.15: Block diagram direct conversion transmitter architecture with upconverted $\Delta\Sigma$ input to a BPF FIR DAC. $r$ is ratio of $f_{IF}$ to $f_{CLK}$.</figcaption></figure>

in the same mode as high pass, or band pass. This architecture has similarity to what is implemented in [Tal+08] except the mixing DAC is replaced with a reconfigurable FIR DAC. Low voltage RF DAC implementation suffers from limited output impedance of current sources more than traditional DACs. This is because high output impedance cascode current sources can be used when there is no additional switching devices overhead for LO. Hence, an architecture with high stopband rejection FIR DAC is more suitable to low voltage operation than RF DACs. Since it does not have LO caused linearity problems, it can deliver better high frequency performance.

<figure><img src="image_27.png" /><figcaption>Figure 3.16: Block diagram of digital-IF transmitter architecture based on $\Delta\Sigma$ BPF/HPF FIR DAC</figcaption></figure>

This architecture can be easily reconfigured for operation at different sections of the first Nyquist zone. It can be reconfigured such that the NCO and delta-sigma modulator and FIR DAC can be programmed for the different IF frequencies. For example, the NCO has to generate $\{1,0,-1,0\}$ for IF of $f_s/4$, then the $\Delta\Sigma$ has to change configuration for band pass noise shaping, and the FIR DAC has also to be reconfigured for band pass filtering with only changes in the delay line as will be explained in Chapter 4. If a different IF is desired, say $f_s/3$, then the NCO has to generate $\{1,-0.5,0.5\}$ and $0, \frac{\sqrt{3}}{2}, -\frac{\sqrt{3}}{2}\}$, and the $\Delta\Sigma$ and FIR DAC can be reconfigured as easily [Van+03].

The FIR DAC in this architecture has to work at higher clock rate and input frequency. It is possible to
use another mixer following the FIR DAC if the desired carrier frequency is too high to be implemented
with reasonable performance in the FIR DAC. Additionally, to decrease the effect of the SINC roll-off
on the FIR DAC response, the NRZ holding has to be replaced with a RZ-type pulse holding [CKR08].

**3.4 Summary and Conclusions**

The chapter introduces basic transmitter operation. It discusses modulation in SC and OFDM transmit-
ters, and briefly summarizes the pros and cons of traditional Cartesian transmitter architectures and polar
transmitters. It also highlights some important performance metrics for transmitters.

All-digital transmitter architectures from recent literature are thoroughly reviewed. A special atten-
tion is given to digital-to-RF converters. A summary table of the discussed works is also included.

In accordance with the target application of this work, multi-standard transmitters are reviewed. More
importantly, novel multi-standard transmitters architectures based on LP, BP, and HP FIR DACs are also
proposed. The FIR DAC concept is discussed in Chapter 4.
# Configurable Finite Impulse Response
## Digital-to-Analog Converter

## 4.1 Operation of a DAC

A digital-to-analog converter is used for converting digital signals into analog signals. In wireless communication transmitters, it is usually followed by an analog reconstruction filter to smooth the staircase signal into pure analog form. Digital processing blocks can be used to change the resolution of the signal before it is fed to the converter.

In this section we are going to introduce time and frequency domain operation of an ideal DAC in a classical wireless transmitter. It will be followed by a discussion of a semi-digital FIR DAC. To help explain the FIR DAC, a brief highlight of traditional multi-bit DAC specifications and architectures are included.

### 4.1.1 Traditional Multi-bit DAC

The operation of a DAC in time domain is shown in Figure 4.1. An L-bit digital word is the input to an L-bit resolution DAC. The DAC reads the input data at instance $nT_s$ and holds the new output until $(n + 1)T_s$ for a clock period, $T_s$, in what is called an NRZ scheme. The DAC could also read the sample and hold the output for half the period of the clock and return the output to zero for the remaining half in an RZ scheme. In time domain, the response of the DAC can be approximated by a rectangular pulse with a width of $T_s$.

The rectangular pulse in time domain is a SINC function in frequency domain. The duty cycle of the RZ DAC in time sets the zero-crossings in frequency as shown in Figure 4.2. While the RZ has a flatter magnitude response in the first Nyquist zone, the NRZ is more selective. For input signals whose bandwidth stretches to near $\frac{f_s}{2}$, using RZ response ensures a smaller ripple across the desired band. Given a sampled input as shown in Figure 4.1, the NRZ response can attenuate the immediate image signal by more than 10 dB. However, the attenuation provided by the DAC response is for most applications not
<figure><img src="image_28.png" /><figcaption>Figure 4.1: Time domain operation of a DAC</figcaption></figure>

enough. Hence, an analog reconstruction low pass filter could do most of the job of filtering out the
image.

<figure><img src="image_29.png" /><figcaption>Figure 4.2: Frequency domain operation of a DAC</figcaption></figure>

**4.1.2 Multi-bit DAC Specification**

The performance of a DAC is commonly specified as static performance, dynamic performance and frequency domain performance. In this sub-section, the main DAC performances metrics are defined,
and some formulas are derived in some cases to clarify the concepts. A graphically summary is shown in Figure 4.3.

**Resolution**

Normally, an *N*-bit input signal is converted to analog by using a *N*-bit resolution DAC. However, that is not always the case as $\Delta\Sigma$ modulators can be used to ease design complexity and lower input signal resolution so that an originally *N*-bit signal can be converted to analog by using a lower resolution DAC at higher speed.

**Output Signal Bandwidth**

In wireless communication, a Nyquist rate DAC is designed to convert input signal bandwidths up to half its update rate. The problem with such a target is that the reconstruction filter that follows the DAC becomes complex as it has to filter out a nearby image when the desired signal is close to $\frac{f_s}{2}$.

**Nonlinearity**

Nonlinearity of a DAC are measured by the INL and DNL. DNL is defined as the maximum difference between the LSB and the measured difference of two consecutive output values. On the other hand, INL is a measure of the total deviation of the time-domain response of the DAC from the ideal response.

**Settling Time**

At each update time, the output may change to a new value, and the time it takes to reach within some range of the value is the settling time. The range of values are usually defined as the percentage of the final theoretical value and they are called percentage tolerance.

**Clock Feedthrough**

This is a manifestation of the clock in the output spectrum. This happens due to parasitic capacitances which link the input side, usually digital, to the analog output. It is easily noticeable in the output spectrum because it appears at the clock frequency and its harmonics.

**Spurious Free Dynamic Range**

SFDR measures the relative power difference between the desired signal and the highest harmonic or spur at the DAC output. This measurement is carried out using a single tone input signal as shown in Figure 4.2.
## Harmonic Distortion

$HD_n$ measures the ratio of the power of the $n^{th}$ harmonic to the power of the fundamental signal. The total harmonics distortion is the ratio of the power of the fundamental to the total power of all the harmonics.

## The Third-Order Intermodulation Product

IMD3 is a measure of the ratio of power of the third order intermodulation product to the power of the fundamental input signals. If the two input single tones are $f_1$ and $f_2$, the third-order intermodulation product is one of $2f_1 \pm f_2$, or $2f_2 \pm f_1$ which falls in the signal band.

## Dynamic Range

DR measures the difference between the maximum output power, also called the full-scale output, and the minimum output power. The minimum output power can be approximated by the total noise at the output. The noise may include the quantization error, thermal noise, and flicker noise depending on the application and their influence on the circuit.

<figure><img src="image_30.png" /><figcaption>Figure 4.3: Metrics of the dynamic performance of a DAC</figcaption></figure>

## 4.2 Traditional DAC Topologies

DAC can be implemented mainly in three modes: voltage, current and charge. We present in the following sections some classical DAC architectures.
**4.2.1 R-2R Ladder DAC**

The most straightforward method of implementation is based on switching binary weighted values depending on the N-bit digital input to the output. The values can be realized using voltage/current division in voltage/current mode implementation respectively or charge-redistribution. If we take the R-2R ladder network as an example, Figure 4.4, a reference voltage is divided according binary-weighted resistance ladder, and the digital inputs bits are used to switch the corresponding weighted resistor to a common node or ground. Usually an op-amp is used for summation [Bak10].

<figure><img src="image_31.png" /><figcaption>Figure 4.4: A *N*-bit R-2R resistance ladder DAC</figcaption></figure>

**4.2.2 Resistor String DAC**

This is a more bulkier type of implementation because it has all the possible analog values of an N-bit digital input. The digital inputs are used to decode which value to send to the output. In resistor string implementation, a reference voltage is divided using identical resistors such that all the analog values can be tapped to the output depending on the digital input as shown in Figure 4.5. The decoding could be done as shown in the figure, with a switch array or even with a row/column matrix to lower the required number of components or to improve dynamic performance.

**4.2.3 Current Steering DAC**

This is the type of implementation more suitable for high speed, high resolution DAC implementation. In the case of thermometric implementation, Figure 4.6, the output is obtained from summation of identical valued current sources. The digital inputs control an identical number of current source proportional to their values. Since there is an LSB ($I_{unit}$) difference between consecutive output values, the transition is smooth and the glitch energy associated with it is low. Mismatch could also be reduced due to the identical nature of the current cells.

The thermometric current steering approach requires a large number of unit current cells for high resolution DACs. The routing requirement limits the achievable speed. To remedy this, a segmented
<figure><img src="image_32.png" /><figcaption>Figure 4.5: A *N*-bit resistor string DAC</figcaption></figure>

<figure><img src="image_33.png" /><figcaption>Figure 4.6: A thermometric current steering DAC</figcaption></figure>

architecture could be implemented where some of the binary digital inputs can be implemented in
binary weights, and the MSB bits in unary thermometric weights. A current steering segmented DAC
implementation is shown in Figure 4.7.

**4.3 Finite Impulse Response DAC**

A general *L*-bit, *N*-tap FIR DAC architecture is shown in Figure 4.8. *C*₁ to *C*ₙ are the filter coefficients which are implemented by using an *L*-bit DAC. *N* is the length of the filter.

A FIR DAC can be viewed as a digital filter whose coefficients are implemented in analog. It can be used as a DAC because its coefficients can be designed to form any desired frequency response and shape the analog output. It can also be seen as a general structure from which the traditional multi-bit
<figure><img src="image_34.png" /><figcaption>Figure 4.7: A segmented current steering DAC</figcaption></figure>

DAC is derived. As it is an *L*-bit, 1-tap, power-of-two weighted coefficients version of the FIR DAC.

The main strengths of the general FIR DAC structure is the flexibility to configure the coefficients to obtain any desired frequency response. The output is a linear sum of each tap output. The other strength is the inherently linearity of the output for the case that the coefficients in the taps are linear.

Each DAC has as an input which is the delayed version of the input to the FIR DAC. Therefore, the output is a sum of the delayed and scaled versions of the input. If *L* equals one, the DACs realizing the coefficients can be replaced by a single switch device that controls a passive or active realization of a coefficient value. This arrangement leads to an *N*-tap, 1-bit FIR DAC. For the case where both *L* and *N* are greater than one, it is an *L*-bit, *N*-tap FIR DAC. The classical DAC is considered as an *L*-bit, 1-tap FIR DAC.

There are many important differences between an *L*-bit, *N*-tap; 1-bit, *N*-tap; and *L*-bit, 1-tap FIR DACs. They differ in the ease of dealing with mismatches, the maximum speed each can achieve under the same constraints, the area required to implement them and other parameters [VFM90]. In the following sub-section, the general issues common to all flavors of the FIR DAC structure are discussed. Subsequently, a quantitative comparison of the different flavors is presented. At the end, the comparisons are summarized in a table.

### 4.3.1 FIR DAC Implementation Issues

The delay cells are usually implemented using clocked dynamic or static or semistatic logic. They can also be implemented with analog circuits. Some power consumption reduction could be obtained using non-clocked delay cells, but the resulting delay inaccuracy could be detrimental to the performance of the filter[OT14].

To faithfully replicate the transfer function, the coefficients have to be realized with high degree of accuracy. Thermometric implementation of the coefficients gives higher accuracy. On the contrary,
weighted implementation of the coefficients is prone to mismatch errors, but could be arranged to save area.

For analog implementation, coefficients have to be quantized as their quantitative values have to be translated to hardware. In other words, accurate coefficients are difficult to realize. In addition to quantization, coefficients assume random values. It increases mismatch errors due to loss of symmetry. Furthermore, the fact that the coefficients are random means we have to look into asymmetrical layout methods to decrease systematic process mismatches during layout. Therefore, coefficient quantization helps in representing one coefficient as a ratio of another smaller one. If integer relationship is maintained for all ratios between any two coefficients, all of them can be represented as a sum of a unit coefficient.

The other source of error is the spread of the coefficients. When there is large spread, the number of required unit coefficients increases exponentially. Therefore, filter design should target low resolution co-efficient set. The length of the filter is another factor that increases the number of unit coefficients. Long filter are required to achieves high stopband rejection, but results in large area and big unit coefficient count.

All these factors have to be considered during selection of a FIR DAC topology. Topologies that use passive components to implement FIR DACs can result in big areas due to the relative size of the unit passive component realizing the unit coefficient. For large bandwidth applications, the unit coefficients should be able to switch at high speeds. In this regard, current-steering architectures are preferable. Topologies that exploit the symmetry of FIR DAC impulse responses have generally lower area due to hardware sharing. Because an implementation of a coefficient would be reused to realize two same-valued coefficients in the left and right side of the impulse response. However, the circuit implementing the coefficient now has to entertain additional conditions. For example, a 1-bit input could be translated to a 0 or a 1 for a coefficient, but a 0, 2, and -2 i.e. 1.5-bit for two coefficients. These would be require a different implementation of the coefficient.

**4.3.2 L-bit, N-tap FIR DAC Design Challenges**

Generally, filter design is a compromise between the number of coefficients of the filter, the transition band and the passband and stopband ripples. With strict requirements on the transition band and stopband rejection for narrowband applications in crowded spectrum, a long filter length is needed. On the other hand, in broadband applications where the required stopband rejectionais low, a short filter length can achieve the required transition band.

The digital input of the FIR DAC can be oversampled to reduce quantization noise and complexity of analog low pass reconstruction filter. The oversampling process eases filtering, so short length filter with
low coefficient spread could be used. In this scenario, the *L*-bit, *N*-tap FIR DAC shares the challenges of a traditional *L*-bit DAC and would closely follow the linearity of the *L*-bit DAC.

A delta-sigma modulator is used for converting the resolution of the digital input, then the FIR DAC has low number of input bits and high number of coefficients with considerable coefficient spread to reduce quantization noise. In this scenario, the *L*-bit, *N*-tap FIR DAC has to maintain matching *N* number of *L*-bit DACs. In other words, a single *L*-bit DAC would outperform the multi-tap FIR DAC. The advantage of the *L*-bit, *N*-tap FIR DAC over the *L*-bit DAC would be in image rejection.

<figure><img src="image_35.png" /><figcaption>Figure 4.8: A general *L*-bit, *N*-tap FIR DAC architecture</figcaption></figure>

### 4.3.3 *N*-tap, 1-bit FIR DAC Design Challenges

A 1-bit, *N*-tap FIR DAC is inherently linear. This is because the 1-bit DACs realizing the coefficients are inherently linear and the output is a sum of the delayed and scaled versions of these linear outputs.

The 1-bit, *N*-tap FIR DAC is best suited, then, for obtaining high filtering performance. However, it has to work at higher speeds compared to an *L*-bit, *N*-tap FIR DAC. This is because the serial data at the 1-bit FIR DAC input passes through a conversion stage containing an oversampling and delta-sigma modulator blocks with higher OSR.

A comparison of the three common structures of a FIR DAC is provided in Table 4.1. Some of the assumption used for comparison are shown as a footnote. The first two structures are assumed to have the same resolution in their coefficients and, also, equal number of coefficients. The third structure is the traditional multi-bit DAC. It is presented in the table as a special FIR DAC with a single-tap, or no delay cell, between its coefficients. Besides, its coefficients are implemented with only weights of two.

As expected, an *L*-bit, *N*-tap FIR DAC have the worst mismatch linearity and speed. A traditional multi-bit DAC can achieve the highest speed due to the absence of a delay line, lowest number of unit coefficients and smaller coefficient spread. A 1-bit, *N*-tap FIR DAC can achieve the same coefficient

<footnote>‡ *L* > 1</footnote>

<footnote>§ *N* > 1</footnote>

<footnote>¶ Traditional multi-bit DAC</footnote>

<footnote>|| Thermometric implementation assumed</footnote>
<table><caption>Table 4.1: Comparison among the three structures of an FIR DAC</caption><thead><tr><th rowspan="2">Parameters</th><th colspan="4">FIR DAC</th></tr><tr><th>L-bit, <sup>‡</sup> N-tap</th><th>1-bit, N-tap <sup>§</sup></th><th>L-bit, 1-tap <sup>¶</sup></th></tr></thead><tbody><tr><td>Mismatch Linearity</td><td>--</td><td>++</td><td>-</td></tr><tr><td>Speed</td><td>--</td><td>-</td><td>++</td></tr><tr><td>Image Rejection</td><td>++</td><td>++</td><td>-</td></tr><tr><td>Coefficient Spread</td><td>--</td><td>++</td><td>++</td></tr><tr><td>Number of Unit Coefficients <sup>||</sup></td><td>--</td><td>-</td><td>++</td></tr></tbody></table>

spread as a multi-bit DAC, but the number of unit coefficients usually increase as *N* increases. Image rejection is better in the first two structures due to the flexibility to implement a filter responses sharper than a SINC function.

### 4.3.4 Frequency Translation of FIR DACs

Once a low pass filter is designed, a bandpass and a high pass filter can be generated by only changing the delay line while keeping the coefficients values the same. In circuit implementation, this behavior of the FIR filter makes it amenable to reconfiguration. By only adding redundant delay cells which can be switched to be in the signal path of the active delay line or not, the filter is frequency translated. Since delay cells consume relatively low power and occupy relatively small area, the share of this frequency translation feature on the total FIR DAC power and area budget is negligible.

#### LPF to HPF Transformation

A linear-phase symmetrical or asymmetrical low pass FIR filter impulse response can be changed to a high pass filter response centered at $\frac{f_s}{2}$ by multiplying each coefficient by $(-1)^n$ where *n* is the tap to which the coefficient belongs. Mathematically, this can be expressed as [Lyo04]:

$$h_{hp}[k] = h_{lp}[k] S_{shift}[k] \qquad (4.1)$$

$$S_{shift}[k] = \{\dots, 1, -1, \dots\} \qquad (4.2)$$

In circuit design, this is simply implemented by changing the flip-flops of the delay line. One method in a 1-bit FIR DAC is to drive coefficients by the negative output, $\bar{Q}$ of flip-flops, every other tap. For reconfigurability, the coefficients can be switched between the positive output, *Q*, and negative output, $\bar{Q}$, for low pass and high pass filtering respectively.
<figure><img src="image_36.png" /><figcaption>Figure 4.9: Impulse response of LPF FIR and its frequency translated HPF version</figcaption></figure>

<figure><img src="image_37.png" /><figcaption>Figure 4.10: Magnitude response of LPF FIR and its frequency translated HPF version</figcaption></figure>

An impulse response in Figure 4.9, which will be revisited in subsequent chapters, is used for explaining the discussed transformation. The LPF impulse response is multiplied by $(-1)^n$ to convert it to a HPF response with the same number of coefficients. The resulting frequency response can be seen in Figure 4.10 where the HPF has the same magnitude as the LPF.

### LPF to BPF Transformation

A linear-phase symmetrical or asymmetrical low pass FIR filter impulse response can be frequency translated to a band pass filter centered at $\frac{f_s}{2}$ by multiplying every other coefficient by 1 and -1 and inserting additional zeros in between each multiplication. Mathematically, this can be expressed as [Lyo04]:
$$h_{bp}[k] = h_{lp}[k] S_{shift}[k] \qquad (4.3)$$

$$S_{shift}[k] = \{\dots, 1, 0, -1, 0, \dots\} \qquad (4.4)$$

In circuit implementation, this is easily realized by adding an untapped delay line between the taps that are switched to the positive output and negative output at every other tap. This transformation, however, comes at a cost due to the inserted zeros. For the same filter length, the magnitude response of the resulting band pass filtering FIR DAC decreases by 6 dB. Nonetheless, the good news is that the effective length of the filter is also decreasing. Thus, for a LPF FIR whose length is twice than desired can be designed and transformed to a BPF filter, and still the resulting number of non-zero coefficients will be the same.

<figure><img src="image_38.png" /><figcaption>Figure 4.11: Impulse response of LPF FIR and its frequency translated BPF version</figcaption></figure>

The LPF impulse response from the previous example is again transformed to a BPF response as shown in Figure 4.11. The magnitude response of the resulting band pass filter is lower by 6dB, as can be witnessed in Figure 4.12, while the number of coefficients have decreased

## Configurable 1-bit FIR DAC Delay Line

The implementation of the above discussed transformation in a 1-bit FIR DAC is straightforward. By designing a reconfigurable delay line with a minimum cost of power consumption and area, a set of FIR DAC coefficients designed for LPF mode can be made to work in BPF and HPF modes also. Figure 4.13 shows the frequency translation of a 1-bit FIR DAC by only exploiting the delay line. This means, the components implementing the coefficients can remain unchanged. The advantages of this approach
<figure><img src="image_39.png" /><figcaption>Figure 4.12: Magnitude response of LPF FIR and its frequency translated BPF version</figcaption></figure>

is that the frequency behavior of the FIR DAC can be changed without modifying the placement and routing of the coefficient circuits array.

<figure><img src="image_40.png" /><figcaption>Figure 4.13: Transformation of a 1-bit FIR DAC from LPF to BPF and HPF using a configurable delay line</figcaption></figure>

Assume the switches in their current state in Figure 4.13 are in state 1, and the other state is 0, then the following table could be used to obtain the transformation discussed in the previous topics.

The configurable delay line can be optimized further by fixing the position of switch $S_1$ to the output of the positive output of a delay cell as shown in Figure 4.14. For this delay line, the additional hardware needed is 2($N-1$) switches and $N-1$ delay cells for a total of $2N-1$ delay cells. The power consumption and area contribution of these additional cells and switches, which are required for the configurability, is a small fraction of the total power consumption and area of the total FIR DAC.
<figure><img src="image_41.png" /><figcaption>Figure 4.14: An optimized configurable delay line with only $2(N - 1)$ switches and $2N - 1$ delay cells.</figcaption></figure>

<table><caption>Table 4.2: Switch states of delay line for frequency translation of the 1-bit FIR DAC</caption><thead><tr><th>Frequency Response</th><th>Switch, S<sub>1</sub></th><th>Switch, S<sub>2</sub></th><th>Switch, S<sub>3</sub></th></tr></thead><tbody><tr><td>LPF FIR DAC</td><td>0</td><td>1</td><td>0</td></tr><tr><td>HPF FIR DAC</td><td>X</td><td>X</td><td>1</td></tr><tr><td>BPF FIR DAC</td><td>X</td><td>0</td><td>0</td></tr></tbody></table>

## 4.4 FIR DAC Architectures in Literature

In this section, the discussion on FIR DAC topologies will continue by reviewing briefly previously published works. Initially, a discussion on reported FIR DAC architectures, their application, and specifications will be presented. The discussion focuses on FIR DAC implemented on the transmitter side. However, it is important to mention that they are also applied in the receiver side as part of the analog-to-digital converter. In [AA10], a discussion of the design of continuous time sigma-delta modulators based on FIR DACs is presented.

### 4.4.1 Multi-bit FIR DACs

Traditional transmitter architectures have a digital filter followed by a DAC and then a reconstruction analog low pass filter. Early works targeted reducing the complexity of the digital filters using what they called digital-analog filter converters [VFM90]. This removed power consuming, silicon area demanding, albeit flexible, multiplication blocks while combining two functionalities into one. A silicon demonstrator of this approach was fabricated in 3µm CMOS technology where the coefficients of a 4-tap FIR filter are implemented using 8-bit algorithmic DACs. The operational amplifier based switched-capacitor summing output generally is a speed bottleneck and could have limited the reported speed of 20 kHz.
A more recent implementation of a multi-bit dac is the 4-bit, 60-tap semidigital filter implementation in [Lin+06]. The idea in the work of Lin et al. is to filter shaped quantization noise out of a delta-sigma modulator using a steep transition band semidigital filter. The drooping at the edge of the passband of the semidigital filter is compensated by a pre-emphasis digital filter. Since steep transition, and high stopband rejection require long filter length, the semidigital filter was designed using interpolated coefficients. The problem with this approach is that it requires a complex analog low pass filter to remove the additional passband in the middle of the semidigital filter response. A third-order low pass filter is used in their work due to the high oversampling ratio, 88, in their frequency planning. For lower OSR values, a higher order analog LP filter would have been used. In other words, effective bandwidth of output signal is exchanged for complexity of analog filter.

4.4.2 1-bit Semi-digital Reconstruction Filter

The potential of an *N* − *tap*, 1-bit FIR DAC to lower the complexity of the analog reconstruction filter that follows a DAC in a classical transmitter architecture is demonstrated in 1.2µm CMOS technology in [SW93]. The implementation is shown in Figure 4.15. A 128-tap current-mode FIR DAC, clocked at 7.76 MHz, is used to remove shaped quantization noise at the output of a ΔΣ modulator. Such a long filter implementation normally has a big area and systematic mismatch errors are a big concern.

A method to reduce the number of filter coefficients based on interpolation was reported in [Kim+98].
A sharper transition band filter is obtained from a filter with twice large passband by upsampling its
coefficient set. In other words, delays are inserted, i.e. zero values, between coefficients of an impulse
response of a filter normally designed for a twice large passband than is desired. This method results
in an unwanted additional passband at f_s/2. To circumvent this problem, an interpolated low pass ΔΣ
modulator that generates an additional low noise region at f_s/2 is used.

The high linearity performance of *N*-tap, 1-bit semi-digital FIR is employed in the signal path of a dual-truncation ΔΣ DAC. In this switched-capacitor 0.18 μm CMOS implementation, the symmetry of a 67-tap FIR impulse response is exploited using a folded delay chain to reduce the number of capacitors by half [FFQ04]. While the method of employing complementary clocks to reuse a coefficient decreases the area required, it normally limits high speed operation due to delay in the decoding logic.

In a similar application to the work in [FFQ04], a 1-bit semi-digital FIR is employed together with a
digital filter to suppress shaped quantization noise in [Bar+04].

In [Doo+05], a semi-digital 322-tap FIR DAC with only positive coefficients is designed for quan-
tization noise filtering at audio frequencies. Silicon area limits the use of high resolution coefficients in
long filter implementation. This problem is overcame in [Doo+05] by limiting the coefficient spread to
<figure><img src="image_42.png" /><figcaption>Figure 4.15: Current-mode FIR DAC architecture in [SW93]</figcaption></figure>

25 and selecting only positive coefficients to improve the mismatch. In implementation, a transmission gate based dynamic delay line was used to save power consumption and area needed for 322 flip-flops. Normally, dynamic circuit implementations have problems of charge injection, and charge sharing. For a robust FIR DAC design at high speeds, a static or semi-static delay line is more robust against noise at the expense of increase in the total power and area by a small percentage.

### 4.4.3 Programmable Filtering DAC

The compatability of the FIR DACs approach for implementing programmable filtering DACs was demonstrated at a bigger area and power cost in [HF94]. The delay line of the FIR DAC was improved by adding redundant delays which were useful for realizing different filter responses. Each tap of the FIR DAC were implemented by segmented 8-bit current steering DACs. The programmability of coefficients was possible by changing the overdrive voltage of current sources in the segmented DAC. Current steering implementation enabled them to switch at higher rates than previously reported.

Programmability of FIR DACs was revisited using a novel current steering architecture in [AR01]. A constant bias current was divided into two positive and negative output branches using a set of differential switches as shown in Figure 4.16. The number of differential switches at each tap are proportional to the coefficient values and are enabled or disabled by a control switch that ensures programmability. A wide swing cascode current source mirrors the currents in the output branches. The frequency domain performance of the architecture depends on the high frequency linearity of the current mirrors at the output. This concept was demonstrated for a 64-tap FIR DAC with limited coefficient spread for audio
<figure><img src="image_43.png" /><figcaption>Figure 4.16: Current steering FIR DAC architecture in [AR01]</figcaption></figure>

applications in 0.25µm CMOS technology.

### 4.4.4 Receive-band Noise Filter

The *N*-tap, *L*-bit FIR structure is also embedded in DIDIMO transmitters for receive-band noise filtering. In [Fuk+12], a 3 + 7 segmented DAC realizes the coefficients of 3-tap FIR filter. Due to the large circuitry at each tap of the filter, the length of the filter is usually short. The coefficients are also equal to avoid mismatch problems. The only flexibility in generating different impulse responses is obtained by controlling the number of delays between the taps. This technique makes the FIR filter in DIDIMO transmitters suitable as a notch-filter to target a specific receive band. The digital signals are directly fed to the filtering structure without major filtering previous stages. Hence, high oversampling ratios are used and high resolution RF-DAC are implemented in each tap of the filter [Gab+11].

### 4.4.5 FIR Power DAC

Delta-sigma noise shaped digital outputs can be directly frequency translated by using image-reject digital mixers [Fra+09]. The resulting single-bit stream can be directly fed to parallel power DACs for amplification and digital-to-analog conversion. The power DACs, tapered buffers, can also form the coefficients of an FIR filter for bandpass filtering of their combined output.

In [Fla+08], a 5-tap reconfigurable bandpass FIR filter with unity positive and negative coefficients is implemented in 65nm CMOS process. The outputs of 56 TPSC dynamic flip-flops of the delay line are connected to three multiplexer. The multiplexers select five taps to drive five power DACs as shown in Figure 4.17. The outputs of the PDACs were, then, combined to realize three different bandpass filters.

Unity coefficient, short length filters may reduce the quantization noise to even fulfill transmit mask
<figure><img src="image_44.png" /><figcaption>Figure 4.17: General structure of the reconfigurable bandpass FIR power DAC architecture in [Fla+08]</figcaption></figure>

requirements. However, the architecture is not fit for applications where the out-of-band noise profile of
the transmitter is expected to respect co-existence issues in a crowded spectrum.

**4.5 High Speed 1-bit, *N*-tap FIR DAC Design**

Unlike passive components, current mode DAC architectures are amenable for high speed operation.
Their mismatch is characterized, they occupy lower area and are scalable. In this analysis, current steer-
ing FIR DAC architectures are assumed.

The analysis presented in this section are important contributions of this PhD work. As explained in the conclusions chapter at the end of this dissertation, a scarcity of literature providing design formulas for estimating non-idealities of high speed current-steering thermometric FIR DAC implementations was the reason that led to these derivations.

**4.5.1 Current Steering Architecture**

Current mode implementation of a FIR DAC is shown in Figure 4.18. The current sources are weighted to implement the coefficients. The differential output enables implementing signed coefficients. For example, the cross-connected outputs of the first and last coefficients realize a negative coefficient values relative to the other coefficients in Figure 4.18.

A UCC is a circuit realization of a unit coefficient. It contains analog current source and a digital
latch. It can be replicated in all coefficients as many times as the quantized coefficient values to create a
resultant current in the desired sign and magnitude of the coefficient as in Figure 4.18. All that is required
is to maintain an integer ratio between all the coefficients. This can be accomplished by quantizing the
coefficients in a fixed number of bits where the largest coefficient represents $2^{quantization\_bits}$. Then the
GCD of the integer values of the coefficients becomes the value of the unit coefficient that is realized
by one UCC. If there is no GCD greater than one, the unit coefficient becomes one, still realized by one
<figure><img src="image_45.png" /><figcaption>Figure 4.18: Current-steering structure for implementing a FIR DAC</figcaption></figure>

UCC, and the largest coefficients requires 2<sup>quantization_bits</sup> UCCs in implementation.

4.5.2 Performance Metrics and Modeling

In a current steering DAC architecture, the main sources of non-idealities are current source mismatch,
finite output impedance of current sources, clock feedthrough, global and local timing errors, output and
cell dependent errors. Modeling these non-idealities and factoring them in the design of the DAC is
important for the measurement to match the theory. In this section, we are going to analyze how these
non-idealities influence the performance metrics discussed earlier in this chapter.

Effect of Coefficient Mismatch

The main advantage of a single-bit FIR DAC is the inherent linearity of the 1-bit DACs it uses at each
tap. Coefficient mismatch has negligible effect on the passband of the transfer function, but it puts a limit
on the stopband attenuation to a degree that even an increase in the length of the filter would not affect
it. An FIR filter output is given by the following equation:

$$
y[n] = \sum_{k=1}^{N} c_k x[n-k] \tag{4.5}
$$

Where $c_k$ are the coefficients and $N$ is the length of the filter. The filter transfer function for a general input $x[n] = e^{-j\omega n}$, where $-\infty < n < \infty$, is [PS08]:

$$
H(\omega) = \sum_{k=0}^{N-1} c_{k+1} e^{j\omega k} \tag{4.6}
$$

If each $c_k$ has a mismatch generated error $\epsilon_k$, then the error transfer function can be written as:

$$
H_e(\omega) = \sum_{k=0}^{N-1} \epsilon_{k+1} e^{j\omega k} \quad (4.7)
$$
The filter magnitude response variation due to error is derived in [PM91] with the assumption that $\epsilon_k$ are uncorrelated Gaussian random variables which are identically distributed with zero mean and standard deviation $\sigma_\epsilon$:

$$|H_e(\omega)| = \frac{\sqrt{\pi N}}{2} \sigma_\epsilon \qquad (4.8)$$

While this equation is important in the characterization of FIR DAC coefficient mismatch errors, it is derived based on the coefficient being implemented as a lumped component. It fails to take into account that coefficients are implemented by replicating a single unit coefficient. A standard deviation which is representative of the errors of all the coefficients should be taken. A slight modification can be applied for the current steering implementation based on unit coefficient. If all the unit coefficients have errors that are uncorrelated Gaussian random variables which are identically distributed with zero mean and a standard deviation of $\sigma_u$, then a coefficient with a $c_k$ unit coefficients has a standard deviation of $\sigma_u \sqrt{|c_k|}$. An average standard deviation of all the coefficients which are implemented with unit coefficients can be found from the pooled variance as:

$$\sigma_{ave} = \sqrt{\frac{\sigma_u^2|c_1| + \sigma_u^2|c_1| + \dots + \sigma_u^2|c_N|}{N}} \qquad (4.9)$$

The error on the magnitude response can then be modified to

$$|H_e(\omega)| = \frac{\sqrt{\pi N}}{2} \sigma_{ave} \qquad (4.10)$$

A new formula for estimation of magnitude variation due to coefficient mismatch and more suitable to a current-steering FIR DAC architecture can then be found using:

$$|H_e(\omega)| = \frac{\sqrt{\pi \sum_{k=1}^{N} |c_k|}}{2} \sigma_u \qquad (4.11)$$

To put this in perspective, an impulse response of an 802.11ad FIR DAC is used in Figure 4.19. The mismatch error magnitude for a 14% standard deviation on each unit coefficient can be estimated using Equation (4.11) to be 0.0143. In other words, the passband can vary from 0.9857 to 1.0143(i.e. -0.1251 to 0.1233 in dB). The passband ripple, $A_p$, is then 0.2484 dB. The stopband, now at < -33 dB or < 0.02239, is raised by this error to 0.03669 or -28.71 dB. The stopband ripple, $A_{st}$, is then 4.29 dB. Then, it can be concluded that the mismatch error affects the stopband more than the passband. The stopband can be affected by the mismatch error to a degree where even longer filter would not deliver better stopband attenuation.

As will be seen in 4.5.2, this estimate gives an optimistic value. A more accurate ripple due to coefficient mismatch is obtained using large number simulation such as Monte Carlo.
<figure><img src="image_46.png" /><figcaption>Figure 4.19: Impulse response of the 802.11ad FIR DAC. The values from Equation (4.11)</figcaption></figure>

Yield Model

This parameter can be further utilized in defining a yield of a FIR DAC. A FIR DAC functionality is dependent on faithfully rendering the theoretically designed transfer function, the yield is defined as the number of FIR DACs that have an acceptable transfer function. Coefficient inaccuracy results in changes in the stopband rejection, then the transfer functions that crosses a certain limit in the stopband can be rejected.

A transfer function with stopband rejection of $\delta_2$ can be guaranteed to be below a desired stopband rejection level of $\hat{\delta}_2$ at a maximum standard deviation $\sigma_{ave,max}$ of with a probability of p given by [PM91]:

$$p = e^{-\frac{1}{N}\left(\frac{\hat{\delta}_2 - \delta_2}{\sigma_{ave,max}}\right)^2} \qquad (4.12)$$

This approach was used in the design of an LP SC mode 802.11ad FIR DAC as reported in [GFK15]. The percentage of the FIR DAC transfer functions that fulfill the 802.11ad mask with a margin are plotted against the standard deviation of the random mismatch in the current sources implementing the coefficients. It was concluded that the stopband of the transfer function does not raise to above 5 dB of the lowest part of the transmit mask with as big as 14% random mismatch standard deviation at a confidence level of $3\sigma$. This is shown in Figures 4.20a and 4.20b.
<figure><img src="image_47.png" /><figcaption>Figure 4.20: The change in passband ripple is small as predicted. The transfer function can withstand coefficient mismatches up to 14%, and still fulfill the stopband attenuation with at least 5 dB margin. The percentage yield is plotted against random coefficient mismatch of unary current sources with coefficients realized as a sum of independent unary current sources.</figcaption></figure>

Random Device Mismatches

Transistors which implement the coefficients are prone to process mismatches. These mismatches can be tackled by classifying them into two: random and systematic mismatches. The random mismatches are dependent on device size, biasing conditions and some technological constants whereas the systematic mismatches appear over the chip area and impart a relativistic error on a device as a function of its distance from the center of the chip (more discussion on this in Chapter 6).

In [Pel+89], a relationship between the device size and biasing and the standard deviation of the normalized random errors of a current flow through the device are observed.
$$ \delta^2(\frac{\Delta I_u}{I_u}) = \frac{1}{Area} (A_{\beta} + \frac{4A_{VT}}{V_{OV}^2}) \qquad (4.13) $$

Where Area = WL of the current source transistor, V<sub>OV</sub> is the overdrive voltage, and A<sub>β</sub>, and A<sub>VT</sub> are technological constants.

$$ \delta(\Delta I_u) = I_u \sqrt{\frac{1}{Area} \left(A_{\beta} + \frac{4A_{VT}}{V_{OV}^2}\right)} \qquad (4.14) $$

Equation (4.14) can be inserted in Equation (4.9) to find the maximum σ<sub>ave</sub> from transistor level parameters. The σ<sub>ave</sub> can be used to calculate the probability until an acceptable confidence level is obtained.

### Effect of Finite Output Impedance

The effect of finite output impedance on the dynamic behavior of the FIR DAC can be analyzed by considering the unary implementation in Figure 4.18.

<figure><img src="image_48.png" /><figcaption>Figure 4.21</figcaption></figure>

The current sources that implement the coefficients have a finite output impedance. The effect of this on the output voltage of a current-steering DAC is analyzed in [Mik+86]. Similar approach can be followed for a current-mode FIR DAC modeled as shown in Figure 4.21. N<sub>p</sub>, and N<sub>n</sub> indicate the total number of current sources that correspond to the coefficients contributing to the positive and negative branches of the output line respectively. Since differential implementation is considered, the negative coefficients which are driven by a 0-bit are grouped under N<sub>p</sub>; and the positive coefficients driven by a 0-bit are grouped under N<sub>n</sub> as the negative coefficients driven by a 1-bit.

$$ I_{load,p} = N_p(I_{out} - G_{out}V_{out,p}) \qquad (4.15) $$
$$I_{load,n} = N_n(I_{out} - G_{out}V_{out,n}) \qquad (4.16)$$

Where $I_{load,p}$, $I_{load,n}$ are the output currents belonging to positive and negative coefficients respectively; $G_{out}$ is the output resistance of a unit current source; and $I_{out}$ is the ideal full scale current divided by the number of current sources. The output voltages of the positive and negative coefficients $V_{out,p}$, $V_{out,n}$ are given as:

$$V_{out,p} = R_{load}I_{load,p} \qquad (4.17)$$

$$V_{out,n} = R_{load}I_{load,n} \qquad (4.18)$$

The above pair of equations can be combined with equations (4.17) and (4.18) to arrive at:

$$V_{out,p} = I_{out} \left( \frac{N_p R_{load}}{1 + N_p R_{load} G_{out}} \right) \qquad (4.19)$$

Similarly for the negative branch,

$$V_{out,n} = I_{out} \left( \frac{N_n R_{load}}{1 + N_n R_{load} G_{out}} \right) \qquad (4.20)$$

The differential output of a current-mode FIR DAC with $G_{out}$ current source output impedance is then:

$$\Delta V_{out} = V_{out,p} - V_{out,n} = I_{out} R_{load} \left( \frac{N_p - N_n}{(1 + N_p R_{load} G_{out})(1 + N_n R_{load} G_{out})} \right) \qquad (4.21)$$

In the ideal case, where $\frac{1}{G_{out}}$ is $\infty$, $\Delta V_{out}$ is the difference between the total output currents of positive and negative coefficients times the load resistance. However, for finite output resistance, it changes depending on ratio between the load resistance and the total output resistance of the paralleled current sources, $\frac{N}{R_{out}}$. This creates data dependent distortion on the output. This has been analyzed in [BSS04]. The SFDR determined by the second-order harmonic for a FIR DAC with $N$ number of current sources is [BSS04]:

$$SFDR_2 = \frac{NR_{load}}{4R_{out} + 2NR_{load}} \qquad (4.22)$$

Similar derivation were followed to obtain an expression for the third order harmonic distortion, IMD3, of a fully-differential implementation [LL03]:

$$IMD3_{FD} = \frac{\frac{14}{3} G_{out}^2 N^2 + \frac{16}{3} (G_{load}^2 + G_{load} G_{out} N)}{G_{out}^2 N^2} \qquad (4.23)$$

Where $G_{load}$ is the load conductance.
Differential circuits cancel even harmonic distortions. Thus, the SFDR is determined by the dominant third order harmonic component. For the case where the output resistance of the current sources is much greater than the load resistance times the number of current sources, $R_{out} \gg NR_{load}$, the n-th harmonic distortion components due to the finite output resistance can be simplified by a general formula [PS10]:

$$HD_n \approx \left( \frac{NR_{load}}{4R_{out}} \right)^{n-1} \qquad (4.24)$$

Furthermore, the output impedance decreases with frequency. This affects the dynamic performance of the FIR DAC. To ensure high linearity in the 802.11ad mode, the current sources has to maintain the required $Z_{out}$ up to near GHz output frequencies.

Assuming Figure 4.22a is the current source in consideration, the parasitic capacitances from the drains of $M_{CAS}$ and $M_{CS}$ to the ground set the poles and zeroes of $Z_{out}$ versus frequency curve [BSS04]. If the layout of the transistors of the differentially-switched cascode current source shown in Figure 4.22a is such that the parasitic capacitances of the interconnects between each transistor is minimal, the output impedance can be made to keep its DC value even at frequency values. This type of placement is discussed in Chapter 6.

## Effect of Noise on FIR DAC Dynamic Range

The generated noise at the output of the current sources of the FIR DAC puts a limit on its dynamic range. For the output of the circuit to have the desired DR, the circuit has to be modeled and the noise output should also be quantified. The analysis is based on the differentially switched cascode current source of Figure 4.22a. The noise sources are mainly drain current thermal noise and $1/f$ noise of the transistors, and thermal noise of the resistors. [Raz01].

The assumption is that the noise sources are uncorrelated. The output-referred noise of each source are superposed to obtain the total noise output. Then, the ratio of the total signal power to the total noise at the output is the DR.

$$\overline{I^2}_{n,total} \approx \overline{I^2}_{n,CS} + \overline{I^2}_{n,CAS} + \overline{I^2}_{n,SW} + \overline{I^2}_{n,load} \qquad (4.25)$$

The small signal equivalent circuit for calculating the output-referred noise due to the drain noise of transistors $M_{CS}$, $\overline{I^2}_{n,CS}$, is shown in Figure 4.22b. The two circuits in Figure 4.23a and 4.23b are for calculating the output-referred noise due to the noise of transistors $M_{CAS}$ and $M_{SW}$ respectively. Using KVL equations at x, y, and output,
<figure><img src="image_49.png" /><figcaption>Figure 4.22: a) Differentially switched cascode current source, b) Small signal model to find the output-referred noise due to $\bar{I}_{n1}$</figcaption></figure>

$$ \bar{I}_{n1} + \frac{V_x}{r_{o1}} + V_x S C_{gs2} + \frac{V_x}{r_{o2}} + g_{m2} V_x - \frac{V_y}{r_{o2}} = 0 \quad (4.26) $$

$$ V_y \left( S C_{g3} + \frac{1}{r_{o2}} + \frac{1}{r_{o3}} + g_{m3} \right) - g_{m2} V_x - \frac{V_x}{r_{o2}} + \frac{I_{out} R_{load}}{r_{o3}} = 0 \quad (4.27) $$

$$ \bar{I}_{n,CS} + g_{m3} V_y + \frac{I_{out} R_{load}}{r_{o3}} + \frac{V_y}{r_{o3}} = 0 \quad (4.28) $$

The above three equations can be combined to solve for the gain from $\bar{I}_{n1}$ to output-referred component $\bar{I}_{n,CS}$,

$$ \frac{\bar{I}_{n,CS}}{\bar{I}_{n1}} = K_1 = \frac{AB \left[ r_{o2} \left( g_{m3} + \frac{1}{r_{o3}} \right) \right]}{-AB \left( \frac{R_{load}}{r_{o3}} + 1 \right) - \left( \frac{r_{o2}}{g_{m3} + \frac{1}{r_{o3}}} \right) \left( 1 + \frac{R_{load}(1-A)}{r_{o3}} \right)} \quad (4.29) $$

$$ \text{Where } A = \frac{g_{m3} + \frac{1}{r_{o3}}}{\frac{1}{r_{o2}} + \frac{1}{r_{o3}} + g_{m3} + S C_{gs3}}, \text{ and } B = \frac{g_{m2} + \frac{1}{r_{o2}}}{\frac{1}{r_{o1}} + \frac{1}{r_{o2}} + g_{m2} + S C_{gs2}}. $$

Similar approach can be followed to find the gains from $\bar{I}_{n2}$ to output-referred component $\bar{I}_{n,CS}$, and from $\bar{I}_{n3}$ to output-referred component $\bar{I}_{n,SW}$ to arrive at:
$$ \frac{\bar{I}_{n,CAS}}{\bar{I}_{n2}} = K_2 = \frac{A(B+1)}{\frac{-AB}{r_{o2}}\left(\frac{R_{load}}{r_{o3}}-1\right)+1+\frac{R_{load}}{r_{o3}}-\left(\frac{AR_{load}}{r_{o3}}\right)} \quad (4.30) $$

$$ \frac{\bar{I}_{n,SW}}{\bar{I}_{n3}} = K_3 = \frac{1 - \frac{1}{A} + \frac{g_{m2} + \frac{1}{r_{o2}}}{Dr_{o2}}}{\frac{R_{load}}{r_{o3} - \frac{1}{A}\left(\frac{R_{load}}{r_{o3}} - 1\right)} + \left(\frac{g_{m2} + \frac{1}{r_{o2}}}{Dr_{o2}}\right)\left(\frac{R_{load}}{r_{o3}} + 1\right)} \quad (4.31) $$

$$ \text{Where } D = \left(g_{m3} + \frac{1}{r_{o3}}\right)\left(\frac{1}{r_{o1}} + \frac{1}{r_{o2}} + g_{m2} + SC_{gs2}\right). $$

Each of the drain noise components, $\overline{I^2}_{n,1}$, $\overline{I^2}_{n,2}$, $\overline{I^2}_{n,3}$, contain both thermal noise, $\overline{I^2}_{n,d}$, and flicker noise, $\overline{I^2}_{n,\frac{1}{J}}$. The flicker noise is represented in the same manner as the drain thermal noise from drain to the source. Thus, the drain noise of the three transistors can be formulated as follows [Gra01].

$$ \overline{I^2}_{n,d} = \overline{I^2}_{n,t} + \overline{I^2}_{n,\frac{1}{J}} = (4\gamma kT g_m + K' \frac{I_{UCC}}{f}) \Delta f \quad (4.32) $$

The other noise components is the thermal noise of the resistor and is given by:

$$ \overline{I^2}_{n,load} = 4kT \frac{1}{R_{load}} \Delta f \quad (4.33) $$

<figure><img src="image_50.png" /><figcaption>Figure 4.23: Small signal model to find the output-referred noise due a) $\bar{I}_{n2}$ b) $\bar{I}_{n3}$</figcaption></figure>
Where $\gamma$ is device dependent coefficient. A value of 2/3 is taken for long channel devices, but it increases for devices in nanometer processes [Gra01]. $k = 1.38 \times 10^{-23}$ is Boltzmann's constant, $T = 300^{\circ}K$ is taken for room temperature, $K'$ is another device dependent constant and $\Delta f$ is the bandwidth over which the noise is integrated.

$$ \overline{I^2}_{n,CS} = K_1^2 \overline{I^2}_{n,d} |_{g_m=g_{m1}} \qquad (4.34) $$

$$ \overline{I^2}_{n,CAS} = K_2^2 \overline{I^2}_{n,d} |_{g_m=g_{m2}} \qquad (4.35) $$

$$ \overline{I^2}_{n,SW} = K_3^2 \overline{I^2}_{n,d} |_{g_m=g_{m3}} \qquad (4.36) $$

The total noise power at the output is then:

$$ P_{noise} = N \overline{I^2}_{n,total} = N(\overline{I^2}_{n,CS} + \overline{I^2}_{n,CAS} + \overline{I^2}_{n,SW} + \overline{I^2}_{n,load}) \qquad (4.37) $$

N is number of UCCs in the FIR DAC implementation. The gate-source parasitic capacitance are evaluated at the bandwidth of the FIR DAC. It is 880 MHz for the 802.11ad mode, and 160 MHz for the 802.11ac 160 MHz modes.

Some assumption could be taken to simplify expressions of $K_1$, $K_2$, and $K_3$. For example, $r_o \gg \frac{1}{g_m}$. Another assumption is the product of the load resistance and the drain-to-source conductance is much smaller than one: $\frac{R_{load}}{r_o} \ll 1$. At the frequency of operation $g_m \gg SC_{gs}$. A and B are approximated to unity with those assumptions. $D \approx g_{m2}g_{m3}$.

$$ K_1^2 \approx (r_{o2}g_{m3})^2 \qquad (4.38) $$

$$ K_2^2 \approx \left( \frac{2g_{m3}}{g_{ds2} + g_{m3}} \right)^2 \approx 4 \qquad (4.39) $$

$$ K_3^2 \approx 1 \qquad (4.40) $$

With this new values the total noise power is approximated to:

$$ P_{noise} \approx 4kTBW[g_{m1}(r_{o2}g_{m3})^2 + 4g_{m2} + g_{m3}] + K'I_{UCC}[5 + (r_{o2}g_{m3})^2] \ln BW \qquad (4.41) $$

The average signal power is a summation of the full-scale current flowing in the load resistors.

$$ P_{sig} = 0.5NI_{UCC}^2 \qquad (4.42) $$
$$DR = \frac{P_{sig}}{P_{noise}} \qquad (4.43)$$

The dynamic range can then be expressed as follows:

$$DR \approx \frac{NI_{UCC}^2}{8kTBW[g_{m1}(r_{o2}g_{m3})^2 + 4g_{m2} + g_{m3}] + K'I_{UCC}[5 + (r_{o2}g_{m3})^2] \ln BW} \qquad (4.44)$$

The transconductance term in $K_1$ can be replaced by an equation containing the current value, $I_{UCC}$, and some technological constants. However, the $r_{o2}$ term in $K_1$ would have to be calculated for each new current value. Hence, it is not straightforward to run multiple simulations with this expression of DR. As can be seen from the values of the gains, the noise contribution from the current source transistor, $M_{CS}$, is much greater than the contribution from both the cascode transistor, $M_{CAS}$, and the switch device, $M_{SW}$. This is because the ratio $(r_{o2}g_{m3})^2$ is on the order of hundreds as per transistor-level simulation of a differentially-switched cascode current source circuit. Therefore, if some additional tolerance is taken on the output noise value of the current source transistor, it simplifies the analysis to ignore the switch and cascode devices. For that, let $(r_{o2}g_{m3})^2$ be $K_{CS\_R}$ then:

$$g_{m1}(r_{o2}g_{m3})^2 + 4g_{m2} + g_{m3} \approx g_{m1}K_{CS\_R} \qquad (4.45)$$

Then the dynamic range formula can be simplified to an expression containing technological constants and the variables $N$, unit current, $I_{UCC}$, and bandwidth, $BW$.

$$DR \approx \frac{NI_{UCC}^2}{8kTBWg_{m1}K_{CS\_R} + K'K_{CS\_R}I_{UCC} \ln BW} \qquad (4.46)$$

This DR expression can be further expanded so that it is expressed only in terms of $I_{UCC}$ and constants. The transconductance of the current source transistor, $g_{m1}$, can be expressed in terms of $I_{UCC}$. Since $M_{CS}$ is expected to be in saturation, the transconductance is given as:

$$g_{m1} = \sqrt{2k_{ox}\frac{W}{L}I_{UCC}} \qquad (4.47)$$

This can be inserted in Equation (4.46) to arrive at an expression for DR which is more insightful.

$$DR \approx 10 \log_{10} \left[ \frac{NI_{UCC}^2}{D_1 \sqrt{I_{UCC}} + D_2 I_{UCC}} \right] \qquad (4.48)$$

Where $k_{ox}$ is a technological constant, the left-hand side denominator constant, $D_1$ is $8kTBW\sqrt{2k_{ox}\frac{W}{L}K_{CS\_R}}$, and the right-hand side denominator constant, $D_2$ is $K'K_{CS\_R} \ln BW$. It is observed in simulation that $K_{CS\_R}$ decreases as current increases due to decrease in drain-source output resistance. Therefore, the dynamic range value given by Equation (4.48) increases with increase of unit current, $I_{UCC}$, and then plateaus.
The dynamic range formula in Equation (4.48) is used to find the optimum current value in the design of the UCC in Chapter 6. Since the *BW* and the number of UCCs, *N*, are different for in the two modes of operation the FIR DAC is designed, the unit current values for the same DR in each mode are separately estimated. A maximum value of the two *I*<sub>UCC</sub> which guarantees the required dynamic range for the two modes is taken.

If the *I*<sub>UCC</sub> is to be controlled off-chip by a reference current as is the case in the implementation of
the prototype FIR DAC discussed in Chapter 6, then the dynamic range can be improved by using higher
reference current values.

**4.6 Summary and Conclusions**

Starting from basic DAC operation, specification, and architecture, the chapter has evolved to analysis of FIR DACs. A detailed treatment of the pros and cons of the different FIR DAC architectures has been presented. The traditional multi-bit DACs are classed under the a general FIR DAC structure as *L* – *bit*, 1-tap, and they are compared with *L*-bit, *N*-tap, and 1-bit, *N*-tap FIR DACs.

Furthermore, frequency translation of FIR DACs, from LPF to BPF, and LPF to HPF, is explained theoretically with examples using impulse responses. A novel configurable delay line that can be used to implement these frequency translation is also introduced.

A thorough literature review on FIR DAC is conducted by grouping the different works according to their applications—multi-bit, 1-bit, programmable, receive-band noise filter and amplifying FIR DACs.

Finally, analysis of a current-steering FIR DAC is presented where expressions for coefficient mis-
match, yield model, and effect of finite output impedance are derived. The discussion of the last section
will be useful in Chapter 6 where the implementation of a FIR DAC in 28nm CMOS FDSOI is dis-
cussed.
# Proposed IEEE 802.11ac/ad Transmitter
## Baseband Architecture

In the discussion of multi-standard transmitters in Chapter 3, the possibility of multi-standard operation by modifying some circuit blocks of the transmitter has been studied. Many of the works that were reviewed focused on the interface between digital and analog parts of the transmitter. In Chapter 4, the FIR DAC was introduced as a key enabling block for multi-standard transmitter. In this chapter, a FIR DAC based multi-standard, multi-mode transmitter baseband architecture is presented.

The proposed architecture is validated using MATLAB® on system level for two recent multi-Gb/s standards. The chapter will start by introducing these standards. Then in the next section, the main components that make up the digital processing block are presented. This is followed by developing the FIR DAC specification for these standards. The chapter ends by presenting some interesting simulation results.

### 5.1 Specification of the standards

This work takes the IEEE 802.11ac and IEEE 802.11ad WiFi standards as target application. The reason this two standards are selected is the extreme nature of their baseband signals—802.11ac has high resolution, medium bandwidth baseband data and 802.11ad has low resolution, wideband baseband data. The FIR DAC specification was driven with the requirements of these two standards in mind. In this section, a brief overview of the features, applications and requirements of these standards is stipulated.

#### 5.1.1 IEEE 802.11ac

The IEEE 802.11ac is a VHT WiFi standard that is transmitted in frequency bands at 5 GHz. It extends the 802.11n standard by adding new channel bandwidth options that achieve higher data rates. It also comes with the advantage of avoiding the crowded 2.4 GHz standard. It supports MIMO to reach gigabit data rates. It has the capacity to support data rates of 7 Gb/s using an 8 x 8 MIMO architecture and a 256QAM modulation. However, for portable devices, only a single spatial stream is envisaged, providing
data rates up to 780 Mb/s. It is also backward compatible with the older WiFi standard such as the 802.11n.

The standard support four contiguous channel bandwidths—20 MHz, 40 MHz, 80 MHz, and 160 MHz—and additional non-contiguous 80+80 MHz channel bandwidth [Int+14]. The 80 MHz, 160 MHz and 80+80 MHz channel bandwidths are new additions compared to the 802.11n 2.4 GHz standard. However, only 20 MHz, 40 MHz and 80 MHz are mandatory, the 80+80 MHz and 160 MHz are stipulated under those the VHT STA can optionally support. The 802.11ac VHT PHY is only defined for OFDM with total number of subcarriers 56, 114, 242, 242, and 484 for the channel widths 20 MHz, 40 MHz, 80 MHz, 80+80 MHz and 160 MHz respectively. The supported modulation methods are BPSK, QPSK, 16-QAM, 64-QAM, and an optional 256-QAM.

An IEEE 802.11ac conforming transmitter has an output spectrum that conforms to the spectrum mask shown in Figure 5.1a. The transmit mask shapes for all of the contiguous channel bandwidths are the same with only the offset frequency changed. A common transmit constellation error is also defined equally for all the contiguous channel bandwidths. There are other additional requirements; however, with respect to the scope of this work they are not applied here.

### 5.1.2 IEEE 802.11ad

Obstruction and propagation losses, at 60 GHz, limit the applicability of the 802.11ad to line-of-sight and short-range services such as wireless display of data, wireless sync, wireless docking, and high speed file transfer between devices. Since the application area which this standard targets are different from the other standards, the possibility of tri-band single radio operation with the 2.4 GHz 802.11n standard and the 5 GHz 802.11ac standard was discussed in Chapter 2.

The IEEE 802.11ad standard, adopted from WiGig, utilizes the unlicensed spectrum from 57 GHz–66 GHz in Europe [Int+14]. There are four available channels that have a channel spacing of 2.16 GHz. The 802.11ad PHY supports four modes of with distinct MCS. They are the Control PHY which is transmitted using $\pi/2$-DBPSK modulation; the SC PHY which is transmitted using $\pi/2$-BPSK, $\pi/2$-QPSK, and $\pi/2$-16QAM modulation methods and at different coding rates; the LP SC PHY which shares the same MCS as the SC PHY except for the absence of the $\pi/2$-16QAM; and finally the OFDM PHY which in addition to the MCS listed in the SC PHY includes 64-QAM in its MCS.

All the first three modes have a chip rate of 1.76 GHz whereas the OFDM mode has a 2.64 GHz sample rate. The standard offers data rates up to 6757 Mb/s in OFDM, 4620 Mb/s in SC, and up to 2503 Mb/s with the low power version of the SC mode. In the transmitter side, a common preamble is defined for both OFDM and SC. While a windowing function is defined for the OFDM, the SC fields are not
<figure><img src="image_51.png" /><figcaption>Figure 5.1: The transmit masks of the IEEE 802.11ac and IEEE 802.11ad standards</figcaption></figure>

windowed. Beamforming training fields are common to all modes. They are added because of the losses at the frequency of transmission of this standard. It makes the transmission directional—hence the name DMG.

A common transmit mask is defined as shown in Figure 5.1b, and different EVM values for each MCS of the OFDM and SC PHYs. The OFDM mode has additional requirements. However, the target applications of this work are mainly low power mobile devices. Transmission with OFDM tend to result in higher power consumption. Hence, the LP SC PHY of the 802.11ad standard is the target mode.

## 5.2 System Level Simulation of Proposed Transmitter Architecture

The purpose of the system level simulation was to obtain a better understanding of the FIR DAC as part of a complete multi-standard transmitter baseband. It helped to set realistic specifications on the rest of the transmitter chain and assess the potential performance limits of the FIR DAC. Furthermore, from a design point of view, a top-down approach helps to keep exploring a single block without losing sight of what the specifications set on the lower level abstraction of that block guarantee on system level.

<table><caption>Table 5.1: Summary of the Specifications of the 802.11ac and 802.11ad standards</caption><thead><tr><th>Parameter</th><th colspan="4">802.11ac</th><th>802.11ad</th></tr></thead><tbody><tr><td>Bandwidth (MHz)</td><td>20</td><td>40</td><td>80</td><td>160</td><td>1760</td></tr><tr><td>Input Resolution</td><td colspan="4">9-bit 10-bit 11-bit 12-bit<br>@ 16-QAM (channelized)</td><td>1-bit<br>@ π/2-QPSK</td></tr><tr><td>Mask (@ offset in MHz)</td><td colspan="4">-40dBr @<br>30 60 120 240</td><td>-30dBr @<br>3060</td></tr></tbody></table>
The system level simulation was carried out for the different channel bandwidths and transmission modes of the 802.11ac and 802.11ad. While it is less challenging to demonstrate the system for the channel bandwidths of 20 MHz and 40 MHz in the 802.11ac case, the potential of the proposed system to integrate with new applications that take advantage of the full potential of the 802.11ac standard would be demonstrated better if the system is validated for the new channel bandwidth flavors of 80 MHz and 160 MHz. Therefore, most of the simulation results would be that of 160 MHz channel bandwidth of the 802.11ac standard.

Complex baseband 802.11ac signals are generated using a reference waveform generator by the IEEE 802.11. The code can generate all channel bandwidths, MCS for both single user and multi-user transmission. As an example, the 160 MHz baseband signal is shown in Figure 5.2.

### 5.2.1 Standard Coexistence

As a 60 GHz standard, 802.11ad offers only a line-of-sight, short-range wireless networking. The fact that it does not interfere with nearby communication is one of its strengths. On the contrary, a 802.11ac transmitter has to still be designed with consideration for its out-of-band noise profile so that it can coexist with others standards. This is despite the fact that the 802.11ac bands at 5 GHz are less crowded than the 2.4 GHz bands.

There are many standards within one octave below the carrier frequencies of the 802.11ac bands. Some of the nearby standards such as GPS, for example, require the interfering emissions in their receive noise floor to be limited to less than or equal to -174 dBm/Hz. This is the same value as the thermal noise floor at room temperature.

If possible the required value for the PSD of the out-of-band noise profile of the 802.11ac transmitter should not also be greater than -174 dBm/Hz. To take this into consideration while designing the FIR DAC transfer function, some practical assumptions can be taken. The expected output PSD at the receiver due to the interfering out-of-band noise of the transmitter can be equated as:

$$PS D_{OOB} - P_{BPF} - P_{ANT} \le -174dBm/Hz \qquad (5.1)$$

Where $P_{BPF}$ and $P_{ANT}$ are the power losses which the out-of-band noise experiences on its way to the receiver. A coexistence bandpass filter at the output of the transmitter can be expected to attenuate the noise by about 40 dB. Then there is coupling loss from antenna of 802.11ac to the receiving antenna of the other standard. This can be taken to be around 12 dB.

$$PS D_{OOB} - 40dB - 12dB \le -174dBm/Hz \qquad (5.2)$$
<figure><img src="image_52.png" /><figcaption>Figure 5.2: 160 MHz Baseband Signal at 802.11ac Transmitter Input</figcaption></figure>

The resulting $PSD_{OOB}$ value is less than or equal to -122 dBm/Hz. If worst case scenario is assumed, then $PSD_{OOB}$ should still be less than -122 dBm/Hz even when transmitting at the maximum allowed output power i.e., 20 dBm in Europe. For the 160 MHz mode of the 802.11ac, this maximum output power divided by the 160 MHz results in a PSD of -62 dBm/Hz in the passband of the 160 MHz channel. The stopband rejection is then estimated relative to this maximum PSD. Therefore, the filter has to attenuate its stopband spurs by at least -60 dB relative to the PSD in the passband of the transmitted output signal for $PSD_{OOB}$ to be lower than -122 dBm/Hz.

The same approach can be followed for the other modes of the 802.11ac. The PSD for the 20 MHz channel bandwidth becomes -53 dBm/Hz in the passband of the 20 MHz channel, which is about 10 dB higher than that of 160 MHz, at the maximum output power of 20 dBm. Everything being the same, the 20 MHz mode of the FIR DAC has to reduce its spurs by further 10 dB for $PSD_{OOB}$ to be lower than -122 dBm/Hz. Therefore, the filter in the 20 MHz mode of the 802.11ac has to be designed for -72 dBc out-of-band attenuation. The good news is that the 20 MHz channel bandwidth can expect a higher SNR from the DSP blocks compared with the 160 MHz due its higher OSR.

### 5.2.2 Transmitter Baseband Architecture

This architecture targets devices that normally operate in a high-throughput 802.11ac standard, but can switch the hardware to an 802.11ad configuration for specific LP multi-Gb/s services. Therefore, the two standards complement each other to deliver power-efficient and high speed communication.
One of the challenges in designing a single-hardware 802.11ac/ad multistandard transmitter stems from the extreme difference in the nature of the signal to be transmitted, as summarized in Table 5.3. The 802.11ac presents high-resolution and narrow-to-medium bandwidth channels. On the other hand, the 802.11ad has a low-resolution broadband input. Additionally, the transmitter mask requirements in the 5 GHz bands are more stringent than those at 60 GHz.

A traditional way of transmitting these data is depicted in Chapter 3 using direct conversion architectures with oversampled DACs followed by low-pass filters to reject the image replicas and respect the required transmission masks. To address a multi-standard within the same hardware, one of the works discussed in Chapter 3 introduces a direct-digital RF modulator for 802.11g WLAN, WCDMA, and GSM/EDGE [Elo+07]. However, this approach is limited to narrow bandwidth signals because of high OSR requirements. In addition, this architecture requires additional image replica filtering or needs highly programmable sample rate converters, as proposed in [Rov+13], to adapt to the appropriate radio channel.

Multi-standard transmitters take advantage of high OSR by introducing noise-shaping $\Delta\Sigma$ modulators to reduce the DAC resolution. This is only possible in the highly oversampled 802.11ac digital front-end path. In the 802.11ad path, the low OSR limits the noise-shaping capability of the modulator. Noise-shaping architectures produce a great deal of quantization noise outside the band of interest, and filtering of this noise is challenging. Otherwise, a high oversampling configuration and an off-chip LC bandpass filter to reject image spectra and minimize the shaped out-of-band quantization noise is required [Moh+12]. However, the required rejection is hardly achievable for large bandwidths with this method.

In order to overcome image and quantization noise requirements, this architecture proposes a low-power multi-mode, multi-standard transmitter based on a 1-bit semi-digital filtering DAC, which is configurable for both narrow band and broadband standards, while optimally reusing hardware. The idea is to configure the semi-digital filter to remove the quantization noise in the 802.11ac mode and to shape the broadband channel according to the mask requirements of the 802.11ad standard. This would advantageously replace the multi-bit DAC and the analog low pass filter, while moderately increasing the complexity of the DSP blocks.

### 5.2.3 DSP Blocks of 802.11ad

The LP SC baseband output of the 802.11ad has a chip rate of 1.76 GHz with a resolution of 1-bit in each I/Q branch in QPSK modulation. To ease filtering of image replicas, the data can be oversampled by a minimum of two to a sample rate of $\ge 3.52$ GS/s at the FIR DAC input. This can be justified by
considering the filtering required to attenuate sampling images sufficiently. A 3.52 GHz clocked DAC output will attenuate the images by at least 2 dB starting from an offset of 2.64 GHz from the center of the desired band of the 802.11ad. However, the required rejection is more than 22 dB, Figure 5.1b, which can be achieved using a reconstruction analog low pass filter following the DAC. Assuming a 2^nd^-order filter, it has at least 12 dB/octave roll-off starting the cut-off frequency. Since 2.64 GHz is more than 3 octaves, the desired image rejection is achieved with the a simple analog circuitry. With no oversampling, the same analysis can be done and a complex high-order analog filtering is required to fulfill the spectrum mask requirements.

<figure><img src="image_53.png" /><figcaption>Figure 5.3: Proposed transmitter architecture for IEEE 802.11ac/ad standards and the DSP part of the 802.11ac</figcaption></figure>

There are different types of oversampling processes that can be implemented for the 802.11ad mode. Oversampling of the 802.11ad LP SC data with interpolation filters is not required at this stage to avoid adding resolution to the data. As that necessitates usage of multi-bit digital to analog converter, or a delta-sigma modulator to convert it to 1-bit. In the second scenario, as the noise shaping capability of a delta-sigma converter is dependent on the OSR of its input data, a modulator with an OSR of two would not achieve high SNR in its in-band. For example, with a 3^rd^-order CRFB 1-bit output delta-sigma modulator at an OSR of two, the peak theoretical in-band SNR is less than 2 dB. It only stabilizes at less than 0.67, i.e. -3.5 dB, of the full scale amplitude [Sch00]. A different approach and a different structure of a modulator may achieve better results than the predicted peak, but generally high OSR is required for the delta-sigma to add value.

There was also a possibility to choose an OSR of more than two. In this scenario, the usage of a
delta-sigma modulator is justified as it shapes the noise with high SNR in its in-band. For example, a 2^nd^-order modulator with an OSR of six is employed here [BA15] for 802.11ad transmitter that also processes higher order modulations such as 16-QAM of the SC mode. For the low power application sought usng the LP SC mode of the 802.11ad, however, an oversampling of two is chosen.

<table><caption>Table 5.2: Frequency Planning for IEEE 802.11ac/ad Transmitter</caption><thead><tr><th>Standard</th><th colspan="4">IEEE 802.11ac</th><th>IEEE 802.11ad</th></tr></thead><tbody><tr><td>Channel Bandwidth (MHz)</td><td>20</td><td>40</td><td>80</td><td>160</td><td>1760</td></tr><tr><td>Half-band filter OSR</td><td>16</td><td>8</td><td>4</td><td>2</td><td>upsample by 2</td></tr><tr><td>New Sample Rates (MHz)</td><td colspan="4">320</td><td>3520</td></tr><tr><td>Common ZOH OSR</td><td colspan="4">11</td><td>N/A</td></tr><tr><td>Multi-standard rate</td><td colspan="4">3.52 GHz</td><td></td></tr></tbody></table>

An oversampling method which does not introduce new data are upsampling, also called zero-insertion, and ZOH response. The SINC response of the ZOH introduces passband drooping which degrades the EVM. Thus, a zero-insertion process is chosen as it requires no additional hardware and keeps the passband ripple unchanged. Zero-insertion leaves the added zeros to be shaped by an interpolation filter. The FIR DAC, in this case, is functioning as an interpolation filter.

### 5.2.4 DSP Blocks of 802.11ac

The required out of band attenuation for the 802.11ac is 60 dBr (discussed in sub-section 5.2.1). The same reconstruction filter as for the 802.11ad is assumed, 2^nd^-order low pass filter with 12 dB/octave roll-off. This filter is not considered in the simulation in this chapter. It is only being assumed for analysis. For the 160 MHz channel bandwidth, a stopband rejection of 60 dBr would be obtained at an offset of 2560 MHz assuming the cut-off frequency of the filter is 80 MHz. In other words, the data has to be oversampled by an OSR of 2560/160 or 16. To operate the FIR DAC at lower speeds, a higher order reconstruction filter than the 2^nd^-order assumed is needed to filter out the images.

An interesting frequency plan is to use a single clock for the FIR DAC for the two standards. To use 3520 MHz clock rate of the 802.11ad at the FIR DAC, the OSR of 802.11ac has to increase to 22 for the 160 MHz mode. Similarly, the other modes of the 802.11ac are oversampled as tabulated in Table 5.2. Intermediate DSP blocks clocking requirements are easily derived from the same frequency synthesizer due to the integer relationship between the different sampling rates. This is a necessary sacrifice to optimize hardware sharing, and it makes the proposed architecture, as detailed in Figure 5.3a, easier to adapt to a complete transceiver implementation.
## Half-Band Filters

<figure><img src="image_54.png" /><figcaption>Figure 5.4: Schematic of the multiplierless half-band filter with coefficients of sub-filter F1 shown</figcaption></figure>

<figure><img src="image_55.png" /><figcaption>Figure 5.5: Schematic of the sub-filter F2 with its 14 long coefficients</figcaption></figure>

In the 802.11ac case, the input data are oversampled using first stage oversampling block to a common sampling rate of 320 MS/s as shown in Figure 5.3b. Half-band filters are the initial interpolating block because of their ability to suppress the lowest image of the input signal without significantly degrading the SNR of the in-band. They are designed based on multiplierless half-band filters [Sar87]. The required coefficients of the filters are generated using functions from a MATLAB® Toolbox [Sch00].

Each half-band filter is designed at $0.23f_s$ cutoff frequency, $f_s$ is sampling rate of the half-band filter, and achieves -89 dB stopband attenuation and a $10^{-4}$ passband ripple. The structure of the half-band filter is shown in Figures 5.4 and 5.5. The half-band filter can be implemented with only 264 additions.

The responses of the main half-band filter and its sub-filters, $F_1$ and $F_2$, are shown in Figure 5.6. Sub-filter F1 has a length of five whereas F2 is 14. Interpolation is included in the structure. The plot shown are for an interpolation by two.

As an illustration, for the 160 MHz of the 802.11ac case, the data is resampled by two to reach an sampling rate of 320 Ms/s. The spectrum of the output of the half-band filter for this case is shown in Figure 5.7.

## ZOH

The 320 MS/s data are then oversampled by a ZOH by a ratio of 11 to reach the final 3.52 GS/s sampling rate. Interpolation using a ZOH method is straightforward but produces residual images at 320-MHz offsets. However, these images will be eliminated by the semidigital low-pass filtering provided to remove
<figure><img src="image_56.png" /></figure>

Figure 5.6: The frequency responses of the main interpolation by two half-band filter and its sub-filters the out-of-band quantization noise. In addition, the passband ripple due to the SINC function of the ZOH does not degrade the integrity of the signal as it passes through at least one half-band filter.

The 160 MHz signal at the output of the ZOH is shown in Figure 5.8. The first image is attenuated by not more than 15dB. As expected, filtering notches as per the OSR are seen at the multiples of the original sampling rate.

## Delta-Sigma Modulator

A configurable third-order 1-bit delta-sigma modulator, at a noise transfer function gain of 1.6, with coefficient sets adjusted for the four different OSR values, delivers the lowest in-band noise floor for each channel bandwidth of the 802.11ac standard. The modulator has scaled coefficients to guarantee maximum input range and stability. This modulator uses the CRFB topology of the Schreier Toolbox [ST05]. The configurability of this block can be implemented at the register transfer level with minimum hardware overhead. A 3rd-order delta-sigma modulator with CIFB architecture whose coefficients are quantized for the four modes of the 802.11ac standard, albeit at relatively higher OSR, is also reported in [Mar+15].

The signal transfer function of the CRFB structure can be made flat in the passband as shown in Figure 5.10 by feeding the input only on the first adder in Figure 5.9 [Sch00]. The noise transfer function is optimized to implement a zero in the in-band of the signal.

The output of the ΔΣ modulator with the ZOH output signal as its input is shown in Figure 5.10.
<figure><img src="image_57.png" /><figcaption>Figure 5.7: Signal at the Output of Half-band Filters for 160 MHz Input</figcaption></figure>

<figure><img src="image_58.png" /><figcaption>Figure 5.8: Output of Zero-Order-Hold for 160 MHz Baseband Input</figcaption></figure>
<figure><img src="image_59.png" /><figcaption>Figure 5.9: Schematic of a 3^rd^-order, 1-bit Delta-Sigma modulator with CRFB topology</figcaption></figure>

<figure><img src="image_60.png" /><figcaption>Figure 5.10: Noise and signal transfer functions of the 3^rd^-order, 1-bit Delta-Sigma modulator with CRFB topology</figcaption></figure>

5.2.5 FIR DAC In Three Modes

Coefficients are designed based on mask requirements. Four transmit masks for each mode of 802.11ac and an additional mask for the 802.11ad standard require five sets of coefficients. In the case of 802.11ac, optimization was performed to utilize one set of coefficients for more than one mode. This is based on the SNR of the delta-sigma modulator output and the spectral mask requirements. For the 802.11ad, the transmit mask and EVM performance of different filter types at different lengths were simulated.
### 802.11ad Mode

FIR filter can be designed with windowing method. The basic idea of this method is that a desired brick-wall filter in frequency domain can be generated by using an infinitely long SINC shaped impulse response in time domain. As this is practically impossible to implement, the length of the SINC function has to be truncated. This results in filter whose frequency response has a transition band with a fast roll-off, but with ripples in the passband. The reason for this behavior is because of multiplication of the SINC function by a rectangular window during truncation.

A better approach is to use a window function which prioritizes some parameter—either passband ripple, stopband ripple or transition band. A Kaiser-Bessel window function has a parameter to trade-off transition band with stopband ripple. This gives the designer a degree of freedom.

Initially the 802.11ad filters was designed based on Kaiser-Bessel window function. The results obtained were a good approximation of the minimum filter length required to achieve the stopband attenuation desired. Then the EVM performance of the designed FIR DACs were compared with the standard requirements. In the case of 802.11ad, the simulated EVM of the designed filter was within a small margin of the standard requirement (-15dB for π/2-QPSK) even at high filter orders. A large EVM contribution from our blocks puts stringent design requirements on remaining analog circuits of the transmitter. Hence, the Kaiser-Bessel function has to be replaced.

<figure><img src="image_61.png" /><figcaption>Figure 5.11: The output of the 802.11ad FIR DAC for 6-bit quantized and 16-bit quantized coefficients. The output fulfills the transmit mask requirements with more than 15dB margin.</figcaption></figure>

Since the receive filter for EVM measurement is specified to be an RRC filter with a roll-off factor
of 0.25 [Int+14], it was only right to design the transmit filter with an RRC filter too. The EVM that resulted with the matched filter approach, -52 dB, was found to be a great improve to the methods tried previously.

A simulated FIR DAC response in the 802.11ad mode is shown in Figure 5.11. The coefficients of the 802.11ad filter are quantized to 6-bit and they are compared with the ideal coefficients, shown with 16-bit quantization. As can be seen, the output of the FIR DAC respects the spectrum mask requirements with a large margin.

## 802.11ac Mode

The delta-sigma modulator coefficients can be reconfigured for each mode of the 802.11ac. It operates with the OSR values shown in Table 5.2. The purpose of the FIR DAC transfer function is to cancel the high pass noise shape coming from the delta-sigma modulator. A single filter transfer function can be used for 20 MHz, 40 MHz, and 80 MHz modes and still fulfill the transmit mask requirements of each of the three modes.

<figure><img src="image_62.png" /><figcaption>Figure 5.12: The FIR DAC filter roll-off cancels the rising quantization noise from the ΔΣ-modulator output in the 160MHz mode of the 802.11ac</figcaption></figure>

For the 160 MHz mode, a different filter is designed. The main reason is the clipping of the subcarriers at the edge of the passband corrupts the EVM when a lower cut-off frequency is used. When the 160 MHz filter is used for the other lower channel bandwidth modes, the quantization noise raises above the transmit mask before it is canceled by the FIR DAC.

A 60 dBr stopband rejection is required of the 160 MHz filter. This requirement applies only at the
frequencies where transmit mask plateaus ($\frac{3}{2}f_s$ in Figure 5.1a). For frequencies before $\frac{3}{2}f_s$, the filter need only cancel the delta-sigma modulator shaped noise to less than the mask requirements. To take advantage of this fact, the filters are designed based on an equiripple method with decaying stopband. It has the advantage from equiripple method of having low ripple passband. A stopband that decays by $\frac{1}{f^N}$ avoids the problem of using a long equiripple filter to address the stopband requirements that exist at $\frac{3}{2}f_s$ but not necessarily earlier frequencies. The passband ripple is set to less than 0.5 dB, the filter order is 63 in both the 160 MHz and the combined 20 MHz, 40 MHz and 80 MHz modes. Since the filters has symmetrical impulse response, they have linear phase responses.

The response of the FIR DAC and the delta-sigma modulator in the 160 MHz mode of the 802.11ac are shown in Figure 5.12. It can be seen that the rising quantization noise at the output of the modulator is canceled by the decaying stopband of the FIR DAC response to less than the requirements of the transmit mask. The margin between the stopband and the transmit mask is large because the stopband rejection value is designed considering standard coexistence.

<figure><img src="image_63.png" /><figcaption>Figure 5.13: Simulated EVM with 16-QAM modulation in the 160MHz mode of the 802.11ac</figcaption></figure>

The EVM of the 160 MHz 802.11ac mode FIR DAC was simulated using Matlab®, and the result for 16-QAM is shown in Figure 5.13. The results compared with the standard requirement leaves a
12dB margin for the subsequent analog blocks of the transmitter. The results for the other modes of the 802.11ac is in [GFK16a]. The EVM simulation method is discussed in Appendix-2.

## 5.3 From Transfer Function to Circuit Parameters

A configurable FIR DAC is implemented for the 160 MHz 802.11ac and the 802.11ad modes. The circuit level discussions are the subject of Chapter 6. In this section, the system level results obtained are further developed in order to arrive at a thorough multi-standard FIR DAC specification. The discussion include filter coefficient quantization, and choices concerning the FIR DAC performance along the lines of the discussion in Chapter 4.

### 5.3.1 Coefficient Quantization

The designed 16th-order 802.11ad filter transfer function with ideal and finite coefficient resolutions is shown in Figure 5.11. Filters with arbitrary valued coefficients are prone to process gradient mismatches, require custom design and layout of coefficients, and have large current source count. Coefficient quantization simplifies the design and allows flexible reconfiguration. Nonetheless, coefficient quantization limits the achievable stopband attenuation level of the filter. The coefficients are quantized to 6-bit. It is interesting to see the degradation due to quantization effects. In the 802.11ad standard, the adjacent channel starts at an offset of 1.22 GHz from the channel center. Quantization with less than 6-bit introduces leakage of up to 15 dB [GFK15].

The 20/40/80 MHz mode of the 802.11ac filter design benefits from a higher SNR resulting from the higher OSR of the respective bandwidths at the ΔΣ modulator. Hence, 6-bit quantized coefficients meet the requirements of each mode associated with this filter. For the 160-MHz coefficient set, a ratio of 2⁸ exists between the biggest center tap coefficient and the smallest. This is done to reach a higher stopband rejection. This ratio, also called coefficient spread, becomes 2⁶ for the 802.11ad and the 20/40/80-MHz cases. Figure 5.15a has the quantized coefficient transfer functions in one plot.

### 5.3.2 Multi-standard FIR DAC Specifications

As discussed in Chapter 4, the standard deviation of coefficient mismatch can be set to the maximum tolerable stopband value of the transfer function. In the 160 MHz 802.11ac mode, the coefficient values were simulated with a 1.7% standard deviation, and the resulting transfer function is in Figure 5.14. The simulation assumed all the unit elements realizing a coefficient have an independent Gaussian mismatch as discussed in Chapter 4.
<figure><img src="image_64.png" /><figcaption>Figure 5.14: The transfer function of the 160MHz of the 802.11ac mode with a unit coefficient mismatch of 1.7% standard deviation.</figcaption></figure>

A 1.7% standard deviation introduces almost 3dB increase from the maximum stopband level desired. While it is possible to go further with smaller mismatch requirement, it comes at the cost of area of the current source transistor implementing a coefficient. This is, then, the first design choice to be made when proceeding to FIR DAC implementation.

To implement the two quantized coefficients, those of 160 MHz 802.11ac and 802.11ad, in one FIR DAC circuit, one set of coefficients must be represented by the other. Since the 802.11ac mode has the highest mismatch requirement, the 802.11ad coefficients has to be constructed from it. The 802.11ac coefficients are composed of unit elements, as in unary implementation, with specified mismatch requirements. Then the 802.11ad coefficients has to be integer multiples of these unit coefficients so that they will be constructed using simple analog circuit addition and subtraction. It is important to mention that when each set of coefficients are quantized, each coefficient of a particular set is represented as an integer multiple of a unit coefficient of that coefficient set. Therefore, it should be understood that the 802.11ac and 802.11ad coefficients are quantized by 8-bit and 6-bit, respectively, and their center taps would be 2<sup>8</sup> and 2<sup>6</sup> times the unit coefficients respectively.

The choice of ratio between one set of coefficient and another of a configurable FIR DAC circuit can be made by equating the DC-sum of their coefficients. It is as if equating the full-scale current, in a current steering implementation, of the two coefficient sets. The original sum of the 802.11ad coefficients is 187 11ad-unit coefficients and those of 160 MHz 802.11ac are 4974 11ac-unit coefficients. A ratio of
<figure><img src="image_65.png" /><figcaption>Figure 5.15: The transfer functions and impulse responses of the 20/40/80 MHz, 160 MHz of the 802.11ac and the LP SC 802.11ad mode. The samples in the impulse responses are scaled according to the number of unit coefficient elements required to implement each coefficient.</figcaption></figure>

twenty between the two unit coefficients results in 3740 11ac-unit coefficients for 802.11ad mode, and 4974 11ac-unit coefficients for the 802.11ac mode. Therefore, a maximum of 3740 unit coefficients can be shared between the two modes. Figure 5.15b illustrates the coefficients values relative to the unit coefficients of the combined multi-standard FIR DAC.

All the coefficients of the 802.11ad mode may not be obtained by addition and subtraction of the 802.11ac coefficients. In this case, some unit coefficients are added for fine-tuning the sums or difference

<footnote>‡ $I_{unit}$ is unit coefficient current</footnote>

<footnote>§ Current-Steering Architecture Assumed</footnote>
<table><caption>Table 5.3: Summary of the specifications of the multi-standard FIR DAC</caption><thead><tr><th>Parameter</th><th>802.11ac mode</th><th>802.11ad mode</th></tr></thead><tbody><tr><td>Clock Speed</td><td>f<sub>s</sub></td><td>f<sub>s</sub></td></tr><tr><td>Bandwidth</td><td>f<sub>s</sub>/22</td><td>f<sub>s</sub>/2</td></tr><tr><td>Unit Coefficient Mismatch, σ<sub>u</sub></td><td>1.7%</td><td>1.7%</td></tr><tr><td>Coefficient Spread</td><td>2<sup>8</sup></td><td>2<sup>6</sup></td></tr><tr><td>Load Resistance <sup>§</sup></td><td>R<sub>load</sub></td><td>R<sub>load</sub></td></tr><tr><td>Full-Scale Swing <sup>‡</sup></td><td>4974I<sub>unit</sub>R<sub>load</sub></td><td>3804I<sub>unit</sub>R<sub>load</sub></td></tr><tr><td>Number of UCC Only in</td><td>1246</td><td>76</td></tr><tr><td>Number of UCC Shared</td><td colspan="2">98% of 802.11ad used in 802.11ac</td></tr></tbody></table>

to make them equal to the actual 802.11ad values.

The specifications of the multi-standard FIR DAC are summarized in Table 5.3. The parameters can be used as a starting point of a multi-standard FIR DAC circuit design. Clearly, the FIR DAC has a single sample rate for the two modes. However, the bandwidth of the 802.11ac mode is smaller than the 802.11ad mode. However, the stringent mismatch requirement in the 802.11ac mode is consistent with the required higher stopband rejection in this mode. The output of the two modes are taken at the same nodes. Their load resistors are also the same. Only their output swing is scaled according to their number of unit coefficients.

## 5.4 Summary and Conclusions

In this chapter, a multi-standard transmitter architecture based on a LPF FIR DAC structure is validated on system level. The specific parametric values for each DSP block of each mode of the transmitter are presented. Further, the response of each block for an 160 MHz OFDM signal are included.

The multi-mode FIR DAC specification that is developed at the end of the chapter will be an input to the next chapter. The coefficients of the multi-mode FIR DAC implemented in Chapter 6 will be the same as those discussed in this chapter. However, a high pass FIR DAC delay line is used for implementation of the circuit. The transistor level implementation of the FIR DAC depends on the coefficient values developed here in this chapter.