# From Space to Industrial Applications: the Latching Current Limiter as Active Current Protection

Alex Musetti, Alessandro Soldati, Pablo Fernandez, Manuel Arias Perez de Azpeitia

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Alex Musetti, Alessandro Soldati, Pablo Fernandez, Manuel Arias Perez de Azpeitia. From Space to Industrial Applications: the Latching Current Limiter as Active Current Protection. The 26th European Conference on Power Electronics and Applications, GDR SEEDS France & EPE Association, Mar 2025, Paris, France. 10.34746/epe2025-0257. hal-05085538

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# From Space to Industrial Applications: the Latching Current Limiter as Active Current Protection

Alex Musetti(1), Alessandro Soldati(1), Pablo Fernandez Miaja(2) and Manuel Arias Perez de Azpeitia(2)

(1)UNIVERSITY OF PARMA - ITALY; (2)UNIVERSITY OF OVIEDO - SPAIN

Parma, Italy; Gijon, Spain

Tel.: +39 0521 905 833

E-Mail: alex.musetti@unipr.it, alessandro.soldati@unipr.it,fernandezmiapablo@uniovi.es, ariasmanuel@uniovi.es

URL: https://pexlab.unipr.it/

***Index Terms***—DC circuit breaker, Synchronous Buck Converter, Fast fault detection, Fault handling strategy, Inrush current.

***Abstract***—This paper presents the Industrial Latching Current Limiter, a converter topology for fast fault detection and management and inrush current limiting in industrial power systems. By integrating a bypass transistor and switching elements in a synchronous buck converter configuration, it enhances efficiency supporting continuous operation under overload conditions.

## I. INTRODUCTION

The DC circuit breaker is a critical component in modern DC power systems, playing essential roles in both controlling and protecting the power grid. Over time, system protection has evolved significantly, transitioning from simple, rudimentary devices with limited capabilities to sophisticated systems equipped with advanced hardware [1]. These modern protective systems are designed to be more precise and selective in their fault detection and operational response, enabling them to handle a wider range of contingencies with greater accuracy [2]. However, this increased complexity also demands more advanced analytical efforts and refined control algorithms to ensure optimal performance in identifying faults, minimizing disruptions, and safeguarding the grid from damage. The continuous development of DC circuit breakers reflects the growing need

for speed, and flexibility in an era where power systems are becoming increasingly decentralized and integrated with renewable energy sources [3].

While conventional electromechanical circuit breakers have a proven track record of being effective and reliable for circuit protection, emerging power distribution technologies and architectures, such as DC microgrids, demand enhanced interruption performance and faster speeds. The need for quicker operation, coupled with advancements in power semiconductor technologies, has driven significant research and development in newer circuit breakers. In High voltage and medium voltage applications, Hybrid DC Breaker (HDCB) take a key role for grid protection [4]. In a conventional HDCB [5], the semiconductors in the commutating branch carry the fault current until the electromechanical switch of the primary branch quenches the arc and restores sufficient voltage. Solid-state circuit breakers (SSCBs) use power semiconductors enabling faster switching, making possible smoother turn-off controls. While ideal for fast, precise applications, SSCBs are less suited for high-current environments [6].

Among the different circuit topologies, a possible solution can come from satellite power systems, those must endure long-term operation in space without any possibility of maintenance. To prevent failure propagation caused by short circuits, overcurrent-protected power
distribution lines are implemented, isolating faults within any subsystem. A commonly used protection device is the latching current limiter (LCL) [7], traditionally linear regulators used with a PMOS transistor. However, the PMOS design has high dissipation and requires large size to handle maximum current. Silicon Carbide (SiC) N-type transistors have been proposed as a better alternative to reduce losses and increase voltage rating [8]. Another alternative is the switching LCL (SwLCL) [9], [10], which uses a synchronous buck topology that switches during fault occurrence, limiting the output current. This design includes an LC filter to reduce harmonics and benefits from wide-bandgap materials like Gallium Nitride (GaN) and SiC to minimize switching losses and allow higher frequencies, reducing size [11].

The SwLCL has lower dissipation compared to the linear one and can operate continuously under overload conditions with proper design. During the normal operation the SwLCL have the pull up transistor fully on and the filter inductor is involved in the current path; this is not an optimal solution, since the transistor needs derating. Additionally, if the current request on the load changes, more power dissipation on the inductor could arise. To fight these issues, considering the more permissive design standards in industrial environment than in aerospace, in this work an additional transistor is added to the circuit to bypass the switching path and the inductor during the normal behavior of the system; this new topology is called Industrial LCL (ILCL). This circuit actively handles faults by maintaining a controlled current regime, but also acts as an inrush current limiter during system startup. The use of this technology in the industrial environment makes possible the implementation of digital controls, which are little used in the space field given the high cost of RADHARD-qualified microcontrollers.

This paper presents the analysis and design of ILCL. The implementation is described, and the basic equations are provided to facilitate the design; also the control algorithm and its tuning are described. A first validation has been performed through a non-ideal simulation using PLECS.

The prototype PCB has been developed and is shown in Fig. 1; the main components of this design are highlighted in red and those will be discussed in section III and IV.

## II. ILCL CONCEPT

ILCL scheme is visible in Fig. 2a, where $M_1$ is the bypass transistor, $M_2$ and $M_3$ are the switching

<figure><img src="image_2.png" /><figcaption>Fig. 1: ILCL board Prototype, in Red are highlighted the main points of the design.</figcaption></figure>

transistors of the synchronous buck converter. C and R represent the load and L is the filter inductor.

As shown in Fig. 3, after the system startup the capacitor is initially discharged: to prevent the initial overcurrent, the system will control the capacitor charge limiting the inrush current. After reaching the nominal voltage, $M_1$ is turned on while $M_2$ and $M_3$ are turned off. If the current exceeds a predefined limit, $M_1$ is immediately turned off and $M_2-M_3$ start switching, to limit the fault current. This condition persists until the current falls below the minimum fault threshold, at which point the bypass takes over or when the trip-off time expires. The functioning parameters of the ILCL were taken from Aerospace standards since they are typically more strict than in the industrial field.

### A. ECSS Regulation

The ECSS engineering standards establish technical criteria for space systems to create consistency within the European space industry. The ECSS-E-ST-20-20C [12] standard specifically addresses linear LCLs defining the requirements for current and time related to fault response depending on LCL class, which is defined from the nominal current. A typical LCL response related to an overcurrent condition is shown in Fig. 4.

If the current goes over “Min limitation current”, the first overshoot must be bounded behind the “Max Current overshoot”, after the first dynamic, the current can drops to zero, and start limiting the fault between “Min” and “Max limitation current”. The “Max overshoot recovery time” defines the max settling time to
<figure><img src="image_3.png" /><figcaption>Fig. 2: ILCL converter scheme and equivalent circuits depending on the switch status.</figcaption></figure>

<figure><img src="image_4.png" /><figcaption>Fig. 3: Flowchart describing the ILCL system operation.</figcaption></figure>

<figure><img src="image_5.png" /><figcaption>Fig. 4: Typical LCL response during overcurrent, taken from ECSS-E-ST-20-20C [12].</figcaption></figure>

reach current regime after a fault occurs. The “Trip-off time” is the maximum duration for current-limited operation after a fault occurs; if the fault persists beyond this limit, the system will shut down. For this design we adopted as a target a class-10 LCL, which criteria are defined in Table I.

<table><caption>TABLE I: LCL class-10 specifics from ECSS-E-ST-20-20C.</caption><thead><tr><th colspan="2">LCL class-10</th></tr></thead><tbody><tr><td>Nominal current [A]</td><td>10</td></tr><tr><td>Min limitation current [A]</td><td>11</td></tr><tr><td>Max limitation current [A]</td><td>14</td></tr><tr><td>Max current ripple [A]</td><td>3</td></tr><tr><td>Max Current overshoot [A]</td><td>50</td></tr><tr><td>Time to current Overshoot [µs]</td><td>5</td></tr><tr><td>Max overshoot recovery time [µs]</td><td>300</td></tr><tr><td>Trip-off min [ms]</td><td>1.5</td></tr><tr><td>Trip-off max [ms]</td><td>3</td></tr></tbody></table>
### III. CONVERTER DESIGN

Due to the industrial cut of this design, the power rating chosen is $P = 1$ kW, the current rating is defined by ECSS guidelines in Table I, so the DC link voltage is $V_{DC} = 100$ V. Due to the unpredictable nature of a fault, the resistive load is supposed to vary between $R = 10$ Ω in the nominal condition and $R = 0.1$ Ω in case of a full short circuit, with admissible all intermediate cases. For simplicity of calculation, the resistive load will be stated as admittance $G = 1/R$. The chosen capacitance related to the value of $V_{DC}$, taking into consideration the capacitance value of industrial DC links [13], has been chosen as $C = 100$ µF. In Fig. 2b and Fig. 2c the switching behavior in the on and off states of ILCL are described, from which is obtained, in the hypothesis of continuous conduction mode (CCM), the well known equations:

$$ \begin{cases} \Delta I_{L \text{ on}} = \frac{v_i - v_o}{L} DT \\ \Delta I_{L \text{ off}} = -\frac{v_o}{L} (1 - D) T \end{cases} \quad (1) $$

where $v_i$, $i_L$ and $v_o$ are the input voltage, inductor current and output voltage respectively and $D$ is the duty ratio defined as $D = v_o/v_i$. It is possible to derive the minimum value of inductance to not exceed the maximum current ripple defined in Table I substituting $D$ in (1),

$$ \Delta I_{L \text{ on}} = \frac{T}{L} \left( v_o - \frac{v_o^2}{v_i} \right). \quad (2) $$

By deriving $I_{L \text{ on}}$ as a function of $v_o$, it is possible to find the ripple worst case $v_{o_{wc}}$ to calculate $L_{\min}$,

$$ \frac{dI_L}{dV_{\text{out}}} = \frac{T}{L} \left( 1 - 2 \frac{v_o}{v_i} \right) = 0 \Rightarrow v_{o_{wc}} = \frac{v_o}{2} \quad (3) $$

substituting $v_{o_{wc}}$ in (2) $L_{\min} = 8.33$ µH can be obtained using the highest ripple possible defined by Table I, applying a margin of safety, $L = 10$ µH.

#### A. Devices selection and inductor sizing

By differentiating the bypass ($M_1$) and switching ($M_2, M_3$) lines, the device sizing of the ILCL can be tailored. $M_1$ should be an high-current device with low $R_{on}$ minimizing conduction losses and the occupied area, for which a high-current silicon device (IPF067N20NM6ATMA1) has been chosen. In nominal conditions $R_{on} = 2.1$ mΩ, so the power losses at $I = 10$ A are $P_j = 210$ mW resulting in an efficiency

<figure><img src="image_6.png" /><figcaption>Fig. 5: Thermal network of switching mosfets and inductor during switching operation in the hypothesis on adiabatic regime.</figcaption></figure>

$\eta = 99.98\%$; While during fault the operation takes place in a few milliseconds not affecting the overall efficiency.

Due to the short operating time of $M_2$ and $M_3$, it is possible to assume an adiabatic regime; the thermal behavior relies only in the transient resulting in the thermal network visible in Fig. 5. This allows optimizing the chosen devices considering the worst case of a single pulse of the trip-off time duration. Needing a very high switching frequency and to minimize losses, GaN transistors (LMG3422R030RQZT) are chosen for the switching stage. A similar assumption can be made for the inductor $L$, for which it is possible to minimize its area occupancy by optimizing the temperature increment over the time span of operation. Because of the preliminary nature of this paper, those aspects of the design will be deferred to future studies using finite elements method to improve the design.

### IV. CONTROL DESIGN AND VALIDATION

In this application, the response time of the first overshoot is crucial since the bypass path cannot limit the current rise in any way. To achieve the response time criteria defined in Table I, the shutdown control should be analog in order to minimize the response time, while the current control could be digital, to maximize the performances, minimizing the number of components.

#### A. Analog Control

In Fig. 6 the analog control is visible. The load current is sensed by a shunt resistor and amplified by an operational amplifier (OPA354AIDDAR) in non-inverting configuration. The op-amp output signal is sampled by an ADC for the digital control and is the positive input of a comparator (TS3011ICT), when the
current exceeds the minimum threshold defined in Table I, the comparator output becomes active, resetting the S-R latch (SN74AUP2G02DCUR) and turning off $M_1$. The turn-on of $M_1$ is controlled by the microcontroller. By choosing these components, also taking into account

<figure><img src="image_7.png" /><figcaption>Fig. 6: Analog shutdown scheme controlling the bypass transistor $M_1$ turn-on and turn-off.</figcaption></figure>

the shutdown time of $M_1$ comprehensive of opto-coupler and gate driver delay, the response time of the system is $t_d = 104$ ns. In order to limit the current during the first overshoot according to the specification of Table I, an inductance in series to the fault current path should be at least of $L_p = 260$ nH in the worst case scenario of a complete short circuit on the load. An inductor can be put in the current path or, while it is very small, it can be supplied by the parasitic inductance of the wiring harness.

## B. Digital Current Control

For the digital control the Nucleo Board STM32 H563ZIT6U has been chosen. From (1) the general analytical average model of buck converter can be obtained and is represented in the following equations:

$$L \frac{di_L}{dt} = v_x - v_o; \quad C \frac{dv_o}{dt} = i_L - G v_o \quad (4)$$

where $v_x = v_i D$ is the product of the inputs. The open loop transfer function is then obtained as

$$H(s) = \frac{I_L}{V_x} = \frac{G + sC}{s^2 LC + sLG + 1}, \quad (5)$$

It can be seen that the system consists of a zero with negative real part, thus minimum phase, and two conjugate complex poles, resulting in an oscillating response. In order to properly control the system, a full state feedback system [14] can be implemented.

From (4) it is possible to define the state space equation as,

$$\begin{cases} \dot{x} = Ax + Bv_x \\ y = Cx + Dv_x \end{cases} \quad (6)$$

where $x = [i_l, v_c]^T$ are the system states needed to being sensed and $v_x$ is the input, the state matrixes are

$$A = \begin{bmatrix} 0 & -1/L \\ 1/C & -G/C \end{bmatrix}, \quad B = [1/L, 0]^T, \quad C = I_2, \quad D = 0 \quad (7)$$

which describes the different features of the system, in this particular case while $C$ is the $2 \times 2$ identity matrix, the outputs are equal to the states. By using the pole placement technique, a pole-zero cancellation can be achieved, simplifying the system to a first-order model. Defining $A_{cl} = A - BK$, where $K = [K_1, K_2]$, it is possible to change the poles position rearranging the state matrix as follows:

$$\dot{x} = A_{cl}x + BK_r v_x \quad (8)$$

While the eigenvalues of $A_{cl}$, $\det(A_{cl} - \lambda I) = 0$ describes the poles, solving the following system it is possible to redefine the poles position,

$$\begin{cases} \lambda^2 + (1 + K_1)\lambda + (K_1 + 4K_2) = 0 \\ a\lambda^2 + b\lambda + c = 0 \end{cases} \quad (9)$$

it is possible to find $a, b$ and $c$ imposing the solutions $\lambda_{1,2}$ of the second degree equation, from (5) it is possible to find the exact value of the zero to perform the pole/zero cancellation with $\lambda_1 = -1100$ rad/s and $\lambda_2 = -20000$ rad/s to settle the remaining pole at the desired cutoff frequency, achieving the wanted settling time not to exceed the “Time to current Overshoot” defined in Table I. Solving the system equation in (9) it is possible to find $K = [0.2, -1]$. While the DC gain of the output is not controlled, the DC gain of the step response $K_{DC}$ can be found and finally $K_r = 1/K_{DC}$, that in this case is $K_r = 5$.

In Fig. 7 the comparison between the open loop and closed loop bode diagrams is shown, the latter is a first order response as expected.

Since the parameters value may be subject to tolerance and given the uncertain nature of the load during fault, a study based on Robust Parametric Control [15] has been conducted, to have the appropriate response to the different combination of parameters. For $L$ and $C$ a 20% tolerance of the nominal value has been chosen; the load $G$ can vary as defined in Sec. III. As shown in Fig. 8 all the possible combinations of parameters result in a stable system response, for clarity only 100 of these combinations are visible in the graph.

A PLECS simulation has been built to validate the proposed control, adding all the non-idealities related to
<figure><img src="image_8.png" /><figcaption>Fig. 7: Bode diagram comparison between open loop and closed loop ILCL, in blue the open loop diagram and in red the closed loop one.</figcaption></figure>

<figure><img src="image_9.png" /><figcaption>Fig. 8: Step response of the system in different parameters settings, the color map defines the deviation from nominal values. The gradient defines how far the various tests deviate from the nominal situation of the parameters, blue defines lower values (on average) of the nominal, and yellow higher values.</figcaption></figure>

a real system implementation as shown in Fig. 9. With a switching frequency of $f_{sw} = 1$ MHz, the sampling frequency has been set at $f_s = 200$ kHz, the delay chain related to the actuators (Opto-couplers, Gate drivers and devices) has been defined from datasheets as such as the

<figure><img src="image_10.png" /><figcaption>Fig. 9: Detailed schematic of the proposed ILCL, for the validation of the system in simulation.</figcaption></figure>

ADC delay. The duty cycle is saturated at $D = 0.95$ and some white noise on the sensed signals has been added.

<figure><img src="image_11.png" /><figcaption>Fig. 10: PLECS current scope data in different conditions, the blue curve represents a full short circuit condition with $R = 0.1 \Omega$, the green curve represents a mid overcurrent condition with $R = 5 \Omega$ and the red curve represents a full load condition with $R = 10 \Omega$ in the situation of inrush current protection.</figcaption></figure>

The current curve can be seen in the Fig. 10 and is consistent with what was expected from the control design; the red curve represents the inrush current condition at full load, in this case the current setpoint is lower while the nominal current is 10 A. The green curve is the worst case fault scenario as defined in (3) while the blue curve represents a full short circuit condition. In all those cases the current ripple respects the criteria stated in Table I.
V. CONCLUSION

This paper presented the design and analysis of the Industrial Latching Current Limiter (ILCL), a converter topology that addresses the growing demand for fast fault detection and inrush current limiting in industrial power systems. The ILCL offers high efficiency, fast switching speeds, and low power dissipation.

The design process involved optimizing the topology to handle overcurrent conditions and ensuring continuous operation under overloads. The inclusion of a bypass transistor and switching elements in a synchronous buck converter configuration allowed for both current limiting and fault management, while retaining the highest efficiency during normal operation. A hybrid control scheme, combining analog and digital elements, was implemented to ensure fast response times and precise control, further validating the effectiveness of the system.

The ILCL demonstrates interesting features, such as low power losses due to the bypass current path, enhanced reliability, and adaptability to industrial environments. Preliminary simulation results, using PLECS, validated the approach, suggesting the circuit feasibility for real-world applications. Future works will focus on optimizing the devices and inductor design to minimize area and further test the system to achieve full validation in industrial settings.

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