# Parasitic Capacitances Effect on Transient Current Sharing in Parallel Connection of GaN FETs

Salvatore Musumeci, Vincenzo Barba, Michele Pastorelli, Marco Palma

► To cite this version:

Salvatore Musumeci, Vincenzo Barba, Michele Pastorelli, Marco Palma. Parasitic Capacitances Effect on Transient Current Sharing in Parallel Connection of GaN FETs. The 26th European Conference on Power Electronics and Applications, GDR SEEDS France & EPE Association, Mar 2025, Paris, France. 10.34746/epe2025-0126. hal-05097519

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# Parasitic Capacitances Effect on Transient Current Sharing in Parallel Connection of GaN FETs

Salvatore Musumeci, Vincenzo Barba,
Michele Pastorelli

POLITECNICO DI TORINO
Corso Duca degli Abruzzi, 24
Turin, Italy

Tel.: +39 0110907127.

E-Mail: salvatore.musumeci@polito.it,
vincenzo.barba@polito.it,
michele.pastorelli@polito.it

URL: https://www.polito.it/

Marco Palma

EFFICIENT POWER CONVERSION
Corso Europa, 603
Volpiano (TO), Italy

Tel.: +39 3487616177.

E-Mail: Marco.Palma@epc-co.com

URL: https://www.epc-co.com/

## Acknowledgements

This research was funded by Project "Innovative Solutions for Renewables in Energy Communities (ISoREC)" through the Italian Ministry of University and Research (MUR) Progetti di Rilevante Interesse Nazionale (PRIN), Bando 2020 under Grant 202054TZLF.

## Keywords

«Device application», « Gallium Nitride (GaN)», «Parallel operation», «Parasitic elements».

## Abstract

The paper deals with the impact of parasitic capacitance on the switching operation of GaN FET devices in parallel connection. A suitable experimental board has been developed to investigate the switching transient current share features for several GaN FETs connected in parallel to perform a single high-current switch. Every device can be driven independently, and a source shunt per each GaN FET monitors the transistor current. Simulation runs and experimental tests show the switching mechanism and parameters involved in the transients' current share. The paper aims to give insights into the designing boards of paralleled GaN FETs regarding the influence of parasitic capacitances in the transient current peak distribution to find the maximum parasitic capacitance reachable without overcoming the limit of impulsive device current. The study

contributes to developing reliable power modules made of several GaN FETs in parallel connection.

## Introduction

In power electronics, the use of emerging high electro-mobility devices like Gallium-Nitride (GaN) FETs is growing due to their remarkable advantages. Especially in low-voltage applications (<100 V), GaN-based power transistors are becoming popular due to their high performance compared to their silicon (Si) device counterparts [1]. To extend the current capability for applications such as inverters for mild hybrid electric vehicles or DC-DC converter [2] charging for battery energy storage systems, the parallel connection of GaN FETs can be arranged [3]. In a parallel connection, the current share shows a mismatch in switching transients as well as in on-state operation due to the differences among technology parameters such as the threshold voltage, $V_{GSth}$, the transconductance $g_{ts}$, the junction temperature $T_j$, the inner gate resistance, and the parasitic capacitances. Furthermore, the output electrical parameters, such as the driver gate resistance and the parasitic inductances, influence the current mismatch [4]. In the proposed paper, the current transient due to the parasitic capacitances and inductances' can be investigated. Simulation results and experimental assessments have been carried out through a specifically developed board used as a workbench performing several tests to investigate the current sharing in transient switching. A testing methodology addressed to separate the contribution of the transient current behavior of
the parasitic capacitance concerning stray inductances has been developed. The parasitic capacitances effect evaluation provides guidelines for optimizing the performance of GaN FET devices in parallel connections. The results allow us to evaluate the maximum peak transient current at power-on relative to the parasitic capacitances caused by the devices and the board's layout. The pulse peak current must not exceed the limits of a single device in terms of value and duration described in the GaN FET datasheets. The dynamic sharing of the drain current is focused on considering the parameters spread impact, the gate driver influence, and the effective layout solutions.

## Testing methodology

The methodology for analyzing the contribution of parasitic capacitances is based on a suitable gate control strategy acting on a programmable delay for each device. For this purpose, an experimental electronic board was developed with several devices in parallel (up to 12 low-voltage GaN FETs), in which every component is driven by its gate driver circuit. For each device, the source current can be evaluated through a resistive shunt. The tests are carried out considering the paralleled devices, (EPC2032 from EPC manufacturer, V<sub>DSmax</sub>=100V, I<sub>D</sub>=101A at 25°C, pulse current I<sub>Dpulse</sub>=408A for 300µs at 25°C) supplying an inductive load (L<sub>load</sub>= 90 nH) and a freewheeling super-fast diode, as illustrated in the schematic circuit model of Fig. 1.

<figure><img src="image_2.png" /><figcaption>Fig. 1: Electrical schematic of the system used for the test with the equivalent electrical model of the board with GaN FETs connected in parallel.</figcaption></figure>

The PCB equivalent parasitic capacitance board (C<sub>PCB</sub>) and GaN FETs output capacitances (C<sub>oss</sub>) is also reported. The DC input voltage is fixed at 24V. In the tests, GaN FETs are driven with a switching frequency of 100 kHz and duty cycle

d=0.5. C<sub>oss</sub> = C<sub>DS</sub> + C<sub>GD</sub> represents the non-linear output capacitance of a single GaN FET [5]. The C<sub>PCB</sub> is related to the layout of the board as described in the next subsection. The inductances arrangement in Fig.1 is essential in the test method presented. L<sub>diode</sub> is the parasitic inductance of the diode (in this case L<sub>diode</sub>=20 nH). L<sub>d</sub> represents the inductance that interconnects the GaN FETs with each other (in this case is estimated at 2.7nH). L<sub>D</sub> is the inductance that connects the board's drain to the load. It has been designed to be 20 times larger than L<sub>d</sub>. This design choice allows to observe the contribution at turn-on of the load inductive current and the discharge currents of the global parasitic capacitances in the transient current peak. To understand better this procedure, several simulation tests (in LTSpice software with a developed GaN FET model [6]) at turn-on are carried out considering n=8 devices in parallel connection. Only one GaN FET (GaN1) is activated while the remaining n-1 are kept off-state (the worst case for the current flowing in the device turned on). The simulations are repeated for various values of L<sub>diode</sub> + L<sub>D</sub>: 0.1%, 1%, 10%, 50%, and 100% concerning the actual value of the PCB design considered. An ideal LTSpice diode in antiparallel of load inductance is considered for the sake of simplicity to focus on the GaN FET performance during the transient operations, without introducing current and voltage oscillations during transients, due to the real diode parasitic components. In Fig. 2a, the top section displays waveforms of the board drain-source voltage (V<sub>DS</sub>), load current (I<sub>load</sub>), and the current in the board drain (I<sub>D</sub>).

In the lower section of Fig.2a, the waveforms of the current conducted by GaN FET1 (I<sub>SGaN1</sub>), and by GaNFET,n (I<sub>SGaN,n</sub>), are shown. In Fig 2a the current peak I<sub>SGaN1</sub> is due to the effect of the V<sub>DS</sub> fall at GaN FET1 turn-on with the parallel parasitic capacitances (see Fig. 1).

Furthermore, the current peak is affected by the load current rising. At the growth of L<sub>D</sub> +L<sub>diode</sub>, the current slope decreases, and the current peak is affected only by the global parasitic capacitances as shown in Fig. 2b, where the I<sub>SGaN1</sub> peak remains constant at I<sub>D</sub> amplitude variation. Therefore, as displayed in Fig. 2b with large drain inductances the effects on currents caused by the discharge of parasitic capacitances and the rise of drain current are decoupled. The current peak due to the parasitic capacitances of N<sub>GaN</sub> used can be estimated as
$$I_{Ctot peak} = C_{tot} \cdot \frac{V_{DC}}{\Delta t} = (C_{PCB} + N_{GaN} \cdot C_{OSS}) \cdot \frac{V_{DC}}{\Delta t} \quad (1)$$

<figure><img src="image_3.png" /><figcaption>Fig. 2: Simulation results a) Turn-on transient at $I_D$=20 A, only GaN FET1 is turned on. Waveforms of $V_{DS}$, $I_D$, $I_{SGaN 1}$, $I_{SGaN n}$ for different $L_D + L_{diode}$: 0.1% 1% 10% 50% and 100% of the actual drain inductance ($L_D + L_{diode}$=50µH). Time =20 ns/div. b) turn on the current peak of GaN FET1 at different drain currents at low di/dt.</figcaption></figure>

With this fundamental achievement is possible to investigate the turn-on current sharing due to the effect of parasitic capacitances.

## The experimental test board developed for the parallel connection operation

The parallel GaN FETs test board for a high current switch (up to 200 A) composed of 12 parallel connected GaN FETs (EPC2302 from Efficient Power Conversion) distributed in two rows used as a workbench for the experimental evaluation is shown in Fig. 3. The board features two driver options— a common PWM gate driver for all devices and a single gate driver for each GaN FET. A shunt resistor $R_{shunt}$=0.1 Ω in the source path, out of the gate loop, is used for the current sense.

## The equivalent capacitance CPCB evaluation procedure

The C<sub>PCB</sub> is related to the layout of the developed circuit board. The portion of the board considered consists of 14 internal layers with a thickness of 2 oz. Each layer is electrically connected to one net between the GaN FETs' drains, GaN FETs' sources or the board's sources, in an alternate sequence. Overall area of the board is A=135 cm². Consequently, the equivalent capacitance between two layers connected to different nets of the board x and y can be calculated as

$$C_{xy} = D_{xy} / (\epsilon_0 \cdot \epsilon_r \cdot A) \quad (2)$$

<figure><img src="image_4.png" /><figcaption>Fig. 3: Test board for GaN FETs in parallel connection</figcaption></figure>

All the switching waveforms are carried out at ambient temperature (27 °C) at V<sub>Load</sub> equal to 24V.

where $\epsilon_0$ is the vacuum permittivity; $\epsilon_r$=3.7 is the relative permittivity of the dielectric; $D_{xy}$ is the distance between the layers x and y minus the thickness of the layer conductors [7]. For the drain (D), device source (FS) and board source (BS) layers. Between the device source and the board source there is the shunt resistance (the gate driver circuit is referred to the device source as described in Fig. 3. The distance $D_{xy}$ is different when considering the case with layer x immediately below layer y (consecutive), or the case where layer x and layer y present a third layer of a different net in the between (non-consecutive). In Fig. 4 the parasitic capacitances model adopted for the actual experimental board schematic is described.

Furthermore, in Fig.4 the parasitic capacitance of an equivalent three layers parasitic capacitances are highlighted, in which the consecutive
capacitance are C<sub>BS,FS</sub> (between BF and FS) and C<sub>FS,D</sub> (between FS and D), while C<sub>BS,D</sub> (between BF and FS) is a parasitic capacitance between two non-consecutive layers (the values of the computed capacitances C<sub>BS,FS</sub>, C<sub>FS,D</sub> and C<sub>BS,D</sub> are described).

<figure><img src="image_5.png" /><figcaption>Fig. 4: Parasitic capacitances schematic model of the experimental test board.</figcaption></figure>

Considering consecutive layers, the distance is D<sub>xy</sub>=0.13 mm and results to C<sub>xy</sub>=3.415 nF, while D<sub>xy</sub>=0.365 mm and C<sub>xy</sub>=1.216 mm are obtained for non-consecutive layers.

Capacitances connected between the same two layers (drain- device source D,FS; drain-board source D,BS; device source-board source FS,BS) are connected in parallel. The equivalent capacitances between the layers are C<sub>FS,BS</sub>= 16.1 nF; C<sub>D,FS</sub>= 13.9 nF; C<sub>FS,BS</sub>= 11.2 nF.

## Parasitic capacitances effect at turn-on switching transients

The designed test board is used considering 8 GaN FETs in parallel connection and the freewheeling super-fast diode (APT40DQ60BG) in antiparallel of load inductance. The number of device used influence the equivalent capacitance C<sub>oss</sub> as described in Fig.1. For focusing the effect of the equivalent capacitance, the test is performed driving two GaN FETs between the 8 with six devices in the turn-off state. The six devices influence the current transient through their output capacitances charge contribute. The purpose of the test is to show the effect in the GaN FET transient current of the parasitic capacitances when they are in parallel connection and driven with a time mismatch. The time mismatch between the GaN FETs represents the effects of a different gate loop inductance or the spread of dynamic parameters, such as the threshold voltage [8]. In the experimental test the delay is obtained acting on the driving signals V<sub>q</sub>.

Fig.5a shows the electrical schematic relative to GaN1 and GaN2 in parallel connection driven with V<sub>q2</sub> in a delay of Δt<sub>delay</sub> respect of V<sub>q1</sub>. The resulting waveforms of the drain-source voltage V<sub>DS</sub> and the board drain current I<sub>D</sub> are depicted in blue and in green respectively in all experimental results. Additionally, Fig. 5 shows the measured currents of GaN1 I<sub>S1</sub> (yellow), GaN2 I<sub>S2</sub> (red), and the one of a generic not driven GaN8 I<sub>S8</sub> (magenta). The transient current is evenly distributed between the two devices. If a turn-on delay on GaN2 compared to GaN1 is introduced, the device that turns on first has a peak much higher than the second, relating to the length of the delay. Results obtained without delay are reported in Fig.5b, while the waveforms achieved with Δt<sub>delay</sub>=5 ns and Δt<sub>delay</sub>=9 ns are depicted in Fig.5c and Fig.5d, respectively.

<figure><img src="image_6.png" /><figcaption>Fig. 5: Turn-on transient driving GaN2 with a delay in respect of GaN1. a) electrical schematic of the two GaN FETs in the board driven with time-delayed V<sub>q</sub>. b) delay=0 ns. c) delay=5 ns. d) delay=9 ns. I<sub>S</sub>=50 A/div. I<sub>D</sub>=2 A/div. V<sub>DS</sub>=10 V/div. Time t = 10 ns/div.</figcaption></figure>

Comparing Fig.5b, Fig.5c and Fig.5d, the I<sub>D</sub> waveform is unchanged. Looking at Fig.5a, during the V<sub>DS</sub> fall, I<sub>S1</sub> and I<sub>S2</sub> have a current peak due to the parasitic capacitances contribution. These peaks are congruent because of the simultaneous turn-on. The total charge of the parasitic capacitances is split equally between GaN1 and GaN2. Introducing a Δt<sub>delay</sub>=5 ns in Fig.5c, I<sub>S1</sub> peak is higher than I<sub>S2</sub> because GaN1 is the only GaN FET that conducts all the capacitive current until GaN2 is turned on. Immediately after the GaN2 turn-on, the capacitive current is conducted by the two devices with different I<sub>S</sub>. In the case of Δt<sub>delay</sub>=9 ns in Fig.5d, the Δt<sub>delay</sub> is long as the V<sub>DS</sub> variation and
GaN2 turn on in zero voltage switching (ZVS) without contributing to the capacitive current conduction [9]. In this case, $I_{S1}$ peak is maximum and $I_{S2}$ acts as $I_{S8}$ (as all the devices in off state). Furthermore, Fig.5 shows that $V_{DS}$ fall and the transitory turn-on duration appear longer in Fig.5c and Fig.5d than Fig.5b, as the $\Delta t_{delay}$ is longer.

Overall, the delay between $V_{q1}$ and $V_{q2}$ lead to higher peak currents in $I_{S1}$, directly correlated with the variations in $V_{DS}$. The $I_{D}$ current does not impact $I_{S}$ because of the slow rise due to the high $L_{D}$ of the PCB. This experimental setup highlights the importance of managing turn-on delays to control peak currents and reduce associated losses in GaN FET applications.

## Parasitic capacitances effect at turn-off switching transients

The experimental tests are extended at turn-off with the same methodology approach.

Fig. 6a illustrates the electrical schematic of GaN1 and GaN2 connected in parallel, with $V_{q2}$ delayed by $\Delta t_{delay}$ relative to $V_{q1}$. The corresponding waveforms for the drain-source voltage $V_{DS}$ and the board drain current $I_{D}$ are shown in blue and green, respectively. Furthermore, Fig. 6 presents the measured currents of GaN1 $I_{S1}$ (yellow), GaN2 $I_{S2}$ (red), and a generic non-driven GaN FET current $I_{Sn}$ (magenta).

<figure><img src="image_7.png" /><figcaption>Fig. 6: Turn-off transient driving GaN2 with a delay in respect of GaN1. a) electrical schematic of the two GaN FETs in the board driven with time-delayed $V_{q}$. b) delay=0 ns. c) delay=5 ns. d) delay=9 ns. $I_{S}=2$ A/div. $I_{D}=2$ A/div. $V_{DS}=10$ V/div. Time =10 ns/div</figcaption></figure>

The results without delay are depicted in Fig. 6b, whereas waveforms with $\Delta t_{delay}=5$ ns and $\Delta t_{delay}=9$ ns are shown in Fig. 6c and Fig. 6d, respectively. A comparative analysis of Fig. 6b, Fig. 6c, and Fig. 6d reveals that the $I_{D}$ and $V_{DS}$ waveform remains unchanged across different delay cases. $I_{D}$ falls slowly following the $V_{DS}$ rising because of the high value of $L_{D}$. In the case without delay in Fig.6b, the turn-off of GaN1 and GaN2 occurs simultaneously due to the immediate turn-off of both FETs. This results in an equal distribution of the load current between GaN1 and GaN2 and the absence of a current peak. Introducing a $\Delta t_{delay}=5$ ns, as illustrated in Fig. 6c, results in a higher $I_{S1}$ peak compared to $I_{S2}$, since GaN1 continues to conduct the entire load current alone immediately after the GaN2 turn-off. In the scenario of $\Delta t_{delay}=5$ ns depicted in Fig. 6d, the delay is long enough to leave GaN1 to conduct all the load current alone until it turns off. Consequently, at turn-off, the maximum $I_{S}$ peak value corresponds to the load current, without contributions of parasitic capacitances [10]. As a result, also the delay in the turn-off has to be maintained short in order to control the maximum peak current. Nevertheless, the turn-off transient is less problematic than the turn-on.

## Energy losses evaluation during switching transients

The characterization and understanding of the dynamic behavior of GaN FETs connected in parallel is crucial in high-power and high-frequency applications. Imbalanced current sharing results in increased losses and potential thermal runaway if not properly managed. By analyzing the turn-on and turn-off delays, and their corresponding energy losses [11], is essential to provide insights that can help in designing more efficient parallel GaN FET systems, ensuring better performance and longevity of the devices.

The GaN FET energy losses resulting from the experimental tests with different turn-on and turn-off delays are calculated as

$$E_{GaN} = \int_{0}^{\Delta t} I_{S} \cdot V_{DS} dt \quad (3)$$

where $\Delta t$ is the time interval defined for the turn-on or the turn-off:

* turn-on: $\Delta t$ the time duration of the $I_{S1}$ peak;
• turn-off: Δt goes from when I<sub>s2</sub> starts falling and finishes when the peak of I<sub>s1</sub> is elapsed.

The calculated energy indicates the contribution of the parasitic capacitances and the turn-on and turn-off delay between GaN FETs connected in parallel [12].

<figure><img src="image_8.png" /><figcaption>Fig. 7: Energy losses of GaN1(E<sub>GaN1</sub>), GaN2(E<sub>GaN2</sub>) and the sum of both (E<sub>tot</sub>) obtained as a function of the driving delay. a) turn-on. b) turn-off.</figcaption></figure>

The design of the PCB considered allows the contribution of losses due to load current to be excluded (the effects on currents caused by the discharge of parasitic capacitances and the rise of drain current are decoupled as discussed in the testing methodology section). Fig.7a depicts the GaN FET energies obtained with various driving delays between V<sub>q1</sub> and V<sub>q2</sub> at turn-on, while Fig.8b shows the results relative to the turn-off. The energy losses for GaN1 (E<sub>GaN1</sub>) and those of GaN2 (E<sub>GaN2</sub>) are represented in yellow and red, respectively, additionally, the sum of the two losses E<sub>tot</sub> is depicted in black.

$$E_{tot} = E_{GaN1} + E_{GaN2} \quad (4)$$

Comparing Fig.7a and Fig.8b is notable that turn-on energy losses are significantly higher than turn-off losses. observation can be attributed to the major contribution of the capacitive current at turn-on. Focusing at turn-on in Fig.7a it is evident that when GaN FETs turn on simultaneously (delay is null), losses are equal for both devices. Introducing a delay in GaN2 results in higher losses in GaN1, while E<sub>GaN2</sub> is reduced. In particular, a delay of 5 ns is the condition in which GaN2 exhibits E<sub>GaN2</sub>=0 J. For delays longer than

5 ns, the negative E<sub>GaN2</sub> indicates that the C<sub>oss</sub> charge of GaN2 is mostly conducted by GaN1. E<sub>GaN2</sub> stabilizes to a minimum value for a Delay higher than 9 ns because all the C<sub>oss</sub> charge of GaN2 is conducted by GaN1. As a consequence, E<sub>GaN1</sub> stabilizes to a maximum value for a delay higher than 9 ns. In this condition, GaN1 conducts the total parasitic current of the PCB and the parallel-connected devices. The total energy E<sub>tot</sub> remains almost constant regardless of the delay since the total energy of the system is determined by the total charge and the applied voltage. The enlarged view of Fig.7b reveals that the turn-off losses of GaN1 (E<sub>GaN1</sub>) and GaN2 (E<sub>GaN2</sub>) are identical at 0 ns of delay due to the simultaneous turn-off of devices. A non-zero delay causes an increase in E<sub>GaN1</sub>, while E<sub>GaN2</sub> remains unchanged [13]. The total energy E<sub>tot</sub> is at a minimum when the delay is null and increases the longer the delay time.

## Conclusion

This paper has comprehensively investigated the parallel connection of Gallium-Nitride (GaN) FET devices for high-current switch applications. The key parameters influencing both the static and dynamic current sharing among paralleled GaN FETs were analyzed, with a particular focus on the parasitic capacitances and the parametric spread causing non-simultaneous switching. Precise layout management and gate driver design allow to minimization of current imbalances and peak currents during switching transients.

Through detailed simulations and experimental validations, it was demonstrated that parasitic capacitances and inductances significantly impact the current peaks during switching events. Furthermore, the energy losses related to the effect of the parasitic capacitance are evaluated. Tests on a prototype board with 8 low-voltage GaN FETs connected in parallel have highlighted the importance of managing turn-on delays to control peak currents and reduce associated losses. Findings suggest that simultaneous turn-on of devices minimizes losses, while delays lead to unequal current sharing and increased peak currents in individual devices.

To minimize parasitic capacitances in PCB design, it is crucial to avoid having areas at different voltage potentials extend across the entire surface of one or more layers. Similarly, layers at different voltage potentials should not be aligned directly one above the other. A
recommended strategy is to partition each layer
into multiple regions (e.g., drain, source, and
common source), ensuring that regions with the
same voltage potential in different layers are
aligned vertically. This approach reduces the
equivalent capacitance of the PCB, thereby
decreasing the charge contributing to turn-on
current spikes during device switching. However,
the reduced equivalent capacitance leads to a
faster voltage variation (dV/dt), which can
increase the GaN FET peak current during turn-
on events.

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