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# HDR Magali Grégoire Silicide in microelectronics: phase sequence, nanoscale effect, and degradation

Magali Gregoire

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Magali Gregoire. HDR Magali Grégoire Silicide in microelectronics: phase sequence, nanoscale effect, and degradation. Physics [physics]. Aix-Marseille Universite, 2022. tel-04193978

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# Habilitation à Diriger des Recherches

Spécialité : Physique et Sciences de la matière
Soutenue à Aix-Marseille Université
le 28 avril 2022 par

## Magali GREGOIRE

Silicides in microelectronics: phase sequence, nanoscale effect, and degradation mechanisms.

### Composition du jury :

Elisabeth BLANQUET, Directeur de recherche CNRS - SIMAP - Grenoble, rapporteur

Christophe DETAVERNIER, Professeur des universités - Université de Gand - Belgique, rapporteur

Fuccio CRISTIANO, Directeur de recherche, CNRS - LAAS - Toulouse, rapporteur
Christophe GIRARDEAUX, Professeur des universités, Aix-Marseille Université - Marseille, examinateur

Dominique MANGELINCK, Directeur de recherche CNRS - IM2NP - Marseille, examinateur

Didier DUTARTRE, Expert technique senior - STMicroelectronics - Crolles, invité
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# CHAPTER I

## Forewords and Curriculum Vitae

### Abstract

In the next pages, I will present the research work done since the beginning of my career including a detailed Curriculum Vitae, publications list, Ph. D. theses and internships supervisions, and collective responsibilities (peer-review, conference organization and Ph. D. thesis defense participation). The objective of this chapter is to give a clear and precise picture of research fields evolutions, Ph. D. theses, and key projects timelines. Thus, the progress of my centers of interest, and subsequent research topics, is presented coming from Cu interconnects properties identification to silicide and advanced contacts integrations on Si and III/V substrates.
Table of Contents

<table><tr><td>I.1 Forewords</td><td>3</td></tr><tr><td>I.2 Curriculum vitae</td><td>5</td></tr><tr><td>I.2.1 Profile</td><td>5</td></tr><tr><td>I.2.2 Professional experiences</td><td>5</td></tr><tr><td>I.2.3 Education</td><td>7</td></tr><tr><td>I.3 Publications list</td><td>7</td></tr><tr><td>I.3.1 Papers in peer-reviewed international journal</td><td>7</td></tr><tr><td>I.3.2 Communications at conferences with proceedings and reading committee</td><td>9</td></tr><tr><td>I.3.3 Communications at conferences with reading committee</td><td>11</td></tr><tr><td>I.3.4 US patents</td><td>12</td></tr><tr><td>I.4 Ph. D Thesis and master internship supervision</td><td>12</td></tr><tr><td>I.4.1 Ph. D Thesis supervision</td><td>12</td></tr><tr><td>I.4.2 Master internship supervision</td><td>13</td></tr><tr><td>I.5 Collective responsibilities and conference organization</td><td>14</td></tr><tr><td>I.5.1 Peer-review for international journal and conferences with reading committee</td><td>14</td></tr><tr><td>I.5.2 European and national research projects contribution</td><td>14</td></tr><tr><td>I.5.3 Participation of Ph. D defense jury</td><td>14</td></tr><tr><td>I.5.4 Conference organization</td><td>15</td></tr></table>
## I.1 Forewords

My first real professional experience in research was my master 2 internship in the Néel Institut (CNRS, Grenoble) on the growth of the first Cu layers on Ni(111) substrate characterized by STM (Scanning Tunneling Microscopy). During these 5 months under the supervision of Pierre Mallet and Jean-Yves Veuillen at Louis Néel Institute, I learned what research in material sciences means and requires. At that time, I found my path for my future professional activity. In general, I am quite sure that being a researcher cannot be learned in books or at school but by being involved inside a real research team on an innovative and challenging project.

After this first experience, I had the opportunity to continue a part of this work on thin Cu layers properties - not exactly in the fundamental field but nevertheless in the material science one - during my Ph. D thesis [1] which was a CIFRE thesis took place at STMicroelectronics Crolles in collaboration with the SIMAP (for "Science et Ingénierie des Matériaux et Procédés" in French).

Throughout my Ph. D thesis, several papers in conference proceedings (detailed in section I.3) and one US patent were published. Working in the research center of STMicroelectronics on 300 mm technology inside an international alliance with NXP and Motorola was exciting; and I decided to pursue my carrier at STMicroelectronics.

After two years in the CMP (Chemical and Mechanical Polishing) group, I was promoted to the position of silicide process owner as responsible of Ni(Pt) and Co depositions for advanced technologies in R&D Metal group. In 2007, even though the industry conversion to Ni silicide had been initiated a few years ago, the clear understanding of what was involved during Ni-silicide formation was not fully achieved. At that time, formation of stable and less resistive Ni silicide layers in a complete integrated microelectronics device was a challenge; and I was every day surprised by what we observed and measured. The main problem we faced with, was the Ni silicide encroachment and we initiated a collaboration research project (ANR) with IM2NP (Marseille), GMP (Rouen) and CEA-LETI (Grenoble), called "TAPAS" (for "Tomography Atom Probe for Advanced Silicide"), which contributed to the arrival of the Atom probe equipment at IM2NP in 2009. Thanks to this new characterization tool, we started an exhaustive and fruitful work on Ni(Pt) silicides phase formation and their further degradation mechanisms, as detailed in Chapter III and in section I.3 (i.e., publication list).

2007 was also the year of my first involvement in a Ph.D thesis supervising. During Bruno Imbert's Ph.D thesis [2] dedicated to the Ni encroachment phenomenon, I was implicated in the sample realization, associated characterizations and final analyses. At the end, I helped Bruno on the final manuscript redaction with a detailed review and this work concluded in the publishing of several papers (namely [3], [4], see for details the section I.3 as well).

In 2009, in collaboration with the IM2NP laboratory, we launched a Ph. D thesis project aiming at characterizing Ni-based silicide layer inside a real device. The results of Federico Panciera's thesis [5] will be mainly presented in Chapter III, and this work was a clear breakthrough in θ-Ni₂Si phase formation, and silicide formation in small dimensions.

At the beginning of 2010, we started an intense R&D activity on a new technology, called 14 nm UTBB-FDSOI (14 nm is the gate width and UTBB-FDSOI a specific Fully Depleted Silicon on Isolator substrate). For this new node, as for the previous one, Ni(Pt) alloys including 10 and 15 at.% of Pt atomic
concentration were introduced and studied in detail. For this specific technology, the integration of Si<sub>0.7</sub>Ge<sub>0.3</sub> raised source drains required a complete analysis of degradation mechanisms, namely Ni(Pt)SiGe agglomeration. This work was performed during Emilie Bourjot's Ph. D thesis [6], as explained in Chapter III.

Between 2010 and 2014, I also supervised two other theses, respectively in collaboration between GPM (Rouen) and IEMN (Lille). I also extended my activity to advanced contact integration as the work dedicated to 10-nm node contacts through Julien Borrel's thesis [7] (details in Chapter IV).

Activity on advanced contacts as TiSi contacts and contacts on III/V became a significant part of my research work for the last past years. In 2017, Laura Esposito's thesis was carried out on the influence of a new type of annealing (UV- NLA for Ultra-Violet Nanoseconds Laser Annealing) applied on TiSi contacts, enabling the study of amorphous and C40-TiSi₂ phases (presented in Chapter IV). Less resistive and stable contacts on III/V substrates were deeply analyzed during Flore Boyer's thesis (also presented in Chapter IV). The work of Laura Esposito is followed-up by a new Ph. D thesis launched in 2021.

Over the years, my activities have extended to all technologies for several sites of STMicroelectronics in Europe (mainly Roussel in France, Agrate and Catania in Italy). Technology transfer is quite interesting because the same problems or questions could be solved with distinct points of view on different sites, which is always attractive to know and analyze.

Based on this work, and since Ni silicide integrations are not possible in our 200 mm-technology fabs, I started new studies on Co silicide formation in 2017. From an industrial perspective, Co silicide formation is well known, and many papers published in the last decades potentially indicate that no innovative work can be performed on this topic. Nevertheless, I would like to provide new Co silicide technological bricks to demonstrate the scalability of this silicide for 65 nm node technology. This is quite challenging because the industry has hugely moved to Ni silicide for this node in the early 2000s. A new thesis in collaboration with the IM2NP laboratory was initiated in 2020.

Since 2007, I have supervised seven theses and that is clearly a major source of satisfaction for me in terms of research advancements, new work publications and deep understanding of our technology functionalities. The technical coaching activity of Ph. D students, including knowledge, methodology, and technical know-how sharing is a main part of my activity that I would like to pursue for the coming years.

As a conclusion, my personal and professional aspirations are to continue in this direction and that is the reason why I am candidate to the HDR ability.
## I.2 Curriculum vitae

### I.2.1 Profile

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Research gate profile

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Google scholar profile

Magali Grégoire, Ph. D

42 years, 3 children, French nationality

Tel: +33(0)4 38 92 28 16, @ magali.gregoire@st.com

STMicroelectronics Crolles

850, Rue Jean Monnet

38920 Crolles Cedex

### I.2.2 Professional experiences

<table><tr><td>2002-2005<br>3 years</td><td>PhD student (SIMAP Grenoble /ST) at STMicroelectronics (Crolles): "Properties of thin copper films and copper interconnections", CIFRE thesis.<br>- Deep study of the thin copper layers microstructure deposited by PVD and ECD: resistivity, stress, EBSD, SEM, SIMS, and ToF-SIMS, ellipsometry.<br>- Characterization and modeling of stress-voiding phenomenon in interconnects.<br>- 11 communications, 1 US patent, 3 presentations at international conferences.</td></tr><tr><td>2005-2007<br>2 years</td><td>CMP R&D engineer at STMicroelectronics (Crolles)<br>- Development of CMP processes on oxide and silicon nitride thin layers.<br>- Evaluation of new polishing chemistries regarding pattern density.</td></tr><tr><td>2007-2010<br>3 years</td><td>Metal R&D engineer at STMicroelectronics (Crolles)<br>- Introduction and development of surface preparation processes before metal deposition (dry and plasma-remote pre-cleans), and Co, Ti, TiN, and Ni(Pt) thin layers deposited by several vacuum deposition techniques such as PVD, CVD, ALD and RFPVD.<br>- Co-supervision of Bruno's Imbert thesis on Ni encroachment phenomena (samples definition, manuscript review).<br>- Ph. D student supervision: Federico Panciera's thesis dedicated on the first studies by atom probe of real CMOS devices.<br>- ST leader for ANR TAPAS (Tomography Atom Probe for Advanced Silicides) project started in 2008.</td></tr></table>
<table><tr><td>2010-2015<br>5 years</td><td>Senior Metal R&D engineer at STMicroelectronics (Crolles)<br>- Germano-silicides studies (SiGe substrates) in the frame of advanced UTBB-FDSOI technology development.<br>- Anticipation work on 10-nm node contacts as metal-isolator-semiconductor (MIS) contacts (Julien Borrel's thesis).<br>- Ph. D and internship student supervision: 3 theses and 1 internship.<br>- Interface for the joint development program in core CMOS technologies between IBM/ST/CEA-LETI (IBM Alliance): technologies transfer and advanced characterization working group member.<br>- Interface for collaborative projects on silicidation and atom probe characterizations with partner laboratories (LETI, IM2NP, IEMN, GPM).</td></tr><tr><td>2015-2018<br>3 years</td><td>Technology Development Staff Engineer at STMicroelectronics (Crolles)<br>- Development of plasma-remote etching process on thin dielectric layers for high aspect ratio technologies (Embedded Non-Volatile Memories, e-NVM).<br>- New integrations for TiSi silicided contacts for advanced imager technologies.<br>- Ph. D and internship student supervision: 1 Ph. D thesis and 1 internship.<br>- Involvement in Nano2017 project: implementation of innovative methods to measure contact resistance based on Time-Line Method (MOSDIIA project). Samples design and processing.<br>- ST leader of CEA-LETI/ST joint development program for contacts development.</td></tr><tr><td>Since 2018</td><td>Member of STMicroelectronics Technical Staff as Silicide, Thin Films, and SiCoNi technical expert<br>Process Technology Development Senior Staff Engineer at STMicroelectronics (Crolles)<br>- In charge of technology transfer between different ST fabs as Rousset (France), Agrate and Catania (Italy) for e-NVM and high-power BICMOS technologies.<br>- Silicide and contacts roadmap definition for a large scale of microelectronics devices as high-power BICMOS, advanced BICMOS, e-NVM, core CMOS, FDSOI-CMOS, imagers technologies (3D and backside).<br>- Ph. D and internship student supervision: 4 theses (2 in course) and 2 internships.<br>- Member of MOSDIIA2 project (follow-up of MOSDIIA). Samples design and processing.<br>- ST leader of CEA-LETI/ST joint development program for contacts development.</td></tr><tr><td>2002 to present</td><td>Papers in peer-reviewed international journal: 19<br>Communications at conferences with proceedings and reading committee: 30<br>Communications at conferences with reading committee: 7<br>US patents: 6</td></tr></table>
I.2.3 Education

<table><tr><td>2006</td><td>Ph. D grade of National Polytechnic Institute of Grenoble, CIFRE thesis (collaboration SIMAP Grenoble /ST) under the supervision of Michel Ignat (CNRS).<br/>- Specialty: "Science and Material Engineering".</td></tr><tr><td>2002</td><td>Mater degree in research of University Grenoble Alpes: "from nano-sciences to large instruments"<br/>- Solid-state physics, condensed matter, optics.<br/>- Interactions particle-matter: X-ray and electronic diffraction, X-ray fluorescence.<br/>- Semi-conductor physics.</td></tr></table>

I.3 Publications list

I.3.1 Papers in peer-reviewed international journal

1. B. Imbert, R. Pantel, S. Zoll, M. Gregoire, R. Beneyton, S. DelMedico and O. Thomas, "Nickel silicide encroachment formation and characterization", Microelectron. Eng. 87 (3), pp. 245-248, 2010.

2. F. Panciera, K. Hoummada, M. Grégoire, M. Juhel, N. Bicais and D. Mangelinck, "Three dimensional distributions of arsenic and platinum within NiSi contact and gate of an n-type transistor", App. Phys. Lett. 99 (5), 051911, 2011.

3. F. Panciera, S. Baudot, K. Hoummada, M. Gregoire, M. Juhel, and D. Mangelinck, "Three-dimensional distribution of Al in high-k metal gate: Impact on transistor voltage threshold", App. Phys. Lett. 100 (20), 201909, 2012.

4. F. Panciera, K. Hoummada, M. Gregoire, M. Juhel, and D. Mangelinck, "Pt redistribution in N-MOS transistors during Ni silicide process", Microelectron. Eng. 107, pp. 173-177, 2013.

5. F. Panciera, K.Hoummada, M.Grégoire, M. Juhel, F. Lorut, N. Bicais, and D. Mangelinck, "Atom probe tomography of SRAM transistors: Specimen preparation methods and analysis", Microelectron. Eng. 107, pp. 167-172, 2013.

6. F. Panciera, D. Mangelinck, K. Hoummada, M. Texier, M. Bertoglio, A. De Luca, M. Gregoire, and D. Mangelinck, "Direct epitaxial growth of θ-Ni₂Si by reaction of a thin Ni (10 at.% Pt) film with Si (100) substrate", Scr. Mater. 78-79, pp. 9-12, 2014.

7. P. F. Morin, R. Beneyton, M. Grégoire, A. Pofelski, L. Clement, S. Muthukrishnan, and A. J Mayur "Macroscopic and nanometer scale stress measurement of Ni(Pt)Si silicide: Impact of thermal treatments ranging from millisecond to several hours", J. Vac. Sci. Technol. B 32 (1), 011211, 2014.

8. J. Borrel, L. Hutin, O. Rozeau, M.-A. Jaud, S. Martinie, M. Gregoire, E. Dubois, and M. Vinet, "Modeling of Fermi-level pinning alleviation with MIS contacts: N and pMOSFETs cointegration considerations—Part I", IEEE Transactions on Electron Devices 63 (9), pp. 3413-3418, 2016.
9. J. Borrel, L. Hutin, O. Rozeau, M.-A. Jaud, S. Martinie, M. Gregoire, E. Dubois, and M. Vinet, "Modeling of Fermi-level pinning alleviation with MIS contacts: N and pMOSFETs cointegration considerations—Part II", IEEE Transactions on Electron Devices 63 (9), pp. 3419-3423, 2016.

10. R. Estivill, M. Juhel, M. Grégoire, A. Grenier, V. Delaye, and D. Blavette "Atomic scale investigation of arsenic segregation in high-k metal gate stacks", Scr. Mater. 113, pp. 231-235, 2016.

11. E. Bourjot, M. Grégoire, F. Nemouchi, and D Mangelinck, "Thermal stability of Ni₁-ₐPtₐ (0<u<0.15) germanosilicide", J. of App. Phys., 121 (13), 135302, 2017.

12. J. Borrel, L. Hutin, D. Kava, R. Gassilloud, N. Bernier, Y. Morand, F. Nemouchi, M. Grégoire, E. Dubois, and M. Vinet, "Ultra-thin dielectric insertions for contact resistivity lowering in advanced CMOS: Promises and challenges", Jpn. J. of App. Phys. 56 (4S), 04CB02, 2017.

13. R. Estivill, M. Juhel, G. Servanton, M. Gregoire, F. Lorut, L. Clement, P. Chevalier, A. Grenier, and D. Blavette, "Boron atomic-scale mapping in advanced microelectronics by atom probe tomography", Applied Physics Letters 110, 252105, 2017.

14. M. Lemang, Ph. Rodriguez, F. Nemouchi, M. Juhel, M. Grégoire, and D. Mangelinck, "Redistribution of phosphorus during Ni0.9Pt0.1-based silicide formation on phosphorus implanted Si substrates", J. of Appl. Phys. 123, 085106, 2018.

15. M. Grégoire, B. Horvat, B.-N. Bozon, D. Combe, K. Dabertrand, and D. Roy "Additional Siconi™ pre-clean for reliable TiSiₓ contacts in advanced imager technologies", Micro and Nano Engineering 2, pp. 104-109, 2019.

16. F. Boyer, P. Gergaud, K. Dabertrand, D. Mariolle, C. Jany, F. Nemouchi, M. Grégoire, Q. Rafhay, and Ph. Rodriguez, "Integration of the Ni/InP system on a 300 mm platform for III-V/Si hybrid lasers", J. of Vacuum Sc. and Tech. B, 38 (1), 012209, 2020.

17. F. Boyer, K. Dabertrand, C. Jany, P. Gergaud, N. Coudurier, F. Nemouchi, M. Grégoire, Q. Rafhay, and Ph. Rodriguez, "Integration, BEOL, and Thermal Stress Impact on CMOS-Compatible Titanium-Based Contacts for III-V Devices on a 300-mm Platform", IEEE Transactions on Electron Devices, 67(6), pp. 2495-2502, 2020.

18. L. Esposito, S. Kerdilès, M. Gregoire, P. Benigni, K. Dabertrand, J.-G. Mattei, and D. Mangelinck, "Impact of nanosecond laser energy density on the C40-TiSi2 formation and C54-TiSi2 transformation temperature", J. of Appl. Phys., 128, 085305 (2020).

19. F. Boyer, K. Dabertrand, P. Gergaud, M. Grégoire, Q. Rafhay, and Ph. Rodriguez, "Platinum redistribution in the Ni0.9Pt0.1/InP system: Impact on solid-state reaction and layer morphology", Materials Science in Semiconductor Processing, 128, 105731, 2021.
I.3.2 Communications at conferences with proceedings and reading committee

1. S. Petitdidier, M. Gregoire, S. Segaud, S. Courtas, M. Juhel, J-P. Jacquemin, and L. Dumas, "Interactions between the conditions of Copper electrodeposition and the density of hillocks," Proceedings of the International Symposium of Electrochemical Society, PV 2003-10, pp. 47-52, 2003.

2. V. Girault, F. Terrier, and M. Gregoire, "Electromigration in narrow and large damascene copper lines", IEEE International Integrated Reliability Workshop Final Report, pp. 71-74, 2004.

3. A. Baldacci, C. Rivero, P. Gergaud, M. Grégoire, O. Sicardy, O. Bostrom, P. Boivin, J.S. Micha, and O. Thomas, "Stresses in copper blanket films and damascene lines: Measurements and finite element analysis", Proceedings of the 30th European Solid-State Circuits Conference, 2004 IEEE International, pp. 105-108, 2004.

4. S. Chhun, L.G. Gosset, N. Casanova, D. Ney, D. Delille, C. Trouiller, M. Hopstaken, P. Chausse, M. Grégoire, B. Gautier, J.-C. Dupuy, J. Torres, "Impact of introducing CuSiN self-aligned barriers in advanced copper interconnects", Microelectron. Eng. 82 (3-4), pp. 587-593, 2005.

5. M. Gregoire, S. Kordic, M. Ignat, X. Federspiel, P. Vannier, and S. Courtas, "New stress voiding observations in Cu interconnects", Proceedings of the IEEE 2005 International Interconnect Technology Conference, pp. 36-38, 2005.

6. M. Gregoire, S. Kordic, P. Gergaud, O. Thomas, and M. Ignat, "Thermomechanical behavior and properties of Passivated PVD and ECD Cu thin films", MRS Proceedings, Symposium on Thin Films, Stresses and Mechanical Properties XI, 875, 04.5, 2005.

7. R. Delsol, J-P. Jacquemin, M. Gregoire, V. Girault, X. Federspiel, R-X. Bouyssou, P. Vannier, and P. Normandon, "Improved electrical and reliability performance of 65nm interconnects with new barrier integration schemes", Microelectron. Eng. 83 (11-12), pp. 2377-2380, 2006.

8. S. Courtas, M. Gregoire, X. Federspiel, N. Bicaïs-Lepinay, and C. Wyon, "Electron BackScattered Diffraction (EBSD) use and applications in newest technologies development", Microelectronics Reliability 46 (9), pp. 1530-1535, 2006.

9. X. Federspiel, and M. Gregoire, "Multimodal analysis of stress induced degradation of 90 nm in newest technologies", Proceedings of the 44th IEEE International Reliability Physics Symposium, pp. 681-682, 2006.

10. M. Ignat, F. Robaud, M. Swain, and M. Gregoire, "Microstructure and mechanical properties of ECD and PVD Cu thin films, Vth Institute of Materials International Conference (East Asia) proceedings, pp. 122-125, 2006.

11. X. Federspiel, S. Courtas, and M. Gregoire, "Characterization of degradation of 65nm node via chains and single vias", Proceedings of the 45th IEEE International Reliability Physics Symposium, pp. 640-641, 2007.

12. M. Gregoire, H. Brillet, and P. Vannier, "Stress-void nucleation induced by local delamination at Cu/Ta interfaces", Conferences Proceedings AMC, pp. 679-685, 2007.
13. B. Imbert, M. Gregoire, S. Zoll, R. Beneyton, S. Del-Medico, C. Trouiller, and O. Thomas, "Nitrogen impurity effects on nickel silicide formation at low temperatures–New "nitrogen co-plasma" approach", Microelectron. Eng. 85 (10), pp. 2005-2008, 2008.

14. M. Grégoire, M. Juhel, P. Vannier, and P. Normandon, "Post electrochemical Cu deposition anneal impact on stress-voiding in individual vias", Microelectron. Eng., 85 (10), pp. 2146-2149, 2008.

15. B. Imbert, R. Pantel, S. Zoll, M. Gregoire, R. Beneyton, S. DelMedico, and O. Thomas, "Nickel silicide encroachment formation and characterization", Microelectron. Eng. 87 (3), pp. 245-248, 2010.

16. M. Grégoire, R. Beneyton, S. Del-Medico, S. Zoll and P. Normandon, "Gate shadowing effect on Ni(Pt)Si abnormal diffusion for sub-45nm technologies", Microelectron. Eng. 88 (5), pp. 548-552, 2011.

17. S. Baudot, P. Caubet, M. Grégoire, R-A. Bianchi, R. Pantel, S. Zoll, M. Gros-Jean, R. Boujamaa, P. Normandon, C. Leroux, and G. Ghibaudo, "Comparison of radio frequency physical vapor deposition target material used for LaOₓ cap layer deposition in 32 nm NMOSFETs", Microelectron. Eng. 88 (5), pp. 569-572, 2011.

18. M. Gregoire, R. Beneyton and P. Morin, "Millisecond annealing for silicide formation: Challenges of NiSi agglomeration free process," IEEE International Interconnect Technology Conference, pp. 1-3, 2011.

19. C. Fenouillet-Beranger et al., "Impact of local back biasing on performance in hybrid FDSOI/bulk high-k/metal gate low power (LP) technology", Solid-State Electronics 88, pp. 165-168, 2012.

20. O. Weber et al., "14nm FDSOI technology for high speed and energy efficient applications", Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers, pp.1-2, 2014.

21. C. Fenouillet-Beranger et al., "FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration", Solid-State Electronics 113, pp. 2-8, 2015.

22. R. Estivill, A. Grenier, T. Printemps, M. Juhel, M. Gregoire, P. Caubet, and D. Blavette, "3D Atomic Scale Analysis of CMOS type structures for 14 nm UTBB-SOI technology", Proceedings of Microscopy and Microanalysis 21 (S3), pp. 521-522, 2015.

23. F. Deprat, F. Nemouchi, C. Fenouillet-Beranger, P. Rodriguez, S. Joblot, M. Gregoire, D. Barge, P. Gergaud, N. Rambal, P. Batude, and M. Vinet, "Technological enhancers effect on Ni₀.₉Co₀.₁ silicide stability for 3D sequential integration", Phys. Stat. Solidi. (c) 13 (10-12), pp. 760-765, 2016.

24. J. Borrel, L. Hutin, H. Grampeix, E. Nolot, E. Ghegin, P. Rodriguez, C. Tabone, F. Allain, J-P. Barnes, Y. Morand, F. Nemouchi, M. Gregoire, E. Dubois, M. Vinet, "Considerations on fermi-depinning, dipoles and oxide tunneling for oxygen-based dielectric insertions in advanced CMOS contacts", IEEE Silicon Nanoelectronics Workshop (SNW), pp. 140-141, 2016.

25. F. Deprat, F. Nemouchi, C. Fenouillet-Beranger, M. Cassé, P. Rodriguez, B. Previtali, N. Rambal, V. Delaye, M. Haond, M. Mellier, M. Gregoire, M. Danielou, S. Favier, P. Batude, and M. Vinet, "First integration of Ni₀.₉Co₀.₁ on pMOS transistors", IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC), pp. 133-135, 2016.
26. J. Borrel, L. Hutin, H. Grampeix, E. Nolot, M. Tessaire, G. Rodriguez Y. Morand, F. Nemouchi, M. Grégoire, E. Dubois, M. Vinet, "Metal/Insulator/Semiconductor contacts for ultimately scaled CMOS nodes: Projected benefits and remaining challenges", 16th International Workshop on Junction Technology (IWJT), pp. 14-18, 2016.

27. I. Mouton, R. Estivill-Stroud, A. Grenier, M. Gregoire, M. Juhel, and J.-P. Barnes, "Improvement of 3D atom probe tomography reconstruction integrating transmission electron microscopy information – Instrumentation and Methods, Correlative microscopy", European Microscopy Congress 2016: proceedings, 2016.

28. L. Lachal, Ph. Rodriguez, M. Grégoire, E. Ghegin, F. Milesi, M. Coig, J. Borrel, S. Joblot, M. Juhel, F. Nemouchi, and F. Mazen, "Effects of pre-amorphization thickness and carbon implantation on NiPt/Si silicidation process", 22nd International Conference on Ion Implantation Technology (IIT), pp. 54-57, 2018.

29. J. Borrel, M. Gregoire, E. Ghegin, S. Joblot, R. Vallat, A. Valery, M. Juhel, and R.-A. Bianchi, "Pre-Amorphization Implants and in-situ Surface Preparation Optimization for Low Co-Silicided Area Density", 19th International Workshop on Junction Technology (IWJT), pp. 1-4, 2019.

30. F. Boyer, C. Jany, J. Da Fonseca, B. Szelag, V. Amalberg, M. Grégoire, Q. Rafhay, and Ph. Rodriguez, "Reliability of CMOS-compatible Ti/n-InP and Ti/p-InGaAs ohmic contacts for hybrid III-V/Si lasers", 16th International Conference on Group IV Photonics (GFP), 1949, pp. 1-2, 2019.

### I.3.3 Communications at conferences with reading committee

1. M. Ignat, M. Swain, and M. Gregoire, "Mechanical Properties and reliability of Copper thin films", Quality and Reliability CCF 2006, 2006.

2. C. Fenouillet-Beranger et al., "Effect of Poly/SiON Gate Stack Combined with Thin BOX and Ground Plane for Low Vth and Analog Applications of FDSOI Devices", International Conference on Solid State Devices and Materials (SSDM2008), 2008.

3. E. Bourjot, T. Tra Nguyen, P. Gergaud, J-M. Hartmann, F. Nemouchi, M. Gregoire, and D. Mangelinck, "Synchrotron Texture Analysis on ultrathin Ni-based germanosilicide in bottom of trenches: application to PMOS 14 nm UTBB SOI", MRS Spring Conference, San Francisco, 2014.

4. R. Estivill, A. Grenier, M. Juhel, M. Gregoire, P. Caubet, N. Rolland, F. Vurpillot, and D. Blavette, "Analysis and reconstruction of HfO2 based gate stacks for CMOS devices", Atom Probe Tomography and Microscopy Conference, 2015.

5. F. Nemouchi et al., "Source and drain contact challenges for 14 and sub-14 nm FDSOI", 32nd annual Advanced Metallization Conference (AMC), 2015.

6. F. Nemouchi, E. Bourjot, F. Deprat, P. Rodriguez, M. Gregoire, D. Mangelinck, P. Gergaud, S. Favier, J.-M. Hartman, V. Loup, S. Joblot, P. Batude, C. Fenouillet, and M. Vinet, "SiGe metallization challenges and developments in context of FD-SOI and Coolcube™ integrations", 7th International Symposium on
Control of Semiconductor Interfaces (ISCSI-VII) and International SiGe Technology and Device Meeting 2016 (ISTDM2016), 2016.

7. A. Valery, L. Gaben, M. Gregoire, Y. Le-Friec, F. Lorut, and L. Clement, "Microstructure Analysis of Nanosized Advanced Materials through the ACOM-TEM Technique", International Conference on Solid State Devices and Materials, 2016.

### I.3.4 US patents

1. P. Caubet, M. Grégoire, "Process for forming integrated circuit comprising copper lines", US Patent App. 7/531,447, 2009.

2. M. Grégoire, "Method for forming a silicide layer at the bottom of a hole and device for implementing said method", US Patent App. 9/257,291, 2016.

3. M. Grégoire, "Siliciding method", US Patent App. 16/412,959, 2019.

4. J. Borrel, M. Gregoire, "Contacts for electronic component", US Patent App. 16/892,732, 2020.

5. M. Grégoire, "Interconnection element and method of manufacturing the same", US Patent App. 16/881,689, 2020.

6. M. Grégoire, "Intermetallic compound", US Patent App. 16/907,986, 2020.

## I.4 Ph. D Thesis and master internship supervision

### I.4.1 Ph. D Thesis supervision

- Federico Panciera, CIFRE thesis, STMicroelectronics Crolles (France) in collaboration with IM2NP (Marseille, France), "La sonde atomique tomographique: applications aux dispositifs CMOS avancés sub-45nm," Aix-Marseille University, 2012. Co-supervision with Marc Juhel (STMicroelectronics) and Dominique Mangelinck (IM2NP).

- Emilie Bourjot, CIFRE thesis, STMicroelectronics Crolles (France) in collaboration with IM2NP (Marseille, France) and CEA-LETI (Grenoble, France), "Germanosiliciuration à base de Ni et d'alliage Ni₁-xPtₓ pour le p-MOS 14 nm FDSOI," Aix-Marseille University, 2015. Co-supervision with Fabrice Nemouchi (CEA-LETI) and Dominique Mangelinck (IM2NP).

- Robert Estivill, CIFRE thesis, STMicroelectronics Crolles (France) in collaboration with GMP (Rouen, France) and CEA-LETI (Grenoble, France), "Analyse chimique en 3D pour les dispositifs avancés de la microélectronique", Normandy University, 2016. Co-supervision with Marc Juhel (STMicroelectronics) and Didier Blavette (GMP).

- Julien Borrel, CIFRE thesis, STMicroelectronics Crolles (France) in collaboration with IEMN (Lille) and CEA-LETI (Grenoble, France), "Innovative contact technology for CMOS FDSOI 10 nm and below", Lille 1 University, 2017. Co-supervision with Louis Hutin (CEA-LETI) and Emmanuel Dubois (IEMN).
- Mathilde Lemang, CIFRE thesis, STMicroelectronics Crolles (France) in collaboration with IM2NP (Marseille, France) and CEA-LETI (Grenoble, France), "Enjeux de siliciuration pour des technologies avancées de la microélectronique : étude de l'interaction entre les siliciures de NiPt et le phosphore," Aix-Marseille University, 2018. Co-supervision with Philippe Rodriguez (CEA-LETI) and Dominique Mangelinck (IM2NP).

- Flore Boyer, CIFRE thesis, STMicroelectronics Crolles (France) in collaboration with IMEP-LaHC (Grenoble, France) and CEA-LETI (Grenoble, France), "Optimization of ohmic contacts on III-V materials: applications to advanced photonic devices," Grenoble Alps University, 2020. Co-supervision with Philippe Rodriguez (CEA-LETI) and Quentin Rafhay (IMEP-LaHC).

- Laura Esposito, CIFRE thesis, STMicroelectronics Crolles (France) in collaboration with IM2NP (Marseille, France) and CEA-LETI (Grenoble, France), "Optimisation des contacts en siliciure de titane pour les technologies imageur avancées," Aix Marseille University, 2021. Co-supervision with Sebastien Kerdiles (CEA-LETI) and Dominique Mangelinck (IM2NP).

In-progress theses started in 2020 and 2021:

- Andrea Newman, CIFRE thesis, STMicroelectronics Crolles (France), Rousset (France) and Agrate (Italy) in collaboration with IM2NP (Grenoble, France), "Approches innovantes pour promouvoir la formation du siliciure CoSi₂ pour les technologies avancées 65 nm caractérisées par sonde atomique tomographique et diffraction de rayons X", ongoing. Co-supervision with Dominique Mangelinck (IM2NP).

- Reda Guelladress, CIFRE thesis, STMicroelectronics Crolles (France) in collaboration with IM2NP (Marseille, France) and CEA-LETI (Grenoble, France), "Impact de la nature des dopants et du confinement sur les couches minces de siliciures de Ti formés par recuit laser nano-seconde", ongoing. Co-supervision with Sebastien Kerdiles (CEA-LETI) and Dominique Mangelinck (IM2NP).

## I.4.2 Master internship supervision

- Oulaya Hajouji, "Etude des dépôts Ni(Pt) à forte concentration de Platine : caractérisations et optimisation. Applications à la siliciuration des technologies CMOS avancées", STMicroelectronics-INSA Toulouse, Master 2-degree internship, 2010. Co-supervision with Jean-Claude Portal (INSA Toulouse).

- Flore Boyer, "Electrical characterization of innovative ohmic contacts for III-V/Silicon photonics devices", STMicroelectronics-LETI-INSA Lyon, Master 2-degree internship, 2017. Co-supervision with Philippe Rodriguez (CEA-LETI) and Bruno Masenelli (INSA Lyon).

- Andrea Newman, "Texture and composition characterizations of thin TiSi₂ layers formed by nanosecond laser annealing", Master 2-degree internship, 2020. Co-supervision with Dominique Mangelinck (IM2NP).
I.5 Collective responsibilities and conference organization

I.5.1 Peer-review for international journal and conferences with reading committee

- Conference reviews:

o Materials for Advanced Metallization (since 2014)

o Solid-State Devices and Materials (since 2018)

o International Electron Devices Meeting (2014-2016)

- Reviewer for AIP (AIP Advances)

I.5.2 European and national research projects contribution

- ST leader for ANR TAPAS (2009-2012): collaboration program with CEA-LETI (Grenoble), GPM (Rouen), IM2NP (Marseille), and ST Crolles, which supports the introduction of atom probe tool at IM2NP.

- ST member of ANR APTITUDE (2014-2017): collaboration program with CEA-LETI (Grenoble), GPM (Rouen), and ST Crolles to define rules for Atom probe results modeling.

- ST member of Nano2017 program MOSDIIA (2014-2017) and MOSDIIA2 (2017-2020): collaboration program with CEA-LETI (Grenoble), LAAS (Toulouse), and ST Crolles for advanced characterization technique of Schottky barrier height.

- ST leader for Advanced Contacts Work Package in the field of bilateral development program with CEA-LETI: “Alpha Program” since 2015.

I.5.3 Participation of Ph. D defense jury

- 2016 – Ph. D defense of Jacques Perrin Toinin : “Étude du dopage et de la formation des contacts pour les technologies germanium”, Ph.D thesis in Condensed matter and Nano-sciences under the supervision of Alain Portavoce and Khalid Hoummada, Aix-Marseille University.

- 2018 – Ph. D defense of Ting Luo: “Study of the mechanisms of silicide formation by isotope diffusion and atom probe tomography”, Ph.D thesis in Condensed matter and Nano-sciences under the supervision of Dominique Mangelinck and Christophe Girardeaux, Aix Marseille University.

- 2019 – Ph. D defense of Hannes Zschiesche : “Formation and segregation in cobalt silicide and manganese germanide thin films : correlative study by electron microscopy and atom probe tomography”, Ph.D thesis in Condensed matter and Nano-sciences under the supervision of Claude Alfonso and Dominique Mangelinck, Aix Marseille University.

- 2020 – Ph. D defense of Julien Sorel, “Tomographie électronique analytique : automatisation du traitement de données et application aux nano-dispositifs 3D en micro-électronique”, Ph.D thesis in Material Science under the supervision of Thierry Epicier and Zineb Saghi, Lyon University.
### I.5.4 Conference organization

- Since 2019 – Member of scientific program committee of Materials for Advanced Metallization conference.

- 2020 – Member of local organization of MAM2020 at Grenoble, virtual event (France).
<figure><img src="image_6.png" /></figure>
# CHAPTER II

## Overview of silicide challenges in microelectronics

### Abstract

In this chapter, the aims of silicide layers in microelectronics devices, the success criteria needed for current technologies under development, and the remaining challenges of Ni, Co and Ti-based silicidation processes will be presented. Silicide integrations as silicide first and silicide last will then be described. The background requested for the reader to deeply understanding the experimental results which will be presented and discussed in the following chapters is introduced afterwards. At the end, the technological issues related to silicide formation, morphological and thermal instabilities addressed during the last 10 years are formerly detailed.
Table of Contents

<table><tr><td>II.1</td><td>Ni, Co and Ti silicides integration vs MOSFET and derivatives devices evolution</td><td>19</td></tr><tr><td>II.1.1</td><td>MOSFET introduction</td><td>19</td></tr><tr><td>II.1.2</td><td>Depleted channels: FinFet and FD-SOI technologies</td><td>20</td></tr><tr><td>II.1.3</td><td>SiGe raised source drains</td><td>21</td></tr><tr><td>II.1.4</td><td>Novel 3D integrations for imaging technologies</td><td>21</td></tr><tr><td>II.1.5</td><td>Silicide integrations evolution</td><td>23</td></tr><tr><td>II.1.6</td><td>Salicide First and Salicide Last integrations</td><td>25</td></tr><tr><td>II.2</td><td>Solid-state reactions in the Ni-Si, Ni-Ge, Co-Si and Ti-Si systems</td><td>26</td></tr><tr><td>II.2.1</td><td>Ni-Si and Ni-Ge systems</td><td>27</td></tr><tr><td>II.2.2</td><td>Co-Si and Ti-Si systems</td><td>30</td></tr><tr><td>II.3</td><td>Remaining challenges for salicide first integration</td><td>32</td></tr><tr><td>II.3.1</td><td>Morphological and thermal instabilities of Ni-silicides and germanides</td><td>32</td></tr><tr><td>II.3.2</td><td>Shallow junctions: silicide thickness control and dopant redistribution</td><td>34</td></tr><tr><td>II.3.3</td><td>Reduction of Ni-systems degradations: alloying and surface preparation</td><td>35</td></tr><tr><td>II.3.4</td><td>CoSi₂ integration limitations</td><td>36</td></tr><tr><td>II.4</td><td>New advanced contacts integrations</td><td>38</td></tr><tr><td>II.4.1</td><td>Ti-silicided contacts</td><td>38</td></tr><tr><td>II.4.2</td><td>Metal-Isolator-Semiconductors (MIS) contacts</td><td>39</td></tr><tr><td>II.4.3</td><td>III/V intermetallic contacts for photonic applications</td><td>42</td></tr><tr><td>II.5</td><td>Conclusions of Chapter II</td><td>44</td></tr></table>
## II.1 Ni, Co, and Ti silicides integration vs MOSFET and derivatives devices evolution

### II.1.1 MOSFET introduction

The development of transistors and their applications, hand in hand with information technology, has revolutionized the society we live in. The existence of most electronic devices, from mobile phones and computers to the microcontrollers found in cars and household appliances, rely on the unique transistor.

During the last century, the first patent on the field-effect-transistor (FET) was proposed by J.E Lilienfeld in 1925. In 1947, a point-contact transistor was invented by J. Bardeen, W. Brattain, and W. Schockley, who received the Nobel prize in 1956 for their work. In the following years, the Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) was introduced by D. Kahng and M. Atalla in the 1960's. This revolutionary architecture allows drastically to increase the speed of transistors and decrease the energy consumption (compared to the bi-polar transistors). As shown in Figure II.1a, the fundamental stack of MOSFET is composed of three main elements. The first is a semiconductor (silicon) where a current of electric carriers can take place. These carriers travel between two reservoirs, source and drain, via a path, the channel. The state of this channel, open or closed, is controlled by a field effect. This field arises from the bias of the third element, the gate, which consists of a metallic electrode separated from the channel by a dielectric layer (known as the gate oxide). Depending on the dopants introduced in the source and drain, the current carriers flowing in the channel can be electrons (the MOSFET shown in Fig. II.1 is referred to as NMOS because electron carries a Negative charge) or quasiparticles equivalent to a lack of electrons, holes (then named PMOS, for Positive charge). The transistor can switch from ON to OFF state by applying a voltage on the control gate (Fig. II.1b).

<figure><img src="image_7.png" /><figcaption>Figure II.1. Schematic of a planar MOSFET on Si bulk substrate, i.e., NMOS (a). Classical $I_d-V_g$ curve which shows the evolution of the drain current $I_d$ when a positive tension is applied on the gate (reproduced from [7]).</figcaption></figure>

For decades, one of the driving forces of the microelectronics industry has been to reduce the dimensions of the transistor, leading to an increase of the transistors density per chip and thus reducing the manufacturing price per transistor [8]. Beyond the economic benefit, it was also shown that such a reduction of dimensions would lead to a gain in device performance [9].

To follow Moore's law, the gate length, which is the most aggressive dimension (and then used for technology node naming), has been reduced from 10 µm in 1971 to sub-10 nm technologies today [10]–[12]. Nevertheless, for the latest generations, scaling this length required innovative integrations as described below. Parasitic effects called Short Channel Effects (SCE) and Drain induced Barrier Lowering (DIBL) appear and diminish the electrostatic control of the channel by the gate. That is the reason of the emergence of newer architectures and integrations.
II.1.2 Depleted channels: FinFet and FD-SOI technologies

Due to the preponderance of the short channel effects, new architectures have been adopted since the 32 nm node as alternatives to the Si-bulk MOSFET: the FinFET (Fin Field Effect Transistor) [13] and the FDSOI (Fully Depleted Silicon On Insulator) [14]. While the FinFET is a 3D device, the FDSOI remains a planar architecture. In both cases, the channel is not doped with the complementary polarity of the transistor (P for NMOS and N for PMOS) but remains intrinsic [15].

Being non-planar, the FinFET represented in Figure II.2 is a 3D integration, and the main advantage of this architecture is that the gate follows the topography of the fin. While in planar architecture only the top surface of the channel is perfectly controlled by the gate, in FinFET, the channel is in the surrounding area of the gate oxide and thus the whole fin is well controlled.

<figure><img src="image_8.png" /><figcaption>Figure II.2. 3D scheme of a FinFET device and the corresponding cross-sections A-A' and B-B' from [16].</figcaption></figure>

For 28 nm nodes and beyond, planar Fully Depleted Silicon On Insulator (FDSOI) technology has demonstrated large performance boost [17], [18], and allows reaching low mismatch variability thanks to un-doped channel [15]. The main characteristic of this architecture deals with the introduction of Silicon On Insulator (SOI) substrate which features a thin silicon top layer on top of a Buried OXide layer (BOX). The principle of this architecture is like to the FinFET one: since SOI layer is ultra-thin (less than 10 nm), the whole depth of the channel is effectively controlled by the gate. Additionally, as shown in Figure II.3, the active zone is separated from the bulk substrate by the BOX thus avoiding one of the leakage current contributions.

For 14 nm node and beyond, planar Ultra-Thin Box and Buried Silicon-On-Isolator (UTBB SOI) CMOS on Fully Depleted SOI (FD-SOI) substrate is an alternative approach to FinFET technology [15].

<figure><img src="image_9.png" /><figcaption>Figure II.3. 3D scheme of a FDSOI device and the corresponding cross-section B-B' from [18].</figcaption></figure>
## II.1.3 SiGe raised source drains

For advanced technologies, below 20 nm node, raised source drains promoted by epitaxy techniques has been introduced [15]. In the frame of silicides integration, the most important change was the introduction of SiGe epitaxial layers in PMOS sources and drains (Fig. II.4). The aim of this new architecture is to enhance the carrier mobility in these areas by using the difference in lattice size between Si and Ge (respectively 5.43 Å and 5.65 Å), which allows a compressive strain inside the channel [19].

<figure><img src="image_10.png" /><figcaption>Figure II.4. TEM cross-section obtained on 14 nm UTBB-SOI PMOS after silicide formation and SiN deposition. This technology integrates SiGe raised source and drain to promote higher carrier mobility (STMicroelectronics internal data).</figcaption></figure>

## II.1.4 Novel 3D integrations for imaging technologies

Furthermore, complementary metal-oxide-semiconductor (CMOS) image sensors have been the subject of extensive research and are widely used for different purposes in several applications (digital camera, smartphone, automotive, security, biotechnology, medical) [20], [21]. This situation has been possible thanks to the fact that CMOS Image Sensor (usually named CIS) have been improving their performance, their functional capability, and their flexibility during last years. Then, CIS has emerged as a strong alternative to Charge Camera Detector (CCD) and presents very promising functionalities. New horizons have been opened, like ultra-low power or camera-on-chip systems. A CMOS image sensor generally consists of an imaging area which comprises an 2D array of pixels. Each pixel contains a photodetector and several transistors used to access each pixel and read the output-electrical signal value of the pixel as presented in Fig. II. 5. The photodetector is usually formed by a vertical pn junction which permits a photo-electronic current generation when light is incident on the pixel area (Fig. II.5a). The incident light is absorbed by silicon and produces electron-holes pairs inside the pn junction (Fig. II.5b). Thus, the produced photo-current is proportional to the input light intensity if the junction is reverse biased [20]. The transfer of this current is provided by the “transfer gate”, i.e., a NMOS transistor located near the photodiode inside the pixel area (Fig. II.5b).
<figure><img src="image_11.png" /><figcaption>Figure II.5. Schematics of CMOS Image Sensor (CIS) including micro-lens and color filters on the top of the photodiode inside the pixel area (a). Schematics of the photodiode as a vertical pn-junction in which the photo-electronic current is generated under illumination and then gathered by the transfer gate to the sense node (b).</figcaption></figure>

Similar to CMOS technologies, several innovations have allowed the improvement of CIS performances: such as noise reduction, image quality, quantum energy increase and crosstalk decrease [20]. One of the most promising is the 3D integration [22], [23].

As shown in Figure II.6, the wafer stacking has given the opportunity to a drastic evolution of the imager technologies [21]. Firstly, in Fig. II.6a, the photodiode was embedded in the substrate and the illumination came from the Front-Side of the wafer (Front-Side Illuminated technology). Secondly, hybrid bonding and wafer thinning enabled the integration of on-chip lens on the backside of the photodiode. This results in a significant improvement of image quality (increase of quantum efficiency), as presented in Fig. II.6b. This integration is known as Back-Side Illuminated (named BSI). Currently, a dual layer device as 3D Stacked Back-Side Illuminated (3D-BSI) imager integrates a CMOS imager sensor on the top of the logic CMOS device layer (Fig. II.6c).

<figure><img src="image_12.png" /><figcaption>Figure II.6. Evolution of imager technologies from Front-Side Illuminated (FSI) (a), to Back-Side Illuminated (BSI) (b), and current 3D Stacked BSI (3D-BSI) (c) [21].</figcaption></figure>

Such 3D integration deals with two wafers bonded together: one is dedicated to photo-electronic current gathering ("pixel layer" or "top tier") and the second one to signal computing ("bottom tier") as detailed below.
<figure><img src="image_13.png" /></figure>

Figure II.7. Bloc diagram of a 3D CMOS Image Sensor device including two 300 mm-wafers bonded each other: the pixels are integrated on the “top tier” and the signal computing is performed by the “bottom tier” [23].

Recently, the 3D sequential integration (named hereafter 3D-sequential) has been applied to imager technologies to provide higher performances and minimize the pixel and final chip dimensions [22], [24]. As described in Fig. II.8, this specific integration includes several “layers” of transistors on the top of the embedded photodiode which enables fast signal computing, lower power consumption (thanks to SOI substrate) and reduction of chip dimensions.

<figure><img src="image_14.png" /></figure>

Figure II.8. 3D sequential integration process flow (3D-sequencial): 1) embedded photodiode fabrication, 2-4) transfer of a second SOI layer by direct bonding, 5) low temperature transistor processing, 6) contacts and BEOL. 7-9) Backside illumination is finally performed (reproduced from [22]).

II.1.5 Silicide integrations evolution

Such large scale of CMOS and derivatives technologies requires a precise dedicated silicide integration. As being extensively explained in the following sections, silicide layer is formed at the surface of active regions (gate, source and drain, photodiode) to provide electrical continuity between interconnections (W contacts and BEOL i.e. Back-End Of the Line) and microelectronic devices. The silicide layer thus becomes the first level of interconnections. To achieve a very low RC delay and high devices performances, Ni(Pt)Si and CoSi₂ silicides have been widely used in planar technologies for several decades [15], [25].

For 3D integrations (as presented before) [26]–[28], Ni and Co-based silicides, defined as “salicide first” process for “Self-Aligned SiLICIDE”, have been replaced by Ti-based silicided contacts (details will be given in Figs. II.9 and 10).

For Finfet and advanced imaging technologies, the Titanium silicide is formed directly inside the contacts, known as “salicide last” integration. This integrations allows to establish a low-Schottky barrier
contacts to silicon, reducing the contact resistivity [29]. For 3D imager technologies, avoiding the classical
silicide first scheme in the photosensitive regions aims to minimize the surrounding metal surface near the
photo-diode detector and suppress potential metal contaminations related to silicide.

For new 3D-Sequential technologies, the co-integration between Ti-silicided contacts on transfer gates and the subsequent Ni-silicided CMOS implies a unique process step for contact filling (Fig. II.8, picture 6). Thus, on the one hand, the formation of low-resistive Ti-silicide phase is needed in the contacts of photosensitive region; on the other hand, very thin NiSi layer is previously formed under the Ti-based contacts. Such co-integration remains definitely a challenge because, as it will be introduced in section II.1.6, the formation of TiSi₂ phase requests higher thermal budgets than could be applied on NiSi thin films leading to the detrimental agglomeration of such layers. That is the reason why, as it will be discussed in Chapter IV, some new processes need to be investigated to reduce the TiSi₂ phase formation temperature.

For Ni, Co and Ti-based silicide integrations, the requirements and the induced constraints remain the same as low resistivity, low Si consumption and high thermal and morphological stabilities, as detailed in the following figure, inspired by Lavoie et al. [27].

<figure><img src="image_15.png" /></figure>

Figure II.9. Evolution of “salicide” integration from C54-TiSi₂ to Ni(Pt)Si and recent Ti-based contacts dedicated to 3D integrations based on [3], [27] and STMicroelectronics internal data. On the x-axis the technology node and the referred integration are notified. On the y-axis the metal diffusion coefficient in silicon at 500 °C is given for Ti, Co and Ni silicide. The dominant diffusing species for each system are Si for Ti-Si, Co and Co for Co-Si, and Ni for Ni(Pt)-Si respectively, based on [31].

Based on these considerations, for each technology, device, and subsequent application (voltage ranking, radiofrequency, power consumption, memories), a precise silicide brick integration is required to minimize the access resistance to active devices without affecting their reliability, by introducing specific failure mechanisms linked to the silicide layer (as will be presented in section II.6).
II.1.6 Salicide First and Salicide Last integrations

As shortly introduced below, for planar microelectronic technologies, a "salicide first" integration
scheme (Fig. II.10) is used and defined as the silicide formation at the top surface of the polysilicon gates
and in the source and drain regions before contact patterning.

<figure><img src="image_16.png" /><figcaption>Figure II.10. Ni(Pt)Si and Ni(Pt)SiGe process flow for a "Salicide first" integration i.e., "self-aligned silicide" formed before the contacts patterning, on the left. Two types of Ni silicide process are used: total and partial reaction related to the total or the partial consumption of Ni(Pt) film. Similar salicide first scheme in the case of Co di-silicide formation, on the right.</figcaption></figure>

Such "pre-contact" silicide formation presents two annealing steps (noted RTA1 and RTA2 for Rapid
Thermal Annealing 1 and 2) after metal deposition, including a wet removal of unreacted metal (called
selective etching, Fig. II.10) after RTA1. This integration is mainly used to form Ni(Pt) and Co-based silicide
on crystalline doped Si or Si₁-xGex epitaxial layers (sources and drains), poly-crystalline doped Si (gates) at
the same time.

Additionally, in the last past years, a novel Ni(Pt) silicide integration arises, usually called "partial
reaction", as described in Fig. II.10 (on the left). The aim of this new process flow is to enhance similar
silicide formation in the small devices and large areas by reducing the potential lack of step-bottom
coverage of Ni(Pt) deposition in aggressive dimensions [32]–[34]. Moreover, by applying a lower thermal budget during the RTA1, the potential formation of the high resistive NiSi₂ phase in very small actives areas is drastically limited or suppressed ([33], further explanations in § II.2.1).

As presented in the previous sections, Ti-based silicide contacts in recent 3D FinFETs and imager technologies have been introduced. This silicide integration is named “salicide last” integration, i.e., *post contact patterning*, and is described in Fig. II.11.

<figure><img src="image_17.png" /><figcaption>Figure II.11. TiSiₓ contacts process flow for a “salicide last” integration which is defined as a “self-aligned silicide” formed after the contacts patterning. For this integration, only one RTA is generally applied at high temperatures.</figcaption></figure>

Some examples of Ni, Co and Ti silicides formed in real devices are presented in Figs. II.12 and II.13. Ni and Co silicide films are the dark layers under the W contacts (Fig. II.12a) and on the top of gates (Fig. II.12b). The TiSiₓ layer at the bottom of contacts is detected by STEM-EDX mappings as shown in Fig. II.13b.

<figure><img src="image_18.png" /><figcaption>Figure II.12. TEM cross-sections of Ni(Pt)Si silicide layers (dark grey) formed on the top of gates and source/drains in 28 nm CMOS devices (a). Similar characterizations of CoSi₂ silicide layers in 90 nm devices (b).</figcaption></figure>

<figure><img src="image_19.png" /><figcaption>Figure II.13. TEM cross sections of TiSiₓ contacts formed in the pixel area by applying a single RTA after Ti/TiN deposition (a). STEM-EDX mappings of the bottom of the contact on gates and extracted 1D atomic percentage following the blue arrow in (b).</figcaption></figure>

## II.2 Solid-state reactions in the Ni-Si, Ni-Ge, Co-Si and Ti-Si systems
Solid-state reaction of a thin metal film with a semiconductor substrate is related to diffusion or nucleation mechanisms [35]. As a first approach, the phase sequence can be deduced from the phase diagrams, even though they have been experimentally determined for bulk materials [36]. The main differences in the phase sequence observed during the reaction of thin metal films are linked to the interfacial reaction rate, change in diffusion coefficient of one component to another, and nucleation barrier height. In the following sections, phase diagrams for Ni-Si, Ni-Ge, Co-Si, Ti-Si systems are presented as well as the related phase sequence for thin films reaction giving a specific highlight in the metal-rich phase formation.

II.2.1 Ni-Si and Ni-Ge systems

In the field of silicide formation, one of the most complex phase diagram as detailed by Lavoie et al. [37] is the Ni-Si one, presented in Fig. II.14.

<figure><img src="image_20.png" /><figcaption>Figure II.14. Phase diagram at equilibrium for the Ni-Si system [36].</figcaption></figure>

Several silicide phases are present with stoichiometric phases (β-Ni₃Si, δ-Ni₂Si, NiSi and α-NiSi₂) in phase diagram, and three presenting a deviation to the stoichiometric value (β₁-Ni₃Si, ε-Ni₃Si₂ and θ-Ni₂Si). The principal characteristics of Ni silicides are detailed in Table. II.1.

<caption>Table II.1. Composition, melting temperature, crystal structure and resistivity of the Ni silicides.</caption>
<table><thead><tr><th>Phase</th><th>Si (at. %)</th><th>T<sub>m</sub> (°C)</th><th>Crystal structure</th><th>Parameter lattice<br>a/b/c (Å)</th><th>Resistivity (μΩ.cm)<br>[37]</th></tr></thead><tbody><tr><td>Ni</td><td>&lt; 10</td><td>1 455</td><td>FCC Fm3m</td><td>3.52</td><td>8</td></tr><tr><td>β-Ni<sub>3</sub>Si</td><td>25</td><td>1240</td><td>Cubic Pm3m</td><td>3.50</td><td>85</td></tr><tr><td>β-Ni<sub>31</sub>Si<sub>12</sub></td><td>27.9</td><td>1240</td><td>Hexagonal P321</td><td>6.68/-/12.29</td><td>120</td></tr><tr><td>δ-Ni<sub>2</sub>Si</td><td>33,33</td><td>1 300</td><td>Orthorhombic Pnma</td><td>5.00/3.37/7.04</td><td>27</td></tr><tr><td>θ-Ni<sub>2</sub>Si</td><td>33 - 42</td><td>1 300</td><td>Hexagonal P63/mmc</td><td>3.80/-/4.89</td><td>27</td></tr><tr><td>ε-Ni<sub>3</sub>Si<sub>2</sub></td><td>39 - 41</td><td>825</td><td>Orthorhombic Cmc21</td><td>12.29/10.80/6.92</td><td>65</td></tr><tr><td>NiSi</td><td>50</td><td>990</td><td>Orthorhombic Pnma</td><td>5.23/3.52/5.62</td><td>17</td></tr><tr><td>α-NiSi<sub>2</sub></td><td>66,66</td><td>993</td><td>FCC Fm3m</td><td>5.40</td><td>40</td></tr><tr><td>Si</td><td>&gt; 99,97</td><td>1 414</td><td>FCC Fd3m</td><td>5.43</td><td>2-4.10<sup>4</sup> (p-type)</td></tr></tbody></table>

The first phases to form for this system have been extensively studied [38]–[41] and still present a great interest in terms of solid-state reaction understanding and, as detailed in this manuscript, are also a key parameter in terms of silicide integration. For typical Ni thickness used in microelectronics devices, comprised between 6 and 20 nm, the first phase to form is the Ni₂Si, as described in [42]:

$$ \mathrm{Ni} \rightarrow \delta\text{-Ni}_2\text{Si} \text{ or } \theta\text{-Ni}_2\text{Si} \rightarrow \mathrm{NiSi} \rightarrow \alpha\text{-NiSi}_2 \qquad \text{Eq. II.1} $$

It has been proven by experiments that Ni atoms are the main diffusing species during the formation of δ-Ni₂Si [39], [43] and NiSi [39]. Moreover, it is also important to point out that the growth of δ-Ni₂Si and NiSi is controlled by Ni diffusion; and contrary to the nucleation-controlled formation of CoSi₂ and NiSi₂, detailed in the next sections, the Ni diffusion-controlled reaction usually evolves uniformly, and allows the formation of flat silicide/silicon interface and silicide layer in aggressive dimensions.

Several parameters can play a role on the first phase formation such as NiSi intermixing layer, Ni layer thickness, nature of the Ni alloy, surface preparation processes, substrate nature (Si, SiGe) and type (n, p), and, at the end, the device dimensions. Such aspects will be deeply discussed in Chapter III.

Furthermore, the solid-state reaction between a thin metal film and a thick substrate should be in principle predicted by considering the thermodynamics and kinetics of the phase formation. Several models have been reported based on thermodynamics, as [44], or diffusion kinetics as D'Heurle and Gas's one [45]; and as a general rule, the first phase to form should be the phase with the fastest diffusion kinetics. Therefore, in Ni-Si system, δ-Ni₂Si phase should be the first silicide to grow.

According to the Ni-Si phase diagram, θ-Ni₂Si is a non-stochiometric phase with a variation in the Ni composition of 33.3 to 40 at. % (Table II.1). A large part of Chapter III will be dedicated to the characterization of first phase formation in the case of Pt addition as Ni alloy for different systems.

High resistive NiSi₂ (Table II.1) with an FCC (CaF₂) structure is usually, for Ni thickness larger than 4 nm, the last silicide to form at high temperature (> 750 °C). NiSi₂ and Si have similar crystal structures and the mismatch in the lattice parameter is small (0.4 % at room temperature [46]). Some studies have proved that NiSi₂ can grow epitaxially on Si substrates, as described in subsection II.3.3. The formation of NiSi₂ phase is controlled by nucleation [47]. However, it is difficult to investigate the growth kinetics of NiSi₂ phase due to its nucleation-controlled growth and because, in the range of studied silicide thicknesses, the agglomeration of NiSi usually precedes the NiSi₂ growth or occurs at similar temperatures.

For Ni-Ge system, the phase diagram reported by Nash et al. [36] is the following:
<figure><img src="image_21.png" /><figcaption>Figure II.15. Phase diagram at equilibrium for the Ni-Ge system [36].</figcaption></figure>

Ni-rich germanide phases are present as well as non-stochiometric phases, as described in Table II.2:

<table><caption>Table II.2. Composition, melting temperature, crystal structure and resistivity of the Ni germanides (from [6], [48]).</caption><thead><tr><th>Phase</th><th>Si (at. %)</th><th>T<sub>m</sub> (°C)</th><th>Crystal structure</th><th>Parameter lattice<br>a/b/c (Å)</th><th>Resistivity (μΩ.cm)<br>[49]</th></tr></thead><tbody><tr><td>Ni</td><td>&lt; 12</td><td>1 455</td><td>FCC Fm3m</td><td>3.52</td><td>8</td></tr><tr><td>Ni<sub>2</sub>Ge</td><td>33.33</td><td>506</td><td>Orthorhombic Pnma</td><td>7.26/5.11/3.83</td><td></td></tr><tr><td>Ni<sub>3</sub>Ge</td><td>40</td><td>1024</td><td>FCC Fm3m</td><td>5.74</td><td></td></tr><tr><td>ε-Ni<sub>5</sub>Ge<sub>2</sub></td><td>33.8-38</td><td>1185</td><td>Hexagonal P63/mmc</td><td>3.95/-/5.04</td><td></td></tr><tr><td>Ni<sub>19</sub>Ge<sub>12</sub></td><td>38-41</td><td>1050</td><td>Monoclinic C2</td><td>11.63/6.72/1.00</td><td></td></tr><tr><td>Ni<sub>3</sub>Ge<sub>2</sub></td><td>41-43</td><td>990</td><td>Hexagonal P63/mmc</td><td>3.95/-/5.04</td><td></td></tr><tr><td>NiGe</td><td>50</td><td>850</td><td>Orthorhombic Pnma</td><td>5.81/5.38/3.43</td><td>14</td></tr><tr><td>Ge</td><td>100</td><td>938.3</td><td>FCC Fd3m</td><td>5.65</td><td>2-4.10<sup>4</sup> (p-type)</td></tr></tbody></table>

The aim of our work was to determine the phase sequence formation in the case of the germano-silicide i.e., for the ternary system Ni-SiGe. In that case, the phase formation is sequential, as described hereafter [50]–[53]:

$$ \mathrm{Ni} \rightarrow \mathrm{Ni}_{2}\mathrm{Si}_{1-x}\mathrm{Ge}_{x} \rightarrow \mathrm{NiSi}_{1-x}\mathrm{Ge}_{x} \qquad \text{Eq. II.2} $$

Hence the phase sequence is clearly dependent of Ge atomic concentration in the initial $Si_{1-x}Ge_x$ substrate. On one hand, for the Ni-Ge system, as reported by De Schutter et al. [54], the Ge concentration might have an impact on the first phase to form at low temperature and a metastable hexagonal phase is hence detected if Ge atomic concentration (x) is comprised between 36 and 48 at. %. On the other hand, for high Ge concentration, $Ni_2Si_{1-x}Ge_x$ phase is no more observed [50]–[53].

The main concerns in achieving a reliable, less resistive, and stable germano-silicide formation on SiGe substrates are the Ge partition and the $NiSi_{1-x}Ge_x$ agglomeration, as detailed in § II.3.3, and in the next chapter. For this system, Ni atoms should be the main diffusing species during the different phase formation. By analogy with the Ni-Si system, the growth of Ni-rich and germano-silicide phases appears to be controlled by Ni and Ge diffusions.
II.2.2 Co-Si and Ti-Si systems

CoSi₂ thin films on Si substrates are widely used in microelectronic applications due to the following advantages: low resistivity, high thermal stability and the good match of the crystal structure with Si (with a mismatch inferior to 2 %, [55], see also Table II.3).

<figure><img src="image_22.png" /><figcaption>Figure II.16. Phase diagram at equilibrium for the Co-Si system [30], [37].</figcaption></figure>

As presented in Figure II.16, the stable silicide phases are Co₂Si, CoSi, and CoSi₂. Similarly to the Ni-Si system, the phase growth is sequential for thin films as [30]:

$$ \varepsilon\text{-Co}\rightarrow\alpha\text{-Co}_2\text{Si}\rightarrow\text{CoSi}\rightarrow\text{CoSi}_2 \qquad \text{Eq. II.3} $$

Co₂Si and CoSi are formed by diffusion-controlled kinetics with respective activation energies of 1.5 eV and 1.9 eV [30]. Moreover, Co₂Si and CoSi phases both show a narrow concentration range, respectively from 32 to 34 at. % for Co₂Si and from 49 to 52 at. % for CoSi [37].

The CoSi₂ formation is driven by nucleation [47] and the nucleation of the CoSi₂ phase occurs at triple points between two CoSi grains and Si substrate. Then lateral growth takes place until a continuous CoSi₂/Si interface is formed. Only a stoichiometric composition is reported for CoSi₂ phase. Such layer exhibits a cubic-face-centered crystal structure, and the lattice parameters are strictly close to Si crystal ones, as previously introduced. These closed structures and lattices parameters allow the growth of epitaxial CoSi₂ films on Si substrates [56]. Such an epitaxial silicide layer can enable enhanced conductivity and could lead to higher morphological stability, as discussed in Chapter IV (see also [57]).

Marker experiments allow to identify the main diffusing species during the formation of the various Co-silicide phases [45]. The experiments show that the Co₂Si layer grows predominantly by Co diffusion and that the CoSi phase grows predominantly by Si diffusion. During CoSi₂ phase growth, the diffusion of Co is predominant. Composition, crystal structure, and resistivity for the main Co silicides are reported in Table II.3, as follows:
<table><caption>Table II.3. Composition, melting temperature, crystal structure, and resistivity of the Co silicides [30], [35].</caption><thead><tr><th>Phase</th><th>Si (at. %)</th><th>T<sub>m</sub> (°C)</th><th>Crystal structure</th><th>Parameter lattice<br>a/b/c (Å)</th><th>Resistivity<br>(μΩ.cm)</th></tr></thead><tbody><tr><td>ε-Co</td><td>&lt; 16.4</td><td>1495</td><td>Hexagonal P63/mmc</td><td>2.50/-/4.06</td><td>8</td></tr><tr><td>α-Co<sub>2</sub>Si</td><td>32-34</td><td>1334</td><td>Orthorhombic Pnma</td><td>7.10/4.91/3.73</td><td>70</td></tr><tr><td>CoSi</td><td>49-50.5</td><td>1460</td><td>Cubic P213</td><td>4.43</td><td>147</td></tr><tr><td>CoSi<sub>2</sub></td><td>66.6</td><td>1326</td><td>FCC Fm3m</td><td>5.35</td><td>15</td></tr><tr><td>Si</td><td>&gt; 99,97</td><td>1414</td><td>FCC Fd3m</td><td>5.43</td><td>2-4.10<sup>4</sup> (p-type)</td></tr></tbody></table>

The solid-state reaction between Ti thin films and Si leads to the formation of Ti<sub>5</sub>Si<sub>3</sub> and TiSi phases, as first phases to grow, converting into TiSi<sub>2</sub> at temperatures higher than 650 °C (Fig. II.17, and [30]).

<figure><img src="image_23.png" /><figcaption>Figure II.17. Phase diagram at equilibrium for the Ti-Si system [55].</figcaption></figure>

For Ti thicknesses lower than 100 nm, the typical phase sequence has been reported as [35]:

$$ \beta\text{-Ti} \rightarrow \text{a-Ti}_{1-x}\text{Si}_x \rightarrow \text{C49-TiSi}_2 \rightarrow \text{C54-TiSi}_2 \qquad \text{Eq. II.4} $$

where a-Ti<sub>1-x</sub>Si<sub>x</sub> is an amorphous phase.

For the TiSi silicide, the phase formation proceeds by diffusion-limited growth [45]. If native oxide removal prior Ti deposition is perfectly done, no Ti-rich phases are observed [30]. A specific highlight on the surface preparation processes before Ti-silicides formation will be then presented in Chapter IV.

During the formation of TiSi<sub>2</sub>, Si has been identified to be the main moving species [30].

After a usual RTA in the 550 to 850 °C temperature range, two phases of titanium disilicides, TiSi<sub>2</sub>, could exist. The high resistive metastable phase, C49-TiSi<sub>2</sub> (with an intrinsic resistivity of 60–70 μΩ.cm, Table II.4), is the first phase to grow at a temperature between 550 and 700 °C [30], [57]. The stable phase, C54-TiSi<sub>2</sub>, with a low resistivity (15–20 μΩ.cm, Table II.4), is formed from C49-TiSi<sub>2</sub> at higher temperatures between 700 and 850 °C [30], [58], [59]. However, the C49–C54 transformation is difficult in narrow lines because of the nucleation-controlled mechanism which occurs at triple grain boundaries between Si substrate and C49-TiSi<sub>2</sub> phase [35], [61].
Recently, studies demonstrated a change in phase sequence induced by pulsed laser annealing process. Indeed, the C54-TiSi₂ phase can be obtained from C40-TiSi₂, by-passing the undesirable C49-TiSi₂ phase [61]–[63]. The C40-TiSi₂ phase, obtained for specific conditions, can thus act as a precursor of C54-TiSi₂ at lower temperatures. As previously given for Ni and Co, the composition and subsequent intrinsic parameters of the main Ti-silicides are presented in Table II.4.

<table><caption>Table II.4. Composition and crystal structure of the Ti silicides (from [30], [64], [65]).</caption><thead><tr><th>Phase</th><th>Si (at. %)</th><th>T<sub>m</sub> (°C)</th><th>Crystal structure</th><th>Parameter lattice<br>a/b/c (Å)</th><th>Resistivity (μΩ.cm)</th></tr></thead><tbody><tr><td>β-Ti</td><td>&lt; 5</td><td>1670</td><td>Hexagonal P63/mmc</td><td>2.95/-/4.68</td><td>For 20 nm: 80-95</td></tr><tr><td>TiSi</td><td>33.33</td><td>506</td><td>Orthorhombic Pnma</td><td>6.53/3.64/5.00</td><td>-</td></tr><tr><td>C49-TiSi<sub>2</sub></td><td>66</td><td>1478</td><td>Orthorhombic Cmcm</td><td>3.54/13.54/3.57</td><td>60-70</td></tr><tr><td>C54-TiSi<sub>2</sub></td><td>66</td><td>1478</td><td>Orthorhombic Fddd</td><td>8.26/4.80/8.55</td><td>15-20</td></tr><tr><td>C40-TiSi<sub>2</sub></td><td>66</td><td>1478</td><td>Hexagonal P6<sub>2</sub>22</td><td>4.72/-/6.58</td><td>35</td></tr><tr><td>Si</td><td>100</td><td>938.3</td><td>FCC Fd3m</td><td>5.65</td><td>2-4.10<sup>4</sup> (p-type)</td></tr></tbody></table>

This short overview of Ni, Co and Ti silicides roles in microelectronics, together with the solid-state reactions of such thin metal films with Si and SiGe substrates, enables to introduce the complexity of their integrations and in essence, the need of their electrical and morphological controls to achieve performant and reliable devices. As introduced in Fig. II.9, the main degradation mechanisms and subsequent drawbacks of each silicide type will be detailed afterwards.

## II.3 Remaining challenges for silicide first integration

### II.3.1 Morphological and thermal instabilities of Ni-silicides and germanides

One of major drawbacks of Ni-silicide is its instability at high temperatures. Three main degradation mechanisms can be identified: abnormal NiSi diffusion in different substrates, the so called “NiSi encroachment or piping” [4], [65], [68], NiSi₂ formation [69]–[71], and NiSi agglomeration [72]–[75].

In real devices, NiSi encroachment induces massive junction leakage due to a deeper penetration of silicide inside the junction under the spacers (Fig. II.18, from [4]).
<figure><img src="image_24.png" /></figure>

Figure II.18. STEM cross-sections (a) and HRTEM image (b) of abnormal NiSi penetration in 45 nm-gate length CMOS devices. This phenomena is usually called NiSi encroachment, from [4].

Another phenomenon, which is almost similar, is named NiSi piping as shown in Figure II.19. NiSi piping might occur on NMOS and PMOS (Fig. II.19a and b respectively) and induce a short-circuit between the source/drain and the channel.

<figure><img src="image_25.png" /></figure>

Figure II.19. TEM-EDX cross-sections of an abnormal diffusion of NiSi under the spacers, known as NiSi piping, in a 28 nm NMOS (a) and PMOS (b). The associated colors of Ni atoms are blue in (a) and red in (b) respectively.

When NiSi$_{2}$ grows in real devices, additionally to a significant increase on the intrinsic resistivity compared to the mono-silicide phase (more than twice, see Table II.1), NiSi$_{2}$ “depth” is measured as 1.5 times what is expected for NiSi phase, leading to the vertical pn or np junction short-circuit in sources and drains. As an example, in Fig II.20a, NiSi$_{2}$ layer thickness is measured by TEM as 33 nm in comparison to the expected 24 nm for NiSi silicide after a similar silicide process.

<figure><img src="image_26.png" /></figure>

Figure II.20. TEM and TEM EDX cross-sections in 40 nm (a) and 55 nm (b, c) PMOS devices respectively showing the typical “inversed pyramid shape” associated to NiSi$_{2}$ formation, instead of Ni-mono silicide phase. NiSi$_{2}$ phase grows preferentially on (111) planes of Si substrate (54.6° angle oriented in the figure plan), in the smallest and p-doped Si active. Ni and W atoms are respectively colored in blue and orange in EDX mapping, presented in (c).

On Si substrates, NiSi agglomeration is usually observed at high temperatures ([41], [76]–[78], Fig. II.21a) and is the consequence of the competition between surface, grain boundary, interface, and volume energies (details will be given in subsection III.2.2.1). Some observations of severe agglomerations
have also been provided in presence of oxygen and after specific annealings (Figs. II.21a to c). On SiGe substrates, the NiSiGe agglomeration is detected at 600 °C on blanket wafers and in devices if the subsequent thermal budgets of the BEOL are not adequate (see Fig. II.21d to e, and further details could be found in section III.2.3).

<figure><img src="image_27.png" /></figure>

Figure II.21. STEM (a, d) and STEM-EDX cross-sections (b, c, e, and f) of agglomerated Ni(Pt)Si film after 1000 °C millisecond laser annealing (a to c, from [73]) and agglomerated Ni(Pt)SiGe layer after a RTA at 700 °C for 30 s (d to f, from [79]). In both cases, agglomeration induces the appearance of exposed substrate regions after the complete removal of Ni silicide layers. One may note the large segregation of As atoms on top of Si areas in b and c. Ni and Pt distributions after agglomeration are given in Figs. b, c, and e, f, respectively.

II.3.2 Shallow junctions: silicide thickness control and dopant redistribution

Down-scaling of devices dimensions induces the reduction of pn or np junction depth in active areas. Then, the silicide formation at the edge of Si active regions requires to be precisely managed to prevent a deep silicide penetration in front of the junction [80], [81]. An example of a deep penetration of silicide at the active edges leading to junction leakage is presented in Figure II. 22 (a and b). In that case, the junction and the silicide depths are similar, measured at 46 nm, along the Si/STI boundary (as STI for Shallow Trench Isolation, trenches filled by SiO₂ to ensure electrical isolation of devices from each other).

Moreover, the emergence of FD-SOI technologies deals with a critical challenge for silicide first integration. Indeed, as shown in Fig. II.22c, the final silicide thickness in such aggressive architecture should be less than 15 nm and needs to be carefully controlled to allow a suitable electrostatic control of transistors (i.e., SOI layer could not be fully silicided, and such NiSi/SiO₂ interface has to be avoided).

<figure><img src="image_28.png" /></figure>

Figure II.22. STEM-EDX cross-sections of Si active regions in the case of deep NiSi formation in front of np junction (a, b). Ni atoms are colored in yellow in b). TEM cross-section in source-drain area for 28 nm FDSOI technology
showing a 12 nm-thick Ni(Pt)Si layer under the contacts. The SOI remaining layer, measured here at 3 nm, is required
to enable device high performances.

The interaction between Ni-silicide and active dopants inside Si substrates has been intensively
studied in the literature and as explained previously, such studies appear essential for forthcoming
technologies in the context of shallow junction integrations.

On one hand, some studies have highlighted that the As was segregated at the silicide surface [67],
[82], [83]. This specific feature is attributed to the Kirkendall effect. In a metal/semiconductor system,
vacancies are exchanged with the controlled diffusing species. In the case in which the diffusing species is
the metal (as well as in the Ni-Si and Co-Si systems), vacancies will move to the metal/silicide interface.
The interface becomes a sink for vacancies and then a preferential site for the dopant segregation.

On the other hand, the dopant accumulation at the silicide/silicon interface has been observed with
arsenic [67] but also with boron [2], [82], [84]–[86]. The so called “snowplow” effect on dopants during
silicide formation (deeply described in [83]) consists of the rejection of dopant at the interface and induces
significant dopant depletion in final silicide layer and also a large dopant accumulation at silicide/silicon
interface. Consequently, even though it is difficult to estimate or model, a significant part of dopants could
not be active in semiconductor crystal matrix after silicide formation, which induces for instance a lack in
drive-in current flowing at junction boundary.

II.3.3 Reduction of Ni-systems degradations: alloying and surface preparation

For the last decades, it has been demonstrated that the addition of a small amount of an alloying
element to Ni films, such as Pt, Pd, Mo or Re, reduces the agglomeration NiSi and prevents its
transformation into NiSi₂ phase [76]. Of all the alloying elements, Pt is the most suitable, and Ni(Pt)Si
silicide is widely employed nowadays.

The introduction of Pt has been reported to increase the formation temperature of NiSi₂ phase and stabilize NiSi phase [41], [76]. Ni(Pt)-alloy silicide allows also to significantly improve the NiSi stability by achieving low junction leakage [4]. Nonetheless, Pt addition might reduce the importance of axiotaxy in NiSi compound [87] and then limit the agglomeration phenomenon.

The influence of Pt addition in solid-state reactions, final microstructure as texture, phase, and thermal
stability of Ni-based silicides and germano-silicides will be deeply analyzed and discussed in the next
chapter, based on experimental results. Then, the role of pre-amorphization using ion implantation (PAI)
on Ni(Pt)Si thermal and morphological stabilities, as already published [88]–[90], will be detailed.

To sum-up, based on my experience on Ni-Si and Ni-SiGe systems, the following figure aims to give a
comprehensive overview of the main degradations observed in real devices for such systems as a function
of Pt concentration (in present case, 0, 5, 10 and 15 at.%) and surface preparation performances
(respectively in x and y-axis in Fig. II.23).
<figure><img src="image_29.png" /></figure>

Figure II.23. Evolution of main degradation mechanisms known for Ni-silicides and Ni-germano-silicides in current planar technologies as a function of Pt alloy atomic concentration in x-axis and performances of surface preparation scheme, in y-axis. The performances in surface preparation includes wet oxide removal (based on HF diluted chemistries) and in-situ pre-clean applied prior metal deposition (in the case of Ni, the usual pre-clean is provided in SiCoNi chamber as described for instance in [91]).

### II.3.4 CoSi₂ integration limitations

For specific technologies, such as imagers or high-voltage power technologies, CoSi₂ remains commonly used as contact layer, and the most important challenges for CoSi₂ integration are similar to the ones explained for Ni silicides just before. The silicide effective resistivity is one of them and is mainly driven by the surface preparation and the O concentration inside the final CoSi₂ layer [30]. In Fig. II.24a, CoSi₂ silicide layer under contact exhibits an embedded cobalt oxide layer (determined by EDX, not shown here) linked to an inefficient surface preparation (more details will be given in Chapter IV). This high resistive layer induces locally a severe increase of contact resistance. Another impact of inefficient surface preparation can be seen in Figure II.24b.

<figure><img src="image_30.png" /></figure>

Figure II.24. TEM cross-sections CoSi₂ layer formed on the top of active regions in real device (a) and (b). An interface is detected inside the CoSi₂ film (clearer layer) leading to an increase of contact resistance (a). On STEM-EDX top-view mapping, CoSi₂ is missing under contacts (W) linked to a local oxidation of the deposited Co layer (b) [92].
In that case, due to a complete Co grain oxidation and the limited transformation in CoSi phase during the RTA1, this grain has been completely removed during the further selective etching. At the end, the STEM-EDX mapping reveals missing CoSi₂ layer under W contacts.

For those concerns, and as previously reported in Fig. II.23 for Ni and Ni(Pt) silicides, the optimization of the surface preparation allows the reduction of the CoSi₂ resistivity, as well as its thermal, and morphological instabilities [93].

Recently, higher morphological stability has been disclosed for CoSi₂ blanket layers after the introduction of specific PAI steps as cryogenic Carbon [94]. For Co silicides, PAI processes appear to be a quite robust solution to delay the agglomeration phenomenon, control the final silicide thickness and its interface roughness. As well as for Ni silicides, another remaining challenge in terms of CoSi₂ integration is the leveraging of the junction leakage in the peripheral area of actives. As reported in [95], [96], drastic improvement of the pn junction leakage current in small actives areas is measured after the introduction of Ar PAI process prior Co deposition as reproduced in Figure II.25a :

<figure><img src="image_31.png" /><figcaption>Figure II.25. Cumulative probabilities of p+/n leakage current with and without Ar PAI process for various actives spaces, measured at a reverse bias of 2.0 V at room temperature (a). TEM micrograph of the silicide formed after PAI in 0.2 µm-wide p+ actives, indicating no over silicide formation in the peripheral area, at Si/STI boundary (b) [96].</figcaption></figure>

The reduction of leakage current is related to the silicide formation inside the amorphous silicon layer during the annealing processes and the inherent smooth CoSi₂/Si interface observed by TEM (Fig. II.25b), namely at the edge of small Si areas, at Si/STI boundaries.

As reported in several papers, [25], [97]–[99], and also briefly introduced in Fig. II.9, for sub-90 nm CMOS devices, CoSi₂ silicide presents two clear limitations due to, first, its proper formation mechanism, i.e. nucleation and, secondly to the induced silicon consumption (3.6 as reported in Fig. II.9). In fact, two main parameters need to be reduced in line with the CMOS technology roadmap: the gate length and source/drain junction depth. As nucleation of the Co-disilicide during the RTA2 step, the formation of CoSi₂ at the triple junctions of CoSi phase is increasingly difficult when gate length is reduced (Fig. II.26). Moreover, for 200 mm-wafer size platforms, the integration of the up-to-date Ni silicide brick is not nowadays possible due to the unavailability of the in-situ pre-clean chamber for these wafer dimensions. As will be described mainly in Chapter IV, the plasma remote pre-clean is required for surface preparation prior Ni deposition (called SiCoNi chamber as the commercial naming from Applied Materials, [93], [100]–[106]). Based on those considerations, the integration of CoSi₂ as silicide layer for sub-90 nm CMOS or derivatives technologies could be a real necessity for 200 mm technologies and remains a great challenge even today.

At the end, as the reduction of Si consumption, the decreasing of pn junction leakage could also be achieved by an improved silicide/Si interface roughness [107]. Moreover, increasing the RTP2
temperature promotes the nucleation of the Co-disilicide grains and is found to result in improved silicide interface roughness [107]. PAI and the promotion of a hetero-epitaxy structure, based on the low mismatch between CoSi₂ and Si (100) lattice parameters, might also play a role on interface roughness (see [94]).

<figure><img src="image_32.png" /><figcaption>Figure II.26. Schematics of NiSi and CoSi₂ formations on Si substrate during the classical salicide first integration including RTA1 and RTA2 thermal budgets. Contrary to NiSi silicides which grow along the Ni₂Si/Si, CoSi₂ nuclei are formed at the triple junction points between CoSi grains and Si.</figcaption></figure>

## II.4 New advanced contacts integrations

### II.4.1 Ti-silicided contacts

3D integrations require the co-integration on the same wafer of digital up-to-date CMOS devices and imager sensors. The former presents a very thin Ni(Pt)-silicide first integration which is very sensitive to high thermal budget; the latter requests a TiSi₂ formation inside the contacts - i.e. silicide last integration - usually achieved at 800 °C, definitely higher than the agglomeration threshold temperature of Ni(Pt)Si reported for RTA annealings [41], [108], [74]. Then, one of the most important challenges remaining is to find a new path to reduce the temperature of the C49-C54 transition. Several groups have been working on the decrease in the thermal budget required to obtain the C54-TiSi₂ phase. Various methods were employed such as PAI by using Ge [110]–[112], As [113], [114], or Sb [115], [116] ions as well as the use of refractory metals either as interlayer or alloying elements [117]–[119]. One of the most promising ways, from my point of view, is the pulsed laser annealing. Several important benefits have been demonstrated with this new annealing type. First, due to its fast ramping rate and short anneal duration, nanosecond laser annealing (UV-NLA) has been found to enable the formation of smaller grains of C49-TiSi₂ than RTA, thereby increasing the density of C54-TiSi₂ nucleation sites [120]–[122]. Chen et al. have also reported that the transformation temperature into C54-TiSi₂ can be significantly reduced by pulsed laser annealing [120]. Another major advantage of the laser annealing process is the modification of the phase sequence: indeed, the C54-TiSi₂ phase can be obtained from C40-TiSi₂, by-passing the undesirable C49-TiSi₂ phase. The C40-TiSi₂ phase can thus act as a precursor of C54-TiSi₂ at lower temperatures [62], [63], [123]. Then, the impact of the UV-NLA energy density on the formation of the C54-TiSi₂ should be deeply investigated
in terms of phase sequence and kinetics of silicide formation. Our work on this specific standpoint is based
on Laura Esposito's PhD. thesis will be presented in Chapter IV.

Additionally, forming a low resistive Ti-silicide layer inside contacts after patterning demands a
precise pre-clean scheme before the Ti deposition. The first objective is the selective removal of the native
oxide at the bottom of the contact (Figs. II.27a and b). And the second one is the etching of organic residues,
induced by patterning/Reactive Ion Etching (RIE) prior steps (see Figs. II.27c and d for instance).

<figure><img src="image_33.png" /><figcaption>Figure II.27. TEM and STEM-EDX cross-sections of TiSi$_x$ contacts presenting high resistivity due to incomplete native oxide removal (a and b) or residues of RIE steps (c and d) at the bottom of the contact (from [91]).</figcaption></figure>

Moreover, such in-situ pre-clean prior Ti deposition may not increase the Critical Dimension (CD) of final W contacts. To do so, Ar-ion-bombardment are commonly used for cleaning the Si surface before Ti silicide formation [30]. Such plasma pre-clean presents some limitations as a lack of selectivity to SiO$_2$ (Fig. II.27a), and potential defects introduction in n-Si substrates [124], which degrades at the end contact resistivity. Besides, a relevant correlation with the Ar-ion-bombardment-induced damages and the Schottky barrier height has been also reported for other metal-semiconductors systems [125]. Some new approaches could then be envisioned for this specific integration, like additional SiCoNi pre-clean, as detailed in subsection IV.3.1 and here [91].

At the end, the very low Si surface (around 60-80 nm²) where the reaction diffusion will take place
presents also a challenge for the nucleation of C54-TiSi₂ phase at the triple points of the C49 one [126].

## II.4.2 Metal-Isolator-Semiconductors (MIS) contacts

As introduced in section II.1, the scaling-down of the dimension beyond 14 nm CMOS technologies
is no longer driven by the gate length shrinking but also by the distance between contact and gate, usually
named Contact Poly Pitch (CPP) (defined in Fig. II.28 from [127]). As illustrated in Fig. II.28, reducing CPP
while keeping a low contact resistivity ($ρ_c$) of 10⁻⁸ Ω·cm² would make the contact resistance a major
contribution of the total access resistance.
<figure><img src="image_34.png" /><figcaption>Figure II.28. Access resistance as a function of the Contact Poly Pitch (CPP) singling out the contribution of the contact resistance from [7], [128].</figcaption></figure>

When a metal and an n-type semiconductor are brought together, a transfer of electrons occurs at the interface to reach an electrostatic equilibrium. The direction and the magnitude of the electron flow is determined by the difference between the metal workfunction ($\Phi_m$) and that of the semiconductor ($\Phi_{sc}$). The first regime is defined $\Phi_m > \Phi_{sc}$ and called “depletion” as the electrons flow from the semiconductor into the metal. The second regime takes place if $\Phi_{sc} > \Phi_m$, leading to an electron flow from the metal into the semiconductor i.e., “accumulation” regime (Fig. II.29a and b).

<figure><img src="image_35.png" /><figcaption>Figure II.29. Simplified band diagram of a metal/n-type semiconductor contact in depletion (a) and accumulation (b) regimes; (c) and (d) represent the $\Phi_m > \Phi_{sc}$ case under respectively a negative and a positive bias (from [7]).</figcaption></figure>

In Figures II.29c and d, which both represent the case of $\Phi_m > \Phi_{sc}$, when a bias is applied to the system, the electrons need to go through the energetic barrier induced by the bending of the band diagram. While this barrier is always impeding the current when applying a negative bias on the metal, it can be overcome when applying a positive one. These contacts responses are referred to a reverse and a forward mode. These contacts are often found to be highly resistive and are called “Schottky contacts”. On the contrary, if $\Phi_{sc} > \Phi_m$, the electrons do not encounter any barrier whatever the bias is. Therefore, the contact is often found to be highly conductive and is called “ohmic contact”.

The height of the barrier induced by the band bending at the metal/semiconductor interface is named “the Schottky Barrier Height (SBH)” and is one of the major parameters to consider when trying to
optimize the contact resistance. Proposed by Schottky [129], this theory implies that the electrical behavior
of a contact can be totally tuned by choosing a metal with an adapted work function to connect a given
semiconductor. Following this theory, a high work function metal would induce a large Schottky barrier
on n-type semiconductor whereas a low work function metal would lead to a small one as formerly detailed
in Figure II.30.

<figure><img src="image_36.png" /><figcaption>Figure II.30. Semiconductors band gap on the right and ideal work function for metals usually used as contact layer with semiconductor on the left [7].</figcaption></figure>

In a real contact case, parasitic electrostatic defects distributed within the forbidden gap of the semiconductor appear at the interface. The two main interface defects are Default-Induced Gap States (DIGS) and Metal-Induced Gap States (MIGS), further details can be found in [130]. Due to the presence of these interface states, the ideal model of metal/semiconductor contacts is no longer relevant and SBHs are in practice found different from the theoretical predictions. Interestingly these effective SBHs are nearly independent from the metal work functions and are pinned around a given value depending on the considered semiconductor [131]. This phenomenon is referred to as the Fermi Level Pinning (noted FLP).

In practice, to maintain the formalism of Schottky's theory, the effective SBH is often translated into an effective metal work function as shown in Fig. II.31a. The FLP is thus represented by the effective behavior of the metal/semiconductor contacts. As presented in Fig. II.31a, the actual control of the effective metal work function can be far from what is expected. Instead of having the possibility of controlling the work function between 3 and 6 eV, the effective metal work function appears to be pinned around 4.7 eV, i.e., a mid-gap value, with only small variations around this point [132].

Due to the FLP, the effective metal work functions on metal/semiconductor contacts are almost independent from their reference value [132], hindering proper optimization of the contact resistivity. As shown in Fig. II.31 b and c, one way to mitigate the FLP could consist of inserting a very thin dielectric layer between the metal and the semiconductor [133]. This counter-intuitive approach enables a trade-off between the induced tunneling resistance, and the FLP mitigation i.e., SBH reduction, hence defining an optimal dielectric thickness around 1 nm.

Several mechanisms have been proposed to explain this effect and all seem to point out an interface states density decrease (as MIGS density). Intuitively, the propensity of the insertion to screen the plane waves from the metal is linked to its thickness. On one hand, the thicker the insertion, the lower the density of MIGS is. On the other hand, the insertion acts as a barrier for the electrons and prevents electrons flowing by tunneling effect.

Such contacts are usually called MIS (for Metal Insulator Semiconductor).
<figure><img src="image_37.png" /></figure>

Figure II.31. Effective metal work function as a function of their ideal values for common metals when contacted to Si (a), from [132]. The band diagram for a Metal-Isolator-Semiconductor contact shows free carriers to tunnel by modifying gap states at the interface (b). The optimum insulator thickness is where the gap states are effectively blocked while free carrier tunneling is still sufficient (c) [133].

Based on Ph.D work of Julien Borrel [7], the main results around the implementation of MIS contacts in real industrial environment using the materials commonly found in microelectronics industry will be presented in section IV.4

### II.4.3 III/V intermetallic contacts for photonic applications

In the present context of the Big Data era, the requirement for higher density data transmission is of the utmost importance, since the demand of data exchange has been growing for over 20 years. Innovative means of communications have inevitably emerged, such as optical devices and interconnections. The latter consists of III-V-based devices, such as emitters (laser) and receptors (photodetector) integrated onto CMOS Si-based circuitry, named Silicon photonics (Fig. II.32a). The input signal is electrical and constitutes the data that needs to be transferred. Firstly, on the transmitter, as presented in Fig. II.32a, the modulator converts the input electrical signal into an optical signal. Then, a suitable light source such as a III-V/Si hybrid laser is integrated on the silicon substrate, as presented in Fig. II.32b. One of the key components required by such integration is the development of CMOS-compatible contacts on n-InP and p-In<sub>0.53</sub>Ga<sub>0.47</sub>As layers constituting the contact layers of the III-V/Si hybrid laser (Fig. II.32b).

<figure><img src="image_38.png" /></figure>

Figure II.32. Optoelectronic circuit schematic (a). Schematic of the proposed laser structure with a zoomed-in area of the multiple quantum wells (b), from [134].

Ni and Ti thin films are then envisioned as intermetallic layers in such integrations (p and n contacts in Fig. II.32b).
For Ni-III/V systems, Appelbaum et al. have investigated the interaction of Ni with InP as a function of annealing time and temperature [135]. The results of their study suggest that in the as-deposited state, the contact is ohmic. Moreover, they also reported the study on a sputtered Ni₂P layer directly onto n-InP and p-In₀.₅₃Ga₀.₄₇As layers. Fatemi et al. have also investigated the electrical and metallurgical behavior of the Ni/n-InP system and highlighted that the Ni₃P phase is the one responsible for the low contact resistivity [136]. Ivey et al. have studied the same system and the formation of an amorphous Ni₃InP layer at the Ni/InP interface has been reported after an initial annealing [137].

In addition, the work led by Zhiou et al. on the TiN/Ni/p-In₀.₅₃Ga₀.₄₇As has reported that at a thermal budget of 300 °C the unreacted Ni is fully consumed, and the Ni₃InGaAs crystallized phase is formed, which has been transformed, after a 400 °C anneal, into the Ni₂InGaAs phase, and then into the NiAs phase after a 550 °C RTA [138].

For Ti-III/V systems, the reactions occurring between Ti thin film and the InP substrate have been described by Wang et al. [139]. An initial interaction occurred at 325 °C and metallic In and the TiP phases have been identified. Takeyama et al. have worked on the Al/Ti/n-InP system and in the as-deposited state, out-diffusion of In has been observed as well as an intermixing Ti-P layer [140]. Ghegin et al. have reported that right after Ti deposition, which had occurred at 100 °C, unreacted Ti is present as well as In, the TiP and Ti₂In₅ phases. As the RTA temperature increases, the Ti is fully consumed after a 450 °C, and at this same temperature, the Ti₂In₅ phase disappears as well, while the In and TiP phases are identified [134] [135].

The Ti/In₀.₅₃Ga₀.₄₇As system has been previously studied as well, namely by Bensalem et al. who reported the presence of a Ti-Ga-As amorphous intermixing layer right after Ti deposition and up to after a 250 °C RTA. At 250 °C, the Ti₂Ga₃ crystallized phase is formed, and at 300 °C, the TiAs₂ phase appears. The TiAs and metallic In phases only appear after a 350 °C RTA, and at this same temperature the amorphous intermixing layer is no longer observed. At 350 °C and above, the In₀.₅₃Ga₀.₄₇As layer is depleted in In and a Ga-rich InₓGa₁₋ₓAs layer appears as a result, leading to the observation of the GaAs phase (depleted of In) after a 550 °C RTA. Regarding the diffusion mechanism, the diffusing species at low thermal budget might be the Ti, while the III-V elements are the main diffusing species at higher temperatures [143].

The described state of the art is summarized in Figure II.33, from [134] including Flore Boyer's Ph.D. dissertation references.

<figure><img src="image_39.png" /><figcaption>Figure II.33. State of the art of the Ni and Ti-based contacts on n-InP a) and p-In₀.₅₃Ga₀.₄₇As b), from [134].</figcaption></figure>
The goal of Flore Boyer's PhD thesis lies in the development of innovative CMOS-compatible contacts to properly integrate the III-V/Si hybrid laser onto a 300 mm platform. In this way, the scope of our work was the study of four metallizations on n-InP and p-In<sub>0.53</sub>Ga<sub>0.47</sub>As layers (based on Ni and Ti). Specific attention has been given to the morphological stability of such ternary and quaternary systems and the emergence of agglomeration and/or delamination. It should however be highlighted that the reliability of such contacts has not been addressed before and will be investigated here. The most important results obtained on this subject will then be presented in section IV.5.

## II.5 Conclusions of Chapter II

The aim of the chapter was to give a brief overview of silicide integrations in microelectronics and the remaining challenges of Ni, Co and Ti-based silicidation processes. This background is required to deeply understand our experimental results and will be useful in the next chapters.

In Chapter III, the specific studies on the phase sequence for Ni, Ni(Pt) silicides formed on Si(100) and SiGe substrates will be summarized. A precise focus will be on the first growing phase in each system and the texture inheritance of the final silicide layer. Moreover, the influence of alloying and surface preparation scheme will be analyzed.

Chapter IV will be dedicated to the recent results on new Co integrations, as well as Ti-based contacts for 3D-BSI imagers technologies. In addition, in the second part of this chapter, the work on innovative contacts based on Metal Isolator Semiconductor (MIS) integration and on III/V layers stacking will be introduced.

Based on all experimental results and further discussions, I will present my research project in Chapter V and detail the main objectives and needs for salicide first integration and innovative contacts including Ti-based ones.
CHAPTER III

Ni and Ni(Pt) silicides formation on Si and SiGe
substrates

Abstract

In this chapter, the specific studies on the phase sequence identification for Ni, Ni(Pt) silicides formed on Si(100) and SiGe substrates will be presented. The role of pre-amorphization, surface preparation, Pt addition, dopant segregation, and redistribution will then be addressed and discussed in detail. A specific focus will be on the first grown phase for each system and the texture inheritance of the final silicide layer. The change in the phase sequence, compared to blanket films, observed through XRD performed at ESRF in confined structures will also be introduced. At the end, a specific highlight will be given on the change in degradation mechanisms known in the real microelectronics devices, namely abnormal Ni diffusion, NiSi, and NiSiGe agglomeration and NiSi₂ formation. The conclusions of this chapter will then provide the guidelines for significant improvement of current and future silicide technologies, in the case of silicide first integration.
Table of Contents

<table><tr><td>III.1</td><td>Introduction</td><td>47</td></tr><tr><td>III.2</td><td>Ni<sub>1-w</sub>Pt<sub>w</sub> (0&lt;w&lt;0.15)-Si system</td><td>48</td></tr><tr><td>III.2.1</td><td>Influence of Pt addition on Ni silicides phase sequence</td><td>48</td></tr><tr><td>III.2.2</td><td>Kinetics study of Ni(10 at.% Pt)-Si solid state reactions</td><td>56</td></tr><tr><td>III.2.3</td><td>Influence of dopants on Ni(Pt)Si silicide formation</td><td>58</td></tr><tr><td>III.2.4</td><td>Benefits of pre-amorphization by implantation</td><td>71</td></tr><tr><td>III.3</td><td>Ni<sub>1-w</sub>Pt<sub>w</sub> (0&lt;w&lt;0.15)-Si<sub>0.7</sub>Ge<sub>0.3</sub> system</td><td>75</td></tr><tr><td>III.3.1</td><td>Impact of Pt addition on Ni-germano-silicides phase sequence</td><td>76</td></tr><tr><td>III.3.2</td><td>Kinetics study of Ni(10 at.% Pt)/Si<sub>0.7</sub>Ge<sub>0.3</sub> solid state reactions</td><td>91</td></tr><tr><td>III.4</td><td>Formation of Ni(Pt)-silicide and germano-silicide in nanoscale dimensions</td><td>94</td></tr><tr><td>III.4.1</td><td>APT analyses in source/drain and gate of CMOS devices</td><td>94</td></tr><tr><td>III.4.2</td><td>Change in phase sequence in nanoscale structures for Ni(Pt 10 at.%)-Si</td><td>98</td></tr><tr><td>III.4.3</td><td>Change in phase sequence in nanoscale structures for Ni(Pt 15 at.%)-SiGe</td><td>101</td></tr><tr><td>III.5</td><td>Agglomeration of Ni-silicides and germano-silicides thin films</td><td>104</td></tr><tr><td>III.5.1</td><td>Solid-state reactions of dewetting in thin films</td><td>104</td></tr><tr><td>III.5.2</td><td>Early agglomeration for 28 nm FDSOI technology: grain size and silicide thickness</td><td>107</td></tr><tr><td>III.5.3</td><td>Ni(Pt)SiGe thermal stability for Ni<sub>1-w</sub>Pt<sub>w</sub> (0&lt;w&lt;0.15) alloys</td><td>109</td></tr><tr><td>III.6</td><td>Conclusions of Chapter III</td><td>117</td></tr></table>
## III.1 Introduction

For planar microelectronic technologies, the silicide first integration scheme related to a silicide formation at the upper surface of all active regions (gates, sources and drains) is required, as previously introduced [144]. This process sequence includes two annealing steps and a removal of unreacted metal after the first one. Several parameters can be precisely adjusted to match the requirements for device performance and reliability, such as: silicide thickness (in terms of substrate consumption), resistivity, thermal stability (linked to agglomeration, abnormal diffusion and high-resistive phase formation [37][41][132][4][66]), stress and, at the end, uniform silicide formation in the small devices and large areas [33][34].

The microstructure, grain size and texture of a thin film predominantly determine its thermal stability and the mechanical/electrical properties. Then, understanding and controlling the final silicide microstructure is of great interest from fundamental research and application perspectives. For Ni-based silicide, it has been reported that the introduction of Pt delays the formation temperature of NiSi₂ and stabilizes NiSi phase [146][76]. Ni(Pt) alloy silicide was demonstrated to significantly improve the NiSi stability by achieving low junction leakage even at high temperatures [147]. In this context, Pt addition was reported to reduce the importance of axiotaxy in NiSi material [87].

Several questions could arise. Does Pt atomic concentration affect the phase sequence during the Ni silicide formation and how? Is the observed improvement in NiSi stability induced by Pt addition linked to a change in the final microstructure/texture of the silicide layer? Moreover, could Pt induce an epitaxial or an hetero-epitaxial growth of NiSi on the Si(100) or SiGe substrates? Indeed if NiSi film can be grown with an epitaxial relationship on different substrates, the thermal endurance and stability will be then drastically improved [148][40][108][149].

Recently, the mechanism of texture inheritance during the phase sequence has been reported by F. Geenen et al. [138][139]. The latter effect succeeds in explaining the occurrence of specific epitaxial and fiber textures through a transformation of the preceding phases. To determine the potential impact of Pt on the final silicide microstructure and more globally on silicide process, the phase sequence formation of Ni(Pt)-based silicide has been deeply studied, as presented in sections II.2 and II.3.

Another major aspect is the influence of dopant species on Ni(Pt)Si formation and final properties of the silicide layer. Then, this is needed to clearly identify the potential failures or changes in real devices where heavily doped n+ and p+ regions are present [152]. In this chapter, the experimental results on phosphorus and arsenic doped Si substrates will be presented.

Moreover, the silicide/substrate interface roughness plays a major role on the degradation of junction leakages [153] and silicide agglomeration [154]. An epitaxial texture of the silicide layer can drastically reduce the agglomeration phenomenon. Amorphization of Si substrate by PAI prior metal deposition [155] has been studied to estimate the potential improvement on electrical silicide properties and agglomeration delay.

In the end, Ni(Pt) silicides or germanides formation in nanometric features remains misunderstood. A specific work based on advanced characterizations such as Atom Probe Tomography (APT) was performed at IM2NP Marseille and synchrotron XRD analyses (ESRF, SOLEIL). Most of it will be depicted in section III.4 and, as we will see, are opening interesting perspectives.
### III.2 Ni$_{1-w}$Pt$_{w}$ ($0<w<0.15$)-Si system

Before describing the Ni$_{1-w}$Pt$_{w}$ ($0<w<0.15$)-Si system, preliminary general remarks need to be made. Firstly, the Pt concentration in this section is always given as the Pt atomic concentration included in the Ni(Pt) alloy of the sputtered target used during the physical vapor deposition of thin metal film. In our studies, four types of alloys are evaluated, namely Ni pure, Ni(5 at.% Pt), Ni(10 at.% Pt), and Ni(15 at.% Pt), which are widely used in microelectronics [37].

Nevertheless, the real Pt concentration inside the deposited NiPt film is less than the one measured inside the metal target. The Pt concentrations inside NiPt films measured by several different techniques are summarized in Table III.1

<table><caption>Table III.1. Pt concentration in atomic percent measured by Rutherford Backscattering Spectrometry (RBS), Time-of-Flight Secondary Ion Mass Spectrometry (ToF-SIMS) and Atom Probe Tomography (APT) techniques in the NiPt layer after physical deposition on SiO$_{2}$ layer.</caption><thead><tr><th rowspan="2">NiPt alloys</th><th colspan="3">Pt concentration (at.%) measured by</th></tr><tr><th>RBS</th><th>ToF-SIMS</th><th>APT</th></tr></thead><tbody><tr><td>Ni(5 at. % Pt)</td><td>3.6 ± 0.3 at.%</td><td>3.5 ± 0.4 at.%</td><td>3.5 ± 0.3 at.%</td></tr><tr><td>Ni(10 at. % Pt)</td><td>8.1 ± 0.3 at.%</td><td>8.4 ± 0.4 at.%</td><td>8 ± 0.3 at.%</td></tr><tr><td>Ni(15 at. % Pt)</td><td>14 ± 0.3 at.%</td><td>-</td><td>-</td></tr></tbody></table>

The effective Pt concentrations displayed in Table II.1 will be included in the lattice parameters calculations in the next sections. Moreover, Pt can decrease the grain size and change the texture of the deposited NiPt layer; both of which can change the NiPt intrinsic resistivity. Following Nordheim's rules, alloy addition in a solid solution increases the film resistivity by adding scattering contribution in the overall resistivity.

Secondly, in the following pages, some discrepancy between experimental results may be explained by the slight changes induced by the presence of a TiN capping layer on top of the NiPt film during annealing, as well as the addition of the Selective Etching (SE) step after first Rapid Thermal Annealing (RTA1). Consequently, a complete description of the samples is provided in the figure captions. Several differences can already be pointed out since the silicide first process including two RTA and a SE step appears different to the in-situ Rs or XRD measurements. Indeed, RTA are really fast (less than 1 min) and RTA1 is always performed on a NiPt/TiN stack in contrary to, for example, the in-situ θ-2θ XRD analyses which represent an annealing of several hours and are most of the time performed on uncapped NiPt layer. As an example, selective etching is needed for ex-situ Rs measurements and is not added for the in-situ one.

#### III.2.1 Influence of Pt addition on Ni silicides phase sequence

Among all the alloying elements, Pt is the most effective, and Ni(Pt)Si with a high Pt concentration (10 at.%) is currently employed as a contact layer in state-of-the-art microelectronic devices.
Extensive work has been undertaken to determine the effects of alloying elements and their redistribution on the stability [41], [23], formation kinetics and phase sequence of Ni silicide growth [41], [149], [157]. For pure Ni, early studies reported the sequential formation of δ-Ni₂Si and NiSi at low temperature. Recently, it was found that θ-Ni₂Si grows as a transient phase in coexistence with δ-Ni₂Si [158], although this phase is metastable below 825 °C, based on the binary phase diagram of Ni-Si system (Table II.1 and Figure II.14). Moreover, it has been reported in a few cases that θ-Ni₂Si forms as the first phase [108], [159], substituting δ-Ni₂Si in the phase sequence for NiPt alloy deposition. The first case is for a high Pt concentration (> 13 at.%) in a 35 nm thick Ni film; the second is a very thin pure Ni film (< 4 nm). In the first case [159], the authors claim that there is an effect of Pt inducing the stabilization of the phase at low temperature; in the second case [108], the authors show that Ni is completely mixed with Si immediately after deposition, and suggest that this intermixing layer induces the nucleation of the non-stoichiometric phase.

This section is devoted to giving a specific insight on the change induced in the phase sequence and silicide microstructure by modifying the amount of Pt based on ex-situ and in-situ analyses.

### III.2.1.1 θ-Ni₂Si phase as the first phase to grow for Ni(10 at.% Pt)-Si(100)

In this work, reported in [160] and deeply described in the Ph.D. dissertation of Federico Panciera [5], Ni and Ni(10 at.% Pt) were deposited on Si(100) substrates. The substrate surface was cleaned with a diluted HF solution, followed by chemical plasma based of NH₃ and NF₃ gazes (SiCoNi pre-clean).

In Figure III.1, the reaction of the Ni or NiPt layer with the Si substrate were analyzed by in-situ θ-2θ XRD based on Bragg-Brentano geometry using the Cu Kα ray, which corresponds to an x-ray wavelength of 1.5406 Å.

<figure><img src="image_40.png" /><figcaption>Figure III.1. In-situ θ-2θ XRD diagrams during annealing of an 11 nm Ni (a) and Ni(10 at.% Pt) (b) deposited on a Si(100) substrate without TiN capping. The heat ramp is 1.2 °C per min from 150 to 400 °C.</figcaption></figure>

For the pure Ni, the in-situ XRD experiments are in accordance with the usual sequence of silicide formation observed for similar Ni thicknesses [158]. The δ-Ni₂Si starts to grow at 200 °C and its growth continues until all the Ni is consumed (around 250 °C). Only one diffraction peak is observed for Ni at 44.5° indicating a (111) fiber texture. The diffraction peaks attributed to δ-Ni₂Si phase are respectively
at 45° and 48.5° related to (211) and (020) planes. A different phase, which is certainly θ-Ni₂Si, appears and disappears rapidly around 310 °C, while the beginning of the NiSi growth coincides with the fast consumption of θ-Ni₂Si and is followed by a slower consumption of δ-Ni₂Si. The identified planes of θ-Ni₂Si phase for a 2θ angle of 47° is (110) and for NiSi both (020) and (211) are detected at 56° and 46.5° respectively. As detailed in Annex, the NiSi 020 peak could also be indexed with the 013 one, due to the extremely low difference in inter-planar distances d$_{hkl}$ (as 1.67 Å for (020) and 1.65 Å for (013)).

For the Ni(10 at.% Pt), as displayed in Fig. III.1b, the phase sequence is different. Firstly, the Ni(Pt) peak shifts from 44.5 to 44°. The Ni(111) peak position changes as a function of Pt concentration because of the presence of Pt, which induces an enlargement of d$_{hkl}$ distance which gives, by applying the Bragg's law, a lower 2θ value (as observed here). The shift in the Ni(Pt) peak position corresponds to an increase of d$_{111}$ from 2.03 Å to 2.052 Å. In the cubic face centered system, this change is related to a widening of the lattice parameter, a, from 3.52 Å for pure Ni crystal to 3.554 Å for Ni(Pt) one. To confirm this point, the effective Pt concentration, w, in the Ni(Pt) alloying layer, can be deduced from the Vegard's law [161]:

$$a_{NiPt} = w \times a_{Pt} + (1 - w) \times a_{Ni} \qquad \text{Eq. III.1}$$

where $a_{NiPt}$, $a_{Pt}$ and $a_{Ni}$ are respectively the lattice parameter of Ni$_{1-w}$Pt$_w$, Pt and Ni films.

One can notice that this law is strictly valid in the absence of stress.

At low temperatures, the extracted $a_{NiPt}$ from the in-situ XRD measurements is then obtained by the addition of 8.5 at.% of Platinum in the Ni layer, in a good agreement with the measured value after deposition reported in Table III.1.

In Figure III.1b, the NiPt film is consumed at a lower temperature (225 °C vs 250 °C) than the pure Ni one and the mono-silicide phase grows more rapidly and at a lower temperature than for the pure Ni (260 °C vs 310 °C). The Ni(Pt)Si phase presents a strong (020) texture compared to the pure Ni sample. The consumption of the metal should correspond to the growth of a phase; however, no XRD peak is visible in the temperature range between 220 and 260 °C.

The absence of an XRD peak could indicate the formation of either an amorphous (or small grained) phase or a highly textured phase presenting XRD peaks that cannot be measured in the Bragg-Brentano geometry used during this experiment.

To clarify this point, another in-situ XRD experiment is performed under the same conditions and stopped at 220 °C. This temperature is chosen to ensure that some unreacted Ni(Pt) film remains. The identification of the first phase to grow is therefore provided by APT, TEM, HAADF-STEM, and HRTEM measurements.

APT analyses were conducted on this sample by Federico Panciera at IM2NP in a LEAP 3000X HR instrument in laser mode. Data reconstruction was done with IVAS software. The evaporation field, the field factor and the image compression factor are set to 28, 3.3 and 1.65 V.nm⁻¹, respectively. The APT specimens are shaped as a sharp tip by Focused Ion Beam (FIB) using the standard lift-out techniques, after the deposition of a Cr protection layer by sputtering [162].

The reconstructed volume is shown in Figure III.2a, where each point corresponds to an atom of Ni, Pt, Si or Cr. A 1D profile (Fig. III.2b) is calculated using the portion of the 3D volume represented
by the cylinder drawn in Figure III.2a. This allowed us to distinguish two zones, in addition to the Cr protective layer and the Si substrate. The first zone between 2 and 6 nm corresponds to the unreacted metal layer: the concentration of Pt in this zone is like the measured value inside the as-deposited film (Table III.1). This indicates that Pt is not rejected from the silicide to the metal layer, in contrast to what is usually observed during the reaction of Ni(Pt) film with Si [157]. The second zone corresponds to silicide since both Ni and Si are present. The Si concentration varies from 25 to 42 at.% within this zone and the Pt concentration close to the unreacted metal reaches 20 at.%. The high concentration of Pt in the silicide phase is also in contrast with what is generally observed [157] and confirms the absence of Pt rejection from the metal film. This observation allows us to conclude that the shift of Ni(Pt) peak diffraction measured during the in-situ XRD analyses is not induced by an Pt enrichment of the metal layer but mainly by a stress relaxation occurring between 200 and 225 °C.

This zone corresponds to a non-stoichiometric Ni-silicide with a gradient of Si and a non-uniform distribution of Pt. The only Ni-silicide with these characteristics is the θ-Ni₂Si phase as highlighted in subsection II.2.1. Nevertheless, the Si concentration gradient is not exactly aligned with the expected one in the θ-Ni₂Si phase. The Si concentration is lower than 33 at.% near the metal/silicide interface. Figure III.2a also shows that the silicide is characterized by sharp interfaces, especially with the Si substrate. No grain boundary (i.e., no preferential segregation or change in atomic density that usually denotes a grain boundary) could be found either in the reconstructed volume or in several other APT volumes, suggesting that the silicide has large grains.

<figure><img src="image_41.png" /><figcaption>Figure III.2. Reconstructed 3D volume of the APT analysis of an 11 nm Ni(10 at.% Pt) sample annealed up to 220 °C: Ni, Pt, Si and Cr atoms are represented respectively as green, blue, grey and pink dots (a). One-dimensional concentration profiles calculated through the cylinder shown in (a) (b) [160].</figcaption></figure>

Conventional and High-Resolution TEM (HR-TEM) analyses were performed on the same sample using an FEI Titan and an FEI Tecnai G20 (Figs. III.3a and b). As shown in Figs. III.3a and b, the cross-section micrographs confirm a very flat NiPt-silicide/Si interface. The HR-TEM image in Figure III.3b shows that the silicide lattice planes present a hexagonal symmetry. At the interface between the silicide layer and Si substrate, the silicide planes perpendicular to the interface are aligned with the Si (110) substrate planes.

Fast Fourier Transform (FFT) of selected areas in the silicide layer (Fig. III.3c) and the Si substrate (Fig. III.3d) were used to identify and compare the orientations of the silicide and the
substrate. A clear hexagonal structure was then detected. The distances between the transmitted beam and the spots labelled 1, 2 and 3 in Figure III.3c give the following values for inter-planar spacings: $d_1 = 1.96 \pm 0.04$ Å, $d_2 = 1.14 \pm 0.02$ Å and $d_3 = 1.98 \pm 0.04$ Å; the angles are $\alpha = 61^\circ \pm 1^\circ$ and $\beta = 31^\circ \pm 1^\circ$. These measurements are consistent with the diffraction patterns obtained for the $\theta$-Ni$_2$Si phase only. The three diffraction spots correspond respectively to:

- Spot 1 : (11-20) planes perpendicular to the interface $\theta$-Ni$_2$Si/Si

- Spot 2 : (2-1-10) planes

- Spot 3 : (3-300) planes parallel to the interface $\theta$-Ni$_2$Si/Si

Furthermore, by comparing the FFT obtained in the silicide (Fig. III.3c) and in the Si substrate (Fig. III.3d), the (11-20) and (3-300) $\theta$-Ni$_2$Si are aligned respectively with (220) and (004) Si ones. This strongly suggests an epitaxial relationship between the $\theta$-Ni$_2$Si phase and the Si substrate.

<figure><img src="image_42.png" /><figcaption>Figure III.3. TEM micrograph of the 220 °C annealed Ni(10 at.% Pt) sample observed in cross-section along a <110> Si direction (a); HRTEM image in the NiPt-silicide/Si interface region (b); FFT of the framed zone in the silicide layer (c); FFT of the Si substrate (d) from [160].</figcaption></figure>

The SAED (for Selective Area Electron Diffraction) patterns, displayed in Figure III.4, obtained in plan-view, exhibits the recognizable 4-fold symmetry characteristics of the Si viewed along the <100> axis. Concentric diffraction rings are also distinguishable and correspond to the fiber texture of unreacted NiPt film.

Other isolated weak reflections, which cannot be attributed to the Si, are also visible in the SAED patterns (red and green circles in Fig. III.4b). The isolated spots form a 4-fold symmetrical pattern, superimposed on the spots coming from the Si substrate. Two families can be identified depending on their distance to the transmitted beam. The spots labelled 1 (red circles) and 2 (green circles) in Figure III.4b correspond to inter-planar distances $d$ respectively of $1.02 \pm 0.02$ Å and $1.19 \pm 0.03$ Å and. Spots 1 are aligned with the reflections 220 of the Si substrate. The angle between the closest type 1 and type 2 reflections is $32.0 \pm 0.5^\circ$ and the angle between two neighboring type 2 reflections is $26.0 \pm 0.5^\circ$.
According to the data available in the literature [163] for the various Ni silicides, all the observed isolated spots can be attributed to the θ-Ni₂Si phase. The type 1 and type 2 spots result from the diffraction of the (0004) and {114} planes of θ-Ni₂Si. Nevertheless, the unique reflection of (0004) and {114} planes could not explain the observed SAED patterns. In fact, in a hexagonal structure, the (0004) planes cannot be perpendicular to each other because only one <001> direction exists (spot 1 in red). Two epitaxial relationships are needed to reproduce properly the SAED patterns, rotated by 90° to each other (Fig. III.4c). In details, in Figure III.4c, the black circles correspond to the diffraction spots of Si substrate, the red and blue squares to the θ-Ni₂Si ones. Then the obtained SAED patterns constituted by the type 1 and type 2 spots can be reproduced by the superimposition of two SAED patterns of the θ-Ni₂Si phase, viewed along [1-10] as presented in Figure III.4c.

<figure><img src="image_43.png" /><figcaption>Figure III.4. SAED patterns obtained by TEM on the 220 °C annealed Ni(10 at.% Pt) sample in plan-view along <001> direction (a). Indexes of Si reflections (white crosses), and marks surrounding (green and red) the additional isolated spots, related to the θ-Ni₂Si phase, are superimposed on the magnified center part of the SAED patterns (b). Crystallographic orientation relations between the two identified variants of θ-Ni₂Si (rotated of 90°) and the Si(100) substrate deduced from the TEM analyses in plan-view (c) [160].</figcaption></figure>

The θ-Ni₂Si grains are thus in epitaxy on the substrate according to the following crystallographic relations: {11-10} θ-Ni₂Si parallel to {110} Si and (0001) θ-Ni₂Si parallel to {110} Si. Obviously, considering that the surface of the Si(100) substrate shows a 4-fold symmetry (i.e., it contains two perpendicular and equivalent <110> directions), the grains of θ-Ni₂Si may reasonably adopt two orientations, rotated by 90° to each other. The relation of epitaxy deduced from the FFTs (Fig. III.3) is, in agreement, with the crystallographic relations obtained through SAED analyses.

However, this epitaxial relation is different from what was reported in a previous paper regarding θ-Ni₂Si formation from an amorphous Ni-Si mixture [40]. Our results show that θ-Ni₂Si grows as the first phase by the reaction between 11 nm of Ni(10 at.% Pt) with the (100)Si substrate.
Firstly, APT shows that the first growing phase is non-stoichiometric (in the Ni–Si and Pt–Si binary systems, only the θ-Ni₂Si phase shows a large non-stoichiometry) and has a composition matching with θ-Ni₂Si phase. Nonetheless, the composition range of the binary θ-Ni₂Si phase (33–42 at.%) is less than that observed in Figure III.2 (25–42 at.%). This might be due to an extended deviation of the stoichiometry due to the presence of Pt. The TEM observations, both in plan-view and in cross-section, are also in accordance with the presence of the θ-Ni₂Si phase. They also show that this phase is in epitaxy with the Si substrate, with two possible variants. The epitaxial relationships, (11-20) θ-Ni₂Si // (110)Si and (0001) θ-Ni₂Si // (1-10)Si, are compatible with the absence of the XRD peak since the theoretical (1-100) XRD peak intensity is low (less than 5% in relative intensity), and the film is very thin. The formation of θ-Ni₂Si as the first phase is not expected since this phase is metastable in the binary Ni–Si system. This might be due to stabilization by epitaxy, which decreases the interfacial energy. Another explanation could be the stabilization of the θ-Ni₂Si phase in the ternary Ni–Pt–Si phase diagram. In fact, the large incorporation of Pt in θ-Ni₂Si (Fig. III.2b) contrasts with the usual snow-plow effect during δ-Ni₂Si growth [152][83] and it suggests of a high solubility of Pt in θ-Ni₂Si. This high solubility could be a stabilization factor for θ-Ni₂Si in the ternary phase diagram. At the end, Figure III.1 shows that the kinetics of formation of θ-Ni₂Si in the presence of 10 at.% Pt is faster than that of δ-Ni₂Si for pure Ni. This difference of kinetics may also contribute to the formation of θ-Ni₂Si as the first phase.

To conclude, during the heat treatment of a 11 nm Ni(10 at.% Pt) film on an Si(100) substrate, in-situ XRD, APT, HRTEM and SAED analyses confirm that the first phase to form in this system is θ-Ni₂Si and that this phase grows in epitaxy on (100)Si substrate with two variants of the epitaxial relationship: (11-20) θ-Ni₂Si // (110)Si and (0001) θ-Ni₂Si // (1-10)Si.

### III.2.1.2 Ni(Pt)Si phase characteristics for Ni(10 at.% Pt) and Ni(15 at.% Pt) on Si(100)

The final phase formed for the Ni(10 at.% Pt)-Si system is then analyzed by APT on a similar sample after a complete in-situ XRD experiments up to 400 °C.

Figure III.5 shows the 1D concentration profiles of Ni, Si and Pt obtained in the reconstructed volume. The silicide in presence is clearly the mono-silicide one and the Si concentration is equal to 50 at.%, as expected, and is uniform inside the Ni(Pt)Si layer. The mono-silicide is thus stoichiometric against the Si concentration. Inside the silicide layer, the Pt and Ni profiles are inverse to each other, and the sum of both metal contributions is equal to 50 at.%. Here, Pt atoms substitute to the Ni atoms in the metal sublattice. The Pt concentration reaches a maximum near the top surface - measured at 12 at.% -, slows down gradually inside the silicide layer and finally increases again near the silicide/Si interface. This Pt profile might be linked to a low diffusion of Pt in Ni(Pt)Si layer and an interface segregation at silicide/Si interface.

The important point here is that the Pt profile observed in the case of Ni(10 at.% Pt) layer is strictly different from the ones reported in the literature for lower Pt concentrations. Indeed, after RTA2 for Ni(5 at.% Pt) the Pt concentration reaches a maximum in the middle of the Ni(Pt)Si layer linked to a higher diffusion in δ-Ni₂Si than in NiSi phase [2] [83]. The main change in the phase sequence induces by 10 at.% Pt addition is the appearance of the θ-Ni₂Si as the first formed phase and the unique one. One can then assume that the knowledge of Pt distribution inside the final silicide layer is clearly the consequence of phase sequence formation.
<figure><img src="image_44.png" /><figcaption>Figure III.5. One-dimensional concentration profiles calculated through a reconstructed 3D volume of the APT analysis of an 11 nm Ni(10 at.% Pt) sample annealed up to 400 °C during in-situ XRD analyses.</figcaption></figure>

The silicide thickness is 29 nm and is higher by several nanometers than the one measured in the real silicide integration: this might be related to the absence of selective etching process.

In addition, blanket wafers are fabricated following the standard 14 nm FD-SOI process flow up to silicide formation and SiN encapsulation. Ni(Pt)Si silicide is formed by reaction of Ni(10 at.% Pt) or Ni(15 at.% Pt) films with Si on a FD-SOI substrates. After NiPt deposition, two RTA1 thermal budgets have been studied either 230 °C or 260 °C during 30 s before selective etching. A second RTA is then carried out to form Ni(Pt)Si phase. Orientation mappings were obtained using the ASTAR™ system on a TEM (known as ACOM-TEM for Automated Crystal Orientation Mapping) and resulting data are exported to MTEX for texture analyses [165]. ToF-SIMS profiles in the same zone enable us to determine the Pt profiles inside the silicide layer for the different studied conditions.

<figure><img src="image_45.png" /><figcaption>Figure III.6. ASTAR™ mappings of Ni(Pt)Si grains formed after Ni(10 at.% Pt) (a, b) and Ni(15 at.% Pt)(c, d) reaction with Si on a FD-SOI substrates. Si[001] and [101] directions are colored respectively in red and green as described in the color map (e). The Ni(Pt)Si grains orientations are colored following the color map in (f).</figcaption></figure>

As presented in Fig. III.6, for Ni(10 at.% Pt) films, two orientations are observed parallel to [001] Si direction whatever the RTA1 thermal budgets. In Figure III.6b, Ni(Pt)Si layer thickness increases with RTA1 temperature, but texture does not change. These orientations are respectively indexed as (010), in blue, and (013), in pink, parallel to (001) substrate planes. For Ni(15 at.% Pt) alloys, the silicide layer is very thin around 8 nm for low RTA1 temperature (Fig. III.6c). We estimate that the layer is too thin to extract with a good accuracy the grain orientation with a good accuracy.
Nevertheless, at higher RTA1 temperature, the silicide thickness rises 10 nm, and the grains can be correctly indexed; No preferred orientation is determined here (Fig. III.6d), contrary to the Ni(10 at.% Pt) sample.

Based on ACOM-TEM analyses after RTA2, the texture observed for Ni(10 at.% Pt) and Ni(15 at.% Pt)-Si systems could be summarized as follows :

- For Ni(10 at.% Pt), the fiber texture is made of an alignment of (013) and (010) Ni(Pt)Si grains on Si (001) planes with a good agreement with the in-situ XRD results shown in Figure III.1.

- For Ni(15 at.% Pt), a random texture is observed.

### III.2.2 Kinetics study of Ni(10 at.% Pt)-Si solid state reactions

The aim of this section is to give an estimation of the activation energies related to the Ni consumption, θ-Ni₂Si and NiSi formation during the reaction of Ni(10 at.% Pt) film with Si(100) substrate.

#### III.2.2.1 Apparent activation energies of θ-Ni₂Si phase formation

During in-situ XRD experiments (as shown in Fig. III.1), at specific temperatures, the XRD peaks intensity of phases in presence are measured during isothermal annealings and then plotted as a function of time.

To determine the activation energy of θ-Ni₂Si phase formation, the NiPt(111) XRD peak intensity is plotted as a function of time for the subsequent temperatures: 50, 180, 200 and 230 °C. The θ-Ni₂Si phase is assumed to be the only phase formed during the Ni consumption. NiPt(111) XRD peaks are fitted with a pseudo-Voigt curve. Integrated intensity has been calculated and plotted as a function of temperature and time (not shown here).

The growth regime of θ-Ni₂Si can also be estimated by finite difference modeling of the XRD peak area evolution as a function of temperature. As reported in [45], θ-Ni₂Si growth is expected to be limited by diffusion and interface reaction. The parabolic and the linear-parabolic models depict two kinds of growth which are applied here to determine the kinetic parameters.

$$ \text{Parabolic model: } \frac{dx}{dt} = \frac{\alpha D}{x} \qquad \text{Eq. III.2} $$

$$ \text{Linear-parabolic model: } \frac{dx}{dt} = \alpha \frac{KD}{D+Kx} \qquad \text{Eq. III.3} $$

where x is the thickness of the growing phase; t, the time; α, the coefficient depending on the formation enthalpy and phase parameters; D, the diffusion coefficient and K the interface reaction coefficient which can be expressed with an Arrhenius law as:
$$D = D_0 \exp \left( - \frac{E_{a1}}{k_B T} \right) \qquad \text{Eq. III.4}$$

$$K = K_0 \exp \left( - \frac{E_{a2}}{k_B T} \right) \qquad \text{Eq. III. 5}$$

where $D_0$ and $K_0$ are the exponential pre-factors, $E_{a1}$ the activation energy of diffusion, $E_{a2}$ the activation energy of interface reaction, T the temperature and $k_B$ the Boltzmann constant (1.38064852 E-23 J·K⁻¹).

The linear-parabolic law was first tried but did not give better fit than a pure parabolic growth in that case. We thus used a parabolic law to fit the experimental results. The parabolic model and experimental curves show a good agreement until 230 °C. The average results are presented in Table III.2 and compared to the reported values in literature for Ni-Si [43] and Ni(5 at.% Pt)-Si [83]. All the details of these simulations are given in F. Panciera's Ph. D dissertation [5].

<table><caption>Table III.2. Kinetic constants estimated from XRD experiments associated to the θ-Ni₂Si growth in the Ni(10 at.% Pt)-Si system. The model used for simulations is a parabolic one related to diffusion mechanism. The results of this work are thus compared to the ones obtained in literature for the δ-Ni₂Si phase for Ni(5 at.% Pt)-Si [83] and Ni-Si systems [43].</caption><thead><tr><th>System</th><th>First phase to grow</th><th>D<sub>0</sub> Exponential pre-factor (cm<sup>2</sup>/s)</th><th>E<sub>a1</sub> Activation energy (eV)</th></tr></thead><tbody><tr><td>Ni(10 at. % Pt)-Si</td><td>θ-Ni<sub>2</sub>Si</td><td>0.2</td><td>1.3</td></tr><tr><td>Ni(5 at. % Pt)-Si</td><td>δ-Ni<sub>2</sub>Si</td><td>1</td><td>1.55</td></tr><tr><td>Ni-Si</td><td>δ-Ni<sub>2</sub>Si</td><td>1.5</td><td>1.5</td></tr></tbody></table>

Thus, the $D_0$ exponential pre-factor is estimated at 0.21 cm²/s and activation energy $E_{a1}$ at 1.3 eV. The error on the exponential pre-factor and on the activation energy is estimated to be around 1 cm²/s and 0.1 eV respectively.

The comparison of the kinetics values shows that the addition of 5 at.% of Pt induces a slow-down of the formation kinetic of δ-Ni₂Si phase compared to the Ni pure system. However, the addition of 10 at.% of Pt induces a faster θ-Ni₂Si formation than δ-Ni₂Si one. This conclusion is quite surprising because, as presented before, the θ-Ni₂Si grows in epitaxy with the substrate and the grain size is drastically large for this phase (estimated to be larger than 10 µm, see for instance Fig. III.3a). At that point, the diffusion at grain boundaries should be low and the predominant diffusion path would be the volume diffusion. But as reported in [166], the volume diffusion is generally lower than the diffusion occurring at grain boundaries.

One potential explanation of the lower activation energy, observed for θ-Ni₂Si here, can be the concentration gradient inside the phase itself, which might be correlated to higher vacancies density and thus promotes a faster diffusion of Ni.

<footnote>*Ea is given in eV as 1eV is equal to 1.60217565E-19 J.</footnote>
### III.2.2.2 Apparent activation energies of NiSi phase formation

In order to extract the activation energies for the mono-silicide phase formation, the latent time $\tau$ between the end of Ni consumption and the appearance of NiSi phase is determined through isothermal XRD experiments for the given temperatures: 90 h at 180 °C, 11.5 h at 200 °C and 1 h at 230 °C. This delay is clearly influenced by temperature. The Arrhenius diagrams are shown in the Figure III.7 for the Ni(10 at.% Pt)-Si system (this study) and then compared to the reported results for Ni and Ni(5 at.% Pt)-Si systems [67]. The inverse of the latent time $\tau$ (in hours) is expressed as a function of the inverse of temperature (multiplied by the Boltzmann constant) as follows:

<figure><img src="image_46.png" /><figcaption>Figure III.7. Arrhenius diagrams related to the mono-silicide phase for the Ni(10 at.% Pt)-Si system, and compared to the results reported in literature for pure Ni and Ni(5 at.% Pt)-Si systems [67].</figcaption></figure>

The activation energies for the three systems are respectively: 1.2 eV for pure Ni, 1.7 eV for Ni(5 at.% Pt) and 1.8 eV for Ni(10 at.% Pt). The high activation energy measured here for Ni(10 at.% Pt) could be explained, as reported in [5], by the stress relaxation inside the θ-Ni₂Si at the first stages of the NiSi formation. Thus, the predominant mechanism inducing stress mitigation would be the Si diffusion inside θ-Ni₂Si phase.

Based on this hypothesis, the increase in the activation energies as a function of Pt concentration might indicate that the large Pt incorporation inside θ-Ni₂Si phase (refer to Fig. III.2) could slow down the Si diffusion in this phase.

### III.2.3 Influence of dopants on Ni(Pt)Si silicide formation

This section is dedicated to the studies of the changes induced by arsenic and phosphorus doping on the phase sequence formation and final properties of Ni(Pt)Si silicide layer. These studies are of great interest to ensure a proper silicide integration in real devices, which includes heavy n+ doped areas. Influence of other doping species, such as boron, have been extensively studied and can be found for instance in the following references [85], [167]–[169].
III.2.3.1 Influence of As doping on sequence formation: in-situ θ-2θ XRD analyses

Figure III.8 presents the in-situ XRD diagrams obtained after the annealing of an 11 nm Ni(10 at.% Pt) layer on Si(100) substrate without TiN capping (Fig. III.8a), with TiN capping (Fig. III.8c) and of the same stacks on As implanted substrates (resp. Figs. III.8b and d). These diagrams show that the NiPt phase is completely consumed at 225 °C for undoped and doped substrates (Figs. III.8 a and b). For the capped samples, the diffraction peak at 36.6° is assigned to the (111) planes of TiN capping. At the end on NiPt consumption, the distortion of Ni(111) peak is not observed anymore, and the total disappearance of Ni(111) peak is measured at 200 °C. Such observations are essential in the context of the real silicide integration in devices because TiN capping is always deposited on the top of Ni or NiPt layer in that case. TiN deposition performed at 100 °C just after the NiPt layer could then induce NiPt grains growth or stress relaxation inside the NiPt layer and probably the thickening of the Ni-Si intermixing layer. All of these changes may play a role in the formation temperature of the first Ni-rich phase during the subsequent annealing of the TiN/Ni(10 at.% Pt) stacks. We can observe that the formation temperature of the first silicide phase, θ-Ni₂Si phase, is reduced by 25 °C for the TiN capped samples.

<figure><img src="image_47.png" /></figure>

Figure III.8. In-situ θ-2θ XRD diagram during the annealing of a 11 nm Ni(10 at.% Pt) on Si(100) substrate (a), As implanted substrate (b), Ni(10 at.% Pt) capped by TiN on undoped substrate (c), and Ni(10 at.% Pt) capped by TiN on As implanted substrate (d) with an average heating ramp of 1.25 °C per min from 150 to 400 °C.
For all samples no diffraction peak is observed near 225 °C coming from the first growing phase θ-Ni₂Si phase as described previously (III.2.1.1, [160]).

Significant changes in the phase sequence, and mainly in the Ni-rich phases formation, are then observed in the case of As doped substrates (Figs. III.8b and d). Between 225 and 300 °C, diffraction peaks appear at 46 ° and 48.5 ° for doped substrates indexed as (013) and (020) planes of the δ-Ni₂Si phase. Nonetheless, the δ-Ni₂Si is formed by consuming the θ-Ni₂Si for both samples. The Ni(Pt)Si formation is subsequently delayed in presence of As and the growing temperature is respectively 250 °C for the undoped substrates and 280 °C for As doped ones. This experimental result is significant in terms of silicide integration because the salicide process is provided at the same time on different substrates (As, P, B doped substrates) meaning that, during the RTA2, Ni(Pt)Si phase should be completely formed whatever the doping species.

The growth of δ-Ni₂Si before and during the NiSi phase growth has been studied by analyzing the evolution of the normalized intensity for each diffraction peak during isothermal annealings. These results presented in [5] can be summarized for As doped samples as follows:

- Between 230 to 260 °C, the δ-Ni₂Si phase grows by consumption of the θ-Ni₂Si phase.

- At 260 °C, Ni(Pt)Si starts to growth and the simultaneous growing of δ-Ni₂Si and Ni(Pt)Si is observed. The δ-Ni₂Si formation kinetics stays unchanged even if Ni(Pt)Si appears and, at the contrary, the growth speed increases. The growing kinetics are the same for both phases.

- Between 270 and 300 °C, Ni(Pt)Si grows by consuming δ-Ni₂Si, but the formation kinetics is strongly limited which could explain the temperature shift measured for the doped samples.

Figure III.9 summarizes the changes induced by As doping species in the phase sequence during the reaction of Ni(10 at. % Pt) layer with Si(100) substrate.

<figure><img src="image_48.png" /></figure>

Figure III.9. Schematic of phase sequence of the solid-state reaction of an 11 nm Ni(10 at.% Pt) layer capped by TiN on undoped and As doped Si(100) substrate based on in-situ θ-2θ XRD and ASTAR analyses. The declining of the diffraction peak of Ni(111) is schematized by a triangle and blank temperature regions indicates the no-diffraction-peaks areas in the θ-2θ XRD diagrams related to epitaxial phase respect to Si substrate.

### III.2.3.2 APT characterizations of phase transitions for As doped samples

Phases in presence and As distribution in the different silicides layers formed after XRD experiment for the Ni(10 at.% Pt)-Si system are analyzed by APT. APT measurements are carried out
on two samples after an annealing up to 220 °C and 285 °C. Indeed, Figures III.10a and b show the 1D-concentration profiles and the reconstructed volume obtained on the sample annealed up to 220 °C, at the end of metal consumption. In addition, similar results obtained after annealing up to 285 °C, around the δ-Ni₂Si/Ni(Pt)Si transition are displayed on Figs. III.10c and d.

<figure><img src="image_49.png" /><figcaption>Figure III.10. One-dimensional concentration profiles measured by APT of an 11 nm Ni(10 at.% Pt) sample annealed up to 220 °C (a) and 285 °C (c). The y-axis of Ni, Pt and Si concentrations is on the left and the As one is on the right. Respective reconstructed 3D volumes for both samples (b, d): Ni, Pt, Si and As atoms are represented respectively as green, blue, grey and pink dots.</figcaption></figure>

At 220 °C, the formed phase is clearly the θ-Ni₂Si phase as indicated by the Si concentration gradient in Fig. III.10a. We could note also that the metal is not completely consumed at that temperature and approximately the remaining Ni(Pt) layer is 5 nm-thick. By comparing Figures III.2a and III.10a, no significant changes in the Ni, Si or Pt profiles can be noticed between undoped and As doped samples at 220 °C. The As distribution inside the θ-Ni₂Si phase is inhomogeneous. Between 3 and 10 nm, the As concentration is particularly low around 0.8 at.%, between 10 and 12 nm, the As concentration decreases significantly and increases near the silicide/Si interface. The higher As concentration at the interface metal/silicide appears to be linked to Kirkendall effect (as detailed in [5]); and the As accumulation near silicide/Si interface is attributed to the moving-up of this interface during the silicide formation. Nevertheless, the As profile inside the substrate is not modified comparing to the as-deposition profile (not shown here), which might indicate that no As snowplowing occurs during the applied thermal budget (for instance please refer to [152]).
At 285 °C, the Ni and Si profiles are almost flat inside the silicide layer, with the Ni and Si concentrations at 55 and 40 at.% respectively (Fig. III.10c). The Si concentration decreases at the extreme silicide surface (between 2 and 6 nm) to reach 35 at.% signifying the θ-Ni₂Si presence. Another clue to the θ-Ni₂Si presence is the Pt distribution observed in the reconstructed volume (Fig. III.10d). Pt is well distributed in all the silicide volume except in one region (white arrow). Iso-dense concentration surfaces are plotted in Fig. III.10d related to a 60 at.% of Si in grey and 66 at.% of Ni in green. The depleted Pt region is then compatible with the δ-Ni₂Si phase in which, as previously reported, the Pt atomic concentration is estimated inferior to 1 at.% at 285 °C [157]. Interesting observations are given on the Ni and As mappings in Fig. III.10d, Ni(Pt)Si phase is then detected, under the Si iso-concentration surface (in grey), at the interface with the substrate. In the same zone, As clusters are observed and a part of them are included in the Ni(Pt)Si phase.

Similar experiments were carried out on Ni(10 at.% Pt) sample after the complete in-situ XRD experiment up to 400 °C, no major changes were notified comparing the undoped sample.

### III.2.3.3 Phosphorus ex-situ and in-situ doping impact

As explained in Chapter II, 28 nm-FDSOI technology deals with ultra-thin silicide layers of less than 12 nm as the final thickness. To do so, thinner NiPt layer deposition, partial reaction, and new RTA2 annealing (known as Direct Surface Annealing, DSA) have been developed. Moreover, memory cells dimensions are decreasing, and new integration roads arise the need of phosphorus in-situ doping as a substitute to P doping by ionic implantation. These two doping types are then investigated. By ionic implantation, the average P dopant concentration is 7.10²⁰ at.cm⁻³ after activation annealing (Fig. III.11a). For in-situ doping, which is made by Low Pressure Chemical Vapor co-Deposition (LPCVD) of Si and phosphorus, the average dopant concentration is 2.8.10²⁰ at.cm⁻³ (Fig. III.11b).

<figure><img src="image_50.png" /><figcaption>Figure III.11. Phosphorus distribution and quantitative concentration obtained by ToF-SIMS after ionic implantation (a) and in-situ doped Si deposition by LPCVD on Si substrate (b) (respectively called implanted and in-situ mono-Si in the following). The activation annealing is a spike anneal at 1050 °C in both cases.</figcaption></figure>

The interaction between NiPt-silicides and phosphorus was studied during the Ph.D work of Mathilde Lemang [170], and the main results of this work will be reported in this section. Two types of samples have been analyzed: 7 nm and 16 nm of Ni(10 at.% Pt) respectively deposited on different substrates i.e., undoped Si(100), P in-situ doped Si substrate (called here P in-situ mono-Si), P in-situ
doped polysilicon Si (named P in-situ poly-Si) and P ex-situ doped Si substrate (P implanted mono-Si). The Rs and the silicide thickness evolutions are measured after RTA1 at temperatures comprised between 150 and 800 °C. The phase sequence changes linked to the substrate nature and doping types are then identified by in-situ XRD experiments.

### III.2.3.3.1 Doping type effect on phase sequence in Ni(10 at.% Pt)-Si system

In Figure III.12, NiPt-silicide sheet resistances and thicknesses - extracted from XRR (X-ray Reflectivity) simulations - formed after the annealing of a 7 nm Ni(10 at.% Pt) film on different doped substrates are presented.

<figure><img src="image_51.png" /></figure>

Figure III.12. Rs measurements of silicide formed from the reaction of a 7 nm of Ni(10 at.% Pt) film with undoped Si(100), P implanted mono-Si, P in-situ mono-Si and P in-situ poly-Si substrates (resp. a, b and c). Silicide thicknesses obtained by XRR on the same samples (d, e and f). The measurements are made after RTA annealings for 30 s and selective etching process.
For undoped samples and annealing temperatures from 180 to 260 °C, the sheet resistance, Rs, decreases from 270 to 130 Ω/sq. Then, between 260 and 280 °C, the Rs is constant. Starting from 300 °C, there is a major Rs decrease indicating that Ni(Pt)Si is formed since it is a less resistive phase [37], [171]. The sheet resistance remains constant at 23 Ω/sq until 700 °C. At higher temperature Rs increases drastically due to Ni(Pt)Si films agglomeration [37], [73], [156].

Regarding the implanted samples (Fig. III.12a), there is a restricted variation in the sheet resistance during the formation of the Ni₂Si phase linked to a better substrate conductivity. The Ni₂Si phase spreads from 180 to 300 °C. The Rs decreases until 240 °C from 100 to 75 Ω/sq and then stays constant from 240 to 300 °C. Between 350 and 600 °C, the Rs falls indicating the Ni(Pt)Si formation. Finally, the agglomeration threshold temperature is the same as undoped samples and the formation of Ni(Pt)Si phase is delayed by 50 °C on P implanted mono-Si substrates.

For P in-situ doped samples in Figs. III.12b and c, Rs measured at 180 °C is divided by a factor 2 for in-situ P doped mono-Si compared to the ex-situ implanted ones whereas the dopant density is lower for these samples than for the implanted ones (Fig. III.11).

Similar Rs evolution is observed for P implanted mono-Si and in-situ poly-Si for temperatures comprised between 180 °C and 300 °C (Fig. III.12c). Whereas the doping type is the same as in-situ doping mono-Si sample the Rs value is twice higher for poly-Si sample. A lower size of Ni₂Si grains is then presumed in this case.

The Ni₂Si and Ni(Pt)Si silicides thicknesses are displayed in Figs. III.12 d, e and f, the main results are summarized in the following table:

<table><caption>Table III.3. Ni₂Si and Ni(Pt)Si silicides thicknesses extracted from XRR spectra and estimated roughness of silicide films linked to reduction of XRR oscillations from [170]. The measurements are made after RTA annealings for 30 s and after selective etching process.</caption><thead><tr><th rowspan="2">Substrate type</th><th colspan="3">Ni₂Si thickness (nm)</th><th colspan="2">Ni(Pt)Si thickness (nm)</th><th rowspan="2">Roughness estimated from XRR spectra</th></tr><tr><th>T = 180 °C</th><th>T = 240 °C</th><th>T = 280 °C</th><th>T = 300 °C</th><th>T = 350 °C</th></tr></thead><tbody><tr><td>Undoped Si(100)</td><td>5 ± 0.5</td><td>10 ± 0.5</td><td>13 ± 0.5</td><td>14 ± 0.5</td><td>15 ± 0.5</td><td>Low</td></tr><tr><td>P implanted mono-Si</td><td>6 ± 0.5</td><td>10 ± 0.5</td><td>10 ± 0.5*</td><td>10 ± 0.5*</td><td>13 ± 0.5</td><td>High</td></tr><tr><td>P in-situ mono-Si</td><td>5 ± 0.5</td><td>10 ± 0.5</td><td>12 ± 0.5</td><td>14 ± 0.5</td><td>15 ± 0.5</td><td>Low</td></tr><tr><td>P in-situ poly-Si</td><td>3 ± 0.5</td><td>9 ± 0.5</td><td>9 ± 0.5</td><td>14 ± 0.5</td><td>15 ± 0.5</td><td>High</td></tr></tbody></table>

Based on Table III.3, at 180 °C the lower Rs measured for implanted samples compared to the undoped one cannot been explained by an increase of Ni₂Si silicide thickness and may be correlated to a higher density of carriers inside the substrate. At the same temperature, similar silicide thicknesses for implanted and in-situ doping samples are extracted which cannot explain the drop of the Rs in the case of in-situ doping.

<footnote>* under Ni₂Si-NiSi transition for ex-situ implanted samples.</footnote>
At 280 °C, lower Ni₂Si silicide thicknesses are observed for implanted mono-Si and in-situ poly-Si in a good agreement with the higher Rs value for these samples comparing to in-situ mono-Si one. In addition to a better substrate conductivity, the slight increase in the Ni₂Si layer thickness could play a role in the measured Rs value for in-situ mono-Si sample at 280 °C, just before Ni(Pt)Si formation.

At 300 °C, the delay in Rs fall is confirmed by XRR measurements for implanted mono-Si sample because the Ni₂Si thickness is equal to 10 nm whereas all other samples exhibit, after Ni(Pt)Si formation, a silicide thickness near 14 nm. As reported in Annex A1, that indicates a delay in Ni(Pt)Si formation as Si consumption is nearer to Ni₂Si phase than NiSi one at that temperature. At the end, Ni(Pt)Si thickness appears to be the same for all samples at 350 °C. One may consider the estimated roughness detected on XRR spectra (reduction of oscillations number) for implanted mono-Si and in-situ poly-Si samples, which could increase experimental discrepancy.

In-situ XRD experiments are then used to follow the diffraction peaks of the phases formed by the reaction of 7 nm Ni(10 at.% Pt) layer capped by TiN layer and each type of substrates (Fig. III.13).

<figure><img src="image_52.png" /><figcaption>Figure III.13. In-situ θ-2θ XRD diagrams during the reaction of a 7 nm Ni(10 at.% Pt) layer capped by TiN deposited on an undoped Si (a), P implanted mono-Si (b), P in-situ doped mono-Si (c), and P in-situ doped poly-Si substrates (d) with a 5 °C step annealing from 45 to 465 °C. Unindexed diffraction peaks at 25.5°, 35°, 43.2°, 47°, 52.5° and 57.5° are attributed to the sample holder in Al₂O₃.</figcaption></figure>
For all samples, the diffraction peak related to NiPt(111) at 44° disappears at 125 °C, which indicates the total consumption of the NiPt layer. One may notice that the first step annealing is set at 45 °C during this experiment, which is clearly different to the previous one which started at 150 °C (Figs. III.1 and III.8). The lower temperature measured here for NiPt layer consumption might be induced by a different thermal budget, applied to these samples compared to the previous study. Moreover, the lower NiPt thickness as 7 nm vs 11 nm for the samples previously studied acts in the same way.

From 125 to 180 °C no more diffraction peaks are detected as expected for the formation of θ-Ni₂Si phase as the first phase to grow during the reaction of Ni(10 at.% Pt) with Si. Thus, for the present study, the Ni-rich phase is θ-Ni₂Si despite the phosphorus implantation and substrate types. Regarding the differences in Rs curves and the XRR measurements for implanted Si samples, in-situ XRD results explicit a unique phase sequence formation for all sample types for this system.

Finally, Ni(Pt)Si is identified through the (013) orientation at 55.8° starting from different temperatures for ex-situ (Rs and XRR) and in-situ XRD measurements. The temperature difference between ex-situ and in-situ experiments is constant whatever the sample types and equals to 105 ± 5 °C. Here, the delay in Ni(Pt)Si phase formation linked to the P implanted in mono-Si substrate is estimated to be 45 °C in good agreement with Rs and XRR measurements (Fig. III. 12). Another orientation of Ni(Pt)Si planes is thus detected for in-situ doped poly-Si substrates, i.e., NiSi(111).

Additional in-situ XRD experiments have been provided on similar substrates after the deposition of a 16 nm-thick NiPt layer capped by TiN, shown in Figure III.14.
<figure><img src="image_53.png" /></figure>

Figure III.14. In-situ θ-2θ XRD diagram during the reaction of a 16 nm Ni(10 at.% Pt) capped by TiN and deposited on an undoped Si substrate (a), P in-situ doped mono-Si (b), and P in-situ doped poly-Si (c) with a 5 °C step annealing from 45 to 465 °C.

For the undoped sample, no major changes are observed except the large number of Ni(Pt)Si orientations here compared to Fig. III.13a. The NiSi fiber texture observed after the reaction of a 7 nm NiPt layer disappears to the benefit of a random one when the NiPt layer is thicker, here 16 nm. We can note that, based on F. Panciera's results presented in Fig. III.8c, for a NiPt thickness of 11 nm, the (013) fiber texture is also detected at 56° meaning that a change in Ni(Pt)Si grains growth apparently occurs when the NiPt layer thickness is larger than 11 nm.

For in-situ doped samples, in Figs. III.14b and c, the δ-Ni₂Si phase is observed at the same time as Ni(Pt)Si forms like in Geenen et al. study [150]. This is a new phase sequence observation, which is different from the one detected for As implanted substrates and also undoped samples in the case of TiN capping (Fig. III.9).

The change in the phase sequence for all the samples studied during this work [170] is detailed in the following schematics:
<figure><img src="image_54.png" /><figcaption>Figure III.15. Schematics of phase sequence of the solid-state reaction of a 7 and 16 nm Ni(10 at.% Pt) layers capped by TiN with undoped, P implanted, P doped in-situ mono-Si and P in-situ poly-Si samples based on in-situ θ-2θ XRD and ASTAR (not shown here) analyses.</figcaption></figure>

### III.2.3.3.2 P redistribution and segregation after annealings

In this section, the potential relationship between phosphorus segregation at Ni(Pt)Si/Si interface and the mitigation of Ni diffusion will be analyzed. In fact, Ni(Pt)Si is formed on undoped substrate at 200 °C for P in-situ mono-Si, contrary to P implanted one at 240 °C (as shown in Fig. III.15). This result could be related to the P redistribution, P clustering in the case of ex-situ doping and P concentration inside the Ni-rich phases.

In Figure III.16, ToF-SIMS analyses performed after annealing of a 7 nm NiPt/TiN stack on the different substrates are shown. Contrary to Rs and XRR experiments, no selective etching is performed on these samples to keep the TiN capping layer in place on the top of NiPt layer to avoid thin metal film oxidation. Based on P profiles no clear evidence of a change in resistivity as an improvement of substrates conductivity is found by comparison with in-situ mono-Si and poly-Si whereas the effective resistivity appears to be 50 % lower for in-situ mono-Si sample (Fig. III.12). A clear accumulation of P at NiPt/Ni₂Si interface is then observed for the implanted sample compared to the other ones which may explain the delay in Ni(Pt)Si formation measured previously for this sample.
<figure><img src="image_55.png" /><figcaption>Figure III.16. Ni, Si, Pt intensities and P concentration profiles measured by ToF-SIMS after the reaction of 7 nm Ni(10 at.% Pt) layers capped by TiN at 230 °C for 20 s with P implanted mono-Si (a), P in-situ doped mono-Si (b) and P in-situ doped poly-Si (c). The P concentration in at/cm³ is given only for in-situ samples in (b) and (c).</figcaption></figure>

As presented in Figure III.17, after DSA2 (for this sample the RTA2 is performed with a Direct Surface Annealing i.e., DSA2), there is a phosphorus accumulation at the Ni(Pt)Si surface and at the Ni(Pt)Si/Si interface. A bump of the phosphorus concentration on top of the Ni(Pt)Si/Si interface is also identified by APT and ToF-SIMS techniques for P implanted samples. This bump is closer to the Ni(Pt)Si/Si interface than to the NiSi surface. The origin of this specific P distribution inside the final silicide layer appears to be the preceding P accumulation at the Ni₂Si/Si interface after RTA1, as shown in Figure III.16a. This is explained by the presence of phosphorus in the silicide/Si interface that hinders the Ni diffusion to the Si during the DSA2. It is also observed for similar annealings, the phosphorus redistribution is the same whatever the thickness of deposited Ni(10 at.% Pt) layer (not shown here).

One may consider the good agreement between the ToF-SIMS and APT analyses on the P distribution inside the silicide layer and at the interfaces.
<figure><img src="image_56.png" /></figure>

Figure III.17. Reconstructed 3D volume obtained by APT after the complete silicide formation of a 7 nm Ni(10 at.% Pt) layer capped by TiN on P implanted mono-Si substrate (a and b). The Ni(Pt)Si layer is formed after a RTA1 followed by a selective etching step and a DSA2. 1D profiles of Ni, Si and P concentrations calculated along the dark arrow (c). Ni and P intensity profiles measured by ToF-SIMS on the same sample (d).

Finally, the phosphorus redistribution and especially the presence of the bump in the Ni(Pt)Si is associated with a combined effect of the initial concentration of phosphorus in the substrate (ToF-SIMS profiles are not all presented here, please refer to [172] for details), and a trace of the former Ni₂Si/Si interface. Moreover, the P accumulation at the interface is linked to a segregation phenomenon.

<figure><img src="image_57.png" /></figure>

Figure III.18. Schematics of Phosphorus redistribution after selective etching process (a): focus on the θ-Ni₂Si/Si interface. During DSA2, at time t, Ni diffusion through the θ-Ni₂Si/Si interface and Ni(Pt)Si formation induces P profile changes as presented in (b). At time t + dt, at the end of DSA2, the P profile inside the final silicide layer forms a bump linked to the Ni(Pt)Si growth on the both sides of the former θ-Ni₂Si/Si interface (c).
During the Ph.D thesis of Mathilde Lemang [167] [169], based on the observations of phosphorus redistribution and phase sequence changes, simulations of the P redistribution were carried out with a finite difference method in one dimension, close to the one described in the Blum et al. study [85]. The model allows to reproduce the different redistribution profiles for in-situ doped and implanted samples. The P redistribution can be explained by interfacial segregation, transport by mobile interfaces and grain boundaries diffusion. **Therefore, the redistribution model that is proposed and the hypotheses concerning the P solubility seem to be valid. Finally, the low concentration of P in the silicide and the segregation at its surfaces can be explained by a low solubility of phosphorous in the θ-Ni₂Si and a fast diffusion of this dopant at its grain boundaries.**

This model enables the modeling of phosphorus redistribution for both kinds of doping with the same parameters. Thus, the physical mechanisms governing the P redistribution are the same whether the substrate is in-situ doped or implanted. Only the position of the bump in the Ni(Pt)Si layer is not exactly aligned with experimental results. In the simulations it is in the middle of the Ni(Pt)Si layer while, on experimental 1D APT profiles, it was measured closer to the Ni(Pt)Si/Si interface. To model the experimental results with more accuracy, the presence of a different Ni-rich phase could then be considered as the Ni₃Si₂ phase whereas this phase is not observed during the in-situ XRD experiments.

### III.2.4 Pre-amorphization by implantation

As previously mentioned one of most important drawbacks of Ni(Pt) silicide is its poor thermal stability [37], [156]. Indeed, at high temperature the resistivity of the Ni-silicide collapses due to its agglomeration and the nucleation of the higher resistive phase NiSi₂ [76]. Thus, high temperature heat treatments are not possible after Ni-silicide formation, which is problematic for some architectures such as 3D sequential technology [24]. For NiPt alloys, a clear improvement of the silicide properties can be achieved through an amorphization of the Si substrate prior NiPt deposition as reported in several papers [90], [155], [173]–[176]. The Pre-Amorphization by Implantation (PAI) appears to reduce the Ni silicide roughness and subsequently the associated junction leakage [90], [173], [175], [176] and delay the silicide agglomeration [155], [174]. Different species were used to perform PAI: Ge, Si and C are part of these elements known to improve the silicide thermal stability [90], [155], [175], [176]. Moreover, the 28 nm-FDSOI technology deals with ultra-thin silicide layers less than 12 nm thick. Amorphizing the Si substrate can play a role in Ni diffusion and first phase formation and then provide a lower Si consumption after the complete silicide process.

In this section, the impact on the Ni-silicide properties of the amorphous silicon (a-Si) thickness generated by the PAI process and the potential benefits of adding a carbon implantation are evaluated. A large part of the presented results have been published in [177].

#### III.2.4.1 Role of Ge and Si PAI on silicide properties: resistivity, thickness, and roughness

P-type Si(100) wafers with a resistivity of 20–40 Ω.cm are used as the starting material. Crystal TRansport of Ions in Matter (CTRIM) simulations are conducted to determine the various energies and doses needed to amorphize the desired Si thicknesses. All the implantation energies are chosen to
localize the projected range within the silicon region consumed during the silicidation process, except for the thickest a-Si layer. TEM (not shown here) is used to measure the a-Si thicknesses. The ionic implantation processes are performed on a VIISTA HCP. Following ion implantation, a 7 nm Ni(10 at.% Pt) film capped by TiN layer is then deposited by PVD without vacuum break. After complete silicide process as a RTA1 at 230 °C for 20 s, a wet removal of unreacted metal and a DSA2 at 815 °C, the samples are characterized by Rs, XRR, ToF-SIMS and STEM analyses.

Firstly, Figure III.19a presents Ni(Pt)Si layer resistivity calculated from Rs measurements and XRR modeling for different Si and Ge PAI conditions inducing an a-Si layer comprised between 2 and 22 nm. One may notice that the final silicide thickness in this case is 11 ± 1 nm for reference sample, i.e., without PAI prior NiPt deposition. In Figure III.19b the silicide thickness and roughness determined from XRR modeling are given for the same samples. The resistivity exhibits a minimum around 8 nm of a-Si for the Ge PAI and around 12 nm for the Si PAI, meaning that the a-Si thickness created by the PAI impacts the silicide electrical properties. The variation of the resistivity can be explained by a change in the microstructure and/or the grain size inside Ni(Pt)Si layer.

<figure><img src="image_58.png" /><figcaption>Figure III.19. Ni(Pt)Si layer resistivity calculated from Rs measurements and XRR modeling for various Si and Ge PAI conditions (a). The a-Si thickness for each PAI condition is estimated by TEM. Ni(Pt)Si thickness and roughness extracted from XRR spectra modeling (b). Thickness and roughness values are respectively plotted in back and blue referring to the left and right y-axes in (b). The silicide layer is formed by the reaction of a 7 nm of Ni(10 at.% Pt) film with undoped Si(100) substrate after the complete silicide process from [177].</figcaption></figure>

As reported in [178], the increase of the resistivity might result from a grain size reduction. Whatever the PAI species (Si or Ge), the Ni(Pt)Si thickness is increased compared to the reference without any PAI treatment. This can be due to either the faster diffusion of Ni inside the Ni₂Si phase presenting a higher grain boundaries density or a faster growth rate at the NiPt/Si interface. Indeed, it was reported that the Ni-silicide growth rate depends on the amorphous or crystalline state of the silicon [90]. A decrease of the Ni(Pt)Si roughness can be seen with Ge PAI in comparison to the reference sample. This decrease of the roughness is independent of the a-Si thickness. Unlike Ge PAI, Si PAI increases the roughness of the silicide, this effect raises with the a-Si thickness. The change in Ni(Pt)Si roughness highlighted by XRR modeling is confirmed by STEM observations in Figure III.20.
<figure><img src="image_59.png" /></figure>

Figure III.20. STEM images in cross-section after the reaction of a 7 nm Ni(10 at.% Pt) film with undoped Si(100) without PAI (a), after Ge (b) and Si (c) PAI steps. The a-Si thickness for PAI processes is 5 nm. The silicide layer is formed after RTA1, selective etching and DSA2 processes.

### III.2.4.2 Impact of carbon PAI addition on silicide properties and thermal stability

Because of highest thermal stability of silicide is needed for new technologies such as the 3D sequential one, an additional implantation of carbon after the Ge or Si PAI is studied. Carbon is known to improve the thermal stability of the silicide [88], [155]. The 5 nm a-Si thickness process conditions are chosen for the Si and the Ge PAI based on previous results. All the other processes remained unchanged and XRR analyses were performed after silicidation process. The silicide thickness decreases for both types of PAI when increasing the carbon dose (Figure III.21). This might be explained by a reduction of the Ni diffusion due to the carbon located at the grain boundaries [179]. When increasing the carbon dose, a strong decrease of the silicide roughness is observed in all cases (see Fig. III.20). This result is even more remarkable for the Si PAI, where the lack of carbon strongly deteriorates the silicide roughness.

<figure><img src="image_60.png" /></figure>

Figure III.21. Ni(Pt)Si thickness and roughness extracted from XRR spectra modeling for Ge PAI+C and Si PAI+C samples. Thickness and roughness values are respectively plotted in back and blue referring to the left and right y-axes. The silicide layer is formed by the reaction of a 7 nm of Ni(10 at.% Pt) film with undoped Si(100) substrate after the complete silicide process (i.e. RTA1, selective etching and DSA2) from [177].
The reduction of the silicide roughness by the addition of a carbon implantation step is confirmed by STEM observations and a minimum of Ni(Pt)Si/Si interface roughness is observed for a carbon dose of 2.10<sup>+15</sup> at/cm<sup>2</sup> as presented in Figure III.22.

<figure><img src="image_61.png" /><figcaption>Figure III.22. STEM images in cross-section after the reaction of a 7 nm Ni(10 at.% Pt) film with undoped Si(100) without PAI (a), after Ge PAI+C with a dose of 2.10<sup>15</sup> at/cm<sup>2</sup> (b) and 4.10<sup>15</sup> at/cm<sup>2</sup> (c). The silicide layer is formed after RTA1, selective etching and DSA2 processes.</figcaption></figure>

To further investigate the effect of the carbon on the silicide formation, ToF-SIMS analyses are performed on the Ge PAI+C samples for two carbon doses. Results shown in Figure III.23 indicate that the carbon profile is the same whatever the dose, no segregation at the interface is visible. By contrast, a change in the Pt distribution can be seen between the two different carbon doses. **With the highest carbon dose, the Pt is distributed uniformly within the silicide thickness (Fig. III.23a).** Whereas for lower dose, the Pt profile is similar to the one observed for undoped Si substrate without PAI as presenting as concentration gradient inside the final silicide layer (see for instance Fig. III.5). A comparable impact of carbon on the Pt diffusion was seen by Pivac et al. at high temperatures [180] and explained by the modification of the distribution of Si interstitial sites, which is the driving force of the Pt diffusion. Another potential explanation could be the change in θ-Ni<sub>2</sub>Si grains size, and this key point needs further investigations, and will be discussed in Chapter V.

<figure><img src="image_62.png" /><figcaption>Figure III.23. Pt, Ni, Si, C and Ge profiles measured by ToF-SIMS after the reaction of a 7 nm Ni(10 at.% Pt) film with undoped Si(100), after Ge PAI+C with a dose of 2.10<sup>15</sup> at/cm<sup>2</sup> (a) and 4.10<sup>15</sup> at/cm<sup>2</sup> (b). The silicide layer is formed after the complete silicide process [177].</figcaption></figure>
To estimate the carbon PAI impact on Ni(Pt)Si thermal stability, Rs measurements are
performed after additional annealings at different temperatures on previous Ge PAI+C and Si PAI+C
samples (shown in Fig. III.24). Significant improvements are observed for the both PAI species by
adding carbon. At 800 °C, only the two highest carbon doses remain under the sheet resistance of the
reference. As previously shown, the carbon addition plays a role in the reduction of Ni(Pt)Si/Si
interface roughness and then in the grain-boundaries grooving (please refer to section III.5.1), as will
be deeply explained in section III.5. The limitation of interface roughness might be a key factor in the
agglomeration delay.

<figure><img src="image_63.png" /><figcaption>Figure III.24. Rs evolution of silicide formed by the reaction of 7 nm of Ni(10 at.% Pt) film with undoped substrate after the complete silicide process as a function of carbon doses added after Ge PAI (a) and Si PAI step (b) [177].</figcaption></figure>

III.3 Ni₁₋wPtw (0<w<0.15)-Si₀.₇Ge₀.₃ system

As detailed in Chapter II (subsection II.1.2), for 14 nm node and beyond, planar transistor FD-SOI
substrate is an alternative approach to FinFET technologies on bulk substrates [15], [17]. The
integration of Si₁₋ₓGeₓ epitaxial layers in source/drain areas enhances the hole mobility by inducing a
compressive stress on the pMOS channel [181]. However, the nickel based germano-silicidation of
source and drain remains a critical challenge [182]. On one hand, the final silicide thickness in such
aggressive architecture should be less than 15 nm. On the other hand, nickel germano-silicide suffers
from Ge out-diffusion and film agglomeration at high temperature, which both degrade the transistor
performances irreversibly. Morphological stability improvement has been achieved by using Ni₁₋wPtw
alloys on Si and Si₁₋ₓGeₓ [77]. Several papers relate to the Ni-Si₁₋ₓGeₓ reactions [78], [183], [184] but
much less deal with Ni₁₋wPtw-Si₁₋ₓGeₓ system [77], [185]. Nevertheless, for this quaternary system, the
solid-state reactions are complex and need to be deeply understood in the frame of microelectronics
applications (i.e., contact integration) and material science research.

This section is dedicated to the study of this quaternary system and will be divided into two parts.
Firstly, we focus on the phase sequence identification during the solid state reactions between Ni films
alloying or not with Pt and a Si<sub>0.7</sub>Ge<sub>0.3</sub> epitaxial layer as reported in Emilie Bourjot's Ph. D dissertation
[6]. Secondly, the kinetics of the phases in presence will be determined through in-situ XRD and Rs measurements which were carried out simultaneously at IM2NP as detailed in [186].

### III.3.1 Impact of Pt addition on Ni-germano-silicides phase sequence

#### III.3.1.1 In-situ Rs and θ-2θ XRD measurements

Undoped 20 nm thick epitaxial Si<sub>0.7</sub>Ge<sub>0.3</sub> layers are grown on SOI substrate. The Si<sub>0.7</sub>Ge<sub>0.3</sub> surface is cleaned with a diluted HF solution, followed by chemical plasma based on NH<sub>3</sub> and NF<sub>3</sub> (SiCoNi pre-clean). Then, Ni-Pt alloy films are deposited by physical vapor deposition (PVD) from different Ni(w at.% Pt) targets (see details in Table III.1).

Ni<sub>1-w</sub>Pt<sub>w</sub>/Si<sub>1-x</sub>Ge<sub>x</sub> solid-state reactions are studied upon annealing up to 500 °C by simultaneous in-situ Rs and XRD diffraction. One can notice that the TiN capping layer is not deposited for these experiments which can induce a change in Ni and NiPt films consumption and mono-germano-silicide temperature formation (see for example Fig. III.8). In-situ XRD measurements are performed on a diffractometer configured in Bragg-Brentano geometry (Philips X'pert MPD) using copper radiation (λ=1.5418 Å). The sample is loaded into a vacuum chamber (10<sup>-6</sup> mbar), equipped with a heating stage and an aligned four-point probe sheet resistance setup [187].

Figure III.25 sums up the in-situ experiments conducted during the reaction of a 7 nm of Ni, Ni(5 at.% Pt), Ni(10 at.% Pt), and Ni(15 at.% Pt) films with Si<sub>0.7</sub>Ge<sub>0.3</sub> substrates. The Rs values are normalized with respect to the maximum value and are given in arbitrary units as a function of temperature. In the in-situ XRD diagrams, the diffracted intensity is normalized as well to the maximum intensity corresponding to the color scales (please note that the color scale is not the same for each figure).

Firstly, for Ni samples (Fig. III.25a), the Rs evolution as a function of temperature enables us to distinguish four distinct and successive steps, noted 1 to 4, in the solid-state reaction. In the first region, the Rs increases slowly associated with the slight increase of Ni resistivity with temperature as generally observed for metals. The XRD diagram indicates the presence of Ni(111) peak, and the film does not react with the substrate until 110 °C. In the second region (noted 2), the Rs increases drastically and reaches the maximum value for a temperature of 170 °C. XRD diagram indicates the consumption of Ni phase observable by the decrease of the Ni(111) peak before its disappearance. The Ni phase is then consumed, and a higher resistive phase is formed. Nevertheless, no diffraction peak is observed near 170 °C coming from the first growing phase as previously shown for other Si systems (III.2.1, [160]). The identification of this phase will be provided through additional in-situ TEM and XRD measurements in the next section. Between 170 and 350 °C (step 3), the Rs decreases, and the slope indicates several inflexion points. The δ-Ni<sub>2</sub>SiGe is identified through two diffracted peaks related to (013)/(211) and (020) planes, respectively.
Between 200 and 250 °C the Rs reaches a plateau indicating the δ-phase thermal stability in this temperature range. For higher temperatures of 250 °C, the Rs decreases linearly whereas the diffraction peaks of δ-phase are still observed. This observation is unexpected for a stable phase and might be related to a reduction of substrate resistivity. The fourth domain starts at 350 °C with the disappearance of δ-phase diffraction peaks to the benefit of mono-germano-silicide formation, identified by the large decrease of Rs related to the less resistive phase nucleation and growth. As reported in following papers [52], [183], at 350 °C the NiSiGe phase could be formed. Nonetheless, no diffraction peaks for this new phase are observed here.

<figure><img src="image_64.png" /><figcaption>Figure III.25. Normalized in-situ Rs and θ-2θ XRD diagrams as the function of temperature during the reaction of 7 nm Ni₁-ωPtω (0<ω<0.15) films with Si₀.₇Ge₀.₃ epitaxial layer. The heating rate is set at 2 °C/min (a to d). The Rs values are normalized respect to the maximum value as well as the diffracted intensity to the maximum intensity (red color) corresponding to the color scale.</figcaption></figure>
Several changes can then be noticed in the solid-state reaction based on in-situ experiments by alloying Pt to Ni as illustrated in Figs. III.25b to d:

- **Step 1:** The consumption of the Ni phase is delayed by adding Pt. For Ni(5 at.% Pt) alloy, the measured shift is 30 °C and the decreasing XRD peak intensity is observed at 140 °C. For Ni(10 at.% Pt) samples, this transition temperature of the first growing phase is similar to the one reported in Figures III. 13 and 15 for undoped silicon substrates. The concomitant gradual increase of Rs reveals the formation of the first phase with higher resistivity for all samples.

- **Step 2:** As previously described for Ni sample, the domain 2 starts at the end of Ni phase consumption and finishes at the δ-phase appearance. For NiPt films, this domain presents a larger temperature scale. The Rs curve shape is the same for all NiPt samples and the Rs value reaches the maximum around 200 °C related to the high resistive Ni-rich phase growing after complete Ni consumption. Between 200 and 275 °C, no XRD peak is detected and the Rs continuously decreases. As presented before in paragraph III.2.1, in Bragg-Brentano geometry, the extinction of XRD peaks might be linked to the formation of an epitaxial phase which presents a continuous reduction of the apparent resistivity.

- **Step 3:** For this step, a clear difference is observed between the Ni and the NiPt alloy films. The temperature range is largely reduced with Pt addition, comprised between 275 and 330 °C for Ni(5 at.% Pt) layer, and clearly reduced for Ni(10 at.% Pt) and Ni(15 at.% Pt) as started at 275 °C and ended at 300 °C.

The Rs plateau, which is observed for Ni sample (Fig. III. 25a) and attributed to the thermal stability of the δ-phase, is only measured for Ni(5 at.% Pt) sample (Fig. III. 25b). For this sample, in addition to the δ-phase formation, the θ-phase is identified at 280 °C in the same range of temperature as the δ-phase. For this phase only one peak is measured related to (020) θ-phase planes.

For Ni(10 at.% Pt) sample (Fig. III. 25c), a new phase grows and disappears as indicated by the rapid appearance/disappearance of two diffraction peaks at 46° and 48° (as (013) and (020) planes of δ-phase) whereas the Rs measurement decreases, and the curve presents an inflexion point. Similar results have been shown for Ni(10 at.% Pt)-Si system (see for example Figure III.8), this phase is indexed as δ-Ni₂SiGe phase even though the peaks have been compared to the observed peaks, but they do not match exactly. The presence of Pt and Ge may explain this shift in position.

For Ni(15 at.% Pt) sample (Fig. III. 25d), no XRD peaks are observed after the complete metal consumption. Nevertheless, the Rs slope is almost the same as the Ni(10 at.% Pt) sample in this domain range and similar inflexion points are then distinguished. At that point, Ni-rich and final mono-germano-silicide phases obtained through the reaction of Ni(15 at.% Pt) layer could not be identified and additional characterizations for this specific system will be then presented in section III.3.1.4.

- **Step 4:** The addition of Pt appears to reduce the temperature formation of the mono-germano-silicide. For Ni sample, this temperature is estimated to be 350 °C related to the disappearance δ-phase and the simultaneous Rs inflexion point. For Ni(5 at.% Pt) sample, the mono-germano-silicide Bragg reflections are detected at 330 °C. For Ni(10 at.% Pt) sample, similar diffraction peaks are observed at
300 °C and for Ni(15 at.% Pt) sample, no XRD peaks have been identified but the Rs inflexion point, related to the mono-germano-silicide formation, is measured at 300 °C.

The conclusions of in-situ Rs and θ-2θ XRD measurements performed together on the Ni₁₋wPtw-Si₁₋ₓGeₓ systems are summarized in the subsequent figure:

<figure><img src="image_65.png" /></figure>

Figure III.26. Schematic of phase sequence of the solid-state reaction of 7 nm Ni₁₋wPtw (0<w<0.15) films deposited on Si₀.₇Ge₀.₃ epitaxial layer based on the in-situ Rs and θ-2θ XRD measurements. The declining of the diffraction peak of Ni(111) is schematized by a triangle and blank temperature regions indicates the no-diffraction-peaks areas in the θ-2θ XRD diagrams related to epitaxial phase respect to Si₀.₇Ge₀.₃ substrate.

### III.3.1.2 SAED and pole figures analyses on Ni-Si₀.₇Ge₀.₃ system

Selective Area Electron Diffraction (SAED) patterns have been recorded during in-situ TEM analyses on a similar Ni/Si₀.₇Ge₀.₃ sample just after deposition (Figs. III.27a and b), and by increasing the temperature step by step from room temperature to 500 °C inside the TEM. The purpose here is to identify phases in presence for the descripted temperature domains 1, 3 and 4 in Figure III.25. The longest temperature steps are realized at 280 °C and 400 °C for 1 hour (shown in Figs. III.27c and d). The diffraction patterns are analyzed through the commercial software Gatan Digital Micrograph.

In Fig. III.27a and b, the initial state is characterized by three different patterns including two networks and a ring. The intense points defining a square network are related to the Si (001) substrate as planes {220} and {400} (d = 1.92 Å and 1.35 Å respectively). The ring is detected for an inter-planes distance equals to 2.01 Å corresponding to the {111} planes of Ni with a fiber texture as already observed during in-situ XRD experiments. The second network is identified as a hexagonal one as detailed in Figure III.27b and three different d-spacing are then measured as: 3.0 Å, 3.5 Å and 6.1 Å. Four hexagonal phases are known in the Ni-Si and Ni-Ge systems (subsections II.2.1). The diffraction patterns observed here might correspond to the Ni(Pt)₃₁(SiGe)₁₂ based on the data given in Annexes. One may notice that the inter-planes distances are larger than the Ni₃₁Si₁₂. The enlargement should be due to the presence of Ge atoms which deals with an increase of lattice width [188]. The phase is in epitaxy with the substrate (001) and the direction [110] is aligned with the [100] of Si.
<figure><img src="image_66.png" /><figcaption>Figure III.27. SAED patterns obtained during in-situ TEM analyses in top view of a 7 nm of uncapped Ni film deposited on Si$_{0.7}$Ge$_{0.3}$ epitaxial layer at room temperature (a, b), at 280 °C (c) and 400 °C (d) [6].</figcaption></figure>

As presented in Figure III.27c, at 280 °C, the diffraction patterns are clearly different than those observed at room temperature. The ring related to the Ni (111) fiber texture and the hexagonal patterns have disappeared. Partial rings are then identified at 3.53 Å, 3.12 Å, 2.93 Å, 2.28 Å, 1.84 Å, 1.72 Å and finally in center of diffraction features at 1.55 Å. By comparing the known phases for the Ni-Si system, these inter-planes distances correspond to the δ-Ni$_{2}$SiGe phase related to the planes families respectively of {002}, {011}, {102}, {112}, {113}, {203} and {213}. This result is in good agreement with the in-situ XRD observations. The change in the diffracted intensity along each ring exhibits preferred orientations grains, close to a fiber texture or linked to small grains formation.

Finally, at 400 °C, the number of rings decreases as can be seen on Figure III.27d, and only two rings are observed with the given position of 3.1 Å and 2.8 Å. A rectangular feature at 2.7 Å and 2.5 Å appears at 400 °C, not observed at 280 °C. Based on the projected d-spacing calculated in Annexes, these observed rings might be related to the {011}, {002}, {200} and {111} of Ni(Pt)SiGe phase.

In-situ Rs, XRD and TEM characterizations permit to identify the phase sequence for the reaction a 7 nm Ni film with Si$_{0.7}$Ge$_{0.3}$ epitaxial layer as:

$$Ni \xrightarrow{110^{\circ}C-160^{\circ}C} Ni_{31}(Si_{1-z}Ge_z)_{12} \xrightarrow{170^{\circ}C} \delta - Ni_2(Si_{1-y}Ge_y) \xrightarrow{350^{\circ}C} Ni(Si_{1-x}Ge_x) \qquad \text{Eq. III. 6}$$
Additionally, the texture of different phases formed during the reaction between Ni and $Si_{0.7}Ge_{0.3}$ layers have been analyzed in depth through Synchrotron X-ray measurements. The beam energy fixed at 8.2 KeV allows to explore the inter-planes distance comprised between 1.5 Å and 2.5 Å for the $\psi$ angles comprised between 0 and 70°. For experiment details, please refer to the Chapter II of Emilie Bourjot's Ph.D dissertation [6].

After RTA1 at 280 °C with additional selective etching, based on the method reported for the Ni-Si system by Gaudet et al. [189], the $\delta$-phase is then identified through the comparison of diffracted intensity signal as a function of d and $\psi$. Figure III.28 presents the relevant pole figures respectively for $d = 2.00$ Å and 1.90 Å, related to the (013) and (020) $\delta$-phase planes.

On Figure III.28a, at $\psi = 0$, a spot is observed in addition to a ring at $\psi = 58°$. This indicates a (013) fiber texture. In the same way, on Figure III.28b, similar features are observed related to a (020) fiber texture of $\delta$-phase and the planes are oriented parallel to the sample surface.

<figure><img src="image_67.png" /><figcaption>Figure III.28. Pole figures obtained from Synchrotron X-ray measurements for $d = 2.00$ Å (a) and $d = 1.90$ Å (b) respectively after the RTA1 (280 °C for 30 s) annealing and selective etching of a 7 nm Ni film deposited on $Si_{0.7}Ge_{0.3}$ epitaxial layer.</figcaption></figure>

### III.3.1.3 Ex-situ $\theta-2\theta$ XRD and ACOM-TEM analyses on Ni(10 at.% Pt)-$Si_{0.7}Ge_{0.3}$ system

To identify the phases in presence with more accuracy, texture measurements were performed on samples annealed at respectively 260 °C and 350 °C using the same heating ramp as experiments described in subsection III.3.1.3. Despite the very bright source used for this analysis, no peak was detected on the first sample annealed at 260 °C whereas Figure III.25 clearly shows the NiPt consumption up to 180 °C. By analogy to Ni-Si system, as no XRD peak, the $\theta$-Ni$_2$Si phase could be formed (see for details subsection III.2.1).

In the Ni-Ge phase diagram, similar non-stochiometric hexagonal phases are present as the $\epsilon$-Ni$_5$Ge$_3$ phase, with a Ge composition range from 33.8 to 38 at.%, and Ni$_3$Ge$_2$ phase with a Ge composition range from 41 to 43 at.%.

Ex-situ $\theta-2\theta$ XRD diagram obtained after an annealing at 350 °C is presented in Fig. III.29.
<figure><img src="image_68.png" /><figcaption>Figure III.29. Ex-situ θ-2θ XRD spectrum obtained at room temperature after an annealing at 350 °C of a 7 nm Ni(10 at.% Pt) film deposited on Si<sub>0.7</sub>Ge<sub>0.3</sub> epitaxial layer.</figcaption></figure>

2θ angles measured on XRD spectrum for this phase are summarized in the first column of Table III.4. At that point, this pattern corresponds to the Ni<sub>1-w</sub>Pt<sub>w</sub>Si<sub>1-x</sub>Ge<sub>x</sub> compound formed at 300 °C during the in-situ experiments (see Fig. III.26).

<table><caption>Table III.4. Peak identification of the mono-germano-silicide phase based on measured 2θ angles from Figure III.29 and calculated 2θ angles corresponding to the theoretical ones. The last ones are determined from lattice parameters that are calculated using a Vegard's law applied between the NiSi<sub>0.7</sub>Ge<sub>0.3</sub> and PtSi<sub>0.7</sub>Ge<sub>0.3</sub> parameters assuming a 0.9/0.1 ratio ([186]).</caption><thead><tr><td>Measured 2θ (°) (from Figure III.29)</td><td>Calculated 2θ (°)</td><td>(hkl)</td><td>Inter-planes distance d (Å)</td></tr></thead><tbody><tr><td>31.22</td><td>31.23</td><td>002</td><td>2.81</td></tr><tr><td>35.55</td><td>35.45</td><td>111</td><td>2.51</td></tr><tr><td>35.55</td><td>35.63</td><td>102</td><td>2.47</td></tr><tr><td>45.08</td><td>45.09</td><td>112</td><td>1.99</td></tr><tr><td>46.55</td><td>46.53</td><td>211</td><td>1.92</td></tr><tr><td>55.19</td><td>55.08</td><td>020</td><td>1.67</td></tr><tr><td>55.55</td><td>55.46</td><td>013</td><td>1.65</td></tr></tbody></table>

To compare the experimental data to the calculated ones, the Vegard's law (presented in section III.2.1.1) is applied between the Ni(Si<sub>0.7</sub>Ge<sub>0.3</sub>) and Pt(Si<sub>0.7</sub>Ge<sub>0.3</sub>) lattice parameters assuming a 0.9/0.1 ratio (like the initial Ni/Pt ratio).

Hence, it is likely to assume the formation of the mono-germano-silicide phase with full miscibility for the metals and the semiconductors. In this assumption, both the Ni and Pt atoms are set on the same sub-lattice whereas Si and Ge atoms share the same sub-lattice. NiSi, PtSi, NiGe and PtGe crystallize in the orthorhombic structure (Pnma) with comparable lattice parameters and a maximum discrepancy of 10 %, as summarized in Table III.5.

Following this hypothesis, Vegard's law is used to calculate the theoretical 2θ values for the mono-germano-silicide as Ni<sub>0.9</sub>Pt<sub>0.1</sub>Si<sub>0.7</sub>Ge<sub>0.3</sub> compound (reported in Table III.4 in the second column).

<caption>Table III.5. Lattice parameters of NiSi, PtSi, NiGe and PtGe in Pnma orthorhombic structure.</caption>
<table><thead><tr><th>Silicides and Germanides</th><th>a (Å)</th><th>b (Å)</th><th>c (Å)</th><th>References</th></tr></thead><tbody><tr><td>NiSi</td><td>5.18</td><td>3.34</td><td>5.62</td><td>[67]</td></tr><tr><td>NiGe</td><td>5.38</td><td>3.43</td><td>5.81</td><td>[74]</td></tr><tr><td>PtSi</td><td>5.59</td><td>3.60</td><td>5.93</td><td>[62]</td></tr><tr><td>PtGe</td><td>5.73</td><td>3.70</td><td>6.08</td><td>[62]</td></tr></tbody></table>

The agreement between both the theoretical and experimental Bragg peak positions suggests that (i) the last phase to form should be the mono-germano-silicide phase, and (ii) the Pt element is fully integrated in this mono-germano-silicide.

To investigate the texture of mono-germano-silicide, some additional experiments have been provided through ASTAR™ system. The studied samples are made by following the standard 14 nm FD-SOI process flow up to silicide formation and SiN encapsulation. Ni(Pt)Si silicide is formed by the reaction of 10 nm Ni(10 at.% Pt) film with in-situ raised source/drains Si<sub>0.7</sub>Ge<sub>0.3</sub> epitaxial zones. After NiPt deposition, RTA1 is performed, followed by the classical selective etching. Two RTA1 thermal budgets have been studied here at 230 °C and 260 °C during 30 s. RTA2 is applied to form the mono-germano-silicide.

For these two samples, orientation mappings of grains formed after RTA2 are shown in Figure III.30. Only the orientation mappings given in the normal direction of the sample, as aligned on Si(001) planes, and in the normal direction of the TEM lamella, as aligned on the Si(110), are presenting to avoid redundant results. At 230 °C, the mono-germano-silicide layer is thinner than at 260 °C as expected. After a RTA1 at 260 °C the Ni(Pt)SiGe grains exhibit a strong fiber texture as shown in Fig. III.30c. All the grains are almost colored in blue in this direction related to an alignment of (010) planes of Ni(Pt)SiGe layer with the (001) Si direction, as it is clearly identified on the following pole figures deduced from Figures III.30c and d.

<figure><img src="image_69.png" /><figcaption>Figure III.30. ASTAR™ mappings of Ni(Pt)SiGe grains formed by the reaction of a 10 nm Ni(10 at.% Pt) film with Si<sub>0.7</sub>Ge<sub>0.3</sub> epitaxial layer after RTA2 for a RTA1 temperature of 230 °C (a, b) and 260 °C (c, d). Si[001] and Si[110] directions are colored respectively in red and green as described in the color map (e). The Ni(Pt)SiGe grains are colored as given in (f).</figcaption></figure>

In Figure III.31, a fiber texture defined by an alignment of (013) planes of Ni(Pt)SiGe grains with the Si(100) direction is observed. As previously described on XRD pole figures (Figure III.28), this
texture induces a circle on the pole figure for (013) projection. An epitaxial texture is also deduced
from Figure III.30d as (001) and (011) planes are parallel to Si(110) direction.

For Ni(10 at.% Pt)-Si<sub>0.7</sub>Ge<sub>0.3</sub> system after RTA2, the texture of mono-germano-silicide layer
could be described as follows :

- (010) epitaxial texture and (013) fiber texture aligned to the (001) Si<sub>0.7</sub>Ge<sub>0.3</sub> planes.

- (001) and (011) epitaxial texture aligned with the (110) Si<sub>0.7</sub>Ge<sub>0.3</sub> planes.

<figure><img src="image_70.png" /></figure>

Figure III.31. Pole figures extracted from ASTAR™ mappings shown in Figures III.30c and d obtained after the complete silicide process of a 10 nm Ni(10 at.% Pt) film deposited on Si<sub>0.7</sub>Ge<sub>0.3</sub> epitaxial layer. Please note that only the Ni(Pt)SiGe diffraction patterns are considered here contrary to the XRD pole figures which integrate the signal coming from the silicide layer and the substrate.

III.3.1.4 Pole figures and ACOM-TEM analyses on Ni(15 at. % Pt)-Si<sub>0.7</sub>Ge<sub>0.3</sub> system

The texture of different phases formed during the reaction between Ni(15 at.% Pt) and Si<sub>0.7</sub>Ge<sub>0.3</sub>
layers have been analyzed in depth through synchrotron X-ray measurements. The beam energy fixed
at 8.2 KeV allows to explore the inter-planes distance d, comprised between 1.5 Å and 2.5 Å for the ψ
angles comprised between 0 and 70°. For experiment details and methodology of simulations with
Carine, please refer directly to Emilie Bourjot's Ph. D dissertation [6].

After a RTA1 at 280 °C during 30 s followed by selective etching, diffraction patterns appear
between the d-spacing of 1.96 Å and 2.08 Å. Furthermore, as displayed in the Figure III.32, for
d = 2.02 Å, several diffraction marks noted c1, c2 and c3 are detected at ψ = 29°, ψ = 51°, and ψ = 65°
respectively.