# Investigation on the Short-Circuit Behavior of HV-SiC-MOSFETs in Quasi Series Connection

Felix Gesele, Christian Bäumler, Thomas Basler, Thomas Brückner

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Felix Gesele, Christian Bäumler, Thomas Basler, Thomas Brückner. Investigation on the Short-Circuit Behavior of HV-SiC-MOSFETs in Quasi Series Connection. The 26th European Conference on Power Electronics and Applications, GDR SEEDS France & EPE Association, Mar 2025, Paris, France. 10.34746/epe2025-0323 . hal-05073990

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# Investigation on the Short-Circuit Behavior of HV-SiC-MOSFETs in Quasi Series Connection

Felix Gesele,<fnref n="1" /> Christian Bäumler,<fnref n="2" /> Thomas Basler,<fnref n="2" /> and Thomas Brückner<fnref n="1" />

E-Mail: felix.gesele@unibw.de, christian.baeumler@etit.tu-chemnitz.de, thomas.basler@etit.tu-chemnitz.de, thomas.brueckner@unibw.de

URL: https://www.unibw.de, https://www.tu-chemnitz.de

## Acknowledgement

This research work has been carried out within the project DEFINE and is funded by dtec.bw Digitalization and Technology Research Center of the Bundeswehr, which we gratefully acknowledge. dtec.bw is funded by European Union NextGenerationEU.

## Keywords

«Gate-drive», «Short circuit», «SiC MOSFET», «Parasitics», «Wide Bandgap devices».

## Abstract

This paper investigates the short-circuit behavior of SiC MOSFETs in a quasi series connection, which can be found in several topologies with three or more switches in a commutation loop. In the event of a device failure, this could offer the opportunity to select a device which had seen less stress up to this point to turn off the short circuit, and thus improve the (general) failure handling. Besides a theoretical analysis, short-circuit tests for such configurations are carried out with state-of-the-art 3.3-kV SiC MOSFET half-bridge modules. The analysis focuses particularly on the voltage distribution between the switches, examining the influence of different physical setups and device parameters.

## Introduction

Several power converter topologies incorporate commutation loops with three or more switches, such as three-level (Active-)Neutral-Point-Clamped ((A)NPC) Converters [1] or certain sub-modules of Modular Multilevel Converters (MMC) like Double-Zero Submodules (DZSM), Semi Full-Bridge, and Double-Zero-Double-Connected Submodules (DZDCSM) [2]. Depending on the topology, this might open up unique opportunities during fault conditions. Assume a

common failure scenario, a device breakdown (of an IGBT or MOSFET) during an active turn-off transient, resulting in a short circuit during the subsequent turn-on transient. In a commutation loop with *n* switches, there would still remain *n* - 1 devices that can potentially limit and turn off the short-circuit (SC) current, and thus bear the potential of an increased reliability. To safely detect the SC and optimize the protection strategy in such case, the behavior of the quasi series connected devices in SC condition needs to be understood first. This, includes the voltage and energy sharing between the devices.

With the introduction of Silicon Carbide (SiC) MOSFETs in medium-voltage applications, the demands on fast SC detection and handling have increased. SiC MOSFETs, with their smaller chip sizes and lower thermal capacitances but higher current densities, generally have a shorter SC withstand time (*t*<sub>SC</sub>), ranging from a few hundred nanoseconds to a very few microseconds.

Therefore, this paper investigates the SC behavior of quasi series connected MOSFETs on the example of a state-of-the-art 3.3-kV SiC MOSFET module. Infineon's FF2000UXTR33T2M1 has been chosen, which is being introduced in high-power applications such as energy distribution and traction systems.

Section 2 briefly describes two different SC scenarios and the corresponding test setup, followed by a brief recap of the theoretical semiconductor device behavior. Selected results of an extensive measurement campaign are described in Section 3, including an explanation of the results and a simulative validation of the discussed points.

## Short-Circuit Scenarios

Two scenarios of a short circuit involving two quasi series connected devices is illustrated using the DZSM of an MMC. Figure 1 presents the circuit diagram, showing current paths for two po-

<footnote n="1">¹Universität der Bundeswehr München, Neubiberg, Germany</footnote>

<footnote n="2">²Technische Universität Chemnitz, Chemnitz, Germany</footnote>
<figure><img src="image_2.png" /><figcaption>Figure 1: Possible short circuit scenarios in DZSM caused by a turn-off failure during commutation</figcaption></figure>

tential SC cases. In both situations, an undetected turn-off failure of an active switch (MOSFET) is assumed, leading to a short circuit during the subsequent turn-on transient within the same commutation loop. The load-current path $i_{pre}$ before the fault and the SC loop are marked in yellow and red, respectively in Fig. 1.

In the case shown in Fig. 1a), the sequence of events unfolds during the intended transition of the DZSM from an output voltage of $+V_C$ to the bypass state (zero output voltage). Prior to this transition, with the load current following the "yellow" path, T1 and T4 are in the off state, and T2, T3, and T5 are in the on state. When T5 is turned off, it is assumed to fail into a drain-source short during the transient. After the dead time, T4 is turned on, closing the SC loop marked in red. Since T3 is already conducting the load current $i_{pre}$, this results in a short circuit type II (SC II) for T3 and type I (SC I) for T4 (per definitions following [4]).

Figure 1b) shows a second scenario, occurring during the transition of the DZSM from the bypass state (zero output voltage) to a negative output voltage $-V_C$. In this case, T3 fails during its turn-off transient, and the SC loop is closed when T5 is turned on. As T5 initiates the short circuit, it experiences a SC I, while the SC type for T4 is to be discussed. According to [4] and with reference to [7], the SC type for T4 depends on

whether the channel is conducting at the moment of SC onset (=SC II with negative initial load current) or the body diode is conducting current (closed channel) and has to release the stored charge carriers during the SC event via a reverse-recovery process (= classical SC III). Subsequently, the condition is just named SC III.

## Experimental Setup

These different cases, where an initial device breakdown leads to a SC during an active turn-on transient, can be reproduced using a double-pulse setup. The failed device is then assumed to form an ideal short and only two other devices remain in the commutation loop. Two scenarios can be distinguished:

* combination of SC I / SC II ([5], [7]) according Fig. 1a)

* combination of SC I / SC III ([6], [7]) according Fig. 1b)

Figure 2 shows the test circuit along with the possible combinations of SC types and the corresponding pulse patterns for the respective switches.

In Fig. 2a) the load inductor is connected in parallel to the high-side (HS) switch T1. This configuration allows the investigation of two combinations: pulse pattern 1 (PP1) results in SC I for T1 and SC II for T2, PP2 results in SC III for T1 and SC I for T2.

If the load inductor is connected across the low-side (LS) switch T2, see Fig. 2b), the SC scenarios of Fig. 2a) are swapped for the respective switches: PP3 results in the combination SC I for T2 and SC II for T1, while PP4 results in SC III for T2 and SC I for T1.

In Fig. 2, the color coding of the current paths corresponds to the respective pulse sequences. In PP2 and PP4, the body diode of T1 and T2, respectively, is shortly conducting within the dead time of 100 ns after $t_1$, where both quasi serial switches are off. During this time, a charge-carrier plasma is built up within the switch. In order to keep the experiment as close as possible to the application, after the 100 ns dead time the channel is turned on in reverse conduction mode (purple bar from $t_1$ to $t_2$ in pulse pattern PP2 and PP4) for a fixed pulse length of 6µs, which is sufficient for the plasma to recombine before the subsequent short circuit is initiated. It has to be noted that 100 ns bipolar conduction time is not sufficient to built-up a complete and stable plasma for this high-voltage class device.
<figure><img src="image_3.png" /><figcaption>Figure 2: Half-bridge test setup and corresponding pulse pattern for different SC types</figcaption></figure>

To ensure a minimal stray inductance in the com-
mutation loop, most high-power SiC MOSFET
modules are designed as half-bridge modules, as
the device tested in this paper. For the implemen-
tation of the DZSM in Fig. 1, this causes some
challenges. If the outer switches, T1/T2 and
T3/T4, are realized as half-bridge modules,
another solution for T5 is needed, e.g. a half-
bridge module with one switch bypassed.
However, this paper focuses on the voltage distri-
bution within one half-bridge module, and T1 and
T2 in the test setup of Fig. 2 always correspond to
the HS and LS switch within one half-bridge
module, respectively.

Expectation based on Output
Characteristics

Before discussing the measurement results, it is
crucial to review the factors influencing voltage
sharing. For MOSFETs, the transfer and output
characteristics remain valid at all times. At chip
level, the drain current depends on gate-source

voltage, drain-source voltage and device temper-
ature, solely. Assuming identical chips without
parameter variations, the voltage sharing during
short circuit in series-connected devices is
governed by four key factors:

• gate-source voltages (vGS)

• junction temperatures (T_j)

* initial load current ($i_{\text{pre}}$) in the
  SC II / SC III device vs. SC I device

* initial drain source voltage level at the beginning of the short circuit

If the gate voltages and junction temperatures are assumed to be identical, a simple rule applies: a device in SC II takes more drain source voltage when paired with a SC I device, and a device in SC I takes more voltage when paired with a SC III device. However, during the SC transient, the junction temperatures and gate voltages may diverge, altering the voltage distribution. This effect is briefly explained on hand of a SiC-MOSFET output characteristic shown in Fig. 3. In Fig. 1a), T3 undergoes SC II when T4 turns on into SC I. If T3 and T4 have identical temperatures and vGS, both follow the same output characteristic (e.g., Tj,1), with T3 taking the higher voltage (v2) vs. T4 (v1) due to the difference in initial load current (ipre). If T4's temperature rises (Tj,2 > Tj,1), voltage distribution may reverse, shifting T4's voltage to v3, surpassing v2 of T3. The total voltage (v3 + v2) remains constant, dictated by the external supply voltage minus the inductive voltage drop, causing shifts along the output characteristic.

Compared to silicon IGBTs, SiC-MOSFETs have a smoother transition into the pinch-off region and also have a more pronounced rise in saturation current at higher drain-source voltages, reducing the influence of the initial load current on the voltage distribution. This is primarily due to the JFET narrowing effect and the Drain-Induced Barrier Lowering (DIBL) effect [8].

<figure><img src="image_4.png" /><figcaption>Figure 3: Typical SiC-MOSFET output characteristic for one gate-source voltage</figcaption></figure>
<figure><img src="image_5.png" /><figcaption>Figure 4: Short-circuit behavior of a single switch (LS switch, $T_j = 25°C$)</figcaption></figure>

## Experimental results

### Short-Circuit Behavior of a Single Switch in the Half-Bridge Module

As a reference, the waveforms for a SC I on a single switch of the investigated half-bridge module are shown in Fig. 4. In this measurement, the capacitor voltage is applied via the DC terminals of the module, with the HS switch turned on with a very high gate voltage ($v_{GS} > 22V$), such that its influence on the SC behavior can be disregarded. The LS switch of the module serves as the device under test. The total stray inductance in the SC loop amounts to approximately 35 nH.

The current rises with an initial slope exceeding 8 kA/µs, reaching a saturation level more than eight times the nominal current after approximately 4 µs. After a current peak, the current decreases due to the increasing device temperature. The relatively slow di/dt during the whole short circuit is a result of a negative feedback in the gate loop, intentionally designed into the power module to facilitate SC handling [3]. This behavior may as well influence the voltage sharing in series-connected devices and must be taken into consideration. The gate-source voltage $v_{GS}$ is measured at the Kelvin terminals, the electrically closest accessible point towards the chip gates. It has to be noted, that – quite obviously – it must be different to the voltage at the chip gates, due to module-internal parasitics in the gate path and internal gate resistors, as will be quantified later.

### Short-Circuit Behavior in Quasi Series Connection

The first measurement results are shown in Fig. 5, which were recorded using a test setup according

<figure><img src="image_6.png" /><figcaption>Figure 5: Short-circuit measurement within one half-bridge module ($T_j = 25°C$); combination of SC I (HS switch) and SC II (LS switch)</figcaption></figure>

to Fig. 2a) with PP1, the same initial temperature ($T_j = 25°C$) for both switches and an initial load current of $i_{pre} = 1100$ A, just above the rated current of the module ($i_{rated} = 1000$ A). The voltage distribution between the two switches behaves as expected, based on their output characteristics. Initially, T2 is conducting, while T1 is blocking the voltage. At the moment when T1 is turned on (shortly after its measured gate voltage rises) and the short circuit occurs ($t_0$), the voltage at T1 drops because the stray inductance in the SC loop requires voltage to support the current transient. During this period, T1 is dominant and dictates the current, which rises with a di/dt of more than 8 kA/µs, similar to a normal turn-on event. When the current through T2 reaches twice the nominal current ($t_1$; $t_1-t_0 = 350$ ns), the di/dt decreases, and T2 begins to take over voltage from T1 with an initial $dv_{DS}/dt$ of more than 4 kV/µs, which gradually decreases. Approximately 1 µs after $t_1$, the LS switch (T2) has taken over most of the voltage ($t_2$) and governs the current rise until the turn-off command is issued. The turn-off command for T2 occurs approximately 10 ns before T1, causing T2 to start turning off the SC current and absorbing the energy from the stray inductance, which results in a voltage peak. Since this 10 ns lead is insufficient for T2 to completely turn off the short circuit, T1 begins to assist in the turn-off process by sharing the voltage. After the short circuit is completely turned off, T2 blocks the full voltage, since the load current is free-wheeling through the body diode of T1.
<figure><img src="image_7.png" /><figcaption>Figure 6: Short-circuit measurement within one half-bridge module ($T_j = 25°C$); combination of SC I (HS switch) and SC III (LS switch)</figcaption></figure>

For the next measurement, shown in Fig. 6, the load inductor is connected across T2; the pulse pattern is PP4 (cf. Fig. 2b)). T1 starts in the blocking mode, again. T2 is in unipolar reverse conduction mode (the channel is active), as indicated in Fig. 2b). The short circuit is triggered by turning on T1. After a short delay, the current begins to rise ($t_0$), with an initial $i_D/dt$ of 7 kA/µs, which causes a voltage drop across T1 due to the stray inductance in the SC loop. After a short period of time, T2 starts to take over the voltage, with an initial $dv_{DS}/dt$ of 1,7 kV/µs ($t_1$). The slope gradually decreases until $t_3$, when the direction of the slope changes. At this point, the voltage distribution between T2 and T1 has reversed compared to the initial voltage distribution, the amount is about $v_{DS,T2}/v_{DS,T1} = 65\% / 35\%$. Following the previous theoretical considerations, T1 should take more voltage, because it has a higher initial load current ($i_{pre,T2} < 0$ A; $i_{pre,T1} = 0$ A) and a stronger self-heating up to the point $t_2$ can be assumed as well. Nevertheless, there is some other effect which makes T2 taking over voltage from T1 and holding it for the most time of the SC event.

## Comparing Different Initial Load Currents

A set of measurements with initial load current varying from 800A to 2000A is displayed for each of the four possible pulse patterns in Fig. 2. For all data shown in this section, the experiments were performed with a pre-tempered junction temperature of $T_j = 25°C$. Figure 7 shows a set of

<figure><img src="image_8.png" /><figcaption>Figure 7: Series of short-circuit measurements with varying initial load currents in the experimental setup like Fig. 2a); $T_j = 25°C$</figcaption></figure>

a) Pulse Pattern: PP1

b) Pulse Pattern: PP2

measurements with the load inductor parallel to T1 (cf. Fig. 2a)).

In Fig. 7a), T2 starts in conduction mode while T1 starts in blocking mode and triggers the short circuit. Initially, T2 has no voltage but gains it during the event. There is a clear kink in the current curve at $t_1$ ($t_1-t_0 = 350$ ns). At this point, T1's voltage drops while T2 rapidly takes over, which indicates T2 entering the pinch-off region. T2 holds the voltage during the whole short circuit. All the different initial load currents in T2 converge during the short circuit to one value, which indicates that T2 governs the current (cf. $i_{D,T2}$ at $t_4$). As T2 limits the current while the load inductor acts as a current source, T1's current must decrease as the initial load current increases. Kirchhoff's Current Law gives:

$$i_{D,T1} = i_{D,T2} - i_{pre} \quad (1)$$
<figure><img src="image_9.png" /><figcaption>Figure 8: Series of short-circuit measurements with varying initial load currents in the experimental setup like Fig. 2b); Tj = 25°C</figcaption></figure>

a) Pulse Pattern: PP3 b) Pulse Pattern: PP4

In Fig. 7b), T2 starts with full voltage due to the pulse pattern, while T1 is in reverse conduction. The short circuit is triggered by T2's turn-on, and T2 dictates the current shape throughout the whole SC event, with T1 always following equation (1).

In both cases, the voltage distribution stabilizes at the final value, with T2 taking almost all the voltage, leaving only a small vDS,T1.

Figure 8 shows the results for the load inductor in parallel to T2 (PP3 in Fig. 8a), PP4 in Fig. 8b)). Ideally, if T1 and T2 were perfectly symmetric, the behavior should mirror Fig. 7. However, this is not the case.

In Figure 8a), T2 starts in blocking mode, while T1 is conducting. Since T1 is in SC II and T2 is in SC I, the drain current of T1 remains higher than T2's. The equation (1) has to be changed to:

$$i_{D,T1} = i_{D,T2} + i_{Pre} \quad (2)$$

caused by the different physical test setup. T2 triggers the short circuit ($t_0$) and during the whole short-circuit event it keeps the higher share of the voltage. Nevertheless, the start of the short-circuit event is a normal SC I turn-on behavior, but at $t_1$, T1 begins taking over some voltage of T2 reaching the pinch-off region. Interestingly, for $i_{pre} < 1,5 i_{rated}$, T1 gives voltage back to T2 at $t_2$, whereas for higher initial load currents, T1 takes the more voltage, the longer the short-circuit event persists.

In Figure 8b), T1 undergoes a SC I in combination with a SC III of T2. T1 has a normal turn-on behavior ($t_0$) and the current of T2 reverses and rises with a $di_D/dt > 7$ kA/µs until it reaches 3,5 times the rated current at $t_1$. At this point, T2 takes over the voltage with an average initial $dv/dt$ of 1,6 kV/µs. The voltage slope depends on the initial load current, decreasing until $t_2$, where it reverses and T1 regains voltage again, until the end of the short-circuit event.

The voltage distribution in Figs. 7 and 8 cannot be explained under the assumption of identical junction temperatures and gate-source voltages ($v_{GS}$). If these were equal, T1 should take more voltage than T2 in Fig. 8, which contradicts the observations.

To analyze the impact of the junction temperature, measurements were performed at 25°C, 75°C, and 165°C for both switches in a half-bridge module, sharing the same cooling plate. The voltage distribution from these tests, measured just before turn off ($t = 4$ µs), is plotted in Fig. 9 against the normalized initial load current ($i_{pre}/i_{rated}$) of the measurement. Figure 9a) shows the results for the load inductor parallel to T1 (cf. Fig. 2a)), while Fig. 9b) corresponds to the load inductor parallel to T2 (cf. Fig. 2b)). On the left side, there is always a combination of SC I and SC III, while the combination of SC I and SC II is on the right side.

Comparing both setups, in Fig. 9a) (load inductor parallel to T1), T2 takes nearly all the voltage at the end of the short-circuit event, independent of temperature or initial load current ($i_{pre}$). Conversely, Fig. 9b) (load inductor parallel to T2) shows a different voltage distribution pattern, where the different SC combinations result in their own shape:
<figure><img src="image_10.png" /></figure>

<figure><img src="image_11.png" /><figcaption>Figure 9: Voltage distribution between HS switch and LS switch in a half-bridge module for the investigated short-circuit combinations at the end of the SC event at $t = 4$ µs</figcaption></figure>

a) load inductor parallel to HS switch (cf. Fig. 2a)

b) load inductor parallel to LS switch (cf. Fig. 2b)

* Right side (SC II of T1 & SC I of T2): At low $i_{pre}$, T2 takes ~90% of the voltage. As $i_{pre}$ increases, T2's voltage decreases non-linearly, reaching an even ~50/50 split at twice the nominal current.

* Left side (SC I of T1 & SC III of T2): For small negative $i_{pre}$, T2 takes ~80% of the voltage. As negative current increases, T1's voltage rises, crossing T2's voltage. At very high negative $i_{pre}$, T2 takes the most voltage.

While the initial MOSFET temperature affects voltage distribution quantitatively, the qualitative shape remains unchanged. But: in SC III (T2) & SC I (T1), higher temperatures shift more voltage to T1, whereas in SC I (T2) & SC II (T1), higher temperatures increase voltage on T2.

<figure><img src="image_12.png" /></figure>

<figure><img src="image_13.png" /><figcaption>Figure 10: Normalized energy distribution between HS switch and LS switch in a half-bridge module for the investigated short-circuit combinations at the end of the SC event at $t = 4$ µs</figcaption></figure>

a) load inductor parallel to HS switch (cf. Fig. 2a)

b) load inductor parallel to LS switch (cf. Fig. 2b)

Fig. 9 shows a gap at zero $i_{pre}$ due to a pulse pattern change at the x-axis crossing. A finer measurement grid improves accuracy near zero $i_{pre}$. However, in general it should be noted that the short-circuit current is measured with the same sensor as $i_{pre}$ (PEMuk CWTMiniHF 60; Rogowski coil with 12 kA peak current). This leads to relatively poor accuracy in very small measuring ranges ($i_{pre}$). Beside the voltage distribution, the energy distribution is considered, as both switches carry short-circuit current in series, though SC II & SC III introduce deviations. The energy is calculated by integrating the product of absolute voltage and current over $t = 0–4$ µs (cf. Figs. 5–8), excluding turn-off energy to avoid an artificial offset. Since the total energy varies across the cases, the results are normalized by dividing each transistor's energy by the total
energy of both transistors. The resulting energy distribution is shown in Fig. 10.

## Explanation of Different Voltage Distribution

The voltage distribution between two quasi-serial MOSFETs depends on the operating points of the two devices, defined by their individual gate-source voltages ($v_{GS}$) and their individual junction temperature ($T_j$), both of which determine their relationship between drain current ($i_D$) and drain-source voltage ($v_{DS}$). During short-circuit events, these parameters undergo highly dynamic processes, resulting in time-dependent and individual values.

The dynamics of $v_{GS}$ are influenced by three key factors:

* impedance of the gate circuit

* reverse-transfer (Miller) capacitance

* common-source passives (inductive and resistive).

Figure 11 illustrates the investigated gate circuit, which will be analyzed in the following chapters in relation to these key factors.

<figure><img src="image_14.png" /><figcaption>Figure 11: schematic model of the gate circuit</figcaption></figure>

### Impedance of Gate Circuit

The impedance of the gate circuit, internal due to the module package and external in the gate-drive circuit, determines to which extend the impact from the common-source passives and the Miller effect are translated into changes of the gate-source voltage $v_{GS}$.

A second important point to mention here is the measurement of the gate voltage $v_{GS}$. As shown in Fig. 11, the closest possible electrical measurement point is at the Kelvin terminals of the module. The resistance ratio $R_{g,int}/R_{g,ext} \approx 1$ and the inductance ratio $L_{g,int}/L_{g,ext} > 2$ result in a decoupling of the measured gate signal $v_{GS,meas}$ from the real chip gate's $v_{GS}$.

## Reverse-Transfer Capacitance / Miller Effect

The Miller effect, describing the coupling of the $dv_{DS}/dt$ into the gate loop via the gate-drain capacitance ($C_{GD}$) has to be considered, too. In a typical SC I case (cf. Fig. 5), the Miller effect is small due to the lack of significant $dv_{DS}/dt$, as $v_{DS}$ primarily drops across the SC loop's stray inductance, but must $v_{DS}$ still remains. However, in cases of SC II or III, where high $dv_{DS}/dt$ occurs, the Miller effect becomes more significant. In SC II or SC III, with no initial voltage (except $i_D * r_{DS,on}$), $dv_{DS}/dt$ increases gate-source voltage, allowing more drain current.

In this investigation, SC I always pairs with SC II or SC III. Without parasitics, voltage distribution follows the pre-current condition of: $v_{DS,SC II} > v_{DS,SC I} > v_{DS,SC III}$. In the combination of SC I and SC III, initial load current and the Miller effect reinforce voltage splitting, whereas in the combination SC I and SC II, they counteract each other. However, recent investigations indicate that the Miller effect has a relatively small impact in SiC MOSFETs compared to IGBTs, due to the smaller $Q_{GD}$ relative to $Q_{GS}$, combined with the significant influence of the DIBL effect [7] resulting in smoother transitions into the pinch-off region, limiting the $dv/dt$.

### Common-Source Passives

The term *common-source passives* refers to all equivalent passive components shared between the gate and power loops, including an equivalent resistance (mainly from bond wires) and inductive effects. The inductive effects arise from:

* self-inductance of source-bond wires and common copper traces on the DCB up to the Kelvin-source lead,

* magnetic coupling between power and gate leads, determined by module layout.

During a short circuit, high $di_D/dt$ induces a positive voltage across $L_{CS}$, which acts as a voltage source in the gate loop. This may temporarily discharge the gate capacitance ($C_{GS}$), affecting the switch behavior. The resistive component also acts as a voltage source in the gate loop but depends on drain current amplitude rather than $di_D/dt$. As shown in Fig. 5, the $di_D/dt$ decreases, so the SC current continues rising. Consequently, the $L_{CS}$-induced voltage decreases while the $R_{CS}$-induced voltage increases with the SC duration. The measured $di_D/dt$ and $i_D$ values along with typical common-source parasitics, allow the esti-
mation of $v_{CS}$. Assuming 0,5 nH inductance and $di_D/dt$ of 5-10 kA/µs, the expected voltage is 2,5-5 V. For a resistance 100-500 µΩ and a 10 kA short-circuit current, the voltage ranges from 1-5 V. These values align with practical considerations, given bond-wire cross-sections and the high number of paralleled dies inside the module.

## Comparison of Different Parasitics for HS vs. LS switch

As indicated in the previous section, the voltage deviation between the HS and LS switches is influenced by the impedances of the gate circuit. The specific values for the investigated module have therefore been determined and are given in Table 1. The internal gate inductance values $L_{G,int}$ are taken from [9], while the common-source inductance values $L_{CS}$ have been evaluated through additional measurements. These measurements follow the method proposed in [10]. An AC-current signal with a fixed frequency is applied to the MOSFET which is turned on via a very high external gate resistor ($R_{G,ext}$). This resistor efficiently blocks any current in the gate path and the voltage change measured across the device's Kelvin terminals ($v_{GS,meas}$ in Fig. 11) is equivalent to the voltage imposed by the common-source parasitics. By evaluating amplitude and phase of the two signals, $L_{CS}$ and $R_{CS}$ can be extracted. For the device under investigation, the values of the parasitics are in a range that requires a high frequency (cf. Eq. (3)) or a large current amplitude for sufficient stimulation to get a measurable response.

$$v_{GS,meas} = v_{GS} + Z_{parasitics} \cdot i_D = v_{GS} + (j \cdot \omega \cdot L_{CS} + R_{CS}) \cdot i_D \quad (3)$$

Because there is no such AC-source available, which has enough power at a high frequency, an alternative stimulus is chosen. The commutation of a turn-on / turn-off transition of a second switch in series connection can be used for this method.

<table><caption>Table 1: Extracted parasitic parameters of investigated module package</caption><thead><tr><th></th><th>L<sub>G,int</sub></th><th>L<sub>CS</sub></th><th>R<sub>CS</sub></th></tr></thead><tbody><tr><td>HS switch (T1)</td><td>80 nH</td><td>820 pH</td><td>513 μΩ</td></tr><tr><td>LS switch (T2)</td><td>70 nH</td><td>790 pH</td><td>686 μΩ</td></tr></tbody></table>

Interestingly, the gate-inductance values appear to be quite large and differ between the HS and

LS switch. On one hand, a large gate inductance intensifies the Miller effect, on the other hand it would help to block HF gate currents and this slowing down the impact of common-source parasitics. The differences between the $L_{CS}$ appear to be negligible, however, the $R_{CS}$ differ by more than 25%. Given the large SC amplitudes, a notable impact on the effective gate-source voltage can be expected.

## Verification by Simulation

In a second step, the behavior of the quasi series-connected devices is investigated by a Spice simulation with a compact model, to validate the effects discussed above and to compare the measurement results with the simulation.

The setups from Fig. 2, including corresponding pulse patterns PP1...4, were established in LTSpice®. Unfortunately, no full-matching compact simulation model was available for the investigated power module. As an alternative to visualize the impact of different common source components, as they are present in the power module, a 2 kV SiC compact model was utilized. The model is based on IMYH200R012M1H, TO-247 package with four leads from Infineon [12]. Different simulation cases were accomplished according to Table 2:

<table><caption>Table 2: Overview of values of common source passives used in the simulation scenarios
Case #1: Symmetric $L_{CS}$ and $R_{CS}$ for HS and LS
Case #2: Asymmetric $L_{CS}$
Case #3: Asymmetric $L_{CS}$ and $R_{CS}$</caption><thead><tr><th></th><th>Case #1</th><th>Case #2</th><th>Case #3</th></tr></thead><tbody><tr><th>R<sub>CS(HS)</sub></th><td rowspan="2">513 μΩ</td><td></td><td>513 μΩ</td></tr><tr><th>R<sub>CS(LS)</sub></th><td></td><td>686 μΩ</td></tr><tr><th>L<sub>CS(HS)</sub></th><td rowspan="2">790 pH</td><td>790 pH</td><td>790 pH</td></tr><tr><th>L<sub>CS(LS)</sub></th><td>820 pH</td><td>820 pH</td></tr></tbody></table>

Within the power module, much higher current slopes and amplitudes are present, as it would be the case for a simulation with a single-chip compact model for high-side and low-side. To account for this, passive components from table 2 were scaled by a factor of 32. (To take 32 compact models in parallel would have the same effect but to the disadvantage of a highly increased simulation time). The value 32 accounts for the amount
<figure><img src="image_15.png" /><figcaption>Figure 12: Simulation of voltage distribution for quasi-serial short-circuit events for different case studies.</figcaption></figure>

a) load inductor parallel to HS switch (cf. Fig. 2a)) b) load inductor parallel to LS switch (cf. Fig. 2b))

Case #1: Symmetric common-source passive for HS and LS Case #2: Asymmetric common-source inductance

Case #3: Asymmetric common-source inductance and resistance

of parallel SiC MOSFET dies for each, high- and low-side, within the power module.

The voltage distribution for different simulation cases is depicted in Fig. 11. In case #1, a symmetric layout with equal common-source passives for high- and low-side, the voltage distribution is mirrored by exchanging the position of the load inductance. A slight asymmetry is provoked, if the asymmetric common-source inductance is considered, as indicated by case #2. However, this asymmetry does not account for the measured distributions according to Fig. 9. Once the asymmetric common-source resistance is considered, as for case #3, the simulated voltage distribution follows qualitatively the trend of the measurement.

Conclusion

The behavior of 3.3-kV SiC MOSFETs in a quasi series connection is investigated. The voltage sharing between the devices is governed by their gate voltages, junction temperatures, and initial load current of devices in SC II or SC III conditions. However, the measurement results do not match the theory that the device with the higher initial load current should take the most of the voltage. The experiments carried out on a state-of-the-art half-bridge module revealed a strong

asymmetry with respect to the voltage sharing between HS and LS switches, independent of current and temperature conditions. This asymmetry can be attributed to the internal module design, especially the impact of common-source parasitics, as could be underlined by Spice based simulations.

These conditions must be considered when designing SC detection and protection circuits. Further investigations will be directed on methods to influence or balance the device stresses during the SC, as well as a simulative analysis of the quantitative impact of the parasitic effects.

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