# Nonlinear modelling of AlN/GaN HEMT accounting for self-biasing effect during RF step stress: analysis and hard-SOA

N. Said, Damien Saugnon, Kathia Harrouche, F Medjdoub, Nathalie Labat, Nathalie Malbert, Jean-Guy Tartarin

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N. Said, Damien Saugnon, Kathia Harrouche, F Medjdoub, Nathalie Labat, et al.. Nonlinear modelling of AlN/GaN HEMT accounting for self-biasing effect during RF step stress: analysis and hard-SOA. 35th ESREF, Sep 2024, Parma (Italie), Italy. hal-05353524

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# Nonlinear modelling of AlN/GaN HEMT accounting for Self-biasing effect during RF step stress: analysis and Hard-SOA

N. Said<sup>a,b,*</sup>, D. Saugnon<sup>a</sup>, K. Harrouche<sup>c</sup>, F. Medjdoub<sup>c</sup>, N. Labat<sup>b</sup>, N. Malbert<sup>b</sup>, J.G. Tartarin<sup>a</sup>

<sup>a</sup> Systems Analysis and Architecture Laboratory, LAAS -CNRS, Toulouse, France

<sup>b</sup> Material to System Integration laboratory, IMS, Talence, France

<sup>c</sup> Institute of Electronics, Microelectronics and Nanotechnology, IEMN -CNRS Lille, France

## Abstract

In this study, we investigate the non-linear (NL) behavior of AlN/GaN HEMT under gain compression technologies when submitted to 10 GHz single-tone RF-step stress, crucial for millimeter-wave power application robustness. We evaluate AlN/GaN transistors, targeting high-power amplifiers with operating frequencies above 30 GHz. We present here an original method that includes, in a unique NL expression, the varying self-biasing effect caused by step-stress sequences. This methodology serves as a tool for comparative analysis across various technological variants and transistor geometries post RF stress. The step-stress are conducted on HEMT in transistor saturated mode and in diode configuration alone, to assess the physical origins and location of the critical SOA of these devices. We identify the mechanism of failure as stemming from the degradation of the Schottky gate when subjected to critical RF power levels, due to its constrained capacity to handle power signals exceeding 18 dBm. Furthermore, we highlight the remarkable RF robustness of this technology, achieving gain compression of around 10 dB without degradation.

## 1. Introduction

Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) stands out as an outstanding candidate for microwave and mmWave applications like radar, military, 5G and 6G telecommunication uses [1]. Tapping into higher frequencies for these technologies can be achieved by gate length ($L_G$) downscaling. But, shrinking $L_G$ comes with its own set of challenges, including keeping the control on short-channel effects to maintain the device performance. To this end, a complete redesign of the AlGaN/GaN epitaxial stack and device structure is required to overcome the limitations of the critical AlGaN barrier thickness and the resulting short-channel effects [2]. The reduction of $L_G$ must be accompanied by a downscaling of the epi-layer, which consists of bringing the gate contact closer to the channel and reducing the channel thickness, altogether to ensure strong confinement of the electrons and high electron density in the 2D-Electron-Gas (2DEG). AlGaN barrier substitution with Ultra-Wide Band Gap (UWBG) AlN, InAlGaN or ScAlN already showed promising results [3-5]. However, the robustness and reliability of these UWBG materials are still under evaluation. The ultrathin AlN/GaN shows great potential for mmWave power applications with PAE of 70% at 40GHz [6]. We assess here, the RF-robustness of AlN/GaN technology via power-step stress tests at 10 GHz. The aim is to evaluate the reliability and identify both strengths and weaknesses when operating under severe RF-conditions.

## 2. Experimental details

The AlN/GaN HEMT under test are fabricated using MOCVD on a 4-inch of SiC substrate. The three different technological variants in Fig. 1 are developed by modifying the GaN undoped channel thickness, the carbon concentration in the GaN buffer and by adding an AlGaN back-barrier (structure E). Structures A and B exhibit the same epitaxy but have different GaN channel thicknesses (100 nm and 150 nm, respectively) while structure E features GaN channel thickness of 150 nm, and a lower C-doped GaN buffer concentration (5×10<sup>18</sup> cm<sup>-3</sup>). Finally, a 3 nm-AlN barrier is used in all structures. More details on the fabrication process can be found in [6].

<figure><img src="image_2.png" /><figcaption>**Fig. 1.** Schematic illustration of different stacked layers of AlN/GaN on SiC epitaxial structures.</figcaption></figure>

Accelerated step-stresses under 10 GHz RF signal are applied to devices featuring gate length of $L_G=100$ nm. All measurements were conducted under initial biasing state of $I_{DS}=300$ mA/mm (near the maximum of transconductance $G_m$). Subsequently, an RF signal at 10 GHz (with a generator impedance of 50 ohms) is applied to the gate of the transistors, with power levels ranging from -10 dBm to +25 dBm by +1 dBm
increments, with a step duration of 1 minute. We follow the evolution of the DC and RF parameters, by a complete I(V) measurement before and after the stress test, and by tracking I<sub>DS</sub>, I<sub>GS</sub>, P<sub>in</sub> and P<sub>out</sub> during the steps sequences. Fig. 2 presents the fully automated RF stress experimental workbench used. We calculate the power ratio by measuring the power at the probes level of the output and input of the Device Under Test (DUT), after correcting the different losses in the system. The data we collect provides analytical insights into the fundamental frequency at 10 GHz, but no information is available for higher harmonics. We intend to develop a new method that can identify all involved harmonics by a combined single-tone and I(V) DC measurements. This is of importance regarding the simplicity of our experimental workbench. Using a spectrum analyzer (SA) to get information up to the 3<sup>rd</sup> or 5<sup>th</sup> harmonic would not only be costly, but also present lower power measurements accuracy. This solution doesn't allow the tracking of the 7<sup>th</sup> or 9<sup>th</sup> order of non-linearity if needed to model the NL behavior. Moreover, such multi-tone measurement as available with a SA would bring its own challenges regarding the stress-step duration.

<figure><img src="image_3.png" /><figcaption>**Fig. 2.** Schematic of the RF-step stress test bench.</figcaption></figure>

### 3. Results and discussion

We previously demonstrated that the devices of structures A and B have similar degradation mechanisms and kinetics during DC step stress [7]. However, the mechanisms activated by traps are more pronounced for structure A, due to its higher trap density [8]. On the other hand, structure E showed significantly improved stability during DC step stress, with far superior operational SOA to those of A and B. Therefore, for this study on the dynamic behavior of transistors under RF step-stress, we selected variants A and E to assess how trap density eventually impacts the electrical performance of the devices under RF stress. All the measurements performed in this study are similar to the results as illustrated in Fig. 3 for device of E-structure. These measurements allow us to identify 3 different zones:

- zone 1 where P<sub>out</sub> varies linearly with P<sub>in</sub> at 10 GHz. This zone also features constant dynamic gain and static drain current as expected.

- zone 2 exhibits nonlinear behavior due to two coexisting phenomena: gain compression and self-biasing effect observable by the drain current I<sub>DS</sub>

increase up to a certain maximum value.

- zone 3 where P<sub>out</sub> saturates, I<sub>DS</sub> begins to degrade and I<sub>GS</sub> increases by more than two orders of magnitude, which leads to the transistor fatal failure (strong non reversible degradation).

In the following sections, each zone is discussed and analyzed independently.

<figure><img src="image_4.png" /><figcaption>**Fig. 3.** RF-step stress measurement on device of structure E with L<sub>G</sub> =100nm and L<sub>GD</sub>=0.5µm. The upper panel shows the output power in blue and the gain evolution in green. The lower panel shows the DC drain and gate current (respectively in blue and red).</figcaption></figure>

#### 3.A. Linear analysis

In this section, we will analyze the linear zone 1 of the measurement. All DC and RF electrical parameters remain constant (except P<sub>out</sub> which increases linearly with P<sub>in</sub>, considering a linear gain such as P<sub>out</sub>(dBm) = P<sub>in</sub>(dBm) + G<sub>0</sub>(dB)). G<sub>0</sub> remains constant at 7.3 dB, indicating the stability of gate and drain bias voltages. Then, we exploit the transfer and output characteristics of the transistor, in current and voltage representation: the power measurements are carried out on a 50Ω load adapted both at the input and at the output, which makes it possible to establish the following relationship between the signal power and voltage: P(W) = 1/2 × V<sub>max</sub><sup>2</sup> / 50.

<figure><img src="image_5.png" /><figcaption>**Fig. 4.** Variation of the measured V<sub>outmax</sub> signal as a function of V<sub>inmax</sub> signal in the zone 1 of Fig. 3 and the linear fit in red</figcaption></figure>

Fig. 4 shows the variation of signal of V<sub>outmax</sub> as a function of V<sub>inmax</sub>. A linear fit reveals a voltage gain
A<sub>v</sub> of 2.33. This value remains constant in a given DC biasing condition, which corresponds to a certain transconductance gain G<sub>m</sub>. If the biasing changes, the associated G<sub>m</sub> also changes according to G<sub>m</sub>-V<sub>GS</sub>(V<sub>DS</sub>) transfer characteristics. This affects the A<sub>v</sub> value according to a linear dependence. Thus, this linear voltage gain is biasing dependent.

### 3.B. Non-Linear analysis and modelling

The largely accepted model for a NL electronic system describes the relationship between the output voltage signal and the input following [9]:

$$V_{out} = a_{1} V_{in} + a_{2} V_{in}^{2} + a_{3} V_{in}^{3} + a_{4} V_{in}^{4} + a_{5} V_{in}^{5} \dots (1)$$

With a<sub>1</sub>=A<sub>v</sub>, the linear coefficient mentioned previously which depends on the bias conditions. All even-order coefficients govern the DC static part, and are thus being responsible for self-biasing as well as the emergence of even-order harmonics: 2f<sub>1</sub>, 4f<sub>1</sub>, etc., with f<sub>1</sub> representing the fundamental frequency of 10 GHz in our study. At the same time, the odd-order terms are responsible for the appearance of odd-order harmonics, through additional components which penalizes the linearity of the fundamental frequency f<sub>1</sub>. The output power signal as measured in our study corresponds to the fundamental frequency. So, all the even coefficients should be forced to zero in the expression (1). However, the even contribution to the self-biasing must be taken into account, in the DC bias value as well as in the resulting variability of the linear gain a<sub>1</sub>. Zone 2 in Fig. 3 illustrates the NL behavior of the output signal as the input signal changes, a result of gain compression phenomena and of the possible self-biasing effect. A priori, it should seem difficult to distinguish DC self-bias from fundamental power compression. This effect of variation of the linear gain induced by self-biasing is isolated using the evolution of I<sub>DS</sub> as seen in Fig. 3, which goes from 15 mA to 25 mA for a P<sub>in</sub> stepping from 0 dBm to +18 dBm. In the following, we take into account the simultaneous effect of the self-biasing phenomenon and gain compression in the proposed NL model. I(V) measurements performed before stress and at P<sub>in</sub>=18dBm show that the device does not degrade. The measurements of the drain current evolution during stress allows us to track the change in biasing on the I(V) characteristics before stress (V<sub>GS</sub>, I<sub>DS</sub>, G<sub>m</sub>, etc.) as well as on the 50Ω load line (Fig. 5). Therefore, by linear regression on the gain A<sub>v</sub>, we calculate its linear variation at each stress level indexed with 'i' in the formula A<sub>vi</sub> = A<sub>v0</sub>G<sub>mi</sub> / G<sub>m0</sub> (the index '0' represents the linear zone 1). From each of the evolving DC conditions as depicted in Figure 5, the dynamic load line diagrams are computed as a resistive load, after linearization of the odd harmonic contribution to the 10 GHz fundamental tone. These contribution are accounted for according to the expression

of V<sub>in</sub>(RF step) as depicted in Equations 2 and 3:

$$ 
\begin{aligned}
V_{outf_1} &= a_1 V_{in} + \frac{3}{4} A_3 V_{in}^3 + \frac{5}{8} A_5 V_{in}^5 + \frac{35}{64} A_7 V_{in}^7 + \frac{63}{128} A_9 V_{in}^9 \quad (2) \\
V_{outf_2} &= a_1 V_{in} + a_3 V_{in}^3 + a_5 V_{in}^5 + a_7 V_{in}^7 + a_9 V_{in}^9 \quad (3)
\end{aligned}
$$

To assess the effect of considering the variation of the gain A<sub>v</sub> as a function of V<sub>in</sub> in the polynomial model, we compared several degrees models. These polynomials correspond to the response of the signal at the fundamental frequency f<sub>1</sub> for a given P<sub>in</sub> step (or V<sub>in</sub> as developed in Eq. 3); we therefore canceled all coefficients of even order. We compared the measurement with mathematical models (a<sub>1</sub> constant) and the physical fit model that reflects the self-biasing effect (a<sub>1</sub> variable) for degrees 3, 5, 7, and 9 (Fig. 6). The fit as applied in this work corresponds to using the least squares method. The results from Fig. 6 show that the models of order 3 and 5 are not realistic enough to convey the relationship between V<sub>out</sub> and V<sub>in</sub> for regions 1 and 2. Through the degree 3 model, we clearly see the capacity of the physical model with a<sub>1</sub> variable to represent the relationship below V<sub>in</sub> = 0.5V and that beyond that, a higher order polynomial is necessary. For degrees 7 and 9, we notice that the two models match the measurement. Except that the coefficients of the two polynomials do not converge from an order to the other one. This means that the mathematical model can indeed fit well to the measurement, but doesn't present the correct coefficients for V<sub>out</sub>(V<sub>in</sub>), taking into account the harmonic electrical representation. In other words, this doesn't provide a realistic representation of the weight of each harmonic on the NL response.

<figure><img src="image_6.png" /><figcaption>Fig. 5. I(V) DC measurements of the device before RF stress in Fig. 3. Left panel shows the transfer characteristics I<sub>DS</sub>.G<sub>m</sub> (V<sub>GS</sub>) at V<sub>DS</sub>= 6V. Right panel shows the output characteristics I<sub>DS</sub>(V<sub>DS</sub>).</figcaption></figure>

<figure><img src="image_7.png" /><figcaption>Fig. 6. Polynomial fits of degrees 3, 5, 7, and 9 illustrating the relation between maximum output voltage (V<sub>outmax</sub>) and maximum input voltage (V<sub>inmax</sub>), for constant and variable A<sub>v</sub> cases.</figcaption></figure>
Starting from degree 9, the model with a coefficient of determination R² = 0.996 is sufficient to represent the measured stress RF response from the beginning of zone 1 to the end of zone 2. Table 1 shows the difference in polynomial coefficients between the model with constant gain a1 and the variable one. As the measurements are scalar and not vectorial, the signs of the coefficients represent a 180° phase shift of the harmonics with a negative coefficient and 0° for those with a positive coefficient. Thus, to evaluate the effect of each harmonic and the level of Pᵢₙ where its contribution is taken into account, we simulate the polynomial of degree 9, for a₁(Vᵢₙ) variable, by removing one by one the highest coefficient until the simulation of order 1 - fundamental (Fig. 7).

<figure><img src="image_8.png" /><figcaption>**Fig. 7.** Decomposition of the 9th degree polynomial model and representation of harmonics contribution at different degrees from the model at variable a₁, 9th order.</figcaption></figure>

<table><caption>Table 1: 9th order polynomial coefficients</caption><thead><tr><th>Models</th><th>a1</th><th>a3</th><th>a5</th><th>a7</th><th>a9</th></tr></thead><tbody><tr><td>Constant a<sub>1</sub></td><td>2.358</td><td>-1.198</td><td>0.551</td><td>-0.128</td><td>0.010</td></tr><tr><td>a<sub>1</sub> (V<sub>in</sub>)</td><td>2.33 to 2.05</td><td>-0.914</td><td>0.386</td><td>-0.086</td><td>0.007</td></tr></tbody></table>

In the final version of the paper, the model with a₁(Vᵢₙ) will be further confirmed by measuring the coefficient of each harmonic with a SA. The polynomial of even degree showing the contribution of harmonics on the DC shift (not presented in this paper) will be discussed.

### 3.C. Reliability analysis and Schottky limits

RF step stress measurements, as shown in Fig. 3, were conducted on a batch of devices from structures A and E featuring L<sub>G</sub> = 100nm and W<sub>G</sub> = 50µm, and for various L<sub>GD</sub> dimension. The robustness results are similar across region 3, regardless of the technological variant or L<sub>GD</sub>. A sudden degradation of the gate current starting from 18 dBm of P<sub>iₙ</sub>, accompanied by a gradual degradation of the drain current, results in a decrease in the output power. To determine if the transistor degradation can be attributed to the only Schottky diode failure mechanism, RF step stress measurement sequence are performed on the same size of transistors in diode mode with V<sub>DS</sub> = 0V (Fig. 8). The results indicate that, regardless of the technology variant and gate-drain distance, all diodes fail at the same power levels as in transistor operation. This reveals that the Schottky diode withstands a certain RF power level, which acts as the cause of failure under accelerated destructive test, whatever the HEMT operating mode configuration. This is thus defined as the RF SOA-hard linked to the gate of AlN/GaN HEMTs.

<figure><img src="image_9.png" /><figcaption>**Fig. 8.** Gate currents evolution during RF-step stress applied on Schottky diode configuration (V<sub>DS</sub> = 0V) of the transistors A and E with gate to drain distances of 0.5µm, 1.5µm and 2.5µm.</figcaption></figure>

### 3. Conclusion and perspectives

This study on the robustness of AlN/GaN HEMTs under RF-step stress has demonstrated that the RF SOA of these technologies is L<sub>GD</sub> independent. It is rather related to the maximum power supported at the input of the device (i.e. the Schottky gate), before the sudden degradation linked to the conduction of the gate Schottky contact. The gate stacked with short length dimension acts as a fuse that fails instantaneously when the gate drives elevated I<sub>GS</sub> current. This gate degradation leads to a significant change in the control of the 2-DEG, implying the electrical physical properties of the transistor. We also validated the good coherence of the physical model of the order 9 polynomial with the measurement: this model accounts for the self-biasing phenomenon at each step-stress. In the final paper, we will present results of the developed approach to compare A and E technologies. A discussion will be proposed to evaluate the influence of the electrical performance improvement and the reduction of trap densities in structure E, regarding the different coefficients, as well as the influence of L<sub>GD</sub>.

### Acknowledgments

This research received funding from the national program LABEX GANEX. The authors wish to express their gratitude to SOITEC Belgium for the provision of high-quality materials. This work was also supported by the PROOF platform at LAAS-CNRS, partially financed by the Occitanie region.

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