# Hf\_0.5Zr\_0.5O\_ FeRAM scalability demonstration at 22nm FDSOI node for embedded applications

Simon Martin, Carine Jahan, Liam Hosier, Fabien Grimaud, Mélanie Louro, Julie Laguerre, Jean Coignus, William Vandendaele, Julien Borrel, Niccolo Castellani, et al.

► To cite this version:

Simon Martin, Carine Jahan, Liam Hosier, Fabien Grimaud, Mélanie Louro, et al. Hf\_0.5Zr\_0.5O\_ FeRAM scalability demonstration at 22nm FDSOI node for embedded applications. IEDM 2024 - IEEE International Electron Devices Meeting, Dec 2024, San Francisco, United States. 10.1109/IEDM50854.2024.10873378. cea-05533766

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https://cea.hal.science/cea-05533766v1

Submitted on 2 Mar 2026

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HZO FeRAM scalability demonstration
at 22nm FDSOI node for embedded applications

S. Martin, C. Jahan, L. Hosier, F. Grimaud, M. Louro, J. Laguerre, J. Coignus, W. Vandendaele, J. Borrel, N. Castellani, V. Meli, J. Rottner, C. Boixaderas, T. Magis, T. Roman, M. Bedjaoui, J. Mercier, S. Minoret, C. Euvrard, J. Sturm, S. Kerdilès, M. Opprecht, C. Comboroure, A. Souhaité, K. Jullian, J.-P. Nacenta Mendivil, L. Couture, O. Glorieux, K. Azizi-Mourier, T. Billon, S. Dumont, O. Guiller, M. Mouhdach, A. Blot-Saby, D. Ly, S. Martinie, C. Charpin, F. Andrieu, O. Billoint, and L. Grenouillet

CEA-Leti, Univ. Grenoble Alpes, F-38000 Grenoble, France

**Abstract**— 7nm HZO-based 2D ferroelectric capacitors (C2D) down to 0.0028µm² area were successfully integrated in the BEOL of 22nm FDSOI node, with 2.Pr > 10µC/cm² and extrapolated breakdown-limited endurance > 10¹³ cycles. C2D exhibit a strong layout-dependent remanent polarization that is attributed to stress relaxation. 16kbit 1T-1C₂D FeRAM arrays were designed and fabricated to quantitatively assess the memory window (MW) dependence with capacitor and transistor dimensions as well as operating voltages. 0 bitfall up to 10¹⁰ cycles is demonstrated on these 22nm FeRAM arrays at 2.4V, with median memory window (MW) larger than 100mV. In order to reduce FeRAM bitcell footprint, 3D-based FeCap (C3D) are also demonstrated, leading to significant 2.Pr up to 140µC/cm², when normalized by footprint.

I. INTRODUCTION

Conventional embedded Flash (eFlash) memories face severe cost and scaling challenges at 28nm node and below, where high-k metal gate stack were introduced. Resistive Back-End Of Line (BEOL) memories, such as MRAM, PCM, or OxRAM, offer serious alternatives to replace eFlash at advanced nodes. However their operation principle requires driving more than 100µA in the memory element, inducing reliability issues, making scalability difficult, especially regarding selector size, and also preventing ultra-low power consumption. Ferroelectric random access memories (FeRAM) are intrinsically ultra-low power due to the voltage-driven switching mechanism, and FeRAM paradigm recently changed due to i) the scalability potential of lead-free HfₓZr₁-xO₂ (HZO) ferroelectric films thinner than 10nm, and ii) the high reliability of HZO through recent demonstration of product-level NV-DRAM for standalone applications [1]. However, so far, hafnia-based 1T-1C FeRAM array demonstrations using standard integration with conventional CMOS transistors for embedded applications were limited to 130nm node [2,3,4,5]. In this paper, we present for the first time an HZO-based ferroelectric capacitor (FeCap) BEOL platform at 22nm FDSOI technology node and explore the performances of 22nm 1T-1C FeRAM arrays.

II. HZO FECAPS INTEGRATED AT 22NM NODE

7nm Hf<sub>0.5</sub>Zr<sub>0.5</sub>O<sub>2</sub>-based 2D FeCaps (C<sub>2D</sub>) with diameter ranging from 300nm (0.07µm<sup>2</sup>) down to 60nm (0.0028µm<sup>2</sup>) were integrated in the BEOL of 22nm FDSOI technology,

between M4 and M5 Cu lines, as shown in Fig.1 and Fig.3. The HZO film is deposited by ALD on a PVD-deposited TiN bottom electrode. A 400°C 1h crystallization anneal is performed under N₂ atmosphere after TiN top electrode deposition. An additional 500°C 30s Rapid Thermal Anneal is optionally implemented post M5 deposition to improve remanent polarization (2.Pr) values and is shown to have no impact on CMOS transistor key metrics (Fig.4).

The integration scheme leads to functional FeCap fields composed of 9306 individual 0.0028µm² C2D. Maximum 2.Pr values of ~20µC/cm² are measured at 10⁴ cycles, with no breakdown up to 10¹⁰ cycles with a 4 MV/cm cycling field (Fig.5). Based on previous extrapolation work on number of cycles to breakdown (C<sub>BD</sub>) dependence with area [6], this shows that C<sub>BD</sub> on single a 0.0028µm² C2D is expected to exceed 10¹³ cycles.

2.Pr C2D layout dependence was then studied. It is evidenced in Fig.6 that 2.Pr values increase as C2D diameter decreases for a given bitcell area, or increase as bitcell area increases for a fixed C2D diameter. The trend is summarized in Fig.7. In order to understand further the origin of this layout dependence, extracted 2.Pr and dielectric constant values were reported in Fig.8 against the ratio of the pitch between FeCaps in the capacitor field and the single FeCap area. A clear trend is evidenced, showing not only that 2.Pr is proportional to this ratio, but also that 2.Pr increase is correlated to the dielectric constant increase (Fig.9). This suggests a higher proportion of orthogonal/tetragonal phases for the smallest FeCaps while larger ones (or closest ones) show lower dielectric constant typical of a higher monoclinic-phase proportion in the HZO mixture. This effect could be due to a partial biaxial stress relaxation during FeCap etch. Indeed, it has recently been reported that decreasing biaxial stress was correlated to an increase in 2.Pr value [7]. HZO biaxial stress reduction is expected to be enhanced when FeCap pitch increases and when FeCap area decreases.

III. HZO FE RAM ARRAY DEMONSTRATION AT 22NM

16kbit 1T-1C<sub>2D</sub> FeRAM arrays with different bitcells were designed and fabricated at 22nm node for in-depth functionality screening, not only regarding 2D FeCap area, but also bitcell area, as well as NMOS transistor type (thin -SG- vs thick -EG- oxide, transistor width W), as shown in Fig.2. Here a conventional Sense Amplifier (SA) is implemented along the
128 bitlines (BL) to sense ferroelectric switching induced voltage elevation along the BL during Read, as in [3]. Note though that using a Capacitive Trans-Impedance Amplifier for sensing instead of a SA is expected to drastically improve the memory window (MW), as reported in [8].

Fig.10 shows ‘0’ and ‘1’ state raw distributions measured on 300nm diameter 7nm HZO 1T-1C2D 16kbit FeRAM with EG NMOS selector (nominal Vdd=1.5V). Although the 300 nm FeCap has the lowest polarization per unit area (Fig.6), overall it develops the highest remanent charge, which explains why it was used for this first demonstration. At 2.4V operating voltage under 250 ns pulses, a median memory window MW0σ of ~130mV is observed along cycling up to 10⁷ cycles, with 0 bitfail and a MW of ~30-40 mV at array level (Fig.11). The inset of Fig.10 showing the bit-to-bit MW bitmap over the whole array sheds light on a strong MW gradient along wordlines (WL), explaining the degraded state slope distributions (> 11mV/dec) on this first design. The bit-to-bit MW showed in Fig.11 is therefore a projection of a potential MW avoiding dispersion due to the design (MW~80mV).

Longer endurance measurements were performed with the same programming/reading conditions at sub-array level (1kbit) for time consideration. As shown in Fig.12, up to 10¹⁰ cycles are reported with 0 bitfail at array level, with bipolar cycling recovery phase [9] performed every 10⁹ cycles to maintain MW fully open and mitigate fatigue effect [10]. This endurance test also demonstrates that transistor functionality is preserved well above nominal Vdd (overdrive of 0.9V) during a long period of time (~115h).

The impact of transistor width W on FeRAM MW (at constant bitcell size) is illustrated in Fig.13 for various Vdd. An improvement of the MW0σ is observed when W is narrowed (particularly as Vdd and FeCap area increase). This effect is well reproduced with SPICE simulations (Fig.14) using LETI Verilog-A FeCap model on a 16kbit array. Two topologically identical 16kbit arrays have been designed with only the modification of bitcell transistor’s W achieved by reducing the active region. BEOL-related parasitics remain unchanged but transistor’s gate-source capacitance CGS reduces, thus lowering BL capacitance (CBL). The MW0σ being defined as:

$$MW_{0\sigma} = \frac{2\text{Pr.S}}{C_{\text{diet}}+C_{\text{BL}}} \quad (1)$$

- with S the FeCap area, Cdiet the dielectric capacitance - will therefore widen for narrower transistors as CGS is proportional to W. W reduction also improves ‘0’ and ‘1’ distribution slopes thus decreasing array-level variability (inset graph of Fig.13).

Fig. 15, depicting the MW0σ normalized by the FeCap area for 0.135µm² EG bitcell, shows that reduction of 2.Pr with FeCap area observed at the FeCap level (Fig. 6&7), translates at the array level. Fig. 15 inset simulates the MW decrease with FeCap area under two conditions: (1) when 2.Pr remains constant over FeCap area, a slight drop in 2.Pr due to the increase in Cdiet is observed (red curve); (2) when 2.Pr decreases with FeCap area (2.Pr values were taken from Fig. 7), the normalized MW0σ trend matches measured data (blue curve), confirming the 2.Pr (MW) layout dependence at the array level. MW0σ against the C2D area for each bitcell (Fig.2) are shown in Fig.16. MW0σ remains constant when both bitcell and FeCap areas decrease simultaneously (as observed in Fig.7 for FeCap

2.Pr). This effect is more prominent for SG bitcells as area ratio between the two SG bitcell areas is equal to 3.7 (compared to 1.7 area ratio of EG bitcells), positively impacting scalability.

## IV. 3D FECA P DEVELOPMENT

Based on the above trends, 3D FeCap (C3D) process was developed to address ultimate bitcell scaling at 22nm FDSOI node. C3D process flow uses the same mask levels as for C2D (Fig.1), but here the TiN/7nm HZO/TiN stack is deposited in 100nm diameter vias with an aspect ratio (AR) of 3.5:1, with TiN electrodes being deposited by CVD. Vias are then filled with W and the ferroelectric stack further etched as illustrated in Fig.17 and Fig.18. These C3D lead to a ferroelectric stack developed area of 0.11µm² with a footprint of 0.0078µm². Ferroelectric characteristics measured by PUND (with the same conditions as the C2D, cf. Fig.5) point towards a good HZO crystallization along the sidewalls (Fig.19), reaching a 2.Pr of 140µC/cm² when normalized by the footprint and coercive voltages below 1V. The 2.Pr shape against cycles shown in Fig.20 is close to C2D characteristics (Fig.6) in terms of wake-up and fatigue, with a maximum 2.Pr reached at around 2.10³ cycles, suggesting that ferroelectric stack properties are close between 3D and 2D FeCaps.

1T-1C3D FeRAM MW0σ projections with C3D at array level were performed (empty points of Fig. 21), based on 1T-1C2D FeRAM MW0σ measurements (full points) for bitcells described in Fig.2. These projections demonstrate a significant MW0σ gain going 3D (Fig.7). This also indicates that 3D-based FeCaps are mandatory to target fully open MW for ultra-scaled bitcells. These MW0σ boost will enable lower voltage operation (Vdd reduction), even with partial ferroelectric switching.

## V. CONCLUSION

For the first time, BEOL integration of 7nm HZO-based 2D and 3D FeCaps are successfully demonstrated at 22nm FDSOI technology node, down to 0.0028µm² and 0.0078µm² footprint area, respectively. 16kbit 1T-1C2D FeRAM arrays were designed and fabricated, demonstrating 0 bitfail at array level at least up to 10¹⁰ cycles, at 2.4V operating voltages with 250ns pulses. Those results, obtained with relatively low 2.Pr values (~10µC/cm²), will be improved based on recent stack optimization reporting 2.Pr values of 60µC/cm² [1,11,12]. 22nm FeRAM bitcell transistors are shown to be robust to 0.9V voltage overdrive vs nominal Vdd at least up to 10 billion cycles. It is also demonstrated that bitcell transistor width narrowing is beneficial for the MW0σ (measured to be up to 150mV) through a reduction of CBL, consistently with SPICE simulations. A strong layout-dependent 2.Pr is evidenced on 2D FeCaps which is detrimental for the MW when bitcell area is reduced. For ultimate bitcell scaling using logic transistors, 3D FeCap are mandatory to widen MW, and we demonstrate that 2.Pr of 140µC/cm² (normalized by footprint) and Vc below 1V can be reached using 3.5 AR FeCaps with 100nm diameter, leading to projected MW0σ ~ 600mV for bitcell area of 0.047µm² (~ 2x smaller than 6T SRAM area at 22nm FDSOI node). Lower FeRAM operating voltages can also be envisioned based on recent results demonstrating ferroelectric films thinner than 7nm with good ferroelectric properties, high reliability, Vc < 0.8V [12,13] and new crystallization techniques [14].
<figure><img src="image_2.png" /><figcaption>**Fig.1:** HAADF-STEM cross section of 1T-1C FeRAM arrays integrated at 22nm FDSOI node between M4 and M5 copper lines. Different 1T-1C<sub>2D</sub> bitcells are explored using 2D-based FeCaps (cf details Fig.2).</figcaption></figure>

<figure><img src="image_3.png" /><figcaption>**Fig.4:** NMOS characteristics (Vth, Ioff, Ion) measurement and the foundry specs indicate that transistors are not affected by FeCap integration and the related thermal budget for crystallization.</figcaption></figure>

<figure><img src="image_4.png" /><figcaption>**Fig.7:** 2.Pr vs 2D FeCap area with theirs fitting curves for the two bitcell areas (FeCap pitch) of Fig.6. Measured 2.Pr is layout-dependent: it increases for smaller FeCaps at fixed pitch (1) and increases for larger pitch at fixed FeCap area (2).</figcaption></figure>

<figure><img src="image_5.png" /><figcaption>**Fig.10:** 22nm 1T-1C<sub>2D</sub> 16kbit FeRAM array raw distributions measured up to 10<sup>7</sup> cycles. 1T-1C<sub>2D</sub> bitcell of 0.227µm<sup>2</sup> (EG NMOS w/ 560nm width). C<sub>2D</sub> area of 0.07µm<sup>2</sup>. tprog=250ns, tread=62.5ns, Vdd=2.4V. Inset graph represents the MW bitmap through the array after 10<sup>4</sup> cycles.</figcaption></figure>

<figure><img src="image_6.png" /><figcaption>**Fig.2:** Summary of 1T-1C<sub>2D</sub> FeRAM bitcells studied with footprint ranging from 0.227µm<sup>2</sup> down to 0.047µm<sup>2</sup>. FeCap diameter ranges from 300nm (0.07µm<sup>2</sup>) down to 60nm (0.0028µm<sup>2</sup>). Two NMOS selector gate oxide thicknesses are explored.</figcaption></figure>

<figure><img src="image_7.png" /><figcaption>**Fig.5:** (a) P-E loops (measured by PUND at 10kHz, 4MV/cm) on 60nm diameter 7nm HZO 2D FeCap fields (9306 FeCaps connected in parallel) at different cycles (100kHz, 4MV/cm). (b) 2.Pr and (c) Vc up to 10<sup>10</sup> cycles (@2MHz, 4MV/cm).</figcaption></figure>

<figure><img src="image_8.png" /><figcaption>**Fig.8:** 2.Pr vs the ratio of 2D FeCap pitch in the capacitor field over the area of a single 2D FeCap. A consistent trend describing the layout-dependent 2.Pr is evidenced.</figcaption></figure>

<figure><img src="image_9.png" /><figcaption>**Fig.11:** Median MW, MW at 16kbit array level and MW bit-to-bit extracted from Fig.10 showing that improved design to avoid MW gradient along WLs will significantly improve the MW at array level.</figcaption></figure>

<figure><img src="image_10.png" /><figcaption>**Fig.3:** (left) BF-STEM and (right) EDX cross-section details of a 170nm diameter integrated 2D FeCap (C<sub>2D</sub>). Hf<sub>0.5</sub>Zr<sub>0.5</sub>O<sub>2</sub> ALD-deposited film is crystallized after top electrode deposition at 400°C 1h under N<sub>2</sub> ambient. Final anneal (500°C 30s) is performed after M5.</figcaption></figure>

<figure><img src="image_11.png" /><figcaption>**Fig.6:** Median 2.Pr vs cycles (100kHz, 4MV/cm) for two different bitcell footprints (i.e. FeCap pitch) and different 7nm HZO 2D FeCap diameters ranging from 300nm (0.07µm<sup>2</sup>) down to 60nm (0.0028µm<sup>2</sup>). 20 dies measured through 300mm wafer. 2.Pr extracted by PUND</figcaption></figure>

<figure><img src="image_12.png" /><figcaption>**Fig.9:** Dielectric constant (extracted by PUND) plotted as function of the same ratio as Fig.8 (2D FeCap pitch / 2D FeCap area), and showing a correlation between the 2.Pr layout-dependent increase and the dielectric constant increase.</figcaption></figure>

<figure><img src="image_13.png" /><figcaption>**Fig.12:** 10<sup>10</sup> cycles endurance (tprog=250ns, tread=62.5ns, Vdd=2.4V w/ recovery of 10<sup>5</sup> cycles @ 4µs 2.8V every 10<sup>9</sup> cycles) at 22nm 1T-1C<sub>2D</sub> 1kbit FeRAM sub-array level, showing no bitfail up to 10<sup>10</sup> cycles. Transistors sustain voltage overdrive (~115h) w/o detrimental impact on this reliability test. Positive impact of recovery mostly after the first 10<sup>9</sup> cycles.</figcaption></figure>
<figure><img src="image_14.png" /><figcaption>**Fig.13:** MW₀₆ vs C₂D area measured on 22nm 1T-1C₂D 16kbit FeRAM arrays for different prog. voltages (Vdd). Bitcell area is fixed (0.227µm²). Reducing bitcell transistor width W from 880nm (right) to 560nm (left) improves MW₀₆ due to Cₛₛₜ reduction (Cₛₛₜ decrease), and improves the distribution slopes (inset).</figcaption></figure>

<figure><img src="image_15.png" /><figcaption>**Fig.16:** MW₀₆ vs C₂D area measured on 22nm 1T-1C₂D 16kbit FeRAM arrays for four different bitcell areas with two transistor flavors for the bitcell selector: either EG thick oxide NMOS (left) or SG logic NMOS (right).</figcaption></figure>

<figure><img src="image_16.png" /><figcaption>**Fig.19:** P-E loops (measured by PUND at 10kHz, 4MV/cm) at different cycles (100kHz, 4MV/cm) up to 10⁷ cycles on 7nm HZO 3D-based FeCap fields (2728 3D FeCaps connected in parallel).</figcaption></figure>

<figure><img src="image_17.png" /><figcaption>**Fig.14:** SPICE simulation of consecutive ‘0’ and ‘1’ states writing/reading sequence with different NMOS W (tprog=250ns,tread=62.5ns,Vdd=2V). The W reduction shows a MW of 120mV for W=560nm while it drops to 80mV with wider transistor.</figcaption></figure>

<figure><img src="image_18.png" /><figcaption>**Fig.17:** HAADF-STEM cross section of 3D-based HZO FeCaps integrated in the BEOL between two Cu metal lines. The 3D-based FeCaps have an aspect ratio of 3.5:1 and a developed area of 0.11 µm² with a footprint of 0.0078 µm².</figcaption></figure>

<figure><img src="image_19.png" /><figcaption>**Fig.20:** (a) 2.Pr and (b) coercive voltages up to 10⁷ cycles on 3D-based 7nm HZO FeCap fields (same measurement conditions as Fig.19)</figcaption></figure>

<figure><img src="image_20.png" /><figcaption>**Fig.15:** 22nm 16kbit FeRAM MW@0σ normalized with the FeCap area (tprog=250ns, tread=62.5ns). 0.135µm² 1T-1C₂D bitcell with EG NMOS. The trend measured on arrays confirms the measurements performed on FeCap fields (Fig.7). The inset graph shows the simulated trend expected assuming constant 2.Pr (red) or layout-dependent 2.Pr according to Fig.7 (blue).</figcaption></figure>

<figure><img src="image_21.png" /><figcaption>**Fig.18:** BF-STEM cross section zoom-in of the bottom (left) and the top (right) of TiN/7nm Hf₀.₅Zr₀.₅O₂/TiN 3D-based FeCap integrated in the BEOL, showing good conformity of the ALD-deposited HZO film as well as top and bottom TiN electrode (CVD-deposited).</figcaption></figure>

<figure><img src="image_22.png" /><figcaption>**Fig.21:** Projections towards 3D FeCap is necessary to improve MW on smallest bitcells. Projections were made on the largest 2D FeCap area for each bitcell with Vdd=1.5V for SG bitcells and Vdd=2.4V for EG bitcells</figcaption></figure>

<table><thead><tr><th></th><th>SONY [2]<br>VLSI'20</th><th>CEA-Left [3]<br>IEDM 21</th><th>IMECAS [4]<br>ISSCC'23</th><th>SONY [5]<br>IEDM'23</th><th>MICRON [1]<br>IEDM'23</th><th>CEA-Left [this work]</th></tr></thead><tbody><tr><td>Technology node</td><td colspan="3">130nm (200nm substrates)</td><td colspan="3">22nm FDSOI (300nm substrates)</td></tr><tr><td>Application /<br>Capacity</td><td>Embedded<br>64 kbit</td><td>Embedded<br>16 kbit</td><td>Embedded<br>9 Mbit (bank)</td><td>Embedded<br>1 Mbit<br>(256x64)</td><td>Standalone<br>32 Gbit</td><td>Embedded<br>16 kbit</td></tr><tr><td>FeCap (2D/3D)<br>2.Pr (µC/cm²)</td><td>2D<br>20-40</td><td>2D<br>20-40</td><td>2D<br>20-40</td><td>3D<br>20-40</td><td>3D<br>55-60</td><td>2D (min area 0.0028 µm²)<br>10-20</td><td>3D (AR=3.5:1), 0.01 µm²<br>80-140 (footprint)</td></tr><tr><td>Ferro film</td><td>HZO 10nm</td><td>HSO 10nm</td><td>HZO 8nm</td><td>HZO 6nm</td><td>HZO 5.7nm</td><td colspan="2">HZO 7nm</td></tr><tr><td>FeRAM bitcell<br>selector</td><td>Standard<br>FET</td><td>Standard FET<br>(thick oxide)</td><td>Standard<br>FET</td><td>Standard<br>FET</td><td>Poly Si FET</td><td colspan="2">Standard FET (EG or SG)</td></tr><tr><td>Voltage (V)</td><td>2.5</td><td>2.5-4.8</td><td>3.3</td><td>1.8-2.4</td><td>1.5</td><td colspan="2">1.5-2.4</td></tr><tr><td>Endurance</td><td>10<sup>6</sup></td><td>&lt; 10<sup>7</sup> (16kbit)</td><td></td><td></td><td></td><td colspan="2">&gt; 10<sup>12</sup> meas. FeCap fields,<br>&gt; 10<sup>13</sup> extrap. 0.0028µm² cell<br>&gt; 10<sup>15</sup> meas. (1kbit FeRAM array)</td></tr><tr><td>Retention</td><td>85°C</td><td>85°C</td><td>85°C</td><td>85°C</td><td>55°C 10 years<br>Ea=</td><td colspan="2">NA<br>Similar stack evaluated in [5]. Ea=</td></tr></tbody></table>

ACKNOWLEDGMENT

This work was funded by European commission through ECSEL-IA 101007321 StorAIge project, French State and Auvergne-Rhône-Alpes region through Nano2026 “Ginko” project.

REFERENCES

[1] N. Ramaswamy et al., IEDM 2023, [2] J. Okuno et al., VLSI 2020, [3] T. Francois et al., IEDM 2021, [4] J. Yang et al., ISSCC 2023, [5] J. Okuno et al., IEDM 2023, [6] R. Alcala et al., JEDS 2022, [7] S.T. Jaszewski et al., Adv. Electron. Mater. 2024, [8] O. Billoyt et al., IMW 2024, [9] J. Okuno et al., JEDS 2022, [10] J. Laguerre et al., accepted at SSDM 2024, [11] M.I. Popovici et al., IEDM 2022 [12] A. Chavan et al., IMW 2024 [13] T. Toprasertpong et al., ACS Appl. Mater. Interfaces 2022 [14] S. Martin et al., SISC 2024 [15] J. Laguerre et al., IRPS 2024 [16] D. Ettisserry et al., IRPS 2024