# Towards Accurate Static Power Model on Multi-Core Operating Systems

Gaëtan Barret, Daniel Chillet, Roland Picard, Joël Penhoat

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Gaëtan Barret, Daniel Chillet, Roland Picard, Joël Penhoat. Towards Accurate Static Power Model on Multi-Core Operating Systems. RAPIDO 2025 - 17th Workshop on Rapid Simulation and Performance Evaluation for Design Optimization, Jan 2025, Barcelona Spain, France. pp.1-7, 10.1145/3721848.3721849. hal-05273576

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# Towards Accurate Static Power Model on Multi-Core Operating Systems

Gaëtan Barret
Orange Labs, INRIA
Lannion, France
gaetan.barret@orange.com

Roland Picard
Orange Labs
Rennes, France
roland.picard@orange.com

## Abstract

Software-based power meters, such as PowerAPI, provide a convenient way to monitor energy consumption in computing infrastructures. However, they often struggle to accurately account for static power consumption—the portion of power that remains constant regardless of system activity. This study aims to address these limitations by developing a robust static power estimation model for multi-core CPUs using offline data from controlled experiments.

Our approach utilizes five key processor metrics: temperature, voltage, frequency, activity levels, and Running Average Power Limit (RAPL) measurements. We created a custom stress workload to gather data across diverse conditions, ensuring thorough core-specific activity. To address inaccuracies in thermal sensors, we implemented a temperature correction algorithm, refining raw data to enable analysis of core-specific parameters like frequency, voltage, and activity levels.

Results show that the static power of all cores combined contributes as much as 12% of the total CPU package power.

This methodology is designed to be reproducible and transparent, contributing to energy efficiency research by addressing the limitations of current software power meters and offering an offline analysis of static power consumption to be later integrated with a dynamic power consumption model.

## Keywords

Power Models, Static power estimation, Heat Source Identification

## ACM Reference Format:

Gaëtan Barret, Daniel Chillet, Roland Picard, and Joël Penhoat. 2025. Towards Accurate Static Power Model on Multi-Core Operating Systems. In *Rapid Simulation and Performance Evaluation for Design (RAPIDO '25), January 21, 2025, Barcelona, Spain*. ACM, New York, NY, USA, 7 pages. https://doi.org/10.1145/3721848.3721849

<figure><img src="image_3.png" /></figure>

This work is licensed under a Creative Commons Attribution International 4.0 License.

RAPIDO '25, Barcelona, Spain
© 2025 Copyright held by the owner/author(s).
ACM ISBN 979-8-4007-1471-9/25/01
https://doi.org/10.1145/3721848.3721849

Daniel Chillet
University of Rennes, INRIA, IRISA
Lannion, France
daniel.chillet@irisa.fr

Joël Penhoat
Orange Labs
Lannion, France
joel.penhoat@orange.com

## 1 Introduction

Energy efficiency has emerged as a critical concern in modern computing systems, driven by the escalating demand for high-performance multi-core processors and the imperative to reduce operational costs and environmental impact. In this context, accurate power consumption modeling is essential for optimizing system performance, managing thermal conditions, and enhancing overall energy efficiency. Among the various components of power consumption in electronic devices, static power—primarily resulting from leakage currents—constitutes a significant portion, especially as transistor sizes continue to shrink in advanced semiconductor technologies [12].

Software-based power meters, such as PowerAPI [14], provide a convenient and easily deployable means of monitoring energy consumption within computing infrastructures. These tools facilitate the measurement and analysis of power usage at the software level, enabling the estimation of power consumption associated with individual processes or applications. However, existing software power meters often focus predominantly on dynamic power, which is related to active computation and depends on factors like clock frequency and voltage, while under-representing static power, which is considered constant regardless of computational activity. This oversight can lead to incomplete or inaccurate assessments of a system's total power consumption [12, 23].

In academic research, state-of-the-art power models [6, 14] rely on metrics such as CPU core frequencies and a fixed set of performance events extracted for each active process to estimate total power consumption. These approaches exhibit limitations in capturing static power accurately, as the selected performance events are more strongly correlated with dynamic power and can vary significantly across different processor architectures [5]. Similarly, in industrial applications, popular container orchestrators, like Kubernetes [15], have integrated electrical power management tools that approximate dynamic power based on CPU frequencies, often neglecting the static power component. This underestimation of static power poses challenges for comprehensive power modeling and energy efficiency optimization, as static power becomes increasingly significant in modern multi-core CPUs.

To address this gap, this study focuses on developing an accurate static power estimation model for multi-core CPU architectures using offline data derived from controlled experiments. The paper is organized as follows:
* **Background:** Introduces the key concepts of CPU power consumption (Section 2).

* **Related Works:** Surveys existing power modeling research (Section 3).

* **Experimental Setup:** Outlines the hardware and software configurations used in our experiments (Section 4).

* **Custom Stress Workload Design:** Develops a tailored stress workload to generate comprehensive power and thermal data under various conditions, facilitating the analysis of static power consumption (Section 5).

* **Temperature Correction and Heat Source Analysis:** Details the statistical methods used to refine temperature data from the CPU core and package, and employs correlation analysis to identify key factors influencing heat generation (Section 6).

* **Static Power Estimation and Validation:** Presents and validates a model that utilizes corrected temperature data and processor metrics to accurately estimate the static power consumption of individual CPU cores, demonstrating that static power can account for up to 12% of the total CPU package power (Section 7).

By providing a reproducible and transparent methodology for static power estimation, this work contributes to the development of more comprehensive and accurate software-based power models. These advancements support researchers and developers in enhancing the energy efficiency of computing systems, promoting more sustainable and cost-effective technological solutions.

## 2 Background

Understanding how heat is generated within a processor is essential for setting up a CPU thermal model. Processors consist mainly of transistors that can be in various states—active, inactive, transitioning, or unpowered—each affecting power dissipation differently:

* **Active Transistor:** Transistor switches from 1 to 0 and vice-versa, which produce power consumption, resulting in power dissipation ($P = V \times I$);

* **Inactive Transistor:** Minimal heat dissipation occurs due to leakage currents despite negligible voltages;

* **State Transition:** Voltage and current variations cause temporary peaks in power dissipation;

* **Unpowered Transistor:** No current flows; no heat is dissipated.

To extract the static power from the total power, a specific CPU feature is needed. Today, that feature does not exist. An alternative would be to approximate the value of the static power based on a CPU leakage currents measurement. Currently, due to the lack of a feature able to isolate leakage current from total current measurement that measurement is impossible. Therefore our work on static power modeling relies on other data and methods. Since the internal states of transistors are inaccessible, we rely on higher-level variables such as CPU thermal sensors, despite their limited precision [8, 9]. Accessible data for modeling includes:

* Core frequencies and voltages;

* Package power consumption via RAPL [17];

* Core activity levels;

* Temperatures of cores, package, and iGPU.

* Performance Monitoring Counters.

To address imprecise temperature data, methods like exponential curve fitting on low-pass filtered data can be employed [19]. This approach reduces measurement noise and characterizes thermal behavior in context. While precise modeling of thermal interactions between cores is complex [20], our work focuses on quantifying these impacts to provide simple insights.

## 3 Related Works

Energy efficiency and thermal management in multi-core CPUs have been extensively studied, particularly due to their importance in optimizing system performance and reducing operational costs [6, 14]. Power consumption in modern processors is broadly categorized into dynamic power, which varies with computational activity, and static power, which is generally considered constant regardless of workload. While dynamic power modeling [10] and thermal-aware scheduling have received significant attention, static power estimation—primarily driven by leakage currents—has been relatively under-explored in real-world hardware environments.

Jay et al. [16] explored the limitations of power estimation tools such as PowerAPI. As depicted in Figure 4.a of their study, PowerAPI exhibits a significant error by consistently overestimating power when compared to RAPL (Running Average Power Limit) measurements.

This discrepancy points to flaws in the estimation formula used by PowerAPI, which employs the SmartWatts [10] model for power estimation. SmartWatts, a self-calibrating software-defined power meter, attempts to isolate static power by logging package and DRAM power consumption during idle state. The static power, $p_{static}$ of a resource res, is calculated as shown in Equation 1.

$$p_{staticres} = \text{median}_{res} - 1.5 \times \text{IQR}_{res} \quad (1)$$

In Equation 1 the median and interquartile range (IQR) are computed from the RAPL measurements to filter out outliers and periodic measurement errors. However, this method only captures the lowest observed power consumption during a period and does not account for the root causes of static power, such as leakage currents that arise from the manufacturing process and temperature variations. SmartWatts, however, only focuses on capturing the results of static power (i.e., observed power at rest) without addressing its fundamental causes, which stem from fabrication processes and temperature.

In contrast, state-of-the-art literature provides more physics-based definitions of static power by focusing on leakage currents. For example, VarSim [22] models static power using the leakage current, $I_{leak}$, with a formula that incorporates key factors such as threshold voltage, gate-to-source voltage, and temperature, as shown in Equation 3 of VarSim [22]. This approach highlights the physical characteristics of transistors and the influence of operating conditions like voltage and temperature.

Compared to the thermally-aware models, such as the one presented by Walker et al. [23], which defines static power as a function $F(V_{dd}, T)$—where $V_{dd}$ is the supply voltage and T is the temperature—we aim to offer a more transparent and analyzable model. These thermally-aware models acknowledge that static power is temperature-dependent and varies with supply voltage, but they do not provide detailed insights into how this function is computed.
<figure><img src="image_4.png" /><figcaption>Figure 1: Workflow of our methodology</figcaption></figure>

Our approach seeks to go beyond these methods by establishing a physically coherent model that is open to analysis and grounded in established principles of leakage current behavior.

This study focuses on developing an offline static power estimation model that adheres to community-approved definitions, while also introducing uncertainty ranges to reflect the absence of a clear ground truth in static power measurement. By using accessible processor metrics and empirical data, we aim to improve the accuracy of software-based power models like PowerAPI, aiming to effectively take into account the static power <fnref n="1" />.

## 4 Experimental Setup

We built the temperature model using an Intel Xeon E-2224 processor (4 cores, hyperthreading disabled), as this was the available hardware for this study, in a controlled environment with stable room temperature <fnref n="2" />. The hardware included only essential components, and for our dataset, we disabled the fan and opened the top case of the U1 server to minimize external cooling effects. The Unified Extensible Firmware Interface (UEFI) was set to "Maximum performance", and we used Ubuntu 22.04 LTS with Linux kernel 5.19. No core isolation was applied, assuming system tasks minimally impact core temperatures. Our methodology comprises three parts:

(1) **Data Generation:** For frequency steps of 0.2 GHz from 0.8 GHz to 3.4 GHz, we executed stress tests for all $2^N$ combinations of active and inactive cores on the CPU with $N$ cores. After each load duration, we included a cool-down phase before the next core combination (see Figure 1a ① and Figure 1b). The monitoring process, not bound to any specific core, collected frequencies, voltages, temperatures, and power consumption four times per second, balancing data granularity and system performance impact.

(2) **Error Correction and Data Correlation Analysis:** Collected temperatures were filtered using a low-pass filter and used to estimate exponential temperature curves for each core. We

conducted a data correlation analysis to identify variables influencing core temperatures and to identify heat sources accordingly utilizing frequencies, voltages and RAPL measurements (Depicted in Figure 1a ②).

(3) **Static Power Estimation and Decomposition:** Using corrected temperatures and heat source decomposition, we estimated the static power of each CPU core to understand the impact of system variables on static power (see Figure 1a ③).

## 5 Custom Stress Test Development

To thoroughly analyze CPU loads, we developed a custom stress test tailored to maximize the load on processor cores while minimizing RAM and shared cache usage. This approach confines activity to the functional units and L1/L2 caches, limiting heat generation to the cores themselves.

Our workload needed to be replicable on all cores without intercore data dependencies. Simple loops with basic operations were insufficient for generating significant activity. Instead, we leveraged the Out-of-Order Execution (OoOE) capabilities of modern processors, which allow instructions to execute in parallel across multiple execution ports if there are no data dependencies [7]. By maximizing port occupancy with carefully selected instructions, we increased instruction throughput, leading to higher power consumption and heat generation.

Previous work, such as the FIRESTARTER tool [11], demonstrated that maximizing power consumption is a multi-parameter problem, with vector instructions (e.g., AVX) being the most energy-consuming. We incorporated these vector instructions into our workload to enhance power usage. Our constraints were:

* Generate heat restricted to CPU cores by using data within L1 and L2 caches.

* Maximize power consumption by fully utilizing execution ports with vector instructions.

* Maintain code simplicity and ease of analysis.

We analyzed our code using tools like LLVM-MCA to estimate instruction execution on processor ports, ensuring efficient parallelization. Considering cache sizes (e.g., for an Intel Xeon E-2224 with 32 KiB L1 and 256 KiB L2 caches per core), we determined the optimal amount of data to use, staying within L2 cache limits to avoid memory bottlenecks.

<footnote n="1">¹Static power is measured in watt, while RAPL measurements are expressed in microjoules.</footnote>

<footnote n="2">²Ambient temperature have an influence on the whole system temperature and needs to be controlled, in our case at 20 degrees Celsius.</footnote>
Through iterative development and testing, we evaluated multiple code versions, measuring power consumption using RAPL registers. We selected the version that maximized power consumption, which utilized a sequence of vector and bit manipulation instructions executed in parallel over the available execution ports:

vfmadd213pd, vfmadd213pd, vpxor, shlx, vfmadd213pd, vpxor, vfmadd213pd, shlx, vfmadd213pd

Our custom stress test provides a consistent and analyzable workload for testing the thermal parameters of CPU cores. We observed that even when only one core is active, inactive cores heat up differently due to thermal coupling and physical proximity as explained in [13].

## 6 Temperature Correction and Heat Source Identification

Accurate temperature measurements are essential for modeling and analyzing the thermal behavior of CPU cores. However, Intel's Digital Thermal Sensors (DTS) exhibit an accuracy of ±5°C [8, 9], introducing noise and outliers into the temperature data. To enhance data reliability, we apply a sliding average filter to smooth short-term fluctuations while preserving temperature trends. We consider that temperature resulting from this filter are close to the ground truth.

With the corrected temperature data, we perform a heat source identification by analyzing the relationships between the processor metrics described in Section 2 and the CPU cores' corrected temperatures.

We employed linear regression across all frequency steps and core combinations to determine the impact of each metric on core temperatures. For each timestamp of our experiment, the linear regression model is defined as follows:

$$y = \theta_0 + \theta_1 \times V_{\text{cores}} + \theta_2 \times F_{\text{cores}} + \theta_3 \times \text{RAPL} + \theta_4 \times A + \theta_5 \times T_p + \epsilon \quad (2)$$

Where:

* $y$ is the **Core Temperature** (Target).

* $V_{\text{cores}}$ denotes **Core Voltages**.

* $F_{\text{cores}}$ stands for **Core Frequencies**.

* RAPL represents RAPL (Running Average Power Limit).

* A indicates **Activity** status ($A = 0$ for Inactive, $A = 1$ for Active).

* $T_p$ is the **Package Temperature**.

* $\theta_0$ is the **intercept**.

* $\theta_1, \theta_2, \theta_3, \theta_4, \theta_5$ are the **regression coefficients** for each respective feature.

* $\epsilon$ is the **error term**.

The regression coefficients were normalized to represent the relative impact of each feature for our setup. Table 1 summarizes these coefficients, highlighting the most impactful features, which, in our case, are the CPU cores' voltages.

Table 1 reveals that each core's temperature is predominantly influenced by its own voltage, accounting for over 50% of the temperature variation. The collective impact of other metrics and cores complements, contributing less than 20%. Summing the impact of all voltages on each core we show that voltages contribute for at least 99% of each core's heat generation.

To validate our regression model, we evaluated its performance using metrics such as Mean Absolute Error (MAE), Root Mean Squared Error (RMSE), and R-squared ($R^2$), as shown in Table 1. The high $R^2$ values and low error metrics indicate that our linear regression model accurately predicts core temperatures based primarily on core-specific voltages. Notably, our MAE and RMSE values are lower than the sensor's precision, which is encouraging and underscores the model's reliability. These results align with existing studies [20], confirming the significant role of core voltages in thermal behavior. In summary, by applying a sliding average filter to correct temperature measurements and performing regression analysis, we identify core voltages as the primary drivers of temperature variations. This streamlined approach enhances the thermal modeling process, facilitating more focused power and temperature management strategies in multi-core CPU architectures.

<table><caption>Table 1: Normalized Feature Importances and Model Performance Metrics for Core Temperatures</caption><thead><tr><th>Feature</th><th>Core 0</th><th>Core 1</th><th>Core 2</th><th>Core 3</th></tr></thead><tbody><tr><td>Voltage Core 0</td><td>82.87%</td><td>11.67%</td><td>3.14%</td><td>5.73%</td></tr><tr><td>Voltage Core 1</td><td>8.18%</td><td>74.71%</td><td>12.02%</td><td>2.74%</td></tr><tr><td>Voltage Core 2</td><td>6.32%</td><td>4.80%</td><td>78.77%</td><td>9.32%</td></tr><tr><td>Voltage Core 3</td><td>1.96%</td><td>8.32%</td><td>5.59%</td><td>81.63%</td></tr><tr><td>Other metrics</td><td>0.67%</td><td>0.50%</td><td>0.48%</td><td>0.58%</td></tr><tr><th colspan="5">Model Performance</th></tr><tr><td>MAE (Celsius)</td><td>1.75</td><td>1.94</td><td>1.91</td><td>2.01</td></tr><tr><td>RMSE (Celsius)</td><td>2.2</td><td>2.46</td><td>2.4</td><td>2.5</td></tr><tr><td>R2 (Unitless)</td><td>0.92</td><td>0.91</td><td>0.91</td><td>0.91</td></tr></tbody></table>

## 7 Static power modeling and model validation

Modeling static power without knowledge of the manufacturing processes of the observed system is a challenge. Indeed, without access to the specifications of the transistors and the density of transistors per functional unit of the CPU, the only way to perform this modeling is through a rough estimation using parameters found in the field of CPU simulation modeling as well as in industrial patents. The list below shows the values we tried to estimate to represent Intel's 14nm technology used for the Coffee Lake Xeon 2224 CPU. The following parameters are the results of an analysis compilation of data from multiple online sources [1-4, 21].

* **Parameters**

- T: One core temperature in Kelvin (variable)

- Vcore: Core voltage in volts (variable)

* **Constants**

- $k = 1.380649 \times 10^{-23}$ J/K

- $q = 1.602176634 \times 10^{-19}$ C

- $V_{gs} = -0.4$ V

- $V_{th} = 0.15$ V

- $V_{off} = 0$ V

- $V_{ds} = 0.05$ V

- $\eta = \frac{4}{3}$

- $\mu_0 = 300 \times 10^{-4}$ cm$^2$/Vs

- $N = 4$

- $N_t = 5 \times 10^9$ (total number of transistors)

- $R_u = 0.5$ (ratio of uncore transistors)
- $\beta_{\text{leak}} = 1 \text{ A/V}^2$ (coefficient of proportionality for leakage current)

- $\beta_{\text{scale}} = 1$ (scaling coefficient)

## Derived Quantity

- $N_{ct} = \frac{N_t \times (1 - R_u)}{N}$ (number of transistors per core)

Basing ourselves on the works [18, 22], we will define the static power using the leakage current by estimating the subthreshold leakage current.

The subthreshold leakage current, $I_{\text{leak}}$ is proportional to the square of the thermal voltage, $V_t$ is defined in equation 3a, and is exponentially dependent on the difference between the gate-to-source voltage, $V_{gs}$, the threshold voltage, $V_{th}$, and the offset voltage, $V_{off}$, divided by the product of the thermal voltage and a constant factor, $\eta$. Additionally, it is modulated by a factor that accounts for the drain-to-source voltage, $V_{ds}$.

$$V_t = \frac{k \times T_{\text{kelvin}}}{q} \qquad (3a)$$

$$I_{\text{leak}} = \beta_{\text{leak}} \times V_t^2 \times \exp\left(\frac{V_{gs} - V_{th} - V_{off}}{\eta V_t}\right) \times \left(1 - \exp\left(\frac{-V_{ds}}{V_t}\right)\right) \quad (3b)$$

Derived from [22], Equations 3a and 3b allow us to estimate the leakage current for one transistor. We introduced the coefficient $\beta_{\text{leak}}$ in our model (see Equation 3b) because Equation 3 in [22] represents a proportional relationship ($\propto$) rather than an equality ($=$) between the two expressions. In the absence of empirical data, we set $\beta_{\text{leak}} = 1$ to assume a direct proportionality for simplification purposes.

To estimate the leakage current at core level, our model makes the hypothesis that the $N_{ct}$ transistors contribution to the core's leakage current is expressed by equation 4. It means that the leakage current of a given transistor can be added with the leakage current of another transistor without any interference between them.

$$I_{\text{core\_leak}} = I_{\text{leak}} \times N_{ct} \qquad (4)$$

Once the leakage current of a core is computed, its static power is obtained by multiplying $I_{\text{core\_leak}}$ with the core's voltage $V_{\text{core}}$ (refer to eq. 5). To account for the scaling of voltage across multiple transistor stages, we introduce an additional proportionality coefficient, $\beta_{\text{scale}}$, into the static power equation. Due to the inability to determine $\beta_{\text{scale}}$, we set $\beta_{\text{scale}} = 1$, assuming that the proportion of voltage across each transistor stage remains consistent. This leads to a linear scaling of static power with leakage current and core voltage, effectively simplifying the model while maintaining its integrity within the scope of available data.

$$\text{Core}_{\text{static\_power}} = \beta_{\text{scale}} \times I_{\text{core\_leak}} \times V_{\text{core}} \qquad (5)$$

In Section 6, we quantified the effect of each CPU metric on core temperatures. Referring to Table 1, we identify core voltage $V_{\text{core}}$ as the main contributor to leakage current $I_{\text{leak}}$. The collective impact of all cores' $V_{\text{core}}$ accounts for more than 99% of the temperature variation, with each individual core's $V_{\text{core}}$ being a substantial contributor. Therefore, we simplify our model by considering only $V_{\text{cores}}$. We estimate the leakage current based on the temperature resulting from each core's $V_{\text{core}}$ defined as $I_{\text{leak}}(T_{V_{\text{cores}}})$, as expressed in Equation 6:

$$I_{\text{leak}}(T) \approx I_{\text{leak}}(T_{V_{\text{cores}}}) \qquad (6)$$

This approximation allows us to estimate the leakage current based solely on the temperature resulting from the core's voltage, effectively capturing the dominant factor influencing $I_{\text{leak}}$. Consequently, we apply the same impact percentages from the temperature variation (Table 1) to the static power, assuming a direct correlation between temperature-induced leakage and static power.

To validate our static power estimation model, we examined the stability of dynamic power ($P_{dyn}$) during the stress phase across various operating frequencies. Under a constant workload and accurate static power estimation, $P_{dyn}$ is expected to remain stable over time, indicated by near-zero slopes in linear regression analysis. Table 2 shows that at lower frequencies (e.g., 0.8 GHz), $P_{dyn}$

<table><caption>Table 2: Dynamic Power Stability Across Frequencies</caption><thead><tr><th>Profile</th><th>Freq. (GHz)</th><th>Slope (W/s)</th><th>R<sup>2</sup></th><th>CV (%)</th></tr></thead><tbody><tr><td>0_0_0_1</td><td>0.8</td><td>1 &times; 10<sup>-4</sup></td><td>0.45</td><td>3.28</td></tr><tr><td>0_0_0_1</td><td>1.0</td><td>-1 &times; 10<sup>-4</sup></td><td>0.27</td><td>2.52</td></tr><tr><td>0_0_0_1</td><td>3.4</td><td>8 &times; 10<sup>-4</sup></td><td>0.05</td><td>4.15</td></tr><tr><td>1_1_1_1</td><td>0.8</td><td>-1 &times; 10<sup>-4</sup></td><td>0.25</td><td>12.75</td></tr><tr><td>1_1_1_1</td><td>3.4</td><td>-0.006</td><td>0.065</td><td>67.31</td></tr></tbody></table>

remains highly stable with minimal slope deviations ($\approx 1 \times 10^{-4}$ W/s) and low coefficients of variation (CV $\approx 3\%$). This confirms the model's accuracy under these conditions. Conversely, higher frequencies (e.g., 3.4 GHz) exhibit increased variability, with larger slope magnitudes (up to -0.006 W/s) and significantly higher CV values (up to 67.31%). These fluctuations at elevated frequencies likely result from model estimation errors, parameter variability, intensified thermal effects under high operational stress or thermal throttling observed at frequencies higher than 2.8GHz (observable on figure 2 through the total power consumption, originating from high frequency variations).

Despite non-zero slopes at higher frequencies, the overall percentage change in $P_{dyn}$ remains low. For example, at 3.4 GHz, the $P_{dyn}$ change over a 300-second stress phase is approximately 0.24 W, which is less than 2% of the mean $P_{dyn}$. This indicates that, although there are inaccuracies in static power estimation at higher frequencies, the model maintains high stability and accuracy across the frequency range under non-throttled scenario.

In conclusion, our analysis validates the static power estimation model by demonstrating stable $P_{dyn}$ under lower-frequency operations. While some inconsistencies appear at higher frequencies, the model effectively captures the primary contributors to leakage current based on core temperature and voltage, highlighting areas for future refinement under more demanding conditions.

# 8 Conclusion and Future Work

This paper addresses the challenge of accurately modeling static power consumption in multi-core CPU architectures. Through experiments and a straightforward methodology, we have demonstrated that CPU core's static power can account for up to 12% of the total power consumption of a CPU package as observable on figure 2. This significant proportion underscores the necessity of incorporating static power considerations into existing power models to achieve a precise understanding of energy consumption in modern processors.
<figure><img src="image_5.png" /><figcaption>Figure 2: Static power validation through dynamic power slope against theoretical dynamic power slope</figcaption></figure>

Our static power modeling approach is founded on three steps: ① data generation utilizing a custom-designed stress test tailored for CPU cores, ② offline temperature data correction to mitigate sensor inaccuracies, data correlation analysis for precise heat source identification, and ③ static power estimation based on the corrected temperature data. This systematic methodology not only enhances the accuracy of static power estimates but also ensures the reproducibility and transparency of our results.

The validation of our model through controlled experiments affirms its reliability and effectiveness across a range of operating frequencies. At higher frequencies, where dynamic power variability posed challenges due to thermal throttling in our setup, our model maintained a some degree of stability but needs to be improved.

Looking ahead, our future work will extend the current framework to encompass uncore and RAM components, thereby providing a more comprehensive power model that accounts for all facets of CPU-related energy consumption. We also plan on addressing the static power estimation irregularities supposedly induced by thermal throttling in our data. Additionally, we intend to investigate the influence of Linux schedulers on static power, offering deeper insights into how system-level software optimizations can further enhance energy efficiency. Our approach could benefit from industrial partnerships to access more data about the CPU electrical specifications.

Furthermore, we acknowledge the necessity of addressing certain limitations identified in this study, particularly the extended duration required to elevate temperatures due to the use of oversized cooling solutions during stress testing. To overcome this challenge, future research will investigate optimized stress-test methodologies that leverage exponential temperature approximation techniques based on initial temperature samples, enabling faster thermal stabilization and more efficient data collection. By implementing these advanced strategies, we aim to significantly enhance the precision of static power estimations and advance the development of more energy-efficient multi-core systems.

In conclusion, this work lays some foundations for advancing static power modeling in multi-core CPUs, offering possible improvement over existing software-based power meters.

## References

[1] [n. d.]. Equivalent Oxide Thickness. https://en.wikichip.org/wiki/equivalent_oxide_thickness. Accessed: 2024-10-20.

[2] 2014. Patent US8772149B2. https://patents.google.com/patent/US8772149B2/en
Accessed: 2024-10-20.

[3] 2019. Patent US10170593B2. https://patents.google.com/patent/US10170593/en
Accessed: 2024-10-20.

[4] 2023. EP Patent EP4254500NWA2. https://data.epo.org/publication-server/est/v1.0/publication-dates/20231004/patents/EP4254500NWA2/document.pdf
Accessed: 2024-10-20.

[5] Andreas Abel and Jan Reineke. 2014. Reverse engineering of cache replacement policies in Intel microprocessors and their evaluation. In *2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)*. IEEE, CA, USA. doi:10.1109/ISPASS.2014.6844475

[6] Marcelo Amaral, Huamin Chen, Tatsuhiro Chiba, Rina Nakazawa, Sunyanan Choochotkaew, Eun Kyung Lee, and Tamar Eilam. 2023. Kepler: A Framework to Calculate the Energy Consumption of Containerized Applications. In *2023 IEEE 16th International Conference on Cloud Computing (CLOUD)*. IEEE, Chicago, IL, USA. doi:10.1109/CLOUD60044.2023.00017

[7] Denis Bakhvalov. 2018. Understanding CPU Port Contention. https://easyperf.net/blog/2018/03/21/port-contention Accessed: 2024-08-14.

[8] Intel Corporation. 2023. Intel 13-14th Gen Datasheet. https://edc.intel.com/conten
t/www/ca/fr/design/products/platforms/details/raptor-lake-s/13th-generation-
core-processors-datasheet-volume-1-of-2/011/digital-thermal-sensor/
Accessed: 2024-08-14.

[9] Intel Corporation. 2023. Intel 8-9th Gen Datasheet. https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/8th-gen-core-family-datasheet-vol-1.pdf. Accessed: 2024-08-14.

[10] Guillaume Fieni, Romain Rouvoy, and Lionel Seinturier. 2020. SmartWatts: Self-Calibrating Software-Defined Power Meter for Containers. IEEE. doi:10.1109/ccgrid49817.2020.00-45

[11] Daniel Hackenberg, Roland Oldenburg, Daniel Molka, and Robert Schone. 2013. Introducing FIRESTARTER: A processor stress test utility. In *2013 International Green Computing Conference Proceedings*. IEEE, Arlington, VA, USA. doi:10.1109/IGCC.2013.6604507

[12] Jawad Haj-Yahya, Avi Mendelson, Yosi Ben Asher, and Anupam Chattopadhyay. 2018. Static Power Modeling for Modern Processor. In *Energy Efficient High Performance Processors*. Springer Singapore, Singapore. doi:10.1007/978-981-10-8554-3_5 Series Title: Computer Architecture and Design Methodologies.

[13] Seyedmehdi Hosseinimotlagh, Daniel Enright, Christian R. Shelton, and Hyoseung Kim. 2021. Data-Driven Structured Thermal Modeling for COTS Multi-core Processors. In *2021 IEEE Real-Time Systems Symposium (RTSS)*. IEEE, Dortmund, DE. doi:10.1109/RTSS52674.2021.00028

[14] Inria. [n. d.]. PowerAPI: Measuring Power Consumption of your Applications. https://powerapi.org/. Accessed: 2024-08-14.

[15] Intel. 2022. Power Manager - Kubernetes Operator Technology Guide. https://networkbuilders.intel.com/solutionslibrary/power-manager-a-kubernetes-power-operator-technology-guide. Accessed: 2024-08-14.

[16] Mathilde Jay, Vladimir Ostapenco, Laurent Lefevre, Denis Trystram, Anne-Cécile Orgerie, and Benjamin Fichel. 2023. An experimental comparison of software-based power meters: focus on CPU and GPU. doi:10.1109/CCGrid57682.2023.00020

[17] lwn.net. [n. d.]. RAPL (Running Average Power Limit) driver. https://lwn.net/Articles/545745/. Accessed: 2024-08-14.

[18] G Ramana Murthy, C Senthilpari, P Velrajkumar, and Lim Tien Sze. [n. d.]. Leakage Current Optimization For Novel MUX-Based Full-Adder Cell In CMOS 130nm Technology. ([n. d.]).
[19] Javier Pérez Rodriguez and Patrick Meumeu Yomsi. 2021. An Efficient Proactive Thermal-Aware Scheduler for DVFS-enabled Single-Core Processors. In *29th International Conference on Real-Time Networks and Systems*. ACM, NANTES France. doi:10.1145/3453417.3453430

[20] Javier Pérez Rodriguez, Patrick Meumeu Yomsi, Yilian Ribot González, and Luis Javier Pente Lam. 2023. B-TSP: An Advanced Power Safe Management Strategy for modern Multi-core Platforms under Thermal-Aware Design. In *The 31st International Conference on Real-Time Networks and Systems*. ACM, Dortmund Germany. doi:10.1145/3575757.3593659

[21] Abdoul Rjoub, Nedal R. Al-Taradeh, and Mamoun F. Al-Mistarihi. 2013. Accurate subthreshold leakage model for nanoscale MOSFET transistor. 711–714. doi:10.1 109/ICECS.2013.6815513

[22] Hameedah Sultan and Smruti R. Sarangi. 2023. VarSim: A Fast Process Variation-aware Thermal Modeling Methodology Using Green's Functions. http://arxiv.org/abs/2307.12119 arXiv:2307.12119 [cs].

[23] Matthew J. Walker, Stephan Diestelhorst, Andreas Hansson, Domenico Balsamo, Geoff V. Merrett, and Bashir M. Al-Hashimi. 2016. Thermally-aware composite run-time CPU power models. IEEE, Bremen, Germany. doi:10.1109/PATMOS.201 6.7833420