<figure><img src="image_71.png" /><figcaption>Figure III.32. Pole figures obtained for d = 2.02 Å after the reaction of a 7 nm Ni(15 at.% Pt) film with Si<sub>0.7</sub>Ge<sub>0.3</sub> substrate during a RTA1 at 280 °C for 30 s. The experiment is performed after the selective etching.</figcaption></figure>

Based on in-situ XRD results (Figs. III. 25 and 26), we suppose that the phase formed after RTA1 presents similar characteristics of θ-Ni<sub>2</sub>Si phase. To confirm this hypothesis, the simulated stereographic projection for θ-Ni<sub>2</sub>Si phase obtained through the Carine Crystallography software in the same range of φ and ψ is given in the Figure III.33:

<figure><img src="image_72.png" /><figcaption>Figure III.33. Simulated stereographic projection of θ-Ni<sub>2</sub>Si phase (in red) growing in epitaxy on Si(001) substrate (in blue). The {311} Si planes are not represented here in the snake of reading simplicity (from [6]).</figcaption></figure>

By comparing the measured and simulated stereographic projections, the “c1” and “c2” diffraction patterns are attributed to the {110} and {102} planes of the θ-Ni(Pt)<sub>2</sub>SiGe phase. Nevertheless, and as previously discussed for Ni(10 at.% Pt) samples the measured inter-planes distances d are strictly larger than expected as presented in the Table III.6:

<table><caption>Table III.6. Calculated inter-planes distances d of θ-Ni<sub>2</sub>Si and calculated ψ angles compared to (001) planes based on the crystallographic data as: a = b = 3.81 Å and c = 4.89 Å, α = β = 90° and γ = 120°.</caption><thead><tr><td>hkl</td><td>d (Å)</td><td>ψ angles compared to (001) planes</td><td>Intensity (%)</td><td>Labels in Figure III.32</td></tr></thead><tbody><tr><td>102</td><td>1.96</td><td>53</td><td>100</td><td>c2</td></tr><tr><td>110</td><td>1.90</td><td>30</td><td>90</td><td>c1</td></tr></tbody></table>
The Pt and Ge addition inside the lattice of θ-Ni₂Si could play a role on the inter-planes distance. This might induce an increase of the lattice parameter and then of the inter-planes distance. Another explanation could be an enrichment in Si inside the lattice since θ-Ni₂Si could be observed with a typical Si concentration comprised between 33 and 40 at.% for Ni(10 at.% Pt)-Si system (as presented in Figure III. 2, [160]). For these calculations, a stoichiometric θ-Ni₂Si phase and then a Si concentration of 33 at.% is used.

Based on the pole figure results, for Ni(15 at.% Pt)-Si<sub>0.7</sub>Ge<sub>0.3</sub> system, the simulated stereographic projection (Figure III.33) enables to clearly identify the epitaxial relationships between Si<sub>0.7</sub>Ge<sub>0.3</sub> substrate and θ-Ni<sub>2</sub>Si after RTA1 as :

- (100) θ-Ni₂SiGe planes aligned on the (001) Si<sub>0.7</sub>Ge<sub>0.3</sub> planes

- (120) and (001) θ-Ni₂SiGe planes aligned on (110) Si<sub>0.7</sub>Ge<sub>0.3</sub> planes

The comparison between the pole figure and simulated stereographic projection does not allow to identify the “c3” patterns.

As explained in section III.3.1.3, ACOM-TEM analyses are provided on additional samples which are produced by following the standard 14 nm FD-SOI process flow up to silicide formation and SiN encapsulation. Ni(Pt)Si silicide is formed by the reaction of 10 nm Ni(15 at.% Pt) film with in-situ raised source/drains Si<sub>0.7</sub>Ge<sub>0.3</sub> epitaxial zones. After NiPt deposition, RTA1 is performed, followed by the classical selective etching. Two RTA1 thermal budgets have been studied here at 230 °C and 260 °C during 30 s. RTA2 is provided to form the mono-germano-silicide. As well as described in the previous section, orientation mappings along Si(100) and Si(110) planes are obtained using the ASTAR™ system and displayed in Figure III.34.

After an RTA1 at 230 °C, the mono-germano-silicide layer is very thin, (Figs. III.34a and b), thinner than measured for Ni(10 at.% Pt) samples (Figs. III.30a and b). This observation is in good accordance with the preliminary conclusions on the phase sequence changes in the reaction between NiPt layer and Si<sub>0.7</sub>Ge<sub>0.3</sub> substrate by increasing the Pt concentration detailed in Figure III.26. The delay observed in the NiPt phase consumption on in-situ XRD diagrams for Ni(15 at.% Pt) samples compared to lower Pt concentration ones explains this result. For Ni(15 at.% Pt) samples, the thickness of θ-Ni₂Si formed after a RTA1 at 230 °C should be low inducing, after selective etching, a very thin layer of mono-germano-silicide in this case after RTA2. Nonetheless, no specific texture is evidenced here even though it is quite difficult to formulate a conclusion on the layer texture due to its thinness.

If the RTA1 temperature is set to 260 °C, as expected, the mono-germano-silicide layer is thicker and a correct indexation of Ni(Pt)SiGe grains orientations could be then provided (Figs. III.34 c and d). Based on previous in-situ XRD (Figure III.26), an epitaxial texture is assumed for this platinum concentration and ASTAR™ orientation mappings confirm this preliminary conclusion.

A continuum of colors between Ni(Pt)SiGe grains and Si<sub>0.7</sub>Ge<sub>0.3</sub> substrate is identified for both studied substrate directions as (001) and (110) (Figs. III.34 c and d). In Figure III.34c, perpendicular to the Si[001] direction, a large numbers of Ni(Pt)SiGe grains are colored in red as the substrate. Moreover, in Figure III.34d, Ni(Pt)SiGe grains are almost colored in green as the substrate
perpendicular to the [101] Si direction (please refer to the color map displayed in Figure III.34 e and f for details).

The inverse pole figures are plotted in the Figures III.34g and h. Referring to the Figure III.34c, along Si(100) planes, two different Ni(Pt)SiGe planes are noticed as red and violet corresponding on the inverse pole figure to (001) and (011) (Fig. III.34g). In Figure III.34d, by comparing the color map and the inverse pole figure parallel to the Si(110) planes (Figs. III.34f and h), the indexation of Ni(Pt)SiGe grains is the following: blue grains are oriented in 010 direction, pink grains refer to 013 and green ones to 100.

<figure><img src="image_73.png" /><figcaption>Figure III.34. ASTAR™ mappings of Ni(Pt)SiGe grains formed by the reaction of a 10 nm Ni(15 at. % Pt) film with Si<sub>0.7</sub>Ge<sub>0.3</sub> epitaxial layer after RTA2 for a RTA1 temperature of 230 °C (a, b) and 260 °C (c, d). Si[001] and Si[110] directions are colored respectively in red and green as described in the color map (e). The Ni(Pt)SiGe grains are colored as given in (f). The inverse pole figure extracted from (c) and (d) aligned on Si(100) and Si(110) planes respectively are then presented in (g) and (h).</figcaption></figure>

Based results presented below, the pole figures, based on ASTAR™ mappings of Figs. III.34c and d, are extracted for the sample submitted to a RTA1 at 260 °C (Fig. III.35).

<figure><img src="image_74.png" /><figcaption>Figure III.35. Pole figures extracted from ASTAR™ mappings shown in Figures III.34c and d obtained after the complete silicide process of a 10 nm Ni(15 at.% Pt) film deposited on Si<sub>0.7</sub>Ge<sub>0.3</sub> epitaxial layer. Please note that only the Ni(Pt)SiGe diffraction patterns are considered here contrary to the XRD pole figures which integrate the signal coming from the silicide layer and the substrate.</figcaption></figure>
Epitaxial texture is obviously detected. The following epitaxial relationships are identified for Ni(15 at.% Pt)-Si<sub>0.7</sub>Ge<sub>0.3</sub> system after RTA2 as :

- (001) and (011) Ni(Pt)SiGe planes aligned on the (001) Si<sub>0.7</sub>Ge<sub>0.3</sub> planes.

- (100), (010) and (013) Ni(Pt)SiGe planes aligned on the (110) Si<sub>0.7</sub>Ge<sub>0.3</sub> planes.

Several studies reported the texture inheritance between the Ni-rich phases and the final mono-silicide phase [150], [190], [191]. Based on the current work on Ni(15 at.% Pt)-Si<sub>0.7</sub>Ge<sub>0.3</sub> system, forming an epitaxial Ni-rich phase, such as θ-Ni<sub>2</sub>Si, after RTA1 and the complete transformation of this phase in an epitaxial mono-germano-silicide layer appears to be the right hypothesis. This novel result is a clear demonstration of the predominant impact on the final silicide layer properties of the first growing phase texture. In the frame of microelectronics devices development and the suppression of Ni-based silicides or germanides thermal instabilities, forming such epitaxial texture could reduce the silicide/substrate interface energy, and potentially the grain boundaries grooving (related to a reduced grain boundary energy, for details please refer to section III.5.1). From another point of view, an hetero-epitaxial Ni(Pt)-based silicide (or germanide) layer is also an enabler in the leveling of shallow junction leakage through the clear reduction of silicide/substrate roughness in this case. In a recent paper of Kim at al. [148], an epitaxially grow of Ni<sub>1-w</sub>Pt<sub>w</sub>Si layer is obtained via a melting/quenching process using high temperature laser annealing on a Si(001) substrate. The authors explain such results by larger Pt incorporation inducing an increase in only one direction parallel to the film surface (lattice parameter a). Then, high Pt concentration could be the explanation of the hetero-epitaxial structure of Ni(Pt)SiGe compound here, as discussed in the next paragraph.

### III.3.1.5 Syntheses and conclusions on NiPt-germano-silicides phase sequence

On one hand, the phase sequence of the reaction between Ni<sub>1-w</sub>Pt<sub>w</sub> (0<w<0.15) films with an epitaxial Si<sub>0.7</sub>Ge<sub>0.3</sub> layer has been investigated through in-situ techniques as four-probe measurements, θ-2θ XRD and TEM. On the other hand, some ex-situ characterizations have been performed to identify the undefined phases during the in-situ XRD experiments as XRD θ-2θ, ACOM-TEM and pole figure analyses obtained at ESRF after RTA1 and RTA2 processes. The in-situ Rs and XRD experiments have been summarized in Fig. III.26 and the summary of complementary characterizations is the following and presented in Figure III.36:

**For Ni sample, in-situ TEM characterizations done at room temperature demonstrate the presence of a hexagonal phase associated to the Ni<sub>31</sub>SiGe<sub>12</sub> phase presenting a clear epitaxial relationship with the substrate as the given epitaxial components of (110) Ni<sub>31</sub>SiGe<sub>12</sub> planes aligned on (001) Si<sub>0.7</sub>Ge<sub>0.3</sub> substrate planes.**

At 280 °C a fiber texture with a strong orientation of δ-phase grains is observed by TEM and confirmed on pole figure as (013) and (020) fiber texture along (001) Si<sub>0.7</sub>Ge<sub>0.3</sub> planes.

At 400 °C a rectangular network is identified related to a potential epitaxy of Ni(Pt)SiGe grains with the substrate. Moreover, a fiber texture is observed but the ring is not continuous, what is indicating a strong texture, and an apparent epitaxial texture is suspected based on in-situ XRD characterizations.
Interesting results are obtained after RTA2 and potentially demonstrate the difference in terms of phase sequence for this system compared to the in-situ “thermal” budget and the real silicide process as a sequence of RTA1, selective etching and RTA2 steps. No specific texture is then observed after RTA2 for the Ni sample, in a disagreement with the in-situ XRD and TEM results.

For the Ni(10 at.% Pt) sample, the ex-situ XRD analyses confirm the presence of an Ni-rich phase growing in epitaxy at 260 °C. Similarly to the Ni(10 at.% Pt)-Si system ([5] [156]), this phase is identified as θ-Ni(Pt)₂SiGe. After RTA2, based on ACOM-TEM results, the texture of mono-germano-silicide layer is depicted as follows:

- (010) epitaxial texture and (013) fiber texture aligned on the (001) Si<sub>0.7</sub>Ge<sub>0.3</sub> planes

- (001) and (011) epitaxial texture aligned on the (110) Si<sub>0.7</sub>Ge<sub>0.3</sub> planes

For the Ni(15 at.% Pt) sample, after RTA1, pole figures explicit the epitaxial relationships as :

- (100) θ-Ni₂SiGe planes aligned on the (001) Si<sub>0.7</sub>Ge<sub>0.3</sub> planes

- (120) and (001) θ-Ni₂SiGe planes aligned on (110) Si<sub>0.7</sub>Ge<sub>0.3</sub> planes

After RTA2, through ACOM-TEM analyses, the mono-germano-silicide presents a hetero-epitaxial texture defined by the following epitaxial relationships as:

- (001) and (011) Ni(Pt)SiGe planes aligned on the (001) Si<sub>0.7</sub>Ge<sub>0.3</sub> planes

- (100), (010) and (013) Ni(Pt)SiGe planes aligned on the (110) Si<sub>0.7</sub>Ge<sub>0.3</sub> planes

Legend : phase texture

<figure><img src="image_75.png" /></figure>

Figure III.36. Schematic of phase sequence during the solid-state reaction of Ni<sub>1-w</sub>Pt<sub>w</sub> (0<w<0.15) films deposited on Si<sub>0.7</sub>Ge<sub>0.3</sub> epitaxial layer based on the in-situ and ex-situ measurements. In addition to in-situ Rs and XRD analyses, the phase texture for Ni, Ni(10 at.% Pt) and Ni(15 at.% Pt) samples have been determined through in-situ TEM, XRD, and ACOM-TEM experiment, as detailed in the dedicated legend.
Here, the main point is the complete epitaxial structure of Ni-rich phase and finally the mono-
germano-silicide one found if the Pt concentration is 15 at.%.

At that point, the hetero-epitaxial texture observed after RTA2 for Ni(15 at.% Pt)-Si<sub>0.7</sub>Ge<sub>0.3</sub> system
could be related to (i) the texture inheritance of θ-Ni<sub>2</sub>SiGe phase or (ii) a change in lattice parameter
inside the final Ni<sub>1-w</sub>Pt<sub>w</sub>Si<sub>1-x</sub>Ge<sub>x</sub> compound due to an increase of Pt incorporation, and a potential
change in Ge concentration also.

To discriminate between these hypotheses, for different Pt and Ge atomic concentrations, the
changes in inter-planar distances d between relevant Ni<sub>1-w</sub>Pt<sub>w</sub>/Si<sub>1-x</sub>Ge<sub>x</sub> planes have been calculated
based on lattice parameters given in Table III.5. As previously explained, in this assumption, both the
Ni and Pt atoms are set on the same sub-lattice whereas Si and Ge atoms share the same sub-lattice.

By applying Vegard's law, the interplanar distances d are calculated for (200) and (220) Si<sub>0.7</sub>Ge<sub>0.3</sub> planes and are respectively equal to 2.752(8) Å and 1.946(5) Å.

The change in Ni<sub>1-w</sub>Pt<sub>w</sub>Si<sub>1-x</sub>Ge<sub>x</sub> lattice parameters linked to Pt or Ge incorporation inside the mono-
germano-silicide phase are calculated for Pt atomic concentration between 1 and 20 at.% (based on
EDX and ToF-SIMS characterizations, not shown here) and for several Ge atomic concentration
between 10 and 33 at.% (as initial epitaxial layer)[76].

Finally, the inter-planar distances d between (002) planes of different mono-germano-silicide are
plotted in Figure III.37a as a function of Pt and Ge atomic concentrations. Moreover, the mismatch
between inter-planar distance d related to (002) Ni(Pt)SiGe and the (200) Si<sub>0.7</sub>Ge<sub>0.3</sub> planes is estimated
and plotted also as a function of Pt and Ge atomic concentrations in Figure III.37b.

<figure><img src="image_76.png" /><figcaption>Figure III.37. Calculated inter-planar distances d (d-spacing) between (002) Ni(Pt)SiGe planes as a function of Pt and Ge atomic concentrations inside Ni(Pt)SiGe phase based on lattice parameter given in Table III.5 (a). Calculated d-spacing mismatch between (002) Ni(Pt)SiGe and the (200) Si<sub>0.7</sub>Ge<sub>0.3</sub> planes as a function of Pt and Ge atomic concentrations inside Ni(Pt)SiGe phase (b).</figcaption></figure>

As shown in Fig. III.37a, the interplanar distances d between (002) Ni(Pt)SiGe planes increase
linearly with Pt and Ge concentrations between a minor value of 2.820(9) and 2.866(0) Å. The
interplanar distance d calculated for (200) Si<sub>0.7</sub>Ge<sub>0.3</sub> planes is estimated to be equal to 2.752(8) Å. Thus,
the d-spacing mismatch between (002) Ni(Pt)SiGe and (200) Si<sub>0.7</sub>Ge<sub>0.3</sub> planes increases significantly as
displayed in Fig. III.37b when Pt and Ge are incorporating in the mono-germano-silicide layer. The
mismatch is estimated to be less than 2.5 % without Pt and for a Ge concentration of 10 at.% and larger
than 4% for the maximum of expected Pt and Ge concentrations.

Such calculations have been performed for all Ni(Pt)SiGe planes in epitaxy with the substrate
detected by ACOM-TEM analyses as (002) (shown in Fig. III.37), (011), (020) and (013).

The only evidence of a suitable change in d-spacing induced by larger Pt incorporation or an
increase of Ge concentration in Ni(Pt)SiGe matrix have been figured out for (020) and (013) planes
with a slight reduction in this case of the d mismatch respectively equal to 13.2% and 15.1%.

At the end, the hetero-epitaxial texture observed by ACOM-TEM for Ni(15 at.% Pt)-Si<sub>0.7</sub>Ge<sub>0.3</sub> system appears to be linked to texture inheritance from θ-Ni<sub>2</sub>SiGe, growing in epitaxy in this case and its complete transformation in the mono-germano-silicide avoiding the δ-Ni<sub>2</sub>SiGe phase formation.

### III.3.2 Kinetics study of Ni(10 at.% Pt)/Si<sub>0.7</sub>Ge<sub>0.3</sub> solid state reactions

III.3.2.1 Apparent activation energies extracted from Kissinger analyses

This paragraph reports the work published by Bourjot at al. on the modeling of in-situ Rs and XRD
measurements obtained from the solid-state reaction between a 7 nm Ni(10 at.% Pt) film and Si<sub>0.7</sub>Ge<sub>0.3</sub>
epitaxial sublayer [186]. Apparent activation energies have been extracted using the Kissinger method
[192] from in-situ sheet resistance measurements with different thermal ramps (Fig. III.38). In order
to determine a growth model of the θ-Ni<sub>2</sub>Si phase, finite difference simulations have been carried out
on both the XRD peak area and the sheet resistance measurements [193].

Figure III.38 shows the normalized in-situ sheet resistance as a function of the temperature for
different thermal ramps between 0.77 °C/min and 9.9 °C/min.

<figure><img src="image_77.png" /><figcaption>Figure III.38. In-situ Rs measurements as a function of temperature during the reaction of a 7 nm Ni(10 at.% Pt) film and Si<sub>0.7</sub>Ge<sub>0.3</sub> epitaxial layer for different thermal ramps comprised between 0.77 and 9.9 °C/min.</figcaption></figure>

The Rs curves have the same shape for all the thermal ramps. However, as the changes in
resistance are associated to the different steps of the reaction, they shift for the different ramps. This
indicates that these steps are thermally activated. From the Kissinger theory applied to silicides [192], the apparent activation energy can be deduced by drawing the Arrhenius plot:

$$ \frac{\ln(\phi)}{T_p^2} = f\left(\frac{1}{k_B T_p}\right) \qquad \text{Eq. III.6} $$

where φ is the thermal ramp given in °C/s, T_p the temperature of the phase transformation given in K and k_B the Boltzmann constant as 1.38064852 E⁻²³ J·K⁻¹.

The apparent activation energy Ea is extracted from the slope of the Arrhenius plot and expressed in eV as 1eV is equal to 1.60217565E⁻¹⁹ J.

However, one may note that the Kissinger method does not take into account any kinetic model. Hence, in case of complex, intermixed or simultaneous phenomena, it refers to an average of activation energies.

In order to extract these activation energies for the θ-Ni₂SiGe, δ-Ni₂SiGe and Ni(Pt)SiGe phases, the critical temperatures for their formation are respectively set to 50 % of the total Ni (10 at.% Pt) consumption for δ-Ni₂SiGe (squares in Fig. III.38, near 200 °C), the first inflexion point related to δ-Ni₂SiGe formation and at the end the second inflexion point at the end of δ-Ni₂SiGe consumption and the beginning of mono-germano-silicide growing (rounds and diamonds in the Fig. III.38 respectively around 280 °C and 300 °C). The Arrhenius diagrams extracted for each phase are plotted in the following figure.

<figure><img src="image_78.png" /><figcaption>Figure III.39. Arrhenius diagrams for θ-Ni₂SiGe, δ-Ni₂SiGe and Ni(Pt)SiGe phases for Ni(10 at.% Pt)-Si₀.₇Ge₀.₃ system.</figcaption></figure>

The apparent activation energies are then 1.0 ± 0.3 eV for the θ-Ni₂SiGe and 1.8 ± 0.3 eV for δ-Ni₂SiGe and mono-germano-silicide phases. This is in a good accordance with the XRD observations, which indicate a very short existence domain for the δ-Ni₂SiGe and the reported simultaneous growing of these two phases by the consumption of θ-Ni₂SiGe [144] [163] [191].
### III.3.2.2 Growth regime of θ-Ni₂SiGe: finite elements simulations

To determine the growth regime of the θ-Ni₂SiGe, finite difference simulations have been performed on both the XRD peak area and the Rs measurements. Kissinger analysis indicates that the temperature of the phase apparition changes as the function of the thermal ramp. Thus, growth limited by diffusion and interface reaction is expected. Then as detailed in subsection III.2.2, for silicides and germanides formation two models could be applied to determine the formation regime of this phase as the linear or the linear-parabolic model [45].

Finite difference simulations based on a parabolic law permit to fit with a good agreement the beginning of Rs curve (Fig. III.38) and of the normalized XRD peak during the consumption of Ni(10 at.% Pt) layer (not shown here), associated to the 9.9 °C/min thermal ramp. Similar fittings were performed for all the temperature ramps and the average results are the following : the exponential pre-factor has been found to be between 0.05 cm²/s and 0.3 cm²/s and activation energy around 1.3 eV whatever the experiment type [186]. The error on the exponential pre-factor and on the activation energy is estimated to be around 1 cm²/s and 0.1 eV respectively.

By comparison with the Kissinger analysis, the activation energy calculated by simulation is in good agreement within the error measurement. For this system, these simulations show that the θ-Ni₂SiGe grows with the parabolic model with an activation energy of 1.3 eV. These results are close to the ones found for Ni(10 at.% Pt)-Si system as presented in § III.2.2.1 based on F. Panciera's Ph.D work.

According to these additional results, two scenarios can be proposed for the phase sequence of the reaction between Ni(10 at.% Pt) and Si₀.₇Ge₀.₃ substrate: (i) as previously presented and detailed in Figs. III.26 and III.36, a sequential phase formation that could be described by a complete consumption of the θ-Ni₂SiGe in δ-Ni₂SiGe before the formation of the mono-germano-silicide. (ii) based on the very close activation energies extracted though Kissinger analyses, the decomposition of θ-Ni₂SiGe in δ-Ni₂SiGe and Ni(Pt)SiGe phases at the same time.

The consumption of the delta phase in mono-germano-silicide for this system becomes more favorable in the kinetics point of view.

To conclude, the increase of Pt concentration inside the NiPt film induce the following changes in terms of phase sequence of the solid-state reaction of NiPt film with the Si₀.₇Ge₀.₃ substrate:

- A preferred formation of θ-Ni₂SiGe and Ni(Pt)SiGe phases to the detriment of the formation and/or the stability of δ-Ni₂SiGe.

- A supposed simultaneous phases formation of δ-Ni₂SiGe and Ni(Pt)SiGe after the decomposition of θ-Ni₂SiGe leading to an early formation of Ni(Pt)SiGe for the higher Pt concentrations of 10 at.%.

- The disappearance of the δ-Ni₂SiGe for Ni(15 at.% Pt) film induces an hetero-epitaxial texture inheritance between θ-Ni₂SiGe and the mono-germano-silicide.
### III.4 Formation of Ni(Pt)-silicide and germano-silicide in nanoscale dimensions

In real microelectronic devices, in-line process control of the silicide formation is only performed after the RTA2 on large undoped active areas, which might be assimilated to blanket Si substrate. Subsequently, if a change occurs in the phase sequence or dopants distribution in the real device induced by the nature of the substrate (poly-Si vs mono-Si, SOI vs bulk), the doping processes or reduced dimensions, this variation will not be well estimated during the die fabrication. Moreover, the formation kinetics might be accelerated or modified in aggressive low-dimensions active areas and the previously established phase sequence formation, including the hexagonal phase one, could be delayed or altered in such zones.

The aim of this section presenting several studies on different substrates, devices, and test structures, is to determine the impact of nano-scale dimensions on the Ni(Pt) silicide and germano-silicide formation.

This section is a summary of experimental results obtained during the Ph. D works of Federico Panciera [5], Mathilde Lemang [170], and Emilie Bourjot [6].

#### III.4.1 APT analyses in source/drain and gate of CMOS devices

Hereafter, the nature of Ni(Pt) silicides contacts and the redistribution of Pt on source, drain and polycrystalline silicon (poly-Si) gate regions of transistors are investigated by APT. The analyzed devices are respectively a 45 nm NMOS taken from a SRAM cell (Static Random-Access Memory) having a typical 0.3 µm² surface and 28 nm NMOS one. These results are then compared to the ones deduced from blanket wafers measurements (§ III.2). For both devices, As species are used for substrate doping.

##### III.4.1.1 45 nm NMOS devices with Ni(5 at.% Pt) alloy

The analyzed 45 nm CMOS device was made following the standard process flow. The Ni-silicide contacts have been formed by reaction of 8.5 nm thick Ni(5 at.% Pt) film with doped silicon after a RTA1 at 340 °C for 60 s, followed by a selective etching and a RTA2 at 390 °C for 30 s. The samples are then covered with a protection Cr layer for APT characterizations. For APT analysis of transistors, specific preparation technique is required to place a transistor at the tip apex [162]. The APT analyses were carried out in a LEAP 3000X HR instrument at IM2NP. Data reconstruction was done with the commercial IVAS software. After RTA1 and RTA2, the silicide phase, Pt and As redistributions are determined on gate and source of this device.

3D reconstructed APT volumes obtained in a gate of 45nm NMOS transistor are shown in Fig.III.40. After RTA1, the silicide composition is similar to the δ-Ni₂Si phase as expected for the 5 at.% Pt concentration (Fig. III.40b). We observe that Pt is mainly located at the surface of the silicide and at the interface of silicide/poly-Si, and As is segregated at silicide/poly-Si interface (Fig. III.40b). After RTA2, the 1D concentration profile enables to identify Pt accumulation in the upper part of the silicide layer and a complete Pt depletion in the lower part of this layer (Figs. III.40c and d). On the
contrary, As is also segregated, as after RTA1, at silicide/poly-Si interface. Indeed, on the gate, the Ni(Pt)Si phase is formed (50 ± 2 at.% Ni and 50 ± 2 at.% Si) after RTA2 and As and Pt distributions are similar to the ones reported for a reaction of Ni(5 at. % Pt) blanket Si wafers [157].

<figure><img src="image_79.png" /><figcaption>Figure III.40. 3D reconstructed APT volume obtained on the gate of a 45 nm NMOS devices (a), after RTA1 (b) and after RTA2 (c, d). The As and Pt distributions are separated in (b). 1D concentration profile of Si, Ni, Pt and As after RTA2 calculated in a 25 nm diameter cylindrical region of (c) following the white arrow (d).</figcaption></figure>

3D reconstructed APT volume obtained in the source (doped mono-Si) of a 45 nm NMOS device is presented in Figure III.41.

<figure><img src="image_80.png" /><figcaption>Figure III.34. 3D reconstructed APT volume obtained in the source/drain of 45nm NMOS device after RTA2 (a). The As and Pt distributions are separated. 1D concentration profile of Si, Ni, Pt and As calculated in a 25 nm diameter cylindrical region of (a) (b).</figcaption></figure>
The composition (65 ± 2 at.% Ni and 35 ± 2 at.% Si) of the silicide corresponds to the δ-Ni₂Si phase (Fig. III.41b) while the two regions, gate and source, have received the same heat treatment. Indeed, on the gate, the NiSi phase is formed whereas in the source, after RTA2, the δ-Ni₂Si phase is clearly detected. This is confirmed also by the large difference in the thickness of the silicide layers on gate and source: respectively 20 and 10 nm. Moreover, the concentration profiles for Pt and As are also very different on the gate and in the source regarding the nature of formed silicide phase.

These results show that APT analysis is making possible the precise determination of the silicidation state after RTA2 in real devices.

Regarding the formation of Ni(Pt)Si, our results show that for an equivalent heat treatment, Ni(Pt)Si is not formed on the 45-nm-transistor sources but is formed on the gates. Of course, this conclusion is taken from a limited number of analyses due to the experimental difficulties and may not be representative of all the transistors. However, it reflects that the formation of NiSi is not always possible in the source after RTA2, and that an high resistive δ-Ni₂Si phase leads to a drastic increase of the access resistance to the transistors which could induce severe device failures. Comparing our results with the literature, the formation of Ni(Pt)Si is expected after RTA2 for the reaction of Ni(5 at.% Pt) with the mono-Si substrate [19]. It is possible that the metal film, for this type of deposition chamber, is thinner in the source/drain area due to shadowing effect of the gate [32]. Nevertheless, lower thickness will induce an acceleration of the reaction and here it slows down in source/drain. Consequently, the main difference between the reactions in these two areas seems not to be the thickness of the metal film but potentially a lack in the surface preparation inducing the surface contamination of O, C, or F impurities during photolithography steps. Such contamination could induce a delay in the phase sequence formation.

### III.4.1.2 28 nm CMOS devices with Ni(10 at.% Pt) alloy

For 28 nm transistor, the analyzed Ni-silicide was formed by the reaction of 11 nm of Ni(10 at.% Pt) film with As doped silicon after a RTA1 at 280 °C for 60 s, a selective etch and a RTA2 at 390 °C for 30 s. In addition, blanket wafer and test zone samples were analyzed after the same silicide process (not shown here, reported in [5], [195]).

After RTA2, Figs. III.42a to c show the 3D reconstructed volume obtained by APT analysis on 28 nm transistor gate. The 1D concentration profile is displayed in Fig. III.42d and Ni(Pt)Si is the only detected phase. Moreover, the Pt distribution inside the mono-silicide is the one measured on doped blanket wafers (§ III.2.3.2). On both substrates, poly-Si and mono-Si, when the Pt content in the Ni(Pt) layer reaches 10 at. %, the first phase to form is θ-Ni₂Si (please refer to section III.2.1.1). In this phase, the diffusion of Pt is faster than in the δ-Ni₂Si one and the Pt can easily diffuse to the interface with the substrate [157].

The As segregation at the silicide/Si interface is almost the same as the one observed on blanket Si(100) wafers whereas the As distribution inside the silicide is slightly different, due to As diffusion in the poly-Si grains boundaries.
<figure><img src="image_81.png" /><figcaption>Figure III.41. 3D reconstructed APT volume obtained in the gate of 28 nm NMOS device after RTA2 (a, b, c). Ni, Si, O, As, and Pt distributions are separated into the different figures. 1D concentration profile of Si, Ni, Pt, and As after RTA2 are calculated in a 25 nm diameter cylindrical region of (a) (d).</figcaption></figure>

For 28 nm node, in the case of Ni(10 at.% Pt), Ni(Pt)Si is the only phase that is formed after RTA2, independently of the substrate nature.

### III.4.1.3 Conclusions on CMOS devices analyses

Table III.7 summarizes the silicide phases, formed after RTA1 and RTA2, as a function of the Pt concentration of initial Ni(Pt) layer, the transistor regions, and sizes (from [195]).

<table><caption>Table III.7. Nature of the silicide phases formed after RTA1 and RTA2 as a function of Pt concentration, transistor regions and sizes.</caption><thead><tr><th>Transistor region and size</th><th>Pt at.%</th><th>Post RTA1</th><th>Post RTA2</th><th>References</th></tr></thead><tbody><tr><td>45 nm NMOS Gate</td><td>5</td><td>δ-Ni<sub>2</sub>Si (340 °C)</td><td>Ni(Pt)Si</td><td>§ III.4.1.1</td></tr><tr><td>45 nm NMOS Source/drain</td><td>5</td><td>δ-Ni<sub>2</sub>Si (340 °C)</td><td>δ-Ni<sub>2</sub>Si</td><td>§ III.4.1.1</td></tr><tr><td>Blanket wafers As doped Si(100)</td><td>5</td><td>?</td><td>?</td><td>Not yet performed</td></tr><tr><td>28 nm NMOS Gate</td><td>10</td><td>θ-Ni<sub>2</sub>Si (280 °C)</td><td>Ni(Pt)Si</td><td>§ III.4.1.2</td></tr><tr><td>28 nm NMOS Source/drain</td><td>10</td><td>θ-Ni<sub>2</sub>Si (280 °C)</td><td>Ni(Pt)Si</td><td>[195]</td></tr><tr><td>Blanket wafers As doped Si(100)</td><td>10</td><td>θ-Ni<sub>2</sub>Si (200-280 °C) or δ-Ni<sub>2</sub>Si (225-325 °C)</td><td>Ni(Pt)Si</td><td>§ III.2.3.2</td></tr></tbody></table>

For a Pt concentration of 5 at.%, after RTA1, δ-Ni₂Si is the only phase formed on the gate and source/drain, while, after RTA2, two different Ni-silicides have been formed: Ni(Pt)Si on the gate and δ-Ni₂Si on the source and drain. For a Pt concentration of 10 at.% the expected phases are observed
after each RTA process in devices. Indeed, θ-Ni₂Si is the first phase to form after RTA1 and Ni(Pt)Si is then formed at the same time on source and gate after RTA2. The absence of the formation of Ni(Pt)Si from δ-Ni₂Si/Si(100) interface compared to θ-Ni₂Si/Si(100) interface could be related to the difference of interface energies (please refer to [195] for details).

The advantages of the Ni(10 at.% Pt) alloy for the real salicide process is then identified through APT results. Pt addition enables modifying the phase sequence and lower the Ni(Pt)Si formation temperature. Inside the real device, such changes deal with a uniform and low resistive mono-silicide formation in nanoscale dimensions whatever the substrate nature.

### III.4.2 Change in phase sequence in nanoscale structures for Ni(Pt 10 at.%)-Si

The influence of device dimensions on the Ni(Pt)-silicides formation are investigated through poles figure comparison based on XRD characterizations performed with laboratory beam for blanket wafers, and with the ESRF synchrotron beam for the confined samples (described for Si substrates in Figure III.42). The experiments were performed at the energy of 11 KeV on each 2-mm-square die. The studied 2θ range from 15 to 70°. Then, in order to expand the range in the reciprocal space, the measurements were also performed at different positions of the sample tilts χ, allowing the capture of the whole range.

<figure><img src="image_82.png" /><figcaption>Figure III.42. Successive process steps used for the fabrication of nanoscale structures, including a TEM cross-section of final structure (a). Total area of each structure is 2 mm² to allow texture analysis with a 6-circle Kappa goniometer plugged on ESRF beamline as presented in (b). The analyzed structures (schematic) present the succession of dielectric and silicide lines with a width of 80 and 110 nm respectively (c).</figcaption></figure>

Finally, by combining all these measurements at different 2θ and χ, the pole figures are extracted. The calibration is done with a LaB6 powder to correct the detector distortions. Then, a 2D integration is performed on all the φ positions. At the end, a software developed by Tra Nguyen-Thanh [196](also used for SiGe substrates presented in the next section) is used to generate the following pole figures. To ensure a significant diffracting signal for the nanoscale structures, Ni(10 at.% Pt) film initial thickness is set at 40 nm for these experiments on patterned wafers as well as blanket ones. In this case only one RTA is applied with a temperature comprised between 280 and 320 °C. Two types
of samples have been carefully studied as the one annealed at 280 °C for 30 s - i.e., before NiSi transition - and at 320 °C for 120 s (the highest thermal treatment here). For experiment details and methodology of simulations with Carine Crystallography software, please refer to Mathilde Lemang's Ph. D dissertation [170].

The Figures III.43a and c describe the poles figures obtained from X-ray measurements after the reaction of a 40 nm Ni(10 at.% Pt) film with Si substrate during a RTA at 280 °C for 30 s. The experiment is performed after selective etching. In that case, diffraction patterns appear for the d-spacings equal to 1.92 Å and 1.98 Å (Fig. III.43 a and c respectively). These inter-planes distances are related to the most intense diffraction peaks of θ-Ni₂Si and δ-Ni₂Si phases (please refer to the Annex). Based on in-situ XRD results (as presented before in Figs. III. 1, 13 and 14), the first phase to grow for this system should be the θ-Ni₂Si phase in epitaxy with the substrate (§ III.2.1.1 and III.3.1.4). To confirm this point, the simulated stereographic projections for θ-Ni₂Si phase obtained through the Carine Crystallography software for the same d-spacing are provided in Figs. III.43b and d respectively.

<figure><img src="image_83.png" /><figcaption>Figure III.43. Pole figures obtained for d = 1.92 Å (a) and for d = 1.98 Å (c) after the reaction of a 40 nm Ni(10 at.% Pt) film with Si substrate during a RTA at 280 °C for 30 s. Simulated stereographic projection of θ-Ni₂Si phase (in pink) with 3 identified orientations (rotated of 90°) for each d-spacing (b and d respectively).</figcaption></figure>

In nanoscale structures, as described in Fig. III.44, the poles figures obtained from Synchrotron X-ray measurements are different from the one obtained for blanket wafers. For the same d-spacings, the simulated stereographic projections for θ-Ni₂Si phase could not explain all the diffraction patterns
(Fig. III.44b and d). Even though the intensity is lower than for blanket wafers due to the lower silicide volume, (221) NiSi and δ-Ni₂Si planes, as (121) and (301), are identified.

Firstly, the (221) NiSi orientation has been already observed by in-situ XRD during the reaction of 16 nm of Ni(10 at.% Pt) film and has never been detected for thinner Ni(Pt) film. Then, for a thicker Ni(Pt) film, this result is consistent with previous observations.

Secondly, when δ-Ni₂Si phase is detected, like in Fig. III.14 for P implanted Si substrates, the unique orientation for this phase is (121).

<figure><img src="image_84.png" /><figcaption>Figure III.44. Pole figures obtained for d = 1.92 Å (a) and for d = 1.98 Å (c) after the reaction of a 40 nm Ni(10 at.% Pt) film with Si substrate in nanoscale structures (Fig. III.42) during a RTA at 280 °C for 30 s. Simulated stereographic projection of θ-Ni₂Si phase (in pink), θ-Ni₂Si (in blue), and NiSi (in orange) with specific orientations for each d-spacing (b and d respectively).</figcaption></figure>

Finally, phases and textures differences are observed between the blanket and the nanoscale structure after a RTA1 at 280 °C for 30 s: θ-Ni₂Si appears to be the only phase in presence for blanket wafers while δ-Ni₂Si and NiSi are early detected in confined structures.

After an annealing at 320 °C, for blanket and nanoscale structures, NiSi and δ-Ni₂Si phases are the only detected phases with different textures indicating a potential influence on grains orientations of confinement or line orientation (results not shown here, please refer to M. Lemang Ph. D dissertation).

The main differences observed in the phase sequence between nanoscale structures and blanket wafers have been provided for an RTA at 280 °C during 30 s. This could be linked to a slight acceleration in the phase sequence due to the confinement; and this is completely aligned with what
we currently observe in nanoscale devices as NiSi₂ formation after standard salicide process, as an example. This "speeding up" in the kinetics of silicide formation is difficult to explain and is one of the most interesting questions - if it is confirmed - to bring out in the future as will be proposed in Chapter V.

### III.4.3 Change in phase sequence in nanoscale structures for Ni(Pt 15 at.%)-SiGe

As previously detailed, similar XRD characterizations obtained on the ESRF synchrotron beamline have been carried out on Si<sub>0.7</sub>Ge<sub>0.3</sub> substrates and the final structure in that case is described in Fig. III.45a.

<figure><img src="image_85.png" /></figure>

Figure III.45. Schematic of final analyzed structures in cross-section displaying the succession of dielectric and silicide lines similar width formed on 20 nm thick Si<sub>0.7</sub>Ge<sub>0.3</sub> epitaxial layer (a). Total area of each structure is 600 µm² to allow texture analysis with a 6-circle Kappa goniometer plugged on ESRF beamline and 6 different networks are present in each die. The dimensional pitch, defined as the sum of dielectric and silicide linewidth, is comprised between 64 and 1000 nm (b) (presented at MRS 2014).

Such structures deal with a 600 µm²-network of dielectric and silicide lines which present the same lateral dimensions. The pitch defined as the sum of a dielectric and a silicided-line width varies from 64 to 1000 nm, as shown in the schematics in Fig. III.45b. Thus, for each sample, 6 different structures related to 64, 90, 160, 300 and 1000 nm-pitch are analyzed. As a first step of analysis, the 1000 nm-pitch structure is estimated to be like blanket wafers and the 64 nm one to the 14 nm-FDSOI CMOS devices.

The experiments were performed at the energy of 8.2 KeV on each 600 µm-square networks. The studied 2θ-range is 30 to 60°. For those experiments the tilt angle χ is fixed at 0 and 50°, the 2D integration is performed on all the φ positions and similar software is used to generate the following pole figures. The Ni(15 at.% Pt) film thickness is 7 nm, as for blanket wafers, and all the measurements are acquired after a RTA1 at 280 °C for 30 s and a selective etching.

In Figure III.46, all the diffraction patterns, and the subsequent deduced pole figures, obtained for a d-spacing range of 1.5 to 3 Å are shown.

As expected, for the largest pitch (1000 nm), the first phase to grow and the unique one is the θ-Ni₂SiGe phase in epitaxy with the substrate, and the pole figure is the one observed on blanket wafers in the same experimental conditions (Figs. III.32 and 33 in subsection III.3.1.4). Then, the following epitaxial relationship is deduced based on simulated stereographic projection in Fig. III.47a as: (100) θ-Ni₂SiGe planes aligned on the (001) Si<sub>0.7</sub>Ge<sub>0.3</sub> planes and (120) and (001) θ-Ni₂SiGe planes aligned on (110) Si<sub>0.7</sub>Ge<sub>0.3</sub> planes.
<table><thead><tr><th>Pitch (nm)</th><th>1.90</th><th>1.92A</th><th>2.01A</th><th>2.12A</th><th>2.15</th><th>Phases</th></tr></thead><tbody><tr><td>1000</td><td>-</td><td>*</td><td>-</td><td>-</td><td>-</td><td>(100) Θ-Ni<sub>2</sub>Si only</td></tr><tr><td>160</td><td>-</td><td>*</td><td>*</td><td>*</td><td>-</td><td>(100) Θ and (210) δ-Ni<sub>2</sub>Si</td></tr><tr><td>90</td><td>*</td><td>*</td><td>*</td><td>*</td><td>*</td><td>(100) Θ and (210) δ-Ni<sub>2</sub>Si (210) NiSi</td></tr><tr><td>64</td><td>*</td><td>*</td><td>*</td><td>*</td><td>*</td><td>(100) Θ and (210) δ-Ni<sub>2</sub>Si (210) NiSi</td></tr></tbody></table>

* Details of phase identification based on simulated stereographic projections are given in Fig. III.47.

Figure III.46. Pole figures obtained and deduced phase identification based on simulated stereographic projections after the reaction of a 7 nm Ni(15 at.% Pt) film with SiGe sublayer in nanoscale structures (Fig. III.45). The inter planes distance d and the dimensional pitch ranges are respectively 1.90 to 2.15 Å, and 1000 to 64 nm.

<figure><img src="image_86.png" /></figure>

Figure III.47. Details of Fig. III.46. Phase identification based on simulated stereographic projections by Carine Crystallography software for different dimensional pitch as 1000 nm (a), 160 nm (b), and 90 nm (c) from [6].
By reducing the dimensions, for the 300 and 160-pitch networks, new diffractions patterns
appear for d = 2.01 Å and 2.12 Å and the δ-Ni₂SiGe phase presence is then established in these reduced
dimensions and in that case this phase is in epitaxy with the substrate as pole figures shown. Based on
Carine Crystallography software simulations, the (111) and (211) planes of δ-phase are identified and
two different orientations of (111) grains need to be considered to properly simulate the pole figure
obtained for 2.12 Å (Fig. III.47b). Finally, for 160 nm pitch, the δ-phase appearance and texture with
(210) orientation in epitaxy with the substrate is clearly a novelty, which has not been observed on
blanket wafers.

For the 90 nm and 64 nm pitch, new pole figures are integrated from diffraction patterns at 1.90 and 2.15 Å and the simulated stereographic projections show the emergence of NiSiGe phase in these networks in addition to θ and δ-Ni₂SiGe ones (Figs. III.46 and 47c). In that case the detected NiSiGe planes are (211), (210), and (201). The (211) planes are aligned on [110] substrate direction.

The emergence of NiSiGe phase after a RTA1 at 280 °C during 30 s is unexpected based on
blanket observations and clearly demonstrates the influence of the confinement for the Ni(Pt 15 at.%)-SiGe system. Moreover, the epitaxial relationships and the NiSiGe phase orientation have not been
detected during experiments on blanket wafers.

As shown in previous section for Ni(Pt 10 at.%)-Si system an acceleration in the kinetics of germano-silicide formation is confirmed for the Ni(Pt 15 at.%)-SiGe one in nanoscale dimensions (inferior to 100 nm).

The change in silicide and germano-silicide phase sequence in nanoscale dimensions is quite
difficult to explain; but might be linked to higher local stress, different surface preparation or lower
interface energies leading to a reduction in free Gibbs energy needed for NiSiGe nucleation.

From my point of view, I suppose also that the NiPt deposition by PVD is different in such
confined structures. Potentially the grain size of the initial NiPt deposition could play a major role and
we formerly expect a reduction of the NiPt grains size here. In that case does the Pt concentration is
the same at the intermixing/substrate interface? Furthermore, if the NiPt grain size drastically
changes, the grain size of Ni-rich phases could be also modified and the Pt concentration at the θ or δ-
Ni₂SiGe/ Si interfaces might be potentially higher. Could this phenomenon induce easier NiSi or NiSiGe
formations?

As introduced at the beginning of this section, the knowledge of the changes induced by the
nanoscale dimensions in phase sequence is key for silicide and germano-silicide integrations. Such
results have allowed to propose the large implementation of the partial reaction process which enables
the complete suppression of the NiSi₂ formation (from NiSi grains during the RTA2) in confined
dimensions.

Nevertheless, some remaining questions are still one of the most interests in silicide
integrations such as the influence of NiPt thickness and the confinement on the θ or δ-phases grain size
and the subsequent phase sequence as will be detailed in the research project in Chapter V.
### III.5 Agglomeration of Ni-silicides and germano-silicides thin films

As an introduction of this section and based on the review presented in the section II.3, addition of Pt as Ni-alloying allows to significantly delay NiSi agglomeration [41], [76], [147], [77], [78], [197], unsuitable NiSi₂ phase formation [41], [76], [147], and Ni abnormal diffusion through the channel, known as "NiSi piping or encroachment" [4], [32], [66].

The introduction of Ni(10 at.% Pt) alloy and the partial reaction process (details in Fig. II.10) have definitely implied a strong reduction of NiSi₂ nucleation and finally permitted to completely suppress the NiSi encroachment occurrence for our bulk and FDSOI technologies. Firstly, the recent results obtained on the positive impact of this new integration, with Ni(10 at.% Pt) alloy in addition to the partial reaction, on NiSi₂ formation will be presented soon in a dedicated paper. Secondly, as shown in Bruno Imbert's Ph. D dissertation [2] and in [4], NiSi encroachment is definitely related to the Ni(Pt) film thickness and the subsequent RTA1 temperature. Then, by increasing the Pt concentration inside the initial NiPt film and by reducing RTA1 temperature - as needed for partial reaction- act in the same way in the suppression of the Ni abnormal diffusion.

Nowadays, the most important, and as I can say, the most unpredictable phenomena occurring in devices we are faced with, remains the silicide and germano-silicide agglomeration. That is the reason why I propose a particular focus on this subject here.

Then, our experimental results on NiSi and NiSiGe agglomeration phenomena will be summarized and discussed in the next paragraphs.

#### III.5.1 Solid-state of dewetting in thin films

The phenomena of dewetting leading to the thin film agglomeration have been widely observed in crystalline materials [74], [182], [198]. The solid thin films are usually not stable on a substrate, and they will agglomerate or dewet into smaller islands at sufficiently high temperature (under the melting temperature). The driving force of agglomeration is the minimization of the total energy of the free surfaces and the film-substrate interface as illustrated in Figure III.48 and detailed in the review paper of C.V. Thompson [154]. For thin films, the large ratio between the surface and the volume induces a larger dewetting driving force than for bulk materials.

<figure><img src="image_87.png" /><figcaption>Figure III.48: The equilibrium shape of an island with an isotropic surface energy after the dewetting on a rigid (a), and non-rigid (b) substrates (reproduced from [199]).</figcaption></figure>
On a rigid substrate (Fig. III.48a), θ is the contact angle, γᵢ, γᵢ, and γₛ respectively represent the surface energy of the island, the island-substrate interface energy, and the surface energy of the substrate. The equilibrium shape of the island gives the following equation:

$$γ_S = γ_i + γ_f \cosθ \qquad \text{Eq. III.7}$$

If γₛ > γᵢ + γf the film is stable, and no agglomeration occurs. On the contrary, the film agglomerates into islands.

For the dewetting at the interface between two phases (Fig. III.48b), two contact angles θ₁ and θ₂ and three interface energies γ₁, γ₂, and γₛ are defined. The contact angles θ₁ and θ₂ deduced from the projection of the interfacial energies vectors is given by:

$$\cos(\theta_1) = \frac{\gamma_s^2 + \gamma_1^2 - \gamma_2^2}{2\gamma_s\gamma_1} \quad \text{and} \quad \cos(\theta_2) = \frac{\gamma_s^2 - \gamma_1^2 + \gamma_2^2}{2\gamma_s\gamma_2} \qquad \text{Eq. III.8}$$

If we consider the case of the studied system as a poly-crystalline thin film on a rigid substrate, the agglomeration phenomena could be divided in four main phases: groove of grain boundaries, hole formation, edge retraction and ligament break-up [199]. Srolovitz and Safran [200] and Nolan [201] proposed an agglomeration model based on an ideal 2D grain structures. To do so, the grain boundaries grooving is introduced as illustrated in the Fig. III.49 (reproduced from [10]):

<figure><img src="image_88.png" /><figcaption>Figure III.49: Schematics of poly-crystalline thin film agglomeration on a rigid substrate. In the initial state the film is continuous, then the grooving of the grain boundaries occurs and induces the curvature of the grain boundaries at film surface and film-substrate interface. Islands are formed through the edge retraction and ligament break-up ([200], [201]).</figcaption></figure>

For this system, if we consider a film with a thickness h and grain size D = 2R (Fig. III.50a), the surface and the grain-boundary energies could achieve an energy balance at the intersection of grain boundary and the film surface: this leads to a curved surface with a groove defined by an angle φ as:

$$2\gamma_f \sin \varphi = \gamma_{gb} \qquad \text{Eq. III.9}$$

The depth of the groove δ is:

$$\delta = R \frac{(2 - 3 \cos \varphi + \cos^3 \varphi)}{3 \sin^3 \varphi} \qquad \text{Eq. III.10}$$
<figure><img src="image_89.png" /><figcaption>Figure III.50: Schematic cross-sectional view of poly-crystalline thin film with in-plan grain diameter D and radius R on a rigid substrate in the equilibrium state presenting first grooves at grain boundary at the film surface (a) and for isotropic interface energies, at film-substrate interface (b) (reproduced from [199]).</figcaption></figure>

If the groove depth δ is equal to the original film thickness h, the groove will contact the substrate and a hole will be formed at this position, indicating the onset of dewetting. Therefore, the radius of the critical grain size R_c is given by the following equation:

$$R_c = \frac{(3 \sin^3 \varphi)}{(2 - 3 \cos \varphi + \cos^3 \varphi)} h \qquad \text{Eq. III.11}$$

The poly-crystalline thin film could be resistant to dewetting if the grain size is smaller than the critical value of 2R_c. The hole formation is likely to occur at high energy grain boundaries and in thin films presenting a small thickness.

In the case of two phases, as represented in Fig. III.50b, the groove angles θ_1 and θ_2 are associated to the isotropic interface energies γ_1 and γ_2. The critical grain size is then deduced as:

$$R_c = \frac{3[\sin(\theta_1 - \theta_2) + \sin\theta_1 - \sin\theta_2]}{2(\cos\theta_2 - \cos\theta_1)} h \qquad \text{Eq. III.12}$$

If we consider the top material as air, the upper interfacial energy γ_1 is the surface energy. Consequently, the grooving arises both at the film surface and at the film-substrate interface. The hole grows through the edge retraction as described in the schematics below:

<figure><img src="image_90.png" /><figcaption>Figure III.51: Schematic cross-sectional view of retracting edge of a film (a). Retraction proceeds by surface self-diffusion and mass accumulation at the edge of the film leads to the development of a rim and finally to the formation of a valley (b-d) (reproduced from [199]).</figcaption></figure>

The original shape of the hole is considered as a sharp corner (dash line in Fig. III.51a). As the material always diffuses away from the high curvature region until a constant curvature, a continuing flux from the hole corner to the hole rim, noted J, is established. With the edge retraction, the film material removed from the substrate accumulates into a thickening of the rim (Figs. III.51b and c). This flux drives the edge retraction and the hole growth. It is generally accepted that the dominant mass
transport in the solid film is the self-diffusion [199]. For surfaces with isotropic energies the flux can be described as [202]:

$$J = - \left( \frac{D_s \gamma_f N_s \Omega}{kT} \right) \nabla_s \kappa \qquad \text{Eq. III.13}$$

Here, Ds is the surface diffusivity, γf is the surface energy, Ns is the number of surface atoms per area, Ω is the atomic volume, k, T, and κ are respectively the Boltzmann's constant, the temperature, and the local surface curvature.

As the edge continues to react, the height of the hole rim increases, and a deep valley is formed near the rim (Fig. III.51d). When the film valley contacts the substrate, the film is broken and form a crystalline string parallel to the film edge. Afterwards, a new hole edge is formed, and starts to react. The dewetting process is then repeated.

Based on the different models, the worsening of the resistance of thin films to the agglomeration might be listed as grain boundaries structures and interface roughness [203], internal film stress [198], grain size [203], and texture (appearance or not of axiotaxy [204]).

### III.5.2 Early agglomeration for 28 nm FDSOI technology: grain size and silicide thickness

As explained in Chapter II, the introduction of 28 nm-FDSOI technology, and 14 nm as well, needs a strong reduction in the final Ni(Pt)Si thickness, targeted less than 12 nm. The subsequent process changes to ensure such silicide integration could be listed as (1) thin Ni(Pt)Si deposition, (2) significant reduction of RTA1 temperature to promote a real partial reaction in all nanoscale devices, and (3) the introduction of new type of RTA2 annealing process as DSA, named then DSA2.

On one hand, the DSA2 annealing, which is characterized by a direct laser interaction during a very short time with the top surface of silicide, causes a significant reduction in Ni(Pt)Si grain size and an increase in the number of grains that are epitaxially oriented, as demonstrated in [205]. Moreover, the laser anneal increases the Pt concentration at the silicide-Si interface. These observations confronted to what has been explained in the previous section on agglomeration phenomena might be considered having a major benefit in the silicide film resistance to agglomeration. Indeed, reducing the grain size, promoting a hetero epitaxy with the substrate, and inducing a Pt segregation at the interfaces, i.e., reducing the interfacial energy, might delay dewetting.

Nevertheless, as will be presented in this section, the agglomeration temperature threshold in the particular case of ultra-thin Ni(Pt)Si layers remains lower than expected.

Firstly, based on our studies on DSA impact on agglomeration [73], one of the most important parameters is the initial NiPt layer thickness. As displayed in Figure III.52, the significant increase in sheet resistance for thinner NiPt layers indicates a clear agglomeration of silicide film for “effective” DSA temperatures above 900 °C. This is confirmed by top-view SEM observations (insets in Fig. III.52). While a very low RTA1 temperature (230 °C) and a Ni(10 at.% Pt) alloy were used, strong agglomeration is observed due to the low NiSi silicide thickness, as reported in [154], and also potentially its roughness at silicide/substrate interface.
<figure><img src="image_91.png" /><figcaption>Figure III.52: Rs measurements of silicide formed from the reaction of 7 and 9 nm of Ni(10 at.% Pt) films with undoped Si(100) substrate after the complete salicide process, including DSA2 as second annealing at temperature between 800 and 1000 °C. A large Rs increase is detected for thinner NiPt layer at high temperatures due to film agglomeration as observed by SEM in the inset top-view images.</figcaption></figure>

In addition, this worsening in Ni(Pt)Si agglomeration resistance has been observed in real devices when Ni(Pt)Si layer is fully integrated in the complete process flow, i.e., including a large number of additional thermal budgets linked to the contacts and BEOL integrations. Recently, a study on 28 nm FDSOI devices demonstrates a clear degradation of the circuits yield associated to the agglomeration of Ni-silicide films [206], as presented in Fig. III.53.

Here, additional thermal budgets (ranging from 450 to 600 °C for 2 h) have been applied to a standard flow after the silicide formation. A slight silicided square resistance increase starts to be observed for thermal budget higher to 500 °C for a 100 nm²-actives mainly on P+ (Fig. III.53a).

<figure><img src="image_92.png" /><figcaption>Figure III.53: Square resistances measured in N and P silicided areas respectively for a width W of 2 and 0.1 µm as the function of additional thermal budgets applied on 28 nm FDSOI devices (a). Yield degradation respect to additional thermal budgets in SRAM (b) and in logic devices (c) due to Ni(Pt)Si film agglomeration [206].</figcaption></figure>

At the same time, one may note that the Rs measurements within the whole wafers start to show a significant dispersion from one die to the other, which is the clear signature of the onset of the agglomeration. The yield is also evaluated on large and dense SRAM circuits presenting more than
5 million bits and a total area of 0.120 µm². The yield stability is unaffected up to 500 °C (Fig. III.53b). Equivalent results are obtained in logic structures as shown in Fig. III.53c.

If we evaluate the results acquired on blanket wafers, presented in section III.2.3 and specially in Fig. III.12, the agglomeration threshold temperature is almost 250 °C less in real devices compared to the blanket experiments. Severe agglomeration causing the drastic drop-off of the yield is observed in devices at 550 °C compared to 800 °C for blanket. As introduced in the previous section, this could be linked to the in-plane stress increase in small dimensions or a change in microstructure (texture, grain size, lack of epitaxy, grain boundaries type) in confined structures.

As a conclusion of the recent work provided on agglomeration of ultra-thin Ni(Pt)Si we could highlight that this degradation mechanism remains the major drawback of silicide first integration and deep studies could be initiated around this subject in the future, as will be detailed in Chapter V.

At the end, the most promising approach is an adapted PAI process. As previously detailed in section III.2.4 significant shift in the agglomeration temperature of Ni(Pt)Si layers is observed by introducing PAI mainly by adding carbon. From my point of view, beyond the silicide roughness decrease, the silicide texture (linked to a potential texture inheritance) is the main point of attention and promoting an epitaxial Ni(Pt)Si layer is in the critical path for agglomeration reduction.

### III.5.3 Ni(Pt)SiGe thermal stability for Ni₁₋wPtw (0<w<0.15) alloys

The integration of Si₀.₇Ge₀.₃ epitaxial layers in source/drain areas in 14 nm FDSOI technology has induced the degradation of germano-silicide morphological stability. Two phenomena could be formerly observed as the Ge out-diffusion and germano-silicide film agglomeration from 400 °C, temperature used for the subsequent processes, namely in BEOL.

Morphological stability improvement has been achieved by using Ni₁₋wPtw alloys on Si and Si₁₋ₓGeₓ [77]. Several papers relate to the Ni/Si₁₋ₓGeₓ reactions [78], [183], [184] but fewer deal with Ni₁₋wPtw-Si₁₋ₓGeₓ system [77], [185]. The Ge out-diffusion from the germano-silicide is controlled by thermodynamics as explained by Jarmar et al., and leads to the formation of Ge enriched regions in the SiGe layer [207].

For Ni-based silicide, morphological stability improvement has been achieved by using Ni(Pt) alloys [76]. Pt delays the formation of the highly resistive NiSi₂ phase [76] and modifies the texture of NiSi which increases considerably the thermal stability [208].

In this section, a specific focus on the effects of Pt content (from 0 to 15 at.%) on the thermal stability of Ni-germano-silicide formed on Si₀.₇Ge₀.₃ epitaxial layers will be presented, analyzed and discussed, as detailed in Emilie Bourjot's Ph.D work and in the following reference [79].

#### III.5.3.1 Experimental results on blanket wafers

As previously described in section III.3, the samples studied here consist of Ni₁₋wPtw (0<w<0.15) films deposited on Si₀.₇Ge₀.₃ epitaxial layer were grown on 300 mm Si(100) wafers. After
RTA and selective etching, Rs, ex-situ XRD θ-2θ, SEM TEM-EDX, APT and XPS analyses enable to evaluate the physical and chemical characteristics of the germano-silicide.

<figure><img src="image_93.png" /><figcaption>Figure III.54. Rs evolution as the function of RTA temperature during the reaction of a 7 nm Ni₁-ₙPtw (0<w<0.15) films deposited on Si₀.₇Ge₀.₃ epitaxial layer. The annealing time is 30 s and measurements are performed after the selective etching (reproduced from [79]).</figcaption></figure>

Figure III.54 shows the Rs evolution as a function of RTA temperature (from 280 to 700 °C) for the different Ni(Pt) alloys. Whatever the Pt content, the curves present the same trend with three domains. At 280 °C, the high value of Rs indicates the presence of Ni-rich phases as previously detailed in Figure III.36. From 280 to 400 °C, Rs steeply decreases toward the Rs minimum value, related to the formation of the mono-germano-silicide. The mono-germano-silicide phase is confirmed by θ-2θ XRD analyses carried out after a RTA at 500 °C (not shown here, [79]). At 700 °C, the abrupt rise of Rs reveals a change in the germano-silicide layer. However, the XRD measurements for samples annealed at 700 °C exhibit the same diffraction patterns as the ones annealed at 500 °C, meaning that no phase change has occurred. This indicates the agglomeration of mono-germano-silicide layer, as confirmed by the top-view SEM observations, displayed in Fig. III.55.

<figure><img src="image_94.png" /><figcaption>Figure III.55. Top-view SEM analyses of Ni (a, d), Ni(10 at.% Pt) (b, e) and Ni(15 at.% Pt) (c, f) based germano-silicide surface after an annealing at 400 °C (a, b, c) and 700 °C (d, e, f) respectively. The anneal time is 30 s and observations are performed after selective etching.</figcaption></figure>
For the pure Ni sample, at 400 °C, dark spots surrounded by clear contrast are present and are assigned to small holes at the surface of the film (Fig. III.55a). By adding Pt, no holes are detected, and the surface of germano-silicide appears continuous and smooth. At 700 °C, all the films are inhomogeneous with large holes (dark regions surrounded by white contrast) as can be seen in Figs. III.55d to f. In addition, they are agglomerated in large grains as indicated by grey islands surrounded by darker grey regions.

These darker regions are supposed to be the “exposed SiGe substrate” after the complete removal of the germano-silicide layer. Precisely, on these top-view SEMs, three specific regions could be then identified at 700 °C as presented below: holes at the surface, mono-germano-silicide agglomerated grains and exposed SiGe regions.

<figure><img src="image_95.png" /><figcaption>Figure III.56. Detail of Fig. III.55d with higher contrast to allow the identification of the three specific regions: holes, NiSiGe agglomerated grains and SiGe substrate.</figcaption></figure>

These three regions are thus observed on TEM cross-sections as follows:

<figure><img src="image_96.png" /><figcaption>Figure III.57. TEM cross-sections of Ni (a,b) and Ni(10 at.% Pt) (c) based germano-silicide after an annealing at 700 °C for 30s and selective etching, allowing the identification of holes, NiSiGe agglomerated grains and SiGe exposed substrate after the mono-germano-silicide agglomeration.</figcaption></figure>

Indeed, the TEM cross-sections show an agglomerated film with large grains separated by the SiGe layer. The germano-silicide grains are large (about 100 nm) compared to the standard grain size observed after the standard silicide process as 25 nm, previously shown in Figure III.34. Moreover, the SiGe layer has also been severely degraded: holes in SiGe layer are observed by TEM similarly to the ones observed by SEM in top-view (Fig. III.56).

After an RTA at 700 °C, the redistribution of Pt and Ge is quite complex, as shown in Fig. III.58. In the NiSiGe grains, Pt is located close to the grain surface but also along the interface with the Si substrate. Contrary to the Pt, Ge is found in a layer beneath the Pt-enriched zone close to the surface
but is depleted close to the surface and close to the interface with the substrate. The Ge and Pt redistributions are thus linked because Ge seems to be present where Pt is not.

<figure><img src="image_97.png" /><figcaption>Figure III.58. EDX mappings of Ni, Ge, O, Pt and Si respectively in pink, green, blue, yellow and red obtained from previous TEM images after the reaction of a 7 nm Ni(15 at.% Pt) film with SiGe layer at 700 °C for 30 s.</figcaption></figure>

Following these observations, XPS spectra on Ni and Ni(15 at.% Pt) samples annealed at 280 °C, 500 °C, and 700 °C are added to investigate the chemical bonds between the elements, respectively for Si2p and Ge3d (Figure III.59).

In the case of pure Ni, only Ge elemental doublet and Ge oxides have been evidenced on Fig. III.59c. At 280 °C, the suboxide $Ge_2O_3$ is found in addition to $GeO_x$ and $GeO_2$ (fully oxidized state of Ge). The relative weight of pure Ge element increases with the temperature, while the number of oxides decreases.

<figure><img src="image_98.png" /><figcaption>Figure III.59. Si2p (a,b) and Ge3d (c,d) energy doublets measured by XPS for pure Ni (a,c) and Ni(15 at. % Pt) (b,d) deposited on $Si_{0.7}Ge_{0.3}$ and annealed at 280, 500 and 700 °C. The anneal time is 30 s and the measurements are performed after selective etching at an energy of 1.4 keV with a power of 4.5 W. The beam size is 20 µm and the detector angle is set at 85°. The energy is calibrated with the elemental peak of Si2p at 99.4 eV.</figcaption></figure>

For Ni(15 at.% Pt) samples after an 280 °C anneal, a new doublet appears at approximately minus 0.5 eV from the Ge3d peak (red arrow in Fig. III.59d). This latter could be related to the
formation of a Ge-metal bond. As reported in [209], during the solid-phase reaction of Ni with a SiGe layer and contrary to the Ni2p3/2 peak, Si2p and Ge3d peaks do not show any detectable chemical shifts due to the germano-silicide formation. Previous XPS studies have demonstrated a chemical shift of the Ge3d of approximately 0.5 eV linked to a Ge-Pt bonds [6].

Thus, we attribute this new doublet to Ge-Pt chemical bond (marked by the red arrow in this figure). One may note that at 500 °C and 700 °C, this doublet disappears to the benefit of the Ge-Ge bindings. By comparison, at 700 °C, the Ge doublet presents the same shape for both samples as Ni and Ni(15 at.% Pt) films respectively. The presence of Ge-Pt binding appears to prevent the GeOₓ oxides formation due to the undetected peak at 35 eV in Figure III.59d, regardless of the RTA temperature. At the end, the presence of platinum leads to Pt-Ge bonds formation and could delay the NiSiGe degradation compared to pure Ni. However, at high temperatures, no more Pt-Ge bonds could be fitted.

For a better understanding of the morphology of Ni-germano-silicide degraded films, APT analyses have been performed on pure Ni samples annealed at 400 °C (Figs. III.60a to c), and at 600 °C (Figs. III.60d to h). The APT analyses have been achieved in the LEAP 3000x HR instrument at IM2NP.

<figure><img src="image_99.png" /><figcaption>Figure III.60. APT analyses of a 7 nm Ni film deposited on Si<sub>0.7</sub>Ge<sub>0.3</sub> annealed at 400 °C (a to c), and at 600 °C for 30 s (d to h). Ni, Ge, Si, and O atoms are colored in green, red, grey and blue respectively in the 3D reconstructions (a, d and f). Ge concentration mapping in the tip (a) related to the color scale on the left (b). Ni, Si and Ge atomic concentration profiles along the indicated dotted lines (c, e, f and h).</figcaption></figure>

At 400 °C, the 3D tip reconstruction (Fig. III.60a) reveals the grain boundary grooving of the NiSiGe grains at NiSiGe/SiGe interface. The Ge 2D mapping of this volume (Fig. III.60b) shows the presence of a Ge enrichment up to 80 at.% at the groove position, and a Ge depletion into the NiSiGe
grain. Therefore, APT reveals a clear morphological degradation and chemical redistribution at the NiSiGe/SiGe interface meaning that both grain boundary grooving (which is the first step of agglomeration), and Ge out diffusion at the grain boundary occur at 400 °C for this system. Ge rich grains could then be formed at the sample surface and could have been properly removed by selective etching as reported by Carron at al. [210]. The principle of selective etching solutions is to remove the metal by oxidation and dissolution of metal oxides until the complete surface passivation with a SiOₓ layer. The etching is thus fast for metal but slow for Si and silicide. Unfortunately, the Ge oxide (GeOₓ) is soluble in H₂O and cannot act as a passivation layer. As presented in XPS spectra, GeOₓ compounds are clearly detected at 280 °C for Ni pure sample. Then, the unprotected Ge rich grains, which do not present the standard composition of germano-silicide layer at 400 °C, are consumed faster. Ge grains are removed and cannot be detected in our samples. Therefore, the holes observed by SEM and TEM techniques in Figs. III.55 and 57 are attributed to the trace of Ge rich grains, formed by Ge out-diffusion, and removed during the selective etching.

At 600 °C, the APT reconstructions present two very heterogeneous volumes. For each volume, Ni germano-silicide grains have grown towards the Si substrate to more than 40 nm depth. As this is much more than the expected 15 nm thickness, an advanced stage of agglomeration is then observed at 600 °C. Furthermore, the composition of the grains is heterogeneous. In particular, the NiSiGe grain, in Fig. III.60g, exhibits a partial core/shell structure with a core that is located close to the surface. This core contains Ge atoms (colored in red), and the extracted compositions from the 1D profile give a NiSi₀.₈Ge₀.₂ ternary compound (Fig. III.60h). One may note that this composition is like the one detected at 400 °C (Fig. III.60c). A slight depletion of Ge concentration in NiSiGe grains compared to the original Ge composition of the Si₀.₇Ge₀.₃ layer seems to be highlighted here. However, the shell is composed of almost pure NiSi (and thus colored in green) as identified in the 1D profile in Fig. III.60h. In Fig. III.60g, the core extends over 20 nm in depth which corresponds to the initial thickness of Si₀.₇Ge₀.₃ layer. The shell is about the same thickness. The composition profiles performed across the NiSi/Si interface (noted f in Fig. III.60d and h in Fig. III.60g) reveal the presence of Ge along this interface.

To sum-up, the increase in Rs (Fig. III.54) observed at relatively low temperatures (below 600 °C compared to the Si based systems, Fig. III.12) for the Ni-germano-silicides is due to the degradation of the film through agglomeration and Ge out-diffusion as previously reported in [53].

Nevertheless, the Rs increase is significantly restricted by adding Pt if the Pt concentration is larger or equals to 10 at.%. No agglomeration is observed on SEM top views for Ni(10 at.% Pt) and Ni(15 at.% Pt) samples at 400 °C contrary to the Ni pure one. The delay in film degradation could be attributed to the formation of Pt-Ge bonds detected by XPS at 280 °C for the Ni(15 at.% Pt) samples. Moreover, APT and TEM-EDX analyses reveal a complex morphology of NiSiGe agglomerated films.

### III.5.3.2 Ge partition and NiSiGe agglomeration

Based on experimental results shown in the previous section, the degradation temporal sequence of Ge partition and NiSiGe agglomeration is proposed in Fig. III.61. Firstly, at low
temperature, NiSiGe grows with a similar proportion of Ge than in the Si<sub>0.7</sub>Ge<sub>0.3</sub> layer as the formation of Ni-germano-silicide is controlled by the diffusion of Ni (Fig. III.61a).

At higher temperatures, the migration of Ge becomes possible, and the **degradation of germano-silicide layer starts with the out diffusion of Ge**. Ge atoms are accumulated at the groove of a grain boundary and form an island as presented in Fig. III.61b. At the same time, Ni diffuses to allow the formation of the Si<sub>0.2</sub>Ge<sub>0.8</sub> island and the concomitant grooving of the NiSiGe grain boundary. The island will continue growing until it reaches the surface and then the agglomeration will start (Fig. III.61c). In some areas, the NiSiGe grains will have reached a depth where there is no more Si<sub>0.7</sub>Ge<sub>0.3</sub> layer and will continue to grow in the Si substrate (also Fig. III.61c). Several results can be underlined: (1) the Si<sub>0.7</sub>Ge<sub>0.3</sub> layer is first consumed and reappears with almost the same thickness and the same composition when the degradation is advanced, (2) the NiSiGe grain has a core/shell structure with a core concentration like the initial concentration of Ge in Si<sub>0.7</sub>Ge<sub>0.3</sub> and almost pure NiSi shell.

<figure><img src="image_100.png" /><figcaption>Figure III.61. Proposed degradation temporal sequence for the Ni-germano-silicide based on experimental results detailed in previous section (reproduced from [6]).</figcaption></figure>

Interesting insights can be established by analyzing the pseudo-ternary phase diagram of Ni-Si-Ge reproduced from [183] in Figure III.62.

<figure><img src="image_101.png" /><figcaption>Figure III.62. Pseudo-ternary diagram of Ni-Si-Ge calculated in [183] at 600 °C. Black lines represent tie lines. The tie lines colored in green allow to identify the NiSi formation and the Ge partition at the NiSiGe/SiGe interface.</figcaption></figure>

In the case of germano-silicide, Ge partition and agglomeration appear simultaneously. As pointed out by Yao et al. [211], the degradation of NiSiGe is different from the agglomeration of the pure NiSi or NiGe. In the Ni pure system, only interfacial energies are involved while both interfacial
and volume energies are acting for NiSiGe layers. As the degradation of NiSiGe occurs at lower temperatures than NiSi and NiGe ones, the partition could activate the agglomeration.

A deeper understanding of this phenomena is achieved by additional simulations. All the details in model assumptions and analytical results of these simulations are presented in [79]. From these models, a rough estimation of the inter-diffusion coefficient of Ge in Ni(Si₀.₇Ge₀.₃) films can be obtained, such as 1.10⁻¹⁹ and 1.10⁻¹⁵ cm²·s⁻¹ at 500 and 700 °C respectively. Towards the modeling of the core/shell composition of Ni-germano-silicide at high temperatures, finite element simulations of the Ge diffusion and partition were performed. In that case, it was assumed that the agglomeration is controlled by the fast diffusion of Ni and that the new NiSiGe layer formed at the bottom of the original Ni(Si₀.₇Ge₀.₃) grain does not contain Ge. Under this assumption, the growth of the Si₁-xGeₓ layer is controlled by the diffusion of Ge from the initial NiSiGe. The problem could be reduced to a one-dimensional problem.

From the initial Ni(Si₀.₇Ge₀.₃) and Si₀.₁Ge₀.₉ compositions at the interface, pure NiSi and Si₀.₇Ge₀.₃ layers are obtained during NiSiGe agglomeration. There is thus a NiSi shell around the Ni(Si₀.₇Ge₀.₃) core, but a gradient is present in the simulations.

However, Ge concentrations profiles obtained through this model reproduce the experimental results, further investigations on 2D or even 3D simulations may be needed to fully reproduce the experimental data.

### III.5.3.3 Effect of Pt on thermal stabilization of NiPt-germano-silicide

Our experiment results show that the addition of Pt allows to delay the degradation of the germano-silicide (Figs. III.54 and 55). As explained before, the degradation is strongly linked to the out-diffusion and the partition of Ge. A potential explanation might be that Pt can have a thermodynamics effect and change the partition of Ge.

To understand the effect of Pt on thermodynamic equilibrium between NiPt and SiGe the equilibrium tie lines in the quaternary system were calculated (Annexe 2 in Bourjot et al. [79]).

Following Hillert [212], the $\Delta^\circ G_{NiGe+PtSi}$, which is the Gibbs free energy of the reaction (Eq. III.14) could be expressed as the function of the Gibbs free energies of different compounds, as follows:

$$NiGe + PtSi \rightarrow PtGe + NiSi \qquad \text{Eq. III.14}$$

$$\Delta^\circ G_{NiGe+PtSi} = ^\circ G_{NiSi} + ^\circ G_{PtSi} - ^\circ G_{NiGe} - ^\circ G_{PtGe} \qquad \text{Eq. III.15}$$

The formation energies for the compounds are the following: $^\circ G_{NiSi} = -45$ kJ, $^\circ G_{NiGe} = -32$ kJ, $^\circ G_{PtSi} = -59$ kJ and $^\circ G_{PtGe} = -46$ kJ [6]. For these values, the term $\Delta^\circ G_{NiGe+PtSi}$ is null and thus there should be no or a slight variation of the tie line. **Therefore, the improvement in terms of degradation with the addition of Pt is not linked to a thermodynamics effect.**

Another hypothesis could be the role in the Ni(Pt)SiGe texture of Pt addition as presented in subsection III.3.1.5. By increasing the Pt concentration, Ni(15 at.% Pt)-Si₀.₇Ge₀.₃ system after RTA2,
through ACOM-TEM analyses, the mono-germano-silicide presents an hetero-epitaxial texture. Then, the promotion of epitaxial texture in the final mono-germano-silicide might limit agglomeration phenomena by a real reduction of the axiotaxy texture at the interface [87].

Finally, the main consideration is that the presence of Pt may also hinder the diffusion of Ge at the NiSiGe/SiGe interface and at the grain boundaries. As shown in the TEM images (Fig. III.58), Pt is mainly located at the NiSiGe/SiGe interface where it can delay the out diffusion of Ge. XPS measurements (Fig. III.59) have also revealed the presence of Pt-Ge bonds when 15 at.% Pt is added with a reduction of the Pt-Ge bindings at high temperatures.

Then, if we consider the binding energies as Ni-Ge (-32 kJ/mol), Ni-Si (-45 kJ/mol), Pt-Ge (-46 kJ/mol) and Pt-Si (-59 kJ/mol) (from [185]), Pt creates strong bindings with Ge which could delay Ge out-diffusion. Indeed, Pt-Ge bindings are created at low temperatures which are stronger than Ni-Ge ones. When temperature increases, the Ni-Ge bindings are the first to break. Without Pt, Ge is free to out-diffuse toward Ge rich grains. When Pt is added, Pt-Ge bindings are still present to hold back Ge and delay Ge out-diffusion. Thus, Ge out-diffusion, and subsequent agglomeration, occurs at higher temperatures.

### III.6 Conclusions of Chapter III

The experimental results and discussions presented in this chapter dedicated to the Ni and Ni(Pt) silicide and germano-silicides formation could be reviewed as follows.

**For the Ni₁-wPtw (0<w<0.15)-Si system,** a drastic change in silicide phase sequence induced by the alloying of 10 at.% of Pt has been observed. For this system, the first phase to grow is the metastable, hexagonal, and non-stochiometric θ-Ni₂Si phase. The main important characteristic of this phase is its texture, reported as an epitaxial one with the Si(100) substrate. Moreover, an increase in the activation energies as a function of Pt concentration has been highlighted and could indicate a large Pt incorporation inside the θ-Ni₂Si phase.

The influence of N⁺ dopants on Ni(Pt)Si formation is significant like arsenic and phosphorus; and the temperature shift in mono-silicide formation is respectively of 30 °C and 50 °C. This is key information in the field of silicide first integration. For doped samples, δ-Ni₂Si phase might grow simultaneously to NiSi or θ-Ni₂Si phases depending on the dopant species, the NiPt thickness and the presence or not of TiN capping.

Regarding the PAI introduction, a decrease of the Ni(Pt)Si roughness has been observed with Ge PAI and a significant improvement is also brought out by adding Carbon. This result might explain the strong delay in agglomeration appearance with Ge PAI+C and Si PAI+C processes.

**For the Ni₁-wPtw (0<w<0.15)-SiGe system,** the main result is the identification of epitaxial relationships, between Si₀.₇Ge₀.₃ substrate and θ-Ni₂SiGe, after RTA1, and also with Ni(Pt)SiGe phase after RTA2, for the specific Pt concentration of 15 at.%. Such hetero-epitaxial texture observed after RTA2 could be related to (i) the texture inheritance of θ-Ni₂SiGe phase or (ii) a change in lattice
parameter inside the final Ni₁₋wPtwSi₁₋Geₓ compound due to an increase of Pt incorporation, and a potential change in Ge concentration also.

Inside real devices, APT results highlight the benefit of Ni(10 at.% Pt) alloy integration on 28 nm node technology. This new integration allows the formation of a uniform and low resistive mono-silicide formation in nanoscale dimensions whatever the substrate nature. In nanoscale structures, for Ni(Pt 10 at.%)-Si and Ni(Pt 15 at.%)-SiGe systems, an acceleration in the kinetics of silicide formation is observed (for dimensions inferior to 100 nm).

Agglomeration of silicide and germano-silicides films at high temperatures remains a major problem for advanced microelectronic devices, and mainly for 28 nm nodes and beyond. Even though Pt addition limits the agglomeration phenomena on Si and SiGe substrates as presented here; the emergence of ultra-thin silicide films together with the nanoscale dimensions presents a great challenge in terms of silicide thermal stability for next years.

The studies presented all along this chapter aim to provide a deep knowledge on the physical mechanisms governing the Ni-silicide and germano-silicide formations on blanket wafers and in nanoscale structures. This deep understanding in phase sequence, minor species redistribution and segregation, texture inheritance, and reaction kinetics allows a clear breakthrough in terms of salicide first integration for advanced microelectronics technologies.

As my last words, the Pt alloying with an atomic concentration of 10 at.% at least in addition of a partial reaction process, perfectly designed in regard to phase sequence, could be estimated as the top-drawer integration for almost all planar technologies beyond the 90 nm nodes. Of course, interesting improvements could be found in the future by exploring innovative PAI processes.

The two remaining open questions I have in mind are the clear understanding of the nanoscale effect on Ni-silicide phase sequence - and the potential change of the downscaling of dimensions on θ-Ni₂Si grains size – and agglomeration phenomena. These two points will be detailed in my research project in Chapter V.
# CHAPTER IV

## New CoSi₂ integrations and innovative contacts as Ti-silicide, MIS, and III/V

### Abstract

In the first part of this chapter, recent results on new Co integrations including with new surface preparation, such as SiCoNi pre-clean, are presented. The objective is to provide a less resistive Co silicide layer for new imagers technologies, inside the logic area. In the zone surrounding the pixel, new TiSiₓ contacts integration has been introduced, and a significant work (still ongoing) has been launched to reduce the C54-TiSi₂ formation temperature by adding an Ultra-Violet Nanoseconds Laser Annealing (UV-NLA). As introduced in Chapter I, new 3D integrations request the co-integration on the same wafer of a very thin Ni(Pt)-silicide layer in logic part, which is very sensitive to high thermal budgets, and a TiSi₂ formation inside the contacts in pixels, usually achieved at 800 °C.

In the second part of this chapter, our research on innovative contacts will be summarized for 10 nm planar technologies, based on Metal Isolator Semiconductor (MIS) integration, and for advanced photonics devices, including a hybrid laser on Si, formed by III/V layers stacking.
Table of Contents

<table><tr><td>IV.1</td><td>Introduction</td><td>122</td></tr><tr><td>IV.2</td><td>Surface preparation influence on CoSi₂ layer properties and stability</td><td>122</td></tr><tr><td>IV.3</td><td>TiSiₓ silicide last integration for imagers technologies</td><td>127</td></tr><tr><td>IV.3.1</td><td>Additional SiCoNi pre-clean for contacts optimization</td><td>127</td></tr><tr><td>IV.3.2</td><td>C₅₄-TiSi₂ formation in contacts: preliminary studies on UV-NLA treatment</td><td>130</td></tr><tr><td>IV.3.2.1</td><td>Significant impact of laser annealing on C₄₉-C₅₄ transition on Si(100) substrates</td><td>131</td></tr><tr><td>IV.3.2.2</td><td>Influence of dopants and substrate type on C₄₉-C₅₄ transition</td><td>135</td></tr><tr><td>IV.3.2.3</td><td>First trials on patterned wafers and perspectives</td><td>137</td></tr><tr><td>IV.4</td><td>MIS contacts experimental results</td><td>137</td></tr><tr><td>IV.5</td><td>Ni and Ti-based intermetallic contacts on III/V</td><td>144</td></tr><tr><td>IV.5.1</td><td>Transfer Length Method (TLM) measurements: contact resistivity extraction</td><td>144</td></tr><tr><td>IV.5.2</td><td>TLM limitations: electrical vs morphological behavior</td><td>147</td></tr><tr><td>IV.5.3</td><td>Polyphasic system: example of Ni-In₀.₅₇Ga₀.₄₃As</td><td>150</td></tr><tr><td>IV.5.4</td><td>Proposed integrations and conclusions on III-V systems</td><td>151</td></tr><tr><td>IV.6</td><td>Conclusions of Chapter IV</td><td>152</td></tr></table>
IV.1 Introduction

The aim of this chapter is to give some relevant insights on new emergent problematics in terms of Co
salicide first integration and innovative contacts introduction in advanced CMOS, imagers, and photonics
technologies.

On top of that, as shortly introduced in subsection II.1.4, in Figs. II.6 and 7 as well, during the recent
evolution of CMOS imager 3D Stacked Back-Side Illuminated (3D-BSI) technologies have emerged. The
subsequent constraints on salicide integrations can be evaluated as follows.

Firstly, the introduction of these new technologies reveals severe Ar-preclean process limitations linked to a drastic change in the top surface composition of the incoming wafer. Thus, SiCoNi pre-clean has been introduced prior to Co deposition. A comprehensive study of surface preparations impact on CoSi₂ properties in terms of silicide resistivity, morphology, microstructure, O content, and roughness will be presented in details in the section IV.2 (reported in [92]). Recent results on the major change in CoSi₂ grains size and, therefore, the worsening of film resistance to agglomeration will be also discussed.

Secondly, as explained in section II.4.1, one of the main concerns in novel 3D-BSI technologies is the formation of a low resistive Ti-silicide layer inside the contacts in the pixel area. As detailed in Fig. II.27, the first step to provide the correct TiSiₓ growth is a proper surface preparation before Ti deposition. In these nano-scale features (presenting a Si contact surface of 70 nm²), the complete removal of minor species coming from contact patterning is quite challenging and our specific studies on this subject will be then summarized in this chapter, in the subsection IV.3.1.

Thirdly, for the next 3D imager technologies, known as 3D-sequential technology (see for instance Fig. II.7), the co-integration of an advanced CMOS layer with imager sensor requires to find a new path to reduce the temperature of the C49-TiSi₂ to C54-TiSi₂ transition. Particularly, nanosecond laser annealing (UV-NLA) has been found to enable the formation of C40-TiSi₂ phase, by-passing the undesirable C49-TiSi₂ one. The C40-TiSi₂ phase can thus act as a precursor of C54-TiSi₂ at lower temperatures [62], [63], [123]. Then, the impact of the UV-NLA energy density on the formation of the C54-TiSi₂, which has been deeply investigated during Laura Esposito's Ph.D thesis, will be presented in subsection IV.3.2.

Finally, the need in terms of innovative contacts for aggressive CMOS node as 10 nm and new
photonics devices has been the stakeholder of studies on MIS (Metal Isolator Semiconductor) contacts on
one hand, and on intermetallic layer formation based on Ni, Ni-alloys and Ti layers on III/V epitaxial layers
on the other hand. The principal results obtained during the Ph.D works of J. Borrel and F. Boyer
respectively will be discussed in sections IV.4 and IV.5.

IV.2 Surface preparation influence on CoSi₂ layer properties and stability

In CMOS technologies, a small area of each die is protected during the silicide formation by a SiO₂/Si₃N₄ stack deposited just before silicide surface preparation processes. The current naming of this stack and the referent areas are “Si-protected”, meaning that no silicide is formed in these zones. The aim of such transistors or resistors is to offer precise high resistances which will be used by the chip software for current regulation or clock time adjustment. For imagers, as described in Fig. IV.1, the presence or not of a SiO₂/Si₃N₄ stack on the top Si surface just before Co-silicide formation will vary with the density of CMOS transistors versus the pixel print. In the pixel area, the electrical contact to the photodiode is only performed though TiSiₓ contacts and all pixels are then “Si-protected”. One may notice that for 3D-BSI
imagers technologies, all the CMOS devices have been plugged on the bonded wafer and then the "Si-protected" area is extremely high compared to FSI ones (more than 80 %, Fig. IV.1c).

<figure><img src="image_102.png" /><figcaption>Figure IV.1. Schematics of the percentage of “Si-protected” areas for different technologies as CMOS (comprised between 0 and 10 %) (a), 2D-Front Side Illumination (FSI) imagers (30 to 50 %) (b), and new 3D-Back Side Illumination (3D-BSI) imagers (larger than 80 %) (c). To prevent silicide formation in “Si-protected” area, a SiO₂/Si₃N₄ stack is deposited and patterned on the wafer top surface prior silicide formation.</figcaption></figure>

The standard surface preparation scheme for Co silicides is an HF wet clean followed by Ar-plasma bombardment to dry etching native SiO₂ layer and potential polymeric carbon residues [99].

Therefore, during the Ar-plasma process, the top surface of the “Si-protection” stack is also etched, in this case the Si₃N₄ layer. On CMOS devices presenting a low Si-protected surface, the Ar plasma is mainly formed by Ar⁺ ions and O (ionic or not) atoms resulting in the etching of SiO₂ film. A very low part of the ions and atoms forming the Ar-plasma is based on Nitrogen compounds (Fig. IV.1a). Hence, for new 3D-BSI technologies, during Ar bombardment, the atoms removed from the surface are mainly Si and N coming from the etching of Si₃N₄ layer (Figs. IV.1b and c). This change induces instabilities inside the Ar plasma introducing a lack of etching efficiency.

During the Ar pre-clean, the pumping of nitrogen species becomes less effective after each processed wafer and the CoSi₂ formation is more difficult when the wafer number increases, as shown in Fig. IV.2.

<figure><img src="image_103.png" /><figcaption>Figure IV.2. Average CoSi₂ thickness after RTA2 (17 points) and 1σ standard deviation measured by ellipsometry on patterned 3D-BSI imagers wafers in the case of a Ar-pre-clean surface preparation for six processed wafers.</figcaption></figure>

Here, the CoSi₂ thickness after RTA2 decreases when the number of wafers processed in Ar-pre clean chamber increases; and simultaneously, the within-wafer non-uniformity drastically rises what is usually correlated to a polycrystalline layer formation. Thus, CoSi and CoSi₂ phases are present after RTA2 as a consequence of a delay in CoSi₂ formation [30]. Another point might be highlighted. The CoSi₂ thickness measured on wafer 3 to 6 is closer to expected CoSi thickness than CoSi₂ one [30]. Therefore, Ar-plasma pre-clean demonstrates clear limitations in the specific integration of 3D-BSI imager technologies to provide an optimized surface preparation before Co deposition.
Based on literature, two main in-situ surface preparation processes (i.e. without vacuum break) could be used before Co deposition: Ar-plasma bombardment process, and NF₃/NH₃ based chemical etch, called SiCoNi, included in Applied Materials platforms (used for Ni-based silicide [93], detailed in section IV.3.1).

Even though the SiCoNi pre-clean introduction has enabled to suppress this issue, the influence of such remote plasma cleaning on CoSi₂ layer properties needs to be deeply investigated.

The samples analyzed for this study have been processed as follows: on blanket Si(100) wafers, two types of in-situ pre-clean are applied before Co and TiN capping depositions as the standard Ar-plasma sputter etch (noted Ar SE in the following) and SiCoNi one. Co and TiN layers thicknesses are respectively 72 and 100 Å. After deposition, RTA1 anneals at temperatures of 470, 500, and 530 °C for 30 s followed by a selective etching (through NH₄OH/H₂O₂/H₂O and HCl/H₂O₂/H₂O chemical mixtures) are performed. RTA2 is set at 790 °C for 20 s. To verify the impact of surface preparation on CoSi₂ film agglomeration, similar samples are made and then subjected to high thermal budgets (high-RTA) at temperatures comprised between 700 and 900 °C for 2 minutes. Such measurements are performed after SiN layer encapsulation.

After RTA1, the sheet resistance of Co silicide layers and the calculated 1σ standard deviation are obtained through the four-probe point technique as presented in Fig. IV.3. The introduction of SiCoNi pre-clean allows to drastically reduce the Rs value in this temperature range. The shift is equal to 5.8 %. Moreover, the Rs value is quite stable after RTA1 anneals: no complete phase transformation is then expected and, based on literature, the phase in presence is the mono-silicide one, CoSi [30]. However, the standard deviation is quite higher for SiCoNi pre-clean and increases with the RTA1 temperature for both pre-cleans. This effect could be related to a change in silicide roughness, microstructure or new phase nucleation [30].

<figure><img src="image_104.png" /><figcaption>Figure IV.3. Sheet resistance (Rs) (on the left Y-axis) and calculated 1σ standard deviation (on the right one) measured after the reaction of a 7 nm Co thin film with Si substrate for different RTA1 temperatures (470, 500, and 530 °C). Two types of surface preparation are applied prior Co deposition: Ar-plasma dry etching (noted Ar SE) and SiCoNi pre-clean (described in detail in the next section).</figcaption></figure>

To identify the origin of the Rs reduction measured with SiCoNi pre-clean, STEM-EDX characterizations have been performed, as shown in Figs. IV.4a and b for Ar SE, and in Figs. IV.4c and d for SiCoNi respectively. By comparing the STEM images, one may note that the Co silicide thickness is similar, the roughness at CoSi/Si interface is more pronounced with SiCoNi pre-clean, and a very thin darker layer is observed with Ar SE pre-clean, exactly in the middle of CoSi layer.
<figure><img src="image_105.png" /></figure>

Figure IV.4. STEM cross-section images and oxygen EDX mappings of CoSi layers formed after a RTA1 at 500 °C for 30 s on Si substrates. Ar SE (a, b) and SiCoNi pre-cleans (c, d) are respectively applied prior Co deposition. With Ar SE (b), an O peak is detected in the middle of CoSi layer which is not observed with SiCoNi (d).

This layer/interface is characterized by EDX mappings, and an oxygen rich layer is observed in Fig. IV.4.b (in addition to the top silicide surface oxidation). ToF-SIMS measurements confirm the presence of this layer as illustrated in Fig. IV.5a. The observed oxygen rich layer is clearly identified after RTA2 for Ar SE samples as presented in Fig. IV.5b on EDX profiles. We estimated that the oxygen rich layer is linked to an insufficient surface preparation with Ar SE pre-clean and is the reminiscence of the initial Si surface before Co deposition. By assuming a diffusion-controlled growth of CoSi phase during RTA1 thermal budget, the CoSi depth should be 8 nm (based on extrapolations from [213]). This is consistent with the O peak position inside CoSi and CoSi₂ layers respectively after RTA1 and RTA2.

<figure><img src="image_106.png" /></figure>

Figure IV.5. 16O- profiles obtained by ToF-SIMS inside CoSi layers formed after a RTA1 at 500 °C, which confirms the presence of an oxygen rich layer with Ar SE pre-clean (a). Si, N, O, and Co profiles deduced from EDX mappings and obtained perpendicularly to the sample surface in CoSi₂ layers after RTA2 for both studied pre-cleans (b). Two oxygen peaks are observed with Ar SE while only one peak is detected with SiCoNi, as highlighted in the inset (b).

In addition, the thicknesses of CoSi and CoSi₂ layers after respective RTAs have been analyzed through different techniques (ellipsometry, TOF-SIMS and TEM, not shown here and reported in [92]). Thanks to these results, a thinner CoSi layer after RTA1 and a subsequent thinner CoSi₂ film after RTA2 is observed for SiCoNi pre-clean. Although the thickness variations are close to the measurement accuracy, the slight slow-down in phase sequence observed with SiCoNi pre-clean could be related to the fluorine contamination of Si surface, which is measured, in our case, by XPS at a level of 3 at.% (see also for instance [93]). Nevertheless, no evidence of remaining F presence is revealed by ToF-SIMS nor EDX measurements.
The intrinsic resistivities of the silicides formed after RTA1 are then extracted. They are respectively comprised between 128.6 and 132.2 µΩ.cm for Ar SE samples, and between 108.5 and 111.5 µΩ.cm for SiCoNi ones. Based on reported resistivities for Co₂Si and CoSi silicides in [30], the phase formed after RTA1 is confirmed to be the mono-silicide one, CoSi, in both cases.

Therefore, SiCoNi pre-clean allows a reduction of the Co silicide resistivity by 14% after RTA1, which might be related to the suppression of the observed oxygen rich layer for Ar pre-clean surface preparation.

As presented in Fig. IV.6, ASTAR™ mappings demonstrate the obvious dependence of CoSi₂ microstructure to surface preparation techniques. For Ar SE pre-clean, the Co silicide microstructure presents a clear epitaxy with the Si(100) substrate (as previously explained in § II.2.2, the CoSi₂ crystal structure is cubic, and the unit cell dimension is the same as Si one). With SiCoNi pre-clean, large grains are detected, presenting a random orientation. As reported recently by Zschiesche et al. [214], diffusion barriers play a major role in reactive diffusion at the interface during silicide growth, and in particular for Co-Si system. In [215], the CoSi₂ growth in epitaxy with the Si(111) has been evidenced when 5 nm Ti interlayer is introduced between Co layer and Si substrate. The impact of the oxygen rich layer, observed only for Ar SE samples in our study, could be similar.

<figure><img src="image_107.png" /><figcaption>Figure IV.6. ASTAR™ mappings of CoSi₂ grains formed after RTA2 on Si substrates for Ar SE (a to c) and SiCoNi (d to f) surface preparation processes. Si substrate and CoSi₂ grains orientations are colored following the map in (g).</figcaption></figure>

Consequently, with Ar-preclean, from one side, remaining O contamination or residual oxide on the top of Si surface prior Co deposition induces a very stable microstructure of CoSi₂ final layer (i.e., hetero-epitaxy); from the other side, the subsequent increase in CoSi₂ effective resistivity could lead to contact integration issues.

Finally, additional RTA at high temperatures (high-RTA) after the capping by SiN of CoSi₂ layers are applied on Ar SE and SiCoNi samples. The silicide morphology is then observed by SEM cross-sections as presented in Fig. IV.7. Early agglomeration of CoSi₂ thin film is detected for SiCoNi pre-clean contrary to Ar-plasma one. As introduced in section III.5, the growth of silicide in hetero-epitaxial structure drastically increases the film resistance to agglomeration by the reduction of interface energies. This work seems to confirm this hypothesis for the Co-Si system.
<figure><img src="image_108.png" /><figcaption>Figure IV.7. SEM cross-sections images of CoSi₂ layer capped by SiN thin film formed after Ar SE (a to c) and SiCoNi pre clean (d to f) and submitted to additional thermal budgets as 700 °C (a,d), 800 °C (b,e), and 900 °C (c,f). Agglomeration is detected in (f) for SiCoNi pre-clean only.</figcaption></figure>

As a conclusion of this study, the drastic improvement induced by SiCoNi pre-clean in terms of effective resistivity and oxygen content in final CoSi₂ silicide is fully mitigated by the major change in microstructure, following the oxygen barrier removal at the interface, and its detrimental effect on CoSi₂ morphological stability.

IV.3 TiSi$_{x}$ silicide last integration for imagers technologies

IV.3.1 Additional SiCoNi pre-clean for contacts optimization

As introduced in subsection II.4.1, forming a low resistive Ti-silicide layer inside contacts after patterning requires a precise pre-clean scheme before the Ti deposition (see for instance Fig. II.27). To do so, Ar-ion-bombardment is commonly used [31] and has revealed some detrimental limitations in current imager technologies for salicide first and last technologies (as in previous section). Then, introducing an additional SiCoNi pre-clean before Ti-silicide metal deposition offers a clear interest but remains a technical challenge [29]. Contrary to Ar plasma pre-clean, SiCoNi process allows to remove selectively the silicon oxide on N⁺ doped Si surfaces without damage [93], [100]–[104]. For the last ten years, this in-situ dry chemical clean becomes the standard surface preparation process before the NiPt deposition to enhance the Ni(Pt)Si formation for CMOS technologies [106]. But, in critical dimensions, the removal of fluorosilicate solid by-products composed by (NH₄)₂SiF₆ salts might be complex.

In this section, the main results published in [91] obtained on blanket wafers and in real devices by applying various pre-clean processes before Ti deposition will be presented and discussed.

In detail, SiCoNi pre-clean, from Applied Materials platform, is based on remote plasma process including two main steps, usually called etch and anneal steps (as described in Figs. IV.8a and b). During the etch step, two reactions can be underlined as: (1) the NH₄F reactive species creation inside the remote plasma, as described by the Eq. IV.1; and (2) by flowing of these species through the showerhead, the
formation on the top of the wafer of the fluorosilicate salts through the reaction of NH₄F species with SiO₂ thin film in presence (Fig. IV.8a and Eq. IV.2).

During the anneal step, the sublimation of (NH₄)₂SiF₆ solid salts is achieved by moving up the Si wafer near the showerhead, the heater here, maintained at 180 °C. Such fluorosilicate salts are quite volatile and then transformed in SiF₄ and NH₃ gazes mainly around 100 °C (Fig. IV.8b and Eq. IV.3). These reactions induce the selective etching of SiO₂ vs Si or silicide (NiSi, CoSi₂), and also Si₃N₄ layers.

The following equations have been rewritten from [106] :

$$NF_3 + NH_3 \rightarrow NH_4F + NH_4F \cdot HF \qquad \text{Eq. IV.1}$$

$$NH_4F + SiO_2 \rightarrow (NH_4)_2SiF_6 (\text{solid}) + H_2O \qquad \text{Eq. IV.2}$$

$$(NH_4)_2SiF_6(\text{solid}) \rightarrow SiF_4(\text{gaz}) + NH_3(\text{gaz}) + HF(\text{gaz}) \qquad \text{Eq. IV.3}$$

<figure><img src="image_109.png" /><figcaption>Figure IV.8. Schematics of SiCoNi process including two main steps as (NH₄)₂SiF₆ salts generation at the top surface of Si in presence of SiO₂ layer (usually called etch) (a) and their sublimation (known as anneal) at 100 °C by moving up the wafer near the heater, here named showerhead (b).</figcaption></figure>

Three types of samples have been provided for this study. The first one is based on 20 nm-thermal oxide Si blanket wafers and is used to characterize the SiO₂ etch amount of different pre-clean combinations by ellipsometry technique. The second one includes specific 300 mm-patterned wafers designed for contact morphology study. At the end, such pre-clean processes have been included in the standard process flow of imager sensors, and electrical measurements have been made to determine the impact of these changes on contact resistance, yield, and product reliability.

In Figure IV.9, one may notice the significant mismatch between the etch amount results obtained on blanket and patterned wafers at the bottom of the contacts, but general conclusions or tendencies can be raised up for both experiments. For all the pre-cleans combined processes, the etch amount inside the contact is larger than the one measured on blanket wafers. This potentially indicates a local change in the oxide density or some confinement effect (as the presence of contact edges in salts generation). If we consider a measurement accuracy of 1 nm, the etch amount inside the contact is almost the same for all tested processes except the ones which induce a lower oxide removal on blanket than 5 nm (dashed line in Fig. IV.9a). This result suggests that no real difference in terms of surface preparation at the bottom of the contact should be observed except for the “soft” pre-cleans. Finally, the only clear difference between the SiO₂ oxide removal measured in contacts and on blanket wafers is detected for the SiCoNi-only pre-
clean, including two times the "etch-anneal" sequence. This approach is interesting to promote an
improved oxide etching in small dimensions as shown in Figure IV.9b.

The degassing time before SiCoNi appears to play a major role as an increase of etch amount in contacts is measured for similar pre-clean scheme when degassing time is reduced from 60 to 30 s (Fig. IV.9). Indeed, the wafer temperature and/or the time between each process (degassing, Ar-plasma and SiCoNi process) modifies the ability of SiCoNi in SiO₂ etching.

<figure><img src="image_110.png" /><figcaption>Figure IV.9. Evolution of SiO₂ etch amount for various pre-cleans processes measured by ellipsometry on blanket wafers and by TEM at the bottom of patterned contacts (average of 12 measurements) (a). Delta of SiO₂ etch amount between the measurements at the bottom of contacts and on blanket wafers (b). The measurement accuracy is estimated to be near 1 nm.</figcaption></figure>

Remarkable variations of 10K-contacts chain resistance are measured as a function of pre-clean conditions, displayed in Fig. IV.10. When the pre-clean is only based on an Ar-plasma process, the contact chain resistance is more than 40 % of the target. A clear reduction of contact resistance is observed by adding SiCoNi pre-clean after the Argon plasma. No clear improvement is detected for the short degassing sequence contrary to morphological observations (see Fig. IV.9). Then, the lack of statistical morphological analyses compared to the yield and electrical measurements could explain this mismatch. Effectively, the limited yield is determined for a large amount of logic and imagers devices including at least 1 million contacts. Indeed, TEM, yield and electrical characterizations do not present similar statistics and could give contrasting responses. Additional SiCoNi after Ar pre-clean (named Degas 60s/Ar 60A/SiC 40A) allows significantly improve the limited yield linked to high resistive TiSiₓ contacts in the pixel areas, as the device reliability.
<figure><img src="image_111.png" /><figcaption>Figure IV.10. Limited yield linked to high resistive TiSiₓ contacts and TiSiₓ contact chains resistance (10000 contacts, noted 10K-contacts chain) as a function of various pre-clean conditions with different combinations of Ar plasma and SiCoNi processes.</figcaption></figure>

To conclude, the introduction of SiCoNi pre-clean prior Ti/TiN deposition enables to achieve all the requirements in terms of resistance, yield, and reliability of TiSiₓ contacts. This experimental study in real devices has properly highlighted the potential reaction between Ti layer and the sub-products of previous patterning steps (C, F, and O as remaining minor species) in contacts. Therefore, for future studies on Ti-silicides contacts, specific attention is needed to surface preparation scheme to allow the low-resistive phases formation inside nano-scale features.

IV.3.2 C54-TiSi₂ formation in contacts: preliminary studies on UV-NLA treatment

As introduced at the beginning of this chapter, the aim of this section is to summarize a part of Laura Esposito's research work on the impact of laser annealing on C49-C54 transition. The laser treatment used for our study, noted UV-NLA, is performed on a SCREEN LT3100 platform at CEA-LETI in Grenoble. This laser is based on a XeCl excimer laser, which displays the following characteristics: $\lambda = 308$ nm as the wavelength and $\tau = 160$ ns as the full width at half maximum. The laser beam had a “top hat” shape, and the beam homogeneity is less than 2.5 % within each field of exposure.

In the next subsections, sheet resistance, STEM-EDX, and θ-2θ XRD analyses will permit to identify the Ti-silicides phase sequence changes induced by the addition of UV-NLA prior standard RTA on different substrates. Furthermore, several up-to-date 3D-sequential wafers have been used to provide preliminary studies on the integration of laser annealing in standard process flow.

For the blanket study, undoped/doped Si(100) and polycrystalline Si (Poly-Si) wafers have been prepared as HF wet surface preparation followed by the in-situ SiCoNi pre-clean, and 10 nm Ti layer deposition encapsulated by ALD TiN film. The samples are annealed either using only UV-NLA or combining UV-NLA and a subsequent RTA.

To have a precise estimation of the effective temperature within the TiN/Ti stack and at the Ti/Si interface during UV-NLA, 1D numerical simulations (for 1 laser pulse) were performed for various laser energy densities (noted ED in the following) using the LIAB software, provided by SCREEN-LASSE. This
computational tool, based on a finite element method, solves self-consistently the heat equation coupled to the time-harmonic solution of Maxwell equations (UV laser light coupling with the sample), including the temperature dependency of materials parameters. In our system, the calculated temperature at Si surface allows us to estimate the laser energy density value for which Si starts melting.

IV.3.2.1 Significant impact of laser annealing on C49-C54 transition on Si(100) substrates

For Si(100) blanket wafers, after 3 UV-NLA pulses, the sheet resistance drastically changes as a function of laser energy density in the 0.3-1.0 J/cm² range, as shown in Fig. IV.11 (black squares). Four different regimes can be deduced from this curve. Below 0.75 J/cm², Rs remains stable and like the post-deposition value around 70 Ω/sq. Between 0.750 and 0.825 J/cm², the resistance increases up to a maximum resistance of 86 Ω/sq. Above 0.825 J/cm², the resistance decreases down to 35 Ω/sq. at 0.875 J/cm², and then, more slowly beyond 0.875 J/cm² down to 24 Ω/sq for 1.00 J/cm².

Additional RTA treatments at temperatures between 500 and 900 °C have been performed on these samples and the minimum Rs at the lowest RTA1 temperature is observed after an RTA at 650 °C, as presented in Fig. IV.11 (red triangles). Indeed, this occurs only for an ED of 0.85 J/cm², and the measured sheet resistance is around 10 Ω/sq. At this ED value before RTA (black squares), the sheet resistance was measured at 60 Ω/sq, in the middle of the Rs decrease slope. For energy densities above 0.85 J/cm², the resistance increases to 28 Ω/sq.

<figure><img src="image_112.png" /><figcaption>Figure IV.11. Sheet resistance measured after the reaction of an 11 nm Ti layer with Si(100) substrate as a function of laser energy density after 3 UV-NLA pulses only (black squares), and after UV-NLA followed by RTA at 650 °C for 30 s (red triangles), from [216].</figcaption></figure>

The identification of phase changes occurring during the UV-NLA treatment for the studied TiN-Ti-Si system is provided by XRD, TEM-EDX analyses [216]. A specific focus is given for the annealed sample by UV-NLA at ED of 0.85 J/cm² to establish which phase sequence allows the strong reduction of silicide resistivity, assumed to be related to the C54-TiSi₂ formation, as a first approach.

Before that, for an ED at 0.80 J/cm², the Rs increase before the sharp decrease is related through XRD and TEM-EDX analyses to the growth of an amorphous phase, noted a-Ti₁-xSix [216].

Following a-Ti₁-xSix formation, after UV-NLA at 0.85 J/cm², HRTEM cross-sections and EDX profiles reveal the presence of two layers on the top of Si substrate as displayed in Figs. IV.12a and b. Top-to-down analysis evidences an unchanged TiN capping layer compared to TEM observations after deposition (not shown here), and the formation of a silicide layer with a thickness varying between 17 and 21 ± 0.6 nm,
depending on the silicide/Si interface morphology (Fig. IV.12a). The analysis of the electron diffraction pattern during TEM observations (again, not shown here) demonstrates that the silicide layer is at least partially crystalline. It was however difficult to determine if this layer is fully crystallized or not. In Fig. IV.12b, a 1:1 Ti/N ratio is detected for the TiN layer and the average Ti:Si ratio in the silicide layer is found to be close to 1:2 indicating the formation of a silicide close to TiSi₂, but with a certain deviation from the exact stoichiometry. Indeed, the Ti and Si EDX depth profiles show a composition gradient inside the silicide layer, being slightly Si-rich at the silicide/Si interface, compared to TiSi₂. APT analyses provided on this sample allows to identify that no Ti layer remains in this system and confirms the Ti/Si composition gradient in silicide layer (see for details [216]).

<figure><img src="image_113.png" /><figcaption>Figure IV.12. HRTEM image corresponding to the sample annealed at 0.85 J/cm² with 3 UV NLA pulses. Two layers are identified as TiN, and crystalline TiSi₂ on top of the Si substrate (noted c-Si, here). (b) 1D EDX profile on the same sample. Normalized θ-2θ XRD measurements corresponding to the as-deposited TiN/Ti/Si sample and those annealed with 3 UV-NLA pulses at various energy densities in the 0.75-1.00 J/cm² range.</figcaption></figure>

In addition, ex-situ θ-2θ XRD results performed on all the samples annealed by UV-NLA (3 pulses) are presented in Fig. IV.12c. For the sample annealed at 0.75 J/cm², the XRD profile is similar to the as-deposited sample one. Three overlapping peaks are observed and can be identified as TiN, TiNOₓ and Ti peaks. They have the same intensity before and after UV-NLA. The peak related to oxidized Ti is attributed to TiNOₓ based on EDX profile in Fig. IV.12 (oxidation of TiN layer). With increasing ED in the 0.80-0.90 J/cm² range, the Ti peak progressively disappears, indicating Ti consumption. The TiNOₓ peak vanishes, suggesting a redistribution of the oxygen in the sample as the ED increases. No other peaks are detected, related to the formation of an amorphous silicide layer during Ti consumption - as shown in [216].

Above 0.90 J/cm², the TiN peak is still present but there is no more Ti peak in the XRD profile, indicating that Ti is fully consumed during the reaction. Moreover, a second peak appears at 40.52° corresponding to the formation of the C40-TiSi₂ phase.

Similar analyses have been realized in the case of additional RTA at 650 °C and the XRD results are the following:
<figure><img src="image_114.png" /></figure>

Figure IV.13. Normalized θ-2θ XRD measurements corresponding to TiN/Ti/Si samples annealed with 3 UV-NLA pulses, at various energy densities in the 0.75-1.00 J/cm² range, followed by an RTA at 650 °C for 30 s.

At 0.80 J/cm², the only detected phase, except TiN, is the C49-TiSi₂ one with the (131) peak at 41.1°. At 0.85 J/cm², the only observable phase is the C54-TiSi₂ one with a (004) peak at 42.2°. However, XRD profiles corresponding to 0.90 and 0.95 J/cm² show again C49-TiSi₂ with an additional peak at 40.0°.

Thus, the formation of C54-TiSi₂ phase, as the only silicide phase in presence, is observed by XRD for three laser pulses at an energy density of 0.85 J/cm² followed by an RTA at 650 °C for 30 s.

The inherent conditions of C40-TiSi₂ phase formation have been investigated through top-views SEM observations (not shown here) and numerical simulations of the effective temperature reached in the system during UV-NLA treatment.

For ED 0.85 J/cm² and higher, the SEM images and the numerical simulations both are indicating that a liquid phase is obtained during the laser pulse. Indeed, top-views SEM images shows that the top surface morphology starts to change with the formation of ripples coming from solidification of a liquid, as discussed in [216]. Interesting insights are then provided by numerical simulations which suggest that the maximum of effective temperature varies between 1455 °C and 1537 °C for ED increasing from 0.85 to 1.00 J/cm² (Fig. IV.14).

<figure><img src="image_115.png" /></figure>

Figure IV.14. Simulated surface temperature as a function of time for laser energy density values from 0.30 to 1.00 J/cm² for one pulse (a) and from 0.70 and 1.00 J/cm² (b), using LIAB software, provided by SCREEN-LASSE.
Moreover, there is only a variation of 30 °C between the top of the TiN layer and the top of the Si substrate. Thus, the temperature might be even in the material stack. As the maximum temperatures in this ED range are much lower than the melting points of Ti (1668 °C) and TiN (2950 °C), these two phases should remain solid. However, these temperatures are larger than the melting point of Si (1415 °C). The temperature at which the amorphous phase, a-Ti₁-xSiₓ, is expected to melt should be lower than the melting points of Si and TiSi₂ (1482 °C). If a-Ti₁-xSiₓ is formed before the temperature reaches the melting point of Si, one can thus expect to obtain a liquid for ED below 0.85 J/cm². Whatsoever, our results strongly suggest that Si and a-Ti₁-xSiₓ phases are the first phases to melt and that the simulations provide an accurate temperature evolution during UV-NLA. This should be the case at least for the ED of 0.85 J/cm² as the maximum temperature is near to melting point of Si. For higher ED, as the melting point of TiSi₂ is also exceeded, the melting of the reaction products (a-Ti₁-xSiₓ, TiSi₂, etc.) could occur.

From 0.85 J/cm², there is a sharp decrease of the Rs and no XRD peaks are observed (Figs. IV. 11 and 12). Moreover, XRD peaks of the C40-TiSi₂ phase are obtained for ED larger than 0.85 J/cm². This strongly suggests that the C40-TiSi₂ is formed from the liquid (as also proposed by D'Anna et al. [217], [218]). However, the formation of the C40-TiSi₂ remains unclear and further measurements will be needed to precisely understand the involved mechanism(s).

At the end, during the UV-NLA treatment, the phase sequence might be:

$$Ti + Si \rightarrow aTi_{1-x}Si_x(s) \rightarrow aTi_{1-x}Si_x(l) + Si(l) \rightarrow C40TiSi_2(s) + aTi_{1-x}Si_x(s) \rightarrow C40TiSi_2(s) \quad \text{Eq. IV.4}$$
where (s) and (l) defined the solid and liquid states, respectively.

A summary of the identified phase sequences after UV-NLA and after UV-NLA followed by an RTA at 650 °C is proposed in Figure IV.15, in parallel to the Rs evolution (same color here).

<figure><img src="image_116.png" /><figcaption>Figure IV.15. Sheet resistance measured after the reaction of an 11 nm Ti layer with Si(100) substrate as a function of laser energy density after UV-NLA only (black square) and after UV-NLA followed by an RTA at 650 °C for 30 s (red triangles) (a). Phases formed at these EDs based on XRD and TEM-EDX analyses for similar thermal treatments (same color) (b).</figcaption></figure>

As a conclusion of this section, the formation of C40-TiSi₂ during UV-NLA enables to enhance the formation of C54-TiSi₂ during subsequent RTA and reduce significantly (from 800 to 650 °C) the formation temperature of the C54-TiSi₂ phase needed for contact integration. There is a threshold in the laser energy density at 0.85 J/cm². Below this threshold, an amorphous silicide grows by a solid-state reaction in accordance with previous studies. The threshold appears to be linked to the melting of Si and the formation of the C40-TiSi₂ from the liquid phase. Above the threshold, only the C40-TiSi₂ phase is obtained. However,
the formation of unique C54-TiSi₂ at low RTA temperatures (650 °C) is only possible at this threshold energy density. It seems that, at this ED, a mixture between C40-TiSi₂ and amorphous silicide is obtained and enables an easier nucleation of C54-TiSi₂ at the low RTA temperature by a template effect of the C40-TiSi₂ phase and a high driving force for nucleation.

Nevertheless, several questions remain and on top of that, the opportunity to integrate the UV-NLA in a real process flow after the contact patterning. Another concern should be the influence of the nano-scale dimensions of the contacts (around 60 nm²) on amorphous, C40, C49 and C54-TiSi₂ nucleation. Is the phase sequence conserved? Is an acceleration in phase sequence in small dimensions, meaning that C54-phase should be formed at lower temperatures in contacts?

IV.3.2.2 Influence of dopants and substrate type on C49-C54 transition

The influence of dopants and substrates crystallinity on C40-TiSi₂ phase nucleation during UV-NLA and further transitions (or not) in C49 and C54 phases needs to be precisely investigated before UV-NLA introduction in standard process flow. In this section, only a summary will be given, and these results will be presented and then discussed in a further paper soon. For this work, in addition to "undoped" samples presented in previous section, two new sets of blanket wafers have been prepared as named afterwards "N⁺ doped Si(100)" and "N⁺ doped Poly-Si" samples. In details the implant doping of the monocrystalline and polycrystalline Si substrates is fully representative of the current process flow, based on three steps of As and P ionic implantations at various energies and doses (comprised respectively between 15 and 30 KeV and 6.10¹³ and 6.10¹⁵ at/cm²). The dopants activation is performed during two annealings as an RTA at 920 °C for 20 s and a spike anneal at 1100 °C. All other parameters remain unchanged.

Figure IV.16 shows Rs evolution after the UV-NLA treatment (3 pulses) for undoped (a, d) and N⁺ doped Si(100) (b, e) samples which could be compared also in this figure to N⁺ doped Poly-Si ones (c, f).

Firstly, one may notice that for N⁺ doped Si(100) sample, the abrupt Rs decrease, associated to C40-TiSi₂ formation during UN-NLA, is slightly shifted to the high energy densities for doped Si(100) substrates. For undoped samples this threshold is observed at 0.825 J/cm², compared to 0.85 J/cm² for doped samples. Secondly, for the doped Poly-Si substrates, the Rs fall is detected at 0,775 J/cm², significantly lower than for monocrystalline ones. A lower melting temperature is thus possible for polycrystalline Si vs Si crystal.

Based on ex-situ θ-2θ XRD analyses (not shown here), the phase sequence induced by UV-NLA and UV-NLA followed by an RTA at 650 °C has been determined, as shown in Figs. IV.16d, e, and f for the three types of samples.

For the doped Si(100) samples, the C40-TiSi₂ phase is only detected from an ED of 0.95 J/cm², definitely higher than expected and contrary to the Rs decrease observed at 0.85 J/cm². Moreover, after RTA, the C54-TiSi₂ phase is then identified for an ED of 0.85 J/cm². A potential specific texture of C40-TiSi₂ phase in the case of doped samples might avoid the out-plane detection of associated diffraction peaks. Nevertheless, the C54-TiSi₂ formation is confirmed at 0.85 J/cm² after an RTA at 650 °C for doped monocrystalline substrates, which might indicate a low influence of doping on its formation. But, at higher ED results are different. The re-appearance of C40 phase for higher ED in addition to a suspected change in silicide texture (or transition to amorphous phase) needs to be confirmed in the future.
<figure><img src="image_117.png" /><figcaption>Figure IV.16. Sheet resistance measured after the reaction of an 11 nm Ti layer with different substrates as a function of laser energy density after UV-NLA and after UV-NLA followed by RTA at 650 °C for 30 s (a to c, respectively for Si(100), doped Si(100) and doped Poly-Si). Phases formed at these EDs based on θ-2θ XRD analyses for undoped and doped substrates after UV-NLA (dark bars) and after UV-NLA followed by RTA (bright bars) (d to f).</figcaption></figure>

For doped Poly-Si substrates, C40-TiSi₂ phase is distinguished at 0.825 J/cm² after UV-NLA, but C54 phase has not been evidenced for RTA temperatures lower than 800 °C (Figs. IV.16c and f). That is quite surprising because the phases formation after UV-NLA for these samples was almost like the previous ones. This might indicate a change in C40 phase microstructure and a lack of nucleation sites for C54 phase. Moreover, some changes in texture could affect the veracity of θ-2θ XRD results and EELS or IPRSM could be promoted on these samples to conclude on this subject.

Nevertheless, at that point, no benefits of UV-NLA introduction have been demonstrated for doped Poly-Si substrates on blanket wafers. Precise analyses of the influence of dopant types (As vs P), as done on Ni-Si system (§ III.2.3), are then required.
IV.3.2.3 First trials on patterned wafers and perspectives

Patterned wafers were prepared for this study following the up-to-date 3D-sequential BSI imager
technology (as described in Fig. II.1.4). These wafers are then submitted to UV-NLA treatment after the
deposition of 11 nm Ti and 4 nm TiN layers. Figure IV.17a illustrates the schematic of the contact
dimensions and shape as a 600 nm deep and 70-125 nm wide cavity inside the PMD isolator layer. Top-
view SEM image of the dense contact chains is also displayed in Fig. IV.17b (dark holes).

<figure><img src="image_118.png" /><figcaption>Figure IV.17. Schematic of a real contact structure after Ti/TiN deposition in 3D-sequential BSI imager technology (a). Top-view SEM observation of the dense contact chains after Ti/TiN deposition (dark holes).</figcaption></figure>

UV-NLA treatments with a chuck at room temperature and for a laser energy density varying in the 0.30-0.70 J/cm² range are applied on these samples, and severe damages on the top surface are observed through top-view SEM analyses as shown below.

<figure><img src="image_119.png" /><figcaption>Figure IV.18. Top-view SEM observations of the dense contact chains after Ti/TiN deposition followed by UV-NLA treatment (1 pulse) at an ED of 0.375 (a), 0.400 (b), and 0.500 J/cm² (c). Additional characterizations evidence some cracks in TiN top layer and associated Ti-rich defects, which might indicate that the melting temperature of Ti (1668 °C) was reached during UV-NLA treatment.</figcaption></figure>

Such degradations of the top surface surrounding the contacts and formed by the Ti/TiN stack have
been investigated through additional characterizations (not shown here) and cracks in TiN, in addition to
the formation of Ti-rich defects have been evidenced. This might indicate that the melting temperature of
Ti (1668 °C) was reached during the 1 pulse UV-NLA treatment contrary to what we observed on blanket wafers.

At that point, the laser energy density range which could be applied on patterned wafers is quite limited compared to the blanket samples and leads to a real limitation of UV-NLA introduction just after Ti/TiN stack deposition.

Indeed, 2D-simulations of the maximum temperature reached at the bottom of contacts, and within the complete patterned structure in the limited ED range as 0.30-0.40 J/cm², are given in Figure IV.19. Here, whatever the energy density, the temperature does not exceed 350 °C in the region of interest, at the bottom of the contact. These values are far from the temperatures targeted to promote the formation of a liquid phase and the subsequent C40-TiSi₂ phase after its fast solidification (as discussed in IV.3.2.1). Nonetheless, these simulation results exhibit a high temperature gradient between the top and the bottom of contacts, which might be consistent with the melting of Ti layer at the top surface.

<figure><img src="image_120.png" /><figcaption>Figure IV.19. Calculated temperature field within contact structure for two laser energy density values as 0.30 J/cm² (a) and 0.40 J/cm² (b). The reached maximum of temperature at the bottom of contact is less than 400 °C, significantly lower than the temperature needed to promote the melting of Si in the region of interest.</figcaption></figure>

To get a more favorable configuration, the possibility to perform laser annealing after W contact filling and planarization, that would remove the top Ti/TiN absorbing layers, is then evaluated. Interesting preliminary results enable to leverage the efficiency of W plug to absorb the laser radiation and redistribute heat in the whole structure. In that case, the ED requested to reach the melt of Si at the bottom of the contact is around 1.1 J/cm², significantly higher than expected based on blanket analyses, but potentially realistic on patterned wafers.

As a conclusion of this preliminary work, we could highlight the clear difficulties in the UV-NLA introduction in standard process flow as heat dissipation and absorption within contact structure change drastically due to the thick dielectric layers in presence. Details around the proposed future works on that subject will be given as well in the next chapter.
IV.4 MIS contacts experimental results

During J. Borrel’s Ph.D thesis and as summarized in the following publications [127],[215], complex numerical simulations were used to identify the potential candidates for MIS contacts application from a theoretical point of view. Based on these simulations, a clear link between contact I-V characteristics with their impact on MOSFETs performance was then provided.

Nevertheless, practical concerns around ultra-thin dielectric layer stability deposited on the top of doped-Si surface remain a key aspect in the field of MIS contacts integrations. After a brief overview of the parasitic phenomena suspected to take place in MIS stacking, a part of experimental results obtained on Al₂O₃, HfO₂ and TiO₂ insertion layers will be presented and discussed.

According to the theory of tunneling, one of the major parameters to consider evaluating the dielectric induced tunnel resistance at a given thickness is the Conduction and Valence Band Offsets (commonly noted CBO and VBO). These values are represented in Figure IV.20 and the minimization of CBO and VBO levels is required on N⁺ and P⁺ doped substrates to allow improved MIS contact resistivities.

<figure><img src="image_121.png" /><figcaption>Figure IV.20. Conduction and Valence Band Offsets (in eV) to Si of various dielectrics [220], [221].</figcaption></figure>

According to the CBO and VBO values, the transmission probability of electrons and holes across these dielectric layers for a given thickness can be sorted as:

$$T_{TiO_2} > T_{HfO_2} > T_{Al_2O_3} \qquad \text{Eq. IV. 5}$$

Another point of interest is the very high tunnel barrier of SiO₂ (Fig. IV.20), and a small thickness of 3 Å, meaning only 2 mono layers of substrate oxide can significantly deteriorate the current flowing. Then it can be anticipated that even a small regrowth of substrate oxide could lead to dramatic degradation of the MIS contacts properties. Therefore, particular attention should be paid to controlling the quality of the substrate surface but also to evaluate the thickness of the interfacial oxide layer, the O gradient and redistribution at the interfaces of insertion layers.

In the literature, using ultra-low temperature ALD process, Ho et al. achieve to deposit 30 ALD cycles of HfO₂ material without SiO₂ layer formation. Nevertheless, after an anneal at 450 °C, thin silicon dioxide is detected. This oxidation is attributed to the diffusion of oxygen contained in HfO₂ into Si. Before
the annealing, H atoms previously adsorbed at the HfO₂/Si interface act as a barrier for diffusion. The annealing removes the remaining hydrogen and allows the excess oxygen to diffuse to Si substrate.

Recently, Yu et al. [Yu_2015] have studied the stability of TiOₓ based MIS contacts as function of the annealing temperature. Using a Ti metallization, a subsequent anneal at 400 °C induced a clear deterioration of the insertion. This degradation is attributed to the diffusion of oxygen on the top of Ti metallic layer (confirmed by simulations).

To prevent these parasitic phenomena, HF-last passivation is applied as wet cleaning of Si surface before dielectric deposition, and the time between ex-situ wet cleaning and in-situ surface preparation is less than 4 hours. Nonetheless, the W filling of contacts performed by CVD deposition requires a process temperature of 440 °C and is applied after insertion and Ti/TiN depositions.

The experiments were carried out in both STMicroelectronics and LETI clean rooms following the standard process flow until contact integration.

In the former, some trials on forming a TiO₂ layer using an indirect process, i.e., by depositing a Ti layer on SiO₂, were launched. This integration will be called “scavenging-TiO₂ layer” in the following.

In the latter, HfO₂ and Al₂O₃ layers were deposited on Si substrates by ALD whereas TiO₂ insertion layer was grown by CVD.

For “scavenging-TiO₂” trials, after implantation steps, wafers are cleaned with a HF (1%) solution and SiO₂ chemical film is regrown in diluted NH₄OH and H₂O₂ solution. A controlled 9 Å thin chemical SiO₂ is then measured. Prior to the Ti deposition, the Si-O bindings on the top of the samples are confirmed by XPS at 103.3 eV, as expected. A specific ultra-thin Ti layer of 11 Å is then deposited by PVD, just after the degassing of the wafer at 390 °C during 30 s. After the deposition of Ti, in-situ annealings are performed without vacuum break. These annealings, performed at 390 °C for various times, are expected to enhance the reaction in the Ti-Si-O system. Without any vacuum break, a thick TiN layer of 200 Å prevents any additional oxidation of the surrounding layers. XPS, and TEM-EDX analyses are used to identify the main changes inside the studied samples in addition to electrical measurements.

<figure><img src="image_122.png" /><figcaption>Figure IV.21. O1s (a,c) and Si2p (b,d) energy measured by XPS before (a,b) and after Ti deposition (c,d) for the “scavenging-TiO₂” samples. Shifts in the binding energies are underlined by the bleu arrows.</figcaption></figure>
As shown in Figs. IV.21a and c, Ti deposition on the top of chemical oxide layer induces a shift of -1.7 eV of the O1s peak, indicating the formation of a TiO₂ compound. Considering the Si2p peaks in Figs. IV.21b and d, the magnitude of the Si-O component appears unmodified by the Ti deposition, as expected if the scavenging effect modifies only the O concentration inside the SiO₂ layer. However, its position is shifted by -1 eV. Therefore, these observations suggest that the amount of Si-O bonds has not decreased but that their chemical environment has been modified. According to [222], this phenomenon is also a signature of Ti-silicate components formation.

To study the influence of the thermal budget on the scavenging effect, similar XPS measurements are performed on samples which have been submitted to an anneal without vacuum break between Ti and TiN depositions. Unfortunately, this type of annealing does not enable to reduce the Si-O peak intensity to the benefit of Ti-O one. Then, this type of process does not allow an enhancement of scavenging effect on those samples and does not fit the MIS contact integration requirements.

For the ALD-based high-k depositions, performed at LETI, a strong delay of nucleation is observed on HF-passivated Si substrate for Al₂O₃ and HfO₂. Nevertheless, by comparing XPS signal after ALD deposition on SiO₂ layer and on HF-passivated Si substrate, a thin SiO₂ layer is evidenced after Al₂O₃ deposition, increasing as a function of cycles number. This might be related to the ALD temperature process set here at 300 °C which appears to be inappropriate with insertion layer requirements.

For Al₂O₃ samples, significant impact of Ti surrounding layer on Al₂O₃ insertion is observed (namely by EELS in Fig. IV.22). In Figs. IV.22a and c, no Ti layer capped the Al₂O₃ insertion layer, and TiN layer is directly deposited on the top of this layer followed by W deposition in the case of Fig. IV.22c. On the right, the complete metallization stack of current contact integration as Ti/TiN/W has been deposited on the top of Al₂O₃ layer. And clear O, Si and Al diffusions are then detected (Figs. IV.22b and d). The formation of silicates, Ti silicides and Al-Ti compounds could induce severe degradations of MIS contacts integrity in that case.

<figure><img src="image_123.png" /><figcaption>Figure IV.22. Si, Al, O, and Ti profiles obtained by EELS on (from the top to the bottom) TiN/Al₂O₃/Si (a), W/TiN/Al₂O₃/Si (b), TiN/Ti/Al₂O₃/Si (c) and the complete metallization stack as W/TiN/Ti/Al₂O₃/Si (d).</figcaption></figure>
In this paragraph, the electrical properties of the TiO₂-, HfO₂- and Al₂O₃- implemented MIS contacts are investigated using Transfer Length Measurement (TLM) structures fabricated on 200 mm wafers at LETI. The TLM configuration allows to precisely estimate the contact resistivity by extrapolating the sheet resistance value between two contacts as a function of the distance between them (deep explanations could be found in [7], [134], [223] and in further section).

As a first step, Metal-Semiconductor contacts (almost equivalent to Ti-based contact previously introduced) consisting of a direct TiN/Ti stack deposition on the top of doped substrate are measured. One may note that no intentional silicidation annealing is performed here contrary to Ti-silicides contacts even though the subsequent processes, as W deposition, could lead to TiSiₓ amorphous or crystalline phase. The results are summarized in Table IV.1 and the Ti-direct contact are noted in the following MS contacts, i.e., Metal Semiconductor.

<table><caption>Table IV.1. Contact resistivities of the reference TiN/Ti/Si and TiN/Si contacts extracted using TLM structures.</caption><thead><tr><th rowspan="2">Sample type</th><th colspan="2">Associated resistivity<br>(10<sup>-8</sup> Ω.cm<sup>2</sup>)</th></tr><tr><th>p-Si</th><th>n-Si</th></tr></thead><tbody><tr><td>Reference TiN/Ti/Si</td><td>29</td><td>3.7</td></tr><tr><td>Reference TiN/Si</td><td>26</td><td>3.1</td></tr></tbody></table>

Similar TLM extractions are attempted on all the combinations of capping and insertion layers as represented in Figure IV.23. Different insertion thicknesses are studied, and the MS references correspond to an insertion layer thickness equal to zero.

<figure><img src="image_124.png" /><figcaption>Figure IV.23. TLM extracted contact resistivity as the function of the thickness of Al₂O₃, HfO₂ and TiO₂ insertion layer for MIS contact in the cases of TiN/Ti and TiN metallizations. The MS contacts used as references correspond to an insertion layer thickness equal to zero.</figcaption></figure>

Presenting similar behavior, the cases of TiO₂ and HfO₂ are treated together. For these dielectrics, only the case of a Ti metallization is commented since it appears that the resistivity extraction was not possible in the case of a direct TiN capping metal. The performances of the MIS contacts are found to be significantly degraded compared to the MS ones. These unexpected high resistivity results could be linked
to the O diffusion from the insertion layer to Ti capped layer, and also a lack in crystallinity of insertion layer [224]. Nevertheless, for TiO₂ and HfO₂-based MIS contacts, no optimal configuration is found, and the resistivity of each MS contact reference remains the lower one.

The case of Al₂O₃-based MIS contacts displays a behavior far different from previous ones. Firstly, the performance of contacts on p-Si does not feature the same significant degradation. Even more, an improvement is observed and the expected “U-shaped curve” (shown in Figure II.31) is obtained with an optimal thickness of 3.8 Å for both TiN/Ti and TiN metallizations. Degradation is only observed in the case of n-Si substrates. This observation appears inconsistent with the initial expectations: Ti could be considered as n-type and TiN as p-type (see [7] for details). Then, whereas contacts on p-Si would be improved with TiN and degraded with Ti, contacts on n-Si should demonstrate the opposite behavior. However, in this work, the tendency of the contact resistivity is the same regardless of the metallization type. This consideration may have two principal explanations. On the one hand, the ideal workfunction of TiN was assumed to be around 4.8 eV meaning closer to a p-type metal. Nevertheless, this value is not a real consensus in literature. On the other hand, if assuming that Ti is effectively n-type and TiN p-type, such behavior could be explained by considering that the dielectric does not mitigate the Fermi Level Pinning (FLP) but induces a FLP at another energy in the Si bandgap. Such a result has already been obtained in [225]. At the end, the optimal thicknesses corresponding to each combination are summarized below.

<table><caption>Table IV.2. Optimal insertion layer thickness and contact resistivities of the Al₂O₃, HfO₂ and TiO₂ MIS contacts extracted using TLM structures.</caption><thead><tr><th rowspan="2">Sample type</th><th colspan="2">Best configuration (thickness in Å)</th><th colspan="2">Associated resistivity (10<sup>-8</sup> Ω.cm<sup>2</sup>)</th></tr><tr><th>p-Si</th><th>n-Si</th><th>p-Si</th><th>n-Si</th></tr></thead><tbody><tr><td>TiN/Ti/Al<sub>2</sub>O<sub>3</sub>/Si</td><td>3.8</td><td>0</td><td>11</td><td>3.7</td></tr><tr><td>TiN/Al<sub>2</sub>O<sub>3</sub>/Si</td><td>3.8</td><td>0</td><td>9.5</td><td>3.1</td></tr><tr><td>TiN/Ti/HfO<sub>2</sub>/Si</td><td>0</td><td>0</td><td>29</td><td>3.7</td></tr><tr><td>TiN/HfO<sub>2</sub>/Si</td><td>x</td><td>x</td><td>x</td><td>x</td></tr><tr><td>TiN/Ti/TiO<sub>2</sub>/Si</td><td>0</td><td>0</td><td>29</td><td>3.7</td></tr><tr><td>TiN/TiO<sub>2</sub>/Si</td><td>x</td><td>x</td><td>x</td><td>x</td></tr></tbody></table>

To summarize, and as highlighted in this table, the main conclusion remains that the ranking of the dielectrics, in terms of induced tunnel resistance, is far from expected. Indeed, TiO₂ was initially anticipated as the best candidate for MIS contacts, and results in the most resistive stacks of our study. This phenomenon seems to be attributed to the intermixing of elements occurring in the Ti-Si-O system. On the contrary, an improvement on p-Si is found when using Al₂O₃.

Most of the MIS contacts studies are performed in a non-industrial environment and are more involved in achieving a proof of concept rather than implementing MIS or MIIS contacts in existing manufactured products with all their constraints.

As demonstrated in this section, stable ultra-thin dielectric insertions are not easily achieved in standard process flow and in our cleanroom environment. The presence of Ti in the classical metallization used in microelectronic industry, namely W/TiN/Ti, leads a clear degradation of the insertion layer. Moreover, such scavenging effect is enhanced by any subsequent thermal budget. In a full CMOS process, the wafers are submitted to thermal budgets needed to fabricate the metal interconnects. These steps are
typically performed around 400 °C. Then a MIS contact dedicated to CMOS industry should be unaltered under this thermal budget. In this work, the deposition of W was performed at 440°C and was found high enough to induce the elements redistribution through the stacks.

Finally, as presented in the preliminary study of ALD based dielectrics, a regrowth of the substrate oxide seems unavoidable when working at 300 °C on an H-passivated surface. Only a precise ALD deposition at low temperatures as 100 °C, from my point of view, could be considered as a promising way for MIS contact integrations.

## IV.5 Ni and Ti-based intermetallic contacts on III/V

The goal of F. Boyer's Ph. D thesis was to determine the eligibility of four metallizations, hence eight systems, to be low-resistive and reliable contacts on InP and In₀.₅₃Ga₀.₄₇As epitaxial layers. Indeed, a deep investigation of phase sequence, layer morphology, element distribution and electrical properties of the subsequent systems is then provided: as Ni-InP, Ni-In₀.₅₃Ga₀.₄₇As, Ni(10 at.% Pt)-InP, Ni(10 at.% Pt)-In₀.₅₃Ga₀.₄₇As, Ni₂P-InP, Ni₂P- In₀.₅₃Ga₀.₄₇As, Ti-InP, and Ti-In₀.₅₃Ga₀.₄₇As. In addition, a reliability study has been performed throughout the emulation of subsequent process steps such as CVD W deposition at 450 °C for 180 s, as well as long-term thermal stress (100 °C for one week). At the end, two innovative contact integrations are proposed in the frame of the introduction of the III-V/Si hybrid laser onto Si, as will be summarized in the last subsection of this chapter.

The aim of this section is not to explain and detail all the results that have been obtained during this thesis; but to highlight the specific results needed for the reader to apprehend the remaining questions such as: 1) the correlation (or not) between electrical behavior and morphological stability; and 2) the clear phase sequence identification for these systems. In that way, the perspectives of F. Boyer's work will be included in the research project in the next chapter. Additionally to the Ph.D manuscript [134], one might find the extended report of these results in the following references [226]–[228].

### IV.5.1 Transfer Length Method (TLM) measurements: contact resistivity extraction

In this section, the Transfer Length Method (TLM), which is a widely used electrical characterization method ([28], [29], [126], [223]) is presented. The Figure IV.24 shows the resistance contributions existing between a metal in contact to a semiconductor (noted SC). The sheet resistance Rₛₕ represents the resistivity averaged over the substrate thickness. R_c is the contact resistance, and the contact dimensions are respectively noted w and d, as described in Fig. IV.25a. In this example, lᵢ represents the distance between the two metallic contact pads and varies in the TLM structure (Fig. IV.25b). The overall encountered resistance Rᵢ is related to other parameters as:

$$R_i = R_{sh} \cdot \frac{l_i}{w} + 2R_c \qquad \text{Eq. IV.6}$$

<figure><img src="image_125.png" /><figcaption>Figure IV.24. Schematics of the resistance contributions between a metal and a semiconductor (noted SC).</figcaption></figure>
In this study, squared-TLM are used and d = w = 200 µm. The squared pads are separated by 5 spacings values: 20, 40, 60, 80 and 120 µm, referred as lᵢ, with i ranging from 1 to 5 (Fig. IV.25b).

<figure><img src="image_126.png" /><figcaption>Figure IV.25. Representation of the TLM test structures in top view a), and in cross-section b). Schematics of metal films deposited on the top of III-V epitaxial layers before electrical measurements (cross-section) c). Ni, Ni₂P, Ni(10 at.% Pt), and Ti are used as “contact metal” in the scope of this work.</figcaption></figure>

Using the four-probe configuration, a voltage range between -2.00 V and +2.00 V is applied for each consecutive pad and the current-voltage (I-V) curves are then extracted for each spacing as described in Fig. IV.26a. The I-V curves are linear here, related to an ohmic contact.

<figure><img src="image_127.png" /><figcaption>Figure IV.26. I-V characteristics extracted by Transfer Length Method in the case of an ohmic contact a), and evolution of the deduced resistance as a function of the spacing value between pads b).</figcaption></figure>

The resistance Rᵢ can be calculated from each I-V characteristics as a function of the spacing value lᵢ, and R_c and R\_sh could be finally deduced from the fit of the linear curve y = ax + b as:

$$R_{sh} = aw \text{ and } R_c = \frac{b}{2} \qquad \text{Eqs. IV.7 and 8}$$

The transfer length (L_T) is defined as the intersection between the Rᵢ = f(lᵢ) curve and the x axis, given by:

$$L_T = \frac{b}{2a} \qquad \text{Eq. IV.9}$$

As a result, the contact resistivity ρ_c is defined as:

$$\rho_c = \frac{R_c L_T w}{\coth\left(\frac{d}{L_T}\right)} \qquad \text{Eq. IV.10}$$

Thus, the TLM measurements allow the determination of contact resistivity, expressed in Ω.cm².
With this type of electrical characterizations, we are also able to define the “non-ohmicity” of studied contacts, i.e. Schottky contacts as first introduced in [229]. The I-V extractions of such contacts are presented in Fig. IV.27 and are non-linear, meaning that the resistance between contact pads and substrate varies as a function of applied voltage.

<figure><img src="image_128.png" /><figcaption>Figure IV.27. I-V characteristics extracted from by Transfer Length Method in the case of a non-ohmic contact (Schottky contact) a), and voltage evolution as a function of ln(I) extracted from a) (for $I_1$).</figcaption></figure>

As a result, the TLM formalism could not be properly applied and the I-V behavior is associated to the diode one, leading to the determination of the contact barrier height $\Phi_B$, as detailed in the following equations (see [134]).

$$I = I_0 \cdot \left( \exp\left(\frac{qV}{nkT}\right) - 1 \right) \qquad \text{Eq. IV.11}$$

With n the ideality factor and $I_0$ the saturation current, which could be expressed as:

$$I_0 = A \cdot A^* \cdot T^2 \cdot \exp\left(-\frac{q\Phi_B}{kT}\right) \qquad \text{Eq. IV.12}$$

where A is the contact area, $A^*$ and k are respectively the Richardson and the Boltzmann constants, and T the temperature.

As presented in Fig. IV.27b, the characteristics of V = ln(I) in the case of non-ohmic contact allows to determine the tangent to the curve when ln(I) tends to zero, and indeed from Eq. IV.12, this value is equal to $\frac{nkT}{qV}$. Finally, the barrier height $\Phi_B$ is given by:

$$\Phi_B = \frac{kT}{q} \ln \left( \frac{A \cdot A^* \cdot T^2}{I_0} \right) \qquad \text{Eq. IV.13}$$

In the following, the contact resistivity is extracted by the TLM method for each system right after the deposition of the complete stack (described in Fig. IV.25c) and an RTA at a temperature ranging from 250 to 500 °C for 60 s.
IV.5.2 TLM limitations: electrical vs morphological behavior

In the frame of the determination of contact stability through electrical measurements, two
examples of TLM measurement limitations will be discussed in this section. Firstly, the contact resistivity
extracted through TLM method is presented for the NiPt-In<sub>0.53</sub>Ga<sub>0.47</sub>As and Ti-InP systems; Secondly, the
morphology of the intermetallic layer formed after RTA in both cases will be verified though STEM-EDX
characterizations in the aim of detecting any agglomeration or delamination of such layer after a high-
temperature thermal budget.

IV.5.2.1 NiPt- In0.53Ga0.47As results after RTA

In the Figure IV.28, the contact resistivity measured for NiPt-In<sub>0.53</sub>Ga<sub>0.47</sub>As system is shown in the as-deposited state and as the function of RTA budget. Overall, ohmic contacts are then observed and a real decrease of contact resistivity is measured after an RTA at 300 °C for 60 s (divided by two compared to an anneal at 250 °C), reaching a plateau around 4.10<sup>-6</sup> Ω.cm<sup>2</sup>. After an RTA at 500 °C, the contact resistivity increases but the contact remains ohmic.

<figure><img src="image_129.png" /><figcaption>Figure IV.28. Contact resistivity obtained for NiPt-In<sub>0.53</sub>Ga<sub>0.47</sub>As system extracted from TLM measurements in the as-deposited state and after various RTA at a temperature ranging from 250 to 500 °C for 60 s.</figcaption></figure>

As could be observed in Fig. IV.29, a polyphasic intermetallic layer is formed at 500 °C, and complementary IPRSM characterizations allows to identify the (NiPt)₂In₀.₅₃Ga₀.₄₇As and several PtₓInᵧ phases in this case (not shown here). In Fig. IV.29a, which represents the EDX profile perpendicular to the sample surface, Ga segregations are also observed at (NiPt)₂In₀.₅₃Ga₀.₄₇As/TiN interface and at the TiN surface. As previously reported in [230], NiGa as well as NiAs phase might also formed in this system by analogy to the Ni pure one. Indeed, in Fig. IV 29b, the EDX mappings allow to identify the Pt-In rich regions, Ni-Ga grains including a certain As content but presenting In depletion; and some discontinuities are detected inside the intermetallic layer, which might definitely indicate the starting point of agglomeration.

Based on physical characterizations, the contact metal layer is not stable at this temperature
whereas electrical measurements could potentially suggest a suitable contact behavior (Fig. IV.28).
<figure><img src="image_130.png" /><figcaption>Figure IV.29. EDX profiles obtained, perpendicularly to the sample, surface after the reaction of an 20 nm Ni(10 at.% Pt) layer with In<sub>0.53</sub>Ga<sub>0.47</sub>As substrate at 500 °C for 60 s a). Ni, Pt, Ti, In, Ga, and As mappings measured by EDX in the same region b).</figcaption></figure>

IV.5.2.2 Ti-InP results after RTA

As previously, the contact resistivity measured for Ti-InP system is represented in the as-deposited state and as the function of RTA budget in Fig. IV.30. For all conditions, contacts are ohmic, but a clear decrease of contact resistivity is observed from the as-deposited state to the highest thermal budget (500 °C for 60 s here). This reduction is almost higher than one decade. In such system where different phases are in presence is quite difficult to estimate if one phase is preferable than another to achieve a lower resistivity and higher system stability.

<figure><img src="image_131.png" /><figcaption>Figure IV.30. Contact resistivity obtained for Ti-InP system extracted from TLM measurements in the as-deposited state and after various RTA at a temperature ranging from 250 to 500 °C for 60 s.</figcaption></figure>
Nevertheless, as presented in Fig. IV.31a, Ti, TiP, Ti₂In₅ are detected after deposition and after all the various thermal budgets whereas at high temperature pure In phase is identified though IPRSM measurements [227]. At the same time, the peak intensity of TiP phase increases significantly whereas the intensity of Ti₂In₅ peak is almost stable. The fast growth of TiP phase could explain the contact resistivity decrease (even though the intrinsic resistivity of TiP phase is not well determined). The formation of In pure phase at 350 °C, and the EDX profiles (not shown here) specify that the main diffusion species should be In and Ti for this system.

<figure><img src="image_132.png" /></figure>

Figure IV.31. Phase sequence deduced from IPRSM measurements for Ti-InP system indicating the formation after deposition, and for all RTA conditions, of TiP and Ti₂In₅ phases, and pure In phase after RTA at temperatures ranging from 350 to 500 °C a). The peak intensity extracted from IPRSM measurements of TiP and Ti₂In₅ phases in the same range of thermal budgets b).

Similar remarks could be formulated for this system concerning the releventness of TLM measurements for certain conditions.

<figure><img src="image_133.png" /></figure>

Figure IV.32. TEM cross-section micrograph obtained after the reaction of a 20 nm Ti layer with InP substrate at 500 °C for 60 s a), included the region 1 and 2 corresponding to the EDX profiles b) and c) respectively of an "undelaminated" and delaminated region. N, Ti, In, and P mappings measured by EDX in the same region (d to g).
In Fig. IV.32, TEM cross-sections and associated EDX profiles and mappings are presented for the Ti/InP sample annealed at 500 °C for 60 s. As shown in Fig. IV.30, for this condition, the contact resistivity is significantly lower, and the contact has been detected ohmic thought TLM measurements. But the intermetallic layer has clearly delaminated (Fig. IV.32a) and layer discontinuity is observed. Such delamination could be related to the vacancies diffusion which is the counterpart of In diffusion to sample surface, known as Kirkendall voiding effect ([82],[220],[37],[147]). Therefore, the contact layer demonstrates an unstable behavior in contrary to what electrical measurements might indicate. This second example explains the difficulty of apprehending the stability and reliability of contacts with the TLM method and highlights the real need to provide deep physical and morphological characterizations.

IV.5.3 Polyphasic system: example of Ni-In<sub>0.57</sub>Ga<sub>0.43</sub>As

For the Ni-In<sub>0.53</sub>Ga<sub>0.47</sub>As system, the contact resistivity and the related layer morphology and phase sequence are presented in Fig. IV.33 and Fig. IV.34 respectively. One may notice that contacts are ohmic after annealing for this system (not in the as-deposited state) and the contact resistivity decreases after an RTA at 300 °C for 60 s and remains stable for higher thermal budgets, around 3.7·10<sup>-6</sup> Ω·cm<sup>2</sup>.

<figure><img src="image_134.png" /><figcaption>Figure IV.33. Contact resistivity obtained for Ni-In<sub>0.53</sub>Ga<sub>0.47</sub>As system extracted from TLM measurements in the as-deposited state and after various RTA at a temperature ranging from 250 to 500 °C for 60 s.</figcaption></figure>

The intermetallic layer is continuous in the range of applied temperatures, indicating a morphology stability (Fig.IV.34a and b). And, based on the phase sequence analyses, no obvious phase transition is observed by IPRSM between 250 and 300 °C (Fig. IV.34c).

<figure><img src="image_135.png" /><figcaption>Figure IV.34. TEM cross-section micrographs realized after the reaction of an 20 nm Ni layer with In<sub>0.53</sub>Ga<sub>0.47</sub>As substrate in the as-deposited state a) and after an RTA at 400 °C for followed by BEOL thermal budgets b). Phase sequence deduced from IPRSM measurements for the same system after RTA at temperatures ranging from 250 to 500 °C, from [230] c).</figcaption></figure>
The reduction of contact resistivity measured at 300 °C could be related to the increase of intermetallic layer thickness and/or its grain size, or a change in phase distribution within this polyphasic system. To conclude, some new experiments between the expected transition temperature (here potentially 270 °C) are then required to estimate if the layer is polyphasic between 250 and 300 °C, which phase grows first, and by which mechanisms, and if there is an “ideal” ratio between each phase to promote the lowest resistive and quite stable contact as possible.

#### IV.5.4 Proposed integrations and conclusions on III-V systems

Out of the four investigated metallization (Ni, Ni(10 at.% Pt), Ni₂P and Ti), on both n-InP and p-In₀.₅₃Ga₀.₄₇As the several conclusions could be proposed:

- With Ni, even though the Ni-In₀.₅₃Ga₀.₄₇As system has shown suitable electrical results and stable morphological characteristics, the TiN/Ni/InP system has however demonstrated severe agglomeration.

- The addition of 10 at.% of Pt has induced an enlargement of the ohmicity window and a temperature delay of the layer agglomeration on InP systems. However, electrical, and morphological issues have been observed on In₀.₅₃Ga₀.₄₇As systems, meaning that this metallization is not a suitable solution for III-V/Si hybrid laser contact integration.

- The Ni₂P metallization has presented on both n-InP and p-In₀.₅₃Ga₀.₄₇As layers suitable and reliable layer morphology.

- Ti as a III-V contact metal has demonstrated, on both n-InP and p-In₀.₅₃Ga₀.₄₇As layers, promising electrical results, as well as reliable morphological characteristics, that are maintained throughout the emulation of W-plug filling, BEOL and long-term thermal budget.

**As a result, Ti metallization is a suitable solution for the simultaneous integration of the III-V/Si hybrid laser n- and p-contacts.**

This study has highlighted various remaining challenges and has defined next steps and opened questions.

Firstly, the proposed integration scheme involves poly-phased states. This configuration is new in manufacturable microelectronic contacts, and one of interesting challenges is the estimation of reliability and the resistivity uniformity of such layers. Moreover, the TiN capping used for this study was based on a RF-PVD deposition performed at room temperature. For standard contacts integration, the TiN capping layer is deposited using ALD method, leading to an additional thermal budget (400 °C for 120 s). Similarly, applying on the top of III/V systems the real W deposition and BEOL integration allows to evaluate the impact of real thermal budgets and introduced stresses on such polyphasic systems.

Secondly, as detailed in sections IV.5.2.1 and IV.5.2.2, good electrical properties can be extracted from TLM method on poor morphological states, such as delaminated or agglomerated layers. This is due to the large surface of the contact pads, as 200 µm-square here. Such results open the way to the precise analyses of the potential implementation of TLM features design nearer to the real contact dimensions. As a first step, some investigations around electronic fields involved in such structures could take place before experimental trials.
IV.6 Conclusions of Chapter IV

**The emergence of new BSI imaging technologies** has induced, at the end, the introduction of SiCoNi pre-clean prior to Co deposition, for first silicide integration, and before Ti deposition for the last silicide one (i.e Ti-silicide contacts). Firstly, the drastic improvement allowed by SiCoNi pre-clean, in terms of effective resistivity and oxygen content in final CoSi₂ silicide, is fully mitigated by the major change in microstructure, following the oxygen barrier removal at the interface. Such changes drastically reduce the CoSi₂ film resistance to agglomeration. Then, additional surface preparation processes, such as PAI, could be envisioned to leverage this deterioration, as detailed in the next chapter. Secondly, SiCoNi pre-clean addition prior to Ti/TiN deposition allows to achieve all the requirements in terms of resistance, yield, and reliability of TiSiₓ contacts for this technology.

**For the 3D-BSI technology,** applying an UV-NLA treatment before standard RTA is envisioned to reduce the C49-C54 transition temperature. Thus, in our work, the formation of C54-TiSi₂ phase, as the only silicide phase in presence, has been observed at an energy density of 0.85 J/cm² followed by an RTA at 650 °C for 30 s. It has been demonstrated that the formation of C40-TiSi₂ during UV-NLA allows to enhance the formation of C54-TiSi₂ during subsequent RTA at lower temperatures, on undoped and doped mono-crystalline substrates. For doped Poly-Si substrates, C40-TiSi₂ phase is distinguished at 0.825 J/cm² after UV-NLA, but C54-TiSi₂ phase has not been evidenced for RTA temperatures lower than 800 °C. This result needs to be confirmed by further characterizations (EELS, IPRSM). Nevertheless, at that point, no benefits of UV-NLA introduction have been demonstrated for doped Poly-Si substrates on blanket wafers. The difficulties of the UV-NLA introduction in standard process flow have also been highlighted in section IV.3.2.3. Details around the proposed future works will be given as well in the next chapter.

**For the advanced FDSOI-CMOS nodes,** MIS contacts have been studied and the experimental results obtained with TiO₂, HfO₂ and Al₂O₃ dielectric insertion layers have been summarized in this chapter and promising behavior has been proven for Al₂O₃ ALD layer. Nevertheless, stable ultra-thin dielectric insertions are not easily achieved in standard process flow and finally ALD deposition provided at low temperatures as 100 °C appears to be the only path to succeed in stable MIS contacts integration.

**For new advanced photonics devices,** the introduction of III-V/Si hybrid laser onto Si requires the investigation of new metallizations schemes. Eight systems have been deeply studied and, from my point of view, Ti metallization is a suitable solution for the simultaneous integration of the III-V/Si hybrid laser n- and p-contacts. Nevertheless, this study allows to identify some needed research works, such as adapted TLM features to the real contact dimensions and the potential impact of real contact and BEOL processes on polyphasic systems, which will be presented in the next chapter.
# CHAPTER V

## Research project

### Abstract

The current and future needs in the field of silicide research will be then discussed in this chapter. In the field of Ni silicide integration, the main objectives might be the reduction of junction leakage, by an improved control of phase sequence and the sensitivity to agglomeration. A specific work is requested in nano-scale dimensions to identify if there is or not an acceleration in the phase transformation. Even though Co silicide formation has been widely studied and well-integrated in the last decade, proper Co silicide formation for dense and up-to-date sub-90 nm CMOS devices has never been demonstrated or reported. Therefore, new studies, on the reduction of CoSi grains size after RTA1, have been launched and will be pursued in the next years to extend the Co silicide brick to the 65 nm node technology. Recent results of advanced contacts and mainly TiSiₓ contacts, lead of course to several new investigations, detailed here. On top of that, the characterization of phase sequence and C49-C54 transition temperature in real contacts after UL-NLA treatment is needed.
Table of Contents

<table><tr><td>V.1</td><td>Ni silicide first integration: nano-scale effect and agglomeration</td><td>156</td></tr><tr><td>V.1.1</td><td>Theta-phase grains size in nano-scale dimensions</td><td>156</td></tr><tr><td>V.1.2</td><td>Thermal stability of ultra-thin Ni(Pt)Si layer</td><td>157</td></tr><tr><td>V.2</td><td>Extendibility of Co silicide brick to 65 nm</td><td>160</td></tr><tr><td>V.3</td><td>TiSi<sub>x</sub> contacts: UV-NLA integration and nano-scale effect</td><td>161</td></tr><tr><td>V.4</td><td>Conclusive remarks</td><td>163</td></tr><tr><td>V.5</td><td>Bibliography</td><td>164</td></tr></table>
# V.1 Ni silicide first integration: nano-scale effect and agglomeration

## V.1.1 Theta-phase grains size in nano-scale dimensions

As detailed in Chapter III, θ-Ni₂Si phase is key to promote a stable NiSi phase in real devices. As could be observed in Fig. V.1, recent observations (still unpublished) allow us to clearly identify, after an RTA at 280 °C for 30 s, the NiSi nucleation at the Ni₂Si/Si interface. As reported in Table V.1, the average EDX atomic concentrations in the bottom area (noted 1 in Fig. V.1d) is relative to the NiSi phase. In the top area, the ratio between Ni and Si is strictly larger than 2, and the increase of Pt concentration inside this phase – compared to the phase below - might indicate a better Pt diffusion inside this phase, known for θ-Ni₂Si phase. Finally, ASTAR mappings on this sample demonstrate that the phase in region 2 (top area) displays a hexagonal crystal structure, and then we conclude that this phase is θ-Ni₂Si one (Fig. V.2). Moreover, the phase in region 1, at the bottom shows a clear orthorhombic structure, which is characteristic of NiSi phase (Fig. V.2).

<figure><img src="image_136.png" /><figcaption>Figure V.1. TEM cross-section micrographs realized in dense patterns after the reaction of an 20 nm Ni layer with Si substrate during an RTA at 280 °C for 30 s in bright a) and dark field b). Two phases are identified thought EDX mappings as Ni₂Si on the top (with grains) and NiSi at the bottom c). The EDX atomic concentrations are measured in regions 1 and 2 corresponding respectively to Ni₂Si and NiSi phase d) (see also Table V.1).</figcaption></figure>

<table><caption>Tables V.1. Average EDX atomic concentrations of Ni, Si, and Pt obtained through mappings obtained inside dense patterns after the reaction of a 20 nm Ni layer with Si substrate during an RTA at 280 °C for 30 s in regions 1 and 2 (Fig. V.1d).</caption><thead><tr><td>Average of EDX atomic concentration (%)</td><td>Region 1</td><td>Region 2</td></tr></thead><tbody><tr><td>Ni</td><td>55.8</td><td>65.5</td></tr><tr><td>Si</td><td>35.5</td><td>20.7</td></tr><tr><td>Pt</td><td>4.6</td><td>10.3</td></tr></tbody></table>

Several questions can be pointed out around the potential influence of nanoscale dimensions on phase sequence. First and furthermore, as presented in Chapter III's conclusions, it appears that reduction of dimensions could potentially lead to an acceleration in phase sequence. If this nanoscale effect impacts the theta-phase grain size, by drastically reducing it, the Ni diffusion through the grain boundary inside this phase could effectively be promoted. The Pt concentration should also be increased at the interface between Ni₂Si and Si or NiSi after RTA1. Moreover, some additional experiments could be started around the partial reaction and the optimization of RTA1 thermal budget in the case of patterned structures.
In the future, the potential change in the Ni-silicide formation linked to the confinement could be estimated by identifying phase in presence by TEM. Another question is: does the initial NiPt thickness have an impact on theta-phase grain size and further transformations inside the Ni-Si system? As an example, for all the technologies including the partial reaction process, the NiPt thickness is generally double compared to other technologies (thus, presenting a total reaction process). Does that change the intermixing layer, or interface? Does the absolute mass of Pt which is available in "thick-NiPt" systems compared to the "classical ones" play a role?

<figure><img src="image_137.png" /><figcaption>Figure V.2. ASTAR mappings and FFT figures obtained in violet and blue areas corresponding to θ-Ni2Si and NiSi phases respectively. Hexagonal mappings are clearly observed in the top area and orthorhombic structure is then defined at the bottom.</figcaption></figure>

The research work around this subject will be started during this year through a novel Ph. D thesis
in collaboration with the IM2NP and the CEA-LETI.

V.1.2 Thermal stability of ultra-thin Ni(Pt)Si layer

Some recent results presented in the Chapter III (section III.5.2, and in [206]) allow to estimate the agglomeration temperature of ultra-thin NiSi layers around 450 °C in real devices. On blanket wafers, as shown in Fig. III.12, the NiSi agglomeration temperature is estimated after a single RTA1 and selective etching and is expected to be around 700 °C. In the classical case of blanket experiments, the temperature of RTA1 is increased step by step on different samples to find the threshold temperature corresponding to NiSi film agglomeration. However, in real devices, if NiSi agglomeration appears during the silicide formation, this degradation will be captured by several process control steps (such as thickness or SEM top view) and will not be a real issue. The real problem - that we are faced with – is the emergence of NiSi agglomeration during the BEOL integration, and the related thermal budgets, or during the lifetime of the final devices or dies.

In this context, we had formally observed that agglomeration seems to begin at lower
temperatures inside the real devices than in blanket films by comparing as a glance Figs. III.12 and 53.

This difference, estimated to be larger than 200 °C, might be considered as an insight to silicide confinement impact (dopants, nano-scale effect, change in grain size, silicide/Si interface roughness etc...).
Effectively, if we would like to figure out the different roles of relevant parameters as detailed in C.V. Thompson's review [154], a summary of global tendencies can be found in the next table:

<table><caption>Table V. 2. Summary on the influent parameters on thin film agglomeration temperature (based on [154]). Note that final silicide grain size induced by a film thickness change could play in both ways. Moreover, all parameters are linked together, and it is complex to estimate the residual in-plane stress impact on other parameters (such as grain size).</caption><thead><tr><th></th><th>Parameter change</th><th>Change in agglomeration temperature</th><th>Impact on other parameters</th></tr></thead><tbody><tr><td>Film thickness</td><td>↗</td><td>↗</td><td>Grain size increase, potential change in microstructure (grain boundaries orientation)</td></tr><tr><td>Grain size</td><td>↗</td><td>↘</td><td>Impact on grain boundaries grooving, and number of triple junctions</td></tr><tr><td>Interface roughness, grain boundaries grooving</td><td>↗</td><td>↘</td><td>Impact of secondary elements concentration inside grain boundaries (Pt, O, N, C)</td></tr><tr><td>Residual in-plane stress</td><td>↗</td><td>↘</td><td>Low for silicide layers</td></tr><tr><td>Impurities at the film/substrate interface</td><td>↗</td><td>↘</td><td>Change in grain boundaries grooving</td></tr></tbody></table>

The main difference between blanket samples characterizations and electrical real devices can be listed as follows:

1) Measurement method: on one hand, a four-probe method is currently used to determine the agglomeration temperature as an increase of Rs value at high temperature on blanket wafer. On the other hand, in devices, the rise of small active resistance, or a global yield drop-down are related to the agglomeration occurrence and the threshold temperature is then deduced. The total area of the 4-point probes is larger than 1 mm² compared to the minimum sizing of active areas for 28 nm technology as 40 nm². This main difference could explain the experimental results and we could then propose further explanations based on the next figure.

<figure><img src="image_138.png" /><figcaption>Figure V.3. Schematics of agglomeration phenomena evolution at triple junctions between NiSi grains at different stages (top views): without agglomeration a), small holes forming at triple points b), growing of the holes c), and large agglomeration of the NiSi film with a breakage of film continuity in several zones d).</figcaption></figure>
Indeed, on blanket wafers, due to the very large area subjected to the electrical field, a significant agglomeration is needed to detect Rs increase. And we could assume that this technique could only detect severe agglomeration of NiSi layer, as shown in Fig. V.3d. This point needs to be consolidated during further studies by a precise agglomeration temperature characterization on blanket wafers (reduced RTA temperature steps). Nevertheless, at that time, we could consider that as described in Fig. V.3a and b, when no agglomeration or small holes appear, the effective resistivity of NiSi layer is not affected as well as the Rs value and devices yielding. When holes start growing, the active resistance starts to increase around 450 °C and the device yield begins to drop (as described in Fig. V.3c). As one may see, during the Rs measurement on such agglomerated NiSi films, an electronic conduction path could be found because there is no breakage of the film continuity at that stage. An Rs plateau and devices degradation could be simultaneously detected in that case. When temperature exceeds 600 or 700 °C, the film continuity is broken off leading to a significant increase of measured silicide resistivity on devices and on blanket wafers (Fig. V.3d).

2) Silicide formation: during ex-situ Rs measurements, the NiSi silicide is formed with only one RTA. For recent technologies, as discussed in the previous sections, the partial reaction has been widely implemented to minimize the devices down-scaling effect on silicide formation. The silicide formation in partial mode might be different than the one-step RTA one. Potential impact on grain size, Pt distribution, Si content and interface roughness could be expected and probably there are no black or white assumptions here. Top-view SEM, TEM-EDX characterizations, together with ASTAR top-view analyses will be necessary to identify the change in the final microstructure of NiSi silicides in the case of one-step RTA compared to the standard Salicide integration.

3) Stress induced by the SiN encapsulation: in devices, just after the silicide formation (post RTA2 or DSA2), a compressive or a tensile SiN layer is deposited on the top of NiSi layer (see integration schemes, for instance Fig. II.12). We have tried to identify the impact of internal stress (in-plane or normal) on silicide layers without success in the past. Nevertheless, the blanket and device samples do not present the same silicide top surface during such experiments. In one case (blanket after selective etching), the surface of silicide layer is free, only oxidation appears, as SiO₂ thin layer (measured around 30 Å). In devices, the silicide surface is well encapsulated by SiN, meaning that lower surface rearrangement and stress relaxation could be possible.

Based on this analysis, we have provided some preliminary trials on continuous CoSi₂ layers formed on blanket wafers including Rs measurement performed after SiN deposition. Thanks to a specific set-up of the equipment, the CoSi₂ resistivity measured before and after SiN deposition is extracted and remains unchanged. **This type of experiment should be performed for Ni-Si systems to know the difference in the potential impact on agglomeration temperature.**

4) Degradation after silicide formation: During standard Rs measurements contrary to devices analyses, the silicide formation (NiSi or NiSiGe phases) and agglomeration occur during a one-step RTA annealing. In real devices, the most widespread ways to estimate the agglomeration threshold temperature is by changing the thermal budget at the end of BEOL (final annealing) or adding a specific annealing after contacts formation [206].
In the future, ex-situ Rs measurements could be performed on complete formed NiSi layer (after RTA2), encapsulated by SiN capping to have a more accurate estimation of agglomeration threshold temperature.

5) Scaling effect: one may first consider that the reduction of agglomeration temperature in devices is linked to a lower NiSi thickness in small areas. By introducing the partial reaction process, all the observations we have made demonstrate the opposite. The thickness of silicide layer is almost the same (± 1 nm, similar regarding the TEM experimental discrepancy) in small actives areas and large ones (larger than 2 µm², like blanket wafers). Nevertheless, the silicide microstructure is clearly different between large and small areas. This point will also be integrated in the next Ph.D thesis work on Ni-Si systems which will address the impact of nano-scale dimensions on Ni-silicide phases formation and NiSi agglomeration.

## V.2 Extendibility of Co silicide brick to 65 nm

To be able to provide some robust Co silicide layer for 65 nm technology node, the main problem will be the nucleation of CoSi₂ phase on small poly-Si gates as presented in section II.3.4 (Fig. II.26). The narrow line effect, as described in Fig. V.4a, is clearly observed on N+ gates.

<figure><img src="image_139.png" /><figcaption>Figure V.4. Sheet resistance measured on N+ and P+ Poly-Si gates for different gate widths. A significant increase in resistance is observed for sub-100 nm gates due to the "narrow lined effect" from [97].</figcaption></figure>

In this context, one of the main objectives is to find a way to decrease the CoSi grain size after RTA1 which could promote an easier CoSi₂ nucleation. Then, several working axes could be reviewed as:

1) Innovative/combined PAI processes as As [95] or Ar: some recent results (unpublished yet) have demonstrated a clear change in CoSi₂ grain size after RTA2 by applying C or As PAI prior Co deposition. This first observation highlights the potential reduction of CoSi grain size for an optimized PAI process leading to an improvement of CoSi₂ formation.

2) New pre-clean schemes: as detailed in section IV.2, strong change in CoSi₂ microstructure is previously observed by introducing SiCoNi pre-clean prior Co deposition. By adding new pre-clean or combined pre-clean and PAI processes a new stable and reliable Co integration could emerge for aggressive nodes.

3) Thin Ti mediating layer: as reported by H. Zschiesche et al. [214], and reproduced in Fig. V.5 from [215], thin Ti layer (5 nm) induces the growth in hetero epitaxy of CoSi₂ on Si substrates. Such stacks could be implemented in a production line, and this is a very interesting new investigation area. We need to pay attention to the segregation of Ti and Si in the Co-Ti-Si systems and well characterize the final microstructure and potential interactions with selective etching.
<figure><img src="image_140.png" /></figure>

Figure V.5. Orientation mappings obtained by the TKD method for a thin CoSi₂ layer formed through Ti mediating layer. The hetero epitaxy of the silicide layer to the substrate is observed at the center on different figures (a,b,c) (from [215]).

4) Ni alloying or co-sputtering: as shown in Fig. V.6, the addition of Ni alloy enables the formation of CoSi phase at lower temperature, then by applying a specific RTA1 process (DSA, or shorter anneal), the CoSi grain size could be modified and the number of triple junctions could be larger in this case after RTA1 [231].

<figure><img src="image_141.png" /></figure>

Figure V.6. Rs measurements obtained on a thin Co film as a function of RTA temperature between 200 and 700 °C for different atomic concentration of Ni, introduced as alloy in Co. The pure Co sample is noted 0 % Ni (from [231]).

This work will be performed during the Ph. D thesis of Andrea Newman which started in November 2020 in collaboration with IM2NP laboratory.

## V.3 TiSiₓ contacts: UV-NLA integration and nano-scale effect

Finally, a new Ph.D thesis on the UV-NLA introduction in standard process flow and the impact of nano-scale dimensions on TiSi₂ formation has been launched early 2021. On one side, a clear difficulty has been pointed out during the preliminary studies on UV-NLA introduction on patterned wafers. On the other hand, the growth of C54-TiSi₂ phase, based on nuclei formation at the triple junctions of C49-TiSi₂ grains for standard RTA could be very complex in reduced dimensions of the contacts since the quantity of nucleation points is very low.
In this context, based on Laura Esposito's results, the objectives of this Ph. D thesis are the following:

1) determine the impact on phase formation and film agglomeration of the confinement inside a 100-nm² contact.

2) estimate the change in minor species as F, C, and O concentrations depending to the involved processes as deposition type (Atomic Layer Deposition vs Chemical Vapor Deposition) and annealings (RTA, UV-NLA).

3) establish the influence of dopants and pre-amorphization (PAI) on phase formation and potential early degradation (agglomeration).

In details, the further studies could be then envisioned as:

- **Feasibility of laser annealing on patterned wafers:** new trials will be initiated on patterned wafers after W deposition and CMP process. And similar methodology will be applied as SEM top-views and numerical simulations to try, at the end, having some electrical measurements on TiSiₓ contacts formed through UV-NLA in imaging technologies.

- **Additional dopants studies:** Si blanket wafers, including dopant species like the real pn junction (as patterned wafers) will be processed to check the impact of laser annealing. The aim of this study is to analyze the deactivation of dopants (monolayer formation), clusters development and the final dopant profile after the melting and the subsequent solidification of Si top layer. Then, a systematic study through in-situ XRD and Rs measurements on doped substrates will be initiated.

- **Influence of nano-scale dimensions on morphology, texture, and O redistribution:** To evaluate this, a specific structure has been designed on a new maskset to include in a very dense area of 1 million of TiSiₓ contacts. A dedicated process flow will provide relevant samples (deposition types, annealing types, dopants) which could be characterized by TEM-EDX at ST Crolles, Atom-probe at IM2NP Marseille and at ESRF (Grenoble) if possible. The aim of this study is to identify a change, i.e., a delay/acceleration in the C54-TiSi₂ formation temperature, due to the confinement and the subsequent change in triple junction number in C49 phase layer (nuclei points for C54 phase). Moreover, a potential early agglomeration might happen regarding the process conditions in such confined environment. This point could also be characterized by TEM-EDX.

- **Minor species redistribution measurements by atom-probe:** As already introduced, the minor species redistribution, mainly the oxygen, which could have a detrimental effect on the junction leakage and requests our attention. Up to now, a new deposition type of TiN has demonstrated a clear improvement in terms of optical performances (current intensity in the darkness), but the real root causes of this phenomena remain misunderstood. Determination of light elements atomic concentration by EDX or TOF-SIMS is quite difficult, and, for this specific study, the Atomic Probe Tomography technic appears to be the most relevant.
Several objectives could then be detailed:

* Establish the impact of deposition type, CVD versus ALD, on oxygen concentration inside each layer and at the interface between them.

* Characterize the oxygen concentration inside the Si substrate (doped substrates).

* Verify the influence of metal thickness and surface preparation on oxygen redistribution.

- **Agglomeration phenomena:** As reported in [216], the agglomeration of C54-TiSi2 and C49-TiSi2 phases occurs very rapidly and potentially before 800 °C. In the real microelectronics devices, due to BEOL integration and reliability tests, the agglomeration temperature needs to be 100 °C higher than the highest thermal budget applied during the complete process flow. For imager technologies, this temperature is between 815 and 850 °C. **Current contact integrations are then sensitive to TiSi2 agglomeration,** and some additional studies are requested to try to delay this phenomenon. For this, the role of Pre-Amorphization by Implantation (PAI) will be studied. An antimony PAI which has been recently introduced at STMicroelectronics Crolles will be tried in that aim.

## V.4 Conclusive remarks

It is time to conclude this work, which allows me to write down on paper the main results of our research work since 2007. Today, of course, we have a better understanding of silicide formation in general, in mechanism involved at the interfaces during each step of phase sequence, and in the degradation, phenomena known in these thin film layers. This precise work paves the route to the development and the implementation of standard process flow of microelectronics devices of stable, robust, reliable, and low-resistive Silicide integrations (for both types, first and last).

Even though, as has been detailed in this chapter, some new challenges are ahead of us and request our attention in the next years.

At the end, such amazing work could not have been done without the very great involvement of all the teams in the different ST fabs (Agrate, Rousset, and Crolles) as characterization, reliability, and metrology groups, process integration, the academic laboratories support as well as the CEA-LETI one, and of course the financial funding of French government (ANR, CIFRE theses), and European Union (EU projects).
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