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Hardware Implementation of a UWB 802.15.4a Receiver

Hoang Tran Manh, Van-Phu Ha, Chi Hoang Phuong, Hieu Dang Quang, Minh Nguyen Duc

► To cite this version:

Hoang Tran Manh, Van-Phu Ha, Chi Hoang Phuong, Hieu Dang Quang, Minh Nguyen Duc. Hardware Implementation of a UWB 802.15.4a Receiver. Journal of Science and Technology Technical Universities, 2014, 104, pp.36-40. hal-04194193

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# Hardware Implementation of a UWB 802.15.4a Receiver

## Triển khai máy thu UWB theo chuẩn 802.15.4a

Tran Manh Hoang*, Ha Van Phu, Hoang Phuong Chi, Dang Quang Hieu, Nguyen Duc Minh

Hanoi University of Science and Technology, No.1 Dai Co Viet Str., Ha Noi, Viet Nam

Received: October 13, 2014; accepted: December 26, 2014

## Abstract

This paper describes a hardware implementation of UWB Receivers accordance with IEEE 802.15.4a standard. First, the whole UWB transceiver including channels and analog front-end is modeled in Simulink. Next, the digital receiver is implemented in Hardware Description Language. The system model is then used as verification environment to validate the behavior of the HDL receiver using co-simulation method. The HDL receiver works properly and use only small amount of hardware resource such that it can fit into small FPGA chip.

Keywords: UWB 802.15.4a, Energy detection, non-coherent, FPGA

## Tóm tắt

Bài báo này triển khai máy thu UWB theo chuẩn IEEE 802.15.4a bằng ngôn ngữ mô tả phần correct. Đầu tiên, máy phát bao gồm cả素质 truyền và các khối xử lý tín hiệu tương tự được mô hình trên Simulink. Tiếp theo, máy thu được triển khai bằng ngôn ngữ mô tả phần correct, cụ thể là ngôn ngữ Verilog. Dựa trên mô hình Simulink đã xây dựng, máy thu được thực nghiệm trên chip FPGA bằng phương pháp đồng mô phỏng. Máy thu UWB sử dụng số lượng nhỏ tài nguyên phần correct nên có thể tích hợp với các chip FPGA kích thước nhỏ.

## 1. Introduction

Ultra wide band (UWB) systems have attracted great attention in the last few years. And now it has become a strong candidate for short range wireless communication systems due to many of its attractive characteristics. It started to gain more attention in the early 1990s due to an invented impulse radio (IR) UWB device consuming only microwatts of battery power. Before this, it had been studied mainly for radar applications. UWB radio was approved for commercial use by FCC [1] in 2001. Then in 2007, the first UWB standard, IEEE 802.15.4a, was published by the IEEE [2]. Based on whether or not to use the information of channel state during detection, UWB receiver is divided into 2 categories: coherent receiver and non-coherent receiver. The choice of coherent or non-coherent architecture for UWB receiver depends on requirements and applications achieved by designers. With the desire to build a simple system, easy to implement on hardware, low price and low power consumption [3], we consider non-coherent receiver architecture.

Transmitted reference (TR) [4] and energy detection (ED) [5] are two popular classes of non-coherent receivers. TR receiver uses a reference pulse (spread by the channel) as a noisy template to detect the data-bearing pulse. This causes at least 3dB loss in performance and a delay line longer than channel delay spread is difficult to implement at sub-nanosecond

precision [6]. Meanwhile, ED receiver computes the signal energy, and detects the data symbol based on the energy presence of pulses in certain positions within a symbol period. Despite its inferior noise performance (because noise is also squared), energy detection is the most feasible receive structure as proposed in IEEE 802.15.4a standard.

In 2012 [7], A group of German researchers have implemented 802.15.4a UWB standard on ASIC on 250 nm SiGe technology, with the goal of building the system consumes less energy to drive the compact device use battery. In [10], the authors also implemented a UWB receiver in FPGA using a bank of distributed amplifiers (DAs) and ADCs. In the implementation, 8 banks with 500MSamples/s ADCs are used. This leads to complex DSP algorithm and FPGA implementation.

This paper concentrates on the implementation of the standard IEEE802.15.4a based on ED-UWB. In contrast to [10], the sampling rate of the ADC is low because of the *integrated and dump* analog front-end. This results in lower complexity in DSP algorithm and FPGA implementation. A prototype was implemented on FPGA development boards (Xilinx XC6SLX 45).

The rest of the paper is organized as follows. Section II and III briefly describe the UWB 802.15.4a standard and the receiver algorithms. The implementation details and analysis are given in section IV. The test procedure and measurement
results are presented in the section V. Finally, Section IV concludes the paper.

## 2. UWB 802.15.4a signals

According to 802.15.4a standard [2], the UWB signals are divided into frames, each of which consists of a synchronization header (SHR), a physical-layer header (PHR) and a data field (PSDU). The structure of the UWB signal frames is illustrated by Fig 1.

The synchronization header SHR contains a synchronization preamble (SYNC) and a frame delimiter (SFD). The SYNC preamble consists of 16, 64, 1024, and 4096 symbol $S_i$. The $S_i$ is created by spreading a certain perfectly balanced sequence $C_i = \{C_i(j)\}$ where $C_i(j)$ is a value in the set $\{-1, 0, 1\}; j = 0, 1, ..., K_{pbs}$ and $K_{pbs} = \{31,127\}$. The sequence $C_i$ is spread by inserting zeros between its elements $C_i(j)$. There are 24 preamble sequences $C_i$ being specified in the standard with the correlation property such that the receiver is easily able to detect the frame. The frame delimiter SFD is created by multiplying the sequence of 8 or 64 symbols $S_i$ with a code sequence. In Fig 1, the SFD is created by multiplying with the code sequence $[0 \text{ + } 1 \text{ 0} \text{ - } 1 \text{ + } 1 \text{ 0} \text{ 0} \text{ - } 1]$.

<figure><img src="image_3.png" /><figcaption>Fig 1. UWB signal frame structure</figcaption></figure>

<figure><img src="image_4.png" /><figcaption>Fig 2. UWB symbol structure</figcaption></figure>

<figure><img src="image_5.png" /><figcaption>Fig 3. Non-coherent ED UWB Receiver</figcaption></figure>

The PHR in UWB signal frames contains 19 bit information about the frame such as data rate, frame

length, as well as the error correction code for the PHR field itself.

Last, the PSDU consists of encoded and modulated user data. The Reed-Solomon block code and the convolutional code are used to encode the user data before it is modulated using BPM-BPSK modulation technique. In BPM-BPSK technique, two information bits are used to create a UWB symbol. Each UWB symbol is divided into $N_c$ possible chip positions, each with duration $T_c$. Moreover, each symbol is divided into two BPM intervals. Depending on the first information bit, a burst of $N_{cpb}$ pulses (chips) is located in the first or the second half of the BPM intervals. The second information bit decides the phase of the burst (either -1 or +1). Fig 2 illustrates the UWB symbol structure.

## 3. UWB receiver algorithms

For the IEEE 802.15.4a UWB transmission, the non-coherent ED receiver architecture is usually used because of its simplicity and low-power consumption. The receiver is illustrated in Fig 3. The signal from antenna is filtered by a band-pass filter to get desired frequency spectrum. It is then passed through square block and a low-pass filter. Next, it is sampled every 16ns by an Intergrated and Dump block. These four blocks are the analog-front end of the receiver. The baseband processor detects the UWB frames and decodes/demodulates them into the SHR, (SYNC, SFD), PHR and PSDU. It means that the baseband processor converts the digital signal from the analog frontend into the user data bits.

### 3.1. Synchronization algorithm

To extract the user data bits from the received UWB sampled signals, the synchronization task need to be done first.

Assuming receiver captures transmitted signal at time instant $t_0$, which may be anywhere in the signal frame (SYNC, PHR or PSDU), the synchronization objective is to locate the beginning of the first PHR. A practical synchronization algorithm for UWB IEEE 802.15.4a receivers was proposed in [8] which will be implemented in this work. The algorithm proposed in [8] consists of two steps as illustrated in Fig 4:

* ✓ Coarse synchronization: determine some time instant $t_1$ during the SYNC interval of received signal.

* ✓ Fine synchronization: from $t_1$, locate the start of first symbol $t_{PHR}$ in the PHR field.

In the following, we briefly describe the algorithm, readers can refer to [8] for detailed algorithm.
<figure><img src="image_6.png" /><figcaption>Fig 4. Synchronization algorithm [8]</figcaption></figure>

<figure><img src="image_7.png" /><figcaption>Fig 5. Fine synchronization purpose [8]</figcaption></figure>

<figure><img src="image_8.png" /><figcaption>Fig 6. Demodulation algorithm</figcaption></figure>

Assume that the received signal is sampled using integrated and dump with the period $T_s$. The number of SYNC symbols in the SHR is $N_{sync}$. The number of samples in one SYNC symbols is $L$. The perfectly balance sequence $C_i$ with the length $K_{pbs}$ is used in the SHR field.

In the coarse synchronization step, the received samples $y(nT_s)$ are divided into $L$-element segments $y_i = [y_{i0}, y_{i1}, \dots, y_{i(L-1)}]$. Then, segments are correlated with the template $S = [s_1, s_2, \dots, s_L]$ generated from $C_i$ by replicating $C_i(j) \ L/K_{pbs}$ times. The positions of the maximum element in the correlation results argmax$_i(y_i \oplus S)$ is found for each segment $y_i$. When $K$ ($K \le N_{sync}$) consecutive

segments $y_i$ with the same argmax$_i$ appear, we can claim that these $K$ segments are all in SYNC. Then the start of the $([K/2])$-th segment is considered as $t_1$.

In the fine synchronization step, the receiver firstly estimates the interval $\tau$ between $t_1$ and the beginning of the next symbol. Then, it determines the start time $t_{phr}$ of the PHR field.

In order to estimate $\tau$, the algorithm seeks the highest peak of the first pulse $q(t)$ of the next symbol to estimate $\tau_h$. Then, the starting of $q(t)$ is searched by finding the first occurrence of the $q(t)$. Knowing the starting position of the $q(t)$, we can calculate $\tau = \tau_h - \Delta$ as illustrated in Fig 5.

Finally, the start of the first PHR symbol $t_{phr}$ is determined based on the difference of the power between three parts of a UWB IEEE 802.15.4a frame. More specifically, the average power during the data field is always much greater than the SHR (approximately 3.75 times [8]). Based on this observation, paper [8] suggests an approach to detect the first PHR symbol as follows.

* Setting the threshold $\alpha = 1.1 * P_{sync}$ where $P_{sync}$ is the average power of symbol $N_\tau$,

* Comparing the average power of each $T_{psym}$-long segment one after another starting from $t_1 + \tau + T_{psym}$ with threshold $\alpha$; the threshold crossing indicates the start of the PHR field.

## 3.2. Demodulation algorithm

After synchronization step, the starting time of the PHR/PSDU fields is known. As the non-coherent receiver architecture will be used, only the position of pulse burst is used to demodulate the information bit.

The two sums $S_1, S_2$ of all signal samples in the burst for a certain user $H$ in two BPM intervals are calculated. If $S_1>S_2$ the information bit is 0 and if $S1<S2$, the information bit is 1. The demodulation algorithm is illustrated in Fig 6.

# 4. UWB Hardware Implementation

In this section, we describe the hardware implementation of the UWB receiver algorithms. Fig 7 shows the high-level block diagram of UWB receiver architecture that consists of six modules as follows:

1. SYN FSM: The finite stage machine controls operation of other modules.

2. SYN COUNTER: counts from 0 to 247 to identify one SYNC symbol or SFD symbol, counts from 0 to 63 to identify one PSDU symbol...
3. SYN_COARSE: The coarse synchronization module.

4. SYN_DATAPATH: The fine synchronization module.

5. MAC PHR_DECODER: Decode PHR data and check

6. DECODE_DATA: Decode information user data

The system has four input signals, and produces four output signals. The system operates at minimum frequency 62.5MHz, because sampling time is 16ns. In Fig 7Error! Reference source not found., data_in signal, 8bit, is input data after passed through analogue front-end block. in_start, in_rst, clk signal is enable system signal, reset signal, and clock signal, respectively. bit_out signal is data bit after decoding. Coarse_off signal signifies coarse synchronization process false to reset counter. Psdu_en signal signifies apparition of PSDU data. coarse_off signal signifies the operating status of the coarse synchronization.

<figure><img src="image_9.png" /><figcaption>Fig 7. UWB 802.15.4a receiver architecture</figcaption></figure>

<figure><img src="image_10.png" /><figcaption>Fig 8. The FSM of the controller</figcaption></figure>

In contrast to the algorithm developed in Matlab/Simulink where the data is processed as arrays, the implementation works in real-time with the streamed data input signals. It means that all modules in the receiver implementation work concurrently.

Therefore, the overall behavior of the receiver needs to be centrally controlled to ensure the synchronization between modules. The SYN FSM module which is the important part in the receiver will be further elaborated in the followings.

In implementation, we choose $K = 12$. Assuming that at $t_0$, the receiver starts receiving the input data. To respond with real time, the coarse synchronization block and synchronization receive data to calculate at $t_0$ and $t_0 + 6 * T_{psym}$, respectively. At the time $t_0$, the coarse synchronization receives 12 maximum consecutive elements with the same index, the fine synchronization continue to be made.

Conversely, if it does not receive 12 maximum consecutive elements with the same index, or in other word, the captured data at the time $t_0$ is not in SYNC part; it will generate a signal to reset system. When system is reset, the synchronization is executed from the beginning, at the time of the reset. The synchronization process is implemented as a FSM with 4 states, as illustrated in Fig 8

When the machine is turned on or reset, the current state of the system is returned to SYNC1 state. In this state, the system detects the start of symbol. When detecting the start of symbol is done, the FSM moves to the next state, SYNC2, at the same time sync2 signal is asserted. In SYNC2, the system detects the first symbol of PHR part by using energy detection algorithm. After detecting the symbol whose energy is more than a calculated threshold, data_start is asserted and the state machine transitions to DATA state. In this state, the system will generate the signal in order that the back functional blocks receive and decode data.

Finally, when data frames are received completely including sync data and the information user data, the system receive the next data frame. Due to the physical information is obtained in the first 19 bits of PHR data, or in other word, the length of SYNC data is determined, the system skip the SYNC and SFD of the next frames. This is done at JUMP state. At this state, the FSM goes to DATA state. At this state, the system will just jump back and forth between JUMP state and DATA state until PHR data is checked as false. In that case, the system needs to be re-synchronized (goes back to SYNC1 state).

## 5. Experimental results

We construct our testing environment as follows. The UWB receiver implementation in Hardware Description Language is embedded into the UWB transmission system consisting of a transmitter, a channel model, a receiver analog front-end and the receiver implementation. The system model is then used as verification environment to validate the
behavior of the HDL receiver using Hardware-in-the-loop (HIL) emulation method.

The proposed UWB receiver design was synthesized using the Xilinx ISE Design Suite tool (version 13.4); target device is Spartan6 XC6SLX45-3csg324. Table 1 shows the resource usage as well as the design speed of our FFT implementation

<table><caption>**Table 1.** UWB implementation hardware resource usage</caption><thead><tr><th>Logic Utilization</th><th>Used</th><th>Available</th><th>Utilization</th></tr></thead><tbody><tr><td>Slice Registers</td><td>5,680</td><td>54,576</td><td>10%</td></tr><tr><td>Slice LUTs</td><td>9,201</td><td>27,288</td><td>33%</td></tr><tr><td>Bonded IOBs</td><td>66</td><td>218</td><td>30%</td></tr><tr><td>Fmax (MHz)</td><td></td><td>86.781MHz</td><td></td></tr></tbody></table>

The implementation is loaded into the FPGA board and is executed together with the UWB transmission system in Simulink environment using HIL methodology. Fig 9 illustrates signal waveform of input/output the signals of the design.

## 6. Conclusion

We have successful implement the UWB 802.15.4a receiver. Thanks to the simple synchronization algorithm and the low sampling rate architecture, the receiver can be implemented in hardware and can be fitted into a small FPGA chip. The next step will be implemented the receiver as an ASIC.

<figure><img src="image_11.png" /><figcaption>**Fig 9.** UWB receiver's signal waveform</figcaption></figure>

## References

[1] "FCC notice of proposed rule making, revision of part 15 of the commission's rules regarding ultra-wideband transmission systems," Federal Communications Commission, Washington, D.C., Tech. Rep. ET-Docket 98-153, Apr. 2002.

[2] IEEE standard 802.15.4a-2007, Specific Requirement Part 15.4: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate

Wireless Personal Area Networks (WPANs), IEEE Standard 802.15.4a-2007 Task Group Std., 2007.

[3] K. Witrisal, G. Leus, G. Janssen, M. Pausini, F. Trösch, T. Zasowski, and J. Romme, "Noncoherent ultra-wideband systems," *Signal Processing Magazine, IEEE*, vol. 26, no. 4, pp. 48-66, 2009.

[4] R. Hoctor and H. Tomlinson, "Delay-hopped transmitted-reference RF communications," 2002, pp. 265-270.

[5] A. A. D'Amico, U. Mengali, and E. Arias-de Reyna, "Energy-detection uwb receivers with multiple energy measurements," *Wireless Communications, IEEE Transactions on*, vol. 6, no. 7, pp. 2652-2659, 2007.

[6] J. Romme and K. Witrisal, "Oversampled weighted autocorrelation receivers for transmitted-reference uwb systems," in *Vehicular Technology Conference, 2005. VTC 2005-Spring. 2005 IEEE 61st*, vol. 2. IEEE, 2005, pp. 1375-1380.

[7] S. Olonbayar, D. Kreiser, D. Martynenko, G. Fischer, O. Klymenko, and R. Kraemer, "Board implementation and its performance for ir-uwb ieee. 802.15. 4a from multiple asic chips," in *European Wireless, 2012. EW. 18th European Wireless Conference. VDE, 2012*, pp. 1-8.

[8] T. N. Duong, M. T. Hoang, M. H. Tran, and Q. H. Dang, "A practical synchronization algorithm for ieee 802.15.4a uwb receivers," in *Advanced Technologies for Communications (ATC), 2013 International Conference on*. IEEE, 2013, pp. 170-175.

[9] A. A. D'Amico, U. Mengali, and L. Taponecco, "Toa estimation with the ieee 802.15.4a standard," *Wireless Communications, IEEE Transactions on*, vol. 9, no. 7, pp. 2238-2247, 2010.

[10] Depeng Yang; Husheng Li; Peterson, G.D.; Fathy, A., "Compressed sensing based UWB receiver: Hardware compressing and FPGA reconstruction," Information Sciences and Systems, 2009. CISS 2009. 43rd Annual Conference on, vol., no., pp.198,201, 18-20 March 2009