# Optimized semi-physical EKV model for simulation of SiC MOSFETs

B.D.R. Bonkoungou, R. Gwoziecki, L. Sterna, Zoubir Khatir

► To cite this version:

B.D.R. Bonkoungou, R. Gwoziecki, L. Sterna, Zoubir Khatir. Optimized semi-physical EKV model for simulation of SiC MOSFETs. Microelectronics Reliability, 2025, 171, pp.115780. 10.1016/j.microrel.2025.115780. hal-05091778

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Distributed under a Creative Commons Attribution 4.0 International License
Research paper

Optimized semi-physical EKV model for simulation of SiC MOSFETs☆

B.D.R. Bonkoungou a,b,c,*, R. Gwoziecki a, G. Perez a, L. Sterna a, Z. Khatir b

ARTICLE INFO

Keywords:

SiC MOSFETs

EKV model

Power electronics

Static characteristic modeling

A B S T R A C T

This paper presents a detailed static characteristic model based on the EKV (Enz Krummenacher and Vittoz) model for 1200 V SiC MOSFETs in power electronic applications, with a specific focus on $I_{ds}(V_{gs})$ at different temperatures. The study explores the nuanced behavior parameters in the model and provides a subset of results in this publication. Additionally, the methodology of parameter fitting for the model is elaborated upon, providing insights into the process of refining the model to match real-world behaviors. To validate the steady state characteristics, this paper integrates MOSFET capacitance modeling, internal diode characteristics, and the influence of parasitic elements in the printed circuit board (PCB) for dynamic simulations and comparison with experimental tests conducted. Notably, the model incorporates the physical behavior of the device and can facilitate the integration of drift models for specific parameters, such as threshold voltage $V_{th}$, on state resistance $R_{ds,on}$. Additionally, with the integration of aging parameters models the current sharing in parallelized devices used in power electronics can be predicted through simulation with the EKV model. This integration can be crucial for establishing models for predictive maintenance of converters equipped with SiC MOSFETs.

1. Introduction

Power electronics is a field of electronics that deals with high-power systems and energy conversion. Energy conversion systems are constructed using semiconductor components such as transistors (MOSFETs, IGBTs, etc.), traditionally based on silicon (Si). However, recent developments have introduced the use of wide-bandgap materials, such as silicon carbide (SiC) and gallium nitride (GaN). These wide-bandgap materials offer significant advantages, allowing the manufacturing of more efficient energy converters with better performance compared to those based on silicon [1,2] Modeling the steady-state and switching characteristics of SiC MOSFETs is crucial for designing, simulating, analyzing, and optimizing electronic circuits, ensuring reliable and efficient performance in various applications.

Several MOSFET electrical models have been developed, taking into account the carrier density in the MOSFET channel. One notable model is the piecewise current model in [3,4], which describes MOSFET current based on operating regions (cutoff, linear and saturation region). It defines the I-V characteristics in each operating region of the MOSFET, considering the physical parameters of the component and modeling the

channel length modulation effect during operation. Using piecewise models necessitates the implementation of smoothing functions to ensure continuity of both first and second derivatives across the entire operating region. This continuity improves the convergence of simulations by reducing numerical instability and enhancing the accuracy of model approximations. Another model based on mobile charges in the channel is the Enz Krummenacher and Vittoz model (EKV model). Unlike piecewise models, this is a continuous equation that defines the MOSFET current in all operating regions, covering both weak and strong inversions. This model, developed in 1970, was notably used in low-power and low-voltage CMOS design, log-domain circuits, RF CMOS circuits, and ultra-low-power radios for wireless sensor networks [5]. In recent studies [6], the EKV model is applied to model SiC MOSFET components, but is not suitable for low values of voltage between gate and source ($V_{gs} < V_{th}$). Wolfspeed has also developed a model utilizing the EKV model [7]. However, this model exhibits discontinuous transfer characteristics curves, introducing simulation challenges due to potential convergence issues in device simulations. While TCAD models [8–10], provide deep physical insights into semiconductor behavior and are useful for process development, they are computationally intensive.

<footnote>a Univ. Grenoble Alpes, CEA, Leti, F-38000 Grenoble, France</footnote>

<footnote>b SATIE, Gustave Eiffel University, 25 allée des marronniers, F-78000 Versailles, France</footnote>

<footnote>c Paris-Saclay Univ., 3 rue Joliot Curie, F-91190 Gif-Sur-Yvette, France</footnote>

<footnote>* This article is part of a Special issue entitled: 'ESREF 2024' published in Microelectronics Reliability.</footnote>

<footnote>* Corresponding author at: Univ. Grenoble Alpes, CEA, Leti, F-38000 Grenoble, France.</footnote>

<footnote>E-mail address: benewende-diane.bonkoungou@cea.fr (B.D.R. Bonkoungou).</footnote>
In contrast, this EKV-based compact model (SPICE models) are optimized for efficient circuit-level simulations, striking a balance between accuracy and computational speed, making them particularly valuable for circuit design and optimization. Furthermore, the EKV model is based on empirical characterizations rather than detailed knowledge of the component's internal design. Without access to manufacturer design data, TCAD modeling is not feasible. The EKV model instead relies on characterization data, making it a generic, adaptable solution that can be calibrated for chips from multiple suppliers, thus providing versatility across different fabrication processes.

In this paper, the EKV model of planar commercial SiC is given by taking into account the physical parameters of the device and adding empirical parameters describing the behavior of the component. The proposed EKV model is generic and remains applicable to trench structures, as it is not based on specific knowledge of the device's physical structure. In the following sections, first, the developed I-V steady state models for SiC MOSFETs will be discussed. This will be followed by a detailed explanation of the methodology used for determining the model parameters. Next, the results of the curve fitting conducted to refine the models will be presented. Additionally, a body diode model, reverse recovery model and a capacitance model, which have been added for transient simulations, will be introduced. Finally, the dynamic characteristics of the developed model will be compared with experimental results for validation and to assess its accuracy.

## 2. Semi-physical EKV model for SiC MOSFETs

A model with eight parameters to be adjusted has been developed, considering the specific geometric characteristics of the device (see Eqs. (1) and (2)).

- The adjustment of the I-V steady state in the saturation region is carried out using the modulation of the channel length with $\lambda^*$ (see Eq. (3)).

- $\theta$ is used to represent the degradation of channel mobility with the increase in $V_{ds}$ voltage due to the induced electric field (see Eq. (4)).

- $\beta$ (see Eq. (5)) ensures that $I_{ds}$ remains almost negligible when the drain to source voltage is low. And $\alpha$ represents the adjustment parameter in the triode region.

- $\mu$ is the mobility of electrons in the channel. W is the channel width and L the channel length. Here these values are adjusted to have the aggregate value $K_{tot}$.

The addition of the drain to source resistance $R_{ds}$ in series with EKV MOSFET model improves the modeling for high $V_{gs}$ values (see Fig. 1). $R_{ds}$ representing the sum of resistance of source contact ($R_s$), resistance of channel region ($R_{ch}$), resistance of the vertical JFET gated by the grounded p base regions ($R_{JFET}$), the drift resistance ($R_{drift}$), the substrate resistance ($R_{sub}$).

<figure><img src="image_2.png" /><figcaption>Fig. 1. MOSFET forward current modeling with series resistance $R_{ds}$.</figcaption></figure>

$$I_{ds} = \lambda^{*} K_{tot}^{*} \left( \left[ \ln \left( 1 + \exp \left( \frac{V_{gs} - V_{th}}{\theta} \right) \right) \right]^{b} - \left[ \ln \left( 1 + \exp \left( \frac{V_{gs} - V_{th} - \beta}{\theta} \right) \right) \right]^{b} \right) \quad (1)$$

$$K_{tot} = \frac{w^* C_{ox}^* \mu}{L} \quad (2)$$

$$\lambda^* = (1 + (\lambda^* V_{ds}^*)) \quad (3)$$

$$\theta = (1 + \theta_G)^* (V_{gs} - V_{\theta_G}) \quad (4)$$

$$\beta = a^* V_{ds}^* \text{ with } V_{ds}^* = V_{ds} - R_{ds}^* I_{ds} \quad (5)$$

The EKV model equation offers the significant advantage of seamlessly interpolating between weak and strong inversion regimes. Additionally, it effectively captures the device characteristics during moderate inversion, providing a comprehensive framework for analyzing the behavior of MOSFETs across various operating conditions.

## 3. Curve fitting procedure

The curve fitting procedure is implemented using the Python programming language. An iterative algorithm based on the method of Genetic Algorithm (GA) and Nonlinear Least Squares (NLS) LevenbergMarquardt (LM)) is utilized for fitting. The NLS is recognized for its efficiency in local optimization, converging to a local optimum rapidly with appropriate initial values [11]. However, as it is not a global optimization algorithm, it tends to converge to a local optimum. Successful convergence relies significantly on the careful selection of initial values. Acknowledging the global optimization capability of the GA which relies on random values for fitting parameters [12], but also recognizing its challenge in converging to a local optimum, the combination of the GA and LM algorithms has been explored. The NLS method ensures fitting accuracy by minimizing the error between given data and the model relying on suitable initial parameters (see Eq. (6) to Eq. (8), where $\sigma$ represent the standard deviation and $\bar{y}$ the average of the measured values).

To address this, results from the genetic algorithm are employed as initial parameters for the least square method. This approach aims to enhance the efficiency of the optimization process and improve the overall convergence of the combined algorithm (see the protocol diagram in Fig. 2).

In the genetic algorithm, the parameters to be adjusted are: $\theta_G$, $K_{tot}$, $\lambda$, $V_{\theta_G}$, $a$, $b$, $R_{ds}$, $V_{th}$. Their lower and upper bounds allow the restriction of the solution space. The fitness function of the genetic algorithm evaluates the sum of squared differences between the model and drain-source currents extracted from measurements at different temperatures. When this sum of squared current differences falls below a predefined tolerance for the genetic algorithm $10^{-8}$, or when the maximum number of iterations (300) is reached, the optimized parameters are generated as output and passed to the least squares algorithm. The implementation of the least squares algorithm is done with 1000 iterations and a tolerance of $10^{-16}$.

$$\text{error} = \frac{\sum_{i=1}^{n} (\mathbf{y}_{\text{modeli}} - \mathbf{y}_{\text{datai}})}{\sigma} \quad (6)$$

$$\sigma = \sqrt{\frac{\sum_{i=1}^{n} (\mathbf{y}_{\text{datai}} - \bar{\mathbf{y}})}{n}} \quad (7)$$

$$\bar{\mathbf{y}} = \frac{\sum_{i=1}^{n} \mathbf{y}_i}{n} \quad (8)$$
<figure><img src="image_3.png" /><figcaption>Fig. 2. Fitting algorithm diagram</figcaption></figure>

## 4. Fitting results

The commercial STMicroelectronics TO-247 discrete device SCTW70N120G2V, with a 21 mΩ $R_{ds,on}$ and 1200 V breakdown voltage rating device is characterized using the B1505A, Keysight power device analyzer with the Kelvin method. This last method is indispensable as it avoids measurement errors due to significant voltage drops caused by the resistance of cables when a high current flows through them. The curve fitting is achieved with a correlation coefficient of approximately 0.98 for each $I_{ds}(V_{gs})$ curve as a function of $V_{ds}$ at various temperatures. This can be observed in Fig. 5 (linear scale) and Fig. 3 (semi-logarithmic scale) where the model is represented by a continuous line and the data by dotted lines. It is important to note that at each temperature, there are four curves corresponding to different values of $V_{ds}$ (0.5 V, 1 V, 1.5 V, and 2 V). The fitting for the four temperatures is carried out progressively from 25 °C to 150 °C. The parameters obtained at a given temperature are used to define the guess boundaries of the fitting for the next temperature. This approach ensures that the parameters retain physical meaning. For example, the threshold voltage $V_{th}$ should

decrease with temperature, and the drain resistance should increase with temperature.

Fig. 4 juxtaposes the $I_{ds}(V_{ds})$ curve derived from measurements with its model counterpart. The $I_{ds}(V_{ds})$ model curve is constructed using fitting parameters obtained from the $I_{ds}(V_{gs})$ curve. Notably, the model demonstrates excellent alignment with the measured data at 25 °C, 50 °C, 100 °C and 150 °C.

Table 1 provides the description, the unit and the values of the fitting parameters considered in the model.

During the fitting process at different temperatures, it is observed that three parameters $K_{tot}$, $\lambda$, $b$ remained constant, while the other namely $\theta_G$, $V_{0G}$, $a$, $R_{ds}$ and $V_{th}$ exhibited dependence on temperature. $V_{th}$, which is a negative temperature coefficient, decreases with increasing temperature, while $R_{ds}$ increases with temperature. Consequently, these parameters are modeled using a polynomial equation, where $a_0$, $a_1$, $a_2$, $a_3$ are adjustable parameters (see Eq. (9)).

$$p = a_0 + a_1 (T - 25) + a_2 (T - 25)^2 + a_3 (T - 25)^3 \quad (9)$$

## 5. MOSFET body diode model and reverse recovering

SiC MOSFETs have an intrinsic body diode that can be used as a freewheeling diode. This intrinsic body diode has a strong dependence on the gate-to-source voltage applied to the MOSFETs. It is important to model this body diode, as it affects turn-off losses when a negative $V_{gs}$ is applied. To ensure accuracy, the model should incorporate the diode's dependency on $V_{gs}$, given that the internal diode characteristics of SiC MOSFETs are highly dependent on $V_{gs}$, as noted in [13–15]. Diode characteristic modeling was performed at a single voltage level using a numerical approach to validate the EKV model under switching conditions. However, a dedicated diode model will be incorporated in future work. The numerical model given by (Eq. (10)) is used in this work, where $C_0$, $C_1$, $C_2$, $V_d$ are fitting parameters. As illustration, a fitting I-V curve is shown in Fig. 6 using $V_{gs} = -5V$. $V_{thd}$ is the threshold voltage of the body diode, modeled as a function of $V_{gs}$ (Eq. (11)), where $a_0$, $a_1$, $a_2$ are fitting parameters.

$$I_{sd} = e^{C_0} \cdot \left( \frac{e^{C_1 \cdot (abs(V_{sd}) - abs(V_{thd}))}}{max(1, (1 + C_2) \cdot abs(V_{sd} - V_d))} - 1 \right) \quad (10)$$

$$V_{thd} = a_0 \cdot V_{gs}^2 + a_1 \cdot V_{gs} + a_2 \quad (11)$$

The reverse recovery of the body diode (Fig. 7), due to its p-i-n structure, is a significant issue because it slows down switching speed and generates a high di/dt during turn-on, which raises reliability concerns. Therefore, accurately modeling the reverse recovery effect is essential. As per current research, the behavioral model of SiC power MOSFETs in [16], address this reverse recovery effect.

In this study, the MOSFET body diode reverse recovery current is modeled following methods from [16], which provide a straightforward

<figure><img src="image_4.png" /><figcaption>Fig. 3. $I_{ds}(V_{gs})$ measurement data alongside the corresponding fitting model at 25 °C, 50 °C, 100 °C and 150 °C in semi-logarithmic scale</figcaption></figure>
<figure><img src="image_5.png" /><figcaption>Fig. 4. $I_{ds}(V_{ds})$ measurement data alongside the corresponding fitting model at 25 °C, 50 °C, 100 °C and 150 °C. With Dt: Data and Md: Model</figcaption></figure>

<figure><img src="image_6.png" /><figcaption>Fig. 5. $I_{ds}(V_{gs})$ measurement data alongside the corresponding fitting model at 25 °C, 50 °C, 100 °C and 150 °C.</figcaption></figure>

<figure><img src="image_7.png" /><figcaption>Fig. 6. $I_{sd}(V_{sd})$ measurement data alongside the corresponding fitting model at 25 °C.</figcaption></figure>

diode model that incorporates reverse recovery. This approach includes the concept of a virtual node, $Q_m$, which is not a physical point in the structure but rather represents the total stored charge in the drift region. The injected charge $Q_e$ in this region is proportional to the body diode current $I_{sd}$, (as shown in Eq. (12)). The recombined charge, represented by $Q_e - Q_m$, links to the injection current $I_{inj}$ (Eq. (13)). Here $Q_m$ (Eqs. (13) and (14)) represents stored charge after recombination at each time step.

Two main parameters impact reverse recovery: the carrier lifetime, represented by $\tau$, and the total transit time, denoted $\tau_m$; they are defined in [16] by Eq. (15), where $\tau_{rr}$ is the reverse recovery time constant (see in Fig. 7). Including the body diode and reverse recovery effects in the model is necessary to maintain model convergence and efficiency.

<figure><img src="image_8.png" /><figcaption>Fig. 7. Reverse recovery current.</figcaption></figure>

<figure><img src="image_9.png" /><figcaption>Fig. 8. MOSFET parasitic capacitances and electrical symbol.</figcaption></figure>
<figure><img src="image_10.png" /><figcaption>Fig. 9. Capacitance $C_{gd} = C_{rss}$ and $C_{ds}$ model.</figcaption></figure>

<figure><img src="image_11.png" /><figcaption>Fig. 10. DPT PCB with DC link capacitors</figcaption></figure>

$$Q_e = \tau^* I_{sd} \qquad (12)$$

$$I_{inj} = (Q_e - Q_m)/\tau_m \qquad (13)$$

$$Q_e = \tau^* \left( I_{inj} - \frac{d}{dt} Q_m \right) \qquad (14)$$

$$\frac{1}{\tau_{rr}} = \frac{1}{\tau} + \frac{1}{\tau_m} \qquad (15)$$

## 6. Additional capacitance model

Due to their internal structure, MOSFETs exhibits parasitic capacitances (Fig. 8) that significantly influence its switching characteristics. The three key capacitances are $C_{iss}$, $C_{oss}$, and $C_{rss}$, all of which are nonlinear and vary with the drain-to-source voltage $V_{DS}$. These parameters are critical when analyzing gate driving behavior and evaluating switching performance.

The input capacitance, $C_{iss}$, represents the total capacitance seen from the gate terminal and is defined as: $C_{iss} = C_{gs} + C_{gd}$ (with $C_{gs}$ gate to source capacitor, $C_{gd}$ gate to drain capacitance). $C_{iss}$ must be

<figure><img src="image_12.png" /><figcaption>Fig. 11. DPT circuit with parasitic elements</figcaption></figure>

<figure><img src="image_13.png" /><figcaption>Fig. 12. PCB impedance simulation versus measurement result</figcaption></figure>

<figure><img src="image_14.png" /><figcaption>Fig. 13. Dynamic switching waveforms looking LS Off: Low Side Off and HS On: High Side On at $V_{ds} = 600V$ and $I_{sd} = 35A$, $T = 25$ °C.</figcaption></figure>
<figure><img src="image_15.png" /><figcaption>**Fig. 14.** Dynamic switching waveforms looking **LS-Off**: Low Side Off and **HS-On**: High Side On at **V<sub>ds</sub>** = **800V** and **I<sub>sd</sub>** = **45A**, T = 25 °C.</figcaption></figure>

<table><caption>**Table 1**
Parameters extracted</caption><thead><tr><td>Parameter</td><td>Value</td></tr></thead><tbody><tr><td>K<sub>tot</sub> (Aggregate value)</td><td>118,701 Fcm<sup>2</sup>/Vs</td></tr><tr><td>θ<sub>G</sub></td><td>0.39 V<sup>-1</sup></td></tr><tr><td>V<sub>th</sub></td><td>4.89 V</td></tr><tr><td>R<sub>ds</sub></td><td>1 mΩ</td></tr><tr><td>V<sub>θG</sub></td><td>1.86 V</td></tr><tr><td>λ</td><td>0.001</td></tr><tr><td>a</td><td>0.5</td></tr><tr><td>b</td><td>5</td></tr></tbody></table>

charged or discharged during switching, directly impacting gate driver requirements and switching speed. The output capacitance, $C_{oss}$, reflects the capacitive load at the drain and is given by: $C_{oss} = C_{ds} + C_{gd}$ ($C_{ds}$ drain to source capacitance). It plays a key role in determining voltage transients and energy dissipation during switching events. The reverse transfer capacitance, $C_{rss}$, also known as the Miller capacitance, is: $C_{rss} = C_{gd}$. A high $C_{rss}$ can delay the increase or decrease of the drain current even after a gate signal is applied or removed, thereby affecting switching speed. These capacitances depend on $V_{DS}$, especially, $C_{oss}$ typically decreases as $V_{DS}$ increases due to the widening of the depletion region, $C_{iss}$ and $C_{rss}$ also exhibit variations with $V_{DS}$, particularly at lower voltages, impacting gate charge and timing behavior. Understanding and modeling the variation of these capacitances with $V_{DS}$ is essential for accurate circuit simulation and efficient design.

Previous works have presented various empirical models of non linear capacitances in [17,18]. In this work, capacitance models have been specifically developed with a focus on $C_{gd}$ and $C_{ds}$. The behavioral model (see Eqs. (16) and (17)) is introduced to represent $C_{gd}$, where $C_{j1}$ and $C_{j2}$ denote junction capacitance, and $\alpha$ and $\beta$ serve as fitting parameters for the slopes of the two segments of the $C_{gd}$ (and, respectively, $C_{ds}$) curve. Additionally, $V_{dep1}$ represents the height separating the plateau of the capacitance curves.

$$ \text{If } V_{dg} = V_d - V_g \ge 0 $$

$$ C_{gd} = \frac{C_{j1}}{\sqrt{1 + V_{dg}^{\alpha} * \alpha_1}} * \left[ \frac{\tan^{-1}(\beta * (V_{dep1} - V_{dg})) + \frac{1}{2}}{\pi} \right] + \frac{C_{j2}}{\sqrt{1 + V_{dg}^{\alpha} * \alpha_2}} \quad (16) $$

$$ \text{If } V_{dg} = V_d - V_g < 0 $$

$$ C_{gd} = C_{j1} + C_{j2} \quad (17) $$

To refine the model, parameters such as $C_{j1}$, $C_{j2}$, $\alpha^i$, $\alpha''$, $\alpha_1$, $\alpha_2$, $V_{dep1}$ and $\beta$ undergo determination through fitting processes utilizing Genetic Algorithm and Nonlinear Least Squares. The obtained parameters yield a well-fitted model (illustration in Fig. 9) with a coefficient of determination approaching 99 %. $C_{ds}$ equation is similar to $C_{dg}$ with fitting process on $C_{ds}$ curve and $C_{gs}$ is considered as constant in this work.

## 7. Experiment result

A double pulse test [19,20] was performed experimentally, allowing the acquisition of dynamic waveforms that provide the switching characteristics of the MOSFET and its body diode current ($I_{sd}$). The experiments were carried out with the Low Side MOSFET switched off (LS_off) and the High Side MOSFET switched on (HS_on). In Fig. 10, it can be seen the PCB board implemented, in Fig. 11 the circuit, and the DPT parameters in Table 2. The DC link $C_{dc}$ capacitor is composed of three capacitors connected in parallel. To validate the EKV model, the DPT test circuit (see Fig. 11) was simulated using EKV model and capacitor model, which are necessary for dynamic simulation (as the MOSFET capacitors charge and discharge during operation). The parasitic inductances and capacitances of the printed circuit board (PCB) were extracted using Keysight PEPro [21] and incorporated into the simulation circuit. The Fig. 12 presents a comparison between the simulated and measured impedance. The results indicate that the impedance extracted from the simulator is in close agreement with the impedance measurements obtained from the PCB.

The extraction process with PEPro generates a complex block that encompasses the parasitic elements, which can be seamlessly integrated into the circuit for simulation purposes. Since the parasitic inductances of the MOSFET could not be modeled with ANSYS Q3D due to the lack of access to the wire bonding length inside the packaging, the package parasitic inductances were estimated and incorporated as self-inductances in the simulation circuit.

The simulations were conducted using Keysight Advanced Design System (ADS), allowing a comprehensive analysis of the circuit's performance, including the effects of the parasitic components, the EKV model, the reverse recovery behavior and capacitances dynamics.

In Fig. 13, the results of the switching characteristics at $V_{ds} = 600V$, $I_{sd} = 35A$, and $T = 25$ °C are shown. It can be observed that the oscillation frequency of $V_{ds}$ in the model matches the experimental results, as does the oscillation frequency of $I_{sd}$. The oscillation amplitudes are also quite similar. The gate turn-on waveforms of the high-side model and

<table><caption>**Table 2**
Parameter of DPT circuit</caption><thead><tr><td>Parameter</td><td>Value</td></tr></thead><tbody><tr><td>V<sub>gs,on</sub></td><td>18 V</td></tr><tr><td>V<sub>gs,off</sub></td><td>-5 V</td></tr><tr><td>R<sub>g,on</sub>=R<sub>g,off</sub></td><td>6,20hm</td></tr><tr><td>C<sub>dc</sub></td><td>20uF//20uF//2,5uF</td></tr><tr><td>L<sub>0</sub></td><td>236uH</td></tr></tbody></table>
the experimental results are closely aligned, although the model exhibits slightly more oscillation. This discrepancy can be explained by the overestimation of parasitic inductance in the gate or the assumption that $C_{gs}$ is constant in this study, whereas it should be $V_{gs}$ dependent, as discussed in this work [22].

Fig. 14 further validates the model developed in this study for $V_{ds} = 800$V, $I_{sd} = 45$A, and T = 25 °C. The oscillation frequency and amplitude are again quite similar, with higher oscillation observed during the low-side turn-off.

## 8. Conclusion

Based on physical considerations, an analytical model is developed in this work for a vertical 4H-SiC MOSFET to represent the current in the MOSFET's forward mode. The model's behavior trends align with measured data. In summary, the model shows promising correspondence with experimental data under certain conditions (such as temperature), this EKV model completed with diode, reverse recovery model and transient capability allow testing the device under different load conditions and switching frequencies at 25 °C. In this work, validation is conducted specifically at 25 °C. Currently, alignment with measurements at other temperatures is not achieved because the reverse recovery model has not yet been validated for temperature variations. Temperature dependence will be added to the reverse recovery model in future work to improve accuracy and allow for validation of switching waveforms at temperatures beyond 25 °C.

By including physical parameters, this EKV model sets the stage for building a drift model once the behavior of these parameters over time is understood. Studying how the device responds under different stresses will help predict how operating conditions impact the long-term performance and reliability of the SiC MOSFET. Furthermore, the model not only supports standalone device characteristics but also enables system-level simulation of parallelized architectures under realistic operating conditions.

## CRediT authorship contribution statement

B.D.R. Bonkoungou: Writing - review & editing. R. Gwoziecki: Review & editing. G. Perez: Review & editing. L. Sterna: Review & editing. Z. Khatir: Review & editing.

## Declaration of competing interest

This work is part of ARCHIMEDES, supported by the Chips Joint Undertaking and its members, including the top-up funding by National Authorities under Grant Agreement No 101112295. This work is also part of the IPCEI Microelectronics and Connectivity and was supported by the French Public Authorities within the frame of France 2030.

## Data availability

Certain data will be made available on request.

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