# Impact of the Recessed Gate Depth on the GaN MIS-HEMT Performances: New Insights on Mobility Extraction

Clémentine Piotrowicz, Blend Mohamad, Nathalie Malbert, Stéphane Becu, Simon Ruel, Cyrille Le Royer

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Clémentine Piotrowicz, Blend Mohamad, Nathalie Malbert, Stéphane Becu, Simon Ruel, et al. Impact of the Recessed Gate Depth on the GaN MIS-HEMT Performances: New Insights on Mobility Extraction. Journal of Applied Physics, 2024, 135 (17), pp.175701. 10.1063/5.0205840. cea-04667617

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# Impact of the recessed gate depth on the GaN metal-oxide-semiconductor high electron mobility transistor performances: New insights on mobility extraction

C. Piotrowicz ; B. Mohamad; N. Malbert; S. Bécu; S. Ruel; C. Le Royer

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# Impact of the recessed gate depth on the GaN metal-oxide-semiconductor high electron mobility transistor performances: New insights on mobility extraction

Cite as: J. Appl. Phys. **135**, 175701 (2024); doi: 10.1063/5.0205840

Submitted: 28 February 2024 · Accepted: 17 April 2024 ·

Published Online: 1 May 2024

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C. Piotrowicz,<fnref n="1" />,<fnref n="2" />,ᵃ) B. Mohamad,<fnref n="1" /> N. Malbert,<fnref n="2" /> S. Bécu,<fnref n="1" /> S. Ruel,<fnref n="1" /> and C. Le Royer<fnref n="1" />

## AFFILIATIONS

## ABSTRACT

This paper provides a comprehensive study of the impact of the gate recess depth (RD) on the GaN-on-Si MOS-HEMTs DC performances. $I_{DS}$ = f($V_{GS}$) and $I_{DS}$ = f($V_{DS}$) measurements are conducted at 25 and 150 °C, respectively, in forward and blocking modes. The gate recessed depth (50, 150, and 350 nm) is modulated by adjusting the plasma etching time, which is a critical step for improving the dielectric/GaN interface quality and the gate channel electron mobility. Three distinct regions can be defined separately: the bottom, the sidewall, and the corner region being the junction between the two previous regions. To assess the impact of gate recessed depth (RD) on the several mobilities around the gate cavity first, we applied our previous methodology allowing us to extract the bottom ($\mu_{bot}$) and the entire sidewall region mobility ($\mu_{T}$), without distinction from the corner. The mobility of the transverse region was found surprisingly to increase with deeper RD. To gain insight into the impact of the RD on this transverse section, a new extraction methodology is proposed to extract separately the gate corner ($\mu_{corner}$) and sidewall ($\mu_{SW}$) mobility. These extractions show that the corner mobility is found to be reduced compared to the sidewall one ($\mu_{corner} < \mu_{SW}$) evidencing the different weighting contributions over the transverse mobility. Moreover, these mobilities are found to be more degraded compared to the bottom one, highlighting the different contributions on the on-state resistance ($R_{ON}$). Indeed, the on-state resistance is lowered with the shallower RD due to the reduced sidewall resistance contribution (lower sidewall length) and despite the incremental contribution of the bottom resistance (larger effective gate length). However, the shallower RD shows an increase in the drain-source leakage current in reason of a lower gate electrostatic control. Technology Computer Aided Design (TCAD) simulations of the three RD morphologies are carried out to validate the experimental trends and the proposed methodology.

© 2024 Author(s). All article content, except where otherwise noted, is licensed under a Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/). https://doi.org/10.1063/5.0205840

## I. INTRODUCTION

In high-power applications, gallium nitride (GaN) is a promising technology for reaching high breakdown fields and high mobilities. Especially, the MOS channel HEMT with a fully recessed MOS gate architecture is an attractive solution among normally-off HEMTs for power conversion systems. MOS-HEMTs are proposed to overcome the limits of the temperature dependency of the resistance $R_{ON}$, typically observed on pGaN gate architectures, as well as improve the gate robustness.<fnref n="1" />,<fnref n="2" /> However, if GaN MOS-HEMTs

are developed to reach low on-state resistance while maintaining normally off-state and higher reliability,³ they still suffer from degraded channel mobility due to gate-etching and Oxide/GaN interface poor quality ($\mu \le 200 \text{ cm}^2 \text{ V}^{-1} \text{ s}^{-1}$).⁴⁻⁷ Indeed, theinductively coupled plasma-reactive ion etching (ICP-RIE) process, used to create the gate cavity, is known to induce surface damage such as dangling bonds, roughness, impurities, defects, and amorphization on the surface.⁸,⁹ To reduce the damages, a few additional steps of atomic layer etching (ALE) have proven their efficiency at the bottom of the gate.<fnref n="2" />,¹⁰ Its principle is as follows: a precursor

<footnote n="1">¹University Grenoble Alpes, CEA, LETI, F-38054 Grenoble, France</footnote>

<footnote n="2">²IMS Laboratory, University of Bordeaux, CNRS UMR 5218, F-33400 Talence, France</footnote>

<footnote>ᵃ) Author to whom correspondence should be addressed: clementine.piotrowicz@cea.fr</footnote>
reacts with surface atoms, then another reagent eliminates both surface atoms and precursors in another reaction, leading to small-step etching of the surface. This process provides better control and improved surface quality for GaN compared to ICP-RIE etching.

In this study, we compared three different RDs and their impacts on the MOS-HEMT DC performances. For this purpose, scanning transmission electron microscope (STEM), forward $I_D(V_G)$, and blocking $I_D(V_D)$ measurements are performed, as well as mobility extractions based on a new methodology. This methodology allows us to distinguish the contributions of the sidewall, corner, and bottom to the channel's resistance.¹⁰⁻¹³ Finally, TCAD simulations of the studied devices are compared to the experimental data, to validate the mobility extractions, giving additional insights into the gate morphology impact on the on-state performances.

## II. PROCESS AND DEVICE TECHNOLOGY

The recessed MOS-HEMT devices are fabricated on 200 mm Si substrates as illustrated in Fig. 1. First, transition layers are used to overcome the lattice and thermal mismatch between GaN and Si.¹⁴ Then, a carbon-doped GaN is added to prevent the vertical breakdown followed by an unintentionally doped (NID) GaN layer grown by metal organic chemical vapor deposition (MOCVD).¹⁵⁻¹⁷ On top of the GaN an AlGaN layer is deposited to form the heterojunction at the origin of the bi-dimensional electron gas (2DEG).¹⁸⁻²⁰ Finally, a MOCVD SiN is used as a passivation layer.²¹⁻²³ The recessed gate structure is fabricated by an AlGaN/GaN dry etching (ICP-RIE), followed by cycles of ALE.⁹,²⁴⁻²⁷ In this work, the recessed depth (RD) is modulated by adjusting the dry etching time leading to three different RDs: 50, 150, and 350 nm. After GaN surface conditioning by wet cleaning, gate stack formation is carried out with the deposition of Al₂O₃ as a dielectric layer by atomic layer deposition (ALD) and then the gate metal, as reported in Fig. 2. Finally, fully recessed Ti/Al ohmic contacts annealed at low temperatures are used for source/drain contacts.

<figure><img src="image_18.png" /><figcaption>FIG. 1. Schematics of the fabricated GaN-on-Si MOS-HEMTs with fully recessed gate.</figcaption></figure>

<figure><img src="image_19.png" /><figcaption>FIG. 2. Process flow with a focus on the gate etching and splits with 3RDs.</figcaption></figure>

The corresponding STEM images of the fabricated devices are shown in Fig. 3 for three different gate lengths ($L_G$): 0.25, 0.5, and 1 µm, corresponding to the mask opening. By comparing the RDs of 50–150 nm and 350 nm, we see differences in the bottom region. At 50 and 150 nm, the bottom cavity is rather horizontal independently of $L_G$, whereas at 350 nm specifically for large $L_G$ of 1 µm, a bowing effect appears.¹³,²⁴ In addition, by decreasing the $L_G$ dimension for the 350 nm case, a trench effect is observed: a change in the slope appears. This was reported in the literature and is likely due to the non-directional incident ions and the difficulty in accessing the deeper part of the cavity.²⁸ In Figs. 4 and 5, we report, respectively, the recess depth and sidewall angle as a function of the effective bottom gate length ($L_{G,eff}$) for the fabricated devices.

In Fig. 4, the RD and the effective bottom gate lengths ($L_{G,eff}$) are reported. These parameters of the devices are measured through eTilt SEM imaging and calibrate with the STEM images.¹² $L_{G,eff}$ is calculated according to the following equation:

$$L_{G,eff} = L_G - \frac{2 \cdot RD}{\tan(\theta)} \quad (1)$$

First, the measured RD corresponds to the expected values (50, 150, and 350 nm). Second, $L_{G,eff}$ is lower than $L_G$ value which is consistent with the fact that, the etching induces an angle of the sidewall. $L_{G,eff}$ is found to be smaller in the case of a deeper RD. Figure 5 illustrates this observation, by reporting the sidewall angle (SWA or $\theta$) variation vs $L_{G,eff}$ for the different RDs. Small variability between the measured devices is observed and the SWA is found to be steeper with smaller $L_G$.

## III. DEVICE ELECTRICAL CHARACTERISTICS

The devices are electrically characterized in forward and blocking modes to determine the effect of the RDs on the DC performances.

### A. Forward mode

$I_D(V_G)$ measurements are carried out in the forward mode varying the gate voltage ($V_G$) from 0 to 6 V at a drain voltage ($V_D$) of 0.5 V at 25 °C in Fig. 6(a) and 150 °C in Fig. 6(b). Regardless of $L_G$ and RD, no effect on the subthreshold regime (SS) and threshold voltage ($V_{TH}$) is observed, whereas $R_{ON}$ ($=V_D/I_D$) increases for
<figure><img src="image_20.png" /><figcaption>FIG. 3. TEMs images of splits varying the RD, respectively, 50, 150, and 350 nm and for three gate lengths: 0.25, 0.5, and 1 µm.</figcaption></figure>

the larger L~G~. A complex dependency between R~ON~ and RD at shal-
lower RD (50 and 150 nm) is reported. Where first for L~G~ of
0.25 µm and 0.5 µm the I~D~ values are higher in the case of the RD
of 50 nm, but that is no longer the case at L~G~ = 1 µm where the

improved I<sub>D</sub> value is obtained for the RD of 150 nm. However, a
substantial signature is observed at the 350 nm RD. This effect can
be related to differences on the bottom mobility and effective gate
length defined by the RD. Similar trends are observed at 150 °C.

<figure><img src="image_21.png" /><figcaption>FIG. 4. Recess depth (RD) as a function of the effective bottom gate length for the three etching conditions (dimensions based on STEM images).</figcaption></figure>

<figure><img src="image_22.png" /><figcaption>FIG. 5. L_{G,eff} as a function of the sidewall angle (SWA) for the three recessed depths measured on several devices.</figcaption></figure>
<figure><img src="image_23.png" /><figcaption>FIG. 6. Drain current vs gate voltage $I_D(V_G)$, for the three gate lengths (in log/lin scale); (a) at 25 °C and (b) at 150 °C.</figcaption></figure>

## B. Blocking mode

Drain ($I_D$), source ($I_S$), and gate ($I_G$) leakage currents are also shown in Fig. 7 during the blocking mode for all the RDs at $L_G$ of 0.5 µm. Measurements are carried out by varying the drain voltage ($V_D$) from 0 to 800 V at a gate voltage of $V_G = -4$ V. At 25 °C [Fig. 7(a)], no differentiable effect on the leakage currents is observed between the splits due to the very low values above the resolution limits. At 150 °C [Fig. 7(b)], for a deeper RD, the effective gate surface increases leading to a larger $I_G$. On the contrary, the lateral current leakage $I_S$ decreases due to better electrostatic control of the gate in a deeper area and the presence of the gate. These differences among the RDs are observed starting at $V_D = 200$ V. However, the limiting mechanism of $I_D$ at $V_D = 800$ V, not represented here is the leakage due to the bulk, whose degradation factor in temperature ($I_B$, 150 °C/$I_B$, 25 °C) is about 10.

# IV. MOBILITY EXTRACTION

## A. General methodology

In order to evaluate the impact of RD on the previous forward characteristics and gain insight on the dependency between $R_{ON}$, RD and effective gate length, a new extraction methodology is proposed.

As represented in Fig. 8, the MIS-HEMT resistance contributions are reported and the total resistance ($R_{ON}$) can be defined as

$$R_{ON} = 2R_{C} + R_{2DEG,S} + R_{2DEG,D} + R_{channel} \quad (2)$$

where $R_C$, $R_{2DEG,S}$, $R_{2DEG,D}$, and $R_{channel}$ are, respectively, the contact, the 2DEG, and the channel resistance. $R_C$ is determined by transmission line measurements (TLM) and is about 0.25 and 0.3 Ω mm, respectively, at 25 and 150 °C which represents the minor contribution to the total on-state resistance. $R_{2DEG}$ is measured on gated Van der Pauw test structure and the corresponding electron mobility is extracted using the Split-CV methodology.²⁹ The $R_{2DEG}$ values are found around 360 and 880 Ω/□, respectively, at 25 and 150 °C, and the associated mobility is around 2140 and 870 cm² V⁻¹ s⁻¹. The degradation factor ($R_{2DEG}$, 150 °C/$R_{2DEG}$, 25 °C) of 2.2 is related directly to the degradation of the mobility.

A methodology utilizing linear interpolations is suggested for assessing the impact of channel resistance ($R_{channel}$) on $R_{ON}$. More precisely, the objective is to differentiate the mobility degradation on the bottom and transverse regions of the gate cavity. The extractions are performed on several devices, for each one taking into account of its specific dimensions in terms of $L_{G,eff}$. Figure 9
<figure><img src="image_24.png" /><figcaption>FIG. 7. Measured drain (I_D), gate (I_G), and source (I_S) leakage currents at 25 °C/150 °C in the blocking mode (L_G = 0.5 µm) for the 3 RD values (median).</figcaption></figure>

illustrates this methodology. First, our previous methodology,¹⁰ recalled in Fig. 9(a), is applied, in order to determine the bottom mobility (μ<sub>bot</sub>) and the transverse mobilities (μ<sub>T</sub>). For that, R<sub>channel</sub> is plotted as a function of L<sub>G,eff</sub> for several V<sub>G</sub> values from 1 V to 6 V, according to Eq. (3). Here, two R<sub>channel</sub>(L<sub>G,eff</sub>) were considered: one using devices (specifically dedicated for such extractions) with large L<sub>G</sub> (10–60 μm) giving more accuracy on the bottom extractions due to the negligible effect of the access; another one using the devices with smaller L<sub>G</sub> (0.5–1 μm) to be more accurate on the effect of the access regions. Then, from the slope, the sheet bottom resistance (r<sub>bot</sub>) is extracted. The transverse resistance (R<sub>T</sub>) is determined at the condition L<sub>G,eff</sub> = 0 and depend on the transversal length (L<sub>T</sub>).

$$R_{\text{channel}}(V_G) = R_T(V_G) + R_{\text{bottom}}(L_{G,\text{eff}}, V_G). \quad (3)$$

The bottom and transverse mobilities are calculated using electron density (N<sub>S</sub>) from the capacitance measurements and the previous extractions of R<sub>T</sub> and R<sub>bottom</sub>.

<figure><img src="image_25.png" /><figcaption>FIG. 8. Schematic of the overall resistance contributions on the on-state resistance.</figcaption></figure>

Second, the new model presented in Fig. 9(b) and in Eq. (4), will be applied to estimate the degradation on the corner and sidewall regions, to give additional insight into the process degradation around the gate cavity,

$$R_{\text{channel}}(V_G) = R_{\text{SW}}(V_G) + R_{\text{corner}}(V_G) + R_{\text{bottom}}(V_G). \quad (4)$$

This method required several sidewall length variations (L<sub>SW</sub>), accessible through the RD splits (50, 150, and 350 nm). The

<figure><img src="image_26.png" /><figcaption>FIG. 9. General mobility extraction methodology to extract the three mobilities μ<sub>bot</sub> (Fig. 13), μ<sub>SW</sub> (Fig. 17), and μ<sub>corner</sub> (Fig. 17), based on (a) the previous model from,¹⁰ (b) the proposed new model.</figcaption></figure>
previous R_T is plotted as a function of LSW. The slope is related to the sidewall resistance (Rsw) and the intercept is related to the corner resistance (Rcorner). Finally, μsw and μcorner will be determined.

## B. Extraction of the bottom mobility (μbot)

To neglect the undesired effects of the morphology such as bowing effect, appearance of double slope on the sidewall of the gate cavity, transistors with large L<sub>G,eff</sub> from 10 μm to 60 μm are considered and characterized by I<sub>D</sub>(V<sub>G</sub>) measurements for the 3 RDs at 25° C and 150 °C from which R<sub>ON</sub> can be calculated [R<sub>ON</sub>(V<sub>G</sub>) = V<sub>D</sub>/I<sub>D</sub>(V<sub>G</sub>)]. R<sub>channel</sub> is then obtained from Eq. (2) by removing the access resistance form the total resistance [R<sub>ON</sub>(V<sub>G</sub>) - (R<sub>C</sub> + R<sub>2DEG</sub>,<sub>S</sub> + R<sub>2DEG,D</sub>)]. The corresponding R<sub>channel</sub>(V<sub>G</sub>) is then plotted vs the L<sub>G,eff</sub> for various V<sub>G</sub> values from 1 to 6 V as reported in Fig. 10.

The sheet bottom resistance [r<sub>□,bot</sub>(V<sub>G</sub>)] is extracted from the slope of the R<sub>channel</sub>(L<sub>G,bot</sub>) characteristic as shown in Fig. 11, as a function of V<sub>G</sub>. In addition, an inset of this resistance at V<sub>G</sub> = 6 V is reported showing a clear evidence of a degradation of the sheet bottom resistance for the deeper RD (350 nm) while an optimum condition is found for 150 nm RD regardless of the V<sub>G</sub> value.

Finally, μ<sub>bot</sub> is determined from the previous r<sub>□,bot</sub>(V<sub>G</sub>) characteristics as a function of the electron density (N<sub>S</sub>) according to Eq. (5), that is,

$$ \mu_{\text{bot}} = \frac{1}{q \cdot N_S \cdot R_{\text{channel}}}, \qquad (5) $$

where q is the electron charge. N<sub>S</sub> is considered uniform around the gate channel (cavity) and is extracted by capacitance measurements C(V<sub>G</sub>) for the three RDs at 25 and 150 °C as reported in Fig. 12. C (V<sub>G</sub>) characteristics are reported at both temperatures and no change is observed for the 3RDs in terms of electron density.

In Fig. 13 we report the extracted bottom mobility (μ<sub>bot</sub>) as a function of N<sub>S</sub>, obtained from Eq. (5), at both 25 and 150 °C. For

<figure><img src="image_27.png" /><figcaption>FIG. 10. Channel resistance (median) as a function of the bottom length for RD = 50 nm at 25 °C/150 °C for V<sub>G</sub> = 1–6 V (with a 0.5 V step).</figcaption></figure>

<figure><img src="image_28.png" /><figcaption>FIG. 11. Extraction of the sheet bottom channel resistance r<sub>□,bot</sub>(V<sub>G</sub>) for the 3RDs at 25 °C/150 °C, insert: zoom on the r<sub>□,bot</sub> values at 6 V for the two temperatures and the 3 RDs.</figcaption></figure>

the shallow RDs (50/150 nm), the bottom mobility are found improved compared to the deepest one (350 nm) at both temperatures. This degradation can be related to either the proximity of the GaN:C layer enhancing the roughness mechanism, either to the degraded GaN bulk quality in deeper regions or the exposition etching time which is longer for the 350 nm RD. By comparing the μ<sub>bot</sub> results at 25 and 150 °C, it comes out that the temperature dependence (T°) is small (<15%) for all the RDs. This slight variation with temperature can be explained by the effect of defects and not to the phonons.

## C. Extraction of the transversal mobility (μT)

Based on previous work,<sup>10</sup> μ<sub>T</sub>(V<sub>G</sub>) is calculated at 25 and 150 °C from the intercept of the R<sub>channel</sub>(L<sub>G,bot</sub>) characteristics at

<figure><img src="image_29.png" /><figcaption>FIG. 12. C(V<sub>G</sub>) measurements performed on large devices at a frequency of 10 kHz.</figcaption></figure>
<figure><img src="image_30.png" /><figcaption>FIG. 13. Bottom channel mobility as a function of the electron density $\mu_{bot}(N_S)$ for the 3 RDs at 25 °C/150 °C.</figcaption></figure>

$L_{G,bot} = 0$ for the overall RDs, according to Eq. (6), as reported as a function of $N_S$ in Fig. 14,

$$ \mu_T(V_G) = \frac{1}{q \cdot N_S(V_G) \cdot R_T(V_G)} \quad (6) $$

For this purpose and in order to have a more precise extraction of $\mu_T$, devices with smaller $L_G$ (0.5, 1, and 2µm) are considered contrary to the previous bottom mobility extraction (Fig. 10). Interestingly, we find that $\mu_T$ increases with deeper RD at both temperatures. Indeed, a value of 22, 81, and 93 cm² V⁻¹ s⁻¹ at 25 °C and 26, 59, 77 cm² V⁻¹ s⁻¹ at 150 °C is obtained at $V_G = 6$ V or equivalently $N_S \approx 8 \times 10^{12}$ cm⁻², respectively, for 50, 150, and 350 nm RD. The small temperature dependency of $\mu_T$ (≈20%) is expected and is similar to the one found for $\mu_{bot}$ for all the RDs.

<figure><img src="image_31.png" /><figcaption>FIG. 14. Extraction of the transversal mobility ($\mu_T$) as a function of the electron density $N_S$ at 25 °C and 150 °C [from the intercept of the $R_{channel}$ ($L_{G,eff}$)].</figcaption></figure>

<figure><img src="image_32.png" /><figcaption>FIG. 15. Transversal resistance ($R_T$) (median) as a function of the sidewall lengths ($L_{sw}$) taken from the STEM images for the 3RDs) at 25 °C/150 °C for $V_G = 1–6$ V (with 0.5 V step).</figcaption></figure>

$\mu_{bot}$ is found to be higher than $\mu_T$, likely due to the anisotropic ALE etching, and to the photolithography process, which induced more defects on the sidewall independently of the RD.

To explain the observed trend on $\mu_T$, the only plausible assumption is to consider a non-uniform mobility along the trench cavity, specifically a difference between the sidewall and corner region. Indeed by assuming a much more degraded mobility in the corner region compared to the sidewall one, a more important weighting contribution of the corner region over the total transversal length ($L_T = L_{sw} + L_{corner}$) for shallower RD¹¹ could explain the observed mobility degradation. Indeed, during dry etching, due to the non-vertical trenches, degradation mechanisms in the corner regions are reported, supposedly due to energetic ions deflected from the sidewall surface to the corners.²⁸

<figure><img src="image_33.png" /><figcaption>FIG. 16. Extraction from the slope and the intercept of the $R_T(L_{sw})$ at 25 °C/ 150 °C of (in Fig. 15); Left) the sheet sidewall channel resistance $r_{\square,sw}$ as a function of $V_G$; and Right) corner resistance ($R_{corner}$), as a function of $V_G$.</figcaption></figure>
<figure><img src="image_34.png" /><figcaption>FIG. 17. Extracted mobility contributions for the sidewall (μsw) and corner (μcorner) vs the electron density Ns at 25 °C/150 °C, for Lcorner = 10 nm.</figcaption></figure>

<figure><img src="image_35.png" /><figcaption>FIG. 19. Comparison of the extracted mobilities μT (measurements) to the calculated μT,cal from the values (at VG = 6 V) of μsw and μcorner (Figs. 14 and 18).</figcaption></figure>

D. The mobility contributions around the gate: Decorrelation of the sidewall and corner mobility

In Fig. 15, the earlier extracted transversal resistance [R<sub>T</sub>(V<sub>G</sub>)] is reported as a function of the gate sidewall length (L<sub>SW</sub>), obtained from the STEM images (Fig. 3), respectively, at 25 and 150 °C. The linear relationship between these two parameters, regardless of V<sub>G</sub> and temperature, proves that the sidewall and corner mobility are identical between the different recess depths. μ<sub>corner</sub>(V<sub>G</sub>) and μ<sub>SW</sub>(V<sub>G</sub>) are then calculated from the corresponding sheet sidewall resistance [r<sub>□,SW</sub>(V<sub>G</sub>)] and corner resistance [R<sub>corner</sub>(V<sub>G</sub>)]. r<sub>□,SW</sub>(V<sub>G</sub>) and R<sub>corner</sub>(V<sub>G</sub>) are extracted, respectively, from the slope and intercept of R<sub>T</sub>(V<sub>G</sub>, L<sub>SW</sub>) characteristics at 25 and 150 °C, as reported in Fig. 16.

<figure><img src="image_36.png" /><figcaption>FIG. 18. Sensibility of L<sub>corner</sub> on μ<sub>SW</sub> and μ<sub>corner</sub>.</figcaption></figure>

Similarly to the bottom mobility, μ<sub>SW</sub> and μ<sub>corner</sub> are evaluated using Eqs. (6) and (7) that are, respectively,

$$ \mu_{SW} = \frac{1}{q \cdot N_s \cdot r_{\square,SW}}, \qquad (7) $$

$$ \mu_{\text{corner}} = \frac{L_{\text{corner}}}{q \cdot N_s \cdot R_{\text{corner}}}, \qquad (8) $$

where L<sub>corner</sub> is the corner length estimated from the STEM images (≈10 nm in Fig. 3). μ<sub>SW</sub> and μ<sub>corner</sub> are shown as a function of Ns at 25 and 150 °C in Fig. 17. μ<sub>corner</sub> is found to be degraded compared to μ<sub>SW</sub> at both temperatures. At high temperatures and Ns = 8.2 × 10<sup>12</sup> cm<sup>-2</sup>, both μ<sub>SW</sub> and μ<sub>corner</sub> are degraded by ~15% and 60%, respectively.

<figure><img src="image_37.png" /><figcaption>FIG. 20. TCAD simulated structures (RD, L<sub>G,eff</sub>, and SWA) according to STEM images (Fig. 3) and representation of the mobility regions (bottom, sidewall, and corner) and electron density.</figcaption></figure>
<figure><img src="image_38.png" /><figcaption>FIG. 21. Simulated $I_D(V_G)$ for the 3RDs for $L_G = 0.5 \mu m$, and comparison with the experimental data (median) at 25 °C and 150 °C.</figcaption></figure>

As illustrated in Fig. 18, the extraction of $\mu_{corner}$ and $\mu_{SW}$ is reported at $V_G = 6$ V as a function of $L_{corner}$. Indeed, the extracted mobility values are impacted by the uncertainty around the $L_{corner}$ value. Specifically $\mu_{corner}$ is found to be highly affected and increases with larger $L_{corner}$. On the contrary, $\mu_{SW}$ is found to be nearly constant, and therefore its extraction is unaffected by this uncertainty. A 20 nm corner length seems maximum considering the previous TEM image (Fig. 3) and Fig. 18, while values around 10 nm look more relevant for extraction. Finally, we can describe these mobilities with the transverse mobility, by considering their simple resistance dependency ($R_T = R_{SW} + R_{corner}$), that leads to the following expression:

$$ \mu_{T,cal} = \frac{(L_{corner} + L_{SW}) \times (\mu_{corner} \times \mu_{SW})}{(L_{SW} \times \mu_{corner}) + (L_{corner} \times \mu_{SW})} \quad (9) $$

In Fig. 19, the calculated $\mu_{T,cal}$ values [Eq. (9)], using the extraction of the $\mu_{SW}$ and $\mu_{corner}$, are compared to the ones extracted experimentally with the previous methodology. The value of $\mu_{T,cal}$ is found to follow a similar trend that of $\mu_T$ which

confirmed the importance of the corner in the interpretation of the degradation mechanism around the gate cavity.

## V. TCAD SIMULATIONS

Finally, TCAD simulations are carried out in order to validate the mobility extractions and to confirm the consequent experimental trend on the DC performances. The simulated gate morphologies for the three RD values for a $L_G$ of 0.5 $\mu m$ are reproduced to account for the experimental STEM observations using the sprocess module of Synopsys, and are illustrated in Fig. 20. Electrical simulations were performed with Synopsys S-Device module. The spontaneous and piezoelectric polarization into the AlGaN, AlN and GaN are taking into account by considering two interface polarization charges at the AlGaN/AlN and AlN/GaN interfaces. To validate the mobility extractions at 25 and 150 °C (Figs. 13 and 17), their values have been directly used as input for the $I_D(V_G)$ simulations. No dependency with temperature and saturation velocity is considered since these experimental values (used as input in TCAD) already take these effects into account. The mobility values at $V_G = 6$ V allows to predict and validate the extraction and the experimental trend observed specifically at strong inversion. In Fig. 21, simulations (dashed lines) are compared to the experimental $I_D(V_G)$ measurements (solid lines) for the three RDs. The results show that the $I_D(V_G)$ curves are well reproduced and close to the experimental data at both temperatures.

We have also mentioned, the effect of the RD on the leakage currents during the blocking mode (Fig. 7), specifically the rise of the lateral leakage current ($I_S$) with shallower RD. This can be explained by the different distributions of the electrostatic potential around the gate cavity between the different RDs. The simulated electrostatic potential distributions at $V_G = -4$ V and $V_D = 650$ V, are reported in Fig. 22 for the three RDs. The electrostatic potential of the gate cavity extends to the deeper GaN-NID region for larger recess depths. Moreover the presence itself of an enlarged gate cavity prevents from the rising of the lateral leakage current. However, the increase of sidewall length and the appearance of a sharper angle with deeper RD, leading to an increase of local electric field, increases the gate leakage current. However, the sharper

<figure><img src="image_39.png" /><figcaption>FIG. 22. Simulated electrostatic potential distribution around the recessed gate of the device, at $V_G = -4$ V, and $V_D = 650$ V.</figcaption></figure>
<figure><img src="image_40.png" /><figcaption>FIG. 23. Determination of the five contributions of the R<sub>ON</sub> (2.R<sub>C</sub> + R<sub>2DEG</sub> + R<sub>bottom</sub> + 2.R<sub>SW</sub> + 2.R<sub>corner</sub>) for a L<sub>G</sub> of 0.5 µm, based on extracted resistances (Figs. 10, 14, and 15) and effective lengths (L<sub>corner</sub>, L<sub>SW</sub>, L<sub>G,bot</sub>).</figcaption></figure>

angle and surface damage inside the trenches would lead to greater
gate leakage current.

VI. R<sub>ON</sub> OPTIMIZATION

In Fig. 23, the R<sub>ON</sub> partitioning [Eqs. (2) and (4)] is summa-
zized for the three RDs at 25 and 150 °C for a L<sub>G</sub> of 0.5 µm. R<sub>ON</sub> is
found to be lowered with shallower RDs due to a reduced R<sub>SW</sub> con-
tribution attributed to a shorter L<sub>SW</sub> and despite the rising contri-
bution of R<sub>bottom</sub> in reason of a larger L<sub>G,eff</sub>. The dependency
between R<sub>ON</sub> and RD is not simply a geometrical relationship (L<sub>SW</sub>,
L<sub>G,eff</sub>), but require to account for the experimental differences in
terms of mobility around the cavity. Indeed, the R<sub>ON</sub> difference

<figure><img src="image_41.png" /><figcaption>FIG. 24. R<sub>ON</sub> at 6 V vs I<sub>S</sub> and I<sub>G</sub> leakage current values at 150 °C, extracted at V<sub>D</sub> = 650 V.</figcaption></figure>

between RDs is explained by a reduction of the sidewall resistance for shorter RDs, which is purely geometrical (L<sub>SW</sub>) since μ<sub>SW</sub> and μ<sub>corner</sub> are assumed independent of the RD, and above a nonlinear contribution of the R<sub>bottom</sub>. The improved μ<sub>bottom</sub> is found for the RD of 150 nm. Concerning the temperature dependency, the R<sub>channel</sub> is weakly impacted (increase by a factor 1.2) due to the low degradation observed in the electron mobility compared to the access resistance (R<sub>2DEG</sub>) where a factor above 2 is reported. As reported, in Fig. 24, by considering both results in forward (R<sub>ON</sub>) and in blocking mode (I<sub>G</sub>, I<sub>S</sub>) and comparing the three RDs for a given L<sub>G</sub> of 0.5 μm, an optimum is found at 150 nm recess depth. Indeed, the RD of 150 nm shows comparable R<sub>ON</sub> and I<sub>G</sub> with the 50 nm RD and the comparable I<sub>S</sub> with 350 nm RD.

VII. CONCLUSIONS

In this study, we evaluated the DC performances of the
MOS-HEMT in terms of R<sub>ON</sub>, channel mobility, and leakage cur-
rents (blocking mode), for three RDs values: 50, 150, and 350 nm,
at 25 and 150 °C. We report that R<sub>ON</sub> is the result of different resis-
tance contributions: R<sub>2DEG</sub> and R<sub>C</sub> corresponding to the acces
regions and which are independent of the etching process and
R<sub>channel</sub> which is strongly impacted. To estimate the effect of the
RD and determine the regions around the gate cavity subject to the
highest mobility degradation, a methodology based on STEM
images, I<sub>D</sub>(V<sub>G</sub>), and C(V<sub>G</sub>) measurements has been proposed. A
stronger degradation for the transverse region of the gate compared
to the bottom (μ<sub>T</sub> < μ<sub>bot</sub>), as well as a dependence with RD of the
transverse mobility are demonstrated. μ<sub>T</sub> is found more degraded
for the shallowest RD. To take account of this observation, the
assumption of a weighting contribution of μ<sub>corner</sub> with respect to
μ<sub>SW</sub> (μ<sub>corner</sub> < μ<sub>SW</sub>) was introduced and validated by TCAD I<sub>D</sub>(V<sub>G</sub>)
simulations. Finally, R<sub>ON</sub> is improved for shallower RDs (50 and
150 nm) due to a reduced impact of R<sub>SW</sub> (lower L<sub>SW</sub>), and despite
the larger contribution of R<sub>bottom</sub> (increase in L<sub>G,eff</sub> and μ<sub>bot</sub>, 50 nm-
<μ<sub>bot</sub>, 150 nm), emphasizing the importance of considering all gate
regions (sidewall, corner, and bottom) for the R<sub>ON</sub> optimization.
To conclude, with regard to blocking characteristics at 150 °C,
improved electrostatic control of the gate (lower I<sub>S</sub> leakage) is
reported for the deeper RD, highlighting an optimum in terms of
R<sub>ON</sub>/I<sub>S</sub> for the 150 nm RD value.

ACKNOWLEDGMENTS

This work was funded by the PSPC French national program
“G-Mobility.”

AUTHOR DECLARATIONS

Conflict of Interest

The authors have no conflicts to disclose.

Author Contributions

C. Piotrowicz: Formal analysis (equal); Investigation (equal); Methodology (equal); Visualization (equal); Writing – original draft (equal); Writing – review & editing (equal). B. Mohamad: Methodology (equal); Supervision (equal); Writing – review &
editing (equal). **N. Malbert:** Methodology (supporting); Supervision (equal); Writing – review & editing (equal). **S. Bécu:** Methodology (supporting); Writing – review & editing (supporting). **S. Ruel:** Investigation (supporting). **C. Le Royer:** Methodology (supporting); Supervision (equal); Writing – review & editing (equal).

DATA AVAILABILITY

The data that support the findings of this study are available
from the corresponding author upon reasonable request.

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