# Monolithic integration of GaAs p-i-n photodetectors grown on 300 mm silicon wafers

H. Mehdi, M. Martin, S. David, J. Hartmann, J. Moeyaert, M. Touraton, C.

Jany, L. Virot, J. da Fonseca, J. Coignus, et al.

► To cite this version:

H. Mehdi, M. Martin, S. David, J. Hartmann, J. Moeyaert, et al. Monolithic integration of GaAs p-i-n photodetectors grown on 300 mm silicon wafers. AIP Advances, 2020, 10 (12), pp.125204. 10.1063/5.0030677. hal-03867652

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# Monolithic integration of GaAs p-i-n photodetectors grown on 300 mm silicon wafers

H. Mehdi Ⓔ ; M. Martin; S. David; J. M. Hartmann; J. Moeyaert; M. L. Touraton; C. Jany; L. Virot Ⓔ ;
J. Da Fonseca; J. Coignus Ⓔ ; D. Blachier; T. Baron ✉

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AIP Advances 10, 125204 (2020)

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# Monolithic integration of GaAs p-i-n photodetectors grown on 300 mm silicon wafers

Cite as: AIP Advances 10, 125204 (2020); doi: 10.1063/5.0030677

Submitted: 24 September 2020 • Accepted: 10 November 2020 •

Published Online: 1 December 2020

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H. Mehdi,<fnref n="1" /> ID M. Martin,<fnref n="1" /> S. David,<fnref n="1" /> J. M. Hartmann,<fnref n="2" /> J. Moeyaert,<fnref n="1" /> M. L. Touraton,<fnref n="1" />,<fnref n="2" />,<fnref n="3" /> C. Jany,<fnref n="2" /> L. Virot,<fnref n="2" /> ID

J. Da Fonseca,<fnref n="2" /> J. Coignus,<fnref n="2" /> ID D. Blachier,<fnref n="2" /> and T. Baron<fnref n="1" />,¹a ID

## AFFILIATIONS

## ABSTRACT

Vertical GaAs p-i-n photodetectors epitaxially grown on GaAs(001), Ge/Si(001), and Si(001) substrates are reported. The performances of such photodetectors were investigated as a function of threading dislocation density in the stacks. A low dark current at room temperature, below 100 pA up to -9 V for all photodetectors, was evidenced. The absorption coefficients of GaAs were extracted from the spectral response of those p-i-n structures between 400 nm and 1100 nm. A responsivity of 0.17 A/W at 850 nm was obtained for a GaAs p-i-n structure grown directly on Si as compared to the value of 0.23 A/W obtained for the GaAs substrate. Such responsivity shows that III-V integration on Si is an efficient way of fabricating high performance optical sensors with low cost large scale productivity.

© 2020 Author(s). All article content, except where otherwise noted, is licensed under a Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/). https://doi.org/10.1063/5.0030677

## I. INTRODUCTION

Monolithic integration of III-V semiconductors on Si has been explored by many research groups in the last few decades. This approach offers the opportunity of fabricating high performance devices such as high speed and low power transistors,<fnref n="1" /> lasers,<fnref n="2" /> and photodetectors<fnref n="3" /> using silicon high volume manufacturing infrastructures. III-V photodetectors have been widely studied since their intrinsic electrical and optical properties make them good candidates for a broad range of applications.⁴⁻⁶

GaAs p-i-n photodetectors have been of interest for high performance computing and data center applications, where large data rates are needed, thanks to their high bandwidth⁷ and sensitivity. These photodetectors have been used for high-speed receivers in vertical cavity surface emitting laser-based optical links⁸ and for photon counting x-ray spectroscopy during space missions, as GaAs offers more resistance to radiation damage than silicon.⁹ From the material and epitaxy point of view, using a GaAs layer as the active material for photodetection is advantageous over more complex structures such as quantum dots (QDs) or multiple quantum wells (MQW) since the latter require well controlled thickness and shape to maximize their performances.

However, GaAs p-i-n photodetectors integrated on Si combine the superior optoelectronic properties of GaAs (e.g., high mobility, direct band gap, and high absorption coefficient) with the low cost and high volume manufacturing of Si integrated circuit technology. The high cost of GaAs substrates and their limited size compared to silicon are the main reasons limiting the use of GaAs photodetectors. Besides, the direct epitaxial growth of GaAs on standard 300 mm microelectronic Si substrates typically results in the formation of anti-phase domains (APD) and high threading dislocation densities (TDDs), which reduce the carrier velocity and photon conversion efficiency. Various approaches have been investigated¹⁰⁻¹² to minimize or avoid such discrepancies. Kume et al.¹³ used selectively grown Ge islands on the Si substrate to integrate GaAs p-i-n photodiodes with Si CMOS-based transimpedance amplifiers (TIA). Kim et al.¹⁴ used wafer bonding and epitaxial lift-off techniques to fabricate GaAs p-i-n photodetector arrays on Si.

In the current work, we have elaborated ultra-thin (total thickness < 1 µm) GaAs p-i-n photodetector structures on (i) GaAs 4 in. wafers and (ii) 300 mm Si(100) substrates with or without a Ge buffer to evaluate the potential of the monolithic approach. Dark current, responsivity, and absorption coefficients were measured, extracted, and benchmarked. Low dark current levels of a

<footnote n="1">¹Univ. Grenoble Alpes, CNRS, CEA/LETI-Minatec, Grenoble INP, LTM, 38000 Grenoble, France</footnote>

<footnote n="2">²University Grenoble Alpes, CEA, LETI, Minatec Campus, F-38054 Grenoble Cedex, France</footnote>

<footnote n="3">³STMicroelectronics, 850 Rue Jean Monnet, F-38926 Crolles Cedex, France</footnote>

<footnote>a) Author to whom correspondence should be addressed: thierry.baron@cea.fr</footnote>
few pA were obtained even for lattice-mismatched structures, with quantum efficiencies in line with literature data. Our results show the potentiality of the monolithic approach to fabricate efficient photodetectors at a large scale with a thin GaAs film.

## II. DEVICE FABRICATION

GaAs p-i-n junctions were epitaxially grown on the GaAs(100) substrate (sample S1), 300 mm Si(001) substrate (sample S2), and 300 mm Si(100) substrate covered with a Ge buffer layer (sample S3). The Ge buffer was grown in a separate group IV epitaxy tool by chemical vapor deposition at 90 Torr with GeH₄ as a precursor. A low temperature (400 °C)/high temperature (600 °C) approach followed by a short cyclic anneal under H₂ (between 650 °C and 850 °C) was used to obtain a smooth, high quality 1.6 µm thick buffer. The misfit dislocations stemming from the 4.1% lattice mismatch between GaAs and Si were confined in the Ge buffer (which had almost the same lattice parameter than GaAs). For samples S2 and S3, an in situ Siconi™ treatment was performed to remove oxides from the Si and Ge surfaces prior to introduction in the III-V metalorganic chemical vapor deposition (MOCVD) reactor. The GaAs p-i-n junctions were free of anti-phase domains.¹⁵⁻¹⁷ The use of three different wafers allows us to vary the TDD between 10⁴ cm⁻² and 10⁹ cm⁻². In the MOCVD growth chamber, ultra-pure H₂ was used as the carrier gas and trimethylgallium (TMGa), tertiarybutylarsine (TBAs), trimethylindium (TMIn), and tertiary-butylphosphine (TBP) as the precursors for Ga, As, In, and P, respectively. The n-type doped GaAs layer was grown in two steps: a 30 nm thick nucleation layer was deposited at low temperature (LT, 350 °C-450 °C) followed by the growth of 400 nm of GaAs at high temperature (HT, 600 °C-700 °C).¹⁷ Disilane was used as the n-type dopant. The 1 µmol/min Si flow resulted in a 2 × 10¹⁸ cm⁻³ n-type doping of GaAs. Afterward, absorber layers made of 550 nm of intrinsic GaAs were grown at 620 °C. The residual doping of those i-GaAs layers was n-type and around 10¹⁶ cm⁻³. Finally, 50 nm of p-type doped GaAs were grown at the same temperature using Diethylzinc (DEZn) as the p-type dopant source. The concentration of the Zn-doped p-GaAs layer was 1 × 10¹⁹ cm⁻³, resulting in good, close to ohmic metal/semiconductor contacts. Eventually, a 38 nm thick InGaP etch stop layer lattice matched with GaAs can be inserted on S1 and S2 samples to facilitate the processing of the n-type contact. Figure 1 shows the cross section schematics of the top illuminated p-i-n GaAs structures on the different substrates with a round mesa diameter of 14 µm.

Thin lamellae are prepared with a FIB-STEM tool (Helios Nanolab 450S from FEI). First, a protective platinum (Pt) layer is deposited at the sample surface using in situ gas injection systems (GIS) with electron and ion beams. The lamellae are thinned to ~100 nm using the ion beam with a range of voltages between 2 kV and 30 kV, different beam currents in the range of 0.021 nA-2.5 nA, and several sample tilts. A low voltage of 2 kV and low current of 21 pA are applied at the last step to reduce the amorphous layer on both sides of the lamella. Then, the structural properties are characterized in the cross section by scanning transmission electron microscopy (STEM) based on a field emission-gun (FEG) electron source across these thin lamellae. STEM images are directly realized under the scanning electron microscope (SEM) column at 30 keV to get the spatial resolution in the range of 1 nm. All layer observations

are taken in the [110] zone axis. The electron channeling contrast image is taken using the scanning electron microscope (Zeiss Merlin) using a backscattering electron detector (EBSD) system. The ECCI was operated at an acceleration voltage of 30 kV and a probe current of 2 nA at a working distance of 5 mm.

## III. RESULTS AND DISCUSSIONS

### A. Threading dislocation quantifications

Cross-sectional STEM for S2 and S3 samples can be found in Figs. 2(a) and 2(b), respectively. As seen in Fig. 2(b), for the S3 sample, the GaAs p-i-n stack is, at the TEM scale, free from defects, thanks to the presence of the high quality Ge buffer. Meanwhile, a high density of misfit and threading dislocations (TDs) is present at the n-GaAs/Si interface in the S2 sample. These TDs propagate into the active region of the p-i-n structure, as shown in Fig. 2(a). In order to observe directly the TDs close to the surface, we have used electron channeling contrast imaging (ECCI) in a scanning electron microscope (SEM Zeiss Merlin).¹⁸ ECCIs for S2 and S3 samples are shown in Figs. 2(c) and 2(d), respectively. Typically, dark/bright spots reveal the presence of TDs, while lines are characteristics of stacking faults. The extracted TDDs for S1, S2, and S3 samples are 3.7 × 10⁴ cm⁻², 2.0 × 10⁹ cm⁻², and 3.3 × 10⁷ cm⁻², respectively. The presence of the Ge buffer has reduced the TDD by two orders of magnitude compared to the direct growth on Si.

### B. Device performance

Room temperature conventional static current-voltage (I-V) measurements under dark and top illumination conditions were performed to quantify the impact of the TDDs. Figure 3 shows the I-V characteristics of all devices (S1, S2, and S3) for photodetectors with a diameter of 14 µm. All devices exhibit a low leakage current between 0.7 pA and 3.5 pA at a reverse bias of 2 V. These values correspond to leakage current densities of 0.45 µA/cm² and 2.27 µA/cm², respectively. These leakage currents are lower than those reported for p-i-n germanium photodetectors with similar responsivity.¹⁹ They are also definitely lower than the one obtained for high-speed GaAs p-i-n photodiodes for 50 Gb/s optical fiber links.²⁰

<figure><img src="image_10.png" /><figcaption>FIG. 1. Cross section schematic of vertical p-i-n GaAs photodetectors processed on different substrates.</figcaption></figure>
<figure><img src="image_11.png" /><figcaption>Plan view</figcaption></figure>

<figure><img src="image_12.png" /><figcaption>FIG. 2. Cross-sectional STEM image of the GaAs p-i-n structure grown on (a) the Si substrate (S2 sample) and (b) Ge/Si (S3 sample). [(c) and (d)] corresponding ECCIs.</figcaption></figure>

Despite the higher TDD in the S2 device, the leakage current did not increase dramatically. It was of the same order of magnitude than the one obtained on the GaAs substrate (S1 device). This is an interesting and promising result for III-V/Si integration technologies and especially photodetection. Such I-V characteristics were unexpected for S2 and S3 devices. We, indeed, thought that high TDDs would result in significantly higher leakage currents.21,22 However, a similar I-V characteristic was observed for In0.2Ga0.8As photodetectors23 with comparable TDD values (around 2.5 × 10⁷ cm⁻²). This relatively low dark current density is likely due to a predominance of the carrier diffusion over the Shockley Read Hall (SRH) phenomenon, which makes the dark current less sensitive to TDD. However, in our case, the dark current has a clear voltage dependence, so this explanation could not be applied.

<figure><img src="image_13.png" /><figcaption>FIG. 3. Dark currents of S1, S2, and S3 devices with mesa diameters of 14 µm.</figcaption></figure>

In order to investigate the leakage current mechanisms, the representative temperature-dependent current-voltage (I-V) characteristics for the S2 device over a wide temperature range of 25 °C-125 °C are performed, as shown in Fig. 4(a). The reverse currents increase gradually with the reverse voltage and the temperature. At a given reverse bias, the slope of the plot of $I_n$ (I<sub>R</sub>) vs 1/(k<sub>B</sub>T) yields the thermal activation energy E<sub>a</sub>. As shown in Fig. 4(c), at a low reverse bias of -0.1 V, the E<sub>a</sub> value is close to E<sub>g</sub>/2 ~ 0.703 eV [value determined from the photoluminescence measurement (not shown here)], indicating that the generation-recombination process was the dominant conduction mechanism. However, by increasing the reverse bias voltage, the E<sub>a</sub> value decreases to a value of 0.42 eV at -9 V, which is much less than E<sub>g</sub>/2 and clearly affected by the reverse bias. Both Schottky and Pool-Frenkel (PF) conduction mechanisms can contribute to the leakage current to induce the lowering of the E<sub>a</sub> value by increasing the applied electric field.

When the reverse leakage current is dominated by the PF or Schottky conduction mechanism, it can be given by Eqs. (1) and (2), respectively,

$$I_R \propto E \cdot \exp\left(\frac{q}{kT} \sqrt{\frac{qE}{\pi\epsilon}}\right), \quad \beta_{PF} = \left(\frac{q^3}{\pi\epsilon}\right)^{1/2}, \quad (1)$$

$$I_R \propto T^2 \cdot \exp\left(\frac{q}{2kT} \sqrt{\frac{qE}{\pi\epsilon}}\right), \quad \beta_{Sc} = \frac{1}{2} \left(\frac{q^3}{\pi\epsilon}\right)^{1/2}, \quad (2)$$

where ε, E, β<sub>PF</sub>, and β<sub>Sc</sub> are the permittivity of GaAs, the maximum electric field in the p-i-n GaAs junction, and the Poole-Frenkel and Schottky coefficients of GaAs, respectively. The electric field E is estimated as $E = (V_{bi} - V)/W$, where V<sub>bi</sub> is the built-in voltage of the
<figure><img src="image_14.png" /><figcaption>FIG. 4. (a) Temperature-dependent current–voltage (T–I–V) characteristic of the S2 device. (b) Arrhenius plot of the reverse leakage current measured at different reverse bias vs 1/k<sub>B</sub>T. (c) Thermal activation energy E<sub>a</sub> extracted from the Arrhenius plot.</figcaption></figure>

S2 device, which has a value of 1.407 eV, V is the applied voltage, and W is the depletion width of 0.52 µm.

Figures 5(a) and 5(b) show, respectively, the plot of Ln (I<sub>R</sub>/E) and Ln (I<sub>R</sub>/T<sup>2</sup>) vs E<sup>1/2</sup> in the 25°C–125°C temperature range. The linear fit of the data in Figs. 5(a) and 5(b) yields the values

of β<sub>PF</sub> and β<sub>sc</sub>, respectively. The experimental β<sub>PF</sub> value is 3.89 × 10<sup>-4</sup> eV V<sup>1/2</sup> cm<sup>1/2</sup> (1.86 × 10<sup>-4</sup> eV V<sup>1/2</sup> cm<sup>1/2</sup>) at 25°C (125°C). These values are very close to the theoretical one of 2.11 × 10<sup>-4</sup> (eV V<sup>1/2</sup> cm<sup>1/2</sup>), while the experimental β<sub>sc</sub> value is 1.12 × 10<sup>-3</sup> eV V<sup>1/2</sup> cm<sup>1/2</sup> (8.83 × 10<sup>-4</sup> eV V<sup>1/2</sup> cm<sup>1/2</sup>) at 25°C

<figure><img src="image_15.png" /><figcaption>FIG. 5. Plot of (a) Ln (I<sub>R</sub>/E) and (b) Ln (I<sub>R</sub>/T<sup>2</sup>) vs E<sup>1/2</sup> for a range of temperatures of 25°C–125°C for the S2 device.</figcaption></figure>
<figure><img src="image_16.png" /><figcaption>FIG. 6. Absorption coefficient α extracted from the measured responsivity at -2 V reverse bias vs photon wavelength λ.</figcaption></figure>

(125 °C), which are much higher than the theoretical value of 1.06 × 10⁻⁴ eV V¹/² cm¹/². This makes the Pool-Frenkel the dominant conduction mechanism governing the reverse current for a high reverse bias. This is in consistent with the high value of TDD in the S2 device that can act as a deep defect center affected by the Poole-Frenkel effect.

The photodetectors' responsivities in the 400 nm–1100 nm wavelength range have been then measured at –2 V. The absorption coefficient (α) of GaAs can be extracted from the measured responsivity (R<sub>meas.</sub>), thanks to the following equation:

$$R_{\text{meas.}} = (1 - r)(1 - e^{-\alpha \cdot t_i}) \cdot R_{\text{max}} \cdot e^{-\alpha \cdot t_p}, \quad (3)$$

where R<sub>max</sub> is the maximum responsivity corresponding to ideal collection and absorption of carriers depending on the photon wavelength λ, t<sub>i</sub> and t<sub>p</sub> are the thickness of the undoped and p-type doped top GaAs layers, respectively, and r is the light reflectance at the air/p-GaAs interface (assumed to be 0.32 in our case). e<sup>-α·t<sub>p</sub></sup> and 1 - e<sup>-α·t<sub>i</sub></sup> are the photon attenuation by the p-type doped GaAs layer and photon absorption in the bulk of the i-GaAs absorber, respectively.

Figure 6 shows the absorption coefficients α extracted using Eq. (3) from spectral responsivities recorded at –2 V vs wavelength for all devices. For the S1 device, a pronounced noise is observed because of technological issues during the diode process leading to a discontinuity between the p-metal ring on the active region and the p-pad. This was not the case for S2 and S3 devices. It shows that the absorption edge around 880 nm does not shift between the photodetectors. Below the band gap of epitaxial GaAs (λ > 855 nm), α starts to decrease before reaching zero between 900 nm and 1100 nm for all

photodetectors. α otherwise monotonously decreases with the wavelength below 670 nm. This is due to high photon absorption near the surface, where the photo-generated carriers are recombined before being collected. Hence, they do not contribute to the photocurrent.²⁴ This can be avoided by using an AlGaInP window layer on top of the photodetector followed by a very thin p-type GaAs layer to ensure electrical contact.²⁵ It is clear that the TDD reduction stemming from the use of a Ge buffer in S3 devices enhanced the value of α compared to S2 devices. Table I summarizes the TDD value, the dark current, the dark current density, and the responsivity at 850 nm for devices biased at –2 V. For S2 devices, the quantum efficiency is 20%–31% for wavelengths in the 700 nm–850 nm range, corresponding to the responsivities of 0.17 A/W and 0.15 A/W. These values are better by a factor of 2.5 than the one obtained for a GaAs p-i-n photodetector integrated on Si using wafer bonding and an epitaxial lift-off technique.¹⁴ It is important to note that our current GaAs p-i-n photodetectors have a small GaAs absorber layer thickness (~0.52 µm) with a potential short transit time for photo-generated carriers, resulting in high speeds of operation. The frequency response of the devices will be reported elsewhere. To further improve the quantum efficiency of the photodiode, an antireflection coating could also be added.

## IV. CONCLUSION

We have fabricated ultra-thin GaAs p-i-n photodetectors on GaAs(001), Ge/Si(001), and Si(001) substrates. A low dark current at room temperature, below 100 pA up to –9 V, was obtained for all the photodetectors. A responsivity of 0.17 A/W at 700 nm wavelength was achieved for GaAs p-i-n photodetectors grown directly on 300 nm Si substrates, with high absorption efficiency between 600 nm and 855 nm. Those photodiodes are expected to achieve high-speed operation and could be of interest for applications ranging from sensing to optical communications. We believe that the integration of III-V stacks on silicon, thanks to direct hetero-epitaxy, could result in the fabrication of high performance optoelectronic devices such as photodetectors or EAM (Electro-Absorption Modulator) at a low cost and large scale, pushing further the boundaries of silicon photonics.

## ACKNOWLEDGMENTS

This work was partially supported by the French “Recherches Technologiques de Base” (Basis Technologies Research), RENATECH programs, and the French National Research Agency in the framework of the Investissements d'Avenir program (Grant Nos. ANR-10-IRT-05 and ANR-15-IDEX-02). The authors want to thank

<table><caption>TABLE I. Threading dislocation density (TDD), dark current, dark current density, and responsivity at 850 nm for S1, S2, and S3 devices biased at –2 V.</caption><thead><tr><th></th><th>TDD (cm<sup>-2</sup>)</th><th>Dark current (pA) at -2 V</th><th>Dark current density (µA/cm<sup>2</sup>) at -2 V</th><th>Responsivity (A/W) at -2 V at 850 nm</th></tr></thead><tbody><tr><td>S1</td><td>3.7 × 10<sup>4</sup></td><td>1.3</td><td>0.84</td><td>0.23</td></tr><tr><td>S2</td><td>2.0 × 10<sup>9</sup></td><td>3.5</td><td>2.27</td><td>0.15</td></tr><tr><td>S3</td><td>3.3 × 10<sup>7</sup></td><td>0.7</td><td>0.45</td><td>0.17</td></tr></tbody></table>
the CEA Leti clean staff, the Nanocharacterization Platform (PFNC), and Applied Materials for technical assistance on the MOCVD tool and fruitful discussions.

DATA AVAILABILITY

The data that support the findings of this study are available within this article.

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