# Towards Direct-Control Data Acquisition by Nano-Probing Non-Volatile Memory Cells

Shawn Mckay, Nathan Hutchins, Steven Baskerville, Sujeet Shenoi

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Shawn Mckay, Nathan Hutchins, Steven Baskerville, Sujeet Shenoi. Towards Direct-Control Data Acquisition by Nano-Probing Non-Volatile Memory Cells. 19th IFIP International Conference on Digital Forensics (DigitalForensics), Jan 2023, Arlington, VA, United States. pp.91-122, 10.1007/978-3-031-42991-0_6. hal-05517483

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# Towards Direct-Control Data Acquisition by Nano-Probing Non-Volatile Memory Cells

Shawn McKay¹, Nathan Hutchins¹, Steven Baskerville², and Sujeet Shenoi¹

¹ University of Tulsa, Tulsa, Oklahoma, USA

sujeet@utulsa.edu

² U.S. Secret Service National Computer Forensics Institute Laboratory, Tulsa, Oklahoma, USA

**Abstract.** This chapter describes a data acquisition method for non-volatile memory that directly interfaces with the floating-gate transistors on a silicon die using nano-probes under a scanning electron microscope. The method involves chip preparation, memory cell reverse engineering, contact point identification and disinterring, following which nano-probes are positioned on control points on the die that are attached to the address, bit and ground lines associated with an individual memory cell. After the connections are established, a highly-sensitive sourcemeter applies voltage in a sweeping pattern to the address lines to enable current to flow between the bit and ground lines. The sourcemeter measures the minuscule current flow in the floating-gate transistor of the targeted memory cell to determine if it stores a zero or one. The research literature does not describe a data acquisition method that actively probes individual memory cells to read data.

Extensive experiments on ATmega328P microcontrollers demonstrate that the chip preparation, memory cell reverse engineering and contact point identification steps are successful. However, after the contact point disinterring step, it was difficult to verify that the contact points were fully exposed and free from contamination and damage. Indeed, the difficulty establishing consistent electrical connections between the nano-probe tips and address, bit and ground lines yielded non-ideal results. Nevertheless, the direct-control data acquisition method for non-volatile memory and the accompanying workflow that customizes a direct-control data acquisition method to a specific microcontroller or memory chip are technically sound.

**Keywords:** Non-Volatile Memory · Silicon Dies · Floating-Gate Transistors · Bit-Level Data Acquisition

## 1 Introduction

Evidence from electronic devices can be recovered non-invasively when the devices are functional and tools are available for data recovery. However, more invasive techniques are required when devices are damaged and non-repairable and/or tools are not available. In these scenarios, the device circuit boards are
exposed and reverse engineered to identify communications ports such as Uni-
versal Asynchronous Receiver-Transmitter (UART), Serial Peripheral Interface
(SPI) [10] and Joint Test Action Group (JTAG) [14, 15, 17]. Following this, com-
mercial or custom data manipulation/debugging tools [13, 15] are used to inter-
act with the communications ports to extract data from microcontrollers and
memory chips.

Device manufacturers often disable communications ports on circuit boards to protect data and intellectual property [7, 17]. In these instances, more invasive techniques are required because the communications connections only reside on the chips. Specifically, a chip is desoldered, and electrical connections are established between the communications pins on the underside of the chip and a data manipulation/debugging tool [13, 15] is employed for data acquisition. This invasive “chip-off” technique is also applied to extract evidence from electronic devices with damaged circuit boards, but whose microcontrollers and memory chips are intact. Rainwater [16] has demonstrated that it is also possible to expose the bond wires in a desoldered chip via laser ablation and ultrasonically weld tiny gold wires to the exposed bond wires on one side and a breakout board on the other side. Having established the connections between the chip and breakout board, a data manipulation/debugging tool [13, 15] can be employed to extract chip data.

Continuing their protection efforts, chip manufacturers may employ encryption [4, 5, 11] and lock bits [12] to thwart data recovery from desoldered chips. In such cases, data may be extracted using side-channel analysis, but the techniques are complex, tedious and have a low probability of success.

To address this problem, even more invasive techniques that expose the sil-
icon dies of chips have been developed. One technique uses laser glitching to
inject faults into a silicon die to defeat its data protection mechanism [3, 9]. A
second technique, passive voltage contrast imaging [6], uses a scanning electron
microscope to image the memory cells on a silicon die; the memory cell images
are subsequently analyzed by image processing software to determine memory
cell content. A third technique uses atomic force microscopy to measure the
capacitance of memory cells on a silicon die to reveal the stored data [8]. Unfor-
tunately, the laser glitching technique is highly unreliable because it uses brute
force on the assumption that glitching will eventually defeat the memory pro-
tection mechanism and affect data recovery. The other two techniques require
extremely precise preparation of silicon die samples and very high quality scan-
ning electron/atomic force microscope images. The preparation of silicon die
samples to the required tolerances often results in data loss due to memory cir-
cuit damage. Additionally, extremely sophisticated image processing algorithms
are required to consistently distinguish between the zeros and ones stored in
micron-scale memory cells.

This chapter describes a direct-control data acquisition method for non-
volatile memory that directly interfaces with floating-gate transistors on a silicon
die using nano-probes under a scanning electron microscope. The nano-probes
are positioned on the die control points attached to the address, bit and ground
lines associated with an individual memory cell. After the connections are es-
tablished, a highly-sensitive sourcemeter applies voltage in a sweeping pattern
(curve) to the address lines to enable current to flow between the bit and ground
lines. The sourcemeter measures the minuscule current flow in the floating-gate
transistor of the targeted memory cell to determine if the cell stores a zero or
one. This strategy would defeat any data protection mechanism implemented for
floating-gate transistors because, as long as transistors store bits, no protections
could be positioned lower than the transistor level.

The principal contribution of this research is a comprehensive workflow for customizing the data acquisition method to a specific non-volatile microcontroller or memory chip. The workflow comprises the method development and method application phases. During the initial method development phase, a custom direct-control data acquisition method is developed for a specific chip. This phase involves five steps, chip preparation, memory cell reverse engineering, contact point identification and disinterring, data acquisition and data verification. The five steps are performed iteratively using sample chips until the custom direct-control data acquisition method is perfected. The custom direct-control data acquisition method is applied to the target chip containing evidentiary data during the final method application phase.

The direct-control data acquisition method is restricted to non-volatile mem-
ory because it is difficult to power volatile memory and/or refresh (rewrite) the
stored data when its silicon die is inside a scanning electron microscope chamber.
Although the proposed data acquisition method is designed to work on any type
of non-volatile memory, the focus is on flash memory due to its ubiquitous use
in modern electronic devices.

2 Background

Memory is a vital component of electronic devices. It stores programs and data needed for electronic devices to function and provides workspaces for devices to perform operations on data. Electronic devices would have minimal functionality without persistent memory. Standard devices with memory include cell phones, flash drives, personal computers and Internet of Things devices. Data is stored in memory as bits (zeros or ones). Each bit is stored in a single memory cell that is implemented using one or more transistors [19].

Memory hardware incorporates transistors that constitute the memory cells
and circuitry that reads data from and writes data to the cells. The transis-
tors that constitute the memory cells and logic reside in a silicon wafer and
are interconnected via very-large-scale integration (VLSI). Memory resides in a
standalone memory chip or is integrated with other logic circuitry in a micro-
controller. Most electronic memory incorporates interconnected transistors that
reside in integrated circuits.

Transistors are the building blocks of integrated circuits. Transistors function like light switches because they control current flow between two points. Depending on the transistor type, current flows or is blocked from flowing when
<figure><img src="image_3.png" /><figcaption>Fig. 1. Single field-effect transistor.</figcaption></figure>

the transistor is not activated; the opposite is the case when the transistor is ac-
tivated. Transistors are used in integrated circuits because they can be controlled
electronically. Integrated circuit logic and memory cells incorporate various ar-
rangements and interconnections of multiple transistors [18].

The two main types of transistors are bipolar junction transistors and field-effect transistors. Non-volatile memory typically incorporates field-effect transistors, so this research deals primarily with field-effect transistors.

**Field-Effect Transistor** A field-effect transistor has three connections, gate, drain and source. It is controlled by a voltage placed at the gate. A field-effect transistor does not leak current like a bipolar junction transistor, making it more energy efficient. Also, it has a much higher switching speed than a bipolar junction transistor. These characteristics render field-effect transistors well suited to implementing integrated circuits and memory cells.

Figure 1 shows a field-effect transistor with the source and drain on either side of a channel with the gate sitting above the channel. The oxide layer electrically isolates the gate from the channel. Depending on the type of field-effect transistor, two default situations are possible. In the n-channel type of transistor, the drain and source pins are electrically connected by default, enabling current to flow. In the p-channel type of transistor, the drain and source pins are electrically isolated by default, blocking current flow.

A field-effect transistor is activated by applying a voltage to the gate. The current flow through the channel is changed by adjusting the voltage *Vg* applied at the gate. Depending on the transistor type, activating the transistor allows current to flow between the source and drain or prevents current flow [18]. Ordinary field-effect transistors can be arranged in groups to store bits of data temporarily. However, an additional electrically-isolated gate, called a floating gate, is required to implement non-volatile memory.

**Floating-Gate Transistor** A floating-gate transistor is a field-effect transistor with an extra floating gate between the gate and channel. Although the floating gate is electrically isolated from the rest of the transistor, it causes the transistor
<table><caption>**Table 1.** Floating-gate transistor states.</caption><thead><tr><th>Charged<br>Floating Gate</th><th>Vg ≤ Vth Vg > Vth</th></tr></thead><tbody><tr><td>No</td><td>Off On</td></tr><tr><td>Yes</td><td>Off Off</td></tr></tbody></table>

to function differently depending on whether or not a charge is stored on the floating gate. If there is no charge on the floating gate, then the transistor works like a standard field-effect transistor. For example, in the case of an n-channel floating-gate transistor with no charge on the floating gate, a high voltage on the gate turns the transistor on, enabling current to flow between the source and drain. However, when the floating gate is charged in an n-channel enhancement-mode floating-gate transistor, a higher voltage at the gate is required to activate the transistor [2]. As a result, applying the same voltage at the gate of a charged floating-gate transistor will not activate the transistor, preventing current from flowing between the source and drain. Detecting the difference in the functionality of a floating-gate transistor with a charged floating gate and an uncharged floating gate enables data storage [20].

Table 1 shows the states of an n-channel enhancement-mode floating-gate field-effect transistor. How a transistor behaves when an activating voltage is applied depends on whether or not the floating gate is charged. A voltage greater than the threshold voltage Vth activates the transistor unless the floating gate is charged. Typically, n-channel enhancement-mode floating-gate field-effect transistors are used to implement electrically-erasable programmable read-only memory and flash memory.

**Memory Operation** Different types of memory are created using combinations of transistors and other electronic components. However, the methods for reading data from many types of memory are similar. A memory cell sits at the intersection of an address line and bit line. The address line connects to the gate of the transistor in the memory cell, controlling when the cell can manipulate the state of the bit line to which it is connected. The data contained in a memory cell is determined by observing the state of the bit line after the cell is activated.

Memory is either volatile or non-volatile. Volatile memory loses the data it stores with the loss of power whereas non-volatile memory retains the stored data with the loss of power.

Flash memory, an example of non-volatile memory, is employed in most devices that collect and store data, mainly due to its low cost to data capacity ratio compared with other types of non-volatile memory. The ability of flash memory to be programmed and erased electronically renders it a great candidate for storing user data such as photographs and videos that take up large amounts of
space and are replaced frequently. Flash memory, currently the most commonly
used non-volatile memory, is the focus of this research.

## 3 Direct-Control Data Acquisition Workflow

The direct-control data acquisition workflow has two phases, method develop-
ment and method application. During the initial method development phase, a
custom direct-control data acquisition method is developed for a specific chip.
During the subsequent method application phase, the custom direct-control data
acquisition method is applied to the target chip containing evidentiary data.

Specialized equipment and techniques are required to implement the work-
flow. In the research, a FALIT laser decapsulator was employed for bulk chip
package removal. An Allied High Tech X-Prep high-precision mill was used to
expose silicon dies and delayer the dies for viewing under an FEI dualbeam (i.e.,
integrated scanning electron microscope and focused ion beam). The focused ion
beam was used for die layer disinterring, platinum contact point creation and
nano-probe tip customization under the scanning electron microscope. The nano-
probe tips were positioned on the contacts using a Zyvex nano-prober under the
scanning electron microscope. A Keithley 6430 sub-femtoamp sourcemeter was
employed to apply voltage to the address line contacts and measure current flow
across the floating-gate transistor (between the bit and ground lines) to read the
bit stored in the targeted memory cell.

### 3.1 Method Development Phase

This phase creates a chip-specific process for data acquisition utilizing sample
chips that are identical to the target chip containing evidentiary data. Figure 2
shows the five steps in the method development workflow: (i) chip preparation,
(ii) memory cell reverse engineering, (iii) contact point identification and disin-
terring, (iv) data acquisition and (v) data verification.

**Step 1: Chip Preparation** In this initial step, known data is written to iden-
tical sample chips and their silicon dies are exposed. Multiple equipment options
exist to perform data population and chip decapsulation. Different chips require
modifications to the process, including the amounts of material removed, equip-
ment used and order in which the equipment is used. Numerous chip preparation
process variations were attempted in this research, so the process described in
this section is a general workflow for developing a custom chip decapsulation
process for a new memory device. Detailed notes should be taken during chip
preparation because the perfected method is repeated on the target chip during
the method application phase.

The four tasks in the chip preparation step are known data population, laser
etching, nitric acid etching, and milling and polishing:
<figure><img src="image_4.png" /><figcaption>Fig. 2. Direct-control data acquisition method development phase.</figcaption></figure>
- **Known Data Population:** Writing known data to the sample chips helps verify that the direct-control data acquisition attempt is successful and the method development phase can be terminated. Specifically, one chip is programmed with repeating patterns of the hex value `0xFFFF` (binary `1111 1111 1111 1111`) and the other chip is programmed with repeating patterns of the hex value `0xFAC0` (binary `1111 1010 1100 0000`). The two data patterns help verify that the acquired data is correct without having to read large numbers of bits from the chips.

- **Laser Etching (Optional):** Laser etching is primarily used for chip preparation. Chips prepared for observation under a scanning electron microscope are “topside-prepped,” meaning that the topsides of the dies are exposed. To reduce the amount of encapsulating material removed by a chip mill or polisher, a laser etcher is used on the backside of the chips to remove as much extraneous material as possible.

A laser etcher removes plastic but does not damage metal. Because a copper lead frame protects the backside of a die, a laser etcher can be used to safely remove all the backside plastic down to the copper without damaging the die. In addition, the laser can be rastered over the entire chip package, even past the edges of the lead frame, to remove all the plastic material surrounding the die. Laser etching can be continued after the lead frame is exposed to remove material surrounding the die. After the surrounding material is thinned with the laser, it can be removed easily, leaving an area the size of the die for continued preparation with a high-precision mill or chip polisher.

- **Nitric Acid Etching (Optional):** Nitric acid etching is used to expose a bare die for further chip preparation. Nitric acid removes the plastic surrounding a die without damaging the die circuitry. Because nitric acid etching is a chemical process, the die is not accidentally scratched or damaged during decapsulation. Starting the die polishing process with a high-precision mill or polisher with a pristine, fully decapsulated die allows for precise leveling and even material removal across the die surface.

- **Milling and Polishing:** Milling and polishing are employed to remove bulk encapsulation material from a chip package that has not been etched using a laser or nitric acid. Milling and polishing may also be used to remove residual material after the optional laser and nitric acid etching tasks.

The goal of chip milling and polishing is to expose die circuitry without damaging the die. An Allied High Tech X-Prep high-precision mill was primarily used for topside decapsulation of integrated circuits. Therefore, a typical process for topside chip decapsulation using an X-Prep high-precision mill is described in this chapter. An X-Prep high-precision mill can also be used for bulk material removal and chip polishing. The mill comes with several milling and polishing tips for the two processes.

The four tasks involved in chip decapsulation and polishing using an X-Prep high-precision mill are chip mounting and leveling, bulk material removal, die leveling and die polishing:
* *Chip Mounting and Leveling:* A chip is mounted securely in an X-Prep high-precision mill before any encapsulation material is removed. A flat glass plate is used to hold the chip. The glass plate is heated and crystalline wax is applied to the plate. The chip is pressed into the crystalline wax before heating is terminated. After it has cooled, the glass plate with the chip is secured in an aluminum mount before it is placed in the X-Prep high-precision mill.

The aluminum mount holding the chip is placed in the X-Prep mill and the chip is leveled using a ruby probe tip positioned on the head of the mill. The ruby tip is a perfect sphere, which increases the precision of the automated leveling process.

The X-Prep mill levels the chip using three points provided by the user. The three points correspond to three corners of the encapsulation material. The X-Prep mill then levels to the surface of the encapsulation material. The ruby tip is periodically placed on each of the three locations, and the height differences are computed. Adjustments are made to the mount based on the height differences. This process is repeated until the chip is leveled within the specified tolerance (0.5 µm in this research).

* *Bulk Encapsulation Material Removal:* Encapsulation material must be removed after leveling the chip in the X-Prep mill. For bulk encapsulation material removal, a milling tip is positioned on the milling head of the X-Prep mill. The encapsulation material thickness above the die may not be known when decapsulating a new chip. In this case, x-ray images are taken of the sides of the die, and measurements of the resulting images are used to determine the thickness of the encapsulation above the die. Another method for estimating the thickness of encapsulating material above a die is to measure the distance from the top of the encapsulation to the top of the metal leads of the chip. This method is not as precise as measuring the thickness using x-ray images, so less material should be removed than the measured thickness to prevent damage to the chip. The first goal of chip decapsulation is to mill down to the bond wires of the chip. Since bond wires typically rise above a die, the wires can be used as landmarks to get close to the die. The milling tip must always be a safe distance from the die. If the milling tip makes contact with the die, the die could be damaged permanently. Until the exact thickness of the material above the die is known, removing less material than the estimated thickness is recommended. Small amounts of material can be removed repeatedly, but removing too much material at one time can result in permanent die damage.

A die is close to the surface when the bond wires become visible. A milling tip can still be used, but only 5 µm to 10 µm of encapsulation should be removed until the die is visible under the plastic material covering.

* *Die Leveling:* After the die is visible under the plastic material, it is re-leveled based on the thickness of the plastic remaining above the die. Edges of the die that appear to have thicker layers of plastic above them
are lower than the other edges. In such a situation, if milling is continued without die leveling, the high edges of the die could be damaged by the milling tip before the lower edges of the die are exposed.

*   **Die Polishing:** After the die is leveled, the X-Prep high-precision mill mounted with a polishing tip is used to remove smaller amounts of material. This creates a smoother surface for observation and does not damage the die as quickly as a milling tip. Guides included with X-Prep mills provide guidance on the appropriate polishing pads, diamond paste and machine parameters for various chip polishing scenarios [1].

**Step 2: Memory Cell Reverse Engineering** After a sample chip is prepped for observation under a scanning electron microscope, individual memory cells are reverse engineered to locate the gates, drains and sources of the floating-gate transistors in the memory cells. The three tasks involved in memory cell reverse engineering are integrated circuit observation, focused die layer disinterring and entire die delayering:

- **Integrated Circuit Observation:** The internal circuitry of an integrated circuit must be viewed under a scanning electron microscope because the features are too small to be seen using a light microscope. Memory circuitry is often easy to identify in an integrated circuit because it is laid out as long, straight lines in a grid pattern. In fact, memory circuitry usually has a rectangular shape and stands out from the other circuitry. Memory cells are located at the intersections of address and bit lines. However, because a scanning electron microscope can only view the top layer of circuitry, layers of the die must be removed to expose the lower layers. This is accomplished by cutting into the die with a focused ion beam or using chip milling and polishing equipment.

- **Focused Die Layer Disinterring:** After locating the memory circuitry on a die via a scanning electron microscope, a focused ion beam is used to make edits to the circuitry and disinter individual memory cells for reverse engineering. A focused ion beam shoots ions at a target in a rastering pattern. The large ions ablate material from the surface, cutting through and/or removing the material.

Because memory comprises numerous identical memory cells, various types of focused ion beam cuts are executed on memory circuitry to reverse engineer memory cells. This enables the memory cells to be observed from multiple angles to create a model of the memory layout and individual memory cell structures.

Rectangular and cross-sectional focused ion beam cuts were employed:

*   **Rectangular Cuts:** Rectangular focused ion beam cuts are executed to remove surface material and de-layer portions of a die to expose small areas of interest on the die.

*   **Cross-Sectional Cuts:** Cross-sectional focused ion beam cuts are rectangular, but are cut in a stair-step pattern. Such a cut is typically executed
to view the wall created by the deepest portion of the cut from the side. In addition to providing side-views of the areas of interest, cross-sectional cuts also make it possible to simultaneously observe multiple layers of memory circuitry. Because memory comprises a large array of identical memory cells, a long cross-sectional cut can be made so that each step of the stair-step pattern shows a different integrated circuit layer. Changing the depths of cross-sectional cuts changes the depths of the stair steps. Cross-sectional cuts may be cut side-by-side to different depths, accelerating the reverse engineering process by showing how multiple layers connect in a single image.

* *Entire Die Delayering:* Additional delayering of an entire die can be performed as needed during chip characterization. For example, after a layer of the die is observed and mapped, the layer can be removed to reveal the next layer of the die.

**Step 3: Contact Point Identification and Disinterring** After locating the gate, drain and source of the floating-gate transistor in a memory cell, potential nano-probe contact points are located and disinterred. The contact points depend on the locations of the targeted memory cells and the limitations of the equipment used in the data acquisition method. After the nano-probe contact points are identified, they may be disinterred using a focused ion beam.

The contact point identification and disinterring step involves two tasks, probe contact point identification and contact point disinterring:

- **Probe Contact Point Identification:** A floating-gate transistor in non-volatile memory has three connectors, gate, drain and source. Current flow through the source and drain is controlled by a voltage applied at the gate. Electrical connections must be made to the three transistor contact points for data acquisition because they control the functionality of the memory cell transistors. However, direct connections do not have to be made to the transistors. Instead, connections may be made to the lines attached to the transistor connections. This provides flexibility with regard to the wires that need to be exposed to uncover contact points for the nano-probes.

- **Contact Point Disinterring:** Having identified the nano-probe contact points, a focused ion beam is used to expose the contact points needed to establish electrical connections. Edits utilizing a focused ion beam must not damage the memory cells and the connections vital to memory cell functionality.

Focused ion beam edits can separate memory circuitry from other connected circuitry. In some cases, the other circuitry may actively pull wires down to ground, preventing manual line control. To address this problem, the circuitry is detached from unnecessary circuitry using a focused ion beam.

Figure 3 shows the results of focused ion beam edits intended to disinter nano-probe contact points. The 45 µm square has exposed contact points along all four edges. The test square is separated from the surrounding circuitry by deep trenches cut by the focused ion beam. The vertical wires are
<figure><img src="image_5.png" /><figcaption>**Fig. 3.** Nano-probe contact points exposed by focused ion beam editing.</figcaption></figure>

address (gate) and activation lines. The horizontal lines are bit lines (drain) and ground (source) lines. The horizontal lines run under the vertical lines. Only the edges of the horizontal lines are exposed to preserve the vertical lines needed to evaluate the direct-control data acquisition method on specific areas of memory.

**Step 4: Data Acquisition** Data acquisition is performed by positioning nano-probes on the exposed contact points and activating the memory cells. Data is read one bit at a time and the probes are repositioned between reads.

The three tasks in the data acquisition step are probe and contact point continuity establishment, bit acquisition and probe relocation:

- **Probe and Contact Point Continuity Establishment:** Nano-probes are positioned on the exposed contact points to manually control memory cells. However, the probe tips are very fragile. When a probe is landed on a contact point, vibrations caused by positioning other probes can damage the landed tip. Therefore, all the probes must be positioned as close as possible to the contact points without touching the points before any probes are landed. This minimizes probe movement after the probe tips are landed, preventing the tips from being damaged.

Landing a probe involves moving the probe tip downward until a slight flex is seen in the probe tip. After the probe is landed, the next probe is brought into view by altering the beam-shift of the scanning electron microscope. This changes the area viewed by the scanning electron microscope without moving the stage, preventing damage to the landed nano-probes.
After all the probes are positioned on their contact points, the scanning electron microscope is turned off because it interferes with the measurement equipment used for bit acquisition.

- **Bit Acquisition:** The threshold voltage of a floating-gate transistor indicates whether or not a charge is stored on the floating-gate, corresponding to a one or a zero, respectively. The threshold voltage is measured by performing a voltage sweep on the control gate and simultaneously measuring the current through the source and drain. Current flow is restricted until the transistor is activated. The voltage at the control gate when current starts to flow between the source and drain reveals the threshold voltage of the floating-gate transistor, which also reveals the bit value stored in the memory cell.

- **Probe Relocation:** After data is read from a memory cell, the nano-probes are relocated to read the next memory cell. One or more probes may have to be moved between reads depending on the arrangement of cells. For example, if the targeted memory cells are controlled by the same address line, only the probe positioned on the bit line has to be moved to the next bit line. However, if a different address line activates the next memory cell, all four probes have to be relocated to the control points of the new memory cell.

**Step 5: Data Verification** The data acquired from the sample chip is verified by comparing it against the known data written to the chip in Step 1. This ensures that the correct nano-probe contact points are identified and the data acquisition method is successful. If the data recovered from the sample chip does not match the known data, additional reverse engineering of the memory circuitry must be performed to identify the correct nano-probe contact points. If the data recovered from the sample device matches the known data, the method development phase for the chip of interest is complete and the method application phase can proceed to acquire data from the target chip.

## 3.2 Method Application Phase

This phase applies the chip-specific method perfected in the method development phase to acquire data from the target chip. Figure 4 shows the three steps in the method development phase: (i) chip preparation, (ii) contact point disinterring and (iii) data acquisition.

**Step 1: Chip Preparation** The chip-specific preparation method developed in Step 1 of the method development phase is applied to prepare the target chip for observation under a scanning electron microscope. However, because chips have variations, the amount of material to be removed from the target chip to expose its die may not be exactly the same as that for the sample chips. Therefore, less material than the measured thickness should be removed from the target device to prevent damage to the die. After the bulk encapsulation is removed, the die is exposed using a polishing tip in the X-Prep high-precision mill following the integrated circuit polishing guidelines provided by Allied High Tech [1].
<figure><img src="image_6.png" /><figcaption>Fig. 4. Direct-control data acquisition method application phase.</figcaption></figure>

**Step 2: Contact Point Disinterring** After the target chip die is exposed, the nano-probe contact points identified in Step 3 of the method development phase are exposed using a focused ion beam. Because the target chip contains data of interest, it is vital to disinter only the contact points to prevent damage to the surrounding circuitry. If the focused ion beam is aimed at areas other than the nano-probe contact points, damage may occur to the memory cells and circuitry that supports data retrieval, resulting in data destruction. Therefore, it is important to proceed cautiously and remove small amounts of material at a time.
<figure><img src="image_7.png" /><figcaption>Fig. 5. Ideal voltage-resistance (left) and voltage-current (right) curves.</figcaption></figure>

**Step 3: Data Acquisition** The same tasks applied to the sample chip die in Step 4 of the method development phase are repeated on the target chip die to acquire data. The nano-probes are positioned on the exposed contact points and data is read one bit at a time. The nano-probes are relocated between reads as necessary and the process is repeated until the data from the target die is acquired.

# 4 Experiments and Results

After extensive preliminary experimentation, a number of experiments were conducted to evaluate the application of the direct-control data acquisition method on ATmega328P microcontrollers. The first baseline experiment was conducted to validate the software, hardware and electrical connections used in subsequent experiments. Following the baseline experiment, 12 data acquisition experiments were conducted. The experiments incorporated modifications to address the limitations encountered in previous experiments. All the experiments adhered to the direct-control data acquisition workflow described in Section 3.

## 4.1 Baseline Experiment

The baseline experiment tested the connectivity between the Keithley source-meter and nano-probes, and validated the Python script used to control the source-meter. This was accomplished by connecting the source-meter cables to a stand-alone through-hole transistor that simulated connections to the ATmega328P microcontroller memory cells in the experiments. The Python script instructed the source-meter to sweep the voltage at the gate and drain of the through-hole transistor while simultaneously taking measurements. This was done twice to generate the ideal voltage-resistance and voltage-current curves.

Figure 5 (left-hand side) shows the ideal voltage-resistance curve for the through-hole transistor. The curve initially shows high resistance because the transistor was inactive and shows low resistance when the transistor was activated. This voltage-resistance curve is expected when a non-volatile memory cell of an ATmega328P microcontroller is probed during a direct-control data acquisition experiment.
<figure><img src="image_8.png" /><figcaption>Fig. 6. Experimental setup.</figcaption></figure>

Figure 5 (right-hand side) shows the voltage-current curve with the current initially limited because the through-hole transistor was inactive; the current was constrained by the in-circuit resistor when the transistor was activated. This voltage-current curve is expected when a non-volatile memory cell of an ATmega328P microcontroller is probed during a direct-control data acquisition experiment.

## 4.2 Data Acquisition Experiments

Twelve direct-control data acquisition experiments are presented in this section. Each experiment incorporated modifications to address the limitations encountered in the previous experiments. The experiments sought to address four principal challenges: discovering three-dimensional memory cell profiles, establishing probe/contact point continuity, adding electrical safeties and improving electrical grounding.

**Experimental Setup** Figure 6 shows the initial experimental setup with four nano-probes for evaluating the direct-control data acquisition method. In the setup, nano-probe 1 for the bit line and nano-probe 2 for the control gate on the activation transistor are connected to cable splitter 2; nano-probe 3 for the control gate on the floating-gate transistor and nano-probe 4 for ground are connected to cable splitter 3. Nano-probes 1, 2 and 3 are connected to the positive signal from the Keithley sourcemeter whereas nano-probe 4 is connected to ground.

**Discovering Memory Cell Profiles** The first set of experiments sought to map the three-dimensional structure of individual memory cells. The shape and placement of memory cells dictate the locations of disinterred contact points for
<figure><img src="image_9.png" /><figcaption>Fig. 7. Focused ion beam edits and nano-probe damage (Experiment 2).</figcaption></figure>

nano-probe placement. The four experiments attempted to shape the layout of
the uncovered test area on the silicon die:

- **Experiment 1:** This experiment executed focused ion beam edits to expose contact points for the nano-probes. The layer containing the control gates and floating-gate transistors (address lines) was kept intact and deep cuts were made on both sides of the address lines to expose the bit and ground lines.

The experiment was unsuccessful because the focused ion beam edits severed
the connections to the tungsten plugs connecting the address lines to the
transistors in the layers below. The address lines stretch across the memory
circuitry, but only periodically extend down to the layers containing the
transistors.

- **Experiment 2:** To address the failure in Experiment 1, the second experiment executed focused ion beam edits to expose the nano-probe contact points while retaining the tungsten plugs connecting the address lines in the top layer to the transistors in the lower layers. This was accomplished by keeping the area containing the tungsten plugs clear of edits and making deep cuts on both sides of the address lines to expose the bit and ground lines. The deep cuts, which exposed the bit and ground lines, were aligned with each other to maximize the number of bit lines that could be accessed without additional focused ion beam edits.

Figure 7 (left-hand side) shows the result after disinterring the nano-probe
contact points. The horizontal lines are the address lines and the vertical
lines running under the address lines are the bit and ground lines.

Experiment 2 was unsuccessful because the area containing the disinterred
nano-probe contact points was too large to be viewed by the scanning elec-
tron microscope without adjusting the position of the stage. Figure 7 (right-
hand side) shows a landed nano-probe tip that was damaged due to stage
<figure><img src="image_10.png" /><figcaption>Fig. 8. Focused ion beam edits (Experiment 3).</figcaption></figure>

movement. The landed nano-probe was damaged when the stage was ad-
justed to view and position the second nano-probe.

- **Experiment 3:** This experiment executed focused ion beam edits to expose the nano-probe contact points while addressing the problems encountered in the previous two experiments. The region containing the disinterred nano-probe contact points was reduced to a 45 µm × 45 µm square to enable all the contact points to be viewed under the scanning electron microscope without moving the stage. The square region was centered on the tungsten plugs connecting the upper address line layer to the lower transistor layers to prevent them from being damaged by the focused ion beam.

Figure 8 shows an attempt at disinterring the nano-probe contact points within the 45 µm × 45 µm square. The vertical lines are the address lines and the horizontal lines running under the address lines are the bit and ground lines.

The experiment was unsuccessful because it was difficult to land nano-probes on different layers of the silicon die. Since the bit and ground lines are located in lower layers of the die than the address lines, the nano-probes on all three types of lines were not simultaneously in focus under the scanning electron microscope. Additionally, the tiny areas for landing nano-probes on the lower layer increased the risk of running the nano-probe tips into the elevated address line layer.

- **Experiment 4:** This experiment executed focused ion beam edits to ablate the top layer containing the address lines to address the problems encountered in Experiment 3. Because the tungsten plugs connect the upper address line layer to the lower transistor layers, suitable contact points for address lines are available in the same layer as the bit and ground lines since the layer
<figure><img src="image_11.png" /><figcaption>Fig. 9. Burrowed address line and focused ion beam edits (Experiment 4).</figcaption></figure>

containing the bit lines and ground lines is located between the address line and transistor layers. Removing the upper address line layer enables nano-probe contact points for the three types of lines to be located in the same layer so that they are simultaneously in focus under the scanning electron microscope. Additionally, having all the nano-probe contact points in the same layer provides ample space for positioning the probes.

Figure 9 (left-hand side) shows a side view of the connection between the upper address line layer and lower transistor layer as an address line burrows through the layer containing the bit and ground lines. Because the address line burrows through the bit and ground line layer, the upper address line layer can be removed while making a suitable contact point available for the address line.

Figure 9 (right-hand side) shows the ion beam edit results. All the contact points are located in the same layer and are simultaneously in focus under the scanning electron microscope.

In Experiment 4, four nano-probes, two for an address line and one each for bit and ground lines, were landed successfully. Following this, voltage-current measurements were attempted using the Keithley sourcemeter. However, no measurements were made because, although the nano-probes were landed successfully, adequate electrical connections were not established between the nano-probes and contact points.

**Establishing Probe/Contact Point Continuity** Good electrical connections provide the best possibility of successful memory cell read operations. Therefore, the second set of experiments focused on establishing nano-probe and contact point continuity. The four experiments in the set sought to define the process used in later experiments for uncovering contact points, depositing platinum to improve electrical connections and modifying nano-probes:
<figure><img src="image_12.png" /><figcaption>Fig. 10. Sample voltage-resistance curves (Experiment 6).</figcaption></figure>

- **Experiment 5:** Experiment 5 executed ion beam edits that produced stair-step cuts to expose the bit and ground lines. Additionally, the focused ion beam was used to deposit platinum on the exposed nano-probe contact points. Platinum deposition on the contact points increases the likelihood of establishing adequate electrical connections between the nano-probes and contact points, and provides elevated surfaces for landing nano-probes. However, the close proximity of the platinum deposited on the bit and ground lines in this experiment made it difficult to position a nano-probe on a single bit or ground line without it touching an adjacent bit or ground line. As a result, the Keithley sourcemeter did not provide any measurements.

- **Experiment 6:** Experiment 6 executed ion beam edits that produced stair-step cuts to expose the bit and ground lines. Also, it sought to address the problem of nano-probes connecting to multiple bit lines by depositing platinum in an offset, alternating pattern.

Figure 10 shows sample voltage-resistance curves obtained in Experiment 6. The curve on the left-hand side shows a steady decrease in resistance with no incline after reaching its lowest resistance measurement. This sample curve differs from the ideal curve in Figure 5 (left-hand side), which invalidated the measurements.

A later experiment yielded the curve on the right-hand side that resembles the ideal voltage-resistance curve in Figure 5 (left-hand side). However, the positive result could not be reproduced in subsequent measurements.

The poor and non-reproducible results indicate weak and/or improper electrical connections. Further investigation of the equipment revealed that the wiring of the fourth nano-probe was frayed and it was not electrically connected to the external port on the scanning electron microscope. As a result, the contact point of the damaged nano-probe was not pulled to ground during Experiment 6.

- **Experiment 7:** Experiment 7 executed ion beam edits that produced stair-step cuts to expose the bit and ground lines and sought to address the problem of nano-probes connecting to multiple bit lines by depositing platinum in an offset, alternating pattern. To establish better electrical connections, the vertical spacings between platinum deposits on the bit and ground lines, and the size of the platinum deposit on the ground line were increased from Experiment 6.
<figure><img src="image_13.png" /><figcaption>Fig. 11. Modified experimental setup (Experiment 7).</figcaption></figure>

Due to the damage to the fourth nano-probe, the two address line contact points were electrically connected via platinum deposition to enable experimentation using the three operational nano-probes. This required the modification of the experimental setup in which splitters isolated the signals so that nano-probes 1 through 3 were connected to the positive signal coming from the Keithley sourcemeter while nano-probe 4 was connected to ground. Figure 11 shows the modified experimental setup using the three operational nano-probes. A platinum pad electrically connects (pairs) the control gates of the two memory cell transistors. In the modified setup, nano-probe 1 for the bit line is connected to cable splitter 1 and nano-probes 2 and 3 for the two paired address lines and ground lines are connected to cable splitter 2. Nano-probes 1 and 2 are connected to the positive signal coming from the Keithley sourcemeter while nano-probe 3 is connected to ground.

<figure><img src="image_14.png" /><figcaption>Fig. 12. Sample voltage-resistance curves (Experiment 7).</figcaption></figure>

Figure 12 shows the voltage-resistance curves obtained in Experiment 7. The curve on the left-hand side does not match the ideal voltage-resistance curve in Figure 5 (left-hand side) and was not reproducible. The curve on the right-hand side resembles the ideal voltage-resistance curve, but it was also not reproducible.
<figure><img src="image_15.png" /><figcaption>Fig. 13. Damaged nano-probe tip and modified nano-probe tip (Experiment 8).</figcaption></figure>

- **Experiment 8:** This experiment was conducted in the same way as Experiment 7, except that the nano-probe tips were modified to improve the electrical connections with the platinum contact points. This was accomplished by using the focused ion beam to excise the tips of damaged nano-probes. Since the tip of a nano-probe is tapered, excising a damaged tip yields a larger contact area for the new probe tip and enhances the mechanical strength of the probe tip.

Figure 13 shows a damaged probe tip (left-hand side) and the probe tip (right-hand side) created from the damaged tip using the focused ion beam.

<figure><img src="image_16.png" /><figcaption>Fig. 14. Focused ion beam edits and damaged memory circuitry (Experiment 8).</figcaption></figure>

Figure 14 (left-hand side) shows the attempt at disinterring nano-probe contact points in Experiment 8 (same as in Experiment 7). Unfortunately, as
<figure><img src="image_17.png" /><figcaption>Fig. 15. Second modified experimental setup (Experiment 9).</figcaption></figure>

seen in Figure 14 (right-hand side), the larger nano-probe tips induced high current flows that damaged the memory circuitry. However, Experiment 8 verified that the platinum deposits were helping establish better connections between the nano-probe tips and contact points.

**Adding Electrical Safeties** The third set of experiments added electrical safeties to protect memory cell transistors and nano-probes from damage caused by excessive current throughput, and to prevent false data reads by eliminating floating address lines:

- **Experiment 9:** This experiment was conducted in the same way as Experiment 8, but with two changes. First, a modified nano-probe tip was used for the ground line because, unlike the address and bit lines, it is possible to create a larger platinum pad for the ground line to accommodate a modified nano-probe tip. Second, four 30 MΩ resistors in series were added inline to the cable supplying current to the memory cell drain to prevent current from damaging memory circuitry as in Experiment 8.

Figure 15 shows the second modified experimental setup using the three operational nano-probes. The modified experimental setup has the same configuration as the previous experimental setup in Figure 11, but with an added resistor between cable splitter 1 and nano-probe 1 to limit the current flow that damaged the memory circuitry in Experiment 8.

Voltage-resistance measurements were attempted through Experiment 7 before switching to voltage-current measurements for the remaining experiments. The voltage-resistance curve was used because the point at which the transistor is activated should be the lowest resistance measurement on the curve and easily discernible. However, since a chip reads data by measuring current flow, the experiments were modified to mimic the chip functionality. Therefore, voltage-current measurements instead of voltage-resistance measurements were made in Experiment 9 and subsequent experiments.
<figure><img src="image_18.png" /><figcaption>Fig. 16. Sample voltage-current curves (Experiment 9).</figcaption></figure>

Figure 16 shows sample voltage-current curves obtained in Experiment 9. The curves on the left- and right-hand sides, obtained from different memory cells, look similar. However, neither curve resembles the ideal voltage-current curve in Figure 5 (right-hand side), invalidating the measurements.

- **Experiment 10:** Most of the voltage-current curves obtained in Experiment 9 resembled each other, potentially indicating that multiple memory cells were activated by nano-probing the floating address lines instead of single memory cells. Experiment 10 sought to remedy this situation by de-positing a large platinum pad over the address lines that were not being probed as well as the ground line, connecting all the unused address lines to ground.

Figure 17 shows the focused ion beam edits, which include the large platinum pad that prevents multiple memory cell activations due to floating address lines.

Unfortunately, satisfactory voltage-current curves were not obtained. Further investigation revealed that the platinum deposits and/or electrical connections made to the memory circuitry were inadequate to address the problems.

Improving Electrical Grounding
The fourth set of experiments improved the electrical grounding of the silicon substrate on the chip. Transistors require the substrate that they sit on to be controlled. In the case of the transistors encountered in the experiments, the substrate has to be grounded for the transistors to function properly. Therefore, two experiments were performed to improve the continuity between the silicon substrate of the target chip and electrical ground:

- **Experiment 11:** This experiment attempted a completely different approach to address the inadequate electrical connections, including the silicon substrate being biased (grounded) incorrectly. In particular, Experiment 11 executed the same focused ion beam edits as Experiment 9, but incorporated two key modifications. The first modification sought to address the problems induced by platinum splatter on adjacent circuitry during platinum pad deposition via focused ion beam ablation. The splatter created a thin layer of platinum that shorted the nano-probe contact points, affecting the measured current flow.
<figure><img src="image_19.png" /><figcaption>Fig. 17. Focused ion beam edits (Experiment 10).</figcaption></figure>

<figure><img src="image_20.png" /><figcaption>Fig. 18. Memory circuitry before and after spatter removal (Experiment 11).</figcaption></figure>

Figure 18 (left-hand side) shows the memory circuitry covered with platinum spatter after platinum pad deposition. Figure 19 (right-hand side) shows the same memory circuitry after the focused ion beam ablated the platinum spatter.

The second modification focused on the silicon substrate bias problem. The die substrate is often considered to be the fourth transistor component apart from the source, drain and gate. The substrate is rarely documented because substrate biasing is typically handled by the chip and is not user-controlled. However, a transistor will not activate without a properly-biased silicon sub-
<figure><img src="image_21.png" /><figcaption>Fig. 19. Sample voltage-current curves (Experiment 11).</figcaption></figure>

strate. In fact, the silicon substrate in the previous experiments may not have biased correctly because, after a die is removed from its package, the substrate may not be pulled to ground. Experiment 11 sought to address the bias problem by placing the lead frame of a chip being read directly on the scanning electron microscope sample holder instead of on a non-conductive crystalline wax support.

The exposed lead frame on the bottom of the chip was placed in direct contact with the sample holder, grounding the lead frame to the scanning electron microscope stage. The lead frame is electrically connected to the silicon substrate on some devices. In the case of electrically-connected lead frames and substrates, grounding the lead frame also grounds the silicon substrate.

Figure 19 shows sample voltage-current curves obtained in Experiment 11. The two curves resemble the ideal voltage-current curve in Figure 5 (right-hand side). However, the maximum current measurements in the two experimental curves greatly exceed the theoretical current maximum of 27.5 nA for a 3.3 V differential applied to a 120 MΩ resistor. If the current measurements are accurate, they would imply that the current traveled from the address line to ground and not through the memory cell transistors. The experimental curves also indicate that grounding the lead frame did not ground the silicon substrate, which prevented the memory cell transistors from activating.

— **Experiment 12:** This experiment executed the same ion beam edits as Experiment 9. Platinum spatter ablation was performed as in Experiment 11, but the silicon substrate bias correction technique was not applied because a new method for prepping sample chips was employed. Specifically, the sample chips were prepped to leave their bond wires and chip leads intact to facilitate the grounding of the silicon substrate. Solder was utilized to ensure good electrical connections between the chip leads and copper tape. This modification sought to enable the utilization of the chip circuitry to ground the silicon substrate through the external chip leads as intended in the chip design.

Figure 20 shows the voltage-current curves obtained in Experiment 12. The majority of the measurements made in Experiment 12 resembled the left-hand side voltage-current curve, which shows a steady increase in current as the voltage is raised. However, these voltage-current curves do not re-
<figure><img src="image_22.png" /><figcaption>Fig. 20. Sample voltage-current curves (Experiment 12).</figcaption></figure>

semble the ideal voltage-current curve in Figure 5 (right-hand side). The right-hand side voltage-current curve in Figure 20 loosely follows the ideal voltage-current curve until the voltage reaches about 2 V, followed by a sudden drop and sporadic increase in current flow. The drop in current at approximately 2 V typically indicates that the probe tip lost contact with the platinum pad. Attempts to repeat the measurements and obtain a similar curve were unsuccessful. As in the previous experiments, the readings were reasonably consistent, but they did not match the expected voltage-current curve obtained in the baseline experiment (Figure 5).

# 5 Discussion

The direct-control data acquisition method for non-volatile memory and the accompanying chip customization workflow involving the iterative method development and final method application phases are logical and technically sound based on the underlying physics and engineering. Clearly, direct-control data acquisition at the transistor level is very challenging. The numerous experiments conducted during the research – many more than the dozen described in this chapter – amply demonstrate this fact. This section discusses the efforts, challenges and opportunities pertaining to the five steps of the data acquisition workflow.

## 5.1 Chip Preparation

Chip preparation readies a sample chip for viewing under a scanning electron microscope. This task, involving chip package removal and silicon die polishing, is fairly standard. Experiments 1 through 11 involved the same chip preparation process. The lack of good, reproducible results in these experiments influenced the application of the less-common process in Experiment 12 to leave the bond wires and chip leads intact to facilitate the grounding of the silicon substrate, which may have been inadequate. However, this modification did not change the results, which implies that the problems were in the subsequent steps in the workflow.
**Memory Cell Reverse Engineering** Memory cell reverse engineering seeks to understand the layout and connectivity of memory cells on a chip die. Reverse engineering is as much an art as a science; it is also tedious and time-consuming. Many months were spent investigating microcontrollers containing non-volatile flash memory under a scanning electron microscope to understand memory cell layout and connectivity. Indeed, it was only after a good understanding of the memory cell structure and connectivity was obtained and the memory reverse engineering results were reproducible did Experiment 1 and the subsequent experiments proceed.

Absent details about the silicon-level layout and connectivity from a chip manufacturer, the only option is to progressively cut into chip samples with a focused ion beam and analyze the scanning electron microscope images to obtain a three-dimensional model of the memory cells at the transistor level. The reverse engineering efforts could also benefit from using energy-dispersive x-ray spectroscopy. If this technique is sensitive enough to detect doped silicon, it could provide insights into the types of transistors involved and the signals required to activate them via nano-probing.

**Contact Point Identification and Disinterring** This important step involves contact point identification and disinterring:

- **Contact Point Identification:** Contact point identification locates the contact points connected to memory cell transistors that accommodate the constraints imposed by the equipment used for data acquisition. After the gate, drain and source of a memory cell were identified via reverse engineering, the experiments progressively improved the focused ion beam edits. The improvements involved reducing the size of the target area to accommodate the limited region of visibility provided by the scanning electron microscope. Subsequent improvements addressed the difficulty of positioning nano-probes by reducing the topographical complexity of the focused ion beam edits. The ATmega328P chip incorporates two connected transistors instead of a single transistor, which rendered the contact point identification task more difficult. Nevertheless, the progressive improvements made in the direct-control data acquisition experiments reduced the difficulty in positioning nano-probes and increased the probability of successful positioning.

- **Contact Point Disinterring:** Contact point disinterring removes the silicon covering the contact points to enable electrical connections to be established between the nano-probe tips and contact points. As in the case of contact point identification, continuous improvements were made to the contact point disinterring process during the series of experiments. Experiments 5 through 9 executed stair-step cuts to the edges of the identified contact lines to improve the chances of uncovering portions of the conductive contacts from under the non-conductive silicon. Other incremental improvements included depositing platinum on the contact points to increase conductivity and facilitate nano-probe positioning.
Unfortunately, the equipment did not support a method for verifying the successful disinterring of nano-probe contact points. Specifically, an energy-dispersive x-ray spectroscope could have been used to identify the materials present on the surfaces of scanning electron microscope samples. This information could have provided valuable feedback in executing additional focused ion beam edits until the successful disinterring of contact points was verified.

**Data Acquisition** Data acquisition attempts to determine the data stored in a memory cell using a high-precision sourcemeter that applies voltage in a sweeping pattern to the control gate and drain lines of the memory cell while simultaneously measuring the resistance or current flow. The data acquisition experiments involved multiple attempts to mitigate the negative factors that impact resistance and current measurements at the micron scale.

Experiments 6 through 12 progressively increased the spacing of platinum pads to address the lack of success in establishing connections between a nano-probe tip and multiple bit lines. Experiment 11 reduced the contamination due to sample exposure to air by executing focused ion beam edits during the same scanning electron microscope sessions as nano-probing (i.e., samples were maintained in the vacuum chamber of the scanning electron microscope during the entire process). Experiments 11 and 12 reduced the possibility of shorted contact points due to platinum spatter by executing focused ion beam edits to remove excess platinum from the surfaces of samples. Experiments 11 and 12 also facilitated transistor activation by grounding the silicon substrate, the fourth contact point of a transistor. Experiment 11 grounded the exposed chip lead frame directly to the conductive sample holder whereas Experiment 12 left the original bond wires and chip leads intact to ground the silicon substrate using the ground pins of the chip.

The data acquisition efforts could have benefitted from process improvements that remove sample contaminants. The improvements include using xenon difluoride and/or plasma cleaning in an anti-contamination unit, as well as contact point cleaning and parallel chip delayering using a focused ion beam.

The efforts could also have benefitted by employing more sophisticated resistance and current measurement equipment. One solution is to use special measurement equipment that comes with some nano-probers. Another solution involves replacing the single sub-femtoamp sourcemeter for activating transistors and measuring resistance and current with a high-precision power supply for transistor activation and restricting the sourcemeter to resistance and current measurement.

Finally, probe tip modifications that enlarge the contact surface area and improve the mechanical stability of the nano-probe tips could have reduced the resistance created by the probe tips and helped establish better electrical connections between the probe tips and contact points.

It is clear that the experiments were unable to extract data from memory cells in a reliable manner. However, the continuous improvements to the data
acquisition process over the experiments are expected to enhance the success of future direct-control data acquisition efforts.

**Data Verification** Data verification checks the data read via direct-control data acquisition against the data originally stored on a chip. Two patterns were programmed on sample chips at the start of the chip preparation step, repeating `0xFFFF` hex values and repeating `0xFAC0` hex values. The data verification step is technically sound. However, the step could not be completed because the memory cell data reads were non-ideal or inconsistent.

# 6 Conclusions

The novel direct-control data acquisition method for non-volatile memory described in this chapter directly interfaces with floating-gate transistors on a silicon die using tungsten nano-probes under a scanning electron microscope. The data acquisition method is restricted to non-volatile memory because it is difficult to power volatile memory and/or refresh the stored data when the silicon die is in the chamber of a scanning electron microscope.

The workflow for customizing the data acquisition method to a specific non-volatile microcontroller or memory chip involves a method development phase and a method application phase. During the method development phase, a custom data acquisition method is developed for a specific chip. This phase involves five steps, chip preparation, memory cell reverse engineering, contact point identification and disinterring, data acquisition, and data verification. The five steps are performed iteratively using sample chips until the custom data acquisition method is perfected. During the final method application phase, the custom data acquisition method is applied to the target chip containing evidentiary data.

Numerous direct-control data acquisition experiments were conducted on AT-mega328P microcontroller chips. The experimental results reveal that the chip preparation, memory cell reverse engineering and contact point identification steps were successful. However, the contact point disinterring step did not produce good results because the available equipment made it difficult to verify that the contact points were completely exposed and free from contamination and damage. The inability to establish consistent electrical connections between the nano-probe tips and address, bit and ground lines caused the data acquisition step to be generally unsuccessful. The data verification step, while technically sound, could not be completed because the memory cell data reads were non-ideal or inconsistent.

Despite the non-ideal and inconsistent experimental results, the direct-control data acquisition method and the workflow for customizing a data acquisition method to a specific microcontroller or memory chip are technically sound. Future research leveraging more sophisticated equipment and detailed knowledge about the structure and layout of the silicon dies would be expected to demonstrate the success of the data acquisition method and its accompanying workflow.
The views expressed in this chapter are those of the authors, and do not reflect the official policy or position of the U.S. Secret Service, U.S. Department of Homeland Security or the U.S. Government.

**Acknowledgment** This research was supported by the National Science Foundation under Grant no. DGE 1501177 and by the U.S. Secret Service National Computer Forensics Institute Laboratory.

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