# Investigations on Phase-Modular PFC with Integrated DC-Link Energy Buffer for On-Board Battery Chargers

Mattia Iurich, Zhen Huang, Franz Vollmaier, Thomas Langbauer, Roberto Petrella

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Mattia Iurich, Zhen Huang, Franz Vollmaier, Thomas Langbauer, Roberto Petrella. Investigations on Phase-Modular PFC with Integrated DC-Link Energy Buffer for On-Board Battery Chargers. The 26th European Conference on Power Electronics and Applications, GDR SEEDS France & EPE Association, Mar 2025, Paris, France. 10.34746/epe2025-0185. hal-05105981

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# Investigations on Phase-Modular PFC with Integrated DC-Link Energy Buffer for On-Board Battery Chargers

Mattia Iurich<fnref n="1" />, Zhen Huang<fnref n="1" />, Franz Vollmaier<fnref n="1" />, Thomas Langbauer<fnref n="1" /> and Roberto Petrella<fnref n="2" />,<fnref n="3" />

¹ Sandgasse 34, 8010
Graz, Austria

² Europastraße 12, 9524
Villach, Austria

³ Via delle Scienze 206, 33100
Udine, Italy

Tel.: +43 / (0) - 664.88200155

E-Mail: mattia.iurich@silicon-austria.com

URL: https://silicon-austria-labs.com/

## ACKNOWLEDGMENT

This work has been jointly supported by AVL List GmbH, Fronius International GmbH, Infineon Technologies Austria AG, Infineon Technologies AG, META SYSTEM S.P.A., TDK Electronics GmbH, Technische Universität Graz and by Silicon Austria Labs (SAL), owned by the Republic of Austria, the Styrian Business Promotion Agency (SFG), the federal state of Carinthia, the Upper Austrian Research (UAR), and the Austrian Association for the Electric and Electronics Industry (FEEI).

## KEYWORDS

«AC-DC converter», «Power factor correction», «Bidirectional converters», «Power density optimisation», «On-board charger».

## ABSTRACT

In this paper a two-stage bidirectional Power Factor Correction (PFC) boost-buck topology featuring a novel built-in energy storage buffer functionality is proposed, specifically tailored for (isolated) On-Board Charger (OBC) applications. Main concept idea is to allow a certain amount of voltage oscillation at twice the line frequency at the output of the boost PFC stage (allowing a significant reduction of the dc-bus capacitor), and let the cascaded step down converter, namely the Series Connected Buck-type (SCB) Pulsating Power Buffer (PPB), to dynamically absorb the pulsating energy, aiming at supplying a stiff voltage for the multi-port

DC transformer (DCX) stage feeding the battery. The topology incorporates modular single-phase totem-pole (TP) modules that deliver 3.6 kW each in a three-phase set-up, or can be configured in parallel for single-phase operation at 2.4 kW each, resulting in total output powers of 11 kW and 7.2 kW, respectively. The proposed active buffer solution allows enhancing the power density of the system, by minimizing the capacitor size, and makes use of varied semiconductor devices with breakdown voltages of 750 V and 1.2 kV. A Multi Objective Optimization (MOO) process is adopted to seek for the most effective balance between bulk capacitance and inductive components against losses and switching frequencies, thus achieving peak power density. Comprehensive analytical and simulation results are shown to validate the effectiveness of the proposal, together with a sketch of the actual experimental prototype.

## I. INTRODUCTION

As mobility applications continue to electrify, the demands on power electronics converters and components are becoming increasingly stringent regarding cost, longevity/reliability, efficiency, and power density. A crucial component of electric vehicles in the automotive sector is the OBC. In addition to the previously mentioned requirements, it must operate globally, which necessitates the capability for both single-phase (1-Φ) and three-phase (3-Φ) operation at specific power levels. The proposed PFC for a high power dense automotive OBC exploits modularity, having three 1-Φ totem pole modules controlling each phase current [1], as illustrated

<footnote n="1">¹ Architectures & Topologies, Division Power Electronics, Silicon Austria Labs GmbH (SAL)</footnote>

<footnote n="2">² System Level Integration Technologies, Division Power Electronics, Silicon Austria Labs GmbH (SAL)</footnote>

<footnote n="3">³ Polytechnic Department of Engineering and Architecture (DPIA), University of Udine</footnote>
<figure><img src="image_2.png" /><figcaption>**Figure 1:** Schematic of the whole OBC application comprising the grid connection relays, the electro-magnetic interference (EMI) filter, the proposed boost-buck power factor correction (PFC) structure including the energy buffers and the subsequent DC/DC stage for connecting the high voltage (HV) battery of an electric vehicle. The suggested boost-buck PFC topology allows $U_{B,x}$ ($x = a, b, c$) to float whilst keeping the input voltage $U_{o,x}$ of the DCX stiff, and to minimize DC-link capacitor for increased power density.</figcaption></figure>

in Fig. 1. Each module is rated for 3.6 kW when in 3-Φ operation (to achieve total of 11 kW output power), whereas they are connected in parallel with power sharing of 2.4 kW each to achieve a total output power of 7.2 kW in 1-Φ operation. A challenge for 1-Φ PFCs is that these suffer from twice line-frequency DC-link voltage fluctuation. This issue is generally solved by employing large electrolytic or foil capacitors, balancing between the trade-offs of lifespan and space consumption [2], or by implementing active power buffers [3], [4]. The active solution allows to increase the power density of the system, at the cost of increased component count and complexity [5], [6] and, in most cases, a slightly reduced efficiency.

This work suggests an integrated buffer solution, in which the DC-link voltage $U_{B,x}$ (refer to Fig. 1) is allowed to float and a cascaded step down converter is used to absorb the pulsating energy at twice line frequency to finally supply a stiff voltage for the subsequent multi-port DCX stage. The higher the voltage fluctuation on the DC-link is allowed, the smaller the bulk capacitor value could be adopted, increasing the overall power density of the system. The use of various types of devices with different breakdown voltages enables different ranges of fluctuation, with a different impact on the allowable energy which can be stored/buffered. In fact, the choice of the power semiconductors (mainly the voltage ratings) is crucial for capacitor density because devices with

high breakdown voltages can handle greater voltage fluctuations, thereby minimizing the bulk capacitor size. However, devices rated for higher voltages tend to have increased losses and it is therefore of paramount importance to carefully analyze the trade-offs among the different choices by means of MOO.

The paper is organized as follows: Section II discusses the choice of the bulk capacitor considering the available technologies and the breakdown voltages of the power semiconductors, specifically 750 V or 1200 V. In Section III the MOO process based on a Pareto front analysis for various passive components and power devices is reported and discussed, with the goal of achieving maximum power density for both the boost-type PFC and the SCB-PPB, i.e., to obtain the most effective balance between bulk capacitance and inductive components against losses, switching frequency and volume. The detailed results and simulations are presented in Section IV. Finally, concluding remarks including a sketch of the hardware prototype and an outlook on future work are reported in Section V.

## II. DC-LINK CAPACITOR DESIGN

The DC-link capacitor designs options have been studied first, which are strongly correlated to the semiconductor devices and to the adopted capacitor technology. Selection of the proper capacitance is straightforward and proves to be more demanding in the 1-Φ case. Capacitor
technology affects power density, losses and cost.

## A. Selection of the DC-link Capacitance

DC-link voltage can be modeled as reported in Eq. (1) (see also [3], [4]) where the term $\Delta u_{B,x}(t)$ refers to the time evolution of the twice line-frequency ripple (i.e. $\propto \sin(2\omega t + \psi_0)$), whereas $|\Delta u_{B,x}|$ indicates the peak of said fluctuation.

$$U_{B,x}(t) = \bar{u}_{B,x} + \Delta u_{B,x}(t) \quad (1)$$

$$|\Delta u_{B,x}| \approx \frac{P_o}{2\omega_g \bar{u}_{B,x} C_{B,x}} \quad (2)$$

The maximum value of $|\Delta u_{B,x}|$ depends on the average DC-link voltage, two times the line-frequency ($2\omega$, which is 100 Hz for the European grid), the DC-link capacitance $C_{B,x}$ and the output power $P_o$. The specific values adopted in the two design options considered in this paper are provided in Tab. I.

<table><caption>**Table I: Converter and Circuit Specifications**</caption><thead><tr><th>Description</th><th>Symbol</th><th>Value</th></tr></thead><tbody><tr><td>Nominal grid voltage</td><td>$u_{ac}$</td><td>230 Vrms</td></tr><tr><td>Max. 1-Φ power rating per module</td><td>$P_o$</td><td>2.4 kW</td></tr><tr><td>Max. 3-Φ power rating per module</td><td>$P_o$</td><td>3.6 kW</td></tr><tr><td>Grid frequency</td><td>$f_{ac}$</td><td>50 Hz</td></tr></tbody></table>

The topology presented in Fig. 1 is designed to maintain constant power across each DCX port. In the case the system is operated in 3-Φ, the adoption of a third harmonic injection technique allows a reduction of the energy storage requirement by roughly 40%, as reported in [2]. Consequently, the 1-Φ case is the most critical and will be the primary focus of the investigations discussed hereafter.

In Tab. II a summary of the possible configurations adopting two different device classes (i.e., 750 V and 1200 V) are considered, aiming at defining allowable maximum and minimum DC-link voltages, as well as the average boosting voltage, thus leading to the actual selection of the DC-link capacitance. The higher voltage solution obviously requires smaller capacitance, hinting that it could possibly result in a design solution with increased power density.

Nonetheless higher fluctuation on the DC-link voltage would increase the losses on the inductors due to higher Volt-second application. Moreover, higher voltage rated devices are notably more lossy with respect to lower voltage ones (once switching frequency and $R_{ds,ON}$ are fixed). A trade-off is likely to take place since the 750 V option requires higher capacitance but smaller inductive

<table><caption>**Table II: Two cases with two different device classes compared.**</caption><thead><tr><th>Description</th><th>Symbol</th><th colspan="2">Value</th></tr></thead><tbody><tr><td>Voltage class device</td><td>$U_{bd}$</td><td>○ 750 V</td><td>◇ 1.2 kV</td></tr><tr><td>Maximum DC-link voltage</td><td>$U_{B,max}$</td><td>600 V</td><td>800 V</td></tr><tr><td>Minimum DC-link voltage</td><td>$U_{B,min}$</td><td>500 V</td><td>500 V</td></tr><tr><td>Average boosting voltage</td><td>$\bar{u}_B$</td><td>550 V</td><td>650 V</td></tr><tr><td>DC-link capacitor value</td><td>$C_{B,x}$</td><td>139 μF</td><td>39 μF</td></tr></tbody></table>

elements, mainly due the possibility of achieving higher switching frequencies, whereas the 1.2 kV version would show smaller capacitance but bigger magnetics.

## B. Selection of the Capacitor Technology

As highlighted in Tab. II, depending on which device class is used (750 V or 1.2 kV) the maximum allowed voltage fluctuation is either 100 V or 300 V in 1-Φ operation and 2.4 kW output power (per phase). Once the allowed fluctuation $\Delta u_{B,x}$ is decided, inversion of Eq. (1) allows to design the needed DC-link capacitance, (3).

$$C_{B,x} \ge \frac{P_o}{2\omega_g \bar{u}_{B,x} \Delta u_{B,x}} \quad (3)$$

Three possible technologies for designing the DC-link capacitor have been considered, namely MLCC-X6S, MLCC-X7T and CeraLink®, aiming at highlighting the available trade-offs between volumetric capacitance and loss densities with the adoption of 750 V breakdown voltage $V_{bd}$ power devices. Suitable configurations for the design of the DC-link capacitor bank are reported in Table III. The target capacitance of 139 μF has been considered for the evaluation, experiencing a voltage fluctuation between 500 V and 600 V around the average value 550 V, as already reported in Tab. II.

It is evident how the MLCC-X6S technology is far superior to all the others. From a capacitance density perspective, it comes very close to the best-in-class CeraLink® (B58035U5106M001) but the losses of X6S (C5750X6S2W225K250KA) are much smaller with respect to the CeraLink® ones at low frequencies (e.g., <150 Hz). This behaviour can be explained thanks to the high Equivalent Series Resistance (ESR) experienced by the CeraLink® capacitors at low-frequency (LF), i.e., in this case at twice the line-frequency. As compared to the X7T 630 V (CAA573X7T2J155M640LH), the X6S solution experience slightly higher losses, but quite an important improvement in terms of energy density.

As far as voltage rating compliance, either in the case 750 V or 1200 V power devices are used, the voltage across the DC-link capacitors can far exceed its maximum rated voltage, i.e., 450 V. Moreover, it's capaci-
<table><caption>**Table III:** Capacitance and loss density for different technologies suitable for DC-link capacitor design.</caption><thead><tr><th>Part number</th><th>Voltage rating (V)</th><th>Technology</th><th>Capacitance density (µF/cm³)</th><th>Loss density (mW/cm³)</th></tr></thead><tbody><tr><td>B58035U7505M001</td><td>700</td><td>CeraLink®</td><td>0.92</td><td>102</td></tr><tr><td>B58035U5106M001</td><td>500</td><td>CeraLink®</td><td>2.4</td><td>195</td></tr><tr><td>CAA573X7T2J155M640LH</td><td>630</td><td>MLCC-X7T</td><td>1.69</td><td>5.94</td></tr><tr><td>CKG57NX7T2W225M500JH</td><td>450</td><td>MLCC-X7T</td><td>1.62</td><td>9.26</td></tr><tr><td>C5750X6S2W225K250KA</td><td>450</td><td>MLCC-X6S</td><td>2.25</td><td>7.73</td></tr></tbody></table>

<figure><img src="image_3.png" /><figcaption>**Figure 2:** DC-voltage bias characteristic of a single capacitor chip (C5750X6S2W225K250KA [7]). In the figure the design of capacitor bank for bulk storage is illustrated, as well as the DC-biasing point of a single chip under the operating conditions highlighted in Tab. II.</figcaption></figure>

tance characteristic exhibits strong non-linear behavior as a function of the applied direct current (DC) voltage. For this reason, two capacitors must be connected in series for voltage sharing purposes, and finally as many branches as needed must be paralleled to reach the capacitance target (namely 139 µF), as illustrated in Fig. 2.

### III. MULTI-OBJECTIVE OPTIMIZATION

A multi-objective optimization procedure (hybrid analytical and time-domain simulation-based) has been designed targeting at obtaining the most effective implementation as far as loss and volume trade-off. The strategy adopted for evaluating different configurations is depicted in Fig. 3.

A first selection has to be made, i.e., choosing the power devices voltage rating, since it affects the design of the DC-link capacitance based on the allowable voltage swings, as discussed in Section II-B and reported in Tab. II.

Then, the boost and buck stages are optimized considering the following degrees of freedom: switching frequency (swept from 50 kHz to 200 kHz in both stages), boost inductor ($L_x$) design, buck inductor ($L_{B,x}$) design, output capacitor ($C_o$). The inductors ($L_x$ and $L_{B,x}$) are designed in order to achieve continuous conduction mode (CCM) operation while minimizing the losses [8], while for the output capacitor ($C_o$) CeraLink® is chosen since only high-frequency (HF) content is filtered.

<figure><img src="image_4.png" /><figcaption>**Figure 3:** Multi-objective optimization flowchart.</figcaption></figure>

#### A. Boost PFC Stage Optimization

Multiple magnetic materials and core shapes have been considered in the optimization procedure for the boost PFC as well as the SCB-PPB inductors selection. Generally if a small number of turns is used, a small inductance is obtained. In this scenario, likely very high current ripple is superimposed on the grid current, making the copper losses in the inductor (mainly the alternating current (AC) components) high due to their big RMS value. Moreover, low number of turns also means that high-flux density is present ultimately making the core
losses high as well. Conversely, if the number of turns is made excessively high, it necessitates the use of very thin wires due to winding window constraints. This, combined with the large number of turns, results in significantly high copper losses, while the core losses may become insignificant since the flux density is decreased. Finally, for each core shape and material selection, an optimal number of turns that minimizes the overall losses of the inductor can be found.

The design strategy considered for the boost inductor is reported in the flowchart of Fig. 4.

<figure><img src="image_5.png" /><figcaption>Figure 4: Boost inductor optimization flowchart.</figcaption></figure>

Once the core shape and material have been selected, it is possible to sweep the number of turns $N$ and to compute the inductance profile as a function of the average value $\bar{i}_x$ of the grid current, i.e., the inductance in relation to the grid phase angle, at a given fundamental component magnitude. Note how the symbol $\bar{i}_x$ is used to identify the grid current averaged in a switching cycle, meaning that only the grid frequency content is highlighted when using said notation (4).

$$ \bar{i}_a(t) \triangleq \frac{1}{T_{sw}} \int_{t}^{t+T_{sw}} i_a(\tau) d\tau \quad (4) $$

Then, the (instantaneous) boost current $i_x(t)$ and flux density $B(t)$ waveforms can be computed. A finite element analysis (FEA) tool is adopted to estimate the AC resistance at the selected switching frequency

and estimate the copper losses. The core losses are estimated using the improved Generalized Steinmetz Equation (iGSE) [9]. In [10] a detailed thermal analysis of a 1-Φ 7.2 kW OBC is carried out, in which the estimated hotspot temperature of the boost inductor stays below 50°C when operated at 20 W total losses, water inlet temperature 20°C. This would give an estimated thermal resistance of $R_{th} \approx 1.5$ K/W. Due to a similar cooling system adopted in this work, it is then assumed that (before having availability of fully detailed thermal analysis), this number can be reasonably adopted for a device pre-selection. It is thus chosen an upper boundary regarding the maximum temperature increase, set to 30°C.

In Fig. 5 a case study for a EQ32-L101 core shape is illustrated (dimensions are reported in Fig. 6), in which 100 kHz operating frequency is used. The four images Fig. 5a-d display the losses of the boost inductor in nominal operating conditions while the number of turns is varied, each for a different material. For this design no airgap is used and the windings are designed using flat wires. The loss profile of each configuration is then compared and it is finally concluded that, by adopting EQ32-L101 core, the solution with 45 turns on 60u material is the most efficient (see Fig. 7).

## B. Series Connected Buck-type Pulsating Power Buffer Optimization

The design of the SCB - PPB follows similarly to the one for the PFC. Different 750 V power devices, different core shapes, materials, inductance values $L_{B,x}$ and switching frequencies $f_{sw,boost}$ are swept to achieve a minimized volume.

The goal of the SCB-PPB is, differently from what happens in commonly adopted power buffer topologies [11]–[13] where the ultimate objective is to store the fluctuating energy and flatten the DC-link voltage $U_{B,x}$, to create a constant voltage $U_{o,x}$ starting from a fluctuating source $U_{B,x}$ as expressed in Eq. (1).

The fluctuation of the input voltage of the SCB-PPB (namely $U_{B,x}$) results in additional losses on the magnetic components (fluctuating Volt-second and current ripple profile) and on power devices (fluctuating turn-on and turn-off switching voltage). All These effects have been considered in the analysis/optimization.

# IV. SIMULATIONS AND RESULTS

The analytical and time domain simulation based models used for the illustrated optimization are illustrated within this Section, referring to the a phase of the converter. From Eq. (1) the voltage on the DC-link is known,
<figure><img src="image_6.png" /></figure>

<figure><img src="image_7.png" /></figure>

<figure><img src="image_8.png" /></figure>

<figure><img src="image_9.png" /><figcaption>Figure 5: Losses of boost inductor EQ32 L101 with different materials, namely a) KoolMu 26u, b) KoolMu 40u, c) KoolMu 60u and d) KoolMu 90u. The number of turns is swept in order to evaluate copper and core losses in each design point, with the aim to minimize total losses.</figcaption></figure>

<figure><img src="image_10.png" /><figcaption>Figure 6: EQ32 L101 core dimensions.</figcaption></figure>

meaning that it is possible to study the duty-cycle and the ripple of the grid current (being angle dependent).

$$d_{\text{PFC}}(t) = \begin{cases} 1 - \frac{u_a(t)}{U_{\text{B,a}}(t)} & \text{if } u_a(t) > 0 \\ \frac{|u_a(t)|}{U_{\text{B,a}}(t)} & \text{if } u_a(t) \le 0 \end{cases} \quad (5)$$

<figure><img src="image_11.png" /><figcaption>Figure 7: EQ32 L101 overall loss comparison: the solution with 45 turns and 60u material results the lowest overall losses.</figcaption></figure>

$$\Delta i_a(t) = \frac{U_{\text{B,a}}(t) d_{\text{PFC}}(t) (1 - d_{\text{PFC}}(t))}{f_{\text{sw,boost}} L_a (\bar{i}_a(t))} \quad (6)$$
Eq. (6) illustrates the peak-to-peak current ripple on the boost current as a function of the boosted voltage $U_{B,a}(t)$, duty cycle $d_{PFC}(t)$ as in Eq. (5), and inductance value as a function of the average grid current $\bar{i}_a$.

<figure><img src="image_12.png" /><figcaption>**Figure 8:** PFC waveforms analytical simulations, obtained solving Eqs. (1)-(6). In **a)** the (rectified) grid voltage $u_a$ and the boosted voltage $U_{B,a}$ are shown. In **b)** the grid current $i_a$ and its averaged value $\bar{i}_a$ are displayed. In **c)** the inductance profile of the boost choke $L_a$ as a function of the grid angle is illustrated.</figcaption></figure>

Then it is possible to write the (total) grid current as reported in Eq. (7) (i.e., instantaneous value is equal to the local average plus the ripple component) and to calculate its RMS value, which will then be used for the calculation of the conduction losses in the inductor windings and the power semiconductor.

$$i_a(t) = \bar{i}_a(t) + \Delta i_a(t) \quad (7)$$

The boost inductance is a function of the LF-current operating point, i.e. its value depends on the grid current and its dependence is a property of the material with which the inductor is built.

The result of PFC operation (described by equations (1)-(6) are illustrated in Fig. 8, where the boost voltage fluctuation at 100 Hz is highlighted (Fig. 8a) to be between 500 V and 600 V. This result is obtained by having the PFC controlled to provide an average boosted voltage of $\bar{u}_{B,a}$ equal to 550 V, while the DC-link capacitance has been set to 139 µF (Tab. II). In Fig. 8b the grid current with the associated ripple is shown, where the red dashed line indicates the low-frequency content of said current,

i.e., $\bar{i}_a(t)$. Finally, the inductance value as a function of grid angle is displayed in Fig. 8c. It is worth noticing that the inductance value is updated only based on the local average current $\bar{i}_a(t)$, without taking the actual current ripple $\Delta i_a(t)$ into account, which has been considered a good approximation for the loss evaluation and MOO. These results are specifically obtained considering a grid voltage of 230 Vrms with an average power absorption of 2.4 kW (needed in 1-Φ operation per module to achieve the 7.2 kW overall power). The high-frequency leg of the PFC converter switches at 100 kHz. The boost inductor characteristic considered for this simulation results is the one obtained in the previous section, i.e., EQ32-L101 in KoolMu-60u material with flat-wire and 45 turns.

Main operational equations for the SCB-PPB are reported in (8)-(10), where the buck switching frequency is $f_{sw,buck}$ and the inductance is $L_{B,a}$.

RMS of the grid current is computed at each switching period by considering a simple triangular approximation of the current ripple, which is then extended to half the fundamental period $T_{half} = 10$ ms of the grid current by summing up all the individual contributions. The index $k$ is introduced to refer to the $k^{th}$ switching period during an half grid-cycle, the total number calculation periods being $K = T_{half} f_{sw,buck}$. $U_{B,a}(k)$ and $U_{o,a}(k)$ are the input and output voltages of the SCB-PPB sampled at the $k^{th}$ switching period, respectively.

$$d_{PPB}(k) = \frac{U_{o,a}(k)}{U_{B,a}(k)} \quad (8)$$

$$\Delta i_{B,a}(k) = \frac{U_{B,a}(k) d_{PPB}(k) (1 - d_{PPB}(k))}{L_{B,a} f_{sw,buck}} \quad (9)$$

$$i_{B,rms,a} = \sqrt{\frac{1}{K} \sum_{k=1}^{K} \left( I_{dc}^{2} + \frac{\Delta i_{B,a}(k)^{2}}{12} \right)} \quad (10)$$

Equations (8)-(10) are adopted in the optimization procedure to compute conduction losses, switching losses and losses in the inductor core. The results of the analysis are reported in Fig. 9. Three colored loss maps (and contour plots) are shown in the figure, namely the inductor losses, the semiconductor losses (including conduction and switching) and the total losses, each one represented as a function of the buck switching frequency $f_{sw,buck}$ and the inductance $L_{B,a}$. One can notice the different effects of the switching frequency and the inductance on the individual loss components. A yellow star is highlighting the optimal design choice leading to minimum total losses.

The global optimization of the converter by a Pareto-front analysis of all possible design options (including
<figure><img src="image_13.png" /><figcaption>**Figure 9:** Results of the Pareto-front optimization of the SCB-PPB components analysis for a) inductor losses, b) semiconductor losses and c) total losses. The colored bar on the right side of each diagram and contour lines in the figure visually represent the loss values in [W].</figcaption></figure>

<table><caption>**Table IV:** Selected design summary.</caption><thead><tr><th>Part</th><th>Symbol</th><th>Loss (W)</th><th>Volume (cm³)</th><th>Description</th></tr></thead><tbody><tr><td>Boost inductor</td><td>L<sub>a</sub></td><td>17.8</td><td>15.5</td><td>EQ32-L101 KoolMu60, 45 turns, 400 µH (unbiased)</td></tr><tr><td>PPB inductor</td><td>L<sub>B,a</sub></td><td>11.6</td><td>6.25</td><td>EQ26-L124 KoolMu60, 47 turns, 169 µH</td></tr><tr><td>Bulk capacitor</td><td>C<sub>B,a</sub></td><td>0.6</td><td>34</td><td>480 MLCC-X6S (C5750X6S2W225K250KA [7])<br>139 µF (biased)</td></tr><tr><td>Output capacitor</td><td>C<sub>o,a</sub></td><td>0.05</td><td>4</td><td>2 × CeraLink B58035U5106M001</td></tr><tr><td>Devices</td><td>S<sub>1÷6</sub></td><td>35</td><td>-</td><td>6 × AIMDQ75R016M1H (16 mΩ SiC, U<sub>bd</sub> = 750 V)</td></tr></tbody></table>

<figure><img src="image_14.png" /><figcaption>**Figure 10:** Pareto-plot of the multi-objective optimization.</figcaption></figure>

<figure><img src="image_15.png" /><figcaption>**Figure 11:** Circuit simulation result of the chosen design comprising a) the DC-link voltage $U_{B,a}$ and the buck stage output voltage $U_{o,a}$ and b) the buck input current $i_{B,a}$ and output current $i_{o,a}$. The figure illustrates an output power $P_{o,a}$ of 2.4 kW.</figcaption></figure>

the two breakdown voltages of the power devices and as already discussed in Section III and Fig. 3) is then considered, the results being reported in Fig. 10. It is evident that the 1.2 kV device option (even though potentially allowing smaller DC-link capacitance) is inferior when compared with the 750 V one, due to their intrinsic higher losses. This limits the operating frequency and finally the possibility of adopting small cores for the

inductor designs. The optimal and selected design option is highlighted in the same plot with a yellow star. The voltage at the output of the buck stage $U_{o,a}$ must be controlled within 250 to 450 V, due to the varying voltage of the connected high voltage battery (in turn being a function of its state-of-charge (SoC)), due to the utilization of a DCX with a conversion ratio of 1 (i.e., 1:1 primary-to-secondary turns ratio). The grid voltage can vary in the range 184 to 276 Vrms in order
to accommodate both the rated value (in Europe) of 230 Vrms and allowing a swing within a the standard tolerance range of ±20%.

Time-domain simulations related to the optimal design option recalled above are reported in Fig. 11, with rated grid voltage of $u_a$ = 230 Vrms, output voltage (battery voltage) $U_{o,a}$ = 250 V and output power $P_{o,a}$ = 2.4 kW. The high-frequency PFC leg switching frequency is 100 kHz, whereas the integrated active buffer buck stage switches at 77 kHz as per result illustrated in Fig. 9. One can notice that the input voltage of the buck stage $U_{B,a}$ (i.e., the DC-link voltage) is let fluctuating within the chosen range, whilst the output voltage $U_{o,a}$ keeps a constant value of 250 V thanks to the SCB-PPB operation.

To verify whether the closed-loop control is able to dynamically maintain the DC-link voltage above the grid voltage peak thus retaining controllability of the output current, a dynamic test has also been conducted in simulation. Test results are reported in Figure 12. A step-wise output current increase from 3 A to 6 A is commanded at 0.3 s, whereas the output voltage $U_{o,a}$ is kept constant at 400 V, i.e., the power level reference value shift from $P_{o,a}^* = 1.2$ kW to $P_{o,a}^* = 2.4$ kW, i.e., 50% to 100% of the rated power. One can notice that control of the grid current $i_a$ does not experience any critical behavior during the transient conditions, even though the DC-link voltage drops temporarily below the required output voltage.

Further investigations are ongoing to improve the PFC control to get rid of the transient under voltage condition and keep the output voltage always above the battery voltage.

The results of the testing and measurement are subject to future investigations, but the first implementation details for the selected components from Tab. IV are already available.

A prototype of the proposed system has been designed and built, main views are shown in Fig. 13¹. The adopted capacitor bank for $C_{B,x}$ is shown in Fig. 14, whilst the part numbers of the adopted components and their relative loss and volume occupation are shown in Table IV. Note that the PCB outlined in Fig. 14 is referred to only one half of the required bank and needs two PCBs to be connected in series, as indicated in Fig. 2 to handle the intended DC-bus voltage $U_{B,a}$. While the outlined PCB primarily serves as a functional demonstrator rather than a high power density example, the choice and

<figure><img src="image_16.png" /><figcaption>**Figure 12:** A load jump at 0.3 s for an output voltage of $U_{o,a}$ = 400 V from $P_{o,a}^* = 1.2$ kW to $P_{o,a}^* = 2.4$ kW is illustrated. Showing **a**) the DC-link voltage $U_{B,a}$, **b**) the grid current $i_a$ and its control reference value $i_a^*$ and **c**) the buck stage current $i_{B,a}$ and the output current $i_{o,a}$.</figcaption></figure>

configuration of components provide a strong indication of its potential for compact implementation.

## V. CONCLUSIONS AND FUTURE WORK

A two-stage bidirectional Power Factor Correction (PFC) boost-buck topology featuring a novel built-in energy storage buffer functionality specifically tailored for (isolated) OBC applications has been presented in this paper. The introduction of a series connected buck stage at the output of the boost PFC allows to absorb the pulsating energy at twice the line frequency coming from the single-phase AC input and passing through the boost PFC stage, and to supply a stiff voltage for the multi-port DCX stage feeding the battery. In this way, a certain amount of voltage oscillation at the output of the boost PFC stage is allowed, leading to a significant reduction of the dc-bus capacitor (size and capacitance). The paper has demonstrated that it is possible to obtain an effective balance between bulk capacitance and inductive components against losses and switching frequencies through an accurate MOO process, thus achieving peak power density of the overall system. Actual power semiconductor technologies (750 V or 1.2 kV) have also been taken into account in the optimization process, leading to the conclusion that 750 V devices allow a better exploitation of the loss/volume design space. Comprehensive analytical and simulation results have been reported aiming at validating the effectiveness of the proposal, together with

<footnote n="1">¹The semiconductor hardware employed has already been investigated and implemented in [14].</footnote>
a sketch of the actual experimental prototype. Additional
simulations in a variety of steady-state and transient
operating conditions will be considered as future work,
including full experimental validation of the proposal.

<figure><img src="image_17.png" /><figcaption>**Figure 13:** Hardware prototype parts illustrating in **a**) the top view of the PCB showing the passive components and the connection terminals. In **b**) the side view of the two stacked PCBs and in **c**) the bottom view outlining the power semiconductors of the TP PFC and the buck stage are shown.</figcaption></figure>

<figure><img src="image_18.png" /><figcaption>**Figure 14:** Capacitors bank for $C_{B,a}$ comprising 240 ceramic MLCCs capacitors shown from the **a**) top view and **b**) side view.</figcaption></figure>

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