# Permanent degradation of p-GaN HEMTs due to repetitive overvoltage stress during hard turn-off switching

Thomas Vadebout, Pascal Bevilacqua, Valeria Rustichelli, Maroun Alam, Laurence Allirand, Hervé Morel

► To cite this version:

Thomas Vadebout, Pascal Bevilacqua, Valeria Rustichelli, Maroun Alam, Laurence Allirand, et al. Permanent degradation of p-GaN HEMTs due to repetitive overvoltage stress during hard turn-off switching. Microelectronics Reliability, 2026, 178, pp.116024. 10.1016/j.microrel.2026.116024. hal-05507060

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Submitted on 12 Feb 2026

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Research paper

# Permanent degradation of p-GaN HEMTs due to repetitive overvoltage stress during hard turn-off switching☆

Thomas Vadebout a,*, Pascal Bevilacqua $^{a}$, Valeria Rustichelli $^{b}$, Maroun Alam$^{b}$,
Laurence Allirand $^{c}$, Hervé Morel a

ARTICLE INFO

Keywords:

GaN HEMT

Reliability

Drain overvoltage

Dynamic breakdown

Degradation mechanisms

UIS3

A B S T R A C T

This study investigates the long-term impact of dynamic overvoltage stress on GaN HEMTs using a newly designed test circuit, UIS3, a variant of classic UIS, which isolates key stress factors. Devices were subjected to short-duration repetitive overvoltage stress near and below their dynamic breakdown voltage. Characterization before and after stress reveals permanent degradation in C<sub>DS</sub>, I<sub>DSS</sub> and I<sub>GSS</sub>, suggesting deep-trapping or structural damage within the device. A distinct alteration in the C<sub>DS</sub> curve is observed, may indicate less spreading of the electric-field within the device. R<sub>DS,on</sub> degradation is also noted, likely due to trapping effects, with partial recovery at room temperature. Higher stress levels accelerate failure. Waveform analysis and post-failure characterization indicate a short-circuit failure mode, likely due to partial dielectric breakdown during overvoltage events. These results provide new insights into GaN HEMT degradation mechanisms under high-voltage stress.

1. Introduction

GaN HEMTs are gaining popularity in power applications due to their superior performance compared to silicon-based technologies [1]. However, the lack of accurate aging models hinders their broader adoption in the industry. As a result, the reliability of GaN HEMTs remains a major research topic.

Unlike silicon (Si) and silicon carbide (SiC) components, GaN HEMTs lack avalanche capability [2], raising concerns about their robustness against voltage spikes that can occur in real-world applications. These transient overvoltages, often unavoidable due to parasitic inductances in circuits, could potentially affect the long-term reliability of GaN devices. Although prior research has explored this issue [2–4], further investigation is needed to better understand the underlying mechanisms and improve degradation prediction models.

Overvoltage events in GaN power devices involve two distinct types of stress: dynamic overvoltage stress, which can arise in various situations such as during the hard-switching transition, and reverse-bias voltage stress applied in the OFF-state. The commonly used Unclamped Inductive Switching (UIS) test [2–4] does not allow these two contributions to be separated, as both are simultaneously present during the test. This limitation is particularly critical for GaN HEMTs, which

are highly sensitive to OFF-state reverse-bias stress [5], making it difficult to isolate the specific role of dynamic overvoltage on device degradation. The literature also emphasizes the importance of studying dynamic breakdown, since devices can withstand significantly higher voltages when the overvoltage duration is short [3].

In addition to distinguishing between dynamic overvoltage stress and OFF-state reverse-bias stress, it is also important to isolate the impact of temperature. Previous studies have reported potential thermal degradation in GaN HEMTs, often associated with an increase in R<sub>DS,on</sub> over the duration of the test [6]. During repetitive stress events, the DUT temperature may rise due to the time spent in conduction mode while charging the inductor in the UIS, potentially confounding the interpretation of purely electrical degradation mechanisms. Thus, careful control and consideration of thermal effects are essential to accurately assess the impact of dynamic overvoltage stress on device degradation.

This article is an extended version of [7], where preliminary results were presented.

In this article, a new test circuit that combines the principles of UIS and DST (Double Source Test) [8] is proposed to better distinguish the different stress factors and minimize conduction time of DUT. Its operating principle, DUT and the test setup will be outlined in Section 2.

<footnote>a INSA Lyon, Université Claude Bernard Lyon 1, Centrale Lyon, CNRS, Ampère, Villeurbanne, F-69621, France</footnote>

<footnote>b IRT Saint Exupery, Toulouse, F-31400, France</footnote>

<footnote>c Schaeffler, Toulouse, F-31100, France</footnote>

<footnote>☆ This article is part of a Special issue entitled: 'ESREF2025' published in Microelectronics Reliability.</footnote>

<footnote>* Corresponding author.
E-mail address: thomas.vadebout@insa-lyon.fr (T. Vadebout).</footnote>
<figure><img src="image_2.png" /><figcaption>Fig. 1. UIS3 circuit schematic.</figcaption></figure>

<figure><img src="image_3.png" /><figcaption>Fig. 2. UIS3 testbench photo.</figcaption></figure>

Results from its use will be presented in Section 3. In Section 4, an analysis of the hypothesis of the phenomena affecting the device based on the observed results is proposed.

## 2. Device under test and test setup

### 2.1. DUT: p-GaN HEMT 650 V - 30 A device

The device tested in this article is a commercial p-GaN HEMT with Schottky gate contact rated for a drain-source voltage of up to 650 V and a maximum drain-source current of 30 A. Field plates are used to enhance its ability to withstand high drain-source voltages [9]. Device packaging is PDFN 8 × 8.

To ensure accurate measurements, a Golden Device (GD) is used, which is not subjected to stress but undergoes characterization before and after the stress tests. This allows us to identify any potential drift caused by the characterization system itself.

### 2.2. Unclamped inductive switching, supply switched: UIS3

The developed stress circuit, presented in Fig. 1, uses a half-bridge of transistors $M_H$ and $M_L$ to couple the DUT to a voltage source and charge inductance $L_{circuit}$, or decouple it to dissipate the energy. This circuit is referred to as UIS3. In contrast to UIS, at OFF-state, no $V_{DS}$ is applied to the DUT, allowing to isolate the overvoltage stress from the reverse-bias stress. This half-bridge also allows for soft-switching ON the DUT, minimizing thermal stress during the stress cycle. To further reduce thermal stress, the conduction time is set to 250 ns, which is long enough to charge the inductor to the desired current level but short enough to minimize self-heating.

Fig. 2 shows a photo of the setup built. Table 1 reports the different phases of one cycle performed by the setup. The device undergoes several identical stress cycles until failure. Fig. 3 illustrates the equivalent

<figure><img src="image_4.png" /><figcaption>Fig. 3. UIS3 testbench operation phases.</figcaption></figure>

circuit of each phase, while Fig. 4 shows the waveform during phases 2 to 5.

The inductor $L_{circuit}$ is made using a short-circuited LMR400 transmission line, providing a low and adjustable inductance (approximately 20 nH for 10 cm), ideal for high-frequency operation and low inductance values.

Oscilloscope measurements of $V_{DS}$, $V_{GS}$, and $I_D$ are taken during the stress tests to monitor the DUT behavior in real-time. A secondary advantage of the UIS3 is to allow the measurement of $Dy nR_{DS,on}$ [10] during the stress test, providing additional insight into the device condition. To implement this, two identical high voltage probes are used to measure $V_{DS}$. One probe focuses on the high-voltage measurement of the peak and the other on the low-voltage measurement of the conduction. As UIS3 do not apply any voltage during the OFF-state, the low-voltage probe channel has time to recover after the high-voltage event. This technique allows to not use a clamping circuit like it is done in literature [10], which would add parasitic that would disturb the measurement and make measurements possible only after some time delays.

The values of $L_{circuit}$ and $R_{circuit}$ has been characterized depending on the length of the transmission line $d_{tl}$ as follows:

$$L_{circuit}(\text{nH}) = 55.4 + 2.2 \cdot d_{tl}(\text{cm}) \qquad (1)$$

$$R_{circuit}(\text{m}\Omega) = 137.7 + 0.7 \cdot d_{tl}(\text{cm}) \qquad (2)$$

### 2.3. Characterization setup

The characterization system used is a Keithley 4200A-SCS, a high-voltage SMU 2657 A for drain DC polarization, a SMU 2636B with two channel for gate and source DC polarization. The 4215-CVU capacitance-voltage unit is used to measure capacitances. The 8020 interface panel is used to couple AC signals for capacitance measurements with a DC polarization.
<figure><img src="image_5.png" /><figcaption>Fig. 4. An U1S3 cycle with zoom on the overvoltage event.</figcaption></figure>

<table><caption>**Table 1**
Phases of a U1S3 cycle.</caption><thead><tr><td>Phase</td><td>DUT</td><td>Half-bridge</td><td>Description</td></tr></thead><tbody><tr><td>1</td><td>OFF</td><td>Low ON</td><td>DUT is at rest with V<sub>DS</sub> at zero, allowing the temperature to decrease.</td></tr><tr><td>2</td><td>ON</td><td>Low ON</td><td>DUT switches to ON state with V<sub>DS</sub> at zero. Therefore, no losses are generated during switching.</td></tr><tr><td>3</td><td>ON</td><td>High ON</td><td>Current flows, and inductor L<sub>circuit</sub> is charged. The slope of the current ramp is adjustable with V<sub>sup</sub>. <sup>di</sup>/<sub>di</sub> ≈ V<sub>sup</sub>/L<sub>circuit</sub>.</td></tr><tr><td>4</td><td>OFF</td><td>High ON</td><td>DUT switches to OFF state, and the energy stored in inductor L<sub>circuit</sub> is dissipated in the C<sub>ons</sub> capacitance of the DUT.</td></tr><tr><td>5</td><td>OFF</td><td>Low ON</td><td>After the overvoltage, the half-bridge switches, and the resulting RLC circuit dissipates the stored energy with R<sub>discharge</sub> adjusted for critical damping.</td></tr></tbody></table>

DUT and the GD are both characterized before and after the stress tests.

The characterization procedure follows this sequence:

* $V_{th}$ without preconditioning

* $R_{DS,on}$ ($I_D$ = 100 mA, $V_{GS}$ = 6 V)

* $V_{th}$ with preconditioning [11,12]

* $C_{DS}$ vs. $V_{GS}$ (sweep from -3 V to 6 V at 0.2 V s⁻¹)

* $C_{DS}$ vs. $V_{DS}$ (sweep from 0 V to 600 V at 6 V s⁻¹)

* $C_{GD}$ and $I_{GSS}$ vs. $V_{GS}$ (sweep from -3 V to 6 V at 70 mV s⁻¹)

* $C_{GD}$ and $I_{DSS}$ vs. $V_{DS}$ (sweep from 0 V to 600 V at 2 V s⁻¹)

* $C_{GS}$ vs. $V_{GS}$ (sweep from -3 V to 6 V at 0.2 V s⁻¹)

* $C_{GS}$ vs. $V_{DS}$ (sweep from 0 V to 600 V at 6 V s⁻¹)

* $R_{DS,on}$ ($I_D$ = 100 mA, $V_{GS}$ = 6 V)

* $V_{th}$ with preconditioning [11,12]

All capacitance measurements are performed at 100 kHz with an AC signal of 100 mV. All measurements are performed at ambient temperature.

## 2.4. The applied stress

The stress cycle waveforms are outlined in Fig. 4.

For each device under test (DUT), the stress cycle is repeated every 1 ms (1 kHz) for a specified duration. This frequency was selected to ensure sufficient cooling time during the OFF-state. The stress frequency $f_{stress}$ is either 1 kHz or 2 Hz, depending on the applied stress level. Higher stress levels, i.e., those closer to $V_{BR,dyn}$, are applied at a lower frequency (2 Hz) to obtain a more accurate estimate of the number of cycles to failure. DUTs stressed at 2 Hz were previously tested at 1 kHz, where failure occurred so rapidly that the number of cycles to failure could not be determined. Therefore, the frequency was reduced to 2 Hz for higher stress levels. The results obtained at 2 Hz are consistent in magnitude with those measured at 1 kHz. Moreover, at 2 Hz, all oscilloscope waveforms can be recorded, allowing the failure process to be observed in real time (as shown in Section 3.3). Thermal considerations are discussed in the next section (Section 2.5).

An overvoltage, $V_{DS,peak}$, is applied at a fixed peak current, $I_{D,switch}$. Through preliminary testing on other DUTs of the same type, the maximum dynamic breakdown drain-source voltage $V_{BR,dyn}$ has been experimentally determined to be approximately 1.43 kV. At this voltage, a single event is sufficient to make the device fail in short-circuit, as it instantly reaches a dielectric breakdown. This finding is consistent with what is reported in the literature for this type of device [3]. Based on this, DUTs are tested near the breakdown voltage using repetitive overvoltages.

The stress conditions applied to each DUT are detailed in Table 2. The minimum voltage applied is 1.3 kV (approximately 90% of $V_{BR,dyn}$), while the maximum voltage applied is 1.42 kV (approximately 99% of $V_{BR,dyn}$). To achieve the desired $V_{DS-peak}$, the inductance $L_1$ and the bus voltage $V_1$ were adjusted to maintain the same $\frac{di}{dt}$ across $L_1$. The conduction time (Phase 3 of Fig. 4) of the DUT is 250 ns for all tests. Since $i_D(t)$ in phase 3 is the same for all test case, conduction losses in the DUT are identical for each test case.

## 2.5. Thermal considerations

Temperature is an accelerator of degradations phenomena [13].

The objective is to focus only on the impact of the dynamic overvoltage stress on the DUT. To achieve this, the thermal stress during the test is minimized by reducing the conduction time of the DUT to $t_{cond}$ = 250 ns, soft-turning ON the DUT, and by allowing sufficient cooling time during the OFF-state.

The worst case thermal scenario in this paper is considering a $I_{D,switch}$ of 20 A and a $L_{circuit}$ of 750 nH at 1 kHz repetition rate.

A theoretical estimation of the maximum temperature rise of the active-area of the device during stress is performed as follows. Within
<table><caption>**Table 2**
List of DUTs.</caption><thead><tr><th>DUT</th><th><i>I</i><sub>D,switch</sub></th><th><i>L</i><sub>circuit</sub></th><th><i>V</i><sub>DS,peak</sub></th><th><i>f</i><sub>stress</sub></th></tr></thead><tbody><tr><td>G1</td><td>20 A</td><td>580 nH</td><td>1300 V</td><td>1 kHz</td></tr><tr><td>G2</td><td>20 A</td><td>670 nH</td><td>1320 V</td><td>1 kHz</td></tr><tr><td>G3</td><td>20 A</td><td>740 nH</td><td>1355 V</td><td>1 kHz</td></tr><tr><td>G4</td><td>20 A</td><td>770 nH</td><td>1330 V</td><td>1 kHz</td></tr><tr><td>G5</td><td>20 A</td><td>770 nH</td><td>1335 V</td><td>1 kHz</td></tr><tr><td>G6</td><td>20 A</td><td>800 nH</td><td>1370 V</td><td>2 Hz</td></tr><tr><td>G7</td><td>20 A</td><td>800 nH</td><td>1385 V</td><td>2 Hz</td></tr><tr><td>G8</td><td>20 A</td><td>825 nH</td><td>1400 V</td><td>2 Hz</td></tr><tr><td>G9</td><td>20 A</td><td>825 nH</td><td>1410 V</td><td>2 Hz</td></tr></tbody></table>

the UIS3 cycle, two main phases contribute to energy dissipation: Phase 3, referred as the conduction phase, and Phase 4, referred to as the overvoltage phase. The power dissipated in the DUT during each conduction phase (phase 3) is calculated as:

$$P_{P3}(t) = DynR_{DS,on} \cdot i_D^2(t) \\ \leq \max(DynR_{DS,on}) \cdot \left( \frac{t \cdot I_{D,switch}}{t_{cond}} \right)^2 \quad (3)$$

The $\max(DynR_{DS,on})$ is considered at 200 mΩ to be conservative and is justified by the $DynR_{DS,on}$ evolution with the stress. $t$ represents the time since the beginning of the conduction phase.

The maximum energy dissipated during the overvoltage phase (Phase 4) is taken to be equal to the energy stored in the inductor $L_{circuit}$.

$$E_{P4} \leq E_{L_{circuit}} \\ = \frac{1}{2} \cdot L_{circuit} \cdot I_{D,switch}^2 \quad (4)$$

The power dissipated during overvoltage phase is maximized by considering all energy stored in the inductor is dissipated uniformly during the duration of the overvoltage:

$$P_{P4}(t) \leq \frac{L_{circuit} \cdot I_{D,switch}^2}{2 \cdot t_{P4 \to peak}} \quad (5)$$

$t$ represents the time since the beginning of the overvoltage phase. $t_{P4 \to peak}$ is the duration between beginning of overvoltage phase to overvoltage peak, which is $\approx 40$ ns.

By adding the two contributions, and by using the RC thermal model given by the device manufacturer, the maximum temperature rise of the device active-area during stress above case temperature is estimated at $\Delta T_{active \to case} = 1.8$ °C. This result is presented in Fig. 5 (solid lines). This estimation is conservative since it assumes that all the energy stored in the inductor is dissipated in the DUT, which is not the case in practice as a part of this energy will be stored in $C_{OSS}$ capacitance and then redistribute to the circuit in quadrant II operation, when $V_{DS}$ decrease after the overvoltage peak. The conduction phase account for 8%, while the overvoltage phase contributes to 92% of temperature rise.

Electro-thermal simulations using LTSpice have been conducted with the device spice model given by the manufacturer to estimate the temperature rise of the DUT during stress. By considering the worst case, the active-area temperature rise above the case temperature is estimated to be $\Delta T_{active \to case} = 0.7$ °C immediately after the overvoltage event. The simulation results are in good agreement with the developed theoretical maximization of the temperature model. This result is shown in Fig. 5 (dashed lines).

Case temperature has been measured during preliminary tests with a thermocouple placed above the DUT. In the worst-case scenario, after 1 h of stress at 1 kHz, the case temperature increased by $T_{case \to ambient} = 1$ °C above ambient temperature.

These considerations ensure that, during the stress tests, the active-area temperature of the device does not exceed $T_{active \to case}+T_{case \to ambient} = 2.8$ °C above ambient temperature.

Hence, the impact of temperature on the degradation of the DUT is considered negligible in this study.

<figure><img src="image_6.png" /><figcaption>**Fig. 5.** LTSpice simulation results showing the active-area temperature rise above the case temperature of the electro-thermal model (dashed lines), compared with the theoretical estimation (solid lines). Results correspond to a single UIS3 worst-case cycle after the device has reached the established thermal state.</figcaption></figure>

<figure><img src="image_7.png" /><figcaption>**Fig. 6.** Evolution of DUT parameters with increasing stress cycles, shown as percentage change relative to the initial (fresh) characterization.</figcaption></figure>

# 3. Results

## 3.1. Observed shifts in characterized parameters

The DUT highlighted in this section is DUT G1 from Table 2. However, all DUTs exhibit similar trends, at different rates depending on the stress conditions an DUT itself.

Drifts have been observed in the characterized parameters of stressed DUTs. Fig. 6 summarizes the evolution of the characterized parameters of one DUT as a function of the cumulative number of stress cycles.

$V_{th}$ do not show shift with the applied stress.

$I_{GSS}$ and $I_{DSS}$ show a slight decrease after stress. This decrease saturates after a few thousand stress cycles.

$R_{DS,on}$ and $C_{DS}$ show the most significant drifts. $R_{DS,on}$ increases with the number of stress cycles, nearly linearly with the number of stress cycles.

$C_{DS}$ shows a distinct drift pattern. Fig. 7 illustrates the evolution of the $C_{DS}$ vs. $V_{DS}$ characteristic of one DUT as a function of the cumulative number of stress cycles. A pocket shape appears between 200 V and 400 V, with a decrease in $C_{DS}$ at these voltages. This drift intensifies with the number of stress cycles.
<figure><img src="image_8.png" /><figcaption>Fig. 7. Evolution of the C<sub>DS</sub>-V<sub>DS</sub> characteristic as a function of cumulative stress cycles (Fresh curve is hidden by the 10k curve).</figcaption></figure>

<figure><img src="image_9.png" /><figcaption>Fig. 8. Recovery at ambient condition. Plot of recovery percent for characterized parameters for a non-failed DUT after 100 million cycles of stress.</figcaption></figure>

The others characterized parameters presented in Section 2.3 do not show significant drifts after stress.

## 3.2. Recovery

After the stress, the DUTs were left at ambient conditions for several weeks to observe any potential recovery in their characteristics. Fig. 8 presents the recovery for a non-failed DUT (G1 from Table 2). This DUT was stressed 100 million cycles and shifts were presented in Fig. 6.

In this case, no significant recovery is observed after 7 days at ambient conditions. After 2 months, a recovery of 65% of the R<sub>DS,on</sub> shift is observed. No recovery is observed for C<sub>DS</sub> and all the other parameters after 2 months. The shape of the C<sub>DS</sub> vs. V<sub>DS</sub> characteristic remains unchanged compared to the post-stress measurement, as shown in Fig. 7.

This suggests that the degradation mechanisms affecting C<sub>DS</sub>, I<sub>DSS</sub> and I<sub>GSS</sub> are more permanent compared to those impacting R<sub>DS,on</sub>.

DynR<sub>DS,on</sub>, measured from oscilloscope waveforms, evolves in the same manner as R<sub>DS,on</sub> obtained from static characterization.

## 3.3. Failure waveforms and post-failure characterization

Fig. 9 shows the measured V<sub>DS</sub> and I<sub>D</sub> waveforms for several UIS3 cycles N-3 through N+1, where N denotes the failure cycle, for device G6 from Table 2. All curves before failure are similar to the N-3 curve

<figure><img src="image_10.png" /><figcaption>Fig. 9. Measured drain-current (I<sub>D</sub>) and drain-to-source voltage (V<sub>DS</sub>) waveforms versus time for individual UIS3 cycles. The color indicates the device state relative to the failure event: blue — normal operation before failure, red — first failure event, green — second failure event (the cycle immediately following the first failure), and orange — post-failure behavior.</figcaption></figure>

(blue curve). During the failure event (red and green), there is a rise of current I<sub>D</sub> and a fast drop of voltage V<sub>DS</sub> when V<sub>DS</sub> is near the peak voltage. This may indicates a partial dielectric breakdown in the first failure event (red), leading to a lowering of breakdown voltage. In the second failure event (green), the device enters a permanent short-circuit state. After failure (orange), the device remains in a short-circuit state, with V<sub>DS</sub> close to zero and I<sub>D</sub> no more able to be controlled by the DUT. Hence, the I<sub>D</sub> decrease is done by the half bridge M<sub>H</sub> and M<sub>L</sub> MOSFETs.

A post characterization of all failed DUTs confirms this failure mode. A resistance like behavior is observed between every pads (the third one is at high impedance) : R<sub>DS</sub> of 24 Ω, R<sub>DG</sub> of 47 Ω and R<sub>GS</sub> of 25 Ω.

For this DUT, all the waveforms before failure where captured and are similar. There is no observed rise of DynR<sub>DS,on</sub> before failure. This suggests that this failure mode may not be directly linked to the DynR<sub>DS,on</sub> increase observed during stress.

## 3.4. Experimental generation of a failure curve

The Fig. 10 shows the number of cycles before failure for different V<sub>DS,peak</sub> values. The switching conduction current I<sub>D,switch</sub> is fixed at 20 A for all tested DUTs. The failure observed is the same for all DUTs. There is an inability to control the DUT, as the device remains in a continuously conducting state.

It was observed that more stress cycles can be endured by a device when the V<sub>DS,peak</sub> is lower.

With these data points, a preliminary failure curve is drawn in Fig. 10. The curve follows a trend similar to an exponential decay as the overvoltage amplitude increases. The equation of the curve is as follows:

$$N_{fail} \approx 10^{\frac{V_{BR,dyn} - V_{DS,peak}}{11.8 \text{ V}}} \qquad (6)$$

Where N<sub>fail</sub> is the number of cycles before failure, and V<sub>BR,dyn</sub> is the dynamic breakdown voltage, estimated at 1.43 kV for this DUT type.

This curve can be used to estimate the lifetime of the DUT under repetitive overvoltage stress at different amplitudes. By extrapolating
<figure><img src="image_11.png" /><figcaption>Fig. 10. The scatter plot shows the failure states of each DUT under 1 kHz stress. An estimated failure curve is included, though additional testing is required to validate and refine it.</figcaption></figure>

the curve to the max in-specification operating voltages (e.g., 650 V), a lifetime of approximately $10^{64}$ cycles is obtained. For example, a converter operating at 1 MHz would last for millions of years. However, at this frequency, other stress factors such as thermal cycling will no more be negligible. This demonstrates that repetitive overvoltage stress at 650 V is not the primary limiting factor for the DUT lifetime under these conditions. It should be noted, however, that this result applies specifically to the considered dynamic repetitive overvoltage stressor, isolated from other stress factors.

This result is a preliminary, more data points are needed to validate and refine the curve.

## 4. Discussion

The $V_{DS}$ and $I_D$ high levels during the switching event may enable creation of hot carrier injection. This hot carrier injection may lead to trapping effects.

The $R_{DS,on}$ increase observed in Fig. 6 is consistent with trapping effects already reported in the literature [14]. However, no saturation effect is observed on $R_{DS,on}$ in contrast with [14]. This rise may be explained by another trapping mechanism, because stress conditions are not the same. These traps may be near the channel and can slowly undergo detrapping at ambient temperature, as shown in Fig. 8.

The permanent shifts observed on the other parameters ($C_{DS}$, $I_{DSS}$, $I_{GSS}$) suggest different degradation mechanisms. One possibility is hot-carrier injection into deeper or more remote trap sites than those affecting $R_{DS,on}$, where detrapping at ambient temperature is unlikely. As the effect seems to be permanent, another hypothesis is that these shifts may be caused by structural degradation in the device. It could be a modification of the material caused by the high electric field that may lead to partial discharges (partial dielectric breakdown [15]) in some part of the insulating layer above the 2DEG channel.

The shape of the $C_{DS}$ characteristic shown in Fig. 7 may provide insights into the physical location of the degradation within the device. The pocket shape appearing between 100 V and 300 V suggests that the degradation is localized in a specific region of the device that becomes active within this voltage range. This could correspond to areas where the electric field is particularly high during the overvoltage event, leading to localized damage or trapping effects.

The evolution of $C_{DS}$ shape also suggest a change in the ability of field plates to spread the electric field in the device. Field plates are designed to reduce peak electric fields and improve breakdown voltage. Steps-like shape in the $C_{DS}$ are caused by the presence of field plates [16]. The disappearing of these steps may indicate that some of the field plates are becoming less effective, possibly due to damage or changes in the surrounding material properties. This field-plates becoming less effective would indicate that the electric-field

distribution in the device is being altered by the stress. And possibly leading to higher local electric fields during operation, which could lower the $V_{BR,dyn}$ over time.

The failure waveforms shown in Fig. 9 indicate that the device fails at high $V_{DS}$ and that the failure is catastrophic, as the HEMT can no longer turn off after the $N-1$ cycle. Notably, the failure does not occur during the first overvoltage event but rather during a subsequent one, suggesting that the device undergoes progressive degradation. In contrast to [6], thermal runaway is not expected to be the dominant failure mechanism here, as the thermal stress during the test is minimized (Section 2.5). Furthermore, the failure systematically occurs at the peak of $V_{DS}$ and at a lower $V_{DS}$ than the initial dynamic breakdown voltage $V_{BR,dyn}$, which was experimentally determined to be 1.43 kV. This behavior confirms the hypothesis that the preceding electrical stress modifies the internal electric field distribution, thereby reducing the effective breakdown voltage and predisposing the device to eventual failure.

Short-circuit failure mode observed is consistent with a dielectric breakdown mechanism, where the insulating layers within the device are compromised, leading to a permanent conductive path between the drain, gate and source. The gate involved in failure may show that bulk is not involved in the failure mechanism, but rather the layers above the 2DEG channel, and close to the gate.

Further investigation, possibly involving microscopic analysis and TCAD simulations, would be necessary to pinpoint the physical changes occurring in the device. These complementary approaches would also help verify the relevance and consistency of the hypotheses proposed in the discussion.

## 5. Conclusion

This study examined the impact of repetitive short-duration overvoltage stress on GaN HEMTs using the U1S3 circuit, whose improved OFF-state stress decoupling and reduced thermal influence enabled clear isolation of overvoltage-induced degradation.

The results show permanent, or very long-term recoverable, shifts of $C_{DS}$, $I_{DSS}$, and $I_{GSS}$, with degradation increasing with overvoltage amplitude, indicating accelerated failure mechanisms. The absence of recovery supports the hypothesis of structural rather than transient degradation. In contrast, $R_{DS,on}$ exhibited trapping-related degradation with partial recovery at ambient conditions.

The observed failure mode corresponds to a short-circuit state, likely caused by partial dielectric breakdown during overvoltage events, as confirmed by waveform analysis and post-failure characterization.

Future work should investigate high-temperature recovery to determine whether the shifts of $C_{DS}$, $I_{DSS}$, and $I_{GSS}$ are truly permanent or linked to deep-level traps. Microscopic failure analysis, TCAD simulations, and an expanded failure-data set are also needed to better understand the degradation mechanisms and enhance predictive-maintenance models. Additionally, the influence of varying $I_{D,switch}$ during overvoltage events should be explored to fully assess its role in device degradation and failure.

### CRediT authorship contribution statement

**Thomas Vadebout:** Conceptualization, Methodology, Formal analysis, Investigation, Data curation, Writing – review & editing, Writing – original draft, Visualization.
**Pascal Bevilacqua:** Software, Resources.
**Valeria Rustichelli:** Resources, Supervision, Conceptualization, Validation.
**Maroun Alam:** Resources, Conceptualization, Validation.
**Lau-rence Allirand:** Funding acquisition, Supervision, Conceptualization, Validation.
**Hervé Morel:** Supervision, Project administration, Funding acquisition, Conceptualization, Validation.
Declaration of competing interest

The authors declare that they have no known competing finan-
cial interests or personal relationships that could have appeared to
influence the work reported in this paper.

Acknowledgments

We extend our sincere gratitude to IRT Saint Exupéry through
the GaNRET project and Schaeffler for their valuable collaboration,
which has significantly enhanced our understanding of degradation
mechanisms caused by dynamic overvoltages.

This project PWEVTF from AMPERE supported by the IPCEI ME-CT
2026 from Schaeffler (former Vitesco technologies France) is funded
by the French government under France 2030. This paper is published
under CC-BY licence.

Data availability

Data will be made available on request.

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