# Nanoscale Reconfigurable Si Transistors: From Wires to Sheets and Unto Multi-Wire Channels

Lukas Wind, Raphael Behrle, Martien I den Hertog, Corban G E Murphey,

James F Cahoon, Masiar Sistani, Walter M Weber

► To cite this version:

Lukas Wind, Raphael Behrle, Martien I den Hertog, Corban G E Murphey, James F Cahoon, et al. Nanoscale Reconfigurable Si Transistors: From Wires to Sheets and Unto Multi-Wire Channels. Advanced Electronic Materials, 2023, 10 (2), pp.2300483. 10.1002/aelm.202300483. hal-04764988

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# Nanoscale Reconfigurable Si Transistors: From Wires to Sheets and Unto Multi-Wire Channels

Lukas Wind, Raphael Behrle, Martien I. den Hertog, Corban G. E. Murphey, James F. Cahoon, Masiar Sistani,* and Walter M. Weber*

In this work, bottom-up Al–Si–Al nanowire (NW) heterostructures are presented, which act as a prototype vehicle toward top-down fabricated nanosheet (NS) and multi-wire (MW) reconfigurable field-effect transistors (RFETs). Evaluating the key parameters of these transistors regarding the on- and off-currents as well as threshold voltages for n- and p-type operation exhibit a high degree of symmetry. Most notably also a low device-to-device variability is achieved. In this respect, the investigated Al–Si material system reveals its relevance for reconfigurable logic cells obtained from Si NSs. To show the versatility of the proposed devices, this work reports on a combinational wired-AND gate obtained from a multi-gate RFET. Additionally, up-scaling the current is achieved by realizing a MW RFET without compromising reconfigurability. The Al–Si–Al platform has substantial potential to enable complex adaptive and self-learning combinational and sequential circuits with energy efficient and small footprint computing paradigms as well as for native components for hardware security circuits.

## 1. Introduction

Reconfigurable logic has attracted considerable attention in recent years as a promising approach to effectively increase the functional density of integrated circuits. Different from conventional complementary metal oxide semiconductor (CMOS) electronics, the functional density is increased not only by the steady

miniaturization of the components, but by the functional diversification at the device level and the alteration of the operation of circuits built thereof.[1,2] From a structural point of view the commonly used field-effect transistor (FET) architecture can be adapted by adding additional independent gate electrodes and replacing the highly doped source and drain regions with abrupt metal-semiconductor junctions in order to deliver the envisioned RFETs. Such transistors embrace the functional enhancement of FETs by being capable of dynamic runtime switching between n- and p-type FET operations. This is in contrast to the static nature of CMOS technology, where the n- and p-type FET polarity is fixed physically by the choice of dopants employed at the source/drain and channel regions. Moreover, the logic circuit topology built from these is predefined lithographically by the interconnection of the n- and p-type FETs. A key technological advantage of RFETs as based on Schottky barrier (SB) FETs (SBFET) is that the devices are universally applicable for n- and p-type operability. They do not require doping to adjust the polarity and profit from not requiring specific gate stack engineering measures, and do not necessarily require high-temperature annealing procedures.[3–5] In this respect, metal-semiconductor-metal heterostructures deliver a convenient platform for the integration of such SBFET devices.[6,7] Independently gating the metal-semiconductor junctions allows electrostatic control of the injection capabilities for electrons and holes, and thus the selection of n- or p-type operation.[2,8] In order to unfold the full potential of RFETs for runtime reconfigurable and hardware-secure logic circuits, a high degree of symmetry regarding on- and off-currents, threshold voltages and subthreshold slopes for n- and p-type operation is essential. Remarkably, the Al–Si material system is particularly promising for reconfigurable electronics, due to its relatively symmetric barrier heights for both electrons and holes[9] as compared to concurrent CoSi, PtSi, and NiSi₂ junction technologies.[10,11] In contrast to other approaches that target symmetric RFET properties, no additional measures, such as, e.g., strain engineering or doping are necessary for the Al–Si material system.[12,13] Notably, using Al as source/drain contacts, the Fermi level pins close to the middle of the Si bandgap and thus exhibit similar SBs for electrons and holes.[14] Contrary to the bulk Al–Si material system, abrupt and void-free

L. Wind, R. Behrle, M. Sistani, W. M. Weber
Institute of Solid State Electronics
TU Wien
Vienna 1040, Austria
E-mail: masiar.sistani@tuwien.ac.at; walter.weber@tuwien.ac.at
M. I. den Hertog
Institut Néel
CNRS
Grenoble 38042, France
C. G. E. Murphey, J. F. Cahoon
Department of Chemistry
University of North Carolina at Chapel Hill
Chapel Hill, NC 27599, USA

<figure><img src="image_2.png" /></figure>

The ORCID identification number(s) for the author(s) of this article can be found under https://doi.org/10.1002/aelm.202300483

© 2023 The Authors. Advanced Electronic Materials published by Wiley-VCH GmbH. This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

DOI: 10.1002/aelm.202300483
metal-semiconductor interfaces are formed within the nanos-
tructure providing well-defined and reproducible Schottky junc-
tions. Additionally, no intermetallic phases are formed, overcom-
ing the often encountered difficulty of multi-phase formation in
state-of-the-art metal-silicides,[15–17] reducing process variability
and yield issues. At a device level and at first glance, RFETs suffer
from smaller drive currents and typically higher supply voltages
compared to conventional MOSFETs. Nevertheless, recent stud-
ies have shown that the exploitation of the enhanced fine-grain
functionality of RFETs at the circuit level provide competitive ad-
vantages over conventional CMOS in terms of area.[18,19] Combin-
ing the functionality of reconfigurable transistors into a logic cell
enables the efficient realization of intrinsic XOR gates,[6,20] wired-
ANDs[21,13] or multifunctional logic gates with the capability of
dynamically switching between NAND and NOR operation.[22,23]
Moreover, due to reconfiguration capabilities, self-learning algo-
rithms allow the realization of intelligent self-adaptable logic de-
vices down to the device level. Thus, the integration of RFETs
offers a wide variety of applications in functional diverse adap-
tive computing,[24] beyond computing purposes as well as new
approaches for hardware security solutions.[25,26]

**2. Results and Discussion**

**2.1. Nanowire-Based RFET**

First, bottom-up RFET devices from vapor-liquid-solid (VLS)
grown NWs are realized as this implementation constitutes a
simple prototyping vehicle without utilizing nanolithography to
define the NW diameter and is used here to discuss the general
properties of the realized RFET architecture. Another crucial ad-
vantage of NWs is the capability to decouple high-temperature
processing, i.e., NW oxidation at the growth substrate from the
final device substrate limiting temperatures to the contact an-
neal temperatures. In this context, contact printing of parallel
arrays of Si NWs[27] as well as a low-cost and flexible platform
for printed circuits were demonstrated.[28] The used NWs with
a predominant (112) growth direction have typical diameters of
dNW = 80 nm and are nominally intrinsic. Thermal oxidation at
1174 K for 3 min leads to the formation of a high-quality SiO2
gate oxide shell of nominally dox = 9 nm. After drop-casting the
suspended NWs in solution on a p-doped Si substrate covered
with a dry thermal SiO2 of 100 nm thickness, Al source/drain
contacts are fabricated. Using rapid thermal annealing (RTA) at a
temperature of 774 K in forming-gas atmosphere, the thermally
induced Al-Si exchange is initiated to achieve well-controllable
Si channels defined by single-crystalline Al contacts with abrupt
Al-Si interfaces.[9] Finally, Ω-shaped Ti/Au top-gates are fabri-
cated. Figure 1a shows a false-color SEM image of the thereof
obtained Al-Si-Al NW-based RFET, with “CG” being the con-
trol gate to turn the transistor on and off and “PG” being the
program gates, which allow dedicated selection between n- and
p-type operation by applying a positive or negative voltage, re-
spectively. Note that the PG top-gate electrodes are electrically
connected and hence are on the same potential for symmetric
tunability.[7,29] Importantly, the PG electrodes need to be accu-
rately aligned above the Al-Si interface for sufficient tunability
of the injection barrier between the metal and semiconductor.[30]
In terms of top-gate scaling, TCAD simulations have shown that

<figure><img src="image_3.png" /><figcaption>**Figure 1.** a) Colored SEM image of a NW-based Al–Si–Al heterostructure integrated as a three top-gate RFET. b) EDX map revealing the abrupt Al–Si interface without any intermetallic phases. The 9 nm thick SiO₂ oxide shell is visible as well. c) HAADF STEM image of the Al–Si interface with the Si part oriented along the [110] direction of observation.</figcaption></figure>

a spacing between the CG and PG electrodes of only 10 nm is
feasible.[30] Figure 1b shows the energy dispersive X-ray (EDX)
map of the obtained Al–Si interface, indicating no intermetallic
phases and an abrupt transition between Al and Si. Additionally,
the evidence of the SiO₂-shell covering the metal and semicon-
ductor channel is clearly visible in particular on the intruded Al
region. A high-angle annular dark field (HAADF) scanning trans-
mission electron microscopy (STEM) image of the Al–Si interface
is shown in Figure 1c, which further shows the high-quality and
abrupt metal-semiconductor interface of the proposed material
system. Note that, in the STEM (cf. Figure 1c), the crystalline na-
ture of the intruded Al is also visible directly at the Al–Si junction.

Investigating relevant transistor parameters as depicted in **Figure 2**, allows for characterization of the RFET performance. One of the most important parameters considering the symmetry of RFETs are the on- and off-currents both in n- and p-type operation, denoted as $I_{on/off}^{n/p}$ in the following. Especially for highly integrated logic circuits, realized with RFETs, this is of particular interest due to the necessity of appropriate driving capabilities and the realization of inverters and other complementary circuits.[6,13,31] Another important aspect in this context is the symmetry of the threshold voltage for n- and p-type operation, denoted as $V_{th}^{n/p}$. For the extraction of the threshold voltage, the transconductance method is used,[32] where the transconductance is obtained from the transfer characteristic ($dI_D/dV_{CG}$). Finally, the subthreshold slope $S^{n/p}$ is of high relevance in the
<figure><img src="image_4.png" /><figcaption>**Figure 2.** Transfer characteristic for applying $V_D = 1$ V of an NW-based Al–Si–Al RFET with characteristic transistor parameters. The inset shows the band diagrams and the underlying electrostatic gating mechanism for n- and p-type operation.</figcaption></figure>

context of logic gates, as it qualitatively describes the transition between the on- and off-state.

## 2.2. Top-Down Integration

As a wafer-scale integration of bottom-up grown NWs still faces significant challenges, i.e., precise placement of single NWs or difficulties in high integration of NW circuits, RFETs based on top-down technology are of utmost importance. Moreover, for NWs, oxide formation, and Al–Si reaction rates heavily depend on the initial NW diameter and orientation, whereas in top-down technology, an enhanced controllability of the Si channel shape and surface results in higher reproducibility. In this respect, NS RFETs were implemented using top-down fabrication techniques. Thereto, Si mesa structures were patterned out of a silicon on insulator (SOI) substrate with a 20 nm device layer using laser lithography and dry etching techniques. Thus, using commercially available SOI substrates, the compatibility and potential integration capability with modern fully depleted SOI (FD-SOI) CMOS technology is guaranteed.[33] These Si NSs range from 320 to 450 nm in width and are covered in 12 nm thick thermally grown SiO$_2$ gate oxide, with a remaining Si device layer of 15 nm after oxidation. Afterwards, annealing at 774 K for 60 s was performed, where a mean Al–Si exchange rate of (57.9 ± 3.0) nm s⁻¹ was evaluated.[9] To derive the optimal operating parameters of the RFETs and thereof created logic circuits, conduction maps are shown in **Figure 3**, showing the drain current $|I_D|$ of the device in logarithmic scale. Tuning the injection barriers of the Al–Si junctions with $V_{PG}$, the RFET can be efficiently switched between electron ($V_{PG} = 7$ V) and hole conduction ($V_{PG} = -7$ V), resulting in two distinct operation windows, marked in Figure 3a. Note that reducing the oxide and/or using high-κ oxides would significantly reduce the required gate voltages.[34] Furthermore, the on-currents for both modes are highly symmetric, with up to $I_{on}^n = 1.6$ µA ($I_{on}^p = 3.7$ µA µm⁻¹) and $I_{on}^p = 4$ µA ($I_{on}^n = 11.6$ µA µm⁻¹) for $V_D = 1$ V. Note that the values in brackets are the respective current values normalized to the width of the Si channel. It needs to be considered that the limiting factor for the maximum on-currents is the tunneling contribution through the Schottky barrier

<figure><img src="image_5.png" /><figcaption>**Figure 3.** Semi-logarithmic conductance maps of a top-down fabricated Al–Si RFET. Panel (a) showing the transition from p- to n-type operation by increasing $V_{PG}$ from negative to positive voltages. b) p-type operation at $V_{PG} = -7$ V and c) n-type operation at $V_{PG} = 7$ V in dependence of the bias voltage $V_D$, revealing distinct and symmetric on- and off-states for both modes. The insets show the respective transfer characteristic at $V_D = 1$ V.</figcaption></figure>

and its band bending capabilities.[11] Moreover, using sufficiently high PG voltages, the undesired charge carrier type is efficiently suppressed, resulting in off-currents below the resolution limit of the measurement setup (250 fA). Figure 3b,c shows the unipolar n- and p-type operation of the RFET for $V_{PG} = 7$ V and -7 V, respectively. Increasing the bias voltage $V_D$ leads to further tuning of the on-states and thus to higher currents and a higher level of symmetry. From the conduction maps, it is evident that
<figure><img src="image_6.png" /><figcaption>**Figure 4.** Extraction of the most relevant parameters of 20 NS (SOI) RFETs: a) $I_{on,off}^{n,p}$, where the solid square points indicate the on-current and the empty square points the off-current. b) $V_{th}^{n,p}$ where the red and blue square points mark n- and p-type operation, respectively.</figcaption></figure>

the proposed RFET devices can be well integrated into reconfigurable logic circuits, since their operation is stable even over a wide voltage range.

Furthermore, evaluating the device-to-device variability and transistor stability in terms of the previously mentioned parameters, twenty NS-based RFET devices were systematically analyzed and evaluated. As the on- and off-currents and the threshold voltages in n- and p-type operation are the most important parameters of transistors, especially for logic circuits, these parameters are visualized in **Figure 4**. Note that for the transfer characteristics, a bias voltage of $V_D = 1$ V was used. The mean on-current normalized to the width of the NSs results in $I_{on}^n = 6.24$ µA µm⁻¹ and $I_{on}^p = 11.81$ µA µm⁻¹ (see Figure 4a), whereas the off-currents $I_{off}^{n,p}$ remain below the resolution limit of the measurement equipment. The corresponding mean current densities

are $J_{on}^n = 41.6$ kA cm⁻² and $J_{on}^p = 78.7$ kA cm⁻² for n- and p-mode operation, respectively, resulting in a mean on-current symmetry of a factor of 1.9. In comparison, a different contact technology based on Ni-silicide NW RFETs shows a symmetry factor of the on-currents of 17.6.[³⁵] In this regard, further symmetry adjustment might be possible by fine-tuning the compressive strain to the Si cross-section. As the threshold voltage $V_{th}$ is another important parameter in driving logic circuits, Figure 4b shows the extracted values in n- (red square points) and p-type (blue square points) operation mode. For the extraction of the threshold voltage, the transconductance method was used.[³²] Remarkably, also the extracted mean $V_{th}$ values exhibit a high degree of symmetry with $V_{th}^n = 1.8$ V and $V_{th}^p = -2.8$ V. For the NS-based RFETs a mean hysteresis of 71 mV in n-mode and 110 mV in p-mode operation was extracted, calculating the difference of the
threshold voltages $V_{th}$ of backward and forward sweeps (≈5 s per sweep direction). Moreover, evaluating the transfer characteristics, the subthreshold slopes were extracted with $S^n = 480$ mV dec⁻¹ and $S^p = 340$ mV dec⁻¹, which again depict well the symmetry of the top-down fabricated Al–Si RFETs. In already published works on single-gated SBFETs[36] and dually gated RFETs,[37] the subthreshold region can be controlled by program gate coupling. This is given by the change of thickness and transmissibility of the Schottky barrier with $V_{CG}$. However, in a three-top-gate RFET device architecture, the potential at the Schottky junctions is fixed by $V_{PG}$. Therefore, the ultimate thermal limit of 64 mV dec⁻¹ can only be reached, if an efficient gate coupling in terms of thin Si layers, thin gate oxides with a low equivalent oxide thickness (EOT), and ideally gate-all-around (GAA) gating geometries are applied.[6,38]

## 2.3. Multi-Control Gate RFET

To show a further significant advantage in terms of flexibility of top-down fabricated RFETs, Figure 5a depicts a false color SEM image of a multi-CG RFET implementation of a three-input wired-AND gate based on the proposed Al–Si–Al NS RFETs. Such devices are of high importance as they feature the advantage of suppressing parasitic charge-sharing effects in dynamic logic gates.[21,39] Further, this type of device enables the realization of logical gates with dedicated pull-up and pull-down networks, with the advantage of replacing the entire lower branch of a NAND gate by a single transistor with multiple inputs (see inset of Figure 5a). Importantly, using this concept, the number of inputs can be increased for the realization of multi-input logic cells, which is only limited by the higher resistance of long-channel RFETs, reducing the drive current. The investigated wired-AND gate is realized by splitting the CG into three independent gate electrodes enabling additional energy barriers to turn the RFET on only when a logic high is applied to all gates. In the actual case the supply voltages $V_{DD} = V_{PG}$ and $V_{SS}$ were chosen to be 3 and –3 V, respectively. Toggling the input signals A, B, and C between ±3 V, we have realized a logic gate only needing one voltage domain, which simplifies the circuit layout. Figure 5b shows the transient operation of the proposed three input wired-AND for driving the inputs A, B, and C with 0.1, 0.2, and 0.4 Hz, respectively. This relatively low operation speed of the wired-AND gate was chosen due to limitations of the measurement setup and our lab-based design of the structures, with large planar contact pads on top of the SOI substrate for contacting the probes, inducing extremely high parasitic capacitances. Nevertheless, the obtained results verify its function. Note that mixed-mode TCAD simulations have already shown the operability of scaled and optimized Si-based RFETs with back-end-of-line interconnect technology in the GHz regime.[30] Analyzing the transient trace of the output current $I_{DD}$ reveals its capability of properly suppressing the current in the off-state, which is below the noise floor of our measurement system (<250 fA), while maintaining on-currents of ≈40 nA, giving an on/off ratio of more than five orders of magnitude. Importantly, applying $V_{PG} = –3$ V, thus operating the RFET in p-mode, current through the device would only be driven for applying –3 V to all inputs. This allows a high degree

<figure><img src="image_7.png" /><figcaption>**Figure 5.** a) Colored SEM image of a multi-CG Al–Si–Al NS RFET resembling a three-input wired-AND gate capable of replacing the lower branch of a NAND gate (see inset). b) Transient operation for driving the inputs A, B, and C with 0.1, 0.2, and 0.3 Hz, respectively. $V_{DD} = V_{PG} = 3$ V and $V_{SS} = –3$ V were set.</figcaption></figure>

of flexibility for circuit and layout designers and is therefore a further advantage of the proposed RFET based wired-AND.

## 2.4. Multi-Wire RFET

To provide an effective strategy for current up-scaling a MW RFET is presented next. Importantly, the advantage of flexibility in the patterning of SOI is a crucial enabler for this type of device. A false-color SEM image of the actual device is shown in Figure 6a. The device consists of ten parallel Al–Si–Al NS heterostructures, which enable a tenfold current increase compared to a single-NS device, enhancing logic gates for, e.g., driving stages of wired gates and power-demanding electronics. The
<figure><img src="image_8.png" /><figcaption>**Figure 6.** a) Colored SEM image of a top-down fabricated MW RFET based on ten parallel Al–Si–Al NS heterostructures. b) The transfer characteristic reveals an increase of the on-current, enhancing the drivability of logic gates compared to single NW/NS RFETs.</figcaption></figure>

realization of such a parallel array of metal-semiconductor het-
erostructures is possible due to the stable crystal phase of the
intruded Al leads, resulting in less process variations compared
to silicidation rates of common NiₓSi₁₋ₓ-Si heterostructures.[¹⁷]
This is of significant importance, as it is crucial to align the PGs
atop all metal-semiconductor junctions in order to efficiently
tune the barriers of the whole device. The transfer characteris-
tic of the fabricated device in Figure 6b shows the significantly
increased on-current, with I<sub>on</sub><sup>n</sup> = 14.7 µA (I<sub>on</sub><sup>n</sup> = 4.2 µA µm<sup>-1</sup>) and
I<sub>on</sub><sup>p</sup> = 172 µA (I<sub>on</sub><sup>p</sup> = 48.9 µA µm<sup>-1</sup>) at V<sub>D</sub> = 2 V, while the off-
currents and hysteresis remain low. The accumulated width of
the individual NSs was used for normalization. Other transis-
tor parameters, such as the threshold voltages V<sub>th</sub><sup>n</sup> = 0.84 V and
V<sub>th</sub><sup>p</sup> = -0.7 V as well as subthreshold slopes S<sup>n</sup> = 310 mV dec<sup>-1</sup>
and S<sup>p</sup> = 230 mV dec<sup>-1</sup> remain similar to the single NS transis-
tor. Compared to parallel arrays of bottom-up grown NWs,[²⁸] the
top-down fabrication approach is much more controllable and
scalable for highly integrated devices and depicts a high poten-
tial toward wafer-scale integration.[⁴⁰] Moreover, the capability to
fabricate parallel NSs demonstrates the possibility for further en-
hancements in realizing logic circuits.

**3. Conclusion**

In conclusion, we have used bottom-up NWs to demonstrate
RFETs and evaluated as well as exploited top-down SOI-based
NS RFETs. The thereof fabricated three top-gate RFETs were ana-
lyzed from a transistor’s perspective, where different highly rele-

vant parameters, such as I<sub>on</sub>, I<sub>off</sub>, V<sub>th</sub>, and the sub-threshold slope S for both n- and p-type operation modes were investigated and discussed. Importantly, due to the combination of symmetric activation energies of electrons and holes for the Al–Si material system and sophisticated top-down fabrication, RFETs with an on-current symmetry between the n- and p-type operation modes of 1.9 are achieved without the need of stress leavers. To exemplary show the flexibility of the presented Al–Si–Al RFET platform, we have demonstrated a multi-CG RFET resembling a three-input wired-AND capable of reducing the overall transistor count by a factor of two. In particular, we have shown that with ten parallel NSs the on-current I<sub>on</sub> can be significantly increased, whereas the off-current I<sub>off</sub> remains at an acceptably low value, which is relevant for power-intensive electronics as well as for logic circuits. Thus, the monolithic Al–Si heterostructure RFET technology is promising towards the realization of high-performance and even self-learning reconfigurable electronics.

**Acknowledgements**

The authors gratefully acknowledge financial support from the Austrian
Science Fund (FWF) project No.: I 5383-N. The NW synthesis was sup-
ported by grant DMR-2121643 from the U.S. National Science Founda-
tion. The authors further thank the Center for Micro- and Nanostructures
(ZMNS) of TU Wien for providing the cleanroom facilities. This project
has received funding from the European Research Council (ERC) under the
European Union's Horizon 2020 research and innovation program for the
e-See project (grant agreement N° 758385). The authors benefited from
the access to the Nano characterization platform (PFNC) in CEA Minatec Grenoble.

## Conflict of Interest

The authors declare no conflict of interest.

## Data Availability Statement

The data that support the findings of this study are available from the corresponding author upon reasonable request.

## Keywords

combinational logic, reconfigurable transistor, RFET, SBFET, silicon on insulator

Received: July 19, 2023

Revised: September 6, 2023

Published online: December 5, 2023

[1] L. Yojo, R. C. Rangel, K. R. Sasaki, J. A. Martino, presented at 32nd Symposium on Microelectronics Technology and Devices (SBMicro), Fortaleza, Brazil, August 2017.

[2] P. E. Gaillardon, Functionality-Enhanced Devices: An alternative to Moore's Law, IET, London 2018.

[3] F. Wessely, T. Krauss, U. Schwalke, Solid-State Electron. 2012, 70, 33.

[4] M. Mongillo, P. Spathis, G. Katsaros, P. Gentile, S. De Franceschi, Nano Lett. 2012, 12, 3074.

[5] A. V. Thathachary, K. N. Bhat, N. Bhat, M. S. Hegde, Appl. Phys. Lett. 2010, 96, 152108.

[6] M. De Marchi, D. Sacchetto, S. Frache, J. Zhang, P. E. Gaillardon, Y. Leblebici, G. De Micheli, presented at Int. Electron Devices Meeting, San Francisco, Dec. 2012.

[7] M. Sistani, R. Böckle, D. Falkensteiner, M. A. Luong, M. I. Den Hertog, A. Lugstein, W. M. Weber, ACS Nano 2021, 15, 18135.

[8] W. M. Weber, J. Trommer, M. Grube, A. Heinzig, M. König, T. Mikolajick, presented at Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, March 2014.

[9] L. Wind, R. Böckle, M. Sistani, P. Schweizer, X. Maeder, J. Michler, C. G. E. Murphey, J. Cahoon, W. M. Weber, ACS Appl. Mater. Interfaces 2022, 14, 26238.

[10] J. Beister, A. Wachowiak, A. Heinzig, J. Trommer, T. Mikolajick, W. M. Weber, Phys. Status Solidi 2014, 11, 1611.

[11] F. Fuchs, S. Gemming, J. Schuster, J. Phys. Cond. Matter 2019, 31, 355002.

[12] A. Heinzig, T. Mikolajick, J. Trommer, D. Grimm, W. M. Weber, Nano Lett. 2013, 13, 4176.

[13] R. Bockle, M. Sistani, M. Bazikova, L. Wind, Z. Sadre-Momtaz, M. I. den Hertog, C. G. Murphey, J. F. Cahoon, W. M. Weber, Adv. Electron. Mater. 2022, 9, 2200567.

[14] R. Clark, Materials 2014, 7, 2913.

[15] N. Breil, C. Lavoie, A. Ozcan, F. Baumann, N. Klymko, K. Nummy, B. Sun, J. Jordan-Sweet, J. Yu, F. Zhu, S. Narasimha, M. Chudzik, Microelectron. Eng. 2015, 137, 79.

[16] J. A. Kittl, A. Lauwers, O. Chamirian, M. Van Dal, A. Akheyar, M. De Potter, R. Lindsay, K. Maex, Microelectron. Eng. 2003, 70, 158.

[17] M. B. Khan, D. Deb, J. Kerbusch, F. Fuchs, M. Löffler, S. Banerjee, U. Mühle, W. M. Weber, S. Gemming, J. Schuster, A. Erbe, Y. M. Georgiev, Appl. Sci. 2019, 9, 3462.

[18] M. Raitza, A. Kumar, M. Volp, D. Walter, J. Trommer, T. Mikolajick, W. M. Weber, presented at Design, Automation & Test in Europe Conference & Exhibition (DATE), Lausanne, Switzerland, March 2017.

[19] S. Rai, S. Patnaik, A. Rupani, J. Knechtel, O. Sinanoglu, A. Kumar, IEEE Trans. Emerg. Top. Comput. 2022, 10, 763.

[20] L. Amaru, P. E. Gaillardon, G. De Micheli, presented at Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, March 2013.

[21] M. Simon, J. Trommer, B. Liang, D. Fischer, T. Baldauf, M. B. Khan, A. Heinzig, M. Knaut, Y. M. Georgiev, A. Erbe, J. W. Bartha, T. Mikolajick, W. M. Weber, presented at 76th Device Research Conference (DRC) Santa Barbara, USA, June 2018.

[22] J. Trommer, A. Heinzig, S. Slesazeck, T. Mikolajick, W. M. Weber, IEEE Electron Device Lett. 2014, 35, 141.

[23] M. D. Marchi, J. Zhang, S. Frache, D. Sacchetto, P.-E. Gaillardon, Y. Leblebici, G. D. Micheli, IEEE Electron Device Lett. 2014, 35, 880.

[24] T. Mikolajick, G. Galderisi, M. Simon, S. Rai, A. Kumar, A. Heinzig, W. M. Weber, J. Trommer, Solid-State Electron. 2021, 186, 108036.

[25] P. Wu, D. Reis, X. S. Hu, J. Appenzeller, Nat. Electron. 2021, 4, 45.

[26] Y. Bi, K. Shamsi, J.-S. Yuan, P.-E. Gaillardon, G. D. Micheli, X. Yin, X. S. Hu, M. Niemier, Y. Jin, ACM J. Emerg. Technol. Comput. Syst. 2016, 13, 1.

[27] S. Pregl, W. M. Weber, D. Nozaki, J. Kunstmann, L. Baraban, J. Opitz, T. Mikolajick, G. Cuniberti, Nano Res. 2013, 6, 381.

[28] S. Pregl, A. Heinzig, L. Baraban, G. Cuniberti, T. Mikolajick, W. M. Weber, IEEE Trans. Nanotechnol. 2016, 15, 549.

[29] W. M. Weber, A. Heinzig, J. Trommer, D. Martin, M. Grube, T. Mikolajick, Solid-State Electron. 2014, 102, 12.

[30] T. Baldauf, A. Heinzig, T. Mikolajick, W. M. Weber, Joint Int. EUROSOI Workshop and Int. Conf. on Ultimate Integration on Silicon (EUROSOI-ULIS), Grenoble, France, April 2019.

[31] M. Simon, B. Liang, D. Fischer, M. Knaut, A. Tahn, T. Mikolajick, W. M. Weber, IEEE Electron Device Lett. 2020, 41, 1110.

[32] M. Tsuno, M. Suga, M. Tanaka, K. Shibahara, M. Miura-Mattausch, M. Hirose, IEEE Trans. Electron Devices 1999, 46, 1429.

[33] M. Wiatr, S. Kolodinski, presented at European Solid-State Device Research Conf., Cracow, Poland, Sept. 2019.

[34] K. H. Jing, M. K. Arshad, A. R. Huda, A. R. Ruslinda, S. C. Gopinath, M. N. Nuzaihan, R. M. Ayub, M. F. Fathil, N. Othman, U. Hashim, AIP Conf. Proc. 2016, 1733, 020073.

[35] A. Heinzig, S. Slesazeck, F. Kreupl, T. Mikolajick, W. M. Weber, Nano Lett. 2012, 12, 119.

[36] J. Knoch, M. Zhang, J. Appenzeller, S. Mantl, Appl. Phys. A: Mater. Sci. Process. 2007, 87, 351.

[37] T. Baldauf, A. Heinzig, J. Trommer, T. Mikolajick, W. M. Weber, Solid-State Electron. 2017, 128, 148.

[38] J. Trommer, A. Heinzig, T. Baldauf, S. Slesazeck, T. Mikolajick, W. M. Weber, IEEE Trans. Nanotechnol. 2015, 14, 689.

[39] D. Vana, P.-E. Gaillardon, A. Teman, IEEE Trans. Nanotechnol. 2020, 19, 123.

[40] N. Singh, K. D. Buddharaju, S. K. Manhas, A. Agarwal, S. C. Rustagi, G. Q. Lo, N. Balasubramanian, D.-L. Kwong, IEEE Trans. Electron Devices 2008, 55, 3107.