# Autonomous FPGA Reconfigurability in Embedded Systems

Hugo Boulissière, Adrien Prost-Boucle, Elena Ioana Vatajelu, Giorgio Di Natale

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Hugo Boulissière, Adrien Prost-Boucle, Elena Ioana Vatajelu, Giorgio Di Natale. Autonomous FPGA Reconfigurability in Embedded Systems. 20th IEEE East-West Design & Test Symposium (EWDTS 2024), IEEE, Nov 2024, Yerevan, Armenia. 10.1109/EWDTS63723.2024.10873607. hal-04917041

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# Autonomous FPGA Reconfigurability in Embedded Systems

Hugo Boulissière, Adrien Prost-Boucle, Elena-Ioana Vatajelu, Giorgio Di Natale

Univ. Grenoble Alpes, CNRS, Grenoble INP*, TIMA, 38000 Grenoble, France

hugo.boulissiere@grenoble-inp.org, {adrien.prost-boucle, ioana.vatajelu, giorgio.di-natale}@univ-grenoble-alpes.fr

**Abstract**—Advances in field-programmable gate array (FPGA) technology have led to their widespread adoption in various applications, from embedded systems and data centers to high-performance computing. FPGAs provide a flexible and cost-effective solution for implementing digital logic, offering a unique balance between performance, power consumption, and reconfigurability. The ability to generate and load the FPGA's configuration data, known as the bitstream, is a crucial aspect of FPGA-based system design, as this bitstream defines the FPGA's functionality and behavior. Recently, architectures that integrate FPGA technology with embedded processors have become increasingly popular, enabling the creation of highly versatile systems-on-chip. In this work, we introduce a design methodology that employs open-source tools to enable the generation of FPGA bitstreams directly within embedded processors. This approach harnesses the advantages of FPGA-based systems, such as their reconfigurability and high-performance characteristics, while smoothly integrating them with embedded processors. Additionally, we propose several research directions and applications where this novel paradigm can be leveraged to develop innovative solutions.

**Index Terms**—FPGA, reconfiguration, embedded systems

## I. INTRODUCTION

Field-programmable gate arrays have gained significant traction in the field of digital system design due to their inherent flexibility, high performance, and energy efficiency [1]. FPGAs allow users to configure the underlying logic and interconnect resources to implement custom digital logic, enabling rapid prototyping and the deployment of application-specific hardware accelerators.

FPGAs are now widely used in a broad spectrum of applications, from embedded systems and data centers to high-performance computing environments. They are a low-cost and flexible solution for digital logic implementation, using reconfigurability to optimise performance and power efficiency. A critical component in FPGA system design is the generation and loading of the bitstream, which dictates the FPGA's functionality and operational behavior. Recently, architectures that merge FPGA technology with embedded processors have seen growing popularity, facilitating the creation of highly adaptable and versatile system-on-chip solutions.

While the bitstream generation process for FPGA-based systems has traditionally involved the use of proprietary design tools provided by FPGA vendors, this complexity has also enabled the development of advanced toolchains and methodologies that can streamline the bitstream generation process. Recent advancements in open-source tools and frameworks have made it possible to generate FPGA bitstreams in a more efficient and accessible manner, reducing the barriers to entry for FPGA-based system development.

In this work, we present a novel design methodology that leverages open-source tools to enable the direct generation of FPGA bitstreams within embedded processors. This approach harnesses the key advantages of FPGA-based systems, such as their exceptional reconfigurability and high-performance characteristics, and integrates them with embedded processors. By empowering embedded processors with the ability to generate FPGA bitstreams on-the-fly, this methodology unlocks new possibilities for creating highly versatile and adaptive systems-on-chip that can dynamically reconfigure their hardware to meet evolving application demands or adapt to changing operational environments.

This methodology is particularly relevant for applications demanding custom adaptability, including:

1. Critical and harsh environments: Systems operating in unpredictable conditions, such as satellites or deep-sea exploration equipment, can utilize on-the-fly bitstream generation to adapt to malfunctions, circumvent faulty hardware, or accommodate evolving operational parameters.

2. Security-sensitive applications: Devices requiring unique configurations for enhanced security, such as those employing device-specific secret keys or implementing robust cryptographic primitives like physically unclonable functions, benefit from the adaptability offered by this approach.

Up to today, synthesis tools have been mostly exclusively used in a classical FPGA-based system design flow, where the bitstream generation is performed on a separate host system. Actually running synthesis, placement and routing tools within embedded systems has been perceived as unreachable. To the best of our knowledge, there is only one related work in this direction, presented in [2] and [3], with a 50 MHz soft CPU Risc-V programmed on a Lattice FPGA. Generation of an FPGA bitstreams is achieved directly within the embedded processor, leveraging a selection of open-source tools and frameworks. The process is extremely slow because of the nature of the underlying processor. The initial bitstream was generated on desktop computer, then when running on-board they only demonstrated synthesis of a tiny counter and not synthesis of the whole system that includes the soft processor.

The rest of this paper is organised as follows: Section II describes the architectural requirements that make the proposed solution viable and efficient; Section III presents a non-exhaustive list of domains where the proposed embedded bitstream generation would greatly improve the characteristics of today's systems; Section IV lists and briefly describes the tools used for the proof-of-concept implementation of our proposed methodology; Section V describes in detail three

<footnote n="1">¹Institute of Engineering Univ. Grenoble Alpes</footnote>
scenarios where the proposed solution can be used and, finally, Section VI concludes the paper.

## II. ARCHITECTURAL REQUIREMENTS

The proposed design methodology is based on the integration of a CPU-FPGA hybrid architecture, where a host processor is coupled with a reconfigurable FPGA fabric. This architecture allows the processor to dynamically reconfigure the FPGA to adapt to changing application requirements or environmental conditions.

One key aspect of the target architecture is the availability of tools and frameworks that enable the generation of FPGA bitstreams within the embedded processor's software stack. This requirement necessitates a processor with sufficient computational capability to execute these complex software tools efficiently. The FPGA should be connected to the processor as a device, using a standard high-speed communication bus such as AXI, to facilitate data transfer and configuration. In many cases, a lightweight operating system, such as Linux, may be necessary to provide the required runtime environment, resource management, and file system support for these tools.

The targeted platforms we selected to evaluate and validate our proposed methodology are the Zybo [4] and Zedboard [5] FPGA boards, both based on the Zynq system-on-chip from Xilinx. These boards are very interesting targets because the Zynq chips feature two-cores hard processors with architecture ARM Cortex-A9, designated as *processor subsystem* (PS), and an FPGA peripheral, designated as *programmable logic* (PL). The Processor Subsystem is powerful enough to run the necessary synthesis tools within a convenient GNU/Linux distribution. Furthermore, the FPGA fabric is connected to the PS via multiple AXI ports, offering both high flexibility and high-performance data transfer capabilities.

## III. PERSPECTIVES ON THE PROPOSED DESIGN METHOD

The design method we propose presents innovative applications across various domains, notably in reliability, security, and artificial intelligence (AI). These areas benefit from hardware reconfigurability, fault tolerance, and optimization techniques. Below are the potential perspectives and utilization in each domain.

**Reliability Domain:** Reliability is crucial for ensuring consistent performance and trustworthiness in systems.

* in highly autonomous systems, such as satellites, the need for fault tolerance is critical. Our method enables real-time hardware reconfiguration to address defects. For example, when a section of the FPGA becomes non-functional due to radiation damage or aging, our method allows for dynamic synthesis, ensuring that the faulty parts are no longer utilized. This enhances the longevity and reliability of mission-critical systems by allowing them to self-heal without requiring manual intervention.

* Reliable Weak PUF (Physical Unclonable Function): Our method introduces a novel approach where the PUF is dynamically reconfigurable at the hardware level to improve its reliability without compromising its security (more details are given in Section V-A).

**Security Domain:** The proposed design method also has significant implications in security applications, providing solutions for enhancing cryptographic resilience and system robustness:

* Encryption with Session Key: This technique involves synthesizing hardware with an embedded secret session key. This not only reduces the area required but also minimizes delays, thus providing a streamlined and efficient encryption process. (an example is shown in Section V-B)

* Strong PUF: a strong PUF could be designed by using the bitstream configuration as challenge, enabling highly secure hardware-level authentication mechanisms that are resistant to cloning or tampering.

* Reconfigurable Weak PUF: Our method introduces a novel approach where the PUF is dynamically reconfigurable at the hardware level to improve its security metrics. Initially, the system measures specific characteristics, such as frequencies from ring oscillators distributed across the FPGA. A software component running on a processor maps the challenges to these pre-measured elements. Subsequently, the system triggers a placement and routing procedure that only reconfigures the connections between ring oscillators and counters, thus enhancing the system's entropy distribution.

**Artificial Intelligence and Optimization Domain:** Our design method can also be leveraged for AI and optimization applications, specifically in hardware adaptability and performance enhancement:

* Self-Regenerating AI Hardware: This application involves hardware for AI systems that can self-regenerate, reconfiguring themselves to optimize specific performance metrics. The hardware adjusts dynamically, adapting to evolving operational conditions to maintain or improve AI performance.

* Software Offloading to Hardware: Based on the characteristics of the specific hardware, certain software blocks can be offloaded into the hardware. This is achieved by dynamically optimizing the placement and routing to maximize performance based on the unique hardware properties of the device. The offloading process allows for increased efficiency and reduced computational overhead on software resources (an example is shown in Section V-C).

This design method, with its emphasis on reconfigurability, security, and optimization, opens new avenues for enhancing the resilience and efficiency of hardware systems across multiple domains. The ability to dynamically adjust the hardware in response to environmental changes, security needs, or performance demands positions this method as a cutting-edge approach in modern computing and embedded systems.

## IV. PRESENTATION OF THE TOOL-CHAINS

### A. Vivado

The reference tool suite for synthesis, placement and routing for the considered AMD/Xilinx FPGA technologies is the vendor-provided suite Vivado. This massive full-featured software suite is expected to offer one of the best support for input languages, of synthesis optimization and performance features, of simulation capabilities, and of integration within the reference vendor-provided operating system (Petalinux). This solution also comes with guaranteed functionality and performance, which makes it a suite of choice for production purposes.
Despite these advantages, the Vivado suite is not suited for
the targeted usage within embedded systems, mainly for the
following reasons:

* This software suite is massive for its size on disk (more than 100 GB in latest versions) and there is no recommendation to reduce this size further.

* It is also usually very demanding on RAM memory to execute, and the on-board 512 MB are clearly not enough.

* It is only available for x84_64 CPUs architectures, so running it on 32-bit ARM architectures is not an option.

This paper will intentionally not show Vivado results of the considered designs, mainly because such results would not be reproducible on-board anyway, and also because publishing such compared results is not allowed by the license. Interested readers with access to Vivado can always reproduce such results independently.

## B. Open-source tools

For the specific purpose of performing bitstream generation, only a subset of functionalities of most vendor tool suites are necessary. The necessary operations are synthesis of RTL-level language, placement and routing for the targeted device, and final generation of the bitstream file. The desired objective of performing these steps in an embedded context is relatively uncommon, so open-source tools were considered. The flexibility of open-source is important in this project, as it enables to recompile the tools for the targeted CPU architecture and to adapt their source code to the target when necessary.

The selected open-source projects are the following:

* **GHDL** [6] to translate VHDL designs into simpler pre-synthesized Verilog.

* **Yosys** [7] to perform logic synthesis of Verilog designs.

* **Nextpnr** [8] to perform placement and routing for various FPGA technologies. Actually a derivative project is used [9], dedicated to experimenting with the targeted FPGA technology.

* and **Prjxray** [10] which provides documentation for the target technology to Nextpnr, and which provides experimental tools to generate the final bitstream file.

Figure 1 shows the target tool-chain using GHDL, Yosys, Nextpnr and Prjxray. It supports VHDL and Verilog code as input languages, and it generates corresponding bitstream files. The sequence of underlying tools is described in more details in the next paragraphs.

a) **GHDL**: GHDL is an open-source analyzer, compiler and simulator for the VHDL language. In addition, it features a light form of synthesis that actually enables to translate VHDL code into simple Verilog code. Hence, this tool enables the toolchain to support both VHDL and Verilog code, thereby expanding the user base.

b) **Yosys**: After translating the entire VHDL code into Verilog code, we synthetize the HDL code using Yosys. Yosys is a open-source framework for RTL synthesis tools that only supports Verilog. It can perform various operations on netlists and conduct simplifications and logic optimizations. The resulting netlist file is represented in the ubiquitous JSON format.

c) **Nextpnr**: Following the Yosys step, to place-and-route operations are performed with the tool Nextpnr. Nextpnr is an open-source multi-architecture place-and-route framework which supports a large number of FPGA architectures. In our

<figure><img src="image_2.png" /><figcaption>Fig. 1: Tool-chain used for the generation of a bitstream from VHDL and/or Verilog code</figcaption></figure>

case, the support for the AMD/Xilinx chips is still experimental, which might cause a lack of stability. The result of the placement and routing is a text-based representation of the FPGA configuration on the open FASM format (FPGA Assembly).

d) **Script fasm2frames**: The FASM file is processed by the script fasm2frames, which is part of the project Prjxray. It performs a conversion of the FASM directives into configuration frames in which the FPGA bits to be programmed (for LUTs, interconnects, I/Os, etc.) are specifically aligned to the low-level structure of the targeted hardware. This frames content is still in a text format to ease development and validation of the tools.

e) **Script xc7frames2bit**: Finally, the text-based representation of the bitstream is converted into binary format by the tool xc7frames2bit which is also part of the project Prjxray. This is the final binary file that can be used directly to program the FPGA device.

## C. Operating system

The complete details of the operating system setup are provided in a dedicated documentation and demonstration project [11]. Overall, the GNU/Linux distribution Archlinux is selected for two main reasons : there is an immediately bootable setup for the board Zedboard, and the repositories of pre-compiled software applications already provide some of the tools and libraries needed for the present works, including Yosys.

The tools Nextpnr and Prjxray have to be compiled from sources, this operation can be performed on-board. The tool GHDL is the major difficulty because of the lack of a pre-compiled ADA compiler. So GHDL was compiled separately on a desktop computer, in a QEMU virtual machine running a compatible variant of the Debian distribution, then transferred
on Zedboard where it is installed as a proper Archlinux package.

## V. USE CASES

In this use case section, we demonstrate the significant potential of the proposed embedded bitstream generation procedure by applying it to three key areas: reliability, security and artificial intelligence. First, we show how the bitstream generation technique can enhance PUF reliability by filtering unstable components, ensuring consistent Challenge-Response Pairs (CRPs) without the need for helper data. Second, the procedure imea and increasing the speed without compromising the secutity. Finally, the same reconfigurability is leveraged to offload neural network inference tasks from software to hardware, significantly speeding up computation while maintaining flexibility. Together, these examples showcase the versatility of the proposed approach in enhancing security, simplifying cryptographic design, and boosting performance for AI applications.

### A. Case Study 1: Reliability Enhancement of Physical Unclonable Functions

Ring Oscillator Physically Unclonable Functions (RO PUFs) are hardware security primitives that generate unique device-specific identifiers by exploiting the inherent variations in the manufacturing process of integrated circuits. These variations cause slight differences in the oscillation frequencies of identical ring oscillators, which are used to generate a unique digital fingerprint for each device. While RO PUFs offer low-cost and efficient solutions for device authentication and cryptographic key generation, they face reliability issues due to environmental factors like temperature fluctuations, supply voltage variations, and aging effects. Filtering techniques [12] can be applied to improve the reliability of RO PUFs by eliminating or reducing the impact of unstable responses. One such approach involves identifying and filtering out ring oscillator (RO) pairs with the smallest frequency differences. These pairs are more prone to environmental variations, such as temperature changes or voltage fluctuations, which can cause their frequency rankings to flip, leading to unreliable PUF responses. By excluding these RO pairs, only those with larger, more stable frequency differences are used to generate the PUF's output, thereby enhancing the overall consistency and robustness of the PUF in real-world conditions. This filtering technique requires the use of helper data (in this example the IDs of the excluded RO pairs), which is additional information stored to assist in stabilizing the output. This helper data comes with trade-offs. First, it increases the overall resource consumption of the system. Second, it makes the Challenge-Response Pair (CRP) generation process more complex, as the system must track and filter responses in real time, which can slow down the PUF's performance. Lastly, helper data introduces potential security vulnerabilities—since it often needs to be stored externally, it could be exposed to attackers. If the helper data is compromised, it could be exploited to reverse-engineer or manipulate the PUF's behavior, reducing the overall security of the system.

By utilizing the proposed embedded bitstream generation method, the need for storing the helper data is eliminated as the information related to the unreliable responses is accounted for at the bitstream generation and only the reliable pairs of ROs are routed in the final design. To ensure this process a

two-step enrollment is necessary (illustrated in Fig. 2). In the first step, a bitstream is used that includes all $2*(N+k)$ ROs (where N is the desired size of the PUF response and k is the number of redundant ROs) along with counters, which are used by the processor to measure their frequencies. The frequency differences of all RO pairs are ranked and the k pairs with the smallest frequency difference are removed. In the second step, an updated version of the circuit (vhdl+xdc files) is synthesised by removing those k pairs of ROs and a new bitstream is generated and uploaded to the FPGA. This approach guarantees a more reliable PUF without the overhead and security concerns of helper data.

<figure><img src="image_3.png" /><figcaption>Fig. 3: Schematic of a 128-bit AES (Advanced Encryption Standard)</figcaption></figure>

<figure><img src="image_4.png" /><figcaption>Fig. 2: Proposed enrollment process for reliable PUFs</figcaption></figure>

### B. Case Study 2: AES Implementation

AES-128 [13] is a widely used symmetric encryption algorithm that processes data in fixed-size blocks of 128 bits (16 bytes). It encrypts 128 bits of plaintext to generate 128 bits of ciphertext using a 128-bit encryption key. The algorithm performs 10 rounds of encryption, each consisting of substitution, permutation, and mixing operations. These rounds make use of a series of round keys generated by expanding the original 128-bit key through a KeyExpansion algorithm. AES implementations are often constrained by their area overhead and speed, which are critical factors in embedded systems, such as FPGAs.

Fig. 3 illustrates the basic schematic of AES-128, highlighting the block-level design that includes the key scheduler, which generates round keys for each encryption cycle.
This encryption process uses session keys, which typically last from a few minutes to several hours and is implemented using two inputs: a plain text and the session (secret) key. If the design were to employ a constant, hardware-wired key, the circuit would benefits significantly in terms of power efficiency, performance, and area optimization at the cost of compromising security. The proposed embedded bitstream generator offers a novel solution for optimizing both the area overhead and speed of the AES-128 implementation by eliminating the conventional key scheduling block while maintaining all the security benefits of using a dynamical session key. Rather than generating round keys dynamically during runtime, the round keys are synthesized together with the circuit. This approach not only removes the need for key storage but also further reduces the area overhead, since all the operations in the KeyExpansion module disappear. In our design, a multiplexer is employed to select from a set of pre-calculated keys, controlled by a counter. This modification simplifies the overall architecture, as key scheduling algorithms are known to be computationally intensive, contributing to increased area usage, power consumption, and critical path delays due to the additional combinatorial logic involved. By replacing the key scheduler with this streamlined multiplexer-based design, the hardware footprint and power consumption are significantly reduced, and operational speed is enhanced.

Fig. 4 presents the schematic of this optimized AES-128 implementation, showing how the key selection mechanism replaces the traditional key scheduler. To evaluate the impact of the proposed design, we conducted a comparative study between two implementations of AES-128: the original design with a key scheduler and the optimized design using the multiplexer. The comparison is performed on two FPGA boards, Zedboard and Zybo, using the proposed open-source tool-chain.

<figure><img src="image_5.png" /><figcaption>Fig. 4: Schematic of the modified version of a 128-bit AES (Advanced Encryption Standard)</figcaption></figure>

Table I presents a performance comparison between the two AES-128 implementations. The results clearly demonstrate that the modified version of the design provides significant improvements in both area and timing. As anticipated, the elimination of the key scheduling block leads to reduced area utilization and improved critical path delays in both cases.

<table><caption>TABLE I: Performance comparison between original and optimized AES designs</caption><thead><tr><td>Design</td><td>Area (LUTs)</td><td>Critical Path (ns)</td></tr></thead><tbody><tr><td>Original design</td><td>1274</td><td>5.23</td></tr><tr><td>Optimized design</td><td>1097 (-14%)</td><td>5.12 (-2.1%)</td></tr></tbody></table>

The execution time of the synthesis and place-and-route processes was also analyzed for both boards, for the synthesis of the modified version of the AES. The Zedboard's FPGA, being larger, required more processing time in the place-and-route step, as seen in Table II. The increase of 82 seconds for the Zedboard compared to the Zybo can be attributed to the larger FPGA, which requires more calculations during the placement and routing phase. However, the final bitstream generation time, despite these differences, remains significant, with the entire process taking around 22 to 27 minutes for both boards.

<table><caption>TABLE II: Execution time to generate the modified AES bitstream on the Zedboard and the Zybo board</caption><thead><tr><td>Step</td><td>Zybo [s]</td><td>Zedboard [s]</td></tr></thead><tbody><tr><td>GHDL (translation)</td><td>6</td><td>6</td></tr><tr><td>Yosys (synthesis)</td><td>300</td><td>320</td></tr><tr><td>Nextpnr (place &amp; route)</td><td>760</td><td>842</td></tr><tr><td>Prjxray (conversion)</td><td>270</td><td>426</td></tr><tr><td><strong>Total</strong></td><td>1336 (≈ 22 min)</td><td>1594 (≈ 27 min)</td></tr></tbody></table>

The results demonstrate that the proposed design methodology offers tangible benefits in terms of area and critical path delay. However, the overall execution time in the embedded processor highlight the need for further optimization in future work. Indeed the scripts in the Prjxray supposedly only consist of sign-off conversion steps but these actually represent a significant portion of the overall generation process.

### C. Case Study 3: Neural networks

Interest of the performing on-board bitstream generation is demonstrated with synthesis of the classic Lenet-5 network[14]. This convolutional network is composed mostly of 5 neuron layers (2 convolutional and 3 dense) and 2 max-pooling layers. So this is a good benchmark to demonstrate the practicability of the proposed flow with a wide variety of operations. The complete VHDL implementation of the pipeline is generated with the open-source project NNawaq [15].

<table><caption>TABLE III: Circuit size with and without keeping hierarchy</caption><thead><tr><td>Metric</td><td>With hierarchy</td><td>Flattened</td></tr></thead><tbody><tr><td>LUT (logic)</td><td>5468</td><td>5000</td></tr><tr><td>LUTRAM</td><td>94</td><td>94</td></tr><tr><td>FF</td><td>6319</td><td>4851</td></tr><tr><td>DSP</td><td>31</td><td>31</td></tr><tr><td>BRAM 36kb</td><td>22.5</td><td>22.5</td></tr></tbody></table>

Logic synthesis results are presented in Table III. The tool Yosys is run in two different conditions, with keeping the design hierarchy and with flattening. This option usually has a strong impact on the footprint of the circuit and on the quality of results. The design is developed and generated in a rather structural way, so the impact on the tool Yosys is moderate, but this is not the general case. For the nextpnr results and the next tools, the design was synthesized with hierarchy kept.
## VI. CONCLUSION

In this work, we introduced a design methodology that enables embedded processors to autonomously generate FPGA bitstreams using open-source tools. This approach leverages FPGA flexibility, offering a solution for developing versatile systems-on-chip and enabling self-sufficient, adaptable computing platforms. While the results demonstrate the feasibility of this novel approach, several limitations remain. The primary constraint encountered was the limited on-board RAM memory (512 MB), which can be extended using techniques such as RAM compression or disk-based swap memory, although these approaches come at the cost of degraded performance and increased energy consumption—key factors that need to be optimized for real-time and energy-sensitive applications. Additionally, the tools used in synthesis, placement, routing, and bitstream generation were originally developed for desktop environments, and some aspects of their implementation would benefit from further optimization. As these open-source tools are still experimental, they lack the reliability and optimization levels needed for production-grade systems, making vendor-provided tools like Vivado currently essential for many applications.

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Is it worth highlighting that the tools seem deterministic and produce identical results when executed on desktop computer and on-board. So the complete flow can be benchmarked on desktop computer before going on-board, notably to monitor the footprint on RAM usage and the performance of generated circuits. Table IV shows the footprint of each tool when run on an average laptop computer based on x86_64 architecture.

<table><caption>TABLE IV: Footprint of the tools on desktop</caption><thead><tr><td>Tool</td><td>Time (s)</td><td>RAM memory (MB)</td></tr></thead><tbody><tr><td>NNawaq</td><td>0.0</td><td>9</td></tr><tr><td>GHDL</td><td>0.1</td><td>23</td></tr><tr><td>Yosys (with hier.)</td><td>26.1</td><td>323</td></tr><tr><td>Yosys (flatten)</td><td>30.3</td><td>356</td></tr><tr><td>Nextpnr (router1)</td><td>231.0</td><td>543</td></tr><tr><td>Nextpnr (router2)</td><td>58.4</td><td>728</td></tr><tr><td>fasm2frames</td><td>34.8</td><td>1157</td></tr><tr><td>xc7frames2bit</td><td>0.1</td><td>10</td></tr></tbody></table>

The placement and routing tool nextpnr offers two routing algorithms with very different scalability. Both routing algorithms produced rather similar performance: 122 MHz for router1, and 126 MHz for router2. So for on-board execution under limited RAM, the algorithm of choice is router1.

<table><caption>TABLE V: Footprint of the tools on board Zybo</caption><thead><tr><td>Tool</td><td>Time (s)</td><td>RAM memory (MB)</td></tr></thead><tbody><tr><td>NNawaq</td><td>0.2</td><td>6</td></tr><tr><td>GHDL</td><td>37</td><td>20</td></tr><tr><td>Yosys (keep hier.)</td><td>721</td><td>230</td></tr><tr><td>Yosys (flatten)</td><td>768</td><td>250</td></tr><tr><td>Nextpnr (router1)</td><td>3720</td><td>405</td></tr><tr><td>Nextpnr (router2)</td><td>800</td><td>(swap used) 465</td></tr><tr><td>fasm2frames</td><td>1390</td><td>(swap used) 489</td></tr><tr><td>xc7frames2bit</td><td>1.1</td><td>8</td></tr></tbody></table>

Results of execution on the board Zybo are presented in Table V. Obviously every tool is slower on this relatively low-performance single-chip device, with slowdown ratios in the range 13x to 40x (with the notable exception of GHDL for which the slowdown is rather extreme, but this tool has marginal relevance for the whole run time). The tools do consume less RAM on-board than on desktop computer. This is due to the on-board processor being 32-bit architecture instead of 64-bit for desktop, so the footprint of software pointers is lower.

The available on-board RAM may still be a serious constraint to comfortably execute the routing operation, especially with algorithm router2. For the sake of presenting these results only, we configured the operating system to use up to 512 MB of swap memory on the SD card. We highlight that this is not a recommended practice, because that kind of workload would kill the SD memory very quickly, and alternatives such as online RAM compression should be preferred.

To conclude on the interest of efficiently offloading this inference task to the FPGA, these results correspond to an inference performance of around 7600 images per second. This is quite significant, and it is not guaranteed that the on-board processors would even be capable of this processing speed. Additional interests are real-time processing independent from the controlling CPU, and very low power consumption (25-150 mW for the FPGA design versus up to 2.2 W for the processor subsystem according to our measures with a USB power meter).