# Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation

Tutu Ajayi, Sumanth Kamineni, Morteza Fayazi, Yaswanth K. Cherivirala, Kyumin Kwon, Shourya Gupta, Wenbo Duan, Jeongsup Lee, Chien-Hen Chen, Mehdi Saligane, et al.

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## To cite this version:

Tutu Ajayi, Sumanth Kamineni, Morteza Fayazi, Yaswanth K. Cherivirala, Kyumin Kwon, et al. "Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation." 28th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC), Oct 2020, Salt Lake City, UT, United States. pp.65-85, 10.1007/978-3-030-81641-4_4. hal-03759730

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# Fully-Autonomous SoC Synthesis using Customizable Cell-Based Analog and Mixed-signal Circuits Generation

Tutu Ajayi¹, Sumanth Kamineni², Morteza Fayazi¹, Yaswanth K Cherivirala¹, Kyumin Kwon¹, Shourya Gupta², Wenbo Duan¹, Jeongsup Lee¹, Chien-Hen Chen², Mehdi Saligane¹, Dennis Sylvester¹, David Blaauw¹, Ronald Dreslinski Jr¹, Benton Calhoun², and David D. Wentzloff¹

¹ University of Michigan, Ann Arbor, MI

² University of Virginia, Charlottesville, VA

**Abstract.** This chapter presents the world's first autonomous mixed-signal SoC framework, driven entirely by user constraints, along with a suite of automated generators for analog blocks. The process-agnostic framework takes high-level user intent as inputs to generate optimized and fully verified analog and mixed-signal blocks using a cell-based design methodology.

The approach is highly scalable and silicon-proven by an SoC prototype which includes 2 PLLs, 3 LDOs, 1 SRAM, and 2 temperature sensors fully integrated with a processor in a 65nm CMOS process. The physical design of all blocks, including analog, is achieved using optimized synthesis and APR flows in commercially available tools. The framework is portable across different planar and FinFET CMOS processes and requires no-human-in-the-loop, dramatically accelerating design time.

**Keywords:** analog synthesis, analog generator, SoC generator

## 1 Introduction

There is an ever-growing need for automation in analog circuit design, validation, and integration to meet modern-day SoC requirements. Time-to-market constraints have become tighter, design complexity has increased and more functional blocks (in number and variety) are being integrated into SoCs. These challenges often translate to increased manual engineering efforts and non-recurring engineering (NRE) costs. FASOC is an open-source<fnref n="3" /> framework for Fully-Autonomous SoC design [1, 2]. Coupled with a suite of analog generators, FASOC can generate complete mixed-signal system-on-chip (SoC) designs from the high-level user specifications. The framework leverages differentiating techniques to automatically synthesize correct-by-construction RTL descriptions for both analog

<footnote n="3">³ Source code for the framework and all generators developed as part of this work can be downloaded from https://github.com/idea-fasoc/fasoc</footnote>
and digital circuits, enabling a technology-agnostic, no-human-in-the-loop im-
plementation flow.

Analog blocks like PLLs, LDOs, ADCs, DC-DC converters, and sensor in-
terfaces are recasted as structures composed largely of digital components while
maintaining analog performance. They are then expressed as synthesizable Ver-
ilog blocks composed of digital standard cells and auxiliary cells (aux-cells). The
framework employs novel techniques to automatically characterize aux-cells and
develop models required for generating bespoke analog blocks. The framework
is portable across processes and scalable in terms of analog performance, layout,
and other figures of merit.

The SoC generation tool translates user intent to low-level specifications re-
quired by the analog generators. The IP-XACT [3] standard is leveraged to
achieve full SoC integration. Added vendor extensions capture additional meta-
data relating to the generated blocks. This enables the composition of vast num-
bers of digital and analog components into a single correct-by-construction de-
sign. The fully composed SoC design is finally realized by running the Verilog
through synthesis and automatic place-and-route (APR) tools to realize full de-
sign automation.

## 2 Overview

<figure><img src="image_4.png" /><figcaption>Fig. 1. FASoC Framework Overview [1]</figcaption></figure>

A high-level representation of the framework is shown in Fig. 1. The *Process setup and modeling* phase is performed once for the process design kit (PDK), and it involves the generation of the aux-cells and models for the generator. The setup process is largely dominated by simulations using the design templates in combination with the characterization scripts. The automation of aux-cell and model generation significantly reduces porting effort across PDKs.
The *SoC generation* phase begins by invoking the *SoC solver* repetitively to translate the high-level user-intent into analog specifications that satisfy the user constraints. The *SoC solver* explores the SoC design space through a combination of mathematical and heuristic system models, to determine the necessary system blocks and their specifications. For instance, it can determine the operating frequency of the PLL to be generated based on the target application, SoC. If targeting a neural network application, it considers parameters such as the supported pipelines, instructions per operation, inference per second and operations per inference. The block generators are invoked as needed and the SoC integrator stitches the composed design and walks it through a synthesis and APR flow to create the final SoC layout. The FASoC framework is tightly integrated with analog generators for PLL, LDO, temperature sensor, SAR ADC, switched-capacitor DC-DC converter and SRAM blocks. Section 4 describes the circuit architecture adopted by the different generators.

## 3 Process Setup and Modeling

<figure><img src="image_5.png" /><figcaption>Fig. 2. Aux-cell and model file generation flow [1]</figcaption></figure>

FASoC employs a synthesizable cell-based approach for generating analog blocks, significantly cutting back on manual layout and verification efforts. Aux-cells are small analog circuits that buttress the standard cell library and provide specific analog functionality required by the generators. Each cell is no larger than a D flip-flop and can be placed on the standard cell rows. The creation of aux-cells is simplified by using a suite of design templates in tandem with PDK characterization scripts. The templates capture the aux-cell's precise circuit behavior without including any PDK-specific information. The characterization scripts operate on the PDK to derive technology-specific parameters required to set knobs within the templates. Example parameters extracted from the PDK include threshold voltage, metal parasitics, MOSFET behavior, and Fan-out of 4. The knobs set within the template include device type, transistor sizing, and other circuit design options. The results from aux-cell generation include the netlist, layout, timing library, and other files required to proceed with conventional synthesis and APR. Presently, the layouts for the aux-cells are manually
created, however, there is an expanding array of tools [4–6] for layout automation that show promising results. The template-based methodology for creating aux-cells enhances process-portability and significantly cuts down on design time. All of the generators presented in this work leverage a suite of aux-cells that are depicted in Fig. 3. The template-based methodology enables users to extend the aux-cell library by creating a design template that captures the respective aux-cell precise behavior without including the PDK information.

<figure><img src="image_6.png" /><figcaption>**Fig. 3.** Schematic for aux-cells used across PLL, LDO and temperature sensor generators [1]</figcaption></figure>

The analog generators use models to predict performance and select design parameters to create optimized block designs that satisfy the input specifications. The models are derived from the parameterized templates that incorporate the aux-cells. The models for each generator vary and are developed from a combination of mathematical equations, machine learning, and design space exploration. The modeling exercise is also performed once per PDK and the results are saved into a model file. Sections 4 briefly describes the modeling approach adopted by each generator integrated into the framework.

## 4 Analog Generator Architecture

Synthesizable analog blocks [7] were introduced a few decades ago and have continued to evolve, closely matching the performance obtainable by full custom designs. Prior works have described techniques for synthesizing analog blocks for UWB transmitters [8], PLLs [9], DACs [10], and other types of analog blocks [11–13]. This approach lowers engineering design costs, increases robustness, eases portability across PDKs, and continues to show promise even at advanced process nodes [14–16]. The analog generators developed as part of this
<figure><img src="image_7.png" /><figcaption>Fig. 4. Analog generator flow [1]</figcaption></figure>

work can be likened to ASIC memory compilers that take in a specification file and produce results in industry-standard file formats, which can then be used in standard synthesis and APR tools. Unlike typical memory compilers, the generators are open-source, process agnostic, and share a scalable framework amenable to different types of blocks. The framework is modular and share a similar process as depicted in Fig. 4. The full generation process is broken down into three steps:

**Verilog Generation:** This step leverages models to produce a synthesizable Verilog description of the block that conforms to the input specifications. It also generates guidance information in a vendor-agnostic format. The guidance includes synthesis constraints, placement instructions, and other information that may be required by the synthesis and/or APR tool to generate blocks that achieve the desired performance. In addition, this step also reports early estimates on performance and the characteristics of the block to be created.

**Macro Generation:** The Verilog and guidance information is passed to a digital flow to create macros that can be embedded into larger SoC designs. The digital flow in this step performs synthesis, APR, DRC, and LVS verification. The digital flow includes an adapter to translate the guidance into vendor-specific commands used in synthesis and APR. The adapter abstraction allows us to (1) express additional design intent without exposing protected vendor-specific commands and (2) easily support multiple EDA tools including open-source alternatives [17–19]

**Macro Validation:** The last step is a comprehensive verification and reporting of the generated block. The full circuit goes through parasitic extraction, SPICE simulations, requirement checks, and other verification to culminate in a detailed datasheet report.

The generators can be invoked standalone, outside of the full SoC generator flow. To simplify the system integration, the AMBA™ APB protocol was adopted as the register interface to all blocks.

The following subsections briefly describe the analog generators currently integrated into the FASoC framework.

## 4.1 PLL

The generated PLLs (Fig. 5) share the same base architecture as ADPLL [20]. The phase difference of the reference and output clocks are captured by the
<figure><img src="image_8.png" /><figcaption>Fig. 5. DCO architecture indicating the aux-cells and designs parameters [1]</figcaption></figure>

embedded time-to-digital converter (TDC), while the digital filter calculates the frequency control word for the digitally controlled oscillator (DCO). The input specification to the generator defines the nominal frequency range and in-band phase noise (PN). The PLL generator uses a physics-based mathematical model [21] for characterization. The first step is building a mathematical relationship between DCO design parameters (number of aux-cells and stages) and the required DCO specifications. Using simulation results from a parametric sweep, the effective ratio of drive strength and capacitance can be derived for each aux-cell. This ratio enables us to predict frequency and power results (frequency range, frequency resolution, frequency gain factor, and power consumption) given a set of input design parameters.

## 4.2 LDO

The generated LDOs (Fig. 6) share the same base architecture as DLDO [22]. The LDO leverages an array of small power transistors that operate as switches for power management. Based on design requirements, the generator can swap the clocked comparator with a synthesizable stochastic flash ADC [23] to improve transient response. The input specifications to the LDO generator are the V<sub>IN</sub> range, I<sub>load,max</sub> range, and the dropout voltage. The generator uses a poly-fit model of the load current (I<sub>load,max</sub>) performance for various combinations of aux-cell connections (connected in parallel and for different VDD inputs) in both ON and OFF states. The model is created by simulating various test circuits after parasitic extraction.
<figure><img src="image_9.png" /><figcaption>Fig. 6. LDO architecture indicating the aux-cells and design parameters derived from input specifications of V<sub>IN</sub>, I<sub>load</sub> and desired transients [1]</figcaption></figure>

4.3 Temperature Sensor

<figure><img src="image_10.png" /><figcaption>Fig. 7. Temperature sensor architecture indicating the aux-cells [1]</figcaption></figure>

The generated sensors (Fig. 7) share the same base architecture as [24]. The sensor relies on a temperature-sensitive ring oscillator and stacked zero-VT devices for better line sensitivity. The input specifications include the temperature range and optimization strategy, for either error or power. For a given temperature range, the generator first checks a modeling file to select an optimized design model. If the modeling file is not already present, the generator will sweep the design parameters and start the internal simulations. The results are then utilized to train a predictive Bayesian neural network model. Doing this can considerably reduce the total simulation time and predict the best design parameters that can match the input specifications.
## 4.4 SAR ADC

<figure><img src="image_11.png" /><figcaption>Fig. 8. SAR ADC architecture indicating the aux-cells</figcaption></figure>

The generated SAR ADC (Fig. 8) utilizes the same base architecture as [25], which consists of capacitors, switches, a comparator, and a SAR controller. The Capacitor DAC includes the capacitor arrays and switches, it samples the differential signals at the input. The comparator uses a NAND-based structure, which is more suitable for design synthesis. The SAR controller generates the control signals for switches in the Capacitor DAC and the comparing clock for the NAND-based comparator. The input specification includes the sampling frequency, the target effective number of bits (ENOB), and the optimization method (for either power or area). For a given ENOB value, the generator selects the optimal number of switches that can satisfy the target sampling frequency.

## 4.5 Switched-capacitor DC-DC converter

<figure><img src="image_12.png" /><figcaption>Fig. 9. Switched-Capacitor DC-DC converter architecture indicating the aux-cells</figcaption></figure>
The generated switched-capacitor DC-DC converter (Fig. 9) utilizes the same base architecture as [26], which consists of multiple stages of 2:1 converters. The conversion ratio of the DC-DC converter is determined by the number of 2:1 converter stages and their configuration. The 2:1 converters are composed of 3 different aux-cells: DCDC_CAP_UNIT, DCDC_XSW_PMOS, and DCDC_XSW_NMOS. One additional aux-cell, i.e. DCDC_NOV_CLKGEN, is also required to generate two non-overlapping clock signals and their inverted signals for the 2:1 converters. Based on the input specifications ($V_{IN}$, $V_{out}$, $I_{load}$, and $f_{clk}$), the generator finds the optimal number of aux-cells in the 2:1 converters as well as determining the number of stages and their configuration.

## 4.6 SRAM

<figure><img src="image_13.png" /><figcaption>Fig. 10. SRAM architecture showing macros and bank strategy</figcaption></figure>

A third party Commercial memory compilers (CMCs) [27–29] can generate an SRAM for a given PDK. However, they are the outcome of a human-driven design effort for each PDK and cover a fixed design space that usually emphasizes high performance. Such limitations restrict compilers’ usage for applications such as ultra-low-power systems, which often operate in the nW to µW space. More importantly, the CMCs are not open source and may not be readily available due to cost or licensing issues, especially for newer technologies. Hence, a memory macro generation framework [30] is developed to address these issues and allow easy and autonomous generation of optimized memory macros in the design space where CMCs can not be used.

The memory generator creates fully-functional tapeout-ready integrated memories across a broad range of user specifications. The compiled SRAMs (Fig. 10) follow a standard multi-bank memory architecture. The memory generator uses a 6T bitcell, a row decoder, column mux, wordline driver, sense amplifier, write driver, and a pre-charge circuit as the aux-cells. The aux-cells are stitched together, bottom-up, to form a bank, and then a multi-bank memory. The user
input specifications are capacity, word size, operating voltage, and operating frequency. The generator adopts a hierarchical memory model to determine the optimal row and column periphery. The model helps to select the SRAM architecture and the leaf-level components that best satisfy the user specifications while minimizing energy consumption and delay.

# 5 SoC Generation

The top-level SoC generation begins with an iterative *SoC solver* to determine the optimal *composite design* which is a combination of blocks, analog specifications, and module connectivity. The strategy is guided by high-level user intent (i.e. target application and power/area budgets), available analog block generators, and a database of IPs. Analog generators are then invoked as necessary to generate bespoke blocks required to satisfy the specifications within the composite design. The generator outputs include all artifacts required to push the block through standard synthesis and APR tools. The outputs are also cached in an *IP database*, allowing for faster SoC generation if a matching entry already exists. Entries in the database can also be populated with 3rd party IPs such as processors and other peripherals.

The IP-XACT format is adopted to describe the composite design as well as the block designs stored in the database. Added Vendor extensions [31] capture additional analog data, simulation, and verification information. The *SoC integrator* begins by stitching the composite design together and translating it to its structural Verilog equivalent that can be run through digital simulation tools. The structural Verilog, along with all required artifacts from the database, is then passed through the embedded EDA tool flow to generate the final verified GDS. This same flow is pervasive across the framework and is also used by all generators (aux-cell, model, and analog). Tools within the flow cover all aspects of chip design including SPICE simulations, digital simulations, synthesis, APR, DRC, LVS, and extraction.

The rest of this section describes key components that make up the SoC generation stage.

## 5.1 SoC Solver

The primary task of the SoC solver is to derive a feasible solution to the supplied user intent and further derive an optimal solution that satisfies the intent. The user intent provides a basic sketch of the target application and includes minimal information relating to the performance, power, and area requirements. The solver takes an iterative approach to perform targeted design space exploration based on predictions learned from prior executions of the analog generators. It essentially builds a correlation between the user intent, analog block specifications (of all supported generators), and the generated block results.

Although the solver relies on a database of existing IP for faster iteration, it can quickly start from a cold cache to narrow down to an optimal solution. The
run-time of the solver is based on the number of blocks in the design, supplied budget, and how warm the cache is. The solver employs a heuristic algorithm to optimize the overall SoC metrics including power, performance, area, and other figures of merit.

The primary result of this process is a composite design in the form of a structural netlist. The netlist includes all specific module instances and information describing the ports and connectivity of all modules that constitute the design. The stitching process employs standard Arm AMBA protocols (e.g. APB and AHB) and includes all necessary interconnects and multiplexers.

## 5.2 IP-XACT and Database

The database entries are implemented using IP-XACT++, an extended version of IP-XACT. The added vendor extension catalogs supplemental meta-data relating to the IP. This non-tabular format allows for the storage of the PPA metrics as well as other figures of merits specific to each generator. This is in addition to the traditional IP information like ports, interfaces, memory maps, and validation data. The information associated with each generated instance of the IP allows the SoC Solver to quickly search the database for specific parameters and eases the stitching process to create the final netlist.

## 5.3 Embedded EDA Flow

The framework relies on an embedded EDA tool flow to accelerate the RTL-to-GDS process. It is a set of scripts and methodologies that leverage commercial EDA tools to accomplish the task of walking arbitrary designs through the synthesis and implementation process as quickly as possible. It builds on several modular abstractions to provide a PDK agnostic flow. Figure 11 shows the main abstractions inherent within the tool flow.

<figure><img src="image_14.png" /><figcaption>Fig. 11. Embedded EDA tool flow abstractions</figcaption></figure>
**Flow scripts:** These are robust reference scripts for all the steps in the flow. It is collection of scripts span several EDA vendors used throughout the steps. It contains the best practices and recommendations from the tool providers and has been stitched together to form a generic end-to-end flow that can easily be customized based on several factors.

**Platform Configuration:** These constitute the PDK specific information, configurations, rules, and requirements for a specific technology node. There is a one-time effort to create this customization for newly supported technologies, however, subsequent designs can re-use that effort transparently

**Site Configuration:** These are configuration parameters that establish points to the required site-specific information. These are file paths to the PDK, standard cells, tool binaries, and license information for the EDA tools.

**Design Files:** This is the design-specific information that contains significantly less information about the EDA tools, PDK, and Site location since those have mostly been abstracted away and are expressed as customization to the generic flow in the EDA scripts. It is intended to express the actual design intent with little reference to the other abstractions.

Combined, these modular abstractions can be customized and combined together to form a block or chip specific flow. The various steps supported in the flow are simulation, synthesis, APR, LVS, DRC and extraction. It has support for 13 PDKs and has been validated with 6 different tape-outs across different PDKs. The flow is used at various levels and steps within the FASoC framework and has also been leveraged for other projects.

# 6 Evaluation

The framework has been fully verified in a planar 65nm and FinFET 12nm processes. The evaluation begins with a focus on the individual generators. The results presented explore the design-space possible with each generator and demonstrate full adherence to the user input specification in a 65nm process. Results are then presented from a prototype SoC created in 65nm process using this framework.

## 6.1 Analog Generation Results

Fig. 12 presents the results of several PLLs generated using different input specifications. It compares the input requirements against the simulated results after parasitic extraction. The results show that the generated frequency ranges cover that of the input requirements and with better phase noise levels. The highlighted PLL 8, corresponds to one of the PLLs integrated into the SoC prototype and also shows measured results that satisfy the given specifications

Fig. 13 shows the spice simulation results of multiple LDO designs after parasitic extraction. The graph shows the maximum load current at different input voltages corresponding to the input parameter array size for a dropout voltage of
<figure><img src="image_15.png" /><figcaption>**Fig. 12.** Generated PLL designs for eight different input specifications. PLL1 is taped-out in the SoC prototype [1]</figcaption></figure>

50mV. The highlighted measurements correspond to the input specification for blocks integrated into the SoC prototype with $V_{IN}$ = 1.3V and $V_{REG}$ = 1.2V.

Fig. 14 presents the simulation results of various memory capacities across a broad range of architectural options and operating voltages (VDD). Each point on the curve corresponds to an energy-delay pair specific to an architecture (rows, columns, and banks) and VDD combination. The generator selects the Pareto-optimal design that satisfies the user requirements. The highlighted point on the 16KB curve corresponds to the memory block integrated into the SoC prototype.

Fig. 15 shows the spice simulation results of multiple temperature sensor designs after parasitic extraction.

Fig. 16 presents the simulation results of various numbers of $V_{cm}$ switches. The generator selects the optimized value to satisfy the input specifications. By using a common-centroid placement strategy on the capacitors, the generator can also reduce the systematic mismatch which affects the accuracy of capacitance ratios. Table 1 shows the spice simulation results of cdl and pex netlists that closely match the input specifications with an area optimization.
<figure><img src="image_16.png" /><figcaption>Fig. 13. $I_{load,max}$ vs. array size, for multiple LDO designs generated [1]</figcaption></figure>

<figure><img src="image_17.png" /><figcaption>Fig. 14. Normalized energy and delay plots for various memory sizes while sweeping VDD. The results are normalized with respect to the 8KB memory. [1]</figcaption></figure>

<table><caption>Table 1. ADC Simulation Results</caption><thead><tr><th>Output Specifications</th><th>CDL</th><th>PEX</th></tr></thead><tbody><tr><td>Sampling Freq (MHz)</td><td colspan="2">1</td></tr><tr><td>Unit Cap Value (fF)</td><td colspan="2">2.6</td></tr><tr><td>Area (mm²)</td><td>-</td><td>0.04</td></tr><tr><td>Power dissipation (µW)</td><td>6.72</td><td>11.2</td></tr><tr><td>Effective Number of Bits</td><td>7.86</td><td>7.75</td></tr></tbody></table>
<figure><img src="image_18.png" /><figcaption>**Fig. 15.** Power and Error results against temperature for various temperature sensor designs (each fitted plot represents a unique design) [1]</figcaption></figure>

<figure><img src="image_19.png" /><figcaption>**Fig. 16.** Effective Number of Bits vs. Number of switches for V<sub>cm</sub></figcaption></figure>
## 6.2 Prototype Chip Results

The 65nm prototype SoC design (Fig. 17) features 2 PLLs, 3 LDOs, a 16KB SRAM, and 2 temperature sensors fully integrated with an Arm® Cortex™-M0 in a 65nm CMOS process. Using off-chip connections, the entire SoC can be powered using one of the LDOs and clocked using the PLLs while monitoring the temperature of the chip.

<figure><img src="image_20.png" /><figcaption>**Fig. 17.** Simplified block diagram (a) and annotated die photo (b) for the 65nm prototype SoC [1]</figcaption></figure>

A similar 12nm prototype SoC (Fig. 18) features a PLL, 2 LDOs, a 64KB SRAM, 3 temperature sensors, a bluetooth transmitter, 2 SAR ADCs, a switched-capacitor DC-DC converter fully integrated with an Arm Cortex-M0 processor.

Fig. 12 presents results for 8 PLL designs generated from different input specifications, including one from the prototype, and the results show output performances in-line with the input specifications. The measured frequency is 10% slower while the phase noise matches the simulation and specification requirement. Table 2 summarizes the results for all PLLs in the prototype.

Table 3 shows the LDO $I_{load,max}$ measurements closely matching the input specification requirements. Compared to the comparator-based architecture (LDO1/2), the ADC based controller architecture (LDO3) achieves better transient performance with a 10x and 7x improvement in settling time and undershoot voltage respectively. The line and load regulation values are measured at
<figure><img src="image_21.png" /><figcaption>**Fig. 18.** Simplified block diagram (a) and annotated die photo (b) for the 12nm prototype SoC</figcaption></figure>

<table><caption>**Table 2.** PLL Simulation vs Measurement Results [1]</caption><thead><tr><th rowspan="2">Output Specifications</th><th colspan="2">PLL1</th><th colspan="2">PLL2</th></tr><tr><th>Sim</th><th>Meas</th><th>Sim</th><th>Meas</th></tr></thead><tbody><tr><td>Min Freq (MHz)</td><td>200</td><td>190</td><td>170</td><td>150</td></tr><tr><td>Max Freq (MHz)</td><td>1,060</td><td>920</td><td>1,080</td><td>930</td></tr><tr><td>F<sub>nom</sub> (MHz)</td><td>643</td><td>558</td><td>627</td><td>548</td></tr><tr><td>Power@F<sub>nom</sub> (mW)</td><td>7.20</td><td>6.90</td><td>8.06</td><td>7.70</td></tr><tr><td>Area (µm<sup>2</sup>)</td><td colspan="2">167,639.04</td><td colspan="2">167,639.04</td></tr></tbody></table>

<table><caption>**Table 3.** LDO Simulation vs Measurement Results @ 200MHz control clock [1]</caption><thead><tr><th rowspan="2">Output Specifications</th><th colspan="2">LDO1</th><th colspan="2">LDO2</th><th colspan="2">LDO3</th></tr><tr><th>Sim</th><th>Meas</th><th>Sim</th><th>Meas</th><th>Sim</th><th>Meas</th></tr></thead><tbody><tr><td>Dropout Voltage (mV)</td><td>50</td><td>70</td><td>50</td><td>80</td><td>50</td><td>80</td></tr><tr><td>I<sub>load,max</sub> (mA)</td><td>15.00</td><td>15.38</td><td>25.00</td><td>24.84</td><td>25.00</td><td>23.72</td></tr><tr><td>Settling Time - Ts (µs)</td><td>1.1</td><td>1.8</td><td>2.1</td><td>2.9</td><td>0.12</td><td>0.19</td></tr><tr><td>Max Undershoot (V)</td><td>0.35</td><td>0.98</td><td>0.57</td><td>0.98</td><td>0.38</td><td>0.14</td></tr><tr><td>Max Current Eff. (%)</td><td>94.2</td><td>96.4</td><td>95.7</td><td>94.5</td><td>81.9</td><td>74.0</td></tr><tr><td>Load Regulation (mV/mA)</td><td>-</td><td>-1.00</td><td>-</td><td>-0.35</td><td>-</td><td>-3.6</td></tr><tr><td>Line Regulation (V/V)</td><td>-</td><td>0.180</td><td>-</td><td>0.004</td><td>-</td><td>0.950</td></tr><tr><td>Area (µm<sup>2</sup>)</td><td colspan="2">17,318.56</td><td colspan="2">31,187.56</td><td colspan="2">127,163.56</td></tr></tbody></table>

$V_{IN}=1.3$V, $V_{REF}=1.2$V, and $I_{load}=10$mA. LDO3 load regulation is comparatively worse due to the high gain of the ADC based controller. While operating
at lower $V_{REF}$ and $I_{load}$ conditions, the line/load regulation degrades for all the LDOs because of the increase in relative switch strength.

The temperature sensor has an area of 2,620µm². A 2-pt calibration is performed at 0°C and 80°C. Measured results show a sensing range between -20°C and 100°C with an accuracy of ±4°C.

<figure><img src="image_22.png" /><figcaption>**Fig. 19.** Measured and simulated performance and power results of SRAM across VDD [1]</figcaption></figure>

Fig. 19 summarizes the SRAM measured and simulated performance across the input operating voltage range of 0.8V to 1.2V. The SRAM peak performance is at 65MHz with the power consumption of 2.09mW at 1.2V, which exceeds the targeted frequency of 50MHz. The measured power for the SRAM also include the leakage power of the processor and peripheral interface. The generated SRAM has an area of 0.68mm² with the custom bitcell area occupying 0.4mm².

## 7 Conclusion

This chapter presented an autonomous framework that generates a completely integrated SoC design based on user input specifications. The framework is PDK agnostic and allows for faster turn-around times when building custom analog blocks and integrating them into larger SoC designs. The framework includes generators for PLL, LDO, temperature sensor, SAR ADC, switched-capacitor
DC-DC, and SRAM blocks. The framework can easily be extended to support more generators and different PDKs. The framework's validation was performed by creating and fabricating SoC prototypes in 12nm and 65nm processes. Silicon measurements for the analog blocks were inline with user requirements and simulation results. This work establishes a new milestone in creating a silicon compiler [32] that further reduces the complexity of realizing modern SoCs and cuts down on design time.

## Acknowledgment

This material is based on research sponsored by Air Force Research Laboratory (AFRL) and Defense Advanced Research Projects Agency (DARPA) under agreement number FA8650-18-2-7844. The U.S. Government is authorized to reproduce and distribute reprints for Governmental purposes notwithstanding any copyright notation thereon.

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