# InP/GaAsSb Double Heterojunction Bipolar Transistor Characterization and Compact Modelling up to 500 GHz

Marina Deng, Chhandak Mukherjee, Lucas Réveil, Akshay Arabhavi, Sara Hamzeloui, Colombo Bolognesi, Magali de Matos, Cristell Maneux

► To cite this version:

Marina Deng, Chhandak Mukherjee, Lucas Réveil, Akshay Arabhavi, Sara Hamzeloui, et al. InP/GaAsSb Double Heterojunction Bipolar Transistor Characterization and Compact Modelling up to 500 GHz. IEEE Transactions on Electron Devices, 2025, 72 (1), pp.175-180. 10.1109/TED.2024.3506505. hal-05056638

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# InP/GaAsSb Double Heterojunction Bipolar Transistor Characterization and Compact Modelling up to 500 GHz

Marina Deng, Member, IEEE, Chhandak Mukherjee, Member, IEEE, Lucas Réveil, Member, IEEE, Akshay M. Arabhavi, Sara Hamzeloui, Colombo R. Bolognesi, Fellow, IEEE, Magali De Matos, Member, IEEE, and Cristell Maneux, Member, IEEE

**Abstract**— This paper presents a new methodology to accurately characterize InP bipolar transistors up to 500 GHz. Following design optimization of RF test structures specifically developed for the on-wafer TRL calibration technique, InP/GaAsSb Double Heterojunction Bipolar Transistors have been successfully characterized up to 500 GHz. Moreover, the HICUM compact model was validated against measurements for different operating conditions and various geometries for the first time up to 500 GHz. The physics-based compact model and the associated scalable parameter extraction flow allowed us to demonstrate the scalability of this THz InP DHBT technology, offering possibilities for further design-level explorations. State-of-the-art cut-off frequencies of this THz transistor technology featuring $f_{MAX}$ reaching 1 THz for transistor geometries with 0.15 µm-emitter-widths were experimentally verified and confirmed by the compact model predictions.

**Index Terms**— characterization, compact modelling, heterojunction bipolar transistors, high frequency, indium-phosphide, sub-millimeter wave, terahertz

## I. INTRODUCTION

As 5G is being widely deployed around the world concurrently with the imminent advent of 6G, we are experiencing a constant need for ever-increasing data rates to support the growing usage of high-bandwidth applications. To mention a few, beyond 5G and 6G mobile communication systems [1], imaging, sensing [2] and space applications are driving the development of terahertz (THz) technologies. Owing to the advancements in the last decade, both silicon and III-V compound semiconductors, exhibiting transistor cut-off frequencies of beyond 600 GHz [3]-[6] and even exceeding the frequency of 1 THz [7],[8], are now capable of addressing

these emerging THz applications. While silicon technologies are more suitable for mass-market millimeter-wave applications due to their very large-scale integration density capabilities at a lower cost, III-V compound semiconductors usually outperform them in terms of cut-off frequencies and power handling capabilities. In particular, Indium-Phosphide (InP) double heterojunction transistors (DHBT) are an alternative candidate for these applications, due to their superior gain and output power in the sub-THz frequency range (0.3-1 THz) [9],[10], compared to Silicon-Germanium (SiGe) HBTs. However, the monolithic heterogeneous integration of InP DHBTs with SiGe BiCMOS technology is envisioned for an optimal combination of advantages offered by both technologies [11]-[13]. Nevertheless, accurate on-wafer measurements are crucial to assess and confirm the RF performances of THz electronic devices in the millimeter and sub-millimeter wave frequency ranges of interest for integrated circuit design. For InP DHBTs, most of the previously reported frequency figures of merit were obtained from measurements performed below 110 GHz using off-wafer calibration methods, such as SOLT or LRRM [4]-[8],[10]. Conventionally, the transit frequency ($f_T$) and maximum oscillation frequency ($f_{MAX}$) are extracted through a single-pole fit on the measured current gain $H_{21}$ and the Mason unilateral gain ($U$), respectively. Experimental verification beyond 110 GHz therefore remains imperative in order to confirm such high values of extracted $f_{MAX}$. To that end, in our previous work [14], on-wafer Thru-Reflect-Line (TRL) calibration and de-embedding test structures were designed in order to characterize an earlier generation ($G1$) of InP/GaAsSb DHBTs fabricated at the ETH Zurich. From the on-wafer measurements up to 330 GHz, we could successfully confirm the expected peak $f_T/f_{MAX}$ of 500/700 GHz for this $G1$ InP DHBTs. With the continuous enhancement of InP DHBT cut-off frequencies in subsequent generations, along with an increasing need for accurate RF measurements, the test structure design has been further optimized, leading to the development of the second generation ($G2$) of test structures. In light of the aforementioned, the present paper has two principal objectives. The first is to present a comprehensive methodology for conducting high-frequency on-wafer transistor characterisation, which has been realised for the first time at frequencies up to 500 GHz for this technology (Section

This work was supported in part by the French National Research Agency (ANR) through the ULTIMATE project under Grant ANR-16-CE93-0007 and in part by the Swiss National Science Foundation (SNSF) and the Chips Joint Undertaking and its members, including the top-up funding by National Authorities, through the Move2THz European project under Grant 101139842.

M. Deng, C. Mukherjee, L. Réveil, M. De Matos and C. Maneux are currently with IMS laboratory, University of Bordeaux, Talence, France (e-mail: marina.deng@ims-bordeaux.fr).

A. Arabhavi, S. Hamzeloui and C. R. Bolognesi are with the Department of Information Technology and Electrical Engineering, ETH Zurich, 8092 Zürich, Switzerland (e-mail: bolognesi@mwe.ee.ethz.ch).
II), and which remains valid for InP bipolar technologies in general. The second is to present the experimental validation of physics-based scalable compact modelling using HICUM for this device generation up to 500 GHz. The validation of the HICUM model for InP bipolar technologies was achieved for the first time at such high frequencies, under various operating conditions and for a large number of device geometries (Section III). This article thus presents an improved co-optimization methodology which combines dedicated approaches for characterization and modelling at sub-THz frequencies, which is pivotal for bridging the gap between the III-V bipolar transistor community and the future THz circuit design efforts.

## II. TECHNOLOGY PROCESS AND ASSOCIATED TEST STRUCTURE IMPROVEMENTS

### A. Device Structure and Fabrication

The epitaxial structure growth and device fabrication, for the DHBTs characterized in this work, were carried out at the FIRST-Lab of ETH-Zurich. The transistors were grown by Metal-Organic Chemical Vapour Deposition (MOCVD) on a 2-inch semi-insulating substrate. The emitter consists of a graded composite GaInP/InP emitter which eliminates the conduction band offset at the E-B interface and minimizes emitter size effects [15]. The 20-nm composite emitter doped at $2.2 \times 10^{16} \text{ cm}^{-3}$ is followed by a 130 nm thick $n^+$-InP layer (doped at $1.4 \times 10^{19} \text{ cm}^{-3}$) and a 35 nm GaInAs heavily doped emitter contact. The base is a 20-nm GaAs$_x$Sb$_{1-x}$ layer implemented with an As-mole fraction ramped from $x=0.60$, at the emitter, to $x=0.40$, at the collector interface. In addition, the base layer incorporates a linear grading of the carbon p-doping with an averaged level of ~$8 \times 10^{19} \text{ cm}^{-3}$. TLM measurements indicate a base sheet resistance of $R_{SH} = 1200 \ \Omega/\square$. The InP 125-nm-collector layer is doped at $1.05 \times 10^{17} \text{ cm}^{-3}$.

The DHBTs were fabricated by a standard self-aligned triple mesa process with emitter and base contacts defined by e-beam lithography. The G2 DHBTs are scaled down to 150 nm emitter widths to enhance $f_{MAX}$. Using the emitter metal as a mask, the emitter mesa was etched by a combination of inductively coupled plasma-reactive ion etching (ICP-RIE) and wet etching. The self-aligned base contacts with a contact resistivity of ~$1 \ \Omega \cdot \mu\text{m}^2$ are formed after in-situ cleaning of the base surface using Ar sputtering. The emitter and the base metal stacks consist of Ti/Pt/Au and Pd/Ni/Pt/Au, respectively. The emitter sidewall and extrinsic base surface were passivated by atomic layer deposited AlOx. Finally, the base-collector mesa was formed using dry/wet etch combinations. In contrast with G1 DHBTs reported in [14], the undercut etching of the GaAsSb base in G2 was optimized to define a base contact width to be close to the transfer length of ~50 nm, so that only a transfer length worth of material remains under the base metal. A FIB/SEM cross-section of the fabricated device is shown in Fig. 1.

A Ti/Pt/Au collector contact is formed after the base-collector mesa formation by optical lithography and e-beam evaporation. Next, the devices are isolated by wet etching, and the Cr/Pt resistors with a sheet resistance of 28-30 $\Omega/\square$ are

evaporated on the semi-insulating substrate. Following a low-temperature planarization of the Teflon, the newly designed G2 contact pads are deposited to enable high-frequency characterization.

### B. Test Structure Improvements Towards Measurements up to 500 GHz

Based on electromagnetic (EM) simulations representing the actual RF probes and the complete chip layout of G1, coupling effects were observed in G1 measurements up to 500 GHz and their types were identified in [14]: i) coupling with neighboring structure, ii) coupling between RF ports (crosstalk), iii) coupling between RF probes and the substrate. The implementation of a continuous shielding ground plane was then proposed in order to mitigate both the coupling between neighboring structures and the probe-to-substrate coupling. The effectiveness of the continuous ground plane was successfully tested in [16] for SiGe HBTs and for type-I InP DHBTs [17] through on-wafer characterizations. For the G2 technology, the coplanar waveguide (CPW) transmission line widths and gaps were reduced in order to prevent parasitic coupling modes expected in a CPW line topology. The THRU length (see Fig. 2) was slightly increased from 60 µm in G1 to 100 µm in G2 to further minimize the crosstalk. This choice, however, was made at the expense of the device density, as it results in larger test structures for all devices present on the chip. More importantly, the 8-term error model, used in the TRL calibration procedure, does not account for crosstalk correction, which is later compensated at the de-embedding step. After on-wafer TRL calibration, the reference plane was set at the inner edge of the access lines, as indicated by dashed lines in Fig. 2. The residual parasitics stemming from the transistor interconnects were removed through an additional Short-Open de-embedding step.

The fabrication steps were adapted to incorporate the formation of the continuous ground plane in the existing fabrication process. From Figs. 2 and 3, showing respectively the THRU, OPEN and SHORT structures, we can see that the G1 structures were isolated from each other while the G2 structures are surrounded by gold deposition, connecting all ground pads together to form one continuous ground plane across the wafer. The G2 also includes thicker pads for multiple probing on the same structure to ensure a better band continuity in the measurements.

Compared to G1, the benefits of the G2 design are manifold. Better accuracy and frequency band continuity can be

<figure><img src="image_2.png" /><figcaption>Fig. 1. Cross-sectional electron micrograph of a DHBT with 150 nm emitter mesa width. The base-collector mesa undercut etch was optimized resulting in a base contact width of ~50 nm to reduce the extrinsic B-C capacitance.</figcaption></figure>
observed in the OPEN and SHORT measurements up to 500 GHz (see Figs. 4 and 5). To validate the physical trend of the measurements, EM simulations of the G1 and G2 OPEN and SHORT test structures were performed, which showed quite good agreement with the experimental data, thus confirming the parasitic contributions from the transistor interconnects extracted from measurements: $C_{open_{1,2}}=5$ fF and $L_{short_{1,2}}=10/15$ pH. $C_x$ and $L_x$ refer to the lumped elements of the electrical equivalent circuits of the OPEN and SHORT structures reported in [14]. The experimental values of these parasitic elements being frequency-independent, as ideally required for the SHORT-OPEN de-embedding model, the validity of using such a conventional de-embedding method can be ensured even up to 500 GHz.

### C. HICUM Compact Model Parameter Extraction

The HICUM compact model [18] has been proven to be efficient for capturing the behaviour of type-I and type-II InP DHBTs [19]-[20], even at very high frequencies (up to 330 GHz) [14]. Consequently, for the new G2 technology, scalable parameter extraction using HICUM model (L2 V2.4.0) was performed at even higher frequencies (up to 500 GHz) in order to provide a physical validation of the transistor measurements. This was achieved using a specific HICUM parameter extraction flow [19], accompanied by an in-house scaling library for different geometries under test, following sequential extractions of: i) the B-E and B-C junction capacitances for different bias conditions (see Fig. 6), ii) base and collector current parameters in the low to medium injection range (see Fig. 7), and iii) transit time parameters under low/medium and high injection conditions. The principle of scalable extraction relies on extraction of global parameter values that are then scaled according to the library of scaling rules for each individual device. An effective strategy is therefore to fix the emitter length for different emitter widths (and vice versa) so that current related parameters (normalized Gummel plot, $I_C/\exp(V_{BE}/V_T)$ and base-emitter recombination current) and junction capacitances ($C_{BC}$ and $C_{BE}$) can be extracted at ambient temperature (25 °C) allowing for parameter extraction at low and medium injections. The transit time parameters can then be extracted with help of the measured $f_{MAX}$ and $f_T$ characteristics first at $V_{BC}=0$ V, in order to extract zero bias transit time, followed by the extraction of delay time constants of the transit time

<figure><img src="image_3.png" /><figcaption>**Fig. 2.** Top-view optical image of the THRU standard dedicated to on-wafer TRL calibration for (a) G1 and (b) G2.</figcaption></figure>

<figure><img src="image_4.png" /><figcaption>**Fig. 3.** Top-view optical images of OPEN (first row) and SHORT (second row) test structures dedicated to transistor's de-embedding from G1 and G2.</figcaption></figure>

<figure><img src="image_5.png" /><figcaption>**Fig. 4.** EM simulation (lines) of (a) OPEN capacitances and (b) SHORT inductances compared to on-wafer TRL calibrated measurement data up to 500 GHz (symbols) from G1.</figcaption></figure>

at varying $V_{BC}$ and critical current-related parameters under high-injection conditions. The above extraction procedure can then be repeated for other temperatures to extract temperature coefficients and self-heating parameters. Further details on the parameter extraction procedure can be found in [21]. Even though HICUM is principally optimized for SiGe HBT technologies, a good overall model accuracy and scalability is observed for the InP DHBTs under test.

## III. INP/GAASSB DHBT CHARACTERIZATION UP TO 500 GHz

### A. S-parameter Measurements up to 500 GHz

For the high frequency characterizations of the InP DHBTs up to 500 GHz, four measurement benches were necessary in order to perform the S-parameter measurements: i) a 1-110 GHz bench using an Agilent E8361A PNA with N5260-600003 millimeter-wave extenders beyond 67 GHz, and ii) 140-220 GHz, 220-330 GHz and 325-500 GHz benches, all three utilizing both a Rohde & Schwarz ZVA24 and frequency extenders. We made use of the same on-wafer TRL calibration kit up to 500 GHz, with two different Line standards for the 1-110 GHz and the 140-500 GHz bands.

Figs. 8 and 9 present all four S-parameters obtained from measurements and HICUM model simulations up to 500 GHz using the scalable model parameter set extracted earlier, in magnitude and phase, for a $0.15 \times 5 \ \mu m^2$ InP DHBT, mounted in common-emitter configuration and biased at a fixed $V_{CE}=1$ V and with a $V_{BE}$ sweep from 0.82 V to 0.9 V in steps of 200 mV. For model extrapolation, we
<figure><img src="image_6.png" /><figcaption>Fig. 5. EM simulation (lines) of (a) capacitances and (b) $S_{11}$ of the OPEN structure, (c) inductances and (d) $S_{11}$ of the SHORT structure, compared to on-wafer TRL calibrated measurement data up to 500 GHz (symbols) from G2.</figcaption></figure>

optimized the high frequency part of the data (especially after 40 GHz) through related parameters such as parameters related to non-quasistatic effects (NQS) [18] along with parasitic capacitance partitioning factors that play an important role at higher frequencies. Moreover, we also considered an external collector-substrate coupling capacitance through an external sub-circuit to capture the frequency-dependence of the cut-off frequencies. The comparison between measurement and simulation results shows an overall fair agreement, further affirming the validity of the scalable parameter extraction even at very high frequencies. Despite a few known limitations of HICUM for III-V HBTs, such as $C_{BC}$ modelling for technologies with complex collector doping profiles [22] [23], our results showcase that the HICUM model remains sufficiently reliable for predictive analyses and performance extrapolation of III-V bipolar transistors up to 500 GHz, demonstrated for the first time in this work. Given that the overall trend of experimental data is correctly captured by HICUM, some minor discrepancies still remain (such as $|S_{11}|$ in Fig. 8(a)). It is to be noted that any visible deviation in the model occurs only after 300 GHz, indicating that additional efforts for further model improvement (such as substrate effects) might

<figure><img src="image_7.png" /><figcaption>Fig. 6. HICUM simulation (line) of the total (a) Base-Collector and (b) Base-Emitter junction capacitances versus $V_{BC}$ and $V_{BE}$ respectively, compared to measurements (symbols).</figcaption></figure>

<figure><img src="image_8.png" /><figcaption>Fig. 7. HICUM simulation (lines) compared to measurements (symbols) of (a) the Gummel plot with $L_E$ and (b) temperature variation, (c) $f_T$ in function $I_C$ for three $L_E$ and (d) the output characteristics.</figcaption></figure>

<figure><img src="image_9.png" /><figcaption>Fig. 8. 0.15 × 5 µm² InP DHBT measured (symbols) and simulated (lines) S-parameters up to 500 GHz, in magnitude.</figcaption></figure>

<figure><img src="image_10.png" /><figcaption>Fig. 9. 0.15 × 5 µm² InP DHBT measured (symbols) and simulated (lines) S-parameters up to 500 GHz, in phase.</figcaption></figure>
be necessary for high frequency modelling of the future InP DHBT generations.

## B. RF Figure of Merits Extraction up to 500 GHz

The transistors under test were characterized up to 500 GHz in order to extract their cut-off frequencies, $f_T$ and $f_{MAX}$. Fig. 10 shows the current gain, $H_{21}$, and the Mason gain, $U$, computed from the S-parameter measurements and HICUM simulations at different bias points for an 0.15 × 5 µm² InP DHBT. The maximum gain was obtained for $V_{BE}$=0.9 V and $V_{CE}$=1 V. To obtain a better estimation of $f_T$ and $f_{MAX}$, it is highly desirable that the gain-bandwidth products are extracted from $H_{21}$ and $U$ by using the following expressions:

$$f_T = |H_{21}| \times \text{frequency} \quad (1)$$

$$f_{MAX} = \sqrt{U} \times \text{frequency} \quad (2)$$

The resulting plots are shown in Fig. 11, depicting that the HICUM model is capable of reproducing the frequency-dependence of the transistor’s high frequency gain quite precisely. This physics-based model and associated scaling rules further corroborate the reliability of the transistor measurements at very high frequencies.

From Fig. 11 (a), we observe an increasing trend of the measured $f_T$ with frequency, exhibiting an excellent frequency band continuity. This behaviour is very well captured by the model through a combined effect from the parasitic capacitance partitioning across the external base resistance and non-quasi-static effects along with a collector-substrate coupling. As shown in Fig. 11 (b), accurate high frequency measurement of $f_{MAX}$ is difficult to achieve since this quantity is very sensitive to any perturbation in the measurements. However,

<figure><img src="image_11.png" /><figcaption>Fig. 10. 0.15 × 5 µm² InP DHBT (a) $|H_{21}|$ and (b) $|U|$ from measurements (symbols) and simulation (line) up to 500 GHz.</figcaption></figure>

<figure><img src="image_12.png" /><figcaption>Fig. 11. 0.15 × 5 µm² InP DHBT (a) $f_T$ and (b) $f_{MAX}$ from measurements (symbols) and simulation (line) up to 500 GHz.</figcaption></figure>

the present results show weaker fluctuations than the ones obtained in [14]. In this context, the HICUM model, validated against DC and S-parameter measurements up to 500 GHz, offers a high degree of confidence for the extraction of the peak $f_{MAX}$=1 THz and a peak $f_T$=550 GHz, at 500 GHz and $V_{BE}$=0.9 V.

In order to reaffirm the scalability of the technology from the high-frequency measurements, other geometries were also characterized up to 500 GHz. Their corresponding $f_T$ and $f_{MAX}$ are shown in Fig. 12. The extracted peak $f_{MAX}$ is also about 1 THz for $L_E$=7.5 µm and $L_E$=10 µm at $V_{BE}$=0.9 V. In all cases, the scalable model again proved to be quite relevant as observed from the model precision in Fig. 12. This modelling framework can thus be further leveraged for performance prediction and design extrapolation of this THz transistor technology to its smallest dimensions, without additional process optimizations.

## IV. CONCLUSION

As a result of process and layout improvements, the characterization of InP DHBT THz transistors was successfully achieved up to 500 GHz, confirming the state-of-the-art figures of merit $f_T/f_{MAX}$=0.55/1 THz from both measurement and simulation for a 0.15 × 5 µm² DHBT. The reduction of parasitics, through design optimization of on-wafer TRL standards, was proven to be a key factor for accurate high frequency measurements, allowing us to use conventional calibration and de-embedding methods even at sub-millimeter-wave frequencies. In addition, EM and HICUM compact model simulations provided a strong physical validation of the on-wafer measurements. Transistor measurements were validated using the HICUM model for different bias conditions and various
<figure><img src="image_13.png" /><figcaption>Fig. 12. Measured (symbols) and simulated (lines) (a) $f_T$ and (b) $f_{MAX}$ (b) up to 500 GHz for three InP DHBT geometries.</figcaption></figure>

geometries, for the first time up to 500 GHz, demonstrating the scalability of this InP DHBT process. Further model improvements, such as base-collector junction modelling in the context of THz InP DHBTs, would follow in order to accompany technological evolution in upcoming generations, leading the way to THz circuit design explorations. These results also showcase the potential of InP bipolar technologies to address upcoming challenges of heterogeneous integrated THz circuits.

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