# Using SiC JBS diode as voltage clamping in SSCB application: performances and limitations

Dominique Tournier, Pierre Brosselard, Pascal Bevilacqua, Jean Francois de Palma

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Dominique Tournier, Pierre Brosselard, Pascal Bevilacqua, Jean Francois de Palma. Using SiC JBS diode as voltage clamping in SSCB application: performances and limitations. The 26th European Conference on Power Electronics and Applications, GDR SEEDS France & EPE Association, Mar 2025, Paris, France. 10.34746/epe2025-0169. hal-05108353

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# Using SiC JBS diode as voltage clamping in SSCB application: performances and limitations.

D. TOURNIER¹, P. BROSSELARD², P. BEVILACQUA², J.F. DE PALMA¹

(1) MERSEN France Saint Bonnet de Mure SAS, France
(dominique.tournier@mersen.com ; jean-francois.depalma@mersen.com)

(2) Univ Lyon, INSA Lyon, Univ. Claude Bernard Lyon 1
Ecole Centrale Lyon, CNRS, Ampere, Villeurbanne, France
(pierre.brosselard@insa-lyon.fr ; pascal.bevilacqua@insa-lyon.fr)

## Acknowledgements

The authors would like to thank the people who made this achievement possible, Juline Valette and Nicolas Thierry-Jebali of former CALY Technologies company and Clas-SiC WaferFab Ltd for their fruitful technical and scientific contributions.

## Keywords

«Silicon carbide», «Solid State Circuit Braker», «Avalanche», «Clamping».

## Abstract

The performances and limitation of SiC JBS diodes used as clamping devices for SSCB have been investigated trough simulation and experimental measurements. The simulations evaluations are based on CAD and electro-thermal circuit modelling of packaged devices. The simulations have been done on a wide blocking voltage range, from 80V to 1.7kV. An optimal trade-off in terms of layout and avalanche capability has been found. A failure criterion in terms of power density has been established, linked to device top metal layers melting (around 500°C) and measured on commercial devices. Avalanche to Nominal current Ratio varies between 6 up to 10 depending on the manufacturer. A LTspice electro-thermal model allows to predict the required SiC devices area to achieve specific performances. Finally, a demonstrator of 1.2kV-2x50A-SOT227 SiC JBS clamping diode is presented.

## Introduction

Solid-State Circuit Breakers (SSCBs) are power semiconductor-based protection apparatuses, with no moving parts for fault current interruption, renowned for their excellent operational and system level benefits [1,2,3]. First

and foremost, the response time of semiconductor devices is several orders of magnitude shorter than that of the electromechanical mechanisms typical of conventional circuit breakers. Second, unlike electromechanical circuit breakers, which rely on contact separation for current interruption, semiconductor devices can interrupt the flow of electrical charges without arcing. Moreover, thanks to the extremely quick current interruption capability, semiconductor-based circuit breakers can limit the let-through energy and arc hazard exposure in the event of a fault by multiple orders of magnitude. Furthermore, because of the absence of moving parts, power semiconductor devices can execute a much higher number of operations. This translates into a greatly increased lifetime for circuit breakers. Finally, because semiconductor devices have no moving parts, they operate without making any noise. On top of the benefits that are true for most power distribution applications, semiconductor-based circuit breakers offer several additional benefits that may be application-specific.

Numerous SSCB have been proposed in the literature, based on either Si-IGBT, IGCT, SiC-JFET and SiC-MOSFET as well as GaN [4,5,6,7]. Demonstrators are implementing conduction branch in parallel with a snubber and a dissipation energy branch, some of them investigating SiC diode as clamping device. Additionally, advance electronic circuitry is part of those SSCB, monitoring current, estimating or measuring temperature and computing I2t to operate the power devices within their SOA. Some developments are also reporting some advance tripping curve like mechanical circuit breaker.

Designing an SSCB requires to take into the operations constrains, being:

* the nominal operation conditions, with acceptable power losses, (conduction branch)
* the transient operating mode, inrush current (energy absorption branch), network impedance [8]

* the fault conditions (short-circuit, over-voltage induced by lightning ...)

* capability to segregate faults from normal operation (control)

* coordination [9] and selectivity [10] within the electrical network (control).

In application requiring a high level of reliability and operating in a high temperature environment, using passive devices such as MOV and capacitor are limited, putting aside classical RCD snubber and MOVs. Designing a high voltage clamping device based on Zener diode would require a high number of elementary diodes stacking. Indeed, SiC Zener diode have been demonstrated [11,12], with current capability as high as 400A [13], but with clamping voltage in the range of 20V. Improving avalanche capabilities of MPS and JBS diode is thus preferable and investigated in this work. *In this approach, the feasibility of a full SiC SSCB including clamping devices has been analysed, to challenge the potential use of SiC JBS/MPS diodes as clamping devices.*

## Scope of the study

The scope of this work is the evaluation of fully solid-state transient voltage suppressor devices to be used instead of more cumbersome traditional solutions. The design of a Silicon Carbide diode used for voltage clamping in any commutation cell requires to take into consideration the following input parameters:

* Clamping voltage value $V_{BR}$

* Dynamic resistance in avalanche mode

* Starting clamping current, $I_{AS}$

* DC BUS voltage $V_{DD}$

* Network impedance (L, R)

The network impedance is storing the fault energy to be dissipated the clamping diode. Both the stored energy and the network impedance are strongly dependent on the operation mode. In nominal operation conditions, the Impedance can be as low as 10 µH and reach several 10's mH in fault operation. In avalanche mode the clamping device will conduct the current and generate a huge amount of power (2). In this study, the network impedance as be set to L=500µH and R=100mOhm. Other parameters are kept variable to evaluate the feasibility boundaries of SiC-Clamping diode for SSCB, considering serial and

parallel association of elementary clamping device.

## Work methodology.

Power TVS are commonly made stacking diodes. To get an optimal "High Voltage, High Current, High Energy" clamping function, a global trade-off study must be done to select the most appropriate elementary die(s) to answer the following questions:

* What is the maximal energy that can be dissipated by a SiC diode operating in avalanche mode,

* Shall we consider serial and parallel stacking of devices?

* Which solution is more competitive in terms of performances/cost

The design work has been divided in the following sub-taks:

* Design: Finite element TCAD simulation using Sentaurus software from Synopsys to optimize a unidirectional diode structure able to have a controlled avalanche behavior. This has been done for 3 voltage ratings [80V, 1200V and 1700V], considering stack association of diodes at system level.

* Testing: Commercial devices avalanche performances analysis and characterization to benchmark available technologies from and main actors on the market).

* Circuit parametric modelling: Device electro-thermal modelling considering the packaging to carry-out a technical and economical assessment.

* Prototype design and manufacturing for SSCB demonstrator with scaling estimation depending on fault conditions and voltage class stacking configurations.

## TCAD design of SiC TVS devices.

The purpose of this section is to define what could be an optimal 4H-SiC TVS structure for:

* low voltage class (80V), addressing low voltage power supply protection,

* high voltage class (1200V and 1700V) dedicated to commutation cell protection.

For both voltage classes, several diodes topologies have been investigated:
* T1: Distributed PiN diodes (JBS of MPS) (Figure 1)

* T2: Distributed PiN diodes with Electric Field Enhancement Layer (EFEL) (Figure 2)

* T3: Classical Punch through diode (PTD) (Figure 3)

* T4: Punch through diode (PTD) (diode with Electric Field Enhancement Layer (Figure 4))

<figure><img src="image_2.png" /><figcaption>Figure 1. Cross section structure T1 : Distributed PiN Diode (either JBS or MPS technology).</figcaption></figure>

<figure><img src="image_3.png" /><figcaption>Figure 2. Cross section structure T2 : Distributed PiN diodes with Electric Field Enhancement Layer (EFEL).</figcaption></figure>

<figure><img src="image_4.png" /><figcaption>Figure 3. Cross section structure T3: Punch through diode (PTD).</figcaption></figure>

<figure><img src="image_5.png" /><figcaption>Figure 4. Cross section structure T4 : Punch through diode (PTD) with Electric Field Enhancement Layer (EFEL).</figcaption></figure>

Both JBS and MPS have distributed PiN diodes pockets in the active area region. MPS are designed to have better surge performances than JBS diodes in forward conduction mode [14] Indeed MPS diode have lower contact resistivity to P+pocket areas than JBS devices. For structure T1, the JBS/MPS p+pocket doping concentration, distance and 3D layout have been designed in a way that the electric field in the peripheral area of the devices is always kept lower than the one in the active area. This device topology (geometry, doping concentration, metal scheme) allows to have a controlled avalanche behavior in the active area and to avoid filamentation in the edge of the devices. This principle has already been demonstrated [15,16] as illustrated on *Figure 5*

<figure><img src="image_6.png" /><figcaption>Figure 5. Early breakdown failure pattern of a 20 A/1200 V diode with an insufficient junction termination design; b) Failure pattern of a robust junction termination of an 8 A/1200 A diode after dissipating 6.9 J/cm2 of energy; c) TCAD (Technology Computer Aided Design with Sentaurus Device) simulation results: breakdown voltage of cell field compared to breakdown voltage of p-JTE [15, 16].</figcaption></figure>
The dependence of the clamping voltage versus the P+-pocket spacing (L1) and epilayer doping concentration (Nepi) is presented on Figure 6. The breakdown voltage V<sub>BR</sub> is strongly depending on L1 for rather low doping concentration (Nepi < 1e17 cm<sup>-3</sup>) and L1<2.5um. For Nepi>2e17 cm<sup>-3</sup> the breakdown voltage sensibility to parameter L1 (P+ spacing) is reduced. The targeted V<sub>BR</sub>=80 V is obtained for Nepi a bit lower than 3e17 cm<sup>-3</sup>.

<figure><img src="image_7.png" /><figcaption>Figure 6. Clamping voltage V<sub>BR</sub> depending on epilayer doping and P+Pocket spacing parameter L1 for 80V class Type T1 JBS diode</figcaption></figure>

For a 80V JBS structure T1, having an optimal design and set of parameters, the avalanche occurs on the bottom edge of the p+ pocket (Figure 7) at the highest point of the electric field in the corner of the P+ implanted pocket, avoiding avalanche in the periphery of the device.

<figure><img src="image_8.png" /><figcaption>Figure 7. TCAD distribution of electric field for 80V class Type T1 JBS diode</figcaption></figure>

<figure><img src="image_9.png" /><figcaption>Figure 8. TCAD distribution of current density ignition (left) and electrostatic potential reduction (right) at pocket corner of P+ region for 80V class Type T1 JBS diode</figcaption></figure>

The current density value is higher in the p+-pocket corner (Figure 8-Left), induces however a hotpot temperature location. To overcome this drawback, structures T2 and following are preferred, to have more distributed current density in the whole active area. In the case of structures T3 and T4, both the electric field and the avalanche current are homogeneous everywhere in the structure (Figure 9) but requires a careful design of the peripheral protection.

<figure><img src="image_10.png" /><figcaption>Figure 9. TCAD distribution of electric field (left), current density (right) for 80V class Type T3 Punch Trough Diode with uniform current density distribution.</figcaption></figure>

To get a uniform and easily adjustable “in volume” avalanche, structure T2 is considered.

<figure><img src="image_11.png" /><figcaption>Figure 10. Clamping voltage V<sub>BR</sub> depending on epilayer doping and P+Pocket spacing parameter L1 for 80V class Type T2 JBS diode</figcaption></figure>

As illustrated on Figure 10, for $N_{NEFE}=2e17 cm^{-3}$, V<sub>BR</sub> dependence on parameters L1 and Nepi is minimized for L1>2um. Using a well designed drift layer (thick and low doped enough), the cell breakdown voltage V<sub>BR</sub> is much smaller than the epi one without edge termination (V<sub>BR-1D</sub>). Distributed PiN diodes with Electric Field Enhancement Layer (EFEL), permit a good control of the avalanche inside the active area, with lower clamping voltage variation than structure T1 and a simplest fabrication process than T3. Choosing T2 structure provide a good control of the clamping action inside the active area and a uniform power dissipation in a large volume area, key points to increase the maximal dissipation energy density value in J/cm<sup>3</sup>.
## TCAD dynamic electrothermal avalanche failure investigation

Electro thermal simulation have been done to evaluate the influence of SiC die dimension on the maximal temperature. Two topologies of structure T2 have been considered (S2 and S4). Differences between structure 2 and structure 4 are the implementation of the Avalanche Control Implanted Layer (doping concentration NEFE). For each topology, 2 die areas have been considered: 3.5x7 mm² and 4x8mm². Simulation have been done using a bi-exponential current waveform, varying both the maximal amplitude and duration (Figure 11).

<figure><img src="image_12.png" /><figcaption>Figure 11. Transient TCAD waveform (current) of SiC Diode in avalanche mode for 2 structures S2 and S4. Die size: [3.5 x 7 mm2 and 4 x 8 mm2]</figcaption></figure>

The simulated clamping response over time is presented on Figure 12 for a 100us half pulse duration. From simulation we can conclude that the structure 2 looks better than structure 4 as it leads to have a better heat distribution. For a 4x8 mm² active area the temperature variation is ΔT= 60K

<figure><img src="image_13.png" /><figcaption>Figure 12. Transient TCAD waveform (temperature) of SiC Diode in avalanche mode for 2 structures S2 and S4. Die size: [3.5 x 7 mm2 and 4 x 8 mm2]</figcaption></figure>

Structure 2 looks also better than Structure 4 because it allows a lower maximum temperature for a similar size (Figure 12) and a lower $V_{KA-max}$ for a similar size (Figure 13).

<figure><img src="image_14.png" /><figcaption>Figure 13. Transient TCAD waveform voltage, of SiC Diode in avalanche mode for 2 structures S2 and S4. Die size: [3.5 x 7 mm2 and 4 x 8 mm2]</figcaption></figure>

A summary of the impact of maximal temperature depending on die size is presented on Figure 14. Melting temperature of Aluminum (650°C) is setting a minimal acceptable die width of 6mm for the simulated fault of 100us bi-exponential surge current waveform. Having a shorter pulse duration allow to use a smaller die size.

<figure><img src="image_15.png" /><figcaption>Figure 14. Top: Dependence of maximal temperature versus die size. Bottom: Maximal dynamic clamping voltage (due to dynamic resistance of diode in avalanche mode) for 80V clamping devices.</figcaption></figure>

The main benefit of Structure 2 over Structure 4 is that the hot spot is located into SiC while the hotspot is located at the SiC / contact interface in classical JBS structures.

A similar design work has been done on 1.2kV and 1.7kV devices. For all voltage classes, the same limits in terms of power dissipation and energy density have been estimated by simulation. 1.2kV devices have been manufactured with optimized set of parameters for T1 and T2 configurations.
Experimental avalanche performances
evaluation of commercial SiC devices

To assess the feasibility of SiC clamping diodes
is it mandatory to confirm simulation trends by
experimental measurement on packaged devices.
Indeed, the thermal limitation of a SiC diode is
related to its topology, the manufacturing process
and the packaging. A weak point is the metal
stack and interconnection (melting temperature of
Aluminum pads and bonding).

The avalanche capabilities of selected
devices have been measured and estimated for
further comparison with TCAD finite elements
simulation analysis and electro-thermal
modelling. A benchmarking approach has been
defined to evaluate the avalanche limits of
existing devices and to confirm the TCAD
simulation results:

- Maximal avalanche current,

- Maximal avalanche energy density (have bare die dimensions)

The measurement of avalanche limits has been
done on various commercial SiC devices as well
as on structure T1 (Figure 1) and T2 (Figure 2).
The test bench schematic is presented on Figure
15. Typical Unclamped Inductive Switching
(UIS) circuit with high voltage BiMOS switch:

- 450µH / 30A air-core inductor

- Max voltage = 3kV

Avalanche current in DUT is measured by shunt
IV characterization in forward and reverse
conduction mode before each pulse. The charging
pulses duration has been increased following the
sequence: [0, 200, 500, 700, 750, 800]µs

For a given device reference (i.e. manufacturer),
several devices have been measured up to
destruction to extract the average avalanche
energy.

<figure><img src="image_16.png" /><figcaption>Figure 15. UIS test bench description (left) and schematic (right).</figcaption></figure>

The Figure 16 presents an example of avalanche
measurement results for a 10A, 1200V SiC Diode
(sample #100) of T2 structure. The failure occurs
at a current of 22A, with an avalanche voltage

V<sub>AV</sub>=1600 V. The measured avalanche duration
to failure is lower than 10µs: t<sub>AV-failure</sub>=7µs. The
failure corresponds to an avalanche energy
average E<sub>AV-failure</sub> < 180mJ, equivalent to an
avalanche energy density of E<sub>av</sub>=6.16 J/cm². The
corresponding failure energy density 30J/cm³ at
semiconductor level with thin wafer.

<figure><img src="image_17.png" /><figcaption>Figure 16. Failure avalanche measurement of 10A 1200V SiC Diode (KE12DJ10T20) in UIS conditions (L=500µH, VDC=30V). Vav=1600V. IAV-failure=22A, Eav-failure < 180mJ.</figcaption></figure>

For a given device topology, statistical avalanche
capabilities measurements have been done on 10
devices. The measured values of maximal current
(Imax), avalanche failure time (tfail) and
avalanche energy (Eav) are quite homogenous as
inferred from Figure 17.

<figure><img src="image_18.png" /><figcaption>Figure 17. Statistical distribution of t<sub>FAI</sub> and E<sub>AV</sub> for a set of 9 tested devices from one device manufacturer.</figcaption></figure>

The benchmarking of market available devices
allows to estimate the avalanche capabilities of
SiC diodes depending on a given technology.
<figure><img src="image_19.png" /><figcaption>Figure 18. Eav vs Inom depending on various devices.</figcaption></figure>

The measured or reported parameters presented on Figure 18. The maximal avalanche energy exhibits a linear dependence over the nominal current, for 650V, 1200V and 1700V voltage ranges. The normalization of the avalanche energy to the current ratings corresponds to a normalization to the surface of the devices (Figure 19). We can observe a trend for each manufacturer. For each of them, this E<sub>AV</sub>/I<sub>NOM</sub> ratio is almost constant and not depending on the current rating (i.e. the surface). One can also observe that this ratio varies from a factor 4 to 16 (Figure 20). This huge discrepancy is related to each manufacturer technology and associated avalanche design capabilities. The failure mechanisms correspond to and excessive top-metal temperature, leading to the Schottky barrier reduction and finally to the fusion while reaching metal melting temperature.

<figure><img src="image_20.png" /><figcaption>Figure 19. Maximal avalanche energy of SiC diode versus nominal current (measurement and estimation left). Ratio between avalanche energy and nominal current (right).</figcaption></figure>

This variation form manufacturer to manufacturer is summarized on Figure 20 illustrating the necessity to perform accurate measurement and modeling to select the most appropriate technology for voltage clamping implementation.

<figure><img src="image_21.png" /><figcaption>Figure 20. SiC Diode avalanche capabilities benchmarking for several devices manufacturer: maximal avalanche current depending on nominal current rating.</figcaption></figure>

The evaluated avalanche density energy is in between 4 J/cm<sup>2</sup> &lt; E<sub>AV-max</sub> &lt; 7J/cm<sup>2</sup> depending on:

- Device topology (planar, trench),

- Schottky metal (Ti, Ni, Mo),

- The die area (i.e. the nominal current)

## Circuit level avalanche performances modelling of SiC devices and trade-off study.

The thermal impact of the die size and packaging on the avalanche performances has been evaluated experimentally for various current ratings. Based on those measurements, an electro-thermal modelling work has been done using 2D-FEM software and LT-Spice circuit simulation tools and specifically tuned for CALY manufacturing technology.

<figure><img src="image_22.png" /><figcaption>Figure 21. Cross section of diode electro-thermal simulation. Structure description: [SiC Diode : defined using Vclamp, Rdyn, capacitance] ; TO 220 Package (for thermal impedance modelling) Variable die size and adjusted thermal impedance [~ 2mm2 to ~ 20mm2]. Fixed Tcase = 25°C</figcaption></figure>

A generic and parametric thermal impedance of diode packaged in a TO220-2L plastic model has been established using 2D Thermal modeling simulation tools. The avalanche analysis methodology consisted in defining a global workbench to evaluate the most affecting
parameters on device performances. For each of
those experiment key parameters have been
extracted:

* Maximal power (kW)

* Avalanche Energy (J)

* Avalanche time (us)

The *Figure 22*, is an illustration of the simulated clamping current and temperature phase for a die width of 2.2 mm, varying the avalanche current between 10A and 30A. The maximal estimated temperature is set to 555°C. The extracted failure time (tav=5us) is within the range of experimental measurement (*Figure 17*) and the reported literature for individual diodes.

<figure><img src="image_23.png" /><figcaption>Figure 22. LTSpice parametric simulation results for a die size=2.2mm, increasing avalanche peak current value from 10A up to 30A. Extracted maximal avalanche current: Iav-max< 25A; Maximal avalanche time to failure : tav = 5µs.</figcaption></figure>

The *Figure 23* is an illustration of the simulated clamping current and temperature phase for a die width of 4mm, The maximal estimated avalanche current increases to Iav-max=78A.

<figure><img src="image_24.png" /><figcaption>Figure 23. LTSpice parametric simulation results for a die size=4mm. tav = 11µs ; Imax = 78A</figcaption></figure>

Using this electro-thermal model, the avalanche
current depending on die width has been extracted
and reported on *Figure 24* for various failure
temperature values between 355°C and 755°C.

<figure><img src="image_25.png" /><figcaption>Figure 24. Simulated maximal avalanche current versus die size depending on maximal temperature criteria.</figcaption></figure>

High current SiC Clamping Power module demonstrator.

Based on both TCAD and circuit modeling, the performances of a 100A-1.2kV SiC clamping module has been evaluated. Devices should be able to sustain at least the nominal current in avalanche mode with limited temperature increase Tjunction < 250°C. A module solution has thus been considered to manufacture a prototype of SiC clamping diode using tow set of 5 diodes (1200 V/10 A) in parallel. The design module view for 1.2 kV 100 A avalanche capability is illustrated on *Figure 25*.

<figure><img src="image_26.png" /><figcaption>Figure 25. 1200V, 100A SiC JBS diode packaged in a SOT227 module and XRAY investigation of die assembly quality (bottom right).</figcaption></figure>

Avalanche performances have been measured
using experimental test bench presented on
Figure 26.
<figure><img src="image_27.png" /><figcaption>Figure 26. UIS test bench view with SOT-227 1.2kV 100A SiC diode module and HV commutation cell.</figcaption></figure>

Experimental results are confirming the satisfying paralleling operation of 5 diodes in avalanche mode for increasing avalanche duration from 2us to 10us (Figure 27).

<figure><img src="image_28.png" /><figcaption>Figure 27. Non-destructive UIS measurements on one leg SOT-227-1.2kV-50A. Vclamp=1.6kV, avalanche current: 8A < I<sub>AV</sub> < 45A.</figcaption></figure>

The module has a clamping voltage of 1.7kV and was tested dissipating 416mJ during 8.7us for an initial current of 53A (for one leg) without failure (Figure 26). The dynamic avalanche differential resistance is $R_{av-diff}$= 0.4 Ohm.

<figure><img src="image_29.png" /><figcaption>Figure 28. Dynamic I(V) characteristics extracted for UIS measurement pointing out thermal effect suitable for devices paralleling (linear regions 1 and 2) and $R_{av-diff}$=0.4 Ohm.</figcaption></figure>

## Conclusion

The main objective of the work was to setup and validate a design workbench to evaluate the performances and the limitation of a full SiC Voltage clamping solution. For a given technology, electro-thermal modeling is in good agreement with experimental measurements. However, benchmarking commercial devices highlights the variation of avalanche capabilities with respect to manufacturer. Indeed, the avalanche capabilities of SiC diodes are strongly related to:

- Die size and topology (planar, trench)

- Manufacturing technology (Schottky metal, contact metal, passivation ...)

- Packaging and 3D topology of the device (backside and frontside soldering).

- Fault energy and duration.

A full SiC JBS diode module can sustain avalanche clamping mode in the range of 100A at 1.7 kV. The energy density dissipate is in the range of 30 J/cm³. The test bench limitation didn't allow higher current level, indeed Si-BIMOS used for the test is rated 4.5 kV 80 A peak.

The benefit at application level of SiC JBS as clamping device is the low leakage current and reduced drift in time in of state in a comparison to an MOV. However, it is not as cost effective as a classical MOV solution able to dissipate high energy levels up to 120 J/cm³. Using such a modeling technic will ease both technical and economical assessment for various configuration, considering application specifications (network impedance), packaging and cooling and to implement such devices in SSCB demonstrators.

Perspective of this work is to conduct UIS avalanche measurement up to destruction to validate both devices modeling and temperature failure criteria, as well as economical tradeoff study of die paralleling. In addition, packaging, voltage and current sharing are technical challenges to investigate. The reliability in case of repetitive avalanche surges depending on the fabrication technology must also be evaluate, considering refractory Schottky metal compounds benefits. A more complex electro-thermal model must be calibrated to consider the packaging dissipation aspect for double side cooling to further improve performances.
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