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# Operando observation of gate defects in quantum dot-based field effect transistors

Mariarosa Cavallo, Dario Mastrippolito, Erwan Bossavit, Clement Gureghian, Albin Colle, Tommaso Gemo, Adrien Khalili, Huichen Zhang, Yoann Prado, Erwan Dandeu, et al.

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Mariarosa Cavallo, Dario Mastrippolito, Erwan Bossavit, Clement Gureghian, Albin Colle, et al. Operating observation of gate defects in quantum dot-based field effect transistors. Nanoscale, In press, 10.1039/D5NR00767D. [hal-05074080](https://hal.science/hal-05074080v1)

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https://hal.science/hal-05074080v1

Submitted on 19 May 2025

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# Operando Observation of Defect and Breakdown of a Quantum Dot based Field Effect Transistor

Mariarosa Cavallo¹, Dario Mastrippolito¹, Erwan Bossavit¹,², Clement Gureghian¹, Albin Colle¹, Tommaso Gemo¹, Adrien Khalili¹, Huichen Zhang¹, Yoann Prado¹, Erwan Dandeu¹, Sandrine Ithurria³, Pavel Dudin², José Avila², Debora Pierucci¹, Emmanuel Lhuillier¹*

¹ Sorbonne Université, CNRS, Institut des NanoSciences de Paris, 4 place Jussieu, 75005 Paris, France.

² Synchrotron SOLEIL, L'Orme des Merisiers, Départementale 128, 91190 Saint-Aubin, France.

³ Laboratoire de Physique et d'Etude des Matériaux, ESPCI, PSL Research University, Sorbonne Université, CNRS, 10 rue Vauquelin, 75005 Paris, France.

**Abstract:** As colloidal nanocrystals mature; they are increasingly integrated into more advanced electronic and optoelectronic devices. The field-effect transistor (FET) has become a central building block. While it is widely used as a phototransistor to combine both light absorption and gate-induced current modulation, its main usage remains as a tool to extract material parameters. The electrical output from FETs serves as the main measurement to probe carrier density and mobility in nanocrystal films. However, such an approach suffers from two main flaws: it relies on modeling to connect material properties to the electrical output, and second, it can be affected by the presence of defects. Here, we use scanning photoemission microscopy to assess the energy profile in such nanocrystal-based FETs. The method is used to quantify the impact of a local gate defect, which appears to be quite dramatic since its impact is stronger and has longer-range effects than the conventional gate operation. We also demonstrate that the method is effective to determine the process at the origin of electrical breakdown. Overall, the method appears well suited to bridge the gap between the material scale and the obtained electrical output and to quantify the impact of potential deviations from ideal behavior.

**Keywords:** Nanocrystals, field effect transistor, operando measurements, defect, nanobeam X-ray photoemission.

*To whom correspondence should be sent: el@insp.upmc.fr
Colloidal quantum dots (CQDs) are now an established material for optoelectronics,¹ addressing applications such as color-pure light sources for display,²,³ single-photon sources, and cost-effective infrared imagers.⁴⁻⁶ The design of these advanced components relies on elementary building blocks such as the *p*-*n* junction and the field effect transistor (FET).⁷

To understand the importance of FETs for CQD optoelectronics,⁸,⁹ it is worth noting that in a CQD array, the electronic transport occurs through hopping conduction, which leads to moderate mobility values. As a result, the Hall effect, the method most commonly used to unveil the nature of the majority carriers, their amount (n) and their mobility (μ) in bulk materials, becomes poorly suited for CQD arrays due to the vanishingly small Hall bias.¹⁰ This is the reason why the FET has emerged as the main tool to estimate these quantities in CQD arrays. A FET is a three-terminal device. Two electrodes, called drain and source, are used to apply a bias that reduces the potential of one electrode with respect to the other.⁸,⁹ This speeds-up holes and electrons in the channel, which try to minimize their potential. In a drift model, they acquire a speed (v) that relates to the applied electric field (F) through v=μ·F. In its most conventional geometry, the third electrode, called the gate, is separated from the semiconductor channel by a dielectric layer. This layer forms a capacitor, on the surface of which charges are generated upon gate bias application. The drain-source electrodes then inject charges into the channel to screen these gate surface charges, inducing a change in the carrier density, which is reflected as band bending in the energy profile. A second common application of FETs is as phototransistors. In such devices, the optical features of the channel are combined with the tunable carrier density provided by the gate. Compared to a two-terminal device, the addition of a gate enables operation under a gate bias that minimizes dark conduction, thus increasing the signal-to-noise ratio.¹¹ By operating the transistor with a large drain-source bias or using multiple gates,¹²,¹³ a *p*-*n* junction can be formed across the channel, therefore leading to planar photodiodes,¹³ and LEDs.¹⁴,¹⁵

Research on CQD-based FETs initially focused on the material level, and more specifically on how surface chemistry can be tuned to boost the carrier mobility.¹⁰,¹⁶⁻¹⁸ The operation of the device is usually probed through its electrical output. To date, CQD-based FETs primarily serve as probes for material characterization, with limited efforts toward advancing their integration into more complex devices, such as logic gates.¹⁹,²⁰ This bottleneck is largely due to the limited reliability of FETs, which suffer from bias stress effects (i.e., changes of output under operation),²¹,²² and potentially irreversible effects, such as electrical breakdowns. The quest for more reliable devices needs to be conducted in parallel with the development of relevant tools giving insight into the material *in situ* and *operando*. However, there is only a very limited effort in this direction, especially in the context of CQD-based devices. The use of optical methods can be quite challenging, as the gate/channel components are often non-transparent, and they generally offer limited spatial resolution.²³ To achieve higher resolution, electrical modes of near-field spectroscopy, such as Kelvin probe force microscopy (KPFM), have been used to image changes in the energy landscape upon gate bias application.²⁴,²⁵ While KPFM offers high spatial resolution, down to a few tens of nanometers, it is highly sensitive to moisture and actual environmental conditions.

Photoemission spectroscopy is already a well-established method when it comes to determining the band alignment of semiconductors in absolute energy scale. In the context of CQD-based optoelectronics, X-ray Photoemission spectroscopy (XPS) is typically used to determine the valence band edge and infer from the optical band gap the conduction band edge, allowing for the rational selection of suitable surrounding electrodes and charge transport layers. Conventional XPS, however, has limited spatial resolution, with laboratory instruments typically offering spot sizes between 100 µm and 1 mm, making it unsuited to provide local information. On the other hand, more advanced XPS methods such as XPEEM (X-ray photoemission electron microscopy),²⁶⁻²⁸ or SPEM (scanning photoemission microscopy) offer improved spatial resolution. Recently, Cavallo *et al.*
reported the use of SPEM,²⁹ as a relevant tool to probe, under operation, the energy landscape of nanocrystal-based optoelectronic devices.³⁰⁻³³ The method offers a sub-µm spatial resolution,³⁴ while being able to provide information on both the scalar (energy) and vectorial (electric field) distribution. Here, we apply this method to track and monitor the impact of a gate defect on the energy landscape of a CQD-based FET. The effect of defects on the FET operation is clearly underestimated until breakdown occurs. As we demonstrate in this paper, small damages, such as those caused by the inadvertent use of metallic tweezers on a thin dielectric, may not lead to complete breakdown of the device but can dramatically alter its operation. Here, SPEM is employed to provide a full description of the consequences of a gate leak on the scalar energy profile and vectorial field distribution. In the last part of the paper, we examine the electrical breakdown effect and how it impacts the device structure and operation. The method appears particularly relevant to probe in situ the device energy landscape and unveil possible structural flaws related to the fabrication process.

To build the FET channel, we first grow HgTe CQDs,³⁵,³⁶ a material relevant for fundamental studies of transport,³⁷ light emission,³⁸⁻⁴⁰ and detection,⁵,⁶ making it a highly relevant platform for infrared optoelectronics. The CQDs are synthesized following the procedure developed by Keuleyan et al.,³⁹ in which mercury chloride reacts with telluride complexed to trioctylphosphine in the presence of long-chain amines. This reaction leads to the formation of faceted nanocrystals (Figure 1a) with a characteristic size at around 10 nm, according to high-resolution transmission electron microscopy (Figure 1b). Reaction conditions are tuned to obtain a band edge at around 3200 cm⁻¹ (3.12 µm or 400 meV), see Figure 1c.

<figure><img src="image_3.png" /><figcaption>b</figcaption></figure>

<figure><img src="image_4.png" /><figcaption>c</figcaption></figure>

<figure><img src="image_5.png" /><figcaption>d</figcaption></figure>

<figure><img src="image_6.png" /><figcaption>e</figcaption></figure>

<figure><img src="image_7.png" /><figcaption>f</figcaption></figure>

<figure><img src="image_8.png" /></figure>

**Figure 1** HgTe CQD-based field-effect transistor. a. Transmission electron microscopy image of HgTe CQDs under study. b. High resolution TEM image of the same CQDs. c. Absorption spectrum
of the HgTe CQDs, after their liquid phase ligand exchange. The electronic transition overlaps with the narrow peak at 2900 cm⁻¹ coming from C-H bond. d. Optical microscopy image of the FET with drain, source and gate electrodes. e. Transfer curve (i.e., drain and gate current as a function of gate-source bias under constant drain-source bias, here 100 mV) for the FET whose channel is made of HgTe CQDs. f. Current as a function of temperature under constant drain-source bias (100 mV) and its Arrhenius fit leading to an activation energy of 130 meV.

Using conventional lithography procedures, we then design a field-effect transistor (see procedure in Figure S1). A bottom gold electrode is separated from the channel by a 40 nm thick alumina layer. Drain and source electrodes are patterned on top of the gate dielectric (see **Figure 1d**) and the whole system is then coated with the CQDs. The native capping ligands are replaced in solution using a hybrid surface chemistry combining ions (HgCl₂) and short thiols (mercaptoethanol), as proposed previously.³⁷,⁴¹ The I-V curve (Figure S2) is linear at room temperature, indicating the formation of ohmic contacts, thanks to the narrow band gap nature of the material which minimizes any possible offset between the band energy and the electrodes' work function. Upon gate bias application, a clear modulation of the drain-source current is observed, see **Figure 1e**, with a signal largely above the leakage current. The transfer curve (**Figure 1e**) displays conduction under both negative bias (i.e., hole injection) and positive gate bias (i.e., electron injection), which is the expected behavior for an ambipolar material. Near room temperature (250 K), the gate-induced modulation of the current is limited to about one order of magnitude. This results from the large thermal activation of carriers in this material, which limits the reduction in the off-current (i.e., the current at the minimum of conduction). Higher current modulation can be obtained by further reducing the operating temperature,⁴² as pointed out by the I-T curve in **Figure 1f**.

To probe the impact of a defective gate, we add a controlled etching step of the dielectric layer prior to CQDs deposition. Using e-beam lithography, we pattern the resist to selectively etch a square area with 3 µm edges on the gate dielectric. Such defect mimics, in a controlled way, what can be induced, for example, by a metallic tweezer scratching the surface of a thin dielectric. The defect size is chosen to be small compared to the channel width (20 µm), ensuring it remains a localized defect, yet large enough compared to the resolution of our photoemission imaging setup (approximately 700 nm) to clearly localize the gate hole, see the schematic of the device in **Figure 2b** and S1.

To map the energy landscape of the device *in operando*, we use a focused soft X-ray setup.⁴³ The high flux from a synchrotron beam is focused using a Fresnel zone plate. The latter is optimized to operate at 95 eV, hence maximizing the available flux while offering the smallest spot size at the sample scale (700 nm). The sample is then mounted on a stage allowing for the application of bias. The sample is scanned under the beam, and for each position, a photoemission spectrum is collected, as depicted in **Figure 2b**. HgTe presents the benefit of having two low-energy core levels that can be excited with the soft X-rays: Hg 5d with a binding energy of 8 eV (Hg 5d₅/₂) and Te 4d with a binding energy of 40 eV (Te 4d₅/₂),³⁴ see **Figure 2a** and S3.

Energy conservation is used to retrieve the binding energy (BE) from the kinetic energy (KE) measured by the analyzer through the equation

$$hv=BE(x,y,V_{DS},V_{GS})+KE(x,y,V_{DS},V_{GS})+WFA \quad (1)$$

where hv is the photon energy and WFA the analyzer work function, determined by measuring a metal Fermi edge and setting its binding energy to zero
To unveil the energy landscape, we then fit the acquired spectrum from each point with a Gaussian line shape and extract the peak energy of the tracked core level, see Figure S4. The obtained map actually mimics the expected shift of the valence band, if we assume a rigid shift of the whole XPS spectrum upon bias application. Even though the high conductivity of the sample (see **Figure 1e**) already limits photo-charging effects, we further subtract the map obtained with all electrodes grounded from those taken under bias to obtain the energy shift map.

$$ \text{Energy shift } (x,y,V_{DS},V_{GS}) = \text{BE}(x,y,V_{DS},V_{GS}) - \text{BE}(x,y,V_{DS}=0,V_{GS}=0) \quad (2) $$

This procedure eliminates the possible residual photo-charging effects in the sample. See Figure S4 for a complete description of the data processing. It is worth pointing out that, until breakdown, the spectra relative to a core level are mostly shifted (i.e., neither broadening nor new components are observed) by bias application, as illustrated in Figure S5.

A typical map of the channel area around the defect is given in **Figure 2c**, obtained here under a -1 V drain-source bias and a -3 V gate bias. The left and right sides of the map show homogeneous potentials, which is the expected behavior for the material atop the gold electrodes, which set the potential. The potentials at the two electrodes are shifted by 1 eV, in agreement with the -1 V bias applied across the channel. Between the two electrodes, we see a gradient of potential, with the profile (black line in **Figure 2e**) showing a continuous drop of potential along the channel, without any accumulation of potential drop at the electrode interface (i.e., no Schottky barrier). This observation is consistent with the ohmic IV curve observed from transport measurements (Figure S2). The defect from the gate is also clearly visible on this map, see the blue feature at the bottom part of the map.

To quantify the impact of such defective gate, we have tracked the potential along the channel for various gate biases, along a profile that overlaps with the gate hole (Figure 2d, at y = 0 µm on Figure 2c) and along one away from the hole (Figure 2e, at y = 10 µm on Figure 2c). Away from the defect (Figure 2e), we observe a gate-induced shift towards lower binding energy under negative gate bias, which translates to a reduction of the energy difference between the valence band edge and the Fermi level, corresponding to a reinforced p-type behavior. Conversely, a positive gate bias leads to the opposite behavior. One can quantize the gate lever arm (the ability of the gate to shift the energy profile) by plotting the induced energy shift as a function of applied gate bias (Figure 2f): a value of 0.25 eV·V⁻¹ is obtained around the center of the channel.
<figure><img src="image_9.png" /></figure>

**Figure 2** Impact of defect on FET energy landscape. a. Survey spectrum focused on the low binding energy region of the spectrum for an HgTe CQD film, acquired with 95 eV photon energy, highlighting the presence of Hg 5d and Te 4d states (see also Figure S3). b. Schematic of the soft X-ray photoemission setup. The synchrotron beam is focused through a Fresnel zone plate (ZP) and an Order Selection Aperture (OSA), reaching the sample with a 700 nm spot. For each position in the x-y plane, a photoemission spectrum is acquired by analyzing the kinetic energy of the emitted electrons using an electron energy analyzer. c. Hg 5d<sub>5/2</sub> binding energy map of the FET channel near the hole. Dashed lines are used to indicate the electrodes localization. The localization of the hole is marked with a dashed square d. Hg 5d<sub>5/2</sub> binding energy profile across the channel along a line intersecting the hole (at y = 0 µm) for various applied gate biases, under a -1 V drain-source bias. e. Hg 5d<sub>5/2</sub> binding energy profile across the channel along a line away from the hole (at y = 10 µm) for various applied gate biases, under a -1 V drain-source bias. f. Energy shift value at x = 0 µm from the profile in part d (intersecting the hole, blue line) and e (away from the hole, black line) as a function of the applied gate bias.

Over the gate defect, the energy profile is deeply modified, as shown in **Figure 2d**. The energy profile modulation is more intense and corresponds to a 1 eV·V<sup>-1</sup> slope, as expected for a non-capacitive coupling (see **Figure 2f**). To further understand how the defect disturbs the FET operation, we also examine the electric field distribution. Thanks to the high spatial resolution of the method, the electric field can be obtained from **F** = -**∇**V, where V is the electric potential. Since we assume the shifts in binding energy relative to the grounded configuration are solely due to the application of a bias, this directly relates to the experimental data through **F** = -**∇**ΔBE = -(∂ΔBE/∂x) **x** + (∂ΔBE/∂y) **y), where ΔBE is the measured binding energy shift. In **Figure 3**, we overlap the binding energy shift map with the electric field map, quantified by the direction and length of local arrows. These maps have been depicted for two cases. In **Figure 3a**, a drain-source potential (-1 V) is applied while the gate is floating. In this case, the field is weak on both the left side and the right side of the image, corresponding to the area of the electrodes over which the potential is set
by the underlying metal. It is worth noting that the presence of the defect does not prevent bias application, as evidenced by the 1 eV difference in potential between electrodes. In the channel, the electric field is mostly homogeneous and directed toward the decreasing potential. In **Figure 3b**, the potential of the gate is now set ($V_{GS}=-3$ V). The energy map is dominated by the dielectric defect and the electric field lines form a point charge-like distribution around the defect, with arrows directed radially toward the center of the hole.

<figure><img src="image_10.png" /><figcaption>**Figure 3 Mapping the current pathway.** Energy shift map and vectorial distribution of the electric field, quantified through the direction and size of the arrows, for floating gate (a) and $V_{GS}=-3$ V (b), while a -1 V drain-source bias is applied. Dashed lines are used to indicate the electrodes localization.</figcaption></figure>

Aside from the intensity of the modulation, the defect impacts spatially the whole channel (i.e., at a distance ≈10 times larger than the defect size). In other words, the gate defect generates a massive and long-distance modulation of the FET energy landscape. The long-range impact is particularly problematic for the operation of the FET since it makes the whole energy profile dominated by a tiny defect while the normal operation capacitive coupling of the rest of the gate only appears as a marginal modulation. This shows that small degradations of the gate (few % of the channel area) in the channel area completely prevent the normal operation of the FET, though the effect is mostly hidden from electrical output.
<figure><img src="image_11.png" /><figcaption>**Figure 4 Breakdown of a FET.** a. (resp. b.) Optical microscopy image of the channel with two defects before (resp. after) the application of 40 V gate bias. c. Zoom on the area corresponding to the dashed red rectangle from part b. d. X-ray photoemission imaging relative to the Te4d<sub>5/2</sub> state around the same area as part c.; measure is conducted after the high gate bias pulses, with V<sub>DS</sub>=-1 V and V<sub>GS</sub>=+6 V. e. Energy profile of the Te 4d doublet over the defect (bottom yellow dashed line from part c and d at y=0 µm) from the map shown in part d. f. Energy profile of the Te 4d doublet over the hole defect (top yellow dashed line from part c and d at y=10 µm) from the map shown in part d.</figcaption></figure>

Though highly problematic, the local defect still enables the driving of the FET (i.e., application of bias) in a reversible manner and the defect impact can be minimized by keeping the gate floating at the cost of losing the carrier density tunability. In the last part of the paper, we push further the degradation of the FET and operate the gate to induce irreversible damages. To reach such a breakdown, we apply an electric field of the order of 1 V·nm<sup>-1</sup> over the dielectric. Various degradation mechanisms have been observed depending on the channel thickness. The FET geometrical factors are also determinants in the actual breakdown mechanism. For the most resistive channel (see Figure S7 and S8c), corresponding to a thinner film coating (30 nm), the material within the channel is removed after the large gate bias application. It certainly corresponds to an evaporation of the film through the Joule effect. This process is difficult to investigate by photoemission imaging since there is no longer material to track the potential. This is the reason why, we have also prepared a sample with a slightly thicker channel (≈100 nm), and therefore a reduced resistance (see Figure 4). Figure 4a and b provide optical images of the device respectively before and after the large gate bias application. In this case, the material within the channel is mostly preserved enabling the tracking of the energy potential. Conversely, the interface between the drain-source electrode and the gate electrode presents a modified aspect. Energy dispersive X-ray spectroscopy (EDX, figure S5) mapping shows the disappearance of the Hg, Te and Al in this area, while one can notice an increased presence of silicon, which suggests that the substrate is now emerging from this area. We then analyze the FET operation in the channel after the high bias pulse, see Figure 4c and 4d and S8b. Though the energy profile is not exactly constant, the potential between the drain-source electrodes is no longer shifted by the amount of bias applied across the channel (-1 V). The potential is instead completely affected by the bias applied over the gate (+6 V), both for a line intersecting
the hole (Figure 4e) and for a line far away from the hole (Figure 4f). Together with EDX mapping, these observations suggest that all electrodes are now shorted via the gate electrode.

Our study suggests a few strategies to limit defect formation and breakdown generation. First, defects within the thin dielectric are very easy to form through scratching. Therefore, FET handling should be conducted with appropriate tweezers, which must be kept far away from the active area. Secondly, the region where drain source electrodes overlap with the gate electrode clearly appears as one of the most fragile and this area should be as small as possible. However, reducing the gate area to only a portion of the channel will lead to uneven doping.34 Thus, the gate electrode should just match the channel area. Additionally, it is probably critical to avoid large height discontinuity in this region, as they are more likely to generate pinholes in the dielectric. To address this, we recommend smooth edges for the bottom gate fabrication (e.g., using rotation during metal deposition) and conformal methods (such as ALD) for the dielectric deposition.

To conclude, we have demonstrated that XPS imaging appears highly suited to unveil the energy landscape of nanocrystal-based devices. Here, we specifically used the high resolution of the method as a way to unveil how a defective structure can impact the potential landscape. In particular, we bring evidence that even a very localized defect in the gate dielectric can impact the whole device operability. The defective gate induces a stronger and longer-distance (>10 µm) modulation of the channel profile than the nominal effect expected from the capacitive gate. This study highlights a critical weakness of FET analysis only based on electrical measurements, since local defects of the gate maintain device operability, though clearly not operating in its nominal manner. Additionally, XPS imaging appears suited to unveil how operations beyond breakdown voltage contribute to irreversible changes in the device operation. This work stresses the importance of always combining electrical measurements with careful structural and local analysis in order to accurately assess the electrical operation of such devices. The generality of XPS imaging makes it particularly effective for directly identifying phenomena that might otherwise only be intuited from electrical measurements (such as ion migration and presence of redox process...).

## DATA AVAILABILITY

The data that support the findings of this study are available from the corresponding author upon request.

## ACKNOWLEDGMENTS

We thank Stephane Lorczy for his help in sample preparation. The project is supported by ERC grant AQDtive (grant n°101086358) and from French National Research Agency (ANR) through the grants Bright (ANR-21-CE24-0012-02), MixDferro (ANR-21-CE09-0029), Quicktera (ANR-22-CE09-0018), Operatwist (ANR-22-CE09-0037-01), E-map (ANR-23-CE50), DIRAC (ANR-24-ASM1-0001), camIR (ANR-24-CE42-2757), Piquant (ANR-24-CE09-0786) and as part of the "Investissements d'Avenir" program (Labex NanoSaclay, reference: ANR-10-LABX-0035). We acknowledge the use of clean-room facilities from the "Centrale de Proximité Paris-Centre" and support from Renatech+ for micro and nanofabrication. This project has also received financial support from the CNRS through the MITI interdisciplinary programs (project WITHIN) and Region Ile de France through Sesame project INSIDE.
## COMPETING INTEREST

The authors declare no competing interests.

## Supporting Information

Supporting Information includes (i) procedure for the fabrication of the FET, (ii) XPS spectra from Hg 5d and Te 4d state, (iii) procedure to process the XPS imaging map and (iv) structural characterization of FET after exposure to gate breakdown bias.

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