# Digital NGD Design for FPGA-based Application

Rivo Randriatsiferana, Ruben Salvador, Ollivier Tamarin

► To cite this version:

Rivo Randriatsiferana, Ruben Salvador, Ollivier Tamarin. Digital NGD Design for FPGA-based Application. INSCIT 2025 - 9th International Symposium on Instrumentation Systems, Circuits and Transducers, Aug 2025, Manaus, Brazil. pp.1-5, 10.1109/INSCIT66472.2025.11181019 . ird-05448291

HAL Id: ird-05448291

https://ird.hal.science/ird-05448291v1

Submitted on 8 Jan 2026

**HAL** is a multi-disciplinary open access
archive for the deposit and dissemination of sci-
entific research documents, whether they are pub-
lished or not. The documents may come from
teaching and research institutions in France or
abroad, or from public or private research centers.

L'archive ouverte pluridisciplinaire HAL, est
destinée au dépôt et à la diffusion de documents
scientifiques de niveau recherche, publiés ou non,
émanant des établissements d'enseignement et de
recherche français ou étrangers, des laboratoires
publics ou privés.

<figure><img src="image_1.png" /></figure>

Distributed under a Creative Commons CC BY 4.0 - Attribution - International License
# Digital NGD Design for FPGA-based Application

1st Rivo Randriatsiferana

Espace Dev

IRD, Univ Guyane, Univ Montpellier

Montpellier, France

rivo.randriatsiferana@ird.fr

2nd Ruben Salvador

CentraleSupélec

Inria, CNRS, IRISA

Rennes, France

ruben.salvador@inria.fr

3th Ollivier Tamarin

Espace Dev

IRD, Univ Guyane, Cayenne

Guyane Française, France

ollivier.tamarin@univ-guyane.fr

**Abstract**—Negative Group Delay (NGD) remains a little-known concept in embedded digital signal processing, and most electronic designers are unfamiliar with its design and analysis. This paper presents a clear, step-by-step theoretical framework and a practical methodology for implementing baseband NGD using a low-order finite impulse response (FIR) filter. All FIR-based NGD parameters and characteristics can be defined under specific conditions based solely on the desired NGD value and the sampling frequency. Our synthesis results confirm that the realized time-advance increases with normalized frequency. We validate the approach through simulation and then demonstrate a proof-of-concept FPGA implementation. In transient experiments using a 3 kHz Gaussian pulse, the NGD circuit produces an advance of approximately 13 µs relative to the input signal and the NGD execution time is about 2µs.

**Index Terms**—Negative Group Delay, Time-advance, Digital FIR NGD, NGD implementation, NGD FPGA.

## I. INTRODUCTION

Low latency is a critical requirement in embedded systems, particularly in applications demanding real-time signal processing, such as industrial control, biomedical monitoring, and communication systems [1]. Latency is commonly characterized by group delay (GD), which quantifies the time delay of the amplitude envelopes of various spectral components of a signal as they pass through a system. To address GD-related challenges, various compensation techniques have been developed. For instance, GD compensation technologies have been explored to enhance signal integrity and system performance [2], [3].

In this context, the concept Negative Group Delay (NGD) has emerged as a promising approach. NGD refers to a phenomenon where the peak of a system's output signal precedes the peak of its input signal in the time domain, without violating causality principles [4], [5]. Although counterintuitive, NGD has potential applications in signal prediction, delay compensation, and synchronization improvement in communication systems [6]–[8].

Previous studies have demonstrated the feasibility of implementing NGD filters in both analog and digital domains. For example, NGD filters have been utilized for real-time prediction of complex band-limited signals, including chaotic systems and biological signals like photoplethysmograms [9], [10]. Moreover, NGD filter implementations on platforms such as STM32 microcontrollers have highlighted their potential for embedded applications requiring failure detection or signal

prediction [11], [12]. Recently, an effort has been made to implement NGD on FPGA platforms, exploring the applicability and effectiveness of second-order FIR-based NGD technology to extend its application scope; however, although execution time is not reported [13].

Despite these advancements, the design and analysis of digital NGD systems remain relatively unfamiliar to many electronic designers. This work aims to bridge this gap by presenting a clear theoretical framework and practical design for implementing a baseband NGD function using a low-order Finite Impulse Response (FIR) filter. We demonstrate that FIR-based NGD parameters can be defined under specific conditions, based solely on the desired NGD value and the sampling frequency. Our synthesis results confirm that the realized time-advance increases with normalized frequency. We validate the approach through simulation and subsequently demonstrate a proof-of-concept FPGA implementation. In transient experiments using a 3 kHz trapezoidal and Gaussian input, the NGD circuit produces an advance of approximately 15 µs relative to the input signal, with an NGD execution time of about 2 µs.

This paper is organized into three main sections. Section II describes the theoretical approach of the digital baseband FIR-based NGD with simulation results. Section III presents the FPGA implementation of the FIR-based NGD. Section IV provides experimental results and discussion. Finally, Section V concludes the paper.

## II. DIGITAL BASEBAND NGD THEORETICAL DESIGN APPROACH

The general transfer function $G[z]$ of FIR filter can be expressed as follows, in the frequency domain using the Z-transform:

$$G[z] = b_0 + b_1 z^{-1}. \qquad (1)$$

where, $b_0$ and $b_1$ are FIR filter coefficients.

We can obtain the harmonic responses of the FIR filter system from its complex frequency response, denoted $G(e^{j\omega})$, where $j$ is a the imaginary unit and $\omega$ is the angular frequency. Let $\varphi(\omega)$ represent the filter's phase response. The group delay (GD) is defined as the negative first derivative of the phase response $\varphi(\omega)$. In contrast, the less familiar NGD function measures the average group-time advance as a function of
frequency. It is defined as the opposite of the GD and is expressed as follows:

$$T(\omega) = \left. \frac{\partial \varphi(\omega)}{\partial \omega} \right|_{\omega=2\pi f/f_s} \qquad (2)$$

where, $f_s$ is the sampling frequency.

Using equations (1) and (2), the phase response $\varphi(\omega)$ can be found by:

$$\varphi(\omega) = \arctan \left[ \frac{-b_1 \sin(\omega)}{b_o + b_1 \cos(\omega)} \right] \qquad (3)$$

With the help of GD the relation 2, which yields:

$$T(\omega) = \frac{b_1^2 + b_1 b_o \cos(\omega)}{[b_o + b_1 \cos(\omega)]^2 + b_1^2 \sin^2(\omega)} \times \frac{1}{f_s} \qquad (4)$$

Then, the magnitude responses can be expressed as:

$$|G(\omega)| = \sqrt{[b_o + b_1 \cos(\omega)]^2 + b_1^2 \sin^2(\omega)} \qquad (5)$$

With the understanding of these fundamental concepts, we can now design the FIR-based NGD system. The following subsection addresses the synthesis and properties of NGD based on first-order FIR filters.

### A. First Order FIR-based NGD synthesis

Based on those expressions, the synthesis methodology of FIR-based NGD system can be established according to the maximum desired NGD value $\tau_o$ and the minimal gain values $g_0$ at lower frequency. From the relation (4), at lower frequencies, i.e. $\omega \approx 0$, GD response can be written as:

$$\tau_0 = \frac{b_1}{b_o + b_1} \times \frac{1}{f_s} \qquad (6)$$

and for the magnitude response at $\omega \approx 0$, relation (5) yields:

$$g_o = |b_o + b_1| \qquad (7)$$

Considering relation (6), the GD can be negative when:

$$\frac{b_1}{b_o + b_1} < 0 \Leftrightarrow (b_1 < 0, b_o + b_1 > 0) \qquad (8)$$

Satisfying these conditions, a novel FIR-based filter operating with NGD can be realized. Therefore, all NGD coefficients can be synthesized from relation (6) and (7), which yields:

$$b_0 = g_0(1 - f_s \tau_0) \qquad (9)$$

And, the coefficient, $b_1$, can be expressed as:

$$b_1 = g_0 f_s \tau_0 \qquad (10)$$

It should be noted that $g_o$ is a non-zero numerical constant. It acts as a linear or proportional coefficient linking the normalized time $f_s\tau_o$ to the NGD coefficients $b_i$. Depending on the initial requirements, $g_o$ may represent a minimum gain or maximum attenuation. To design a FIR-based NGD system, $\tau_o$ must be negative. This condition implies that coefficient $b_1$ should also be negative, and its absolute value must be smaller than $b_0$.

### B. First Order FIR-based NGD filter Property

In signal processing, it is important to determine the bandwidth or cutoff frequency to maintain signal integrity. Using these synthesis parameters, we can specify the properties of the FIR-based NGD system. Practically, the FIR-based NGD is also characterized by its limited frequency bandwidth. In this study, we focus exclusively on baseband signal processing. Therefore, the first cutoff frequency can be considered as the lowest significant frequency. The NGD cutoff frequency can be obtained by solving the equation $T(\omega) = 0$. Using equation (4), we have:

$$f_c = \frac{f_s}{2\pi} \arccos\left(-\frac{b_1}{b_o}\right) \qquad (11)$$

Fig. 1 shows the relationship between the normalized frequency $f_c/f_s$ and the coefficients $b_o$ and $b_1$. This helps to better understanding the behavior of the system being studied. Based on Fig. 1(a), the normalized cutoff frequency

<figure><img src="image_2.png" /><figcaption>Fig. 1. Normalized frequency: (a) MAP (b) 3D plots versus $b_o$ and $b_1$.</figcaption></figure>

value ranges from 0.05 to 0.25, depending on the values of $b_0 \in [3, 11]$ and $b_1 \in [-10, -2]$. Using Fig. 1(b), we observe that the cutoff frequency decreases as the NGD coefficient values increase. Furthermore, by substituting the values of $b_0$ and $b_1$ into relation (11) and assuming $T_s = 1/f_s$, it can be expressed as:

$$f_c = \frac{1}{2\pi T_s} \arccos\left(\frac{\tau_0}{\tau_0 - T_s}\right) \qquad (12)$$

This relationship is independent of the parameter $g_0$. It is important to note that from this relation, we can determine the NGD coefficients $b_i$ based on a targeted specification, which is the pair $(\tau_0, f_c)$. Fig. 2 shows the normalized time-advance $\tau_0/T_s$ as a function of the NGD coefficients and the normalized frequency $f_c/f_s$. As a result, the normalized time-advance varies between [-10, -2] within the range $b_0 \in [3, 10]$ and $b_1 \in [1, 10]$.

<figure><img src="image_3.png" /><figcaption>Fig. 2. Normalized NGD value: (a) versus $b_o$ and $b_1$ (b) versus normalized frequency</figcaption></figure>
As shown in Fig. 2(a), the NGD value increases linearly with the increase in NGD coefficients. Fig. 2(b) demonstrates that the cutoff frequency decreases as the NGD values increase. Hence, to transmit all spectral components evenly through the NGD system, the cutoff frequency $f_c$ must be at least equal to the signal's bandwidth.

### III. FIR-BASED NGD REAL-TIME IMPLEMENTATION

The IIR-based NGD filter was integrated into a complete real-time signal processing system implemented on a ZyboZ7 SoC-FPGA board from Digilent, featuring a Xilinx Zynq-7000 family. This chip includes a dual-core ARM Cortex-A9 processor and an internal 12-bit analog-to-digital converter (XADC), dual channel, 1 MSPS, supporting input voltages from 0 to 3.3 V. The FPGA contains 4400 logic cells, 4.9 Mb of internal memory, 220 DSP blocks, 80 I/O pins, and multiple internal clock sources.

Figure 3 shows the block design for this NGD circuit implementation. The complete design comprises five blocks: NGD_FIR_0, which implements the NGD circuit we designed using VHDL. The ADC block consists of two subcomponents: an XADC Wizard to handle the analog-to-digital conversion settings and an ADC Control block to manage its initialization and configuration. The ADC block, which initializes and configures the XADC so that the NGD circuit's input can be digitized; DA2RedComp_0, which drives the external digital-to-analog converter (DAC) to convert the NGD output back to analog; Ila_0, an Integrated Logic Analyzer (ILA) used to observe the NGD block's input and output from an internal perspective; and clk_wiz_0, a Clocking Wizard that generates the various clock signals required by all the other blocks.

<figure><img src="image_4.png" /><figcaption>Fig. 3. NGD implemented on ZyboZ7 SoC platform using Xilinx Vivado</figcaption></figure>

Table I gives a statistic hardware resources used by the complete system, considering the used hardware platform. As it can be seen, the NGD uses very few logical resources, less than 0.4% of the total hardware resources available regarding Look-Up Tables (LUT) and Flip-flops (FF), and 2.5% and 8% DSP and IO units, respectively. The static power consumption of the complete circuit is 94 mW, while the dynamic power consumption is 120 mW. However, the NGD circuit's power consumption is negligible—approximately 2 mW according to the Vivado power estimator after implementation. This opens many exciting possibilities for implementing the NGD technique in highly constrained embedded devices across a

<table><caption>TABLE I
NGD HARDWARE RESOURCES FOOTPRINT ON ZYBOZ7.</caption><thead><tr><th>Ressource</th><th>LUT</th><th>FF</th><th>DSP</th><th>IO</th></tr></thead><tbody><tr><td>Quantity</td><td>58 (0.33%)</td><td>59 (0.17%)</td><td>2 (2.5%)</td><td>8 (8%)</td></tr></tbody></table>

<figure><img src="image_5.png" /><figcaption>Fig. 4. Experimental setup: (a) synoptic and (b) photograph</figcaption></figure>

wide range of applications, such as smart IoT devices and digital communication systems.

Figure 4 illustrates the synoptic and experimental setup. It includes a Zybo Z7 SoC-FPGA platform, a Digilent Analog Discovery 2 (Analog2) for both waveform generation and oscilloscope functionality, and a 12-bit Pmod DA2 DAC module from Digilent [14]. To observe the NGD circuit's input and output on an external scope, we use the onboard XADC and the Pmod DA2 DAC. Internally, the input signal—after digitization by the XADC—and the NGD circuit's output are monitored via an ILA for system validation. Once these signals are verified, they are routed through the DAC module for display on the scope.

For this study, the experimental equipment specifications are summarized in Table II.

### IV. RESULTS AND DISCUSSIONS

NGD performance can be evaluated using transient tests that reveal its key characteristics. A Gaussian-shaped input is ideal, as its smooth spectrum fits within the NGD passband, making it easier to analyze the transient behavior of an FIR-based NGD filter [13]. The input waveform is defined analytically as follows:

$$v_{input}(t) = \hat{v} \times \exp \left[ -\frac{(t - t_0)^2}{2t_a^2} \right] \quad (13)$$

With $\hat{v}$ is the peak amplitude occurs at the mean time $t_0$; in other words, $\hat{v} = v_{input}(t_0)$. The temporal standard deviation $t_a$ of the Gaussian pulse is obtained from its full width at half maximum, the time interval between the two instants at which the waveform falls to $\hat{v}/2$. In our experiments, the circuit is driven by a Gaussian pulse centered at $\tau_0 = 47\mu s$. The pulse is generated with a Analog2 wave generator set to 3 kHz, 3.3 V amplitude, and captured at 14 MS/s over 8192 samples.
<table><caption>TABLE II
SETUP ELEMENTS SPECIFICATIONS AND PARAMETERS.</caption><thead><tr><th>N</th><th>Ref.</th><th>Function</th><th>Description</th><th>Parameter</th><th>Value</th></tr></thead><tbody><tr><td>1</td><td>Analog discovery</td><td>Waveform generator</td><td>Input test signals</td><td>Sampling rate<br>Bandwidth</td><td>62.5 MS/s<br>30 MHz</td></tr><tr><td>2</td><td>Analog discovery</td><td>Digital oscilloscope</td><td>Input/output signal monitoring</td><td>Sampling rate<br>Bandwidth<br>Channels<br>Resolution</td><td>1 GS/s<br>30 MHz<br>2<br>12 bits</td></tr><tr><td>3</td><td>Pmod DA2</td><td>DAC</td><td>Dual-channel digital-to-analog converter</td><td>Sampling rate<br>Resolution</td><td>25 MS/s<br>12 bits</td></tr><tr><td>4</td><td>Zybo Z7 (XADC)</td><td>ADC</td><td>Analog-to-digital converter</td><td>Sampling rate<br>Resolution</td><td>1 MS/s<br>12 bits</td></tr></tbody></table>

PC & Picoscope 6 application

As an application of the previous concept, the desired values for magnitude and group delay are arbitrarily chosen as follows: $g_0 = -0.57$ dB and $\tau_0 = -2$ ns. Based on these parameters, the FIR NGD filter coefficients can be obtained as $b_0 = 15.924$ and $b_1 = -14.952$.

<figure><img src="image_6.png" /><figcaption>Fig. 5. Magnitude and group delay</figcaption></figure>

According to Fig. 5, and as expected from theory, the baseband NGD reaches a minimum value of $-2$ ns, with a cut-off frequency of approximately 429 MHz for a sampling time of $T_s = 0.13$ ns.

Figure 6 shows the Integrated Logic Analyzer (ILA) capture and oscilloscope trace for this measurement.

Fig. 6(a) shows two signals acquired simultaneously using an Integrated Logic Analyzer (ILA) analyzer. The top waveform represents the input signal, while the bottom waveform corresponds to the output signal of the NGD circuit, allowing for a temporal analysis of their behavior. Two vertical cursors of different colors (blue and yellow) have been positioned at characteristic points of the signals, such as the maxima. The associated numerical values indicate that the blue cursor, positioned at 28.80 ns (output), and the yellow cursor, positioned at 30.52 ns (input). Then, NGD output is advanced in time by about 1.7 ns in the ILA observation. This difference corresponds to the advancement time of the output signal with respect to the input signal of the NGD system. This

difference, about of 0.28 ns, from the theoretical prediction can be explained by hardware limitations, particularly the actual number of samples that can be applied.

Fig. 6(b) shows two signals acquired simultaneously using a digital oscilloscope, with the yellow and blue traces corresponding to the input signal (yellow) and the NGD output signal (blue), respectively. Both signals exhibit similar periodic shapes, but with a clearly visible temporal shift. The vertical axis represents the voltage (in volts) and the horizontal axis

<figure><img src="image_7.png" /><figcaption>(a) ILA result Gaussian waveform</figcaption></figure>

<figure><img src="image_8.png" /><figcaption>(b) Scope result Gaussian waveform
Fig. 6. ILA and Scope screenshots of Gaussian waveforms at 3kHz.</figcaption></figure>
represents time (in microseconds). Two red vertical cursors have been placed at the maxima of each signal to allow for precise time measurement. The numerical values indicate that the first cursor (X1, NGD output) is positioned at 47.585 µs, and the second (X2, input) at 62.56 µs, corresponding to the peaks of the output (blue) and input (yellow) signals, respectively. The measured voltages at these points are also shown: 3.161 V for C2 (output) and 3.087 V for C1 (input). The time difference between the two peaks, approximately 14.975 µs, corresponds to a propagation advance between the two signals, related to the characteristics of the tested NGD circuit. The total signal-processing latency of the proposed NGD circuit is approximately 2 µs.

<figure><img src="image_9.png" /><figcaption>Fig. 7. Trapezoidal waveforms test at 3kHz</figcaption></figure>

Fig. 7 shows the waveforms of two trapezoidal signals acquired simultaneously using a digital oscilloscope. The yellow trace represents the input signal, while the blue trace corresponds to the output signal of the tested circuit. Both signals exhibit sharp transitions between two voltage levels, forming a waveform similar to a square or ramp signal. At the amplitude level of 1 V, the plot clearly demonstrates a temporal advance of the blue signal (output) compared to the yellow signal (input). Specifically, during the rising edge, the blue signal reaches the 1 V level before the yellow signal, indicating a negative delay of approximately 15 µs introduced by the circuit. The same phenomenon is observed during the falling edge, where the blue signal drops below 1 V before the yellow signal does. This temporal advance at the 1 V level illustrates the typical behavior of a negative group delay (NGD) circuit, in which the output signal precedes the input at certain amplitude thresholds. This property is essential for highlighting the unique characteristics of the NGD circuit under test and for accurately quantifying the time shift induced at a specific amplitude.

The two tests conducted with trapezoidal and Gaussian input signals both demonstrate the characteristic behavior of the NGD circuit. In both cases, a temporal advance of the output signal relative to the input was observed at certain amplitude levels, confirming the circuit's ability to generate a negative delay between input and output. The nature of this temporal advance varies depending on the input waveform: with the trapezoidal signal, the advance is especially pronounced during sharp transitions, while with the Gaussian signal, the NGD effect appears more gradually around the signal's peak. These

results highlight the robustness and repeatability of the NGD effect in the tested circuit, regardless of the input signal shape.

## V. CONCLUSION

This work has demonstrated that even a simple, low-order FIR filter can be engineered to exhibit negative group delay at baseband, opening new possibilities for real-time signal pre-processing in resource-constrained embedded platforms. Through both simulation and an FPGA-based proof-of-concept, we have validated that the proposed design reliably time-advances in line with theoretical predictions. This work highlights the NGD-FIR's exceptional efficiency and practicality, laying the groundwork for its integration into smart IoT network, real-time communication front-ends, and other latency-sensitive applications based on FPGA [15]. Future investigations might explore higher-order designs for broader bandwidths and adaptive NGD tuning.

## REFERENCES

[1] Y. Salathé, P. Kurpiers, T. Karg, C. Lang, C. K. Andersen, A. Akin, S. Krinner, C. Eichler, and A. Wallraff, "Low-latency digital signal processing for feedback and feedforward in quantum computing and communication," *Phys. Rev. Applied*, vol. 9, p. 034011, Mar 2018.

[2] M. Lu, X. Wang, P. C. Loh, F. Blaabjerg, and T. Dragicevic, "Graphical evaluation of time-delay compensation techniques for digitally controlled converters," *IEEE Transactions on Power Electronics*, vol. 33, no. 3, pp. 2601-2614, 2018.

[3] J. Liu and R. Xu, "Adaptive synchronisation of memristor-based neural networks with leakage delays and applications in chaotic masking secure communication," *International Journal of Systems Science*, vol. 49, no. 6, pp. 1300-1315, 2018.

[4] M. W. Mitchell and R. Y. Chiao, "Negative group delay and "fronts" in a causal system: An experiment with very low frequency bandpass amplifiers," *Physics Letters A*, vol. 230, no. 3-4, pp. 133-138, 1997.

[5] —, "Causality and negative group delays in a simple bandpass amplifier," *American Journal of Physics*, vol. 66, no. 1, pp. 14-19, 1998.

[6] O. Baloglu, O. Cicekoglu, and N. Herencsar, "Single cfoa-based active negative group delay circuits for signal anticipation," *Engineering Science and Technology, an International Journal*, vol. 48, p. 101590, 2023.

[7] T. Eudes and B. Ravelo, "Cancellation of delays in the high-rate interconnects with uwb ngd active cells," *Applied Physics Research*, vol. 3, no. 2, p. 81, 2011.

[8] S. Lalléchère, L. Rajaoarisoa, L. Clavier, R. S. Galan, and B. Ravelo, "Bandpass NGD function design for 5G microwave signal delay synchronization application," *Comptes Rendus. Physique*, vol. 22, no. S1, pp. 53-71, 2021.

[9] T. Pyragiene and K. Pyragas, "Design of a negative group delay filter via reservoir computing approach: Real-time prediction of chaotic signals," *Physics Letters A*, vol. 383, no. 25, pp. 3088-3094, 2019.

[10] P.-Y. Chou, J.-F. Chien, K. S. Chen, Y.-T. Huang, C.-C. Chen, and C. K. Chan, "Anticipation and negative group delay in a retina," *Phys. Rev. E*, vol. 103, p. L020401, Feb 2021.

[11] B. Ravelo, M. Guerin, W. Rahajandraibe, and L. Rajaoarisoa, "All-pass ngd fir original study for sensor failure detection application," *IEEE Transactions on Industrial Electronics*, vol. 70, no. 9, pp. 9561-9571, 2023.

[12] B. Ravelo, M. Guerin, W. Rahajandraibe, V. Gies, L. Rajaoarisoa, and S. Lalléchère, "Low-pass ngd numerical function and STM32 mcu emulation test," *IEEE Transactions on Industrial Electronics*, vol. 69, no. 8, pp. 8346-8355, 2021.

[13] R. Randriatsiferana, J. Lorandel, R. Salvador, and C. Moy, "Novel digital ngd methodology for fpga-based embedded systems," *IEEE Access*, vol. 12, pp. 71520-71534, 2024.

[14] Digilent, "Pmodda2™ reference manual," 2016. [Online]. Available: https://digilent.com/reference/pmod/pmodda2/start

[15] A. Magyari and Y. Chen, "Review of state-of-the-art fpga applications in iot networks," *Sensors*, vol. 22, no. 19, 2022.