# Test Setup for Measuring the Impact of Gate Stress on a GaN-HEMT's Output Characteristic

Daniel Breidenstein, Sophia Roesel, Benedikt Kohlhepp, Thomas Duerbaum

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Daniel Breidenstein, Sophia Roesel, Benedikt Kohlhepp, Thomas Duerbaum. Test Setup for Measuring the Impact of Gate Stress on a GaN-HEMT's Output Characteristic. The 26th European Conference on Power Electronics and Applications, GDR SEEDS France & EPE Association, Mar 2025, Paris, France. 10.34746/epe2025-0034. hal-05075778

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# Test Setup for Measuring the Impact of Gate Stress on a GaN-HEMT's Output Characteristic

Daniel Breidenstein

Friedrich-Alexander-Universität
Erlangen-Nürnberg

Department EEI, Institute of Optoelectronics
Erlangen, Germany

E-Mail: daniel.breidenstein@fau.de

Sophia Roesel

Friedrich-Alexander-Universität
Erlangen-Nürnberg

Department EEI, Institute of Optoelectronics
Erlangen, Germany

E-Mail: sophia.roesel@fau.de

Benedikt Kohlhepp

Technische Universität Berlin

Department of Power Electronics
Berlin, Germany

E-Mail: benedikt.kohlhepp@tu-berlin

Thomas Duerbaum

Friedrich-Alexander-Universität
Erlangen-Nürnberg

Department EEI, Institute of Optoelectronics
Erlangen, Germany

E-Mail: thomas.duerbaum@fau.de

**Index Terms**—Gallium Nitride (GaN), HEMT, Device Characterization, DC Bias, Transient Analysis

**Abstract**—Precisely estimating conduction losses requires knowledge of the device's output characteristic in the ohmic region. For GaN-HEMTs, it dynamically depends on time, temperature, and applied biases. To study the impact of gate bias over time, a transient measurement approach is applied, that can acquire the start of the output characteristic with a single pulse. This ensures neglectable impact of temperature changes and trapping state on the single measurement. In addition, the short acquisition time allows studying the impact of the bias in the milliseconds range. Therefore, the measurement pulses are altered with stress intervals. While reference measurements for a traditional Si-MOSFET under constant gate bias show almost no change in the output characteristic over time, test results for a commercial GaN-HEMT reveal changes for low gate voltages. This demonstrates that the user should at least be aware of such trapping problems effecting measurements, which may lead to differences in characterization and application.

## I. INTRODUCTION

Low on-state resistance in combination with small capacitances make GaN-HEMTs (Gallium Nitride High-Electron-Mobility Transistors) attractive candidates for power converters. However, dynamic on-state resistance

[1] and threshold voltage instability [1–4] – caused by trapping due to e.g. gate or drain bias as well as switching operation – are widely known in literature. Those impact conduction as well as switching losses and, therefore, the converter's performance. The complex dependencies on bias type, time, as well as temperature [1] can not be derived from the conventional datasheets, which therefore lack application relevant data.

Multiple new characterization methods are discussed in the literature, including clamping circuits to measure the dynamic on-state resistance in switched operation [5], or study of threshold voltage shift over time under drain and gate bias [3, 4, 6].

This paper focuses on the ohmic region of the output characteristic, shown in Fig. 1, necessary for precise prediction of conduction losses in power converters. Regarding the impact of DC bias on the output characteristic

<figure><img src="image_2.png" /><figcaption>Figure 1. Output characteristic and conventions of the current and voltages of the device</figcaption></figure>
teristic, [7] shows the influence of drain bias after 10 min of stress – measured with a conventional B1506A power device analyzer. A shift of the output characteristic's saturation current at low gate voltages was observed, impacting the switching losses. For high gate voltages, the impact of the stress is negligible.

Due to the required number of pulses – which accumulate trapping – as well as pulse length, widely used pulsed methods lack in their capability to analyze short-term effects as well as a constant trapping state during the measurement.

In addition, for GaN-HEMTs, self-heating is much more pronounced due to the significantly smaller active area. Requirements for accurate results are therefore isothermal and isodynamic conditions [8]. Isothermal means constant temperature and, therefore, negligible self-heating and isodynamic means a constant trapping state of the device.

To ensure isodynamic conditions during IV-characterization of transistors, [9] uses a double pulse technique to keep the trapping state constant during all measurement pulses.

To analyze the impact of gate stress over time as well as following recovery after stress, this paper proposes to utilize a transient measurement procedure – previously discussed in [10] for MOSFET characterization with limited self-heating and revisited in [11] to study the ohmic region of the output characteristic of GaN-HEMTs at different temperatures. Controlled turn-on of an auxiliary switch, with adapted turn-on speed, connected in series to the DUT, leads to a transiently rising drain voltage and current. Simultaneous acquiring the voltage and current delivers the output characteristic for a given gate voltage. With the single pulse required for the entire ohmic region of the output characteristic, this method approaches a consistent trapping state of the device (isodynamic condition) during the measurement as closely as possible. In contrast, pulsed methods combine results from different time stamps and, thus, trapping states.

In this paper, after acquiring the unstressed output characteristic, the gate-source voltage remains constant within the so-called stress interval. After stressing the device, another measurement obtains the corresponding output characteristic, revealing the impact of the bias on the output characteristic. After finishing the stressing of the devices for a defined time interval, removing the bias allows for studying the regeneration process.

Section II describes the measurement setup and sequence in detail. Section III presents results for a commercial GaN-HEMT as well as a conventional Si-MOSFET for verification.

## II. MEASUREMENT SETUP

Fig. 2 shows the proposed measurement setup, extending the idea of [10]. First Section II-A describes the transient measurement technique for the single output characteristic, followed by the extension to obtain its shift over time due to gate bias in Section II-B.

<figure><img src="image_3.png" /><figcaption>Figure 2. Measurement setup</figcaption></figure>

### A. Measurement of single output characteristic

While measuring the waveforms for a single output characteristic, $S_{g,on}$ is always turned on and applies the constant voltage $u_{bias,gs}$ to the DUT's gate. So $u_{gs}$ equals $u_{bias,gs}$, which is stabilized by the external capacitance $C_{gs}$. The DUT is connected in series to a shunt resistor $R_{shunt}$ for current acquisition and an auxiliary MOSFET switch $S_{aux}$. Before measurement, $u_{aux,gs}$ is 0 V, so $S_{aux}$ blocks the entire voltage $U_{in}$.

The measurement is initiated by applying a rising edge at $u_{pulse}$, that slowly turns on $S_{aux}$ through the RC-circuit consisting of $C_{aux}$ and $R_{aux,on}$ in a well-defined manner. $S_{aux}$ is operating in the saturation region, so with rising gate voltage $u_{aux,gs}$ the drain current $i_d$ of $S_{aux}$ slowly increases (µs-scale), which is equal to the DUT's drain current. The DUT's drain-source voltage also rises according to the output characteristic. The remaining part of $U_{in}$ drops at $R_{shunt}$ and $S_{aux}$. Fig. 3 illustrates the procedure.
<figure><img src="image_4.png" /><figcaption>Figure 3. Measurement of single output characteristic</figcaption></figure>

Simultaneous acquisition of the voltages $u_{Ch1}$ and $u_{Ch0}$ in Fig. 2 gives the DUT's drain-source voltage and drain current according to Eq. (1) and (2), resulting in the output characteristic of the DUT for a given gate voltage $u_{gs}$.

$$u_{ds} = u_{Ch1} \qquad (1)$$

$$i_d = \frac{u_{Ch0} - u_{Ch1}}{R_{shunt}} \qquad (2)$$

In addition to the rising edge output characteristic, the falling edge one after the end of $t_{pulse}$ can be recorded, by a corresponding selection of $R_{aux,off}$, which is also

shown in Fig. 3. It can serve to verify that self-heating as well as the impact of parasitic inductances are negligible. As an alternative, a fast turn-off can reduce stress and self-heating.

## B. Measurement of output characteristic shift

To study the impact of gate bias on the output characteristic, the measurement procedure described in the previous section alternates with stress and relax intervals. The switches $S_{g,on}$ and $S_{g,off}$ are complementary controlled to apply and remove the gate voltage of the DUT. Fig. 4 illustrates the measurement sequence. Prior to $t_{0,s}$ the DUT is preconditioned by removing all stress types for a sufficient amount of time (> 2 days), ensuring a detrapped device. Therefore, $S_{g,off}$ is turned on, keeping $u_{gs}$ at 0 V and $S_{aux}$ blocks $U_{in}$.

The stress phase starts with the turn-off of $S_{g,off}$ and simultaneous turn-on of $S_{g,on}$, charging $u_{gs}$ to $u_{bias,gs}$. In addition, the previously described measurement procedure is initiated with the rising edge of $u_{pulse}$, resulting in the unstressed output characteristic. Note that $u_{gs}$ and $u_{pulse}$ can be applied at the same time in case of a sufficiently small time constant of $C_{gs}$ and $R_{g,on}$ due to the fact that $u_{aux,gs}$ has to reach the threshold voltage of $S_{aux}$ before $i_d$ rises. This minimizes prestress of the device before the first measurement.

A stress phase with the length $t_{stress1}$ follows, with applied gate voltage. At $t_{1,s}$, the first stressed output characteristic is recorded. The process of stressing phases

<figure><img src="image_5.png" /><figcaption>Figure 4. Measurement procedure of the output characteristic shift during stressing and relaxing</figcaption></figure>
and measuring phases can be repeated the desired number of times before the gate stress is removed at $t_{0,r}$ by discharging $C_{gs}$ with $R_{g,off}$ and $S_{g,off}$.

After the first relaxing phase, the output characteristic is recorded at $t_{1,r}$. Therefore, $C_{gs}$ must be charged to $u_{bias,gs}$, interrupting the relaxation. After the falling edge of $u_{pulse}$ it remains charged until finishing the falling edge measurement, or it is immediately discharged if only the rising edge is recorded. Those relaxing and measurement phases can again be alternated the desired number of times, giving a rising and optional falling edge output characteristic per measurement. This procedure allows studying the impact of trapping accumulation (and detrapping) on the output characteristic.

### III. MEASUREMENT RESULTS

Fig. 5 shows the implemented setup for a 200 V commercial GaN-HEMT [12]. As previously shown [10], proper selection of the time constant $\tau_{RC}$ of $C_{aux}$ with $R_{aux,on}$ or $R_{aux,off}$ is critical. Fast turn-on of $S_{aux}$ falsifies the results as voltage drops across parasitic inductances in the measurement loop. On the other hand, isothermal and isodynamic performances degrade with increasing time constants. So, finding the right compromise in turn-on (and turn-off) speed is essential, which can be achieved by comparing measurement results for different time constants. To maximize the possible turn-on speed at which the impact of parasitic inductances is negligible, the PCB layout is optimized for low coupling inductances by a vertical commutation loop. For DUTs with low on-state resistance, like the one studied in this paper, proper placement of the measurement points and ground is also critical to minimize errors.

So, for example in case of a larger shunt value compared to on-state resistance, the connection of $u_{Ch1}$ should prioritize measuring $u_{ds}$ over the shunt voltage. Table I summarizes the relevant circuit parameters (see

<figure><img src="image_6.png" /><figcaption>Figure 5. Image of measurement setup</figcaption></figure>

<table><caption>Table I
CIRCUIT PARAMETERS OF MEASUREMENT SETUP</caption><thead><tr><td>Parameter</td><td>Value</td></tr></thead><tbody><tr><td>R<sub>aux,on</sub></td><td>5.1 kΩ</td></tr><tr><td>R<sub>aux,off</sub></td><td>6.8 kΩ or 100 Ω (only rising)</td></tr><tr><td>C<sub>aux</sub></td><td>22 nF</td></tr><tr><td>R<sub>shunt</sub></td><td>100 mΩ</td></tr><tr><td>U<sub>in</sub></td><td>4 V</td></tr><tr><td>t<sub>pulse</sub></td><td>150 μs</td></tr></tbody></table>

Fig. 2) used in the following. For accurate extraction of small shifts in the output characteristic, a digitizer card of the type PXIe-5922 records the two voltages at 1 MS s⁻¹ with 24 bit resolution. Utilizing a conventional oscilloscope is also possible but can increase noise.

A programmable arbitrary waveform generator controls the two switches $S_{g,on}$ and $S_{g,off}$ as well as $u_{pulse}$, implementing the measurement sequence shown in Fig. 4.

#### A. Verification of the Measurement Setup with a Si-MOSFET

To verify that no other external influences, like an offset-drift, are present, measurements are first performed for a conventional Si-MOSFET [13], whereby no significant shift of the output characteristic is expected. Fig. 6 shows the obtained rising edge output characteristics after different stress periods.

<figure><img src="image_7.png" /><figcaption>Figure 6. Measurement results for a Si-MOSFET after different gate voltage stress periods</figcaption></figure>

The measurement time instances during the stressing phase are spaced logarithmically to cover a large range
of time constants. The time-labels define the total time passed since $t_{0,s}$ (Fig. 4). Only a minor change of the output characteristic is present at for example $u_{gs} = 5.5$ V. The corresponding change in on-state resistance ($\Delta R_{ds,on}$) extracted for a drain-current of $i_d = 20$ A is shown in Fig. 7 and is less than 60 µΩ (0.4 %) for the smallest gate voltage, thus excluding other effects affecting the measurement.

<figure><img src="image_8.png" /><figcaption>Figure 7. Change in on-state resistance of Si-MOSFET after different stress periods at $i_d = 20$ A</figcaption></figure>

## B. Influence of self-heating and parasitic inductances

Secondly, it is verified with measurements performed on the GaN-device that effects of self-heating and parasitic inductances are neglectable with the given time constant $\tau_{RC}$ and pulse length $t_{pulse}$ in Table I. This procedure of tuning the parameters must be performed for every type of device individually, since the optimal values depend on the package of the device and the layout of the test setup. For inductances, Fig. 8 compares the rising and falling edge measurements of the configuration in Table I ($1 \cdot \tau_{RC}$ for rising and falling) to an increased turn-on speed ($0.1 \cdot \tau_{RC}$ for rising and falling).

While the rising and falling edge measurements of the slow configuration ($1 \cdot \tau_{RC}$) are almost congruent, at the increased turn-on speed, a small deviation is present, verifying proper selection of the time constants.

On the other hand, Fig. 9 demonstrates the effect of self-heating by an increased pulse length, resulting in a hysteresis. The deviation of falling and rising edge results verifies the selection of the pulse length. Note that the decrease in voltage and current at the end of the falling edge is due to the capacitor stabilizing $U_{in}$ getting discharged.

<figure><img src="image_9.png" /><figcaption>Figure 8. Comparison of influence of parasitic inductances on rising and falling edge measurement for the GaN-HEMT at $u_{gs} = 3$ V; For $1 \cdot \tau_{RC}$ falling and rising edge overlap</figcaption></figure>

<figure><img src="image_10.png" /><figcaption>Figure 9. Comparison of influence of self-heating on rising and falling edge measurement; For $t_{pulse} = 150$ µs falling and rising edge overlap</figcaption></figure>

## C. Measurement results for a GaN-HEMT

For the studies on the impact of gate stress over time, only the rising edge characteristic is recorded ($R_{aux,off} = 100$ Ω) to reduce measurement time as well as stress on the device. Fig. 10 exemplarily shows the acquired waveforms of one measurement for $u_{gs} = 3$ V. Eq. (1) and Eq. (2) deliver the drain current and drain-source voltage.
<figure><img src="image_11.png" /><figcaption>Figure 10. Recorded waveforms for GaN-HEMT at $u_{gs} = 3$ V and extracted $u_{ds}$ and $i_d$</figcaption></figure>

The measurement instances during the stressing phase are again spaced logarithmically and refer to $t_{0,s}$. Fig. 11 shows the rising edge results for different gate voltages during the stressing interval after different stress times.

<figure><img src="image_12.png" /><figcaption>Figure 11. Measured output characteristic shift of a 200 V enhancement-mode GaN-HEMT after different gate voltage stress periods</figcaption></figure>

For 5 V applied to the gate, a neglectable small impact is visible while for 3 V a clear shift to higher on-resistances is present. For a power electronics application, this means that conduction losses are almost unaffected when the device is fully turned on, but switching losses can be affected.

For the second phase of the study – the relaxing phase – Fig. 12 shows the obtained rising edge output characteristics. In addition, the initial (unstressed) characteristic is plotted together with the last one of the stressing phase. The measurement instances are again

logarithmically spaced in time and refer to the total time passed since $t_{0,r}$.

<figure><img src="image_13.png" /><figcaption>Figure 12. Measured output characteristic shift of a 200 V enhancement-mode GaN-HEMT after different relax periods following stressing</figcaption></figure>

For all gate voltages the output characteristics return towards the initial unstressed state. The extracted change in on-state resistance for $i_d = 20$ A is shown in Fig. 13.

<figure><img src="image_14.png" /><figcaption>Figure 13. Change in on-state resistance of a 200 V enhancement-mode GaN-HEMT after different stress and relax periods at $i_d = 20$ A</figcaption></figure>

For $u_{gs} = 3$ V an increase of 2.1 mΩ (13.1%) can be observed after 100 s of applied gate stress.

## IV. CONCLUSION

To predict conduction losses in power electronic applications, the impact of trapping caused by gate bias on the ohmic region of the output characteristic is studied. Therefore, a transient measurement approach is used, minimizing self-heating as well as measurement time. This ensures an isodynamic trapping state during measurement and allows performing studies in
smaller time scales. While results for a conventional Si-MOSFET show no shift of the output characteristic at different gate voltages, a clear shift to increased on-resistance is present for the studied low-voltage GaN-HEMT at lower gate voltages. When fully turned on, the effect becomes less notable. This calls for further studies regarding effects under different stress types (e.g. drain bias) or switched operation as well as their impact on lifetime.

## REFERENCES

[1] M. Meneghini et al., "GaN-based power devices: Physics, reliability, and perspectives," *Journal of Applied Physics*, vol. 130, no. 18, p. 181101, Nov. 2021. DOI: 10.1063/5.0061354.

[2] J. Chen et al., "OFF-State Drain-Voltage-Stress-Induced VTH Instability in Schottky-Type p-GaN Gate HEMTs," *IEEE Journal of Emerging and Selected Topics in Power Electronics*, vol. 9, no. 3, pp. 3686-3694, Jun. 2021. DOI: 10.1109/JESTPE.2020.3010408.

[3] D. Breidenstein, B. Kohlhepp, and T. Dürbaum, "Cost-Effective Test Setup for Measuring Threshold Voltage Shift of GaN-HEMTs under Long-Term Drain-Voltage Stress," in *2023 IEEE 10th Workshop on Wide Bandgap Power Devices & Applications (WiPDA)*, Charlotte, NC, USA, 2023. DOI: 10.1109/WiPDA58524.2023.10382213.

[4] B. Kohlhepp, D. Breidenstein, and T. Dürbaum, "Test Setup to Study Threshold Voltage Shift of GaN-HEMTs Under Short- and Long-Term Gate and Drain Bias," *IEEE Journal of Emerging and Selected Topics in Power Electronics*, pp. 1-1, 2024. DOI: 10.1109/JESTPE.2024.3464613.

[5] B. Kohlhepp, D. Kübrich, M. Tannhauser, A. Hoffmann, and T. Dürbaum, "Test Setup for Dynamic ON-State Resistance Measurement of High- and Low-Voltage GaN-HEMTs Under Hard and Soft Switching Operations," *IEEE Transactions on Instrumentation and Measurement*, vol. 69, no. 10, pp. 7740-7751, Oct. 2020. DOI: 10.1109/TIM.2020.2985186.

[6] R. Yu, S. Jahdi, P. Mellor, J. O. Gonzalez, and A. Olayiwola, "Performance Instability of 650 V p-GaN Gate HEMT Device under Temperature-related Positive Gate Bias Stresses," in *PCIM Europe 2024; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management*, Nuremberg, Germany, Jun. 2024.

[7] F. Yang, C. Xu, and B. Akin, "Characterization of Threshold Voltage Instability Under Off-State Drain Stress and Its Impact on p-GaN HEMT Performance," *IEEE Journal of Emerging and Selected Topics in Power Electronics*, vol. 9, no. 4, pp. 4026-4035, Aug. 2021. DOI: 10.1109/JESTPE.2020.2970335.

[8] B. Charles and L. Dunleavy, "Performing and analyzing pulsed current-voltage measurements," Feb. 2004.

[9] A. Santarelli et al., "A Double-Pulse Technique for the Dynamic I/V Characterization of GaN FETs," *IEEE Microwave and Wireless Components Letters*, vol. 24, no. 2, pp. 132-134, Feb. 2014. DOI: 10.1109/LMWC.2013.2290216.

[10] T. Lopez and R. Elferich, "Measurement Technique for the Static Output Characterization of High-Current Power MOSFETs," *IEEE Transactions on Instrumentation and Measurement*, vol. 56, no. 4, pp. 1347-1354, Aug. 2007. DOI: 10.1109/TIM.2007.900146.

[11] S. Roesel, D. Breidenstein, and T. Dürbaum, "Transient Measurement of the Output Characteristics with Focus on the Ohmic Region for Si-MOSFETs and GaN-HEMTs," in *PELSS Power Electronics Student Summit 2024*, Kassel, Germany, Aug. 2024.

[12] Efficient Power Conversion Corporation (EPC), *Datasheet EPC2307*, El Segundo, CA, USA, 2023.

[13] Infineon Technologies AG, *Datasheet BSC097N06NS (OptiMOS Power-Transistor 60V)*, München, Germany, Nov. 2019.