# Convolutions Predictable Offloading to an Accelerator: Formalization and Optimization

Benjamin Husson, Mohammed Belcaïd, Thomas Carle, Claire Pagetti

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Benjamin Husson, Mohammed Belcaïd, Thomas Carle, Claire Pagetti. Convolutions Predictable Offloading to an Accelerator: Formalization and Optimization. 13th European Congress of Embedded Real Time Systems (ERTS), Feb 2026, Toulouse, France. 10.82331/ERTS.2026.25. hal-05513761

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# Convolutions Predictable Offloading to an Accelerator:
Formalization and Optimization

Benjamin Husson¹, Mohammed Belcaid², Thomas Carle³, and Claire Pagetti⁴

1,2 CS Group, Toulouse, France

³ Université de Toulouse – IRIT, Toulouse, France

⁴ ONERA, Toulouse, France

## ABSTRACT

Convolutional neural networks (CNNs) require a large number of multiply-accumulate (MAC) operations. To meet real-time constraints, they often need to be executed on specialized accelerators composed of an on-chip memory and a processing unit. However, the on-chip memory is often insufficient to store all the data required to compute a CNN layer. Thus, the computation must be performed in several offloading steps. We formalise such sequences of steps and apply our formalism to a state of the art decomposition of convolutions. In order to find optimal strategies in terms of duration, we encode the problem with a set of constraints. A Python-based simulator allows to analyse in-depth computed strategies.

## 1. INTRODUCTION

The advent of Machine Learning has opened unprecedented possibilities across the industry. Among Machine Learning models, Convolutional Neural Networks (CNNs) have proven their capabilities in image segmentation, classification, and detection. This work focuses on the use of off-line trained CNNs for safety-critical real-time applications. A first observation is that convolutions and dense layers often result in a large number of MAC (multiply-accumulate) operations, leading to high computational demand. Thus, to achieve reasonable temporal performance, CNNs often need to be executed on specialized accelerators such as Graphics Processing Units [20], Tensor Processing Units (TPUs) [11], Neural Processing Units [19], and FPGA-based accelerators [18] [14] [15]. Such accelerators may, for instance, contain parallel MAC hardware units that permit efficient MAC operations execution. Figure 1 illustrates a generic accelerator architecture where *MEM* is the on-chip memory and *PE* is the processing part. Data are exchanged between the CPU and the accelerator via an off-chip DRAM.

### 1.1. Problem statement

Usually, the on-chip memory is rather small, preventing complete local storage of both the CNN parameters and the input needed to realize the computation. Consequently, the computation

<figure><img src="image_2.png" /><figcaption>Figure 1. Generic accelerator architecture</figcaption></figure>

has to be done in several steps [25]. Here, a step corresponds to a sequence of: 1) invalidating / freeing the memory from the loaded elements; 2) optionally writing back the computed value to the DRAM; 3) loading a slice of the input and a subset of the parameters (e.g., kernels for a convolution or weights for a dense layer); 4) performing the partial computation involving the slice and the subset of parameters; 5) and looping back to 1) as long as needed. Figure 2 illustrates the sequence involved in a step.

<figure><img src="image_3.png" /><figcaption>(a) 1) free the memory and 2) store the results</figcaption></figure>

<figure><img src="image_4.png" /><figcaption>(b) 3) load the elements</figcaption></figure>

<figure><img src="image_5.png" /><figcaption>(c) 4) launch the computation
Figure 2. A step = sequence of execution</figcaption></figure>

The CNNs we consider contribute to safety-critical real-time applications (e.g. drone detection [1] or visual-based landing [5]). Consequently, it is mandatory to estimate the time required to execute the model, which amounts to estimating the latency of each step and their combination. To do so, we rely

<footnote>Benjamin Husson et al. This is an open-access article distributed under the terms of the Creative Commons Attribution 4.0 License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.</footnote>
on a formal model of the offloading process.

## 1.2. Contributions

In this work, we address the offloading of convolutional layers to specialized accelerators when the on-chip memory is insufficient to contain a layer, meaning that the computation must be performed in multiple steps. Our contributions include:

* The formalization of the notion of *strategy*, where a strategy is a sequence of steps. This requires defining how the input and the kernels are decomposed per step, quantifying the induced memory transactions between on-chip memory and DRAM, and tracking the on-chip memory footprint.

* The application of our formalism to one of the four strategies proposed in [23], resulting in a formal strategy denoted further S1-baseline. Contrary to our work, which considers a fixed accelerator and searches for end-to-end durations, the purpose of the authors was to minimize the on-chip memory size and reduce the bandwidth between the DRAM and the on-chip memory.

* The translation of S1 into an ILP problem in charge of finding an optimal strategy (in terms of duration) for a given accelerator and a given convolutional layer to be mapped.

* A Python-based simulator to track which data are loaded, freed, computed, and what is stored in the on-chip memory at each step for a user defined strategy.

## 1.3. Applicability of the proposed approach

The purpose of the approach is manifold. Even though the formalism remains at a high level of abstraction, it can model state-of-the-art execution strategies and hardware architectures. This, for instance, enables the comparison between different solutions with respect to the end-to-end duration criteria. The simulator complements the analysis by offering visual inspection of the behaviours (e.g. showing which data are loaded, freed, computed and written at each step), and a detailed description of the internal state of the accelerator (memory footprint of the input, kernels and output at each step). The ILP formulation and two heuristic-based strategies offer an efficient way to help designers deploy convolution layers.

We detail several hardware architectures that comply with our work. Daini et al. [3] deploy CNNs on multi-core processors which come with local scratch-pad memory (SPM) and a shared DRAM as illustrated in Figure 3. We can map this architecture to our generic one of Figure 1: the on-chip memory corresponds to the union of the local SPMs and the processing part is the union of the cores. Contrary to us, the authors of [3] consider that a step is the execution of a full layer (e.g. a convolution). We can thus complete their work by decomposing layers themselves into a succession of steps. In that case, both our notion of strategy and our ILP problem can help find efficient strategies.

Chen et al. [2] introduced and implemented the Eyeriss accelerator, see Figure 4, with the objective of optimising the dataflow for convolutional neural networks. Our formalism can be applied at different levels of the memory hierarchy: by considering the on-chip memory to be either the global buffer

or the union of the scratch-pad memories. The processing part is the PE array. In addition, the hardware architecture enables the computation of 2D convolution by dividing it into 1D convolution primitives. Thus, the ILP problem is also applicable.

<figure><img src="image_6.png" /><figcaption>Figure 3. Multi-core with local SPM (e.g. AURIX)</figcaption></figure>

<figure><img src="image_7.png" /><figcaption>Figure 4. Eyeriss architecture</figcaption></figure>

Another example is the FPGA-based accelerator, named TMMA (see Figure 5), of [15] featuring matrix multiplications. It means that convolutions are translated into matrix multiplication operations and more precisely block GeMM (General Matrix Multiplication) algorithm. Practically, to perform $C = A \times B + C$, the matrices are sliced into tiles and the intermediate results are accumulated. It means that such operation is performed in several computation steps. Our formalism can be applied to this architecture by considering the BRAM as the on-chip memory, the DRAM as the off-chip memory and the computation as a matrix multiplication (we do not model the sub-decomposition into tiles). However, we cannot use our detailed strategies (heuristic or those found with the ILP solver) because convolutions are translated into matrix operations. We need to slightly adapt our ILP problem.

<figure><img src="image_8.png" /><figcaption>Figure 5. TMMA architecture</figcaption></figure>

The VTA (Versatile Tensor Accelerator) [18, 6] illustrated in Figure 6 has been designed to accelerate convolutions with ALU and GeMM-based operations. It is a kind of generalization of the TMMA as the user can access VTA instructions and data addresses in the on-chip memory (making it versatile). Our formalism can be applied to this architecture as it contains a DRAM, an on-chip memory, and a processing part. However, the strategies, as for the TMMA, must be adapted. The list of applicable accelerators is not exhaustive, but we see that convolution can be modeled as strategies for a large range of accelerators.

## 1.4. Outline

The remainder of this paper is organised as follows: Section 2 introduces our model for formulating a strategy. Section 3 defines the method to decompose a convolution into slices. Building on this formalism, Section 4 presents the formalisa-
<figure><img src="image_9.png" /><figcaption>Figure 6. VTA architecture</figcaption></figure>

tion of the strategy for S1 and its extended version. Section 5 then formulates the associated optimisation problem. Section 6 describes the design and Python implementation of the simulator. Finally, Section 7 presents the experimental results and Section 8 provides a review of the related work.

## 2. SYSTEM MODEL – PROPOSED FORMALISM

Our system model comprises a platform model (CPU, accelerator, on-chip memory, and DRAM) and an application model that details the computation steps required to execute any application (e.g. convolution layer).

### 2.1. Platform model

The considered accelerator is capable of nbop<sub>PE</sub> MAC operations per $t_{acc}$ cycles. The on-chip memory has a size $size_{MEM}$. When dealing with memory or data size, we omit the unit (e.g. MB, GB) and only deal with integers that are all expressed in the same unit. We assume the DRAM is large enough to contain all the data required to execute the application (a convolution layer in our case). All durations are expressed in the number of accelerator cycles. We assume that the duration to free parts of the on-chip memory is negligible. We also assume that the duration to load data from the DRAM to the on-chip memory (resp. to write back data from the on-chip memory to the DRAM) is proportional to the size of the data.

We denote the duration to load one element from the DRAM to the on-chip memory by $t_l$ and the duration to write back one element from the on-chip memory to the DRAM by $t_w$.

### 2.2. Application model: Steps and actions

The on-chip memory size is rarely sufficient to store all the data required to compute a convolution layer. As a consequence, the computation is performed in several steps.

**Assumption 1** The on-chip memory is abstracted as a mathematical set, equipped with the set operations: intersection $\cap$, union $\cup$, set difference $\setminus$ and cardinal $||$.

**Definition 1 (n-step computation)** A n-step computation $S = (s_1, ..., s_n)$ is defined as an ordered execution of steps $s_i$

$$s_i = (F_i^{\text{inp}}, F_i^{\text{ker}}, W_i, I_i^{\text{slice}}, K_i^{\text{sub}})$$

where $F_i^{\text{inp}}, F_i^{\text{ker}}, W_i, I_i^{\text{slice}},$ and $K_i^{\text{sub}}$ correspond, respectively, to the subset of input part to be freed from the on-chip memory, the subset of kernels to be released from the on-chip memory, the subset of output data to be written back to the DRAM, the subset input slice loaded from the DRAM to the on-chip memory, and the subset of kernels loaded from the DRAM to the on-chip memory.

**Definition 2 (Semantics of a n-step computation)** Each step

$s_i = (F_i^{\text{inp}}, F_i^{\text{ker}}, W_i, I_i^{\text{slice}}, K_i^{\text{sub}})$ is a sequence of actions. Actions $s_i = (a_1, a_2, a_3, a_4, a_5, a_6)$ and results in a new on-chip memory state $M_i = [M_i^{\text{inp}}, M_i^{\text{ker}}, M_i^{\text{out}}]$ where $M_i^{\text{inp}}, M_i^{\text{ker}}$ and $M_i^{\text{out}}$ correspond, respectively, to the input part, the kernels, and the results that are stored at the end of step $s_i$ in the on-chip memory. We suppose that the on-chip memory is initially empty, thus $M_0^{\text{inp}} = \emptyset$, $M_0^{\text{ker}} = \emptyset$ and $M_0^{\text{out}} = \emptyset$. We use temporary variables $M_i^{\text{inp}}, M_i^{\text{ker}}$ and $M_i^{\text{out}}$ to represent the evolution of the memory. Practically, a step works as follows:

1. $a_1$ removes the input slice $F_i^{\text{inp}}$ from on-chip memory, leading to $M_i^{\text{inp}} = M_{i-1}^{\text{inp}} \setminus F_i^{\text{inp}}$;

2. $a_2$ removes parts of the kernels $F_i^{\text{ker}}$ from on-chip memory, leading to $M_i^{\text{ker}} = M_{i-1}^{\text{ker}} \setminus F_i^{\text{ker}}$;

3. $a_3$ writes back the computed values $W_i$ in the DRAM, leading to $M_i^{\text{out}} = M_{i-1}^{\text{out}} \setminus W_i$.

4. $a_4$ an input slice $I_i^{\text{slice}}$ is loaded from the DRAM to the on-chip memory. Thus, at this moment, the on-chip memory contains the parts of the input $M_i^{\text{inp}} = M_i^{\text{inp}} \cup I_i^{\text{slice}}$. Indeed, we may keep some input parts in the on-chip memory for further steps and $M_i^{\text{inp}}$ represents what was still in the on-chip memory after the action $a_1$;

5. $a_5$ a subset of kernels $K_i^{\text{sub}}$ is loaded from the DRAM. At this moment, the on-chip memory contains the parts of the kernels $M_i^{\text{ker}} = M_i^{\text{ker}} \cup K_i^{\text{sub}}$. Indeed, we may keep some kernels in the on-chip memory for further steps, and $M_i^{\text{ker}}$ represents what was still in the on-chip memory after the action $a_2$.

6. $a_6$ the computation is made. Once the computation is finished, the result of this computation $Out_i$ is stored in the on-chip memory, leading to $M_i^{\text{out}} = M_i^{\text{out}} \cup Out_i$. Indeed, we assume that not all results are written back after a step;

Some sets may be empty (e.g. $I_i^{\text{slice}}, K_i^{\text{sub}},$ ...). After the very last step $s_n$ the on-chip memory has to be empty and the results have to be written back.

**Definition 3 (Duration of an n-step strategy)** The duration of one step $s_i$ is a function $f$ of $I_i^{\text{slice}}, W_i$ and $K_i^{\text{sub}},$ i.e. $\delta(s_i) = f(I_i^{\text{slice}}, W_i, K_i^{\text{sub}})$. Thus, the duration of an n-step strategy is $\delta = \sum_{i=1}^{n} \delta(s_i) = \sum_{i=1}^{n} f(I_i^{\text{slice}}, W_i, K_i^{\text{sub}})$

We assume that the duration is proportional to the size of the data involved, we can compute at any time the size (in the expected unit) of the data stored in the on-chip memory using the cardinal function of a set of data (or a memory). Thus:

* the duration of a step $s_i$, $\delta(s_i) =$

$$((|I_i^{\text{slice}}| + |(K_i^{\text{sub}})|) \times t_l + |(W_i)| \times t_w + t_{acc})$$

* the size of data stored in the on-chip memory during $s_i$:

$$size_i^{\text{step}} = |M_{i-1}^{\text{inp}} \cup I_i^{\text{slice}}| + |M_{i-1}^{\text{ker}} \cup K_i^{\text{sub}}| + |M_{i-1}^{\text{out}} \cup Out_i|$$

### 2.3. Assumptions

We consider the same assumptions as the paper [23] that are the following:
* Each input and kernel must be loaded into the on-chip memory from the DRAM a bounded number of times. Indeed, the higher the number, the higher the memory exchange (and possibly the higher the duration). Subsequently, we fix this number to at most twice;

* The data loaded in the on-chip memory has to be directly processed by the accelerator. This ensures to not waste memory or in other word, the on-chip memory is sized to contain data that could be computed immediately.

* The compute action must consume all the inputs and kernels parts stored in the on-chip in a unique execution. Thus, the number of operations to be done in a step must be lower than the number of operations provided by PE, i.e. nbop<sub>PE</sub>.

### 3. REPRESENTING THE SLICES FOR CONVOLUTIONS

The purpose of this section is to remind how convolutions are computed and how they can be decomposed into slices for off-floating part of them on the accelerator.

#### 3.1. Reminder on convolutions

In general, convolutional layers manipulate tensors in order to represent input and output data, as well as kernels.

**Definition 4 (Tensor)** A tensor T is a multi-dimensional array defined as:

$$T \in \mathbb{R}^{n_1 \times n_2 \times \dots \times n_k}$$

We denote by $T_{i_1, i_2, \dots, i_k}$ the value of the tensor at indices $(i_1, i_2, \dots, i_k) \in [0, n_1 - 1] \times [0, n_2 - 1] \times \dots \times [0, n_k - 1]$.

**Definition 5 (2D convolution operation)** A 2D convolution operation is a function $f_c$ defined :

$$f_c : \mathbb{R}^{C_{in} \times H_{in} \times W_{in}} \times (\mathbb{R}^{C_{in} \times H_{K} \times W_{K}})^N \rightarrow \mathbb{R}^{N \times H_{out} \times W_{out}} \\ (I, \Lambda) \mapsto O \qquad (1)$$

The function $f_c$ computes the cross-correlation between the input tensor I and the kernel set $\Lambda$ according to the strides and the paddings.

**Remark 1** Note that, although it is called a 2D convolution layer, it takes 3D input because the '2D' refers to the kernel, which moves along two spatial axes on the input ($H_{in}$ and $W_{in}$).

**Definition 6 (3D-Input tensor)** A 3D-input tensor I ∈ $\mathbb{R}^{C_{in} \times H_{in} \times W_{in}}$ is of dimension $C_{in}$ channels, $H_{in}$ height and $W_{in}$ width.

A 2D-convolution is parametrized by a set of N kernels $K^i$.

**Definition 7 (Kernels)** $\Lambda = \{K^0, K^1, \dots, K^{N-1}\}$ with $K^i$ $i^{th}$ kernel tensor of a convolution layer : $\forall i \in [0, N-1]$, $K^i \in \mathbb{R}^{C_{in} \times H_{K} \times W_{K}}$, wherein $C_{in}$, $H_{K}$ and $W_{K}$ represent respectively the channel, the height and the width dimensions of the $i^{th}$ kernel tensor. All the kernels in $\Lambda$ share the same dimensions.

A 2D-convolution computes a 3D output tensor

**Definition 8 (3D-Output tensor)** A 3D-output tensor $O \in \mathbb{R}^{C_{out} \times H_{out} \times W_{out}}$ is of dimension $C_{out}$ channels, $H_{out}$ height and $W_{out}$ width. Those dimensions depend on the input dimension, the kernels size, the stride $s_w$ along the width dimension, the stride $s_h$ along the height dimensions, the padding $p_r$, $p_l$, $p_t$, $p_b$ respectively the right, left, top and bottom. We have:

$$C_{out} = N \\ H_{out} = \lfloor \frac{H_{in} - H_{K} + (p_{t} + p_{b})}{s_{h}} \rfloor + 1 \\ W_{out} = \lfloor \frac{W_{in} - W_{K} + (p_{l} + p_{r})}{s_{w}} \rfloor + 1$$

**Remark 2** For the sake of clarity, in the remainder of this paper, we assume that the input I is already padded when necessary

The output tensor value is given $\forall (l, i, j) \in [0, C_{out} - 1] \times [0, H_{out} - 1] \times [0, W_{out} - 1]$ by:

$$O_{l,i,j} = \sum_{c=0}^{C_{in}-1} \sum_{h=0}^{H_{K}-1} \sum_{w=0}^{W_{K}-1} I_{c,i \times s_h+h,j \times s_w+w} \times K_{c,h,w}^{l}$$

This equation shows that the computation of each output value is independent of the others, meaning their computation order does not impact the output result. Consequently, sequencing the execution into independent steps on the accelerator is possible, as long as the slicing is adequate.

For the remainder of this paper, we will write the convolution operation as *.

#### 3.2. Slicing of convolution

In this section, the concept of slicing a tensor is defined, and we consider the particular case of slicing the 3D-Input tensor in a way to compute one output element.

**Definition 9 (Tensor slice)** Let T be a kD-tensor. A slice $S \in \mathbb{R}^{l_1, \dots, l_k}$ of T is a kD-tensor with $a_i, b_i \in [0, n_i - 1]$ such that $b_i \ge a_i$, $l_i = (b_i - a_i)$ and $\forall (i_1, \dots, i_k) \in [0, l_1 - 1] \times \dots \times [0, l_k - 1]$, $S_{i_1, i_2, \dots, i_k} = T_{i_1 + a_1, i_2 + a_2, \dots, i_k + a_k}$.

The slice of the input tensor involved in computing one output element is called a *patch*.

**Definition 10 (Patch)** Consider a convolution layer with an input tensor I ∈ $\mathbb{R}^{C_{in} \times H_{in} \times W_{in}}$. Let us denote $\alpha_h^i$ and $\alpha_w^j$ as $\alpha_h^i = s_h \times i$ and $\alpha_w^j = s_w \times j$. The patch $P_{i,j}$ involved in the computation of the output elements $O_{l,j,i}$ with $l \in [0, C_{out} - 1]$ is defined by:

$$P_{i,j} = \{I_{j_1, j_2, j_3} | \forall (j_1, j_2, j_3) \in [0, C_{in} - 1] \times [\alpha_h^i, \alpha_h^i + H_K] \times [\alpha_w^j, \alpha_w^j + W_K]\}$$

**Example 1 (Patches of a convolution layer)** We consider a convolution layer composed of an input tensor I ∈ $\mathbb{R}^{2 \times 5 \times 5}$, a kernel subset $\Lambda = \{K^0, K^1\}$ with $K^i \in \mathbb{R}^{2 \times 3 \times 3}$. The strides of the convolution are set as follows $s_h = s_w = 1$.

Figure 7 illustrates three different patches of the input image.
<figure><img src="image_10.png" /><figcaption>Figure 7. Example of patches</figcaption></figure>

The patch on the left corresponds to $P_{0,0}$, the patch in the centre to $P_{1,1}$, and the patch on the right to $P_{2,2}$.

**Definition 11 (Set of patches)** The set of patches is defined as $X = \{P_{0,0}, P_{0,1}, ..., P_{H_{out}-1, W_{out}-1}\}$, X encompasses all the patches necessary to compute a convolution layer.

**Remark 3** We consider that $X$ is the set of patch identifiers and a patch, when manipulated (e.g., to define the slices), is a set of input values.

# 4. STRATEGY FORMALIZATION

The work of [23] has proposed four strategies and we selected one of them, denoted S1-baseline, that offers very interesting settings. We encode this baseline with our strategy formalisation and propose an improvement to to minimise the duration $\delta$.

## 4.1. S1-baseline formalization

Figure 8 shows an example of a step of S1-baseline. During the first step, all the kernels are loaded into the on-chip memory and they remain there until the last step.

**Assumption 2** At each step, one patch of the input is loaded.

The strategy requires $n = |X| = H_{out} \times W_{out}$ steps to compute a convolution.

<figure><img src="image_11.png" /><figcaption>Figure 8. S1-baseline</figcaption></figure>

Let us formalise the strategy S1-baseline with our definition 1.

**Definition 12 (n-step computation of S1-baseline from [23])** Each step consists of computing the convolution of a patch with all kernels. A step $s_i = (F_i^{inp}, F_i^{ker}, W_i, I_i^{slice}, K_i^{sub})$ is defined as follows.

* $I_i^{slice}, F_i^{inp}$: we have $I_1^{slice} = P_{k_1,l_1}$ where $P_{k_1,l_1} \in X$ is one patch. Let us denote by $X_i^{done}$ the set of patches already computed until step $i$. We have $X_1^{done} = \{P_{k_1,l_1}\}$. Then, for $i > 1$, we have $I_i^{slice} = P_{k_i,l_i} \setminus M_{i-1}^{inp}$ where $P_{k_i,l_i} \in X \setminus X_{i-1}^{done}$ is a patch not treated. $X_i^{done} = X_{i-1}^{done} \cup \{P_{k_i,l_i}\}$. $F_i^{inp} = M_{i-1}^{inp} \setminus P_{k_i,l_i}$.

* $K_i^{sub}, M_{ker}^i, F_i^{ker}$: All the kernels are loaded into the on-chip memory during the first step and never free until the last step. Thus, $K_{sub}^1 = \Lambda$ and $K_{sub}^i = \emptyset$ for $i > 1$. We also have $M_{ker}^i = \Lambda$ for $i < n$, $F_n^{ker} = \Lambda$ and $F_i^{ker} = \emptyset$ for $i < n$.

* In S1-baseline we do not know when the output elements are stored in the DRAM, and this means we do not know for each step the value of $W_i$.

As reflected in the previous definition, the authors of [23] do not specify 1) the order in which the patches are loaded into the on-chip memory; 2) how and when data are freed and 3) when the computed values are stored back into the DRAM.

In addition, the choice of loading one patch per step is not optimal as it does not account for the accelerator computational capacity. Let us compute the number of operations needed to compute one output value.

**Definition 13 (One output value demand)** Let $O_{l,i,j}$ be an output value of the output tensor $O$, the number of MAC operations required to compute $O_{l,i,j}$ is:

$$nb\_op\_value = C_{in} \times H_K \times W_K$$

We need to compute the number of operations performed for one patch when complying with the S1-baseline assumptions.

**Property 1 (Number of operations for S1-baseline)** In the assumptions, all kernels are loaded into the on-chip memory, thus for a step of S1-baseline, the output values of all output channels are computed. The number of operations performed in one S1-baseline step is: $nb\_op\_value \times C_{out}$.

## 4.2. S1 formalization

We propose to transform S1-baseline into an optimal strategy S1 that shares the assumptions of S1-baseline and those listed in section 2.3. This entails that we want 1) to compute an ideal order but also 2) to load as many patches as the accelerator can handle (up to $nbop_{PE}$ operations).

Thus, in S1, the maximal number of patches that need to be loaded into the on-chip memory is

$$nb\_patches\_max\_S1 = \lfloor \frac{nbop_{PE}}{nb\_op\_value \times C_{out}} \rfloor$$

**Definition 14 (Minimal number of steps $K_{min}$ for S1)** Let $K_{min}$ be the minimal number of steps required to process the convolution layer. A step can handle at most $nb\_patches\_max\_S1$ patches, which means $K_{min} = \lfloor \frac{|X|}{nb\_patches\_max\_S1} \rfloor$.

**Definition 15 (Minimal number of steps $K_{max}$ for S1)** Let $K_{max}$ be the maximum number of steps required to process the convolution layer. A step handles at least one patch, which means $K_{max} = |X|$.

Therefore, the number of steps to perform the convolution with S1 is $n \in \llbracket K_{min}, K_{max} \rrbracket$.

**Example 2 (Row-by-Row VS ZigZag strategies)** We consider the same convolution layer as in example 1. The accelerator is capable of $nbop_{PE} = 120$ MAC operations. Thus, the maximum number of patches that can be processed in a step is $nb\_patches\_max\_S1 = 2$. Figure 9 shows two strategies (Row-by-Row and ZigZag) for computing the convolution layer in multiple steps, in these strategies we assume that each output result is written back at the next step. Let us use our formalism to compare both strategies in the second step:
* $F_2^{inp}_Row = \{I_{0,0,0}, I_{1,0,0}, I_{0,0,1}, I_{1,0,1}\}$
  $F_2^{inp}_ZigZag = \{I_{0,0,0}, I_{1,0,0}, I_{0,0,1}, I_{1,0,1}, I_{0,1,0}, I_{1,1,0}, I_{0,1,1}, I_{1,1,1}, I_{0,2,0}, I_{1,2,0}, I_{0,2,1}, I_{1,2,1}\}$

* $F_2^{ker}_Row = F_2^{ker}_ZigZag = \emptyset$

* $W_2\_Row = W_2\_ZigZag = \{O_{0,0,0}, O_{1,0,0}, O_{0,1,0}, O_{1,1,0}\}$

* $I_2^{slice}_Row = \{I_{0,0,4}, I_{1,0,4}, I_{0,1,4}, I_{1,1,4}, I_{0,2,4}, I_{1,2,4}, I_{0,3,0}, I_{1,3,0}, I_{0,3,1}, I_{1,3,1}, I_{0,3,2}, I_{1,3,2}\}$
  $I_2^{slice}_ZigZag = \{I_{0,0,4}, I_{1,0,4}, I_{0,1,4}, I_{1,1,4}, I_{0,2,4}, I_{1,2,4}, I_{0,3,4}, I_{1,3,4}, I_{0,3,3}, I_{1,3,3}, I_{0,3,2}, I_{1,3,2}\}$

* $K_2^{sub}_Row = K_2^{sub}_ZigZag = \emptyset$

Moreover, the memory footprint due to the input for each strategy is: $M_2^{inp}_Row = 32$ and $M_2^{inp}_ZigZag = 24$. Finally, we can express the duration of the second step for each step using our duration defined in Section 2. The size function in this case is the cardinal of a set. Thus, $\delta(s_2\_Row) = (|I_2^{slice}_Row| + |K_2^{sub}_Row|) \times t_l + |W_2\_Row| \times t_w + t_{acc} = 6 \times t_l + 2 \times t_w + t_{acc}$ and in the same way $\delta(s_2\_ZigZag) = 6 \times t_l + 2 \times t_w + t_{acc}$.

Example 2 demonstrates that the order in which patches are computed affects data reuse, traffic between the on-chip memory and DRAM, and the input memory footprint. Therefore, the order of computation is an important factor to consider.

<figure><img src="image_12.png" /><figcaption>Figure 9. Example of two different strategies generated by the simulator described in Section 6</figcaption></figure>

**Definition 16 (n-step strategy of S1)** Each step involves computing a group of patches, $g_i$, where the index $i$ corresponds to the step at which this group is processed. Practically, to

determine the group $g_i$, the set $X$ is partitioned into $n$ partitions, each partition corresponds to a group $g_i$. Thus $G = \{g_0, g_1, ..., g_n\}$ where $g_0 = \emptyset$.

A step $s_i = (F_i^{inp}, F_i^{ker}, W^i, I_i^{slice}, K_i^{sub})$ is defined as follows:

* $I_i^{slice}, F_i^{inp}$: we have $I_1^{slice} = g_1$ Then, for $i > 1$,

$$ 
\begin{aligned}
I_i^{slice} &= \bigcup_{P_{i,j} \in g_i} P_{i,j} \setminus M_{inp}^{i-1} \\
F_{inp}^i &= M_{i-1}^{inp} \setminus \bigcup_{P_{i,j} \in g_i} P_{i,j}
\end{aligned}
$$

* $K_i^{sub}, M_i^i, F_i^{ker}$: All the kernels are loaded into the on-chip memory during the first step and never free until the last step. Thus, $K_1^{sub} = \Lambda$ and $K_i^{sub} = \emptyset$ for $i > 1$. We also have $M_i^{ker} = \Lambda$ for $i < n$, $F_n^{ker} = \Lambda$ and $F_i^{ker} = \emptyset$ for $i < n$.

## 5. OPTIMIZATION PROBLEM ASSOCIATED WITH S1

In this section, we describe how we formulate our optimization problem to find an optimal strategy which respects our constraints and assumptions.

**Remark 4** The row-major order is used to linearise the indices of the two-dimensional patch into a one-dimensional index. This simplification makes it easier to express the decision variables and constraints in a format that is more suitable for the solver.

**Remark 5** The channel-major order is used to linearise the indices of the three-dimensional pixel into a one-dimensional index. This simplification makes it easier to express the decision variables and constraints in a format that is more suitable for the solver.

<table><caption>Table 1. Variable description</caption><thead><tr><td>Variable</td><td>Description</td></tr></thead><tbody><tr><td>pxl_in_P</td><td>Pixel-to-patch assignment</td></tr><tr><td>P_g</td><td>Patch-to-group assignment</td></tr><tr><td>pxl_g</td><td>Pixel-to-group assignment</td></tr><tr><td>pxl_ovlp</td><td>Presence of a pixel in a group</td></tr><tr><td>pxl_I</td><td>Presence of a pixel in I<sup>slice</sup></td></tr><tr><td>nb_pxl_ovlp</td><td>Pixels in commons between g<sub>i</sub> et g<sub>i+1</sub></td></tr></tbody></table>

### 5.1. Problem constants

In this section, we define the necessary constants to model the optimization problem. The parameters defined in the previous sections, such as the convolution parameters, are also employed throughout this section. To represent the belonging of a pixel to a patch, we define the set:

$pxl\_in\_P = \{(i, j) | j \in P_i\}$. This set allows us to model the overlapping between patches and groups. Another constant that we need to define is $nb\_data\_reload$ which represents the assumption that each input element and kernel element must be loaded into the on-chip memory from the DRAM a bounded number of times.

**Remark 6** In the definition of pxl\_in\_P, we do not take into account the channel dimension. Indeed, to reduce the number of variables, we can work on a 2D tensor when we define the pixels because we do not slice along the channel dimension.
**Example 3** We consider the same convolutional layer as in Example 1. In this example, there are nine patches and 50 pixels. However, as mentioned in Remark 6, we do not consider the channel dimension. Therefore, the number of pixels is 25. In this example, therefore, pxl_in_P is defined as follows: $pxl\_in\_P = \{(0, 0), (0, 1), (0, 2), (0, 5), (0, 6), (0, 7), (0, 10), (0, 11), (0, 12),...(8, 24)\}$

## 5.2. Decision variables with associated constraints

In this section, we define the necessary decision variables and constraints to model the optimization problem.

### 5.2.1. Patches mapping

The binary decision variable $P_g \in \{0, 1\}$ represents the presence of a patch $P_i$ in the $k^{th}$ group. The variable $P_g_{i,k}$ is defined as follows:

$$P_g_{i,k} = \begin{cases} 1 & \text{if } P_i \in g_k \\ 0 & \text{otherwise} \end{cases} \qquad (2)$$

In this strategy, a patch must be assigned to a single group. Therefore, the sum of $P_g$ over the number of groups must be equal to one.

$$\forall i \in [0, H_{out} \times W_{out} - 1], \sum_{k=0}^{K_{max}} P_g_{i,k} = 1 \quad (3)$$

Moreover, the cardinality of a group cannot exceed the maximum number of patches defined by $nb\_patches\_max\_S1$. This is because $nb\_patches\_max\_S1$ is defined as the maximum number of patches that the accelerator can process in one step, so each group cardinal must be less than or equal to $nb\_patches\_max\_S1$.

$$\forall k \in [0, K_{max}], \sum_{i} P_g_{i,k} \le nb\_patches\_max\_S1 \quad (4)$$

### 5.2.2. Pixels mapping

The binary decision variable $pxl\_g \in \{0, 1\}$ represents the presence of a pixel $j$ in the $k^{th}$ group. This decision variable is induced by the choice of $P_g$. The variable $pxl\_g_{j,k}$ is defined as follows:

$$pxl\_g_{j,k} = \begin{cases} 1 & \text{if } pixel_j \in g_k \\ 0 & \text{otherwise} \end{cases} \qquad (5)$$

The constraint that induces the value of $pxl\_g$ according to $P_g$ is defined as follows:

$$pxl\_g_{j,k} = \bigvee_{i \in |X|} P_g_{i,k} \qquad (6)$$

This constraint is not linear due to the OR operation, but it can be linearised using well-known techniques [17].

### 5.2.3. Pixel overlapped

The binary decision variable $pxl\_ovlp \in \{0, 1\}$ represents the presence of a pixel $j$ in the $k^{th}$ group and $(k - 1)^{th}$ group. This decision variable is induced by the choice of $P_g$. The variable $pxl\_ovlp_{j,k}$ is expressed as follows:

$$pxl\_ovlp_{j,k} = \begin{cases} pxl\_g_{j,k} \wedge pxl\_g_{j,k-1} & \text{if } k \ge 1 \\ 0 & \text{otherwise} \end{cases} \qquad (7)$$

The AND operator can also be linearised using well-known techniques [17].

### 5.2.4. Pixel in $I_{slice}$

The binary decision variable $pxl\_I \in \{0, 1\}$ represents the presence of a pixel $j$ in the $k^{th}$ slice of the input ($I_{slice}^k$). This decision variable is induced by the choice of $P_g$. The variable $pxl\_I_{j,k}$ is expressed as follows:

$$pxl\_I_{j,k} = pxl\_g_{j,k} \wedge \neg pxl\_ovlp_{j,k} \qquad (8)$$

Using this decision variable, we can express the constraint that each input element and kernel element must be loaded into the on-chip memory from the DRAM a bounded number of times.

$$\sum_k pxl\_I_{j,k} \le nb\_data\_reload \qquad (9)$$

## 5.3. Decision expressions with associated constraints

To simplify the expression of our optimisation problem, we introduce decision expressions to make the model more readable and to define useful variables.

### 5.3.1. Number of pixels that overlap between two consecutive groups

The decision expression $nb\_pxl\_ovlp \in \mathbb{N}$ represents the number of pixels in common between two consecutive groups and is defined as follows:

$$nb\_pxl\_ovlp_k = \sum_{j=0}^{C_{in} \times H_{in} \times W_{in} - 1} pxl\_ovlp_{j,k} \qquad (10)$$

### 5.3.2. Size of a group

The decision expression $size\_group \in \mathbb{N}$ represents the number of pixels in a group and is defined as follows:

$$size\_group_k = \sum_{j=0}^{C_{in} \times H_{in} \times W_{in} - 1} pxl\_g_{j,k} \qquad (11)$$

Now, we can express the constraint that ensures that the data in the on-chip memory fit at any given step. The constraint is defined as follows:

$$\forall k \in [0, K_{max}], size\_group_k + C_{out} \times C_{in} \times H_K \times W_K + \sum_{i} P_g_{i,k} \times C_{out} \le size_{MEM} \qquad (12)$$
The first, second and last terms respectively represent the memory footprint due to input, kernels and computed output.

### 5.3.3. Size of $I_{slice}^k$

The decision expression $size_{slice} I_{slice}^k \in \mathbb{N}$ represents the number of pixels to load in the on-chip memory in step k :

$$size_{slice} I_{slice}^k = \sum_j pxl_I_{j,k} \quad (13)$$

### 5.4. Objective function

Our goal is to minimize the duration of executing an n-step strategy defined in Definition 3. Thus, our objective function is as follows:

$$\delta^* = \min_{I_i^{slice}, W_i, K_i^{sub}} \left( \sum_{i=1}^{n} f(I_i^{slice}, W_i, K_i^{sub}) \right) \quad (14)$$

However, we use the duration proportional to the data size defined in Section 2. Moreover, in this optimisation, we are dealing with S1, meaning that all the kernels are in the on-chip memory. This allows us to assume that the kernels are preloaded in the on-chip memory and that the duration for loading them is not taken into account. Furthermore, we assume that at each step, the computed result is written back into the DRAM, meaning that it is not taken into account in the objective function. Thus, the objective function can be written as follows in this case:

$$\delta^* = \min_{I_i^{slice}} (t_l \times \sum_{i=1}^{n} size(I_i^{slice}) + n \times t_{acc}) \quad (15)$$

## 6. SIMULATOR DESIGN AND IMPLEMENTATION

<figure><img src="image_13.png" /><figcaption>Figure 10. Diagram of the simulator</figcaption></figure>

Based on the formalism of section 2 we have implemented a Python-based simulator that enables a user-defined strategy to be executed on a generic accelerator architecture. This simulator enables users to compare different strategies and visualise the execution of convolutions. Figure 9 is an example of a visualisation from the simulator. The simulator inputs are: the convolution layer description (stride, layer dimensions, kernel dimensions, number of kernels and the padding) and the data necessary to compute (input tensor and the kernel tensors). It also requires the hardware description (DRAM size, on-chip memory size and accelerator compute capacity) and a strategy that is user-defined or from an ILP solver CSV file. The outputs of the simulator are: a step-by-step execution, a visualisation of the step-by-step strategy, assessment of different

metrics (duration and the memory footprint) and a functional simulation that can assess if the result of the step-by-step convolution is correct. Figure 10 shows the main building blocks of the simulator. The simulator is implemented in Python and composed of several classes. First, the system acts as an orchestrator, providing instructions to the other classes at each step from the strategy instance; 1) reads the current step from the strategy, 2) frees the unnecessary elements in the on-chip memory, 3) writes the results to the DRAM, 4) loads the necessary elements from DRAM to on-chip memory, 5) triggers the accelerator to perform the computation 6) loops to 1). The classes that simulate the hardware are: the accelerator class that implements the on-chip memory and computation part and the DRAM class that implements the off-chip memory. The convolution layer class contains all the parameters and data (patches, pixels and kernels) required for computation. The strategy class implements the sequence of user-defined steps. The simulator will be available open-source on GitHub.

# 7. EXPERIMENTATIONS

## 7.1. Experimental Setup

We implemented the ILP formulation in the Optimization Programming Language (OPL) and solved it with the IBM CPLEX Optimizer (v22.1) [9]. All experiments were run on a 24-core Intel(R) Xeon(R) CPU E5-2420 0 @ 1.90GHz.

### OPL setup:

* We set the OPL solver timeout to between 0.5 and 5h.

* We use the MIP Start functionality to reduce the solving time and guide the solver toward the optimal solution. This allows us to initialize the decision variables with a feasible starting point. Specifically, we inject a solution from either the ZigZag or Row-by-Row strategy, depending on which was best for the given convolution parameters.

* We use the Solution Polishing feature, which switches the solver's strategy from the Branch-and-Cut algorithm to a genetic algorithm, enabling faster convergence towards an optimal solution. As we provide a feasible initial solution, we have configured this switch to occur after 60 seconds of computation.

* We constrain the search space to a number of groups equal to $K_{min}$ instead of the upper bound $K_{max}$ which leads to a sub-optimal solution. This choice was made to ensure that the problem could be solved in a reasonable amount of time. Using $K_{max}$ would lead to a combinatorial explosion as the number of decision variables $N_{var} = K_{max} \times (3 \times (H_{in} \times W_{in}) + H_{out} \times W_{out})$. Therefore, using $K_{min}$ instead of $K_{max}$ drastically reduces the number of groups and reduces the search space.

**Convolution Layers and Hardware Accelerators assessed:**
We evaluated our ILP model on various convolutional layers, adopting the following configuration:

* Fixed parameters: The strides were set to $s_h = s_w = 1$ to maximize data reuse opportunities. The number of kernels was set to 1 as this does not affect the optimization of the S1 strategy, with its dimensions set to $H_K = W_K = 3$.
*   **Layers dimensions:** We evaluate input sizes ($H_{in}, W_{in}$) ∈ $\llbracket 4, 12 \rrbracket \times \llbracket 4, 12 \rrbracket$ and considering that $H_{in} = W_{in}$.

*   **Accelerator computational capacity:** To assess computational impact the parameter `nb patches max S1` (representing the number of patches that can be loaded into the on-chip memory and directly processed by the accelerator) was varied from 2 to 10.

*   **Memory assumptions:** We assume sufficient the on-chip memory to store all kernels, the `nb patches max S1` patches, and the resulting output for each step.

**Metrics:** The metric used to compare the strategies (ZigZag, Row-by-Row, OPL strategy) is the duration $\delta$. We consider the duration, to be linear and use the definition given in Section 2.2. As we are evaluating S1 and considering that each output result is written at each step. Thus the duration for performing the computation of the convolutional layer is $\delta = t_l \times \sum_{i=1}^{n} size(I_i^{slice}) + n \times t_{acc}$, we set $t_l = t_{acc} = 1$. Therefore, the duration is $\delta = \sum_{i=1}^{n} size(I_i^{slice}) + n$.

## 7.2. ZigZag vs Row-by-Row strategies

We compare the ZigZag and Row-by-Row strategies on the convolutional layers of ResNet8 and LeNet-5. All experiments were conducted using the simulator. The Row-by-Row strategy operates by grouping `nb patches max S1` patches sequentially from left to right for every row, as shown in Figure 9. In contrast, the ZigZag strategy organizes the patches by processing even rows from left to right order and odd rows from right to left order, alternating directions, as shown in Figure 9.

<figure><img src="image_14.png" /><figcaption>Figure 11. Comparison of the duration of the first LeNet-5 layer using the ZigZag and Row-by-Row strategies for different group sizes.</figcaption></figure>

The results shown in Figure 11 and other experiments not presented in this work on other convolutional layers demonstrate that the curves have the same shape for ZigZag and Row-by-Row. Secondly, we notice that for small group size, ZigZag outperforms Row-by-Row, whereas after the crossover point the trend reverses. A special case happens for group sizes that are a multiple of $W_{out}$ because ZigZag and Row-by-Row strategies are identical. Our simulator rapidly determines the optimal strategy based on the accelerator's constraints. Furthermore, our experimental results suggest that the crossover point at which Row-by-Row outperforms ZigZag depends on $W_{out}$ and the stride.

## 7.3. ILP Evaluation

We compare the strategies found by the ILP solver against ZigZag, Row-by-Row and S1-baseline from [23].

<figure><img src="image_15.png" /><figcaption>Figure 12. Comparison of the duration for a group size of 4 using the OPL, ZigZag Row-by-Row and S1 strategies for different input sizes.</figcaption></figure>

<figure><img src="image_16.png" /><figcaption>Figure 13. The performance gain between the OPL strategy and the best ZigZag/Row-by-Row strategy.</figcaption></figure>

The results shown in Figure 12 and Figure 13 demonstrate the efficiency of the ILP formulation. Our method finds a strategy that minimizes the duration $\delta$ more efficiently than the other strategies considered. In Figure 13 we observe 2 distinct regions: the upper-right region where is no performance gain (0% ) corresponds to the case where the group size (SG) is larger than the image size. Consequently, filling each group becomes trivial. Therefore, ZigZag and Row-by-Row already give an optimal solution. Conversely, the lower-left region highlights cases where the ILP formulation outperforms other strategies, with performance gain reaching up to 30%.

## 8. RELATED WORK

In related work, CoSA [8] and LEMON [21] propose to address the problem of scheduling DNN layers on generic specialized accelerators featuring a PE array and a multi-level memory hierarchy. To schedule the computation, the authors use a constrained optimization approach to simultaneously solve optimal loop tiling, loop permutation, and spatial mapping in a single pass. The scheduling space is formulated as a prime-factor allocation problem where the solver determines
the optimal allocation of these factors to maximize data reuse and satisfy the memory capacity constraints. Built upon this, LEMON extends the model by considering bandwidths constraints between different memory levels.

At a coarser granularity, COSMA [16] proposes addressing the problem of scheduling DNNs on similar to the generic accelerator architecture we consider but operates at the inter-layer level, considering the layer as the minimal unit, unlike us that optimise within a layer. Their goal is to minimize access to off-chip memory while jointly considering the scheduling of operators, memory allocation, and tensor replacement across the entire DNN graph. Daini et al.[3] propose scheduling the inference of a CNN model on a multicore system with local SPM and shared DRAM. To achieve this, the authors propose an ILP implementation to optimise the allocation of computational and memory operations on each core, while ensuring that real-time constraints are met. As COSMA, they work at a different granularity level compared to us. Indeed, the authors optimise either layer by layer or the complete CNN model. Unlike us, they take into account the contiguity constraint of loading in the local SPM but our formalism enables to model different architectures compared to them.

In addition to ILP methods for scheduling Deep Neural Networks on specialized accelerators, heuristics and meta-heuristics techniques are employed to explore the vast solution space. GAMMA [13] and MEDEA [22] employ genetic algorithms to explore the solution space. Reinforcement learning can also be used for this purpose as demonstrated in [24] [12]. Based on our formalism, we could use these techniques to solve our problem instead of ILP. However, this does not guarantee finding an optimal solution. Another approach to solve this problem is to use gradient-based search methods such as MindMapping [7]. However, this technique is incompatible with our formalism, as it requires the problem to be differentiable, whereas the current problem formulation is mainly discrete.

The most ubiquitous technique to compute convolution is General Matrix Multiplication (GeMM). This technique relies on efficient matrix multiplication (e.g. the Strassen algorithm). The input tensor is transformed into a matrix using the im2col algorithm. A drawback of this technique is that it involves memory overhead as the overlapping elements between patches are duplicated in the input matrix. Moreover, each patch defined in Section 3 corresponds to a distinct column of the input matrix; therefore, our formalism can be adapted to this technique. However, the sequence of steps found by the ILP solver cannot be used, as the input elements are duplicated, meaning there is no opportunity for data reuse. For future work, we plan to adapt both our formalism and our ILP formulation for the GeMM algorithm.

Finally, there exist other techniques for computing convolution other than the classical one [4] [10]. The Fast Fourier Transform (FFT)-based convolution leverages the Fourier transform to project both the input and kernel tensors into the frequency domain. This reduces the number of required operations since convolution in the frequency domain becomes a Hadamard product. However, FFT-based convolution requires the input and kernel tensors to have the same dimensions, which necessitates zero-padding the kernel. Therefore, FFT-

based convolution is only computationally more efficient than other techniques if the kernel size is large, which rarely occurs in state-of-the-art CNNs. In fact, CNNs mainly rely on kernel sizes of 1x1 and 3x3. The second is Winograd-based convolution. Similarly to FFT-based convolution, it projects the tensors into a polynomial basis. Winograd-based convolution is efficient for small kernels (3x3 and 1x1), but becomes unstable numerically as the size of the input and kernel increases.

## 9. CONCLUSION

We proposed a formalism to define a strategy of computation on a generic accelerator. We applied this formalism to a strategy from the literature. We then extended it to take into account the computation capacity of the accelerator. Based on the formalism, we formulated an ILP problem to minimise the duration $\delta$ for computing a convolution while meeting the on-chip memory size constraint. Our results demonstrate that the ILP solution is more efficient than the ZigZag and Row-by-Row strategies. Finally, we developed a Python-based simulator to analyse strategies. This has enabled us to compare the ZigZag and Row-by-Row strategies and to assess the solutions found by the ILP solver.

In future work, we plan to present the formalism and ILP formulation of other offloading strategies that operate at a finer granularity than patches and do not assume that all kernels are stored in on-chip memory during computation. Secondly, in our current model we have completely abstracted the memory organization (assumption 1). To offload a part of the input and have a linear duration, this supposes that the data are packed into the correct order. We plan to provide a more representative memory model similar to the one in [3]. Finally, to address larger model, we plan to find a hybrid solution combining heuristics and ILP.

## ACKNOWLEDGMENT

This work has benefited from the AI cluster ANITI2 funded by the French government through the ANR under the France 2030 program (grant ANR-23-IACL-0002).

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