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# Novel Quadruple Cross-Coupled Memory Cell Designs Protected against Single Event Upsets and Double-Node Upsets

Aibin Yan, Yuanjie Hu, Jun Zhou, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen

► To cite this version:

Aibin Yan, Yuanjie Hu, Jun Zhou, Jie Cui, Zhengfeng Huang, et al. Novel Quadruple Cross-Coupled Memory Cell Designs Protected against Single Event Upsets and Double-Node Upsets. IEEE Access, 2019, 7, pp.176188-176196. 10.1109/ACCESS.2019.2958109. lirmm-02395589

HAL Id: lirmm-02395589

https://hal-lirmm.ccsd.cnrs.fr/lirmm-02395589

Submitted on 29 Oct 2020

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Distributed under a Creative Commons Attribution 4.0 International License
Received October 22, 2019, accepted December 3, 2019, date of publication December 6, 2019, date of current version December 23, 2019.

Digital Object Identifier 10.1109/ACCESS.2019.2958109

# Novel Quadruple Cross-Coupled Memory Cell Designs With Protection Against Single Event Upsets and Double-Node Upsets

AIBIN YAN<sup>1</sup>, JUN ZHOU<sup>1</sup>, YUANJIE HU<sup>1</sup>, JIE CUI<sup>1</sup>, ZHENGFENG HUANG<sup>1,2</sup>, PATRICK GIRARD<sup>1,3</sup>, (Fellow, IEEE), AND XIAOQING WEN<sup>1,4</sup>, (Fellow, IEEE)

Corresponding author: Zhengfeng Huang (huangzhengfeng@139.com)

This work was supported in part by the National Natural Science Foundation of China under Grant 61974001, Grant 61874156, Grant 61674048, Grant 61604001, Grant 61834006, and Grant 61872001, and in part by the Anhui University Doctor Startup Fund under Grant Y040435009.

**ABSTRACT** This paper presents two novel quadruple cross-coupled memory cell designs, namely QCCM10T and QCCM12T, with protection against single event upsets (SEUs) and double-node upsets (DNUs). First, the QCCM10T cell consisting of four cross-coupled input-split inverters is proposed. The cell achieves full SEU tolerance and partial DNU tolerance through a novel feedback mechanism among its internal nodes. It also has a low cost in terms of area and power dissipation mainly due to the use of only a few transistors. Next, based on the QCCM10T cell, the QCCM12T cell is proposed that uses two extra access transistors. The QCCM12T cell has a reduced read-and-write access time with the same soft error tolerance when compared to the QCCM10T cell. Simulation results demonstrate the robustness of the proposed memory cells. Moreover, compared with the state-of-the-art hardened memory cells, the proposed QCCM12T cell saves 28.59% write access time, 55.83% read access time, and 4.46% power dissipation at the cost of 4.04% silicon area on average.

**INDEX TERMS** Double-node upset, memory cell, radiation hardening, single event upset, soft error.

## I. INTRODUCTION

As one of the most extensively used memory devices, *static random access memories* (*SRAMs*) play an increasingly important role in modern circuits and systems. Meanwhile, *SRAM-circuit integration* and *performance in nano-scale CMOS technologies* have significantly improved. However, the aggressive shrinking of transistor feature sizes makes modern advanced *SRAMs* more and more sensitive to soft errors caused by the strike of particles, such as protons, neutrons, heavy ions, electrons, muons, and alpha particles [1]. Soft errors can lead to data corruptions, execution errors, or even system crashes in the worst case [2]. The recent adoption of *FinFET* technologies can reduce the soft error rate at transistor or cell level [3]. However, this feature of

The associate editor coordinating the review of this manuscript and approving it for publication was Tae Hyoung Kim <sup>1</sup>.

FinFET-based circuits does not exempt designers to provide valuable and scalable solutions for soft error tolerance, especially for safety-critical applications in harsh environments. Therefore, *SRAM-circuit reliability* caused by soft errors is still an increasing concern.

In a combinational logic circuit, when a particle strikes a sensitive node in a logic gate, the collected charges may cause a transient pulse, i.e., a *single event transient (SET)*, at the output of the struck logic gate. Subsequently, the SET pulse may propagate through the downstream logic gates arriving at a storage element, and the pulse may be captured, thus leading to invalid value-retention. For a storage module such as a memory cell or a flip-flop, particle strike may result in the state change of a single node, thus leading to a soft error. This is called a *single event upset (SEU)*. However, in modern advanced nano-scale CMOS technologies, the aggressive shrinking of transistor feature sizes can make circuit

<footnote n="1">¹Anhui Engineering Laboratory of IoT Security Technologies, School of Computer Science and Technology, Anhui University, Hefei 230039, China</footnote>

<footnote n="2">²School of Electronic Science and Applied Physics, Hefei University of Technology, Hefei 230009, China</footnote>

<footnote n="3">³Laboratory of Informatics, Robotics and Microelectronics of Montpellier, University of Montpellier/CNRS, 34090 Montpellier, France</footnote>

<footnote n="4">⁴Graduate School of Computer Science and Systems Engineering, Kyushu Institute of Technology, Fukuoka 804-8550, Japan</footnote>
integration higher and circuit node-spacing smaller. As a result, due to charge-sharing, the strike of one particle may simultaneously change the states of two nodes in a storage element, which is called a *double-node upset (DNU)*. SEUs and DNUs may cause storage elements to retain incorrect values, resulting in potential errors and failures in circuits and systems. Therefore, to improve robustness of circuits and systems, there is a strong need for IC designers and manufacturers to perform radiation hardening against SEUs and DNUs.

To tolerate SEUs and/or even DNUs, researchers have proposed a series of latches, flip-flops, and memory cells. The designs in [4]–[7] consider hardening for flip-flops, the designs in [8]–[16] consider hardening for latches, while the other designs in [17]–[26] and the designs proposed in this paper consider hardening for memory cells. The traditional memory cell is called 6T, which consists of six transistors, i.e., two PMOS and two NMOS transistors for retaining values, and two extra NMOS transistors for access operations. Since the 6T cell cannot tolerate SEUs, many radiation hardened memory cells have been proposed to improve robustness. Typical SEU and/or even DNU hardened cells include NASA13T [17], Lin12T [18], RHD12T [19], RH12T [20], QUCC10T [21], and QUCC12T [21]. However, these memory cells still have the following problems.

(1) Most of the existing memory cells suffer from a large silicon area and power dissipation, such as NASA13T [17], Lin12T [18], and RH12T [20]. Moreover, some cells suffer from a large read and write access time, such as NASA13T [17] and QUCC10T [21].

(2) Most of the existing memory cells have not been effectively hardened, since one or more nodes cannot tolerate SEUs, such as NASA13T [17]. Moreover, some memory cells cannot tolerate DNUs, such as Lin12T [18], RHD12T [19], RH12T [20], QUCC10T [21], and QUCC12T [21].

Based on a *radiation hardening by design (RHBD)* approach, this paper first presents a novel and highly reliable Quadruple Cross-Coupled Memory cell, namely QCCM10T. The storage module of the memory cell consists of four interlocked input-split inverters. Since the QCCM10T cell uses a few transistors, it has lower cost in terms of area and power consumption. Due to a special feedback mechanism among the internal nodes of the QCCM10T cell, it effectively tolerates SEUs. To reduce read and write access time, the QCCM12T cell is further proposed. This cell has the same soft error tolerance ability when compared to the QCCM10T cell. Moreover, using two extra access transistors, the QCCM12T cell has smaller overhead in terms of read-and-write access time. Simulation results demonstrate the reliability and low overhead of the proposed memory cells.

The rest of this paper is organized as follows. Section II describes the typical SEU and/or DNU hardened cells. Section III describes the schematics and working principles of the proposed memory cell designs. Section IV presents experimental results and comparison results. Section V concludes the paper.

<figure><img src="image_3.png" /><figcaption>FIGURE 1. Schematic of the traditional 6T cell.</figcaption></figure>

## II. PREVIOUS HARDENED MEMORY CELLS

The schematic of the traditional 6T cell is shown in FIGURE 1. The storage module of the 6T cell consists of a couple of cross-coupled inverters. The 6T cell is widely used because of its simple construction and small area. However, the 6T cell cannot tolerate an SEU. Therefore, many radiation hardened cells have been proposed for reliability improvement. FIGURE 2 shows the schematics of typical hardened memory cells, including the NASA13T [17], Lin12T [18], RHD12T [19], RH12T [20], QUCC10T [21], and QUCC12T [21].

The schematic of the NASA13T cell [17] is shown in FIGURE 2-(a). It can be seen that the NASA13T cell consists of three parts. The upper left part acts as a value storage module with write access transistors N1 and N2. The lower left part is redundant for value protection. The right part is a special read module for reading values. Compared with 6T, NASA13T provides an improved level of protection against SEUs. However, the NASA13T cell is not effectively SEU-hardened since it cannot tolerate SEUs caused by large energy particles.

The schematic of the Lin12T cell [18] is shown in FIGURE 2-(b). The source and drain terminals of access transistors N5 and N6 connect bit lines (BL and BLN) and storage nodes (Q and QN). Moreover, gate terminals (S0 and S1) of cross-coupled transistors P1 and P4 are also storage nodes, which increase the redundancy of nodes for SEU tolerance. The Lin12T cell is completely SEU-hardened, but only one pair of nodes (i.e., <S0, S1>) is DNU-hardened.

The schematic of the RHD12T cell [19] is shown in FIGURE 2-(c). It can be seen that the RHD12T cell is composed of 12 transistors. NMOS transistors N1 and N2 are access transistors that are controlled by word line WL, and output nodes Q and QN are connected to bit lines BL and BLN through transistors N1 and N2, respectively. The storage module of the cell consists of 10 transistors in which P1 to P6 are PMOS transistors and N3 to N6 are NMOS transistors. Due to the special construction of feedback loops, the RHD12T cell is completely SEU-hardened, but only one pair of nodes (i.e., <S0, S1>) is DNU-hardened.

The schematic of the RH12T cell [20] is shown in FIGURE 2-(d). S0, S1, Q, and QN are storage nodes used for keeping values. Consider the status shown in FIGURE 2-(d)
<figure><img src="image_4.png" /><figcaption>FIGURE 2. Schematics of typical hardened memory cells. (a) NASA13T [17]. (b) Lin12T [18]. (c) RHD12T [19]. (d) RH12T [20]. (e) QUCE10T [21]. (f) QUCE12T [21].</figcaption></figure>

as an example (i.e., Q = S1 = 1 and QN = S0 = 0), nodes S0, S1, Q, and QN constitute a feedback loop allowing the cell to keep the stored value effectively. Transistors N1 and N2 split output nodes of two traditional cross-coupled inverters into two nodes (i.e., <Q, QN>), respectively. Moreover, nodes S0 and S1 are connected to gate terminals of transistors N1 and N2 to intercept errors. Similarly to Lin12T and RHD12T, the RH12T cell is completely SEU-hardened, but only one pair of nodes (i.e., <S0, S1>) is DNU-hardened.

The schematic of the QUCE10T cell [21] is shown in FIGURE 2-(e). The QUCE10T cell has four storage nodes A, Q, QN, and B. The cell mainly consists of four cross-coupled input-split inverters, constructing a large error- interceptive feedback loop to robustly retain the stored values. As shown in the FIGURE 2-(e), when Q = 1, nodes A, Q, QN and B constitute a robust feedback loop (A → Q → QN → B → A). The QUCE10T cell is SEU-hardened.

The schematic of the QUCE12T cell [21] is shown in FIGURE 2-(f). It can be seen that the QUCE12T cell uses two extra access transistors with respect to the QUCE10T cell to improve performance. The QUCE12T cell has a reduced read-and-write access time with the same soft-error tolerance ability when compared with the QUCE10T cell.

### III. PROPOSED MEMORY CELL DESIGNS

#### A. SCHEMATIC AND NORMAL OPERATIONS

FIGURE 3 shows the schematic of the proposed Quadruple Cross-Coupled Memory (QCCM10T) cell. From FIGURE 3,

<figure><img src="image_5.png" /><figcaption>FIGURE 3. Schematic of the proposed QCCM10T cell.</figcaption></figure>

it can be seen that the QCCM10T cell is composed of 10 transistors in which P1 to P4 are PMOS transistors and N1 to N6 are NMOS transistors. Transistors N5 and N6 are used for access operations and their gate terminals are connected to word-line WL. BL and BLN are bit-lines. I1, I2, I3, and I4 are storage nodes for keeping values. FIGURE 4 shows the layout of the proposed QCCM10T cell. When WL is high (WL = 1), the access transistors are ON, allowing read/write operations to be executed. When WL is low (WL = 0), the cell keeps the stored values.

The normal operations of the proposed QCCM10T cell are described as follows. Let us first consider the case of
<figure><img src="image_6.png" /><figcaption>FIGURE 4. Layout of the proposed QCCM10T cell.</figcaption></figure>

<figure><img src="image_7.png" /><figcaption>FIGURE 5. Simulation results for normal operations of the proposed QCCM10T cell.</figcaption></figure>

writing 1. Before the normal write operation, owing to the writing circuitry, BL = 1 and BLN = 0. When WL = 1, the operation of writing 1 is executed. Transistors P1, N2, P3, and N4 are ON. Meanwhile, transistors N1, P2, N3, and P4 are OFF, so that the stored value is rightly changed to 1, and the operation of writing 1 is completed. Next, let us consider the case of reading 1. Before the normal read operation, owing to a pre-charge circuitry, the voltages of bit-lines BL and BLN will be set to 1. During the read operation, WL = 1, and access transistors N5 and N6 become ON immediately. Nodes I1, I2, I3, and I4 are keeping the stored values, and the voltage of BL does not change. However, the voltage of BLN decreases due to the discharge operation through N4. BL and BLN are directly connected to a differential sense amplifier, and once the voltage difference between BL and BLN becomes a constant value, the read operation is completed and 1 is read out. Note that, similar scenarios can be observed when writing/reading 0. The simulation results of normal operations of the proposed QCCM10T cell are shown in FIGURE 5. It can be seen that “write 0, read 0, write 1, and read 1” operations are correctly executed.

Next, the fault tolerance principle of the proposed QCCM10T cell is described. For the purpose of illustration,

we consider the case of a 1 being stored in the cell (i.e., I1 = I3 = 1 and I2 = I4 = 0). In the next section, we discuss the SEU-tolerance principle and the DNU-tolerance principle, respectively.

## B. SEU-TOLERANCE PRINCIPLE

The cell state shown in FIGURE 3 is considered for SEU-tolerance analysis. Let us first consider the case where I1 is affected by an SEU. In this case, I1 is temporarily changed to 0 from 1, and hence N2 and N4 are temporarily changed from ON to OFF. Since I3 is not affected (i.e., I3 = 1), P2 and P4 are still OFF. Thus, I2 and I4 still have the same original correct value 0. Thus, N1 is still OFF and P1 is still ON, so that I1 can self-recover from the SEU. Note that the similar SEU self-recovery principle can be obtained when I2 is affected by an SEU.

Let us now describe the case where I3 is affected by an SEU. In this case, I3 is temporarily changed to 0 from 1, and hence P2 and P4 are temporarily changed from OFF to ON. I2 has the value 1 (weak 1) since P2 is temporarily changed from OFF to ON. Since I1 is not affected (i.e., I1 = 1), N2 is still ON and I2 has the value 0 (strong 0). However, the strong 0 of I2 can neutralize the weak 1 and hence I2 is still correct (I2 = 0). Similarly, I4 has the value 1 (weak 1) since P4 is temporarily changed from OFF to ON. Since I1 is not affected (i.e., I1 = 1), N4 is still ON and I4 has the value 0 (strong 0). However, the strong 0 of I4 can neutralize the weak 1 and hence I4 is still correct (I4 = 0). Thus, P3 is still ON and N3 is still OFF, and I3 can self-recover from the SEU.

Let us now describe the case where I4 is affected by an SEU. In this case, I4 is temporarily changed to 1 from 0, and hence N1 and N3 are temporarily changed from OFF to ON. I1 has the value 0 (weak 0) since N1 is temporarily changed from OFF to ON. Since I2 is not directly affected (i.e., I2 = 0), P1 is still ON and I1 has the value 1 (strong 1). However, the strong 1 of I1 can neutralize the weak 0 and hence I1 is still correct (I1 = 1). Thus, N4 is still ON. Similarly, I3 has the value 0 (weak 0) since N3 is temporarily changed from OFF to ON. Since I2 is not directly affected (i.e., I2 = 0), P3 is still ON and I3 has the value 1 (strong 1). However, the strong 1 of I3 can neutralize the weak 0 and hence I3 is still correct (I3 = 1). Since P4 is still OFF, I4 can self-recover from the SEU (N4 is still ON as mentioned above). However, when the striking-particle energy is sufficiently large, I4 will be upset since I1 and I3 can be changed to 0 and P2 and P4 can be ON, so that the stored value of the cell can be flipped. To summarize, the proposed QCCM10T cell exhibits effective SEU self-recovery ability, especially for I1, I2, and I3 when 1 is stored in the cell. Note that the OCCM10T cell exhibits effective SEU self-recovery ability, especially for I2, I3, and I4 when 0 is stored in the cell.

## C. DNU-TOLERANCE PRINCIPLE

The cell state shown in FIGURE 3 is considered for DNU-tolerance analysis. Obviously, the proposed QCCM10T cell has six node pairs, i.e., <I1, I2>, <I1, I3>, <I1, I4>,
<figure><img src="image_8.png" /><figcaption>FIGURE 6. Simulation results for SEU and DNU self-recovery of the proposed QCCM10T cell.</figcaption></figure>

<I2, I3>, <I2, I4>, and <I3, I4>. Let us first describe the case where <I1, I2> is affected by a DNU. In this case, I1 is changed to 0 from 1 and I2 is changed to 1 from 0, and hence P1, P3, N2, and N4 are changed from ON to OFF. I3 and I4 cannot be determined since P3 and N4 are OFF. As time passes, all nodes and transistors cannot self-recover to their original states. In other words, <I1, I2> of the proposed QCCM10T cell cannot self-recover from the DNU. Note that, the similar scenario can be obtained when <I3, I4> is affected by a DNU. Let us now consider the case where <I1, I3> is affected by a DNU. The nodes in the pair are not adjacent considering the layout shown in FIGURE 2, and hence the proposed cell can avoid the occurrence of this DNU. Note that, <I1, I4> and <I2, I4> have the same behavior as <I1, I3>.

Let us now describe the case where <I2, I3> is affected by a DNU. In this case, I2 is temporarily changed to 1 from 0 and I3 is temporarily changed to 0 from 1. Hence, P1 and P3 are temporarily changed from ON to OFF, and P2 and P4 are temporarily changed from OFF to ON. Clearly, N1, N2, N3, and N4 are not directly affected, having their original ON/OFF states. Since I1 = 1, N4 is ON and I4 has the value 0 (strong 0). Meanwhile, since P4 is temporarily changed from OFF to ON, I4 has the value 1 (weak 1). However, the strong 0 of I4 can neutralize the weak 1 and hence I4 is still correct (I4 = 0). Since I1 = 1, N2 is ON and I2 has the value 0 (strong 0). Since P2 is temporarily changed from OFF to ON, I2 has the value 1 (weak 1). However, the strong 0 of I2 can neutralize the weak 1 and hence I2 is still correct (I2 = 0). Obviously, P3 is ON and N3 is OFF, and hence I3 can self-recover from the DNU. In other words, node pair <I2, I3> of the cell can self-recover from the DNU. To summarize, the proposed QCCM10T cell exhibits effective DNU tolerance ability, especially for <I1, I3>, <I1, I4>, <I2, I4>, and <I2, I3>.

FIGURE 6 shows the simulation results for SEU and DNU self-recovery of the proposed QCCM10T cell. As shown in FIGURE 6, when I1 = 1, SEUs were respectively injected on nodes I1, I2, and I3 at 20 ns, 40 ns, and 60 ns. When I1 = 0,

<figure><img src="image_9.png" /><figcaption>FIGURE 7. Schematic of the proposed QCCM12T cell.</figcaption></figure>

SEUs were respectively injected on nodes I2, I3, and I4 at 150 ns, 190 ns, and 250 ns. It can be seen that the proposed QCCM10T cell can self-recover from these injected SEUs. Moreover, a DNU was injected on <I2, I3> at 380 ns as shown in FIGURE 4. It can be seen that the proposed QCCM10T cell can self-recover from the DNU on <I2, I3>. The injection of DNUs on <I1, I3>, <I1, I4>, and <I2, I4> are omitted since DNUs are hardly to happen on these pairs considering the layout of the cell.

In the above simulations, a flexible double-exponential current source model was used to perform all fault injections. The time constant of the rise and fall of the current pulse was set to 0.1 and 3 ps, respectively [26]. The proposed cells are implemented using an advanced 22 nm CMOS library from GlobalFoundries under the room temperature and 0.8V supply voltage. All simulations were performed using Synopsys HSPICE tool.

In order to reduce the read and write access time, the QCCM12T cell is proposed and the schematic of the cell is shown in FIGURE 7. It can be seen that the storage module of QCCM12T is the same as that of QCCM10T. Therefore, the QCCM12T cell has the same soft-error tolerance ability when compared to the QCCM10T cell, i.e., they have the same SEU and DNU tolerance principles. However, the QCCM12T cell uses two extra access transistors compared to the QCCM10T cell to effectively improve the access-operation performance. FIGURE 8 shows the layout of the proposed QCCM12T cell.

## IV. COMPARISON AND EVALUATION RESULTS

In the following, the comparison and evaluation results for the proposed QCCM10T and QCCM12T cells and the state-of-the-art cells described in Section I (i.e., NASA13T [17], Lin12T [18], RHD12T [19], RH12T [20], QUCE10T [21], and QUCE12T [21]) are described. The same implementation conditions that described in the above section were used to implement all cells. Table 1 shows the reliability and overhead comparison results of the unhardened and hardened memory cells, in terms of SEU tolerance, number of DNU-hardened node-pairs (#DHNP), silicon area,
<table><caption>TABLE 1. Reliability and overhead comparison results of the unhardened and hardened memory cells.</caption><thead><tr><th>SRAM</th><th>6T</th><th>NASA13T</th><th>Lin12T</th><th>RHD12T</th><th>RH12T</th><th>QUCCE10T</th><th>QUCCE12T</th><th>QCCM10T</th><th>QCCM12T</th></tr></thead><tbody><tr><th>Ref.</th><td>-</td><td>[17]</td><td>[18]</td><td>[19]</td><td>[20]</td><td>[21]</td><td>[21]</td><td>Proposed</td><td>Proposed</td></tr><tr><th>SEU Hardness</th><td>×</td><td>×</td><td>√</td><td>√</td><td>√</td><td>√</td><td>√</td><td>√</td><td>√</td></tr><tr><th>#DHNP</th><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>4</td><td>4</td></tr><tr><th>10<sup>-3</sup>×Area (nm<sup>2</sup>)</th><td>4.35</td><td>9.70</td><td>9.28</td><td>8.27</td><td>9.28</td><td>6.16</td><td>8.71</td><td>7.79</td><td>8.71</td></tr><tr><th>Power (nW)</th><td>5.24</td><td>18.92</td><td>9.74</td><td>10.38</td><td>9.74</td><td>10.08</td><td>10.43</td><td>8.50</td><td>10.43</td></tr><tr><th>RAT (ps)</th><td>25.88</td><td>128.67</td><td>37.68</td><td>25.72</td><td>37.72</td><td>36.36</td><td>13.02</td><td>18.20</td><td>12.99</td></tr><tr><th>WAT (ps)</th><td>3.65</td><td>16.39</td><td>3.78</td><td>5.06</td><td>3.85</td><td>6.29</td><td>4.31</td><td>23.21</td><td>3.65</td></tr></tbody></table>

<figure><img src="image_10.png" /><figcaption>FIGURE 8. Layout of the proposed QCCM12T cell.</figcaption></figure>

power dissipation, *read access time* (RAT), and *write access time* (WAT).

Let us first describe the reliability comparison results. It can be seen from Table 1 that all cells except the 6T and the NASA13T are SEU hardened, providing high reliability. Regarding #DHNP, only the proposed QCCM10T and QCCM12T cells can tolerate DNUs for 4 node-pairs, while the other cells can only tolerate DNUs for 0 or 1 node-pair. To summarize, the proposed QCCM10T and QCCM12T cells can provide much better reliability.

Let us now discuss the overhead comparison results. For power and area, we consider that a cell using only a few transistors has a small area and small power consumption, and a cell having a larger area will consume extra power. It can be seen from Table 1 that the 6T cell has the smallest power consumption and area overhead since it uses only 6 transistors. Since NASA13T uses extra transistors and there is more current competition in its feedback loops, it has the largest area and power. Lin12T, RHD12T, RH12T, QUCCE12T, and

the proposed QCCM12T use the same amount of transistors and they have similar cell constructions, and hence they have similar area and power consumption. It can be seen from Table 1 that the proposed QCCM10T cell has the smallest power consumption, except when compared with the 6T cell, mainly due to the smaller area and the less current competition in its feedback loops.

For WATs and RATs, we consider that the intrinsic charge/discharge of cell nodes through access transistors can affect WATs and RATs. It can be seen from Table 1 that the 6T cell has the smallest WAT, mainly because the cell has less current competition when the write operation is executed. The proposed QCCM12T also has the smallest WAT due to the use of extra access transistors. However, the NASA13T has the largest WAT, mainly due to more current competition when the write operation is executed. The proposed QCCM10T has the largest RAT mainly due to the slow current flow from the cell when the read operation is executed. However, the proposed QCCM12T has the smallest RAT owing to the use of extra access transistors.

$$ \Delta Area = \frac{Area_{compared}(i) - Area_{proposed}(i)}{Area_{compared}(i)} \times 100\% \quad (1) $$

$$ PRC_{Area}^{Average} = \sum_{i=1}^{n} \frac{Area_{compared}(i) - Area_{proposed}(i)}{Area_{compared}(i)} \times 100\% \quad (2) $$

The percentages of reduced costs (PRCs) of the proposed QCCM10T cell compared with the other memory cells are calculated and analyzed. The PRC of the area can be calculated with Eq. (1). Similarly, the PRCs of the power dissipation, RAT, and WAT can be calculated. The average PRC of the area can be calculated with Eq. (2). Similarly, the average PRCs of the power dissipation, RAT, and WAT can also be calculated. Table 2 shows the PRCs for the proposed QCCM10T cell compared with the other memory cells. For the sake of brevity, only the average PRCs are discussed. It can be seen from Table 2 that compared with the six hardened cells, the average PRCs of the silicon area, power dissipation, WAT, and RAT for the proposed QCCM10T cell are 6.95%, 22.14%, 38.12%, and -353.97%, respectively.
<table><caption>TABLE 2. Percentages of reduced costs for the proposed QCCM10T cell compared with the other memory cells.</caption><thead><tr><th>SRAM</th><th>Δ Area (%)</th><th>Δ Power (%)</th><th>Δ RAT (%)</th><th>Δ WAT (%)</th></tr></thead><tbody><tr><td>NASA13T</td><td>19.69</td><td>55.07</td><td>85.86</td><td>-41.61</td></tr><tr><td>Lin12T</td><td>16.06</td><td>12.73</td><td>51.70</td><td>-514.02</td></tr><tr><td>RHD12T</td><td>5.80</td><td>18.11</td><td>29.24</td><td>-358.70</td></tr><tr><td>RH12T</td><td>16.06</td><td>12.73</td><td>51.75</td><td>-502.86</td></tr><tr><td>QUCCE10T</td><td>-26.46</td><td>15.67</td><td>49.94</td><td>-268.10</td></tr><tr><td>QUCCE12T</td><td>10.56</td><td>18.50</td><td>-39.78</td><td>-438.52</td></tr><tr><td>Average</td><td>6.95</td><td>22.14</td><td>38.12</td><td>-353.97</td></tr></tbody></table>

<table><caption>TABLE 3. Percentages of reduced costs for the proposed QCCM12T cell compared with the other memory cells.</caption><thead><tr><th>SRAM</th><th>Δ Area (%)</th><th>Δ Power (%)</th><th>Δ RAT (%)</th><th>Δ WAT (%)</th></tr></thead><tbody><tr><td>NASA13T</td><td>10.21</td><td>44.87</td><td>89.90</td><td>77.73</td></tr><tr><td>Lin12T</td><td>6.14</td><td>-7.08</td><td>65.53</td><td>3.44</td></tr><tr><td>RHD12T</td><td>-5.32</td><td>-0.48</td><td>49.49</td><td>27.87</td></tr><tr><td>RH12T</td><td>6.14</td><td>-7.08</td><td>65.56</td><td>5.19</td></tr><tr><td>QUCCE10T</td><td>-41.39</td><td>-3.47</td><td>64.27</td><td>41.97</td></tr><tr><td>QUCCE12T</td><td>0</td><td>0</td><td>0.23</td><td>15.31</td></tr><tr><td>Average</td><td>-4.04</td><td>4.46</td><td>55.83</td><td>28.59</td></tr></tbody></table>

It means that the proposed QCCM10T cell saves 6.95% silicon area, 22.14% power dissipation, and 38.12% WAT on average. However, the proposed QCCM10T cell has an extra 353.97% WAT on average, which motivates us to use extra access transistors to reduce the WAT.

The PRCs of the QCCM12T cell compared with the other memory cells are calculated and analyzed. Table 3 shows the PRCs for the proposed QCCM12T cell compared with the other memory cells. For the sake of brevity, only the average PRCs are discussed. It can be seen from Table 3 that compared with the six hardened cells, the average PRCs of the silicon area, power dissipation, WAT, and RAT for the proposed QCCM12T are -4.04%, 4.46%, 55.83%, and 28.59%, respectively. It means that the proposed QCCM12T cell saves 4.46% power dissipation, 55.83% WAT, and 28.59% RAT on average. On the other side, the proposed QCCM12T cell only increases silicon area by 4.04% on average.

To summarize, the proposed QCCM10T and QCCM12T cells have been effectively hardened. Compared with the existing state-of-the-art hardened cells, the proposed QCCM10T cell has lower overhead especially in terms

of silicon area and power dissipation, and the proposed QCCM12T cell has lower overhead especially in terms of RAT and WAT.

## V. CONCLUSION

CMOS technology scaling makes modern memory cells more and more sensitive to soft errors that include SEUs and DNUs. In this paper, first, a novel and highly reliable QCCM10T cell has been proposed. The cell is effectively hardened against SEUs and DNUs and has a low cost especially in terms of area and power consumption. Next, to reduce the read and write access time, the QCCM12T cell has further been proposed. The cell has the same soft error tolerance ability compared to the QCCM10T cell and can achieve low overhead in terms of the read and write access time. The proposed cells can be effectively applied for safety-critical applications, such as aerospace, nuclear plants, and banking, where high reliability is required.

## REFERENCES

[1] M. Ebara, K. Yamada, K. Kojima, J. Furuta, and K. Kobayashi, "Process dependence of soft errors induced by alpha particles, heavy ions, and high energy neutrons on flip flops in FDSOI," *IEEE J. Electron Devices Soc.*, vol. 7, no. 1, pp. 817-824, Mar. 2019, doi: 10.1109/JEDS.2019.2907299.

[2] M. Hashimoto, K. Kobayashi, J. Furuta, S. Abe, and Y. Watanabe, "Characterizing SRAM and FF soft error rates with measurement and simulation," *Integr. VLSI J.*, vol. 69, pp. 161-179, Oct. 2019, doi: 10.1016/j.vlsi.2019.03.005.

[3] B. Narasimham, "Scaling trends and bias dependence of the soft error rate of 16 nm and 7 nm FinFET SRAMs," in *Proc. Int. Reliab. Phys. Symp., Burlingame, CA, USA, Mar. 2018*, pp. 1-4.

[4] S. K. Thirumala, "Dual mode ferroelectric transistor based non-volatile flip-flops for intermittently-powered systems," in *Proc. Int. Symp. Low Power Electron. Design*, Seattle, WA, USA, Jul. 2018, pp. 1421-1432.

[5] B. Xia, J. Wu, H. Liu, K. Zhou, and Z. Miao, "Design and comparison of high-reliable radiation-hardened flip-flops under SMIC 40 nm process," *J. Circuit, Syst. Comput.*, vol. 25, no. 12, pp. 1-19, Aug. 2016, doi: 10.1142/S0218126616501632.

[6] R. Bishnoi, F. Oboril, and M. B. Tahoori, "Design of defect and fault-tolerant nonvolatile spintronic flip-flops," *IEEE Trans. Very Large Scale Integr. (VLSI) Syst.*, vol. 25, no. 4, pp. 1421-1432, Dec. 2016, doi: 10.1109/TVLSI.2016.2630315.

[7] Y.-Q. Li, H.-B. Wang, R. Liu, L. Chen, I. Nofal, S.-T. Shi, A.-L He, G. Guo, S. H. Baeg, S.-J. Wen, R. Wong, M. Chen, and Q. Wu, "A quatro-based 65-nm flip-flop circuit for soft-error resilience," *IEEE Trans. Nucl. Sci.*, vol. 64, no. 6, pp. 1554-1561, May 2017, doi: 10.1109/TNS.2017.2704062.

[8] H. Nan and K. Choi, "High performance, low cost, and robust soft error tolerant latch designs for nanoscale CMOS technology," *IEEE Trans. Circuits Syst. I, Reg. Papers*, vol. 59, no. 7, pp. 1445-1457, Jan. 2012, doi: 10.1109/TCSI.2011.2177135.

[9] A. Yan, H. Liang, Z. Huang, C. Jiang, and M. Yi, "A self-recoverable, frequency-aware and cost-effective robust latch design for nanoscale CMOS technology," *IEICE Trans. Electron.*, vol. E98-C, no. 12, pp. 1171-1178, Dec. 2015, doi: 10.1587/transele.E98.C.1171.

[10] N. Eftaxiopoulos, N. Axelos, and K. Pekmestzi, "DIRT latch: A novel low cost double node upset tolerant latch," *Microelectron. Rel.*, vol. 68, pp. 57-68, Jan. 2017, doi: 10.1016/j.microrel.2016.11.006.

[11] A. Watkins and S. Tragouodas, "A highly robust double node upset tolerant latch," in *Proc. IEEE Int. Symp. Defect Fault Tolerance VLSI Nanotechnol. Syst.*, Storrs, CT, USA, Oct. 2016, pp. 1421-1432.

[12] X. Hui and Z. Yun, "Circuit and layout combination technique to enhance multiple nodes upset tolerance in latches," *IEICE Electron. Exp.*, vol. 12, no. 9, pp. 1-7, Mar. 2015, doi: 10.1587/elex.12.20150286.

[13] S. Lin, Y.-B. Kim, and F. Lombardi, "Design and performance evaluation of radiation hardened latches for nanoscale CMOS," *IEEE Trans. Very Large Scale Integr. (VLSI) Syst.*, vol. 19, no. 7, pp. 1315-1319, Jul. 2011, doi: 10.1109/TVLSI.2010.2047954.
[14] A. Yan, Z. Huang, M. Yi, X. Xu, Y. Ouyang, and H. Liang, "Double-node-upset-resilient latch design for nanoscale CMOS technology," *IEEE Trans. Very Large Scale Integr. (VLSI) Syst.*, vol. 25, no. 6, pp. 1978-1982, Jun. 2017, doi: 10.1109/TVLSI.2017.2655079.

[15] Z. Huang, H. Liang, and S. Hellebrand, "A high performance SEU tolerant latch," *J. Electro. Test.*, vol. 31, no. 4, pp. 349-359, Jul. 2015, doi: 10.1007/s10836-015-5533-5.

[16] R. Rajaei, M. Tabandeh, and M. Fazeli, "Single event multiple upset (SEMU) tolerant latch designs in presence of process and temperature variations," *J. Circuits, Syst. Comput.*, vol. 24, no. 1, pp. 1-31, Sep. 2015, doi: 10.1142/S0218126615500073.

[17] Y. Shiyanovskii, A. Rajendran, and C. Papachristou, "A low power memory cell design for SEU protection against radiation effects," in *Proc. Conf. Adapt. Hardw. Syst.*, Erlangen, Germany, 2012, pp. 288-295.

[18] D. Lin, "A novel highly reliable and low-power radiation hardened SRAM bit-cell design," *IEICE Electron. Exp.*, vol. 15, no. 3, pp. 1-8, Feb. 2018, doi: 10.1587/elex.15.20171129.

[19] C. Qi, L. Xiao, T. Wang, J. Li, and L. Li, "A highly reliable memory cell design combined with layout-level approach to tolerant single-event upsets," *IEEE Trans. Device Mater. Rel.*, vol. 16, no. 3, pp. 388-395, Sep. 2016, doi: 10.1109/TDMR.2016.2593590.

[20] C. Hu, S. Yue, and S. Lu, "Design of a novel 12T radiation hardened memory cell tolerant to single event upsets (SEU)," in *Proc. 2nd IEEE Int. Conf. Integr. Circuits Microsyst.*, Nanjing, China, Jan. 2017, pp. 182-185.

[21] J. Jiang, Y. Xu, W. Zhu, J. Xiao, and S. Zou, "Quadruple cross-coupled latch-based 10T and 12T SRAM bit-cell designs for highly reliable terrestrial applications," *IEEE Trans. Circuits Syst. I, Reg. Papers*, vol. 66, no. 3, pp. 967-977, Oct. 2019, doi: 10.1109/TCSI.2018.2872507.

[22] C. Peng, "Radiation-hardened 14T SRAM bitcell with speed and power optimized for space application," *IEEE Trans. Very Large Scale Integr. (VLSI) Syst.*, vol. 27, no. 2, pp. 407-415, Nov. 2019, doi: 10.1109/TVLSI.2018.2879341.

[23] J. Guo, "Novel radiation-hardened-by-design (RHBD) 12T memory cell for aerospace applications in nanoscale CMOS technology," *IEEE Trans. Very Large Scale Integr. (VLSI) Syst.*, vol. 25, no. 5, pp. 1593-1600, May 2017, doi: 10.1109/TVLSI.2016.2645282.

[24] A. Yan, C. Lai, Y. Zhang, J. Cui, Z. Huang, J. Song, J. Guo, and X. Wen, "Novel low cost, double-and-triple-node-upset-tolerant latch designs for nano-scale CMOS," *IEEE Trans. Emerg. Topics Comput.*, to be published, doi: 10.1109/TETC.2018.2871861.

[25] D. Lin, "A novel SEU tolerant memory cell for space applications," *IEICE Electron. Exp.*, vol. 15, no. 17, pp. 1-8, Aug. 2018, doi: 10.1587/elex.15.20180656.

[26] A. Yan, "Design of a sextuple cross-coupled SRAM cell with optimized access operations for highly reliable terrestrial applications," in *Proc. IEEE Asian Test Symp.*, Kolkata, India, Dec. 2019, pp. 1-6.

<figure><img src="image_11.png" /></figure>

**JUN ZHOU** received the B.S. degree from Anhui University, in 2017. He is currently pursuing the M.S. degree in computer technology major with Anhui University. His research interests include radiation hardening by design for nano-scale CMOS ICs, such as latches, memory cells, and flip-flops.

<figure><img src="image_12.png" /></figure>

**YUANJIE HU** received the B.S. degree from Chuzhou Colleague, in 2018. She is currently pursuing the M.S. degree in software engineering major with Anhui University. Her research interests include radiation hardening by design for nano-scale CMOS ICs, such as latches, flip-flops, and memory cells.

<figure><img src="image_13.png" /></figure>

**JIE CUI** received the Ph.D. degree from the University of Science and Technology of China, Hefei, China, in 2012. He is currently an Associate Professor with the School of Computer Science and Technology, Anhui University, Hefei. His research interests include the IoT security, applied cryptography, software-defined networking, vehicular ad hoc networks, and radiation hardening for nano-scale ICs.

<figure><img src="image_14.png" /></figure>

**AIBIN YAN** received the M.S. degree in software engineering from the University of Science and Technology of China (USTC), Hefei, in 2009, and the Ph.D. degree in computer application technology from the Hefei University of Technology, in 2015.

From 2010 to 2012, he was a Senior Software Engineer with USTC Sinovate Software Company, Ltd. His research interests include soft error rate analysis (SERA), nano-scale CMOS IC design automation by developing novel simulation tools, and radiation hardening by design for nano-scale CMOS ICs, such as latches, flip-flops, and memory cells.

<figure><img src="image_15.png" /></figure>

**ZHENGFENG HUANG** received the Ph.D. degree in computer engineering from the Hefei University of Technology, in 2009. He joined the Hefei University of Technology, as an Assistant Professor, in 2004, and has been an Associate Professor, since 2010. He worked as a Visiting Scholar at the University of Paderborn, Germany, from 2014 to 2015. He has been a Professor, since 2018. His current research interest includes design for soft error tolerance/mitigation. He is a member of Technical Committee on Fault Tolerant Computing which belongs to China Computer Federation. He served on the organizing committee for the IEEE European Test Symposium, in 2014.
<figure><img src="image_16.png" /></figure>

**PATRICK GIRARD** received the M.Sc. degree in electrical engineering and the Ph.D. degree in microelectronics from the University of Montpellier, France, in 1988 and 1992, respectively. From 2010 to 2014, he was the Head of the Microelectronics Department. He is currently the Research Director with the CNRS (French National Center for Scientific Research), where he works at the Laboratory of Informatics, Robotics and Microelectronics of Montpellier (LIRMM),

Microelectronics Department, France. He is the Co-Director of the International Associated Laboratory << LAFISI >> (French-Italian Research Laboratory on Hardware-Software Integrated Systems) created, in 2013, by the CNRS and the University of Montpellier with the Politecnico di Torino, Italy. He has supervised 37 Ph.D. dissertations and has published seven books or book chapters, 65 journal articles, and more than 230 conference and symposium papers on these fields. His research interests include all aspects of digital testing and memory testing, with emphasis on critical constraints, such as timing and power. Reliability and fault tolerance are also part of his research activities. He has served on numerous conference committees. He is the Founder and the Editor-in-Chief of the *ASP Journal of Low Power Electronics* (JOLPE). He is also an Associate Editor of the *IEEE TRANSACTIONS ON COMPUTERS*, *IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING*, and the *Journal of Electronic Testing – Theory and Applications* (JETTA) (Springer).

<figure><img src="image_17.png" /></figure>

**XIAOQING WEN** (M'89-SM'08-F'12) received the B.E. degree from Tsinghua University, China, in 1986, the M.E. degree from Hiroshima University, Japan, in 1990, and the Ph.D. degree from Osaka University, Japan, in 1993. From 1993 to 1997, he was an Assistant Professor with Akita University, Japan. He was a Visiting Researcher with the University of Wisconsin, Madison, USA, from October 1995 to March 1996. He joined SynTest Technologies, Inc., USA, in 1998, and served

as the Chief Technology Officer, until 2003. In 2004, he joined the Kyushu Institute of Technology, Japan, where he is currently a Professor. He founded Dependable Integrated Systems Research Center, in 2015, and served as the Director, until 2017. His research interests include VLSI test, diagnosis, and testable design. He has coauthored and co-edited two books: *VLSI Test Principles and Architectures: Design for Testability* (Morgan Kaufmann, 2006) and *Power-Aware Testing and Test Strategies for Low Power Devices* (Springer, 2009). He holds 43 U.S. patents and 14 Japan patents on VLSI testing. He is a member of the IEICE, and a Senior Member of the IPSJ. He received the 2008 IEICE-ISS Best Paper Award. He is currently serving as an Associate Editor of the *IEEE TRANSACTIONS ON VLSI SYSTEMS*, and *Journal of Electronic Testing: Theory and Applications*.