# Low Trapping Effects and High Blocking Voltage in Sub-Micron-Thick AlN/GaN Millimeter-Wave Transistors Grown by MBE on Silicon Substrate

Elodie Carneiro, Stéphanie Rennesson, Sebastian Tamariz, Kathia Harrouche, Fabrice Semond, Farid Medjdoub

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Elodie Carneiro, Stéphanie Rennesson, Sebastian Tamariz, Kathia Harrouche, Fabrice Semond, et al. Low Trapping Effects and High Blocking Voltage in Sub-Micron-Thick AlN/GaN Millimeter-Wave Transistors Grown by MBE on Silicon Substrate. Electronics, 2023, 12 (13), 10.3390/electronics12132974. [https://doi.org/10.3390/electronics12132974](https://doi.org/10.3390/electronics12132974)

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# Low Trapping Effects and High Blocking Voltage in Sub-Micron-Thick AlN/GaN Millimeter-Wave Transistors Grown by MBE on Silicon Substrate

Elodie Carneiro<sup>1,2,*</sup> <sup>1</sup> ID, Stéphanie Rennesson<sup>2,1</sup> <sup>2</sup> ID, Sebastian Tamariz<sup>2,3</sup>, Kathia Harrouche<sup>1</sup>, Fabrice Semond<sup>2,3</sup> and Farid Medjdoub<sup>1</sup> <sup>1</sup> ID

**Abstract:** In this work, sub-micron-thick AlN/GaN transistors (HEMTs) grown on a silicon substrate for high-frequency power applications are reported. Using molecular beam epitaxy, an innovative ultrathin step-graded buffer with a total stack thickness of 450 nm enables one to combine an excellent electron confinement, as reflected by the low drain-induced barrier lowering, a low leakage current below 10 µA/mm and low trapping effects up to a drain bias V<sub>DS</sub> = 30 V while using sub-150 nm gate lengths. As a result, state-of-the-art GaN-on-silicon power performances at 40 GHz have been achieved, showing no degradation after multiple large signal measurements in deep class AB up to V<sub>DS</sub> = 30 V. Pulsed-mode large-signal characteristics reveal a combination of power-added efficiency (PAE) higher than 35% with a saturated output power density (P<sub>OUT</sub>) of 2.5 W/mm at V<sub>DS</sub> = 20 V with a gate-drain distance of 500 nm. To the best of our knowledge, this is the first demonstration of high RF performance achieved with sub-micron-thick GaN HEMTs grown on a silicon substrate.

**Keywords:** load pull; GaN-on-Si; MBE; PAE; P<sub>OUT</sub>; HEMT; mm wave

## 1. Introduction

GaN-based High-Electron-Mobility Transistors (HEMTs) have been commercially available for about a decade and are being used for power applications into the millimeter-wave range, thanks to their attractive material properties, including high thermal and chemical stability, high electron saturation velocity (2.5 × 10<sup>7</sup> cm/s), and high breakdown field (3.3 MV/cm) [1–3]. To minimize growth defect/dislocation density due to the large lattice mismatch between GaN and the substrate as well as bow/curvature due to the thermal expansion coefficient mismatch between epilayers and substrates (SiC and Si), thick and complex buffer layers (several µm) are typically used [4–9]. However, thick buffer layers, including multiple interfaces, generally degrade the thermal dissipation and increase the growth cost. The latest results showed that sub-micron-thick AlGaN/GaN HEMTs grown via Metal Organic Chemical Vapor Deposition (MOCVD) on Silicon Carbide (SiC) can deliver competitive RF performances [10,11]. Although more challenging to achieve due to both the large thermal expansion coefficient mismatch and the large lattice mismatch between GaN and Silicon (Si), potentially leading to cracks/defects, the use of a Si substrate would significantly decrease the cost and significantly increase the availability of devices. Moreover, on top of using thinner buffer layers, short channel effects must also be mitigated while shrinking the device dimensions in order to achieve high-output power density (P<sub>OUT</sub>) and power-added efficiency (PAE) above the Ka-band [12]. The ultrathin

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**Citation:** Carneiro, E.; Rennesson, S.; Tamariz, S.; Harrouche, K.; Semond, F.; Medjdoub, F. Low Trapping Effects and High Blocking Voltage in Sub-Micron-Thick AlN/GaN Millimeter-Wave Transistors Grown by MBE on Silicon Substrate.
*Electronics* **2023**, *12*, 2974. https://doi.org/10.3390/electronics12132974

Academic Editor: Francesco
Giuseppe Della Corte

Received: 1 June 2023

Revised: 30 June 2023

Accepted: 4 July 2023

Published: 6 July 2023

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**Copyright:** © 2023 by the authors.
Licensee MDPI, Basel, Switzerland.
This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).

<footnote n="1">¹ French National Centre for Scientific Research (CNRS), Institute of Electronics, Microelectronics and Nanotechnology (IEMN), Av. Poincare, 59650 Villeneuve d'Ascq, France; kathia.harrouche@iemn.fr (K.H.); farid.medjdoub@iemn.fr (F.M.)</footnote>

<footnote n="2">² EasyGaN SAS, Rue Bernard Gregory, 06560 Sophia Antipolis, France; stephanie.rennesson@easy-gan.com (S.R.); sebastian.tamariz@crhea.cnrs.fr (S.T.); fabrice.semond@crhea.cnrs.fr (F.S.)</footnote>

<footnote n="3">³ Côte d'Azur University, CNRS, CRHEA, Bernard Gregory Street, 06905 Sophia Antipolis, France</footnote>

<footnote>* Correspondence: elodie.carneiro@iemn.fr</footnote>
AlN/GaN material system has become an alternative candidate for high-power millimeter-wave applications, owing to the use of sub 10 nm barrier thickness while benefiting from a high current density [13–17]. However, one of the main challenges in this goal is to achieve a high-quality nucleation layer followed by thin buffer layers on a silicon substrate while avoiding high electron trapping and delivering high blocking voltage under an extreme electric field. In this study, the possibility to combine low trapping effects and high blocking voltage in sub-micron-thick AlN/GaN-on-silicon HEMTs, resulting in high-power performances at 40 GHz, is demonstrated.

## 2. Experimental Details

The epitaxial AlN/GaN heterostructure was grown via ammonia-molecular beam epitaxy (NH₃-MBE) on 4-inch high-resistivity Si (111) substrates ($ρ > 5$ KΩ·cm) using a RIBER MBE49 growth reactor. The cross-section and FIB view of the HEMT structures with 140 nm T-gates are shown in Figure 1. It consists of a high-quality lower than 100 nm AlN nucleation layer (NL), followed by a step-graded AlₓGa₁₋ₓN buffer layers (Al₀.₀₅Ga₀.₉₂N/Al₀.₃₀Ga₀.₇₀N/Al₀.₆₀Ga₀.₄₀N), with a total thickness of 450 nm, a 150 nm thick undoped GaN channel layer, and a 7 nm thick AlN barrier layer. Finally, an in situ SiN layer was used to cap the structure. It can be noticed that the total stack thickness is as low as 650 nm (Figure 1b). The step-graded AlₓGa₁₋ₓN buffer plays the role of back barrier, increasing the overall buffer bandgap to enhance both the breakdown voltage and the electron confinement under high electric field. The source and drain ohmic contacts were first fabricated. The contacts were directly deposited on top of the AlN barrier. A Ti/Al/Ni/Au metal stack was annealed at 850 °C, yielding contact resistances of 0.4 Ω·mm. Nitrogen implantation was used to isolate the devices. Then, Ni/Au T-gates of 140 nm, 250 nm, and 500 nm gate lengths (L<sub>G</sub>) were defined by e-beam lithography. Finally, 200 nm PECVD Si₃N₄ passivation layer was deposited prior to Ti/Au pad deposition. Hall effect measurements at room temperature showed a charge density of 1.7 × 10¹³ cm⁻² with an electron mobility of 745 cm²/V·s. The electron mobility can be significantly improved by further tuning the growth parameters [18].

<figure><img src="image_5.png" /><figcaption>**Figure 1.** (a) Schematic cross-section and (b) FIB view of the ultrathin AlN/GaN HEMTs grown on Si(111) substrate by MBE and using a step-graded AlₓGa₁₋ₓN buffer layers.</figcaption></figure>

## 3. DC and RF Characteristics

Thus, 2 × 50 µm transistors with L<sub>G</sub> = 140 nm and a gate-to-drain distance (L<sub>GD</sub>) of 500 nm typical output and transfer characteristics are shown in Figure 2. The gate source voltage was swept from -6 V to +2 V with a 1 V step. A maximum drain current density (I<sub>D,max</sub>) of 1.2 A/mm (Figure 2a) and a transconductance (G<sub>m</sub>) of 340 mS/mm were measured (Figure 2b), despite the rather limited electron mobility and access resistances that can still be optimized. Transfer characteristics with a compliance fixed at 150 mA/mm and swept from a drain bias of 2 to 30 V using a 1 V step are displayed in Figure 2c. A
drain leakage current lower than 10 µA/mm up to V<sub>DS</sub> = 30 V (shown in Figure 2c) is uniformly observed. A limited threshold voltage shift is observed as a function of V<sub>DS</sub> under high electric field, which reflects the proper 2DEG electron confinement confirmed by a low drain-induced barrier lowering (DIBL) of 12 mV/V. The transistors' three-terminal off-state breakdown voltage was assessed at V<sub>GS</sub> = -4 V. A hard breakdown voltage between 60 V and 70 V was observed. This translates to a lateral breakdown strength up to 140 V/µm, further proving the quality of the buffer, especially considering the sub-micron total epi-stack thickness.

<figure><img src="image_6.png" /><figcaption>**Figure 2.** (a) Output characteristics, (b) extrinsic transconductance, (c) transfer characteristics up to V<sub>DS</sub> = 30 V, and (d) open channel pulsed I<sub>D</sub>-V<sub>DS</sub> output characteristics of 2 × 50 µm ultrathin AlN/GaN-on-Si HEMTs with L<sub>GD</sub> = 500 nm and L<sub>G</sub> = 140 nm.</figcaption></figure>

Figure 2d depicts pulsed I<sub>D</sub>-V<sub>DS</sub> characteristics, revealing the electron trapping effects. For various quiescent drain voltages, the open-channel DC-pulsed measurements are shown at V<sub>GS</sub> = +2 V and at room temperature. A pulse width of 1 µs and a duty cycle of 1% were employed. Thus, 2 × 50 µm transistors with L<sub>GD</sub> of 500 nm and L<sub>G</sub> of 140 nm show low-electron trapping effects with about 10% current collapse at V<sub>DS</sub> = 20 V, despite the low epilayer total thickness. This is attributed to the high nucleation layer quality and subsequent step-graded Al-rich AlGaN layers as well as the absence of doping compensation, such as iron or carbon, which are known to act as acceptors and, thus, generate trapping. Low unintentional carbon and oxygen concentrations within the structure were measured using secondary-ion mass spectrometry (SIMS). The carbon concentration is about 1–5 × 10<sup>15</sup> atoms/cm<sup>3</sup>, both in the step-graded Al<sub>x</sub>Ga<sub>1-x</sub>N buffer layers and the GaN channel, while the oxygen concentration is below 1 × 10<sup>17</sup> atoms/cm<sup>3</sup> in the buffer layers. The rather low unintentional carbon doping is considered to be satisfactory to avoid buffer-trapping effects [19,20].
The S-parameters were measured for different gate lengths from 250 MHz to 67 GHz with a Rhode and Schwarz ZVA67GHz network analyzer, as shown in Figure 3. The current gain extrinsic cut-off frequency ($F_T$) slightly decreases as a function of $V_{DS}$ and shows a good scaling for short $L_G$ (shown in Figure 3a), owing to the reduced short channel effects enabled by the ultrathin barrier. The maximum oscillation frequency ($F_{max}$) increases as a function of $V_{DS}$ (Figure 3b). $F_T/F_{max}$ of 51/169 GHz are achieved at $V_{DS}$ = 20 V with $L_{GD}$ = 500 nm and $L_G$ = 140 nm. The $F_{max}/F_T$ ratio above 3 for all gate lengths results from the highly favorable aspect ratio: gate length/gate-to-channel distance and the T-gate height higher than 100 nm, ensuring a reduced parasitic gate resistance [21,22].

<figure><img src="image_7.png" /><figcaption>Figure 3. (a) Current gain extrinsic cut-off frequency and (b) maximum oscillation frequency of 2 × 50 µm ultrathin AlN/GaN HEMTs with $L_{GD}$ = 500 nm for various gate lengths.</figcaption></figure>

## 4. Large Signal Characteristics (10 GHz and 40 GHz)

Large signal characterizations were carried out at 10 GHz and 40 GHz on a nonlinear vector network analyzer system (Keysight Network Analyser: PNA-X, N5245A-NVNA) capable of on-wafer large signal device characterization up to the Q-band in continuous-wave (CW) and pulsed mode. Further details about the power bench can be found in Ref. [23]. Figure 4a,b show typical CW and pulsed mode power performances at 10 GHz in deep class AB of 2 × 50 µm transistors with $L_{GD}$ = 500 nm and $L_G$ = 140 nm at $V_{DS}$ = 10 V and 30 V, respectively. A 1.1 W/mm saturated output power density ($P_{OUT}$) with a power-added efficiency (PAE) of 53.6% and 47.2% at $V_{DS}$ = 10 V is measured in pulsed and CW mode, respectively. As expected, at $V_{DS}$ = 30 V, the $P_{OUT}$ increases substantially well above 3 W/mm with a PAE > 42%. Figure 5a,b show CW and pulsed power performances at 40 GHz of similar 2 × 50 µm transistors with $L_G$ = 140 nm at $V_{DS}$ = 10 V and 30 V, respectively. A saturated $P_{OUT}$ close to 1 W/mm associated to a PAE of 40.0% and 31.4% at $V_{DS}$ = 10 V is measured in pulsed and CW mode, respectively. At $V_{DS}$ = 30 V, a $P_{OUT}$ of 3.5 W/mm and 2.5 W/mm with a PAE of 28.9% and 19.2% are observed in pulsed and CW mode, respectively. Moreover, it can be pointed out that following several tenths of CW Load-Pull sweeps under high-gain compression (up to 10 dB), we did not observe any major degradation of the devices up to $V_{DS}$ = 30 V (see Figure 5c). Degradation reflected by an increase in the off-state leakage current is observed at a bias $V_{DS}$ as high as 35 V (see Figure 5c), while typical safe operating drain bias for mm wave GaN-on-silicon HEMTs is well below 20 V. This indicates an excellent robustness of this heterostructure, handling an extreme electric field and, thus, enabling high-voltage operation without degradation while using a sub-150 nm gate length. The promising device reliability results from the excellent electron confinement and low trapping effects despite the absence of any thermal management. Indeed, unlike semi-insulating SiC substrates that are favorable for high-power operation, silicon has a much lower dissipation, which results in significantly higher junction temperature in GaN-on-silicon HEMTs.
<figure><img src="image_8.png" /><figcaption>Figure 4. CW and pulsed large signal performances at 10 GHz of 2 × 50 µm ultrathin AlN/GaN HEMTs with L<sub>GD</sub> = 500 nm and L<sub>G</sub> = 140 nm at (a) V<sub>DS</sub> = 10 V and (b) V<sub>DS</sub>= 30 V.</figcaption></figure>

<figure><img src="image_9.png" /><figcaption>Figure 5. Typical CW and pulsed large signal performances at 40 GHz of 2 × 50 µm ultrathin AlN/GaN HEMTs with L<sub>GD</sub> = 500 nm and L<sub>G</sub> = 140 nm at (a) V<sub>DS</sub> = 10 V and (b) V<sub>DS</sub>= 30 V. (c) Transfer characteristics after more than 40 CW Load-Pull sweeps in deep class AB under high compression up to V<sub>DS</sub> = 35 V.</figcaption></figure>

Figure 6 depicts typical pulsed PAE and P<sub>OUT</sub> of 2 × 50 µm AlN/GaN on silicon transistors with L<sub>GD</sub> = 500 nm and L<sub>G</sub> = 140 nm as a function of V<sub>DS</sub> at 40 GHz. The PAE decreases with the V<sub>DS</sub> increase but remains about 30% under 3.5 W/mm at V<sub>DS</sub> = 30 V, which sets a new performance benchmark at this frequency band for GaN-on-Si HEMTs (Figure 6b). As shown in Figure 6c, it can be pointed out that this represents the first high-
performance mm wave transistors using a sub-micron-thick GaN-on-silicon heterostructure. The drop in the PAE/P<sub>OUT</sub> between pulsed and CW measurements is mainly attributed to the low thermal dissipation of the Si substrate, as seen from the increasing CW/pulsed P<sub>OUT</sub> gap that is more pronounced under higher output power. Therefore, further optimization of the structure to enhance the electron mobility and, thus, the power gain, combined with well-known techniques, such as substrate thinning/or vias, with subsequent related heat sink based on copper will certainly boost these reported GaN-on-Si mm wave device performances [24].

<figure><img src="image_10.png" /><figcaption>**Figure 6.** (a) Pulsed PAE and P<sub>OUT</sub> as a function of V<sub>DS</sub> at 40 GHz with L<sub>GD</sub> = 500 nm and L<sub>G</sub> = 140 nm for 2 × 50 µm ultrathin AlN/GaN HEMTs. Benchmark of (b) power performances and (c) PAE as a function of total stack thickness at 40 GHz for GaN-on-Si HEMTs [25–29].</figcaption></figure>

**5. Conclusions**

We developed a sub-micron-thick AlN/GaN heterostructure grown via NH₃-MBE on a silicon substrate, enabling the combination of low-electron trapping effects, extreme robustness under a high electric field, and high mm wave power gain. This, in turn, allows for unprecedented class AB bias operation (up to V<sub>DS</sub> = 30 V) for 140 nm gate-length GaN-on-Si HEMTs. Consequently, the proposed AlN/GaN-on-silicon HEMT structure delivers high-output power density together with state-of-the-art PAE of 40%/29% at V<sub>DS</sub> = 10 V/30 V at 40 GHz, respectively. This achievement is attributed to the optimization of material, epi-design, and processing quality, enabling a high-electron confinement together with reduced short channel effects under a high electric field. The results show
the potential of MBE to grow ultrathin cost-effective AlN/GaN-on-Si HEMTs for mm wave applications.

**Author Contributions:** Material growth, S.R., S.T. and F.S.; device processing, E.C. and F.M.; device characterization, E.C., K.H. and F.M.; validation, E.C., S.R., S.T., K.H., F.S. and F.M.; writing—review and editing, E.C., S.R., S.T., K.H., F.S. and F.M.; funding acquisition, F.S. and F.M. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was funded by the French National grant GaNeXT ANR-11-LABX-0014, and by a BPI France aid for innovation.

**Data Availability Statement:** The dataset is not applicable.

**Acknowledgments:** This work was supported by the French RENATECH network, the French National grant GaNeXT ANR-11-LABX-0014, and by a BPI France aid for innovation. The authors would also like to thank Riber for his amazing technical support.

**Conflicts of Interest:** The authors declare no conflict of interest. The funders had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript; or in the decision to publish the results.

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