# Machine Learning-Based Defect Detection, Output Matching Assessment, and Performance Recentering of a 79-GHz Four-Way CMOS Power Amplifier

Oumayma Belkhadra, Florent Cilici, Sébastien Crampon, Jérémie Arbouet, Loïc Vincent, Gilles Montoriol, Salvador Mir, Emmanuel Pistono, Sylvain Bourdel, Manuel J. Barragan, et al.

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## ► To cite this version:

Oumayma Belkhadra, Florent Cilici, Sébastien Crampon, Jérémie Arbouet, Loïc Vincent, et al. Machine Learning-Based Defect Detection, Output Matching Assessment, and Performance Recentering of a 79-GHz Four-Way CMOS Power Amplifier. IEEE Transactions on Microwave Theory and Techniques, 2025, 74 (1), pp.1005 - 1022. 10.1109/TMTT.2025.3619021. hal-05375041

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Machine Learning-Based Defect Detection, Output Matching Assessment and Performance Recentering of a 79-GHz 4-way CMOS Power Amplifier

Oumayma Belkhadra *Member, IEEE*, Florent Cilici, Sebastien Crampon, Jérémie Arbouet, Loïc Vincent, Gilles Montoriol, Salvador Mir *Member, IEEE*, Emmanuel Pistono, Sylvain Bourdel *Member, IEEE* and Manuel J. Barragan *Member, IEEE*

**Abstract**—This work proposes the use of machine learning-based techniques for enhanced testability and performance calibration of an industrial 79-GHz power amplifier (PA) designed for an automotive radar system. The proposed techniques are based on a set of built-in test structures including nonintrusive process monitors based on digital ring oscillators and a built-in reflectometer. The indirect signatures provided by these test structures allow us to a) identify defective instances of the PA under test, b) evaluate the quality of the output matching adaptation, and c) calibrate the performance of the PA to compensate for process variations. Defect detection is based on a defect filtering algorithm that employs outlier identification techniques; mismatch evaluation employs a machine learning regressor; and, finally, the proposed performance calibration is based on a one-shot statistical calibration that predicts the optimum configuration of the power amplifier. The proposed techniques are experimentally demonstrated on a set of 32 fabricated chips designed in 28 nm CMOS technology.

***Index Terms***—Power amplifier, machine-learning, defect detection, intrusive, nonintrusive, process control monitors, process variations, matching assessment, one-shot calibration, tuning knobs, ring oscillators, reflectometer, feature-selection.

I. INTRODUCTION

IN recent years, there has been a pronounced focus on developing circuits that operate at millimeter-wave frequencies, driven by the need for higher data rates and larger available bandwidths. These frequencies also facilitate the miniaturization of components and improve resolution in sensing technologies, which are crucial for advanced applications like 5G networks and beyond, automotive radar systems, and the Internet-of-Things (IoT). With the advancements in CMOS technologies, it has become increasingly feasible to fabricate efficient millimeter-wave integrated circuits that enable new technological innovations.

Nevertheless, as mm-Wave technologies expand into high-
volume markets for which efficiency is critical, CMOS-based

Manuscript received XX, XX; revised XX, XX.

Oumayma Belkhadra is with NXP Semiconductors, Toulouse, France and with Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA, F-38000, Grenoble, France.

Florent Cilici, Sebastien Crampon, Jérémie Arbouet and Gilles Montoriol
are with NXP Semiconductors, Toulouse, France.

Loïc Vincent is with Université Grenoble-Alpes, Grenoble INP, CIME Nanotech F-38000 Grenoble, France.

Salvador Mir, Emmanuel Pistono, Sylvain Bourdel and Manuel J. Barragan are with Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA, F-38000, Grenoble, France.

systems are susceptible to process variations and fabrication
defects which can adversely affect their performance. Thus,
a cost-effective deployment requires: 1) careful design to
assure a good fabrication yield, 2) early identification of
faulty instances, and 3) detection (and correction if possible)
of underperforming circuits to maintain optimal functionality
along the lifetime of the circuit.

Following the advancements in mm-wave integrated circuit
technologies, design and test engineers have to face the afore-
mentioned problems to ensure reliable circuit performance.
From a design perspective, mm-wave integrated circuits for
stringent industrial applications such as automotive or health-
care are fabricated with ample design margins to take into
account extreme corner variations. However, this is done at
the cost of increasing the area and power budgets. Calibra-
tion techniques (such as trimming, performance tuning, self-
healing, etc.) appear as alternative (or complementary) tech-
niques that can ease these constraints, allowing the optimiza-
tion of performances for given design targets. In a classical
implementation, a set of tuning knobs is integrated within the
circuit under calibration and a calibration algorithm decides
the optimal position of these knobs as a function of some
circuit measurements [1]–[4]. As a result, not only fabrication
yield can be improved by recovering some underperforming
devices, but also functional devices can be centered around
the desired power-performance trade-off.

Recent implementations of the calibration techniques lever-
age the predictive power of machine learning algorithms to
optimize the procedure. Moreover, direct performance mea-
surement at RF or mm-wave frequencies can be replaced by
simpler signatures at DC and low frequency. These simpler
measurements are then used to predict the performance of
the circuit under calibration or, directly, the optimal positions
of the tuning knobs. This way, lengthy iterative calibration
loops are avoided. This is the working principle of the so-
called statistical one-shot calibration techniques. Recent works
on statistical one-shot calibration exploit nonintrusive perfor-
mance monitoring techniques, in which the calibrated state is
estimated from a set of process monitors sensitive to process
variations [5]–[8].

In this work we further advance one-shot calibration tech-
niques and their application to mm-wave integrated circuits.
Previous works on nonintrusive one-shot calibration reported
in the literature have a number of limitations that severely
limit the adoption of the technique by the industry. Firstly, reported nonintrusive one-shot calibration schemes are aimed only at correcting an excessive process variation, but they are blind to local phenomena affecting the actual circuit under calibration such as mismatch or spot defects. Moreover, previously presented proof-of-concept demonstrators rely on a set of analog DC and low-frequency process control monitors that have to be measured individually on a probe station. Finally, previous works are validated using academic proof-of-concept demonstrators that are far from the state-of-the-art and do not comply to the stringent design requirements of an industrial-level circuit for safety-critical applications. In this paper, we overcome the aforementioned limitations and advance towards the industrialization of these techniques by proposing a statistical one-shot calibration strategy based on a combination of novel process control monitors and built-in test instruments. A set of especially crafted ring oscillators is employed to track process variations non-intrusively, while a built-in reflectometer and power detectors are employed to complement the nonintrusive monitors. These built-in instruments will be used for a) increasing the quality of the calibration, b) early identification of faulty PAs and c) evaluating the quality of the PA output impedance matching. The proposed test and calibration strategies are then validated in an industrial-level Power Amplifier from NXP Semiconductors developed in 28 nm CMOS technology for automotive radar applications.

The rest of the paper is outlined as follows. Section II provides an overview of previous works on on-chip test and calibration techniques for mm-wave integrated circuits. Section III presents the proposed one-shot calibration methodology, while Section IV presents its practical implementation using a 79-GHz PA for automotive applications as case study. Section V validates the feasibility of the proposed calibration with experimental results on a set of 32 fabricated dies. Finally, Section VI summarizes our main contributions.

## II. PREVIOUS WORKS

Initial works on on-chip test and calibration for integrated mm-wave circuits dealt with the built-in implementation of embedded test instruments and dedicated tunable mm-wave devices for performance monitoring and tuning. In this regard, the work in [2] presents a 28 GHz self-healing PA featuring a tunable transmission line stub that can be shorted at discrete lengths to tune its impedance. Built-in test instruments for measuring bias current, signal power, and temperature are used to track the performance of the PA, while an iterative algorithm is employed to search for the appropriate configuration of the tuning knobs.

The works in [3], [4] also exploit digitally tunable transmission lines. [3] employs tunable transmission lines in a 60-GHz amplifier to reduce the impact of process variations in the amplifier S-parameters. In this case, the tunable lines are implemented as differential coplanar transmission lines over an array of floating metal fingers. By shorting these metal fingers for a fixed voltage, it is possible to change the effective dielectric permittivity. [4] is aimed at recentering the

performance of a 60-GHz LNA for improving the trade-off between power consumption and Noise Figure (NF). Built-in test instruments are included to monitor the DC operation point of the LNA and the device temperature, while tunability is implemented using a programmable bias current and digitally controlled transmission lines. Other works have proposed dedicated tunable elements by exploiting some properties of a particular design. For example, [1] proposes a dedicated calibration feedback loop based on a linearization technique that controls the DC operation point of a 60-GHz PA as a function of the observed output power.

Advanced machine learning algorithms have been recently used to simplify the estimation of the performance of the circuit under calibration, optimize the calibration algorithm, and, in general, to reduce the design complexity of the required built-in calibration resources. [9], [10] propose a classical test-and-tune iterative calibration algorithm for RF circuits in which circuit performance measurements are replaced by simpler indirect signatures. A machine learning regression algorithm is employed to predict the circuit performance from the indirect measurements. In particular, the circuit performance is predicted from the envelope of the circuit response to an optimized analog stimulus. Similarly, [11], [12] employ a machine learning regressor to predict the optimum positions of the tuning knobs from a set of indirect signatures for a 1.57-GHz LNA case study. A built-in VCO and a peak detector are used to excite the LNA and to estimate the power of the output response, respectively. A machine learning regression algorithm predicts the optimum bias configuration from the peak detector output in order to comply with the design targets. The search of the design space during a test-and-tune calibration loop has been optimized using reinforcement learning algorithms [13]–[15]. Basically, these algorithms learn the appropriate actions to calibrate a given circuit as they explore the calibration space. They strike a balance between an exhaustive exploration of the tuning space and the exploitation of current knowledge as more states are visited during the different calibration iterations. Compared to one-shot calibration algorithms, the techniques based on reinforcement learning have the advantage of not requiring a previously trained regression model, although this is at the cost of requiring multiple iterations to converge to the calibrated state.

Recent works on RF and mm-Wave IC test and calibration techniques [6], [8] exploit the concept of nonintrusive test (firstly introduced for mixed-signal circuits [16]–[18]). This further simplifies the built-in implementation of one-shot calibration algorithms [5], [7]. [7] presents a one-shot calibration strategy for a 69-GHz PA based on nonintrusive process control monitors. Process monitor circuits are stand-alone circuits, not connected to the circuit under calibration, that are sensitive to process variations. The calibrated state is predicted directly from these nonintrusive signatures, without the need of tapping into the PA under calibration. Nonintrusive test and calibration techniques do not require to modify the design of the circuit under calibration for adding built-in test instruments. As a disadvantage, they are only sensitive to process variations. They are blind to local defects and
mismatch affecting the actual circuitry, which is a serious
limitation for the adoption of the technique as an industry
standard for safety-critical applications.

### III. PROPOSED MM-WAVE POWER AMPLIFIER WITH TEST AND CALIBRATION CAPABILITIES

As mentioned in Section I, our goal is to advance towards the industrialization of statistical one-shot calibration techniques for mm-wave integrated circuits. Fig. 1 shows a system-level block diagram of the proposed PA with built-in calibration capabilities. The system comprises a state-of-the-art 4-way PA for automotive radar applications that includes both nonintrusive process control monitors and built-in test instruments. Nonintrusive process monitors are implemented as a set of digital ring oscillators. These ring oscillators have been especially tailored to be sensitive to the critical process parameters for the performance of the PA. Additionally, a reflectometer and power detectors have been integrated to monitor matching issues with the output antenna and local phenomena such as mismatch and spot defects that may lead to non-functional PAs. Tunability is achieved by externally controlling the bias current and power supply of the different stages of the PA. The optimum value of these tuning knobs is predicted by a machine learning-based one-shot calibration algorithm from the signatures provided by the on-chip process monitors and built-in instruments. The goal of the calibration is to bias the PA in the operation point that maximizes its Power Added Efficiency (PAE) and Drain Efficiency (DE) while complying with the minimum requirement for the rest of the PA specifications.

Sections III-A, III-B, III-C and III-D detail the design of the PA under calibration, the ring oscillator-based process monitors and the on-chip reflectometer and power detectors.

#### A. 79-GHz 4-Way PA for Automotive Radar

The architecture of the PA under calibration, designed and fabricated in a 28 nm CMOS technology, consists in a four-identical-way power combining amplifier with 50Ω input matching. It adopts a pseudo-differential architecture to reduce even harmonic distortion and improve common-mode rejection.

Each of the four channels consists of a predriver amplifier implemented as a Neutralized CAscode stage (NCA) followed by a driver amplifier implemented as two Neutralized Common Source stages (NCS). This configuration offers a good trade-off between gain, output power and PAE, while offering a relatively compact implementation [19].

The three-stage unit amplifier (UA) design was optimized stage by stage, from output to pre-driver, to deliver a target output power of 9 dBm. The power levels were calculated with a 3-dB margin to prevent compression. To identify the optimal configuration, different topology combinations were evaluated, including NCS, NCA, and NBCA, i.e., Neutralized Bootstrapped Cascode Amplifier. Load-pull simulations were performed to maximize PAE. Results show that an NCS-based driver and output stage provides the highest efficiency.

Although the two-stage NCS+NCS UA provided a favorable trade-off between gain and efficiency, it did not fully meet system-level requirements due to two main limitations: challenging input matching and insufficient overall gain. In the two-stage configuration, the first-stage NCS device with a total gate width of 115.2 µm, exhibits a low, capacitive input impedance (≈ 7 + j57Ω). When four UAs are paralleled, the input impedance seen from the splitter drops to (≈ 1.75 + j14.25Ω), making matching to a 50Ω source extremely difficult. This requires a high-ratio (≈ 25 : 1) impedance transformation, which is sensitive to bandwidth, losses, and process variations. Moreover, the total gain of the two-stage UA (≈ 13.8 dB) becomes insufficient once splitter and combiner losses are considered, falling short of the 15 dB required at the system level.

To address both issues, a third amplification stage was introduced at the UA input. This predriver stage adopts an NCA topology which offers a higher input impedance given its smaller gate width size of 19.2 µm, thus relaxing input matching constraints. The NCA also provides higher gain than the NCS topology, making it a more effective choice for this stage, where gain is the primary design criterion. Furthermore, this additional stage maintains a high overall PAE. Indeed, the PAE of the unit amplifier can be expressed as,

$$PAE_{UA} = \frac{G_3 L_2 L_1 G_2 - 1/G_1}{1/DE_1 + (L_1 G_2)/DE_2 + G_3 L_1 L_2 G_2/DE_3} \quad (1)$$

where $G_1$, $G_2$ and $G_3$ are the power gains of predriver, driver and output stages, respectively, $DE_1$, $DE_2$ and $DE_3$ are their drain efficiencies, and $L_1$, $L_2$ the insertion losses of the matching networks between these stages. As shown in (1), the drain efficiency of the first stage $DE_1$ has a limited impact on the total PAE, not only due to its position in the gain chain, but also because its power consumption is very low. As a result, its contribution to total consumption is negligible, while its gain plays a fundamental role in reducing the required input drive power.

Integrated transformers are used for inter-stage matching, reducing size and enabling DC biasing. Passive components are used to efficiently manage signal splitting and combining. The differential input signal is initially distributed using transformer-based dividers as shown in Fig. 2, which further partition the signal across the four paths of the PA. To minimize signal loss by the substrate, the transmission lines (TLs) are designed with a slow-wave structure.

For the combination of the output signals from the 4 PA units, the design adopts a similar approach used in earlier CMOS technologies [20]. The power combiner is composed of two transformer-based combiners and a combining TL as presented in Fig. 3. The differential input signals are connected through half-primary windings made of thick metal layers to improve coupling and reduce loss. A tap-bar connecting the two half windings ensures uniform bias across the PA output stages. The secondary winding, implemented in the thickest metal layer, further minimizes resistive losses. The interested reader is referred to [19] for a more detailed description of the PA design.
<figure><img src="image_3.png" /><figcaption>Fig. 1. General block diagram of the proposed PA with built-in calibration capabilities.</figcaption></figure>

<figure><img src="image_4.png" /><figcaption>Fig. 2. Transformer-based power divider configuration.</figcaption></figure>

<table><caption>TABLE I
PA PERFORMANCE GOALS AND MEASUREMENT RESULTS FOR A REPRESENTATIVE FABRICATED SAMPLE</caption><thead><tr><td>Specification</td><td>Design target @79 GHz</td><td>Measurement</td></tr></thead><tbody><tr><td>PAE (%)</td><td>&gt; 16</td><td>20</td></tr><tr><td>DE (%)</td><td>&gt; 16</td><td>20</td></tr><tr><td>P<sub>sat</sub> (dBm)</td><td>&gt; 15</td><td>17</td></tr><tr><td>Gain@PAE<sub>max</sub>(dB)</td><td>&gt; 15</td><td>22.4</td></tr><tr><td>Power(mW)</td><td>&lt; 300</td><td>255</td></tr></tbody></table>

The PA has been designed and fabricated in a 28 nm CMOS technology. Table I lists the design goals of the PA together with the measurement results obtained in the laboratory from a representative fabricated sample. The measured performance of the fabricated PA is comparable to the state-of-the-art integrated PAs in sub-65 nm CMOS technologies [20]–[25], and the design presents a very low sensitivity to process variations to comply with strict industrial quality standards.

This, together with the relative complexity of the 4-way PA architecture (especially if we compare to previous work on nonintrusive calibration [5], [7] featuring a single-channel demonstrator), makes the developed PA a quite challenging case study for the proposed test and calibration strategies.

## B. Design of Tuning Knobs

Providing performance calibration capabilities requires the addition of suitable tuning knobs that can compensate for the expected performance degradation mechanisms affecting our PA case study. In this regard, significant design effort was devoted to minimize the impact of fabrication mismatch between the four differential signal paths. Thus, the PA layout ensures symmetry in the four parallel paths differential, carefully matching the geometries and minimizing parasitic imbalances. As a metric of this imbalance, post-layout simulations confirmed that the output impedances of the four branches exhibit minimal sensitivity to mismatch. The results show that the real and imaginary parts of each branch output impedance vary by less than 0.7 Ω, while the impedance difference between the four different branches varies by less than 1.5 Ω for the real part and less than 2 Ω for the imaginary part. The limited impact of local mismatch makes global process variations the main source of performance degradation in fabrication. Hence, global tuning knobs for the complete PA, shared for the four signal paths, can be used, which greatly simplify their design. In the same way, the built-in test instruments and the nonintrusive process monitors that will be presented
<figure><img src="image_5.png" /><figcaption>Fig. 3. Transformer-based power combiner configuration combining 4-Unit Amplifiers.</figcaption></figure>

in Sections III-C and III-D, are not required to be sensitive to
local mismatch.

In this work, we propose to employ the bias currents and
supply voltages of the pre-driver, driver and output stages as
tuning knobs. Since they control the DC operation point of
the amplification stages, they have a dramatic impact in PA
performance and can be employed for calibration purposes.
However, resorting to controlling bias currents and voltages
avoids significant modifications to the PA design or the use of
complex programmable passive elements that may introduce
additional electrical losses [2]–[4], [7].

The available bias currents and supply voltages that can be
potentially employed as tuning knobs are $I_{pd}$, $V_{DD\_pd}$, $V_{DD\_d}$,
$I_{out}$ and $V_{DD\_out}$, which stand for the bias current of the pre-
driver and the first driver stage, the supply voltage of the pre-
driver stage, the supply voltage of the driver stage, the bias
current of the output stage and the supply voltage of the output
stage, respectively, as depicted in Fig. 1.

Extreme corner simulation and Monte Carlo analysis were
performed to determine both the expected variation ranges
for each of the PA performances and the appropriate vari-
ation range for each tuning knob in order to correct these
variations. The results of the analysis are shown in Table
II. A performance range is obtained for the variations of
each individual tuning knob, and a normalized performance
sensitivity is calculated in each case. The tuning knob variation
ranges were carefully designed to cover the full expected
performance space under manufacturing variations. The nor-
malized sensitivity is defined as the relative variation of
performance over the relative variation of a single tuning knob,
when all other tuning knobs are kept at their nominal values.
These nominal values correspond to post-layout simulations
of a sample in the typical corner of the technology and are
given by $I_{pd} = 120~\mu\text{A}$, $V_{DD\_d} = 0.75~\text{V}$, $I_{out} = 230~\mu\text{A}$,
$V_{DD\_out} = 0.9~\text{V}$, and $V_{DD\_pd} = 1.5~\text{V}$.

In order to select the most relevant tuning knobs for the PA
under calibration, we ranked the candidate tuning knobs using
a weighted average of their associated normalized sensitivities.
The coefficients of the weighted average are defined according
to the importance of each specification in the target radar

application. Namely, the gain gets a normalized weight of one,
the *PAE* and *DE* a normalized weight of two and the output
power a normalized weight of six. Since the output power
at maximum *PAE* conditions is deemed as the most critical
specification, tuning knob $V_{DD\_pd}$ was discarded due to its
limited impact on this performance.

The final design includes four tuning knobs: $I_{pd}$, $V_{DD\_d}$,
$I_{out}$ and $V_{DD\_out}$. Specifically, three discrete values were
chosen for $V_{DD\_d}$ and $V_{DD\_out} \in \{0.75 \text{ V}, 0.825 \text{ V}, 0.9 \text{ V}\}$,
while four discrete values were selected for
$I_{pd} \in \{60 \mu\text{A}, 120 \mu\text{A}, 180 \mu\text{A}, 240 \mu\text{A}\}$ and
$I_{out} \in \{110 \mu\text{A}, 170 \mu\text{A}, 230 \mu\text{A}, 290 \mu\text{A}\}$.

To further validate the choice of tuning knobs, Table III
lists the attainable performance values for the PA, obtained
by simulation at the typical corner considering all possible
combinations of the four tuning knobs. Unlike Table II, where
a single tuning knob is varied at a time, Table III captures the
combined impact of jointly adjusting all four parameters. The
reported minimum and maximum values reflect the extreme
performance points achievable through tuning under nominal
conditions. As can be seen, the available tuning range is wider
than the observed process variation range. Finally, to guarantee
a stable operation in the considered tuning range, harmonic
balance simulations were performed incorporating loop gain
extraction, capturing both gain and phase margins. The results
confirmed that all tuning knob configurations remain stable,
with adequate phase and gain margins, even under worst-case
bias combinations. Notably, stability verification was carried
out at -40 °C, representing the most critical operating temper-
ature for loop gain degradation, thereby ensuring robustness
under the most challenging thermal conditions.

In this work, these voltages and currents are supplied
externally, but the design is fully compatible with an on-chip
implementation using low-resolution digital-to-analog convert-
ers (DACs) for a fully on-chip calibration solution.

### C. Ring Oscillator-Based Nonintrusive Process Control Monitors

In order to track process variations, previous works on non-
intrusive mm-wave test and calibration rely on a set of stand-
<table><caption>TABLE II
VARIATION RANGE AND NORMALIZED SENSITIVITIES FOR EACH TUNING KNOB</caption><thead><tr><th>Tuning Knob</th><th>Performance</th><th>Min</th><th>Max</th><th>S<sub>norm</sub>(%)</th></tr></thead><tbody><tr><td rowspan="4">I<sub>pd</sub> ∈ [60μA, 240μA]</td><td>PAE (%)</td><td>17.2</td><td>20.9</td><td>19.4%</td></tr><tr><td>DE (%)</td><td>17.5</td><td>21.1</td><td>18.8%</td></tr><tr><td>P<sub>out</sub>@PAE<sub>max</sub> (dBm)</td><td>14.3</td><td>16.4</td><td>13.9%</td></tr><tr><td>Gain@PAE<sub>max</sub> (dB)</td><td>18.2</td><td>20.4</td><td>11.6%</td></tr><tr><td rowspan="4">I<sub>out</sub> ∈ [110μA, 290μA]</td><td>PAE (%)</td><td>20.1</td><td>21.5</td><td>7.4%</td></tr><tr><td>DE (%)</td><td>20.3</td><td>21.7</td><td>7.6%</td></tr><tr><td>P<sub>out</sub>@PAE<sub>max</sub> (dBm)</td><td>15.8</td><td>16.7</td><td>6.2%</td></tr><tr><td>Gain@PAE<sub>max</sub> (dB)</td><td>19.8</td><td>20.6</td><td>4.5%</td></tr><tr><td rowspan="4">V<sub>DD_d</sub> ∈ [0.75V, 0.9V]</td><td>PAE (%)</td><td>20.1</td><td>20.9</td><td>20.6%</td></tr><tr><td>DE (%)</td><td>20.3</td><td>21.1</td><td>20.2%</td></tr><tr><td>P<sub>out</sub>@PAE<sub>max</sub> (dBm)</td><td>16.2</td><td>16.5</td><td>9.0%</td></tr><tr><td>Gain@PAE<sub>max</sub> (dB)</td><td>20.2</td><td>20.5</td><td>8.1%</td></tr><tr><td rowspan="4">V<sub>DD_out</sub> ∈ [0.75V, 0.9V]</td><td>PAE (%)</td><td>20.9</td><td>22.3</td><td>35.7%</td></tr><tr><td>DE (%)</td><td>21.1</td><td>22.4</td><td>34.6%</td></tr><tr><td>P<sub>out</sub>@PAE<sub>max</sub> (dBm)</td><td>16.2</td><td>17.2</td><td>33.5%</td></tr><tr><td>Gain@PAE<sub>max</sub> (dB)</td><td>20.2</td><td>21.2</td><td>27.0%</td></tr><tr><td rowspan="4">V<sub>DD_pd</sub> ∈ [1.4V, 1.6V]</td><td>PAE (%)</td><td>20.7</td><td>21.0</td><td>10.0%</td></tr><tr><td>DE (%)</td><td>20.9</td><td>21.2</td><td>10.0%</td></tr><tr><td>P<sub>out</sub>@PAE<sub>max</sub> (dBm)</td><td>16.2</td><td>16.2</td><td>1.3%</td></tr><tr><td>Gain@PAE<sub>max</sub> (dB)</td><td>20.1</td><td>20.2</td><td>2.6%</td></tr></tbody></table>

<table><caption>TABLE III
TUNING RANGE AND EXPECTED PERFORMANCE VARIATION</caption><thead><tr><th rowspan="2"></th><th colspan="2">Tuning range</th><th colspan="2">Process variation</th></tr><tr><th>min.</th><th>max.</th><th>worst</th><th>best</th></tr></thead><tbody><tr><td>PAE (%)</td><td>16.0</td><td>23.0</td><td>19.2</td><td>21.8</td></tr><tr><td>DE (%)</td><td>16.2</td><td>23.2</td><td>19.4</td><td>22.0</td></tr><tr><td>P<sub>out</sub>@PAE<sub>max</sub> (dBm)</td><td>13.7</td><td>18.2</td><td>15.7</td><td>16.5</td></tr><tr><td>Gain@PAE<sub>max</sub> (dB)</td><td>17.6</td><td>22.2</td><td>19.7</td><td>20.7</td></tr></tbody></table>

<figure><img src="image_6.png" /><figcaption>Fig. 4. (a) Ring oscillator block diagram. (b) Schematic of the implementation of 15 ring oscillators for process monitoring.</figcaption></figure>

alone test structures (transistors, transmission lines, capacitors, etc.) that have to be individually characterized with dedicated DC and low-frequency AC measurements in a probe station [5]–[7]. In this work, we propose a more efficient implementation of the process control monitors based on especially crafted digital ring oscillators. Indeed, ring oscillators have been proposed for monitoring transistor variations (threshold voltage, parasitic capacitance, etc.) and are routinely employed to recenter the performance of digital integrated circuits [26]–[28]. In this work, we extend ring oscillator-based process variation monitoring to the mm-wave domain.

Fig. 4 shows a conceptual schematic of the proposed ring oscillator-based process control monitors. The system has been developed internally at NXP as a generic IP for tracking the variations of technological parameters in RF/mm-wave integrated circuits. It consists of an array of 15 digital inverter-based ring oscillators. Two of these oscillators are reference oscillators composed only by digital inverters, while the rest have been modified by loading its internal nodes with different circuit elements, labeled as DUM (Devices Under Measurement). The reference oscillators are used to isolate intrinsic ring oscillator variability from that introduced by the load. The 13 skewed ring oscillators are intentionally loaded to target the main sources of process variation affecting mm-wave active and passive circuit performance, with each structure emphasizing either FEOL or BEOL effects. FEOL sensitive loads include LVT NMOS and PMOS transistors, designed to capture threshold voltage shifts and gate contact variations. BEOL oriented loads include fringe capacitors (for monitoring metal height, pitch and dielectric thickness), plate capacitors

(related to IMD thickness), CICMOM capacitors (for detecting mismatch in dense capacitive structures), and resistive via stacks (to capture interconnect resistance variations). Table IV summarizes the classification of the 15 ring oscillators according to their integration layer. This diversity enables the monitoring system to capture a wide range of variations affecting different layers of the chip, thereby improving the correlation between process variations and RF performance.

The sizing and biasing (for active devices) of the different loads have been optimized to maximize the sensitivity of the oscillation frequency to process variations. Due to confidentiality reasons, we cannot show a more detailed schematic of these structures. The frequency of the resulting oscillators is a signature of the different process variation mechanisms affecting the performance of the PA under calibration. Digital control signals enable and select the output of each oscillator for connection to a frequency divider (division factor of 512) and measurement of the output oscillating signal. The frequency of the signal can be easily extracted using a conventional oscilloscope off-chip, or by a simple on-chip digital counter.

Compared to previous nonintrusive monitoring techniques based on a variety of analog measurements on a probe station, the approach based on ring oscillators offers a simplified, efficient and digital-friendly approach for tracking process variations in mm-wave ICs.

<table><caption>TABLE IV
CLASSIFICATION OF THE RING OSCILLATORS BASED ON THEIR STRUCTURAL AND FUNCTIONAL CHARACTERISTICS</caption><thead><tr><th>Category</th><th>Ring oscillators</th></tr></thead><tbody><tr><td>FEOL (contacts)</td><td>ringo<sub>2</sub>, ringo<sub>10</sub>, ringo<sub>11</sub></td></tr><tr><td>BEOL (vias, fringe)</td><td>ringo<sub>1</sub>, ringo<sub>4</sub>, ringo<sub>7</sub>, ringo<sub>8</sub>, ringo<sub>12</sub>, ringo<sub>14</sub></td></tr><tr><td>BEOL (plate capacitors)</td><td>ringo<sub>3</sub>, ringo<sub>6</sub>, ringo<sub>13</sub></td></tr><tr><td>BEOL (MOM capacitors)</td><td>ringo<sub>15</sub></td></tr><tr><td>Reference oscillators</td><td>ringo<sub>5</sub>, ringo<sub>9</sub></td></tr></tbody></table>
## D. Built-In Test Instruments

The ring oscillator-based process control monitors allow tracking the effect of process variations on the circuit under calibration. However, since the process monitors are not actually connected to the circuit, any local disturbances affecting the circuit, such as mismatch or local defects, even if they lead to non-functional PAs, will not be detected. This limitation, common to previous work on nonintrusive test and calibration [5]–[7], [17], is not acceptable in an industrial level IC targeting a safety-critical application such as automotive. For this reason, in this work we introduce built-in test instruments that complete and complement the test information provided by the process monitors.

The proposed built-in test instruments form an on-chip reflectometer shown in Fig. 1. This test instrument is mainly targeted at detecting both catastrophic defects and impedance mismatch issues at the output of the PA due to the connection to the antenna. A Dual Directional Coupler (DDC) is integrated in the PA output line. It consists of two back-to-back directional couplers separating the RF signal into incident and reflected signals, allowing the magnitude and phase of the reflection coefficient to be computed with the help of two passive mixers and two Peak Power Detectors (PPDs). Intrusive sensors are known to degrade the performance of the circuit under test, especially when inserted on RF paths. For these reasons, the coupler is designed to minimize its impact on the output power. In this regard, the designed dual directional coupler has a low insertion loss of 0.9 dB, a reverse isolation of 30 dB, a coupling coefficient of 13 dB and a directivity of 20 dB. Two power detectors are required for sensing the incident and reflected signals. These detectors are standard diode-based peak power detectors. The diode operates under reverse bias, allowing it to conduct half of the time. The signal is rectified by the diodes and then passed through an RC low-pass filter to smooth the rectified signal. The PPDs consume 0.3 mW.

The mixers are passive differential double-balanced rectifiers, as shown in Fig. 5, known for their high linearity, low flicker noise and minimal power consumption compared to active mixers. Each mixer consists of four NMOS switches, where the RF signal is applied to the drains, LO signals control the gates, and the IF signal is extracted from the sources. Resistors $R_1$ and $R_2$ help to reduce voltage swing, ease power matching and improve RF-LO isolation. The interested reader is referred to [29] for a more detailed description of the reflectometer design.

In order to optimize the trade-off between the conversion loss and the noise factor of the mixers, the LO signal level was set to 10 dBm and an IF of 100 kHz was chosen. Electrical transistor-level simulations of the mixers demonstrate a conversion loss of 4.5 dB and an input-referred 1-dB compression point of -1 dBm. The simulated dynamic range is 107 dB. Since the mixers perform vectorial measurements, they can assess circuit mismatch through the reflection coefficient value, which depends on the incident and reflected mixer output

<figure><img src="image_7.png" /><figcaption>Fig. 5. Passive mixer schematic.</figcaption></figure>

signals as follows

$$ \Gamma = \frac{V_L^-}{V_L^+} = |\Gamma|(\cos(\phi) + j \sin(\phi)) \quad (2) $$

where $V_L^+$ is the incident wave, $V_L^-$ is the reflective wave, and $|\Gamma|$ and $\phi$ denote the reflection coefficient magnitude and phase, respectively.

Although the integration of a built-in mixer may apparently make the Power Peak Detectors redundant (the same information is certainly provided by the mixer), in our context, the inclusion of the PPDs have three significant advantages. The PPDs yield a DC signature that can be extracted with a simpler setup than the mixer measurements. These cheap signatures can be used for early and cheap identification of faulty devices, as it will be shown in Section IV-A1. Moreover, both the PPD and mixer signatures will be employed to guide our machine learning-based calibration algorithm. As it is well known, considering different measurements of the same physical magnitude will actually improve the prediction models. Measurement noise will be naturally reduced and the sensitivity to variations will be increased. Finally, the presence of the PPDs relaxes the design constraints on the mixer. While the mixer performs better at low input power, the PPDs are more accurate near saturation. This is particularly relevant for automotive radar applications, where the PA typically operates close to saturation, making the inclusion of the PPDs essential to maintain high prediction accuracy in the target operating region.

# IV. MACHINE LEARNING-BASED TEST AND CALIBRATION TECHNIQUES

## A. Defect Detection and Output Matching Evaluation

The inclusion of built-in test instruments has multiple purposes in the proposed test and calibration strategy. Their sensitivity to local variations and fabrication defects affecting the PA circuitry not only enhances the accuracy of the calibration, as will be shown in Section IV-B, but it also enables filtering non-functional devices from entering the calibration stage. The latter is a fundamental improvement with respect to previously presented non-intrusive test and calibration strategies. A faulty circuit containing catastrophic fabrication defects cannot be detected nor calibrated by non-intrusive methods, that will
only track and correct global process variations. Indeed, a defect filter is always necessary for any test and/or calibration strategy based on machine learning predictions: since these methodologies only track variations of defect-free devices, predictions from a device containing physical defects would be meaningless. Moreover, detecting defective chips early is essential to prevent them from interfering with the calibration process and corrupting machine learning models with misleading data.

Unless additional intrusive testing (i.e., actually tapping into the signal path) is performed to screen local defects, non-intrusive test and calibration would result in test escapes, incorrect calibration models, and, ultimately, in shipping non-functional circuits to customers. In this work, we propose to employ the statistical properties of the signatures generated by the built-in test instruments to enable local defect detection and output matching evaluation.

1) Defect Detection: In order to enable defect detection, we employ the two DC signatures generated by the built-in peak-power detectors, $PPD_{inc}$ and $PPD_{reflect}$, to build a defect filter [30]–[32]. A defect filter is an algorithm that evaluates some statistical properties of the available signatures to identify devices that contain defects. The rationale of the method is that a device containing a local fabrication defect generates test signatures that are far from the expected distribution of test signatures corresponding to process variations. Signatures from faulty devices are expected to be outliers with respect to the process variation distribution of fault-free devices.

In this work, we propose a simple implementation of a defect filter as a k-filter outlier detection algorithm [32]. The k-filter is built as follows. Firstly we evaluate the considered signatures $S_{k-filter} = [PPD_{inc}, PPD_{reflect}]$ for a set of known good dies under nominal positions of the tuning knobs. (The nominal positions of the tuning knobs are defined in the design stage as the optimal positions of the tuning knobs under typical corner conditions.) Then, we consider the mean $\mu_{k-filter} = [\mu_1, \mu_2]$ and standard deviation $\sigma_{k-filter} = [\sigma_1, \sigma_2]$ of the two signatures. Formally, we can then define a k-filter in the space of signatures as the rectangle $H_{k-filter}$ described as,

$$H_{k-filter} = [\mu_1 \pm k\sigma_1, \mu_2 \pm k\sigma_2] \quad (3)$$

where k is a positive real number. All PAs whose signatures for nominal positions of the tuning knobs fall outside of the $H_{k-filter}$ rectangle are considered as outliers and probably faulty. These samples should be screened from the calibration and either discarded or sent to additional test programs.

2) Output matching evaluation: Local process variations affecting the PA and imperfections in the connection to the transmitting antenna may lead to impedance mismatch at the output of the PA. This mismatch can cause efficiency losses and signal distortions. Non-intrusive signatures cannot capture this local effect, which, again, would lead to incorrect test and calibration results. The built-in reflectometer can be employed to evaluate the output matching in terms of the reflection coefficient, $\Gamma$, by measuring the magnitude and phase of the incident and reflected waves, as in (2). However, the direct measurement of the reflection coefficient requires a complex measurement calibration procedure to compensate

the nonideality of the dual directional coupler that introduces a phase error, and the mixer circuitry that has a nonlinear behavior across its input range. Compensating these effects requires calibrating the phase and magnitude response of the reflectometer, which is a lengthy procedure, such as the 3-term calibration proposed in [29], [33], [34], requiring multiple measurements and hence not suitable for production test.

In the present work we propose to predict the magnitude, $|\Gamma|$, and phase, $\phi$, of the reflection coefficient from the mixer signatures, $S_{output_match}$ = [mixer$_{inc_IF}$, mixer$_{reflect_IF}$, mixer$_{\phi_IF}$], where mixer$_{\phi_IF}$ denotes the phase difference between the reflected and incident mixer outputs, with the help of a machine learning regression function. This regression function is built in two stages.

In a first stage, the training stage, we use a load-pull measurement setup on a set of known good dies using an impedance tuner to set a known output impedance condition. The signatures $S_{output_match}$ are extracted and the magnitude and phase of the reflection coefficient are evaluated. This data is then employed to train three regression functions, as,

$$|\Gamma| = f_1(S_{output_match}) \quad (4)$$

$$\cos(\phi) = f_2(S_{output_match}) \quad (5)$$

$$\sin(\phi) = f_3(S_{output_match}) \quad (6)$$

In this way, we avoid complex reflectometer calibration procedures since the mapping between the mixer outputs and the actual reflection coefficient is learned in the training stage. In this work, the regression functions $f_1$, $f_2$ and $f_3$ are approximated using a machine learning regression model. The choice of the regression model is driven by the trade-off between model simplicity and prediction accuracy. Simple lightweight models behave better in scenarios with scarce data, require less computing resources and allow for fast evaluation. However, a too simplistic model would not be able to capture the nonlinear multidimensional link between signatures and target performances, yielding poor generalization capabilities. In this work, we considered a multilayer perceptron model with fully connected layers of neurons. Multilayer perceptrons are complex enough to capture nonlinear behavior while remaining computationally efficient [35], [36].

In a second stage, the testing stage, only the signatures are measured and the magnitude and phase of the reflection coefficient are predicted using (4)-(6). A key advantage of this approach is its ability to perform vectorial measurements, providing both amplitude and phase information for accurate monitoring of PA performances.

## B. One-Shot Calibration Strategy

As previously described, the proposed PA architecture integrates four tuning knobs $I_{pd}$, $V_{DD_d}$, $I_{out}$ and $V_{DD_out}$, to calibrate the performance of the pre-driver, driver and output stages, with their discrete values carefully selected based on corner and Monte Carlo simulations.

The proposed calibration strategy is aimed at predicting, from the available signatures generated by the ring oscillators
and the on-chip reflectometer, which is the optimum configura-
tion of tuning knobs for maximizing Power Added Efficiency
(PAE) and Drain Efficiency (DE), while complying with the
minimum design target for the saturation output power ($P_{sat}$)
and power gain ($G_p$).

Formally, the calibration of a particular sample *i* can be
described as an optimization problem such as

$$
\max_{\mathbf{T}} (\mathrm{PAE}_i(\mathbf{T})) \qquad (7)
$$

$$
\max_{\mathbf{T}} (DE_i(\mathbf{T})) \qquad (8)
$$

with the constraints

$$
P_{sat,i}(\mathbf{T}) > P_{sat\_min} \qquad (9)
$$

$$
G_{p,i}(\mathbf{T}) > G_{p,\min} \qquad (10)
$$

$$
\mathbf{T} \in \mathbf{T}^* \qquad (11)
$$

where **T** is the vector of tuning knobs **T** =
($I_{pd}$, $V_{DD\_d}$, $I_{out}$, $V_{DD\_out}$), $P_{sat\_min}$ and $G_{p\_min}$ are
the minimum design targets for the PA output saturation
power and power gain, respectively, and **T**\* is the space
of 144 combinations of possible tuning knob values. The
unknown functions $PAE_i(\mathbf{T})$, $DE_i(\mathbf{T})$, $P_{sat,i}(\mathbf{T})$ and $G_{p,i}(\mathbf{T})$
represent the variations of the PA specifications as a function
of the tuning knob values, for the particular sample *i*. Notice
that in general, due to sample-to-sample process variations,
these functions will be different for each sample.

In order to solve the described optimization problem, in
this work we propose to employ machine learning regression
algorithms to approximate these functions from the set of
available indirect signatures, i.e.,

$$
PAE_i(\mathbf{T}) = PAE(\mathbf{S}, \mathbf{T})|_{\mathbf{S}=\mathbf{s}_i} \qquad (12)
$$

$$
DE_i(\mathbf{T}) = DE(\mathbf{S}, \mathbf{T})|_{\mathbf{S}=\mathbf{s}_i} \qquad (13)
$$

$$
P_{sat,i}(\mathbf{T}) = P_{sat}(\mathbf{S}, \mathbf{T})|_{\mathbf{S}=\mathbf{s}_i} \qquad (14)
$$

$$
G_{p,i}(\mathbf{T}) = G_p(\mathbf{S}, \mathbf{T})|_{\mathbf{S}=\mathbf{s}_i} \qquad (15)
$$

where functions X(S, T) are regression functions that allow
the prediction of the performance figures from the measured
signatures S and the position of the tuning knobs T. For
a given sample i, particularizing to S = Sᵢ, we obtain an
approximation of the i-th PA performance figures as a function
of the tuning knob positions Xᵢ(T).

The complete calibration process comprises two main
stages: a training stage and a calibration stage. The training
stage is aimed at building the regression functions X(S, T).
These regression functions are here built using supervised
machine learning techniques. That is, for a reduced set of
fabricated PA samples, i.e., the training set, typically the
set of pre-production samples, both the signatures and the
PA specifications are measured under different tuning knob
configurations. Then, a multilayer perceptron regressor is
employed to find the mapping function between signatures,
tuning knobs and PA performance figures. In order to improve
the accuracy of the regression, in this work, a pre-processing
stage is added before the training to select which signatures
are actually relevant for each of the PA specifications. Indeed,
not all the signatures would be relevant for the prediction of
all the PA specifications. This process is denoted as feature

selection in the machine learning literature and allows for the
removal of non-relevant, redundant or noisy information in
the signature set, significantly improving the accuracy of the
resulting regression functions [35].

The proposed calibration algorithm is guided by 19 signa-
tures provided by the proposed process control monitors and
built-in instruments: 15 extracted from the digital ring oscilla-
tors, 2 from PPDs and 2 from the mixers. The feature selection
stage is implemented as a Brownian distance correlation-
directed search [37] in this space of 19 signatures. This feature
selection algorithm ranks the available signatures according
to their relevance for predicting each of the considered four
PA specifications. The subsets of selected signatures are then
employed to train perceptron neural networks to obtain the
regression functions (12)-(15).

In the calibration stage, for the rest of the production
samples of the PA, only the signatures are measured. Since
the perceptron predictive models are very lightweight and
the number of available combinations of the tuning knobs is
limited, we can simply approximate functions (12)-(15) in all
the 144 possible combinations to evaluate the complete tuning
space for each particular sample. The calibrated state is then
chosen as the tuning knob combination that complies with
our design optimization targets and constraints (7)-(11) and
that minimizes power consumption. This way, the calibration
problem is solved without the need of a test-and-tune calibra-
tion loop.

It should be noticed that in a more complex problem,
an optimization algorithm may be necessary to efficiently
navigate the tuning space, if a complete evaluation is not
computationally feasible. Multiple multi-objective optimizers
suitable for this task are already available in the literature [38],
[39].

From a cost perspective, replacing traditional test-and-tune
calibration loops based on functional measurements by the
proposed one-shot calibration may bring a significant cost
reduction. Following the formalism in [7], the cost of the
proposed machine learning-based calibration, $C_{ML}$, can be
expressed as,

$$
\begin{align}
C_{ML} &= C_{train} + C_{cal} \tag{16} \\
&= N_T (N_C F + S_{ni} + N_C S_i) + (N - N_T) (S_{ni} + N_C S_i) \nonumber
\end{align}
$$

where $C_{train}$ is the cost associated to the training stage, $C_{cal}$ is the cost associated to the calibration stage, $N_T$ is the number of training samples, $N_C$ is the number of possible tuning knob combinations, $N$ is the total number of fabricated samples in the production, $F$ is the cost of functional performance characterization, $S_{ni}$ is the cost of measuring the non-intrusive signatures provided by the ring oscillators, and $S_i$ is the cost of measuring the intrusive signatures provided by the reflectometer and PPDs. This cost can be directly compared to the cost of a standard test-and-tune calibration loop, $C_{iter}$ that can be expressed as,

$$
C_{iter} = N N_{iter} F. \qquad (17)
$$

In a typical application scenario, $N \gg N_T$, and the cost
associated to $S_i$ and $S_{ni}$, that only require low-frequency or
DC equipment, is significantly lower than the cost *F* of a
complete functional characterization at mm-wave frequencies.

V. EXPERIMENTAL RESULTS

The proposed PA was designed and manufactured using 28 nm CMOS technology. A micrograph of one of the fabricated chips is shown in Fig. 6, highlighting the placement of the non-intrusive process monitors, the built-in test instruments and the PA itself. The built-in test instruments, consisting of PPDs and mixers are connected to the output of the PA, while the non-intrusive process monitors (i.e., the digital ring oscillators), are positioned in the close proximity of the PA to experience the same process variations. The chip includes three RF pads accessible through GSG probes: two are allocated for the input and output signals of the PA, while the third one is reserved for the local oscillator (LO) signal, which is required for driving the mixer switches, allowing the generation of the IF signal at a frequency of 100 kHz. DC pads are wire-bonded to a Printed Circuit Board (PCB). Baluns are employed to convert the PA differential input and output signals into single-ended, which is then measured using GSG probes. The PA occupies a total area of 0.39 mm², while the reflectometer occupies 0.33 mm², highlighted in blue in Fig. 6, and the ring oscillators, highlighted in green, occupy 0.12 mm². The rest of the silicon area, that actually accounts for the majority of the chip area in Fig. 6, includes additional passive structures employed for pad de-embedding (Open, Short, Load, Thru, Delay) and the PA input and output baluns. These structures will not be included when the PA is integrated in a complete transceiver.

A total of 32 samples from the same wafer were measured in our characterization laboratory. The locations of the measured chips on the wafer are detailed in Fig. 7. The locations of the measured chips on the wafer are detailed in Fig. 7. These chips were selected from various positions on the wafer, including center devices like chips number 30, 31, and 21, as well as chip number 2, which is one of the complete chips closest to one of the edges. This selection ensures a reasonable representation of the process variations observed across a typical wafer.

The signals from the PPDs are measured using multimeters connected to the auxiliary board via SMB connectors, while the signals from the mixers and the ring oscillators are analyzed with a Real-Time Oscilloscope (RTO 2044).

A. Characterization of the PA at Nominal Tuning Knob Positions

Firstly, the fabricated PA samples are characterized under nominal positions for the tuning knobs. The measured large signal characteristics are depicted in Fig. 8 as a function of the PA input power for the 32 fabricated samples. Then, the PA performance has been characterized in the operating conditions, i.e., for an input power of -5 dBm corresponding to maximum *PAE* conditions. The obtained minimum and maximum performance results across the 32 fabricated samples are listed in Table V and compared to the state-of-the-art of 4-way PAs integrated in sub-65 nm CMOS technologies. As can be seen, all considered samples comply with the design

<figure><img src="image_8.png" /><figcaption>Fig. 6. Micrograph of the fabricated chip. The PA is highlighted in red, the reflectometer in blue, and the ring oscillators in green.</figcaption></figure>

<figure><img src="image_9.png" /><figcaption>Fig. 7. Measured chips within the wafer (in blue color).</figcaption></figure>

targets defined in Table I and obtained results are competitive compared to the state-of-the-art. Additionally, the observed variations of gain, $G_p$, and saturation output power, $P_{sat}$, are fairly contained as expected in an industrial design. Significant variations are, however, observed in the *PAE* at maximum efficiency conditions for the different samples.

B. One-Shot Calibration

In view of the results in Fig. 8, since all the considered samples are within the target design specifications, the goal of the calibration algorithm will be to recenter the performance

<table><caption>TABLE V
MEASURED PA PERFORMANCE AT NOMINAL TUNING KNOB POSITIONS AND COMPARISON WITH THE STATE-OF-THE-ART</caption><thead><tr><th>Specification</th><th>This work (min - max)</th><th>[20]</th><th>[21]</th><th>[22]</th><th>[23]</th><th>[24]</th><th>[25]</th></tr></thead><tbody><tr><td>Frequency (GHz)</td><td>79</td><td>73</td><td>60</td><td>60</td><td>60</td><td>77</td><td>80</td></tr><tr><td>Technology (nm)</td><td>28</td><td>45</td><td>65</td><td>65</td><td>65</td><td>40</td><td>40</td></tr><tr><td>G<sub>p</sub> @ PAE<sub>max</sub> (dB)</td><td>22.0 - 22.6</td><td>25.3</td><td>29.7</td><td>32.4</td><td>28.0</td><td>12.0</td><td>18.0</td></tr><tr><td>P<sub>out</sub> @ PAE<sub>max</sub> (dBm)</td><td>16.7 - 17.3</td><td>22.6</td><td>23.7</td><td>19.9</td><td>19.7</td><td>20.2</td><td>20.9</td></tr><tr><td>PAE<sub>max</sub> (%)</td><td>18 - 21</td><td>19.3</td><td>22.1</td><td>20</td><td>13.4</td><td>18</td><td>22.3</td></tr><tr><td>Power (mW)</td><td>252 - 260</td><td>182</td><td>235</td><td>510</td><td>NA</td><td>NA</td><td>375</td></tr><tr><td>Area (mm<sup>2</sup>)</td><td>0.39**</td><td>0.25*</td><td>0.65**</td><td>0.32**</td><td>0.32**</td><td>0.152**</td><td>0.19*</td></tr></tbody></table>

<footnote>*:with pads; **:without pads</footnote>
<figure><img src="image_10.png" /><figcaption>Fig. 8. Measured large signal performance for 32 chips under nominal bias conditions : $I_{pd}$ = 120 µA, $V_{DD\_d}$ = 0.75 V, $I_{out}$ = 230 µA, and $V_{DD\_out}$ = 0.9 V.</figcaption></figure>

of each sample at the operation frequency of 79 GHz in order to maximize its power efficiency, i.e., *PAE* and *DE*, while complying with the minimum target output power and gain specifications. As presented above, the proposed calibration methodology comprises three main stages, feature selection, model training and performance calibration.

1) Feature Selection: As advanced earlier, before training the regression functions, in this work we perform a feature selection pre-processing to improve the efficiency and accuracy of the regression functions. A random 80% split of the 32 samples were characterized under the 144 possible combinations of the tuning knobs. The resulting database was processed using the hybrid feature selection method in [37] using the remaining 20% of the samples as an independent validation set. That is, the complete input data base consists in a matrix of $0.8 \times 32 \times 144 \approx 26 \times 144 = 3744$ entries. Each entry in this matrix is a row vector in the form $[T_1, ..., T_4, S_1, ..., S_{19}]$, where $T_i$ are the four available tuning knobs and $S_i$ are the 19 candidate signatures.

The feature selection algorithm ranks the available signatures according to their relevancy to predict the PA specifications. The obtained results are shown in Table VI that details the list of most relevant signatures for the considered PA specifications, as selected by the feature selection algorithm and ranked by order of relevancy. The algorithm selects signatures as long as they improve the predictive models. Based on this approach, 9 signatures were selected for *DE*, 13 for *PAE*, 7 for $P_{sat}$ and 6 for $G_p$ as presented in Table VI. To better illustrate these results, Fig. 9 shows the learning curves for the predictive functions (12)-(15). These learning curves show the Root Mean Square Error (RMSE) for the predictions of the PA Gain, *PAE*, *DE* and $P_{sat}$ (evaluated both in the training set and in the independent validation set) as a function of the number of input signatures considered. Signatures are added according to their relevancy. By observing the list of selected signatures in Table VI and the learning curves in Fig. 9, it is easy to see that only a handful of signatures are enough for building an accurate regression model and that both the

non-intrusive process monitors and intrusive signatures (from the peak-power detectors and the reflectometer) are required for accurate predictions. This is further exemplified in Fig. 10 that shows scatterplots of predicted versus actual $P_{sat}$, *DE*, gain and *PAE* for four different scenarios: a) considering only the signatures from the ring oscillators, b) considering only the signatures from the built-in test instruments (PPD and reflectometer), c) considering the complete set of 19 signatures from the ring oscillators, PPD and reflectometer, and d) considering only the selected most relevant signatures for each specification. It is clear to see that combining nonintrusive signatures with built-in test instruments yields consistently better results than any of them separately.

Indeed, if only the nonintrusive signatures are considered, as in Fig. 10a, the correlation between the signatures vectors have visible effects in the predictions. As can be seen in Fig. 10a, the predictions for the validation set samples are structured as parallel lines, each one corresponding to a different sample in the validation set. This effect derives from the fact that all the data points from a same chip instance share the same set of ring oscillator signatures, since they are not affected by the tuning knob positions. The introduction of the built-in test instruments in combination with the nonintrusive signatures, as in Fig. 10c and 10d, effectively decorrelates the input data vectors, improving this way the predictions.

Quantitatively, the RMSE for *DE* improves from 0.83% to 0.68%, with the corresponding $R^2$ increasing from 0.66 to 0.78. For *PAE*, the RMSE decreases from 0.82% to 0.77%, with an $R^2$ improvement from 0.67 to 0.71. Similarly, the gain $G_p$ shows an RMSE reduction from 0.26 dB to 0.17 dB, with $R^2$ enhancement from 0.84 to 0.93, while $P_{sat}$ improves from an RMSE of 0.22 dBm to 0.19 dBm, alongside an $R^2$ rise from 0.89 to 0.92.

It is also clear that feature selection improves the predictions, or at least does not degrade them, while significantly reducing the number of required measurements for predicting each target performance. This is due to the fact that the feature selection algorithm filters out signatures that are not relevant to the prediction of the target performance, or that are only weakly (or not at all) correlated to the target. Removing these non-relevant features, the prediction models can better capture the behavior of the system and avoid possible overfitting issues. For example, the prediction error for $P_{sat}$ and $G_p$ remains approximately constant even when the number of signatures is reduced from 19 to 7 and 6, respectively. This is an indication that additional signatures do not bring any significant information not contained already in the first 7 signatures. In contrast, for *PAE*, reducing the number of signatures from 19 to 13 leads to an RMSE improvement from 0.77% to 0.66% with $R^2$ increasing from 0.71 to 0.79. Similarly, for *DE*, the error improves slightly from 0.68% to 0.62%, with $R^2$ rising from 0.78 to 0.81. In this case, removing non-relevant signatures improves the predictions as we avoid noisy or weakly correlated information that can mislead the training. The evolution of the fitting coefficient $R^2$ and the RMS error justifies the combination of nonintrusive signatures from the ring oscillators and intrusive ones from the built-in test instruments.
<figure><img src="image_11.png" /><figcaption>Fig. 9. Feature selection results for the considered PA specifications.</figcaption></figure>

2) *Model Training*: The available 32 fabricated samples were calibrated based on regression functions trained with the most relevant features described in Section V-B1. In this work, these regression functions were implemented as multilayer perceptron networks with fully connected layers of neurons with a rectifier activation function (rectified linear unit, or ReLu). The number of layers and the number of neurons per layer were optimized in order to minimize the size of the network while maximizing generalization accuracy. The optimized multilayer perceptron employed in this work has three fully-connected hidden layers with 39, 24, and 8 neurons, respectively. A rectifier activation function has been employed as a computationally efficient way of introducing nonlinearity in the model without the issues of vanishing or exploding gradient that other activation functions have (e.g., sigmoid, tanh, etc) [36].

It should be noticed that machine learning test and cali-
bration techniques require access to large data volumes for
training learning models that can accurately capture process
variations. This technique is intended to be deployed in
production, where prediction models can be trained in the
characterization stage over a few hundreds of pre-production
samples. Since we only have access to 32 samples, to provide a
significant estimation of the calibration performance, we resort
to a leave-one-out cross-validation technique [35]. That is, we
start by considering 31 samples for the training stage and the
remaining sample as an independent test sample. The process
is then repeated for each sample in our initial dataset, that
is, leaving a different sample out as independent test sample

and training with the remaining 31 samples each time, until
all samples have been calibrated. As demonstrated in [6],
[35], this cross-validation technique allows us to provide the
best possible validation in a scenario with limited available
data. Models are trained with data from 31 samples and the
calibrated sample is never in the training set.

3) *Performance Calibration*: The calibration goals, as described above, are to recenter the PA performance around the maximum power efficiency while complying with the minimum gain and output power design targets. The obtained calibration results are shown in Fig. 11. Fig. 11 shows the histograms of the considered PA specifications, *PAE*, *DE*, gain and *P*<sub>sat</sub>, before and after calibration. The performance before calibration, in blue, corresponds to the nominal positions of the tuning knobs. To further validate the machine learning-based calibration methodology, Fig. 11 shows the predicted calibrated performance obtained by the regression functions (12)-(15) for the identified optimum combination of tuning knobs, in red, and the measured calibrated performance for these tuning knob positions, in green. To complete these results, Fig. 12 shows the histograms of measured power consumption before (blue) and after (green) calibration. Power consumption is significantly reduced, which brings the advantages of energy savings and improved reliability due to reduced electrical stress. The proposed calibration successfully re-centers the performance of the 32 PA samples around a maximum value of *PAE* and *DE* around 21%, the power consumption is minimized, and the gain and *P*<sub>sat</sub> comply with the minimum design targets. Additionally, it can be seen
<figure><img src="image_12.png" /><figcaption>Fig. 10. Predicted versus actual scatterplots for the PA performances considering: a) only the ring oscillator signatures; b) only the reflectometer and PPD signatures; c) all available signatures (reflectometer, PPD and ring oscillators); and d) most relevant signatures identified by the feature selection algorithm.</figcaption></figure>

<table><caption>TABLE VI
HYBRID FEATURE SELECTION RESULTS FOR THE PREDICTION OF THE PA SPECIFICATIONS</caption><thead><tr><th>Performance</th><th>Most correlated signatures</th></tr></thead><tbody><tr><td>PAE</td><td>PPD<sub>inc</sub>, ringo7, mixer<sub>inc_IF</sub>, PPD<sub>reflect</sub>, mixer<sub>reflect_IF</sub>, ringo3, ringo9, ringo13, ringo4, ringo6, ringo10, ringo8, ringo12</td></tr><tr><td>Gp</td><td>PPD<sub>inc</sub>, ringo1, mixer<sub>inc_IF</sub>, ringo10, ringo15, ringo13</td></tr><tr><td>P<sub>sat</sub></td><td>PPD<sub>inc</sub>, ringo1, ringo7, ringo10, ringo8, ringo15, ringo13</td></tr><tr><td>DE</td><td>PPD<sub>inc</sub>, ringo7, ringo11, mixer<sub>reflect_IF</sub>, PPD<sub>reflect</sub>, mixer<sub>inc_IF</sub>, ringo13, ringo9, ringo2</td></tr></tbody></table>

that both the predicted and measured calibrated performance match within the expected prediction errors for each of the PA performances, which validates the accuracy of the proposed machine learning-based approach.

### C. Defect Detection

In order to verify the feasibility of the proposed defect detection strategy, we have built a *k*-filter using the signatures generated by the built-in peak-power detectors, i.e., *PPD*<sub>inc</sub> and *PPD*<sub>reflect</sub>. These signatures were measured for the 32 available samples considering the nominal positions of the tuning knobs. The mean value and standard deviation of each signature were computed and a *k*-filter was constructed according to equation (3) using 5σ (*k* = 5). The choice of *k* = 5 is motivated as a trade-off solution between a strict filter

(*k* <<), which may reject as faulty many functional devices, and a lenient filter (*k* >>), which may accept as functional many faulty devices. The resulting nominal distributions and the boundaries of the *k*-filter, that is, the projections of the edges of the rectangle *H*<sub>*k*-filter</sub> defined in (3), are represented in Fig. 13.

Since our fabricated wafer does not contain actual defective silicon samples (in a mature technology, we would need access to high-volume production to capture actual fabrication defects), we emulate faulty devices on silicon by selecting tuning knob settings that result in extreme performance deviations or non-functional devices. In an industrial production, as described in the IEEE P2427 standard [40], the presence of a fabrication defect can cause either catastrophic or parametric faults. A catastrophic fault is a “hard” fault and usually leads
<figure><img src="image_13.png" /><figcaption>Fig. 11. Histograms of PA performances before and after calibration: a) *PAE*; b) *DE*; c) Gain; and d) *Psat*.</figcaption></figure>

<figure><img src="image_14.png" /><figcaption>Fig. 12. Histogram of measured PA power consumption before and after calibration.</figcaption></figure>

<figure><img src="image_15.png" /><figcaption>Fig. 13. Defect detection using the built-in peak-power detectors and a k-filter for outlier detection for $k = 5$. Projections of the $H_k$-filter rectangle on the: a) $PPD_{inc}$ axis and b) $PPD_{reflect}$ axis.</figcaption></figure>

to a drastic or total loss of functionality. On the other hand, parametric faults are deviations in the performance of a circuit element that are outside the specified tolerance limits, but do not necessarily cause a complete functional failure. Usually, catastrophic faults are detected based on standardized structural tests, while parametric faults may be quite challenging to detect and require a complete functional test. In this regard, our emulated faults cover both the catastrophic and parametric faults described in the IEEE P2427 standard.

A total of 154 emulated defective samples were generated. These artificially created defective samples serve as test cases for the fault detection filter, allowing us to assess its capability to identify anomalies. Successfully flagging these synthetic defects would demonstrate that the proposed method is effective in detecting faulty chips and preventing them from being included in the calibration and machine learning training process. The results are shown in Fig. 13. The positions of the defective samples are marked with orange arrows. As can be seen, all of the 154 defective samples fall outside of the rectangle defined by the proposed defect filter and are successfully identified as outliers.

the phase of the reflection coefficient at the operation point corresponding to peak *PAE* conditions. The predictive model was then verified using the remaining 20% of the data as an independent test set. The results in Fig. 14 show the scatterplots of predicted versus actual magnitude and phase (sine and cosine) for the reflection coefficient, both for the training and test sets. As can be observed, a very good agreement between predictions and actual values is observed, with fitting coefficients $R^2$ above 0.9 for both magnitude and phase predictions and an RMS error lower than 1%.

## D. Output Matching Evaluation

In order to show the feasibility of the proposed strategy for output matching evaluation, the fabricated PA was characterized, for nominal tuning knob settings, in a load-pull setup using an impedance tuner. A total of 213 positions and three operation frequencies (78 GHz, 79 GHz, and 80 GHz) were considered to synthesize a wide range of output matching conditions covering $|\Gamma|$ values from 0 to 0.8. Signatures $mixer_{inc IF}$, $mixer_{reflect IF}$, and $mixer_{\phi IF}$ were extracted for each of the considered test conditions. Predictive models were then trained using 80% of the available data for regressing the magnitude and the sine and cosine of

## E. Comparison to the State-of-the-Art

In order to put our results and contributions into perspective, Table VII presents a comparison of the strengths and weaknesses of the presented test and calibration techniques with prior art. Thanks to a combination of non-intrusive process monitors and built-in test instruments, our approach enables one-shot performance recentering and calibration, the detection of faulty devices and the assessment of the output matching conditions of the PA, which were unfeasible in previous non-intrusive calibration strategies. Additionally, the proposed techniques are demonstrated using an industrial 79 GHz
<figure><img src="image_16.png" /><figcaption>Fig. 14. Predicted vs actual scatterplots for: a) Magnitude of the reflection coefficient, |Γ|; b) Sine of the reflection coefficient phase, sin(φ); c) Cosine of the reflection coefficient phase, cos(φ).</figcaption></figure>

power amplifier for automotive radar applications, proving the
robustness of our calibration method in an industrial context.

Regarding the limitations of our work, the integration of
both process monitors and built-in test instruments incurs in
a total area overhead of 0.45 mm² and introduces 0.9 dB of
insertion losses due to the back-to-back integrated directional
couplers. Regarding the area overhead, it is worth noting
that the average area of published mm-wave transceivers is
above 4 mm² per transmitter/receiver (Tx/Rx) pair. More-
over, multiple Tx/Rx pairs are implemented in state-of-the-
art beamforming transceivers [41], [42]. The total area of the
on-chip test circuitry is acceptable compared to the area of
a complete beamforming mm-wave transceiver. In a high-
volume production the cost of this area overhead has to be
compared to the improvements in yield loss and test escapes
enabled by the proposed test and calibration techniques. This
analysis, however, requires access to production data and is
out of the scope of the present work.

With respect to the performance impact of the built-in test
instruments, the added electrical losses are compensated by
the enhanced test and calibration capabilities that they bring
over a solution employing only non-intrusive process monitors.
As experimentally demonstrated, the PA performance after
calibration can be recentered around a lower consumption-
higher power efficiency operation point, despite the added
losses.

It should also be noticed that the obtained results were
achieved with a dataset of only 32 available PA samples. The
fact that the proposed machine learning techniques could be
validated with such limited dataset is a strong indication of the
feasibility of the technique. Future work in larger production
volumes has the potential to significantly improve the perfor-
mance of the proposed test and calibration techniques.

VI. CONCLUSION

This work presents machine learning-based test and cali-
bration techniques for a mm-wave PA for automotive radar
applications. The proposed calibration is guided by a com-
bination of non-intrusive process control monitors, imple-
mented as digital ring oscillators, and a set of built-in test
instruments, including a reflectometer and two Peak-Power
Detectors. These built-in test instruments not only help in
the calibration procedure, but they also allowed us to define

a defect detection strategy based on outlier identification in
the space of signatures, and to evaluate the output matching
condition of the PA to detect potential interconnection issues
with the transmitter antenna.

Compared to previous works, the proposed integrated imple-
mentation simplifies the industrialization of machine learning-
based test and calibration techniques for mm-wave circuits
by resorting to digital, DC and low-frequency measurements.
Moreover, the combination of non-intrusive monitors and
built-in test instruments makes the techniques robust against
local variations, mismatch and local defects. Additionally,
we demonstrate that the inclusion of a feature selection
pre-processing stage before training the calibration functions
greatly improves the calibration accuracy.

The proposed machine learning-based test and calibration
techniques have been validated on a set of 32 fabricated
samples of a 79 GHz 4-way PA designed in 28 nm CMOS
technology. Experimental results demonstrate the ability of the
proposed techniques to re-center the PA specifications around
the best power efficiency for each of the considered samples,
detect faulty instances of the PA in an early stage, and evaluate
its output matching conditions.

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<figure><img src="image_17.png" /></figure>

**Oumayma Belkhadra** received a M.Eng. in Radio Systems and Telecommunications from ENSEIRB-MATMECA, Bordeaux, France, and a Master's degree in Electronic Systems from the University of Bordeaux, both in 2020. She is currently completing the Ph.D. as part of a CIFRE collaboration between NXP Semiconductors and the TIMA Laboratory, and is based at NXP in Grenoble. Her research focuses on the design, calibration, and testing of millimeter-wave integrated circuits.

<figure><img src="image_18.png" /></figure>

**Florent Cilici** (S'18) received a M.Eng. in integrated electronic systems in 2016 from Phelma, Grenoble Institute of Technology and the Ph.D. degree in 2019 from the Grenoble Alpes University as a part of TIMA and RFIC-Lab laboratories. He is currently with NXP Toulouse, France. His research interests include the design, calibration, and test of millimeter-wave integrated circuits.

<figure><img src="image_19.png" /></figure>

**Sebastien Crampon** received a M.Eng. in analog microelectronics and microtechnology in 2007 from Clermont Ferrand II University. He joined NXP in 2014 as RF Physical Designer, working on all Radar Front End generation since. His main expertise is in the physical design of the millimeter-wave integrated circuits.

<figure><img src="image_20.png" /></figure>

**Jérémy Arbouet** received a M.Eng. in electronic in 2018 from ENSEEIHT, Toulouse National Institute of Technology. He joined NXP in 2019 as RF Validation Engineer to characterize the 5th Radar Front End generation. His expertise is mainly on millimeter wave measurement and instrumentation.
<figure><img src="image_21.png" /></figure>

**Loïc Vincent** received the Ph.D. degree in elec-
trotechnical and electronic engineering from Greno-
ble Institute of Technology (Grenoble INP, France)
in 2010. From 2007 to 2015 he was with the CIME
Nanotech, France as an engineer in microsystems
and sensors. Since 2015 he mainly focuses on mi-
crowave and millimeter-wave instrumentation.

**Gilles Montoriol** received the Ph.D. degree in microelectronics from the University of Limoges in 1988, focusing on GaAs transistor modeling. He began his career at the GaAs Division of THOMSON-CSF, where he designed components for military applications. In 1993, he joined Motorola Semiconductors in Toulouse as an RF power amplifier designer for cellular applications. He later contributed to the development of millimeter-wave automotive radar technologies at Freescale Semiconductors and subsequently NXP Semiconductors, where he has been involved for over 15 years, contributing to the development of five generations of radar products. He is the author or co-author of more than fifteen patents and has supervised several Ph.D. students.

<figure><img src="image_22.png" /></figure>

**Salvador Mir** (M'99) received an Industrial Engi-
neering degree (Electrical, 1987) from the Polytech-
nic University of Catalonia, Barcelona, Spain, M.Sc.
(1989) and Ph.D. (1993) degrees in Computer Sci-
ence from the University of Manchester, UK, and the
Habilitation à Diriger des Recherches (2005) from
Institut National Polytechnique de Grenoble, France.
He is a Research Director of CNRS (Centre National
de la Recherche Scientifique) at TIMA Laboratory
in Grenoble, France. He created the Reliable Mixed-
signal Systems Group at TIMA Laboratory in 2002

which he led until 2014. He was director of TIMA Laboratory from January 2015 until December 2020. He is currently a member of the RMS team. His area of expertise is analog/mixed-signal/RF/MEMS design for test. He has been General, Program, Topic Chair and member of the Steering Committee of many IEEE/IFIP International Conferences. He is editor and co-author of two books on silicon Microsystems, and the co-author of 5 best paper awards in IEEE ETS'09, IFIP/IEEE VLSI-SoC'10, IEEE ETS'12, IEEE ETS'15 and IEEE ETS'18.

<figure><img src="image_23.png" /></figure>

**Emmanuel Pistono** received the Ph.D. degree from the Institut National Polytechnique de Grenoble (INPG), Grenoble, France, in 2006. In 2007, he joined Université Joseph Fourier (now Université Grenoble Alpes), Grenoble, as an Assistant Professor. He is now member of the TIMA laboratory (Université Grenoble Alpes) as an Associate Professor. His research interests include miniaturized and high-performance RF/millimeter-wave passive circuits in various technologies such as PCB, CMOS, interposers, 3D-integration.

<figure><img src="image_24.png" /></figure>

**Sylvain Bourdel** received the Ph. D in microelec-
tronics from the National Institute of Applied Sci-
ence (INSA) of Toulouse in 2000. He was with the
LAAS laboratory of Toulouse where he was involved
in radiofrequency systems modeling and he was
particularly focused on spread spectrum techniques
applied to 2.45GHz transceivers. In 2002 he joined
the IM2NP in Marseille where he headed with Pr
H. Barthélemy the Integrated Circuit Design Team
of the IM2NP. He joined in 2013 the IMEP-LAHC
laboratory of Grenoble-INP as a full Professor. He

led the RFIC-Lab laboratory until 2021 and is now with TIMA laboratory. He works on RF and mm-wave IC design and integration. He particularly focuses on low-cost and low-power applications. His area of interest also includes system-level specifications, UWB, and RFID. He is the author and co-author of more than 80 referenced IEEE publications.

<figure><img src="image_25.png" /></figure>

**Manuel J. Barragan** (M'14) received an M.Sc.
degree in Physics in 2003 and a Ph.D. in Microelec-
tronics in 2009, both from the University of Seville,
Spain. He is currently a Research Director with the
French National Research Council (CNRS) at TIMA
Laboratory, France, where he leads the Reliable RF
and Mixed-Signal Systems group. His research is
focused on the topics of testing and design for
testability of analog, mixed-signal, and RF systems.
His Ph.D. research won a Silver Leaf Award at the
IEEE PRIME conference in 2009 and, in 2011, his

work was selected for inclusion in the 20th Anniversary Compendium of Most Influential Papers from the IEEE Asian Test Symposium. He received the Best Special Session Award in the 2015 IEEE VLSI Test Symposium, the Best Paper Award in the 2018 IEEE European Test Symposium, and the Best Paper Award in the 2023 IEEE NEWCAS conference.