# Fine pitch superconducting interconnects obtained with Nb-Nb direct bonding

Candice Thomas, Pablo Renaud, Meriem Guergour, Edouard Deschaseaux, Christophe Dubarry, Jennifer Guillaume, Elisa Vermande, Alain Campo, Frank Fournel, Hadi Hijazi, et al.

► To cite this version:

Candice Thomas, Pablo Renaud, Meriem Guergour, Edouard Deschaseaux, Christophe Dubarry, et al.. Fine pitch superconducting interconnects obtained with Nb-Nb direct bonding. Materials for Quantum Technology, 2025, 5, pp.016001. cea-05513793

HAL Id: cea-05513793

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# Fine pitch superconducting interconnects obtained with Nb-Nb direct bonding

Candice Thomas, Pablo Renaud, Meriem Guergour, Edouard Deschaseaux, Christophe Dubarry, Jennifer Guillaume, Elisa Vermande, Alain Campo, Frank Fournel, Hadi Hijazi, et al.

► To cite this version:

Candice Thomas, Pablo Renaud, Meriem Guergour, Edouard Deschaseaux, Christophe Dubarry, et al.. Fine pitch superconducting interconnects obtained with Nb-Nb direct bonding. Materials for Quantum Technology, 2025, 5, pp.016001. cea-05513793

HAL Id: cea-05513793

https://cea.hal.science/view/index/docid/5513793

Submitted on 16 Feb 2026

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PAPER

# Fine pitch superconducting interconnects obtained with Nb–Nb direct bonding

Candice Thomas, Pablo Renaud, Meriem Guergour, Edouard Deschaseaux, Christophe Dubarry, Jennifer Guillaume, Elisa Vermande, Alain Campo, Frank Fournel, Hadi Hijazi, Anne-Marie Papon, Catherine Pellissier and Jean Charbonnier*

University Grenoble Alpes, CEA, LETI, Grenoble, France

* Author to whom any correspondence should be addressed.

E-mail: jean.charbonnier@cea.fr

**Keywords:** 3D integration, superconducting interconnect, direct bonding, low temperature electrical characterizations

## Abstract

For cryogenic systems, the development of superconducting interconnects is nowadays essential to reach large-scale integration schemes while addressing the associated challenges of signal dispersion and cross talk as well as thermal management. To achieve interconnects with micrometer and potentially sub-micrometer pitches, we investigate wafer-to-wafer direct bonding of Nb pads, using 200 mm processes developed for Cu/SiO₂ hybrid bonding and for Nb routing levels. Contrarily to standard hybrid bonding, the Nb pads of these interconnects are surrounded by air instead of dielectric to reduce signal and thermal losses in between the wafers. We report on the fabrication and characterization of this technology using 20–7 µm-pitch direct bonded Nb pads. Transmission electron microscopy of the bonded interface and wafer-level parametric tests at 300 K of various daisy chains assess the bonding quality with a yield exceeding 90%. Low temperature electrical measurements in a cryostat demonstrate the promise of these interconnects with a critical temperature of 4.6 K, a critical magnetic field of 3.2 T and a critical current density of 1.25 kA/cm² at 2 K and 0 T for 10 µm × 10 µm bonded Nb pads.

## 1. Introduction

Achieving scalable superconducting circuits is currently driving important efforts for applications such as high performance computing [1], quantum computing or even advanced sensing. To do so, one can start by increasing the number of Josephson junctions [2] by introducing high kinetic inductance materials such as NbN or by using multiple Josephson junction layers within the chip. Multiple multilayer processes with different characteristics are already available such as SFQ5ee at MIT-Lincoln Laboratory [3], ADP2 at AIST [4] or even RIPPLE at HYPRES [5]. To go one step further and continue increasing the density of superconducting circuits, work on the interconnects has been identified as essential. New processes are especially developed to reduce via and routing line dimensions within multilayer integrations. For example, Nb stud-via technology was introduced to reduce the via diameters [5, 6] and recently 50 nm-wide NbTiN routing lines were demonstrated using damascene processes [7].

Concurrently to these progresses at the chip level, efforts are also put on 2.5D integration [8] with the development of large superconducting platforms capable of hosting chiplets made of high-density superconducting circuits. Recently, the fabrication of a 88 mm × 88 mm active chip carrier, ELASIC, was reported by MIT-Lincoln Laboratory [9]. Such an approach benefits from developments carried especially for high performance computing systems for which heterogeneous integration is key [10]. Thanks to their ductile behavior, their superconducting properties and years of development for infrared applications and more recently for quantum applications [11–15], Indium microbumps appear as the key technology to connect the superconducting chiplets to the chip carrier. This bump technology enables to reach fine pitches as low as 5 µm [16], which might become insufficient to achieve ultra-dense integration schemes. To tackle
that, wafer-to-wafer direct bonding appears as a promising alternative to reach pitches of the order of 1 µm or below [17, 18].

Conditioned by material and process developments, direct bonding might also offer the opportunity to fabricate interconnect with superior superconducting properties than those of In bumps. Recent studies have been reported in this line. Among them, Fujino et al demonstrated the direct bonding of Nb pads using surface activated bonding (SAB) process [19–21]. Daisy chains (DC) with either 200 µm or 1.4 mm wide bonding pads were fabricated and characterized, exhibiting a critical temperature of the order of 7.2 K and 9.3 K, respectively. Reduction of the critical temperature of the DC with 200 µm pads was attributed to an insufficient bonding interface likely resulting from the presence of a 3 nm-thick Si layer at the bonding interface due to material redeposition during SAB [21]. Direct bonding of millimeters wide NbN patterns was reported by Li et al [22] using thermo-compression. While no critical temperature measurement of the resulting NbN–NbN interconnect was presented in this study, the use of this material is promising to reach critical temperature of the order of 15 K.

In this letter, we report on the fabrication and characterization of fine pitch Nb interconnects obtained by
hydrophilic direct bonding process using alignment-bonding tool already used in industry for mass
production. The processes rely on the 3D integration knowledge and know-how developed especially for
Cu/SiO2 hybrid bonding [18] and for superconducting interconnects [23–26] at CEA-LETI. After detailing
the investigated test vehicles and the process flow, morphological characterizations using transmission
electron microscopy (TEM) enable to assess the quality of the presented integration. Concurrently,
wafer-level parametric tests at 300 K and die-level low temperature electrical measurements allow evaluating
the electrical and superconducting properties of this interconnect technology comprising directly bonded Nb
pads.

## 2. Test vehicle description

This study completes a preliminary study reported in [25], in which the direct bonding of Nb pads using 200 mm Si wafer technologies was morphologically qualified using structures only made with the pad level.

To electrically evaluate the direct bonding processes of Nb pads, two different types of test vehicles have been designed and fabricated. Figure 1(a) schematically describes the integration with a bottom and a top wafers comprising both a routing level in Nb, denoted BR for bottom routing and TR for top routing respectively in the figure. These routing levels are connected to Nb pads (labeled TP for top pad and BP for bottom pad in figure 1) through 2 × 2 arrays of TiN vias. The two wafers are then connected after direct bonding of the Nb pads. Four DC going from BR to TR through the vias and pads are investigated to characterize the whole integration. The DC are formed with a different number of interconnections ranging from 62 for DC1 to 31960 for DC4. A unitary link is represented in figure 1(b). For all the DC, the via diameter $d_{via}$ is kept the same while the width of the routing levels $W_L$, the width of the pads $W_{pad}$ and the pitch are varying as summarized in table 1. Note that pitches in the range of 20 µm down to 7 µm are investigated through these DC but smaller pitches down to 1 µm could be achieved [27]. Concurrently, a Kelvin-type test structure as displayed in figure 1(c) is also investigated. This structure is formed using only the pad levels allowing this part of the integration to be characterized alone, without the contribution of the TiN vias and the TR and BR Nb levels.

## 3. Fabrication

The main steps of the integration are detailed in figure 2. The fabrication starts on top of a thermally oxidized 200 mm Si substrate with the physical vapor deposition (PVD) of a 200 nm-thick Nb layer. This layer is embedded in between two 10 nm-thick TiN cap layers, also deposited by PVD, aiming to protect the Nb during the following etch step and to limit its oxidization. This routing level is then patterned using lithography and dry etch techniques such as in [24]. The process flow continues with the passivation using plasma-enhanced chemical vapor deposition of a 600 nm-thick SiO2 layer made with TEOS precursor. The latter is then planarized using chemical mechanical polishing (CMP) until reaching a thickness of 150 nm on top of the Nb routing level. 500 nm-diameter openings are then defined to create the vias, which are filled with the chemical vapor deposition (CVD) of TiN. Subsequently, the excess of TiN is removed from the surface by CMP enabling also to planarize the surface for the fabrication of the upper pad level.

The pads are then formed using processes qualified in [25]. Namely, it starts with the PVD of a 200 nm-thick Nb layer on top of a 10 nm-thick TiN seed layer. Development of adapted CMP process [23] allows to obtain an ultra-smooth and flat Nb surface with a quadratic roughness of 0.1 nm [25], making it compatible with hydrophilic direct bonding. After that polishing step, a 100 nm-thick Nb layer is obtained. Following this, the TiN/Nb layers are etched and shaped into square pads of different sizes, with widths
<figure><img src="image_5.png" /></figure>

<figure><img src="image_6.png" /></figure>

<figure><img src="image_7.png" /><figcaption>**Figure 1.** Schemes of the test vehicles: (a) cross-section representation of the integration, (b) 3D scheme of a unitary link of a daisy chain (without representing the dielectrics and the substrates for clarity) and (c) 3D scheme of the Kelvin test structure (only representing the pad levels).</figcaption></figure>

<table><caption>**Table 1.** Description of the test vehicles.</caption><thead><tr><th rowspan="2">Test vehicle</th><th rowspan="2">Number of links</th><th rowspan="2">Pitch (μm)</th><th colspan="3">Routing line</th><th colspan="1">Via</th><th colspan="1">Pad</th></tr><tr><th>W<sub>L</sub> (μm)</th><th>d<sub>via</sub> (μm)</th><th>W<sub>pad</sub> (μm)</th></tr></thead><tbody><tr><td>Kelvin</td><td>1</td><td>/</td><td>/</td><td>/</td><td>/</td><td>10</td><td>10</td></tr><tr><td>DC1</td><td>62</td><td>20</td><td>10</td><td>0,5</td><td>10</td><td>10</td><td>8</td></tr><tr><td>DC2</td><td>7068</td><td>15</td><td>5</td><td>0,5</td><td>8</td><td>8</td><td>6</td></tr><tr><td>DC3</td><td>11 056</td><td>12</td><td>3</td><td>0,5</td><td>6</td><td>6</td><td>3</td></tr><tr><td>DC4</td><td>31 960</td><td>7</td><td>3</td><td>0,5</td><td>3</td><td>3</td><td>3</td></tr></tbody></table>

ranging from 3 to 10 μm (for pitches varying from 7 to 20 μm), using photolithography, dry etching, and stripping processes. Note that unlike conventional hybrid bonding methods, no dielectric is present around the Nb pads. The presence of air instead of dielectric is indeed favored to reduce loss mechanisms for RF signals and to help with thermal management.

The wafers are bonded at room temperature under atmospheric pressure immediately after stripping. Bonding is performed using processes described in [25] with an EVG®GEMINI®FB tool equipped with a Smartview® bonder, enabling precise alignment of the top and bottom wafers (95° centile or 3 sigma <1 μm) allowing to maximize the contact area between the pads. After bonding, the wafers undergo a 2 h annealing at 400 °C to help interface reconstruction and Nb oxide removal at the bonding interface. The quality of the bonding has then been assessed at the wafer and field scales through Scanning Acoustic Microscopy as reported in [25].

Subsequently, the silicon bulk of the top wafer is removed by grinding and wet etching to give access to the pads for electrical tests. The final stage of the process either completely removes the SiO₂ layer above the TR level or defines opening in it. At this stage, top-view optical observations of the integration are thus possible. These observations are presented in figure 3. Optical micrographs of figures 3(a) and (b) focus on
<figure><img src="image_8.png" /><figcaption>**Figure 2.** Description of the main integration steps.</figcaption></figure>

DC2 and DC4 DC characterized with a pitch of 15 and 7 µm, respectively. The top and bottom routing lines, TR and BR, are well visible for both chains. The pads of DC2 are also well distinguishable as their dimensions exceed the ones of the routing levels. One can notice a slight misalignment of the top and bottom pads in figure 3(a), which is attributed to the alignment precision of the bonding process. This is not visible for DC4 as the pads have the same dimensions as TR and BR levels. Overall, no defect is evidenced with these top-view observations.

## 4. Morphological characterizations

To have a first evaluation of the bonding quality, a cross-section of DC4, characterized with the most aggressive pitch of 7 µm, was performed using TEM techniques. The TEM lamella was prepared using a FIB HELIOS 450 and the observations were made using an Osiris TEM with an operating voltage of 200 kV. The corresponding micrographs are presented in figure 4 with increasing magnification levels.
<figure><img src="image_9.png" /><figcaption>**Figure 3.** Optical micrographs zooming on (a) DC2 with a 15 µm-pitch and (b) DC4 with a 7 µm-pitch.</figcaption></figure>

<figure><img src="image_10.png" /><figcaption>**Figure 4.** Cross-section micrographs of the integration obtained with transmission electron microscopy techniques. (a) Micrograph of the entire TEM lamella showing two links of DC4. (b) Zoom on one pair of bonded pads, evidencing BR, TR, and the TiN vias of the top wafer. (c) Further zoom on the Nb bonded pads, and (d) high resolution micrograph of the bonding interface.</figcaption></figure>
The entire TEM lamella is displayed in figure 4(a), showing two links of the DC, along with the Nb top and bottom routing lines (BR and TR), the TiN vias of the top wafer (the vias of the bottom wafer are not visible here in the selected cutting area) and two pairs of bonded Nb pads. One can see that despite the removal of the top Si substrate, the presence of the air gaps and a slight misalignment (~300 nm) of the bonded pads, the wafer assembly seems mechanically robust with no defect.

Figure 4(b) provides a zoom on one of the links, where the interfaces between the routing levels TR and BR, the top and bottom Nb pads, and the TiN vias are distinguishable. No defect is evidenced in the levels nor at their interfaces. Figure 4(c) focus on the bonding interface between TP and BP Nb bonding pads. In this figure, one can see various grain boundaries associated to different grain orientations within the Nb pads. No structural defects are noticeable in the pads and no cavities or nodules are visible at the bonding interface. At this magnification, the interface appears completely sealed. High-resolution TEM of the bonding interface was then performed to complete this analysis. In figure 4(d), one can distinguish a ~3 nm amorphous layer at the interface distributed equally along TP and BP Nb pads. Energy dispersive x-ray spectroscopy conducted in a previous study on similar Nb pads [25] evidenced the oxide-rich nature of this layer. Concurrently, the interface is formed with a very thin and bright layer characterized with a thickness of <0.2 nm. This latter layer is associated to a lower-density zone, likely due to the Nb pad's roughness after the stripping process, and thus possibly reflects a non-complete sealing of the interface. Pre-bonding chemical treatment or queue time improvement might be envisioned to optimize the interface quality and sealing by reducing the roughness and the oxidation of the pads.

# 5. Electrical characterizations

The electrical qualification of the integration happens in two steps. First, the wafers are tested at 300 K using an automated probe station. Then, die-level measurements are performed to evaluate the superconducting properties of the test structures.

In this study, we will present the results obtained on different daisy chains DC1, DC2, DC3 and DC4 characterized with different link number, different routing width $W_L$ and different pad size $W_{pad}$ as summarized in table 1. A Kelvin test structure allowing to solely characterize the bonding of two Nb pads is also investigated. For all measurements, the total resistance $R$ or the link resistance $R_{link}$ of the chains will be presented. The link resistance corresponds to the total resistance $R$ of the device divided by the number of links in the chain.

## 5.1. Wafer-level parametric tests at 300 K

Wafer-level parametric tests are presented in figure 5 for three chains, DC2, DC3 and DC4, on the same wafer. These measurements have been performed across 61 fields of the 200 mm wafer. This extensive data set permits a statistical analysis of the integration yield along the wafers. Note that similar measurements on the other test vehicles (DC1 and Kelvin) were not performed due to an incompatibility between the pad design and the probes.

Initial observations on the cumulative percentage of figure 5(a) indicate a yield exceeding 90% for the three chains. This suggests that the integration process is highly stable and compatible with different pitch size, at least down to 7 µm.

By analyzing only the data within these 90%, one can notice a low dispersion of the resistance measurements with a standard deviation below 10%, suggesting a good reproducibility of the process across the wafer. Wafer maps of figures 5(b)–(d) complete this analysis by showing the distribution of the resistance data for DC2, DC3 and DC4. For all the chains, the die at the center of the wafer exhibits abnormally high $R_{link}$ values, which could be attributed to a lack of bonding quality at this location. A few other dies show similar resistance behavior but as they are not the same for the three chains, it suggests a failure mechanism due to randomly distributed microscopic defects on the different integration levels. No clear center to edge effect is evidenced on these mappings, supporting a good homogeneity of the processes across the wafers.

One can then look at the resistance values obtained for the three chains. With a mean $R_{link}$ value of 7.1 Ω, DC3 is the more resistive chain in front of DC2 (5.8 Ω per link) and DC4 (5.4 Ω per link). This is explained by the fact that DC3 has the thinnest (3 µm) and longest (12 µm) routing contribution per link. With a sheet resistance of 1.35 Ω/sq [24], Nb routing is indeed expected to dominate the resistance at 300 K.

## 5.2. Die-level electrical measurements at low temperature

### 5.2.1. Evaluation of the critical temperature

Electrical measurements at low temperature were performed using a Physical Property Measurement System cryostat with a base temperature of 2 K. Standard four-probe measurement techniques with a current bias ≤20 µA enabled the extraction of the resistance as a function of the temperature in between 300 and 2 K.
<figure><img src="image_11.png" /></figure>

Figure 6 displays the resistance per link of the four chains (DC1, DC2, DC3 and DC4) and the Kelvin test structure characterized with different routing line widths in between 3 and 10 µm and different pad sizes ranging from 3 to 10 µm. The data are only presented in between 2 and 10 K for better visibility of the superconducting transitions at stake. Note that the data presented here have been obtained using dies located close to the center of the bonded wafers but similar results (not shown here) were obtained on dies located close to the edge.

In figure 6(e), the resistance of a Kelvin test structure is presented allowing to solely characterize the superconducting properties of the bonded pads. A superconducting transition is evidenced at a critical temperature $T_c$ of 4.6 K with a drop and vanishing of the resistance. Note that a slight elbow is visible at the center of the transition, which might be explained by a small difference of $T_c$ between the top Nb pad and the bottom one. Such a small variation might be related to minor process variations between the bonded wafers. In the following and in figure 6, the transitions associated to the Nb pads of the top and bottom wafers are denoted ‘2a’ and ‘2b’.

In figures 6(a)–(d) displaying the resistance of the DC, one can see additional superconducting transitions attributed to the Nb routing lines and the TiN vias. A first transition, labeled ‘1’, is visible at $T_c \ge 7.3$ K for the different chains. It is worth noting that the transitions of the Nb routing lines happen at lower $T_c$ compared to unpassivated Nb routing lines (see inset of figure 6(e)), possibly due to the thermal budget of the integration enhancing Nb oxidation process. We reported a similar $T_c$ reduction in a prior study after passivating Nb lines [28]. Besides, the width of the routing lines seems also to affect the critical temperature of this transition with: $T_c = 7.3$ K for both DC3 and DC4 with $W_L = 3$ µm (see figures 6(a) and (b)), $T_c = 8.2$ K for the chain with $W_L = 5$ µm (see figure 6(c)) and $T_c = 8.7$ K for $W_L = 10$ µm (see figure 6(d)). By decreasing further the temperature, the superconducting transitions of the bonded pads (transitions ‘2a’ and ‘2b’) are visible with critical temperatures that differ a bit from the measurements performed on the Kelvin test structure possibly due to smaller pad dimensions. Indeed, this transition appears to shift to the lower temperatures with the reduction of the pad size $W_{pad}$. Additionally, one can see that these transitions are less sharp for the DC than for the Kelvin test structure. This might be explained by a slight dispersion of the critical temperature of the pads along the chains due to minor process variations across the wafers. Finally, a third transition, labeled ‘3’ in figure 6, is distinguishable around 2.9 K. Based on the value of $T_c$ and the fact that this transition happens at a similar temperature for all the tested chains, one can conclude that it is related to the TiN vias.
<figure><img src="image_12.png" /><figcaption>**Figure 6.** Die-level resistance measurements as a function of the temperature in between 10 and 2 K for: (a) chain DC4 with 31 960 links, (b) chain DC3 with 11 056 links, (c) chain DC2 with 7068 links, (d) chain DC1 with 62 links (inset of (d) shows the same graph without a break on y-axis) and (e) a Kelvin test structure solely characterizing a unique bonded pad. As a reference, inset of (e) shows the sheet resistance ($R_{sq}$) of a 200 nm-thick Nb routing line after patterning (w/o passivation) as a function of the temperature.</figcaption></figure>

Based on these measurements, it clearly appears that the presence of TiN vias limits the superconducting transition of the developed integration. To improve that, future wafers will be fabricated with the Nb pads directly on top of the Nb routing lines. For both the Nb routing lines and the Nb pads, one can see an effect of the brick dimensions on the critical temperature. This can suggest a deep oxidation of Nb, possibly driven by defects or grain boundaries [29], leading to superconducting properties equivalent to those of much thinner lines or pads. Proximity effect with the TiN vias might also play a role.

It is worth noting that the critical temperature of the Nb bonded pads is also low compared to the one of the Nb routing lines. This can be explained by the non-complete sealing of the bonding interface. Such a
difference might also come from the bonding process itself impacting the pads and/or by the absence of
encapsulation around the pads. To compare the material quality between the pads and the routing lines, one
can look at the residual resistivity ratio (RRR) of both technological bricks. The RRR defined here as
$R(300 \text{ K})/R(T_c + 1 \text{ K})$ is indeed a reliable metric of the impurity and defects present in a material. From
measurements performed on different Kelvin structures (data not shown here), the RRR of the Nb bonded
pads is estimated in between 1.2 and 1.5. Such a value is smaller than the RRR of 2.3 assessed for
encapsulated Nb routing lines in a prior study [24]. This comforts the fact that even though the pads and
routing lines are made with the same material in the same equipment, the process steps associated to each
brick are damaging more or less the Nb layers. To go further in the analysis, additional material
characterizations evaluating especially the oxidation levels of each technological brick would be needed.

### 5.2.2. Evaluation of the critical magnetic field

To continue characterizing the properties of directly bonded Nb pads, evaluation of the critical magnetic field $B_{c2}$ is carried on the Kelvin-type test structure. $B_{c2}$ is a metric of the magnetic field driven superconducting to normal transition in type II superconductors such as Nb. To do so, the resistance measurements as a function of the temperature were repeated for several values of magnetic field $B$ ranging from 0 to 1 T. Note that $B$ is a static magnetic field perpendicularly applied to the sample's surface. Similar measurements with in-plane magnetic field were not possible due to the cryostat set-up but as in-plane critical magnetic field is typically larger than the out-of-plane one [30], the measured value of $B_{c2}$ provides a low limit for the in-plane critical magnetic field of the developed interconnect.

Figure 7 displays the associated measurements, evidencing a regular shift of the superconducting transition when increasing $B$. The extracted values of $T_c$ are plotted as a function of $B$ in figure 7(b), evidencing a linear relation between them. By using a linear extrapolation of the data, $B_{c2}$ (0 K) is estimated to 3.2 K, which is in line with the critical magnetic fields reported in prior studies for Nb routing lines [24] and Nb-based vias [26] using the same analysis method. When considering the linear extrapolation, one should note that this fit method does not take into account possible deviations from the linear relations at ultra-low temperatures [31].

### 5.2.3. Evaluation of the critical current

Evaluation of the critical current of the direct bonded Nb pads was then performed. The measurements were carried on the Kelvin test structure by applying an excitation current from 0 mA to a positive value and then sweeping it back to 0 mA after reaching the superconducting to normal transition. These measurements were done at several temperatures below the critical temperature of the Nb bonded pads and at four different magnetic field values: $B = 0$ T, 0.01 T, 0.1 T and 1 T. The critical current $I_c$ is extracted when the voltage switches to a non-zero value using a 5 µV criterion. Figure 8 displays the measured $I_c$ values for the 10 µm × 10 µm bonded pads. At 2 K and 0 T, a critical current of 1.25 mA is obtained. At the same temperature, increasing the magnetic field to 0.1 T has little to no impact on $I_c$ with 1.22 mA at 0.01 T and 1.18 mA at 0.1 T. However, a significant drop of the critical current is noticeable at 1 T with 0.57 mA at 2 K.

From the extraction of $I_c$, one can calculate the critical current density $J_c$ of such interconnect using $J_c(T) = \frac{I_c(T)}{S}$, with $S$ the pad area. At 2 K and 0 T, this gives $J_c = 1.25 \text{ kA/cm}^2$. This value is almost three order of magnitude larger than the one obtained by Fujino et al [21]. Indeed, with a critical current of 1.4 mA measured across 200 µm diameter pads, one can estimate $J_c = 4.5 \text{ A/cm}^2$ for SAB bonded Nb pads. Such a difference of critical current density between these two bonding technologies can be explained by different quality of bonding and/or by the presence of a thin amorphous Si-based layer at the interface of the SAB bonded Nb pads [21].

### 5.2.4. Discussion

The electrical and superconducting properties of the direct bonded Nb pads are summarized in table 2.

With a critical temperature of 4.6 K, direct bonded Nb pads show a normal to superconducting transition happening at a larger temperature than In microbumps for which this transition typically arrives around 3 K [12, 13]. Using SAB bonding, Fujino et al [21] reported even larger $T_c$ for 200 µm and 1.4 mm diameter bonded Nb pads with values in between 7.2 and 9.3 K, respectively. The larger critical temperatures observed in this latter study might be due to the bigger size of the pads and potentially to the limited thermal budget of the involved process as no annealing is performed with SAB. Additionally, in our case, the remaining oxide layer found at the Nb bonded interface, a more general oxidation of the Nb pads or the non-perfect sealing of the bonding interface might affect the critical temperature.

Another advantage of such interconnect technology is that it could be made of a unique material, here Nb, allowing to benefit entirely from the superconducting properties of this material. As discussed in previous section, one could indeed envision an integration without TiN vias, where the Nb pads would be in
<figure><img src="image_13.png" /><figcaption>**Figure 7.** Evaluation of the critical magnetic field of the Nb bonded pads. (a) Resistance of the Kelvin test structure as a function of the temperature between 6 and 2 K for different magnetic field values in between 0 and 1 T. (b) Evolution of the critical temperature $T_c$ as a function of B and the associated linear fit for the extraction of the critical magnetic field at 0 K.</figcaption></figure>

<figure><img src="image_14.png" /><figcaption>**Figure 8.** Evaluation of the critical current of 10 µm × 10 µm Nb bonded pads. Measurements were performed at 0 T, 0.01 T, 0.1 T and 1 T.</figcaption></figure>
<table><caption>**Table 2.** Electrical and superconducting properties of direct bonded Nb pads.</caption><thead><tr><th></th><th>Dimensions</th><th>RRR</th><th>T<sub>c</sub> (K)</th><th>B<sub>c2</sub>(0) (T)</th><th>J<sub>c</sub> (kA/cm<sup>2</sup>)<br>@ 2 K and 0 T</th></tr></thead><tbody><tr><td>Direct bonded Nb pads</td><td>10 &mu;m &times; 10 &mu;m</td><td>1.2–1.5</td><td>4.6</td><td>3.2</td><td>1.25</td></tr></tbody></table>

direct contact with the Nb routing underneath. This is not possible with In microbumps, for which one needs to use a different material for the under bump metallizations (UBMs) and eventually another material for the routing. These other materials could limit the superconducting properties of the whole interconnect as reported by Foxen *et al* [11] who evidenced a $T_c$ of 1.1 K using In microbumps on TiN UBMs and Al routing layer.

Together with optimized superconducting properties, direct bonding of Nb pads also offers promises to increase interconnect density by targeting pitches of the order of 1 µm or below, which are nowadays demonstrated with Cu hybrid bonding [17, 18]. This should help scaling superconducting electronics and quantum systems, especially those made using complementary metal-oxide-semiconductor technologies [32]. This is particularly the case for silicon spin qubits, which are characterized by a small footprint of the order of 100 nm × 100 nm.

The critical current density of the interconnects is an essential property to be able to design pads with low critical dimensions to achieve fine pitch integration. Typical current of a few mA are generally used in quantum systems to operate the control and read-out tools of superconducting or spin qubits. Tens of µm-wide In microbumps allow to carry such currents. For example, a critical current of the order of 40 mA was reported for 17 µm × 17 µm In microbumps [12], corresponding to a critical current density $J_c$ of 13 kA/cm². Concurrently, the In microbumps of Foxen *et al* [11] showed a critical current of the order of 25 mA. With $J_c$ = 1.25 kA/cm², the direct bonded Nb pads developed in this study will be able to carry 10 mA only if they are designed with a width of about 30 µm. Such dimension is not compatible with fine pitch integration schemes and illustrate the need to optimize the direct bonding process to achieve a larger critical current density. $J_c$ of the order of a few MA/cm² are typically reported for Nb micrometer structures [24, 33, 34], showing the room available for improvement. Efforts on reducing the annealing temperature, preventing or limiting the oxide-rich interface between the bonded Nb pads are already started.

When considering specific integrations such as the ones of spin qubits, it is essential that the interconnects could sustain the application of a static magnetic field of the order of a few hundreds of mT as this is needed for spin manipulation [35]. With a critical magnetic field of the order of 3.2 K and the stability of the critical current at least up to 0.1 T, the direct bonded Nb pads seem to meet this requirement.

Overall, these first results on direct bonded Nb pads at pitch as low as 7 µm are very promising for the future development of fine pitch superconducting interconnects. This study draws a first report of the status of this technology after using standard off the shelves processes developed historically for Cu/SiO₂ hybrid bonding. It allows highlighting the parameters to improve to make this technology fully compatible with the specifications of dense superconducting and quantum systems. In terms of accessibility, note that the use of hydrophilic direct bonding as reported in this study has a clear advantage over SAB processes as it can be performed using standard industry-compatible bonding equipments typically used for hybrid bonding and allowing very precise alignments. This is an essential point for the integration of these fine pitch Nb interconnects on top of various technologies.

## 6. Conclusion

We have reported the direct bonding of superconducting Nb pads at a pitch as low as 7 µm using 200 mm Si wafer technologies. Morphological characterizations using TEM enabled to assess the quality of the integration and the sealing of the interface, while evidencing the presence of a ~3 nm rich oxide layer at the interface. Wafer-level parametric tests at 300 K confirmed the bonding yield across the wafers with cumulative percentage exceeding 90% for the measured DC. The superconducting properties of the directly bonded Nb pads were then extracted using die-level low temperature measurements. With $T_c$ of ~4.6 K, $B_{c2}$ of 3.2 T and $J_c$ of 1.25 kA/cm² at 2 K and 0 T, these interconnects, made using existing bonding processes developed historically for Cu/SiO₂ hybrid bonding, show already good promises for future integration within quantum or superconducting systems.

Process optimizations, including a decrease of the annealing temperature and protective treatment of the pad surfaces, are ongoing to improve the bonding interface quality, get rid of the amorphous layer at the bonding interface and possibly improve the superconducting properties of the developed interconnect. Reducing the annealing temperature would also make this interconnect technology more compatible with
Josephson junction's integration [36–39], which are a key brick for superconducting electronics and superconducting qubits.

Concurrently, efforts are driven on reducing the pitch below 1 µm and increasing the stand-off or wafer-to-wafer distance. These two aspects should offer interesting leverages in term of architecture. Additionally to the above mentioned process and integration studies, the characterizations of the interconnect's bandwidth and thermal conductivity will be conducted to complete the presented dataset and assess the full potential of the direct bonded Nb pads with airgaps for quantum and superconducting assemblies. Besides these efforts on improving and characterizing this interconnect module by itself, its co-integration with Josephson junctions using wafer-scale processes will be investigated.

## Data availability statement

All data that support the findings of this study are included within the article (and any supplementary files).

## Acknowledgment

This work is part of the IPCEI Microelectronics and Connectivity and was supported by the French Public Authorities within the frame of France 2030. The authors would like to thank the CEA Si 200 mm platform and the Pheliqs laboratory of CEA-IRIG for the access to the PPMS cryostat.

## ORCID iDs

Candice Thomas https://orcid.org/0000-0002-9794-1813

Hadi Hijazi https://orcid.org/0000-0003-0426-7127

Jean Charbonnier https://orcid.org/0000-0003-3769-3712

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