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# Speculative High-Level Synthesis of RISC-V Processors

Thomas Feuilletin, Dylan Leothaud, Jean-Michel Gorius, Steven Derrien, Simon Rokicki

► To cite this version:

Thomas Feuilletin, Dylan Leothaud, Jean-Michel Gorius, Steven Derrien, Simon Rokicki. Speculative High-Level Synthesis of RISC-V Processors. RISC-V summit Europe 2025, May 2025, Paris, France. pp.1-1, 2025. [hal-05140615](https://hal.science/hal-05140615v1)

HAL Id: hal-05140615

https://hal.science/hal-05140615v1

Submitted on 2 Jul 2025

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Distributed under a Creative Commons Attribution 4.0 International License
# Designing a RISC-V CPU should be as simple as writing an Instruction Set Simulator

## Introduction

**Context:** Increasing need for customizable architectures for embedded applications.

**Problem:** Micro-architectural design is tedious and error-prone, how do we make such customizations available to everyone?

**Our approach:** Leverage High-Level Synthesis to synthesize **micro-architectures** from a single instruction set simulator in C.

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## Key takeaway

High-Level Synthesis (HLS) tools allow automatic generation of hardware from C programs

## Pipelined RISC-V processors require Speculative HLS

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## Modeling a full RISC-V ISS

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## Complex techniques

* Memory speculation [5]
* Multiple speculations [1]
* Efficient exploration [3]

## Competitive hardware

Generated design is comparable with manual implementations

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GeCoS
Generic Compiler Suite

## Designing advanced micro-architectural features

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### Promising technique

Speculative HLS can be used to describe more complex features (caches, branch predictor, etc...)

Example of a branch predictor

## Conclusion

We need speculation to synthesize processor cores [2, 4]. Processor design from an ISS using **speculative pipelining** enables **fast iteration times** and **intuitive** design exploration.

## More information

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Project website

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Github page

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Contact link

<footnote>[1] Gorius, J.-M., Rokicki, S., and Derrien, S. *SpecHLS: Speculative Accelerator Design using High-Level Synthesis*. IEEE MICRO.</footnote>

<footnote>[2] Gorius, J.-M., Rokicki, S., and Derrien, S. *Design Exploration of RISC-V Soft-Cores through Speculative High-Level Synthesis*. ICFPT'22.</footnote>

<footnote>[3] Leothaud, D., Gorius, J.-M., Rokicki, S., and Derrien, S. *Efficient Design Space Exploration for Dynamic and Speculative High-Level Synthesis*. FPL'24.</footnote>

<footnote>[4] Derrien, S., Marty, T., Rokicki, S., and Yuki, T. *Toward speculative loop pipelining for high-level synthesis*. TCAD.</footnote>

<footnote>[5] Gorius, J.-M., Rokicki, S., and Derrien, S. *A Unified Memory Dependency Framework for Speculative High-Level Synthesis*. CC'24</footnote>