# SiGe-enhanced Si capacitive modulator integration in a 300 mm silicon photonics platform for low power consumption

Maurin Douix, Diego Perez-Galacho, Ismael Charlet, Charles Baudot, Pablo

Acosta-Alba, Sébastien Kerdilès, Catherine Euvrard, Philippe Grosse,

Jonathan Planchot, Romuald Blanc, et al.

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To cite this version:

Maurin Douix, Diego Perez-Galacho, Ismael Charlet, Charles Baudot, Pablo Acosta-Alba, et al. SiGe-enhanced Si capacitive modulator integration in a 300 mm silicon photonics platform for low power consumption. Optics Express, 2019, 27 (13), pp.17701. 10.1364/oe.27.017701. hal-04438450

HAL Id: hal-04438450

https://hal.science/hal-04438450v1

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# SiGe-enhanced Si capacitive modulator integration in a 300 mm silicon photonics platform for low power consumption

MAURIN DOUIX,<fnref n="1" />,<fnref n="2" />,* DIEGO PEREZ-GALACHO,<fnref n="2" />,<fnref n="4" /> ISMAEL

CHARLET,<fnref n="1" />,<fnref n="2" />,<fnref n="3" /> CHARLES BAUDOT,<fnref n="1" /> PABLO ACOSTA-ALBA,<fnref n="3" />

SÉBASTIEN KERDILÈS,<fnref n="3" /> CATHERINE EUVRARD,<fnref n="3" /> PHILIPPE

GROSSE,<fnref n="3" /> JONATHAN PLANCHOT,<fnref n="1" /> ROMUALD BLANC,<fnref n="1" /> RÉMI

BENEYTON,<fnref n="1" /> OLIVIER GOURHANT,<fnref n="1" /> SÉBASTIEN CRÉMER,<fnref n="1" /> AURÉLIE

SOUHAITÉ,<fnref n="1" /> NATHALIE VULLIET,<fnref n="1" /> LAURENT VIVIEN,<fnref n="2" /> DELPHINE

MARRIS-MORINI,<fnref n="2" /> AND FRÉDÉRIC BOEUF<fnref n="1" />

**Abstract:** The successful integration of capacitive phase shifters featuring a p-type strained SiGe layer in a 300 mm silicon photonics platform is presented. The phase shift is evaluated with a voltage swing of only 0.9 Vpp, compatible with CMOS technology. A good correlation is shown between the phase shift efficiency from 10 to 60°/mm and the capacitive oxide thickness varying from 15 to 4 nm. Corresponding insertion losses are as low as 3 dB/mm thanks to the development of low loss poly-silicon and to a careful design of the doped layers within the waveguide. The thin SiGe layer brings an additional 20% gain in efficiency due to higher hole efficiency in strained SiGe.

© 2019 Optical Society of America under the terms of the OSA Open Access Publishing Agreement

## 1. Introduction

Data center growth follows an exponential trend in the amount of annually exchanged data [1, 2]. Thanks to low fabrication costs, high yield and high volume, Silicon-On-Insulator (SOI) photonics technologies are answering the needs for higher data rates in datacom applications [3, 4]. Among the different building blocks to be included in photonic transceivers, the performance of the optical modulator strongly influences the quality of the communication link. Most of silicon modulators are based on PN diodes in depletion regime [5–12]. PN junctions provide high speed modulation, up to 50 Gb/s data rate, and low optical losses, in the range of 1 dB/mm. However, the typical linear phase shifter length is of a few millimeters combined with driving voltages of a few volts, due to the moderate effective electro-optic effect in depletion regime.

Capacitive modulators are currently under development in order to challenge PN junctions in terms of power consumption. Modulator lengths below 1 mm with driving voltages reduced down to 1 V is then achievable [13–18]. Furthermore, it has been shown previously that the integration of a thin SiGe layer in a depletion based PN diode can increase the phase shifter efficiency thanks to a higher hole electro-optic efficiency [8]. In this context, we report in this paper for the first time the successful integration of a capacitive modulator in a 300-mm platform process flow. As a main objective, only a few additional process steps have been added with

<footnote n="1">¹STMicroelectronics, 850 rue Jean Monnet, 38926 CROLLES CEDEX, France</footnote>

<footnote n="2">²Centre for Nanosciences and Nanotechnologies, Université Paris-Sud, CNRS UMR 9001, 10 Boulevard Thomas Gobert, 91120 PALAISEAU, France</footnote>

<footnote n="3">³Commissariat à l'Énergie Atomique et aux Énergies Alternatives, MINATEC Campus, 17 rue des Martyrs, 38054 GRENOBLE CEDEX, France</footnote>

<footnote n="4">⁴ITEAM Research Institute, Universitat Politècnica de València, Camino de Vera s/n, 46022, Valencia, Spain</footnote>

<footnote>*maurin.douix@st.com</footnote>
full compatibility to the existing photonics circuit fabrication flow [19]. Interestingly, a good correlation is shown between phase shift efficiency varying from 10 to 60°/mm and capacitive oxide thickness from 15 to 4 nm, while the impact of adding a thin SiGe layer inside the capacitor is also evaluated.

## 2. Device architecture and fabrication flow

<figure><img src="image_3.png" /><figcaption>Fig. 1. (a) Cut view of capacitive modulator active region, from TCAD process simulation; (b)-(c) Transverse Electric (TE) mode for different waveguide design. Mode size shrinkage with width reduction is shown in (b) and (c) while the final design is shown in (d), in which partial etching of semiconductor electrical access arms allows a good mode confinement in the active region.</figcaption></figure>

The capacitive modulator consists of an active region, a poly-silicon - oxide - silicon capacitance, shaped as a waveguide and embedded inside a linear Mach Zehnder Interferometer (MZI). The active region aims at dynamically modifying the phase of the propagating optical carrier by accumulating carriers around the oxide layer. Optimization of the active region by numerical simulations has been reported previously [13, 20–24, 26]. The cross section is reported in Figs. 1(a) and 1(d). Interestingly, both the top and the bottom parts of the waveguide are slightly etched to optimize the mode confinement, opposite to the designs reported in Figs. 1(b) and 1(c) as used in the previously reported work [15].

In terms of fabrication, the bottom arm of the waveguide is obtained by patterning the SOI, and it is implanted with p-type dopants so that free holes can accumulate as majority carriers at the oxide interface (Fig. 2(a)). The top arm is fabricated following a damascene fabrication process, in which a cavity above the SOI arm is defined (Figs. 2(b) and 2(c)). An optional selective epitaxy of a thin SiGe layer (30 nm, with a fraction of Ge of 30%) is performed at the exposed silicon surface inside the cavity. The capacitor oxide is either grown from rapid thermal oxidation of the SOI (above 800°C) or deposited, as in the case of wafers carrying the optional SiGe layer. The insulator lies in horizontal position through the middle of the waveguide where the optical intensity is maximum (Fig. 1). Its thickness varies from 4 to 15 nm from one to another wafer. The top arm of the device is made up of poly-silicon deposition on top of the insulator. It is finally followed by poly-Si patterning, n-type implantation and standard back end of line for active region metallization (Fig. 2(d)).
<figure><img src="image_4.png" /><figcaption>Fig. 2. Fabrication flow: (a) SOI 3-step patterning, encapsulation and CMP, (b) damascene cavity patterning, (c) SiGe epitaxy, oxide growth and amorphous silicon deposition, (d) CMP, crystallization, implantations, partial etching, encapsulation and contact opening.</figcaption></figure>

Poly-Si optical losses has been studied previously [25]. An optimal deposition process has been defined, based on amorphous silicon deposition followed by solid phase crystallization. Optical loss of such poly-Si based waveguides is below 1 dB/mm at 1310 nm. Considering the overlap of the optical mode of the phase shifter with poly-Si part of the capacitive structure, a corresponding 0.5 dB/mm loss is expected from poly-Si losses.

### 3. Static characterization

<figure><img src="image_5.png" /><figcaption>Fig. 3. (a) Transmission Electron Micrograph of the fabricated capacitive modulator active region, (b) corresponding mode electric field and (c) TEM view of the active region including an additional thin layer of strained SiGe.</figcaption></figure>

0.7 mm-long phase shifters (Fig. 3) are embedded in asymmetric Mach Zehnder Interferometers. From the measurement of the transmission of the MZI as a function of the bias applied in one arm, static phase shifter efficiencies are derived by tracking the wavelength shift of the
spectrum dips (Fig. 4) [5]. The phase shift with respect to 0 V is plotted in Fig. 4(a) against the equivalent oxide thickness derived from capacitance measurement at 2.5 V (in accumulation regime) which is inversely proportional to insulator thickness. At 0.9 V, the phase shift lies at 10°/mm, corresponding to a depletion regime, in which the modulation does not depend on oxide thickness but on the doping levels only. At 1.8 V, the phase shift is increasing with decreasing oxide thickness. This corresponds to the accumulation regime. Indeed, while the oxide thickness decreases, more free carriers are gathering at oxide interfaces, providing higher efficiency. At 4 nm oxide thickness, 60°/mm are measured between 0.9 V and 1.8 V, which corresponds to $V_πL_π = 2.7V.mm$.

<figure><img src="image_6.png" /><figcaption>Fig. 4. Static electro-optic characterization: (a) extracted phase shifts for different oxide thicknesses (W=400 nm) and (b) as a function of device width with and without SiGe layer.</figcaption></figure>

Electro-optical simulations are overlaid in Fig. 4(a). In order to compute effective indices with Lumerical mode finite element solver [20, 22], 2D electrical simulations of free carrier densities are first investigated with Sentaurus process and device solvers [21]. An optimal fit between derived static phase shift and measurements depends strongly on simulated input doping concentration in poly-Si. The final active phosphorous concentration (n-type) is $2 \times 10^{16}$ at/cm$^3$ in the poly-Si top part of the waveguide, which is 20 times lower than the actual implanted phosphorous dose. This low effective doping can be explained by the boundaries effects in polysilicon [27]. As a consequence, the depletion region in poly-Si is wider than in p-Si implanted with the same dose level, leading to a low-efficiency depletion regime at 0.9 V.

The phase shift is also plotted against waveguide width and applied DC bias (Fig. 4(b)), with and without integration of a SiGe strained layer below the 13 nm thick insulator (deposited oxide). First we observe that the phase shift does not depend much on waveguide width above 400 nm. Below this optimal width, mode confinement starts degrading the overlap factor at the cost of efficiency. Secondly, SiGe thin layer epitaxy boosts the efficiency with a gain above 20% thanks to higher accumulated hole electro-optic efficiency in strained SiGe [8]. A minor contribution to the gain can arise from a better electrooptic overlap due to the thickness of the SiGe layer itself. Indeed, hole accumulation region is shifted 20 nm higher in the waveguide thickness as compared with samples without SiGe, hence closer to mode maximum intensity.

Insertion losses are measured on 0.5 mm long active capacitive waveguides. After normalization of grating couplers ($2 \times 2.5$ dB) and adiabatic transitions ($2 \times 0.6$ dB), total propagation losses reduce to 3 dB/mm at 1.8 V through the active region, including only 0.5 dB/mm of absorption in poly-Si [25, 28]. Compared to PN junctions, the accumulation regime of capacitive modulators increases losses with applied voltage (above flat-band voltage) as free carrier density increases
within the waveguide. Indeed, 1.8 V losses are a worse case than 0.9 V.

The total capacitance may impede these static performances in dynamic operation. An optimal trade-off between device length, optical modulation amplitude and electrical RC constant is found for oxide thicknesses around 13 nm and waveguide width around 400 nm. The corresponding efficiency is around 15°/mm (between 0.9 V and 1.8 V) with 3 dB/mm for a measured total electrical static capacitance of C=1.2 pF/mm in accumulation regime. The extrapolated power consumption at optimal optical modulation amplitude is expected below 1 pJ/bit (0.9Vpp swing, 2 × 2 mm in PUSH-PULL configuration). A 20% gain from the SiGe layer is expected with reasonable capacitance increase (around 10%).

## 4. Dynamic characterization

<figure><img src="image_7.png" /><figcaption>Fig. 5. Dynamic S-parameters: (a) measured $S_{12}$, (b) measured and model $S_{11}$.</figcaption></figure>

In order to evaluate the limitation of capacitance on device bandwidth, first dynamic characterizations are performed on samples without SiGe. First, active region bandwidth is characterized by the electro-optic transmission $S_{12}$ (Fig. 5(a)). The selected device is designed with reduced access resistance thanks to aggressive doping profiles with high levels close to the propagating mode. Its capacitance is also reduced for improved electrical bandwidth by using thick oxide (15 nm) and a narrow waveguide width (W=320 nm). Single drive measurements give a 4 GHz bandwidth (0.9 Vpp in accumulation regime) depending on the applied DC bias.

The lumped reflection coefficient $S_{11}$ is then analyzed with a small signal equivalent circuit model (Fig. 5(b)). From this model, we derive that the reduced 4 GHz bandwidth comes from an access resistance nearly 10 times higher than expected in simulations (simulated waveguide resistance <5 Ω.mm when assuming a full dopant activation). By strongly improving doping profiles in the electrical access arms, especially increasing active dopant concentration at poly-Si side, it is expected that the access resistance will decrease. A careful doping profile engineering is needed in order to strongly decrease access resistance with reduced damages on insertion losses.

## 5. Conclusion

First integration of capacitive phase shifters in a 300 mm silicon photonics platform has been demonstrated. It can optimally provide a 15°/mm efficiency with low driving voltages of 0.9 Vpp, ready for low power CMOS technology. Corresponding insertion losses are as low as 3 dB/mm
thanks to the development of low loss poly-silicon and to a careful design of the doped layers within the waveguide. The addition of a thin SiGe layer brings an additional 20% gain in efficiency and is interesting for pursuing the race towards highest photonic link throughput.

## Funding

European project Cosmicc (H2020-ICT-27-2015-688516)

## References

1. D. Thomson, A. Zilkie, J. Bowers, T. Komljenovic, G. Reed, L. Vivien, D. Marris-Morini, E. Cassan, L. Virot, J.-M. Fedeli, J.-M. Hartmann, J. Schmid, D.-X. Xu, F. Boeuf, P. O'Brien, G. Mashanovich, and M. Nedeljković "Roadmap on silicon photonics," J. Opt. **18**, 1–20 (2016).

2. D. Mahgerefteh, C. Thompson, C. Cole, G. Denoyer, T. Nguyen, I. Lyubomirsky, C. Kocot, and J. Tatum "Techno-Economic Comparison of Silicon Photonics and Multimode VCSELs," J. Light. Technol. **34**, 233–242 (2016).

3. F. Boeuf and K. Ouellette "Industrialization of Si-Photonics into a 300nm CMOS fab," in "2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)," (IEEE, 2016), pp. 1–2.

4. G. T. Reed, G. Mashanovich, F. Y. Gardes, and D. J. Thomson "Silicon optical modulators," Nat. Photonics **4**, 518–526 (2010).

5. D. Pérez-Galacho, C. Baudot, T. Hirtzlin, S. Messaoudène, N. Vulliet, P. Crozat, F. Boeuf, L. Vivien, and D. Marris-Morini "Low voltage 25Gbps silicon Mach-Zehnder modulator in the O-band," Opt. Express **25**, 11217 (2017).

6. E. Temporiti, G. Minoia, M. Repossi, D. Baldi, A. Ghilioni, and F. Svelto "23.4 A 56Gb/s 300mW silicon-photonics transmitter in 3D-integrated PIC25G and 55nm BiCMOS technologies," in "Solid-State Circuits Conference (ISSCC), 2016 IEEE International," (IEEE, 2016), pp. 404–405.

7. T. Ferrotti, B. Blampey, C. Jany, H. Duprez, A. Chantre, F. Boeuf, C. Seassal, and B. B. Bakir "Co-integrated 13µm hybrid III-V/silicon tunable laser and silicon Mach-Zehnder modulator operating at 25gb/s," Opt. Express **24**, 30379 (2016).

8. J. Fujikata, K. Kinoshita, J. Han, T. Horikawa, S. Takahashi, K. Yashiki, M. Kurihara, Y. Hagihara, M. Takenaka, T. Nakamura, K. Kurata, and T. Mogami "High-Performance Si Optical Modulator with Strained p-SiGe Layer and its Application to 25 Gbps Optical Transceiver," (Berlin, 2017), p. WD.3.

9. S. Shao, J. Ding, L. Zheng, K. Zou, L. Zhang, F. Zhang, and L. Yang "Optical PAM-4 signal generation using a silicon Mach-Zehnder optical modulator," Opt. Express **25**, 23003 (2017).

10. R. Li, D. Patel, A. Samani, E. El-Fiky, Z. Xing, M. Sowailem, Q. Zhong, and D. V. Plant "An 80 Gb/s Silicon Photonic Modulator Based on the Principle of Overlapped Resonances," IEEE Photonics J. **9**, 1–11 (2017).

11. Z. Yong, W. D. Sacher, Y. Huang, J. C. Mikkelsen, Y. Yang, X. Luo, P. Dumais, D. Goodwill, H. Bahrami, P. G.-Q. Lo, E. Bernier, and J. K. S. Poon "U-shaped PN junctions for efficient silicon Mach-Zehnder and microring modulators in the O-band," Opt. Express **25**, 8425 (2017).

12. D. Vermeulen, R. Aroca, L. Chen, L. Pellach, G. McBrien, and C. Doerr "Demonstration of Silicon Photonics Push-Pull Modulators Designed for Manufacturability," IEEE Photonics Technol. Lett. **28**, 1127–1129 (2016).

13. M. Douix, D. Marris-Morini, C. Baudot, S. Cremer, D. Rideau, D. Perez-Galacho, A. Souhaite, R. Blanc, E. Batail, N. Vulliet, L. Vivien, E. Cassan, and F. Boeuf "Design of integrated capacitive modulators for 56gbps operation," (IEEE, 2016), pp. 5–7.

14. A. Abraham, S. Olivier, D. Marris-Morini, and L. Vivien "Evaluation of the performances of a silicon optical modulator based on a silicon-oxide-silicon capacitor," in "Group IV Photonics (GFP), 2014 IEEE 11th International Conference on," (IEEE, 2014), pp. 3–4.

15. A. Shastri, C. Muzio, M. Webster, G. Jeans, P. Metz, S. Sunder, B. Chattin, B. Dama, and K. Shastri "Ultra-Low-Power Single-Polarization QAM-16 Generation Without DAC Using a CMOS Photonics Based Segmented Modulator," J. Light. Technol. **33**, 1255–1260 (2015).

16. M. Sodagar, A. H. Hosseinnia, P. Isautier, H. Moradinejad, S. Ralph, A. A. Eftekhar, and A. Adibi "Compact, 15 Gb/s electro-optic modulator through carrier accumulation in a hybrid Si/SiO₂/Si microdisk," Opt. Express **23**, 28306 (2015).

17. J. Van Campenhout, M. Pantouvaki, P. Verheyen, S. Selvaraja, G. Lepage, H. Yu, W. Lee, J. Wouters, D. Goossens, M. Moelants "Low-voltage, low-loss, multi-Gb/s silicon micro-ring modulator based on a MOS capacitor," in "Optical Fiber Communication Conference and Exposition (OFC/NFOEC), 2012 and the National Fiber Optic Engineers Conference," (IEEE, 2012), pp. 1–3.

18. D. A. B. Miller "Energy consumption in optical modulators for interconnects," Opt. Express **20**, A293–A308 (2012).

19. C. Baudot, A. Fincato, D. Fowler, D. Perez-Galacho, A. Souhaité, S. Messaoudène, R. Blanc, C. Richard, J. Planchot, C. De-Buttet, B. Orlando, F. Gays, C. Mezzomo, E. Bernard, D. Marris-Morini, L. Vivien, C. Kopp, and F. Boeuf "DAPHNE silicon photonics technological platform for research and development on WDM applications," in "Silicon Photonics and Photonic Integrated Circuits V," (SPIE Photonics Europe, 2016), p. 98911D.

20. Lumerical Inc. "Innovative Photonic Design Tools," https://www.lumerical.com/ (2017).
21. Synopsys Inc. "Synopsys Inc. Sentaurus TCAD," https://www.synopsys.com/silicon/tcad.html (2017).

22. M. Nedeljkovic, R. Soref, and G. Z. Mashanovich "Free-Carrier Electrorefraction and Electroabsorption Modulation Predictions for Silicon Over the 1-14-µm Infrared Wavelength Range," IEEE Photonics J. 3, 1171–1180 (2011).

23. S. M. Sze *Physics of Semiconductor Devices* (Wiley, 1981), 2nd ed.

24. G. Rasigade, D. Marris-Morini, M. Ziebell, E. Cassan, and L. Vivien "Analytical model for depletion-based silicon modulator simulation," Opt. express 19, 3919–3924 (2011).

25. M. Douix, C. Baudot, D. Marris-Morini, A. Valéry, D. Fowler, P. Acosta-Alba, S. Kerdilès, C. Euvrard, R. Blanc, R. Beneyton, A. Souhaité, S. Crémer, N. Vulliet, L. Vivien, and F. Boeuf "Low Loss Poly-Silicon for High Performance Capacitive Silicon Modulators," Opt. Express, Opt. Soc. Am. 26, 5983–5990 (2018).

26. F. Boeuf, J.-H. Han, S. Takagi, and M. Takenaka "Benchmarking Si, SiGe, and III-V/Si Hybrid SIS Optical Modulators for Datacenter Applications," J. Light. Technol. 35, 4047–4055 (2017).

27. T. I. Kamins *Polycrystalline silicon for integrated circuit applications*, no. SECS 45 in Kluwer international series in engineering and computer science (Kluwer Academic Publishers, 1988).

28. S. Zhu, G. Q. Lo, J. D. Ye, and D. L. Kwong "Influence of RTA and LTA on the Optical Propagation Loss in Polycrystalline Silicon Wire Waveguides," IEEE Photonics Technol. Lett. 22, 480–482 (2010).