# Metal-insulator transition in annealed Mos2 devices

Ivanovitch Castillo Arvelo, Thibault Sohier, Matthieu Paillet, Julien Chaste, Matthieu Verstraete, Abdelkarim Ouerghi, Benoit Jouault, Sébastien Nanot

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## To cite this version:

Ivanovitch Castillo Arvelo, Thibault Sohier, Matthieu Paillet, Julien Chaste, Matthieu Verstraete, et al. Metal-insulator transition in annealed Mos2 devices. HOWDI 2022 Annual meeting, May 2022, Dourdan, France. hal-04794024

HAL Id: hal-04794024

https://hal.science/hal-04794024v1

Submitted on 20 Nov 2024

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GDR HOWDI 2022 MEETING:
METAL-INSULATOR TRANSITION IN ANNEALED MOS₂ DEVICES

Ivanovitch Castillo Arvelo¹, Thibault Sohier¹,², Matthieu Paillet¹, Julien Chaste³, Matthieu Verstraete², Abdelkarim Ouerghi³, Benoit Jouault¹, Sébastien Nanot¹

¹Laboratoire Charles Coulomb (L2C), Université de Montpellier, CNRS, Montpellier 34095, FRANCE

²Nanomat/QMAT/CESAM, University of Liège, Liège 4000, BELGIUM

³Centre de Nanosciences et de Nanotechnologies (C2N), Université Paris-Saclay, Palaiseau 91120, FRANCE

Single-layer MoS₂ has been widely studied due to its promising electronic and optoelectronic properties, which can be efficiently tuned by electrostatic doping in a transistor configuration [1]. To consider actual applications, a perfect understanding and control of the contacts and transport regime in the devices is required [2-3]. We present a systematic study of the transport characteristics of monolayer MoS₂ as a function of electron density and temperature. High quality MoS₂ flakes are grown by CVD on a Si/SiO₂ substrate, then plasma etched into the desired shape and top-contacted with Ti/Au through electron beam lithography (Fig. 1).

More than 10 devices were studied by electrical measurements after in-situ annealing at 600 K under vacuum. The 2- and 4-probe resistance was systematically recorded as a function of temperature (down to 20 K), gate voltage and source-drain voltage. In this presentation, we will focus on the intrinsic conductivity of the MoS₂ channel (4-probe measurements). For all the devices the conductivity increases with gate voltage and the apparent threshold voltage decreases with temperature. Insulating or metallic-type temperature dependencies are observed (without the need of top-gating or high-k dielectric capping) depending on carrier density (see Fig. 2), with a transition occurring around 2x10¹² cm⁻². The devices exhibit high mobilities at low temperature (for CVD MoS₂ on SiO₂) on the order of 200 cm²/Vs, with a nontrivial dependence between the gate voltage and the density of occupied states above the mobility edge (i.e., extended states).

A detailed analysis with different models fitting these results [3,4] will be presented to clearly elucidate the dominant transport mechanism for each doping and temperature range. For low gate voltages, thermally activated and variable-range hopping transport of in-gap states explain the drastic change in threshold voltage and the insulating transport [e.g. Ref. 2]. For higher gate voltages, the metallic behavior is well explained by phonon and static defects scattering, in agreement with a theoretical model done through a full energy- and momentum-dependent Boltzmann transport equation [5]. All these results are consistent with other device characterization such as Raman spectroscopy. We will show that this metal-insulator transition also matches more elaborate models involving quantum phase transitions. We will tentatively discuss how this approach can be reconciled with the previous models, which are more consistent with the temperature and mobility ranges observed.

References

[1] Radisavljevic, B et al., *Nature Nanotechnology*, **3** (2011), pp. 147-150.

[2] Songang Peng et al., *Advanced Electronics Materials*, **7** (2019), p. 1900042.

[3] Byoung Hee Moon et al., *Nature Communications*, **9** (2018), p. 2052.

[4] S. Das Sarma and E. H. Hwang, *Scientific Reports*, **5** (2015), p. 16655.

[5] T. Sohier et al., *Physical Review Materials*, **2** (2018), p. 114010.

<figure><img src="image_3.png" /><figcaption>**Figure 1:** SEM Image of a typical device in Hall bar shape (MoS₂, SiO₂ and Au from dark to light gray).</figcaption></figure>

<figure><img src="image_4.png" /><figcaption>**Figure 2:** Typical conductivity versus gate voltage characteristic. One can notice that the conductivity increases with gate voltage (conductivity band doping), and either increases or decreases with temperature, corresponding to what is typically called a metallic or insulating behavior respectively.</figcaption></figure>