# Modeling of the steady-state ac current fluctuation in two-stage electric car fast chargers based on solid-state transformers

David Elizondo-Martinez, Ernesto L. Barrios, Pablo Sanchis

PUBLIC UNIVERSITY OF NAVARRE (UPNA), DEPT. OF ELECTRICAL, ELECTRONIC AND COMMUNICATIONS ENGINEERING

Campus Arrosadia
Pamplona, Spain

E-Mail: david.elizondo@unavarra.es

URL: https://www.unavarra.es/home

## ACKNOWLEDGMENT

This work is partially funded by UPNA, and is part of the Projects PID2022-142791OB-I00 and TED2021-132604B-I00, funded by MICIU/AEI /10.13039/501100011033, by ERDF/UE and by the European Union NextGenerationEU/PRTR.

**Index Terms**—Electric vehicle (EV), solid-state transformer, analytical model, DC-DC power converter.

**Abstract**—Two-stage conversion structures are increasingly attracting attention, particularly for electric vehicles fast charging, and those based on a solid-state transformer (SST) and with a postregulator stand out. As a consequence of this postregulator, there is a steady-state fluctuation in the ac current of the SST, which turns into a greater rms current value that can impact on the converter performance. Hence, an analytical formula of this fluctuation should be considered during the design process. This work proposes a model for two different conversion structures (two-level and three-level), which is validated through simulations. The design process can be benefited from implementing the presented model, as it shows the interactions between the two power conversion stages and allows accomplishing a limited current fluctuation in the SST while avoiding more expensive and bulkier dc-link capacitors than necessary.

## I. INTRODUCTION

Two battery systems coexist nowadays in the electric car market: the 400 V and the 800 V battery systems [1]. As a consequence, dc fast chargers shall provide a wide output voltage, typically from 200 V up to 900 V [2],

<figure><img src="image_1.png" /><figcaption>Fig. 1. Diagram of a full-power, two-stage postregulated converter.</figcaption></figure>

if they aim to being able to recharge the battery of any modern electric car.

In single-stage conversion topologies, the ample operating region of the EV charger requires the dc-dc isolated converter, such as a dual active bridge or a resonant converter, to vary its voltage gain within a large range, to the detriment of the converter efficiency [3]. A promising step towards higher efficiency are the so-called two-stage converters, which comprise of an isolated dc-dc power stage and a regulating stage. The most common conversion structure is based on an *LLC* resonant converter working as a solid-state transformer (SST) or dc transformer (DCX) [4].

In the last years, the two-stage postregulated converters have gathered notable attention [5]–[8]. They consist of two-stage conversion structures where the regulator is placed after the dc-dc isolated stage. There are solutions where the regulating power stage only delivers part of the total power, known as partial-power converters [5], [6]. Alternatively, the regulator can handle the whole power. Those structures, exemplified in the block diagram of Fig. 1, are called full-power converters [7], [8].

In any postregulated conversion structure, the regulator demands a discontinuous current intensity in the form
of a rectangular wave, as it is a switching converter. As a result, there is a fluctuation in the ac current intensity of the SST (that is, the dc-dc isolated stage), both in the primary and the secondary sides, which increases the rms value of the current through the semiconductors and the transformer, although it does not carry active power.

The fluctuation in the ac currents of the SST is intrinsic to two-stage converters and remains in steady state. It leads to increased power losses and can affect the converter performance, so it is useful to estimate it and analyze how it can be limited by means of a proper hardware design. Not addressing this matter during the design process can lead to large current fluctuations in the SST, even if large dc-link capacitances are placed.

The main goal of this work is to propose an analytical model of the ac current fluctuation in two different conversion architectures: the two-stage, two-level (2S2L) converter and the two-stage, three-level (2S3L) converter.

## II. REVIEW OF THE 2S2L AND 2S3L CONVERTERS

The 2S2L converter is a full-power two-stage, two-level conversion architecture, as represented in Fig. 2 (a). It comprises of a conventional LLC resonant converter (Stage 1), and a buck converter (Stage 2). Stage 1 is characterized by operating as a solid-state transformer (SST), as it is unregulated with a fixed duty cycle $d_1 = 0.5$ and a fixed switching frequency $f_{sw1}$. The inverter of Stage 1 switches just below (or at) the series resonant frequency $f_{r1}$. The resonance is between the series capacitor $C_r$ and the leakage inductance $L_{lk}$ of the transformer. Switching with $f_{sw1} \le f_{r1}$ enables that the LLC converter of Stage 1 works as an SST. Hence, the ac current in Stage 1 is piece-wise sinusoidal. The current of the secondary side under ideal conditions (no fluctuations) can be expressed for the 2S2L converter as [9]:

$$ 
\begin{aligned}
i_{2*} &= \frac{P\pi n_{2L}}{2kV_{DD1}} \sin(2\pi f_{sw1}/kt), \quad t \in [0, T_{r1}/2) \\
&= 0, \quad t \in [T_{r1}/2, T_{sw1}/2),
\end{aligned} 
\quad (1) 
$$

being equal, but negative, for $t \in [T_{sw1}/2, T_{sw1})$. The delivered power is noted as $P$; $n_{2L}$ is the 2S2L transformer turns ratio; the switching-to-resonant frequency ratio is $k = f_{sw1}/f_{r1}$; the input dc-link voltage of the LLC resonant converter is $V_{DD1}$; and $T_{r1} = 1/f_{r1}$ is the period of the series resonance in the LLC resonant converter.

As Stage 1 behaves as an SST, the voltage gain of the converter is constant, so the dc output voltage is $V_{DD2} = V_{DD1}/n_{2L}$. Then, Stage 2 is in charge of

stepping down the voltage and match it to the battery voltage $V_B$, delivering the desired power. Therefore, Stage 2 acts as a postregulator. Its switching frequency is $f_{sw2}$ (switching period $T_{sw2}$), and its duty cycle is $d_2$.

The buck converter delivers to the battery the same average power as does the LLC resonant converter when the 2S2L converter operates under steady-state conditions. Nevertheless, both Stage 1 and Stage 2 are switching converters, so the in and out power flows are not instantaneously equal at their dc link, consisting in capacitor $C_2$ [see Fig. 2 (a)]. As shown in Fig. 2 (b), during the on time of $S_h$ in the buck converter, $d_2T_{sw2}$, the current through $C_2$ is $i_{C_2} = |i_2| - I_{DD2} = |i_2| - i_3 < 0$, where $|i_2|$ is the output rectified current from Stage 1, and $i_3$ is the output current of Stage 2. During the off time of $S_h$, $i_{C_2} = |i_2| - I_{DD2} = |i_2| > 0$. As illustrated in Fig. 2 (b), the output current of Stage 1 (input of Stage 2), $I_{DD2}$, is a rectangular current waveform where the high and low values are $i_3$ and zero, respectively, with a frequency $f_{sw2}$ and a duty cycle $d_2$. As a consequence of the discontinuous power demanded by Stage 2, $i_2$ of Stage 1 experiments a fluctuation in steady state at $f_{sw2}$, which can be seen in $|i_2|$ plotted in Fig. 2 (b).

The 2S3L converter, which is presented in [8], is a full-power two-stage, three-level conversion architecture whose circuit schematic appears in Fig. 3 (a). In this case, Stage 1 is a modified LLC resonant converter that comprises of two identical resonant blocks (top and bottom) connected in series at the output, generating two dc half-buses with voltages $V_{DD2t}$ and $V_{DD2b}$, respectively. The resonant blocks work as SST, so $f_{sw1}$ and their voltage gains are fixed. Their ac currents are piece-wise sinusoidal and equal under ideal conditions (identical resonant blocks and no fluctuations). They can be expressed for the 2S3L converter as follows:

$$ 
\begin{aligned}
i_{2t*} &= i_{2b*} = \\
&= \frac{P\pi n_{3L}}{4kV_{DD1}} \sin(2\pi f_{sw1}/kt), \quad t \in [0, T_{r1}/2) \\
&= 0, \quad t \in [T_{r1}/2, T_{sw1}/2),
\end{aligned} 
\quad (2) 
$$

being equal, but negative, for $t \in [T_{sw1}/2, T_{sw1})$. It must be noted that each resonant block carries half of the total power $P$, and that $n_{3L}$ is the 2S3L transformer turns ratio, which is $n_{3L} = 2n_{2L}$ if the same output dc-link voltage $V_{DD2} = V_{DD2t} + V_{DD2b}$ wants to be obtained from the same input dc voltage $V_{DD1}$.

Stage 2 comprises of a three-level buck converter as the postregulator. It is connected to the SST output dc link, which provides a midpoint connection whose
<figure><img src="image_2.png" /><figcaption>Fig. 2. 2S2L converter: (a) Circuit. (b) Representative waveforms.</figcaption></figure>

voltage is fixed by Stage 1, ensuring that $V_{DD2t}$ and $V_{DD2b}$ are always balanced. Further details on the 2S3L converter can be found in [8].

Fig. 3 (b) shows an example of the key waveforms in the dc link between Stage 1 and Stage 2, for a duty cycle $d_2 < 0.5$ of the latter power stage. It can be seen that $I_{DD2t}$ and $I_{DD2b}$ are the currents demanded by Stage 2 to the top and bottom resonant blocks of Stage 1, respectively. Both are identical rectangular waveforms, with duty cycle $d_2$, but shifted $180^\circ$. $I_{DD2t}$ is $i_3$ when the switch $S_{th}$ is on, during $d_2T_{sw2}$, and is zero otherwise. $I_{DD2b}$ is $i_3$ when $S_{bl}$ is on, during $d_2T_{sw2}$, and is zero the rest of the period.

The top capacitor $C_{2t}$ current is $i_{C_{2t}} = |i_{2t}| - i_3 < 0$, when $S_{th}$ is on and $I_{DD2} = i_3$. The current intensity $|i_{2t}|$ is the secondary current of Stage 1 top resonant block once rectified by the diode bridge (switches $S_{5t} - S_{8t}$). When $S_{th}$ is off, $I_{DD2} = 0$ and $i_{C_{2t}} = |i_{2t}| > 0$. As in the 2S2L converter, a permanent fluctuation in the ac current of Stage 1 can be seen in Fig. 3 (b) for the 2S3L converter, as a consequence of the discontinuous current

<figure><img src="image_3.png" /><figcaption>Fig. 3. 2S3L converter: (a) Circuit. (b) Representative waveforms.</figcaption></figure>

demand from the buck converter (Stage 2).

In both the 2S2L and the 2S3L converters, the frequency of the rectangular waveform $I_{DD2}$ (or $I_{DD2t}$ and $I_{DD2b}$) is the switching frequency $f_{sw2}$ of Stage 2, so the ac current in Stage 1 fluctuates at that frequency. It must be noted too that Stage 1 in both converters can work under soft-switching conditions in all its semiconductors [8], [9], which enables a higher switching frequency $f_{sw1}$ in the SST than the one achievable in the postregulator.

### III. MODELING OF THE AC CURRENT FLUCTUATION IN THE *LLC* RESONANT CONVERTER

The models derived in this work for the 2S2L and the 2S3L converters are based on the dynamic passive equivalent circuit for piece-wise sinusoidal currents used in [10]. The model is extended in this paper to two-stage power conversion architectures, which show steady-state
current fluctuations. The 2S2L converter model is more generic and applicable to other two-stage conversion structures, being partial-power or full-power converters. The one for the 2S3L converter is a particular case of the first.

The analysis hereafter considers the following assumptions:

* The converters are lossless.

* The magnetizing inductance of the transformer is much larger than the leakage inductance, $L_m \gg L_{lk}$, so its effect in the models can be neglected.

* The dc-link capacitors are much larger than the resonant capacitor, $C_1, C_2, C_{2t}, C_{2b} \gg C_r$.

## A. Definition of the ac current affected by the fluctuation

Firstly, a conventional SST directly connected to the load is considered, i.e. without postregulation. Once in steady state, its dc output current $I_{DD2*}$ and its ac current would be as represented in Fig. 4 (a). The instantaneous value of the secondary ac current is noted as $i_{2*}$. The local average value of $i_{2*}$ over half of a switching period $T_{sw1}/2$ is noted as $\bar{i}_{2*}$, and the peak value or enveloping of $i_{2*}$ is $\hat{i}_{2*}$. Since the converter is delivering a constant instantaneous power, $I_{DD2*}$, $\bar{i}_{2*}$ and $\hat{i}_{2*}$ are all constant. The relationship between the last two values is [10]:

$$ \hat{i}_{2*} = \alpha \bar{i}_{2*}, \quad (3) $$

where $\alpha$ is defined as:

$$ \alpha = \frac{\pi f_{r1}}{2 f_{sw1}} = \frac{\pi}{2k}. \quad (4) $$

When the SST is connected to a switching converter, as it is the case in postregulated two-stage architectures, the current demanded by the second converter is not constant in steady state. This is illustrated by means of $I_{DD2}$ in the top graph of Fig. 4 (b). The postregulator (Stage 2) can be modeled as a current source. The dc current component of this source is related to $P$, and it is equal to $\bar{I}_{DD2*}$ and thus, to $d_2 I_B$, as the output current of Stage 2 is the battery current $I_B$. The ac current component, noted as $\bar{I}_{DD2*}$, is the first harmonic of $I_{DD2}$ and can be defined as:

$$ \bar{I}_{DD2*} = \frac{2}{\pi} I_B \sin(\pi d_2) \cos(2\pi f_{sw2} t), \quad (5) $$

since $I_{DD2}$ is a rectangular waveform of duty cycle $d_2$. The notation in $\bar{I}_{DD2*}$ with the overline shows that this component causes the fluctuation of the instantaneous active power demanded to the unregulated LLC resonant

<figure><img src="image_4.png" /></figure>

<figure><img src="image_5.png" /><figcaption>Fig. 4. Current intensity in the output and in the secondary ac side of the LLC resonant converter (SST), in steady state: (a) Directly connected to a load. (b) Connected to a switching converter.</figcaption></figure>

converter, thus causing its current $i_2$ to fluctuate too, as can be seen in the bottom graph of Fig. 4 (b). As a result, the local average value $\bar{i}_2$ and the peak value or enveloping $\hat{i}_2$ are no longer constant. Each comprises of a dc or constant value plus an ac component at the first-harmonic frequency of $I_{DD2}$.

If the same average active power $P$ is delivered by both systems – SST alone as in Fig. 4 (a) and SST with postregulator as in Fig. 4 (b) – the dc component of $\bar{i}_2$ is equal to $\bar{i}_{2*}$. The same for $\hat{i}_2$, whose dc component is $\hat{i}_{2*}$. The ac components are noted as $\bar{i}_{2*}$ and $\hat{i}_{2*}$, respectively. Therefore, the local average value and the peak or enveloping value can be expressed according to:

$$ \begin{aligned} \bar{i}_2 &= \bar{i}_{2*} + \bar{i}_{2*}, \\ \hat{i}_2 &= \hat{i}_{2*} + \hat{i}_{2*}. \end{aligned} \quad (6) $$
which are depicted in the bottom graph of Fig. 4 (b). The peak-to-peak values of the local average ac component $\tilde{i}_{2\sim}$ and the enveloping ac component $\tilde{i}_{2\sim}$ are defined as $\Delta\tilde{I}_{2\sim}$ and $\Delta\hat{I}_{2\sim}$, respectively, and satisfy:

$$ \Delta\hat{I}_{2\sim} = \alpha\Delta\bar{I}_{2\sim}. \qquad (7) $$

In this work, each two-stage converter is modeled in steady state as the superposition of two equivalent circuits: a dc circuit, whose variables are constant, and an ac circuit, whose variables are sinusoidal at the switching frequency of the postregulator. Firstly, the model for $\Delta\hat{I}_{2\sim}$ is obtained for the two-level converter, the so-called 2S2L. That is, a model is derived for the peak-to-peak value of the enveloping of the ac current in the SST. Secondly, $\Delta\hat{I}_{2t\sim}$ and $\Delta\hat{I}_{2b\sim}$, which are equal due to symmetry between the top and bottom resonant blocks, are also modeled for the 2S3L converter.

## B. Modeling of the ac current fluctuation in the 2S2L converter

Considering the LLC resonant converter (Stage 1) of Fig. 2 (a), it can be assumed that under steady-state conditions $I_{DD1} = \bar{I}_{DD1*}$, so the input of the inverter is a constant-current source. The output current $I_{DD2}$ however is not constant, due to the switching buck converter (Stage 2). The 2S2L converter can be represented by means of superposition through two dynamic equivalent circuits: a dc circuit [see Fig. 5 (a)], whose variables are constant in steady state and noted with an asterisk; and an ac circuit [see Fig. 5 (b)], whose variables are sinusoidal and oscillate at the switching frequency $f_{sw2}$ of Stage 2. The latter are noted with the subscript $\sim$.

The delivered average power $P$ can be expressed as the product $\bar{V}_{DD1*}\bar{I}_{DD1*}$. As Stage 1 is an SST, $\bar{V}_{DD1*} = \bar{V}'_{DD2*}$, where $\bar{V}'_{DD2*}$ is the dc component of $V_{DD2}$ referred to the primary. Therefore, attending to the circuit in Fig. 5 (a) and the input-to-output power balance, it is obtained that $\bar{I}_{DD1*} = \bar{i}'_{2*} = \bar{I}'_{DD2*} = d_2\bar{I}'_B$.

The main interest is on the ac equivalent circuit of Fig. 5 (b). This dynamic equivalent model is obtained considering the local average value of the system variables. The energy in the converter is stored in the input dc-link capacitor $C_1$, in the transformer leakage inductance $L_{lk}$, and in the output dc-link capacitor $C_2$. In the equivalent model, regarding the local average value of the voltages and the currents, the dc-link capacitors are

<figure><img src="image_6.png" /><figcaption>Fig. 5. Equivalent model of the 2S2L converter: (a) DC. (b) AC.</figcaption></figure>

directly $C_1$ and $C_2$, but the equivalent series inductance is $L_{dc}$, which can be calculated as follows [10]:

$$ L_{dc} = \alpha^2 L_{lk}. \qquad (8) $$

As it has been previously introduced, the postregulator can be modeled as a current source with a dc component $\bar{I}'_{DD2*}$ and an ac component $\bar{I}'_{DD2\sim}$, both referred to the primary side. Considering the ac equivalent circuit, the peak-to-peak value of $\bar{I}'_{DD2\sim}$ is obtained from (5) as:

$$ \Delta\bar{I}'_{DD2\sim} = \frac{4}{\pi n_{2L}} I_B \sin(\pi d_2). \qquad (9) $$

Solving the circuit in Fig. 5 (b) by means of the peak-to-peak values, it is obtained that the peak-to-peak value of the enveloping of the ac current can be calculated as follows:

$$ \Delta\hat{I}'_{2\sim} = \Delta\bar{I}'_{DD2\sim} \frac{\alpha}{\left| 1 + \frac{C_2'}{C_1} - (2\pi f_{sw2})^2 L_{dc} C_2' \right|}, \qquad (10) $$

where the factor $\alpha$ has already been defined in (4). By substituting (8) and $C_2' = C_2/n_{2L}^2$ in (10), the following formula is obtained:

$$ \Delta\hat{I}'_{2\sim} = \frac{\Delta\bar{I}'_{DD2\sim}\alpha}{\left| 1 + \frac{C_2}{C_1 n_{2L}^2} - (2\pi f_{sw2}\alpha)^2 L_{lk} \frac{C_2}{n_{2L}^2} \right|}. \qquad (11) $$

which models the peak-to-peak ac current fluctuation in the LLC resonant converter for the 2S2L architecture.
### C. Modeling of the ac current fluctuation in the 2S3L converter

In the 2S3L converter, Stage 1 comprises of a modified *LLC* resonant converter which comprises of a single dc input and two dc outputs that are connected in series, as represented in Fig. 3 (a). Following the same methodology as in subsection III-B for the 2S2L converter, the 2S3L converter under steady-state conditions can be expressed by means of the superposition of two equivalent circuits: a dc circuit, depicted in Fig. 6 (a); and an ac circuit operating at $f_{sw2}$, shown in Fig. 6 (b). The variables on the secondary side have been referred to the primary side.

It can be seen in both circuits of Fig. 6 that Stage 1 is split up in two parts meaning the two resonant blocks, which are identical. Hence, the circuit parts representing the top and bottom resonant blocks have the same dc equivalent inductance $L_{dc}$ and they share the power equally.

In the dc dynamic equivalent circuit of the 2S3L converter [see Fig. 3 (a)], the variables are constant in steady state, and they fulfill that:

$$ \begin{gathered} \overline{V}_{DD1*} = \overline{V}'_{DD2t*} = \overline{V}'_{DD2b*} = \overline{V}'_{DD2*}/2, \quad (12) \\ \overline{I}_{DD1*} = \overline{i}'_{2t*} + \overline{i}'_{2b*} = \overline{I}'_{DD2t*} + \overline{I}'_{DD2b*}, \end{gathered} $$

where $\overline{i}'_{2t*} = \overline{i}'_{2b*} = \overline{I}'_{DD2t*} = \overline{I}'_{DD2b*} = d_2 \overline{I}'_{B*}$.

In the 2S3L converter, it must be noted that the first-harmonic components of $I_{DD2t}$ and $I_{DD2b}$ [see Fig. 3 (b)] have the same amplitude, but with a phase shift of 180°. This must be considered in the current sources that model the postregulator in the ac dynamic equivalent circuit [see Fig. 3 (b)]. Therefore, $\Delta \overline{I}'_{DD2t} \sim \Delta \overline{I}'_{DD2b}$, regarding their peak-to-peak values. The same relationship is true for the ac current fluctuation in the top and bottom resonant blocks, which satisfy that $\Delta \overline{I}'_{2t} \sim \Delta \overline{I}'_{2b}$ for the local average value, and $\Delta \overline{I}'_{2t} \sim \Delta \overline{I}'_{2b}$ for the enveloping value. As a consequence of the symmetry of the top and bottom circuits and the 180° phase shift between their corresponding waveforms, it is obtained that:

* The combined effect of $\overline{I}'_{DD2t}$ and $\overline{I}'_{DD2b}$ of Stage 2 on the currents $\overline{i}'_{2t}$ and $\overline{i}'_{2b}$ of Stage 1 add up, as the two ac current sources have the same amplitude and are in counter phase, with their 'negative' terminals in common.

* The combined effect of $\overline{i}'_{2t}$ and $\overline{i}'_{2b}$ in the input dc-link voltage can be neglected, as they cancel out each other in the parallel connection point of the primary side in Stage 1. As a result, there is no ac

<figure><img src="image_7.png" /><figcaption>Fig. 6. Equivalent model of the 2S3L converter: (a) DC. (b) AC.</figcaption></figure>

current at the frequency of the fluctuation through $C_1$, and this capacitor plays no role in the 2S3L ac equivalent model.

* The ac currents and voltages in the ac circuit are equal for the top and bottom resonant blocks, but in counter phase. Hereafter, only the 'top' waveforms are considered in the calculations for the sake of simplicity.

Considering these properties, the ac dynamic equivalent circuit can be solved regarding the peak-to-peak values of the variables, resulting in:

$$ \Delta \overline{I}'_{2t} \sim \frac{\Delta \overline{I}'_{DD2t} \alpha}{\left| 1 - (2\pi f_{sw2}\alpha)^2 L_{lk} \frac{C_{2b}}{n_{3L}^2} \right|}, \quad (13) $$

which models the peak-to-peak ac current fluctuation in one resonant block of the *LLC* resonant converter for the 2S3L architecture. The factor $\alpha$ can be computed as in (4); $C_{2b}$ is the output dc-link capacitor of the bottom resonant block, equal to $C_{2t}$; and $\Delta \overline{I}'_{DD2t}$ can be expressed as:

$$ \Delta \overline{I}'_{DD2t} \sim \frac{4}{\pi n_{3L}} I_B \sin(\pi d_2), \quad (14) $$

which is the peak-to-peak value of the first harmonic of $I_{DD2t}$, referred to the primary side.

## IV. VALIDATION OF THE PROPOSED AC CURRENT FLUCTUATION MODELS

The obtained formulas for the peak-to-peak current fluctuation in the *LLC* resonant converters of the 2S2L
<table><caption>TABLE I
PARAMETERS OF THE 1<sup>ST</sup> SET OF SIMULATIONS</caption><thead><tr><th>Parameter</th><th>Symbol</th><th>Value</th></tr></thead><tbody><tr><td>Input cap.</td><td>C<sub>1</sub></td><td>[25, 100] &mu;F</td></tr><tr><td>Sw. freq. Stage 1</td><td>f<sub>sw1</sub></td><td>200 kHz</td></tr><tr><td>Sw.-to-res. freq. ratio</td><td>k</td><td>1</td></tr><tr><td>Leakage induct.</td><td>L<sub>lk</sub></td><td>[2.0, 2.5, 3.0] &mu;H</td></tr><tr><td>Turns ratio (2S2L)</td><td>n<sub>2L</sub> : 1</td><td>0.8:1</td></tr><tr><td>Turns ratio (2S3L)</td><td>n<sub>3L</sub> : 1</td><td>1.6:1</td></tr><tr><td>Sw. freq. Stage 2</td><td>f<sub>sw2</sub></td><td>[18, 24, 30, 36, 42, 48] kHz</td></tr><tr><td>Output cap. (2S2L)</td><td>C<sub>2</sub></td><td>80 &mu;F</td></tr><tr><td>Output cap. (2S3L)</td><td>C<sub>2t</sub>, C<sub>2b</sub></td><td>160 &mu;F</td></tr><tr><td>Duty cycle Stage 2</td><td>d<sub>2</sub></td><td>0.427</td></tr></tbody></table>

and the 2S3L conversion architectures are validated by means of simulations using the software PSIM. The main parameters of the simulated converters can be found in Table I.

The converters work within the operating area described in [8], which is for dc charging of electric cars and is considered as an application example. In the interval $d_2 \in [0.211, 0.427)$, the converter can deliver the maximum current $I_B = 37.5$ A to the battery, while in the range $d_2 \in (0.427, 0.947]$, it can deliver the rated power $P = 15$ kW.

It is interesting to calculate $d_2$ that maximizes the current fluctuation, as it is the worst-case scenario for a certain converter design. Considering the operating area in [8], it is obtained that $d_2 = 0.427$ is the operating point where both $\Delta\hat{I}'_{DD2\sim}$ in (9) for the 2S2L converter and $\Delta\hat{I}'_{DD2t\sim}$ in (14) for the 2S3L converter are maximized.

The results of the theoretical models (lines) and the simulations in PSIM (markers) are depicted in Fig. 7 (a) for $\Delta\hat{I}'_{2\sim}$ (2S2L architecture), and (b) for $\Delta\hat{I}'_{2t\sim}$ (2S3L architecture). It should be noted that the y axis are in log scale. The proposed models are in good agreement with the simulation results. The significant influence of $C_1$ on $\Delta\hat{I}'_{2\sim}$ can be observed, while it has no effect on $\Delta\hat{I}'_{2t\sim}$ in the case of the 2S3L converter.

V. IMPLICATIONS OF THE HARDWARE DESIGN ON THE AC CURRENT FLUCTUATION

As it can be deduced from the expressions in (11) and (13), the amplitude of the steady-state fluctuation in the ac current of the SST can be too large if the denominator is close to zero, which essentially depends on the design of the hardware. Hence, it is paramount to include a reliable model of the converter in the design process. Regarding the possible design parameters

<figure><img src="image_8.png" /><figcaption>Fig. 7. Results of the proposed model (lines) and simulation results (markers) for the peak-to-peak ac current fluctuation in the SST: (a) 2S2L converter. (b) 2S3L converter.</figcaption></figure>

that influence the current fluctuation, $f_{sw2}$, $\alpha$, $L_{lk}$, $n_{2L}$ (or $n_{3L}$), $C_1$, and $C_2$ (or $C_{2t}$ and $C_{2b}$) play a role in it, being the dc-link capacitors the most convenient design parameters in order to accomplish an adequate, limited current fluctuation in the SST.

The selection of the dc-link capacitances is not trivial. The 2S2L conversion architecture is considered in order to illustrate the importance of carefully choosing appropriate values for $C_1$ and $C_2$, and the usefulness of the proposed model for this task. A set of designs of the 2S2L converter is considered, with the parameters shown in Table II. Those that are not modified with respect to the simulations defined by Table I are not included again in the second table. The results for the peak-to-peak current fluctuation according to the proposed model are presented in Fig. 8 (a), along with several simulation results from PSIM, depicted as markers.

The proposed model is valid until $\Delta\hat{I}'_{2\sim}$ surpasses an upper limit, obtained for this converter and shown
<table><caption>TABLE II
PARAMETERS OF THE 2ND SET OF SIMULATIONS</caption><thead><tr><th>Parameter</th><th>Symbol</th><th>Value</th></tr></thead><tbody><tr><td>Input cap.</td><td>C<sub>1</sub></td><td>[10, 25, 100, ∞] μF</td></tr><tr><td>Leakage induct.</td><td>L<sub>lk</sub></td><td>1.5 μH</td></tr><tr><td>Sw. freq. Stage 2</td><td>∫<sub>s,w</sub>2</td><td>18 kHz</td></tr><tr><td>Output cap.</td><td>C<sub>2</sub></td><td>[20 50 80 110 140 170] μF</td></tr></tbody></table>

<figure><img src="image_9.png" /><figcaption>Fig. 8. Influence of $C_1$ and $C_2$ on the ac current fluctuation in the SST of the 2S2L converter. (a) Proposed model (lines) and simulation results (markers) for $\Delta\hat{I}'_{2\sim}$. (b) Instantaneous current with large fluctuation causing discontinuous conduction.</figcaption></figure>

in Fig. 8 (a) as a dashed line. Values above that line mean that the current in the SST becomes zero during certain time (discontinuous conduction) every cycle of the fluctuation, as Fig. 8 (b) illustrates for a design with $C_1 = 25$ μF and $C_2 = 170$ μF.

It is noticeable that selecting a large output capacitor $C_2$ is not always the best approach, as can be deduced from the behavior of the peak-to-peak current fluctuation when $C_1 = 25$ μF. The fluctuation becomes larger as $C_2$ is increased from 10 μF. It is not until $C_2 > 160$ μF that $\Delta\hat{I}'_{2\sim}$ decreases below its initial value for 10 μF. Actually, the SST would work with a discontinuous current when $C_1 = 25$ μF, as $\Delta\hat{I}'_{2\sim}$ is over the aforementioned boundary in all the considered design points. Increasing $C_1$ does not naturally lead to a smaller current fluctuation either. On the contrary, in this converter, $C_1 = 10$ μF is a better election regarding this matter than the other three

options (even $C_1 \to \infty$), which all mean a bulkier input capacitor. Ignoring the interaction between power stages can also have consequences on the efficiency: selecting $C_1 = 10$ μF and $C_2 = 50$ μF, results in an $i'_2$ rms current of 22.5 A, while $C_1 = 100$ μF and $C_2 = 50$ μF results in 25 A, which means an estimated increase of 23% in conduction losses in the SST. Thus, using the proposed model would not only avoid unexpectedly large current fluctuations and conduction losses in the converter, but it can also be useful to avoid unnecessarily bulky dc links.

## VI. CONCLUSIONS

In this work, an analytical model is obtained for the steady-state fluctuation of the current in the *LLC* resonant converter of two-stage postregulated structures, which are promising for battery fast-charging applications. The presented model is derived by means of a dynamic equivalent circuit, and it is obtained for two different conversion architectures. The analytical formulas are validated through simulations, varying relevant parameters. Finally, the notable impact of the hardware components, particularly the dc-link capacitors, on the ac current fluctuation of the converter is addressed. The performed analysis shows the usefulness of the proposed models to help achieving a limited current fluctuation while avoiding bulkier and more expensive dc-link capacitors than strictly necessary.

## REFERENCES

[1] L. Ulrich, "800-Volt EV Charging: The Other Palliative for Range Anxiety," *IEEE Spectrum*, 2022, https://spectrum.ieee.org/ev-charging-800-volt. Accessed on January 13, 2023.

[2] C. Suarez and W. Martinez, "Fast and ultra-fast charging for battery electric vehicles – a review," in *2019 IEEE Energy Conversion Congress and Exposition (ECCE)*, 2019, pp. 569–575.

[3] F. Krismer, "Modeling and optimization of bidirectional dual active bridge dc-dc converter topologies," Ph.D. dissertation, ETH Zurich, 2010.

[4] F. Flores-Bahamonde, H. Renaudineau, A. M. Llor, A. Chub, and S. Kouro, "The dc transformer power electronic building block: Powering next-generation converter design," *IEEE Industrial Electronics Magazine*, pp. 2–16, 2022.

[5] G. Fan, X. Wu, T. Liu, and Y. Xu, "High-efficiency high-density mhz cellular dc/dc converter for on-board charger," *IEEE Transactions on Power Electronics*, vol. 37, no. 12, pp. 15666–15677, 2022.

[6] Z. Cao, W. Chen, Z. Shen, Y. Chen, L. Jin, D. Ma, and B. Zou, "A low loss orthogonal decoupling magnetic integrated structure for dual active bridge converter," *IEEE Transactions on Power Electronics*, vol. 37, no. 6, pp. 7013–7027, 2022.

[7] B. O. Aarninkhof, D. Lyu, T. B. Soeiro, and P. Bauer, "A reconfigurable two-stage 11 kw dc-dc resonant converter for ev charging with a 150–1000 v output voltage range," *IEEE Transactions on Transportation Electrification*, vol. 10, no. 1, pp. 509–522, 2024.
[8] D. Elizondo-Martinez, E. L. Barrios, M. Galdeano, A. Ursúa, and P. Sanchis, “Novel two-stage three-level converter with inherently-balanced dc voltage for ev fast-charging applications,” *IEEE Transactions on Transportation Electrification*, pp. 1–1, 2023.

[9] D. Elizondo, E. L. Barrios, I. Larequi, A. Ursúa, and P. Sanchis, “Zero-loss switching in LLC resonant converters under discontinuous conduction mode: Analysis and design methodology,” *IEEE Transactions on Industry Applications*, vol. 59, no. 3, pp. 3576–3592, 2023.

[10] J. E. Huber, J. Miniböck, and J. W. Kolar, “Generic derivation of dynamic model for half-cycle DCM series resonant converters,” *IEEE Transactions on Power Electronics*, vol. 33, no. 1, 2018.